gcc/config/nios2/nios2.md

   1 ;; Machine Description for Altera Nios II.
   2 ;; Copyright (C) 2012-2017 Free Software Foundation, Inc.
   3 ;; Contributed by Jonah Graham (jgraham@altera.com) and
   4 ;; Will Reece (wreece@altera.com).
   5 ;; Contributed by Mentor Graphics, Inc.
   6 ;;
   7 ;; This file is part of GCC.
   8 ;;
   9 ;; GCC is free software; you can redistribute it and/or modify
  10 ;; it under the terms of the GNU General Public License as published by
  11 ;; the Free Software Foundation; either version 3, or (at your option)
  12 ;; any later version.
  13 ;;
  14 ;; GCC is distributed in the hope that it will be useful,
  15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ;; GNU General Public License for more details.
  18 ;;
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;; Register numbers
  24 (define_constants
  25   [
  26    (FIRST_RETVAL_REGNO     2)   ; Return value registers
  27    (LAST_RETVAL_REGNO      3)   ;
  28    (FIRST_ARG_REGNO        4)   ; Argument registers
  29    (LAST_ARG_REGNO         7)   ;
  30
  31    (TP_REGNO              23)   ; Thread pointer register
  32    (GP_REGNO              26)   ; Global pointer register
  33    (SP_REGNO              27)   ; Stack pointer register
  34    (FP_REGNO              28)   ; Frame pointer register
  35    (EA_REGNO              29)   ; Exception return address register
  36    (RA_REGNO              31)   ; Return address register
  37    (LAST_GP_REG           31)   ; Last general purpose register
  38
  39    ;; Target register definitions
  40    (STATIC_CHAIN_REGNUM        12)
  41    (STACK_POINTER_REGNUM       27)
  42    (HARD_FRAME_POINTER_REGNUM  28)
  43    (PC_REGNUM                  37)
  44    (FRAME_POINTER_REGNUM       38)
  45    (ARG_POINTER_REGNUM         39)
  46    (FIRST_PSEUDO_REGISTER      40)
  47   ]
  48 )
  49
  50 ;; Enumeration of UNSPECs
  51
  52 (define_c_enum "unspecv" [
  53   UNSPECV_BLOCKAGE
  54   UNSPECV_WRCTL
  55   UNSPECV_RDCTL
  56   UNSPECV_FWRX
  57   UNSPECV_FWRY
  58   UNSPECV_FRDXLO
  59   UNSPECV_FRDXHI
  60   UNSPECV_FRDY
  61   UNSPECV_CUSTOM_NXX
  62   UNSPECV_CUSTOM_XNXX
  63   UNSPECV_LDXIO
  64   UNSPECV_STXIO
  65   UNSPECV_RDPRS
  66   UNSPECV_FLUSHD
  67   UNSPECV_FLUSHDA
  68   UNSPECV_WRPIE
  69   UNSPECV_ENI
  70   UNSPECV_LDEX
  71   UNSPECV_LDSEX
  72   UNSPECV_STEX
  73   UNSPECV_STSEX
  74 ])
  75
  76 (define_c_enum "unspec" [
  77   UNSPEC_FCOS
  78   UNSPEC_FSIN
  79   UNSPEC_FTAN
  80   UNSPEC_FATAN
  81   UNSPEC_FEXP
  82   UNSPEC_FLOG
  83   UNSPEC_ROUND
  84   UNSPEC_LOAD_GOT_REGISTER
  85   UNSPEC_PIC_SYM
  86   UNSPEC_PIC_CALL_SYM
  87   UNSPEC_PIC_GOTOFF_SYM
  88   UNSPEC_LOAD_TLS_IE
  89   UNSPEC_ADD_TLS_LE
  90   UNSPEC_ADD_TLS_GD
  91   UNSPEC_ADD_TLS_LDM
  92   UNSPEC_ADD_TLS_LDO
  93   UNSPEC_EH_RETURN
  94   UNSPEC_SYNC
  95 ])
  96
  97 \f
  98 ;;  Instruction scheduler
  99
 100 ; No schedule info is currently available, using an assumption that no
 101 ; instruction can use the results of the previous instruction without
 102 ; incuring a stall.
 103
 104 ; length of an instruction (in bytes)
 105 (define_attr "length" ""
 106   (if_then_else (match_test "nios2_cdx_narrow_form_p (insn)")
 107     (const_int 2)
 108     (const_int 4)))
 109
 110 (define_attr "type"
 111   "unknown,complex,control,alu,cond_alu,st,ld,stwm,ldwm,push,pop,mul,div,\
 112    custom,add,sub,mov,and,or,xor,neg,not,sll,srl,sra,rol,ror,nop"
 113   (const_string "complex"))
 114
 115 (define_asm_attributes
 116  [(set_attr "length" "4")
 117   (set_attr "type" "complex")])
 118
 119 (define_automaton "nios2")
 120 (automata_option "v")
 121 ;(automata_option "no-minimization")
 122 (automata_option "ndfa")
 123
 124 ; The nios2 pipeline is fairly straightforward for the fast model.
 125 ; Every alu operation is pipelined so that an instruction can
 126 ; be issued every cycle.  However, there are still potential
 127 ; stalls which this description tries to deal with.
 128
 129 (define_cpu_unit "cpu" "nios2")
 130
 131 (define_insn_reservation "complex" 1
 132   (eq_attr "type" "complex")
 133   "cpu")
 134
 135 (define_insn_reservation "control" 1
 136   (eq_attr "type" "control,pop")
 137   "cpu")
 138
 139 (define_insn_reservation "alu" 1
 140   (eq_attr "type" "alu,add,sub,mov,and,or,xor,neg,not")
 141   "cpu")
 142
 143 (define_insn_reservation "cond_alu" 1
 144   (eq_attr "type" "cond_alu")
 145   "cpu")
 146
 147 (define_insn_reservation "st" 1
 148   (eq_attr "type" "st,stwm,push")
 149   "cpu")
 150
 151 (define_insn_reservation "custom" 1
 152   (eq_attr "type" "custom")
 153   "cpu")
 154
 155 ; shifts, muls and lds have three cycle latency
 156 (define_insn_reservation "ld" 3
 157   (eq_attr "type" "ld,ldwm")
 158   "cpu")
 159
 160 (define_insn_reservation "shift" 3
 161   (eq_attr "type" "sll,srl,sra,rol,ror")
 162   "cpu")
 163
 164 (define_insn_reservation "mul" 3
 165   (eq_attr "type" "mul")
 166   "cpu")
 167
 168 (define_insn_reservation "div" 1
 169   (eq_attr "type" "div")
 170   "cpu")
 171
 172 (include "predicates.md")
 173 (include "constraints.md")
 174
 175 \f
 176 ;; Move instructions
 177
 178 (define_mode_iterator M [QI HI SI])
 179
 180 (define_expand "mov<mode>"
 181   [(set (match_operand:M 0 "nonimmediate_operand" "")
 182         (match_operand:M 1 "general_operand" ""))]
 183   ""
 184 {
 185   if (nios2_emit_move_sequence (operands, <MODE>mode))
 186     DONE;
 187 })
 188
 189 (define_insn "*high"
 190   [(set (match_operand:SI 0 "register_operand" "=r")
 191         (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
 192   ""
 193   "movhi\\t%0, %H1"
 194   [(set_attr "type" "alu")])
 195
 196 (define_insn "*lo_sum"
 197   [(set (match_operand:SI 0 "register_operand" "=r")
 198         (lo_sum:SI (match_operand:SI 1 "register_operand"  "r")
 199                    (match_operand:SI 2 "immediate_operand" "i")))]
 200   ""
 201   "addi\\t%0, %1, %L2"
 202   [(set_attr "type" "alu")])
 203
 204 (define_insn_and_split "movqi_internal"
 205   [(set (match_operand:QI 0 "nonimmediate_operand" "=m, r,r")
 206         (match_operand:QI 1 "general_operand"       "rM,m,rI"))]
 207   "(register_operand (operands[0], QImode)
 208     || reg_or_0_operand (operands[1], QImode))"
 209   {
 210     switch (which_alternative)
 211       {
 212       case 0:
 213         if (get_attr_length (insn) != 2)
 214           return "stb%o0\\t%z1, %0";
 215         else if (const_0_operand (operands[1], QImode))
 216           return "stbz.n\\t%z1, %0";
 217         else
 218           return "stb.n\\t%z1, %0";
 219       case 1:
 220         return "ldbu%o1%.\\t%0, %1";
 221       case 2:
 222         return "mov%i1%.\\t%0, %z1";
 223       default:
 224         gcc_unreachable ();
 225       }
 226   }
 227   "(nios2_large_constant_memory_operand_p (operands[0])
 228    || nios2_large_constant_memory_operand_p (operands[1]))"
 229   [(set (match_dup 0) (match_dup 1))]
 230   {
 231     if (nios2_large_constant_memory_operand_p (operands[0]))
 232       operands[0] = nios2_split_large_constant_memory_operand (operands[0]);
 233     else
 234       operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
 235   }
 236   [(set_attr "type" "st,ld,mov")])
 237
 238 (define_insn_and_split "movhi_internal"
 239   [(set (match_operand:HI 0 "nonimmediate_operand" "=m, r,r")
 240         (match_operand:HI 1 "general_operand"       "rM,m,rI"))]
 241   "(register_operand (operands[0], HImode)
 242     || reg_or_0_operand (operands[1], HImode))"
 243   {
 244     switch (which_alternative)
 245       {
 246       case 0:
 247         return "sth%o0%.\\t%z1, %0";
 248       case 1:
 249         return "ldhu%o1%.\\t%0, %1";
 250       case 2:
 251         return "mov%i1%.\\t%0, %z1";
 252       default:
 253         gcc_unreachable ();
 254       }
 255   }
 256   "(nios2_large_constant_memory_operand_p (operands[0])
 257    || nios2_large_constant_memory_operand_p (operands[1]))"
 258   [(set (match_dup 0) (match_dup 1))]
 259   {
 260     if (nios2_large_constant_memory_operand_p (operands[0]))
 261       operands[0] = nios2_split_large_constant_memory_operand (operands[0]);
 262     else
 263       operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
 264   }
 265   [(set_attr "type" "st,ld,mov")])
 266
 267 (define_insn_and_split "movsi_internal"
 268   [(set (match_operand:SI 0 "nonimmediate_operand" "=m, r,r,   r")
 269         (match_operand:SI 1 "general_operand"       "rM,m,rIJK,S"))]
 270   "(register_operand (operands[0], SImode)
 271     || reg_or_0_operand (operands[1], SImode))"
 272   {
 273     switch (which_alternative)
 274       {
 275       case 0:
 276         if (get_attr_length (insn) != 2)
 277           return "stw%o0\\t%z1, %0";
 278         else if (stack_memory_operand (operands[0], SImode))
 279           return "stwsp.n\\t%z1, %0";
 280         else if (const_0_operand (operands[1], SImode))
 281           return "stwz.n\\t%z1, %0";
 282         else
 283           return "stw.n\\t%z1, %0";
 284       case 1:
 285         if (get_attr_length (insn) != 2)
 286           return "ldw%o1\\t%0, %1";
 287         else if (stack_memory_operand (operands[1], SImode))
 288           return "ldwsp.n\\t%0, %1";
 289         else
 290           return "ldw.n\\t%0, %1";
 291       case 2:
 292         return "mov%i1%.\\t%0, %z1";
 293       case 3:
 294         return "addi\\t%0, gp, %%gprel(%1)";
 295       default:
 296         gcc_unreachable ();
 297       }
 298   }
 299   "(nios2_large_constant_memory_operand_p (operands[0])
 300     || nios2_large_constant_memory_operand_p (operands[1])
 301     || (nios2_large_constant_p (operands[1])
 302         && !SMALL_INT_UNSIGNED (INTVAL (operands[1]))
 303         && !UPPER16_INT (INTVAL (operands[1]))))"
 304   [(set (match_dup 0) (match_dup 1))]
 305   {
 306     if (nios2_large_constant_memory_operand_p (operands[0]))
 307       operands[0] = nios2_split_large_constant_memory_operand (operands[0]);
 308     else if (nios2_large_constant_memory_operand_p (operands[1]))
 309       operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
 310     else
 311       operands[1] = nios2_split_large_constant (operands[1], operands[0]);
 312   }
 313   [(set_attr "type" "st,ld,mov,alu")])
 314
 315 (define_mode_iterator BH [QI HI])
 316 (define_mode_iterator BHW [QI HI SI])
 317 (define_mode_attr bh [(QI "b") (HI "h")])
 318 (define_mode_attr bhw [(QI "b") (HI "h") (SI "w")])
 319 (define_mode_attr bhw_uns [(QI "bu") (HI "hu") (SI "w")])
 320
 321 (define_insn "ld<bhw_uns>io"
 322   [(set (match_operand:BHW 0 "register_operand" "=r")
 323         (unspec_volatile:BHW
 324           [(match_operand:BHW 1 "ldstio_memory_operand" "w")] UNSPECV_LDXIO))]
 325   ""
 326   "ld<bhw_uns>io\\t%0, %1"
 327   [(set_attr "type" "ld")])
 328
 329 (define_expand "ld<bh>io"
 330   [(set (match_operand:BH 0 "register_operand" "=r")
 331         (match_operand:BH 1 "ldstio_memory_operand" "w"))]
 332   ""
 333 {
 334   rtx tmp = gen_reg_rtx (SImode);
 335   emit_insn (gen_ld<bh>io_signed (tmp, operands[1]));
 336   emit_insn (gen_mov<mode> (operands[0], gen_lowpart (<MODE>mode, tmp)));
 337   DONE;
 338 })
 339
 340 (define_insn "ld<bh>io_signed"
 341   [(set (match_operand:SI 0 "register_operand" "=r")
 342         (sign_extend:SI
 343           (unspec_volatile:BH
 344             [(match_operand:BH 1 "ldstio_memory_operand" "w")] UNSPECV_LDXIO)))]
 345   ""
 346   "ld<bh>io\\t%0, %1"
 347   [(set_attr "type" "ld")])
 348
 349 (define_insn "st<bhw>io"
 350   [(set (match_operand:BHW 0 "ldstio_memory_operand" "=w")
 351         (unspec_volatile:BHW
 352           [(match_operand:BHW 1 "reg_or_0_operand" "rM")] UNSPECV_STXIO))]
 353   ""
 354   "st<bhw>io\\t%z1, %0"
 355   [(set_attr "type" "st")])
 356
 357 \f
 358 ;; QI to [HI, SI] extension patterns are collected together
 359 (define_mode_iterator QX [HI SI])
 360
 361 ;; Zero extension patterns
 362 (define_insn_and_split "zero_extendhisi2"
 363   [(set (match_operand:SI 0 "register_operand" "=r,r")
 364         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 365   ""
 366   "@
 367     andi%.\\t%0, %1, 0xffff
 368     ldhu%o1%.\\t%0, %1"
 369   "nios2_large_constant_memory_operand_p (operands[1])"
 370   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
 371   {
 372     operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
 373   }
 374   [(set_attr "type"     "and,ld")])
 375
 376 (define_insn_and_split "zero_extendqi<mode>2"
 377   [(set (match_operand:QX 0 "register_operand" "=r,r")
 378         (zero_extend:QX (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 379   ""
 380   "@
 381     andi%.\\t%0, %1, 0xff
 382     ldbu%o1%.\\t%0, %1"
 383   "nios2_large_constant_memory_operand_p (operands[1])"
 384   [(set (match_dup 0) (zero_extend:QX (match_dup 1)))]
 385   {
 386     operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
 387   }
 388   [(set_attr "type"     "and,ld")])
 389
 390 ;; Sign extension patterns
 391
 392 (define_insn_and_split "extendhisi2"
 393   [(set (match_operand:SI 0 "register_operand"                     "=r,r")
 394         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand"  "r,m")))]
 395   ""
 396   "@
 397    #
 398    ldh%o1%.\\t%0, %1"
 399   "nios2_large_constant_memory_operand_p (operands[1])"
 400   [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
 401   {
 402     operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
 403   }
 404   [(set_attr "type" "alu,ld")])
 405
 406 (define_insn_and_split "extendqi<mode>2"
 407   [(set (match_operand:QX 0 "register_operand"                     "=r,r")
 408         (sign_extend:QX (match_operand:QI 1 "nonimmediate_operand"  "r,m")))]
 409   ""
 410   "@
 411    #
 412    ldb%o1%.\\t%0, %1"
 413   "nios2_large_constant_memory_operand_p (operands[1])"
 414   [(set (match_dup 0) (sign_extend:QX (match_dup 1)))]
 415   {
 416     operands[1] = nios2_split_large_constant_memory_operand (operands[1]);
 417   }
 418   [(set_attr "type" "alu,ld")])
 419
 420 ;; Split patterns for register alternative cases.
 421 (define_split
 422   [(set (match_operand:SI 0 "register_operand" "")
 423         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
 424   "reload_completed"
 425   [(set (match_dup 0)
 426         (and:SI (match_dup 1) (const_int 65535)))
 427    (set (match_dup 0)
 428         (xor:SI (match_dup 0) (const_int 32768)))
 429    (set (match_dup 0)
 430         (plus:SI (match_dup 0) (const_int -32768)))]
 431   "operands[1] = gen_lowpart (SImode, operands[1]);")
 432
 433 (define_split
 434   [(set (match_operand:QX 0 "register_operand" "")
 435         (sign_extend:QX (match_operand:QI 1 "register_operand" "")))]
 436   "reload_completed"
 437   [(set (match_dup 0)
 438         (and:SI (match_dup 1) (const_int 255)))
 439    (set (match_dup 0)
 440         (xor:SI (match_dup 0) (const_int 128)))
 441    (set (match_dup 0)
 442         (plus:SI (match_dup 0) (const_int -128)))]
 443   "operands[0] = gen_lowpart (SImode, operands[0]);
 444    operands[1] = gen_lowpart (SImode, operands[1]);")
 445
 446 \f
 447 ;; Arithmetic Operations
 448
 449 (define_insn "addsi3"
 450   [(set (match_operand:SI 0 "register_operand"            "=r")
 451         (plus:SI (match_operand:SI 1 "register_operand"   "%r")
 452                  (match_operand:SI 2 "add_regimm_operand" "rIT")))]
 453   ""
 454 {
 455   return nios2_add_insn_asm (insn, operands);
 456 }
 457   [(set_attr "type" "add")])
 458
 459 (define_insn "subsi3"
 460   [(set (match_operand:SI 0 "register_operand"           "=r")
 461         (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rM")
 462                   (match_operand:SI 2 "register_operand" "r")))]
 463   ""
 464   "sub%.\\t%0, %z1, %2"
 465   [(set_attr "type" "sub")])
 466
 467 (define_insn "mulsi3"
 468   [(set (match_operand:SI 0 "register_operand"          "=r")
 469         (mult:SI (match_operand:SI 1 "register_operand" "%r")
 470                  (match_operand:SI 2 "arith_operand"    "rI")))]
 471   "TARGET_HAS_MUL"
 472   "mul%i2\\t%0, %1, %z2"
 473   [(set_attr "type" "mul")])
 474
 475 (define_expand "divsi3"
 476   [(set (match_operand:SI 0 "register_operand"          "=r")
 477         (div:SI (match_operand:SI 1 "register_operand"   "r")
 478                 (match_operand:SI 2 "register_operand"   "r")))]
 479   ""
 480 {
 481   if (!TARGET_HAS_DIV)
 482     {
 483       if (TARGET_FAST_SW_DIV)
 484         {
 485           nios2_emit_expensive_div (operands, SImode);
 486           DONE;
 487         }
 488       else
 489         FAIL;
 490     }
 491 })
 492
 493 (define_insn "divsi3_insn"
 494   [(set (match_operand:SI 0 "register_operand"            "=r")
 495         (div:SI (match_operand:SI 1 "register_operand"     "r")
 496                 (match_operand:SI 2 "register_operand"     "r")))]
 497   "TARGET_HAS_DIV"
 498   "div\\t%0, %1, %2"
 499   [(set_attr "type" "div")])
 500
 501 (define_insn "udivsi3"
 502   [(set (match_operand:SI 0 "register_operand"            "=r")
 503         (udiv:SI (match_operand:SI 1 "register_operand"    "r")
 504                  (match_operand:SI 2 "register_operand"    "r")))]
 505   "TARGET_HAS_DIV"
 506   "divu\\t%0, %1, %2"
 507   [(set_attr "type" "div")])
 508
 509 (define_code_iterator EXTEND [sign_extend zero_extend])
 510 (define_code_attr us [(sign_extend "s") (zero_extend "u")])
 511 (define_code_attr mul [(sign_extend "mul") (zero_extend "umul")])
 512
 513 (define_insn "<us>mulsi3_highpart"
 514   [(set (match_operand:SI 0 "register_operand"                       "=r")
 515         (truncate:SI
 516          (lshiftrt:DI
 517           (mult:DI (EXTEND:DI (match_operand:SI 1 "register_operand"  "r"))
 518                    (EXTEND:DI (match_operand:SI 2 "register_operand"  "r")))
 519           (const_int 32))))]
 520   "TARGET_HAS_MULX"
 521   "mulx<us><us>\\t%0, %1, %2"
 522   [(set_attr "type" "mul")])
 523
 524 (define_expand "<mul>sidi3"
 525   [(set (match_operand:DI 0 "register_operand" "")
 526         (mult:DI (EXTEND:DI (match_operand:SI 1 "register_operand" ""))
 527                  (EXTEND:DI (match_operand:SI 2 "register_operand" ""))))]
 528   "TARGET_HAS_MULX"
 529 {
 530   rtx hi = gen_reg_rtx (SImode);
 531   rtx lo = gen_reg_rtx (SImode);
 532
 533   emit_insn (gen_<us>mulsi3_highpart (hi, operands[1], operands[2]));
 534   emit_insn (gen_mulsi3 (lo, operands[1], operands[2]));
 535   emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
 536   emit_move_insn (gen_highpart (SImode, operands[0]), hi);
 537   DONE;
 538 })
 539
 540 \f
 541 ;;  Negate and ones complement
 542
 543 (define_insn "negsi2"
 544   [(set (match_operand:SI 0 "register_operand"        "=r")
 545         (neg:SI (match_operand:SI 1 "register_operand" "r")))]
 546   ""
 547 {
 548   if (get_attr_length (insn) == 2)
 549     return "neg.n\\t%0, %1";
 550   else
 551     return "sub\\t%0, zero, %1";
 552 }
 553   [(set_attr "type" "neg")])
 554
 555 (define_insn "one_cmplsi2"
 556   [(set (match_operand:SI 0 "register_operand"        "=r")
 557         (not:SI (match_operand:SI 1 "register_operand" "r")))]
 558   ""
 559 {
 560   if (get_attr_length (insn) == 2)
 561     return "not.n\\t%0, %1";
 562   else
 563     return "nor\\t%0, zero, %1";
 564 }
 565   [(set_attr "type" "not")])
 566
 567 \f
 568 ;;  Integer logical Operations
 569
 570 (define_insn "andsi3"
 571   [(set (match_operand:SI 0 "register_operand"          "=r")
 572         (and:SI (match_operand:SI 1 "register_operand"  "%r")
 573                 (match_operand:SI 2 "and_operand"     "rJKP")))]
 574   ""
 575   "and%x2%.\\t%0, %1, %y2"
 576   [(set_attr "type" "and")])
 577
 578 (define_code_iterator LOGICAL [ior xor])
 579 (define_code_attr logical_asm [(ior "or") (xor "xor")])
 580
 581 (define_insn "<code>si3"
 582   [(set (match_operand:SI 0 "register_operand"             "=r")
 583         (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r")
 584                     (match_operand:SI 2 "logical_operand" "rJK")))]
 585   ""
 586   "<logical_asm>%x2%.\\t%0, %1, %y2"
 587   [(set_attr "type" "<logical_asm>")])
 588
 589 (define_insn "*norsi3"
 590   [(set (match_operand:SI 0 "register_operand"                 "=r")
 591         (and:SI (not:SI (match_operand:SI 1 "register_operand" "%r"))
 592                 (not:SI (match_operand:SI 2 "register_operand"  "r"))))]
 593   ""
 594   "nor\\t%0, %1, %2"
 595   [(set_attr "type" "alu")])
 596
 597 \f
 598 ;;  Shift instructions
 599
 600 (define_code_iterator SHIFT  [ashift ashiftrt lshiftrt rotate])
 601 (define_code_attr shift_op   [(ashift "ashl") (ashiftrt "ashr")
 602                               (lshiftrt "lshr") (rotate "rotl")])
 603 (define_code_attr shift_asm  [(ashift "sll") (ashiftrt "sra")
 604                               (lshiftrt "srl") (rotate "rol")])
 605
 606 (define_insn "<shift_op>si3"
 607   [(set (match_operand:SI 0 "register_operand"          "=r")
 608         (SHIFT:SI (match_operand:SI 1 "register_operand" "r")
 609                   (match_operand:SI 2 "shift_operand"    "rL")))]
 610   ""
 611   "<shift_asm>%i2%.\\t%0, %1, %z2"
 612   [(set_attr "type" "<shift_asm>")])
 613
 614 (define_insn "rotrsi3"
 615   [(set (match_operand:SI 0 "register_operand"             "=r")
 616         (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 617                      (match_operand:SI 2 "register_operand" "r")))]
 618   ""
 619   "ror\\t%0, %1, %2"
 620   [(set_attr "type" "ror")])
 621
 622 ;; Nios II R2 Bit Manipulation Extension (BMX), provides
 623 ;; bit merge/insertion/extraction instructions.
 624
 625 (define_insn "*merge"
 626   [(set (zero_extract:SI (match_operand:SI 0 "register_operand"   "+r")
 627                          (match_operand:SI 1 "const_shift_operand" "L")
 628                          (match_operand:SI 2 "const_shift_operand" "L"))
 629         (zero_extract:SI (match_operand:SI 3 "register_operand"    "r")
 630                          (match_dup 1) (match_dup 2)))]
 631   "TARGET_HAS_BMX"
 632 {
 633   operands[4] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]) - 1);
 634   return "merge\\t%0, %3, %4, %2";
 635 }
 636   [(set_attr "type" "alu")])
 637
 638 (define_insn "extzv"
 639   [(set (match_operand:SI 0 "register_operand" "=r")
 640         (zero_extract:SI (match_operand:SI 1 "register_operand"    "r")
 641                          (match_operand:SI 2 "const_shift_operand" "L")
 642                          (match_operand:SI 3 "const_shift_operand" "L")))]
 643   "TARGET_HAS_BMX"
 644 {
 645   operands[4] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
 646   return "extract\\t%0, %1, %4, %3";
 647 }
 648   [(set_attr "type" "alu")])
 649
 650 (define_insn "insv"
 651   [(set (zero_extract:SI (match_operand:SI 0 "register_operand"   "+r")
 652                          (match_operand:SI 1 "const_shift_operand" "L")
 653                          (match_operand:SI 2 "const_shift_operand" "L"))
 654         (match_operand:SI 3 "reg_or_0_operand" "rM"))]
 655   "TARGET_HAS_BMX"
 656 {
 657   operands[4] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]) - 1);
 658   return "insert\\t%0, %z3, %4, %2";
 659 }
 660   [(set_attr "type" "alu")])
 661
 662
 663 \f
 664 ;; Floating point instructions
 665
 666 ;; Mode iterator for single/double float
 667 (define_mode_iterator F [SF DF])
 668 (define_mode_attr f [(SF "s") (DF "d")])
 669
 670 ;; Basic arithmetic instructions
 671 (define_code_iterator FOP3 [plus minus mult div])
 672 (define_code_attr fop3 [(plus "add") (minus "sub") (mult "mul") (div "div")])
 673
 674 (define_insn "<fop3><mode>3"
 675   [(set (match_operand:F 0 "register_operand"        "=r")
 676         (FOP3:F (match_operand:F 1 "register_operand" "r")
 677                 (match_operand:F 2 "register_operand" "r")))]
 678   "nios2_fpu_insn_enabled (n2fpu_f<fop3><f>)"
 679   { return nios2_fpu_insn_asm (n2fpu_f<fop3><f>); }
 680   [(set_attr "type" "custom")])
 681
 682 ;; Floating point min/max operations
 683 (define_code_iterator SMINMAX [smin smax])
 684 (define_code_attr minmax [(smin "min") (smax "max")])
 685 (define_insn "<code><mode>3"
 686   [(set (match_operand:F 0 "register_operand" "=r")
 687         (SMINMAX:F (match_operand:F 1 "register_operand" "r")
 688                    (match_operand:F 2 "register_operand" "r")))]
 689   "nios2_fpu_insn_enabled (n2fpu_f<minmax><f>)"
 690   { return nios2_fpu_insn_asm (n2fpu_f<minmax><f>); }
 691   [(set_attr "type" "custom")])
 692
 693 ;; These 2-operand FP operations can be collected together
 694 (define_code_iterator FOP2 [abs neg sqrt])
 695 (define_insn "<code><mode>2"
 696   [(set (match_operand:F 0 "register_operand" "=r")
 697         (FOP2:F (match_operand:F 1 "register_operand" "r")))]
 698   "nios2_fpu_insn_enabled (n2fpu_f<code><f>)"
 699   { return nios2_fpu_insn_asm (n2fpu_f<code><f>); }
 700   [(set_attr "type" "custom")])
 701
 702 ;; X, Y register access instructions
 703 (define_insn "nios2_fwrx"
 704   [(unspec_volatile [(match_operand:DF 0 "register_operand" "r")] UNSPECV_FWRX)]
 705   "nios2_fpu_insn_enabled (n2fpu_fwrx)"
 706   { return nios2_fpu_insn_asm (n2fpu_fwrx); }
 707   [(set_attr "type" "custom")])
 708
 709 (define_insn "nios2_fwry"
 710   [(unspec_volatile [(match_operand:SF 0 "register_operand" "r")] UNSPECV_FWRY)]
 711   "nios2_fpu_insn_enabled (n2fpu_fwry)"
 712   { return nios2_fpu_insn_asm (n2fpu_fwry); }
 713   [(set_attr "type" "custom")])
 714
 715 ;; The X, Y read insns uses an int iterator
 716 (define_int_iterator UNSPEC_READ_XY [UNSPECV_FRDXLO UNSPECV_FRDXHI
 717                                      UNSPECV_FRDY])
 718 (define_int_attr read_xy [(UNSPECV_FRDXLO "frdxlo") (UNSPECV_FRDXHI "frdxhi")
 719                           (UNSPECV_FRDY "frdy")])
 720 (define_insn "nios2_<read_xy>"
 721   [(set (match_operand:SF 0 "register_operand" "=r")
 722         (unspec_volatile:SF [(const_int 0)] UNSPEC_READ_XY))]
 723   "nios2_fpu_insn_enabled (n2fpu_<read_xy>)"
 724   { return nios2_fpu_insn_asm (n2fpu_<read_xy>); }
 725   [(set_attr "type" "custom")])
 726
 727 ;; Various math functions
 728 (define_int_iterator MATHFUNC
 729   [UNSPEC_FCOS UNSPEC_FSIN UNSPEC_FTAN UNSPEC_FATAN UNSPEC_FEXP UNSPEC_FLOG])
 730 (define_int_attr mathfunc [(UNSPEC_FCOS "cos") (UNSPEC_FSIN "sin")
 731                            (UNSPEC_FTAN "tan") (UNSPEC_FATAN "atan")
 732                            (UNSPEC_FEXP "exp") (UNSPEC_FLOG "log")])
 733
 734 (define_insn "<mathfunc><mode>2"
 735   [(set (match_operand:F 0 "register_operand" "=r")
 736         (unspec:F [(match_operand:F 1 "register_operand" "r")] MATHFUNC))]
 737   "nios2_fpu_insn_enabled (n2fpu_f<mathfunc><f>)"
 738   { return nios2_fpu_insn_asm (n2fpu_f<mathfunc><f>); }
 739   [(set_attr "type" "custom")])
 740
 741 ;; Converting between floating point and fixed point
 742
 743 (define_code_iterator FLOAT [float unsigned_float])
 744 (define_code_iterator FIX [fix unsigned_fix])
 745
 746 (define_code_attr conv_op [(float "float") (unsigned_float "floatuns")
 747                            (fix "fix") (unsigned_fix "fixuns")])
 748 (define_code_attr i [(float "i") (unsigned_float "u")
 749                      (fix "i") (unsigned_fix "u")])
 750
 751 ;; Integer to float conversions
 752 (define_insn "<conv_op>si<mode>2"
 753   [(set (match_operand:F 0 "register_operand" "=r")
 754         (FLOAT:F (match_operand:SI 1 "register_operand" "r")))]
 755   "nios2_fpu_insn_enabled (n2fpu_float<i><f>)"
 756   { return nios2_fpu_insn_asm (n2fpu_float<i><f>); }
 757   [(set_attr "type" "custom")])
 758
 759 ;; Float to integer conversions
 760 (define_insn "<conv_op>_trunc<mode>si2"
 761   [(set (match_operand:SI 0 "register_operand" "=r")
 762         (FIX:SI (match_operand:F 1 "general_operand" "r")))]
 763   "nios2_fpu_insn_enabled (n2fpu_fix<f><i>)"
 764   { return nios2_fpu_insn_asm (n2fpu_fix<f><i>); }
 765   [(set_attr "type" "custom")])
 766
 767 (define_insn "lroundsfsi2"
 768   [(set (match_operand:SI 0 "register_operand" "=r")
 769         (unspec:SI [(match_operand:SF 1 "general_operand" "r")] UNSPEC_ROUND))]
 770   "nios2_fpu_insn_enabled (n2fpu_round)"
 771   { return nios2_fpu_insn_asm (n2fpu_round); }
 772   [(set_attr "type" "custom")])
 773
 774 (define_insn "extendsfdf2"
 775   [(set (match_operand:DF 0 "register_operand" "=r")
 776         (float_extend:DF (match_operand:SF 1 "general_operand" "r")))]
 777   "nios2_fpu_insn_enabled (n2fpu_fextsd)"
 778   { return nios2_fpu_insn_asm (n2fpu_fextsd); }
 779   [(set_attr "type" "custom")])
 780
 781 (define_insn "truncdfsf2"
 782   [(set (match_operand:SF 0 "register_operand" "=r")
 783         (float_truncate:SF (match_operand:DF 1 "general_operand" "r")))]
 784   "nios2_fpu_insn_enabled (n2fpu_ftruncds)"
 785   { return nios2_fpu_insn_asm (n2fpu_ftruncds); }
 786   [(set_attr "type" "custom")])
 787
 788
 789 \f
 790 ;; Prologue, Epilogue and Return
 791
 792 (define_expand "prologue"
 793   [(const_int 1)]
 794   ""
 795 {
 796   nios2_expand_prologue ();
 797   DONE;
 798 })
 799
 800 (define_expand "epilogue"
 801   [(return)]
 802   ""
 803 {
 804   nios2_expand_epilogue (false);
 805   DONE;
 806 })
 807
 808 (define_expand "sibcall_epilogue"
 809   [(return)]
 810   ""
 811 {
 812   nios2_expand_epilogue (true);
 813   DONE;
 814 })
 815
 816 (define_expand "return"
 817   [(simple_return)]
 818   "nios2_can_use_return_insn ()"
 819 {
 820   if (nios2_expand_return ())
 821     DONE;
 822 })
 823
 824 (define_insn "simple_return"
 825   [(simple_return)]
 826   ""
 827   "ret%."
 828   [(set_attr "type" "control")])
 829
 830 ;; Block any insns from being moved before this point, since the
 831 ;; profiling call to mcount can use various registers that aren't
 832 ;; saved or used to pass arguments.
 833
 834 (define_insn "blockage"
 835   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
 836   ""
 837   ""
 838   [(set_attr "type" "unknown")
 839    (set_attr "length" "0")])
 840
 841 ;; This is used in compiling the unwind routines.
 842 (define_expand "eh_return"
 843   [(use (match_operand 0 "general_operand"))]
 844   ""
 845 {
 846   if (GET_MODE (operands[0]) != Pmode)
 847     operands[0] = convert_to_mode (Pmode, operands[0], 0);
 848   emit_insn (gen_eh_set_ra (operands[0]));
 849   DONE;
 850 })
 851
 852 ;; Modify the return address for EH return.  We can't expand this
 853 ;; until we know where it will be put in the stack frame.
 854
 855 (define_insn_and_split "eh_set_ra"
 856   [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
 857    (clobber (match_scratch:SI 1 "=&r"))]
 858   ""
 859   "#"
 860   "reload_completed"
 861   [(const_int 0)]
 862 {
 863   nios2_set_return_address (operands[0], operands[1]);
 864   DONE;
 865 })
 866
 867 \f
 868 ;;  Jumps and calls
 869
 870 ; Note that the assembler fixes up any out-of-range branch instructions not
 871 ; caught by the compiler branch shortening code.  The sequence emitted by
 872 ; the assembler can be very inefficient, but it is correct for PIC code.
 873 ; For non-PIC we are better off converting to an absolute JMPI.
 874 ;
 875 ; Direct calls and sibcalls use the CALL and JMPI instructions, respectively.
 876 ; These instructions have an immediate operand that specifies the low 28 bits
 877 ; of the PC, effectively allowing direct calls within a 256MB memory segment.
 878 ; Per the Nios II Processor Reference Handbook, the linker is not required to
 879 ; check or adjust for overflow.
 880
 881 (define_insn "indirect_jump"
 882   [(set (pc) (match_operand:SI 0 "register_operand" "c"))]
 883   ""
 884   "jmp%!\\t%0"
 885   [(set_attr "type" "control")])
 886
 887 (define_insn "jump"
 888   [(set (pc)
 889         (label_ref (match_operand 0 "" "")))]
 890   ""
 891   {
 892     if (get_attr_length (insn) == 2)
 893       return "br.n\\t%0";
 894     else if (get_attr_length (insn) == 4)
 895       return "br\\t%0";
 896     else
 897       return "jmpi\\t%0";
 898   }
 899   [(set_attr "type" "control")
 900    (set (attr "length")
 901         (if_then_else
 902             (and (match_test "TARGET_HAS_CDX")
 903                  (and (ge (minus (match_dup 0) (pc)) (const_int -1022))
 904                       (le (minus (match_dup 0) (pc)) (const_int 1022))))
 905             (const_int 2)
 906             (if_then_else
 907                 (ior (match_test "flag_pic")
 908                      (and (ge (minus (match_dup 0) (pc)) (const_int -32764))
 909                           (le (minus (match_dup 0) (pc)) (const_int 32764))))
 910                 (const_int 4)
 911                 (const_int 8))))])
 912
 913 (define_expand "call"
 914   [(parallel [(call (match_operand 0 "" "")
 915                     (match_operand 1 "" ""))
 916               (clobber (reg:SI RA_REGNO))])]
 917   ""
 918   "nios2_adjust_call_address (&operands[0], NULL_RTX);")
 919
 920 (define_expand "call_value"
 921   [(parallel [(set (match_operand 0 "" "")
 922                    (call (match_operand 1 "" "")
 923                          (match_operand 2 "" "")))
 924               (clobber (reg:SI RA_REGNO))])]
 925   ""
 926   "nios2_adjust_call_address (&operands[1], NULL_RTX);")
 927
 928 (define_insn "*call"
 929   [(call (mem:QI (match_operand:SI 0 "call_operand" "i,r"))
 930          (match_operand 1 "" ""))
 931    (clobber (reg:SI RA_REGNO))]
 932   ""
 933   "@
 934    call\\t%0
 935    callr%.\\t%0"
 936   [(set_attr "type" "control")])
 937
 938 (define_insn "*call_value"
 939   [(set (match_operand 0 "" "")
 940         (call (mem:QI (match_operand:SI 1 "call_operand" "i,r"))
 941               (match_operand 2 "" "")))
 942    (clobber (reg:SI RA_REGNO))]
 943   ""
 944   "@
 945    call\\t%1
 946    callr%.\\t%1"
 947   [(set_attr "type" "control")])
 948
 949 (define_expand "sibcall"
 950   [(parallel [(call (match_operand 0 "" "")
 951                     (match_operand 1 "" ""))
 952               (return)])]
 953   ""
 954   "nios2_adjust_call_address (&operands[0], NULL_RTX);")
 955
 956 (define_expand "sibcall_value"
 957   [(parallel [(set (match_operand 0 "" "")
 958                    (call (match_operand 1 "" "")
 959                          (match_operand 2 "" "")))
 960               (return)])]
 961   ""
 962   "nios2_adjust_call_address (&operands[1], NULL_RTX);")
 963
 964 (define_insn "sibcall_internal"
 965  [(call (mem:QI (match_operand:SI 0 "call_operand" "i,j"))
 966         (match_operand 1 "" ""))
 967   (return)]
 968   ""
 969   "@
 970    jmpi\\t%0
 971    jmp%!\\t%0"
 972   [(set_attr "type" "control")])
 973
 974 (define_insn "sibcall_value_internal"
 975  [(set (match_operand 0 "register_operand" "")
 976        (call (mem:QI (match_operand:SI 1 "call_operand" "i,j"))
 977              (match_operand 2 "" "")))
 978   (return)]
 979   ""
 980   "@
 981    jmpi\\t%1
 982    jmp%!\\t%1"
 983   [(set_attr "type" "control")])
 984
 985 (define_expand "tablejump"
 986   [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
 987               (use (label_ref (match_operand 1 "" "")))])]
 988   ""
 989 {
 990   if (flag_pic)
 991     {
 992       /* Hopefully, CSE will eliminate this copy.  */
 993       rtx reg1 = copy_addr_to_reg (gen_rtx_LABEL_REF (Pmode, operands[1]));
 994       rtx reg2 = gen_reg_rtx (SImode);
 995
 996       emit_insn (gen_addsi3 (reg2, operands[0], reg1));
 997       operands[0] = reg2;
 998     }
 999 })
1000
1001 (define_insn "*tablejump"
1002   [(set (pc)
1003         (match_operand:SI 0 "register_operand" "c"))
1004    (use (label_ref (match_operand 1 "" "")))]
1005   ""
1006   "jmp%!\\t%0"
1007   [(set_attr "type" "control")])
1008
1009 \f
1010 ;; cstore, cbranch patterns
1011
1012 (define_mode_iterator CM [SI SF DF])
1013
1014 (define_expand "cstore<mode>4"
1015   [(set (match_operand:SI 0 "register_operand" "=r")
1016         (match_operator:SI 1 "expandable_comparison_operator"
1017           [(match_operand:CM 2 "register_operand")
1018            (match_operand:CM 3 "nonmemory_operand")]))]
1019   ""
1020 {
1021   if (!nios2_validate_compare (<MODE>mode, &operands[1], &operands[2],
1022                                &operands[3]))
1023     FAIL;
1024 })
1025
1026 (define_expand "cbranch<mode>4"
1027   [(set (pc)
1028      (if_then_else
1029        (match_operator 0 "expandable_comparison_operator"
1030          [(match_operand:CM 1 "register_operand")
1031           (match_operand:CM 2 "nonmemory_operand")])
1032        (label_ref (match_operand 3 ""))
1033        (pc)))]
1034   ""
1035 {
1036   if (!nios2_validate_compare (<MODE>mode, &operands[0], &operands[1],
1037                                &operands[2]))
1038     FAIL;
1039   if (GET_MODE_CLASS (<MODE>mode) == MODE_FLOAT
1040       || !reg_or_0_operand (operands[2], <MODE>mode))
1041     {
1042       rtx condreg = gen_reg_rtx (SImode);
1043       emit_insn (gen_cstore<mode>4
1044                   (condreg, operands[0], operands[1], operands[2]));
1045       operands[1] = condreg;
1046       operands[2] = const0_rtx;
1047       operands[0] = gen_rtx_fmt_ee (NE, VOIDmode, condreg, const0_rtx);
1048     }
1049 })
1050
1051 (define_insn "nios2_cbranch"
1052   [(set (pc)
1053      (if_then_else
1054        (match_operator 0 "ordered_comparison_operator"
1055          [(match_operand:SI 1 "reg_or_0_operand" "rM")
1056           (match_operand:SI 2 "reg_or_0_operand" "rM")])
1057        (label_ref (match_operand 3 "" ""))
1058        (pc)))]
1059   ""
1060 {
1061   if (get_attr_length (insn) == 2)
1062     return "b%0z.n\t%z1, %l3";
1063   else if (get_attr_length (insn) == 4)
1064     return "b%0\t%z1, %z2, %l3";
1065   else if (get_attr_length (insn) == 6)
1066     return "b%R0z.n\t%z1, .+6;jmpi\t%l3";
1067   else
1068     return "b%R0\t%z1, %z2, .+8;jmpi\t%l3";
1069 }
1070   [(set_attr "type" "control")
1071    (set (attr "length")
1072         (cond
1073          [(and (match_test "nios2_cdx_narrow_form_p (insn)")
1074                (ge (minus (match_dup 3) (pc)) (const_int -126))
1075                (le (minus (match_dup 3) (pc)) (const_int 126)))
1076           (const_int 2)
1077           (ior (match_test "flag_pic")
1078                (and (ge (minus (match_dup 3) (pc)) (const_int -32764))
1079                     (le (minus (match_dup 3) (pc)) (const_int 32764))))
1080           (const_int 4)
1081           (match_test "nios2_cdx_narrow_form_p (insn)")
1082           (const_int 6)]
1083          (const_int 8)))])
1084
1085 ;; Floating point comparisons
1086 (define_code_iterator FCMP [eq ne gt ge le lt])
1087 (define_insn "nios2_s<code><mode>"
1088   [(set (match_operand:SI 0 "register_operand"        "=r")
1089         (FCMP:SI (match_operand:F 1 "register_operand" "r")
1090                  (match_operand:F 2 "register_operand" "r")))]
1091   "nios2_fpu_insn_enabled (n2fpu_fcmp<code><f>)"
1092   { return nios2_fpu_insn_asm (n2fpu_fcmp<code><f>); }
1093   [(set_attr "type" "custom")])
1094
1095 ;; Integer comparisons
1096
1097 (define_code_iterator EQNE [eq ne])
1098 (define_insn "nios2_cmp<code>"
1099   [(set (match_operand:SI 0 "register_operand"           "=r")
1100         (EQNE:SI (match_operand:SI 1 "register_operand"  "%r")
1101                  (match_operand:SI 2 "arith_operand"     "rI")))]
1102   ""
1103   "cmp<code>%i2\\t%0, %1, %z2"
1104   [(set_attr "type" "alu")])
1105
1106 (define_code_iterator SCMP [ge lt])
1107 (define_insn "nios2_cmp<code>"
1108   [(set (match_operand:SI 0 "register_operand"           "=r")
1109         (SCMP:SI (match_operand:SI 1 "reg_or_0_operand"  "rM")
1110                  (match_operand:SI 2 "arith_operand"     "rI")))]
1111   ""
1112   "cmp<code>%i2\\t%0, %z1, %z2"
1113   [(set_attr "type" "alu")])
1114
1115 (define_code_iterator UCMP [geu ltu])
1116 (define_insn "nios2_cmp<code>"
1117   [(set (match_operand:SI 0 "register_operand"           "=r")
1118         (UCMP:SI (match_operand:SI 1 "reg_or_0_operand"  "rM")
1119                  (match_operand:SI 2 "uns_arith_operand" "rJ")))]
1120   ""
1121   "cmp<code>%u2\\t%0, %z1, %z2"
1122   [(set_attr "type" "alu")])
1123
1124
1125 \f
1126 ;; Custom instruction patterns.  The operands are intentionally
1127 ;; mode-less, to serve as generic carriers of all Altera defined
1128 ;; built-in instruction/function types.
1129
1130 (define_insn "custom_nxx"
1131   [(unspec_volatile [(match_operand 0 "custom_insn_opcode" "N")
1132                      (match_operand 1 "reg_or_0_operand"  "rM")
1133                      (match_operand 2 "reg_or_0_operand"  "rM")]
1134     UNSPECV_CUSTOM_NXX)]
1135   ""
1136   "custom\\t%0, zero, %z1, %z2"
1137   [(set_attr "type" "custom")])
1138
1139 (define_insn "custom_xnxx"
1140   [(set (match_operand 0 "register_operand"   "=r")
1141         (unspec_volatile [(match_operand 1 "custom_insn_opcode" "N")
1142                           (match_operand 2 "reg_or_0_operand"  "rM")
1143                           (match_operand 3 "reg_or_0_operand"  "rM")]
1144          UNSPECV_CUSTOM_XNXX))]
1145   ""
1146   "custom\\t%1, %0, %z2, %z3"
1147   [(set_attr "type" "custom")])
1148
1149 \f
1150 ;;  Misc. patterns
1151
1152 (define_insn "nop"
1153   [(const_int 0)]
1154   ""
1155   "nop%."
1156   [(set_attr "type" "nop")])
1157
1158 ;; Connect 'sync' to 'memory_barrier' standard expand name
1159 (define_expand "memory_barrier"
1160   [(const_int 0)]
1161   ""
1162 {
1163   emit_insn (gen_sync ());
1164   DONE;
1165 })
1166
1167 ;; For the nios2 __builtin_sync built-in function
1168 (define_expand "sync"
1169   [(set (match_dup 0)
1170         (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
1171   ""
1172 {
1173   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
1174   MEM_VOLATILE_P (operands[0]) = 1;
1175 })
1176
1177 (define_insn "*sync_insn"
1178   [(set (match_operand:BLK 0 "" "")
1179         (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
1180   ""
1181   "sync"
1182   [(set_attr "type" "control")])
1183
1184 (define_insn "rdctl"
1185   [(set (match_operand:SI 0 "register_operand" "=r")
1186         (unspec_volatile:SI [(match_operand:SI 1 "rdwrctl_operand" "O")]
1187          UNSPECV_RDCTL))]
1188   ""
1189   "rdctl\\t%0, ctl%1"
1190   [(set_attr "type" "control")])
1191
1192 (define_insn "wrctl"
1193   [(unspec_volatile:SI [(match_operand:SI 0 "rdwrctl_operand"  "O")
1194                         (match_operand:SI 1 "reg_or_0_operand" "rM")]
1195     UNSPECV_WRCTL)]
1196   ""
1197   "wrctl\\tctl%0, %z1"
1198   [(set_attr "type" "control")])
1199
1200 (define_insn "rdprs"
1201   [(set (match_operand:SI 0 "register_operand" "=r")
1202         (unspec_volatile:SI [(match_operand:SI 1 "rdwrctl_operand" "O")
1203                              (match_operand:SI 2 "arith_operand"   "U")]
1204          UNSPECV_RDPRS))]
1205   ""
1206   "rdprs\\t%0, %1, %2"
1207   [(set_attr "type" "control")])
1208
1209 ;; Cache Instructions
1210
1211 (define_insn "flushd"
1212   [(unspec_volatile:SI [(match_operand:SI 0 "ldstio_memory_operand" "w")]
1213                         UNSPECV_FLUSHD)]
1214   ""
1215   "flushd\\t%0"
1216   [(set_attr "type" "control")])
1217
1218 (define_insn "flushda"
1219   [(unspec_volatile:SI [(match_operand:SI 0 "ldstio_memory_operand" "w")]
1220                         UNSPECV_FLUSHDA)]
1221   ""
1222   "flushda\\t%0"
1223   [(set_attr "type" "control")])
1224
1225 ;; R2 Instructions
1226
1227 (define_insn "wrpie"
1228   [(set (match_operand:SI 0 "register_operand" "=r")
1229         (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")]
1230                              UNSPECV_WRPIE))]
1231   "TARGET_ARCH_R2"
1232   "wrpie\\t%0, %1"
1233   [(set_attr "type" "control")])
1234
1235 (define_insn "eni"
1236   [(unspec:VOID [(match_operand 0 "const_int_operand" "i")]
1237                  UNSPECV_ENI)]
1238   "TARGET_ARCH_R2"
1239   "eni\\t%0"
1240   [(set_attr "type" "control")])
1241
1242 ;; Trap patterns
1243 (define_insn "trap"
1244   [(trap_if (const_int 1) (const_int 3))]
1245   ""
1246   "trap%.\\t3"
1247   [(set_attr "type" "control")])
1248
1249 (define_insn "ctrapsi4"
1250   [(trap_if (match_operator 0 "ordered_comparison_operator"
1251               [(match_operand:SI 1 "reg_or_0_operand" "rM")
1252                (match_operand:SI 2 "reg_or_0_operand" "rM")])
1253             (match_operand 3 "const_int_operand" "i"))]
1254   ""
1255 {
1256   if (get_attr_length (insn) == 6)
1257     return "b%R0\\t%z1, %z2, 1f\;trap.n\\t%3\;1:";
1258   else
1259     return "b%R0\\t%z1, %z2, 1f\;trap\\t%3\;1:";
1260 }
1261   [(set_attr "type" "control")
1262    (set (attr "length")
1263         (if_then_else (match_test "nios2_cdx_narrow_form_p (insn)")
1264                       (const_int 6) (const_int 8)))])
1265
1266 ;; Load the GOT register.
1267 (define_insn "load_got_register"
1268   [(set (match_operand:SI 0 "register_operand" "=&r")
1269          (unspec:SI [(const_int 0)] UNSPEC_LOAD_GOT_REGISTER))
1270    (set (match_operand:SI 1 "register_operand" "=r")
1271          (unspec:SI [(const_int 0)] UNSPEC_LOAD_GOT_REGISTER))]
1272   ""
1273   "nextpc\\t%0
1274 \\t1:
1275 \\tmovhi\\t%1, %%hiadj(_gp_got - 1b)
1276 \\taddi\\t%1, %1, %%lo(_gp_got - 1b)"
1277   [(set_attr "length" "12")])
1278
1279 ;; Read thread pointer register
1280 (define_expand "get_thread_pointersi"
1281   [(match_operand:SI 0 "register_operand" "=r")]
1282   "TARGET_LINUX_ABI"
1283 {
1284   emit_move_insn (operands[0], gen_rtx_REG (Pmode, TP_REGNO));
1285   DONE;
1286 })
1287
1288 ;; Synchronization Primitives
1289 (include "sync.md")
1290
1291 ;; Include the ldwm/stwm/push.n/pop.n patterns and peepholes.
1292 (include "ldstwm.md")
1293