1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
38 /* Save the operands last given to a compare for use when we
39 generate a scc or bcc insn. */
41 rtx hppa_compare_op0
, hppa_compare_op1
;
42 enum cmp_type hppa_branch_type
;
44 rtx hppa_save_pic_table_rtx
;
46 /* Set by the FUNCTION_PROFILER macro. */
47 int hp_profile_labelno
;
49 static rtx
find_addr_reg ();
51 /* Return non-zero only if OP is a register of mode MODE,
54 reg_or_0_operand (op
, mode
)
56 enum machine_mode mode
;
58 return (op
== CONST0_RTX (mode
) || register_operand (op
, mode
));
61 /* Return non-zero if OP is suitable for use in a call to a named
64 (???) For 2.5 try to eliminate either call_operand_address or
65 function_label_operand, they perform very similar functions. */
67 call_operand_address (op
, mode
)
69 enum machine_mode mode
;
71 return (CONSTANT_P (op
) && ! TARGET_LONG_CALLS
);
74 /* Return 1 if X contains a symbolic expression. We know these
75 expressions will have one of a few well defined forms, so
76 we need only check those forms. */
78 symbolic_expression_p (x
)
82 /* Strip off any HIGH. */
83 if (GET_CODE (x
) == HIGH
)
86 return (symbolic_operand (x
, VOIDmode
));
90 symbolic_operand (op
, mode
)
92 enum machine_mode mode
;
94 switch (GET_CODE (op
))
101 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
102 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
103 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
109 /* Return truth value of statement that OP is a symbolic memory
110 operand of mode MODE. */
113 symbolic_memory_operand (op
, mode
)
115 enum machine_mode mode
;
117 if (GET_CODE (op
) == SUBREG
)
118 op
= SUBREG_REG (op
);
119 if (GET_CODE (op
) != MEM
)
122 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
123 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
126 /* Return 1 if the operand is either a register or a memory operand that is
130 reg_or_nonsymb_mem_operand (op
, mode
)
132 enum machine_mode mode
;
134 if (register_operand (op
, mode
))
137 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
143 /* Return 1 if the operand is either a register, zero, or a memory operand
144 that is not symbolic. */
147 reg_or_0_or_nonsymb_mem_operand (op
, mode
)
149 enum machine_mode mode
;
151 if (register_operand (op
, mode
))
154 if (op
== CONST0_RTX (mode
))
157 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
163 /* Accept any constant that can be moved in one instructions into a
166 cint_ok_for_move (intval
)
169 /* OK if ldo, ldil, or zdepi, can be used. */
170 return (VAL_14_BITS_P (intval
) || (intval
& 0x7ff) == 0
171 || zdepi_cint_p (intval
));
174 /* Accept anything that can be moved in one instruction into a general
177 move_operand (op
, mode
)
179 enum machine_mode mode
;
181 if (register_operand (op
, mode
))
184 if (GET_CODE (op
) == CONST_INT
)
185 return cint_ok_for_move (INTVAL (op
));
187 if (GET_MODE (op
) != mode
)
189 if (GET_CODE (op
) == SUBREG
)
190 op
= SUBREG_REG (op
);
191 if (GET_CODE (op
) != MEM
)
195 if (GET_CODE (op
) == LO_SUM
)
196 return (register_operand (XEXP (op
, 0), Pmode
)
197 && CONSTANT_P (XEXP (op
, 1)));
198 return memory_address_p (mode
, op
);
201 /* Accept REG and any CONST_INT that can be moved in one instruction into a
204 reg_or_cint_move_operand (op
, mode
)
206 enum machine_mode mode
;
208 if (register_operand (op
, mode
))
211 if (GET_CODE (op
) == CONST_INT
)
212 return cint_ok_for_move (INTVAL (op
));
218 pic_operand (op
, mode
)
220 enum machine_mode mode
;
222 return flag_pic
&& GET_CODE (op
) == LABEL_REF
;
226 fp_reg_operand (op
, mode
)
228 enum machine_mode mode
;
230 return reg_renumber
&& FP_REG_P (op
);
234 extern int current_function_uses_pic_offset_table
;
235 extern rtx
force_reg (), validize_mem ();
237 /* The rtx for the global offset table which is a special form
238 that *is* a position independent symbolic constant. */
241 /* Ensure that we are not using patterns that are not OK with PIC. */
247 extern rtx recog_operand
[];
251 if (GET_CODE (recog_operand
[i
]) == SYMBOL_REF
252 || (GET_CODE (recog_operand
[i
]) == CONST
253 && ! rtx_equal_p (pic_pc_rtx
, recog_operand
[i
])))
261 /* Return truth value of whether OP can be used as an operand in a
262 three operand arithmetic insn that accepts registers of mode MODE
263 or 14-bit signed integers. */
265 arith_operand (op
, mode
)
267 enum machine_mode mode
;
269 return (register_operand (op
, mode
)
270 || (GET_CODE (op
) == CONST_INT
&& INT_14_BITS (op
)));
273 /* Return truth value of whether OP can be used as an operand in a
274 three operand arithmetic insn that accepts registers of mode MODE
275 or 11-bit signed integers. */
277 arith11_operand (op
, mode
)
279 enum machine_mode mode
;
281 return (register_operand (op
, mode
)
282 || (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
)));
285 /* A constant integer suitable for use in a PRE_MODIFY memory
288 pre_cint_operand (op
, mode
)
290 enum machine_mode mode
;
292 return (GET_CODE (op
) == CONST_INT
293 && INTVAL (op
) >= -0x2000 && INTVAL (op
) < 0x10);
296 /* A constant integer suitable for use in a POST_MODIFY memory
299 post_cint_operand (op
, mode
)
301 enum machine_mode mode
;
303 return (GET_CODE (op
) == CONST_INT
304 && INTVAL (op
) < 0x2000 && INTVAL (op
) >= -0x10);
308 arith_double_operand (op
, mode
)
310 enum machine_mode mode
;
312 return (register_operand (op
, mode
)
313 || (GET_CODE (op
) == CONST_DOUBLE
314 && GET_MODE (op
) == mode
315 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op
))
316 && (CONST_DOUBLE_HIGH (op
) >= 0
317 == ((CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
320 /* Return truth value of whether OP is a integer which fits the
321 range constraining immediate operands in three-address insns. */
324 int5_operand (op
, mode
)
326 enum machine_mode mode
;
328 return (GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
));
332 uint5_operand (op
, mode
)
334 enum machine_mode mode
;
336 return (GET_CODE (op
) == CONST_INT
&& INT_U5_BITS (op
));
341 int11_operand (op
, mode
)
343 enum machine_mode mode
;
345 return (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
));
349 arith5_operand (op
, mode
)
351 enum machine_mode mode
;
353 return register_operand (op
, mode
) || int5_operand (op
, mode
);
356 /* True iff zdepi can be used to generate this CONST_INT. */
361 unsigned lsb_mask
, t
;
363 /* This might not be obvious, but it's at least fast.
364 This function is critcal; we don't have the time loops would take. */
366 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
367 /* Return true iff t is a power of two. */
368 return ((t
& (t
- 1)) == 0);
371 /* True iff depi or extru can be used to compute (reg & mask). */
377 mask
+= mask
& -mask
;
378 return (mask
& (mask
- 1)) == 0;
381 /* True iff depi or extru can be used to compute (reg & OP). */
383 and_operand (op
, mode
)
385 enum machine_mode mode
;
387 return (register_operand (op
, mode
)
388 || (GET_CODE (op
) == CONST_INT
&& and_mask_p (INTVAL (op
))));
391 /* True iff depi can be used to compute (reg | MASK). */
396 mask
+= mask
& -mask
;
397 return (mask
& (mask
- 1)) == 0;
400 /* True iff depi can be used to compute (reg | OP). */
402 ior_operand (op
, mode
)
404 enum machine_mode mode
;
406 return (GET_CODE (op
) == CONST_INT
&& ior_mask_p (INTVAL (op
)));
410 lhs_lshift_operand (op
, mode
)
412 enum machine_mode mode
;
414 return register_operand (op
, mode
) || lhs_lshift_cint_operand (op
, mode
);
417 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
418 Such values can be the left hand side x in (x << r), using the zvdepi
421 lhs_lshift_cint_operand (op
, mode
)
423 enum machine_mode mode
;
426 if (GET_CODE (op
) != CONST_INT
)
428 x
= INTVAL (op
) >> 4;
429 return (x
& (x
+ 1)) == 0;
433 arith32_operand (op
, mode
)
435 enum machine_mode mode
;
437 return register_operand (op
, mode
) || GET_CODE (op
) == CONST_INT
;
441 pc_or_label_operand (op
, mode
)
443 enum machine_mode mode
;
445 return (GET_CODE (op
) == PC
|| GET_CODE (op
) == LABEL_REF
);
448 /* Legitimize PIC addresses. If the address is already
449 position-independent, we return ORIG. Newly generated
450 position-independent addresses go to REG. If we need more
451 than one register, we lose. */
454 legitimize_pic_address (orig
, mode
, reg
)
456 enum machine_mode mode
;
460 if (GET_CODE (orig
) == SYMBOL_REF
)
467 emit_insn (gen_rtx (SET
, VOIDmode
, reg
,
468 gen_rtx (HIGH
, Pmode
, orig
)));
469 emit_insn (gen_rtx (SET
, VOIDmode
, reg
,
470 gen_rtx (LO_SUM
, Pmode
, reg
, orig
)));
473 pic_ref
= gen_rtx (MEM
, Pmode
,
474 gen_rtx (PLUS
, Pmode
,
475 pic_offset_table_rtx
, orig
));
476 current_function_uses_pic_offset_table
= 1;
477 RTX_UNCHANGING_P (pic_ref
) = 1;
478 emit_move_insn (reg
, pic_ref
);
481 else if (GET_CODE (orig
) == CONST
)
485 if (GET_CODE (XEXP (orig
, 0)) == PLUS
486 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
492 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
494 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
495 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
496 base
== reg
? 0 : reg
);
499 if (GET_CODE (orig
) == CONST_INT
)
501 if (INT_14_BITS (orig
))
502 return plus_constant_for_output (base
, INTVAL (orig
));
503 orig
= force_reg (Pmode
, orig
);
505 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
506 /* Likewise, should we set special REG_NOTEs here? */
511 /* Set up PIC-specific rtl. This should not cause any insns
519 /* Emit special PIC prologues and epilogues. */
524 if (hppa_save_pic_table_rtx
)
526 emit_insn_after (gen_rtx (SET
, VOIDmode
,
527 hppa_save_pic_table_rtx
,
528 gen_rtx (REG
, Pmode
, 19)),
530 /* Need to emit this whether or not we obey regdecls,
531 since setjmp/longjmp can cause life info to screw up. */
532 hppa_save_pic_table_rtx
= 0;
534 emit_insn (gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
));
538 /* Try machine-dependent ways of modifying an illegitimate address
539 to be legitimate. If we find one, return the new, valid address.
540 This macro is used in only one place: `memory_address' in explow.c.
542 OLDX is the address as it was before break_out_memory_refs was called.
543 In some cases it is useful to look at this to decide what needs to be done.
545 MODE and WIN are passed so that this macro can use
546 GO_IF_LEGITIMATE_ADDRESS.
548 It is always safe for this macro to do nothing. It exists to recognize
549 opportunities to optimize the output.
551 For the PA, transform:
553 memory(X + <large int>)
557 if (<large int> & mask) >= 16
558 Y = (<large int> & ~mask) + mask + 1 Round up.
560 Y = (<large int> & ~mask) Round down.
562 memory (Z + (<large int> - Y));
564 This is for CSE to find several similar references, and only use one Z.
566 X can either be a SYMBOL_REF or REG, but because combine can not
567 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
568 D will not fit in 14 bits.
570 MODE_FLOAT references allow displacements which fit in 5 bits, so use
573 MODE_INT references allow displacements which fit in 14 bits, so use
576 This relies on the fact that most mode MODE_FLOAT references will use FP
577 registers and most mode MODE_INT references will use integer registers.
578 (In the rare case of an FP register used in an integer MODE, we depend
579 on secondary reloads to clean things up.)
582 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
583 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
584 adressing modes to be used).
586 Put X and Z into registers. Then put the entire expression into
590 hppa_legitimize_address (x
, oldx
, mode
)
592 enum machine_mode mode
;
597 /* Strip off CONST. */
598 if (GET_CODE (x
) == CONST
)
601 if (GET_CODE (x
) == PLUS
602 && GET_CODE (XEXP (x
, 1)) == CONST_INT
603 && (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
604 || GET_CODE (XEXP (x
, 0)) == REG
))
606 rtx int_part
, ptr_reg
;
608 int offset
= INTVAL (XEXP (x
, 1));
609 int mask
= GET_MODE_CLASS (mode
) == MODE_FLOAT
? 0x1f : 0x3fff;
611 /* Choose which way to round the offset. Round up if we
612 are >= halfway to the next boundary. */
613 if ((offset
& mask
) >= ((mask
+ 1) / 2))
614 newoffset
= (offset
& ~ mask
) + mask
+ 1;
616 newoffset
= (offset
& ~ mask
);
618 /* If the newoffset will not fit in 14 bits (ldo), then
619 handling this would take 4 or 5 instructions (2 to load
620 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
621 add the new offset and the SYMBOL_REF.) Combine can
622 not handle 4->2 or 5->2 combinations, so do not create
624 if (! VAL_14_BITS_P (newoffset
)
625 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
627 rtx const_part
= gen_rtx (CONST
, VOIDmode
,
628 gen_rtx (PLUS
, Pmode
,
630 GEN_INT (newoffset
)));
633 gen_rtx (HIGH
, Pmode
, const_part
));
636 gen_rtx (LO_SUM
, Pmode
,
637 tmp_reg
, const_part
));
641 if (! VAL_14_BITS_P (newoffset
))
642 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
644 int_part
= GEN_INT (newoffset
);
646 ptr_reg
= force_reg (Pmode
,
647 gen_rtx (PLUS
, Pmode
,
648 force_reg (Pmode
, XEXP (x
, 0)),
651 return plus_constant (ptr_reg
, offset
- newoffset
);
653 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
654 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
655 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
657 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
659 reg1
= force_reg (Pmode
, force_operand (XEXP (x
, 1), 0));
660 reg2
= force_reg (Pmode
,
661 force_operand (XEXP (XEXP (x
, 0), 0), 0));
662 return force_reg (Pmode
,
663 gen_rtx (PLUS
, Pmode
,
664 gen_rtx (MULT
, Pmode
, reg2
,
669 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
674 /* For the HPPA, REG and REG+CONST is cost 0
675 and addresses involving symbolic constants are cost 2.
677 PIC addresses are very expensive.
679 It is no coincidence that this has the same structure
680 as GO_IF_LEGITIMATE_ADDRESS. */
682 hppa_address_cost (X
)
685 if (GET_CODE (X
) == PLUS
)
687 else if (GET_CODE (X
) == LO_SUM
)
689 else if (GET_CODE (X
) == HIGH
)
694 /* Emit insns to move operands[1] into operands[0].
696 Return 1 if we have written out everything that needs to be done to
697 do the move. Otherwise, return 0 and the caller will emit the move
701 emit_move_sequence (operands
, mode
, scratch_reg
)
703 enum machine_mode mode
;
706 register rtx operand0
= operands
[0];
707 register rtx operand1
= operands
[1];
709 /* Handle secondary reloads for loads/stores of FP registers from
710 REG+D addresses where D does not fit in 5 bits. */
711 if (fp_reg_operand (operand0
, mode
)
712 && GET_CODE (operand1
) == MEM
713 /* Using DFmode forces only short displacements be be
714 recognized as valid in reg+d addressing modes. */
715 && ! memory_address_p (DFmode
, XEXP (operand1
, 0))
718 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
719 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, gen_rtx (MEM
, mode
,
723 else if (fp_reg_operand (operand1
, mode
)
724 && GET_CODE (operand0
) == MEM
725 /* Using DFmode forces only short displacements be be
726 recognized as valid in reg+d addressing modes. */
727 && ! memory_address_p (DFmode
, XEXP (operand0
, 0))
730 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
731 emit_insn (gen_rtx (SET
, VOIDmode
, gen_rtx (MEM
, mode
, scratch_reg
),
735 /* Handle secondary reloads for loads of FP registers from constant
736 expressions by forcing the constant into memory.
738 use scratch_reg to hold the address of the memory location.
740 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
741 NO_REGS when presented with a const_int and an register class
742 containing only FP registers. Doing so unfortunately creates
743 more problems than it solves. Fix this for 2.5. */
744 else if (fp_reg_operand (operand0
, mode
)
745 && CONSTANT_P (operand1
)
750 /* Force the constant into memory and put the address of the
751 memory location into scratch_reg. */
752 xoperands
[0] = scratch_reg
;
753 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
754 emit_move_sequence (xoperands
, mode
, 0);
756 /* Now load the destination register. */
757 emit_insn (gen_rtx (SET
, mode
, operand0
,
758 gen_rtx (MEM
, mode
, scratch_reg
)));
761 /* Handle secondary reloads for SAR. These occur when trying to load
762 the SAR from memory or from a FP register. */
763 else if (GET_CODE (operand0
) == REG
764 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
765 && (GET_CODE (operand1
) == MEM
766 || (GET_CODE (operand1
) == REG
767 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1
)))))
770 emit_move_insn (scratch_reg
, operand1
);
771 emit_move_insn (operand0
, scratch_reg
);
774 /* Handle most common case: storing into a register. */
775 else if (register_operand (operand0
, mode
))
777 if (register_operand (operand1
, mode
)
778 || (GET_CODE (operand1
) == CONST_INT
&& INT_14_BITS (operand1
))
779 || (operand1
== CONST0_RTX (mode
))
780 || (GET_CODE (operand1
) == HIGH
781 && !symbolic_operand (XEXP (operand1
, 0)))
782 /* Only `general_operands' can come here, so MEM is ok. */
783 || GET_CODE (operand1
) == MEM
)
785 /* Run this case quickly. */
786 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
790 else if (GET_CODE (operand0
) == MEM
)
792 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
794 /* Run this case quickly. */
795 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
798 if (! reload_in_progress
)
800 operands
[0] = validize_mem (operand0
);
801 operands
[1] = operand1
= force_reg (mode
, operand1
);
805 /* Simplify the source if we need to. */
806 if (GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
)
807 || (GET_CODE (operand1
) == HIGH
808 && symbolic_operand (XEXP (operand1
, 0), mode
)
813 if (GET_CODE (operand1
) == HIGH
)
816 operand1
= XEXP (operand1
, 0);
818 if (symbolic_operand (operand1
, mode
))
822 rtx temp
= reload_in_progress
? operand0
: gen_reg_rtx (Pmode
);
823 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
824 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operands
[1]));
826 /* On the HPPA, references to data space are supposed to */
827 /* use dp, register 27, but showing it in the RTL inhibits various
828 cse and loop optimizations. */
833 if (reload_in_progress
)
834 temp
= scratch_reg
? scratch_reg
: operand0
;
836 temp
= gen_reg_rtx (mode
);
839 set
= gen_rtx (SET
, mode
, operand0
, temp
);
841 set
= gen_rtx (SET
, VOIDmode
,
843 gen_rtx (LO_SUM
, mode
, temp
, operand1
));
845 emit_insn (gen_rtx (SET
, VOIDmode
,
847 gen_rtx (HIGH
, mode
, operand1
)));
848 if (function_label_operand (operand1
, mode
))
850 rtx temp
= reload_in_progress
? scratch_reg
851 : gen_reg_rtx (mode
);
854 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
857 gen_rtx (CLOBBER
, VOIDmode
,
866 else if (GET_CODE (operand1
) != CONST_INT
867 || ! cint_ok_for_move (INTVAL (operand1
)))
869 rtx temp
= reload_in_progress
? operand0
: gen_reg_rtx (mode
);
870 emit_insn (gen_rtx (SET
, VOIDmode
, temp
,
871 gen_rtx (HIGH
, mode
, operand1
)));
872 operands
[1] = gen_rtx (LO_SUM
, mode
, temp
, operand1
);
875 /* Now have insn-emit do whatever it normally does. */
879 /* Does operand (which is a symbolic_operand) live in text space? If
880 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
883 read_only_operand (operand
)
886 if (GET_CODE (operand
) == CONST
)
887 operand
= XEXP (XEXP (operand
, 0), 0);
888 if (GET_CODE (operand
) == SYMBOL_REF
)
889 return SYMBOL_REF_FLAG (operand
) || CONSTANT_POOL_ADDRESS_P (operand
);
894 /* Return the best assembler insn template
895 for moving operands[1] into operands[0] as a fullword. */
897 singlemove_string (operands
)
900 if (GET_CODE (operands
[0]) == MEM
)
902 else if (GET_CODE (operands
[1]) == MEM
)
904 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
905 && GET_MODE (operands
[1]) == SFmode
)
908 union real_extract u
;
909 union float_extract
{ float f
; int i
; } v
;
911 bcopy (&CONST_DOUBLE_LOW (operands
[1]), &u
, sizeof u
);
912 v
.f
= REAL_VALUE_TRUNCATE (SFmode
, u
.d
);
915 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
);
917 /* See if we can handle this constant in a single instruction. */
918 if (cint_ok_for_move (INTVAL (operands
[1])))
920 int intval
= INTVAL (operands
[1]);
924 else if (VAL_14_BITS_P (intval
))
926 else if ((intval
& 0x7ff) == 0)
927 return "ldil L'%1,%0";
928 else if (zdepi_cint_p (intval
))
929 return "zdepi %Z1,%0";
932 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
935 else if (GET_CODE (operands
[1]) == CONST_INT
)
937 /* See if we can handle this in a single instruction. */
938 if (cint_ok_for_move (INTVAL (operands
[1])))
940 int intval
= INTVAL (operands
[1]);
944 else if (VAL_14_BITS_P (intval
))
946 else if ((intval
& 0x7ff) == 0)
947 return "ldil L'%1,%0";
948 else if (zdepi_cint_p (intval
))
949 return "zdepi %Z1,%0";
952 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
958 /* Compute position (in OP[1]) and width (in OP[2])
959 useful for copying IMM to a register using the zdepi
960 instructions. Store the immediate value to insert in OP[0]. */
962 compute_zdepi_operands (imm
, op
)
968 /* Find the least significant set bit in IMM. */
969 for (lsb
= 0; lsb
< 32; lsb
++)
976 /* Choose variants based on *sign* of the 5-bit field. */
977 if ((imm
& 0x10) == 0)
978 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
981 /* Find the width of the bitstring in IMM. */
982 for (len
= 5; len
< 32; len
++)
984 if ((imm
& (1 << len
)) == 0)
988 /* Sign extend IMM as a 5-bit value. */
989 imm
= (imm
& 0xf) - 0x10;
997 /* Output assembler code to perform a doubleword move insn
998 with operands OPERANDS. */
1001 output_move_double (operands
)
1004 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
1006 rtx addreg0
= 0, addreg1
= 0;
1008 /* First classify both operands. */
1010 if (REG_P (operands
[0]))
1012 else if (offsettable_memref_p (operands
[0]))
1014 else if (GET_CODE (operands
[0]) == MEM
)
1019 if (REG_P (operands
[1]))
1021 else if (CONSTANT_P (operands
[1]))
1023 else if (offsettable_memref_p (operands
[1]))
1025 else if (GET_CODE (operands
[1]) == MEM
)
1030 /* Check for the cases that the operand constraints are not
1031 supposed to allow to happen. Abort if we get one,
1032 because generating code for these cases is painful. */
1034 if (optype0
!= REGOP
&& optype1
!= REGOP
)
1037 /* Handle auto decrementing and incrementing loads and stores
1038 specifically, since the structure of the function doesn't work
1039 for them without major modification. Do it better when we learn
1040 this port about the general inc/dec addressing of PA.
1041 (This was written by tege. Chide him if it doesn't work.) */
1043 if (optype0
== MEMOP
)
1045 /* We have to output the address syntax ourselves, since print_operand
1046 doesn't deal with the addresses we want to use. Fix this later. */
1048 rtx addr
= XEXP (operands
[0], 0);
1049 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1051 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1053 operands
[0] = XEXP (addr
, 0);
1054 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1057 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1059 /* No overlap between high target register and address
1060 register. (We do this in a non-obvious way to
1061 save a register file writeback) */
1062 if (GET_CODE (addr
) == POST_INC
)
1063 return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
1064 return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
1069 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1071 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1073 operands
[0] = XEXP (addr
, 0);
1074 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1077 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1079 /* No overlap between high target register and address
1080 register. (We do this in a non-obvious way to
1081 save a register file writeback) */
1082 if (GET_CODE (addr
) == PRE_INC
)
1083 return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
1084 return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
1090 if (optype1
== MEMOP
)
1092 /* We have to output the address syntax ourselves, since print_operand
1093 doesn't deal with the addresses we want to use. Fix this later. */
1095 rtx addr
= XEXP (operands
[1], 0);
1096 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1098 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1100 operands
[1] = XEXP (addr
, 0);
1101 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1104 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1106 /* No overlap between high target register and address
1107 register. (We do this in a non-obvious way to
1108 save a register file writeback) */
1109 if (GET_CODE (addr
) == POST_INC
)
1110 return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
1111 return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
1115 /* This is an undefined situation. We should load into the
1116 address register *and* update that register. Probably
1117 we don't need to handle this at all. */
1118 if (GET_CODE (addr
) == POST_INC
)
1119 return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
1120 return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
1123 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1125 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1127 operands
[1] = XEXP (addr
, 0);
1128 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1131 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1133 /* No overlap between high target register and address
1134 register. (We do this in a non-obvious way to
1135 save a register file writeback) */
1136 if (GET_CODE (addr
) == PRE_INC
)
1137 return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
1138 return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
1142 /* This is an undefined situation. We should load into the
1143 address register *and* update that register. Probably
1144 we don't need to handle this at all. */
1145 if (GET_CODE (addr
) == PRE_INC
)
1146 return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
1147 return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
1152 /* If an operand is an unoffsettable memory ref, find a register
1153 we can increment temporarily to make it refer to the second word. */
1155 if (optype0
== MEMOP
)
1156 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1158 if (optype1
== MEMOP
)
1159 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1161 /* Ok, we can do one word at a time.
1162 Normally we do the low-numbered word first.
1164 In either case, set up in LATEHALF the operands to use
1165 for the high-numbered word and in some cases alter the
1166 operands in OPERANDS to be suitable for the low-numbered word. */
1168 if (optype0
== REGOP
)
1169 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1170 else if (optype0
== OFFSOP
)
1171 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1173 latehalf
[0] = operands
[0];
1175 if (optype1
== REGOP
)
1176 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1177 else if (optype1
== OFFSOP
)
1178 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1179 else if (optype1
== CNSTOP
)
1180 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1182 latehalf
[1] = operands
[1];
1184 /* If the first move would clobber the source of the second one,
1185 do them in the other order.
1187 RMS says "This happens only for registers;
1188 such overlap can't happen in memory unless the user explicitly
1189 sets it up, and that is an undefined circumstance."
1191 but it happens on the HP-PA when loading parameter registers,
1192 so I am going to define that circumstance, and make it work
1195 if (optype0
== REGOP
&& (optype1
== MEMOP
|| optype1
== OFFSOP
)
1196 && reg_overlap_mentioned_p (operands
[0], XEXP (operands
[1], 0)))
1198 /* XXX THIS PROBABLY DOESN'T WORK. */
1199 /* Do the late half first. */
1201 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1202 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1204 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1206 return singlemove_string (operands
);
1209 if (optype0
== REGOP
&& optype1
== REGOP
1210 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1212 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1213 return singlemove_string (operands
);
1216 /* Normal case: do the two words, low-numbered first. */
1218 output_asm_insn (singlemove_string (operands
), operands
);
1220 /* Make any unoffsettable addresses point at high-numbered word. */
1222 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
1224 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1227 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1229 /* Undo the adds we just did. */
1231 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
1233 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1239 output_fp_move_double (operands
)
1242 if (FP_REG_P (operands
[0]))
1244 if (FP_REG_P (operands
[1])
1245 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1246 output_asm_insn ("fcpy,dbl %r1,%0", operands
);
1248 output_asm_insn ("fldds%F1 %1,%0", operands
);
1250 else if (FP_REG_P (operands
[1]))
1252 output_asm_insn ("fstds%F0 %1,%0", operands
);
1254 else if (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1256 if (GET_CODE (operands
[0]) == REG
)
1259 xoperands
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1260 xoperands
[0] = operands
[0];
1261 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
1263 /* This is a pain. You have to be prepared to deal with an
1264 arbritary address here including pre/post increment/decrement.
1266 so avoid this in the MD. */
1274 /* Return a REG that occurs in ADDR with coefficient 1.
1275 ADDR can be effectively incremented by incrementing REG. */
1278 find_addr_reg (addr
)
1281 while (GET_CODE (addr
) == PLUS
)
1283 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1284 addr
= XEXP (addr
, 0);
1285 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1286 addr
= XEXP (addr
, 1);
1287 else if (CONSTANT_P (XEXP (addr
, 0)))
1288 addr
= XEXP (addr
, 1);
1289 else if (CONSTANT_P (XEXP (addr
, 1)))
1290 addr
= XEXP (addr
, 0);
1294 if (GET_CODE (addr
) == REG
)
1299 /* Emit code to perform a block move.
1301 Restriction: If the length argument is non-constant, alignment
1304 OPERANDS[0] is the destination pointer as a REG, clobbered.
1305 OPERANDS[1] is the source pointer as a REG, clobbered.
1307 OPERANDS[2] is a register for temporary storage.
1308 OPERANDS[4] is the size as a CONST_INT
1310 OPERANDS[2] is a REG which will contain the size, clobbered.
1311 OPERANDS[3] is a register for temporary storage.
1312 OPERANDS[5] is the alignment safe to use, as a CONST_INT. */
1315 output_block_move (operands
, size_is_constant
)
1317 int size_is_constant
;
1319 int align
= INTVAL (operands
[5]);
1320 unsigned long n_bytes
;
1322 /* We can't move more than four bytes at a time because the PA
1323 has no longer integer move insns. (Could use fp mem ops?) */
1327 if (size_is_constant
)
1329 unsigned long n_items
;
1330 unsigned long offset
;
1333 n_bytes
= INTVAL (operands
[4]);
1339 /* Don't unroll too large blocks. */
1341 goto copy_with_loop
;
1343 /* Read and store using two registers, and hide latency
1344 by deferring the stores until three instructions after
1345 the corresponding load. The last load insn will read
1346 the entire word were the last bytes are, possibly past
1347 the end of the source block, but since loads are aligned,
1348 this is harmless. */
1350 output_asm_insn ("ldws,ma 4(0,%1),%2", operands
);
1352 for (offset
= 4; offset
< n_bytes
; offset
+= 4)
1354 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1355 output_asm_insn ("stws,ma %2,4(0,%0)", operands
);
1358 operands
[2] = operands
[3];
1361 if (n_bytes
% 4 == 0)
1362 /* Store the last word. */
1363 output_asm_insn ("stw %2,0(0,%0)", operands
);
1366 /* Store the last, partial word. */
1367 operands
[4] = gen_rtx (CONST_INT
, VOIDmode
, n_bytes
% 4);
1368 output_asm_insn ("stbys,e %2,%4(0,%0)", operands
);
1373 if (align
>= 2 && n_bytes
>= 2)
1375 output_asm_insn ("ldhs,ma 2(0,%1),%2", operands
);
1377 for (offset
= 2; offset
+ 2 <= n_bytes
; offset
+= 2)
1379 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands
);
1380 output_asm_insn ("sths,ma %2,2(0,%0)", operands
);
1383 operands
[2] = operands
[3];
1386 if (n_bytes
% 2 != 0)
1387 output_asm_insn ("ldb 0(0,%1),%3", operands
);
1389 output_asm_insn ("sths,ma %2,2(0,%0)", operands
);
1391 if (n_bytes
% 2 != 0)
1392 output_asm_insn ("stb %3,0(0,%0)", operands
);
1397 output_asm_insn ("ldbs,ma 1(0,%1),%2", operands
);
1399 for (offset
= 1; offset
+ 1 <= n_bytes
; offset
+= 1)
1401 output_asm_insn ("ldbs,ma 1(0,%1),%3", operands
);
1402 output_asm_insn ("stbs,ma %2,1(0,%0)", operands
);
1405 operands
[2] = operands
[3];
1408 output_asm_insn ("stb %2,0(0,%0)", operands
);
1418 if (size_is_constant
)
1420 /* Size is compile-time determined, and also not
1421 very small (such small cases are handled above). */
1422 operands
[4] = gen_rtx (CONST_INT
, VOIDmode
, n_bytes
- 4);
1423 output_asm_insn ("ldo %4(0),%2", operands
);
1427 /* Decrement counter by 4, and if it becomes negative, jump past the
1428 word copying loop. */
1429 output_asm_insn ("addib,<,n -4,%2,.+16", operands
);
1432 /* Copying loop. Note that the first load is in the annulled delay slot
1433 of addib. Is it OK on PA to have a load in a delay slot, i.e. is a
1434 possible page fault stopped in time? */
1435 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1436 output_asm_insn ("addib,>= -4,%2,.-4", operands
);
1437 output_asm_insn ("stws,ma %3,4(0,%0)", operands
);
1439 /* The counter is negative, >= -4. The remaining number of bytes are
1440 determined by the two least significant bits. */
1442 if (size_is_constant
)
1444 if (n_bytes
% 4 != 0)
1446 /* Read the entire word of the source block tail. */
1447 output_asm_insn ("ldw 0(0,%1),%3", operands
);
1448 operands
[4] = gen_rtx (CONST_INT
, VOIDmode
, n_bytes
% 4);
1449 output_asm_insn ("stbys,e %3,%4(0,%0)", operands
);
1454 /* Add 4 to counter. If it becomes zero, we're done. */
1455 output_asm_insn ("addib,=,n 4,%2,.+16", operands
);
1457 /* Read the entire word of the source block tail. (Also this
1458 load is in an annulled delay slot.) */
1459 output_asm_insn ("ldw 0(0,%1),%3", operands
);
1461 /* Make %0 point at the first byte after the destination block. */
1462 output_asm_insn ("add %2,%0,%0", operands
);
1463 /* Store the leftmost bytes, up to, but not including, the address
1465 output_asm_insn ("stbys,e %3,0(0,%0)", operands
);
1470 /* Count the number of insns necessary to handle this block move.
1472 Basic structure is the same as emit_block_move, except that we
1473 count insns rather than emit them. */
1476 compute_movstrsi_length (insn
)
1479 rtx pat
= PATTERN (insn
);
1480 int size_is_constant
;
1481 int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
1482 unsigned long n_bytes
;
1485 if (GET_CODE (XEXP (XVECEXP (pat
, 0, 5), 0)) == CONST_INT
)
1487 size_is_constant
= 1;
1488 n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 5), 0));
1492 size_is_constant
= 0;
1496 /* We can't move more than four bytes at a time because the PA
1497 has no longer integer move insns. (Could use fp mem ops?) */
1501 if (size_is_constant
)
1503 unsigned long n_items
;
1504 unsigned long offset
;
1512 /* Don't unroll too large blocks. */
1514 goto copy_with_loop
;
1519 /* Count the unrolled insns. */
1520 for (offset
= 4; offset
< n_bytes
; offset
+= 4)
1523 /* Count last store or partial store. */
1525 return insn_count
* 4;
1528 if (align
>= 2 && n_bytes
>= 2)
1533 /* Unrolled loop. */
1534 for (offset
= 2; offset
+ 2 <= n_bytes
; offset
+= 2)
1537 /* ??? odd load/store */
1538 if (n_bytes
% 2 != 0)
1541 /* ??? final store from loop. */
1544 return insn_count
* 4;
1550 /* The unrolled loop. */
1551 for (offset
= 1; offset
+ 1 <= n_bytes
; offset
+= 1)
1557 return insn_count
* 4;
1565 /* setup for constant and non-constant case. */
1568 /* The copying loop. */
1571 /* The counter is negative, >= -4. The remaining number of bytes are
1572 determined by the two least significant bits. */
1574 if (size_is_constant
)
1576 if (n_bytes
% 4 != 0)
1581 return insn_count
* 4;
1586 output_and (operands
)
1589 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
1591 unsigned mask
= INTVAL (operands
[2]);
1592 int ls0
, ls1
, ms0
, p
, len
;
1594 for (ls0
= 0; ls0
< 32; ls0
++)
1595 if ((mask
& (1 << ls0
)) == 0)
1598 for (ls1
= ls0
; ls1
< 32; ls1
++)
1599 if ((mask
& (1 << ls1
)) != 0)
1602 for (ms0
= ls1
; ms0
< 32; ms0
++)
1603 if ((mask
& (1 << ms0
)) == 0)
1616 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, len
);
1617 return "extru %1,31,%2,%0";
1621 /* We could use this `depi' for the case above as well, but `depi'
1622 requires one more register file access than an `extru'. */
1627 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, p
);
1628 operands
[3] = gen_rtx (CONST_INT
, VOIDmode
, len
);
1629 return "depi 0,%2,%3,%0";
1633 return "and %1,%2,%0";
1637 output_ior (operands
)
1640 unsigned mask
= INTVAL (operands
[2]);
1641 int bs0
, bs1
, bs2
, p
, len
;
1643 if (INTVAL (operands
[2]) == 0)
1644 return "copy %1,%0";
1646 for (bs0
= 0; bs0
< 32; bs0
++)
1647 if ((mask
& (1 << bs0
)) != 0)
1650 for (bs1
= bs0
; bs1
< 32; bs1
++)
1651 if ((mask
& (1 << bs1
)) == 0)
1654 if (bs1
!= 32 && ((unsigned) 1 << bs1
) <= mask
)
1660 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
, p
);
1661 operands
[3] = gen_rtx (CONST_INT
, VOIDmode
, len
);
1662 return "depi -1,%2,%3,%0";
1665 /* Output an ascii string. */
1666 output_ascii (file
, p
, size
)
1673 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
1675 /* The HP assembler can only take strings of 256 characters at one
1676 time. This is a limitation on input line length, *not* the
1677 length of the string. Sigh. Even worse, it seems that the
1678 restriction is in number of input characters (see \xnn &
1679 \whatever). So we have to do this very carefully. */
1681 fprintf (file
, "\t.STRING \"");
1684 for (i
= 0; i
< size
; i
+= 4)
1688 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
1690 register unsigned int c
= p
[i
+ io
];
1692 if (c
== '\"' || c
== '\\')
1693 partial_output
[co
++] = '\\';
1694 if (c
>= ' ' && c
< 0177)
1695 partial_output
[co
++] = c
;
1699 partial_output
[co
++] = '\\';
1700 partial_output
[co
++] = 'x';
1701 hexd
= c
/ 16 - 0 + '0';
1703 hexd
-= '9' - 'a' + 1;
1704 partial_output
[co
++] = hexd
;
1705 hexd
= c
% 16 - 0 + '0';
1707 hexd
-= '9' - 'a' + 1;
1708 partial_output
[co
++] = hexd
;
1711 if (chars_output
+ co
> 243)
1713 fprintf (file
, "\"\n\t.STRING \"");
1716 fwrite (partial_output
, 1, co
, file
);
1720 fprintf (file
, "\"\n");
1723 /* You may have trouble believing this, but this is the HP-PA stack
1728 Variable arguments (optional; any number may be allocated)
1730 SP-(4*(N+9)) arg word N
1735 Fixed arguments (must be allocated; may remain unused)
1744 SP-32 External Data Pointer (DP)
1746 SP-24 External/stub RP (RP')
1750 SP-8 Calling Stub RP (RP'')
1755 SP-0 Stack Pointer (points to next available address)
1759 /* This function saves registers as follows. Registers marked with ' are
1760 this function's registers (as opposed to the previous function's).
1761 If a frame_pointer isn't needed, r4 is saved as a general register;
1762 the space for the frame pointer is still allocated, though, to keep
1768 SP (FP') Previous FP
1769 SP + 4 Alignment filler (sigh)
1770 SP + 8 Space for locals reserved here.
1774 SP + n All call saved register used.
1778 SP + o All call saved fp registers used.
1782 SP + p (SP') points to next available address.
1786 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
1787 Handle case where DISP > 8k by using the add_high_const pattern.
1789 Note in DISP > 8k case, we will leave the high part of the address
1790 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1792 store_reg (reg
, disp
, base
)
1793 int reg
, disp
, base
;
1795 if (VAL_14_BITS_P (disp
))
1797 emit_move_insn (gen_rtx (MEM
, SImode
,
1798 gen_rtx (PLUS
, SImode
,
1799 gen_rtx (REG
, SImode
, base
),
1801 gen_rtx (REG
, SImode
, reg
));
1805 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
1806 gen_rtx (REG
, SImode
, base
),
1808 emit_move_insn (gen_rtx (MEM
, SImode
,
1809 gen_rtx (LO_SUM
, SImode
,
1810 gen_rtx (REG
, SImode
, 1),
1812 gen_rtx (REG
, SImode
, reg
));
1816 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
1817 Handle case where DISP > 8k by using the add_high_const pattern.
1819 Note in DISP > 8k case, we will leave the high part of the address
1820 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1822 load_reg (reg
, disp
, base
)
1823 int reg
, disp
, base
;
1825 if (VAL_14_BITS_P (disp
))
1827 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1828 gen_rtx (MEM
, SImode
,
1829 gen_rtx (PLUS
, SImode
,
1830 gen_rtx (REG
, SImode
, base
),
1836 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
1837 gen_rtx (REG
, SImode
, base
),
1839 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1840 gen_rtx (MEM
, SImode
,
1841 gen_rtx (LO_SUM
, SImode
,
1842 gen_rtx (REG
, SImode
, 1),
1847 /* Emit RTL to set REG to the value specified by BASE+DISP.
1848 Handle case where DISP > 8k by using the add_high_const pattern.
1850 Note in DISP > 8k case, we will leave the high part of the address
1851 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1853 set_reg_plus_d(reg
, base
, disp
)
1854 int reg
, base
, disp
;
1856 if (VAL_14_BITS_P (disp
))
1858 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1859 gen_rtx (PLUS
, SImode
,
1860 gen_rtx (REG
, SImode
, base
),
1866 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
1867 gen_rtx (REG
, SImode
, base
),
1869 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1870 gen_rtx (LO_SUM
, SImode
,
1871 gen_rtx (REG
, SImode
, 1),
1876 /* Global variables set by FUNCTION_PROLOGUE. */
1877 /* Size of frame. Need to know this to emit return insns from
1879 static int actual_fsize
;
1880 static int local_fsize
, save_fregs
;
1883 compute_frame_size (size
, fregs_live
)
1887 extern int current_function_outgoing_args_size
;
1890 /* 8 is space for frame pointer + filler. If any frame is allocated
1891 we need to add this in because of STARTING_FRAME_OFFSET. */
1892 fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
1894 /* fp is stored in a special place. */
1895 if (frame_pointer_needed
)
1897 for (i
= 18; i
>= 5; i
--)
1898 if (regs_ever_live
[i
])
1901 if (regs_ever_live
[3])
1906 for (i
= 18; i
>= 3; i
--)
1907 if (regs_ever_live
[i
])
1910 fsize
= (fsize
+ 7) & ~7;
1914 for (i
= 43; i
>= 40; i
--)
1915 if (regs_ever_live
[i
])
1924 for (i
= 78; i
>= 60; i
-= 2)
1925 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
1932 fsize
+= current_function_outgoing_args_size
;
1933 if (! leaf_function_p () || fsize
)
1935 return TARGET_SNAKE
? (fsize
+ 63 & ~63) : fsize
;
1938 rtx hp_profile_label_rtx
;
1939 static char hp_profile_label_name
[8];
1941 output_function_prologue (file
, size
)
1946 /* hppa_expand_prologue does the dirty work now. We just need
1947 to output the assembler directives which denote the start
1949 fprintf (file
, "\t.PROC\n\t.CALLINFO FRAME=%d", actual_fsize
);
1950 if (regs_ever_live
[2] || profile_flag
)
1951 fprintf (file
, ",CALLS,SAVE_RP");
1953 fprintf (file
, ",NO_CALLS");
1955 if (frame_pointer_needed
)
1956 fprintf (file
, ",SAVE_SP");
1958 fprintf (file
, "\n\t.ENTRY\n");
1960 /* Horrid hack. emit_function_prologue will modify this RTL in
1961 place to get the expected results. */
1963 sprintf(hp_profile_label_name
, "LP$%04d", hp_profile_labelno
);
1966 hppa_expand_prologue()
1969 extern char call_used_regs
[];
1970 int size
= get_frame_size ();
1971 int merge_sp_adjust_with_store
= 0;
1973 rtx tmpreg
, size_rtx
;
1977 local_fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
1978 actual_fsize
= compute_frame_size (size
, &save_fregs
);
1980 /* Compute a few things we will use often. */
1981 tmpreg
= gen_rtx (REG
, SImode
, 1);
1982 size_rtx
= GEN_INT (actual_fsize
);
1984 /* Save RP first. The calling conventions manual states RP will
1985 always be stored into the caller's frame at sp-20. */
1986 if (regs_ever_live
[2] || profile_flag
)
1987 store_reg (2, -20, STACK_POINTER_REGNUM
);
1989 /* Allocate the local frame and set up the frame pointer if needed. */
1991 if (frame_pointer_needed
)
1993 /* Copy the old frame pointer temporarily into %r1. Set up the
1994 new stack pointer, then store away the saved old frame pointer
1995 into the stack at sp+actual_fsize and at the same time update
1996 the stack pointer by actual_fsize bytes. Two versions, first
1997 handles small (<8k) frames. The second handles large (>8k)
1999 emit_move_insn (tmpreg
, frame_pointer_rtx
);
2000 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
2001 if (VAL_14_BITS_P (actual_fsize
))
2002 emit_insn (gen_post_stwm (stack_pointer_rtx
,
2007 store_reg (1, 0, FRAME_POINTER_REGNUM
);
2008 set_reg_plus_d (STACK_POINTER_REGNUM
,
2009 STACK_POINTER_REGNUM
,
2013 /* no frame pointer needed. */
2016 /* In some cases we can perform the first callee register save
2017 and allocating the stack frame at the same time. If so, just
2018 make a note of it and defer allocating the frame until saving
2019 the callee registers. */
2020 if (VAL_14_BITS_P (-actual_fsize
)
2024 merge_sp_adjust_with_store
= 1;
2025 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2026 else if (actual_fsize
!= 0)
2027 set_reg_plus_d (STACK_POINTER_REGNUM
,
2028 STACK_POINTER_REGNUM
,
2031 /* The hppa calling conventions say that that %r19, the pic offset
2032 register, is saved at sp - 32 (in this function's frame) when
2033 generating PIC code. */
2035 store_reg (19, -32, STACK_POINTER_REGNUM
);
2039 Instead of taking one argument, the counter label, as most normal
2040 mcounts do, _mcount appears to behave differently on the HPPA. It
2041 takes the return address of the caller, the address of this routine,
2042 and the address of the label. Also, it isn't magic, so
2043 argument registre hsave to be preserved. */
2046 int pc_offset
, i
, arg_offset
, basereg
, offsetadj
;
2048 pc_offset
= 4 + (frame_pointer_needed
2049 ? (VAL_14_BITS_P (actual_fsize
) ? 12 : 20)
2050 : (VAL_14_BITS_P (actual_fsize
) ? 4 : 8));
2052 /* When the function has a frame pointer, use it as the base
2053 register for saving/restore registers. Else use the stack
2054 pointer. Adjust the offset according to the frame size if
2055 this function does not have a frame pointer. */
2057 basereg
= frame_pointer_needed
? FRAME_POINTER_REGNUM
2058 : STACK_POINTER_REGNUM
;
2059 offsetadj
= frame_pointer_needed
? 0 : actual_fsize
;
2061 /* Horrid hack. emit_function_prologue will modify this RTL in
2062 place to get the expected results. sprintf here is just to
2063 put something in the name. */
2064 sprintf(hp_profile_label_name
, "LP$%04d", -1);
2065 hp_profile_label_rtx
= gen_rtx (SYMBOL_REF
, SImode
,
2066 hp_profile_label_name
);
2067 if (current_function_returns_struct
)
2068 store_reg (STRUCT_VALUE_REGNUM
, - 12 - offsetadj
, basereg
);
2070 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2071 if (regs_ever_live
[i
])
2073 store_reg (i
, arg_offset
, basereg
);
2074 /* Deal with arg_offset not fitting in 14 bits. */
2075 pc_offset
+= VAL_14_BITS_P (arg_offset
) ? 4 : 8;
2078 emit_move_insn (gen_rtx (REG
, SImode
, 26), gen_rtx (REG
, SImode
, 2));
2079 emit_move_insn (tmpreg
, gen_rtx (HIGH
, SImode
, hp_profile_label_rtx
));
2080 emit_move_insn (gen_rtx (REG
, SImode
, 24),
2081 gen_rtx (LO_SUM
, SImode
, tmpreg
, hp_profile_label_rtx
));
2082 /* %r25 is set from within the output pattern. */
2083 emit_insn (gen_call_profiler (GEN_INT (- pc_offset
- 20)));
2085 /* Restore argument registers. */
2086 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2087 if (regs_ever_live
[i
])
2088 load_reg (i
, arg_offset
, basereg
);
2090 if (current_function_returns_struct
)
2091 load_reg (STRUCT_VALUE_REGNUM
, -12 - offsetadj
, basereg
);
2095 /* Normal register save.
2097 Do not save the frame pointer in the frame_pointer_needed case. It
2098 was done earlier. */
2099 if (frame_pointer_needed
)
2101 for (i
= 18, offset
= local_fsize
; i
>= 3; i
--)
2102 if (regs_ever_live
[i
] && ! call_used_regs
[i
]
2103 && i
!= FRAME_POINTER_REGNUM
)
2105 store_reg (i
, offset
, FRAME_POINTER_REGNUM
);
2109 /* No frame pointer needed. */
2112 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
2113 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2115 /* If merge_sp_adjust_with_store is nonzero, then we can
2116 optimize the first GR save. */
2117 if (merge_sp_adjust_with_store
)
2119 merge_sp_adjust_with_store
= 0;
2120 emit_insn (gen_post_stwm (stack_pointer_rtx
,
2123 gen_rtx (REG
, SImode
, i
)));
2126 store_reg (i
, offset
, STACK_POINTER_REGNUM
);
2130 /* If we wanted to merge the SP adjustment with a GR save, but we never
2131 did any GR saves, then just emit the adjustment here. */
2132 if (merge_sp_adjust_with_store
)
2133 set_reg_plus_d (STACK_POINTER_REGNUM
,
2134 STACK_POINTER_REGNUM
,
2138 /* Align pointer properly (doubleword boundary). */
2139 offset
= (offset
+ 7) & ~7;
2141 /* Floating point register store. */
2145 /* First get the frame or stack pointer to the start of the FP register
2147 if (frame_pointer_needed
)
2148 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
2150 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
2152 /* Now actually save the FP registers. */
2155 for (i
= 43; i
>= 40; i
--)
2157 if (regs_ever_live
[i
])
2158 emit_move_insn (gen_rtx (MEM
, DFmode
,
2159 gen_rtx (POST_INC
, DFmode
, tmpreg
)),
2160 gen_rtx (REG
, DFmode
, i
));
2165 for (i
= 78; i
>= 60; i
-= 2)
2166 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2168 emit_move_insn (gen_rtx (MEM
, DFmode
,
2169 gen_rtx (POST_INC
, DFmode
, tmpreg
)),
2170 gen_rtx (REG
, DFmode
, i
));
2178 output_function_epilogue (file
, size
)
2183 rtx insn
= get_last_insn ();
2185 /* hppa_expand_epilogue does the dirty work now. We just need
2186 to output the assembler directives which denote the end
2189 To make debuggers happy, emit a nop if the epilogue was completely
2190 eliminated due to a volatile call as the last insn in the
2191 current function. That way the return address (in %r2) will
2192 always point to a valid instruction in the current function. */
2194 /* Get the last real insn. */
2195 if (GET_CODE (insn
) == NOTE
)
2196 insn
= prev_real_insn (insn
);
2198 /* If it is a sequence, then look inside. */
2199 if (insn
&& GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2200 insn
= XVECEXP (PATTERN (insn
), 0, 0);
2202 /* If insn is a CALL_INSN, then it must be a call to a volatile
2203 function (otherwise there would be epilogue insns). */
2204 if (insn
&& GET_CODE (insn
) == CALL_INSN
)
2205 fprintf (file
, "\tnop\n");
2207 fprintf (file
, "\t.EXIT\n\t.PROCEND\n");
2211 hppa_expand_epilogue ()
2215 int merge_sp_adjust_with_load
= 0;
2217 /* We will use this often. */
2218 tmpreg
= gen_rtx (REG
, SImode
, 1);
2220 /* Try to restore RP early to avoid load/use interlocks when
2221 RP gets used in the return (bv) instruction. This appears to still
2222 be necessary even when we schedule the prologue and epilogue. */
2223 if (frame_pointer_needed
2224 && (regs_ever_live
[2] || profile_flag
))
2225 load_reg (2, -20, FRAME_POINTER_REGNUM
);
2227 /* No frame pointer, and stack is smaller than 8k. */
2228 else if (! frame_pointer_needed
2229 && VAL_14_BITS_P (actual_fsize
+ 20)
2230 && (regs_ever_live
[2] || profile_flag
))
2231 load_reg (2, - (actual_fsize
+ 20), STACK_POINTER_REGNUM
);
2233 /* General register restores. */
2234 if (frame_pointer_needed
)
2236 for (i
= 18, offset
= local_fsize
; i
>= 3; i
--)
2237 if (regs_ever_live
[i
] && ! call_used_regs
[i
]
2238 && i
!= FRAME_POINTER_REGNUM
)
2240 load_reg (i
, offset
, FRAME_POINTER_REGNUM
);
2246 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
2247 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2249 /* Only for the first load.
2250 merge_sp_adjust_with_load holds the register load
2251 with which we will merge the sp adjustment. */
2252 if (VAL_14_BITS_P (actual_fsize
+ 20)
2254 && ! merge_sp_adjust_with_load
)
2255 merge_sp_adjust_with_load
= i
;
2257 load_reg (i
, offset
, STACK_POINTER_REGNUM
);
2262 /* Align pointer properly (doubleword boundary). */
2263 offset
= (offset
+ 7) & ~7;
2265 /* FP register restores. */
2268 /* Adjust the register to index off of. */
2269 if (frame_pointer_needed
)
2270 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
2272 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
2274 /* Actually do the restores now. */
2277 for (i
= 43; i
>= 40; i
--)
2278 if (regs_ever_live
[i
])
2279 emit_move_insn (gen_rtx (REG
, DFmode
, i
),
2280 gen_rtx (MEM
, DFmode
,
2281 gen_rtx (POST_INC
, DFmode
, tmpreg
)));
2286 for (i
= 78; i
>= 60; i
-= 2)
2287 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2288 emit_move_insn (gen_rtx (REG
, DFmode
, i
),
2289 gen_rtx (MEM
, DFmode
,
2290 gen_rtx (POST_INC
, DFmode
, tmpreg
)));
2294 /* No frame pointer, but we have a stack greater than 8k. We restore
2295 %r2 very late in this case. (All other cases are restored as early
2297 if (! frame_pointer_needed
2298 && ! VAL_14_BITS_P (actual_fsize
+ 20)
2299 && (regs_ever_live
[2] || profile_flag
))
2301 set_reg_plus_d (STACK_POINTER_REGNUM
,
2302 STACK_POINTER_REGNUM
,
2304 /* Uses value left over in %r1 by set_reg_plus_d. */
2305 load_reg (2, - (actual_fsize
+ 20 + ((- actual_fsize
) & ~0x7ff)), 1);
2308 /* Reset stack pointer (and possibly frame pointer). The stack */
2309 /* pointer is initially set to fp + 64 to avoid a race condition.
2310 ??? What race condition?!? */
2311 else if (frame_pointer_needed
)
2313 /* Emit a blockage insn here to keep these insns from being moved
2314 to the beginning of the prologue or into the main instruction
2315 stream, doing so avoids some very obscure problems. */
2316 emit_insn (gen_blockage ());
2317 set_reg_plus_d (STACK_POINTER_REGNUM
, FRAME_POINTER_REGNUM
, 64);
2318 emit_insn (gen_pre_ldwm (stack_pointer_rtx
, stack_pointer_rtx
,
2319 GEN_INT (-64), frame_pointer_rtx
));
2321 /* If we were deferring a callee register restore, do it now. */
2322 else if (! frame_pointer_needed
&& merge_sp_adjust_with_load
)
2323 emit_insn (gen_pre_ldwm (stack_pointer_rtx
,
2325 GEN_INT (- actual_fsize
),
2326 gen_rtx (REG
, SImode
,
2327 merge_sp_adjust_with_load
)));
2328 else if (actual_fsize
!= 0)
2329 set_reg_plus_d (STACK_POINTER_REGNUM
,
2330 STACK_POINTER_REGNUM
,
2334 /* This is only valid once reload has completed because it depends on
2335 knowing exactly how much (if any) frame there is and...
2337 It's only valid if there is no frame marker to de-allocate and...
2339 It's only valid if %r2 hasn't been saved into the caller's frame
2340 (we're not profiling and %r2 isn't live anywhere). */
2342 hppa_can_use_return_insn_p ()
2344 return (reload_completed
2345 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
2347 && ! regs_ever_live
[2]
2348 && ! frame_pointer_needed
);
2352 emit_bcond_fp (code
, operand0
)
2356 emit_jump_insn (gen_rtx (SET
, VOIDmode
, pc_rtx
,
2357 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2358 gen_rtx (code
, VOIDmode
,
2359 gen_rtx (REG
, CCFPmode
, 0),
2361 gen_rtx (LABEL_REF
, VOIDmode
, operand0
),
2367 gen_cmp_fp (code
, operand0
, operand1
)
2369 rtx operand0
, operand1
;
2371 return gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, CCFPmode
, 0),
2372 gen_rtx (code
, CCFPmode
, operand0
, operand1
));
2375 /* Adjust the cost of a scheduling dependency. Return the new cost of
2376 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2379 pa_adjust_cost (insn
, link
, dep_insn
, cost
)
2385 if (! recog_memoized (insn
))
2388 if (REG_NOTE_KIND (link
) == 0)
2390 /* Data dependency; DEP_INSN writes a register that INSN reads some
2393 if (get_attr_type (insn
) == TYPE_FPSTORE
)
2395 rtx pat
= PATTERN (insn
);
2396 rtx dep_pat
= PATTERN (dep_insn
);
2397 if (GET_CODE (pat
) == PARALLEL
)
2399 /* This happens for the fstXs,mb patterns. */
2400 pat
= XVECEXP (pat
, 0, 0);
2402 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
2403 /* If this happens, we have to extend this to schedule
2404 optimally. Return 0 for now. */
2407 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
2409 if (! recog_memoized (dep_insn
))
2411 /* DEP_INSN is writing its result to the register
2412 being stored in the fpstore INSN. */
2413 switch (get_attr_type (dep_insn
))
2416 /* This cost 3 cycles, not 2 as the md says. */
2423 case TYPE_FPSQRTSGL
:
2424 case TYPE_FPSQRTDBL
:
2425 /* In these important cases, we save one cycle compared to
2426 when flop instruction feed each other. */
2435 /* For other data dependencies, the default cost specified in the
2439 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
2441 /* Anti dependency; DEP_INSN reads a register that INSN writes some
2444 if (get_attr_type (insn
) == TYPE_FPLOAD
)
2446 rtx pat
= PATTERN (insn
);
2447 rtx dep_pat
= PATTERN (dep_insn
);
2448 if (GET_CODE (pat
) == PARALLEL
)
2450 /* This happens for the fldXs,mb patterns. */
2451 pat
= XVECEXP (pat
, 0, 0);
2453 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
2454 /* If this happens, we have to extend this to schedule
2455 optimally. Return 0 for now. */
2458 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
2460 if (! recog_memoized (dep_insn
))
2462 switch (get_attr_type (dep_insn
))
2468 case TYPE_FPSQRTSGL
:
2469 case TYPE_FPSQRTDBL
:
2470 /* A fpload can't be issued until one cycle before a
2471 preceeding arithmetic operation has finished, if
2472 the target of the fpload is any of the sources
2473 (or destination) of the arithmetic operation. */
2482 /* For other anti dependencies, the cost is 0. */
2486 /* For output dependencies, the cost is often one too high. */
2490 /* Return any length adjustment needed by INSN which already has its length
2491 computed as LENGTH. Return zero if no adjustment is necessary.
2493 For the PA: function calls, millicode calls, and backwards short
2494 conditional branches with unfilled delay slots need an adjustment by +1
2495 (to account for the NOP which will be inserted into the instruction stream).
2497 Also compute the length of an inline block move here as it is too
2498 complicated to express as a length attribute in pa.md. */
2500 pa_adjust_insn_length (insn
, length
)
2504 rtx pat
= PATTERN (insn
);
2506 /* Call insns which are *not* indirect and have unfilled delay slots. */
2507 if (GET_CODE (insn
) == CALL_INSN
)
2510 if (GET_CODE (XVECEXP (pat
, 0, 0)) == CALL
2511 && GET_CODE (XEXP (XEXP (XVECEXP (pat
, 0, 0), 0), 0)) == SYMBOL_REF
)
2513 else if (GET_CODE (XVECEXP (pat
, 0, 0)) == SET
2514 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat
, 0, 0), 1), 0), 0))
2520 /* Millicode insn with an unfilled delay slot. */
2521 else if (GET_CODE (insn
) == INSN
2522 && GET_CODE (pat
) != SEQUENCE
2523 && GET_CODE (pat
) != USE
2524 && GET_CODE (pat
) != CLOBBER
2525 && get_attr_type (insn
) == TYPE_MILLI
)
2527 /* Block move pattern. */
2528 else if (GET_CODE (insn
) == INSN
2529 && GET_CODE (pat
) == PARALLEL
2530 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
2531 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
2532 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
2533 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
2534 return compute_movstrsi_length (insn
) - 4;
2535 /* Conditional branch with an unfilled delay slot. */
2536 else if (GET_CODE (insn
) == JUMP_INSN
&& ! simplejump_p (insn
))
2538 /* Adjust a short backwards conditional with an unfilled delay slot. */
2539 if (GET_CODE (pat
) == SET
2541 && ! forward_branch_p (insn
))
2543 /* Adjust dbra insn with short backwards conditional branch with
2544 unfilled delay slot -- only for case where counter is in a
2545 general register register. */
2546 else if (GET_CODE (pat
) == PARALLEL
2547 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
2548 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
2549 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
2551 && ! forward_branch_p (insn
))
2560 /* Print operand X (an rtx) in assembler syntax to file FILE.
2561 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2562 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2565 print_operand (file
, x
, code
)
2573 /* Output a 'nop' if there's nothing for the delay slot. */
2574 if (dbr_sequence_length () == 0)
2575 fputs ("\n\tnop", file
);
2578 /* Output an nullification completer if there's nothing for the */
2579 /* delay slot or nullification is requested. */
2580 if (dbr_sequence_length () == 0 ||
2582 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
2586 /* Print out the second register name of a register pair.
2587 I.e., R (6) => 7. */
2588 fputs (reg_names
[REGNO (x
)+1], file
);
2591 /* A register or zero. */
2593 || (x
== CONST0_RTX (DFmode
))
2594 || (x
== CONST0_RTX (SFmode
)))
2601 case 'C': /* Plain (C)ondition */
2603 switch (GET_CODE (x
))
2606 fprintf (file
, "="); break;
2608 fprintf (file
, "<>"); break;
2610 fprintf (file
, ">"); break;
2612 fprintf (file
, ">="); break;
2614 fprintf (file
, ">>="); break;
2616 fprintf (file
, ">>"); break;
2618 fprintf (file
, "<"); break;
2620 fprintf (file
, "<="); break;
2622 fprintf (file
, "<<="); break;
2624 fprintf (file
, "<<"); break;
2626 printf ("Can't grok '%c' operator:\n", code
);
2631 case 'N': /* Condition, (N)egated */
2632 switch (GET_CODE (x
))
2635 fprintf (file
, "<>"); break;
2637 fprintf (file
, "="); break;
2639 fprintf (file
, "<="); break;
2641 fprintf (file
, "<"); break;
2643 fprintf (file
, "<<"); break;
2645 fprintf (file
, "<<="); break;
2647 fprintf (file
, ">="); break;
2649 fprintf (file
, ">"); break;
2651 fprintf (file
, ">>"); break;
2653 fprintf (file
, ">>="); break;
2655 printf ("Can't grok '%c' operator:\n", code
);
2660 /* For floating point comparisons. Need special conditions to deal
2661 with NaNs properly. */
2663 switch (GET_CODE (x
))
2666 fprintf (file
, "!="); break;
2668 fprintf (file
, "="); break;
2670 fprintf (file
, "!>"); break;
2672 fprintf (file
, "!>="); break;
2674 fprintf (file
, "!<"); break;
2676 fprintf (file
, "!<="); break;
2678 printf ("Can't grok '%c' operator:\n", code
);
2683 case 'S': /* Condition, operands are (S)wapped. */
2684 switch (GET_CODE (x
))
2687 fprintf (file
, "="); break;
2689 fprintf (file
, "<>"); break;
2691 fprintf (file
, "<"); break;
2693 fprintf (file
, "<="); break;
2695 fprintf (file
, "<<="); break;
2697 fprintf (file
, "<<"); break;
2699 fprintf (file
, ">"); break;
2701 fprintf (file
, ">="); break;
2703 fprintf (file
, ">>="); break;
2705 fprintf (file
, ">>"); break;
2707 printf ("Can't grok '%c' operator:\n", code
);
2712 case 'B': /* Condition, (B)oth swapped and negate. */
2713 switch (GET_CODE (x
))
2716 fprintf (file
, "<>"); break;
2718 fprintf (file
, "="); break;
2720 fprintf (file
, ">="); break;
2722 fprintf (file
, ">"); break;
2724 fprintf (file
, ">>"); break;
2726 fprintf (file
, ">>="); break;
2728 fprintf (file
, "<="); break;
2730 fprintf (file
, "<"); break;
2732 fprintf (file
, "<<"); break;
2734 fprintf (file
, "<<="); break;
2736 printf ("Can't grok '%c' operator:\n", code
);
2742 if (GET_CODE (x
) == CONST_INT
)
2744 fprintf (file
, "%d", ~INTVAL (x
));
2749 if (GET_CODE (x
) == CONST_INT
)
2751 fprintf (file
, "%d", 32 - (INTVAL (x
) & 31));
2756 if (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0)
2758 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
2763 if (GET_CODE (x
) == CONST_INT
)
2765 fprintf (file
, "%d", 31 - (INTVAL (x
) & 31));
2770 if (GET_CODE (x
) == CONST_INT
)
2774 switch (GET_CODE (XEXP (x
, 0)))
2778 fprintf (file
, "s,mb");
2782 fprintf (file
, "s,ma");
2789 switch (GET_CODE (XEXP (x
, 0)))
2793 fprintf (file
, ",mb");
2797 fprintf (file
, ",ma");
2804 output_global_address (file
, x
);
2806 case 0: /* Don't do anything special */
2811 compute_zdepi_operands (INTVAL (x
), op
);
2812 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
2818 if (GET_CODE (x
) == REG
)
2819 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
2820 else if (GET_CODE (x
) == MEM
)
2822 int size
= GET_MODE_SIZE (GET_MODE (x
));
2823 rtx base
= XEXP (XEXP (x
, 0), 0);
2824 switch (GET_CODE (XEXP (x
, 0)))
2828 fprintf (file
, "-%d(0,%s)", size
, reg_names
[REGNO (base
)]);
2832 fprintf (file
, "%d(0,%s)", size
, reg_names
[REGNO (base
)]);
2835 output_address (XEXP (x
, 0));
2839 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
2841 union { double d
; int i
[2]; } u
;
2842 union { float f
; int i
; } u1
;
2843 u
.i
[0] = XINT (x
, 0); u
.i
[1] = XINT (x
, 1);
2846 fprintf (file
, "0r%.9g", u1
.f
);
2848 fprintf (file
, "0x%x", u1
.i
);
2850 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != DImode
)
2852 union { double d
; int i
[2]; } u
;
2853 u
.i
[0] = XINT (x
, 0); u
.i
[1] = XINT (x
, 1);
2854 fprintf (file
, "0r%.20g", u
.d
);
2857 output_addr_const (file
, x
);
2860 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
2863 output_global_address (file
, x
)
2868 /* Imagine (high (const (plus ...))). */
2869 if (GET_CODE (x
) == HIGH
)
2872 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
))
2873 assemble_name (file
, XSTR (x
, 0));
2874 else if (GET_CODE (x
) == SYMBOL_REF
)
2876 assemble_name (file
, XSTR (x
, 0));
2877 fprintf (file
, "-$global$");
2879 else if (GET_CODE (x
) == CONST
)
2882 int offset
= 0; /* assembler wants -$global$ at end */
2885 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
2887 base
= XEXP (XEXP (x
, 0), 0);
2888 output_addr_const (file
, base
);
2890 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == CONST_INT
)
2891 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
2894 if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == SYMBOL_REF
)
2896 base
= XEXP (XEXP (x
, 0), 1);
2897 output_addr_const (file
, base
);
2899 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2900 offset
= INTVAL (XEXP (XEXP (x
, 0),1));
2903 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2913 else if (GET_CODE (XEXP (x
, 0)) == MINUS
2914 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
2918 if (!read_only_operand (base
))
2919 fprintf (file
, "-$global$");
2920 fprintf (file
, "%s", sep
);
2921 if (offset
) fprintf (file
,"%d", offset
);
2924 output_addr_const (file
, x
);
2927 /* HP's millicode routines mean something special to the assembler.
2928 Keep track of which ones we have used. */
2930 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, mulU
, end1000
};
2931 static char imported
[(int)end1000
];
2932 static char *milli_names
[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
2933 static char import_string
[] = ".IMPORT $$....,MILLICODE";
2934 #define MILLI_START 10
2938 enum millicodes code
;
2940 char str
[sizeof (import_string
)];
2942 if (!imported
[(int)code
])
2944 imported
[(int)code
] = 1;
2945 strcpy (str
, import_string
);
2946 strncpy (str
+ MILLI_START
, milli_names
[(int)code
], 4);
2947 output_asm_insn (str
, 0);
2951 /* The register constraints have put the operands and return value in
2952 the proper registers. */
2955 output_mul_insn (unsignedp
, insn
)
2962 import_milli (mulU
);
2963 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$mulU"),
2964 gen_rtx (REG
, SImode
, 31));
2968 import_milli (mulI
);
2969 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$mulI"),
2970 gen_rtx (REG
, SImode
, 31));
2974 /* If operands isn't NULL, then it's a CONST_INT with which we can do
2978 /* Emit the rtl for doing a division by a constant. */
2980 /* Do magic division millicodes exist for this value? */
2982 static int magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
2985 /* We'll use an array to keep track of the magic millicodes and
2986 whether or not we've used them already. [n][0] is signed, [n][1] is
2989 static int div_milli
[16][2];
2992 div_operand (op
, mode
)
2994 enum machine_mode mode
;
2996 return (mode
== SImode
2997 && ((GET_CODE (op
) == REG
&& REGNO (op
) == 25)
2998 || (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) > 0
2999 && INTVAL (op
) < 16 && magic_milli
[INTVAL (op
)])));
3003 emit_hpdiv_const (operands
, unsignedp
)
3007 if (GET_CODE (operands
[2]) == CONST_INT
3008 && INTVAL (operands
[2]) > 0
3009 && INTVAL (operands
[2]) < 16
3010 && magic_milli
[INTVAL (operands
[2])])
3012 emit_move_insn ( gen_rtx (REG
, SImode
, 26), operands
[1]);
3015 (PARALLEL
, VOIDmode
,
3016 gen_rtvec (5, gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, SImode
, 29),
3017 gen_rtx (unsignedp
? UDIV
: DIV
, SImode
,
3018 gen_rtx (REG
, SImode
, 26),
3020 gen_rtx (CLOBBER
, VOIDmode
, operands
[3]),
3021 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 26)),
3022 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 25)),
3023 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 31)))));
3024 emit_move_insn (operands
[0], gen_rtx (REG
, SImode
, 29));
3031 output_div_insn (operands
, unsignedp
, insn
)
3038 /* If the divisor is a constant, try to use one of the special
3040 if (GET_CODE (operands
[0]) == CONST_INT
)
3042 static char buf
[100];
3043 divisor
= INTVAL (operands
[0]);
3044 if (!div_milli
[divisor
][unsignedp
])
3046 div_milli
[divisor
][unsignedp
] = 1;
3048 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
3050 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
3054 sprintf (buf
, "$$divU_%d", INTVAL (operands
[0]));
3055 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, buf
),
3056 gen_rtx (REG
, SImode
, 31));
3060 sprintf (buf
, "$$divI_%d", INTVAL (operands
[0]));
3061 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, buf
),
3062 gen_rtx (REG
, SImode
, 31));
3065 /* Divisor isn't a special constant. */
3070 import_milli (divU
);
3071 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$divU"),
3072 gen_rtx (REG
, SImode
, 31));
3076 import_milli (divI
);
3077 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$divI"),
3078 gen_rtx (REG
, SImode
, 31));
3083 /* Output a $$rem millicode to do mod. */
3086 output_mod_insn (unsignedp
, insn
)
3092 import_milli (remU
);
3093 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$remU"),
3094 gen_rtx (REG
, SImode
, 31));
3098 import_milli (remI
);
3099 return output_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$remI"),
3100 gen_rtx (REG
, SImode
, 31));
3105 output_arg_descriptor (insn
)
3109 enum machine_mode arg_mode
;
3111 int i
, output_flag
= 0;
3114 for (i
= 0; i
< 4; i
++)
3117 for (prev_insn
= PREV_INSN (insn
); GET_CODE (prev_insn
) == INSN
;
3118 prev_insn
= PREV_INSN (prev_insn
))
3120 if (!(GET_CODE (PATTERN (prev_insn
)) == USE
&&
3121 GET_CODE (XEXP (PATTERN (prev_insn
), 0)) == REG
&&
3122 FUNCTION_ARG_REGNO_P (REGNO (XEXP (PATTERN (prev_insn
), 0)))))
3124 arg_mode
= GET_MODE (XEXP (PATTERN (prev_insn
), 0));
3125 regno
= REGNO (XEXP (PATTERN (prev_insn
), 0));
3126 if (regno
>= 23 && regno
<= 26)
3128 arg_regs
[26 - regno
] = "GR";
3129 if (arg_mode
== DImode
)
3130 arg_regs
[25 - regno
] = "GR";
3132 else if (!TARGET_SNAKE
) /* fp args */
3134 if (arg_mode
== SFmode
)
3135 arg_regs
[regno
- 32] = "FR";
3138 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
3139 arg_regs
[regno
- 33] = "FR";
3140 arg_regs
[regno
- 32] = "FU";
3142 arg_regs
[regno
- 33] = "FU";
3143 arg_regs
[regno
- 32] = "FR";
3149 if (arg_mode
== SFmode
)
3150 arg_regs
[(regno
- 44) / 2] = "FR";
3153 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
3154 arg_regs
[(regno
- 46) / 2] = "FR";
3155 arg_regs
[(regno
- 46) / 2 + 1] = "FU";
3157 arg_regs
[(regno
- 46) / 2] = "FU";
3158 arg_regs
[(regno
- 46) / 2 + 1] = "FR";
3163 fputs ("\t.CALL ", asm_out_file
);
3164 for (i
= 0; i
< 4; i
++)
3169 fputc (',', asm_out_file
);
3170 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
3173 fputc ('\n', asm_out_file
);
3176 /* Memory loads/stores to/from the shift need to go through
3177 the general registers. */
3180 secondary_reload_class (class, mode
, in
)
3181 enum reg_class
class;
3182 enum machine_mode mode
;
3185 int regno
= true_regnum (in
);
3187 if (function_label_operand (in
, mode
)
3188 || ((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
3189 && GET_MODE_CLASS (mode
) == MODE_INT
3190 && FP_REG_CLASS_P (class))
3191 || (class == SHIFT_REGS
&& (regno
<= 0 || regno
>= 32)))
3192 return GENERAL_REGS
;
3194 if (GET_CODE (in
) == HIGH
)
3197 if (TARGET_KERNEL
&& class != R1_REGS
&& symbolic_operand (in
, VOIDmode
))
3204 function_arg_padding (mode
, type
)
3205 enum machine_mode mode
;
3210 if (mode
== BLKmode
)
3212 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
3213 size
= int_size_in_bytes (type
) * BITS_PER_UNIT
;
3215 return upward
; /* Don't know if this is right, but */
3216 /* same as old definition. */
3219 size
= GET_MODE_BITSIZE (mode
);
3220 if (size
< PARM_BOUNDARY
)
3222 else if (size
% PARM_BOUNDARY
)
3229 /* Do what is necessary for `va_start'. The argument is ignored;
3230 We look at the current function to determine if stdargs or varargs
3231 is used and fill in an initial va_list. A pointer to this constructor
3235 hppa_builtin_saveregs (arglist
)
3238 rtx block
, float_addr
, offset
, float_mem
;
3239 tree fntype
= TREE_TYPE (current_function_decl
);
3240 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
3241 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
3242 != void_type_node
)))
3243 ? UNITS_PER_WORD
: 0);
3246 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
3248 offset
= current_function_arg_offset_rtx
;
3250 /* Store general registers on the stack. */
3251 move_block_from_reg (23,
3252 gen_rtx (MEM
, BLKmode
,
3254 (current_function_internal_arg_pointer
, -16)),
3255 4, 4 * UNITS_PER_WORD
);
3256 return copy_to_reg (expand_binop (Pmode
, add_optab
,
3257 current_function_internal_arg_pointer
,
3258 offset
, 0, 0, OPTAB_LIB_WIDEN
));
3261 /* This routine handles all the normal conditional branch sequences we
3262 might need to generate. It handles compare immediate vs compare
3263 register, nullification of delay slots, varying length branches,
3264 negated branches, and all combinations of the above. It returns the
3265 output appropriate to emit the branch corresponding to all given
3269 output_cbranch (operands
, nullify
, length
, negated
, insn
)
3271 int nullify
, length
, negated
;
3274 static char buf
[100];
3277 /* A conditional branch to the following instruction (eg the delay slot) is
3278 asking for a disaster. This can happen when not optimizing.
3280 In such cases it is safe to emit nothing. */
3282 if (JUMP_LABEL (insn
) == next_nonnote_insn (insn
))
3285 /* If this is a long branch with its delay slot unfilled, set `nullify'
3286 as it can nullify the delay slot and save a nop. */
3287 if (length
== 8 && dbr_sequence_length () == 0)
3290 /* If this is a short forward conditional branch which did not get
3291 its delay slot filled, the delay slot can still be nullified. */
3292 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3293 nullify
= forward_branch_p (insn
);
3295 /* A forward branch over a single nullified insn can be done with a
3296 comclr instruction. This avoids a single cycle penalty due to
3297 mis-predicted branch if we fall through (branch not taken). */
3299 && next_real_insn (insn
) != 0
3300 && get_attr_length (next_real_insn (insn
)) == 4
3301 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
3307 /* All short conditional branches except backwards with an unfilled
3311 strcpy (buf
, "com%I2clr,");
3313 strcpy (buf
, "com%I2b,");
3315 strcat (buf
, "%B3");
3317 strcat (buf
, "%S3");
3319 strcat (buf
, " %2,%1,0");
3321 strcat (buf
, ",n %2,%1,%0");
3323 strcat (buf
, " %2,%1,%0");
3326 /* All long conditionals. Note an short backward branch with an
3327 unfilled delay slot is treated just like a long backward branch
3328 with an unfilled delay slot. */
3330 /* Handle weird backwards branch with a filled delay slot
3331 with is nullified. */
3332 if (dbr_sequence_length () != 0
3333 && ! forward_branch_p (insn
)
3336 strcpy (buf
, "com%I2b,");
3338 strcat (buf
, "%S3");
3340 strcat (buf
, "%B3");
3341 strcat (buf
, ",n %2,%1,.+12\n\tbl %0,0");
3345 strcpy (buf
, "com%I2clr,");
3347 strcat (buf
, "%S3");
3349 strcat (buf
, "%B3");
3351 strcat (buf
, " %2,%1,0\n\tbl,n %0,0");
3353 strcat (buf
, " %2,%1,0\n\tbl %0,0");
3363 /* This routine handles all the branch-on-bit conditional branch sequences we
3364 might need to generate. It handles nullification of delay slots,
3365 varying length branches, negated branches and all combinations of the
3366 above. it returns the appropriate output template to emit the branch. */
3369 output_bb (operands
, nullify
, length
, negated
, insn
, which
)
3371 int nullify
, length
, negated
;
3375 static char buf
[100];
3378 /* A conditional branch to the following instruction (eg the delay slot) is
3379 asking for a disaster. I do not think this can happen as this pattern
3380 is only used when optimizing; jump optimization should eliminate the
3381 jump. But be prepared just in case. */
3383 if (JUMP_LABEL (insn
) == next_nonnote_insn (insn
))
3386 /* If this is a long branch with its delay slot unfilled, set `nullify'
3387 as it can nullify the delay slot and save a nop. */
3388 if (length
== 8 && dbr_sequence_length () == 0)
3391 /* If this is a short forward conditional branch which did not get
3392 its delay slot filled, the delay slot can still be nullified. */
3393 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3394 nullify
= forward_branch_p (insn
);
3396 /* A forward branch over a single nullified insn can be done with a
3397 extrs instruction. This avoids a single cycle penalty due to
3398 mis-predicted branch if we fall through (branch not taken). */
3401 && next_real_insn (insn
) != 0
3402 && get_attr_length (next_real_insn (insn
)) == 4
3403 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
3410 /* All short conditional branches except backwards with an unfilled
3414 strcpy (buf
, "extrs,");
3416 strcpy (buf
, "bb,");
3417 if ((which
== 0 && negated
)
3418 || (which
== 1 && ! negated
))
3423 strcat (buf
, " %0,%1,1,0");
3424 else if (nullify
&& negated
)
3425 strcat (buf
, ",n %0,%1,%3");
3426 else if (nullify
&& ! negated
)
3427 strcat (buf
, ",n %0,%1,%2");
3428 else if (! nullify
&& negated
)
3429 strcat (buf
, "%0,%1,%3");
3430 else if (! nullify
&& ! negated
)
3431 strcat (buf
, " %0,%1,%2");
3434 /* All long conditionals. Note an short backward branch with an
3435 unfilled delay slot is treated just like a long backward branch
3436 with an unfilled delay slot. */
3438 /* Handle weird backwards branch with a filled delay slot
3439 with is nullified. */
3440 if (dbr_sequence_length () != 0
3441 && ! forward_branch_p (insn
)
3444 strcpy (buf
, "bb,");
3445 if ((which
== 0 && negated
)
3446 || (which
== 1 && ! negated
))
3451 strcat (buf
, " %0,%1,.+12\n\tbl %3,0");
3453 strcat (buf
, " %0,%1,.+12\n\tbl %2,0");
3457 strcpy (buf
, "extrs,");
3458 if ((which
== 0 && negated
)
3459 || (which
== 1 && ! negated
))
3463 if (nullify
&& negated
)
3464 strcat (buf
, " %0,%1,1,0\n\tbl,n %3,0");
3465 else if (nullify
&& ! negated
)
3466 strcat (buf
, " %0,%1,1,0\n\tbl,n %2,0");
3468 strcat (buf
, " %0,%1,1,0\n\tbl %3,0");
3470 strcat (buf
, " %0,%1,1,0\n\tbl %2,0");
3480 /* Return the output template for emitting a dbra type insn.
3482 Note it may perform some output operations on its own before
3483 returning the final output string. */
3485 output_dbra (operands
, insn
, which_alternative
)
3488 int which_alternative
;
3491 /* A conditional branch to the following instruction (eg the delay slot) is
3492 asking for a disaster. Be prepared! */
3494 if (JUMP_LABEL (insn
) == next_nonnote_insn (insn
))
3496 if (which_alternative
== 0)
3497 return "ldo %1(%0),%0";
3498 else if (which_alternative
== 1)
3500 output_asm_insn ("fstws %0,-16(0,%%r30)",operands
);
3501 output_asm_insn ("ldw -16(0,%%r30),%4",operands
);
3502 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
3503 return "fldws -16(0,%%r30),%0";
3507 output_asm_insn ("ldw %0,%4", operands
);
3508 return "ldo %1(%4),%4\n\tstw %4,%0";
3512 if (which_alternative
== 0)
3514 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
3515 int length
= get_attr_length (insn
);
3517 /* If this is a long branch with its delay slot unfilled, set `nullify'
3518 as it can nullify the delay slot and save a nop. */
3519 if (length
== 8 && dbr_sequence_length () == 0)
3522 /* If this is a short forward conditional branch which did not get
3523 its delay slot filled, the delay slot can still be nullified. */
3524 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3525 nullify
= forward_branch_p (insn
);
3527 /* Handle short versions first. */
3528 if (length
== 4 && nullify
)
3529 return "addib,%C2,n %1,%0,%3";
3530 else if (length
== 4 && ! nullify
)
3531 return "addib,%C2 %1,%0,%3";
3532 else if (length
== 8)
3534 /* Handle weird backwards branch with a fulled delay slot
3535 which is nullified. */
3536 if (dbr_sequence_length () != 0
3537 && ! forward_branch_p (insn
)
3539 return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
3541 /* Handle normal cases. */
3543 return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
3545 return "addi,%N2 %1,%0,%0\n\tbl %3,0";
3550 /* Deal with gross reload from FP register case. */
3551 else if (which_alternative
== 1)
3553 /* Move loop counter from FP register to MEM then into a GR,
3554 increment the GR, store the GR into MEM, and finally reload
3555 the FP register from MEM from within the branch's delay slot. */
3556 output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands
);
3557 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
3558 if (get_attr_length (insn
) == 24)
3559 return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
3561 return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
3563 /* Deal with gross reload from memory case. */
3566 /* Reload loop counter from memory, the store back to memory
3567 happens in the branch's delay slot. */
3568 output_asm_insn ("ldw %0,%4", operands
);
3569 if (get_attr_length (insn
) == 12)
3570 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
3572 return "addi,%N2 %1,%4,%0\n\tbl %3,0\n\tstw %4,%0";
3576 /* Return the output template for emitting a dbra type insn.
3578 Note it may perform some output operations on its own before
3579 returning the final output string. */
3581 output_movb (operands
, insn
, which_alternative
, reverse_comparison
)
3584 int which_alternative
;
3585 int reverse_comparison
;
3588 /* A conditional branch to the following instruction (eg the delay slot) is
3589 asking for a disaster. Be prepared! */
3591 if (JUMP_LABEL (insn
) == next_nonnote_insn (insn
))
3593 if (which_alternative
== 0)
3594 return "copy %1,%0";
3595 else if (which_alternative
== 1)
3597 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
3598 return "fldws -16(0,%%r30),%0";
3604 /* Support the second variant. */
3605 if (reverse_comparison
)
3606 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
3608 if (which_alternative
== 0)
3610 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
3611 int length
= get_attr_length (insn
);
3613 /* If this is a long branch with its delay slot unfilled, set `nullify'
3614 as it can nullify the delay slot and save a nop. */
3615 if (length
== 8 && dbr_sequence_length () == 0)
3618 /* If this is a short forward conditional branch which did not get
3619 its delay slot filled, the delay slot can still be nullified. */
3620 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3621 nullify
= forward_branch_p (insn
);
3623 /* Handle short versions first. */
3624 if (length
== 4 && nullify
)
3625 return "movb,%C2,n %1,%0,%3";
3626 else if (length
== 4 && ! nullify
)
3627 return "movb,%C2 %1,%0,%3";
3628 else if (length
== 8)
3630 /* Handle weird backwards branch with a fulled delay slot
3631 which is nullified. */
3632 if (dbr_sequence_length () != 0
3633 && ! forward_branch_p (insn
)
3635 return "movb,%N2,n %1,%0,.+12\n\ttbl %3,0";
3637 /* Handle normal cases. */
3639 return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
3641 return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
3646 /* Deal with gross reload from FP register case. */
3647 else if (which_alternative
== 1)
3649 /* Move loop counter from FP register to MEM then into a GR,
3650 increment the GR, store the GR into MEM, and finally reload
3651 the FP register from MEM from within the branch's delay slot. */
3652 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
3653 if (get_attr_length (insn
) == 12)
3654 return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
3656 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
3658 /* Deal with gross reload from memory case. */
3661 /* Reload loop counter from memory, the store back to memory
3662 happens in the branch's delay slot. */
3663 if (get_attr_length (insn
) == 8)
3664 return "comb,%S2 0,%1,%3\n\tstw %1,%0";
3666 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
3671 /* INSN is either a function call or a millicode call. It may have an
3672 unconditional jump in its delay slot.
3674 CALL_DEST is the routine we are calling.
3676 RETURN_POINTER is the register which will hold the return address.
3677 %r2 for most calls, %r31 for millicode calls. */
3679 output_call (insn
, call_dest
, return_pointer
)
3689 /* Handle common case -- empty delay slot or no jump in the delay slot. */
3690 if (dbr_sequence_length () == 0
3691 || (dbr_sequence_length () != 0
3692 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
))
3694 xoperands
[0] = call_dest
;
3695 xoperands
[1] = return_pointer
;
3696 output_asm_insn ("bl %0,%r1%#", xoperands
);
3700 /* This call has an unconditional jump in its delay slot. */
3702 /* Use the containing sequence insn's address. */
3703 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
3705 distance
= insn_addresses
[INSN_UID (JUMP_LABEL (NEXT_INSN (insn
)))]
3706 - insn_addresses
[INSN_UID (seq_insn
)] - 8;
3708 /* If the branch was too far away, emit a normal call followed
3709 by a nop, followed by the unconditional branch.
3711 If the branch is close, then adjust %r2 from within the
3712 call's delay slot. */
3714 xoperands
[0] = call_dest
;
3715 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
3716 xoperands
[2] = return_pointer
;
3717 if (! VAL_14_BITS_P (distance
))
3718 output_asm_insn ("bl %0,%r2\n\tnop\n\tbl,n %1,%%r0", xoperands
);
3721 xoperands
[3] = gen_label_rtx ();
3722 output_asm_label (xoperands
[3]);
3723 output_asm_insn ("\n\tbl %0,%r2\n\tldo %1-%3-8(%r2),%r2", xoperands
);
3726 /* Delete the jump. */
3727 PUT_CODE (NEXT_INSN (insn
), NOTE
);
3728 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
3729 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
3733 extern struct obstack
*saveable_obstack
;
3735 /* In HPUX 8.0's shared library scheme, special relocations are needed
3736 for function labels if they might be passed to a function
3737 in a shared library (because shared libraries don't live in code
3738 space), and special magic is needed to construct their address. */
3741 hppa_encode_label (sym
)
3744 char *str
= XSTR (sym
, 0);
3745 int len
= strlen (str
);
3746 char *newstr
= obstack_alloc (saveable_obstack
, len
+ 2) ;
3750 strcpy (newstr
+ 1, str
);
3752 XSTR (sym
,0) = newstr
;
3756 function_label_operand (op
, mode
)
3758 enum machine_mode mode
;
3760 return GET_CODE (op
) == SYMBOL_REF
&& FUNCTION_NAME_P (XSTR (op
, 0));
3763 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
3764 use in fmpyadd instructions. */
3766 fmpyaddoperands(operands
)
3769 enum machine_mode mode
= GET_MODE (operands
[0]);
3771 /* All modes must be the same. */
3772 if (! (mode
== GET_MODE (operands
[1])
3773 && mode
== GET_MODE (operands
[2])
3774 && mode
== GET_MODE (operands
[3])
3775 && mode
== GET_MODE (operands
[4])
3776 && mode
== GET_MODE (operands
[5])))
3779 /* Both DFmode and SFmode should work. But using SFmode makes the
3780 assembler complain. Just turn it off for now. */
3784 /* Only 2 real operands to the addition. One of the input operands must
3785 be the same as the output operand. */
3786 if (! rtx_equal_p (operands
[3], operands
[4])
3787 && ! rtx_equal_p (operands
[3], operands
[5]))
3790 /* Inout operand of add can not conflict with any operands from multiply. */
3791 if (rtx_equal_p (operands
[3], operands
[0])
3792 || rtx_equal_p (operands
[3], operands
[1])
3793 || rtx_equal_p (operands
[3], operands
[2]))
3796 /* multiply can not feed into addition operands. */
3797 if (rtx_equal_p (operands
[4], operands
[0])
3798 || rtx_equal_p (operands
[5], operands
[0]))
3801 /* Passed. Operands are suitable for fmpyadd. */
3805 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
3806 use in fmpysub instructions. */
3808 fmpysuboperands(operands
)
3811 enum machine_mode mode
= GET_MODE (operands
[0]);
3813 /* All modes must be the same. */
3814 if (! (mode
== GET_MODE (operands
[1])
3815 && mode
== GET_MODE (operands
[2])
3816 && mode
== GET_MODE (operands
[3])
3817 && mode
== GET_MODE (operands
[4])
3818 && mode
== GET_MODE (operands
[5])))
3821 /* Both DFmode and SFmode should work. But using SFmode makes the
3822 assembler complain. Just turn it off for now. */
3826 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
3827 operation, so operands[4] must be the same as operand[3]. */
3828 if (! rtx_equal_p (operands
[3], operands
[4]))
3831 /* multiply can not feed into subtraction. */
3832 if (rtx_equal_p (operands
[5], operands
[0]))
3835 /* Inout operand of sub can not conflict with any operands from multiply. */
3836 if (rtx_equal_p (operands
[3], operands
[0])
3837 || rtx_equal_p (operands
[3], operands
[1])
3838 || rtx_equal_p (operands
[3], operands
[2]))
3841 /* Passed. Operands are suitable for fmpysub. */
3846 plus_xor_ior_operator (op
, mode
)
3848 enum machine_mode mode
;
3850 return (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == XOR
3851 || GET_CODE (op
) == IOR
);
3854 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
3855 constants for shadd instructions. */
3857 shadd_constant_p (val
)
3860 if (val
== 2 || val
== 4 || val
== 8)
3866 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
3867 the valid constant for shadd instructions. */
3869 shadd_operand (op
, mode
)
3871 enum machine_mode mode
;
3873 return (GET_CODE (op
) == CONST_INT
&& shadd_constant_p (INTVAL (op
)));
3876 /* Return 1 if INSN branches forward. Should be using insn_addresses
3877 to avoid walking through all the insns... */
3879 forward_branch_p (insn
)
3882 rtx label
= JUMP_LABEL (insn
);
3889 insn
= NEXT_INSN (insn
);
3892 return (insn
== label
);
3895 /* Return 1 if OP is an equality comparison, else return 0. */
3897 eq_neq_comparison_operator (op
, mode
)
3899 enum machine_mode mode
;
3901 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
3904 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
3906 movb_comparison_operator (op
, mode
)
3908 enum machine_mode mode
;
3910 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
3911 || GET_CODE (op
) == LT
|| GET_CODE (op
) == GE
);
3914 /* Return 1 if INSN is in the delay slot of a call instruction. */
3916 jump_in_call_delay (insn
)
3920 if (GET_CODE (insn
) != JUMP_INSN
)
3923 if (PREV_INSN (insn
)
3924 && PREV_INSN (PREV_INSN (insn
))
3925 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn
)))) == INSN
)
3927 rtx test_insn
= next_active_insn (PREV_INSN (PREV_INSN (insn
)));
3929 return (GET_CODE (PATTERN (test_insn
)) == SEQUENCE
3930 && XVECEXP (PATTERN (test_insn
), 0, 1) == insn
);