1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
40 /* Save the operands last given to a compare for use when we
41 generate a scc or bcc insn. */
43 rtx hppa_compare_op0
, hppa_compare_op1
;
44 enum cmp_type hppa_branch_type
;
46 /* Which cpu we are scheduling for. */
47 enum processor_type pa_cpu
;
49 /* String to hold which cpu we are scheduling for. */
52 /* Set by the FUNCTION_PROFILER macro. */
53 int hp_profile_labelno
;
55 /* Counts for the number of callee-saved general and floating point
56 registers which were saved by the current function's prologue. */
57 static int gr_saved
, fr_saved
;
59 /* Whether or not the current function uses an out-of-line prologue
61 static int out_of_line_prologue_epilogue
;
63 static rtx
find_addr_reg ();
65 /* Keep track of the number of bytes we have output in the CODE subspaces
66 during this compilation so we'll know when to emit inline long-calls. */
68 unsigned int total_code_bytes
;
70 /* Variables to handle plabels that we discover are necessary at assembly
71 output time. They are output after the current function. */
77 } *deferred_plabels
= 0;
78 int n_deferred_plabels
= 0;
83 /* Default to 7100 scheduling. If the 7100LC scheduling ever
84 gets reasonably tuned, it should be the default since that
85 what most PAs sold now are. */
86 if (pa_cpu_string
== NULL
87 || ! strcmp (pa_cpu_string
, "7100"))
89 pa_cpu_string
= "7100";
90 pa_cpu
= PROCESSOR_7100
;
92 else if (! strcmp (pa_cpu_string
, "700"))
94 pa_cpu_string
= "700";
95 pa_cpu
= PROCESSOR_700
;
97 else if (! strcmp (pa_cpu_string
, "7100LC"))
99 pa_cpu_string
= "7100LC";
100 pa_cpu
= PROCESSOR_7100LC
;
104 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100 and 7100LC\n", pa_cpu_string
);
107 if (flag_pic
&& TARGET_PORTABLE_RUNTIME
)
109 warning ("PIC code generation is not supported in the portable runtime model\n");
112 if (flag_pic
&& (TARGET_NO_SPACE_REGS
|| TARGET_FAST_INDIRECT_CALLS
))
114 warning ("PIC code generation is not compatable with fast indirect calls\n");
117 if (flag_pic
&& profile_flag
)
119 warning ("PIC code generation is not compatable with profiling\n");
122 if (TARGET_SPACE
&& (flag_pic
|| profile_flag
))
124 warning ("Out of line entry/exit sequences are not compatable\n");
125 warning ("with PIC or profiling\n");
128 if (! TARGET_GAS
&& write_symbols
!= NO_DEBUG
)
130 warning ("-g is only supported when using GAS on this processor,");
131 warning ("-g option disabled.");
132 write_symbols
= NO_DEBUG
;
137 /* Return non-zero only if OP is a register of mode MODE,
140 reg_or_0_operand (op
, mode
)
142 enum machine_mode mode
;
144 return (op
== CONST0_RTX (mode
) || register_operand (op
, mode
));
147 /* Return non-zero if OP is suitable for use in a call to a named
150 (???) For 2.5 try to eliminate either call_operand_address or
151 function_label_operand, they perform very similar functions. */
153 call_operand_address (op
, mode
)
155 enum machine_mode mode
;
157 return (CONSTANT_P (op
) && ! TARGET_PORTABLE_RUNTIME
);
160 /* Return 1 if X contains a symbolic expression. We know these
161 expressions will have one of a few well defined forms, so
162 we need only check those forms. */
164 symbolic_expression_p (x
)
168 /* Strip off any HIGH. */
169 if (GET_CODE (x
) == HIGH
)
172 return (symbolic_operand (x
, VOIDmode
));
176 symbolic_operand (op
, mode
)
178 enum machine_mode mode
;
180 switch (GET_CODE (op
))
187 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
188 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
189 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
195 /* Return truth value of statement that OP is a symbolic memory
196 operand of mode MODE. */
199 symbolic_memory_operand (op
, mode
)
201 enum machine_mode mode
;
203 if (GET_CODE (op
) == SUBREG
)
204 op
= SUBREG_REG (op
);
205 if (GET_CODE (op
) != MEM
)
208 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
209 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
212 /* Return 1 if the operand is either a register or a memory operand that is
216 reg_or_nonsymb_mem_operand (op
, mode
)
218 enum machine_mode mode
;
220 if (register_operand (op
, mode
))
223 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
229 /* Return 1 if the operand is either a register, zero, or a memory operand
230 that is not symbolic. */
233 reg_or_0_or_nonsymb_mem_operand (op
, mode
)
235 enum machine_mode mode
;
237 if (register_operand (op
, mode
))
240 if (op
== CONST0_RTX (mode
))
243 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
249 /* Accept any constant that can be moved in one instructions into a
252 cint_ok_for_move (intval
)
253 HOST_WIDE_INT intval
;
255 /* OK if ldo, ldil, or zdepi, can be used. */
256 return (VAL_14_BITS_P (intval
) || (intval
& 0x7ff) == 0
257 || zdepi_cint_p (intval
));
260 /* Accept anything that can be moved in one instruction into a general
263 move_operand (op
, mode
)
265 enum machine_mode mode
;
267 if (register_operand (op
, mode
))
270 if (GET_CODE (op
) == CONST_INT
)
271 return cint_ok_for_move (INTVAL (op
));
273 if (GET_CODE (op
) == SUBREG
)
274 op
= SUBREG_REG (op
);
275 if (GET_CODE (op
) != MEM
)
279 if (GET_CODE (op
) == LO_SUM
)
280 return (register_operand (XEXP (op
, 0), Pmode
)
281 && CONSTANT_P (XEXP (op
, 1)));
283 /* Since move_operand is only used for source operands, we can always
284 allow scaled indexing! */
285 if (GET_CODE (op
) == PLUS
286 && ((GET_CODE (XEXP (op
, 0)) == MULT
287 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == REG
288 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
289 && INTVAL (XEXP (XEXP (op
, 0), 1)) == GET_MODE_SIZE (mode
)
290 && GET_CODE (XEXP (op
, 1)) == REG
)
291 || (GET_CODE (XEXP (op
, 1)) == MULT
292 &&GET_CODE (XEXP (XEXP (op
, 1), 0)) == REG
293 && GET_CODE (XEXP (XEXP (op
, 1), 1)) == CONST_INT
294 && INTVAL (XEXP (XEXP (op
, 1), 1)) == GET_MODE_SIZE (mode
)
295 && GET_CODE (XEXP (op
, 0)) == REG
)))
298 return memory_address_p (mode
, op
);
301 /* Accept REG and any CONST_INT that can be moved in one instruction into a
304 reg_or_cint_move_operand (op
, mode
)
306 enum machine_mode mode
;
308 if (register_operand (op
, mode
))
311 if (GET_CODE (op
) == CONST_INT
)
312 return cint_ok_for_move (INTVAL (op
));
318 pic_label_operand (op
, mode
)
320 enum machine_mode mode
;
325 switch (GET_CODE (op
))
331 return (GET_CODE (XEXP (op
, 0)) == LABEL_REF
332 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
339 fp_reg_operand (op
, mode
)
341 enum machine_mode mode
;
343 return reg_renumber
&& FP_REG_P (op
);
348 /* Return truth value of whether OP can be used as an operand in a
349 three operand arithmetic insn that accepts registers of mode MODE
350 or 14-bit signed integers. */
352 arith_operand (op
, mode
)
354 enum machine_mode mode
;
356 return (register_operand (op
, mode
)
357 || (GET_CODE (op
) == CONST_INT
&& INT_14_BITS (op
)));
360 /* Return truth value of whether OP can be used as an operand in a
361 three operand arithmetic insn that accepts registers of mode MODE
362 or 11-bit signed integers. */
364 arith11_operand (op
, mode
)
366 enum machine_mode mode
;
368 return (register_operand (op
, mode
)
369 || (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
)));
372 /* A constant integer suitable for use in a PRE_MODIFY memory
375 pre_cint_operand (op
, mode
)
377 enum machine_mode mode
;
379 return (GET_CODE (op
) == CONST_INT
380 && INTVAL (op
) >= -0x2000 && INTVAL (op
) < 0x10);
383 /* A constant integer suitable for use in a POST_MODIFY memory
386 post_cint_operand (op
, mode
)
388 enum machine_mode mode
;
390 return (GET_CODE (op
) == CONST_INT
391 && INTVAL (op
) < 0x2000 && INTVAL (op
) >= -0x10);
395 arith_double_operand (op
, mode
)
397 enum machine_mode mode
;
399 return (register_operand (op
, mode
)
400 || (GET_CODE (op
) == CONST_DOUBLE
401 && GET_MODE (op
) == mode
402 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op
))
403 && (CONST_DOUBLE_HIGH (op
) >= 0
404 == ((CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
407 /* Return truth value of whether OP is a integer which fits the
408 range constraining immediate operands in three-address insns, or
409 is an integer register. */
412 ireg_or_int5_operand (op
, mode
)
414 enum machine_mode mode
;
416 return ((GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
))
417 || (GET_CODE (op
) == REG
&& REGNO (op
) > 0 && REGNO (op
) < 32));
420 /* Return truth value of whether OP is a integer which fits the
421 range constraining immediate operands in three-address insns. */
424 int5_operand (op
, mode
)
426 enum machine_mode mode
;
428 return (GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
));
432 uint5_operand (op
, mode
)
434 enum machine_mode mode
;
436 return (GET_CODE (op
) == CONST_INT
&& INT_U5_BITS (op
));
440 int11_operand (op
, mode
)
442 enum machine_mode mode
;
444 return (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
));
448 uint32_operand (op
, mode
)
450 enum machine_mode mode
;
452 #if HOST_BITS_PER_WIDE_INT > 32
453 /* All allowed constants will fit a CONST_INT. */
454 return (GET_CODE (op
) == CONST_INT
455 && (INTVAL (op
) >= 0 && INTVAL (op
) < 0x100000000L
));
457 return (GET_CODE (op
) == CONST_INT
458 || (GET_CODE (op
) == CONST_DOUBLE
459 && CONST_DOUBLE_HIGH (op
) == 0));
464 arith5_operand (op
, mode
)
466 enum machine_mode mode
;
468 return register_operand (op
, mode
) || int5_operand (op
, mode
);
471 /* True iff zdepi can be used to generate this CONST_INT. */
474 unsigned HOST_WIDE_INT x
;
476 unsigned HOST_WIDE_INT lsb_mask
, t
;
478 /* This might not be obvious, but it's at least fast.
479 This function is critical; we don't have the time loops would take. */
481 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
482 /* Return true iff t is a power of two. */
483 return ((t
& (t
- 1)) == 0);
486 /* True iff depi or extru can be used to compute (reg & mask).
487 Accept bit pattern like these:
493 unsigned HOST_WIDE_INT mask
;
496 mask
+= mask
& -mask
;
497 return (mask
& (mask
- 1)) == 0;
500 /* True iff depi or extru can be used to compute (reg & OP). */
502 and_operand (op
, mode
)
504 enum machine_mode mode
;
506 return (register_operand (op
, mode
)
507 || (GET_CODE (op
) == CONST_INT
&& and_mask_p (INTVAL (op
))));
510 /* True iff depi can be used to compute (reg | MASK). */
513 unsigned HOST_WIDE_INT mask
;
515 mask
+= mask
& -mask
;
516 return (mask
& (mask
- 1)) == 0;
519 /* True iff depi can be used to compute (reg | OP). */
521 ior_operand (op
, mode
)
523 enum machine_mode mode
;
525 return (GET_CODE (op
) == CONST_INT
&& ior_mask_p (INTVAL (op
)));
529 lhs_lshift_operand (op
, mode
)
531 enum machine_mode mode
;
533 return register_operand (op
, mode
) || lhs_lshift_cint_operand (op
, mode
);
536 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
537 Such values can be the left hand side x in (x << r), using the zvdepi
540 lhs_lshift_cint_operand (op
, mode
)
542 enum machine_mode mode
;
544 unsigned HOST_WIDE_INT x
;
545 if (GET_CODE (op
) != CONST_INT
)
547 x
= INTVAL (op
) >> 4;
548 return (x
& (x
+ 1)) == 0;
552 arith32_operand (op
, mode
)
554 enum machine_mode mode
;
556 return register_operand (op
, mode
) || GET_CODE (op
) == CONST_INT
;
560 pc_or_label_operand (op
, mode
)
562 enum machine_mode mode
;
564 return (GET_CODE (op
) == PC
|| GET_CODE (op
) == LABEL_REF
);
567 /* Legitimize PIC addresses. If the address is already
568 position-independent, we return ORIG. Newly generated
569 position-independent addresses go to REG. If we need more
570 than one register, we lose. */
573 legitimize_pic_address (orig
, mode
, reg
)
575 enum machine_mode mode
;
579 /* Labels need special handling. */
580 if (pic_label_operand (orig
))
582 emit_insn (gen_pic_load_label (reg
, orig
));
583 current_function_uses_pic_offset_table
= 1;
586 if (GET_CODE (orig
) == SYMBOL_REF
)
593 emit_insn (gen_pic2_highpart (reg
, pic_offset_table_rtx
, orig
));
594 pic_ref
= gen_rtx (MEM
, Pmode
,
595 gen_rtx (LO_SUM
, Pmode
, reg
,
596 gen_rtx (UNSPEC
, SImode
, gen_rtvec (1, orig
), 0)));
599 pic_ref
= gen_rtx (MEM
, Pmode
,
600 gen_rtx (PLUS
, Pmode
, pic_offset_table_rtx
, orig
));
601 current_function_uses_pic_offset_table
= 1;
602 RTX_UNCHANGING_P (pic_ref
) = 1;
603 emit_move_insn (reg
, pic_ref
);
606 else if (GET_CODE (orig
) == CONST
)
610 if (GET_CODE (XEXP (orig
, 0)) == PLUS
611 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
617 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
619 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
620 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
621 base
== reg
? 0 : reg
);
624 if (GET_CODE (orig
) == CONST_INT
)
626 if (INT_14_BITS (orig
))
627 return plus_constant_for_output (base
, INTVAL (orig
));
628 orig
= force_reg (Pmode
, orig
);
630 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
631 /* Likewise, should we set special REG_NOTEs here? */
636 /* Try machine-dependent ways of modifying an illegitimate address
637 to be legitimate. If we find one, return the new, valid address.
638 This macro is used in only one place: `memory_address' in explow.c.
640 OLDX is the address as it was before break_out_memory_refs was called.
641 In some cases it is useful to look at this to decide what needs to be done.
643 MODE and WIN are passed so that this macro can use
644 GO_IF_LEGITIMATE_ADDRESS.
646 It is always safe for this macro to do nothing. It exists to recognize
647 opportunities to optimize the output.
649 For the PA, transform:
651 memory(X + <large int>)
655 if (<large int> & mask) >= 16
656 Y = (<large int> & ~mask) + mask + 1 Round up.
658 Y = (<large int> & ~mask) Round down.
660 memory (Z + (<large int> - Y));
662 This is for CSE to find several similar references, and only use one Z.
664 X can either be a SYMBOL_REF or REG, but because combine can not
665 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
666 D will not fit in 14 bits.
668 MODE_FLOAT references allow displacements which fit in 5 bits, so use
671 MODE_INT references allow displacements which fit in 14 bits, so use
674 This relies on the fact that most mode MODE_FLOAT references will use FP
675 registers and most mode MODE_INT references will use integer registers.
676 (In the rare case of an FP register used in an integer MODE, we depend
677 on secondary reloads to clean things up.)
680 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
681 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
682 addressing modes to be used).
684 Put X and Z into registers. Then put the entire expression into
688 hppa_legitimize_address (x
, oldx
, mode
)
690 enum machine_mode mode
;
695 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
697 /* Strip off CONST. */
698 if (GET_CODE (x
) == CONST
)
701 /* Special case. Get the SYMBOL_REF into a register and use indexing.
702 That should always be safe. */
703 if (GET_CODE (x
) == PLUS
704 && GET_CODE (XEXP (x
, 0)) == REG
705 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
707 rtx reg
= force_reg (SImode
, XEXP (x
, 1));
708 return force_reg (SImode
, gen_rtx (PLUS
, SImode
, reg
, XEXP (x
, 0)));
711 /* Note we must reject symbols which represent function addresses
712 since the assembler/linker can't handle arithmetic on plabels. */
713 if (GET_CODE (x
) == PLUS
714 && GET_CODE (XEXP (x
, 1)) == CONST_INT
715 && ((GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
716 && !FUNCTION_NAME_P (XSTR (XEXP (x
, 0), 0)))
717 || GET_CODE (XEXP (x
, 0)) == REG
))
719 rtx int_part
, ptr_reg
;
721 int offset
= INTVAL (XEXP (x
, 1));
722 int mask
= GET_MODE_CLASS (mode
) == MODE_FLOAT
? 0x1f : 0x3fff;
724 /* Choose which way to round the offset. Round up if we
725 are >= halfway to the next boundary. */
726 if ((offset
& mask
) >= ((mask
+ 1) / 2))
727 newoffset
= (offset
& ~ mask
) + mask
+ 1;
729 newoffset
= (offset
& ~ mask
);
731 /* If the newoffset will not fit in 14 bits (ldo), then
732 handling this would take 4 or 5 instructions (2 to load
733 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
734 add the new offset and the SYMBOL_REF.) Combine can
735 not handle 4->2 or 5->2 combinations, so do not create
737 if (! VAL_14_BITS_P (newoffset
)
738 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
740 rtx const_part
= gen_rtx (CONST
, VOIDmode
,
741 gen_rtx (PLUS
, Pmode
,
743 GEN_INT (newoffset
)));
746 gen_rtx (HIGH
, Pmode
, const_part
));
749 gen_rtx (LO_SUM
, Pmode
,
750 tmp_reg
, const_part
));
754 if (! VAL_14_BITS_P (newoffset
))
755 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
757 int_part
= GEN_INT (newoffset
);
759 ptr_reg
= force_reg (Pmode
,
760 gen_rtx (PLUS
, Pmode
,
761 force_reg (Pmode
, XEXP (x
, 0)),
764 return plus_constant (ptr_reg
, offset
- newoffset
);
767 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
769 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
770 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
771 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1)))
772 && (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == 'o'
773 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
774 && GET_CODE (XEXP (x
, 1)) != CONST
)
776 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
780 if (GET_CODE (reg1
) != REG
)
781 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
783 reg2
= XEXP (XEXP (x
, 0), 0);
784 if (GET_CODE (reg2
) != REG
)
785 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
787 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
788 gen_rtx (MULT
, Pmode
,
789 reg2
, GEN_INT (val
)),
793 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
795 Only do so for floating point modes since this is more speculative
796 and we lose if it's an integer store. */
797 if (GET_CODE (x
) == PLUS
798 && GET_CODE (XEXP (x
, 0)) == PLUS
799 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
800 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
801 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
802 && (mode
== SFmode
|| mode
== DFmode
))
805 /* First, try and figure out what to use as a base register. */
806 rtx reg1
, reg2
, base
, idx
, orig_base
;
808 reg1
= XEXP (XEXP (x
, 0), 1);
813 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
814 then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
815 know it's a base register below. */
816 if (GET_CODE (reg1
) != REG
)
817 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
819 if (GET_CODE (reg2
) != REG
)
820 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
822 /* Figure out what the base and index are. */
824 if (GET_CODE (reg1
) == REG
825 && REGNO_POINTER_FLAG (REGNO (reg1
)))
828 orig_base
= XEXP (XEXP (x
, 0), 1);
829 idx
= gen_rtx (PLUS
, Pmode
,
830 gen_rtx (MULT
, Pmode
,
831 XEXP (XEXP (XEXP (x
, 0), 0), 0),
832 XEXP (XEXP (XEXP (x
, 0), 0), 1)),
835 else if (GET_CODE (reg2
) == REG
836 && REGNO_POINTER_FLAG (REGNO (reg2
)))
839 orig_base
= XEXP (x
, 1);
846 /* If the index adds a large constant, try to scale the
847 constant so that it can be loaded with only one insn. */
848 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
849 && VAL_14_BITS_P (INTVAL (XEXP (idx
, 1))
850 / INTVAL (XEXP (XEXP (idx
, 0), 1)))
851 && INTVAL (XEXP (idx
, 1)) % INTVAL (XEXP (XEXP (idx
, 0), 1)) == 0)
853 /* Divide the CONST_INT by the scale factor, then add it to A. */
854 int val
= INTVAL (XEXP (idx
, 1));
856 val
/= INTVAL (XEXP (XEXP (idx
, 0), 1));
857 reg1
= XEXP (XEXP (idx
, 0), 0);
858 if (GET_CODE (reg1
) != REG
)
859 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
861 reg1
= force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, reg1
, GEN_INT (val
)));
863 /* We can now generate a simple scaled indexed address. */
864 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
865 gen_rtx (MULT
, Pmode
, reg1
,
866 XEXP (XEXP (idx
, 0), 1)),
870 /* If B + C is still a valid base register, then add them. */
871 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
872 && INTVAL (XEXP (idx
, 1)) <= 4096
873 && INTVAL (XEXP (idx
, 1)) >= -4096)
875 int val
= INTVAL (XEXP (XEXP (idx
, 0), 1));
878 reg1
= force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, base
, XEXP (idx
, 1)));
880 reg2
= XEXP (XEXP (idx
, 0), 0);
881 if (GET_CODE (reg2
) != CONST_INT
)
882 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
884 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
885 gen_rtx (MULT
, Pmode
,
886 reg2
, GEN_INT (val
)),
890 /* Get the index into a register, then add the base + index and
891 return a register holding the result. */
893 /* First get A into a register. */
894 reg1
= XEXP (XEXP (idx
, 0), 0);
895 if (GET_CODE (reg1
) != REG
)
896 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
898 /* And get B into a register. */
899 reg2
= XEXP (idx
, 1);
900 if (GET_CODE (reg2
) != REG
)
901 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
903 reg1
= force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
904 gen_rtx (MULT
, Pmode
, reg1
,
905 XEXP (XEXP (idx
, 0), 1)),
908 /* Add the result to our base register and return. */
909 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, base
, reg1
));
913 /* Uh-oh. We might have an address for x[n-100000]. This needs
914 special handling to avoid creating an indexed memory address
915 with x-100000 as the base.
917 If the constant part is small enough, then it's still safe because
918 there is a guard page at the beginning and end of the data segment.
920 Scaled references are common enough that we want to try and rearrange the
921 terms so that we can use indexing for these addresses too. Only
922 do the optimization for floatint point modes. */
924 if (GET_CODE (x
) == PLUS
925 && symbolic_expression_p (XEXP (x
, 1)))
927 /* Ugly. We modify things here so that the address offset specified
928 by the index expression is computed first, then added to x to form
929 the entire address. */
931 rtx regx1
, regx2
, regy1
, regy2
, y
;
933 /* Strip off any CONST. */
935 if (GET_CODE (y
) == CONST
)
938 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
940 /* See if this looks like
941 (plus (mult (reg) (shadd_const))
942 (const (plus (symbol_ref) (const_int))))
944 Where const_int is small. In that case the const
945 expression is a valid pointer for indexing.
947 If const_int is big, but can be divided evenly by shadd_const
948 and added to (reg). This allows more scaled indexed addresses. */
949 if (GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
950 && GET_CODE (XEXP (x
, 0)) == MULT
951 && GET_CODE (XEXP (y
, 1)) == CONST_INT
952 && INTVAL (XEXP (y
, 1)) >= -4096
953 && INTVAL (XEXP (y
, 1)) <= 4095
954 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
955 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
957 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
961 if (GET_CODE (reg1
) != REG
)
962 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
964 reg2
= XEXP (XEXP (x
, 0), 0);
965 if (GET_CODE (reg2
) != REG
)
966 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
968 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
,
969 gen_rtx (MULT
, Pmode
,
970 reg2
, GEN_INT (val
)),
973 else if ((mode
== DFmode
|| mode
== SFmode
)
974 && GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
975 && GET_CODE (XEXP (x
, 0)) == MULT
976 && GET_CODE (XEXP (y
, 1)) == CONST_INT
977 && INTVAL (XEXP (y
, 1)) % INTVAL (XEXP (XEXP (x
, 0), 1)) == 0
978 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
979 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
982 = force_reg (Pmode
, GEN_INT (INTVAL (XEXP (y
, 1))
983 / INTVAL (XEXP (XEXP (x
, 0), 1))));
984 regx2
= XEXP (XEXP (x
, 0), 0);
985 if (GET_CODE (regx2
) != REG
)
986 regx2
= force_reg (Pmode
, force_operand (regx2
, 0));
987 regx2
= force_reg (Pmode
, gen_rtx (GET_CODE (y
), Pmode
,
989 return force_reg (Pmode
,
990 gen_rtx (PLUS
, Pmode
,
991 gen_rtx (MULT
, Pmode
, regx2
,
992 XEXP (XEXP (x
, 0), 1)),
993 force_reg (Pmode
, XEXP (y
, 0))));
995 else if (GET_CODE (XEXP (y
, 1)) == CONST_INT
996 && INTVAL (XEXP (y
, 1)) >= -4096
997 && INTVAL (XEXP (y
, 1)) <= 4095)
999 /* This is safe because of the guard page at the
1000 beginning and end of the data space. Just
1001 return the original address. */
1006 /* Doesn't look like one we can optimize. */
1007 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1008 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1009 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1010 regx1
= force_reg (Pmode
,
1011 gen_rtx (GET_CODE (y
), Pmode
, regx1
, regy2
));
1012 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, regx1
, regy1
));
1020 /* For the HPPA, REG and REG+CONST is cost 0
1021 and addresses involving symbolic constants are cost 2.
1023 PIC addresses are very expensive.
1025 It is no coincidence that this has the same structure
1026 as GO_IF_LEGITIMATE_ADDRESS. */
1028 hppa_address_cost (X
)
1031 if (GET_CODE (X
) == PLUS
)
1033 else if (GET_CODE (X
) == LO_SUM
)
1035 else if (GET_CODE (X
) == HIGH
)
1040 /* Emit insns to move operands[1] into operands[0].
1042 Return 1 if we have written out everything that needs to be done to
1043 do the move. Otherwise, return 0 and the caller will emit the move
1047 emit_move_sequence (operands
, mode
, scratch_reg
)
1049 enum machine_mode mode
;
1052 register rtx operand0
= operands
[0];
1053 register rtx operand1
= operands
[1];
1055 if (reload_in_progress
&& GET_CODE (operand0
) == REG
1056 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1057 operand0
= reg_equiv_mem
[REGNO (operand0
)];
1058 else if (reload_in_progress
&& GET_CODE (operand0
) == SUBREG
1059 && GET_CODE (SUBREG_REG (operand0
)) == REG
1060 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
1062 SUBREG_REG (operand0
) = reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))];
1063 operand0
= alter_subreg (operand0
);
1066 if (reload_in_progress
&& GET_CODE (operand1
) == REG
1067 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
1068 operand1
= reg_equiv_mem
[REGNO (operand1
)];
1069 else if (reload_in_progress
&& GET_CODE (operand1
) == SUBREG
1070 && GET_CODE (SUBREG_REG (operand1
)) == REG
1071 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
1073 SUBREG_REG (operand1
) = reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))];
1074 operand1
= alter_subreg (operand1
);
1077 /* Handle secondary reloads for loads/stores of FP registers from
1078 REG+D addresses where D does not fit in 5 bits, including
1079 (subreg (mem (addr))) cases. */
1080 if (fp_reg_operand (operand0
, mode
)
1081 && ((GET_CODE (operand1
) == MEM
1082 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
1083 || ((GET_CODE (operand1
) == SUBREG
1084 && GET_CODE (XEXP (operand1
, 0)) == MEM
1085 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
1088 if (GET_CODE (operand1
) == SUBREG
)
1089 operand1
= XEXP (operand1
, 0);
1091 scratch_reg
= gen_rtx (REG
, SImode
, REGNO (scratch_reg
));
1093 /* D might not fit in 14 bits either; for such cases load D into
1095 if (!memory_address_p (SImode
, XEXP (operand1
, 0)))
1097 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1098 emit_move_insn (scratch_reg
, gen_rtx (GET_CODE (XEXP (operand1
, 0)),
1100 XEXP (XEXP (operand1
, 0), 0),
1104 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
1105 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, gen_rtx (MEM
, mode
,
1109 else if (fp_reg_operand (operand1
, mode
)
1110 && ((GET_CODE (operand0
) == MEM
1111 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
1112 || ((GET_CODE (operand0
) == SUBREG
)
1113 && GET_CODE (XEXP (operand0
, 0)) == MEM
1114 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
1117 if (GET_CODE (operand0
) == SUBREG
)
1118 operand0
= XEXP (operand0
, 0);
1120 scratch_reg
= gen_rtx (REG
, SImode
, REGNO (scratch_reg
));
1121 /* D might not fit in 14 bits either; for such cases load D into
1123 if (!memory_address_p (SImode
, XEXP (operand0
, 0)))
1125 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
1126 emit_move_insn (scratch_reg
, gen_rtx (GET_CODE (XEXP (operand0
, 0)),
1128 XEXP (XEXP (operand0
, 0), 0),
1132 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
1133 emit_insn (gen_rtx (SET
, VOIDmode
, gen_rtx (MEM
, mode
, scratch_reg
),
1137 /* Handle secondary reloads for loads of FP registers from constant
1138 expressions by forcing the constant into memory.
1140 use scratch_reg to hold the address of the memory location.
1142 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
1143 NO_REGS when presented with a const_int and an register class
1144 containing only FP registers. Doing so unfortunately creates
1145 more problems than it solves. Fix this for 2.5. */
1146 else if (fp_reg_operand (operand0
, mode
)
1147 && CONSTANT_P (operand1
)
1152 /* Force the constant into memory and put the address of the
1153 memory location into scratch_reg. */
1154 xoperands
[0] = scratch_reg
;
1155 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
1156 emit_move_sequence (xoperands
, Pmode
, 0);
1158 /* Now load the destination register. */
1159 emit_insn (gen_rtx (SET
, mode
, operand0
,
1160 gen_rtx (MEM
, mode
, scratch_reg
)));
1163 /* Handle secondary reloads for SAR. These occur when trying to load
1164 the SAR from memory a FP register, or with a constant. */
1165 else if (GET_CODE (operand0
) == REG
1166 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
1167 && (GET_CODE (operand1
) == MEM
1168 || GET_CODE (operand1
) == CONST_INT
1169 || (GET_CODE (operand1
) == REG
1170 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1
)))))
1173 emit_move_insn (scratch_reg
, operand1
);
1174 emit_move_insn (operand0
, scratch_reg
);
1177 /* Handle most common case: storing into a register. */
1178 else if (register_operand (operand0
, mode
))
1180 if (register_operand (operand1
, mode
)
1181 || (GET_CODE (operand1
) == CONST_INT
&& INT_14_BITS (operand1
))
1182 || (operand1
== CONST0_RTX (mode
))
1183 || (GET_CODE (operand1
) == HIGH
1184 && !symbolic_operand (XEXP (operand1
, 0), VOIDmode
))
1185 /* Only `general_operands' can come here, so MEM is ok. */
1186 || GET_CODE (operand1
) == MEM
)
1188 /* Run this case quickly. */
1189 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1193 else if (GET_CODE (operand0
) == MEM
)
1195 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
1197 /* Run this case quickly. */
1198 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1201 if (! (reload_in_progress
|| reload_completed
))
1203 operands
[0] = validize_mem (operand0
);
1204 operands
[1] = operand1
= force_reg (mode
, operand1
);
1208 /* Simplify the source if we need to. */
1209 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1210 || (GET_CODE (operand1
) == HIGH
1211 && symbolic_operand (XEXP (operand1
, 0), mode
)))
1215 if (GET_CODE (operand1
) == HIGH
)
1218 operand1
= XEXP (operand1
, 0);
1220 if (symbolic_operand (operand1
, mode
))
1222 rtx const_part
= NULL
;
1224 /* Argh. The assembler and linker can't handle arithmetic
1225 involving plabels. We'll have to split up operand1 here
1226 if it's a function label involved in an arithmetic
1227 expression. Luckily, this only happens with addition
1228 of constants to plabels, which simplifies the test.
1230 We add the constant back in just before returning to
1232 if (GET_CODE (operand1
) == CONST
1233 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1234 && function_label_operand (XEXP (XEXP (operand1
, 0), 0), Pmode
))
1236 /* Save away the constant part of the expression. */
1237 const_part
= XEXP (XEXP (operand1
, 0), 1);
1238 if (GET_CODE (const_part
) != CONST_INT
)
1241 /* Set operand1 to just the SYMBOL_REF. */
1242 operand1
= XEXP (XEXP (operand1
, 0), 0);
1249 if (reload_in_progress
|| reload_completed
)
1250 temp
= scratch_reg
? scratch_reg
: operand0
;
1252 temp
= gen_reg_rtx (Pmode
);
1254 /* If operand1 is a function label, then we've got to
1255 force it to memory, then load op0 from memory. */
1256 if (function_label_operand (operand1
, mode
))
1258 operands
[1] = force_const_mem (mode
, operand1
);
1259 emit_move_sequence (operands
, mode
, temp
);
1261 /* Likewise for (const (plus (symbol) (const_int))) when
1262 generating pic code during or after reload and const_int
1263 will not fit in 14 bits. */
1264 else if (GET_CODE (operand1
) == CONST
1265 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1266 && GET_CODE (XEXP (XEXP (operand1
, 0), 1)) == CONST_INT
1267 && !INT_14_BITS (XEXP (XEXP (operand1
, 0), 1))
1268 && (reload_completed
|| reload_in_progress
)
1271 operands
[1] = force_const_mem (mode
, operand1
);
1272 operands
[1] = legitimize_pic_address (XEXP (operands
[1], 0),
1274 emit_move_sequence (operands
, mode
, temp
);
1278 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
1279 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operands
[1]));
1282 /* On the HPPA, references to data space are supposed to use dp,
1283 register 27, but showing it in the RTL inhibits various cse
1284 and loop optimizations. */
1289 if (reload_in_progress
|| reload_completed
)
1290 temp
= scratch_reg
? scratch_reg
: operand0
;
1292 temp
= gen_reg_rtx (mode
);
1294 /* Loading a SYMBOL_REF into a register makes that register
1295 safe to be used as the base in an indexed address.
1297 Don't mark hard registers though. That loses. */
1298 if (GET_CODE (operand0
) == REG
1299 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1300 REGNO_POINTER_FLAG (REGNO (operand0
)) = 1;
1301 if (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
)
1302 REGNO_POINTER_FLAG (REGNO (temp
)) = 1;
1304 set
= gen_rtx (SET
, mode
, operand0
, temp
);
1306 set
= gen_rtx (SET
, VOIDmode
,
1308 gen_rtx (LO_SUM
, mode
, temp
, operand1
));
1310 emit_insn (gen_rtx (SET
, VOIDmode
,
1312 gen_rtx (HIGH
, mode
, operand1
)));
1317 /* Add back in the constant part if needed. */
1318 if (const_part
!= NULL
)
1319 expand_inc (operand0
, const_part
);
1322 else if (GET_CODE (operand1
) != CONST_INT
1323 || ! cint_ok_for_move (INTVAL (operand1
)))
1327 if (reload_in_progress
|| reload_completed
)
1330 temp
= gen_reg_rtx (mode
);
1332 emit_insn (gen_rtx (SET
, VOIDmode
, temp
,
1333 gen_rtx (HIGH
, mode
, operand1
)));
1334 operands
[1] = gen_rtx (LO_SUM
, mode
, temp
, operand1
);
1337 /* Now have insn-emit do whatever it normally does. */
1341 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1342 it will need a link/runtime reloc). */
1350 switch (TREE_CODE (exp
))
1357 reloc
= reloc_needed (TREE_OPERAND (exp
, 0));
1358 reloc
|= reloc_needed (TREE_OPERAND (exp
, 1));
1363 case NON_LVALUE_EXPR
:
1364 reloc
= reloc_needed (TREE_OPERAND (exp
, 0));
1370 for (link
= CONSTRUCTOR_ELTS (exp
); link
; link
= TREE_CHAIN (link
))
1371 if (TREE_VALUE (link
) != 0)
1372 reloc
|= reloc_needed (TREE_VALUE (link
));
1382 /* Does operand (which is a symbolic_operand) live in text space? If
1383 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1386 read_only_operand (operand
)
1389 if (GET_CODE (operand
) == CONST
)
1390 operand
= XEXP (XEXP (operand
, 0), 0);
1393 if (GET_CODE (operand
) == SYMBOL_REF
)
1394 return SYMBOL_REF_FLAG (operand
) && !CONSTANT_POOL_ADDRESS_P (operand
);
1398 if (GET_CODE (operand
) == SYMBOL_REF
)
1399 return SYMBOL_REF_FLAG (operand
) || CONSTANT_POOL_ADDRESS_P (operand
);
1405 /* Return the best assembler insn template
1406 for moving operands[1] into operands[0] as a fullword. */
1408 singlemove_string (operands
)
1411 HOST_WIDE_INT intval
;
1413 if (GET_CODE (operands
[0]) == MEM
)
1414 return "stw %r1,%0";
1415 if (GET_CODE (operands
[1]) == MEM
)
1417 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1422 if (GET_MODE (operands
[1]) != SFmode
)
1425 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1427 REAL_VALUE_FROM_CONST_DOUBLE (d
, operands
[1]);
1428 REAL_VALUE_TO_TARGET_SINGLE (d
, i
);
1430 operands
[1] = GEN_INT (i
);
1431 /* Fall through to CONST_INT case. */
1433 if (GET_CODE (operands
[1]) == CONST_INT
)
1435 intval
= INTVAL (operands
[1]);
1437 if (VAL_14_BITS_P (intval
))
1439 else if ((intval
& 0x7ff) == 0)
1440 return "ldil L'%1,%0";
1441 else if (zdepi_cint_p (intval
))
1442 return "zdepi %Z1,%0";
1444 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1446 return "copy %1,%0";
1450 /* Compute position (in OP[1]) and width (in OP[2])
1451 useful for copying IMM to a register using the zdepi
1452 instructions. Store the immediate value to insert in OP[0]. */
1454 compute_zdepi_operands (imm
, op
)
1455 unsigned HOST_WIDE_INT imm
;
1460 /* Find the least significant set bit in IMM. */
1461 for (lsb
= 0; lsb
< 32; lsb
++)
1468 /* Choose variants based on *sign* of the 5-bit field. */
1469 if ((imm
& 0x10) == 0)
1470 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
1473 /* Find the width of the bitstring in IMM. */
1474 for (len
= 5; len
< 32; len
++)
1476 if ((imm
& (1 << len
)) == 0)
1480 /* Sign extend IMM as a 5-bit value. */
1481 imm
= (imm
& 0xf) - 0x10;
1489 /* Output assembler code to perform a doubleword move insn
1490 with operands OPERANDS. */
1493 output_move_double (operands
)
1496 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
1498 rtx addreg0
= 0, addreg1
= 0;
1500 /* First classify both operands. */
1502 if (REG_P (operands
[0]))
1504 else if (offsettable_memref_p (operands
[0]))
1506 else if (GET_CODE (operands
[0]) == MEM
)
1511 if (REG_P (operands
[1]))
1513 else if (CONSTANT_P (operands
[1]))
1515 else if (offsettable_memref_p (operands
[1]))
1517 else if (GET_CODE (operands
[1]) == MEM
)
1522 /* Check for the cases that the operand constraints are not
1523 supposed to allow to happen. Abort if we get one,
1524 because generating code for these cases is painful. */
1526 if (optype0
!= REGOP
&& optype1
!= REGOP
)
1529 /* Handle auto decrementing and incrementing loads and stores
1530 specifically, since the structure of the function doesn't work
1531 for them without major modification. Do it better when we learn
1532 this port about the general inc/dec addressing of PA.
1533 (This was written by tege. Chide him if it doesn't work.) */
1535 if (optype0
== MEMOP
)
1537 /* We have to output the address syntax ourselves, since print_operand
1538 doesn't deal with the addresses we want to use. Fix this later. */
1540 rtx addr
= XEXP (operands
[0], 0);
1541 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1543 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1545 operands
[0] = XEXP (addr
, 0);
1546 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1549 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1551 /* No overlap between high target register and address
1552 register. (We do this in a non-obvious way to
1553 save a register file writeback) */
1554 if (GET_CODE (addr
) == POST_INC
)
1555 return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
1556 return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
1561 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1563 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1565 operands
[0] = XEXP (addr
, 0);
1566 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1569 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1571 /* No overlap between high target register and address
1572 register. (We do this in a non-obvious way to
1573 save a register file writeback) */
1574 if (GET_CODE (addr
) == PRE_INC
)
1575 return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
1576 return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
1582 if (optype1
== MEMOP
)
1584 /* We have to output the address syntax ourselves, since print_operand
1585 doesn't deal with the addresses we want to use. Fix this later. */
1587 rtx addr
= XEXP (operands
[1], 0);
1588 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1590 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1592 operands
[1] = XEXP (addr
, 0);
1593 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1596 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1598 /* No overlap between high target register and address
1599 register. (We do this in a non-obvious way to
1600 save a register file writeback) */
1601 if (GET_CODE (addr
) == POST_INC
)
1602 return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
1603 return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
1607 /* This is an undefined situation. We should load into the
1608 address register *and* update that register. Probably
1609 we don't need to handle this at all. */
1610 if (GET_CODE (addr
) == POST_INC
)
1611 return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
1612 return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
1615 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1617 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1619 operands
[1] = XEXP (addr
, 0);
1620 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1623 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1625 /* No overlap between high target register and address
1626 register. (We do this in a non-obvious way to
1627 save a register file writeback) */
1628 if (GET_CODE (addr
) == PRE_INC
)
1629 return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
1630 return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
1634 /* This is an undefined situation. We should load into the
1635 address register *and* update that register. Probably
1636 we don't need to handle this at all. */
1637 if (GET_CODE (addr
) == PRE_INC
)
1638 return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
1639 return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
1644 /* If an operand is an unoffsettable memory ref, find a register
1645 we can increment temporarily to make it refer to the second word. */
1647 if (optype0
== MEMOP
)
1648 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1650 if (optype1
== MEMOP
)
1651 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1653 /* Ok, we can do one word at a time.
1654 Normally we do the low-numbered word first.
1656 In either case, set up in LATEHALF the operands to use
1657 for the high-numbered word and in some cases alter the
1658 operands in OPERANDS to be suitable for the low-numbered word. */
1660 if (optype0
== REGOP
)
1661 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1662 else if (optype0
== OFFSOP
)
1663 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1665 latehalf
[0] = operands
[0];
1667 if (optype1
== REGOP
)
1668 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1669 else if (optype1
== OFFSOP
)
1670 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1671 else if (optype1
== CNSTOP
)
1672 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1674 latehalf
[1] = operands
[1];
1676 /* If the first move would clobber the source of the second one,
1677 do them in the other order.
1679 This can happen in two cases:
1681 mem -> register where the first half of the destination register
1682 is the same register used in the memory's address. Reload
1683 can create such insns.
1685 mem in this case will be either register indirect or register
1686 indirect plus a valid offset.
1688 register -> register move where REGNO(dst) == REGNO(src + 1)
1689 someone (Tim/Tege?) claimed this can happen for parameter loads.
1691 Handle mem -> register case first. */
1692 if (optype0
== REGOP
1693 && (optype1
== MEMOP
|| optype1
== OFFSOP
)
1694 && refers_to_regno_p (REGNO (operands
[0]), REGNO (operands
[0]) + 1,
1697 /* Do the late half first. */
1699 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1700 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1704 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1705 return singlemove_string (operands
);
1708 /* Now handle register -> register case. */
1709 if (optype0
== REGOP
&& optype1
== REGOP
1710 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1712 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1713 return singlemove_string (operands
);
1716 /* Normal case: do the two words, low-numbered first. */
1718 output_asm_insn (singlemove_string (operands
), operands
);
1720 /* Make any unoffsettable addresses point at high-numbered word. */
1722 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
1724 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1727 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1729 /* Undo the adds we just did. */
1731 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
1733 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1739 output_fp_move_double (operands
)
1742 if (FP_REG_P (operands
[0]))
1744 if (FP_REG_P (operands
[1])
1745 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1746 output_asm_insn ("fcpy,dbl %r1,%0", operands
);
1748 output_asm_insn ("fldd%F1 %1,%0", operands
);
1750 else if (FP_REG_P (operands
[1]))
1752 output_asm_insn ("fstd%F0 %1,%0", operands
);
1754 else if (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1756 if (GET_CODE (operands
[0]) == REG
)
1759 xoperands
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1760 xoperands
[0] = operands
[0];
1761 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
1763 /* This is a pain. You have to be prepared to deal with an
1764 arbitrary address here including pre/post increment/decrement.
1766 so avoid this in the MD. */
1774 /* Return a REG that occurs in ADDR with coefficient 1.
1775 ADDR can be effectively incremented by incrementing REG. */
1778 find_addr_reg (addr
)
1781 while (GET_CODE (addr
) == PLUS
)
1783 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1784 addr
= XEXP (addr
, 0);
1785 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1786 addr
= XEXP (addr
, 1);
1787 else if (CONSTANT_P (XEXP (addr
, 0)))
1788 addr
= XEXP (addr
, 1);
1789 else if (CONSTANT_P (XEXP (addr
, 1)))
1790 addr
= XEXP (addr
, 0);
1794 if (GET_CODE (addr
) == REG
)
1799 /* Emit code to perform a block move.
1801 OPERANDS[0] is the destination pointer as a REG, clobbered.
1802 OPERANDS[1] is the source pointer as a REG, clobbered.
1803 OPERANDS[2] is a register for temporary storage.
1804 OPERANDS[4] is the size as a CONST_INT
1805 OPERANDS[3] is a register for temporary storage.
1806 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1807 OPERNADS[6] is another temporary register. */
1810 output_block_move (operands
, size_is_constant
)
1812 int size_is_constant
;
1814 int align
= INTVAL (operands
[5]);
1815 unsigned long n_bytes
= INTVAL (operands
[4]);
1817 /* We can't move more than four bytes at a time because the PA
1818 has no longer integer move insns. (Could use fp mem ops?) */
1822 /* Note that we know each loop below will execute at least twice
1823 (else we would have open-coded the copy). */
1827 /* Pre-adjust the loop counter. */
1828 operands
[4] = GEN_INT (n_bytes
- 8);
1829 output_asm_insn ("ldi %4,%2", operands
);
1832 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1833 output_asm_insn ("ldws,ma 4(0,%1),%6", operands
);
1834 output_asm_insn ("stws,ma %3,4(0,%0)", operands
);
1835 output_asm_insn ("addib,>= -8,%2,.-12", operands
);
1836 output_asm_insn ("stws,ma %6,4(0,%0)", operands
);
1838 /* Handle the residual. There could be up to 7 bytes of
1839 residual to copy! */
1840 if (n_bytes
% 8 != 0)
1842 operands
[4] = GEN_INT (n_bytes
% 4);
1843 if (n_bytes
% 8 >= 4)
1844 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1845 if (n_bytes
% 4 != 0)
1846 output_asm_insn ("ldw 0(0,%1),%6", operands
);
1847 if (n_bytes
% 8 >= 4)
1848 output_asm_insn ("stws,ma %3,4(0,%0)", operands
);
1849 if (n_bytes
% 4 != 0)
1850 output_asm_insn ("stbys,e %6,%4(0,%0)", operands
);
1855 /* Pre-adjust the loop counter. */
1856 operands
[4] = GEN_INT (n_bytes
- 4);
1857 output_asm_insn ("ldi %4,%2", operands
);
1860 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands
);
1861 output_asm_insn ("ldhs,ma 2(0,%1),%6", operands
);
1862 output_asm_insn ("sths,ma %3,2(0,%0)", operands
);
1863 output_asm_insn ("addib,>= -4,%2,.-12", operands
);
1864 output_asm_insn ("sths,ma %6,2(0,%0)", operands
);
1866 /* Handle the residual. */
1867 if (n_bytes
% 4 != 0)
1869 if (n_bytes
% 4 >= 2)
1870 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands
);
1871 if (n_bytes
% 2 != 0)
1872 output_asm_insn ("ldb 0(0,%1),%6", operands
);
1873 if (n_bytes
% 4 >= 2)
1874 output_asm_insn ("sths,ma %3,2(0,%0)", operands
);
1875 if (n_bytes
% 2 != 0)
1876 output_asm_insn ("stb %6,0(0,%0)", operands
);
1881 /* Pre-adjust the loop counter. */
1882 operands
[4] = GEN_INT (n_bytes
- 2);
1883 output_asm_insn ("ldi %4,%2", operands
);
1886 output_asm_insn ("ldbs,ma 1(0,%1),%3", operands
);
1887 output_asm_insn ("ldbs,ma 1(0,%1),%6", operands
);
1888 output_asm_insn ("stbs,ma %3,1(0,%0)", operands
);
1889 output_asm_insn ("addib,>= -2,%2,.-12", operands
);
1890 output_asm_insn ("stbs,ma %6,1(0,%0)", operands
);
1892 /* Handle the residual. */
1893 if (n_bytes
% 2 != 0)
1895 output_asm_insn ("ldb 0(0,%1),%3", operands
);
1896 output_asm_insn ("stb %3,0(0,%0)", operands
);
1905 /* Count the number of insns necessary to handle this block move.
1907 Basic structure is the same as emit_block_move, except that we
1908 count insns rather than emit them. */
1911 compute_movstrsi_length (insn
)
1914 rtx pat
= PATTERN (insn
);
1915 int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
1916 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 5), 0));
1917 unsigned int n_insns
= 0;
1919 /* We can't move more than four bytes at a time because the PA
1920 has no longer integer move insns. (Could use fp mem ops?) */
1924 /* The basic opying loop. */
1928 if (n_bytes
% (2 * align
) != 0)
1930 /* Any residual caused by unrolling the copy loop. */
1931 if (n_bytes
% (2 * align
) > align
)
1934 /* Any residual because the number of bytes was not a
1935 multiple of the alignment. */
1936 if (n_bytes
% align
!= 0)
1940 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
1946 output_and (operands
)
1949 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
1951 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
1952 int ls0
, ls1
, ms0
, p
, len
;
1954 for (ls0
= 0; ls0
< 32; ls0
++)
1955 if ((mask
& (1 << ls0
)) == 0)
1958 for (ls1
= ls0
; ls1
< 32; ls1
++)
1959 if ((mask
& (1 << ls1
)) != 0)
1962 for (ms0
= ls1
; ms0
< 32; ms0
++)
1963 if ((mask
& (1 << ms0
)) == 0)
1976 operands
[2] = GEN_INT (len
);
1977 return "extru %1,31,%2,%0";
1981 /* We could use this `depi' for the case above as well, but `depi'
1982 requires one more register file access than an `extru'. */
1987 operands
[2] = GEN_INT (p
);
1988 operands
[3] = GEN_INT (len
);
1989 return "depi 0,%2,%3,%0";
1993 return "and %1,%2,%0";
1997 output_ior (operands
)
2000 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
2001 int bs0
, bs1
, p
, len
;
2003 if (INTVAL (operands
[2]) == 0)
2004 return "copy %1,%0";
2006 for (bs0
= 0; bs0
< 32; bs0
++)
2007 if ((mask
& (1 << bs0
)) != 0)
2010 for (bs1
= bs0
; bs1
< 32; bs1
++)
2011 if ((mask
& (1 << bs1
)) == 0)
2014 if (bs1
!= 32 && ((unsigned HOST_WIDE_INT
) 1 << bs1
) <= mask
)
2020 operands
[2] = GEN_INT (p
);
2021 operands
[3] = GEN_INT (len
);
2022 return "depi -1,%2,%3,%0";
2025 /* Output an ascii string. */
2027 output_ascii (file
, p
, size
)
2034 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
2036 /* The HP assembler can only take strings of 256 characters at one
2037 time. This is a limitation on input line length, *not* the
2038 length of the string. Sigh. Even worse, it seems that the
2039 restriction is in number of input characters (see \xnn &
2040 \whatever). So we have to do this very carefully. */
2042 fputs ("\t.STRING \"", file
);
2045 for (i
= 0; i
< size
; i
+= 4)
2049 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
2051 register unsigned int c
= p
[i
+ io
];
2053 if (c
== '\"' || c
== '\\')
2054 partial_output
[co
++] = '\\';
2055 if (c
>= ' ' && c
< 0177)
2056 partial_output
[co
++] = c
;
2060 partial_output
[co
++] = '\\';
2061 partial_output
[co
++] = 'x';
2062 hexd
= c
/ 16 - 0 + '0';
2064 hexd
-= '9' - 'a' + 1;
2065 partial_output
[co
++] = hexd
;
2066 hexd
= c
% 16 - 0 + '0';
2068 hexd
-= '9' - 'a' + 1;
2069 partial_output
[co
++] = hexd
;
2072 if (chars_output
+ co
> 243)
2074 fputs ("\"\n\t.STRING \"", file
);
2077 fwrite (partial_output
, 1, co
, file
);
2081 fputs ("\"\n", file
);
2084 /* Try to rewrite floating point comparisons & branches to avoid
2085 useless add,tr insns.
2087 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2088 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2089 first attempt to remove useless add,tr insns. It is zero
2090 for the second pass as reorg sometimes leaves bogus REG_DEAD
2093 When CHECK_NOTES is zero we can only eliminate add,tr insns
2094 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2097 remove_useless_addtr_insns (insns
, check_notes
)
2103 static int pass
= 0;
2105 /* This is fairly cheap, so always run it when optimizing. */
2109 int fbranch_count
= 0;
2111 /* Walk all the insns in this function looking for fcmp & fbranch
2112 instructions. Keep track of how many of each we find. */
2113 insns
= get_insns ();
2114 for (insn
= insns
; insn
; insn
= next_insn (insn
))
2118 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2119 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
2122 tmp
= PATTERN (insn
);
2124 /* It must be a set. */
2125 if (GET_CODE (tmp
) != SET
)
2128 /* If the destination is CCFP, then we've found an fcmp insn. */
2129 tmp
= SET_DEST (tmp
);
2130 if (GET_CODE (tmp
) == REG
&& REGNO (tmp
) == 0)
2136 tmp
= PATTERN (insn
);
2137 /* If this is an fbranch instruction, bump the fbranch counter. */
2138 if (GET_CODE (tmp
) == SET
2139 && SET_DEST (tmp
) == pc_rtx
2140 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
2141 && GET_CODE (XEXP (SET_SRC (tmp
), 0)) == NE
2142 && GET_CODE (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == REG
2143 && REGNO (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == 0)
2151 /* Find all floating point compare + branch insns. If possible,
2152 reverse the comparison & the branch to avoid add,tr insns. */
2153 for (insn
= insns
; insn
; insn
= next_insn (insn
))
2157 /* Ignore anything that isn't an INSN. */
2158 if (GET_CODE (insn
) != INSN
)
2161 tmp
= PATTERN (insn
);
2163 /* It must be a set. */
2164 if (GET_CODE (tmp
) != SET
)
2167 /* The destination must be CCFP, which is register zero. */
2168 tmp
= SET_DEST (tmp
);
2169 if (GET_CODE (tmp
) != REG
|| REGNO (tmp
) != 0)
2172 /* INSN should be a set of CCFP.
2174 See if the result of this insn is used in a reversed FP
2175 conditional branch. If so, reverse our condition and
2176 the branch. Doing so avoids useless add,tr insns. */
2177 next
= next_insn (insn
);
2180 /* Jumps, calls and labels stop our search. */
2181 if (GET_CODE (next
) == JUMP_INSN
2182 || GET_CODE (next
) == CALL_INSN
2183 || GET_CODE (next
) == CODE_LABEL
)
2186 /* As does another fcmp insn. */
2187 if (GET_CODE (next
) == INSN
2188 && GET_CODE (PATTERN (next
)) == SET
2189 && GET_CODE (SET_DEST (PATTERN (next
))) == REG
2190 && REGNO (SET_DEST (PATTERN (next
))) == 0)
2193 next
= next_insn (next
);
2196 /* Is NEXT_INSN a branch? */
2198 && GET_CODE (next
) == JUMP_INSN
)
2200 rtx pattern
= PATTERN (next
);
2202 /* If it a reversed fp conditional branch (eg uses add,tr)
2203 and CCFP dies, then reverse our conditional and the branch
2204 to avoid the add,tr. */
2205 if (GET_CODE (pattern
) == SET
2206 && SET_DEST (pattern
) == pc_rtx
2207 && GET_CODE (SET_SRC (pattern
)) == IF_THEN_ELSE
2208 && GET_CODE (XEXP (SET_SRC (pattern
), 0)) == NE
2209 && GET_CODE (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == REG
2210 && REGNO (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == 0
2211 && GET_CODE (XEXP (SET_SRC (pattern
), 1)) == PC
2212 && (fcmp_count
== fbranch_count
2214 && find_regno_note (next
, REG_DEAD
, 0))))
2216 /* Reverse the branch. */
2217 tmp
= XEXP (SET_SRC (pattern
), 1);
2218 XEXP (SET_SRC (pattern
), 1) = XEXP (SET_SRC (pattern
), 2);
2219 XEXP (SET_SRC (pattern
), 2) = tmp
;
2220 INSN_CODE (next
) = -1;
2222 /* Reverse our condition. */
2223 tmp
= PATTERN (insn
);
2224 PUT_CODE (XEXP (tmp
, 1),
2225 reverse_condition (GET_CODE (XEXP (tmp
, 1))));
2235 /* You may have trouble believing this, but this is the HP-PA stack
2240 Variable arguments (optional; any number may be allocated)
2242 SP-(4*(N+9)) arg word N
2247 Fixed arguments (must be allocated; may remain unused)
2256 SP-32 External Data Pointer (DP)
2258 SP-24 External/stub RP (RP')
2262 SP-8 Calling Stub RP (RP'')
2267 SP-0 Stack Pointer (points to next available address)
2271 /* This function saves registers as follows. Registers marked with ' are
2272 this function's registers (as opposed to the previous function's).
2273 If a frame_pointer isn't needed, r4 is saved as a general register;
2274 the space for the frame pointer is still allocated, though, to keep
2280 SP (FP') Previous FP
2281 SP + 4 Alignment filler (sigh)
2282 SP + 8 Space for locals reserved here.
2286 SP + n All call saved register used.
2290 SP + o All call saved fp registers used.
2294 SP + p (SP') points to next available address.
2298 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2299 Handle case where DISP > 8k by using the add_high_const pattern.
2301 Note in DISP > 8k case, we will leave the high part of the address
2302 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2304 store_reg (reg
, disp
, base
)
2305 int reg
, disp
, base
;
2307 if (VAL_14_BITS_P (disp
))
2309 emit_move_insn (gen_rtx (MEM
, SImode
,
2310 gen_rtx (PLUS
, SImode
,
2311 gen_rtx (REG
, SImode
, base
),
2313 gen_rtx (REG
, SImode
, reg
));
2317 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
2318 gen_rtx (REG
, SImode
, base
),
2320 emit_move_insn (gen_rtx (MEM
, SImode
,
2321 gen_rtx (LO_SUM
, SImode
,
2322 gen_rtx (REG
, SImode
, 1),
2324 gen_rtx (REG
, SImode
, reg
));
2328 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2329 Handle case where DISP > 8k by using the add_high_const pattern.
2331 Note in DISP > 8k case, we will leave the high part of the address
2332 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2334 load_reg (reg
, disp
, base
)
2335 int reg
, disp
, base
;
2337 if (VAL_14_BITS_P (disp
))
2339 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2340 gen_rtx (MEM
, SImode
,
2341 gen_rtx (PLUS
, SImode
,
2342 gen_rtx (REG
, SImode
, base
),
2347 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
2348 gen_rtx (REG
, SImode
, base
),
2350 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2351 gen_rtx (MEM
, SImode
,
2352 gen_rtx (LO_SUM
, SImode
,
2353 gen_rtx (REG
, SImode
, 1),
2358 /* Emit RTL to set REG to the value specified by BASE+DISP.
2359 Handle case where DISP > 8k by using the add_high_const pattern.
2361 Note in DISP > 8k case, we will leave the high part of the address
2362 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2364 set_reg_plus_d(reg
, base
, disp
)
2365 int reg
, base
, disp
;
2367 if (VAL_14_BITS_P (disp
))
2369 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2370 gen_rtx (PLUS
, SImode
,
2371 gen_rtx (REG
, SImode
, base
),
2376 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
2377 gen_rtx (REG
, SImode
, base
),
2379 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
2380 gen_rtx (LO_SUM
, SImode
,
2381 gen_rtx (REG
, SImode
, 1),
2386 /* Global variables set by FUNCTION_PROLOGUE. */
2387 /* Size of frame. Need to know this to emit return insns from
2389 static int actual_fsize
;
2390 static int local_fsize
, save_fregs
;
2393 compute_frame_size (size
, fregs_live
)
2397 extern int current_function_outgoing_args_size
;
2400 /* 8 is space for frame pointer + filler. If any frame is allocated
2401 we need to add this in because of STARTING_FRAME_OFFSET. */
2402 fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
2404 /* We must leave enough space for all the callee saved registers
2405 from 3 .. highest used callee save register since we don't
2406 know if we're going to have an inline or out of line prologue
2408 for (i
= 18; i
>= 3; i
--)
2409 if (regs_ever_live
[i
])
2411 fsize
+= 4 * (i
- 2);
2415 /* Round the stack. */
2416 fsize
= (fsize
+ 7) & ~7;
2418 /* We must leave enough space for all the callee saved registers
2419 from 3 .. highest used callee save register since we don't
2420 know if we're going to have an inline or out of line prologue
2422 for (i
= 66; i
>= 48; i
-= 2)
2423 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2428 fsize
+= 4 * (i
- 46);
2432 fsize
+= current_function_outgoing_args_size
;
2433 if (! leaf_function_p () || fsize
)
2435 return (fsize
+ 63) & ~63;
2438 rtx hp_profile_label_rtx
;
2439 static char hp_profile_label_name
[8];
2441 output_function_prologue (file
, size
)
2445 /* The function's label and associated .PROC must never be
2446 separated and must be output *after* any profiling declarations
2447 to avoid changing spaces/subspaces within a procedure. */
2448 ASM_OUTPUT_LABEL (file
, XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0));
2449 fputs ("\t.PROC\n", file
);
2451 /* hppa_expand_prologue does the dirty work now. We just need
2452 to output the assembler directives which denote the start
2454 fprintf (file
, "\t.CALLINFO FRAME=%d", actual_fsize
);
2455 if (regs_ever_live
[2] || profile_flag
)
2456 fputs (",CALLS,SAVE_RP", file
);
2458 fputs (",NO_CALLS", file
);
2460 if (frame_pointer_needed
)
2461 fputs (",SAVE_SP", file
);
2463 /* Pass on information about the number of callee register saves
2464 performed in the prologue.
2466 The compiler is supposed to pass the highest register number
2467 saved, the assembler then has to adjust that number before
2468 entering it into the unwind descriptor (to account for any
2469 caller saved registers with lower register numbers than the
2470 first callee saved register). */
2472 fprintf (file
, ",ENTRY_GR=%d", gr_saved
+ 2);
2475 fprintf (file
, ",ENTRY_FR=%d", fr_saved
+ 11);
2477 fputs ("\n\t.ENTRY\n", file
);
2479 /* Horrid hack. emit_function_prologue will modify this RTL in
2480 place to get the expected results. */
2482 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name
, "LP",
2483 hp_profile_labelno
);
2485 /* If we're using GAS and not using the portable runtime model, then
2486 we don't need to accumulate the total number of code bytes. */
2487 if (TARGET_GAS
&& ! TARGET_PORTABLE_RUNTIME
)
2488 total_code_bytes
= 0;
2489 else if (insn_addresses
)
2491 unsigned int old_total
= total_code_bytes
;
2493 total_code_bytes
+= insn_addresses
[INSN_UID (get_last_insn())];
2494 total_code_bytes
+= FUNCTION_BOUNDARY
/ BITS_PER_UNIT
;
2496 /* Be prepared to handle overflows. */
2497 total_code_bytes
= old_total
> total_code_bytes
? -1 : total_code_bytes
;
2500 total_code_bytes
= -1;
2502 remove_useless_addtr_insns (get_insns (), 0);
2506 hppa_expand_prologue()
2508 extern char call_used_regs
[];
2509 int size
= get_frame_size ();
2510 int merge_sp_adjust_with_store
= 0;
2512 rtx tmpreg
, size_rtx
;
2517 local_fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
2518 actual_fsize
= compute_frame_size (size
, &save_fregs
);
2520 /* Compute a few things we will use often. */
2521 tmpreg
= gen_rtx (REG
, SImode
, 1);
2522 size_rtx
= GEN_INT (actual_fsize
);
2524 /* Handle out of line prologues and epilogues. */
2529 int outline_insn_count
= 0;
2530 int inline_insn_count
= 0;
2532 /* Count the number of insns for the inline and out of line
2533 variants so we can choose one appropriately.
2535 No need to screw with counting actual_fsize operations -- they're
2536 done for both inline and out of line prologues. */
2537 if (regs_ever_live
[2])
2538 inline_insn_count
+= 1;
2540 if (! cint_ok_for_move (local_fsize
))
2541 outline_insn_count
+= 2;
2543 outline_insn_count
+= 1;
2545 /* Put the register save info into %r22. */
2546 for (i
= 18; i
>= 3; i
--)
2547 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2549 /* -1 because the stack adjustment is normally done in
2550 the same insn as a register save. */
2551 inline_insn_count
+= (i
- 2) - 1;
2556 for (i
= 66; i
>= 48; i
-= 2)
2557 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2559 /* +1 needed as we load %r1 with the start of the freg
2561 inline_insn_count
+= (i
/2 - 23) + 1;
2562 saves
|= ((i
/2 - 12 ) << 16);
2566 if (frame_pointer_needed
)
2567 inline_insn_count
+= 3;
2569 if (! cint_ok_for_move (saves
))
2570 outline_insn_count
+= 2;
2572 outline_insn_count
+= 1;
2574 if (TARGET_PORTABLE_RUNTIME
)
2575 outline_insn_count
+= 2;
2577 outline_insn_count
+= 1;
2579 /* If there's a lot of insns in the prologue, then do it as
2580 an out-of-line sequence. */
2581 if (inline_insn_count
> outline_insn_count
)
2583 /* Put the local_fisze into %r19. */
2584 operands
[0] = gen_rtx (REG
, SImode
, 19);
2585 operands
[1] = GEN_INT (local_fsize
);
2586 emit_move_insn (operands
[0], operands
[1]);
2588 /* Put the stack size into %r21. */
2589 operands
[0] = gen_rtx (REG
, SImode
, 21);
2590 operands
[1] = size_rtx
;
2591 emit_move_insn (operands
[0], operands
[1]);
2593 operands
[0] = gen_rtx (REG
, SImode
, 22);
2594 operands
[1] = GEN_INT (saves
);
2595 emit_move_insn (operands
[0], operands
[1]);
2597 /* Now call the out-of-line prologue. */
2598 emit_insn (gen_outline_prologue_call ());
2599 emit_insn (gen_blockage ());
2601 /* Note that we're using an out-of-line prologue. */
2602 out_of_line_prologue_epilogue
= 1;
2607 out_of_line_prologue_epilogue
= 0;
2609 /* Save RP first. The calling conventions manual states RP will
2610 always be stored into the caller's frame at sp-20. */
2611 if (regs_ever_live
[2] || profile_flag
)
2612 store_reg (2, -20, STACK_POINTER_REGNUM
);
2614 /* Allocate the local frame and set up the frame pointer if needed. */
2616 if (frame_pointer_needed
)
2618 /* Copy the old frame pointer temporarily into %r1. Set up the
2619 new stack pointer, then store away the saved old frame pointer
2620 into the stack at sp+actual_fsize and at the same time update
2621 the stack pointer by actual_fsize bytes. Two versions, first
2622 handles small (<8k) frames. The second handles large (>8k)
2624 emit_move_insn (tmpreg
, frame_pointer_rtx
);
2625 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
2626 if (VAL_14_BITS_P (actual_fsize
))
2627 emit_insn (gen_post_stwm (stack_pointer_rtx
, tmpreg
, size_rtx
));
2630 /* It is incorrect to store the saved frame pointer at *sp,
2631 then increment sp (writes beyond the current stack boundary).
2633 So instead use stwm to store at *sp and post-increment the
2634 stack pointer as an atomic operation. Then increment sp to
2635 finish allocating the new frame. */
2636 emit_insn (gen_post_stwm (stack_pointer_rtx
, tmpreg
, GEN_INT (64)));
2637 set_reg_plus_d (STACK_POINTER_REGNUM
,
2638 STACK_POINTER_REGNUM
,
2642 /* no frame pointer needed. */
2645 /* In some cases we can perform the first callee register save
2646 and allocating the stack frame at the same time. If so, just
2647 make a note of it and defer allocating the frame until saving
2648 the callee registers. */
2649 if (VAL_14_BITS_P (-actual_fsize
)
2653 merge_sp_adjust_with_store
= 1;
2654 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2655 else if (actual_fsize
!= 0)
2656 set_reg_plus_d (STACK_POINTER_REGNUM
,
2657 STACK_POINTER_REGNUM
,
2660 /* The hppa calling conventions say that that %r19, the pic offset
2661 register, is saved at sp - 32 (in this function's frame) when
2662 generating PIC code. FIXME: What is the correct thing to do
2663 for functions which make no calls and allocate no frame? Do
2664 we need to allocate a frame, or can we just omit the save? For
2665 now we'll just omit the save. */
2666 if (actual_fsize
!= 0 && flag_pic
)
2667 store_reg (PIC_OFFSET_TABLE_REGNUM
, -32, STACK_POINTER_REGNUM
);
2671 Instead of taking one argument, the counter label, as most normal
2672 mcounts do, _mcount appears to behave differently on the HPPA. It
2673 takes the return address of the caller, the address of this routine,
2674 and the address of the label. Also, it isn't magic, so
2675 argument registers have to be preserved. */
2678 int pc_offset
, i
, arg_offset
, basereg
, offsetadj
;
2680 pc_offset
= 4 + (frame_pointer_needed
2681 ? (VAL_14_BITS_P (actual_fsize
) ? 12 : 20)
2682 : (VAL_14_BITS_P (actual_fsize
) ? 4 : 8));
2684 /* When the function has a frame pointer, use it as the base
2685 register for saving/restore registers. Else use the stack
2686 pointer. Adjust the offset according to the frame size if
2687 this function does not have a frame pointer. */
2689 basereg
= frame_pointer_needed
? FRAME_POINTER_REGNUM
2690 : STACK_POINTER_REGNUM
;
2691 offsetadj
= frame_pointer_needed
? 0 : actual_fsize
;
2693 /* Horrid hack. emit_function_prologue will modify this RTL in
2694 place to get the expected results. sprintf here is just to
2695 put something in the name. */
2696 sprintf(hp_profile_label_name
, "LP$%04d", -1);
2697 hp_profile_label_rtx
= gen_rtx (SYMBOL_REF
, SImode
,
2698 hp_profile_label_name
);
2699 if (current_function_returns_struct
)
2700 store_reg (STRUCT_VALUE_REGNUM
, - 12 - offsetadj
, basereg
);
2702 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2703 if (regs_ever_live
[i
])
2705 store_reg (i
, arg_offset
, basereg
);
2706 /* Deal with arg_offset not fitting in 14 bits. */
2707 pc_offset
+= VAL_14_BITS_P (arg_offset
) ? 4 : 8;
2710 emit_move_insn (gen_rtx (REG
, SImode
, 26), gen_rtx (REG
, SImode
, 2));
2711 emit_move_insn (tmpreg
, gen_rtx (HIGH
, SImode
, hp_profile_label_rtx
));
2712 emit_move_insn (gen_rtx (REG
, SImode
, 24),
2713 gen_rtx (LO_SUM
, SImode
, tmpreg
, hp_profile_label_rtx
));
2714 /* %r25 is set from within the output pattern. */
2715 emit_insn (gen_call_profiler (GEN_INT (- pc_offset
- 20)));
2717 /* Restore argument registers. */
2718 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2719 if (regs_ever_live
[i
])
2720 load_reg (i
, arg_offset
, basereg
);
2722 if (current_function_returns_struct
)
2723 load_reg (STRUCT_VALUE_REGNUM
, -12 - offsetadj
, basereg
);
2727 /* Normal register save.
2729 Do not save the frame pointer in the frame_pointer_needed case. It
2730 was done earlier. */
2731 if (frame_pointer_needed
)
2733 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
2734 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2736 store_reg (i
, offset
, FRAME_POINTER_REGNUM
);
2740 /* Account for %r3 which is saved in a special place. */
2743 /* No frame pointer needed. */
2746 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
2747 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2749 /* If merge_sp_adjust_with_store is nonzero, then we can
2750 optimize the first GR save. */
2751 if (merge_sp_adjust_with_store
)
2753 merge_sp_adjust_with_store
= 0;
2754 emit_insn (gen_post_stwm (stack_pointer_rtx
,
2755 gen_rtx (REG
, SImode
, i
),
2756 GEN_INT (-offset
)));
2759 store_reg (i
, offset
, STACK_POINTER_REGNUM
);
2764 /* If we wanted to merge the SP adjustment with a GR save, but we never
2765 did any GR saves, then just emit the adjustment here. */
2766 if (merge_sp_adjust_with_store
)
2767 set_reg_plus_d (STACK_POINTER_REGNUM
,
2768 STACK_POINTER_REGNUM
,
2772 /* Align pointer properly (doubleword boundary). */
2773 offset
= (offset
+ 7) & ~7;
2775 /* Floating point register store. */
2778 /* First get the frame or stack pointer to the start of the FP register
2780 if (frame_pointer_needed
)
2781 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
2783 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
2785 /* Now actually save the FP registers. */
2786 for (i
= 66; i
>= 48; i
-= 2)
2788 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2790 emit_move_insn (gen_rtx (MEM
, DFmode
,
2791 gen_rtx (POST_INC
, DFmode
, tmpreg
)),
2792 gen_rtx (REG
, DFmode
, i
));
2798 /* When generating PIC code it is necessary to save/restore the
2799 PIC register around each function call. We used to do this
2800 in the call patterns themselves, but that implementation
2801 made incorrect assumptions about using global variables to hold
2802 per-function rtl code generated in the backend.
2804 So instead, we copy the PIC register into a reserved callee saved
2805 register in the prologue. Then after each call we reload the PIC
2806 register from the callee saved register. We also reload the PIC
2807 register from the callee saved register in the epilogue ensure the
2808 PIC register is valid at function exit.
2810 This may (depending on the exact characteristics of the function)
2811 even be more efficient.
2813 Avoid this if the callee saved register wasn't used (these are
2815 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM_SAVED
])
2816 emit_move_insn (gen_rtx (REG
, SImode
, PIC_OFFSET_TABLE_REGNUM_SAVED
),
2817 gen_rtx (REG
, SImode
, PIC_OFFSET_TABLE_REGNUM
));
2822 output_function_epilogue (file
, size
)
2826 rtx insn
= get_last_insn ();
2829 /* hppa_expand_epilogue does the dirty work now. We just need
2830 to output the assembler directives which denote the end
2833 To make debuggers happy, emit a nop if the epilogue was completely
2834 eliminated due to a volatile call as the last insn in the
2835 current function. That way the return address (in %r2) will
2836 always point to a valid instruction in the current function. */
2838 /* Get the last real insn. */
2839 if (GET_CODE (insn
) == NOTE
)
2840 insn
= prev_real_insn (insn
);
2842 /* If it is a sequence, then look inside. */
2843 if (insn
&& GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2844 insn
= XVECEXP (PATTERN (insn
), 0, 0);
2846 /* If insn is a CALL_INSN, then it must be a call to a volatile
2847 function (otherwise there would be epilogue insns). */
2848 if (insn
&& GET_CODE (insn
) == CALL_INSN
)
2849 fputs ("\tnop\n", file
);
2851 fputs ("\t.EXIT\n\t.PROCEND\n", file
);
2853 /* If we have deferred plabels, then we need to switch into the data
2854 section and align it to a 4 byte boundary before we output the
2855 deferred plabels. */
2856 if (n_deferred_plabels
)
2859 ASM_OUTPUT_ALIGN (file
, 2);
2862 /* Now output the deferred plabels. */
2863 for (i
= 0; i
< n_deferred_plabels
; i
++)
2865 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (deferred_plabels
[i
].internal_label
));
2866 assemble_integer (deferred_plabels
[i
].symbol
, 4, 1);
2868 n_deferred_plabels
= 0;
2872 hppa_expand_epilogue ()
2876 int merge_sp_adjust_with_load
= 0;
2878 /* Handle out of line prologues and epilogues. */
2879 if (TARGET_SPACE
&& out_of_line_prologue_epilogue
)
2884 /* Put the register save info into %r22. */
2885 for (i
= 18; i
>= 3; i
--)
2886 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2892 for (i
= 66; i
>= 48; i
-= 2)
2893 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2895 saves
|= ((i
/2 - 12 ) << 16);
2899 emit_insn (gen_blockage ());
2901 /* Put the local_fisze into %r19. */
2902 operands
[0] = gen_rtx (REG
, SImode
, 19);
2903 operands
[1] = GEN_INT (local_fsize
);
2904 emit_move_insn (operands
[0], operands
[1]);
2906 /* Put the stack size into %r21. */
2907 operands
[0] = gen_rtx (REG
, SImode
, 21);
2908 operands
[1] = GEN_INT (actual_fsize
);
2909 emit_move_insn (operands
[0], operands
[1]);
2911 operands
[0] = gen_rtx (REG
, SImode
, 22);
2912 operands
[1] = GEN_INT (saves
);
2913 emit_move_insn (operands
[0], operands
[1]);
2915 /* Now call the out-of-line epilogue. */
2916 emit_insn (gen_outline_epilogue_call ());
2920 /* We will use this often. */
2921 tmpreg
= gen_rtx (REG
, SImode
, 1);
2923 /* Try to restore RP early to avoid load/use interlocks when
2924 RP gets used in the return (bv) instruction. This appears to still
2925 be necessary even when we schedule the prologue and epilogue. */
2926 if (frame_pointer_needed
2927 && (regs_ever_live
[2] || profile_flag
))
2928 load_reg (2, -20, FRAME_POINTER_REGNUM
);
2930 /* No frame pointer, and stack is smaller than 8k. */
2931 else if (! frame_pointer_needed
2932 && VAL_14_BITS_P (actual_fsize
+ 20)
2933 && (regs_ever_live
[2] || profile_flag
))
2934 load_reg (2, - (actual_fsize
+ 20), STACK_POINTER_REGNUM
);
2936 /* General register restores. */
2937 if (frame_pointer_needed
)
2939 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
2940 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2942 load_reg (i
, offset
, FRAME_POINTER_REGNUM
);
2948 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
2950 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2952 /* Only for the first load.
2953 merge_sp_adjust_with_load holds the register load
2954 with which we will merge the sp adjustment. */
2955 if (VAL_14_BITS_P (actual_fsize
+ 20)
2957 && ! merge_sp_adjust_with_load
)
2958 merge_sp_adjust_with_load
= i
;
2960 load_reg (i
, offset
, STACK_POINTER_REGNUM
);
2966 /* Align pointer properly (doubleword boundary). */
2967 offset
= (offset
+ 7) & ~7;
2969 /* FP register restores. */
2972 /* Adjust the register to index off of. */
2973 if (frame_pointer_needed
)
2974 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
2976 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
2978 /* Actually do the restores now. */
2979 for (i
= 66; i
>= 48; i
-= 2)
2981 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2983 emit_move_insn (gen_rtx (REG
, DFmode
, i
),
2984 gen_rtx (MEM
, DFmode
,
2985 gen_rtx (POST_INC
, DFmode
, tmpreg
)));
2990 /* Emit a blockage insn here to keep these insns from being moved to
2991 an earlier spot in the epilogue, or into the main instruction stream.
2993 This is necessary as we must not cut the stack back before all the
2994 restores are finished. */
2995 emit_insn (gen_blockage ());
2996 /* No frame pointer, but we have a stack greater than 8k. We restore
2997 %r2 very late in this case. (All other cases are restored as early
2999 if (! frame_pointer_needed
3000 && ! VAL_14_BITS_P (actual_fsize
+ 20)
3001 && (regs_ever_live
[2] || profile_flag
))
3003 set_reg_plus_d (STACK_POINTER_REGNUM
,
3004 STACK_POINTER_REGNUM
,
3007 /* This used to try and be clever by not depending on the value in
3008 %r30 and instead use the value held in %r1 (so that the 2nd insn
3009 which sets %r30 could be put in the delay slot of the return insn).
3011 That won't work since if the stack is exactly 8k set_reg_plus_d
3012 doesn't set %r1, just %r30. */
3013 load_reg (2, - 20, STACK_POINTER_REGNUM
);
3016 /* Reset stack pointer (and possibly frame pointer). The stack
3017 pointer is initially set to fp + 64 to avoid a race condition. */
3018 else if (frame_pointer_needed
)
3020 set_reg_plus_d (STACK_POINTER_REGNUM
, FRAME_POINTER_REGNUM
, 64);
3021 emit_insn (gen_pre_ldwm (frame_pointer_rtx
,
3025 /* If we were deferring a callee register restore, do it now. */
3026 else if (! frame_pointer_needed
&& merge_sp_adjust_with_load
)
3027 emit_insn (gen_pre_ldwm (gen_rtx (REG
, SImode
,
3028 merge_sp_adjust_with_load
),
3030 GEN_INT (- actual_fsize
)));
3031 else if (actual_fsize
!= 0)
3032 set_reg_plus_d (STACK_POINTER_REGNUM
,
3033 STACK_POINTER_REGNUM
,
3037 /* Fetch the return address for the frame COUNT steps up from
3038 the current frame, after the prologue. FRAMEADDR is the
3039 frame pointer of the COUNT frame.
3041 We want to ignore any export stub remnants here. */
3044 return_addr_rtx (count
, frameaddr
)
3052 saved_rp
= gen_reg_rtx (Pmode
);
3054 /* First, we start off with the normal return address pointer from
3057 emit_move_insn (saved_rp
, plus_constant (frameaddr
, -5 * UNITS_PER_WORD
));
3059 /* Get pointer to the instruction stream. We have to mask out the
3060 privilege level from the two low order bits of the return address
3061 pointer here so that ins will point to the start of the first
3062 instruction that would have been executed if we returned. */
3063 ins
= copy_to_reg (gen_rtx (AND
, Pmode
,
3064 copy_to_reg (gen_rtx (MEM
, Pmode
, saved_rp
)),
3066 label
= gen_label_rtx ();
3068 /* Check the instruction stream at the normal return address for the
3071 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3072 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3073 0x00011820 | stub+16: mtsp r1,sr0
3074 0xe0400002 | stub+20: be,n 0(sr0,rp)
3076 If it is an export stub, than our return address is really in
3079 emit_cmp_insn (gen_rtx (MEM
, SImode
, ins
),
3080 GEN_INT (0x4bc23fd1),
3081 NE
, NULL_RTX
, SImode
, 1, 0);
3082 emit_jump_insn (gen_bne (label
));
3084 emit_cmp_insn (gen_rtx (MEM
, SImode
, plus_constant (ins
, 4)),
3085 GEN_INT (0x004010a1),
3086 NE
, NULL_RTX
, SImode
, 1, 0);
3087 emit_jump_insn (gen_bne (label
));
3089 emit_cmp_insn (gen_rtx (MEM
, SImode
, plus_constant (ins
, 8)),
3090 GEN_INT (0x00011820),
3091 NE
, NULL_RTX
, SImode
, 1, 0);
3092 emit_jump_insn (gen_bne (label
));
3094 emit_cmp_insn (gen_rtx (MEM
, SImode
, plus_constant (ins
, 12)),
3095 GEN_INT (0xe0400002),
3096 NE
, NULL_RTX
, SImode
, 1, 0);
3098 /* If there is no export stub then just use our initial guess of
3101 emit_jump_insn (gen_bne (label
));
3103 /* Here we know that our return address pointer points to an export
3104 stub. We don't want to return the address of the export stub,
3105 but rather the return address that leads back into user code.
3106 That return address is stored at -24[frameaddr]. */
3108 emit_move_insn (saved_rp
, plus_constant (frameaddr
, -6 * UNITS_PER_WORD
));
3111 return gen_rtx (MEM
, Pmode
, memory_address (Pmode
, saved_rp
));
3114 /* This is only valid once reload has completed because it depends on
3115 knowing exactly how much (if any) frame there is and...
3117 It's only valid if there is no frame marker to de-allocate and...
3119 It's only valid if %r2 hasn't been saved into the caller's frame
3120 (we're not profiling and %r2 isn't live anywhere). */
3122 hppa_can_use_return_insn_p ()
3124 return (reload_completed
3125 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3127 && ! regs_ever_live
[2]
3128 && ! frame_pointer_needed
);
3132 emit_bcond_fp (code
, operand0
)
3136 emit_jump_insn (gen_rtx (SET
, VOIDmode
, pc_rtx
,
3137 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
3138 gen_rtx (code
, VOIDmode
,
3139 gen_rtx (REG
, CCFPmode
, 0),
3141 gen_rtx (LABEL_REF
, VOIDmode
, operand0
),
3147 gen_cmp_fp (code
, operand0
, operand1
)
3149 rtx operand0
, operand1
;
3151 return gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, CCFPmode
, 0),
3152 gen_rtx (code
, CCFPmode
, operand0
, operand1
));
3155 /* Adjust the cost of a scheduling dependency. Return the new cost of
3156 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3159 pa_adjust_cost (insn
, link
, dep_insn
, cost
)
3165 if (! recog_memoized (insn
))
3168 if (REG_NOTE_KIND (link
) == 0)
3170 /* Data dependency; DEP_INSN writes a register that INSN reads some
3173 if (get_attr_type (insn
) == TYPE_FPSTORE
)
3175 rtx pat
= PATTERN (insn
);
3176 rtx dep_pat
= PATTERN (dep_insn
);
3177 if (GET_CODE (pat
) == PARALLEL
)
3179 /* This happens for the fstXs,mb patterns. */
3180 pat
= XVECEXP (pat
, 0, 0);
3182 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3183 /* If this happens, we have to extend this to schedule
3184 optimally. Return 0 for now. */
3187 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
3189 if (! recog_memoized (dep_insn
))
3191 /* DEP_INSN is writing its result to the register
3192 being stored in the fpstore INSN. */
3193 switch (get_attr_type (dep_insn
))
3196 /* This cost 3 cycles, not 2 as the md says for the
3197 700 and 7100. Note scaling of cost for 7100. */
3198 return cost
+ (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3205 case TYPE_FPSQRTSGL
:
3206 case TYPE_FPSQRTDBL
:
3207 /* In these important cases, we save one cycle compared to
3208 when flop instruction feed each other. */
3209 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3217 /* For other data dependencies, the default cost specified in the
3221 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3223 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3226 if (get_attr_type (insn
) == TYPE_FPLOAD
)
3228 rtx pat
= PATTERN (insn
);
3229 rtx dep_pat
= PATTERN (dep_insn
);
3230 if (GET_CODE (pat
) == PARALLEL
)
3232 /* This happens for the fldXs,mb patterns. */
3233 pat
= XVECEXP (pat
, 0, 0);
3235 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3236 /* If this happens, we have to extend this to schedule
3237 optimally. Return 0 for now. */
3240 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
3242 if (! recog_memoized (dep_insn
))
3244 switch (get_attr_type (dep_insn
))
3251 case TYPE_FPSQRTSGL
:
3252 case TYPE_FPSQRTDBL
:
3253 /* A fpload can't be issued until one cycle before a
3254 preceding arithmetic operation has finished if
3255 the target of the fpload is any of the sources
3256 (or destination) of the arithmetic operation. */
3257 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3264 else if (get_attr_type (insn
) == TYPE_FPALU
)
3266 rtx pat
= PATTERN (insn
);
3267 rtx dep_pat
= PATTERN (dep_insn
);
3268 if (GET_CODE (pat
) == PARALLEL
)
3270 /* This happens for the fldXs,mb patterns. */
3271 pat
= XVECEXP (pat
, 0, 0);
3273 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3274 /* If this happens, we have to extend this to schedule
3275 optimally. Return 0 for now. */
3278 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
3280 if (! recog_memoized (dep_insn
))
3282 switch (get_attr_type (dep_insn
))
3286 case TYPE_FPSQRTSGL
:
3287 case TYPE_FPSQRTDBL
:
3288 /* An ALU flop can't be issued until two cycles before a
3289 preceding divide or sqrt operation has finished if
3290 the target of the ALU flop is any of the sources
3291 (or destination) of the divide or sqrt operation. */
3292 return cost
- (pa_cpu
== PROCESSOR_700
) ? 2 : 4;
3300 /* For other anti dependencies, the cost is 0. */
3303 else if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
3305 /* Output dependency; DEP_INSN writes a register that INSN writes some
3307 if (get_attr_type (insn
) == TYPE_FPLOAD
)
3309 rtx pat
= PATTERN (insn
);
3310 rtx dep_pat
= PATTERN (dep_insn
);
3311 if (GET_CODE (pat
) == PARALLEL
)
3313 /* This happens for the fldXs,mb patterns. */
3314 pat
= XVECEXP (pat
, 0, 0);
3316 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3317 /* If this happens, we have to extend this to schedule
3318 optimally. Return 0 for now. */
3321 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
3323 if (! recog_memoized (dep_insn
))
3325 switch (get_attr_type (dep_insn
))
3332 case TYPE_FPSQRTSGL
:
3333 case TYPE_FPSQRTDBL
:
3334 /* A fpload can't be issued until one cycle before a
3335 preceding arithmetic operation has finished if
3336 the target of the fpload is the destination of the
3337 arithmetic operation. */
3338 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
3345 else if (get_attr_type (insn
) == TYPE_FPALU
)
3347 rtx pat
= PATTERN (insn
);
3348 rtx dep_pat
= PATTERN (dep_insn
);
3349 if (GET_CODE (pat
) == PARALLEL
)
3351 /* This happens for the fldXs,mb patterns. */
3352 pat
= XVECEXP (pat
, 0, 0);
3354 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3355 /* If this happens, we have to extend this to schedule
3356 optimally. Return 0 for now. */
3359 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
3361 if (! recog_memoized (dep_insn
))
3363 switch (get_attr_type (dep_insn
))
3367 case TYPE_FPSQRTSGL
:
3368 case TYPE_FPSQRTDBL
:
3369 /* An ALU flop can't be issued until two cycles before a
3370 preceding divide or sqrt operation has finished if
3371 the target of the ALU flop is also the target of
3372 of the divide or sqrt operation. */
3373 return cost
- (pa_cpu
== PROCESSOR_700
) ? 2 : 4;
3381 /* For other output dependencies, the cost is 0. */
3388 /* Return any length adjustment needed by INSN which already has its length
3389 computed as LENGTH. Return zero if no adjustment is necessary.
3391 For the PA: function calls, millicode calls, and backwards short
3392 conditional branches with unfilled delay slots need an adjustment by +1
3393 (to account for the NOP which will be inserted into the instruction stream).
3395 Also compute the length of an inline block move here as it is too
3396 complicated to express as a length attribute in pa.md. */
3398 pa_adjust_insn_length (insn
, length
)
3402 rtx pat
= PATTERN (insn
);
3404 /* Call insns which are *not* indirect and have unfilled delay slots. */
3405 if (GET_CODE (insn
) == CALL_INSN
)
3408 if (GET_CODE (XVECEXP (pat
, 0, 0)) == CALL
3409 && GET_CODE (XEXP (XEXP (XVECEXP (pat
, 0, 0), 0), 0)) == SYMBOL_REF
)
3411 else if (GET_CODE (XVECEXP (pat
, 0, 0)) == SET
3412 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat
, 0, 0), 1), 0), 0))
3418 /* Jumps inside switch tables which have unfilled delay slots
3419 also need adjustment. */
3420 else if (GET_CODE (insn
) == JUMP_INSN
3421 && simplejump_p (insn
)
3422 && GET_MODE (PATTERN (insn
)) == DImode
)
3424 /* Millicode insn with an unfilled delay slot. */
3425 else if (GET_CODE (insn
) == INSN
3426 && GET_CODE (pat
) != SEQUENCE
3427 && GET_CODE (pat
) != USE
3428 && GET_CODE (pat
) != CLOBBER
3429 && get_attr_type (insn
) == TYPE_MILLI
)
3431 /* Block move pattern. */
3432 else if (GET_CODE (insn
) == INSN
3433 && GET_CODE (pat
) == PARALLEL
3434 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
3435 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
3436 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
3437 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
3438 return compute_movstrsi_length (insn
) - 4;
3439 /* Conditional branch with an unfilled delay slot. */
3440 else if (GET_CODE (insn
) == JUMP_INSN
&& ! simplejump_p (insn
))
3442 /* Adjust a short backwards conditional with an unfilled delay slot. */
3443 if (GET_CODE (pat
) == SET
3445 && ! forward_branch_p (insn
))
3447 else if (GET_CODE (pat
) == PARALLEL
3448 && get_attr_type (insn
) == TYPE_PARALLEL_BRANCH
3451 /* Adjust dbra insn with short backwards conditional branch with
3452 unfilled delay slot -- only for case where counter is in a
3453 general register register. */
3454 else if (GET_CODE (pat
) == PARALLEL
3455 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
3456 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
3457 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
3459 && ! forward_branch_p (insn
))
3467 /* Print operand X (an rtx) in assembler syntax to file FILE.
3468 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3469 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3472 print_operand (file
, x
, code
)
3480 /* Output a 'nop' if there's nothing for the delay slot. */
3481 if (dbr_sequence_length () == 0)
3482 fputs ("\n\tnop", file
);
3485 /* Output an nullification completer if there's nothing for the */
3486 /* delay slot or nullification is requested. */
3487 if (dbr_sequence_length () == 0 ||
3489 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
3493 /* Print out the second register name of a register pair.
3494 I.e., R (6) => 7. */
3495 fputs (reg_names
[REGNO (x
)+1], file
);
3498 /* A register or zero. */
3500 || (x
== CONST0_RTX (DFmode
))
3501 || (x
== CONST0_RTX (SFmode
)))
3508 case 'C': /* Plain (C)ondition */
3510 switch (GET_CODE (x
))
3513 fputs ("=", file
); break;
3515 fputs ("<>", file
); break;
3517 fputs (">", file
); break;
3519 fputs (">=", file
); break;
3521 fputs (">>=", file
); break;
3523 fputs (">>", file
); break;
3525 fputs ("<", file
); break;
3527 fputs ("<=", file
); break;
3529 fputs ("<<=", file
); break;
3531 fputs ("<<", file
); break;
3536 case 'N': /* Condition, (N)egated */
3537 switch (GET_CODE (x
))
3540 fputs ("<>", file
); break;
3542 fputs ("=", file
); break;
3544 fputs ("<=", file
); break;
3546 fputs ("<", file
); break;
3548 fputs ("<<", file
); break;
3550 fputs ("<<=", file
); break;
3552 fputs (">=", file
); break;
3554 fputs (">", file
); break;
3556 fputs (">>", file
); break;
3558 fputs (">>=", file
); break;
3563 /* For floating point comparisons. Need special conditions to deal
3564 with NaNs properly. */
3566 switch (GET_CODE (x
))
3569 fputs ("!=", file
); break;
3571 fputs ("=", file
); break;
3573 fputs ("<=", file
); break;
3575 fputs ("<", file
); break;
3577 fputs (">=", file
); break;
3579 fputs (">", file
); break;
3584 case 'S': /* Condition, operands are (S)wapped. */
3585 switch (GET_CODE (x
))
3588 fputs ("=", file
); break;
3590 fputs ("<>", file
); break;
3592 fputs ("<", file
); break;
3594 fputs ("<=", file
); break;
3596 fputs ("<<=", file
); break;
3598 fputs ("<<", file
); break;
3600 fputs (">", file
); break;
3602 fputs (">=", file
); break;
3604 fputs (">>=", file
); break;
3606 fputs (">>", file
); break;
3611 case 'B': /* Condition, (B)oth swapped and negate. */
3612 switch (GET_CODE (x
))
3615 fputs ("<>", file
); break;
3617 fputs ("=", file
); break;
3619 fputs (">=", file
); break;
3621 fputs (">", file
); break;
3623 fputs (">>", file
); break;
3625 fputs (">>=", file
); break;
3627 fputs ("<=", file
); break;
3629 fputs ("<", file
); break;
3631 fputs ("<<", file
); break;
3633 fputs ("<<=", file
); break;
3639 if (GET_CODE (x
) == CONST_INT
)
3641 fprintf (file
, "%d", ~INTVAL (x
));
3646 if (GET_CODE (x
) == CONST_INT
)
3648 fprintf (file
, "%d", 32 - (INTVAL (x
) & 31));
3653 if (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0)
3655 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
3660 if (GET_CODE (x
) == CONST_INT
)
3662 fprintf (file
, "%d", 31 - (INTVAL (x
) & 31));
3667 if (GET_CODE (x
) == CONST_INT
)
3672 switch (GET_CODE (XEXP (x
, 0)))
3676 fputs ("s,mb", file
);
3680 fputs ("s,ma", file
);
3683 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3684 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
3685 fputs ("x,s", file
);
3686 else if (code
== 'F')
3696 output_global_address (file
, x
, 0);
3699 output_global_address (file
, x
, 1);
3701 case 0: /* Don't do anything special */
3706 compute_zdepi_operands (INTVAL (x
), op
);
3707 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
3713 if (GET_CODE (x
) == REG
)
3715 fputs (reg_names
[REGNO (x
)], file
);
3716 if (FP_REG_P (x
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4 && (REGNO (x
) & 1) == 0)
3719 else if (GET_CODE (x
) == MEM
)
3721 int size
= GET_MODE_SIZE (GET_MODE (x
));
3722 rtx base
= XEXP (XEXP (x
, 0), 0);
3723 switch (GET_CODE (XEXP (x
, 0)))
3727 fprintf (file
, "-%d(0,%s)", size
, reg_names
[REGNO (base
)]);
3731 fprintf (file
, "%d(0,%s)", size
, reg_names
[REGNO (base
)]);
3734 if (GET_CODE (XEXP (x
, 0)) == PLUS
3735 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
3736 fprintf (file
, "%s(0,%s)",
3737 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 0), 0))],
3738 reg_names
[REGNO (XEXP (XEXP (x
, 0), 1))]);
3739 else if (GET_CODE (XEXP (x
, 0)) == PLUS
3740 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
3741 fprintf (file
, "%s(0,%s)",
3742 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 1), 0))],
3743 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
3745 output_address (XEXP (x
, 0));
3750 output_addr_const (file
, x
);
3753 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3756 output_global_address (file
, x
, round_constant
)
3762 /* Imagine (high (const (plus ...))). */
3763 if (GET_CODE (x
) == HIGH
)
3766 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
))
3767 assemble_name (file
, XSTR (x
, 0));
3768 else if (GET_CODE (x
) == SYMBOL_REF
&& !flag_pic
)
3770 assemble_name (file
, XSTR (x
, 0));
3771 fputs ("-$global$", file
);
3773 else if (GET_CODE (x
) == CONST
)
3776 int offset
= 0; /* assembler wants -$global$ at end */
3779 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
3781 base
= XEXP (XEXP (x
, 0), 0);
3782 output_addr_const (file
, base
);
3784 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == CONST_INT
)
3785 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
3788 if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == SYMBOL_REF
)
3790 base
= XEXP (XEXP (x
, 0), 1);
3791 output_addr_const (file
, base
);
3793 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
3794 offset
= INTVAL (XEXP (XEXP (x
, 0),1));
3797 /* How bogus. The compiler is apparently responsible for
3798 rounding the constant if it uses an LR field selector.
3800 The linker and/or assembler seem a better place since
3801 they have to do this kind of thing already.
3803 If we fail to do this, HP's optimizing linker may eliminate
3804 an addil, but not update the ldw/stw/ldo instruction that
3805 uses the result of the addil. */
3807 offset
= ((offset
+ 0x1000) & ~0x1fff);
3809 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
3819 else if (GET_CODE (XEXP (x
, 0)) == MINUS
3820 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3824 if (!read_only_operand (base
) && !flag_pic
)
3825 fputs ("-$global$", file
);
3827 fprintf (file
,"%s%d", sep
, offset
);
3830 output_addr_const (file
, x
);
3833 /* HP's millicode routines mean something special to the assembler.
3834 Keep track of which ones we have used. */
3836 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, mulU
, end1000
};
3837 static char imported
[(int)end1000
];
3838 static char *milli_names
[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
3839 static char import_string
[] = ".IMPORT $$....,MILLICODE";
3840 #define MILLI_START 10
3844 enum millicodes code
;
3846 char str
[sizeof (import_string
)];
3848 if (!imported
[(int)code
])
3850 imported
[(int)code
] = 1;
3851 strcpy (str
, import_string
);
3852 strncpy (str
+ MILLI_START
, milli_names
[(int)code
], 4);
3853 output_asm_insn (str
, 0);
3857 /* The register constraints have put the operands and return value in
3858 the proper registers. */
3861 output_mul_insn (unsignedp
, insn
)
3865 import_milli (mulI
);
3866 return output_millicode_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$mulI"));
3869 /* Emit the rtl for doing a division by a constant. */
3871 /* Do magic division millicodes exist for this value? */
3872 static int magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
3875 /* We'll use an array to keep track of the magic millicodes and
3876 whether or not we've used them already. [n][0] is signed, [n][1] is
3879 static int div_milli
[16][2];
3882 div_operand (op
, mode
)
3884 enum machine_mode mode
;
3886 return (mode
== SImode
3887 && ((GET_CODE (op
) == REG
&& REGNO (op
) == 25)
3888 || (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) > 0
3889 && INTVAL (op
) < 16 && magic_milli
[INTVAL (op
)])));
3893 emit_hpdiv_const (operands
, unsignedp
)
3897 if (GET_CODE (operands
[2]) == CONST_INT
3898 && INTVAL (operands
[2]) > 0
3899 && INTVAL (operands
[2]) < 16
3900 && magic_milli
[INTVAL (operands
[2])])
3902 emit_move_insn ( gen_rtx (REG
, SImode
, 26), operands
[1]);
3905 (PARALLEL
, VOIDmode
,
3906 gen_rtvec (5, gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, SImode
, 29),
3907 gen_rtx (unsignedp
? UDIV
: DIV
, SImode
,
3908 gen_rtx (REG
, SImode
, 26),
3910 gen_rtx (CLOBBER
, VOIDmode
, operands
[3]),
3911 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 26)),
3912 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 25)),
3913 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 31)))));
3914 emit_move_insn (operands
[0], gen_rtx (REG
, SImode
, 29));
3921 output_div_insn (operands
, unsignedp
, insn
)
3928 /* If the divisor is a constant, try to use one of the special
3930 if (GET_CODE (operands
[0]) == CONST_INT
)
3932 static char buf
[100];
3933 divisor
= INTVAL (operands
[0]);
3934 if (!div_milli
[divisor
][unsignedp
])
3936 div_milli
[divisor
][unsignedp
] = 1;
3938 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
3940 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
3944 sprintf (buf
, "$$divU_%d", INTVAL (operands
[0]));
3945 return output_millicode_call (insn
,
3946 gen_rtx (SYMBOL_REF
, SImode
, buf
));
3950 sprintf (buf
, "$$divI_%d", INTVAL (operands
[0]));
3951 return output_millicode_call (insn
,
3952 gen_rtx (SYMBOL_REF
, SImode
, buf
));
3955 /* Divisor isn't a special constant. */
3960 import_milli (divU
);
3961 return output_millicode_call (insn
,
3962 gen_rtx (SYMBOL_REF
, SImode
, "$$divU"));
3966 import_milli (divI
);
3967 return output_millicode_call (insn
,
3968 gen_rtx (SYMBOL_REF
, SImode
, "$$divI"));
3973 /* Output a $$rem millicode to do mod. */
3976 output_mod_insn (unsignedp
, insn
)
3982 import_milli (remU
);
3983 return output_millicode_call (insn
,
3984 gen_rtx (SYMBOL_REF
, SImode
, "$$remU"));
3988 import_milli (remI
);
3989 return output_millicode_call (insn
,
3990 gen_rtx (SYMBOL_REF
, SImode
, "$$remI"));
3995 output_arg_descriptor (call_insn
)
3999 enum machine_mode arg_mode
;
4001 int i
, output_flag
= 0;
4004 for (i
= 0; i
< 4; i
++)
4007 /* Specify explicitly that no argument relocations should take place
4008 if using the portable runtime calling conventions. */
4009 if (TARGET_PORTABLE_RUNTIME
)
4011 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4016 if (GET_CODE (call_insn
) != CALL_INSN
)
4018 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); link
; link
= XEXP (link
, 1))
4020 rtx use
= XEXP (link
, 0);
4022 if (! (GET_CODE (use
) == USE
4023 && GET_CODE (XEXP (use
, 0)) == REG
4024 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
4027 arg_mode
= GET_MODE (XEXP (use
, 0));
4028 regno
= REGNO (XEXP (use
, 0));
4029 if (regno
>= 23 && regno
<= 26)
4031 arg_regs
[26 - regno
] = "GR";
4032 if (arg_mode
== DImode
)
4033 arg_regs
[25 - regno
] = "GR";
4035 else if (regno
>= 32 && regno
<= 39)
4037 if (arg_mode
== SFmode
)
4038 arg_regs
[(regno
- 32) / 2] = "FR";
4041 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4042 arg_regs
[(regno
- 34) / 2] = "FR";
4043 arg_regs
[(regno
- 34) / 2 + 1] = "FU";
4045 arg_regs
[(regno
- 34) / 2] = "FU";
4046 arg_regs
[(regno
- 34) / 2 + 1] = "FR";
4051 fputs ("\t.CALL ", asm_out_file
);
4052 for (i
= 0; i
< 4; i
++)
4057 fputc (',', asm_out_file
);
4058 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
4061 fputc ('\n', asm_out_file
);
4064 /* Return the class of any secondary reload register that is needed to
4065 move IN into a register in class CLASS using mode MODE.
4067 Profiling has showed this routine and its descendants account for
4068 a significant amount of compile time (~7%). So it has been
4069 optimized to reduce redundant computations and eliminate useless
4072 It might be worthwhile to try and make this a leaf function too. */
4075 secondary_reload_class (class, mode
, in
)
4076 enum reg_class
class;
4077 enum machine_mode mode
;
4080 int regno
, is_symbolic
;
4082 /* Trying to load a constant into a FP register during PIC code
4083 generation will require %r1 as a scratch register. */
4085 && GET_MODE_CLASS (mode
) == MODE_INT
4086 && FP_REG_CLASS_P (class)
4087 && (GET_CODE (in
) == CONST_INT
|| GET_CODE (in
) == CONST_DOUBLE
))
4090 /* Profiling showed the PA port spends about 1.3% of its compilation
4091 time in true_regnum from calls inside secondary_reload_class. */
4093 if (GET_CODE (in
) == REG
)
4096 if (regno
>= FIRST_PSEUDO_REGISTER
)
4097 regno
= true_regnum (in
);
4099 else if (GET_CODE (in
) == SUBREG
)
4100 regno
= true_regnum (in
);
4104 if (((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
4105 && GET_MODE_CLASS (mode
) == MODE_INT
4106 && FP_REG_CLASS_P (class))
4107 || (class == SHIFT_REGS
&& (regno
<= 0 || regno
>= 32)))
4108 return GENERAL_REGS
;
4110 if (GET_CODE (in
) == HIGH
)
4113 /* Profiling has showed GCC spends about 2.6% of its compilation
4114 time in symbolic_operand from calls inside secondary_reload_class.
4116 We use an inline copy and only compute its return value once to avoid
4118 switch (GET_CODE (in
))
4128 is_symbolic
= ((GET_CODE (XEXP (tmp
, 0)) == SYMBOL_REF
4129 || GET_CODE (XEXP (tmp
, 0)) == LABEL_REF
)
4130 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
);
4139 && read_only_operand (in
))
4142 if (class != R1_REGS
&& is_symbolic
)
4149 function_arg_padding (mode
, type
)
4150 enum machine_mode mode
;
4155 if (mode
== BLKmode
)
4157 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4158 size
= int_size_in_bytes (type
) * BITS_PER_UNIT
;
4160 return upward
; /* Don't know if this is right, but */
4161 /* same as old definition. */
4164 size
= GET_MODE_BITSIZE (mode
);
4165 if (size
< PARM_BOUNDARY
)
4167 else if (size
% PARM_BOUNDARY
)
4174 /* Do what is necessary for `va_start'. The argument is ignored;
4175 We look at the current function to determine if stdargs or varargs
4176 is used and fill in an initial va_list. A pointer to this constructor
4180 hppa_builtin_saveregs (arglist
)
4184 tree fntype
= TREE_TYPE (current_function_decl
);
4185 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
4186 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4187 != void_type_node
)))
4188 ? UNITS_PER_WORD
: 0);
4191 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
4193 offset
= current_function_arg_offset_rtx
;
4195 /* Store general registers on the stack. */
4196 move_block_from_reg (23,
4197 gen_rtx (MEM
, BLKmode
,
4199 (current_function_internal_arg_pointer
, -16)),
4200 4, 4 * UNITS_PER_WORD
);
4201 return copy_to_reg (expand_binop (Pmode
, add_optab
,
4202 current_function_internal_arg_pointer
,
4203 offset
, 0, 0, OPTAB_LIB_WIDEN
));
4206 /* This routine handles all the normal conditional branch sequences we
4207 might need to generate. It handles compare immediate vs compare
4208 register, nullification of delay slots, varying length branches,
4209 negated branches, and all combinations of the above. It returns the
4210 output appropriate to emit the branch corresponding to all given
4214 output_cbranch (operands
, nullify
, length
, negated
, insn
)
4216 int nullify
, length
, negated
;
4219 static char buf
[100];
4222 /* A conditional branch to the following instruction (eg the delay slot) is
4223 asking for a disaster. This can happen when not optimizing.
4225 In such cases it is safe to emit nothing. */
4227 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4230 /* If this is a long branch with its delay slot unfilled, set `nullify'
4231 as it can nullify the delay slot and save a nop. */
4232 if (length
== 8 && dbr_sequence_length () == 0)
4235 /* If this is a short forward conditional branch which did not get
4236 its delay slot filled, the delay slot can still be nullified. */
4237 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4238 nullify
= forward_branch_p (insn
);
4240 /* A forward branch over a single nullified insn can be done with a
4241 comclr instruction. This avoids a single cycle penalty due to
4242 mis-predicted branch if we fall through (branch not taken). */
4244 && next_real_insn (insn
) != 0
4245 && get_attr_length (next_real_insn (insn
)) == 4
4246 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
4252 /* All short conditional branches except backwards with an unfilled
4256 strcpy (buf
, "com%I2clr,");
4258 strcpy (buf
, "com%I2b,");
4260 strcat (buf
, "%B3");
4262 strcat (buf
, "%S3");
4264 strcat (buf
, " %2,%1,0");
4266 strcat (buf
, ",n %2,%1,%0");
4268 strcat (buf
, " %2,%1,%0");
4271 /* All long conditionals. Note an short backward branch with an
4272 unfilled delay slot is treated just like a long backward branch
4273 with an unfilled delay slot. */
4275 /* Handle weird backwards branch with a filled delay slot
4276 with is nullified. */
4277 if (dbr_sequence_length () != 0
4278 && ! forward_branch_p (insn
)
4281 strcpy (buf
, "com%I2b,");
4283 strcat (buf
, "%S3");
4285 strcat (buf
, "%B3");
4286 strcat (buf
, ",n %2,%1,.+12\n\tbl %0,0");
4288 /* Handle short backwards branch with an unfilled delay slot.
4289 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4290 taken and untaken branches. */
4291 else if (dbr_sequence_length () == 0
4292 && ! forward_branch_p (insn
)
4294 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4295 - insn_addresses
[INSN_UID (insn
)] - 8))
4297 strcpy (buf
, "com%I2b,");
4299 strcat (buf
, "%B3 %2,%1,%0%#");
4301 strcat (buf
, "%S3 %2,%1,%0%#");
4305 strcpy (buf
, "com%I2clr,");
4307 strcat (buf
, "%S3");
4309 strcat (buf
, "%B3");
4311 strcat (buf
, " %2,%1,0\n\tbl,n %0,0");
4313 strcat (buf
, " %2,%1,0\n\tbl %0,0");
4323 /* This routine handles all the branch-on-bit conditional branch sequences we
4324 might need to generate. It handles nullification of delay slots,
4325 varying length branches, negated branches and all combinations of the
4326 above. it returns the appropriate output template to emit the branch. */
4329 output_bb (operands
, nullify
, length
, negated
, insn
, which
)
4331 int nullify
, length
, negated
;
4335 static char buf
[100];
4338 /* A conditional branch to the following instruction (eg the delay slot) is
4339 asking for a disaster. I do not think this can happen as this pattern
4340 is only used when optimizing; jump optimization should eliminate the
4341 jump. But be prepared just in case. */
4343 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4346 /* If this is a long branch with its delay slot unfilled, set `nullify'
4347 as it can nullify the delay slot and save a nop. */
4348 if (length
== 8 && dbr_sequence_length () == 0)
4351 /* If this is a short forward conditional branch which did not get
4352 its delay slot filled, the delay slot can still be nullified. */
4353 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4354 nullify
= forward_branch_p (insn
);
4356 /* A forward branch over a single nullified insn can be done with a
4357 extrs instruction. This avoids a single cycle penalty due to
4358 mis-predicted branch if we fall through (branch not taken). */
4361 && next_real_insn (insn
) != 0
4362 && get_attr_length (next_real_insn (insn
)) == 4
4363 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
4370 /* All short conditional branches except backwards with an unfilled
4374 strcpy (buf
, "extrs,");
4376 strcpy (buf
, "bb,");
4377 if ((which
== 0 && negated
)
4378 || (which
== 1 && ! negated
))
4383 strcat (buf
, " %0,%1,1,0");
4384 else if (nullify
&& negated
)
4385 strcat (buf
, ",n %0,%1,%3");
4386 else if (nullify
&& ! negated
)
4387 strcat (buf
, ",n %0,%1,%2");
4388 else if (! nullify
&& negated
)
4389 strcat (buf
, "%0,%1,%3");
4390 else if (! nullify
&& ! negated
)
4391 strcat (buf
, " %0,%1,%2");
4394 /* All long conditionals. Note an short backward branch with an
4395 unfilled delay slot is treated just like a long backward branch
4396 with an unfilled delay slot. */
4398 /* Handle weird backwards branch with a filled delay slot
4399 with is nullified. */
4400 if (dbr_sequence_length () != 0
4401 && ! forward_branch_p (insn
)
4404 strcpy (buf
, "bb,");
4405 if ((which
== 0 && negated
)
4406 || (which
== 1 && ! negated
))
4411 strcat (buf
, ",n %0,%1,.+12\n\tbl %3,0");
4413 strcat (buf
, ",n %0,%1,.+12\n\tbl %2,0");
4415 /* Handle short backwards branch with an unfilled delay slot.
4416 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4417 taken and untaken branches. */
4418 else if (dbr_sequence_length () == 0
4419 && ! forward_branch_p (insn
)
4421 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4422 - insn_addresses
[INSN_UID (insn
)] - 8))
4424 strcpy (buf
, "bb,");
4425 if ((which
== 0 && negated
)
4426 || (which
== 1 && ! negated
))
4431 strcat (buf
, " %0,%1,%3%#");
4433 strcat (buf
, " %0,%1,%2%#");
4437 strcpy (buf
, "extrs,");
4438 if ((which
== 0 && negated
)
4439 || (which
== 1 && ! negated
))
4443 if (nullify
&& negated
)
4444 strcat (buf
, " %0,%1,1,0\n\tbl,n %3,0");
4445 else if (nullify
&& ! negated
)
4446 strcat (buf
, " %0,%1,1,0\n\tbl,n %2,0");
4448 strcat (buf
, " %0,%1,1,0\n\tbl %3,0");
4450 strcat (buf
, " %0,%1,1,0\n\tbl %2,0");
4460 /* This routine handles all the branch-on-variable-bit conditional branch
4461 sequences we might need to generate. It handles nullification of delay
4462 slots, varying length branches, negated branches and all combinations
4463 of the above. it returns the appropriate output template to emit the
4467 output_bvb (operands
, nullify
, length
, negated
, insn
, which
)
4469 int nullify
, length
, negated
;
4473 static char buf
[100];
4476 /* A conditional branch to the following instruction (eg the delay slot) is
4477 asking for a disaster. I do not think this can happen as this pattern
4478 is only used when optimizing; jump optimization should eliminate the
4479 jump. But be prepared just in case. */
4481 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4484 /* If this is a long branch with its delay slot unfilled, set `nullify'
4485 as it can nullify the delay slot and save a nop. */
4486 if (length
== 8 && dbr_sequence_length () == 0)
4489 /* If this is a short forward conditional branch which did not get
4490 its delay slot filled, the delay slot can still be nullified. */
4491 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4492 nullify
= forward_branch_p (insn
);
4494 /* A forward branch over a single nullified insn can be done with a
4495 extrs instruction. This avoids a single cycle penalty due to
4496 mis-predicted branch if we fall through (branch not taken). */
4499 && next_real_insn (insn
) != 0
4500 && get_attr_length (next_real_insn (insn
)) == 4
4501 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
4508 /* All short conditional branches except backwards with an unfilled
4512 strcpy (buf
, "vextrs,");
4514 strcpy (buf
, "bvb,");
4515 if ((which
== 0 && negated
)
4516 || (which
== 1 && ! negated
))
4521 strcat (buf
, " %0,1,0");
4522 else if (nullify
&& negated
)
4523 strcat (buf
, ",n %0,%3");
4524 else if (nullify
&& ! negated
)
4525 strcat (buf
, ",n %0,%2");
4526 else if (! nullify
&& negated
)
4527 strcat (buf
, "%0,%3");
4528 else if (! nullify
&& ! negated
)
4529 strcat (buf
, " %0,%2");
4532 /* All long conditionals. Note an short backward branch with an
4533 unfilled delay slot is treated just like a long backward branch
4534 with an unfilled delay slot. */
4536 /* Handle weird backwards branch with a filled delay slot
4537 with is nullified. */
4538 if (dbr_sequence_length () != 0
4539 && ! forward_branch_p (insn
)
4542 strcpy (buf
, "bvb,");
4543 if ((which
== 0 && negated
)
4544 || (which
== 1 && ! negated
))
4549 strcat (buf
, ",n %0,.+12\n\tbl %3,0");
4551 strcat (buf
, ",n %0,.+12\n\tbl %2,0");
4553 /* Handle short backwards branch with an unfilled delay slot.
4554 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4555 taken and untaken branches. */
4556 else if (dbr_sequence_length () == 0
4557 && ! forward_branch_p (insn
)
4559 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4560 - insn_addresses
[INSN_UID (insn
)] - 8))
4562 strcpy (buf
, "bvb,");
4563 if ((which
== 0 && negated
)
4564 || (which
== 1 && ! negated
))
4569 strcat (buf
, " %0,%3%#");
4571 strcat (buf
, " %0,%2%#");
4575 strcpy (buf
, "vextrs,");
4576 if ((which
== 0 && negated
)
4577 || (which
== 1 && ! negated
))
4581 if (nullify
&& negated
)
4582 strcat (buf
, " %0,1,0\n\tbl,n %3,0");
4583 else if (nullify
&& ! negated
)
4584 strcat (buf
, " %0,1,0\n\tbl,n %2,0");
4586 strcat (buf
, " %0,1,0\n\tbl %3,0");
4588 strcat (buf
, " %0,1,0\n\tbl %2,0");
4598 /* Return the output template for emitting a dbra type insn.
4600 Note it may perform some output operations on its own before
4601 returning the final output string. */
4603 output_dbra (operands
, insn
, which_alternative
)
4606 int which_alternative
;
4609 /* A conditional branch to the following instruction (eg the delay slot) is
4610 asking for a disaster. Be prepared! */
4612 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4614 if (which_alternative
== 0)
4615 return "ldo %1(%0),%0";
4616 else if (which_alternative
== 1)
4618 output_asm_insn ("fstws %0,-16(0,%%r30)",operands
);
4619 output_asm_insn ("ldw -16(0,%%r30),%4",operands
);
4620 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
4621 return "fldws -16(0,%%r30),%0";
4625 output_asm_insn ("ldw %0,%4", operands
);
4626 return "ldo %1(%4),%4\n\tstw %4,%0";
4630 if (which_alternative
== 0)
4632 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
4633 int length
= get_attr_length (insn
);
4635 /* If this is a long branch with its delay slot unfilled, set `nullify'
4636 as it can nullify the delay slot and save a nop. */
4637 if (length
== 8 && dbr_sequence_length () == 0)
4640 /* If this is a short forward conditional branch which did not get
4641 its delay slot filled, the delay slot can still be nullified. */
4642 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4643 nullify
= forward_branch_p (insn
);
4645 /* Handle short versions first. */
4646 if (length
== 4 && nullify
)
4647 return "addib,%C2,n %1,%0,%3";
4648 else if (length
== 4 && ! nullify
)
4649 return "addib,%C2 %1,%0,%3";
4650 else if (length
== 8)
4652 /* Handle weird backwards branch with a fulled delay slot
4653 which is nullified. */
4654 if (dbr_sequence_length () != 0
4655 && ! forward_branch_p (insn
)
4657 return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
4658 /* Handle short backwards branch with an unfilled delay slot.
4659 Using a addb;nop rather than addi;bl saves 1 cycle for both
4660 taken and untaken branches. */
4661 else if (dbr_sequence_length () == 0
4662 && ! forward_branch_p (insn
)
4664 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4665 - insn_addresses
[INSN_UID (insn
)] - 8))
4666 return "addib,%C2 %1,%0,%3%#";
4668 /* Handle normal cases. */
4670 return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
4672 return "addi,%N2 %1,%0,%0\n\tbl %3,0";
4677 /* Deal with gross reload from FP register case. */
4678 else if (which_alternative
== 1)
4680 /* Move loop counter from FP register to MEM then into a GR,
4681 increment the GR, store the GR into MEM, and finally reload
4682 the FP register from MEM from within the branch's delay slot. */
4683 output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands
);
4684 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
4685 if (get_attr_length (insn
) == 24)
4686 return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
4688 return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
4690 /* Deal with gross reload from memory case. */
4693 /* Reload loop counter from memory, the store back to memory
4694 happens in the branch's delay slot. */
4695 output_asm_insn ("ldw %0,%4", operands
);
4696 if (get_attr_length (insn
) == 12)
4697 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
4699 return "addi,%N2 %1,%4,%4\n\tbl %3,0\n\tstw %4,%0";
4703 /* Return the output template for emitting a dbra type insn.
4705 Note it may perform some output operations on its own before
4706 returning the final output string. */
4708 output_movb (operands
, insn
, which_alternative
, reverse_comparison
)
4711 int which_alternative
;
4712 int reverse_comparison
;
4715 /* A conditional branch to the following instruction (eg the delay slot) is
4716 asking for a disaster. Be prepared! */
4718 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4720 if (which_alternative
== 0)
4721 return "copy %1,%0";
4722 else if (which_alternative
== 1)
4724 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
4725 return "fldws -16(0,%%r30),%0";
4727 else if (which_alternative
== 2)
4733 /* Support the second variant. */
4734 if (reverse_comparison
)
4735 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
4737 if (which_alternative
== 0)
4739 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
4740 int length
= get_attr_length (insn
);
4742 /* If this is a long branch with its delay slot unfilled, set `nullify'
4743 as it can nullify the delay slot and save a nop. */
4744 if (length
== 8 && dbr_sequence_length () == 0)
4747 /* If this is a short forward conditional branch which did not get
4748 its delay slot filled, the delay slot can still be nullified. */
4749 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4750 nullify
= forward_branch_p (insn
);
4752 /* Handle short versions first. */
4753 if (length
== 4 && nullify
)
4754 return "movb,%C2,n %1,%0,%3";
4755 else if (length
== 4 && ! nullify
)
4756 return "movb,%C2 %1,%0,%3";
4757 else if (length
== 8)
4759 /* Handle weird backwards branch with a filled delay slot
4760 which is nullified. */
4761 if (dbr_sequence_length () != 0
4762 && ! forward_branch_p (insn
)
4764 return "movb,%N2,n %1,%0,.+12\n\tbl %3,0";
4766 /* Handle short backwards branch with an unfilled delay slot.
4767 Using a movb;nop rather than or;bl saves 1 cycle for both
4768 taken and untaken branches. */
4769 else if (dbr_sequence_length () == 0
4770 && ! forward_branch_p (insn
)
4772 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4773 - insn_addresses
[INSN_UID (insn
)] - 8))
4774 return "movb,%C2 %1,%0,%3%#";
4775 /* Handle normal cases. */
4777 return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
4779 return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
4784 /* Deal with gross reload from FP register case. */
4785 else if (which_alternative
== 1)
4787 /* Move loop counter from FP register to MEM then into a GR,
4788 increment the GR, store the GR into MEM, and finally reload
4789 the FP register from MEM from within the branch's delay slot. */
4790 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
4791 if (get_attr_length (insn
) == 12)
4792 return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
4794 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
4796 /* Deal with gross reload from memory case. */
4797 else if (which_alternative
== 2)
4799 /* Reload loop counter from memory, the store back to memory
4800 happens in the branch's delay slot. */
4801 if (get_attr_length (insn
) == 8)
4802 return "comb,%S2 0,%1,%3\n\tstw %1,%0";
4804 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
4806 /* Handle SAR as a destination. */
4809 if (get_attr_length (insn
) == 8)
4810 return "comb,%S2 0,%1,%3\n\tmtsar %r1";
4812 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tmtsar %r1";
4817 /* INSN is a millicode call. It may have an unconditional jump in its delay
4820 CALL_DEST is the routine we are calling. */
4823 output_millicode_call (insn
, call_dest
)
4831 /* Handle common case -- empty delay slot or no jump in the delay slot,
4832 and we're sure that the branch will reach the beginning of the $CODE$
4834 if ((dbr_sequence_length () == 0
4835 && (get_attr_length (insn
) == 8 || get_attr_length (insn
) == 28))
4836 || (dbr_sequence_length () != 0
4837 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
4838 && get_attr_length (insn
) == 4))
4840 xoperands
[0] = call_dest
;
4841 output_asm_insn ("bl %0,%%r31%#", xoperands
);
4845 /* This call may not reach the beginning of the $CODE$ subspace. */
4846 if (get_attr_length (insn
) > 4)
4848 int delay_insn_deleted
= 0;
4852 /* We need to emit an inline long-call branch. */
4853 if (dbr_sequence_length () != 0
4854 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
4856 /* A non-jump insn in the delay slot. By definition we can
4857 emit this insn before the call. */
4858 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
4860 /* Now delete the delay insn. */
4861 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4862 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4863 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4864 delay_insn_deleted
= 1;
4867 /* If we're allowed to use be/ble instructions, then this is the
4868 best sequence to use for a long millicode call. */
4869 if (TARGET_NO_SPACE_REGS
|| TARGET_FAST_INDIRECT_CALLS
4870 || ! (flag_pic
|| TARGET_PORTABLE_RUNTIME
))
4872 xoperands
[0] = call_dest
;
4873 output_asm_insn ("ldil L%%%0,%%r31", xoperands
);
4874 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands
);
4875 output_asm_insn ("nop", xoperands
);
4877 /* Pure portable runtime doesn't allow be/ble; we also don't have
4878 PIC support int he assembler/linker, so this sequence is needed. */
4879 else if (TARGET_PORTABLE_RUNTIME
)
4881 xoperands
[0] = call_dest
;
4882 /* Get the address of our target into %r29. */
4883 output_asm_insn ("ldil L%%%0,%%r29", xoperands
);
4884 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands
);
4886 /* Get our return address into %r31. */
4887 output_asm_insn ("blr 0,%%r31", xoperands
);
4889 /* Jump to our target address in %r29. */
4890 output_asm_insn ("bv,n 0(%%r29)", xoperands
);
4892 /* Empty delay slot. Note this insn gets fetched twice and
4893 executed once. To be safe we use a nop. */
4894 output_asm_insn ("nop", xoperands
);
4897 /* PIC long millicode call sequence. */
4900 xoperands
[0] = call_dest
;
4901 xoperands
[1] = gen_label_rtx ();
4902 /* Get our address + 8 into %r1. */
4903 output_asm_insn ("bl .+8,%%r1", xoperands
);
4905 /* Add %r1 to the offset of our target from the next insn. */
4906 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands
);
4907 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4908 CODE_LABEL_NUMBER (xoperands
[1]));
4909 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands
);
4911 /* Get the return address into %r31. */
4912 output_asm_insn ("blr 0,%%r31", xoperands
);
4914 /* Branch to our target which is in %r1. */
4915 output_asm_insn ("bv,n 0(%%r1)", xoperands
);
4917 /* Empty delay slot. Note this insn gets fetched twice and
4918 executed once. To be safe we use a nop. */
4919 output_asm_insn ("nop", xoperands
);
4922 /* If we had a jump in the call's delay slot, output it now. */
4923 if (dbr_sequence_length () != 0
4924 && !delay_insn_deleted
)
4926 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
4927 output_asm_insn ("b,n %0", xoperands
);
4929 /* Now delete the delay insn. */
4930 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4931 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4932 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4937 /* This call has an unconditional jump in its delay slot and the
4938 call is known to reach its target or the beginning of the current
4941 /* Use the containing sequence insn's address. */
4942 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
4944 distance
= insn_addresses
[INSN_UID (JUMP_LABEL (NEXT_INSN (insn
)))]
4945 - insn_addresses
[INSN_UID (seq_insn
)] - 8;
4947 /* If the branch was too far away, emit a normal call followed
4948 by a nop, followed by the unconditional branch.
4950 If the branch is close, then adjust %r2 from within the
4951 call's delay slot. */
4953 xoperands
[0] = call_dest
;
4954 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
4955 if (! VAL_14_BITS_P (distance
))
4956 output_asm_insn ("bl %0,%%r31\n\tnop\n\tbl,n %1,%%r0", xoperands
);
4959 xoperands
[3] = gen_label_rtx ();
4960 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands
);
4961 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4962 CODE_LABEL_NUMBER (xoperands
[3]));
4965 /* Delete the jump. */
4966 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4967 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4968 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4972 /* INSN is either a function call. It may have an unconditional jump
4975 CALL_DEST is the routine we are calling. */
4978 output_call (insn
, call_dest
)
4986 /* Handle common case -- empty delay slot or no jump in the delay slot,
4987 and we're sure that the branch will reach the beginning of the $CODE$
4989 if ((dbr_sequence_length () == 0
4990 && get_attr_length (insn
) == 8)
4991 || (dbr_sequence_length () != 0
4992 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
4993 && get_attr_length (insn
) == 4))
4995 xoperands
[0] = call_dest
;
4996 output_asm_insn ("bl %0,%%r2%#", xoperands
);
5000 /* This call may not reach the beginning of the $CODE$ subspace. */
5001 if (get_attr_length (insn
) > 8)
5003 int delay_insn_deleted
= 0;
5007 /* We need to emit an inline long-call branch. Furthermore,
5008 because we're changing a named function call into an indirect
5009 function call well after the parameters have been set up, we
5010 need to make sure any FP args appear in both the integer
5011 and FP registers. Also, we need move any delay slot insn
5012 out of the delay slot. And finally, we can't rely on the linker
5013 being able to fix the call to $$dyncall! -- Yuk!. */
5014 if (dbr_sequence_length () != 0
5015 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
5017 /* A non-jump insn in the delay slot. By definition we can
5018 emit this insn before the call (and in fact before argument
5020 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
5022 /* Now delete the delay insn. */
5023 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5024 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5025 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5026 delay_insn_deleted
= 1;
5029 /* Now copy any FP arguments into integer registers. */
5030 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
5032 int arg_mode
, regno
;
5033 rtx use
= XEXP (link
, 0);
5034 if (! (GET_CODE (use
) == USE
5035 && GET_CODE (XEXP (use
, 0)) == REG
5036 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
5039 arg_mode
= GET_MODE (XEXP (use
, 0));
5040 regno
= REGNO (XEXP (use
, 0));
5041 /* Is it a floating point register? */
5042 if (regno
>= 32 && regno
<= 39)
5044 /* Copy from the FP register into an integer register
5046 if (arg_mode
== SFmode
)
5048 xoperands
[0] = XEXP (use
, 0);
5049 xoperands
[1] = gen_rtx (REG
, SImode
, 26 - (regno
- 32) / 2);
5050 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands
);
5051 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
5055 xoperands
[0] = XEXP (use
, 0);
5056 xoperands
[1] = gen_rtx (REG
, DImode
, 25 - (regno
- 34) / 2);
5057 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands
);
5058 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands
);
5059 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
5065 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5066 we don't have any direct calls in that case. */
5069 /* We have to load the address of the function using a procedure
5070 label (plabel). The LP and RP relocs don't work reliably for PIC,
5071 so we make a plain 32 bit plabel in the data segment instead. We
5072 have to defer outputting it of course... Not pretty. */
5074 xoperands
[0] = gen_label_rtx ();
5075 xoperands
[1] = gen_label_rtx ();
5076 output_asm_insn ("addil LT%%%0,%%r19", xoperands
);
5077 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands
);
5078 output_asm_insn ("ldw 0(0,%%r22),%%r22", xoperands
);
5080 if (deferred_plabels
== 0)
5081 deferred_plabels
= (struct defer_plab
*)
5082 xmalloc (1 * sizeof (struct defer_plab
));
5084 deferred_plabels
= (struct defer_plab
*)
5085 xrealloc (deferred_plabels
,
5086 (n_deferred_plabels
+ 1) * sizeof (struct defer_plab
));
5087 deferred_plabels
[n_deferred_plabels
].internal_label
= xoperands
[0];
5088 deferred_plabels
[n_deferred_plabels
].symbol
= call_dest
;
5089 n_deferred_plabels
++;
5091 /* Get our address + 8 into %r1. */
5092 output_asm_insn ("bl .+8,%%r1", xoperands
);
5094 /* Add %r1 to the offset of dyncall from the next insn. */
5095 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands
);
5096 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5097 CODE_LABEL_NUMBER (xoperands
[1]));
5098 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands
);
5100 /* Get the return address into %r31. */
5101 output_asm_insn ("blr 0,%%r31", xoperands
);
5103 /* Branch to our target which is in %r1. */
5104 output_asm_insn ("bv 0(%%r1)", xoperands
);
5106 /* Copy the return address into %r2 also. */
5107 output_asm_insn ("copy %%r31,%%r2", xoperands
);
5111 /* No PIC stuff to worry about. We can use ldil;ble. */
5112 xoperands
[0] = call_dest
;
5114 /* Get the address of our target into %r22. */
5115 output_asm_insn ("ldil LP%%%0,%%r22", xoperands
);
5116 output_asm_insn ("ldo RP%%%0(%%r22),%%r22", xoperands
);
5118 /* Get the high part of the address of $dyncall into %r2, then
5119 add in the low part in the branch instruction. */
5120 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands
);
5121 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands
);
5123 /* Copy the return pointer into both %r31 and %r2. */
5124 output_asm_insn ("copy %%r31,%%r2", xoperands
);
5127 /* If we had a jump in the call's delay slot, output it now. */
5128 if (dbr_sequence_length () != 0
5129 && !delay_insn_deleted
)
5131 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5132 output_asm_insn ("b,n %0", xoperands
);
5134 /* Now delete the delay insn. */
5135 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5136 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5137 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5142 /* This call has an unconditional jump in its delay slot and the
5143 call is known to reach its target or the beginning of the current
5146 /* Use the containing sequence insn's address. */
5147 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
5149 distance
= insn_addresses
[INSN_UID (JUMP_LABEL (NEXT_INSN (insn
)))]
5150 - insn_addresses
[INSN_UID (seq_insn
)] - 8;
5152 /* If the branch was too far away, emit a normal call followed
5153 by a nop, followed by the unconditional branch.
5155 If the branch is close, then adjust %r2 from within the
5156 call's delay slot. */
5158 xoperands
[0] = call_dest
;
5159 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5160 if (! VAL_14_BITS_P (distance
))
5161 output_asm_insn ("bl %0,%%r2\n\tnop\n\tbl,n %1,%%r0", xoperands
);
5164 xoperands
[3] = gen_label_rtx ();
5165 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands
);
5166 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5167 CODE_LABEL_NUMBER (xoperands
[3]));
5170 /* Delete the jump. */
5171 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5172 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5173 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5177 extern struct obstack permanent_obstack
;
5178 extern struct obstack
*saveable_obstack
;
5180 /* In HPUX 8.0's shared library scheme, special relocations are needed
5181 for function labels if they might be passed to a function
5182 in a shared library (because shared libraries don't live in code
5183 space), and special magic is needed to construct their address.
5185 For reasons too disgusting to describe storage for the new name
5186 is allocated either on the saveable_obstack (released at function
5187 exit) or on the permanent_obstack for things that can never change
5188 (libcall names for example). */
5191 hppa_encode_label (sym
, permanent
)
5195 char *str
= XSTR (sym
, 0);
5196 int len
= strlen (str
);
5199 newstr
= obstack_alloc ((permanent
? &permanent_obstack
: saveable_obstack
),
5204 strcpy (newstr
+ 1, str
);
5206 XSTR (sym
,0) = newstr
;
5210 function_label_operand (op
, mode
)
5212 enum machine_mode mode
;
5214 return GET_CODE (op
) == SYMBOL_REF
&& FUNCTION_NAME_P (XSTR (op
, 0));
5217 /* Returns 1 if OP is a function label involved in a simple addition
5218 with a constant. Used to keep certain patterns from matching
5219 during instruction combination. */
5221 is_function_label_plus_const (op
)
5224 /* Strip off any CONST. */
5225 if (GET_CODE (op
) == CONST
)
5228 return (GET_CODE (op
) == PLUS
5229 && function_label_operand (XEXP (op
, 0), Pmode
)
5230 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
5233 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5234 use in fmpyadd instructions. */
5236 fmpyaddoperands (operands
)
5239 enum machine_mode mode
= GET_MODE (operands
[0]);
5241 /* Must be a floating point mode. */
5242 if (mode
!= SFmode
&& mode
!= DFmode
)
5245 /* All modes must be the same. */
5246 if (! (mode
== GET_MODE (operands
[1])
5247 && mode
== GET_MODE (operands
[2])
5248 && mode
== GET_MODE (operands
[3])
5249 && mode
== GET_MODE (operands
[4])
5250 && mode
== GET_MODE (operands
[5])))
5253 /* All operands must be registers. */
5254 if (! (GET_CODE (operands
[1]) == REG
5255 && GET_CODE (operands
[2]) == REG
5256 && GET_CODE (operands
[3]) == REG
5257 && GET_CODE (operands
[4]) == REG
5258 && GET_CODE (operands
[5]) == REG
))
5261 /* Only 2 real operands to the addition. One of the input operands must
5262 be the same as the output operand. */
5263 if (! rtx_equal_p (operands
[3], operands
[4])
5264 && ! rtx_equal_p (operands
[3], operands
[5]))
5267 /* Inout operand of add can not conflict with any operands from multiply. */
5268 if (rtx_equal_p (operands
[3], operands
[0])
5269 || rtx_equal_p (operands
[3], operands
[1])
5270 || rtx_equal_p (operands
[3], operands
[2]))
5273 /* multiply can not feed into addition operands. */
5274 if (rtx_equal_p (operands
[4], operands
[0])
5275 || rtx_equal_p (operands
[5], operands
[0]))
5278 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5280 && (REGNO (operands
[0]) < 57
5281 || REGNO (operands
[1]) < 57
5282 || REGNO (operands
[2]) < 57
5283 || REGNO (operands
[3]) < 57
5284 || REGNO (operands
[4]) < 57
5285 || REGNO (operands
[5]) < 57))
5288 /* Passed. Operands are suitable for fmpyadd. */
5292 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5293 use in fmpysub instructions. */
5295 fmpysuboperands (operands
)
5298 enum machine_mode mode
= GET_MODE (operands
[0]);
5300 /* Must be a floating point mode. */
5301 if (mode
!= SFmode
&& mode
!= DFmode
)
5304 /* All modes must be the same. */
5305 if (! (mode
== GET_MODE (operands
[1])
5306 && mode
== GET_MODE (operands
[2])
5307 && mode
== GET_MODE (operands
[3])
5308 && mode
== GET_MODE (operands
[4])
5309 && mode
== GET_MODE (operands
[5])))
5312 /* All operands must be registers. */
5313 if (! (GET_CODE (operands
[1]) == REG
5314 && GET_CODE (operands
[2]) == REG
5315 && GET_CODE (operands
[3]) == REG
5316 && GET_CODE (operands
[4]) == REG
5317 && GET_CODE (operands
[5]) == REG
))
5320 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
5321 operation, so operands[4] must be the same as operand[3]. */
5322 if (! rtx_equal_p (operands
[3], operands
[4]))
5325 /* multiply can not feed into subtraction. */
5326 if (rtx_equal_p (operands
[5], operands
[0]))
5329 /* Inout operand of sub can not conflict with any operands from multiply. */
5330 if (rtx_equal_p (operands
[3], operands
[0])
5331 || rtx_equal_p (operands
[3], operands
[1])
5332 || rtx_equal_p (operands
[3], operands
[2]))
5335 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5337 && (REGNO (operands
[0]) < 57
5338 || REGNO (operands
[1]) < 57
5339 || REGNO (operands
[2]) < 57
5340 || REGNO (operands
[3]) < 57
5341 || REGNO (operands
[4]) < 57
5342 || REGNO (operands
[5]) < 57))
5345 /* Passed. Operands are suitable for fmpysub. */
5350 plus_xor_ior_operator (op
, mode
)
5352 enum machine_mode mode
;
5354 return (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == XOR
5355 || GET_CODE (op
) == IOR
);
5358 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
5359 constants for shadd instructions. */
5361 shadd_constant_p (val
)
5364 if (val
== 2 || val
== 4 || val
== 8)
5370 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
5371 the valid constant for shadd instructions. */
5373 shadd_operand (op
, mode
)
5375 enum machine_mode mode
;
5377 return (GET_CODE (op
) == CONST_INT
&& shadd_constant_p (INTVAL (op
)));
5380 /* Return 1 if OP is valid as a base register in a reg + reg address. */
5383 basereg_operand (op
, mode
)
5385 enum machine_mode mode
;
5387 /* cse will create some unscaled indexed addresses, however; it
5388 generally isn't a win on the PA, so avoid creating unscaled
5389 indexed addresses until after cse is finished. */
5390 if (!cse_not_expected
)
5393 /* Once reload has started everything is considered valid. Reload should
5394 only create indexed addresses using the stack/frame pointer, and any
5395 others were checked for validity when created by the combine pass.
5397 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
5398 we don't have to worry about the braindamaged implicit space register
5399 selection using the basereg only (rather than effective address)
5400 screwing us over. */
5401 if (TARGET_NO_SPACE_REGS
|| reload_in_progress
|| reload_completed
)
5402 return (GET_CODE (op
) == REG
);
5404 /* Stack is always OK for indexing. */
5405 if (op
== stack_pointer_rtx
)
5408 /* While it's always safe to index off the frame pointer, it's not
5409 always profitable, particularly when the frame pointer is being
5411 if (! flag_omit_frame_pointer
&& op
== frame_pointer_rtx
)
5414 /* The only other valid OPs are pseudo registers with
5415 REGNO_POINTER_FLAG set. */
5416 if (GET_CODE (op
) != REG
5417 || REGNO (op
) < FIRST_PSEUDO_REGISTER
5418 || ! register_operand (op
, mode
))
5421 return REGNO_POINTER_FLAG (REGNO (op
));
5424 /* Return 1 if this operand is anything other than a hard register. */
5427 non_hard_reg_operand (op
, mode
)
5429 enum machine_mode mode
;
5431 return ! (GET_CODE (op
) == REG
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
);
5434 /* Return 1 if INSN branches forward. Should be using insn_addresses
5435 to avoid walking through all the insns... */
5437 forward_branch_p (insn
)
5440 rtx label
= JUMP_LABEL (insn
);
5447 insn
= NEXT_INSN (insn
);
5450 return (insn
== label
);
5453 /* Return 1 if OP is an equality comparison, else return 0. */
5455 eq_neq_comparison_operator (op
, mode
)
5457 enum machine_mode mode
;
5459 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
5462 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
5464 movb_comparison_operator (op
, mode
)
5466 enum machine_mode mode
;
5468 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
5469 || GET_CODE (op
) == LT
|| GET_CODE (op
) == GE
);
5472 /* Return 1 if INSN is in the delay slot of a call instruction. */
5474 jump_in_call_delay (insn
)
5478 if (GET_CODE (insn
) != JUMP_INSN
)
5481 if (PREV_INSN (insn
)
5482 && PREV_INSN (PREV_INSN (insn
))
5483 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn
)))) == INSN
)
5485 rtx test_insn
= next_active_insn (PREV_INSN (PREV_INSN (insn
)));
5487 return (GET_CODE (PATTERN (test_insn
)) == SEQUENCE
5488 && XVECEXP (PATTERN (test_insn
), 0, 1) == insn
);
5495 /* Output an unconditional move and branch insn. */
5498 output_parallel_movb (operands
, length
)
5502 /* These are the cases in which we win. */
5504 return "mov%I1b,tr %1,%0,%2";
5506 /* None of these cases wins, but they don't lose either. */
5507 if (dbr_sequence_length () == 0)
5509 /* Nothing in the delay slot, fake it by putting the combined
5510 insn (the copy or add) in the delay slot of a bl. */
5511 if (GET_CODE (operands
[1]) == CONST_INT
)
5512 return "bl %2,0\n\tldi %1,%0";
5514 return "bl %2,0\n\tcopy %1,%0";
5518 /* Something in the delay slot, but we've got a long branch. */
5519 if (GET_CODE (operands
[1]) == CONST_INT
)
5520 return "ldi %1,%0\n\tbl %2,0";
5522 return "copy %1,%0\n\tbl %2,0";
5526 /* Output an unconditional add and branch insn. */
5529 output_parallel_addb (operands
, length
)
5533 /* To make life easy we want operand0 to be the shared input/output
5534 operand and operand1 to be the readonly operand. */
5535 if (operands
[0] == operands
[1])
5536 operands
[1] = operands
[2];
5538 /* These are the cases in which we win. */
5540 return "add%I1b,tr %1,%0,%3";
5542 /* None of these cases win, but they don't lose either. */
5543 if (dbr_sequence_length () == 0)
5545 /* Nothing in the delay slot, fake it by putting the combined
5546 insn (the copy or add) in the delay slot of a bl. */
5547 return "bl %3,0\n\tadd%I1 %1,%0,%0";
5551 /* Something in the delay slot, but we've got a long branch. */
5552 return "add%I1 %1,%0,%0\n\tbl %3,0";
5556 /* Return nonzero if INSN (a jump insn) immediately follows a call. This
5557 is used to discourage creating parallel movb/addb insns since a jump
5558 which immediately follows a call can execute in the delay slot of the
5561 following_call (insn
)
5564 /* Find the previous real insn, skipping NOTEs. */
5565 insn
= PREV_INSN (insn
);
5566 while (insn
&& GET_CODE (insn
) == NOTE
)
5567 insn
= PREV_INSN (insn
);
5569 /* Check for CALL_INSNs and millicode calls. */
5571 && (GET_CODE (insn
) == CALL_INSN
5572 || (GET_CODE (insn
) == INSN
5573 && GET_CODE (PATTERN (insn
)) != SEQUENCE
5574 && GET_CODE (PATTERN (insn
)) != USE
5575 && GET_CODE (PATTERN (insn
)) != CLOBBER
5576 && get_attr_type (insn
) == TYPE_MILLI
)))
5582 /* We use this hook to perform a PA specific optimization which is difficult
5583 to do in earlier passes.
5585 We want the delay slots of branches within jump tables to be filled.
5586 None of the compiler passes at the moment even has the notion that a
5587 PA jump table doesn't contain addresses, but instead contains actual
5590 Because we actually jump into the table, the addresses of each entry
5591 must stay constant in relation to the beginning of the table (which
5592 itself must stay constant relative to the instruction to jump into
5593 it). I don't believe we can guarantee earlier passes of the compiler
5594 will adhere to those rules.
5596 So, late in the compilation process we find all the jump tables, and
5597 expand them into real code -- eg each entry in the jump table vector
5598 will get an appropriate label followed by a jump to the final target.
5600 Reorg and the final jump pass can then optimize these branches and
5601 fill their delay slots. We end up with smaller, more efficient code.
5603 The jump instructions within the table are special; we must be able
5604 to identify them during assembly output (if the jumps don't get filled
5605 we need to emit a nop rather than nullifying the delay slot)). We
5606 identify jumps in switch tables by marking the SET with DImode. */
5613 remove_useless_addtr_insns (insns
, 1);
5615 pa_combine_instructions (get_insns ());
5617 /* This is fairly cheap, so always run it if optimizing. */
5620 /* Find and explode all ADDR_VEC insns. */
5621 insns
= get_insns ();
5622 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
5624 rtx pattern
, tmp
, location
;
5625 unsigned int length
, i
;
5627 /* Find an ADDR_VEC insn to explode. */
5628 if (GET_CODE (insn
) != JUMP_INSN
5629 || GET_CODE (PATTERN (insn
)) != ADDR_VEC
)
5632 /* If needed, emit marker for the beginning of the branch table. */
5634 emit_insn_before (gen_begin_brtab (), insn
);
5636 pattern
= PATTERN (insn
);
5637 location
= PREV_INSN (insn
);
5638 length
= XVECLEN (pattern
, 0);
5640 for (i
= 0; i
< length
; i
++)
5642 /* Emit the jump itself. */
5643 tmp
= gen_switch_jump (XEXP (XVECEXP (pattern
, 0, i
), 0));
5644 tmp
= emit_jump_insn_after (tmp
, location
);
5645 JUMP_LABEL (tmp
) = XEXP (XVECEXP (pattern
, 0, i
), 0);
5646 LABEL_NUSES (JUMP_LABEL (tmp
))++;
5648 /* Emit a BARRIER after the jump. */
5649 location
= NEXT_INSN (location
);
5650 emit_barrier_after (location
);
5652 /* Put a CODE_LABEL before each so jump.c does not optimize
5654 location
= NEXT_INSN (location
);
5655 tmp
= gen_label_rtx ();
5656 LABEL_NUSES (tmp
) = 1;
5657 emit_label_after (tmp
, location
);
5658 location
= NEXT_INSN (location
);
5661 /* If needed, emit marker for the end of the branch table. */
5663 emit_insn_before (gen_end_brtab (), location
);
5664 /* Delete the ADDR_VEC. */
5668 else if (TARGET_GAS
)
5670 /* Sill need an end_brtab insn. */
5671 insns
= get_insns ();
5672 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
5674 /* Find an ADDR_VEC insn. */
5675 if (GET_CODE (insn
) != JUMP_INSN
5676 || GET_CODE (PATTERN (insn
)) != ADDR_VEC
)
5679 /* Now generate markers for the beginning and end of the
5681 emit_insn_before (gen_begin_brtab (), insn
);
5682 emit_insn_after (gen_end_brtab (), insn
);
5687 /* The PA has a number of odd instructions which can perform multiple
5688 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
5689 it may be profitable to combine two instructions into one instruction
5690 with two outputs. It's not profitable PA2.0 machines because the
5691 two outputs would take two slots in the reorder buffers.
5693 This routine finds instructions which can be combined and combines
5694 them. We only support some of the potential combinations, and we
5695 only try common ways to find suitable instructions.
5697 * addb can add two registers or a register and a small integer
5698 and jump to a nearby (+-8k) location. Normally the jump to the
5699 nearby location is conditional on the result of the add, but by
5700 using the "true" condition we can make the jump unconditional.
5701 Thus addb can perform two independent operations in one insn.
5703 * movb is similar to addb in that it can perform a reg->reg
5704 or small immediate->reg copy and jump to a nearby (+-8k location).
5706 * fmpyadd and fmpysub can perform a FP multiply and either an
5707 FP add or FP sub if the operands of the multiply and add/sub are
5708 independent (there are other minor restrictions). Note both
5709 the fmpy and fadd/fsub can in theory move to better spots according
5710 to data dependencies, but for now we require the fmpy stay at a
5713 * Many of the memory operations can perform pre & post updates
5714 of index registers. GCC's pre/post increment/decrement addressing
5715 is far too simple to take advantage of all the possibilities. This
5716 pass may not be suitable since those insns may not be independent.
5718 * comclr can compare two ints or an int and a register, nullify
5719 the following instruction and zero some other register. This
5720 is more difficult to use as it's harder to find an insn which
5721 will generate a comclr than finding something like an unconditional
5722 branch. (conditional moves & long branches create comclr insns).
5724 * Most arithmetic operations can conditionally skip the next
5725 instruction. They can be viewed as "perform this operation
5726 and conditionally jump to this nearby location" (where nearby
5727 is an insns away). These are difficult to use due to the
5728 branch length restrictions. */
5730 pa_combine_instructions (insns
)
5735 /* This can get expensive since the basic algorithm is on the
5736 order of O(n^2) (or worse). Only do it for -O2 or higher
5737 levels of optimizaton. */
5741 /* Walk down the list of insns looking for "anchor" insns which
5742 may be combined with "floating" insns. As the name implies,
5743 "anchor" instructions don't move, while "floating" insns may
5745 new = gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2, NULL_RTX
, NULL_RTX
));
5746 new = make_insn_raw (new);
5748 for (anchor
= get_insns (); anchor
; anchor
= NEXT_INSN (anchor
))
5750 enum attr_pa_combine_type anchor_attr
;
5751 enum attr_pa_combine_type floater_attr
;
5753 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
5754 Also ignore any special USE insns. */
5755 if (GET_CODE (anchor
) != INSN
5756 && GET_CODE (anchor
) != JUMP_INSN
5757 && GET_CODE (anchor
) != CALL_INSN
5758 || GET_CODE (PATTERN (anchor
)) == USE
5759 || GET_CODE (PATTERN (anchor
)) == CLOBBER
5760 || GET_CODE (PATTERN (anchor
)) == ADDR_VEC
5761 || GET_CODE (PATTERN (anchor
)) == ADDR_DIFF_VEC
)
5764 anchor_attr
= get_attr_pa_combine_type (anchor
);
5765 /* See if anchor is an insn suitable for combination. */
5766 if (anchor_attr
== PA_COMBINE_TYPE_FMPY
5767 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
5768 || (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
5769 && ! forward_branch_p (anchor
)))
5773 for (floater
= PREV_INSN (anchor
);
5775 floater
= PREV_INSN (floater
))
5777 if (GET_CODE (floater
) == NOTE
5778 || (GET_CODE (floater
) == INSN
5779 && (GET_CODE (PATTERN (floater
)) == USE
5780 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
5783 /* Anything except a regular INSN will stop our search. */
5784 if (GET_CODE (floater
) != INSN
5785 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
5786 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
5792 /* See if FLOATER is suitable for combination with the
5794 floater_attr
= get_attr_pa_combine_type (floater
);
5795 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
5796 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
5797 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
5798 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
5800 /* If ANCHOR and FLOATER can be combined, then we're
5801 done with this pass. */
5802 if (pa_can_combine_p (new, anchor
, floater
, 0,
5803 SET_DEST (PATTERN (floater
)),
5804 XEXP (SET_SRC (PATTERN (floater
)), 0),
5805 XEXP (SET_SRC (PATTERN (floater
)), 1)))
5809 else if (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
5810 && floater_attr
== PA_COMBINE_TYPE_ADDMOVE
)
5812 if (GET_CODE (SET_SRC (PATTERN (floater
))) == PLUS
)
5814 if (pa_can_combine_p (new, anchor
, floater
, 0,
5815 SET_DEST (PATTERN (floater
)),
5816 XEXP (SET_SRC (PATTERN (floater
)), 0),
5817 XEXP (SET_SRC (PATTERN (floater
)), 1)))
5822 if (pa_can_combine_p (new, anchor
, floater
, 0,
5823 SET_DEST (PATTERN (floater
)),
5824 SET_SRC (PATTERN (floater
)),
5825 SET_SRC (PATTERN (floater
))))
5831 /* If we didn't find anything on the backwards scan try forwards. */
5833 && (anchor_attr
== PA_COMBINE_TYPE_FMPY
5834 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
))
5836 for (floater
= anchor
; floater
; floater
= NEXT_INSN (floater
))
5838 if (GET_CODE (floater
) == NOTE
5839 || (GET_CODE (floater
) == INSN
5840 && (GET_CODE (PATTERN (floater
)) == USE
5841 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
5845 /* Anything except a regular INSN will stop our search. */
5846 if (GET_CODE (floater
) != INSN
5847 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
5848 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
5854 /* See if FLOATER is suitable for combination with the
5856 floater_attr
= get_attr_pa_combine_type (floater
);
5857 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
5858 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
5859 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
5860 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
5862 /* If ANCHOR and FLOATER can be combined, then we're
5863 done with this pass. */
5864 if (pa_can_combine_p (new, anchor
, floater
, 1,
5865 SET_DEST (PATTERN (floater
)),
5866 XEXP (SET_SRC (PATTERN(floater
)),0),
5867 XEXP(SET_SRC(PATTERN(floater
)),1)))
5873 /* FLOATER will be nonzero if we found a suitable floating
5874 insn for combination with ANCHOR. */
5876 && (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
5877 || anchor_attr
== PA_COMBINE_TYPE_FMPY
))
5879 /* Emit the new instruction and delete the old anchor. */
5880 emit_insn_before (gen_rtx (PARALLEL
, VOIDmode
,
5881 gen_rtvec (2, PATTERN (anchor
),
5882 PATTERN (floater
))),
5884 PUT_CODE (anchor
, NOTE
);
5885 NOTE_LINE_NUMBER (anchor
) = NOTE_INSN_DELETED
;
5886 NOTE_SOURCE_FILE (anchor
) = 0;
5888 /* Emit a special USE insn for FLOATER, then delete
5889 the floating insn. */
5890 emit_insn_before (gen_rtx (USE
, VOIDmode
, floater
), floater
);
5891 delete_insn (floater
);
5896 && anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
)
5899 /* Emit the new_jump instruction and delete the old anchor. */
5900 temp
= emit_jump_insn_before (gen_rtx (PARALLEL
, VOIDmode
,
5901 gen_rtvec (2, PATTERN (anchor
),
5902 PATTERN (floater
))),
5904 JUMP_LABEL (temp
) = JUMP_LABEL (anchor
);
5905 PUT_CODE (anchor
, NOTE
);
5906 NOTE_LINE_NUMBER (anchor
) = NOTE_INSN_DELETED
;
5907 NOTE_SOURCE_FILE (anchor
) = 0;
5909 /* Emit a special USE insn for FLOATER, then delete
5910 the floating insn. */
5911 emit_insn_before (gen_rtx (USE
, VOIDmode
, floater
), floater
);
5912 delete_insn (floater
);
5920 pa_can_combine_p (new, anchor
, floater
, reversed
, dest
, src1
, src2
)
5921 rtx
new, anchor
, floater
;
5923 rtx dest
, src1
, src2
;
5925 int insn_code_number
;
5928 /* Create a PARALLEL with the patterns of ANCHOR and
5929 FLOATER, try to recognize it, then test constraints
5930 for the resulting pattern.
5932 If the pattern doesn't match or the constraints
5933 aren't met keep searching for a suitable floater
5935 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor
);
5936 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater
);
5937 INSN_CODE (new) = -1;
5938 insn_code_number
= recog_memoized (new);
5939 if (insn_code_number
< 0
5940 || !constrain_operands (insn_code_number
, 1))
5954 /* There's up to three operands to consider. One
5955 output and two inputs.
5957 The output must not be used between FLOATER & ANCHOR
5958 exclusive. The inputs must not be set between
5959 FLOATER and ANCHOR exclusive. */
5961 if (reg_used_between_p (dest
, start
, end
))
5964 if (reg_set_between_p (src1
, start
, end
))
5967 if (reg_set_between_p (src2
, start
, end
))
5970 /* If we get here, then everything is good. */