1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
45 #ifndef DO_FRAME_NOTES
46 #ifdef INCOMING_RETURN_ADDR_RTX
47 #define DO_FRAME_NOTES 1
49 #define DO_FRAME_NOTES 0
53 static void pa_init_machine_status
PARAMS ((struct function
*));
54 static void pa_mark_machine_status
PARAMS ((struct function
*));
55 static void pa_free_machine_status
PARAMS ((struct function
*));
56 static void pa_combine_instructions
PARAMS ((rtx
));
57 static int pa_can_combine_p
PARAMS ((rtx
, rtx
, rtx
, int, rtx
, rtx
, rtx
));
58 static int forward_branch_p
PARAMS ((rtx
));
59 static int shadd_constant_p
PARAMS ((int));
60 static void pa_add_gc_roots
PARAMS ((void));
61 static void mark_deferred_plabels
PARAMS ((void *));
62 static void compute_zdepwi_operands
PARAMS ((unsigned HOST_WIDE_INT
, unsigned *));
63 static int compute_movstrsi_length
PARAMS ((rtx
));
64 static void remove_useless_addtr_insns
PARAMS ((rtx
, int));
65 static rtx store_reg
PARAMS ((int, int, int));
66 static rtx load_reg
PARAMS ((int, int, int));
67 static rtx set_reg_plus_d
PARAMS ((int, int, int));
69 /* Save the operands last given to a compare for use when we
70 generate a scc or bcc insn. */
72 rtx hppa_compare_op0
, hppa_compare_op1
;
73 enum cmp_type hppa_branch_type
;
75 /* Which cpu we are scheduling for. */
76 enum processor_type pa_cpu
;
78 /* String to hold which cpu we are scheduling for. */
79 const char *pa_cpu_string
;
81 /* Which architecture we are generating code for. */
82 enum architecture_type pa_arch
;
84 /* String to hold which architecture we are generating code for. */
85 const char *pa_arch_string
;
87 /* Counts for the number of callee-saved general and floating point
88 registers which were saved by the current function's prologue. */
89 static int gr_saved
, fr_saved
;
91 static rtx find_addr_reg
PARAMS ((rtx
));
93 /* Keep track of the number of bytes we have output in the CODE subspaces
94 during this compilation so we'll know when to emit inline long-calls. */
96 unsigned int total_code_bytes
;
98 /* Variables to handle plabels that we discover are necessary at assembly
99 output time. They are output after the current function. */
101 struct deferred_plabel
105 } *deferred_plabels
= 0;
106 int n_deferred_plabels
= 0;
111 /* Default to 7100LC scheduling. */
112 if (pa_cpu_string
&& ! strcmp (pa_cpu_string
, "7100"))
114 pa_cpu_string
= "7100";
115 pa_cpu
= PROCESSOR_7100
;
117 else if (pa_cpu_string
&& ! strcmp (pa_cpu_string
, "700"))
119 pa_cpu_string
= "700";
120 pa_cpu
= PROCESSOR_700
;
122 else if (pa_cpu_string
== NULL
123 || ! strcmp (pa_cpu_string
, "7100LC"))
125 pa_cpu_string
= "7100LC";
126 pa_cpu
= PROCESSOR_7100LC
;
128 else if (pa_cpu_string
&& ! strcmp (pa_cpu_string
, "7200"))
130 pa_cpu_string
= "7200";
131 pa_cpu
= PROCESSOR_7200
;
133 else if (pa_cpu_string
&& ! strcmp (pa_cpu_string
, "8000"))
135 pa_cpu_string
= "8000";
136 pa_cpu
= PROCESSOR_8000
;
140 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string
);
143 /* Set the instruction set architecture. */
144 if (pa_arch_string
&& ! strcmp (pa_arch_string
, "1.0"))
146 pa_arch_string
= "1.0";
147 pa_arch
= ARCHITECTURE_10
;
148 target_flags
&= ~(MASK_PA_11
| MASK_PA_20
);
150 else if (pa_arch_string
&& ! strcmp (pa_arch_string
, "1.1"))
152 pa_arch_string
= "1.1";
153 pa_arch
= ARCHITECTURE_11
;
154 target_flags
&= ~MASK_PA_20
;
155 target_flags
|= MASK_PA_11
;
157 else if (pa_arch_string
&& ! strcmp (pa_arch_string
, "2.0"))
159 pa_arch_string
= "2.0";
160 pa_arch
= ARCHITECTURE_20
;
161 target_flags
|= MASK_PA_11
| MASK_PA_20
;
163 else if (pa_arch_string
)
165 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string
);
168 if (flag_pic
&& TARGET_PORTABLE_RUNTIME
)
170 warning ("PIC code generation is not supported in the portable runtime model\n");
173 if (flag_pic
&& TARGET_FAST_INDIRECT_CALLS
)
175 warning ("PIC code generation is not compatible with fast indirect calls\n");
178 if (! TARGET_GAS
&& write_symbols
!= NO_DEBUG
)
180 warning ("-g is only supported when using GAS on this processor,");
181 warning ("-g option disabled.");
182 write_symbols
= NO_DEBUG
;
185 /* We only support the "big PIC" model now. And we always generate PIC
186 code when in 64bit mode. */
187 if (flag_pic
== 1 || TARGET_64BIT
)
190 /* Register global variables with the garbage collector. */
193 /* Arrange to save and restore machine status around nested functions. */
194 init_machine_status
= pa_init_machine_status
;
195 mark_machine_status
= pa_mark_machine_status
;
196 free_machine_status
= pa_free_machine_status
;
199 /* Functions to initialize pic_offset_table_save_rtx.
200 These will be called, via pointer variables,
201 from push_function_context and pop_function_context. */
204 pa_init_machine_status (p
)
207 p
->machine
= (machine_function
*) xmalloc (sizeof (machine_function
));
209 p
->machine
->pic_offset_table_save_rtx
= NULL_RTX
;
213 pa_mark_machine_status (p
)
217 ggc_mark_rtx (p
->machine
->pic_offset_table_save_rtx
);
221 pa_free_machine_status (p
)
224 if (p
->machine
== NULL
)
232 /* Return non-zero only if OP is a register of mode MODE,
235 reg_or_0_operand (op
, mode
)
237 enum machine_mode mode
;
239 return (op
== CONST0_RTX (mode
) || register_operand (op
, mode
));
242 /* Return non-zero if OP is suitable for use in a call to a named
245 For 2.5 try to eliminate either call_operand_address or
246 function_label_operand, they perform very similar functions. */
248 call_operand_address (op
, mode
)
250 enum machine_mode mode ATTRIBUTE_UNUSED
;
252 return (GET_MODE (op
) == word_mode
253 && CONSTANT_P (op
) && ! TARGET_PORTABLE_RUNTIME
);
256 /* Return 1 if X contains a symbolic expression. We know these
257 expressions will have one of a few well defined forms, so
258 we need only check those forms. */
260 symbolic_expression_p (x
)
264 /* Strip off any HIGH. */
265 if (GET_CODE (x
) == HIGH
)
268 return (symbolic_operand (x
, VOIDmode
));
272 symbolic_operand (op
, mode
)
274 enum machine_mode mode ATTRIBUTE_UNUSED
;
276 switch (GET_CODE (op
))
283 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
284 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
285 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
291 /* Return truth value of statement that OP is a symbolic memory
292 operand of mode MODE. */
295 symbolic_memory_operand (op
, mode
)
297 enum machine_mode mode ATTRIBUTE_UNUSED
;
299 if (GET_CODE (op
) == SUBREG
)
300 op
= SUBREG_REG (op
);
301 if (GET_CODE (op
) != MEM
)
304 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
305 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
308 /* Return 1 if the operand is either a register or a memory operand that is
312 reg_or_nonsymb_mem_operand (op
, mode
)
314 enum machine_mode mode
;
316 if (register_operand (op
, mode
))
319 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
325 /* Return 1 if the operand is either a register, zero, or a memory operand
326 that is not symbolic. */
329 reg_or_0_or_nonsymb_mem_operand (op
, mode
)
331 enum machine_mode mode
;
333 if (register_operand (op
, mode
))
336 if (op
== CONST0_RTX (mode
))
339 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
345 /* Accept any constant that can be moved in one instructions into a
348 cint_ok_for_move (intval
)
349 HOST_WIDE_INT intval
;
351 /* OK if ldo, ldil, or zdepi, can be used. */
352 return (CONST_OK_FOR_LETTER_P (intval
, 'J')
353 || CONST_OK_FOR_LETTER_P (intval
, 'N')
354 || CONST_OK_FOR_LETTER_P (intval
, 'K'));
357 /* Accept anything that can be moved in one instruction into a general
360 move_operand (op
, mode
)
362 enum machine_mode mode
;
364 if (register_operand (op
, mode
))
367 if (GET_CODE (op
) == CONSTANT_P_RTX
)
370 if (GET_CODE (op
) == CONST_INT
)
371 return cint_ok_for_move (INTVAL (op
));
373 if (GET_CODE (op
) == SUBREG
)
374 op
= SUBREG_REG (op
);
375 if (GET_CODE (op
) != MEM
)
380 /* We consider a LO_SUM DLT reference a move_operand now since it has
381 been merged into the normal movsi/movdi patterns. */
382 if (GET_CODE (op
) == LO_SUM
383 && GET_CODE (XEXP (op
, 0)) == REG
384 && REG_OK_FOR_BASE_P (XEXP (op
, 0))
385 && GET_CODE (XEXP (op
, 1)) == UNSPEC
386 && GET_MODE (op
) == Pmode
)
389 /* Since move_operand is only used for source operands, we can always
390 allow scaled indexing! */
391 if (! TARGET_DISABLE_INDEXING
392 && GET_CODE (op
) == PLUS
393 && ((GET_CODE (XEXP (op
, 0)) == MULT
394 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == REG
395 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
396 && INTVAL (XEXP (XEXP (op
, 0), 1)) == GET_MODE_SIZE (mode
)
397 && GET_CODE (XEXP (op
, 1)) == REG
)
398 || (GET_CODE (XEXP (op
, 1)) == MULT
399 &&GET_CODE (XEXP (XEXP (op
, 1), 0)) == REG
400 && GET_CODE (XEXP (XEXP (op
, 1), 1)) == CONST_INT
401 && INTVAL (XEXP (XEXP (op
, 1), 1)) == GET_MODE_SIZE (mode
)
402 && GET_CODE (XEXP (op
, 0)) == REG
)))
405 return memory_address_p (mode
, op
);
408 /* Accept REG and any CONST_INT that can be moved in one instruction into a
411 reg_or_cint_move_operand (op
, mode
)
413 enum machine_mode mode
;
415 if (register_operand (op
, mode
))
418 if (GET_CODE (op
) == CONST_INT
)
419 return cint_ok_for_move (INTVAL (op
));
425 pic_label_operand (op
, mode
)
427 enum machine_mode mode ATTRIBUTE_UNUSED
;
432 switch (GET_CODE (op
))
438 return (GET_CODE (XEXP (op
, 0)) == LABEL_REF
439 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
446 fp_reg_operand (op
, mode
)
448 enum machine_mode mode ATTRIBUTE_UNUSED
;
450 return reg_renumber
&& FP_REG_P (op
);
455 /* Return truth value of whether OP can be used as an operand in a
456 three operand arithmetic insn that accepts registers of mode MODE
457 or 14-bit signed integers. */
459 arith_operand (op
, mode
)
461 enum machine_mode mode
;
463 return (register_operand (op
, mode
)
464 || (GET_CODE (op
) == CONST_INT
&& INT_14_BITS (op
)));
467 /* Return truth value of whether OP can be used as an operand in a
468 three operand arithmetic insn that accepts registers of mode MODE
469 or 11-bit signed integers. */
471 arith11_operand (op
, mode
)
473 enum machine_mode mode
;
475 return (register_operand (op
, mode
)
476 || (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
)));
479 /* A constant integer suitable for use in a PRE_MODIFY memory
482 pre_cint_operand (op
, mode
)
484 enum machine_mode mode ATTRIBUTE_UNUSED
;
486 return (GET_CODE (op
) == CONST_INT
487 && INTVAL (op
) >= -0x2000 && INTVAL (op
) < 0x10);
490 /* A constant integer suitable for use in a POST_MODIFY memory
493 post_cint_operand (op
, mode
)
495 enum machine_mode mode ATTRIBUTE_UNUSED
;
497 return (GET_CODE (op
) == CONST_INT
498 && INTVAL (op
) < 0x2000 && INTVAL (op
) >= -0x10);
502 arith_double_operand (op
, mode
)
504 enum machine_mode mode
;
506 return (register_operand (op
, mode
)
507 || (GET_CODE (op
) == CONST_DOUBLE
508 && GET_MODE (op
) == mode
509 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op
))
510 && ((CONST_DOUBLE_HIGH (op
) >= 0)
511 == ((CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
514 /* Return truth value of whether OP is a integer which fits the
515 range constraining immediate operands in three-address insns, or
516 is an integer register. */
519 ireg_or_int5_operand (op
, mode
)
521 enum machine_mode mode ATTRIBUTE_UNUSED
;
523 return ((GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
))
524 || (GET_CODE (op
) == REG
&& REGNO (op
) > 0 && REGNO (op
) < 32));
527 /* Return nonzero if OP is an integer register, else return zero. */
529 ireg_operand (op
, mode
)
531 enum machine_mode mode ATTRIBUTE_UNUSED
;
533 return (GET_CODE (op
) == REG
&& REGNO (op
) > 0 && REGNO (op
) < 32);
536 /* Return truth value of whether OP is a integer which fits the
537 range constraining immediate operands in three-address insns. */
540 int5_operand (op
, mode
)
542 enum machine_mode mode ATTRIBUTE_UNUSED
;
544 return (GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
));
548 uint5_operand (op
, mode
)
550 enum machine_mode mode ATTRIBUTE_UNUSED
;
552 return (GET_CODE (op
) == CONST_INT
&& INT_U5_BITS (op
));
556 int11_operand (op
, mode
)
558 enum machine_mode mode ATTRIBUTE_UNUSED
;
560 return (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
));
564 uint32_operand (op
, mode
)
566 enum machine_mode mode ATTRIBUTE_UNUSED
;
568 #if HOST_BITS_PER_WIDE_INT > 32
569 /* All allowed constants will fit a CONST_INT. */
570 return (GET_CODE (op
) == CONST_INT
571 && (INTVAL (op
) >= 0 && INTVAL (op
) < (HOST_WIDE_INT
) 1 << 32));
573 return (GET_CODE (op
) == CONST_INT
574 || (GET_CODE (op
) == CONST_DOUBLE
575 && CONST_DOUBLE_HIGH (op
) == 0));
580 arith5_operand (op
, mode
)
582 enum machine_mode mode
;
584 return register_operand (op
, mode
) || int5_operand (op
, mode
);
587 /* True iff zdepi can be used to generate this CONST_INT. */
590 unsigned HOST_WIDE_INT x
;
592 unsigned HOST_WIDE_INT lsb_mask
, t
;
594 /* This might not be obvious, but it's at least fast.
595 This function is critical; we don't have the time loops would take. */
597 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
598 /* Return true iff t is a power of two. */
599 return ((t
& (t
- 1)) == 0);
602 /* True iff depi or extru can be used to compute (reg & mask).
603 Accept bit pattern like these:
609 unsigned HOST_WIDE_INT mask
;
612 mask
+= mask
& -mask
;
613 return (mask
& (mask
- 1)) == 0;
616 /* True iff depi or extru can be used to compute (reg & OP). */
618 and_operand (op
, mode
)
620 enum machine_mode mode
;
622 return (register_operand (op
, mode
)
623 || (GET_CODE (op
) == CONST_INT
&& and_mask_p (INTVAL (op
))));
626 /* True iff depi can be used to compute (reg | MASK). */
629 unsigned HOST_WIDE_INT mask
;
631 mask
+= mask
& -mask
;
632 return (mask
& (mask
- 1)) == 0;
635 /* True iff depi can be used to compute (reg | OP). */
637 ior_operand (op
, mode
)
639 enum machine_mode mode ATTRIBUTE_UNUSED
;
641 return (GET_CODE (op
) == CONST_INT
&& ior_mask_p (INTVAL (op
)));
645 lhs_lshift_operand (op
, mode
)
647 enum machine_mode mode
;
649 return register_operand (op
, mode
) || lhs_lshift_cint_operand (op
, mode
);
652 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
653 Such values can be the left hand side x in (x << r), using the zvdepi
656 lhs_lshift_cint_operand (op
, mode
)
658 enum machine_mode mode ATTRIBUTE_UNUSED
;
660 unsigned HOST_WIDE_INT x
;
661 if (GET_CODE (op
) != CONST_INT
)
663 x
= INTVAL (op
) >> 4;
664 return (x
& (x
+ 1)) == 0;
668 arith32_operand (op
, mode
)
670 enum machine_mode mode
;
672 return register_operand (op
, mode
) || GET_CODE (op
) == CONST_INT
;
676 pc_or_label_operand (op
, mode
)
678 enum machine_mode mode ATTRIBUTE_UNUSED
;
680 return (GET_CODE (op
) == PC
|| GET_CODE (op
) == LABEL_REF
);
683 /* Legitimize PIC addresses. If the address is already
684 position-independent, we return ORIG. Newly generated
685 position-independent addresses go to REG. If we need more
686 than one register, we lose. */
689 legitimize_pic_address (orig
, mode
, reg
)
691 enum machine_mode mode
;
695 /* Labels need special handling. */
696 if (pic_label_operand (orig
, mode
))
698 /* We do not want to go through the movXX expanders here since that
699 would create recursion.
701 Nor do we really want to call a generator for a named pattern
702 since that requires multiple patterns if we want to support
705 So instead we just emit the raw set, which avoids the movXX
706 expanders completely. */
707 emit_insn (gen_rtx_SET (VOIDmode
, reg
, orig
));
708 current_function_uses_pic_offset_table
= 1;
711 if (GET_CODE (orig
) == SYMBOL_REF
)
717 gen_rtx_PLUS (word_mode
, pic_offset_table_rtx
,
718 gen_rtx_HIGH (word_mode
, orig
)));
720 = gen_rtx_MEM (Pmode
,
721 gen_rtx_LO_SUM (Pmode
, reg
,
722 gen_rtx_UNSPEC (Pmode
,
726 current_function_uses_pic_offset_table
= 1;
727 RTX_UNCHANGING_P (pic_ref
) = 1;
728 emit_move_insn (reg
, pic_ref
);
731 else if (GET_CODE (orig
) == CONST
)
735 if (GET_CODE (XEXP (orig
, 0)) == PLUS
736 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
742 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
744 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
745 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
746 base
== reg
? 0 : reg
);
749 if (GET_CODE (orig
) == CONST_INT
)
751 if (INT_14_BITS (orig
))
752 return plus_constant_for_output (base
, INTVAL (orig
));
753 orig
= force_reg (Pmode
, orig
);
755 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
756 /* Likewise, should we set special REG_NOTEs here? */
761 /* Try machine-dependent ways of modifying an illegitimate address
762 to be legitimate. If we find one, return the new, valid address.
763 This macro is used in only one place: `memory_address' in explow.c.
765 OLDX is the address as it was before break_out_memory_refs was called.
766 In some cases it is useful to look at this to decide what needs to be done.
768 MODE and WIN are passed so that this macro can use
769 GO_IF_LEGITIMATE_ADDRESS.
771 It is always safe for this macro to do nothing. It exists to recognize
772 opportunities to optimize the output.
774 For the PA, transform:
776 memory(X + <large int>)
780 if (<large int> & mask) >= 16
781 Y = (<large int> & ~mask) + mask + 1 Round up.
783 Y = (<large int> & ~mask) Round down.
785 memory (Z + (<large int> - Y));
787 This is for CSE to find several similar references, and only use one Z.
789 X can either be a SYMBOL_REF or REG, but because combine can not
790 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
791 D will not fit in 14 bits.
793 MODE_FLOAT references allow displacements which fit in 5 bits, so use
796 MODE_INT references allow displacements which fit in 14 bits, so use
799 This relies on the fact that most mode MODE_FLOAT references will use FP
800 registers and most mode MODE_INT references will use integer registers.
801 (In the rare case of an FP register used in an integer MODE, we depend
802 on secondary reloads to clean things up.)
805 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
806 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
807 addressing modes to be used).
809 Put X and Z into registers. Then put the entire expression into
813 hppa_legitimize_address (x
, oldx
, mode
)
814 rtx x
, oldx ATTRIBUTE_UNUSED
;
815 enum machine_mode mode
;
820 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
822 /* Strip off CONST. */
823 if (GET_CODE (x
) == CONST
)
826 /* Special case. Get the SYMBOL_REF into a register and use indexing.
827 That should always be safe. */
828 if (GET_CODE (x
) == PLUS
829 && GET_CODE (XEXP (x
, 0)) == REG
830 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
832 rtx reg
= force_reg (Pmode
, XEXP (x
, 1));
833 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg
, XEXP (x
, 0)));
836 /* Note we must reject symbols which represent function addresses
837 since the assembler/linker can't handle arithmetic on plabels. */
838 if (GET_CODE (x
) == PLUS
839 && GET_CODE (XEXP (x
, 1)) == CONST_INT
840 && ((GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
841 && !FUNCTION_NAME_P (XSTR (XEXP (x
, 0), 0)))
842 || GET_CODE (XEXP (x
, 0)) == REG
))
844 rtx int_part
, ptr_reg
;
846 int offset
= INTVAL (XEXP (x
, 1));
849 mask
= (GET_MODE_CLASS (mode
) == MODE_FLOAT
850 ? (TARGET_PA_20
? 0x3fff : 0x1f) : 0x3fff);
852 /* Choose which way to round the offset. Round up if we
853 are >= halfway to the next boundary. */
854 if ((offset
& mask
) >= ((mask
+ 1) / 2))
855 newoffset
= (offset
& ~ mask
) + mask
+ 1;
857 newoffset
= (offset
& ~ mask
);
859 /* If the newoffset will not fit in 14 bits (ldo), then
860 handling this would take 4 or 5 instructions (2 to load
861 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
862 add the new offset and the SYMBOL_REF.) Combine can
863 not handle 4->2 or 5->2 combinations, so do not create
865 if (! VAL_14_BITS_P (newoffset
)
866 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
868 rtx const_part
= plus_constant (XEXP (x
, 0), newoffset
);
871 gen_rtx_HIGH (Pmode
, const_part
));
874 gen_rtx_LO_SUM (Pmode
,
875 tmp_reg
, const_part
));
879 if (! VAL_14_BITS_P (newoffset
))
880 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
882 int_part
= GEN_INT (newoffset
);
884 ptr_reg
= force_reg (Pmode
,
886 force_reg (Pmode
, XEXP (x
, 0)),
889 return plus_constant (ptr_reg
, offset
- newoffset
);
892 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
894 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
895 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
896 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1)))
897 && (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == 'o'
898 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
899 && GET_CODE (XEXP (x
, 1)) != CONST
)
901 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
905 if (GET_CODE (reg1
) != REG
)
906 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
908 reg2
= XEXP (XEXP (x
, 0), 0);
909 if (GET_CODE (reg2
) != REG
)
910 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
912 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
,
919 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
921 Only do so for floating point modes since this is more speculative
922 and we lose if it's an integer store. */
923 if (GET_CODE (x
) == PLUS
924 && GET_CODE (XEXP (x
, 0)) == PLUS
925 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
926 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
927 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
928 && (mode
== SFmode
|| mode
== DFmode
))
931 /* First, try and figure out what to use as a base register. */
932 rtx reg1
, reg2
, base
, idx
, orig_base
;
934 reg1
= XEXP (XEXP (x
, 0), 1);
939 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
940 then emit_move_sequence will turn on REG_POINTER so we'll know
941 it's a base register below. */
942 if (GET_CODE (reg1
) != REG
)
943 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
945 if (GET_CODE (reg2
) != REG
)
946 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
948 /* Figure out what the base and index are. */
950 if (GET_CODE (reg1
) == REG
951 && REG_POINTER (reg1
))
954 orig_base
= XEXP (XEXP (x
, 0), 1);
955 idx
= gen_rtx_PLUS (Pmode
,
957 XEXP (XEXP (XEXP (x
, 0), 0), 0),
958 XEXP (XEXP (XEXP (x
, 0), 0), 1)),
961 else if (GET_CODE (reg2
) == REG
962 && REG_POINTER (reg2
))
965 orig_base
= XEXP (x
, 1);
972 /* If the index adds a large constant, try to scale the
973 constant so that it can be loaded with only one insn. */
974 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
975 && VAL_14_BITS_P (INTVAL (XEXP (idx
, 1))
976 / INTVAL (XEXP (XEXP (idx
, 0), 1)))
977 && INTVAL (XEXP (idx
, 1)) % INTVAL (XEXP (XEXP (idx
, 0), 1)) == 0)
979 /* Divide the CONST_INT by the scale factor, then add it to A. */
980 int val
= INTVAL (XEXP (idx
, 1));
982 val
/= INTVAL (XEXP (XEXP (idx
, 0), 1));
983 reg1
= XEXP (XEXP (idx
, 0), 0);
984 if (GET_CODE (reg1
) != REG
)
985 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
987 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg1
, GEN_INT (val
)));
989 /* We can now generate a simple scaled indexed address. */
992 (Pmode
, gen_rtx_PLUS (Pmode
,
993 gen_rtx_MULT (Pmode
, reg1
,
994 XEXP (XEXP (idx
, 0), 1)),
998 /* If B + C is still a valid base register, then add them. */
999 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
1000 && INTVAL (XEXP (idx
, 1)) <= 4096
1001 && INTVAL (XEXP (idx
, 1)) >= -4096)
1003 int val
= INTVAL (XEXP (XEXP (idx
, 0), 1));
1006 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, XEXP (idx
, 1)));
1008 reg2
= XEXP (XEXP (idx
, 0), 0);
1009 if (GET_CODE (reg2
) != CONST_INT
)
1010 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1012 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
,
1013 gen_rtx_MULT (Pmode
,
1019 /* Get the index into a register, then add the base + index and
1020 return a register holding the result. */
1022 /* First get A into a register. */
1023 reg1
= XEXP (XEXP (idx
, 0), 0);
1024 if (GET_CODE (reg1
) != REG
)
1025 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1027 /* And get B into a register. */
1028 reg2
= XEXP (idx
, 1);
1029 if (GET_CODE (reg2
) != REG
)
1030 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1032 reg1
= force_reg (Pmode
,
1033 gen_rtx_PLUS (Pmode
,
1034 gen_rtx_MULT (Pmode
, reg1
,
1035 XEXP (XEXP (idx
, 0), 1)),
1038 /* Add the result to our base register and return. */
1039 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, reg1
));
1043 /* Uh-oh. We might have an address for x[n-100000]. This needs
1044 special handling to avoid creating an indexed memory address
1045 with x-100000 as the base.
1047 If the constant part is small enough, then it's still safe because
1048 there is a guard page at the beginning and end of the data segment.
1050 Scaled references are common enough that we want to try and rearrange the
1051 terms so that we can use indexing for these addresses too. Only
1052 do the optimization for floatint point modes. */
1054 if (GET_CODE (x
) == PLUS
1055 && symbolic_expression_p (XEXP (x
, 1)))
1057 /* Ugly. We modify things here so that the address offset specified
1058 by the index expression is computed first, then added to x to form
1059 the entire address. */
1061 rtx regx1
, regx2
, regy1
, regy2
, y
;
1063 /* Strip off any CONST. */
1065 if (GET_CODE (y
) == CONST
)
1068 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1070 /* See if this looks like
1071 (plus (mult (reg) (shadd_const))
1072 (const (plus (symbol_ref) (const_int))))
1074 Where const_int is small. In that case the const
1075 expression is a valid pointer for indexing.
1077 If const_int is big, but can be divided evenly by shadd_const
1078 and added to (reg). This allows more scaled indexed addresses. */
1079 if (GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1080 && GET_CODE (XEXP (x
, 0)) == MULT
1081 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1082 && INTVAL (XEXP (y
, 1)) >= -4096
1083 && INTVAL (XEXP (y
, 1)) <= 4095
1084 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1085 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
1087 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1091 if (GET_CODE (reg1
) != REG
)
1092 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1094 reg2
= XEXP (XEXP (x
, 0), 0);
1095 if (GET_CODE (reg2
) != REG
)
1096 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1098 return force_reg (Pmode
,
1099 gen_rtx_PLUS (Pmode
,
1100 gen_rtx_MULT (Pmode
,
1105 else if ((mode
== DFmode
|| mode
== SFmode
)
1106 && GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1107 && GET_CODE (XEXP (x
, 0)) == MULT
1108 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1109 && INTVAL (XEXP (y
, 1)) % INTVAL (XEXP (XEXP (x
, 0), 1)) == 0
1110 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1111 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
1114 = force_reg (Pmode
, GEN_INT (INTVAL (XEXP (y
, 1))
1115 / INTVAL (XEXP (XEXP (x
, 0), 1))));
1116 regx2
= XEXP (XEXP (x
, 0), 0);
1117 if (GET_CODE (regx2
) != REG
)
1118 regx2
= force_reg (Pmode
, force_operand (regx2
, 0));
1119 regx2
= force_reg (Pmode
, gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1123 gen_rtx_PLUS (Pmode
,
1124 gen_rtx_MULT (Pmode
, regx2
,
1125 XEXP (XEXP (x
, 0), 1)),
1126 force_reg (Pmode
, XEXP (y
, 0))));
1128 else if (GET_CODE (XEXP (y
, 1)) == CONST_INT
1129 && INTVAL (XEXP (y
, 1)) >= -4096
1130 && INTVAL (XEXP (y
, 1)) <= 4095)
1132 /* This is safe because of the guard page at the
1133 beginning and end of the data space. Just
1134 return the original address. */
1139 /* Doesn't look like one we can optimize. */
1140 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1141 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1142 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1143 regx1
= force_reg (Pmode
,
1144 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1146 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1154 /* For the HPPA, REG and REG+CONST is cost 0
1155 and addresses involving symbolic constants are cost 2.
1157 PIC addresses are very expensive.
1159 It is no coincidence that this has the same structure
1160 as GO_IF_LEGITIMATE_ADDRESS. */
1162 hppa_address_cost (X
)
1165 if (GET_CODE (X
) == PLUS
)
1167 else if (GET_CODE (X
) == LO_SUM
)
1169 else if (GET_CODE (X
) == HIGH
)
1174 /* Emit insns to move operands[1] into operands[0].
1176 Return 1 if we have written out everything that needs to be done to
1177 do the move. Otherwise, return 0 and the caller will emit the move
1180 Note SCRATCH_REG may not be in the proper mode depending on how it
1181 will be used. This routine is resposible for creating a new copy
1182 of SCRATCH_REG in the proper mode. */
1185 emit_move_sequence (operands
, mode
, scratch_reg
)
1187 enum machine_mode mode
;
1190 register rtx operand0
= operands
[0];
1191 register rtx operand1
= operands
[1];
1195 && reload_in_progress
&& GET_CODE (operand0
) == REG
1196 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1197 operand0
= reg_equiv_mem
[REGNO (operand0
)];
1198 else if (scratch_reg
1199 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
1200 && GET_CODE (SUBREG_REG (operand0
)) == REG
1201 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
1203 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1204 the code which tracks sets/uses for delete_output_reload. */
1205 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
1206 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
1207 SUBREG_BYTE (operand0
));
1208 operand0
= alter_subreg (temp
);
1212 && reload_in_progress
&& GET_CODE (operand1
) == REG
1213 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
1214 operand1
= reg_equiv_mem
[REGNO (operand1
)];
1215 else if (scratch_reg
1216 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
1217 && GET_CODE (SUBREG_REG (operand1
)) == REG
1218 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
1220 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1221 the code which tracks sets/uses for delete_output_reload. */
1222 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
1223 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
1224 SUBREG_BYTE (operand1
));
1225 operand1
= alter_subreg (temp
);
1228 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
1229 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
1230 != XEXP (operand0
, 0)))
1231 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
1232 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
1233 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
1234 != XEXP (operand1
, 0)))
1235 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
1237 /* Handle secondary reloads for loads/stores of FP registers from
1238 REG+D addresses where D does not fit in 5 bits, including
1239 (subreg (mem (addr))) cases. */
1240 if (fp_reg_operand (operand0
, mode
)
1241 && ((GET_CODE (operand1
) == MEM
1242 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
1243 || ((GET_CODE (operand1
) == SUBREG
1244 && GET_CODE (XEXP (operand1
, 0)) == MEM
1245 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
1248 if (GET_CODE (operand1
) == SUBREG
)
1249 operand1
= XEXP (operand1
, 0);
1251 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1252 it in WORD_MODE regardless of what mode it was originally given
1254 scratch_reg
= gen_rtx_REG (word_mode
, REGNO (scratch_reg
));
1256 /* D might not fit in 14 bits either; for such cases load D into
1258 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
1260 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1261 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
1263 XEXP (XEXP (operand1
, 0), 0),
1267 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
1268 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
1269 gen_rtx_MEM (mode
, scratch_reg
)));
1272 else if (fp_reg_operand (operand1
, mode
)
1273 && ((GET_CODE (operand0
) == MEM
1274 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
1275 || ((GET_CODE (operand0
) == SUBREG
)
1276 && GET_CODE (XEXP (operand0
, 0)) == MEM
1277 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
1280 if (GET_CODE (operand0
) == SUBREG
)
1281 operand0
= XEXP (operand0
, 0);
1283 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1284 it in WORD_MODE regardless of what mode it was originally given
1286 scratch_reg
= gen_rtx_REG (word_mode
, REGNO (scratch_reg
));
1288 /* D might not fit in 14 bits either; for such cases load D into
1290 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
1292 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
1293 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
1296 XEXP (XEXP (operand0
, 0),
1301 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
1302 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
1306 /* Handle secondary reloads for loads of FP registers from constant
1307 expressions by forcing the constant into memory.
1309 use scratch_reg to hold the address of the memory location.
1311 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1312 NO_REGS when presented with a const_int and an register class
1313 containing only FP registers. Doing so unfortunately creates
1314 more problems than it solves. Fix this for 2.5. */
1315 else if (fp_reg_operand (operand0
, mode
)
1316 && CONSTANT_P (operand1
)
1321 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1322 it in WORD_MODE regardless of what mode it was originally given
1324 scratch_reg
= gen_rtx_REG (word_mode
, REGNO (scratch_reg
));
1326 /* Force the constant into memory and put the address of the
1327 memory location into scratch_reg. */
1328 xoperands
[0] = scratch_reg
;
1329 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
1330 emit_move_sequence (xoperands
, Pmode
, 0);
1332 /* Now load the destination register. */
1333 emit_insn (gen_rtx_SET (mode
, operand0
,
1334 gen_rtx_MEM (mode
, scratch_reg
)));
1337 /* Handle secondary reloads for SAR. These occur when trying to load
1338 the SAR from memory, FP register, or with a constant. */
1339 else if (GET_CODE (operand0
) == REG
1340 && REGNO (operand0
) < FIRST_PSEUDO_REGISTER
1341 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
1342 && (GET_CODE (operand1
) == MEM
1343 || GET_CODE (operand1
) == CONST_INT
1344 || (GET_CODE (operand1
) == REG
1345 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1
)))))
1348 /* D might not fit in 14 bits either; for such cases load D into
1350 if (GET_CODE (operand1
) == MEM
1351 && !memory_address_p (Pmode
, XEXP (operand1
, 0)))
1353 /* We are reloading the address into the scratch register, so we
1354 want to make sure the scratch register is a full register. */
1355 scratch_reg
= gen_rtx_REG (word_mode
, REGNO (scratch_reg
));
1357 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1358 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
,
1361 XEXP (XEXP (operand1
, 0),
1365 /* Now we are going to load the scratch register from memory,
1366 we want to load it in the same width as the original MEM,
1367 which must be the same as the width of the ultimate destination,
1369 scratch_reg
= gen_rtx_REG (GET_MODE (operand0
), REGNO (scratch_reg
));
1371 emit_move_insn (scratch_reg
, gen_rtx_MEM (GET_MODE (operand0
),
1376 /* We want to load the scratch register using the same mode as
1377 the ultimate destination. */
1378 scratch_reg
= gen_rtx_REG (GET_MODE (operand0
), REGNO (scratch_reg
));
1379 emit_move_insn (scratch_reg
, operand1
);
1382 /* And emit the insn to set the ultimate destination. We know that
1383 the scratch register has the same mode as the destination at this
1385 emit_move_insn (operand0
, scratch_reg
);
1388 /* Handle most common case: storing into a register. */
1389 else if (register_operand (operand0
, mode
))
1391 if (register_operand (operand1
, mode
)
1392 || (GET_CODE (operand1
) == CONST_INT
&& INT_14_BITS (operand1
))
1393 || (operand1
== CONST0_RTX (mode
))
1394 || (GET_CODE (operand1
) == HIGH
1395 && !symbolic_operand (XEXP (operand1
, 0), VOIDmode
))
1396 /* Only `general_operands' can come here, so MEM is ok. */
1397 || GET_CODE (operand1
) == MEM
)
1399 /* Run this case quickly. */
1400 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operand1
));
1404 else if (GET_CODE (operand0
) == MEM
)
1406 if (mode
== DFmode
&& operand1
== CONST0_RTX (mode
)
1407 && !(reload_in_progress
|| reload_completed
))
1409 rtx temp
= gen_reg_rtx (DFmode
);
1411 emit_insn (gen_rtx_SET (VOIDmode
, temp
, operand1
));
1412 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, temp
));
1415 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
1417 /* Run this case quickly. */
1418 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operand1
));
1421 if (! (reload_in_progress
|| reload_completed
))
1423 operands
[0] = validize_mem (operand0
);
1424 operands
[1] = operand1
= force_reg (mode
, operand1
);
1428 /* Simplify the source if we need to.
1429 Note we do have to handle function labels here, even though we do
1430 not consider them legitimate constants. Loop optimizations can
1431 call the emit_move_xxx with one as a source. */
1432 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1433 || function_label_operand (operand1
, mode
)
1434 || (GET_CODE (operand1
) == HIGH
1435 && symbolic_operand (XEXP (operand1
, 0), mode
)))
1439 if (GET_CODE (operand1
) == HIGH
)
1442 operand1
= XEXP (operand1
, 0);
1444 if (symbolic_operand (operand1
, mode
))
1446 /* Argh. The assembler and linker can't handle arithmetic
1449 So we force the plabel into memory, load operand0 from
1450 the memory location, then add in the constant part. */
1451 if ((GET_CODE (operand1
) == CONST
1452 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1453 && function_label_operand (XEXP (XEXP (operand1
, 0), 0), Pmode
))
1454 || function_label_operand (operand1
, mode
))
1456 rtx temp
, const_part
;
1458 /* Figure out what (if any) scratch register to use. */
1459 if (reload_in_progress
|| reload_completed
)
1461 scratch_reg
= scratch_reg
? scratch_reg
: operand0
;
1462 /* SCRATCH_REG will hold an address and maybe the actual
1463 data. We want it in WORD_MODE regardless of what mode it
1464 was originally given to us. */
1465 scratch_reg
= gen_rtx_REG (word_mode
, REGNO (scratch_reg
));
1468 scratch_reg
= gen_reg_rtx (Pmode
);
1470 if (GET_CODE (operand1
) == CONST
)
1472 /* Save away the constant part of the expression. */
1473 const_part
= XEXP (XEXP (operand1
, 0), 1);
1474 if (GET_CODE (const_part
) != CONST_INT
)
1477 /* Force the function label into memory. */
1478 temp
= force_const_mem (mode
, XEXP (XEXP (operand1
, 0), 0));
1482 /* No constant part. */
1483 const_part
= NULL_RTX
;
1485 /* Force the function label into memory. */
1486 temp
= force_const_mem (mode
, operand1
);
1490 /* Get the address of the memory location. PIC-ify it if
1492 temp
= XEXP (temp
, 0);
1494 temp
= legitimize_pic_address (temp
, mode
, scratch_reg
);
1496 /* Put the address of the memory location into our destination
1499 emit_move_sequence (operands
, mode
, scratch_reg
);
1501 /* Now load from the memory location into our destination
1503 operands
[1] = gen_rtx_MEM (Pmode
, operands
[0]);
1504 emit_move_sequence (operands
, mode
, scratch_reg
);
1506 /* And add back in the constant part. */
1507 if (const_part
!= NULL_RTX
)
1508 expand_inc (operand0
, const_part
);
1517 if (reload_in_progress
|| reload_completed
)
1519 temp
= scratch_reg
? scratch_reg
: operand0
;
1520 /* TEMP will hold an address and maybe the actual
1521 data. We want it in WORD_MODE regardless of what mode it
1522 was originally given to us. */
1523 temp
= gen_rtx_REG (word_mode
, REGNO (temp
));
1526 temp
= gen_reg_rtx (Pmode
);
1528 /* (const (plus (symbol) (const_int))) must be forced to
1529 memory during/after reload if the const_int will not fit
1531 if (GET_CODE (operand1
) == CONST
1532 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1533 && GET_CODE (XEXP (XEXP (operand1
, 0), 1)) == CONST_INT
1534 && !INT_14_BITS (XEXP (XEXP (operand1
, 0), 1))
1535 && (reload_completed
|| reload_in_progress
)
1538 operands
[1] = force_const_mem (mode
, operand1
);
1539 operands
[1] = legitimize_pic_address (XEXP (operands
[1], 0),
1541 emit_move_sequence (operands
, mode
, temp
);
1545 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
1546 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operands
[1]));
1549 /* On the HPPA, references to data space are supposed to use dp,
1550 register 27, but showing it in the RTL inhibits various cse
1551 and loop optimizations. */
1556 if (reload_in_progress
|| reload_completed
)
1558 temp
= scratch_reg
? scratch_reg
: operand0
;
1559 /* TEMP will hold an address and maybe the actual
1560 data. We want it in WORD_MODE regardless of what mode it
1561 was originally given to us. */
1562 temp
= gen_rtx_REG (word_mode
, REGNO (temp
));
1565 temp
= gen_reg_rtx (mode
);
1567 /* Loading a SYMBOL_REF into a register makes that register
1568 safe to be used as the base in an indexed address.
1570 Don't mark hard registers though. That loses. */
1571 if (GET_CODE (operand0
) == REG
1572 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1573 REG_POINTER (operand0
) = 1;
1574 if (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
)
1575 REG_POINTER (temp
) = 1;
1577 set
= gen_rtx_SET (mode
, operand0
, temp
);
1579 set
= gen_rtx_SET (VOIDmode
,
1581 gen_rtx_LO_SUM (mode
, temp
, operand1
));
1583 emit_insn (gen_rtx_SET (VOIDmode
,
1585 gen_rtx_HIGH (mode
, operand1
)));
1591 else if (GET_CODE (operand1
) != CONST_INT
1592 || ! cint_ok_for_move (INTVAL (operand1
)))
1595 int need_zero_extend
= 0;
1597 if (TARGET_64BIT
&& GET_CODE (operand1
) == CONST_INT
1598 && HOST_BITS_PER_WIDE_INT
> 32
1599 && GET_MODE_BITSIZE (GET_MODE (operand0
)) > 32)
1601 HOST_WIDE_INT val
= INTVAL (operand1
);
1604 /* If the value is the same after a 32->64bit sign
1605 extension, then we can use it as-is. Else we will
1606 need to sign extend the constant from 32->64bits
1607 then zero extend the result from 32->64bits. */
1608 nval
= ((val
& (((HOST_WIDE_INT
) 2 << 31) - 1))
1609 ^ ((HOST_WIDE_INT
) 1 << 31)) - ((HOST_WIDE_INT
) 1 << 31);
1612 need_zero_extend
= 1;
1613 operand1
= GEN_INT (nval
);
1617 if (reload_in_progress
|| reload_completed
)
1620 temp
= gen_reg_rtx (mode
);
1622 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1623 gen_rtx_HIGH (mode
, operand1
)));
1624 operands
[1] = gen_rtx_LO_SUM (mode
, temp
, operand1
);
1625 emit_move_insn (operands
[0], operands
[1]);
1627 if (need_zero_extend
)
1629 emit_insn (gen_zero_extendsidi2 (operands
[0],
1630 gen_rtx_SUBREG (SImode
,
1638 /* Now have insn-emit do whatever it normally does. */
1642 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1643 it will need a link/runtime reloc). */
1651 switch (TREE_CODE (exp
))
1658 reloc
= reloc_needed (TREE_OPERAND (exp
, 0));
1659 reloc
|= reloc_needed (TREE_OPERAND (exp
, 1));
1664 case NON_LVALUE_EXPR
:
1665 reloc
= reloc_needed (TREE_OPERAND (exp
, 0));
1671 for (link
= CONSTRUCTOR_ELTS (exp
); link
; link
= TREE_CHAIN (link
))
1672 if (TREE_VALUE (link
) != 0)
1673 reloc
|= reloc_needed (TREE_VALUE (link
));
1686 /* Does operand (which is a symbolic_operand) live in text space? If
1687 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1690 read_only_operand (operand
, mode
)
1692 enum machine_mode mode ATTRIBUTE_UNUSED
;
1694 if (GET_CODE (operand
) == CONST
)
1695 operand
= XEXP (XEXP (operand
, 0), 0);
1698 if (GET_CODE (operand
) == SYMBOL_REF
)
1699 return SYMBOL_REF_FLAG (operand
) && !CONSTANT_POOL_ADDRESS_P (operand
);
1703 if (GET_CODE (operand
) == SYMBOL_REF
)
1704 return SYMBOL_REF_FLAG (operand
) || CONSTANT_POOL_ADDRESS_P (operand
);
1710 /* Return the best assembler insn template
1711 for moving operands[1] into operands[0] as a fullword. */
1713 singlemove_string (operands
)
1716 HOST_WIDE_INT intval
;
1718 if (GET_CODE (operands
[0]) == MEM
)
1719 return "stw %r1,%0";
1720 if (GET_CODE (operands
[1]) == MEM
)
1722 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1727 if (GET_MODE (operands
[1]) != SFmode
)
1730 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1732 REAL_VALUE_FROM_CONST_DOUBLE (d
, operands
[1]);
1733 REAL_VALUE_TO_TARGET_SINGLE (d
, i
);
1735 operands
[1] = GEN_INT (i
);
1736 /* Fall through to CONST_INT case. */
1738 if (GET_CODE (operands
[1]) == CONST_INT
)
1740 intval
= INTVAL (operands
[1]);
1742 if (VAL_14_BITS_P (intval
))
1744 else if ((intval
& 0x7ff) == 0)
1745 return "ldil L'%1,%0";
1746 else if (zdepi_cint_p (intval
))
1747 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1749 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1751 return "copy %1,%0";
1755 /* Compute position (in OP[1]) and width (in OP[2])
1756 useful for copying IMM to a register using the zdepi
1757 instructions. Store the immediate value to insert in OP[0]. */
1759 compute_zdepwi_operands (imm
, op
)
1760 unsigned HOST_WIDE_INT imm
;
1765 /* Find the least significant set bit in IMM. */
1766 for (lsb
= 0; lsb
< 32; lsb
++)
1773 /* Choose variants based on *sign* of the 5-bit field. */
1774 if ((imm
& 0x10) == 0)
1775 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
1778 /* Find the width of the bitstring in IMM. */
1779 for (len
= 5; len
< 32; len
++)
1781 if ((imm
& (1 << len
)) == 0)
1785 /* Sign extend IMM as a 5-bit value. */
1786 imm
= (imm
& 0xf) - 0x10;
1794 /* Compute position (in OP[1]) and width (in OP[2])
1795 useful for copying IMM to a register using the depdi,z
1796 instructions. Store the immediate value to insert in OP[0]. */
1798 compute_zdepdi_operands (imm
, op
)
1799 unsigned HOST_WIDE_INT imm
;
1802 HOST_WIDE_INT lsb
, len
;
1804 /* Find the least significant set bit in IMM. */
1805 for (lsb
= 0; lsb
< HOST_BITS_PER_WIDE_INT
; lsb
++)
1812 /* Choose variants based on *sign* of the 5-bit field. */
1813 if ((imm
& 0x10) == 0)
1814 len
= ((lsb
<= HOST_BITS_PER_WIDE_INT
- 4)
1815 ? 4 : HOST_BITS_PER_WIDE_INT
- lsb
);
1818 /* Find the width of the bitstring in IMM. */
1819 for (len
= 5; len
< HOST_BITS_PER_WIDE_INT
; len
++)
1821 if ((imm
& ((unsigned HOST_WIDE_INT
)1 << len
)) == 0)
1825 /* Sign extend IMM as a 5-bit value. */
1826 imm
= (imm
& 0xf) - 0x10;
1834 /* Output assembler code to perform a doubleword move insn
1835 with operands OPERANDS. */
1838 output_move_double (operands
)
1841 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
1843 rtx addreg0
= 0, addreg1
= 0;
1845 /* First classify both operands. */
1847 if (REG_P (operands
[0]))
1849 else if (offsettable_memref_p (operands
[0]))
1851 else if (GET_CODE (operands
[0]) == MEM
)
1856 if (REG_P (operands
[1]))
1858 else if (CONSTANT_P (operands
[1]))
1860 else if (offsettable_memref_p (operands
[1]))
1862 else if (GET_CODE (operands
[1]) == MEM
)
1867 /* Check for the cases that the operand constraints are not
1868 supposed to allow to happen. Abort if we get one,
1869 because generating code for these cases is painful. */
1871 if (optype0
!= REGOP
&& optype1
!= REGOP
)
1874 /* Handle auto decrementing and incrementing loads and stores
1875 specifically, since the structure of the function doesn't work
1876 for them without major modification. Do it better when we learn
1877 this port about the general inc/dec addressing of PA.
1878 (This was written by tege. Chide him if it doesn't work.) */
1880 if (optype0
== MEMOP
)
1882 /* We have to output the address syntax ourselves, since print_operand
1883 doesn't deal with the addresses we want to use. Fix this later. */
1885 rtx addr
= XEXP (operands
[0], 0);
1886 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1888 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
1890 operands
[0] = XEXP (addr
, 0);
1891 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1894 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1896 /* No overlap between high target register and address
1897 register. (We do this in a non-obvious way to
1898 save a register file writeback) */
1899 if (GET_CODE (addr
) == POST_INC
)
1900 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
1901 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
1906 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1908 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
1910 operands
[0] = XEXP (addr
, 0);
1911 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1914 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1916 /* No overlap between high target register and address
1917 register. (We do this in a non-obvious way to
1918 save a register file writeback) */
1919 if (GET_CODE (addr
) == PRE_INC
)
1920 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
1921 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
1927 if (optype1
== MEMOP
)
1929 /* We have to output the address syntax ourselves, since print_operand
1930 doesn't deal with the addresses we want to use. Fix this later. */
1932 rtx addr
= XEXP (operands
[1], 0);
1933 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1935 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
1937 operands
[1] = XEXP (addr
, 0);
1938 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1941 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1943 /* No overlap between high target register and address
1944 register. (We do this in a non-obvious way to
1945 save a register file writeback) */
1946 if (GET_CODE (addr
) == POST_INC
)
1947 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
1948 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0}";
1952 /* This is an undefined situation. We should load into the
1953 address register *and* update that register. Probably
1954 we don't need to handle this at all. */
1955 if (GET_CODE (addr
) == POST_INC
)
1956 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
1957 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
1960 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1962 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
1964 operands
[1] = XEXP (addr
, 0);
1965 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1968 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1970 /* No overlap between high target register and address
1971 register. (We do this in a non-obvious way to
1972 save a register file writeback) */
1973 if (GET_CODE (addr
) == PRE_INC
)
1974 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
1975 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
1979 /* This is an undefined situation. We should load into the
1980 address register *and* update that register. Probably
1981 we don't need to handle this at all. */
1982 if (GET_CODE (addr
) == PRE_INC
)
1983 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
1984 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
1987 else if (GET_CODE (addr
) == PLUS
1988 && GET_CODE (XEXP (addr
, 0)) == MULT
)
1990 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
1992 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1996 xoperands
[0] = high_reg
;
1997 xoperands
[1] = XEXP (addr
, 1);
1998 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
1999 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
2000 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2002 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2008 xoperands
[0] = high_reg
;
2009 xoperands
[1] = XEXP (addr
, 1);
2010 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
2011 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
2012 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2014 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2019 /* If an operand is an unoffsettable memory ref, find a register
2020 we can increment temporarily to make it refer to the second word. */
2022 if (optype0
== MEMOP
)
2023 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2025 if (optype1
== MEMOP
)
2026 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2028 /* Ok, we can do one word at a time.
2029 Normally we do the low-numbered word first.
2031 In either case, set up in LATEHALF the operands to use
2032 for the high-numbered word and in some cases alter the
2033 operands in OPERANDS to be suitable for the low-numbered word. */
2035 if (optype0
== REGOP
)
2036 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2037 else if (optype0
== OFFSOP
)
2038 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
2040 latehalf
[0] = operands
[0];
2042 if (optype1
== REGOP
)
2043 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2044 else if (optype1
== OFFSOP
)
2045 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
2046 else if (optype1
== CNSTOP
)
2047 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2049 latehalf
[1] = operands
[1];
2051 /* If the first move would clobber the source of the second one,
2052 do them in the other order.
2054 This can happen in two cases:
2056 mem -> register where the first half of the destination register
2057 is the same register used in the memory's address. Reload
2058 can create such insns.
2060 mem in this case will be either register indirect or register
2061 indirect plus a valid offset.
2063 register -> register move where REGNO(dst) == REGNO(src + 1)
2064 someone (Tim/Tege?) claimed this can happen for parameter loads.
2066 Handle mem -> register case first. */
2067 if (optype0
== REGOP
2068 && (optype1
== MEMOP
|| optype1
== OFFSOP
)
2069 && refers_to_regno_p (REGNO (operands
[0]), REGNO (operands
[0]) + 1,
2072 /* Do the late half first. */
2074 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2075 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2079 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2080 return singlemove_string (operands
);
2083 /* Now handle register -> register case. */
2084 if (optype0
== REGOP
&& optype1
== REGOP
2085 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
2087 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2088 return singlemove_string (operands
);
2091 /* Normal case: do the two words, low-numbered first. */
2093 output_asm_insn (singlemove_string (operands
), operands
);
2095 /* Make any unoffsettable addresses point at high-numbered word. */
2097 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
2099 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2102 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2104 /* Undo the adds we just did. */
2106 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
2108 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2114 output_fp_move_double (operands
)
2117 if (FP_REG_P (operands
[0]))
2119 if (FP_REG_P (operands
[1])
2120 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
2121 output_asm_insn ("fcpy,dbl %f1,%0", operands
);
2123 output_asm_insn ("fldd%F1 %1,%0", operands
);
2125 else if (FP_REG_P (operands
[1]))
2127 output_asm_insn ("fstd%F0 %1,%0", operands
);
2129 else if (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
2131 if (GET_CODE (operands
[0]) == REG
)
2134 xoperands
[1] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2135 xoperands
[0] = operands
[0];
2136 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
2138 /* This is a pain. You have to be prepared to deal with an
2139 arbitrary address here including pre/post increment/decrement.
2141 so avoid this in the MD. */
2149 /* Return a REG that occurs in ADDR with coefficient 1.
2150 ADDR can be effectively incremented by incrementing REG. */
2153 find_addr_reg (addr
)
2156 while (GET_CODE (addr
) == PLUS
)
2158 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2159 addr
= XEXP (addr
, 0);
2160 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2161 addr
= XEXP (addr
, 1);
2162 else if (CONSTANT_P (XEXP (addr
, 0)))
2163 addr
= XEXP (addr
, 1);
2164 else if (CONSTANT_P (XEXP (addr
, 1)))
2165 addr
= XEXP (addr
, 0);
2169 if (GET_CODE (addr
) == REG
)
2174 /* Emit code to perform a block move.
2176 OPERANDS[0] is the destination pointer as a REG, clobbered.
2177 OPERANDS[1] is the source pointer as a REG, clobbered.
2178 OPERANDS[2] is a register for temporary storage.
2179 OPERANDS[4] is the size as a CONST_INT
2180 OPERANDS[3] is a register for temporary storage.
2181 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2182 OPERANDS[6] is another temporary register. */
2185 output_block_move (operands
, size_is_constant
)
2187 int size_is_constant ATTRIBUTE_UNUSED
;
2189 int align
= INTVAL (operands
[5]);
2190 unsigned long n_bytes
= INTVAL (operands
[4]);
2192 /* We can't move more than four bytes at a time because the PA
2193 has no longer integer move insns. (Could use fp mem ops?) */
2197 /* Note that we know each loop below will execute at least twice
2198 (else we would have open-coded the copy). */
2202 /* Pre-adjust the loop counter. */
2203 operands
[4] = GEN_INT (n_bytes
- 8);
2204 output_asm_insn ("ldi %4,%2", operands
);
2207 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2208 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands
);
2209 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2210 output_asm_insn ("addib,>= -8,%2,.-12", operands
);
2211 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands
);
2213 /* Handle the residual. There could be up to 7 bytes of
2214 residual to copy! */
2215 if (n_bytes
% 8 != 0)
2217 operands
[4] = GEN_INT (n_bytes
% 4);
2218 if (n_bytes
% 8 >= 4)
2219 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2220 if (n_bytes
% 4 != 0)
2221 output_asm_insn ("ldw 0(%1),%6", operands
);
2222 if (n_bytes
% 8 >= 4)
2223 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2224 if (n_bytes
% 4 != 0)
2225 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands
);
2230 /* Pre-adjust the loop counter. */
2231 operands
[4] = GEN_INT (n_bytes
- 4);
2232 output_asm_insn ("ldi %4,%2", operands
);
2235 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2236 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands
);
2237 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2238 output_asm_insn ("addib,>= -4,%2,.-12", operands
);
2239 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands
);
2241 /* Handle the residual. */
2242 if (n_bytes
% 4 != 0)
2244 if (n_bytes
% 4 >= 2)
2245 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2246 if (n_bytes
% 2 != 0)
2247 output_asm_insn ("ldb 0(%1),%6", operands
);
2248 if (n_bytes
% 4 >= 2)
2249 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2250 if (n_bytes
% 2 != 0)
2251 output_asm_insn ("stb %6,0(%0)", operands
);
2256 /* Pre-adjust the loop counter. */
2257 operands
[4] = GEN_INT (n_bytes
- 2);
2258 output_asm_insn ("ldi %4,%2", operands
);
2261 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands
);
2262 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands
);
2263 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands
);
2264 output_asm_insn ("addib,>= -2,%2,.-12", operands
);
2265 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands
);
2267 /* Handle the residual. */
2268 if (n_bytes
% 2 != 0)
2270 output_asm_insn ("ldb 0(%1),%3", operands
);
2271 output_asm_insn ("stb %3,0(%0)", operands
);
2280 /* Count the number of insns necessary to handle this block move.
2282 Basic structure is the same as emit_block_move, except that we
2283 count insns rather than emit them. */
2286 compute_movstrsi_length (insn
)
2289 rtx pat
= PATTERN (insn
);
2290 unsigned int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
2291 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 5), 0));
2292 unsigned int n_insns
= 0;
2294 /* We can't move more than four bytes at a time because the PA
2295 has no longer integer move insns. (Could use fp mem ops?) */
2299 /* The basic copying loop. */
2303 if (n_bytes
% (2 * align
) != 0)
2305 if ((n_bytes
% (2 * align
)) >= align
)
2308 if ((n_bytes
% align
) != 0)
2312 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2318 output_and (operands
)
2321 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
2323 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
2324 int ls0
, ls1
, ms0
, p
, len
;
2326 for (ls0
= 0; ls0
< 32; ls0
++)
2327 if ((mask
& (1 << ls0
)) == 0)
2330 for (ls1
= ls0
; ls1
< 32; ls1
++)
2331 if ((mask
& (1 << ls1
)) != 0)
2334 for (ms0
= ls1
; ms0
< 32; ms0
++)
2335 if ((mask
& (1 << ms0
)) == 0)
2348 operands
[2] = GEN_INT (len
);
2349 return "{extru|extrw,u} %1,31,%2,%0";
2353 /* We could use this `depi' for the case above as well, but `depi'
2354 requires one more register file access than an `extru'. */
2359 operands
[2] = GEN_INT (p
);
2360 operands
[3] = GEN_INT (len
);
2361 return "{depi|depwi} 0,%2,%3,%0";
2365 return "and %1,%2,%0";
2368 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2369 storing the result in operands[0]. */
2371 output_64bit_and (operands
)
2374 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
2376 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
2377 int ls0
, ls1
, ms0
, p
, len
;
2379 for (ls0
= 0; ls0
< HOST_BITS_PER_WIDE_INT
; ls0
++)
2380 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls0
)) == 0)
2383 for (ls1
= ls0
; ls1
< HOST_BITS_PER_WIDE_INT
; ls1
++)
2384 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls1
)) != 0)
2387 for (ms0
= ls1
; ms0
< HOST_BITS_PER_WIDE_INT
; ms0
++)
2388 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ms0
)) == 0)
2391 if (ms0
!= HOST_BITS_PER_WIDE_INT
)
2394 if (ls1
== HOST_BITS_PER_WIDE_INT
)
2401 operands
[2] = GEN_INT (len
);
2402 return "extrd,u %1,63,%2,%0";
2406 /* We could use this `depi' for the case above as well, but `depi'
2407 requires one more register file access than an `extru'. */
2412 operands
[2] = GEN_INT (p
);
2413 operands
[3] = GEN_INT (len
);
2414 return "depdi 0,%2,%3,%0";
2418 return "and %1,%2,%0";
2422 output_ior (operands
)
2425 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
2426 int bs0
, bs1
, p
, len
;
2428 if (INTVAL (operands
[2]) == 0)
2429 return "copy %1,%0";
2431 for (bs0
= 0; bs0
< 32; bs0
++)
2432 if ((mask
& (1 << bs0
)) != 0)
2435 for (bs1
= bs0
; bs1
< 32; bs1
++)
2436 if ((mask
& (1 << bs1
)) == 0)
2439 if (bs1
!= 32 && ((unsigned HOST_WIDE_INT
) 1 << bs1
) <= mask
)
2445 operands
[2] = GEN_INT (p
);
2446 operands
[3] = GEN_INT (len
);
2447 return "{depi|depwi} -1,%2,%3,%0";
2450 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2451 storing the result in operands[0]. */
2453 output_64bit_ior (operands
)
2456 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
2457 int bs0
, bs1
, p
, len
;
2459 if (INTVAL (operands
[2]) == 0)
2460 return "copy %1,%0";
2462 for (bs0
= 0; bs0
< HOST_BITS_PER_WIDE_INT
; bs0
++)
2463 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs0
)) != 0)
2466 for (bs1
= bs0
; bs1
< HOST_BITS_PER_WIDE_INT
; bs1
++)
2467 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs1
)) == 0)
2470 if (bs1
!= HOST_BITS_PER_WIDE_INT
2471 && ((unsigned HOST_WIDE_INT
) 1 << bs1
) <= mask
)
2477 operands
[2] = GEN_INT (p
);
2478 operands
[3] = GEN_INT (len
);
2479 return "depdi -1,%2,%3,%0";
2482 /* Output an ascii string. */
2484 output_ascii (file
, p
, size
)
2486 const unsigned char *p
;
2491 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
2493 /* The HP assembler can only take strings of 256 characters at one
2494 time. This is a limitation on input line length, *not* the
2495 length of the string. Sigh. Even worse, it seems that the
2496 restriction is in number of input characters (see \xnn &
2497 \whatever). So we have to do this very carefully. */
2499 fputs ("\t.STRING \"", file
);
2502 for (i
= 0; i
< size
; i
+= 4)
2506 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
2508 register unsigned int c
= p
[i
+ io
];
2510 if (c
== '\"' || c
== '\\')
2511 partial_output
[co
++] = '\\';
2512 if (c
>= ' ' && c
< 0177)
2513 partial_output
[co
++] = c
;
2517 partial_output
[co
++] = '\\';
2518 partial_output
[co
++] = 'x';
2519 hexd
= c
/ 16 - 0 + '0';
2521 hexd
-= '9' - 'a' + 1;
2522 partial_output
[co
++] = hexd
;
2523 hexd
= c
% 16 - 0 + '0';
2525 hexd
-= '9' - 'a' + 1;
2526 partial_output
[co
++] = hexd
;
2529 if (chars_output
+ co
> 243)
2531 fputs ("\"\n\t.STRING \"", file
);
2534 fwrite (partial_output
, 1, co
, file
);
2538 fputs ("\"\n", file
);
2541 /* Try to rewrite floating point comparisons & branches to avoid
2542 useless add,tr insns.
2544 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2545 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2546 first attempt to remove useless add,tr insns. It is zero
2547 for the second pass as reorg sometimes leaves bogus REG_DEAD
2550 When CHECK_NOTES is zero we can only eliminate add,tr insns
2551 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2554 remove_useless_addtr_insns (insns
, check_notes
)
2559 static int pass
= 0;
2561 /* This is fairly cheap, so always run it when optimizing. */
2565 int fbranch_count
= 0;
2567 /* Walk all the insns in this function looking for fcmp & fbranch
2568 instructions. Keep track of how many of each we find. */
2569 insns
= get_insns ();
2570 for (insn
= insns
; insn
; insn
= next_insn (insn
))
2574 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2575 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
2578 tmp
= PATTERN (insn
);
2580 /* It must be a set. */
2581 if (GET_CODE (tmp
) != SET
)
2584 /* If the destination is CCFP, then we've found an fcmp insn. */
2585 tmp
= SET_DEST (tmp
);
2586 if (GET_CODE (tmp
) == REG
&& REGNO (tmp
) == 0)
2592 tmp
= PATTERN (insn
);
2593 /* If this is an fbranch instruction, bump the fbranch counter. */
2594 if (GET_CODE (tmp
) == SET
2595 && SET_DEST (tmp
) == pc_rtx
2596 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
2597 && GET_CODE (XEXP (SET_SRC (tmp
), 0)) == NE
2598 && GET_CODE (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == REG
2599 && REGNO (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == 0)
2607 /* Find all floating point compare + branch insns. If possible,
2608 reverse the comparison & the branch to avoid add,tr insns. */
2609 for (insn
= insns
; insn
; insn
= next_insn (insn
))
2613 /* Ignore anything that isn't an INSN. */
2614 if (GET_CODE (insn
) != INSN
)
2617 tmp
= PATTERN (insn
);
2619 /* It must be a set. */
2620 if (GET_CODE (tmp
) != SET
)
2623 /* The destination must be CCFP, which is register zero. */
2624 tmp
= SET_DEST (tmp
);
2625 if (GET_CODE (tmp
) != REG
|| REGNO (tmp
) != 0)
2628 /* INSN should be a set of CCFP.
2630 See if the result of this insn is used in a reversed FP
2631 conditional branch. If so, reverse our condition and
2632 the branch. Doing so avoids useless add,tr insns. */
2633 next
= next_insn (insn
);
2636 /* Jumps, calls and labels stop our search. */
2637 if (GET_CODE (next
) == JUMP_INSN
2638 || GET_CODE (next
) == CALL_INSN
2639 || GET_CODE (next
) == CODE_LABEL
)
2642 /* As does another fcmp insn. */
2643 if (GET_CODE (next
) == INSN
2644 && GET_CODE (PATTERN (next
)) == SET
2645 && GET_CODE (SET_DEST (PATTERN (next
))) == REG
2646 && REGNO (SET_DEST (PATTERN (next
))) == 0)
2649 next
= next_insn (next
);
2652 /* Is NEXT_INSN a branch? */
2654 && GET_CODE (next
) == JUMP_INSN
)
2656 rtx pattern
= PATTERN (next
);
2658 /* If it a reversed fp conditional branch (eg uses add,tr)
2659 and CCFP dies, then reverse our conditional and the branch
2660 to avoid the add,tr. */
2661 if (GET_CODE (pattern
) == SET
2662 && SET_DEST (pattern
) == pc_rtx
2663 && GET_CODE (SET_SRC (pattern
)) == IF_THEN_ELSE
2664 && GET_CODE (XEXP (SET_SRC (pattern
), 0)) == NE
2665 && GET_CODE (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == REG
2666 && REGNO (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == 0
2667 && GET_CODE (XEXP (SET_SRC (pattern
), 1)) == PC
2668 && (fcmp_count
== fbranch_count
2670 && find_regno_note (next
, REG_DEAD
, 0))))
2672 /* Reverse the branch. */
2673 tmp
= XEXP (SET_SRC (pattern
), 1);
2674 XEXP (SET_SRC (pattern
), 1) = XEXP (SET_SRC (pattern
), 2);
2675 XEXP (SET_SRC (pattern
), 2) = tmp
;
2676 INSN_CODE (next
) = -1;
2678 /* Reverse our condition. */
2679 tmp
= PATTERN (insn
);
2680 PUT_CODE (XEXP (tmp
, 1),
2681 reverse_condition_maybe_unordered (GET_CODE (XEXP (tmp
,
2692 /* You may have trouble believing this, but this is the 32 bit HP-PA stack
2697 Variable arguments (optional; any number may be allocated)
2699 SP-(4*(N+9)) arg word N
2704 Fixed arguments (must be allocated; may remain unused)
2713 SP-32 External Data Pointer (DP)
2715 SP-24 External/stub RP (RP')
2719 SP-8 Calling Stub RP (RP'')
2724 SP-0 Stack Pointer (points to next available address)
2728 /* This function saves registers as follows. Registers marked with ' are
2729 this function's registers (as opposed to the previous function's).
2730 If a frame_pointer isn't needed, r4 is saved as a general register;
2731 the space for the frame pointer is still allocated, though, to keep
2737 SP (FP') Previous FP
2738 SP + 4 Alignment filler (sigh)
2739 SP + 8 Space for locals reserved here.
2743 SP + n All call saved register used.
2747 SP + o All call saved fp registers used.
2751 SP + p (SP') points to next available address.
2755 /* Global variables set by FUNCTION_PROLOGUE. */
2756 /* Size of frame. Need to know this to emit return insns from
2758 static int actual_fsize
;
2759 static int local_fsize
, save_fregs
;
2761 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2762 Handle case where DISP > 8k by using the add_high_const patterns.
2764 Note in DISP > 8k case, we will leave the high part of the address
2765 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2768 store_reg (reg
, disp
, base
)
2769 int reg
, disp
, base
;
2771 rtx i
, dest
, src
, basereg
;
2773 src
= gen_rtx_REG (word_mode
, reg
);
2774 basereg
= gen_rtx_REG (Pmode
, base
);
2775 if (VAL_14_BITS_P (disp
))
2777 dest
= gen_rtx_MEM (word_mode
, plus_constant (basereg
, disp
));
2778 i
= emit_move_insn (dest
, src
);
2782 rtx delta
= GEN_INT (disp
);
2783 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
2784 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
2785 emit_move_insn (tmpreg
, high
);
2786 dest
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
2787 i
= emit_move_insn (dest
, src
);
2792 /* Emit RTL to set REG to the value specified by BASE+DISP.
2793 Handle case where DISP > 8k by using the add_high_const patterns.
2795 Note in DISP > 8k case, we will leave the high part of the address
2796 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2799 set_reg_plus_d (reg
, base
, disp
)
2800 int reg
, base
, disp
;
2804 if (VAL_14_BITS_P (disp
))
2806 i
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
2807 plus_constant (gen_rtx_REG (Pmode
, base
), disp
));
2811 rtx delta
= GEN_INT (disp
);
2812 emit_move_insn (gen_rtx_REG (Pmode
, 1),
2813 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, base
),
2814 gen_rtx_HIGH (Pmode
, delta
)));
2815 i
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
2816 gen_rtx_LO_SUM (Pmode
, gen_rtx_REG (Pmode
, 1),
2823 compute_frame_size (size
, fregs_live
)
2829 /* Space for frame pointer + filler. If any frame is allocated
2830 we need to add this in because of STARTING_FRAME_OFFSET.
2832 Similar code also appears in hppa_expand_prologue. Change both
2833 of them at the same time. */
2834 fsize
= size
+ (size
|| frame_pointer_needed
? STARTING_FRAME_OFFSET
: 0);
2836 /* Account for space used by the callee general register saves. */
2837 for (i
= 18; i
>= 3; i
--)
2838 if (regs_ever_live
[i
])
2839 fsize
+= UNITS_PER_WORD
;
2841 /* Round the stack. */
2842 fsize
= (fsize
+ 7) & ~7;
2844 /* Account for space used by the callee floating point register saves. */
2845 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
2846 if (regs_ever_live
[i
]
2847 || (! TARGET_64BIT
&& regs_ever_live
[i
+ 1]))
2852 /* We always save both halves of the FP register, so always
2853 increment the frame size by 8 bytes. */
2857 /* The various ABIs include space for the outgoing parameters in the
2858 size of the current function's stack frame. */
2859 fsize
+= current_function_outgoing_args_size
;
2861 /* Allocate space for the fixed frame marker. This space must be
2862 allocated for any function that makes calls or otherwise allocates
2864 if (!current_function_is_leaf
|| fsize
)
2867 return (fsize
+ STACK_BOUNDARY
- 1) & ~(STACK_BOUNDARY
- 1);
2871 output_function_prologue (file
, size
)
2873 int size ATTRIBUTE_UNUSED
;
2875 /* The function's label and associated .PROC must never be
2876 separated and must be output *after* any profiling declarations
2877 to avoid changing spaces/subspaces within a procedure. */
2878 ASM_OUTPUT_LABEL (file
, XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0));
2879 fputs ("\t.PROC\n", file
);
2881 /* hppa_expand_prologue does the dirty work now. We just need
2882 to output the assembler directives which denote the start
2884 fprintf (file
, "\t.CALLINFO FRAME=%d", actual_fsize
);
2885 if (regs_ever_live
[2])
2886 fputs (",CALLS,SAVE_RP", file
);
2888 fputs (",NO_CALLS", file
);
2890 if (frame_pointer_needed
)
2891 fputs (",SAVE_SP", file
);
2893 /* Pass on information about the number of callee register saves
2894 performed in the prologue.
2896 The compiler is supposed to pass the highest register number
2897 saved, the assembler then has to adjust that number before
2898 entering it into the unwind descriptor (to account for any
2899 caller saved registers with lower register numbers than the
2900 first callee saved register). */
2902 fprintf (file
, ",ENTRY_GR=%d", gr_saved
+ 2);
2905 fprintf (file
, ",ENTRY_FR=%d", fr_saved
+ 11);
2907 fputs ("\n\t.ENTRY\n", file
);
2909 /* If we're using GAS and not using the portable runtime model, then
2910 we don't need to accumulate the total number of code bytes. */
2911 if (TARGET_GAS
&& ! TARGET_PORTABLE_RUNTIME
)
2912 total_code_bytes
= 0;
2913 else if (INSN_ADDRESSES_SET_P ())
2915 unsigned int old_total
= total_code_bytes
;
2917 total_code_bytes
+= INSN_ADDRESSES (INSN_UID (get_last_insn()));
2918 total_code_bytes
+= FUNCTION_BOUNDARY
/ BITS_PER_UNIT
;
2920 /* Be prepared to handle overflows. */
2921 total_code_bytes
= old_total
> total_code_bytes
? -1 : total_code_bytes
;
2924 total_code_bytes
= -1;
2926 remove_useless_addtr_insns (get_insns (), 0);
2934 RTX_FRAME_RELATED_P (insn) = 1; \
2938 #define FRP (INSN) INSN
2942 hppa_expand_prologue ()
2944 extern char call_used_regs
[];
2945 int size
= get_frame_size ();
2946 int merge_sp_adjust_with_store
= 0;
2948 rtx tmpreg
, size_rtx
;
2954 /* Allocate space for frame pointer + filler. If any frame is allocated
2955 we need to add this in because of STARTING_FRAME_OFFSET.
2957 Similar code also appears in compute_frame_size. Change both
2958 of them at the same time. */
2959 local_fsize
= size
+ (size
|| frame_pointer_needed
2960 ? STARTING_FRAME_OFFSET
: 0);
2962 actual_fsize
= compute_frame_size (size
, &save_fregs
);
2964 /* Compute a few things we will use often. */
2965 tmpreg
= gen_rtx_REG (word_mode
, 1);
2966 size_rtx
= GEN_INT (actual_fsize
);
2968 /* Save RP first. The calling conventions manual states RP will
2969 always be stored into the caller's frame at sp - 20 or sp - 16
2970 depending on which ABI is in use. */
2971 if (regs_ever_live
[2])
2972 FRP (store_reg (2, TARGET_64BIT
? -16 : -20, STACK_POINTER_REGNUM
));
2974 /* Allocate the local frame and set up the frame pointer if needed. */
2975 if (actual_fsize
!= 0)
2977 if (frame_pointer_needed
)
2979 /* Copy the old frame pointer temporarily into %r1. Set up the
2980 new stack pointer, then store away the saved old frame pointer
2981 into the stack at sp+actual_fsize and at the same time update
2982 the stack pointer by actual_fsize bytes. Two versions, first
2983 handles small (<8k) frames. The second handles large (>=8k)
2985 emit_move_insn (tmpreg
, frame_pointer_rtx
);
2986 FRP (emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
));
2987 if (VAL_14_BITS_P (actual_fsize
))
2989 rtx insn
= emit_insn (gen_post_store (stack_pointer_rtx
, tmpreg
,
2994 RTX_FRAME_RELATED_P (insn
) = 1;
2996 gen_rtx_SET (VOIDmode
,
2997 gen_rtx_MEM (word_mode
,
3000 gen_rtx_SET (VOIDmode
,
3002 gen_rtx_PLUS (word_mode
,
3006 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3007 gen_rtx_SEQUENCE (VOIDmode
, vec
),
3013 /* It is incorrect to store the saved frame pointer at *sp,
3014 then increment sp (writes beyond the current stack boundary).
3016 So instead use stwm to store at *sp and post-increment the
3017 stack pointer as an atomic operation. Then increment sp to
3018 finish allocating the new frame. */
3019 int adjust1
= 8192 - 64;
3020 int adjust2
= actual_fsize
- adjust1
;
3021 rtx delta
= GEN_INT (adjust1
);
3022 rtx insn
= emit_insn (gen_post_store (stack_pointer_rtx
, tmpreg
,
3027 RTX_FRAME_RELATED_P (insn
) = 1;
3029 gen_rtx_SET (VOIDmode
,
3030 gen_rtx_MEM (word_mode
,
3033 gen_rtx_SET (VOIDmode
,
3035 gen_rtx_PLUS (word_mode
,
3039 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3040 gen_rtx_SEQUENCE (VOIDmode
, vec
),
3044 FRP (set_reg_plus_d (STACK_POINTER_REGNUM
,
3045 STACK_POINTER_REGNUM
,
3048 /* Prevent register spills from being scheduled before the
3049 stack pointer is raised. Necessary as we will be storing
3050 registers using the frame pointer as a base register, and
3051 we happen to set fp before raising sp. */
3052 emit_insn (gen_blockage ());
3054 /* no frame pointer needed. */
3057 /* In some cases we can perform the first callee register save
3058 and allocating the stack frame at the same time. If so, just
3059 make a note of it and defer allocating the frame until saving
3060 the callee registers. */
3061 if (VAL_14_BITS_P (actual_fsize
) && local_fsize
== 0)
3062 merge_sp_adjust_with_store
= 1;
3063 /* Can not optimize. Adjust the stack frame by actual_fsize
3066 FRP (set_reg_plus_d (STACK_POINTER_REGNUM
,
3067 STACK_POINTER_REGNUM
,
3072 /* Normal register save.
3074 Do not save the frame pointer in the frame_pointer_needed case. It
3075 was done earlier. */
3076 if (frame_pointer_needed
)
3078 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
3079 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3081 FRP (store_reg (i
, offset
, FRAME_POINTER_REGNUM
));
3082 offset
+= UNITS_PER_WORD
;
3085 /* Account for %r3 which is saved in a special place. */
3088 /* No frame pointer needed. */
3091 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
3092 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3094 /* If merge_sp_adjust_with_store is nonzero, then we can
3095 optimize the first GR save. */
3096 if (merge_sp_adjust_with_store
)
3098 rtx delta
= GEN_INT (-offset
);
3099 merge_sp_adjust_with_store
= 0;
3100 FRP (emit_insn (gen_post_store (stack_pointer_rtx
,
3101 gen_rtx_REG (word_mode
, i
),
3105 FRP (store_reg (i
, offset
, STACK_POINTER_REGNUM
));
3106 offset
+= UNITS_PER_WORD
;
3110 /* If we wanted to merge the SP adjustment with a GR save, but we never
3111 did any GR saves, then just emit the adjustment here. */
3112 if (merge_sp_adjust_with_store
)
3113 FRP (set_reg_plus_d (STACK_POINTER_REGNUM
,
3114 STACK_POINTER_REGNUM
,
3118 /* The hppa calling conventions say that %r19, the pic offset
3119 register, is saved at sp - 32 (in this function's frame)
3120 when generating PIC code. FIXME: What is the correct thing
3121 to do for functions which make no calls and allocate no
3122 frame? Do we need to allocate a frame, or can we just omit
3123 the save? For now we'll just omit the save. */
3124 if (flag_pic
&& actual_fsize
!= 0 && !TARGET_64BIT
)
3125 store_reg (PIC_OFFSET_TABLE_REGNUM
, -32, STACK_POINTER_REGNUM
);
3127 /* Align pointer properly (doubleword boundary). */
3128 offset
= (offset
+ 7) & ~7;
3130 /* Floating point register store. */
3133 /* First get the frame or stack pointer to the start of the FP register
3135 if (frame_pointer_needed
)
3136 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
));
3138 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
));
3140 /* Now actually save the FP registers. */
3141 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
3143 if (regs_ever_live
[i
]
3144 || (! TARGET_64BIT
&& regs_ever_live
[i
+ 1]))
3147 addr
= gen_rtx_MEM (DFmode
, gen_rtx_POST_INC (DFmode
, tmpreg
));
3148 reg
= gen_rtx_REG (DFmode
, i
);
3149 FRP (emit_move_insn (addr
, reg
));
3156 /* ?!? Do we want frame notes in the epilogue yet? */
3157 #undef DO_FRAME_NOTES
3158 #define DO_FRAME_NOTES 0
3160 #define FRP(INSN) INSN
3162 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3163 Handle case where DISP > 8k by using the add_high_const patterns. */
3166 load_reg (reg
, disp
, base
)
3167 int reg
, disp
, base
;
3169 rtx i
, src
, dest
, basereg
;
3171 dest
= gen_rtx_REG (word_mode
, reg
);
3172 basereg
= gen_rtx_REG (Pmode
, base
);
3173 if (VAL_14_BITS_P (disp
))
3175 src
= gen_rtx_MEM (word_mode
, plus_constant (basereg
, disp
));
3176 i
= emit_move_insn (dest
, src
);
3180 rtx delta
= GEN_INT (disp
);
3181 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
3182 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3183 emit_move_insn (tmpreg
, high
);
3184 src
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
3185 i
= emit_move_insn (dest
, src
);
3191 output_function_epilogue (file
, size
)
3193 int size ATTRIBUTE_UNUSED
;
3195 rtx insn
= get_last_insn ();
3197 /* hppa_expand_epilogue does the dirty work now. We just need
3198 to output the assembler directives which denote the end
3201 To make debuggers happy, emit a nop if the epilogue was completely
3202 eliminated due to a volatile call as the last insn in the
3203 current function. That way the return address (in %r2) will
3204 always point to a valid instruction in the current function. */
3206 /* Get the last real insn. */
3207 if (GET_CODE (insn
) == NOTE
)
3208 insn
= prev_real_insn (insn
);
3210 /* If it is a sequence, then look inside. */
3211 if (insn
&& GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3212 insn
= XVECEXP (PATTERN (insn
), 0, 0);
3214 /* If insn is a CALL_INSN, then it must be a call to a volatile
3215 function (otherwise there would be epilogue insns). */
3216 if (insn
&& GET_CODE (insn
) == CALL_INSN
)
3217 fputs ("\tnop\n", file
);
3219 fputs ("\t.EXIT\n\t.PROCEND\n", file
);
3223 hppa_expand_epilogue ()
3227 int merge_sp_adjust_with_load
= 0;
3230 /* We will use this often. */
3231 tmpreg
= gen_rtx_REG (word_mode
, 1);
3233 /* Try to restore RP early to avoid load/use interlocks when
3234 RP gets used in the return (bv) instruction. This appears to still
3235 be necessary even when we schedule the prologue and epilogue. */
3236 if (regs_ever_live
[2])
3238 ret_off
= TARGET_64BIT
? -16 : -20;
3239 if (frame_pointer_needed
)
3241 FRP (load_reg (2, ret_off
, FRAME_POINTER_REGNUM
));
3246 /* No frame pointer, and stack is smaller than 8k. */
3247 if (VAL_14_BITS_P (ret_off
- actual_fsize
))
3249 FRP (load_reg (2, ret_off
- actual_fsize
, STACK_POINTER_REGNUM
));
3255 /* General register restores. */
3256 if (frame_pointer_needed
)
3258 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
3259 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3261 FRP (load_reg (i
, offset
, FRAME_POINTER_REGNUM
));
3262 offset
+= UNITS_PER_WORD
;
3267 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
3269 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3271 /* Only for the first load.
3272 merge_sp_adjust_with_load holds the register load
3273 with which we will merge the sp adjustment. */
3274 if (merge_sp_adjust_with_load
== 0
3276 && VAL_14_BITS_P (-actual_fsize
))
3277 merge_sp_adjust_with_load
= i
;
3279 FRP (load_reg (i
, offset
, STACK_POINTER_REGNUM
));
3280 offset
+= UNITS_PER_WORD
;
3285 /* Align pointer properly (doubleword boundary). */
3286 offset
= (offset
+ 7) & ~7;
3288 /* FP register restores. */
3291 /* Adjust the register to index off of. */
3292 if (frame_pointer_needed
)
3293 FRP (set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
));
3295 FRP (set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
));
3297 /* Actually do the restores now. */
3298 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
3299 if (regs_ever_live
[i
]
3300 || (! TARGET_64BIT
&& regs_ever_live
[i
+ 1]))
3302 rtx src
= gen_rtx_MEM (DFmode
, gen_rtx_POST_INC (DFmode
, tmpreg
));
3303 rtx dest
= gen_rtx_REG (DFmode
, i
);
3304 FRP (emit_move_insn (dest
, src
));
3308 /* Emit a blockage insn here to keep these insns from being moved to
3309 an earlier spot in the epilogue, or into the main instruction stream.
3311 This is necessary as we must not cut the stack back before all the
3312 restores are finished. */
3313 emit_insn (gen_blockage ());
3315 /* Reset stack pointer (and possibly frame pointer). The stack
3316 pointer is initially set to fp + 64 to avoid a race condition. */
3317 if (frame_pointer_needed
)
3319 rtx delta
= GEN_INT (-64);
3320 FRP (set_reg_plus_d (STACK_POINTER_REGNUM
, FRAME_POINTER_REGNUM
, 64));
3321 FRP (emit_insn (gen_pre_load (frame_pointer_rtx
,
3325 /* If we were deferring a callee register restore, do it now. */
3326 else if (merge_sp_adjust_with_load
)
3328 rtx delta
= GEN_INT (-actual_fsize
);
3329 rtx dest
= gen_rtx_REG (word_mode
, merge_sp_adjust_with_load
);
3330 FRP (emit_insn (gen_pre_load (dest
, stack_pointer_rtx
, delta
)));
3332 else if (actual_fsize
!= 0)
3333 FRP (set_reg_plus_d (STACK_POINTER_REGNUM
,
3334 STACK_POINTER_REGNUM
,
3337 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3338 frame greater than 8k), do so now. */
3340 FRP (load_reg (2, ret_off
, STACK_POINTER_REGNUM
));
3343 /* Set up a callee saved register for the pic offset table register. */
3345 hppa_init_pic_save ()
3349 picreg
= gen_rtx_REG (word_mode
, PIC_OFFSET_TABLE_REGNUM
);
3350 PIC_OFFSET_TABLE_SAVE_RTX
= gen_reg_rtx (Pmode
);
3351 RTX_UNCHANGING_P (PIC_OFFSET_TABLE_SAVE_RTX
) = 1;
3352 insn
= gen_rtx_SET (VOIDmode
, PIC_OFFSET_TABLE_SAVE_RTX
, picreg
);
3354 /* Emit the insn at the beginning of the function after the prologue. */
3355 if (tail_recursion_reentry
)
3356 emit_insn_before (insn
, tail_recursion_reentry
);
3358 /* We must have been called via PROFILE_HOOK. */
3363 hppa_profile_hook (label_no
)
3364 int label_no ATTRIBUTE_UNUSED
;
3368 /* No profiling for inline functions. We don't want extra calls to
3369 _mcount when the inline function is expanded. Even if that made
3370 sense, it wouldn't work here as there is no function label for
3371 the inline expansion. */
3372 if (DECL_INLINE (cfun
->decl
))
3376 emit_move_insn (arg_pointer_rtx
,
3377 gen_rtx_PLUS (word_mode
, virtual_outgoing_args_rtx
,
3380 if (flag_pic
&& PIC_OFFSET_TABLE_SAVE_RTX
== NULL_RTX
)
3381 hppa_init_pic_save ();
3383 emit_move_insn (gen_rtx_REG (word_mode
, 26), gen_rtx_REG (word_mode
, 2));
3385 #ifndef NO_PROFILE_COUNTERS
3387 rtx count_label_rtx
, addr
, r24
;
3388 char label_name
[16];
3390 ASM_GENERATE_INTERNAL_LABEL (label_name
, "LP", label_no
);
3391 count_label_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (label_name
));
3397 current_function_uses_pic_offset_table
= 1;
3398 tmpreg
= gen_rtx_REG (Pmode
, 1);
3399 emit_move_insn (tmpreg
,
3400 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3401 gen_rtx_HIGH (Pmode
, count_label_rtx
)));
3402 addr
= gen_rtx_MEM (Pmode
,
3403 gen_rtx_LO_SUM (Pmode
, tmpreg
, count_label_rtx
));
3407 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3408 emit_move_insn (tmpreg
, gen_rtx_HIGH (Pmode
, count_label_rtx
));
3409 addr
= gen_rtx_LO_SUM (Pmode
, tmpreg
, count_label_rtx
);
3411 r24
= gen_rtx_REG (Pmode
, 24);
3412 emit_move_insn (r24
, addr
);
3414 /* %r25 is set from within the output pattern. */
3416 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode
, "_mcount"),
3417 GEN_INT (TARGET_64BIT
? 24 : 12),
3418 XEXP (DECL_RTL (cfun
->decl
), 0)));
3420 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), r24
);
3423 /* %r25 is set from within the output pattern. */
3425 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode
, "_mcount"),
3426 GEN_INT (TARGET_64BIT
? 16 : 8),
3427 XEXP (DECL_RTL (cfun
->decl
), 0)));
3430 /* Indicate the _mcount call cannot throw, nor will it execute a
3432 REG_NOTES (call_insn
)
3433 = gen_rtx_EXPR_LIST (REG_EH_REGION
, constm1_rtx
, REG_NOTES (call_insn
));
3437 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), pic_offset_table_rtx
);
3439 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), arg_pointer_rtx
);
3441 emit_move_insn (pic_offset_table_rtx
, PIC_OFFSET_TABLE_SAVE_RTX
);
3445 /* Fetch the return address for the frame COUNT steps up from
3446 the current frame, after the prologue. FRAMEADDR is the
3447 frame pointer of the COUNT frame.
3449 We want to ignore any export stub remnants here.
3451 The value returned is used in two different ways:
3453 1. To find a function's caller.
3455 2. To change the return address for a function.
3457 This function handles most instances of case 1; however, it will
3458 fail if there are two levels of stubs to execute on the return
3459 path. The only way I believe that can happen is if the return value
3460 needs a parameter relocation, which never happens for C code.
3462 This function handles most instances of case 2; however, it will
3463 fail if we did not originally have stub code on the return path
3464 but will need code on the new return path. This can happen if
3465 the caller & callee are both in the main program, but the new
3466 return location is in a shared library.
3468 To handle this correctly we need to set the return pointer at
3469 frame-20 to point to a return stub frame-24 to point to the
3470 location we wish to return to. */
3473 return_addr_rtx (count
, frameaddr
)
3474 int count ATTRIBUTE_UNUSED
;
3482 return gen_rtx_MEM (Pmode
, plus_constant (frameaddr
, -16));
3484 if (TARGET_NO_SPACE_REGS
)
3485 return gen_rtx_MEM (Pmode
, plus_constant (frameaddr
, -20));
3487 /* First, we start off with the normal return address pointer from
3490 saved_rp
= gen_reg_rtx (Pmode
);
3491 emit_move_insn (saved_rp
, plus_constant (frameaddr
, -20));
3493 /* Get pointer to the instruction stream. We have to mask out the
3494 privilege level from the two low order bits of the return address
3495 pointer here so that ins will point to the start of the first
3496 instruction that would have been executed if we returned. */
3497 ins
= copy_to_reg (gen_rtx_AND (Pmode
,
3498 copy_to_reg (gen_rtx_MEM (Pmode
, saved_rp
)),
3500 label
= gen_label_rtx ();
3502 /* Check the instruction stream at the normal return address for the
3505 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3506 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3507 0x00011820 | stub+16: mtsp r1,sr0
3508 0xe0400002 | stub+20: be,n 0(sr0,rp)
3510 If it is an export stub, than our return address is really in
3513 emit_cmp_insn (gen_rtx_MEM (SImode
, ins
),
3514 GEN_INT (0x4bc23fd1),
3515 NE
, NULL_RTX
, SImode
, 1, 0);
3516 emit_jump_insn (gen_bne (label
));
3518 emit_cmp_insn (gen_rtx_MEM (SImode
, plus_constant (ins
, 4)),
3519 GEN_INT (0x004010a1),
3520 NE
, NULL_RTX
, SImode
, 1, 0);
3521 emit_jump_insn (gen_bne (label
));
3523 emit_cmp_insn (gen_rtx_MEM (SImode
, plus_constant (ins
, 8)),
3524 GEN_INT (0x00011820),
3525 NE
, NULL_RTX
, SImode
, 1, 0);
3526 emit_jump_insn (gen_bne (label
));
3528 emit_cmp_insn (gen_rtx_MEM (SImode
, plus_constant (ins
, 12)),
3529 GEN_INT (0xe0400002),
3530 NE
, NULL_RTX
, SImode
, 1, 0);
3532 /* If there is no export stub then just use our initial guess of
3535 emit_jump_insn (gen_bne (label
));
3537 /* Here we know that our return address pointer points to an export
3538 stub. We don't want to return the address of the export stub,
3539 but rather the return address that leads back into user code.
3540 That return address is stored at -24[frameaddr]. */
3542 emit_move_insn (saved_rp
, plus_constant (frameaddr
, -24));
3545 return gen_rtx_MEM (Pmode
, memory_address (Pmode
, saved_rp
));
3548 /* This is only valid once reload has completed because it depends on
3549 knowing exactly how much (if any) frame there is and...
3551 It's only valid if there is no frame marker to de-allocate and...
3553 It's only valid if %r2 hasn't been saved into the caller's frame
3554 (we're not profiling and %r2 isn't live anywhere). */
3556 hppa_can_use_return_insn_p ()
3558 return (reload_completed
3559 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3560 && ! regs_ever_live
[2]
3561 && ! frame_pointer_needed
);
3565 emit_bcond_fp (code
, operand0
)
3569 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
3570 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3571 gen_rtx_fmt_ee (code
,
3573 gen_rtx_REG (CCFPmode
, 0),
3575 gen_rtx_LABEL_REF (VOIDmode
, operand0
),
3581 gen_cmp_fp (code
, operand0
, operand1
)
3583 rtx operand0
, operand1
;
3585 return gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCFPmode
, 0),
3586 gen_rtx_fmt_ee (code
, CCFPmode
, operand0
, operand1
));
3589 /* Adjust the cost of a scheduling dependency. Return the new cost of
3590 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3593 pa_adjust_cost (insn
, link
, dep_insn
, cost
)
3599 enum attr_type attr_type
;
3601 /* Don't adjust costs for a pa8000 chip. */
3602 if (pa_cpu
>= PROCESSOR_8000
)
3605 if (! recog_memoized (insn
))
3608 attr_type
= get_attr_type (insn
);
3610 if (REG_NOTE_KIND (link
) == 0)
3612 /* Data dependency; DEP_INSN writes a register that INSN reads some
3615 if (attr_type
== TYPE_FPSTORE
)
3617 rtx pat
= PATTERN (insn
);
3618 rtx dep_pat
= PATTERN (dep_insn
);
3619 if (GET_CODE (pat
) == PARALLEL
)
3621 /* This happens for the fstXs,mb patterns. */
3622 pat
= XVECEXP (pat
, 0, 0);
3624 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3625 /* If this happens, we have to extend this to schedule
3626 optimally. Return 0 for now. */
3629 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
3631 if (! recog_memoized (dep_insn
))
3633 /* DEP_INSN is writing its result to the register
3634 being stored in the fpstore INSN. */
3635 switch (get_attr_type (dep_insn
))
3638 /* This cost 3 cycles, not 2 as the md says for the
3647 case TYPE_FPSQRTSGL
:
3648 case TYPE_FPSQRTDBL
:
3649 /* In these important cases, we save one cycle compared to
3650 when flop instruction feed each other. */
3659 /* For other data dependencies, the default cost specified in the
3663 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3665 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3668 if (attr_type
== TYPE_FPLOAD
)
3670 rtx pat
= PATTERN (insn
);
3671 rtx dep_pat
= PATTERN (dep_insn
);
3672 if (GET_CODE (pat
) == PARALLEL
)
3674 /* This happens for the fldXs,mb patterns. */
3675 pat
= XVECEXP (pat
, 0, 0);
3677 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3678 /* If this happens, we have to extend this to schedule
3679 optimally. Return 0 for now. */
3682 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
3684 if (! recog_memoized (dep_insn
))
3686 switch (get_attr_type (dep_insn
))
3693 case TYPE_FPSQRTSGL
:
3694 case TYPE_FPSQRTDBL
:
3695 /* A fpload can't be issued until one cycle before a
3696 preceding arithmetic operation has finished if
3697 the target of the fpload is any of the sources
3698 (or destination) of the arithmetic operation. */
3706 else if (attr_type
== TYPE_FPALU
)
3708 rtx pat
= PATTERN (insn
);
3709 rtx dep_pat
= PATTERN (dep_insn
);
3710 if (GET_CODE (pat
) == PARALLEL
)
3712 /* This happens for the fldXs,mb patterns. */
3713 pat
= XVECEXP (pat
, 0, 0);
3715 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3716 /* If this happens, we have to extend this to schedule
3717 optimally. Return 0 for now. */
3720 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
3722 if (! recog_memoized (dep_insn
))
3724 switch (get_attr_type (dep_insn
))
3728 case TYPE_FPSQRTSGL
:
3729 case TYPE_FPSQRTDBL
:
3730 /* An ALU flop can't be issued until two cycles before a
3731 preceding divide or sqrt operation has finished if
3732 the target of the ALU flop is any of the sources
3733 (or destination) of the divide or sqrt operation. */
3742 /* For other anti dependencies, the cost is 0. */
3745 else if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
3747 /* Output dependency; DEP_INSN writes a register that INSN writes some
3749 if (attr_type
== TYPE_FPLOAD
)
3751 rtx pat
= PATTERN (insn
);
3752 rtx dep_pat
= PATTERN (dep_insn
);
3753 if (GET_CODE (pat
) == PARALLEL
)
3755 /* This happens for the fldXs,mb patterns. */
3756 pat
= XVECEXP (pat
, 0, 0);
3758 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3759 /* If this happens, we have to extend this to schedule
3760 optimally. Return 0 for now. */
3763 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
3765 if (! recog_memoized (dep_insn
))
3767 switch (get_attr_type (dep_insn
))
3774 case TYPE_FPSQRTSGL
:
3775 case TYPE_FPSQRTDBL
:
3776 /* A fpload can't be issued until one cycle before a
3777 preceding arithmetic operation has finished if
3778 the target of the fpload is the destination of the
3779 arithmetic operation. */
3787 else if (attr_type
== TYPE_FPALU
)
3789 rtx pat
= PATTERN (insn
);
3790 rtx dep_pat
= PATTERN (dep_insn
);
3791 if (GET_CODE (pat
) == PARALLEL
)
3793 /* This happens for the fldXs,mb patterns. */
3794 pat
= XVECEXP (pat
, 0, 0);
3796 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
3797 /* If this happens, we have to extend this to schedule
3798 optimally. Return 0 for now. */
3801 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
3803 if (! recog_memoized (dep_insn
))
3805 switch (get_attr_type (dep_insn
))
3809 case TYPE_FPSQRTSGL
:
3810 case TYPE_FPSQRTDBL
:
3811 /* An ALU flop can't be issued until two cycles before a
3812 preceding divide or sqrt operation has finished if
3813 the target of the ALU flop is also the target of
3814 the divide or sqrt operation. */
3823 /* For other output dependencies, the cost is 0. */
3830 /* Return any length adjustment needed by INSN which already has its length
3831 computed as LENGTH. Return zero if no adjustment is necessary.
3833 For the PA: function calls, millicode calls, and backwards short
3834 conditional branches with unfilled delay slots need an adjustment by +1
3835 (to account for the NOP which will be inserted into the instruction stream).
3837 Also compute the length of an inline block move here as it is too
3838 complicated to express as a length attribute in pa.md. */
3840 pa_adjust_insn_length (insn
, length
)
3844 rtx pat
= PATTERN (insn
);
3846 /* Call insns which are *not* indirect and have unfilled delay slots. */
3847 if (GET_CODE (insn
) == CALL_INSN
)
3850 if (GET_CODE (XVECEXP (pat
, 0, 0)) == CALL
3851 && GET_CODE (XEXP (XEXP (XVECEXP (pat
, 0, 0), 0), 0)) == SYMBOL_REF
)
3853 else if (GET_CODE (XVECEXP (pat
, 0, 0)) == SET
3854 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat
, 0, 0), 1), 0), 0))
3860 /* Jumps inside switch tables which have unfilled delay slots
3861 also need adjustment. */
3862 else if (GET_CODE (insn
) == JUMP_INSN
3863 && simplejump_p (insn
)
3864 && GET_MODE (insn
) == SImode
)
3866 /* Millicode insn with an unfilled delay slot. */
3867 else if (GET_CODE (insn
) == INSN
3868 && GET_CODE (pat
) != SEQUENCE
3869 && GET_CODE (pat
) != USE
3870 && GET_CODE (pat
) != CLOBBER
3871 && get_attr_type (insn
) == TYPE_MILLI
)
3873 /* Block move pattern. */
3874 else if (GET_CODE (insn
) == INSN
3875 && GET_CODE (pat
) == PARALLEL
3876 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
3877 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
3878 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
3879 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
3880 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
3881 return compute_movstrsi_length (insn
) - 4;
3882 /* Conditional branch with an unfilled delay slot. */
3883 else if (GET_CODE (insn
) == JUMP_INSN
&& ! simplejump_p (insn
))
3885 /* Adjust a short backwards conditional with an unfilled delay slot. */
3886 if (GET_CODE (pat
) == SET
3888 && ! forward_branch_p (insn
))
3890 else if (GET_CODE (pat
) == PARALLEL
3891 && get_attr_type (insn
) == TYPE_PARALLEL_BRANCH
3894 /* Adjust dbra insn with short backwards conditional branch with
3895 unfilled delay slot -- only for case where counter is in a
3896 general register register. */
3897 else if (GET_CODE (pat
) == PARALLEL
3898 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
3899 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
3900 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
3902 && ! forward_branch_p (insn
))
3910 /* Print operand X (an rtx) in assembler syntax to file FILE.
3911 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3912 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3915 print_operand (file
, x
, code
)
3923 /* Output a 'nop' if there's nothing for the delay slot. */
3924 if (dbr_sequence_length () == 0)
3925 fputs ("\n\tnop", file
);
3928 /* Output an nullification completer if there's nothing for the */
3929 /* delay slot or nullification is requested. */
3930 if (dbr_sequence_length () == 0 ||
3932 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
3936 /* Print out the second register name of a register pair.
3937 I.e., R (6) => 7. */
3938 fputs (reg_names
[REGNO (x
)+1], file
);
3941 /* A register or zero. */
3943 || (x
== CONST0_RTX (DFmode
))
3944 || (x
== CONST0_RTX (SFmode
)))
3946 fputs ("%r0", file
);
3952 /* A register or zero (floating point). */
3954 || (x
== CONST0_RTX (DFmode
))
3955 || (x
== CONST0_RTX (SFmode
)))
3957 fputs ("%fr0", file
);
3966 xoperands
[0] = XEXP (XEXP (x
, 0), 0);
3967 xoperands
[1] = XVECEXP (XEXP (XEXP (x
, 0), 1), 0, 0);
3968 output_global_address (file
, xoperands
[1], 0);
3969 fprintf (file
, "(%s)", reg_names
[REGNO (xoperands
[0])]);
3973 case 'C': /* Plain (C)ondition */
3975 switch (GET_CODE (x
))
3978 fputs ("=", file
); break;
3980 fputs ("<>", file
); break;
3982 fputs (">", file
); break;
3984 fputs (">=", file
); break;
3986 fputs (">>=", file
); break;
3988 fputs (">>", file
); break;
3990 fputs ("<", file
); break;
3992 fputs ("<=", file
); break;
3994 fputs ("<<=", file
); break;
3996 fputs ("<<", file
); break;
4001 case 'N': /* Condition, (N)egated */
4002 switch (GET_CODE (x
))
4005 fputs ("<>", file
); break;
4007 fputs ("=", file
); break;
4009 fputs ("<=", file
); break;
4011 fputs ("<", file
); break;
4013 fputs ("<<", file
); break;
4015 fputs ("<<=", file
); break;
4017 fputs (">=", file
); break;
4019 fputs (">", file
); break;
4021 fputs (">>", file
); break;
4023 fputs (">>=", file
); break;
4028 /* For floating point comparisons. Note that the output predicates are the
4029 complement of the desired mode. */
4031 switch (GET_CODE (x
))
4034 fputs ("!=", file
); break;
4036 fputs ("=", file
); break;
4038 fputs ("!>", file
); break;
4040 fputs ("!>=", file
); break;
4042 fputs ("!<", file
); break;
4044 fputs ("!<=", file
); break;
4046 fputs ("!<>", file
); break;
4048 fputs (">", file
); break;
4050 fputs (">=", file
); break;
4052 fputs ("<", file
); break;
4054 fputs ("<=", file
); break;
4056 fputs ("<>", file
); break;
4058 fputs ("<=>", file
); break;
4060 fputs ("!<=>", file
); break;
4065 case 'S': /* Condition, operands are (S)wapped. */
4066 switch (GET_CODE (x
))
4069 fputs ("=", file
); break;
4071 fputs ("<>", file
); break;
4073 fputs ("<", file
); break;
4075 fputs ("<=", file
); break;
4077 fputs ("<<=", file
); break;
4079 fputs ("<<", file
); break;
4081 fputs (">", file
); break;
4083 fputs (">=", file
); break;
4085 fputs (">>=", file
); break;
4087 fputs (">>", file
); break;
4092 case 'B': /* Condition, (B)oth swapped and negate. */
4093 switch (GET_CODE (x
))
4096 fputs ("<>", file
); break;
4098 fputs ("=", file
); break;
4100 fputs (">=", file
); break;
4102 fputs (">", file
); break;
4104 fputs (">>", file
); break;
4106 fputs (">>=", file
); break;
4108 fputs ("<=", file
); break;
4110 fputs ("<", file
); break;
4112 fputs ("<<", file
); break;
4114 fputs ("<<=", file
); break;
4120 if (GET_CODE (x
) == CONST_INT
)
4122 fprintf (file
, "%d", ~INTVAL (x
));
4127 if (GET_CODE (x
) == CONST_INT
)
4129 fprintf (file
, "%d", 64 - (INTVAL (x
) & 63));
4134 if (GET_CODE (x
) == CONST_INT
)
4136 fprintf (file
, "%d", 32 - (INTVAL (x
) & 31));
4141 if (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0)
4143 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
4148 if (GET_CODE (x
) == CONST_INT
)
4150 fprintf (file
, "%d", 63 - (INTVAL (x
) & 63));
4155 if (GET_CODE (x
) == CONST_INT
)
4157 fprintf (file
, "%d", 31 - (INTVAL (x
) & 31));
4162 if (GET_CODE (x
) == CONST_INT
)
4167 switch (GET_CODE (XEXP (x
, 0)))
4171 if (ASSEMBLER_DIALECT
== 0)
4172 fputs ("s,mb", file
);
4174 fputs (",mb", file
);
4178 if (ASSEMBLER_DIALECT
== 0)
4179 fputs ("s,ma", file
);
4181 fputs (",ma", file
);
4184 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4185 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
4187 if (ASSEMBLER_DIALECT
== 0)
4188 fputs ("x,s", file
);
4192 else if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
4196 if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
4202 output_global_address (file
, x
, 0);
4205 output_global_address (file
, x
, 1);
4207 case 0: /* Don't do anything special */
4212 compute_zdepwi_operands (INTVAL (x
), op
);
4213 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
4219 compute_zdepdi_operands (INTVAL (x
), op
);
4220 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
4224 /* We can get here from a .vtable_inherit due to our
4225 CONSTANT_ADDRESS_P rejecting perfectly good constant
4231 if (GET_CODE (x
) == REG
)
4233 fputs (reg_names
[REGNO (x
)], file
);
4234 if (TARGET_64BIT
&& FP_REG_P (x
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4)
4240 && GET_MODE_SIZE (GET_MODE (x
)) <= 4
4241 && (REGNO (x
) & 1) == 0)
4244 else if (GET_CODE (x
) == MEM
)
4246 int size
= GET_MODE_SIZE (GET_MODE (x
));
4247 rtx base
= NULL_RTX
;
4248 switch (GET_CODE (XEXP (x
, 0)))
4252 base
= XEXP (XEXP (x
, 0), 0);
4253 fprintf (file
, "-%d(%s)", size
, reg_names
[REGNO (base
)]);
4257 base
= XEXP (XEXP (x
, 0), 0);
4258 fprintf (file
, "%d(%s)", size
, reg_names
[REGNO (base
)]);
4261 if (GET_CODE (XEXP (x
, 0)) == PLUS
4262 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
4263 fprintf (file
, "%s(%s)",
4264 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 0), 0))],
4265 reg_names
[REGNO (XEXP (XEXP (x
, 0), 1))]);
4266 else if (GET_CODE (XEXP (x
, 0)) == PLUS
4267 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
4268 fprintf (file
, "%s(%s)",
4269 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 1), 0))],
4270 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
4272 output_address (XEXP (x
, 0));
4277 output_addr_const (file
, x
);
4280 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4283 output_global_address (file
, x
, round_constant
)
4289 /* Imagine (high (const (plus ...))). */
4290 if (GET_CODE (x
) == HIGH
)
4293 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
, VOIDmode
))
4294 assemble_name (file
, XSTR (x
, 0));
4295 else if (GET_CODE (x
) == SYMBOL_REF
&& !flag_pic
)
4297 assemble_name (file
, XSTR (x
, 0));
4298 fputs ("-$global$", file
);
4300 else if (GET_CODE (x
) == CONST
)
4302 const char *sep
= "";
4303 int offset
= 0; /* assembler wants -$global$ at end */
4304 rtx base
= NULL_RTX
;
4306 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
4308 base
= XEXP (XEXP (x
, 0), 0);
4309 output_addr_const (file
, base
);
4311 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == CONST_INT
)
4312 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
4315 if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == SYMBOL_REF
)
4317 base
= XEXP (XEXP (x
, 0), 1);
4318 output_addr_const (file
, base
);
4320 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
4321 offset
= INTVAL (XEXP (XEXP (x
, 0),1));
4324 /* How bogus. The compiler is apparently responsible for
4325 rounding the constant if it uses an LR field selector.
4327 The linker and/or assembler seem a better place since
4328 they have to do this kind of thing already.
4330 If we fail to do this, HP's optimizing linker may eliminate
4331 an addil, but not update the ldw/stw/ldo instruction that
4332 uses the result of the addil. */
4334 offset
= ((offset
+ 0x1000) & ~0x1fff);
4336 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4346 else if (GET_CODE (XEXP (x
, 0)) == MINUS
4347 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
4351 if (!read_only_operand (base
, VOIDmode
) && !flag_pic
)
4352 fputs ("-$global$", file
);
4354 fprintf (file
,"%s%d", sep
, offset
);
4357 output_addr_const (file
, x
);
4361 output_deferred_plabels (file
)
4365 /* If we have deferred plabels, then we need to switch into the data
4366 section and align it to a 4 byte boundary before we output the
4367 deferred plabels. */
4368 if (n_deferred_plabels
)
4371 ASM_OUTPUT_ALIGN (file
, 2);
4374 /* Now output the deferred plabels. */
4375 for (i
= 0; i
< n_deferred_plabels
; i
++)
4377 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (deferred_plabels
[i
].internal_label
));
4378 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode
,
4379 deferred_plabels
[i
].name
), 4, 1);
4383 /* HP's millicode routines mean something special to the assembler.
4384 Keep track of which ones we have used. */
4386 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, mulU
, end1000
};
4387 static void import_milli
PARAMS ((enum millicodes
));
4388 static char imported
[(int)end1000
];
4389 static const char * const milli_names
[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4390 static char import_string
[] = ".IMPORT $$....,MILLICODE";
4391 #define MILLI_START 10
4395 enum millicodes code
;
4397 char str
[sizeof (import_string
)];
4399 if (!imported
[(int)code
])
4401 imported
[(int)code
] = 1;
4402 strcpy (str
, import_string
);
4403 strncpy (str
+ MILLI_START
, milli_names
[(int)code
], 4);
4404 output_asm_insn (str
, 0);
4408 /* The register constraints have put the operands and return value in
4409 the proper registers. */
4412 output_mul_insn (unsignedp
, insn
)
4413 int unsignedp ATTRIBUTE_UNUSED
;
4416 import_milli (mulI
);
4417 return output_millicode_call (insn
, gen_rtx_SYMBOL_REF (Pmode
, "$$mulI"));
4420 /* Emit the rtl for doing a division by a constant. */
4422 /* Do magic division millicodes exist for this value? */
4423 static int magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4426 /* We'll use an array to keep track of the magic millicodes and
4427 whether or not we've used them already. [n][0] is signed, [n][1] is
4430 static int div_milli
[16][2];
4433 div_operand (op
, mode
)
4435 enum machine_mode mode
;
4437 return (mode
== SImode
4438 && ((GET_CODE (op
) == REG
&& REGNO (op
) == 25)
4439 || (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) > 0
4440 && INTVAL (op
) < 16 && magic_milli
[INTVAL (op
)])));
4444 emit_hpdiv_const (operands
, unsignedp
)
4448 if (GET_CODE (operands
[2]) == CONST_INT
4449 && INTVAL (operands
[2]) > 0
4450 && INTVAL (operands
[2]) < 16
4451 && magic_milli
[INTVAL (operands
[2])])
4453 emit_move_insn (gen_rtx_REG (SImode
, 26), operands
[1]);
4456 (PARALLEL
, VOIDmode
,
4457 gen_rtvec (6, gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, 29),
4458 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4460 gen_rtx_REG (SImode
, 26),
4462 gen_rtx_CLOBBER (VOIDmode
, operands
[4]),
4463 gen_rtx_CLOBBER (VOIDmode
, operands
[3]),
4464 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 26)),
4465 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 25)),
4466 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 31)))));
4467 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 29));
4474 output_div_insn (operands
, unsignedp
, insn
)
4481 /* If the divisor is a constant, try to use one of the special
4483 if (GET_CODE (operands
[0]) == CONST_INT
)
4485 static char buf
[100];
4486 divisor
= INTVAL (operands
[0]);
4487 if (!div_milli
[divisor
][unsignedp
])
4489 div_milli
[divisor
][unsignedp
] = 1;
4491 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
4493 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
4497 sprintf (buf
, "$$divU_%d", INTVAL (operands
[0]));
4498 return output_millicode_call (insn
,
4499 gen_rtx_SYMBOL_REF (SImode
, buf
));
4503 sprintf (buf
, "$$divI_%d", INTVAL (operands
[0]));
4504 return output_millicode_call (insn
,
4505 gen_rtx_SYMBOL_REF (SImode
, buf
));
4508 /* Divisor isn't a special constant. */
4513 import_milli (divU
);
4514 return output_millicode_call (insn
,
4515 gen_rtx_SYMBOL_REF (SImode
, "$$divU"));
4519 import_milli (divI
);
4520 return output_millicode_call (insn
,
4521 gen_rtx_SYMBOL_REF (SImode
, "$$divI"));
4526 /* Output a $$rem millicode to do mod. */
4529 output_mod_insn (unsignedp
, insn
)
4535 import_milli (remU
);
4536 return output_millicode_call (insn
,
4537 gen_rtx_SYMBOL_REF (SImode
, "$$remU"));
4541 import_milli (remI
);
4542 return output_millicode_call (insn
,
4543 gen_rtx_SYMBOL_REF (SImode
, "$$remI"));
4548 output_arg_descriptor (call_insn
)
4551 const char *arg_regs
[4];
4552 enum machine_mode arg_mode
;
4554 int i
, output_flag
= 0;
4557 /* We neither need nor want argument location descriptors for the
4558 64bit runtime environment or the ELF32 environment. */
4559 if (TARGET_64BIT
|| TARGET_ELF32
)
4562 for (i
= 0; i
< 4; i
++)
4565 /* Specify explicitly that no argument relocations should take place
4566 if using the portable runtime calling conventions. */
4567 if (TARGET_PORTABLE_RUNTIME
)
4569 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4574 if (GET_CODE (call_insn
) != CALL_INSN
)
4576 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); link
; link
= XEXP (link
, 1))
4578 rtx use
= XEXP (link
, 0);
4580 if (! (GET_CODE (use
) == USE
4581 && GET_CODE (XEXP (use
, 0)) == REG
4582 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
4585 arg_mode
= GET_MODE (XEXP (use
, 0));
4586 regno
= REGNO (XEXP (use
, 0));
4587 if (regno
>= 23 && regno
<= 26)
4589 arg_regs
[26 - regno
] = "GR";
4590 if (arg_mode
== DImode
)
4591 arg_regs
[25 - regno
] = "GR";
4593 else if (regno
>= 32 && regno
<= 39)
4595 if (arg_mode
== SFmode
)
4596 arg_regs
[(regno
- 32) / 2] = "FR";
4599 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4600 arg_regs
[(regno
- 34) / 2] = "FR";
4601 arg_regs
[(regno
- 34) / 2 + 1] = "FU";
4603 arg_regs
[(regno
- 34) / 2] = "FU";
4604 arg_regs
[(regno
- 34) / 2 + 1] = "FR";
4609 fputs ("\t.CALL ", asm_out_file
);
4610 for (i
= 0; i
< 4; i
++)
4615 fputc (',', asm_out_file
);
4616 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
4619 fputc ('\n', asm_out_file
);
4622 /* Return the class of any secondary reload register that is needed to
4623 move IN into a register in class CLASS using mode MODE.
4625 Profiling has showed this routine and its descendants account for
4626 a significant amount of compile time (~7%). So it has been
4627 optimized to reduce redundant computations and eliminate useless
4630 It might be worthwhile to try and make this a leaf function too. */
4633 secondary_reload_class (class, mode
, in
)
4634 enum reg_class
class;
4635 enum machine_mode mode
;
4638 int regno
, is_symbolic
;
4640 /* Trying to load a constant into a FP register during PIC code
4641 generation will require %r1 as a scratch register. */
4643 && GET_MODE_CLASS (mode
) == MODE_INT
4644 && FP_REG_CLASS_P (class)
4645 && (GET_CODE (in
) == CONST_INT
|| GET_CODE (in
) == CONST_DOUBLE
))
4648 /* Profiling showed the PA port spends about 1.3% of its compilation
4649 time in true_regnum from calls inside secondary_reload_class. */
4651 if (GET_CODE (in
) == REG
)
4654 if (regno
>= FIRST_PSEUDO_REGISTER
)
4655 regno
= true_regnum (in
);
4657 else if (GET_CODE (in
) == SUBREG
)
4658 regno
= true_regnum (in
);
4662 /* If we have something like (mem (mem (...)), we can safely assume the
4663 inner MEM will end up in a general register after reloading, so there's
4664 no need for a secondary reload. */
4665 if (GET_CODE (in
) == MEM
4666 && GET_CODE (XEXP (in
, 0)) == MEM
)
4669 /* Handle out of range displacement for integer mode loads/stores of
4671 if (((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
4672 && GET_MODE_CLASS (mode
) == MODE_INT
4673 && FP_REG_CLASS_P (class))
4674 || (class == SHIFT_REGS
&& (regno
<= 0 || regno
>= 32)))
4675 return GENERAL_REGS
;
4677 if (GET_CODE (in
) == HIGH
)
4680 /* Profiling has showed GCC spends about 2.6% of its compilation
4681 time in symbolic_operand from calls inside secondary_reload_class.
4683 We use an inline copy and only compute its return value once to avoid
4685 switch (GET_CODE (in
))
4695 is_symbolic
= ((GET_CODE (XEXP (tmp
, 0)) == SYMBOL_REF
4696 || GET_CODE (XEXP (tmp
, 0)) == LABEL_REF
)
4697 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
);
4707 && read_only_operand (in
, VOIDmode
))
4710 if (class != R1_REGS
&& is_symbolic
)
4717 function_arg_padding (mode
, type
)
4718 enum machine_mode mode
;
4723 if (mode
== BLKmode
)
4725 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4726 size
= int_size_in_bytes (type
) * BITS_PER_UNIT
;
4728 return upward
; /* Don't know if this is right, but */
4729 /* same as old definition. */
4732 size
= GET_MODE_BITSIZE (mode
);
4733 if (size
< PARM_BOUNDARY
)
4735 else if (size
% PARM_BOUNDARY
)
4742 /* Do what is necessary for `va_start'. We look at the current function
4743 to determine if stdargs or varargs is used and fill in an initial
4744 va_list. A pointer to this constructor is returned. */
4747 hppa_builtin_saveregs ()
4750 tree fntype
= TREE_TYPE (current_function_decl
);
4751 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
4752 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4753 != void_type_node
)))
4754 ? UNITS_PER_WORD
: 0);
4757 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
4759 offset
= current_function_arg_offset_rtx
;
4765 /* Adjust for varargs/stdarg differences. */
4767 offset
= plus_constant (current_function_arg_offset_rtx
, -argadj
);
4769 offset
= current_function_arg_offset_rtx
;
4771 /* We need to save %r26 .. %r19 inclusive starting at offset -64
4772 from the incoming arg pointer and growing to larger addresses. */
4773 for (i
= 26, off
= -64; i
>= 19; i
--, off
+= 8)
4774 emit_move_insn (gen_rtx_MEM (word_mode
,
4775 plus_constant (arg_pointer_rtx
, off
)),
4776 gen_rtx_REG (word_mode
, i
));
4778 /* The incoming args pointer points just beyond the flushback area;
4779 normally this is not a serious concern. Howver, when we are doing
4780 varargs/stdargs we want to make the arg pointer point to the start
4781 of the incoming argument area. */
4782 emit_move_insn (virtual_incoming_args_rtx
,
4783 plus_constant (arg_pointer_rtx
, -64));
4785 /* Now return a pointer to the first anonymous argument. */
4786 return copy_to_reg (expand_binop (Pmode
, add_optab
,
4787 virtual_incoming_args_rtx
,
4788 offset
, 0, 0, OPTAB_LIB_WIDEN
));
4791 /* Store general registers on the stack. */
4792 dest
= gen_rtx_MEM (BLKmode
,
4793 plus_constant (current_function_internal_arg_pointer
,
4795 MEM_ALIAS_SET (dest
) = get_varargs_alias_set ();
4796 move_block_from_reg (23, dest
, 4, 4 * UNITS_PER_WORD
);
4798 /* move_block_from_reg will emit code to store the argument registers
4799 individually as scalar stores.
4801 However, other insns may later load from the same addresses for
4802 a structure load (passing a struct to a varargs routine).
4804 The alias code assumes that such aliasing can never happen, so we
4805 have to keep memory referencing insns from moving up beyond the
4806 last argument register store. So we emit a blockage insn here. */
4807 emit_insn (gen_blockage ());
4809 if (current_function_check_memory_usage
)
4810 emit_library_call (chkr_set_right_libfunc
, 1, VOIDmode
, 3,
4812 GEN_INT (4 * UNITS_PER_WORD
), TYPE_MODE (sizetype
),
4813 GEN_INT (MEMORY_USE_RW
),
4814 TYPE_MODE (integer_type_node
));
4816 return copy_to_reg (expand_binop (Pmode
, add_optab
,
4817 current_function_internal_arg_pointer
,
4818 offset
, 0, 0, OPTAB_LIB_WIDEN
));
4822 hppa_va_start (stdarg_p
, valist
, nextarg
)
4823 int stdarg_p ATTRIBUTE_UNUSED
;
4827 nextarg
= expand_builtin_saveregs ();
4828 std_expand_builtin_va_start (1, valist
, nextarg
);
4832 hppa_va_arg (valist
, type
)
4835 HOST_WIDE_INT align
, size
, ofs
;
4840 /* Every argument in PA64 is passed by value (including large structs).
4841 Arguments with size greater than 8 must be aligned 0 MOD 16. */
4843 size
= int_size_in_bytes (type
);
4844 if (size
> UNITS_PER_WORD
)
4846 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4847 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
4848 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4849 build_int_2 (-2 * UNITS_PER_WORD
, -1));
4850 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4851 TREE_SIDE_EFFECTS (t
) = 1;
4852 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4854 return std_expand_builtin_va_arg (valist
, type
);
4857 /* Compute the rounded size of the type. */
4858 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
4859 size
= int_size_in_bytes (type
);
4861 ptr
= build_pointer_type (type
);
4863 /* "Large" types are passed by reference. */
4866 t
= build (PREDECREMENT_EXPR
, TREE_TYPE (valist
), valist
,
4867 build_int_2 (POINTER_SIZE
/ BITS_PER_UNIT
, 0));
4868 TREE_SIDE_EFFECTS (t
) = 1;
4870 pptr
= build_pointer_type (ptr
);
4871 t
= build1 (NOP_EXPR
, pptr
, t
);
4872 TREE_SIDE_EFFECTS (t
) = 1;
4874 t
= build1 (INDIRECT_REF
, ptr
, t
);
4875 TREE_SIDE_EFFECTS (t
) = 1;
4879 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4880 build_int_2 (-size
, -1));
4882 /* Copied from va-pa.h, but we probably don't need to align
4883 to word size, since we generate and preserve that invariant. */
4884 t
= build (BIT_AND_EXPR
, TREE_TYPE (valist
), t
,
4885 build_int_2 ((size
> 4 ? -8 : -4), -1));
4887 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4888 TREE_SIDE_EFFECTS (t
) = 1;
4890 ofs
= (8 - size
) % 4;
4893 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), t
, build_int_2 (ofs
, 0));
4894 TREE_SIDE_EFFECTS (t
) = 1;
4897 t
= build1 (NOP_EXPR
, ptr
, t
);
4898 TREE_SIDE_EFFECTS (t
) = 1;
4902 return expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
4907 /* This routine handles all the normal conditional branch sequences we
4908 might need to generate. It handles compare immediate vs compare
4909 register, nullification of delay slots, varying length branches,
4910 negated branches, and all combinations of the above. It returns the
4911 output appropriate to emit the branch corresponding to all given
4915 output_cbranch (operands
, nullify
, length
, negated
, insn
)
4917 int nullify
, length
, negated
;
4920 static char buf
[100];
4923 /* A conditional branch to the following instruction (eg the delay slot) is
4924 asking for a disaster. This can happen when not optimizing.
4926 In such cases it is safe to emit nothing. */
4928 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4931 /* If this is a long branch with its delay slot unfilled, set `nullify'
4932 as it can nullify the delay slot and save a nop. */
4933 if (length
== 8 && dbr_sequence_length () == 0)
4936 /* If this is a short forward conditional branch which did not get
4937 its delay slot filled, the delay slot can still be nullified. */
4938 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4939 nullify
= forward_branch_p (insn
);
4941 /* A forward branch over a single nullified insn can be done with a
4942 comclr instruction. This avoids a single cycle penalty due to
4943 mis-predicted branch if we fall through (branch not taken). */
4945 && next_real_insn (insn
) != 0
4946 && get_attr_length (next_real_insn (insn
)) == 4
4947 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
4953 /* All short conditional branches except backwards with an unfilled
4957 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
4959 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
4960 if (GET_MODE (operands
[1]) == DImode
)
4963 strcat (buf
, "%B3");
4965 strcat (buf
, "%S3");
4967 strcat (buf
, " %2,%r1,%%r0");
4969 strcat (buf
, ",n %2,%r1,%0");
4971 strcat (buf
, " %2,%r1,%0");
4974 /* All long conditionals. Note an short backward branch with an
4975 unfilled delay slot is treated just like a long backward branch
4976 with an unfilled delay slot. */
4978 /* Handle weird backwards branch with a filled delay slot
4979 with is nullified. */
4980 if (dbr_sequence_length () != 0
4981 && ! forward_branch_p (insn
)
4984 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
4985 if (GET_MODE (operands
[1]) == DImode
)
4988 strcat (buf
, "%S3");
4990 strcat (buf
, "%B3");
4991 strcat (buf
, ",n %2,%r1,.+12\n\tb %0");
4993 /* Handle short backwards branch with an unfilled delay slot.
4994 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4995 taken and untaken branches. */
4996 else if (dbr_sequence_length () == 0
4997 && ! forward_branch_p (insn
)
4998 && INSN_ADDRESSES_SET_P ()
4999 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
5000 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
5002 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
5003 if (GET_MODE (operands
[1]) == DImode
)
5006 strcat (buf
, "%B3 %2,%r1,%0%#");
5008 strcat (buf
, "%S3 %2,%r1,%0%#");
5012 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
5013 if (GET_MODE (operands
[1]) == DImode
)
5016 strcat (buf
, "%S3");
5018 strcat (buf
, "%B3");
5020 strcat (buf
, " %2,%r1,%%r0\n\tb,n %0");
5022 strcat (buf
, " %2,%r1,%%r0\n\tb %0");
5027 /* Very long branch. Right now we only handle these when not
5028 optimizing. See "jump" pattern in pa.md for details. */
5032 /* Create a reversed conditional branch which branches around
5033 the following insns. */
5035 strcpy (buf
, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5037 strcpy (buf
, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5038 if (GET_MODE (operands
[1]) == DImode
)
5042 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5045 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5047 output_asm_insn (buf
, operands
);
5049 /* Output an insn to save %r1. */
5050 output_asm_insn ("stw %%r1,-16(%%r30)", operands
);
5052 /* Now output a very long branch to the original target. */
5053 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands
);
5055 /* Now restore the value of %r1 in the delay slot. We're not
5056 optimizing so we know nothing else can be in the delay slot. */
5057 return "ldw -16(%%r30),%%r1";
5060 /* Very long branch when generating PIC code. Right now we only
5061 handle these when not optimizing. See "jump" pattern in pa.md
5066 /* Create a reversed conditional branch which branches around
5067 the following insns. */
5069 strcpy (buf
, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5071 strcpy (buf
, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5072 if (GET_MODE (operands
[1]) == DImode
)
5075 strcpy (buf
, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5077 strcpy (buf
, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5079 output_asm_insn (buf
, operands
);
5081 /* Output an insn to save %r1. */
5082 output_asm_insn ("stw %%r1,-16(%%r30)", operands
);
5084 /* Now output a very long PIC branch to the original target. */
5088 xoperands
[0] = operands
[0];
5089 xoperands
[1] = operands
[1];
5090 xoperands
[2] = operands
[2];
5091 xoperands
[3] = operands
[3];
5092 xoperands
[4] = gen_label_rtx ();
5094 output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
5096 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5097 CODE_LABEL_NUMBER (xoperands
[4]));
5098 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
5102 /* Now restore the value of %r1 in the delay slot. We're not
5103 optimizing so we know nothing else can be in the delay slot. */
5104 return "ldw -16(%%r30),%%r1";
5112 /* This routine handles all the branch-on-bit conditional branch sequences we
5113 might need to generate. It handles nullification of delay slots,
5114 varying length branches, negated branches and all combinations of the
5115 above. it returns the appropriate output template to emit the branch. */
5118 output_bb (operands
, nullify
, length
, negated
, insn
, which
)
5119 rtx
*operands ATTRIBUTE_UNUSED
;
5120 int nullify
, length
, negated
;
5124 static char buf
[100];
5127 /* A conditional branch to the following instruction (eg the delay slot) is
5128 asking for a disaster. I do not think this can happen as this pattern
5129 is only used when optimizing; jump optimization should eliminate the
5130 jump. But be prepared just in case. */
5132 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
5135 /* If this is a long branch with its delay slot unfilled, set `nullify'
5136 as it can nullify the delay slot and save a nop. */
5137 if (length
== 8 && dbr_sequence_length () == 0)
5140 /* If this is a short forward conditional branch which did not get
5141 its delay slot filled, the delay slot can still be nullified. */
5142 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
5143 nullify
= forward_branch_p (insn
);
5145 /* A forward branch over a single nullified insn can be done with a
5146 extrs instruction. This avoids a single cycle penalty due to
5147 mis-predicted branch if we fall through (branch not taken). */
5150 && next_real_insn (insn
) != 0
5151 && get_attr_length (next_real_insn (insn
)) == 4
5152 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
5159 /* All short conditional branches except backwards with an unfilled
5163 strcpy (buf
, "{extrs,|extrw,s,}");
5165 strcpy (buf
, "bb,");
5166 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
5167 strcpy (buf
, "extrd,s,*");
5168 else if (GET_MODE (operands
[0]) == DImode
)
5169 strcpy (buf
, "bb,*");
5170 if ((which
== 0 && negated
)
5171 || (which
== 1 && ! negated
))
5176 strcat (buf
, " %0,%1,1,%%r0");
5177 else if (nullify
&& negated
)
5178 strcat (buf
, ",n %0,%1,%3");
5179 else if (nullify
&& ! negated
)
5180 strcat (buf
, ",n %0,%1,%2");
5181 else if (! nullify
&& negated
)
5182 strcat (buf
, "%0,%1,%3");
5183 else if (! nullify
&& ! negated
)
5184 strcat (buf
, " %0,%1,%2");
5187 /* All long conditionals. Note an short backward branch with an
5188 unfilled delay slot is treated just like a long backward branch
5189 with an unfilled delay slot. */
5191 /* Handle weird backwards branch with a filled delay slot
5192 with is nullified. */
5193 if (dbr_sequence_length () != 0
5194 && ! forward_branch_p (insn
)
5197 strcpy (buf
, "bb,");
5198 if (GET_MODE (operands
[0]) == DImode
)
5200 if ((which
== 0 && negated
)
5201 || (which
== 1 && ! negated
))
5206 strcat (buf
, ",n %0,%1,.+12\n\tb %3");
5208 strcat (buf
, ",n %0,%1,.+12\n\tb %2");
5210 /* Handle short backwards branch with an unfilled delay slot.
5211 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5212 taken and untaken branches. */
5213 else if (dbr_sequence_length () == 0
5214 && ! forward_branch_p (insn
)
5215 && INSN_ADDRESSES_SET_P ()
5216 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
5217 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
5219 strcpy (buf
, "bb,");
5220 if (GET_MODE (operands
[0]) == DImode
)
5222 if ((which
== 0 && negated
)
5223 || (which
== 1 && ! negated
))
5228 strcat (buf
, " %0,%1,%3%#");
5230 strcat (buf
, " %0,%1,%2%#");
5234 strcpy (buf
, "{extrs,|extrw,s,}");
5235 if (GET_MODE (operands
[0]) == DImode
)
5236 strcpy (buf
, "extrd,s,*");
5237 if ((which
== 0 && negated
)
5238 || (which
== 1 && ! negated
))
5242 if (nullify
&& negated
)
5243 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %3");
5244 else if (nullify
&& ! negated
)
5245 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %2");
5247 strcat (buf
, " %0,%1,1,%%r0\n\tb %3");
5249 strcat (buf
, " %0,%1,1,%%r0\n\tb %2");
5259 /* This routine handles all the branch-on-variable-bit conditional branch
5260 sequences we might need to generate. It handles nullification of delay
5261 slots, varying length branches, negated branches and all combinations
5262 of the above. it returns the appropriate output template to emit the
5266 output_bvb (operands
, nullify
, length
, negated
, insn
, which
)
5267 rtx
*operands ATTRIBUTE_UNUSED
;
5268 int nullify
, length
, negated
;
5272 static char buf
[100];
5275 /* A conditional branch to the following instruction (eg the delay slot) is
5276 asking for a disaster. I do not think this can happen as this pattern
5277 is only used when optimizing; jump optimization should eliminate the
5278 jump. But be prepared just in case. */
5280 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
5283 /* If this is a long branch with its delay slot unfilled, set `nullify'
5284 as it can nullify the delay slot and save a nop. */
5285 if (length
== 8 && dbr_sequence_length () == 0)
5288 /* If this is a short forward conditional branch which did not get
5289 its delay slot filled, the delay slot can still be nullified. */
5290 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
5291 nullify
= forward_branch_p (insn
);
5293 /* A forward branch over a single nullified insn can be done with a
5294 extrs instruction. This avoids a single cycle penalty due to
5295 mis-predicted branch if we fall through (branch not taken). */
5298 && next_real_insn (insn
) != 0
5299 && get_attr_length (next_real_insn (insn
)) == 4
5300 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
5307 /* All short conditional branches except backwards with an unfilled
5311 strcpy (buf
, "{vextrs,|extrw,s,}");
5313 strcpy (buf
, "{bvb,|bb,}");
5314 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
5315 strcpy (buf
, "extrd,s,*}");
5316 else if (GET_MODE (operands
[0]) == DImode
)
5317 strcpy (buf
, "bb,*");
5318 if ((which
== 0 && negated
)
5319 || (which
== 1 && ! negated
))
5324 strcat (buf
, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5325 else if (nullify
&& negated
)
5326 strcat (buf
, "{,n %0,%3|,n %0,%%sar,%3}");
5327 else if (nullify
&& ! negated
)
5328 strcat (buf
, "{,n %0,%2|,n %0,%%sar,%2}");
5329 else if (! nullify
&& negated
)
5330 strcat (buf
, "{%0,%3|%0,%%sar,%3}");
5331 else if (! nullify
&& ! negated
)
5332 strcat (buf
, "{ %0,%2| %0,%%sar,%2}");
5335 /* All long conditionals. Note an short backward branch with an
5336 unfilled delay slot is treated just like a long backward branch
5337 with an unfilled delay slot. */
5339 /* Handle weird backwards branch with a filled delay slot
5340 with is nullified. */
5341 if (dbr_sequence_length () != 0
5342 && ! forward_branch_p (insn
)
5345 strcpy (buf
, "{bvb,|bb,}");
5346 if (GET_MODE (operands
[0]) == DImode
)
5348 if ((which
== 0 && negated
)
5349 || (which
== 1 && ! negated
))
5354 strcat (buf
, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5356 strcat (buf
, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5358 /* Handle short backwards branch with an unfilled delay slot.
5359 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5360 taken and untaken branches. */
5361 else if (dbr_sequence_length () == 0
5362 && ! forward_branch_p (insn
)
5363 && INSN_ADDRESSES_SET_P ()
5364 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
5365 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
5367 strcpy (buf
, "{bvb,|bb,}");
5368 if (GET_MODE (operands
[0]) == DImode
)
5370 if ((which
== 0 && negated
)
5371 || (which
== 1 && ! negated
))
5376 strcat (buf
, "{ %0,%3%#| %0,%%sar,%3%#}");
5378 strcat (buf
, "{ %0,%2%#| %0,%%sar,%2%#}");
5382 strcpy (buf
, "{vextrs,|extrw,s,}");
5383 if (GET_MODE (operands
[0]) == DImode
)
5384 strcpy (buf
, "extrd,s,*");
5385 if ((which
== 0 && negated
)
5386 || (which
== 1 && ! negated
))
5390 if (nullify
&& negated
)
5391 strcat (buf
, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5392 else if (nullify
&& ! negated
)
5393 strcat (buf
, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5395 strcat (buf
, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5397 strcat (buf
, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5407 /* Return the output template for emitting a dbra type insn.
5409 Note it may perform some output operations on its own before
5410 returning the final output string. */
5412 output_dbra (operands
, insn
, which_alternative
)
5415 int which_alternative
;
5418 /* A conditional branch to the following instruction (eg the delay slot) is
5419 asking for a disaster. Be prepared! */
5421 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
5423 if (which_alternative
== 0)
5424 return "ldo %1(%0),%0";
5425 else if (which_alternative
== 1)
5427 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)",operands
);
5428 output_asm_insn ("ldw -16(%%r30),%4",operands
);
5429 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
5430 return "{fldws|fldw} -16(%%r30),%0";
5434 output_asm_insn ("ldw %0,%4", operands
);
5435 return "ldo %1(%4),%4\n\tstw %4,%0";
5439 if (which_alternative
== 0)
5441 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
5442 int length
= get_attr_length (insn
);
5444 /* If this is a long branch with its delay slot unfilled, set `nullify'
5445 as it can nullify the delay slot and save a nop. */
5446 if (length
== 8 && dbr_sequence_length () == 0)
5449 /* If this is a short forward conditional branch which did not get
5450 its delay slot filled, the delay slot can still be nullified. */
5451 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
5452 nullify
= forward_branch_p (insn
);
5454 /* Handle short versions first. */
5455 if (length
== 4 && nullify
)
5456 return "addib,%C2,n %1,%0,%3";
5457 else if (length
== 4 && ! nullify
)
5458 return "addib,%C2 %1,%0,%3";
5459 else if (length
== 8)
5461 /* Handle weird backwards branch with a fulled delay slot
5462 which is nullified. */
5463 if (dbr_sequence_length () != 0
5464 && ! forward_branch_p (insn
)
5466 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5467 /* Handle short backwards branch with an unfilled delay slot.
5468 Using a addb;nop rather than addi;bl saves 1 cycle for both
5469 taken and untaken branches. */
5470 else if (dbr_sequence_length () == 0
5471 && ! forward_branch_p (insn
)
5472 && INSN_ADDRESSES_SET_P ()
5473 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
5474 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
5475 return "addib,%C2 %1,%0,%3%#";
5477 /* Handle normal cases. */
5479 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5481 return "addi,%N2 %1,%0,%0\n\tb %3";
5486 /* Deal with gross reload from FP register case. */
5487 else if (which_alternative
== 1)
5489 /* Move loop counter from FP register to MEM then into a GR,
5490 increment the GR, store the GR into MEM, and finally reload
5491 the FP register from MEM from within the branch's delay slot. */
5492 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands
);
5493 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
5494 if (get_attr_length (insn
) == 24)
5495 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5497 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5499 /* Deal with gross reload from memory case. */
5502 /* Reload loop counter from memory, the store back to memory
5503 happens in the branch's delay slot. */
5504 output_asm_insn ("ldw %0,%4", operands
);
5505 if (get_attr_length (insn
) == 12)
5506 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5508 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5512 /* Return the output template for emitting a dbra type insn.
5514 Note it may perform some output operations on its own before
5515 returning the final output string. */
5517 output_movb (operands
, insn
, which_alternative
, reverse_comparison
)
5520 int which_alternative
;
5521 int reverse_comparison
;
5524 /* A conditional branch to the following instruction (eg the delay slot) is
5525 asking for a disaster. Be prepared! */
5527 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
5529 if (which_alternative
== 0)
5530 return "copy %1,%0";
5531 else if (which_alternative
== 1)
5533 output_asm_insn ("stw %1,-16(%%r30)",operands
);
5534 return "{fldws|fldw} -16(%%r30),%0";
5536 else if (which_alternative
== 2)
5542 /* Support the second variant. */
5543 if (reverse_comparison
)
5544 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
5546 if (which_alternative
== 0)
5548 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
5549 int length
= get_attr_length (insn
);
5551 /* If this is a long branch with its delay slot unfilled, set `nullify'
5552 as it can nullify the delay slot and save a nop. */
5553 if (length
== 8 && dbr_sequence_length () == 0)
5556 /* If this is a short forward conditional branch which did not get
5557 its delay slot filled, the delay slot can still be nullified. */
5558 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
5559 nullify
= forward_branch_p (insn
);
5561 /* Handle short versions first. */
5562 if (length
== 4 && nullify
)
5563 return "movb,%C2,n %1,%0,%3";
5564 else if (length
== 4 && ! nullify
)
5565 return "movb,%C2 %1,%0,%3";
5566 else if (length
== 8)
5568 /* Handle weird backwards branch with a filled delay slot
5569 which is nullified. */
5570 if (dbr_sequence_length () != 0
5571 && ! forward_branch_p (insn
)
5573 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5575 /* Handle short backwards branch with an unfilled delay slot.
5576 Using a movb;nop rather than or;bl saves 1 cycle for both
5577 taken and untaken branches. */
5578 else if (dbr_sequence_length () == 0
5579 && ! forward_branch_p (insn
)
5580 && INSN_ADDRESSES_SET_P ()
5581 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
5582 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
5583 return "movb,%C2 %1,%0,%3%#";
5584 /* Handle normal cases. */
5586 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5588 return "or,%N2 %1,%%r0,%0\n\tb %3";
5593 /* Deal with gross reload from FP register case. */
5594 else if (which_alternative
== 1)
5596 /* Move loop counter from FP register to MEM then into a GR,
5597 increment the GR, store the GR into MEM, and finally reload
5598 the FP register from MEM from within the branch's delay slot. */
5599 output_asm_insn ("stw %1,-16(%%r30)",operands
);
5600 if (get_attr_length (insn
) == 12)
5601 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5603 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5605 /* Deal with gross reload from memory case. */
5606 else if (which_alternative
== 2)
5608 /* Reload loop counter from memory, the store back to memory
5609 happens in the branch's delay slot. */
5610 if (get_attr_length (insn
) == 8)
5611 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5613 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5615 /* Handle SAR as a destination. */
5618 if (get_attr_length (insn
) == 8)
5619 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5621 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5626 /* INSN is a millicode call. It may have an unconditional jump in its delay
5629 CALL_DEST is the routine we are calling. */
5632 output_millicode_call (insn
, call_dest
)
5640 xoperands
[3] = gen_rtx_REG (Pmode
, TARGET_64BIT
? 2 : 31);
5642 /* Handle common case -- empty delay slot or no jump in the delay slot,
5643 and we're sure that the branch will reach the beginning of the $CODE$
5645 if ((dbr_sequence_length () == 0
5646 && (get_attr_length (insn
) == 8 || get_attr_length (insn
) == 28))
5647 || (dbr_sequence_length () != 0
5648 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
5649 && get_attr_length (insn
) == 4))
5651 xoperands
[0] = call_dest
;
5652 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands
);
5656 /* This call may not reach the beginning of the $CODE$ subspace. */
5657 if (get_attr_length (insn
) > 4)
5659 int delay_insn_deleted
= 0;
5661 /* We need to emit an inline long-call branch. */
5662 if (dbr_sequence_length () != 0
5663 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
5665 /* A non-jump insn in the delay slot. By definition we can
5666 emit this insn before the call. */
5667 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
5669 /* Now delete the delay insn. */
5670 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5671 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5672 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5673 delay_insn_deleted
= 1;
5676 /* PIC long millicode call sequence. */
5679 xoperands
[0] = call_dest
;
5680 xoperands
[1] = gen_label_rtx ();
5681 /* Get our address + 8 into %r1. */
5682 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
5684 /* Add %r1 to the offset of our target from the next insn. */
5685 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands
);
5686 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5687 CODE_LABEL_NUMBER (xoperands
[1]));
5688 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands
);
5690 /* Get the return address into %r31. */
5691 output_asm_insn ("blr 0,%3", xoperands
);
5693 /* Branch to our target which is in %r1. */
5694 output_asm_insn ("bv,n %%r0(%%r1)", xoperands
);
5696 /* Empty delay slot. Note this insn gets fetched twice and
5697 executed once. To be safe we use a nop. */
5698 output_asm_insn ("nop", xoperands
);
5700 /* Pure portable runtime doesn't allow be/ble; we also don't have
5701 PIC support in the assembler/linker, so this sequence is needed. */
5702 else if (TARGET_PORTABLE_RUNTIME
)
5704 xoperands
[0] = call_dest
;
5705 /* Get the address of our target into %r29. */
5706 output_asm_insn ("ldil L%%%0,%%r29", xoperands
);
5707 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands
);
5709 /* Get our return address into %r31. */
5710 output_asm_insn ("blr %%r0,%3", xoperands
);
5712 /* Jump to our target address in %r29. */
5713 output_asm_insn ("bv,n %%r0(%%r29)", xoperands
);
5715 /* Empty delay slot. Note this insn gets fetched twice and
5716 executed once. To be safe we use a nop. */
5717 output_asm_insn ("nop", xoperands
);
5719 /* If we're allowed to use be/ble instructions, then this is the
5720 best sequence to use for a long millicode call. */
5723 xoperands
[0] = call_dest
;
5724 output_asm_insn ("ldil L%%%0,%3", xoperands
);
5725 output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands
);
5726 output_asm_insn ("nop", xoperands
);
5729 /* If we had a jump in the call's delay slot, output it now. */
5730 if (dbr_sequence_length () != 0
5731 && !delay_insn_deleted
)
5733 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5734 output_asm_insn ("b,n %0", xoperands
);
5736 /* Now delete the delay insn. */
5737 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5738 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5739 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5744 /* This call has an unconditional jump in its delay slot and the
5745 call is known to reach its target or the beginning of the current
5748 /* Use the containing sequence insn's address. */
5749 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
5751 distance
= INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn
))))
5752 - INSN_ADDRESSES (INSN_UID (seq_insn
)) - 8;
5754 /* If the branch was too far away, emit a normal call followed
5755 by a nop, followed by the unconditional branch.
5757 If the branch is close, then adjust %r2 from within the
5758 call's delay slot. */
5760 xoperands
[0] = call_dest
;
5761 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5762 if (! VAL_14_BITS_P (distance
))
5763 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands
);
5766 xoperands
[2] = gen_label_rtx ();
5767 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
5769 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5770 CODE_LABEL_NUMBER (xoperands
[2]));
5773 /* Delete the jump. */
5774 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5775 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5776 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5780 extern struct obstack permanent_obstack
;
5782 /* INSN is either a function call. It may have an unconditional jump
5785 CALL_DEST is the routine we are calling. */
5788 output_call (insn
, call_dest
, sibcall
)
5797 /* Handle common case -- empty delay slot or no jump in the delay slot,
5798 and we're sure that the branch will reach the beginning of the $CODE$
5800 if ((dbr_sequence_length () == 0
5801 && get_attr_length (insn
) == 8)
5802 || (dbr_sequence_length () != 0
5803 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
5804 && get_attr_length (insn
) == 4))
5806 xoperands
[0] = call_dest
;
5807 xoperands
[1] = gen_rtx_REG (word_mode
, sibcall
? 0 : 2);
5808 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands
);
5812 /* This call may not reach the beginning of the $CODE$ subspace. */
5813 if (get_attr_length (insn
) > 8)
5815 int delay_insn_deleted
= 0;
5819 /* We need to emit an inline long-call branch. Furthermore,
5820 because we're changing a named function call into an indirect
5821 function call well after the parameters have been set up, we
5822 need to make sure any FP args appear in both the integer
5823 and FP registers. Also, we need move any delay slot insn
5824 out of the delay slot. And finally, we can't rely on the linker
5825 being able to fix the call to $$dyncall! -- Yuk!. */
5826 if (dbr_sequence_length () != 0
5827 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
5829 /* A non-jump insn in the delay slot. By definition we can
5830 emit this insn before the call (and in fact before argument
5832 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
5834 /* Now delete the delay insn. */
5835 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5836 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5837 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
5838 delay_insn_deleted
= 1;
5841 /* Now copy any FP arguments into integer registers. */
5842 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
5844 int arg_mode
, regno
;
5845 rtx use
= XEXP (link
, 0);
5846 if (! (GET_CODE (use
) == USE
5847 && GET_CODE (XEXP (use
, 0)) == REG
5848 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
5851 arg_mode
= GET_MODE (XEXP (use
, 0));
5852 regno
= REGNO (XEXP (use
, 0));
5853 /* Is it a floating point register? */
5854 if (regno
>= 32 && regno
<= 39)
5856 /* Copy from the FP register into an integer register
5858 if (arg_mode
== SFmode
)
5860 xoperands
[0] = XEXP (use
, 0);
5861 xoperands
[1] = gen_rtx_REG (SImode
, 26 - (regno
- 32) / 2);
5862 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
5864 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
5868 xoperands
[0] = XEXP (use
, 0);
5869 xoperands
[1] = gen_rtx_REG (DImode
, 25 - (regno
- 34) / 2);
5870 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
5872 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands
);
5873 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
5878 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5879 we don't have any direct calls in that case. */
5882 const char *name
= XSTR (call_dest
, 0);
5884 /* See if we have already put this function on the list
5885 of deferred plabels. This list is generally small,
5886 so a liner search is not too ugly. If it proves too
5887 slow replace it with something faster. */
5888 for (i
= 0; i
< n_deferred_plabels
; i
++)
5889 if (strcmp (name
, deferred_plabels
[i
].name
) == 0)
5892 /* If the deferred plabel list is empty, or this entry was
5893 not found on the list, create a new entry on the list. */
5894 if (deferred_plabels
== NULL
|| i
== n_deferred_plabels
)
5896 const char *real_name
;
5898 if (deferred_plabels
== 0)
5899 deferred_plabels
= (struct deferred_plabel
*)
5900 xmalloc (1 * sizeof (struct deferred_plabel
));
5902 deferred_plabels
= (struct deferred_plabel
*)
5903 xrealloc (deferred_plabels
,
5904 ((n_deferred_plabels
+ 1)
5905 * sizeof (struct deferred_plabel
)));
5907 i
= n_deferred_plabels
++;
5908 deferred_plabels
[i
].internal_label
= gen_label_rtx ();
5909 deferred_plabels
[i
].name
= obstack_alloc (&permanent_obstack
,
5911 strcpy (deferred_plabels
[i
].name
, name
);
5913 /* Gross. We have just implicitly taken the address of this
5914 function, mark it as such. */
5915 STRIP_NAME_ENCODING (real_name
, name
);
5916 TREE_SYMBOL_REFERENCED (get_identifier (real_name
)) = 1;
5919 /* We have to load the address of the function using a procedure
5920 label (plabel). Inline plabels can lose for PIC and other
5921 cases, so avoid them by creating a 32bit plabel in the data
5925 xoperands
[0] = deferred_plabels
[i
].internal_label
;
5926 xoperands
[1] = gen_label_rtx ();
5928 output_asm_insn ("addil LT%%%0,%%r19", xoperands
);
5929 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands
);
5930 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands
);
5932 /* Get our address + 8 into %r1. */
5933 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
5935 /* Add %r1 to the offset of dyncall from the next insn. */
5936 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands
);
5937 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
5938 CODE_LABEL_NUMBER (xoperands
[1]));
5939 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands
);
5941 /* Get the return address into %r31. */
5942 output_asm_insn ("blr %%r0,%%r31", xoperands
);
5944 /* Branch to our target which is in %r1. */
5945 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
5949 /* This call never returns, so we do not need to fix the
5951 output_asm_insn ("nop", xoperands
);
5955 /* Copy the return address into %r2 also. */
5956 output_asm_insn ("copy %%r31,%%r2", xoperands
);
5961 xoperands
[0] = deferred_plabels
[i
].internal_label
;
5963 /* Get the address of our target into %r22. */
5964 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands
);
5965 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands
);
5967 /* Get the high part of the address of $dyncall into %r2, then
5968 add in the low part in the branch instruction. */
5969 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands
);
5970 output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
5975 /* This call never returns, so we do not need to fix the
5977 output_asm_insn ("nop", xoperands
);
5981 /* Copy the return address into %r2 also. */
5982 output_asm_insn ("copy %%r31,%%r2", xoperands
);
5987 /* If we had a jump in the call's delay slot, output it now. */
5988 if (dbr_sequence_length () != 0
5989 && !delay_insn_deleted
)
5991 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
5992 output_asm_insn ("b,n %0", xoperands
);
5994 /* Now delete the delay insn. */
5995 PUT_CODE (NEXT_INSN (insn
), NOTE
);
5996 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
5997 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
6002 /* This call has an unconditional jump in its delay slot and the
6003 call is known to reach its target or the beginning of the current
6006 /* Use the containing sequence insn's address. */
6007 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
6009 distance
= INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn
))))
6010 - INSN_ADDRESSES (INSN_UID (seq_insn
)) - 8;
6012 /* If the branch was too far away, emit a normal call followed
6013 by a nop, followed by the unconditional branch.
6015 If the branch is close, then adjust %r2 from within the
6016 call's delay slot. */
6018 xoperands
[0] = call_dest
;
6019 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
6020 if (! VAL_14_BITS_P (distance
))
6021 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands
);
6024 xoperands
[3] = gen_label_rtx ();
6025 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6027 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
6028 CODE_LABEL_NUMBER (xoperands
[3]));
6031 /* Delete the jump. */
6032 PUT_CODE (NEXT_INSN (insn
), NOTE
);
6033 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
6034 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
6038 /* In HPUX 8.0's shared library scheme, special relocations are needed
6039 for function labels if they might be passed to a function
6040 in a shared library (because shared libraries don't live in code
6041 space), and special magic is needed to construct their address. */
6044 hppa_encode_label (sym
)
6047 const char *str
= XSTR (sym
, 0);
6048 int len
= strlen (str
) + 1;
6051 p
= newstr
= alloca (len
+ 1);
6060 XSTR (sym
,0) = ggc_alloc_string (newstr
, len
);
6064 function_label_operand (op
, mode
)
6066 enum machine_mode mode ATTRIBUTE_UNUSED
;
6068 return GET_CODE (op
) == SYMBOL_REF
&& FUNCTION_NAME_P (XSTR (op
, 0));
6071 /* Returns 1 if OP is a function label involved in a simple addition
6072 with a constant. Used to keep certain patterns from matching
6073 during instruction combination. */
6075 is_function_label_plus_const (op
)
6078 /* Strip off any CONST. */
6079 if (GET_CODE (op
) == CONST
)
6082 return (GET_CODE (op
) == PLUS
6083 && function_label_operand (XEXP (op
, 0), Pmode
)
6084 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
6087 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6088 use in fmpyadd instructions. */
6090 fmpyaddoperands (operands
)
6093 enum machine_mode mode
= GET_MODE (operands
[0]);
6095 /* Must be a floating point mode. */
6096 if (mode
!= SFmode
&& mode
!= DFmode
)
6099 /* All modes must be the same. */
6100 if (! (mode
== GET_MODE (operands
[1])
6101 && mode
== GET_MODE (operands
[2])
6102 && mode
== GET_MODE (operands
[3])
6103 && mode
== GET_MODE (operands
[4])
6104 && mode
== GET_MODE (operands
[5])))
6107 /* All operands must be registers. */
6108 if (! (GET_CODE (operands
[1]) == REG
6109 && GET_CODE (operands
[2]) == REG
6110 && GET_CODE (operands
[3]) == REG
6111 && GET_CODE (operands
[4]) == REG
6112 && GET_CODE (operands
[5]) == REG
))
6115 /* Only 2 real operands to the addition. One of the input operands must
6116 be the same as the output operand. */
6117 if (! rtx_equal_p (operands
[3], operands
[4])
6118 && ! rtx_equal_p (operands
[3], operands
[5]))
6121 /* Inout operand of add can not conflict with any operands from multiply. */
6122 if (rtx_equal_p (operands
[3], operands
[0])
6123 || rtx_equal_p (operands
[3], operands
[1])
6124 || rtx_equal_p (operands
[3], operands
[2]))
6127 /* multiply can not feed into addition operands. */
6128 if (rtx_equal_p (operands
[4], operands
[0])
6129 || rtx_equal_p (operands
[5], operands
[0]))
6132 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6134 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
6135 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
6136 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
6137 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
6138 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
6139 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
6142 /* Passed. Operands are suitable for fmpyadd. */
6146 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6147 use in fmpysub instructions. */
6149 fmpysuboperands (operands
)
6152 enum machine_mode mode
= GET_MODE (operands
[0]);
6154 /* Must be a floating point mode. */
6155 if (mode
!= SFmode
&& mode
!= DFmode
)
6158 /* All modes must be the same. */
6159 if (! (mode
== GET_MODE (operands
[1])
6160 && mode
== GET_MODE (operands
[2])
6161 && mode
== GET_MODE (operands
[3])
6162 && mode
== GET_MODE (operands
[4])
6163 && mode
== GET_MODE (operands
[5])))
6166 /* All operands must be registers. */
6167 if (! (GET_CODE (operands
[1]) == REG
6168 && GET_CODE (operands
[2]) == REG
6169 && GET_CODE (operands
[3]) == REG
6170 && GET_CODE (operands
[4]) == REG
6171 && GET_CODE (operands
[5]) == REG
))
6174 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6175 operation, so operands[4] must be the same as operand[3]. */
6176 if (! rtx_equal_p (operands
[3], operands
[4]))
6179 /* multiply can not feed into subtraction. */
6180 if (rtx_equal_p (operands
[5], operands
[0]))
6183 /* Inout operand of sub can not conflict with any operands from multiply. */
6184 if (rtx_equal_p (operands
[3], operands
[0])
6185 || rtx_equal_p (operands
[3], operands
[1])
6186 || rtx_equal_p (operands
[3], operands
[2]))
6189 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6191 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
6192 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
6193 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
6194 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
6195 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
6196 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
6199 /* Passed. Operands are suitable for fmpysub. */
6204 plus_xor_ior_operator (op
, mode
)
6206 enum machine_mode mode ATTRIBUTE_UNUSED
;
6208 return (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == XOR
6209 || GET_CODE (op
) == IOR
);
6212 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6213 constants for shadd instructions. */
6215 shadd_constant_p (val
)
6218 if (val
== 2 || val
== 4 || val
== 8)
6224 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6225 the valid constant for shadd instructions. */
6227 shadd_operand (op
, mode
)
6229 enum machine_mode mode ATTRIBUTE_UNUSED
;
6231 return (GET_CODE (op
) == CONST_INT
&& shadd_constant_p (INTVAL (op
)));
6234 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6237 basereg_operand (op
, mode
)
6239 enum machine_mode mode
;
6241 /* cse will create some unscaled indexed addresses, however; it
6242 generally isn't a win on the PA, so avoid creating unscaled
6243 indexed addresses until after cse is finished. */
6244 if (!cse_not_expected
)
6247 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6248 we don't have to worry about the braindamaged implicit space
6249 register selection from the basereg. */
6250 if (TARGET_NO_SPACE_REGS
)
6251 return (GET_CODE (op
) == REG
);
6253 /* While it's always safe to index off the frame pointer, it's not
6254 always profitable, particularly when the frame pointer is being
6256 if (! flag_omit_frame_pointer
&& op
== frame_pointer_rtx
)
6259 return (GET_CODE (op
) == REG
6261 && register_operand (op
, mode
));
6264 /* Return 1 if this operand is anything other than a hard register. */
6267 non_hard_reg_operand (op
, mode
)
6269 enum machine_mode mode ATTRIBUTE_UNUSED
;
6271 return ! (GET_CODE (op
) == REG
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
);
6274 /* Return 1 if INSN branches forward. Should be using insn_addresses
6275 to avoid walking through all the insns... */
6277 forward_branch_p (insn
)
6280 rtx label
= JUMP_LABEL (insn
);
6287 insn
= NEXT_INSN (insn
);
6290 return (insn
== label
);
6293 /* Return 1 if OP is an equality comparison, else return 0. */
6295 eq_neq_comparison_operator (op
, mode
)
6297 enum machine_mode mode ATTRIBUTE_UNUSED
;
6299 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
6302 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6304 movb_comparison_operator (op
, mode
)
6306 enum machine_mode mode ATTRIBUTE_UNUSED
;
6308 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
6309 || GET_CODE (op
) == LT
|| GET_CODE (op
) == GE
);
6312 /* Return 1 if INSN is in the delay slot of a call instruction. */
6314 jump_in_call_delay (insn
)
6318 if (GET_CODE (insn
) != JUMP_INSN
)
6321 if (PREV_INSN (insn
)
6322 && PREV_INSN (PREV_INSN (insn
))
6323 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn
)))) == INSN
)
6325 rtx test_insn
= next_active_insn (PREV_INSN (PREV_INSN (insn
)));
6327 return (GET_CODE (PATTERN (test_insn
)) == SEQUENCE
6328 && XVECEXP (PATTERN (test_insn
), 0, 1) == insn
);
6335 /* Output an unconditional move and branch insn. */
6338 output_parallel_movb (operands
, length
)
6342 /* These are the cases in which we win. */
6344 return "mov%I1b,tr %1,%0,%2";
6346 /* None of these cases wins, but they don't lose either. */
6347 if (dbr_sequence_length () == 0)
6349 /* Nothing in the delay slot, fake it by putting the combined
6350 insn (the copy or add) in the delay slot of a bl. */
6351 if (GET_CODE (operands
[1]) == CONST_INT
)
6352 return "b %2\n\tldi %1,%0";
6354 return "b %2\n\tcopy %1,%0";
6358 /* Something in the delay slot, but we've got a long branch. */
6359 if (GET_CODE (operands
[1]) == CONST_INT
)
6360 return "ldi %1,%0\n\tb %2";
6362 return "copy %1,%0\n\tb %2";
6366 /* Output an unconditional add and branch insn. */
6369 output_parallel_addb (operands
, length
)
6373 /* To make life easy we want operand0 to be the shared input/output
6374 operand and operand1 to be the readonly operand. */
6375 if (operands
[0] == operands
[1])
6376 operands
[1] = operands
[2];
6378 /* These are the cases in which we win. */
6380 return "add%I1b,tr %1,%0,%3";
6382 /* None of these cases win, but they don't lose either. */
6383 if (dbr_sequence_length () == 0)
6385 /* Nothing in the delay slot, fake it by putting the combined
6386 insn (the copy or add) in the delay slot of a bl. */
6387 return "b %3\n\tadd%I1 %1,%0,%0";
6391 /* Something in the delay slot, but we've got a long branch. */
6392 return "add%I1 %1,%0,%0\n\tb %3";
6396 /* Return nonzero if INSN (a jump insn) immediately follows a call to
6397 a named function. This is used to discourage creating parallel movb/addb
6398 insns since a jump which immediately follows a call can execute in the
6399 delay slot of the call.
6401 It is also used to avoid filling the delay slot of a jump which
6402 immediately follows a call since the jump can usually be eliminated
6403 completely by modifying RP in the delay slot of the call. */
6406 following_call (insn
)
6409 /* We do not parallel movb,addb or place jumps into call delay slots when
6410 optimizing for the PA8000. */
6411 if (pa_cpu
!= PROCESSOR_8000
)
6414 /* Find the previous real insn, skipping NOTEs. */
6415 insn
= PREV_INSN (insn
);
6416 while (insn
&& GET_CODE (insn
) == NOTE
)
6417 insn
= PREV_INSN (insn
);
6419 /* Check for CALL_INSNs and millicode calls. */
6421 && ((GET_CODE (insn
) == CALL_INSN
6422 && get_attr_type (insn
) != TYPE_DYNCALL
)
6423 || (GET_CODE (insn
) == INSN
6424 && GET_CODE (PATTERN (insn
)) != SEQUENCE
6425 && GET_CODE (PATTERN (insn
)) != USE
6426 && GET_CODE (PATTERN (insn
)) != CLOBBER
6427 && get_attr_type (insn
) == TYPE_MILLI
)))
6433 /* We use this hook to perform a PA specific optimization which is difficult
6434 to do in earlier passes.
6436 We want the delay slots of branches within jump tables to be filled.
6437 None of the compiler passes at the moment even has the notion that a
6438 PA jump table doesn't contain addresses, but instead contains actual
6441 Because we actually jump into the table, the addresses of each entry
6442 must stay constant in relation to the beginning of the table (which
6443 itself must stay constant relative to the instruction to jump into
6444 it). I don't believe we can guarantee earlier passes of the compiler
6445 will adhere to those rules.
6447 So, late in the compilation process we find all the jump tables, and
6448 expand them into real code -- eg each entry in the jump table vector
6449 will get an appropriate label followed by a jump to the final target.
6451 Reorg and the final jump pass can then optimize these branches and
6452 fill their delay slots. We end up with smaller, more efficient code.
6454 The jump instructions within the table are special; we must be able
6455 to identify them during assembly output (if the jumps don't get filled
6456 we need to emit a nop rather than nullifying the delay slot)). We
6457 identify jumps in switch tables by marking the SET with DImode.
6459 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6460 insns. This serves two purposes, first it prevents jump.c from
6461 noticing that the last N entries in the table jump to the instruction
6462 immediately after the table and deleting the jumps. Second, those
6463 insns mark where we should emit .begin_brtab and .end_brtab directives
6464 when using GAS (allows for better link time optimizations). */
6472 remove_useless_addtr_insns (insns
, 1);
6474 if (pa_cpu
< PROCESSOR_8000
)
6475 pa_combine_instructions (get_insns ());
6478 /* This is fairly cheap, so always run it if optimizing. */
6479 if (optimize
> 0 && !TARGET_BIG_SWITCH
)
6481 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6482 insns
= get_insns ();
6483 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
6485 rtx pattern
, tmp
, location
;
6486 unsigned int length
, i
;
6488 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6489 if (GET_CODE (insn
) != JUMP_INSN
6490 || (GET_CODE (PATTERN (insn
)) != ADDR_VEC
6491 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
))
6494 /* Emit marker for the beginning of the branch table. */
6495 emit_insn_before (gen_begin_brtab (), insn
);
6497 pattern
= PATTERN (insn
);
6498 location
= PREV_INSN (insn
);
6499 length
= XVECLEN (pattern
, GET_CODE (pattern
) == ADDR_DIFF_VEC
);
6501 for (i
= 0; i
< length
; i
++)
6503 /* Emit a label before each jump to keep jump.c from
6504 removing this code. */
6505 tmp
= gen_label_rtx ();
6506 LABEL_NUSES (tmp
) = 1;
6507 emit_label_after (tmp
, location
);
6508 location
= NEXT_INSN (location
);
6510 if (GET_CODE (pattern
) == ADDR_VEC
)
6512 /* Emit the jump itself. */
6513 tmp
= gen_jump (XEXP (XVECEXP (pattern
, 0, i
), 0));
6514 tmp
= emit_jump_insn_after (tmp
, location
);
6515 JUMP_LABEL (tmp
) = XEXP (XVECEXP (pattern
, 0, i
), 0);
6516 /* It is easy to rely on the branch table markers
6517 during assembly output to trigger the correct code
6518 for a switch table jump with an unfilled delay slot,
6520 However, that requires state and assumes that we look
6523 We can't make such assumptions when computing the length
6524 of instructions. Ugh. We could walk the insn chain to
6525 determine if this instruction is in a branch table, but
6526 that can get rather expensive, particularly during the
6527 branch shortening phase of the compiler.
6529 So instead we mark this jump as being special. This is
6530 far from ideal and knows that no code after this will
6531 muck around with the mode of the JUMP_INSN itself. */
6532 PUT_MODE (tmp
, SImode
);
6533 LABEL_NUSES (JUMP_LABEL (tmp
))++;
6534 location
= NEXT_INSN (location
);
6538 /* Emit the jump itself. */
6539 tmp
= gen_jump (XEXP (XVECEXP (pattern
, 1, i
), 0));
6540 tmp
= emit_jump_insn_after (tmp
, location
);
6541 JUMP_LABEL (tmp
) = XEXP (XVECEXP (pattern
, 1, i
), 0);
6542 /* It is easy to rely on the branch table markers
6543 during assembly output to trigger the correct code
6544 for a switch table jump with an unfilled delay slot,
6546 However, that requires state and assumes that we look
6549 We can't make such assumptions when computing the length
6550 of instructions. Ugh. We could walk the insn chain to
6551 determine if this instruction is in a branch table, but
6552 that can get rather expensive, particularly during the
6553 branch shortening phase of the compiler.
6555 So instead we mark this jump as being special. This is
6556 far from ideal and knows that no code after this will
6557 muck around with the mode of the JUMP_INSN itself. */
6558 PUT_MODE (tmp
, SImode
);
6559 LABEL_NUSES (JUMP_LABEL (tmp
))++;
6560 location
= NEXT_INSN (location
);
6563 /* Emit a BARRIER after the jump. */
6564 emit_barrier_after (location
);
6565 location
= NEXT_INSN (location
);
6568 /* Emit marker for the end of the branch table. */
6569 emit_insn_before (gen_end_brtab (), location
);
6570 location
= NEXT_INSN (location
);
6571 emit_barrier_after (location
);
6573 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6579 /* Sill need an end_brtab insn. */
6580 insns
= get_insns ();
6581 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
6583 /* Find an ADDR_VEC insn. */
6584 if (GET_CODE (insn
) != JUMP_INSN
6585 || (GET_CODE (PATTERN (insn
)) != ADDR_VEC
6586 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
))
6589 /* Now generate markers for the beginning and end of the
6591 emit_insn_before (gen_begin_brtab (), insn
);
6592 emit_insn_after (gen_end_brtab (), insn
);
6597 /* The PA has a number of odd instructions which can perform multiple
6598 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6599 it may be profitable to combine two instructions into one instruction
6600 with two outputs. It's not profitable PA2.0 machines because the
6601 two outputs would take two slots in the reorder buffers.
6603 This routine finds instructions which can be combined and combines
6604 them. We only support some of the potential combinations, and we
6605 only try common ways to find suitable instructions.
6607 * addb can add two registers or a register and a small integer
6608 and jump to a nearby (+-8k) location. Normally the jump to the
6609 nearby location is conditional on the result of the add, but by
6610 using the "true" condition we can make the jump unconditional.
6611 Thus addb can perform two independent operations in one insn.
6613 * movb is similar to addb in that it can perform a reg->reg
6614 or small immediate->reg copy and jump to a nearby (+-8k location).
6616 * fmpyadd and fmpysub can perform a FP multiply and either an
6617 FP add or FP sub if the operands of the multiply and add/sub are
6618 independent (there are other minor restrictions). Note both
6619 the fmpy and fadd/fsub can in theory move to better spots according
6620 to data dependencies, but for now we require the fmpy stay at a
6623 * Many of the memory operations can perform pre & post updates
6624 of index registers. GCC's pre/post increment/decrement addressing
6625 is far too simple to take advantage of all the possibilities. This
6626 pass may not be suitable since those insns may not be independent.
6628 * comclr can compare two ints or an int and a register, nullify
6629 the following instruction and zero some other register. This
6630 is more difficult to use as it's harder to find an insn which
6631 will generate a comclr than finding something like an unconditional
6632 branch. (conditional moves & long branches create comclr insns).
6634 * Most arithmetic operations can conditionally skip the next
6635 instruction. They can be viewed as "perform this operation
6636 and conditionally jump to this nearby location" (where nearby
6637 is an insns away). These are difficult to use due to the
6638 branch length restrictions. */
6641 pa_combine_instructions (insns
)
6642 rtx insns ATTRIBUTE_UNUSED
;
6646 /* This can get expensive since the basic algorithm is on the
6647 order of O(n^2) (or worse). Only do it for -O2 or higher
6648 levels of optimization. */
6652 /* Walk down the list of insns looking for "anchor" insns which
6653 may be combined with "floating" insns. As the name implies,
6654 "anchor" instructions don't move, while "floating" insns may
6656 new = gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, NULL_RTX
, NULL_RTX
));
6657 new = make_insn_raw (new);
6659 for (anchor
= get_insns (); anchor
; anchor
= NEXT_INSN (anchor
))
6661 enum attr_pa_combine_type anchor_attr
;
6662 enum attr_pa_combine_type floater_attr
;
6664 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6665 Also ignore any special USE insns. */
6666 if ((GET_CODE (anchor
) != INSN
6667 && GET_CODE (anchor
) != JUMP_INSN
6668 && GET_CODE (anchor
) != CALL_INSN
)
6669 || GET_CODE (PATTERN (anchor
)) == USE
6670 || GET_CODE (PATTERN (anchor
)) == CLOBBER
6671 || GET_CODE (PATTERN (anchor
)) == ADDR_VEC
6672 || GET_CODE (PATTERN (anchor
)) == ADDR_DIFF_VEC
)
6675 anchor_attr
= get_attr_pa_combine_type (anchor
);
6676 /* See if anchor is an insn suitable for combination. */
6677 if (anchor_attr
== PA_COMBINE_TYPE_FMPY
6678 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6679 || (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
6680 && ! forward_branch_p (anchor
)))
6684 for (floater
= PREV_INSN (anchor
);
6686 floater
= PREV_INSN (floater
))
6688 if (GET_CODE (floater
) == NOTE
6689 || (GET_CODE (floater
) == INSN
6690 && (GET_CODE (PATTERN (floater
)) == USE
6691 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
6694 /* Anything except a regular INSN will stop our search. */
6695 if (GET_CODE (floater
) != INSN
6696 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
6697 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
6703 /* See if FLOATER is suitable for combination with the
6705 floater_attr
= get_attr_pa_combine_type (floater
);
6706 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
6707 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
6708 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6709 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
6711 /* If ANCHOR and FLOATER can be combined, then we're
6712 done with this pass. */
6713 if (pa_can_combine_p (new, anchor
, floater
, 0,
6714 SET_DEST (PATTERN (floater
)),
6715 XEXP (SET_SRC (PATTERN (floater
)), 0),
6716 XEXP (SET_SRC (PATTERN (floater
)), 1)))
6720 else if (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
6721 && floater_attr
== PA_COMBINE_TYPE_ADDMOVE
)
6723 if (GET_CODE (SET_SRC (PATTERN (floater
))) == PLUS
)
6725 if (pa_can_combine_p (new, anchor
, floater
, 0,
6726 SET_DEST (PATTERN (floater
)),
6727 XEXP (SET_SRC (PATTERN (floater
)), 0),
6728 XEXP (SET_SRC (PATTERN (floater
)), 1)))
6733 if (pa_can_combine_p (new, anchor
, floater
, 0,
6734 SET_DEST (PATTERN (floater
)),
6735 SET_SRC (PATTERN (floater
)),
6736 SET_SRC (PATTERN (floater
))))
6742 /* If we didn't find anything on the backwards scan try forwards. */
6744 && (anchor_attr
== PA_COMBINE_TYPE_FMPY
6745 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
))
6747 for (floater
= anchor
; floater
; floater
= NEXT_INSN (floater
))
6749 if (GET_CODE (floater
) == NOTE
6750 || (GET_CODE (floater
) == INSN
6751 && (GET_CODE (PATTERN (floater
)) == USE
6752 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
6756 /* Anything except a regular INSN will stop our search. */
6757 if (GET_CODE (floater
) != INSN
6758 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
6759 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
6765 /* See if FLOATER is suitable for combination with the
6767 floater_attr
= get_attr_pa_combine_type (floater
);
6768 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
6769 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
6770 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6771 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
6773 /* If ANCHOR and FLOATER can be combined, then we're
6774 done with this pass. */
6775 if (pa_can_combine_p (new, anchor
, floater
, 1,
6776 SET_DEST (PATTERN (floater
)),
6777 XEXP (SET_SRC (PATTERN(floater
)),0),
6778 XEXP(SET_SRC(PATTERN(floater
)),1)))
6784 /* FLOATER will be nonzero if we found a suitable floating
6785 insn for combination with ANCHOR. */
6787 && (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
6788 || anchor_attr
== PA_COMBINE_TYPE_FMPY
))
6790 /* Emit the new instruction and delete the old anchor. */
6791 emit_insn_before (gen_rtx_PARALLEL
6793 gen_rtvec (2, PATTERN (anchor
),
6794 PATTERN (floater
))),
6797 PUT_CODE (anchor
, NOTE
);
6798 NOTE_LINE_NUMBER (anchor
) = NOTE_INSN_DELETED
;
6799 NOTE_SOURCE_FILE (anchor
) = 0;
6801 /* Emit a special USE insn for FLOATER, then delete
6802 the floating insn. */
6803 emit_insn_before (gen_rtx_USE (VOIDmode
, floater
), floater
);
6804 delete_insn (floater
);
6809 && anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
)
6812 /* Emit the new_jump instruction and delete the old anchor. */
6814 = emit_jump_insn_before (gen_rtx_PARALLEL
6816 gen_rtvec (2, PATTERN (anchor
),
6817 PATTERN (floater
))),
6820 JUMP_LABEL (temp
) = JUMP_LABEL (anchor
);
6821 PUT_CODE (anchor
, NOTE
);
6822 NOTE_LINE_NUMBER (anchor
) = NOTE_INSN_DELETED
;
6823 NOTE_SOURCE_FILE (anchor
) = 0;
6825 /* Emit a special USE insn for FLOATER, then delete
6826 the floating insn. */
6827 emit_insn_before (gen_rtx_USE (VOIDmode
, floater
), floater
);
6828 delete_insn (floater
);
6836 pa_can_combine_p (new, anchor
, floater
, reversed
, dest
, src1
, src2
)
6837 rtx
new, anchor
, floater
;
6839 rtx dest
, src1
, src2
;
6841 int insn_code_number
;
6844 /* Create a PARALLEL with the patterns of ANCHOR and
6845 FLOATER, try to recognize it, then test constraints
6846 for the resulting pattern.
6848 If the pattern doesn't match or the constraints
6849 aren't met keep searching for a suitable floater
6851 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor
);
6852 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater
);
6853 INSN_CODE (new) = -1;
6854 insn_code_number
= recog_memoized (new);
6855 if (insn_code_number
< 0
6856 || !constrain_operands (1))
6870 /* There's up to three operands to consider. One
6871 output and two inputs.
6873 The output must not be used between FLOATER & ANCHOR
6874 exclusive. The inputs must not be set between
6875 FLOATER and ANCHOR exclusive. */
6877 if (reg_used_between_p (dest
, start
, end
))
6880 if (reg_set_between_p (src1
, start
, end
))
6883 if (reg_set_between_p (src2
, start
, end
))
6886 /* If we get here, then everything is good. */
6890 /* Return nonzero if references for INSN are delayed.
6892 Millicode insns are actually function calls with some special
6893 constraints on arguments and register usage.
6895 Millicode calls always expect their arguments in the integer argument
6896 registers, and always return their result in %r29 (ret1). They
6897 are expected to clobber their arguments, %r1, %r29, and %r31 and
6900 By considering this effects delayed reorg reorg can put insns
6901 which set the argument registers into the delay slot of the millicode
6902 call -- thus they act more like traditional CALL_INSNs.
6904 get_attr_type will try to recognize the given insn, so make sure to
6905 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6908 insn_refs_are_delayed (insn
)
6911 return ((GET_CODE (insn
) == INSN
6912 && GET_CODE (PATTERN (insn
)) != SEQUENCE
6913 && GET_CODE (PATTERN (insn
)) != USE
6914 && GET_CODE (PATTERN (insn
)) != CLOBBER
6915 && get_attr_type (insn
) == TYPE_MILLI
));
6918 /* Return the location of a parameter that is passed in a register or NULL
6919 if the parameter has any component that is passed in memory.
6921 This is new code and will be pushed to into the net sources after
6924 ??? We might want to restructure this so that it looks more like other
6927 function_arg (cum
, mode
, type
, named
, incoming
)
6928 CUMULATIVE_ARGS
*cum
;
6929 enum machine_mode mode
;
6931 int named ATTRIBUTE_UNUSED
;
6934 int max_arg_words
= (TARGET_64BIT
? 8 : 4);
6941 /* If this arg would be passed partially or totally on the stack, then
6942 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
6943 handle arguments which are split between regs and stack slots if
6944 the ABI mandates split arguments. */
6945 if (cum
->words
+ FUNCTION_ARG_SIZE (mode
, type
) > max_arg_words
6946 || mode
== VOIDmode
)
6952 if (FUNCTION_ARG_SIZE (mode
, type
) > 1 && (cum
->words
& 1))
6954 if (cum
->words
+ offset
>= max_arg_words
6955 || mode
== VOIDmode
)
6959 /* The 32bit ABIs and the 64bit ABIs are rather different,
6960 particularly in their handling of FP registers. We might
6961 be able to cleverly share code between them, but I'm not
6962 going to bother in the hope that splitting them up results
6963 in code that is more easily understood.
6965 The 64bit code probably is very wrong for structure passing. */
6968 /* Advance the base registers to their current locations.
6970 Remember, gprs grow towards smaller register numbers while
6971 fprs grow to higher register numbers. Also remember FP regs
6972 are always 4 bytes wide, while the size of an integer register
6973 varies based on the size of the target word. */
6974 gpr_reg_base
= 26 - cum
->words
;
6975 fpr_reg_base
= 32 + cum
->words
;
6977 /* If the argument is more than a word long, then we need to align
6978 the base registers. Same caveats as above. */
6979 if (FUNCTION_ARG_SIZE (mode
, type
) > 1)
6981 if (mode
!= BLKmode
)
6983 /* First deal with alignment of the doubleword. */
6984 gpr_reg_base
-= (cum
->words
& 1);
6986 /* This seems backwards, but it is what HP specifies. We need
6987 gpr_reg_base to point to the smaller numbered register of
6988 the integer register pair. So if we have an even register
6989 number, then decrement the gpr base. */
6990 gpr_reg_base
-= ((gpr_reg_base
% 2) == 0);
6992 /* FP values behave sanely, except that each FP reg is only
6994 fpr_reg_base
+= ((fpr_reg_base
% 2) == 0);
6999 int i
, offset
= 0, ub
;
7000 ub
= FUNCTION_ARG_SIZE (mode
, type
);
7002 MAX(0, max_arg_words
- cum
->words
- (cum
->words
& 1)));
7003 gpr_reg_base
-= (cum
->words
& 1);
7004 for (i
= 0; i
< ub
; i
++)
7006 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
7007 gen_rtx_REG (DImode
,
7016 return XEXP (loc
[0], 0);
7018 return gen_rtx_PARALLEL(mode
, gen_rtvec_v(ub
, loc
));
7024 /* If the argument is larger than a word, then we know precisely
7025 which registers we must use. */
7026 if (FUNCTION_ARG_SIZE (mode
, type
) > 1)
7041 /* We have a single word (32 bits). A simple computation
7042 will get us the register #s we need. */
7043 gpr_reg_base
= 26 - cum
->words
;
7044 fpr_reg_base
= 32 + 2 * cum
->words
;
7048 if (TARGET_64BIT
&& mode
== TFmode
)
7054 gen_rtx_EXPR_LIST (VOIDmode
,
7055 gen_rtx_REG (DImode
, gpr_reg_base
+ 1),
7057 gen_rtx_EXPR_LIST (VOIDmode
,
7058 gen_rtx_REG (DImode
, gpr_reg_base
),
7061 /* Determine if the register needs to be passed in both general and
7062 floating point registers. */
7063 if ((TARGET_PORTABLE_RUNTIME
|| TARGET_64BIT
|| TARGET_ELF32
)
7064 /* If we are doing soft-float with portable runtime, then there
7065 is no need to worry about FP regs. */
7066 && ! TARGET_SOFT_FLOAT
7067 /* The parameter must be some kind of float, else we can just
7068 pass it in integer registers. */
7069 && FLOAT_MODE_P (mode
)
7070 /* The target function must not have a prototype. */
7071 && cum
->nargs_prototype
<= 0
7072 /* libcalls do not need to pass items in both FP and general
7074 && type
!= NULL_TREE
7075 /* All this hair applies to outgoing args only. */
7082 gen_rtx_EXPR_LIST (VOIDmode
,
7083 gen_rtx_REG (mode
, fpr_reg_base
),
7085 gen_rtx_EXPR_LIST (VOIDmode
,
7086 gen_rtx_REG (mode
, gpr_reg_base
),
7091 /* See if we should pass this parameter in a general register. */
7092 if (TARGET_SOFT_FLOAT
7093 /* Indirect calls in the normal 32bit ABI require all arguments
7094 to be passed in general registers. */
7095 || (!TARGET_PORTABLE_RUNTIME
7098 /* If the parameter is not a floating point parameter, then
7099 it belongs in GPRs. */
7100 || !FLOAT_MODE_P (mode
))
7101 retval
= gen_rtx_REG (mode
, gpr_reg_base
);
7103 retval
= gen_rtx_REG (mode
, fpr_reg_base
);
7109 /* If this arg would be passed totally in registers or totally on the stack,
7110 then this routine should return zero. It is currently called only for
7111 the 64-bit target. */
7113 function_arg_partial_nregs (cum
, mode
, type
, named
)
7114 CUMULATIVE_ARGS
*cum
;
7115 enum machine_mode mode
;
7117 int named ATTRIBUTE_UNUSED
;
7119 unsigned int max_arg_words
= 8;
7120 unsigned int offset
= 0;
7122 if (FUNCTION_ARG_SIZE (mode
, type
) > 1 && (cum
->words
& 1))
7125 if (cum
->words
+ offset
+ FUNCTION_ARG_SIZE (mode
, type
) <= max_arg_words
)
7126 /* Arg fits fully into registers. */
7128 else if (cum
->words
+ offset
>= max_arg_words
)
7129 /* Arg fully on the stack. */
7133 return max_arg_words
- cum
->words
- offset
;
7138 /* Return 1 if this is a comparison operator. This allows the use of
7139 MATCH_OPERATOR to recognize all the branch insns. */
7142 cmpib_comparison_operator (op
, mode
)
7144 enum machine_mode mode
;
7146 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
7147 && (GET_CODE (op
) == EQ
7148 || GET_CODE (op
) == NE
7149 || GET_CODE (op
) == GT
7150 || GET_CODE (op
) == GTU
7151 || GET_CODE (op
) == GE
7152 || GET_CODE (op
) == LT
7153 || GET_CODE (op
) == LE
7154 || GET_CODE (op
) == LEU
));
7157 /* Mark ARG (which is really a struct deferred_plabel **) for GC. */
7160 mark_deferred_plabels (arg
)
7163 struct deferred_plabel
*dp
= *(struct deferred_plabel
**) arg
;
7166 for (i
= 0; i
< n_deferred_plabels
; ++i
)
7167 ggc_mark_rtx (dp
[i
].internal_label
);
7170 /* Called to register all of our global variables with the garbage
7176 ggc_add_rtx_root (&hppa_compare_op0
, 1);
7177 ggc_add_rtx_root (&hppa_compare_op1
, 1);
7178 ggc_add_root (&deferred_plabels
, 1, sizeof (&deferred_plabels
),
7179 &mark_deferred_plabels
);