1 ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; millicode call delay slot description. Note it disallows delay slot
109 ;; when TARGET_PORTABLE_RUNTIME is true.
110 (define_delay (eq_attr "type" "milli")
111 [(and (eq_attr "in_call_delay" "true")
112 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0)))
115 ;; Return and other similar instructions.
116 (define_delay (eq_attr "type" "branch,parallel_branch")
117 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
119 ;; Floating point conditional branch delay slot description and
120 (define_delay (eq_attr "type" "fbranch")
121 [(eq_attr "in_branch_delay" "true")
122 (eq_attr "in_nullified_branch_delay" "true")
125 ;; Integer conditional branch delay slot description.
126 ;; Nullification of conditional branches on the PA is dependent on the
127 ;; direction of the branch. Forward branches nullify true and
128 ;; backward branches nullify false. If the direction is unknown
129 ;; then nullification is not allowed.
130 (define_delay (eq_attr "type" "cbranch")
131 [(eq_attr "in_branch_delay" "true")
132 (and (eq_attr "in_nullified_branch_delay" "true")
133 (attr_flag "forward"))
134 (and (eq_attr "in_nullified_branch_delay" "true")
135 (attr_flag "backward"))])
137 (define_delay (and (eq_attr "type" "uncond_branch")
138 (eq (symbol_ref "following_call (insn)")
140 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
142 ;; Function units of the HPPA. The following data is for the 700 CPUs
143 ;; (Mustang CPU + Timex FPU aka PA-89) because that's what I have the docs for.
144 ;; Scheduling instructions for PA-83 machines according to the Snake
145 ;; constraints shouldn't hurt.
147 ;; (define_function_unit {name} {num-units} {n-users} {test}
148 ;; {ready-delay} {issue-delay} [{conflict-list}])
151 ;; (Noted only for documentation; units that take one cycle do not need to
154 ;; (define_function_unit "alu" 1 0
155 ;; (and (eq_attr "type" "unary,shift,nullshift,binary,move,address")
156 ;; (eq_attr "cpu" "700"))
160 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
161 ;; load: 2, fpload: 3
162 ;; store, fpstore: 3, no D-cache operations should be scheduled.
164 (define_function_unit "pa700memory" 1 0
165 (and (eq_attr "type" "load,fpload")
166 (eq_attr "cpu" "700")) 2 0)
167 (define_function_unit "pa700memory" 1 0
168 (and (eq_attr "type" "store,fpstore")
169 (eq_attr "cpu" "700")) 3 3)
171 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
173 ;; Instruction Time Unit Minimum Distance (unit contention)
180 ;; fmpyadd 3 ALU,MPY 2
181 ;; fmpysub 3 ALU,MPY 2
182 ;; fmpycfxt 3 ALU,MPY 2
185 ;; fdiv,sgl 10 MPY 10
186 ;; fdiv,dbl 12 MPY 12
187 ;; fsqrt,sgl 14 MPY 14
188 ;; fsqrt,dbl 18 MPY 18
190 (define_function_unit "pa700fp_alu" 1 0
191 (and (eq_attr "type" "fpcc")
192 (eq_attr "cpu" "700")) 4 2)
193 (define_function_unit "pa700fp_alu" 1 0
194 (and (eq_attr "type" "fpalu")
195 (eq_attr "cpu" "700")) 3 2)
196 (define_function_unit "pa700fp_mpy" 1 0
197 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
198 (eq_attr "cpu" "700")) 3 2)
199 (define_function_unit "pa700fp_mpy" 1 0
200 (and (eq_attr "type" "fpdivsgl")
201 (eq_attr "cpu" "700")) 10 10)
202 (define_function_unit "pa700fp_mpy" 1 0
203 (and (eq_attr "type" "fpdivdbl")
204 (eq_attr "cpu" "700")) 12 12)
205 (define_function_unit "pa700fp_mpy" 1 0
206 (and (eq_attr "type" "fpsqrtsgl")
207 (eq_attr "cpu" "700")) 14 14)
208 (define_function_unit "pa700fp_mpy" 1 0
209 (and (eq_attr "type" "fpsqrtdbl")
210 (eq_attr "cpu" "700")) 18 18)
212 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
213 ;; floating point computations with non-floating point computations (fp loads
214 ;; and stores are not fp computations).
217 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
218 ;; take two cycles, during which no Dcache operations should be scheduled.
219 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
220 ;; all have the same memory characteristics if one disregards cache misses.
221 (define_function_unit "pa7100memory" 1 0
222 (and (eq_attr "type" "load,fpload")
223 (eq_attr "cpu" "7100,7100LC")) 2 0)
224 (define_function_unit "pa7100memory" 1 0
225 (and (eq_attr "type" "store,fpstore")
226 (eq_attr "cpu" "7100,7100LC")) 2 2)
228 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
230 ;; Instruction Time Unit Minimum Distance (unit contention)
237 ;; fmpyadd 2 ALU,MPY 1
238 ;; fmpysub 2 ALU,MPY 1
239 ;; fmpycfxt 2 ALU,MPY 1
243 ;; fdiv,dbl 15 DIV 15
245 ;; fsqrt,dbl 15 DIV 15
247 (define_function_unit "pa7100fp_alu" 1 0
248 (and (eq_attr "type" "fpcc,fpalu")
249 (eq_attr "cpu" "7100")) 2 1)
250 (define_function_unit "pa7100fp_mpy" 1 0
251 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
252 (eq_attr "cpu" "7100")) 2 1)
253 (define_function_unit "pa7100fp_div" 1 0
254 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
255 (eq_attr "cpu" "7100")) 8 8)
256 (define_function_unit "pa7100fp_div" 1 0
257 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
258 (eq_attr "cpu" "7100")) 15 15)
260 ;; To encourage dual issue we define function units corresponding to
261 ;; the instructions which can be dual issued. This is a rather crude
262 ;; approximation, the "pa7100nonflop" test in particular could be refined.
263 (define_function_unit "pa7100flop" 1 1
265 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
266 (eq_attr "cpu" "7100")) 1 1)
268 (define_function_unit "pa7100nonflop" 1 1
270 (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
271 (eq_attr "cpu" "7100")) 1 1)
274 ;; Memory subsystem works just like 7100/7150 (except for cache miss times which
275 ;; we don't model here).
277 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
278 ;; Note divides and sqrt flops lock the cpu until the flop is
279 ;; finished. fmpy and xmpyu (fmpyi) lock the cpu for one cycle.
280 ;; There's no way to avoid the penalty.
282 ;; Instruction Time Unit Minimum Distance (unit contention)
289 ;; fmpyadd,sgl 2 ALU,MPY 1
290 ;; fmpyadd,dbl 3 ALU,MPY 2
291 ;; fmpysub,sgl 2 ALU,MPY 1
292 ;; fmpysub,dbl 3 ALU,MPY 2
293 ;; fmpycfxt,sgl 2 ALU,MPY 1
294 ;; fmpycfxt,dbl 3 ALU,MPY 2
299 ;; fdiv,dbl 15 DIV 15
301 ;; fsqrt,dbl 15 DIV 15
303 (define_function_unit "pa7100LCfp_alu" 1 0
304 (and (eq_attr "type" "fpcc,fpalu")
305 (eq_attr "cpu" "7100LC,7200")) 2 1)
306 (define_function_unit "pa7100LCfp_mpy" 1 0
307 (and (eq_attr "type" "fpmulsgl")
308 (eq_attr "cpu" "7100LC,7200")) 2 1)
309 (define_function_unit "pa7100LCfp_mpy" 1 0
310 (and (eq_attr "type" "fpmuldbl")
311 (eq_attr "cpu" "7100LC,7200")) 3 2)
312 (define_function_unit "pa7100LCfp_div" 1 0
313 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
314 (eq_attr "cpu" "7100LC,7200")) 8 8)
315 (define_function_unit "pa7100LCfp_div" 1 0
316 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
317 (eq_attr "cpu" "7100LC,7200")) 15 15)
319 ;; Define the various functional units for dual-issue.
321 ;; There's only one floating point unit.
322 (define_function_unit "pa7100LCflop" 1 1
324 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
325 (eq_attr "cpu" "7100LC,7200")) 1 1)
327 ;; Shifts and memory ops execute in only one of the integer ALUs
328 (define_function_unit "pa7100LCshiftmem" 1 1
330 (eq_attr "type" "shift,nullshift,load,fpload,store,fpstore")
331 (eq_attr "cpu" "7100LC,7200")) 1 1)
333 ;; We have two basic ALUs.
334 (define_function_unit "pa7100LCalu" 2 1
336 (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
337 (eq_attr "cpu" "7100LC,7200")) 1 1)
339 ;; I don't have complete information on the PA7200; however, most of
340 ;; what I've heard makes it look like a 7100LC without the store-store
341 ;; penalty. So that's how we'll model it.
343 ;; Memory. Disregarding Cache misses, memory loads and stores take
344 ;; two cycles. Any special cases are handled in pa_adjust_cost.
345 (define_function_unit "pa7200memory" 1 0
346 (and (eq_attr "type" "load,fpload,store,fpstore")
347 (eq_attr "cpu" "7200")) 2 0)
349 ;; I don't have detailed information on the PA7200 FP pipeline, so I
350 ;; treat it just like the 7100LC pipeline.
351 ;; Similarly for the multi-issue fake units.
354 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
355 ;; traditional architecture.
357 ;; The PA8000 has a large (56) entry reorder buffer that is split between
358 ;; memory and non-memory operations.
360 ;; The PA800 can issue two memory and two non-memory operations per cycle to
361 ;; the function units. Similarly, the PA8000 can retire two memory and two
362 ;; non-memory operations per cycle.
364 ;; Given the large reorder buffer, the processor can hide most latencies.
365 ;; According to HP, they've got the best results by scheduling for retirement
366 ;; bandwidth with limited latency scheduling for floating point operations.
367 ;; Latency for integer operations and memory references is ignored.
369 ;; We claim floating point operations have a 2 cycle latency and are
370 ;; fully pipelined, except for div and sqrt which are not pipelined.
372 ;; It is not necessary to define the shifter and integer alu units.
374 ;; These first two define_unit_unit descriptions model retirement from
375 ;; the reorder buffer.
376 (define_function_unit "pa8000lsu" 2 1
378 (eq_attr "type" "load,fpload,store,fpstore")
379 (eq_attr "cpu" "8000")) 1 1)
381 (define_function_unit "pa8000alu" 2 1
383 (eq_attr "type" "!load,fpload,store,fpstore")
384 (eq_attr "cpu" "8000")) 1 1)
386 ;; Claim floating point ops have a 2 cycle latency, excluding div and
387 ;; sqrt, which are not pipelined and issue to different units.
388 (define_function_unit "pa8000fmac" 2 0
390 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
391 (eq_attr "cpu" "8000")) 2 1)
393 (define_function_unit "pa8000fdiv" 2 1
395 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
396 (eq_attr "cpu" "8000")) 17 17)
398 (define_function_unit "pa8000fdiv" 2 1
400 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
401 (eq_attr "cpu" "8000")) 31 31)
404 ;; Compare instructions.
405 ;; This controls RTL generation and register allocation.
407 ;; We generate RTL for comparisons and branches by having the cmpxx
408 ;; patterns store away the operands. Then, the scc and bcc patterns
409 ;; emit RTL for both the compare and the branch.
412 (define_expand "cmpdi"
414 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
415 (match_operand:DI 1 "register_operand" "")))]
420 hppa_compare_op0 = operands[0];
421 hppa_compare_op1 = operands[1];
422 hppa_branch_type = CMP_SI;
426 (define_expand "cmpsi"
428 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
429 (match_operand:SI 1 "arith5_operand" "")))]
433 hppa_compare_op0 = operands[0];
434 hppa_compare_op1 = operands[1];
435 hppa_branch_type = CMP_SI;
439 (define_expand "cmpsf"
441 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
442 (match_operand:SF 1 "reg_or_0_operand" "")))]
443 "! TARGET_SOFT_FLOAT"
446 hppa_compare_op0 = operands[0];
447 hppa_compare_op1 = operands[1];
448 hppa_branch_type = CMP_SF;
452 (define_expand "cmpdf"
454 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
455 (match_operand:DF 1 "reg_or_0_operand" "")))]
456 "! TARGET_SOFT_FLOAT"
459 hppa_compare_op0 = operands[0];
460 hppa_compare_op1 = operands[1];
461 hppa_branch_type = CMP_DF;
467 (match_operator:CCFP 2 "comparison_operator"
468 [(match_operand:SF 0 "reg_or_0_operand" "fG")
469 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
470 "! TARGET_SOFT_FLOAT"
471 "fcmp,sgl,%Y2 %f0,%f1"
472 [(set_attr "length" "4")
473 (set_attr "type" "fpcc")])
477 (match_operator:CCFP 2 "comparison_operator"
478 [(match_operand:DF 0 "reg_or_0_operand" "fG")
479 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
480 "! TARGET_SOFT_FLOAT"
481 "fcmp,dbl,%Y2 %f0,%f1"
482 [(set_attr "length" "4")
483 (set_attr "type" "fpcc")])
488 [(set (match_operand:SI 0 "register_operand" "")
494 /* fp scc patterns rarely match, and are not a win on the PA. */
495 if (hppa_branch_type != CMP_SI)
497 /* set up operands from compare. */
498 operands[1] = hppa_compare_op0;
499 operands[2] = hppa_compare_op1;
500 /* fall through and generate default code */
504 [(set (match_operand:SI 0 "register_operand" "")
510 /* fp scc patterns rarely match, and are not a win on the PA. */
511 if (hppa_branch_type != CMP_SI)
513 operands[1] = hppa_compare_op0;
514 operands[2] = hppa_compare_op1;
518 [(set (match_operand:SI 0 "register_operand" "")
524 /* fp scc patterns rarely match, and are not a win on the PA. */
525 if (hppa_branch_type != CMP_SI)
527 operands[1] = hppa_compare_op0;
528 operands[2] = hppa_compare_op1;
532 [(set (match_operand:SI 0 "register_operand" "")
538 /* fp scc patterns rarely match, and are not a win on the PA. */
539 if (hppa_branch_type != CMP_SI)
541 operands[1] = hppa_compare_op0;
542 operands[2] = hppa_compare_op1;
546 [(set (match_operand:SI 0 "register_operand" "")
552 /* fp scc patterns rarely match, and are not a win on the PA. */
553 if (hppa_branch_type != CMP_SI)
555 operands[1] = hppa_compare_op0;
556 operands[2] = hppa_compare_op1;
560 [(set (match_operand:SI 0 "register_operand" "")
566 /* fp scc patterns rarely match, and are not a win on the PA. */
567 if (hppa_branch_type != CMP_SI)
569 operands[1] = hppa_compare_op0;
570 operands[2] = hppa_compare_op1;
573 (define_expand "sltu"
574 [(set (match_operand:SI 0 "register_operand" "")
575 (ltu:SI (match_dup 1)
580 if (hppa_branch_type != CMP_SI)
582 operands[1] = hppa_compare_op0;
583 operands[2] = hppa_compare_op1;
586 (define_expand "sgtu"
587 [(set (match_operand:SI 0 "register_operand" "")
588 (gtu:SI (match_dup 1)
593 if (hppa_branch_type != CMP_SI)
595 operands[1] = hppa_compare_op0;
596 operands[2] = hppa_compare_op1;
599 (define_expand "sleu"
600 [(set (match_operand:SI 0 "register_operand" "")
601 (leu:SI (match_dup 1)
606 if (hppa_branch_type != CMP_SI)
608 operands[1] = hppa_compare_op0;
609 operands[2] = hppa_compare_op1;
612 (define_expand "sgeu"
613 [(set (match_operand:SI 0 "register_operand" "")
614 (geu:SI (match_dup 1)
619 if (hppa_branch_type != CMP_SI)
621 operands[1] = hppa_compare_op0;
622 operands[2] = hppa_compare_op1;
625 ;; Instruction canonicalization puts immediate operands second, which
626 ;; is the reverse of what we want.
629 [(set (match_operand:SI 0 "register_operand" "=r")
630 (match_operator:SI 3 "comparison_operator"
631 [(match_operand:SI 1 "register_operand" "r")
632 (match_operand:SI 2 "arith11_operand" "rI")]))]
634 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
635 [(set_attr "type" "binary")
636 (set_attr "length" "8")])
639 [(set (match_operand:DI 0 "register_operand" "=r")
640 (match_operator:DI 3 "comparison_operator"
641 [(match_operand:DI 1 "register_operand" "r")
642 (match_operand:DI 2 "arith11_operand" "rI")]))]
644 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
645 [(set_attr "type" "binary")
646 (set_attr "length" "8")])
648 (define_insn "iorscc"
649 [(set (match_operand:SI 0 "register_operand" "=r")
650 (ior:SI (match_operator:SI 3 "comparison_operator"
651 [(match_operand:SI 1 "register_operand" "r")
652 (match_operand:SI 2 "arith11_operand" "rI")])
653 (match_operator:SI 6 "comparison_operator"
654 [(match_operand:SI 4 "register_operand" "r")
655 (match_operand:SI 5 "arith11_operand" "rI")])))]
657 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
658 [(set_attr "type" "binary")
659 (set_attr "length" "12")])
662 [(set (match_operand:DI 0 "register_operand" "=r")
663 (ior:DI (match_operator:DI 3 "comparison_operator"
664 [(match_operand:DI 1 "register_operand" "r")
665 (match_operand:DI 2 "arith11_operand" "rI")])
666 (match_operator:DI 6 "comparison_operator"
667 [(match_operand:DI 4 "register_operand" "r")
668 (match_operand:DI 5 "arith11_operand" "rI")])))]
670 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
671 [(set_attr "type" "binary")
672 (set_attr "length" "12")])
674 ;; Combiner patterns for common operations performed with the output
675 ;; from an scc insn (negscc and incscc).
676 (define_insn "negscc"
677 [(set (match_operand:SI 0 "register_operand" "=r")
678 (neg:SI (match_operator:SI 3 "comparison_operator"
679 [(match_operand:SI 1 "register_operand" "r")
680 (match_operand:SI 2 "arith11_operand" "rI")])))]
682 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
683 [(set_attr "type" "binary")
684 (set_attr "length" "8")])
687 [(set (match_operand:DI 0 "register_operand" "=r")
688 (neg:DI (match_operator:DI 3 "comparison_operator"
689 [(match_operand:DI 1 "register_operand" "r")
690 (match_operand:DI 2 "arith11_operand" "rI")])))]
692 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
693 [(set_attr "type" "binary")
694 (set_attr "length" "8")])
696 ;; Patterns for adding/subtracting the result of a boolean expression from
697 ;; a register. First we have special patterns that make use of the carry
698 ;; bit, and output only two instructions. For the cases we can't in
699 ;; general do in two instructions, the incscc pattern at the end outputs
700 ;; two or three instructions.
703 [(set (match_operand:SI 0 "register_operand" "=r")
704 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
705 (match_operand:SI 3 "arith11_operand" "rI"))
706 (match_operand:SI 1 "register_operand" "r")))]
708 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
709 [(set_attr "type" "binary")
710 (set_attr "length" "8")])
713 [(set (match_operand:DI 0 "register_operand" "=r")
714 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
715 (match_operand:DI 3 "arith11_operand" "rI"))
716 (match_operand:DI 1 "register_operand" "r")))]
718 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
719 [(set_attr "type" "binary")
720 (set_attr "length" "8")])
722 ; This need only accept registers for op3, since canonicalization
723 ; replaces geu with gtu when op3 is an integer.
725 [(set (match_operand:SI 0 "register_operand" "=r")
726 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
727 (match_operand:SI 3 "register_operand" "r"))
728 (match_operand:SI 1 "register_operand" "r")))]
730 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
731 [(set_attr "type" "binary")
732 (set_attr "length" "8")])
735 [(set (match_operand:DI 0 "register_operand" "=r")
736 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
737 (match_operand:DI 3 "register_operand" "r"))
738 (match_operand:DI 1 "register_operand" "r")))]
740 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
741 [(set_attr "type" "binary")
742 (set_attr "length" "8")])
744 ; Match only integers for op3 here. This is used as canonical form of the
745 ; geu pattern when op3 is an integer. Don't match registers since we can't
746 ; make better code than the general incscc pattern.
748 [(set (match_operand:SI 0 "register_operand" "=r")
749 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
750 (match_operand:SI 3 "int11_operand" "I"))
751 (match_operand:SI 1 "register_operand" "r")))]
753 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
754 [(set_attr "type" "binary")
755 (set_attr "length" "8")])
758 [(set (match_operand:DI 0 "register_operand" "=r")
759 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
760 (match_operand:DI 3 "int11_operand" "I"))
761 (match_operand:DI 1 "register_operand" "r")))]
763 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
764 [(set_attr "type" "binary")
765 (set_attr "length" "8")])
767 (define_insn "incscc"
768 [(set (match_operand:SI 0 "register_operand" "=r,r")
769 (plus:SI (match_operator:SI 4 "comparison_operator"
770 [(match_operand:SI 2 "register_operand" "r,r")
771 (match_operand:SI 3 "arith11_operand" "rI,rI")])
772 (match_operand:SI 1 "register_operand" "0,?r")))]
775 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
776 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
777 [(set_attr "type" "binary,binary")
778 (set_attr "length" "8,12")])
781 [(set (match_operand:DI 0 "register_operand" "=r,r")
782 (plus:DI (match_operator:DI 4 "comparison_operator"
783 [(match_operand:DI 2 "register_operand" "r,r")
784 (match_operand:DI 3 "arith11_operand" "rI,rI")])
785 (match_operand:DI 1 "register_operand" "0,?r")))]
788 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
789 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
790 [(set_attr "type" "binary,binary")
791 (set_attr "length" "8,12")])
794 [(set (match_operand:SI 0 "register_operand" "=r")
795 (minus:SI (match_operand:SI 1 "register_operand" "r")
796 (gtu:SI (match_operand:SI 2 "register_operand" "r")
797 (match_operand:SI 3 "arith11_operand" "rI"))))]
799 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
800 [(set_attr "type" "binary")
801 (set_attr "length" "8")])
804 [(set (match_operand:DI 0 "register_operand" "=r")
805 (minus:DI (match_operand:DI 1 "register_operand" "r")
806 (gtu:DI (match_operand:DI 2 "register_operand" "r")
807 (match_operand:DI 3 "arith11_operand" "rI"))))]
809 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
810 [(set_attr "type" "binary")
811 (set_attr "length" "8")])
814 [(set (match_operand:SI 0 "register_operand" "=r")
815 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
816 (gtu:SI (match_operand:SI 2 "register_operand" "r")
817 (match_operand:SI 3 "arith11_operand" "rI")))
818 (match_operand:SI 4 "register_operand" "r")))]
820 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
821 [(set_attr "type" "binary")
822 (set_attr "length" "8")])
825 [(set (match_operand:DI 0 "register_operand" "=r")
826 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
827 (gtu:DI (match_operand:DI 2 "register_operand" "r")
828 (match_operand:DI 3 "arith11_operand" "rI")))
829 (match_operand:DI 4 "register_operand" "r")))]
831 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
832 [(set_attr "type" "binary")
833 (set_attr "length" "8")])
835 ; This need only accept registers for op3, since canonicalization
836 ; replaces ltu with leu when op3 is an integer.
838 [(set (match_operand:SI 0 "register_operand" "=r")
839 (minus:SI (match_operand:SI 1 "register_operand" "r")
840 (ltu:SI (match_operand:SI 2 "register_operand" "r")
841 (match_operand:SI 3 "register_operand" "r"))))]
843 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
844 [(set_attr "type" "binary")
845 (set_attr "length" "8")])
848 [(set (match_operand:DI 0 "register_operand" "=r")
849 (minus:DI (match_operand:DI 1 "register_operand" "r")
850 (ltu:DI (match_operand:DI 2 "register_operand" "r")
851 (match_operand:DI 3 "register_operand" "r"))))]
853 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
854 [(set_attr "type" "binary")
855 (set_attr "length" "8")])
858 [(set (match_operand:SI 0 "register_operand" "=r")
859 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
860 (ltu:SI (match_operand:SI 2 "register_operand" "r")
861 (match_operand:SI 3 "register_operand" "r")))
862 (match_operand:SI 4 "register_operand" "r")))]
864 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
865 [(set_attr "type" "binary")
866 (set_attr "length" "8")])
869 [(set (match_operand:DI 0 "register_operand" "=r")
870 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
871 (ltu:DI (match_operand:DI 2 "register_operand" "r")
872 (match_operand:DI 3 "register_operand" "r")))
873 (match_operand:DI 4 "register_operand" "r")))]
875 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
876 [(set_attr "type" "binary")
877 (set_attr "length" "8")])
879 ; Match only integers for op3 here. This is used as canonical form of the
880 ; ltu pattern when op3 is an integer. Don't match registers since we can't
881 ; make better code than the general incscc pattern.
883 [(set (match_operand:SI 0 "register_operand" "=r")
884 (minus:SI (match_operand:SI 1 "register_operand" "r")
885 (leu:SI (match_operand:SI 2 "register_operand" "r")
886 (match_operand:SI 3 "int11_operand" "I"))))]
888 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
889 [(set_attr "type" "binary")
890 (set_attr "length" "8")])
893 [(set (match_operand:DI 0 "register_operand" "=r")
894 (minus:DI (match_operand:DI 1 "register_operand" "r")
895 (leu:DI (match_operand:DI 2 "register_operand" "r")
896 (match_operand:DI 3 "int11_operand" "I"))))]
898 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
899 [(set_attr "type" "binary")
900 (set_attr "length" "8")])
903 [(set (match_operand:SI 0 "register_operand" "=r")
904 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
905 (leu:SI (match_operand:SI 2 "register_operand" "r")
906 (match_operand:SI 3 "int11_operand" "I")))
907 (match_operand:SI 4 "register_operand" "r")))]
909 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
910 [(set_attr "type" "binary")
911 (set_attr "length" "8")])
914 [(set (match_operand:DI 0 "register_operand" "=r")
915 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
916 (leu:DI (match_operand:DI 2 "register_operand" "r")
917 (match_operand:DI 3 "int11_operand" "I")))
918 (match_operand:DI 4 "register_operand" "r")))]
920 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
921 [(set_attr "type" "binary")
922 (set_attr "length" "8")])
924 (define_insn "decscc"
925 [(set (match_operand:SI 0 "register_operand" "=r,r")
926 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
927 (match_operator:SI 4 "comparison_operator"
928 [(match_operand:SI 2 "register_operand" "r,r")
929 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
932 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
933 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
934 [(set_attr "type" "binary,binary")
935 (set_attr "length" "8,12")])
938 [(set (match_operand:DI 0 "register_operand" "=r,r")
939 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
940 (match_operator:DI 4 "comparison_operator"
941 [(match_operand:DI 2 "register_operand" "r,r")
942 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
945 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
946 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
947 [(set_attr "type" "binary,binary")
948 (set_attr "length" "8,12")])
950 ; Patterns for max and min. (There is no need for an earlyclobber in the
951 ; last alternative since the middle alternative will match if op0 == op1.)
953 (define_insn "sminsi3"
954 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
955 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
956 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
959 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
960 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
961 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
962 [(set_attr "type" "multi,multi,multi")
963 (set_attr "length" "8,8,8")])
965 (define_insn "smindi3"
966 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
967 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
968 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
971 cmpclr,*> %2,%0,%%r0\;copy %2,%0
972 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
973 cmpclr,*> %1,%r2,%0\;copy %1,%0"
974 [(set_attr "type" "multi,multi,multi")
975 (set_attr "length" "8,8,8")])
977 (define_insn "uminsi3"
978 [(set (match_operand:SI 0 "register_operand" "=r,r")
979 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
980 (match_operand:SI 2 "arith11_operand" "r,I")))]
983 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
984 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
985 [(set_attr "type" "multi,multi")
986 (set_attr "length" "8,8")])
988 (define_insn "umindi3"
989 [(set (match_operand:DI 0 "register_operand" "=r,r")
990 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
991 (match_operand:DI 2 "arith11_operand" "r,I")))]
994 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
995 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
996 [(set_attr "type" "multi,multi")
997 (set_attr "length" "8,8")])
999 (define_insn "smaxsi3"
1000 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1001 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1002 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1005 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1006 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1007 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1008 [(set_attr "type" "multi,multi,multi")
1009 (set_attr "length" "8,8,8")])
1011 (define_insn "smaxdi3"
1012 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1013 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1014 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1017 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1018 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1019 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1020 [(set_attr "type" "multi,multi,multi")
1021 (set_attr "length" "8,8,8")])
1023 (define_insn "umaxsi3"
1024 [(set (match_operand:SI 0 "register_operand" "=r,r")
1025 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1026 (match_operand:SI 2 "arith11_operand" "r,I")))]
1029 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1030 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1031 [(set_attr "type" "multi,multi")
1032 (set_attr "length" "8,8")])
1034 (define_insn "umaxdi3"
1035 [(set (match_operand:DI 0 "register_operand" "=r,r")
1036 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1037 (match_operand:DI 2 "arith11_operand" "r,I")))]
1040 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1041 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1042 [(set_attr "type" "multi,multi")
1043 (set_attr "length" "8,8")])
1045 (define_insn "abssi2"
1046 [(set (match_operand:SI 0 "register_operand" "=r")
1047 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1049 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1050 [(set_attr "type" "multi")
1051 (set_attr "length" "8")])
1053 (define_insn "absdi2"
1054 [(set (match_operand:DI 0 "register_operand" "=r")
1055 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1057 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1058 [(set_attr "type" "multi")
1059 (set_attr "length" "8")])
1061 ;;; Experimental conditional move patterns
1063 (define_expand "movsicc"
1064 [(set (match_operand:SI 0 "register_operand" "")
1066 (match_operator 1 "comparison_operator"
1069 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1070 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1074 enum rtx_code code = GET_CODE (operands[1]);
1076 if (hppa_branch_type != CMP_SI)
1079 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1080 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1083 /* operands[1] is currently the result of compare_from_rtx. We want to
1084 emit a compare of the original operands. */
1085 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1086 operands[4] = hppa_compare_op0;
1087 operands[5] = hppa_compare_op1;
1090 ;; We used to accept any register for op1.
1092 ;; However, it loses sometimes because the compiler will end up using
1093 ;; different registers for op0 and op1 in some critical cases. local-alloc
1094 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1096 ;; If/when global register allocation supports tying we should allow any
1097 ;; register for op1 again.
1099 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1101 (match_operator 2 "comparison_operator"
1102 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1103 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1104 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1108 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1109 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1110 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1111 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1112 [(set_attr "type" "multi,multi,multi,nullshift")
1113 (set_attr "length" "8,8,8,8")])
1116 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1118 (match_operator 5 "comparison_operator"
1119 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1120 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1121 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1122 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1125 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1126 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1127 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1128 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1129 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1130 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1131 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1132 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1133 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1134 (set_attr "length" "8,8,8,8,8,8,8,8")])
1136 (define_expand "movdicc"
1137 [(set (match_operand:DI 0 "register_operand" "")
1139 (match_operator 1 "comparison_operator"
1142 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1143 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1147 enum rtx_code code = GET_CODE (operands[1]);
1149 if (hppa_branch_type != CMP_SI)
1152 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1153 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1156 /* operands[1] is currently the result of compare_from_rtx. We want to
1157 emit a compare of the original operands. */
1158 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1159 operands[4] = hppa_compare_op0;
1160 operands[5] = hppa_compare_op1;
1163 ; We need the first constraint alternative in order to avoid
1164 ; earlyclobbers on all other alternatives.
1166 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1168 (match_operator 2 "comparison_operator"
1169 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1170 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1171 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1175 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1176 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1177 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1178 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1179 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1180 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1181 (set_attr "length" "8,8,8,8,8")])
1184 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1186 (match_operator 5 "comparison_operator"
1187 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1188 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1189 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1190 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1193 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1194 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1195 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1196 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1197 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1198 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1199 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1200 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1201 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1202 (set_attr "length" "8,8,8,8,8,8,8,8")])
1204 ;; Conditional Branches
1206 (define_expand "beq"
1208 (if_then_else (eq (match_dup 1) (match_dup 2))
1209 (label_ref (match_operand 0 "" ""))
1214 if (hppa_branch_type != CMP_SI)
1216 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1217 emit_bcond_fp (NE, operands[0]);
1220 /* set up operands from compare. */
1221 operands[1] = hppa_compare_op0;
1222 operands[2] = hppa_compare_op1;
1223 /* fall through and generate default code */
1226 (define_expand "bne"
1228 (if_then_else (ne (match_dup 1) (match_dup 2))
1229 (label_ref (match_operand 0 "" ""))
1234 if (hppa_branch_type != CMP_SI)
1236 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1237 emit_bcond_fp (NE, operands[0]);
1240 operands[1] = hppa_compare_op0;
1241 operands[2] = hppa_compare_op1;
1244 (define_expand "bgt"
1246 (if_then_else (gt (match_dup 1) (match_dup 2))
1247 (label_ref (match_operand 0 "" ""))
1252 if (hppa_branch_type != CMP_SI)
1254 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1255 emit_bcond_fp (NE, operands[0]);
1258 operands[1] = hppa_compare_op0;
1259 operands[2] = hppa_compare_op1;
1262 (define_expand "blt"
1264 (if_then_else (lt (match_dup 1) (match_dup 2))
1265 (label_ref (match_operand 0 "" ""))
1270 if (hppa_branch_type != CMP_SI)
1272 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1273 emit_bcond_fp (NE, operands[0]);
1276 operands[1] = hppa_compare_op0;
1277 operands[2] = hppa_compare_op1;
1280 (define_expand "bge"
1282 (if_then_else (ge (match_dup 1) (match_dup 2))
1283 (label_ref (match_operand 0 "" ""))
1288 if (hppa_branch_type != CMP_SI)
1290 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1291 emit_bcond_fp (NE, operands[0]);
1294 operands[1] = hppa_compare_op0;
1295 operands[2] = hppa_compare_op1;
1298 (define_expand "ble"
1300 (if_then_else (le (match_dup 1) (match_dup 2))
1301 (label_ref (match_operand 0 "" ""))
1306 if (hppa_branch_type != CMP_SI)
1308 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1309 emit_bcond_fp (NE, operands[0]);
1312 operands[1] = hppa_compare_op0;
1313 operands[2] = hppa_compare_op1;
1316 (define_expand "bgtu"
1318 (if_then_else (gtu (match_dup 1) (match_dup 2))
1319 (label_ref (match_operand 0 "" ""))
1324 if (hppa_branch_type != CMP_SI)
1326 operands[1] = hppa_compare_op0;
1327 operands[2] = hppa_compare_op1;
1330 (define_expand "bltu"
1332 (if_then_else (ltu (match_dup 1) (match_dup 2))
1333 (label_ref (match_operand 0 "" ""))
1338 if (hppa_branch_type != CMP_SI)
1340 operands[1] = hppa_compare_op0;
1341 operands[2] = hppa_compare_op1;
1344 (define_expand "bgeu"
1346 (if_then_else (geu (match_dup 1) (match_dup 2))
1347 (label_ref (match_operand 0 "" ""))
1352 if (hppa_branch_type != CMP_SI)
1354 operands[1] = hppa_compare_op0;
1355 operands[2] = hppa_compare_op1;
1358 (define_expand "bleu"
1360 (if_then_else (leu (match_dup 1) (match_dup 2))
1361 (label_ref (match_operand 0 "" ""))
1366 if (hppa_branch_type != CMP_SI)
1368 operands[1] = hppa_compare_op0;
1369 operands[2] = hppa_compare_op1;
1372 ;; Match the branch patterns.
1375 ;; Note a long backward conditional branch with an annulled delay slot
1376 ;; has a length of 12.
1380 (match_operator 3 "comparison_operator"
1381 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1382 (match_operand:SI 2 "arith5_operand" "rL")])
1383 (label_ref (match_operand 0 "" ""))
1388 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1389 get_attr_length (insn), 0, insn);
1391 [(set_attr "type" "cbranch")
1392 (set (attr "length")
1393 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1396 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1399 (eq (symbol_ref "flag_pic") (const_int 0))
1403 ;; Match the negated branch.
1408 (match_operator 3 "comparison_operator"
1409 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1410 (match_operand:SI 2 "arith5_operand" "rL")])
1412 (label_ref (match_operand 0 "" ""))))]
1416 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1417 get_attr_length (insn), 1, insn);
1419 [(set_attr "type" "cbranch")
1420 (set (attr "length")
1421 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1424 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1427 (eq (symbol_ref "flag_pic") (const_int 0))
1434 (match_operator 3 "comparison_operator"
1435 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1436 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1437 (label_ref (match_operand 0 "" ""))
1442 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1443 get_attr_length (insn), 0, insn);
1445 [(set_attr "type" "cbranch")
1446 (set (attr "length")
1447 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1450 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1453 (eq (symbol_ref "flag_pic") (const_int 0))
1457 ;; Match the negated branch.
1462 (match_operator 3 "comparison_operator"
1463 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1464 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1466 (label_ref (match_operand 0 "" ""))))]
1470 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1471 get_attr_length (insn), 1, insn);
1473 [(set_attr "type" "cbranch")
1474 (set (attr "length")
1475 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1478 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1481 (eq (symbol_ref "flag_pic") (const_int 0))
1487 (match_operator 3 "cmpib_comparison_operator"
1488 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1489 (match_operand:DI 2 "arith5_operand" "rL")])
1490 (label_ref (match_operand 0 "" ""))
1495 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1496 get_attr_length (insn), 0, insn);
1498 [(set_attr "type" "cbranch")
1499 (set (attr "length")
1500 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1503 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1506 (eq (symbol_ref "flag_pic") (const_int 0))
1510 ;; Match the negated branch.
1515 (match_operator 3 "cmpib_comparison_operator"
1516 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1517 (match_operand:DI 2 "arith5_operand" "rL")])
1519 (label_ref (match_operand 0 "" ""))))]
1523 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1524 get_attr_length (insn), 1, insn);
1526 [(set_attr "type" "cbranch")
1527 (set (attr "length")
1528 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1531 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1534 (eq (symbol_ref "flag_pic") (const_int 0))
1538 ;; Branch on Bit patterns.
1542 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1544 (match_operand:SI 1 "uint5_operand" ""))
1546 (label_ref (match_operand 2 "" ""))
1551 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1552 get_attr_length (insn), 0, insn, 0);
1554 [(set_attr "type" "cbranch")
1555 (set (attr "length")
1556 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1564 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1566 (match_operand:DI 1 "uint32_operand" ""))
1568 (label_ref (match_operand 2 "" ""))
1573 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1574 get_attr_length (insn), 0, insn, 0);
1576 [(set_attr "type" "cbranch")
1577 (set (attr "length")
1578 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1586 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1588 (match_operand:SI 1 "uint5_operand" ""))
1591 (label_ref (match_operand 2 "" ""))))]
1595 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1596 get_attr_length (insn), 1, insn, 0);
1598 [(set_attr "type" "cbranch")
1599 (set (attr "length")
1600 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1608 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1610 (match_operand:DI 1 "uint32_operand" ""))
1613 (label_ref (match_operand 2 "" ""))))]
1617 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1618 get_attr_length (insn), 1, insn, 0);
1620 [(set_attr "type" "cbranch")
1621 (set (attr "length")
1622 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1630 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1632 (match_operand:SI 1 "uint5_operand" ""))
1634 (label_ref (match_operand 2 "" ""))
1639 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1640 get_attr_length (insn), 0, insn, 1);
1642 [(set_attr "type" "cbranch")
1643 (set (attr "length")
1644 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1652 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1654 (match_operand:DI 1 "uint32_operand" ""))
1656 (label_ref (match_operand 2 "" ""))
1661 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1662 get_attr_length (insn), 0, insn, 1);
1664 [(set_attr "type" "cbranch")
1665 (set (attr "length")
1666 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1674 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1676 (match_operand:SI 1 "uint5_operand" ""))
1679 (label_ref (match_operand 2 "" ""))))]
1683 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1684 get_attr_length (insn), 1, insn, 1);
1686 [(set_attr "type" "cbranch")
1687 (set (attr "length")
1688 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1696 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1698 (match_operand:DI 1 "uint32_operand" ""))
1701 (label_ref (match_operand 2 "" ""))))]
1705 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1706 get_attr_length (insn), 1, insn, 1);
1708 [(set_attr "type" "cbranch")
1709 (set (attr "length")
1710 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1715 ;; Branch on Variable Bit patterns.
1719 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1721 (match_operand:SI 1 "register_operand" "q"))
1723 (label_ref (match_operand 2 "" ""))
1728 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1729 get_attr_length (insn), 0, insn, 0);
1731 [(set_attr "type" "cbranch")
1732 (set (attr "length")
1733 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1741 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1743 (match_operand:DI 1 "register_operand" "q"))
1745 (label_ref (match_operand 2 "" ""))
1750 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1751 get_attr_length (insn), 0, insn, 0);
1753 [(set_attr "type" "cbranch")
1754 (set (attr "length")
1755 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1763 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1765 (match_operand:SI 1 "register_operand" "q"))
1768 (label_ref (match_operand 2 "" ""))))]
1772 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1773 get_attr_length (insn), 1, insn, 0);
1775 [(set_attr "type" "cbranch")
1776 (set (attr "length")
1777 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1785 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1787 (match_operand:DI 1 "register_operand" "q"))
1790 (label_ref (match_operand 2 "" ""))))]
1794 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1795 get_attr_length (insn), 1, insn, 0);
1797 [(set_attr "type" "cbranch")
1798 (set (attr "length")
1799 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1807 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1809 (match_operand:SI 1 "register_operand" "q"))
1811 (label_ref (match_operand 2 "" ""))
1816 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1817 get_attr_length (insn), 0, insn, 1);
1819 [(set_attr "type" "cbranch")
1820 (set (attr "length")
1821 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1829 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1831 (match_operand:DI 1 "register_operand" "q"))
1833 (label_ref (match_operand 2 "" ""))
1838 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1839 get_attr_length (insn), 0, insn, 1);
1841 [(set_attr "type" "cbranch")
1842 (set (attr "length")
1843 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1851 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1853 (match_operand:SI 1 "register_operand" "q"))
1856 (label_ref (match_operand 2 "" ""))))]
1860 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1861 get_attr_length (insn), 1, insn, 1);
1863 [(set_attr "type" "cbranch")
1864 (set (attr "length")
1865 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1873 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1875 (match_operand:DI 1 "register_operand" "q"))
1878 (label_ref (match_operand 2 "" ""))))]
1882 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1883 get_attr_length (insn), 1, insn, 1);
1885 [(set_attr "type" "cbranch")
1886 (set (attr "length")
1887 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1892 ;; Floating point branches
1894 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1895 (label_ref (match_operand 0 "" ""))
1897 "! TARGET_SOFT_FLOAT"
1900 if (INSN_ANNULLED_BRANCH_P (insn))
1901 return \"ftest\;b,n %0\";
1903 return \"ftest\;b%* %0\";
1905 [(set_attr "type" "fbranch")
1906 (set_attr "length" "8")])
1909 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1911 (label_ref (match_operand 0 "" ""))))]
1912 "! TARGET_SOFT_FLOAT"
1915 if (INSN_ANNULLED_BRANCH_P (insn))
1916 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
1918 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
1920 [(set_attr "type" "fbranch")
1921 (set_attr "length" "12")])
1923 ;; Move instructions
1925 (define_expand "movsi"
1926 [(set (match_operand:SI 0 "general_operand" "")
1927 (match_operand:SI 1 "general_operand" ""))]
1931 if (emit_move_sequence (operands, SImode, 0))
1935 ;; Reloading an SImode or DImode value requires a scratch register if
1936 ;; going in to or out of float point registers.
1938 (define_expand "reload_insi"
1939 [(set (match_operand:SI 0 "register_operand" "=Z")
1940 (match_operand:SI 1 "non_hard_reg_operand" ""))
1941 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
1945 if (emit_move_sequence (operands, SImode, operands[2]))
1948 /* We don't want the clobber emitted, so handle this ourselves. */
1949 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1953 (define_expand "reload_outsi"
1954 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
1955 (match_operand:SI 1 "register_operand" "Z"))
1956 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
1960 if (emit_move_sequence (operands, SImode, operands[2]))
1963 /* We don't want the clobber emitted, so handle this ourselves. */
1964 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1968 ;;; pic symbol references
1971 [(set (match_operand:SI 0 "register_operand" "=r")
1972 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
1973 (match_operand:SI 2 "symbolic_operand" ""))))]
1974 "flag_pic && operands[1] == pic_offset_table_rtx"
1976 [(set_attr "type" "load")
1977 (set_attr "length" "4")])
1980 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
1981 "=r,r,r,r,r,Q,*q,!f,f,*TR")
1982 (match_operand:SI 1 "move_operand"
1983 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
1984 "(register_operand (operands[0], SImode)
1985 || reg_or_0_operand (operands[1], SImode))
1986 && ! TARGET_SOFT_FLOAT"
1991 {zdepi|depwi,z} %Z1,%0
1998 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
1999 (set_attr "pa_combine_type" "addmove")
2000 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
2003 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2005 (match_operand:SI 1 "move_operand"
2006 "r,J,N,K,RQ,rM,rM"))]
2007 "(register_operand (operands[0], SImode)
2008 || reg_or_0_operand (operands[1], SImode))
2009 && TARGET_SOFT_FLOAT"
2014 {zdepi|depwi,z} %Z1,%0
2018 [(set_attr "type" "move,move,move,move,load,store,move")
2019 (set_attr "pa_combine_type" "addmove")
2020 (set_attr "length" "4,4,4,4,4,4,4")])
2023 [(set (match_operand:SI 0 "register_operand" "=r")
2024 (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2025 (match_operand:SI 2 "register_operand" "r"))))]
2026 "! TARGET_DISABLE_INDEXING"
2027 "{ldwx|ldw} %2(%1),%0"
2028 [(set_attr "type" "load")
2029 (set_attr "length" "4")])
2032 [(set (match_operand:SI 0 "register_operand" "=r")
2033 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2034 (match_operand:SI 2 "basereg_operand" "r"))))]
2035 "! TARGET_DISABLE_INDEXING"
2036 "{ldwx|ldw} %1(%2),%0"
2037 [(set_attr "type" "load")
2038 (set_attr "length" "4")])
2040 ;; Load or store with base-register modification.
2042 (define_expand "pre_load"
2043 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2044 (mem (plus (match_operand 1 "register_operand" "")
2045 (match_operand 2 "pre_cint_operand" ""))))
2047 (plus (match_dup 1) (match_dup 2)))])]
2053 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2056 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2060 (define_insn "pre_ldw"
2061 [(set (match_operand:SI 0 "register_operand" "=r")
2062 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2063 (match_operand:SI 2 "pre_cint_operand" ""))))
2065 (plus:SI (match_dup 1) (match_dup 2)))]
2069 if (INTVAL (operands[2]) < 0)
2070 return \"{ldwm|ldw,mb} %2(%1),%0\";
2071 return \"{ldws|ldw},mb %2(%1),%0\";
2073 [(set_attr "type" "load")
2074 (set_attr "length" "4")])
2076 (define_insn "pre_ldd"
2077 [(set (match_operand:DI 0 "register_operand" "=r")
2078 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2079 (match_operand:DI 2 "pre_cint_operand" ""))))
2081 (plus:DI (match_dup 1) (match_dup 2)))]
2084 [(set_attr "type" "load")
2085 (set_attr "length" "4")])
2088 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2089 (match_operand:SI 1 "pre_cint_operand" "")))
2090 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2092 (plus:SI (match_dup 0) (match_dup 1)))]
2096 if (INTVAL (operands[1]) < 0)
2097 return \"{stwm|stw,mb} %r2,%1(%0)\";
2098 return \"{stws|stw},mb %r2,%1(%0)\";
2100 [(set_attr "type" "store")
2101 (set_attr "length" "4")])
2104 [(set (match_operand:SI 0 "register_operand" "=r")
2105 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2107 (plus:SI (match_dup 1)
2108 (match_operand:SI 2 "post_cint_operand" "")))]
2112 if (INTVAL (operands[2]) > 0)
2113 return \"{ldwm|ldw,ma} %2(%1),%0\";
2114 return \"{ldws|ldw},ma %2(%1),%0\";
2116 [(set_attr "type" "load")
2117 (set_attr "length" "4")])
2119 (define_expand "post_store"
2120 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2121 (match_operand 1 "reg_or_0_operand" ""))
2124 (match_operand 2 "post_cint_operand" "")))])]
2130 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2133 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2137 (define_insn "post_stw"
2138 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2139 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2141 (plus:SI (match_dup 0)
2142 (match_operand:SI 2 "post_cint_operand" "")))]
2146 if (INTVAL (operands[2]) > 0)
2147 return \"{stwm|stw,ma} %r1,%2(%0)\";
2148 return \"{stws|stw},ma %r1,%2(%0)\";
2150 [(set_attr "type" "store")
2151 (set_attr "length" "4")])
2153 (define_insn "post_std"
2154 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2155 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2157 (plus:DI (match_dup 0)
2158 (match_operand:DI 2 "post_cint_operand" "")))]
2161 [(set_attr "type" "store")
2162 (set_attr "length" "4")])
2164 ;; For loading the address of a label while generating PIC code.
2165 ;; Note since this pattern can be created at reload time (via movsi), all
2166 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2168 [(set (match_operand 0 "pmode_register_operand" "=a")
2169 (match_operand 1 "pic_label_operand" ""))]
2173 rtx label_rtx = gen_label_rtx ();
2175 extern FILE *asm_out_file;
2177 xoperands[0] = operands[0];
2178 xoperands[1] = operands[1];
2179 xoperands[2] = label_rtx;
2180 output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
2181 output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
2182 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2183 CODE_LABEL_NUMBER (label_rtx));
2185 /* If we're trying to load the address of a label that happens to be
2186 close, then we can use a shorter sequence. */
2187 if (GET_CODE (operands[1]) == LABEL_REF
2188 && INSN_ADDRESSES_SET_P ()
2189 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2190 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2192 /* Prefixing with R% here is wrong, it extracts just 11 bits and is
2193 always non-negative. */
2194 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2198 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2199 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2203 [(set_attr "type" "multi")
2204 (set_attr "length" "16")]) ; 12 or 16
2207 [(set (match_operand:SI 0 "register_operand" "=a")
2208 (plus:SI (match_operand:SI 1 "register_operand" "r")
2209 (high:SI (match_operand 2 "" ""))))]
2210 "symbolic_operand (operands[2], Pmode)
2211 && ! function_label_operand (operands[2], Pmode)
2214 [(set_attr "type" "binary")
2215 (set_attr "length" "4")])
2218 [(set (match_operand:DI 0 "register_operand" "=a")
2219 (plus:DI (match_operand:DI 1 "register_operand" "r")
2220 (high:DI (match_operand 2 "" ""))))]
2221 "symbolic_operand (operands[2], Pmode)
2222 && ! function_label_operand (operands[2], Pmode)
2226 [(set_attr "type" "binary")
2227 (set_attr "length" "4")])
2229 ; We need this to make sure CSE doesn't simplify a memory load with a
2230 ; symbolic address, whose content it think it knows. For PIC, what CSE
2231 ; think is the real value will be the address of that value.
2233 [(set (match_operand:SI 0 "register_operand" "=r")
2235 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2237 [(match_operand:SI 2 "symbolic_operand" "")] 0))))]
2243 return \"ldw RT'%G2(%1),%0\";
2245 [(set_attr "type" "load")
2246 (set_attr "length" "4")])
2249 [(set (match_operand:DI 0 "register_operand" "=r")
2251 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2253 [(match_operand:DI 2 "symbolic_operand" "")] 0))))]
2259 return \"ldd RT'%G2(%1),%0\";
2261 [(set_attr "type" "load")
2262 (set_attr "length" "4")])
2264 ;; Always use addil rather than ldil;add sequences. This allows the
2265 ;; HP linker to eliminate the dp relocation if the symbolic operand
2266 ;; lives in the TEXT space.
2268 [(set (match_operand:SI 0 "register_operand" "=a")
2269 (high:SI (match_operand 1 "" "")))]
2270 "symbolic_operand (operands[1], Pmode)
2271 && ! function_label_operand (operands[1], Pmode)
2272 && ! read_only_operand (operands[1], Pmode)
2276 if (TARGET_LONG_LOAD_STORE)
2277 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2279 return \"addil LR'%H1,%%r27\";
2281 [(set_attr "type" "binary")
2282 (set (attr "length")
2283 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2288 ;; This is for use in the prologue/epilogue code. We need it
2289 ;; to add large constants to a stack pointer or frame pointer.
2290 ;; Because of the additional %r1 pressure, we probably do not
2291 ;; want to use this in general code, so make it available
2292 ;; only after reload.
2294 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2295 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2296 (high:SI (match_operand 2 "const_int_operand" ""))))]
2300 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2301 [(set_attr "type" "binary,binary")
2302 (set_attr "length" "4,8")])
2305 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2306 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2307 (high:DI (match_operand 2 "const_int_operand" ""))))]
2308 "reload_completed && TARGET_64BIT"
2311 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2312 [(set_attr "type" "binary,binary")
2313 (set_attr "length" "4,8")])
2316 [(set (match_operand:SI 0 "register_operand" "=r")
2317 (high:SI (match_operand 1 "" "")))]
2318 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2319 && !is_function_label_plus_const (operands[1])"
2322 if (symbolic_operand (operands[1], Pmode))
2323 return \"ldil LR'%H1,%0\";
2325 return \"ldil L'%G1,%0\";
2327 [(set_attr "type" "move")
2328 (set_attr "length" "4")])
2331 [(set (match_operand:DI 0 "register_operand" "=r")
2332 (high:DI (match_operand 1 "const_int_operand" "")))]
2335 [(set_attr "type" "move")
2336 (set_attr "length" "4")])
2339 [(set (match_operand:DI 0 "register_operand" "=r")
2340 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2341 (match_operand:DI 2 "const_int_operand" "i")))]
2344 [(set_attr "type" "move")
2345 (set_attr "length" "4")])
2348 [(set (match_operand:SI 0 "register_operand" "=r")
2349 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2350 (match_operand:SI 2 "immediate_operand" "i")))]
2351 "!is_function_label_plus_const (operands[2])"
2354 if (flag_pic && symbolic_operand (operands[2], Pmode))
2356 else if (symbolic_operand (operands[2], Pmode))
2357 return \"ldo RR'%G2(%1),%0\";
2359 return \"ldo R'%G2(%1),%0\";
2361 [(set_attr "type" "move")
2362 (set_attr "length" "4")])
2364 ;; Now that a symbolic_address plus a constant is broken up early
2365 ;; in the compilation phase (for better CSE) we need a special
2366 ;; combiner pattern to load the symbolic address plus the constant
2367 ;; in only 2 instructions. (For cases where the symbolic address
2368 ;; was not a common subexpression.)
2370 [(set (match_operand:SI 0 "register_operand" "")
2371 (match_operand:SI 1 "symbolic_operand" ""))
2372 (clobber (match_operand:SI 2 "register_operand" ""))]
2373 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2374 [(set (match_dup 2) (high:SI (match_dup 1)))
2375 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2378 ;; hppa_legitimize_address goes to a great deal of trouble to
2379 ;; create addresses which use indexing. In some cases, this
2380 ;; is a lose because there isn't any store instructions which
2381 ;; allow indexed addresses (with integer register source).
2383 ;; These define_splits try to turn a 3 insn store into
2384 ;; a 2 insn store with some creative RTL rewriting.
2386 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2387 (match_operand:SI 1 "shadd_operand" ""))
2388 (plus:SI (match_operand:SI 2 "register_operand" "")
2389 (match_operand:SI 3 "const_int_operand" ""))))
2390 (match_operand:SI 4 "register_operand" ""))
2391 (clobber (match_operand:SI 5 "register_operand" ""))]
2393 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2395 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2399 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2400 (match_operand:SI 1 "shadd_operand" ""))
2401 (plus:SI (match_operand:SI 2 "register_operand" "")
2402 (match_operand:SI 3 "const_int_operand" ""))))
2403 (match_operand:HI 4 "register_operand" ""))
2404 (clobber (match_operand:SI 5 "register_operand" ""))]
2406 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2408 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2412 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2413 (match_operand:SI 1 "shadd_operand" ""))
2414 (plus:SI (match_operand:SI 2 "register_operand" "")
2415 (match_operand:SI 3 "const_int_operand" ""))))
2416 (match_operand:QI 4 "register_operand" ""))
2417 (clobber (match_operand:SI 5 "register_operand" ""))]
2419 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2421 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2424 (define_expand "movhi"
2425 [(set (match_operand:HI 0 "general_operand" "")
2426 (match_operand:HI 1 "general_operand" ""))]
2430 if (emit_move_sequence (operands, HImode, 0))
2435 [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2436 (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2437 "register_operand (operands[0], HImode)
2438 || reg_or_0_operand (operands[1], HImode)"
2443 {zdepi|depwi,z} %Z1,%0
2448 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2449 (set_attr "pa_combine_type" "addmove")
2450 (set_attr "length" "4,4,4,4,4,4,4,4")])
2453 [(set (match_operand:HI 0 "register_operand" "=r")
2454 (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2455 (match_operand:SI 2 "register_operand" "r"))))]
2456 "! TARGET_DISABLE_INDEXING"
2457 "{ldhx|ldh} %2(%1),%0"
2458 [(set_attr "type" "load")
2459 (set_attr "length" "4")])
2462 [(set (match_operand:HI 0 "register_operand" "=r")
2463 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
2464 (match_operand:SI 2 "basereg_operand" "r"))))]
2465 "! TARGET_DISABLE_INDEXING"
2466 "{ldhx|ldh} %1(%2),%0"
2467 [(set_attr "type" "load")
2468 (set_attr "length" "4")])
2470 ; Now zero extended variants.
2472 [(set (match_operand:SI 0 "register_operand" "=r")
2473 (zero_extend:SI (mem:HI
2475 (match_operand:SI 1 "basereg_operand" "r")
2476 (match_operand:SI 2 "register_operand" "r")))))]
2477 "! TARGET_DISABLE_INDEXING"
2478 "{ldhx|ldh} %2(%1),%0"
2479 [(set_attr "type" "load")
2480 (set_attr "length" "4")])
2483 [(set (match_operand:SI 0 "register_operand" "=r")
2484 (zero_extend:SI (mem:HI
2486 (match_operand:SI 1 "register_operand" "r")
2487 (match_operand:SI 2 "basereg_operand" "r")))))]
2488 "! TARGET_DISABLE_INDEXING"
2489 "{ldhx|ldh} %1(%2),%0"
2490 [(set_attr "type" "load")
2491 (set_attr "length" "4")])
2494 [(set (match_operand:HI 0 "register_operand" "=r")
2495 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2496 (match_operand:SI 2 "int5_operand" "L"))))
2498 (plus:SI (match_dup 1) (match_dup 2)))]
2500 "{ldhs|ldh},mb %2(%1),%0"
2501 [(set_attr "type" "load")
2502 (set_attr "length" "4")])
2504 ; And a zero extended variant.
2506 [(set (match_operand:SI 0 "register_operand" "=r")
2507 (zero_extend:SI (mem:HI
2509 (match_operand:SI 1 "register_operand" "+r")
2510 (match_operand:SI 2 "int5_operand" "L")))))
2512 (plus:SI (match_dup 1) (match_dup 2)))]
2514 "{ldhs|ldh},mb %2(%1),%0"
2515 [(set_attr "type" "load")
2516 (set_attr "length" "4")])
2519 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2520 (match_operand:SI 1 "int5_operand" "L")))
2521 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2523 (plus:SI (match_dup 0) (match_dup 1)))]
2525 "{sths|sth},mb %r2,%1(%0)"
2526 [(set_attr "type" "store")
2527 (set_attr "length" "4")])
2530 [(set (match_operand:HI 0 "register_operand" "=r")
2531 (high:HI (match_operand 1 "const_int_operand" "")))]
2534 [(set_attr "type" "move")
2535 (set_attr "length" "4")])
2538 [(set (match_operand:HI 0 "register_operand" "=r")
2539 (lo_sum:HI (match_operand:HI 1 "register_operand" "r")
2540 (match_operand 2 "const_int_operand" "")))]
2543 [(set_attr "type" "move")
2544 (set_attr "length" "4")])
2546 (define_expand "movqi"
2547 [(set (match_operand:QI 0 "general_operand" "")
2548 (match_operand:QI 1 "general_operand" ""))]
2552 if (emit_move_sequence (operands, QImode, 0))
2557 [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2558 (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2559 "register_operand (operands[0], QImode)
2560 || reg_or_0_operand (operands[1], QImode)"
2565 {zdepi|depwi,z} %Z1,%0
2570 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2571 (set_attr "pa_combine_type" "addmove")
2572 (set_attr "length" "4,4,4,4,4,4,4,4")])
2575 [(set (match_operand:QI 0 "register_operand" "=r")
2576 (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2577 (match_operand:SI 2 "register_operand" "r"))))]
2578 "! TARGET_DISABLE_INDEXING"
2579 "{ldbx|ldb} %2(%1),%0"
2580 [(set_attr "type" "load")
2581 (set_attr "length" "4")])
2584 [(set (match_operand:QI 0 "register_operand" "=r")
2585 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
2586 (match_operand:SI 2 "basereg_operand" "r"))))]
2587 "! TARGET_DISABLE_INDEXING"
2588 "{ldbx|ldb} %1(%2),%0"
2589 [(set_attr "type" "load")
2590 (set_attr "length" "4")])
2592 ; Indexed byte load with zero extension to SImode or HImode.
2594 [(set (match_operand:SI 0 "register_operand" "=r")
2595 (zero_extend:SI (mem:QI
2597 (match_operand:SI 1 "basereg_operand" "r")
2598 (match_operand:SI 2 "register_operand" "r")))))]
2599 "! TARGET_DISABLE_INDEXING"
2600 "{ldbx|ldb} %2(%1),%0"
2601 [(set_attr "type" "load")
2602 (set_attr "length" "4")])
2605 [(set (match_operand:SI 0 "register_operand" "=r")
2606 (zero_extend:SI (mem:QI
2608 (match_operand:SI 1 "register_operand" "r")
2609 (match_operand:SI 2 "basereg_operand" "r")))))]
2610 "! TARGET_DISABLE_INDEXING"
2611 "{ldbx|ldb} %1(%2),%0"
2612 [(set_attr "type" "load")
2613 (set_attr "length" "4")])
2616 [(set (match_operand:HI 0 "register_operand" "=r")
2617 (zero_extend:HI (mem:QI
2619 (match_operand:SI 1 "basereg_operand" "r")
2620 (match_operand:SI 2 "register_operand" "r")))))]
2621 "! TARGET_DISABLE_INDEXING"
2622 "{ldbx|ldb} %2(%1),%0"
2623 [(set_attr "type" "load")
2624 (set_attr "length" "4")])
2627 [(set (match_operand:HI 0 "register_operand" "=r")
2628 (zero_extend:HI (mem:QI
2630 (match_operand:SI 1 "register_operand" "r")
2631 (match_operand:SI 2 "basereg_operand" "r")))))]
2632 "! TARGET_DISABLE_INDEXING"
2633 "{ldbx|ldb} %1(%2),%0"
2634 [(set_attr "type" "load")
2635 (set_attr "length" "4")])
2638 [(set (match_operand:QI 0 "register_operand" "=r")
2639 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2640 (match_operand:SI 2 "int5_operand" "L"))))
2641 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2643 "{ldbs|ldb},mb %2(%1),%0"
2644 [(set_attr "type" "load")
2645 (set_attr "length" "4")])
2647 ; Now the same thing with zero extensions.
2649 [(set (match_operand:SI 0 "register_operand" "=r")
2650 (zero_extend:SI (mem:QI (plus:SI
2651 (match_operand:SI 1 "register_operand" "+r")
2652 (match_operand:SI 2 "int5_operand" "L")))))
2653 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2655 "{ldbs|ldb},mb %2(%1),%0"
2656 [(set_attr "type" "load")
2657 (set_attr "length" "4")])
2660 [(set (match_operand:HI 0 "register_operand" "=r")
2661 (zero_extend:HI (mem:QI (plus:SI
2662 (match_operand:SI 1 "register_operand" "+r")
2663 (match_operand:SI 2 "int5_operand" "L")))))
2664 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2666 "{ldbs|ldb},mb %2(%1),%0"
2667 [(set_attr "type" "load")
2668 (set_attr "length" "4")])
2671 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2672 (match_operand:SI 1 "int5_operand" "L")))
2673 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2675 (plus:SI (match_dup 0) (match_dup 1)))]
2677 "{stbs|stb},mb %r2,%1(%0)"
2678 [(set_attr "type" "store")
2679 (set_attr "length" "4")])
2681 ;; The definition of this insn does not really explain what it does,
2682 ;; but it should suffice
2683 ;; that anything generated as this insn will be recognized as one
2684 ;; and that it will not successfully combine with anything.
2685 (define_expand "movstrsi"
2686 [(parallel [(set (match_operand:BLK 0 "" "")
2687 (match_operand:BLK 1 "" ""))
2688 (clobber (match_dup 7))
2689 (clobber (match_dup 8))
2690 (clobber (match_dup 4))
2691 (clobber (match_dup 5))
2692 (clobber (match_dup 6))
2693 (use (match_operand:SI 2 "arith_operand" ""))
2694 (use (match_operand:SI 3 "const_int_operand" ""))])]
2700 /* HP provides very fast block move library routine for the PA;
2701 this routine includes:
2703 4x4 byte at a time block moves,
2704 1x4 byte at a time with alignment checked at runtime with
2705 attempts to align the source and destination as needed
2708 With that in mind, here's the heuristics to try and guess when
2709 the inlined block move will be better than the library block
2712 If the size isn't constant, then always use the library routines.
2714 If the size is large in respect to the known alignment, then use
2715 the library routines.
2717 If the size is small in repsect to the known alignment, then open
2718 code the copy (since that will lead to better scheduling).
2720 Else use the block move pattern. */
2722 /* Undetermined size, use the library routine. */
2723 if (GET_CODE (operands[2]) != CONST_INT)
2726 size = INTVAL (operands[2]);
2727 align = INTVAL (operands[3]);
2728 align = align > 4 ? 4 : align;
2730 /* If size/alignment > 8 (eg size is large in respect to alignment),
2731 then use the library routines. */
2732 if (size / align > 16)
2735 /* This does happen, but not often enough to worry much about. */
2736 if (size / align < MOVE_RATIO)
2739 /* Fall through means we're going to use our block move pattern. */
2741 = change_address (operands[0], VOIDmode,
2742 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
2744 = change_address (operands[1], VOIDmode,
2745 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
2746 operands[4] = gen_reg_rtx (SImode);
2747 operands[5] = gen_reg_rtx (SImode);
2748 operands[6] = gen_reg_rtx (SImode);
2749 operands[7] = XEXP (operands[0], 0);
2750 operands[8] = XEXP (operands[1], 0);
2753 ;; The operand constraints are written like this to support both compile-time
2754 ;; and run-time determined byte count. If the count is run-time determined,
2755 ;; the register with the byte count is clobbered by the copying code, and
2756 ;; therefore it is forced to operand 2. If the count is compile-time
2757 ;; determined, we need two scratch registers for the unrolled code.
2758 (define_insn "movstrsi_internal"
2759 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
2760 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
2761 (clobber (match_dup 0))
2762 (clobber (match_dup 1))
2763 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
2764 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
2765 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
2766 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
2767 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
2769 "* return output_block_move (operands, !which_alternative);"
2770 [(set_attr "type" "multi,multi")])
2772 ;; Floating point move insns
2774 ;; This pattern forces (set (reg:DF ...) (const_double ...))
2775 ;; to be reloaded by putting the constant into memory when
2776 ;; reg is a floating point register.
2778 ;; For integer registers we use ldil;ldo to set the appropriate
2781 ;; This must come before the movdf pattern, and it must be present
2782 ;; to handle obscure reloading cases.
2784 [(set (match_operand:DF 0 "register_operand" "=?r,f")
2785 (match_operand:DF 1 "" "?F,m"))]
2786 "GET_CODE (operands[1]) == CONST_DOUBLE
2787 && operands[1] != CONST0_RTX (DFmode)
2789 && ! TARGET_SOFT_FLOAT"
2790 "* return (which_alternative == 0 ? output_move_double (operands)
2791 : \"fldd%F1 %1,%0\");"
2792 [(set_attr "type" "move,fpload")
2793 (set_attr "length" "16,4")])
2795 (define_expand "movdf"
2796 [(set (match_operand:DF 0 "general_operand" "")
2797 (match_operand:DF 1 "general_operand" ""))]
2801 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
2802 operands[1] = force_const_mem (DFmode, operands[1]);
2804 if (emit_move_sequence (operands, DFmode, 0))
2808 ;; Reloading an SImode or DImode value requires a scratch register if
2809 ;; going in to or out of float point registers.
2811 (define_expand "reload_indf"
2812 [(set (match_operand:DF 0 "register_operand" "=Z")
2813 (match_operand:DF 1 "non_hard_reg_operand" ""))
2814 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2818 if (emit_move_sequence (operands, DFmode, operands[2]))
2821 /* We don't want the clobber emitted, so handle this ourselves. */
2822 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2826 (define_expand "reload_outdf"
2827 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
2828 (match_operand:DF 1 "register_operand" "Z"))
2829 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2833 if (emit_move_sequence (operands, DFmode, operands[2]))
2836 /* We don't want the clobber emitted, so handle this ourselves. */
2837 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2842 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
2843 "=f,*r,RQ,?o,?Q,f,*r,*r")
2844 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
2845 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
2846 "(register_operand (operands[0], DFmode)
2847 || reg_or_0_operand (operands[1], DFmode))
2848 && ! (GET_CODE (operands[1]) == CONST_DOUBLE
2849 && GET_CODE (operands[0]) == MEM)
2851 && ! TARGET_SOFT_FLOAT"
2854 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
2855 || operands[1] == CONST0_RTX (DFmode))
2856 return output_fp_move_double (operands);
2857 return output_move_double (operands);
2859 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
2860 (set_attr "length" "4,8,4,8,16,4,8,16")])
2863 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
2865 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
2867 "(register_operand (operands[0], DFmode)
2868 || reg_or_0_operand (operands[1], DFmode))
2870 && TARGET_SOFT_FLOAT"
2873 return output_move_double (operands);
2875 [(set_attr "type" "move,store,store,load,load")
2876 (set_attr "length" "8,8,16,8,16")])
2879 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
2880 "=r,r,r,r,r,Q,*q,!f,f,*TR")
2881 (match_operand:DF 1 "move_operand"
2882 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
2883 "(register_operand (operands[0], DFmode)
2884 || reg_or_0_operand (operands[1], DFmode))
2885 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
2897 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2898 (set_attr "pa_combine_type" "addmove")
2899 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
2902 [(set (match_operand:DF 0 "register_operand" "=fx")
2903 (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2904 (match_operand:SI 2 "register_operand" "r"))))]
2905 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2906 "{flddx|fldd} %2(%1),%0"
2907 [(set_attr "type" "fpload")
2908 (set_attr "length" "4")])
2911 [(set (match_operand:DF 0 "register_operand" "=fx")
2912 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
2913 (match_operand:SI 2 "basereg_operand" "r"))))]
2914 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2915 "{flddx|fldd} %1(%2),%0"
2916 [(set_attr "type" "fpload")
2917 (set_attr "length" "4")])
2920 [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2921 (match_operand:SI 2 "register_operand" "r")))
2922 (match_operand:DF 0 "register_operand" "fx"))]
2923 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2924 "{fstdx|fstd} %0,%2(%1)"
2925 [(set_attr "type" "fpstore")
2926 (set_attr "length" "4")])
2929 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
2930 (match_operand:SI 2 "basereg_operand" "r")))
2931 (match_operand:DF 0 "register_operand" "fx"))]
2932 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2933 "{fstdx|fstd} %0,%1(%2)"
2934 [(set_attr "type" "fpstore")
2935 (set_attr "length" "4")])
2937 (define_expand "movdi"
2938 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
2939 (match_operand:DI 1 "general_operand" ""))]
2943 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
2944 operands[1] = force_const_mem (DImode, operands[1]);
2946 if (emit_move_sequence (operands, DImode, 0))
2950 (define_expand "reload_indi"
2951 [(set (match_operand:DI 0 "register_operand" "=Z")
2952 (match_operand:DI 1 "non_hard_reg_operand" ""))
2953 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2957 if (emit_move_sequence (operands, DImode, operands[2]))
2960 /* We don't want the clobber emitted, so handle this ourselves. */
2961 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2965 (define_expand "reload_outdi"
2966 [(set (match_operand:DI 0 "general_operand" "")
2967 (match_operand:DI 1 "register_operand" "Z"))
2968 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2972 if (emit_move_sequence (operands, DImode, operands[2]))
2975 /* We don't want the clobber emitted, so handle this ourselves. */
2976 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2981 [(set (match_operand:DI 0 "register_operand" "=r")
2982 (high:DI (match_operand 1 "" "")))]
2986 rtx op0 = operands[0];
2987 rtx op1 = operands[1];
2989 if (GET_CODE (op1) == CONST_INT)
2991 operands[0] = operand_subword (op0, 1, 0, DImode);
2992 output_asm_insn (\"ldil L'%1,%0\", operands);
2994 operands[0] = operand_subword (op0, 0, 0, DImode);
2995 if (INTVAL (op1) < 0)
2996 output_asm_insn (\"ldi -1,%0\", operands);
2998 output_asm_insn (\"ldi 0,%0\", operands);
3001 else if (GET_CODE (op1) == CONST_DOUBLE)
3003 operands[0] = operand_subword (op0, 1, 0, DImode);
3004 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3005 output_asm_insn (\"ldil L'%1,%0\", operands);
3007 operands[0] = operand_subword (op0, 0, 0, DImode);
3008 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3009 output_asm_insn (singlemove_string (operands), operands);
3015 [(set_attr "type" "move")
3016 (set_attr "length" "8")])
3019 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3020 "=r,o,Q,r,r,r,f,f,*TR")
3021 (match_operand:DI 1 "general_operand"
3022 "rM,r,r,o*R,Q,i,fM,*TR,f"))]
3023 "(register_operand (operands[0], DImode)
3024 || reg_or_0_operand (operands[1], DImode))
3026 && ! TARGET_SOFT_FLOAT"
3029 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3030 || (operands[1] == CONST0_RTX (DImode)))
3031 return output_fp_move_double (operands);
3032 return output_move_double (operands);
3034 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
3035 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
3038 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3039 "=r,r,r,r,r,Q,*q,!f,f,*TR")
3040 (match_operand:DI 1 "move_operand"
3041 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3042 "(register_operand (operands[0], DImode)
3043 || reg_or_0_operand (operands[1], DImode))
3044 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3056 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3057 (set_attr "pa_combine_type" "addmove")
3058 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3061 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3063 (match_operand:DI 1 "general_operand"
3065 "(register_operand (operands[0], DImode)
3066 || reg_or_0_operand (operands[1], DImode))
3068 && TARGET_SOFT_FLOAT"
3071 return output_move_double (operands);
3073 [(set_attr "type" "move,store,store,load,load,multi")
3074 (set_attr "length" "8,8,16,8,16,16")])
3077 [(set (match_operand:DI 0 "register_operand" "=r,&r")
3078 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
3079 (match_operand:DI 2 "immediate_operand" "i,i")))]
3083 /* Don't output a 64 bit constant, since we can't trust the assembler to
3084 handle it correctly. */
3085 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3086 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3087 if (which_alternative == 1)
3088 output_asm_insn (\"copy %1,%0\", operands);
3089 return \"ldo R'%G2(%R1),%R0\";
3091 [(set_attr "type" "move,move")
3092 (set_attr "length" "4,8")])
3094 ;; This pattern forces (set (reg:SF ...) (const_double ...))
3095 ;; to be reloaded by putting the constant into memory when
3096 ;; reg is a floating point register.
3098 ;; For integer registers we use ldil;ldo to set the appropriate
3101 ;; This must come before the movsf pattern, and it must be present
3102 ;; to handle obscure reloading cases.
3104 [(set (match_operand:SF 0 "register_operand" "=?r,f")
3105 (match_operand:SF 1 "" "?F,m"))]
3106 "GET_CODE (operands[1]) == CONST_DOUBLE
3107 && operands[1] != CONST0_RTX (SFmode)
3108 && ! TARGET_SOFT_FLOAT"
3109 "* return (which_alternative == 0 ? singlemove_string (operands)
3110 : \" fldw%F1 %1,%0\");"
3111 [(set_attr "type" "move,fpload")
3112 (set_attr "length" "8,4")])
3114 (define_expand "movsf"
3115 [(set (match_operand:SF 0 "general_operand" "")
3116 (match_operand:SF 1 "general_operand" ""))]
3120 if (emit_move_sequence (operands, SFmode, 0))
3124 ;; Reloading an SImode or DImode value requires a scratch register if
3125 ;; going in to or out of float point registers.
3127 (define_expand "reload_insf"
3128 [(set (match_operand:SF 0 "register_operand" "=Z")
3129 (match_operand:SF 1 "non_hard_reg_operand" ""))
3130 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3134 if (emit_move_sequence (operands, SFmode, operands[2]))
3137 /* We don't want the clobber emitted, so handle this ourselves. */
3138 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3142 (define_expand "reload_outsf"
3143 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
3144 (match_operand:SF 1 "register_operand" "Z"))
3145 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3149 if (emit_move_sequence (operands, SFmode, operands[2]))
3152 /* We don't want the clobber emitted, so handle this ourselves. */
3153 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3158 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3160 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3161 "fG,rG,RQ,RQ,f,rG"))]
3162 "(register_operand (operands[0], SFmode)
3163 || reg_or_0_operand (operands[1], SFmode))
3164 && ! TARGET_SOFT_FLOAT"
3172 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
3173 (set_attr "pa_combine_type" "addmove")
3174 (set_attr "length" "4,4,4,4,4,4")])
3177 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3179 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3181 "(register_operand (operands[0], SFmode)
3182 || reg_or_0_operand (operands[1], SFmode))
3183 && TARGET_SOFT_FLOAT"
3188 [(set_attr "type" "move,load,store")
3189 (set_attr "pa_combine_type" "addmove")
3190 (set_attr "length" "4,4,4")])
3193 [(set (match_operand:SF 0 "register_operand" "=fx")
3194 (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3195 (match_operand:SI 2 "register_operand" "r"))))]
3196 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3197 "{fldwx|fldw} %2(%1),%0"
3198 [(set_attr "type" "fpload")
3199 (set_attr "length" "4")])
3202 [(set (match_operand:SF 0 "register_operand" "=fx")
3203 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3204 (match_operand:SI 2 "basereg_operand" "r"))))]
3205 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3206 "{fldwx|fldw} %1(%2),%0"
3207 [(set_attr "type" "fpload")
3208 (set_attr "length" "4")])
3211 [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3212 (match_operand:SI 2 "register_operand" "r")))
3213 (match_operand:SF 0 "register_operand" "fx"))]
3214 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3215 "{fstwx|fstw} %0,%2(%1)"
3216 [(set_attr "type" "fpstore")
3217 (set_attr "length" "4")])
3220 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3221 (match_operand:SI 2 "basereg_operand" "r")))
3222 (match_operand:SF 0 "register_operand" "fx"))]
3223 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3224 "{fstwx|fstw} %0,%1(%2)"
3225 [(set_attr "type" "fpstore")
3226 (set_attr "length" "4")])
3229 ;;- zero extension instructions
3230 ;; We have define_expand for zero extension patterns to make sure the
3231 ;; operands get loaded into registers. The define_insns accept
3232 ;; memory operands. This gives us better overall code than just
3233 ;; having a pattern that does or does not accept memory operands.
3235 (define_expand "zero_extendhisi2"
3236 [(set (match_operand:SI 0 "register_operand" "")
3238 (match_operand:HI 1 "register_operand" "")))]
3243 [(set (match_operand:SI 0 "register_operand" "=r,r")
3245 (match_operand:HI 1 "move_operand" "r,RQ")))]
3246 "GET_CODE (operands[1]) != CONST_INT"
3248 {extru|extrw,u} %1,31,16,%0
3250 [(set_attr "type" "shift,load")
3251 (set_attr "length" "4,4")])
3253 (define_expand "zero_extendqihi2"
3254 [(set (match_operand:HI 0 "register_operand" "")
3256 (match_operand:QI 1 "register_operand" "")))]
3261 [(set (match_operand:HI 0 "register_operand" "=r,r")
3263 (match_operand:QI 1 "move_operand" "r,RQ")))]
3264 "GET_CODE (operands[1]) != CONST_INT"
3266 {extru|extrw,u} %1,31,8,%0
3268 [(set_attr "type" "shift,load")
3269 (set_attr "length" "4,4")])
3271 (define_expand "zero_extendqisi2"
3272 [(set (match_operand:SI 0 "register_operand" "")
3274 (match_operand:QI 1 "register_operand" "")))]
3279 [(set (match_operand:SI 0 "register_operand" "=r,r")
3281 (match_operand:QI 1 "move_operand" "r,RQ")))]
3282 "GET_CODE (operands[1]) != CONST_INT"
3284 {extru|extrw,u} %1,31,8,%0
3286 [(set_attr "type" "shift,load")
3287 (set_attr "length" "4,4")])
3289 (define_insn "zero_extendqidi2"
3290 [(set (match_operand:DI 0 "register_operand" "=r")
3291 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3293 "extrd,u %1,63,8,%0"
3294 [(set_attr "type" "shift")
3295 (set_attr "length" "4")])
3297 (define_insn "zero_extendhidi2"
3298 [(set (match_operand:DI 0 "register_operand" "=r")
3299 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3301 "extrd,u %1,63,16,%0"
3302 [(set_attr "type" "shift")
3303 (set_attr "length" "4")])
3305 (define_insn "zero_extendsidi2"
3306 [(set (match_operand:DI 0 "register_operand" "=r")
3307 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3309 "extrd,u %1,63,32,%0"
3310 [(set_attr "type" "shift")
3311 (set_attr "length" "4")])
3313 ;;- sign extension instructions
3315 (define_insn "extendhisi2"
3316 [(set (match_operand:SI 0 "register_operand" "=r")
3317 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
3319 "{extrs|extrw,s} %1,31,16,%0"
3320 [(set_attr "type" "shift")
3321 (set_attr "length" "4")])
3323 (define_insn "extendqihi2"
3324 [(set (match_operand:HI 0 "register_operand" "=r")
3325 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
3327 "{extrs|extrw,s} %1,31,8,%0"
3328 [(set_attr "type" "shift")
3329 (set_attr "length" "4")])
3331 (define_insn "extendqisi2"
3332 [(set (match_operand:SI 0 "register_operand" "=r")
3333 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
3335 "{extrs|extrw,s} %1,31,8,%0"
3336 [(set_attr "type" "shift")
3337 (set_attr "length" "4")])
3339 (define_insn "extendqidi2"
3340 [(set (match_operand:DI 0 "register_operand" "=r")
3341 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3343 "extrd,s %1,63,8,%0"
3344 [(set_attr "type" "shift")
3345 (set_attr "length" "4")])
3347 (define_insn "extendhidi2"
3348 [(set (match_operand:DI 0 "register_operand" "=r")
3349 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3351 "extrd,s %1,63,16,%0"
3352 [(set_attr "type" "shift")
3353 (set_attr "length" "4")])
3355 (define_insn "extendsidi2"
3356 [(set (match_operand:DI 0 "register_operand" "=r")
3357 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3359 "extrd,s %1,63,32,%0"
3360 [(set_attr "type" "shift")
3361 (set_attr "length" "4")])
3364 ;; Conversions between float and double.
3366 (define_insn "extendsfdf2"
3367 [(set (match_operand:DF 0 "register_operand" "=f")
3369 (match_operand:SF 1 "register_operand" "f")))]
3370 "! TARGET_SOFT_FLOAT"
3371 "{fcnvff|fcnv},sgl,dbl %1,%0"
3372 [(set_attr "type" "fpalu")
3373 (set_attr "length" "4")])
3375 (define_insn "truncdfsf2"
3376 [(set (match_operand:SF 0 "register_operand" "=f")
3378 (match_operand:DF 1 "register_operand" "f")))]
3379 "! TARGET_SOFT_FLOAT"
3380 "{fcnvff|fcnv},dbl,sgl %1,%0"
3381 [(set_attr "type" "fpalu")
3382 (set_attr "length" "4")])
3384 ;; Conversion between fixed point and floating point.
3385 ;; Note that among the fix-to-float insns
3386 ;; the ones that start with SImode come first.
3387 ;; That is so that an operand that is a CONST_INT
3388 ;; (and therefore lacks a specific machine mode).
3389 ;; will be recognized as SImode (which is always valid)
3390 ;; rather than as QImode or HImode.
3392 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
3393 ;; to be reloaded by putting the constant into memory.
3394 ;; It must come before the more general floatsisf2 pattern.
3396 [(set (match_operand:SF 0 "register_operand" "=f")
3397 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
3398 "! TARGET_SOFT_FLOAT"
3399 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
3400 [(set_attr "type" "fpalu")
3401 (set_attr "length" "8")])
3403 (define_insn "floatsisf2"
3404 [(set (match_operand:SF 0 "register_operand" "=f")
3405 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3406 "! TARGET_SOFT_FLOAT"
3407 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
3408 [(set_attr "type" "fpalu")
3409 (set_attr "length" "4")])
3411 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
3412 ;; to be reloaded by putting the constant into memory.
3413 ;; It must come before the more general floatsidf2 pattern.
3415 [(set (match_operand:DF 0 "register_operand" "=f")
3416 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
3417 "! TARGET_SOFT_FLOAT"
3418 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
3419 [(set_attr "type" "fpalu")
3420 (set_attr "length" "8")])
3422 (define_insn "floatsidf2"
3423 [(set (match_operand:DF 0 "register_operand" "=f")
3424 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3425 "! TARGET_SOFT_FLOAT"
3426 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
3427 [(set_attr "type" "fpalu")
3428 (set_attr "length" "4")])
3430 (define_expand "floatunssisf2"
3431 [(set (subreg:SI (match_dup 2) 1)
3432 (match_operand:SI 1 "register_operand" ""))
3433 (set (subreg:SI (match_dup 2) 0)
3435 (set (match_operand:SF 0 "register_operand" "")
3436 (float:SF (match_dup 2)))]
3437 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3442 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
3445 operands[2] = gen_reg_rtx (DImode);
3448 (define_expand "floatunssidf2"
3449 [(set (subreg:SI (match_dup 2) 1)
3450 (match_operand:SI 1 "register_operand" ""))
3451 (set (subreg:SI (match_dup 2) 0)
3453 (set (match_operand:DF 0 "register_operand" "")
3454 (float:DF (match_dup 2)))]
3455 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3460 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
3463 operands[2] = gen_reg_rtx (DImode);
3466 (define_insn "floatdisf2"
3467 [(set (match_operand:SF 0 "register_operand" "=f")
3468 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3469 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3470 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
3471 [(set_attr "type" "fpalu")
3472 (set_attr "length" "4")])
3474 (define_insn "floatdidf2"
3475 [(set (match_operand:DF 0 "register_operand" "=f")
3476 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3477 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3478 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
3479 [(set_attr "type" "fpalu")
3480 (set_attr "length" "4")])
3482 ;; Convert a float to an actual integer.
3483 ;; Truncation is performed as part of the conversion.
3485 (define_insn "fix_truncsfsi2"
3486 [(set (match_operand:SI 0 "register_operand" "=f")
3487 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3488 "! TARGET_SOFT_FLOAT"
3489 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
3490 [(set_attr "type" "fpalu")
3491 (set_attr "length" "4")])
3493 (define_insn "fix_truncdfsi2"
3494 [(set (match_operand:SI 0 "register_operand" "=f")
3495 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3496 "! TARGET_SOFT_FLOAT"
3497 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
3498 [(set_attr "type" "fpalu")
3499 (set_attr "length" "4")])
3501 (define_insn "fix_truncsfdi2"
3502 [(set (match_operand:DI 0 "register_operand" "=f")
3503 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3504 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3505 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
3506 [(set_attr "type" "fpalu")
3507 (set_attr "length" "4")])
3509 (define_insn "fix_truncdfdi2"
3510 [(set (match_operand:DI 0 "register_operand" "=f")
3511 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3512 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3513 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
3514 [(set_attr "type" "fpalu")
3515 (set_attr "length" "4")])
3517 (define_insn "floatunssidf2_pa20"
3518 [(set (match_operand:DF 0 "register_operand" "=f")
3519 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
3520 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3522 [(set_attr "type" "fpalu")
3523 (set_attr "length" "4")])
3525 (define_insn "floatunssisf2_pa20"
3526 [(set (match_operand:SF 0 "register_operand" "=f")
3527 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
3528 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3530 [(set_attr "type" "fpalu")
3531 (set_attr "length" "4")])
3533 (define_insn "floatunsdisf2"
3534 [(set (match_operand:SF 0 "register_operand" "=f")
3535 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
3536 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3537 "fcnv,udw,sgl %1,%0"
3538 [(set_attr "type" "fpalu")
3539 (set_attr "length" "4")])
3541 (define_insn "floatunsdidf2"
3542 [(set (match_operand:DF 0 "register_operand" "=f")
3543 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
3544 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3545 "fcnv,udw,dbl %1,%0"
3546 [(set_attr "type" "fpalu")
3547 (set_attr "length" "4")])
3549 (define_insn "fixuns_truncsfsi2"
3550 [(set (match_operand:SI 0 "register_operand" "=f")
3551 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3552 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3553 "fcnv,t,sgl,uw %1,%0"
3554 [(set_attr "type" "fpalu")
3555 (set_attr "length" "4")])
3557 (define_insn "fixuns_truncdfsi2"
3558 [(set (match_operand:SI 0 "register_operand" "=f")
3559 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3560 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3561 "fcnv,t,dbl,uw %1,%0"
3562 [(set_attr "type" "fpalu")
3563 (set_attr "length" "4")])
3565 (define_insn "fixuns_truncsfdi2"
3566 [(set (match_operand:DI 0 "register_operand" "=f")
3567 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3568 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3569 "fcnv,t,sgl,udw %1,%0"
3570 [(set_attr "type" "fpalu")
3571 (set_attr "length" "4")])
3573 (define_insn "fixuns_truncdfdi2"
3574 [(set (match_operand:DI 0 "register_operand" "=f")
3575 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3576 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3577 "fcnv,t,dbl,udw %1,%0"
3578 [(set_attr "type" "fpalu")
3579 (set_attr "length" "4")])
3581 ;;- arithmetic instructions
3583 (define_expand "adddi3"
3584 [(set (match_operand:DI 0 "register_operand" "")
3585 (plus:DI (match_operand:DI 1 "register_operand" "")
3586 (match_operand:DI 2 "arith_operand" "")))]
3590 ;; We allow arith_operand for operands2, even though strictly speaking it
3591 ;; we would prefer to us arith11_operand since that's what the hardware
3592 ;; can actually support.
3594 ;; But the price of the extra reload in that case is worth the simplicity
3595 ;; we get by allowing a trivial adddi3 expander to be used for both
3599 [(set (match_operand:DI 0 "register_operand" "=r")
3600 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3601 (match_operand:DI 2 "arith_operand" "rI")))]
3605 if (GET_CODE (operands[2]) == CONST_INT)
3607 if (INTVAL (operands[2]) >= 0)
3608 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
3610 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
3613 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
3615 [(set_attr "type" "binary")
3616 (set_attr "length" "8")])
3619 [(set (match_operand:DI 0 "register_operand" "=r,r")
3620 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
3621 (match_operand:DI 2 "arith_operand" "r,J")))]
3624 {addl|add,l} %1,%2,%0
3626 [(set_attr "type" "binary,binary")
3627 (set_attr "pa_combine_type" "addmove")
3628 (set_attr "length" "4,4")])
3631 [(set (match_operand:DI 0 "register_operand" "=r")
3632 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
3633 (match_operand:DI 2 "register_operand" "r")))]
3636 [(set_attr "type" "binary")
3637 (set_attr "length" "4")])
3640 [(set (match_operand:SI 0 "register_operand" "=r")
3641 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3642 (match_operand:SI 2 "register_operand" "r")))]
3645 [(set_attr "type" "binary")
3646 (set_attr "length" "4")])
3648 ;; define_splits to optimize cases of adding a constant integer
3649 ;; to a register when the constant does not fit in 14 bits. */
3651 [(set (match_operand:SI 0 "register_operand" "")
3652 (plus:SI (match_operand:SI 1 "register_operand" "")
3653 (match_operand:SI 2 "const_int_operand" "")))
3654 (clobber (match_operand:SI 4 "register_operand" ""))]
3655 "! cint_ok_for_move (INTVAL (operands[2]))
3656 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
3657 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
3658 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
3661 int val = INTVAL (operands[2]);
3662 int low = (val < 0) ? -0x2000 : 0x1fff;
3663 int rest = val - low;
3665 operands[2] = GEN_INT (rest);
3666 operands[3] = GEN_INT (low);
3670 [(set (match_operand:SI 0 "register_operand" "")
3671 (plus:SI (match_operand:SI 1 "register_operand" "")
3672 (match_operand:SI 2 "const_int_operand" "")))
3673 (clobber (match_operand:SI 4 "register_operand" ""))]
3674 "! cint_ok_for_move (INTVAL (operands[2]))"
3675 [(set (match_dup 4) (match_dup 2))
3676 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
3680 HOST_WIDE_INT intval = INTVAL (operands[2]);
3682 /* Try dividing the constant by 2, then 4, and finally 8 to see
3683 if we can get a constant which can be loaded into a register
3684 in a single instruction (cint_ok_for_move).
3686 If that fails, try to negate the constant and subtract it
3687 from our input operand. */
3688 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
3690 operands[2] = GEN_INT (intval / 2);
3691 operands[3] = GEN_INT (2);
3693 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
3695 operands[2] = GEN_INT (intval / 4);
3696 operands[3] = GEN_INT (4);
3698 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
3700 operands[2] = GEN_INT (intval / 8);
3701 operands[3] = GEN_INT (8);
3703 else if (cint_ok_for_move (-intval))
3705 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
3706 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
3713 (define_insn "addsi3"
3714 [(set (match_operand:SI 0 "register_operand" "=r,r")
3715 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3716 (match_operand:SI 2 "arith_operand" "r,J")))]
3719 {addl|add,l} %1,%2,%0
3721 [(set_attr "type" "binary,binary")
3722 (set_attr "pa_combine_type" "addmove")
3723 (set_attr "length" "4,4")])
3725 (define_expand "subdi3"
3726 [(set (match_operand:DI 0 "register_operand" "")
3727 (minus:DI (match_operand:DI 1 "register_operand" "")
3728 (match_operand:DI 2 "register_operand" "")))]
3733 [(set (match_operand:DI 0 "register_operand" "=r")
3734 (minus:DI (match_operand:DI 1 "register_operand" "r")
3735 (match_operand:DI 2 "register_operand" "r")))]
3737 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
3738 [(set_attr "type" "binary")
3739 (set_attr "length" "8")])
3742 [(set (match_operand:DI 0 "register_operand" "=r,r,q")
3743 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,U")
3744 (match_operand:DI 2 "register_operand" "r,r,r")))]
3750 [(set_attr "type" "binary,binary,move")
3751 (set_attr "length" "4,4,4")])
3753 (define_expand "subsi3"
3754 [(set (match_operand:SI 0 "register_operand" "")
3755 (minus:SI (match_operand:SI 1 "arith11_operand" "")
3756 (match_operand:SI 2 "register_operand" "")))]
3761 [(set (match_operand:SI 0 "register_operand" "=r,r")
3762 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
3763 (match_operand:SI 2 "register_operand" "r,r")))]
3768 [(set_attr "type" "binary,binary")
3769 (set_attr "length" "4,4")])
3772 [(set (match_operand:SI 0 "register_operand" "=r,r,q")
3773 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
3774 (match_operand:SI 2 "register_operand" "r,r,r")))]
3780 [(set_attr "type" "binary,binary,move")
3781 (set_attr "length" "4,4,4")])
3783 ;; Clobbering a "register_operand" instead of a match_scratch
3784 ;; in operand3 of millicode calls avoids spilling %r1 and
3785 ;; produces better code.
3787 ;; The mulsi3 insns set up registers for the millicode call.
3788 (define_expand "mulsi3"
3789 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3790 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3791 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
3792 (clobber (match_dup 3))
3793 (clobber (reg:SI 26))
3794 (clobber (reg:SI 25))
3795 (clobber (reg:SI 31))])
3796 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3800 if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
3802 rtx scratch = gen_reg_rtx (DImode);
3803 operands[1] = force_reg (SImode, operands[1]);
3804 operands[2] = force_reg (SImode, operands[2]);
3805 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
3806 /* We do not want (subreg:SI (XX:DI) 1)) for TARGET_64BIT since
3807 that has no real meaning. */
3810 emit_insn (gen_rtx_SET (VOIDmode,
3812 gen_rtx_SUBREG (SImode, scratch, 0)));
3816 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3817 gen_rtx_SUBREG (SImode, scratch, 1)));
3820 operands[3] = gen_reg_rtx (SImode);
3823 (define_insn "umulsidi3"
3824 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
3825 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
3826 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
3827 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
3829 [(set_attr "type" "fpmuldbl")
3830 (set_attr "length" "4")])
3833 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
3834 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
3835 (match_operand:DI 2 "uint32_operand" "f")))]
3836 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
3838 [(set_attr "type" "fpmuldbl")
3839 (set_attr "length" "4")])
3842 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
3843 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
3844 (match_operand:DI 2 "uint32_operand" "f")))]
3845 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3847 [(set_attr "type" "fpmuldbl")
3848 (set_attr "length" "4")])
3851 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
3852 (clobber (match_operand:SI 0 "register_operand" "=a"))
3853 (clobber (reg:SI 26))
3854 (clobber (reg:SI 25))
3855 (clobber (reg:SI 31))]
3857 "* return output_mul_insn (0, insn);"
3858 [(set_attr "type" "milli")
3859 (set (attr "length")
3861 ;; Target (or stub) within reach
3862 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
3864 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3869 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
3873 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
3874 ;; same as NO_SPACE_REGS code
3875 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3877 (eq (symbol_ref "flag_pic")
3881 ;; Out of range and either PIC or PORTABLE_RUNTIME
3884 (define_expand "muldi3"
3885 [(set (match_operand:DI 0 "register_operand" "")
3886 (mult:DI (match_operand:DI 1 "register_operand" "")
3887 (match_operand:DI 2 "register_operand" "")))]
3888 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
3891 rtx low_product = gen_reg_rtx (DImode);
3892 rtx cross_product1 = gen_reg_rtx (DImode);
3893 rtx cross_product2 = gen_reg_rtx (DImode);
3894 rtx cross_scratch = gen_reg_rtx (DImode);
3895 rtx cross_product = gen_reg_rtx (DImode);
3896 rtx op1l, op1r, op2l, op2r;
3897 rtx op1shifted, op2shifted;
3899 op1shifted = gen_reg_rtx (DImode);
3900 op2shifted = gen_reg_rtx (DImode);
3901 op1l = gen_reg_rtx (SImode);
3902 op1r = gen_reg_rtx (SImode);
3903 op2l = gen_reg_rtx (SImode);
3904 op2r = gen_reg_rtx (SImode);
3906 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
3908 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
3910 op1r = gen_rtx_SUBREG (SImode, operands[1], 0);
3911 op2r = gen_rtx_SUBREG (SImode, operands[2], 0);
3912 op1l = gen_rtx_SUBREG (SImode, op1shifted, 0);
3913 op2l = gen_rtx_SUBREG (SImode, op2shifted, 0);
3915 /* Emit multiplies for the cross products. */
3916 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
3917 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
3919 /* Emit a multiply for the low sub-word. */
3920 emit_insn (gen_umulsidi3 (low_product, op2r, op1r));
3922 /* Sum the cross products and shift them into proper position. */
3923 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
3924 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
3926 /* Add the cross product to the low product and store the result
3927 into the output operand . */
3928 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
3932 ;;; Division and mod.
3933 (define_expand "divsi3"
3934 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3935 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3936 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
3937 (clobber (match_dup 3))
3938 (clobber (match_dup 4))
3939 (clobber (reg:SI 26))
3940 (clobber (reg:SI 25))
3941 (clobber (reg:SI 31))])
3942 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3946 operands[3] = gen_reg_rtx (SImode);
3947 operands[4] = gen_reg_rtx (SImode);
3949 operands[4] = gen_rtx_REG (SImode, 2);
3950 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
3956 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
3957 (clobber (match_operand:SI 1 "register_operand" "=a"))
3958 (clobber (match_operand:SI 2 "register_operand" "=&r"))
3959 (clobber (reg:SI 26))
3960 (clobber (reg:SI 25))
3961 (clobber (reg:SI 31))]
3964 return output_div_insn (operands, 0, insn);"
3965 [(set_attr "type" "milli")
3966 (set (attr "length")
3968 ;; Target (or stub) within reach
3969 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
3971 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3976 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
3980 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
3981 ;; same as NO_SPACE_REGS code
3982 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3984 (eq (symbol_ref "flag_pic")
3988 ;; Out of range and either PIC or PORTABLE_RUNTIME
3991 (define_expand "udivsi3"
3992 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3993 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3994 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
3995 (clobber (match_dup 3))
3996 (clobber (match_dup 4))
3997 (clobber (reg:SI 26))
3998 (clobber (reg:SI 25))
3999 (clobber (reg:SI 31))])
4000 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4004 operands[3] = gen_reg_rtx (SImode);
4005 operands[4] = gen_reg_rtx (SImode);
4007 operands[4] = gen_rtx_REG (SImode, 2);
4008 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
4014 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4015 (clobber (match_operand:SI 1 "register_operand" "=a"))
4016 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4017 (clobber (reg:SI 26))
4018 (clobber (reg:SI 25))
4019 (clobber (reg:SI 31))]
4022 return output_div_insn (operands, 1, insn);"
4023 [(set_attr "type" "milli")
4024 (set (attr "length")
4026 ;; Target (or stub) within reach
4027 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4029 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4034 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4038 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4039 ;; same as NO_SPACE_REGS code
4040 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4042 (eq (symbol_ref "flag_pic")
4046 ;; Out of range and either PIC or PORTABLE_RUNTIME
4049 (define_expand "modsi3"
4050 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4051 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4052 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4053 (clobber (match_dup 3))
4054 (clobber (match_dup 4))
4055 (clobber (reg:SI 26))
4056 (clobber (reg:SI 25))
4057 (clobber (reg:SI 31))])
4058 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4062 operands[4] = gen_reg_rtx (SImode);
4064 operands[4] = gen_rtx_REG (SImode, 2);
4065 operands[3] = gen_reg_rtx (SImode);
4069 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4070 (clobber (match_operand:SI 0 "register_operand" "=a"))
4071 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4072 (clobber (reg:SI 26))
4073 (clobber (reg:SI 25))
4074 (clobber (reg:SI 31))]
4077 return output_mod_insn (0, insn);"
4078 [(set_attr "type" "milli")
4079 (set (attr "length")
4081 ;; Target (or stub) within reach
4082 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4084 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4089 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4093 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4094 ;; same as NO_SPACE_REGS code
4095 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4097 (eq (symbol_ref "flag_pic")
4101 ;; Out of range and either PIC or PORTABLE_RUNTIME
4104 (define_expand "umodsi3"
4105 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4106 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4107 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4108 (clobber (match_dup 3))
4109 (clobber (match_dup 4))
4110 (clobber (reg:SI 26))
4111 (clobber (reg:SI 25))
4112 (clobber (reg:SI 31))])
4113 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4117 operands[4] = gen_reg_rtx (SImode);
4119 operands[4] = gen_rtx_REG (SImode, 2);
4120 operands[3] = gen_reg_rtx (SImode);
4124 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4125 (clobber (match_operand:SI 0 "register_operand" "=a"))
4126 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4127 (clobber (reg:SI 26))
4128 (clobber (reg:SI 25))
4129 (clobber (reg:SI 31))]
4132 return output_mod_insn (1, insn);"
4133 [(set_attr "type" "milli")
4134 (set (attr "length")
4136 ;; Target (or stub) within reach
4137 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4139 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4144 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4148 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4149 ;; same as NO_SPACE_REGS code
4150 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4152 (eq (symbol_ref "flag_pic")
4156 ;; Out of range and either PIC or PORTABLE_RUNTIME
4159 ;;- and instructions
4160 ;; We define DImode `and` so with DImode `not` we can get
4161 ;; DImode `andn`. Other combinations are possible.
4163 (define_expand "anddi3"
4164 [(set (match_operand:DI 0 "register_operand" "")
4165 (and:DI (match_operand:DI 1 "arith_double_operand" "")
4166 (match_operand:DI 2 "arith_double_operand" "")))]
4170 if (! register_operand (operands[1], DImode)
4171 || ! register_operand (operands[2], DImode))
4172 /* Let GCC break this into word-at-a-time operations. */
4177 [(set (match_operand:DI 0 "register_operand" "=r")
4178 (and:DI (match_operand:DI 1 "register_operand" "%r")
4179 (match_operand:DI 2 "register_operand" "r")))]
4181 "and %1,%2,%0\;and %R1,%R2,%R0"
4182 [(set_attr "type" "binary")
4183 (set_attr "length" "8")])
4186 [(set (match_operand:DI 0 "register_operand" "=r,r")
4187 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
4188 (match_operand:DI 2 "and_operand" "rO,P")))]
4190 "* return output_64bit_and (operands); "
4191 [(set_attr "type" "binary")
4192 (set_attr "length" "4")])
4194 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
4195 ; constant with ldil;ldo.
4196 (define_insn "andsi3"
4197 [(set (match_operand:SI 0 "register_operand" "=r,r")
4198 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
4199 (match_operand:SI 2 "and_operand" "rO,P")))]
4201 "* return output_and (operands); "
4202 [(set_attr "type" "binary,shift")
4203 (set_attr "length" "4,4")])
4206 [(set (match_operand:DI 0 "register_operand" "=r")
4207 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4208 (match_operand:DI 2 "register_operand" "r")))]
4210 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
4211 [(set_attr "type" "binary")
4212 (set_attr "length" "8")])
4215 [(set (match_operand:DI 0 "register_operand" "=r")
4216 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4217 (match_operand:DI 2 "register_operand" "r")))]
4220 [(set_attr "type" "binary")
4221 (set_attr "length" "4")])
4224 [(set (match_operand:SI 0 "register_operand" "=r")
4225 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4226 (match_operand:SI 2 "register_operand" "r")))]
4229 [(set_attr "type" "binary")
4230 (set_attr "length" "4")])
4232 (define_expand "iordi3"
4233 [(set (match_operand:DI 0 "register_operand" "")
4234 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
4235 (match_operand:DI 2 "arith_double_operand" "")))]
4239 if (! register_operand (operands[1], DImode)
4240 || ! register_operand (operands[2], DImode))
4241 /* Let GCC break this into word-at-a-time operations. */
4246 [(set (match_operand:DI 0 "register_operand" "=r")
4247 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4248 (match_operand:DI 2 "register_operand" "r")))]
4250 "or %1,%2,%0\;or %R1,%R2,%R0"
4251 [(set_attr "type" "binary")
4252 (set_attr "length" "8")])
4255 [(set (match_operand:DI 0 "register_operand" "=r,r")
4256 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
4257 (match_operand:DI 2 "ior_operand" "M,i")))]
4259 "* return output_64bit_ior (operands); "
4260 [(set_attr "type" "binary,shift")
4261 (set_attr "length" "4,4")])
4264 [(set (match_operand:DI 0 "register_operand" "=r")
4265 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4266 (match_operand:DI 2 "register_operand" "r")))]
4269 [(set_attr "type" "binary")
4270 (set_attr "length" "4")])
4272 ;; Need a define_expand because we've run out of CONST_OK... characters.
4273 (define_expand "iorsi3"
4274 [(set (match_operand:SI 0 "register_operand" "")
4275 (ior:SI (match_operand:SI 1 "register_operand" "")
4276 (match_operand:SI 2 "arith32_operand" "")))]
4280 if (! (ior_operand (operands[2], SImode)
4281 || register_operand (operands[2], SImode)))
4282 operands[2] = force_reg (SImode, operands[2]);
4286 [(set (match_operand:SI 0 "register_operand" "=r,r")
4287 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
4288 (match_operand:SI 2 "ior_operand" "M,i")))]
4290 "* return output_ior (operands); "
4291 [(set_attr "type" "binary,shift")
4292 (set_attr "length" "4,4")])
4295 [(set (match_operand:SI 0 "register_operand" "=r")
4296 (ior:SI (match_operand:SI 1 "register_operand" "%r")
4297 (match_operand:SI 2 "register_operand" "r")))]
4300 [(set_attr "type" "binary")
4301 (set_attr "length" "4")])
4303 (define_expand "xordi3"
4304 [(set (match_operand:DI 0 "register_operand" "")
4305 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
4306 (match_operand:DI 2 "arith_double_operand" "")))]
4310 if (! register_operand (operands[1], DImode)
4311 || ! register_operand (operands[2], DImode))
4312 /* Let GCC break this into word-at-a-time operations. */
4317 [(set (match_operand:DI 0 "register_operand" "=r")
4318 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4319 (match_operand:DI 2 "register_operand" "r")))]
4321 "xor %1,%2,%0\;xor %R1,%R2,%R0"
4322 [(set_attr "type" "binary")
4323 (set_attr "length" "8")])
4326 [(set (match_operand:DI 0 "register_operand" "=r")
4327 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4328 (match_operand:DI 2 "register_operand" "r")))]
4331 [(set_attr "type" "binary")
4332 (set_attr "length" "4")])
4334 (define_insn "xorsi3"
4335 [(set (match_operand:SI 0 "register_operand" "=r")
4336 (xor:SI (match_operand:SI 1 "register_operand" "%r")
4337 (match_operand:SI 2 "register_operand" "r")))]
4340 [(set_attr "type" "binary")
4341 (set_attr "length" "4")])
4343 (define_expand "negdi2"
4344 [(set (match_operand:DI 0 "register_operand" "")
4345 (neg:DI (match_operand:DI 1 "register_operand" "")))]
4350 [(set (match_operand:DI 0 "register_operand" "=r")
4351 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4353 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
4354 [(set_attr "type" "unary")
4355 (set_attr "length" "8")])
4358 [(set (match_operand:DI 0 "register_operand" "=r")
4359 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4362 [(set_attr "type" "unary")
4363 (set_attr "length" "4")])
4365 (define_insn "negsi2"
4366 [(set (match_operand:SI 0 "register_operand" "=r")
4367 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
4370 [(set_attr "type" "unary")
4371 (set_attr "length" "4")])
4373 (define_expand "one_cmpldi2"
4374 [(set (match_operand:DI 0 "register_operand" "")
4375 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
4379 if (! register_operand (operands[1], DImode))
4384 [(set (match_operand:DI 0 "register_operand" "=r")
4385 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4387 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
4388 [(set_attr "type" "unary")
4389 (set_attr "length" "8")])
4392 [(set (match_operand:DI 0 "register_operand" "=r")
4393 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4396 [(set_attr "type" "unary")
4397 (set_attr "length" "4")])
4399 (define_insn "one_cmplsi2"
4400 [(set (match_operand:SI 0 "register_operand" "=r")
4401 (not:SI (match_operand:SI 1 "register_operand" "r")))]
4404 [(set_attr "type" "unary")
4405 (set_attr "length" "4")])
4407 ;; Floating point arithmetic instructions.
4409 (define_insn "adddf3"
4410 [(set (match_operand:DF 0 "register_operand" "=f")
4411 (plus:DF (match_operand:DF 1 "register_operand" "f")
4412 (match_operand:DF 2 "register_operand" "f")))]
4413 "! TARGET_SOFT_FLOAT"
4415 [(set_attr "type" "fpalu")
4416 (set_attr "pa_combine_type" "faddsub")
4417 (set_attr "length" "4")])
4419 (define_insn "addsf3"
4420 [(set (match_operand:SF 0 "register_operand" "=f")
4421 (plus:SF (match_operand:SF 1 "register_operand" "f")
4422 (match_operand:SF 2 "register_operand" "f")))]
4423 "! TARGET_SOFT_FLOAT"
4425 [(set_attr "type" "fpalu")
4426 (set_attr "pa_combine_type" "faddsub")
4427 (set_attr "length" "4")])
4429 (define_insn "subdf3"
4430 [(set (match_operand:DF 0 "register_operand" "=f")
4431 (minus:DF (match_operand:DF 1 "register_operand" "f")
4432 (match_operand:DF 2 "register_operand" "f")))]
4433 "! TARGET_SOFT_FLOAT"
4435 [(set_attr "type" "fpalu")
4436 (set_attr "pa_combine_type" "faddsub")
4437 (set_attr "length" "4")])
4439 (define_insn "subsf3"
4440 [(set (match_operand:SF 0 "register_operand" "=f")
4441 (minus:SF (match_operand:SF 1 "register_operand" "f")
4442 (match_operand:SF 2 "register_operand" "f")))]
4443 "! TARGET_SOFT_FLOAT"
4445 [(set_attr "type" "fpalu")
4446 (set_attr "pa_combine_type" "faddsub")
4447 (set_attr "length" "4")])
4449 (define_insn "muldf3"
4450 [(set (match_operand:DF 0 "register_operand" "=f")
4451 (mult:DF (match_operand:DF 1 "register_operand" "f")
4452 (match_operand:DF 2 "register_operand" "f")))]
4453 "! TARGET_SOFT_FLOAT"
4455 [(set_attr "type" "fpmuldbl")
4456 (set_attr "pa_combine_type" "fmpy")
4457 (set_attr "length" "4")])
4459 (define_insn "mulsf3"
4460 [(set (match_operand:SF 0 "register_operand" "=f")
4461 (mult:SF (match_operand:SF 1 "register_operand" "f")
4462 (match_operand:SF 2 "register_operand" "f")))]
4463 "! TARGET_SOFT_FLOAT"
4465 [(set_attr "type" "fpmulsgl")
4466 (set_attr "pa_combine_type" "fmpy")
4467 (set_attr "length" "4")])
4469 (define_insn "divdf3"
4470 [(set (match_operand:DF 0 "register_operand" "=f")
4471 (div:DF (match_operand:DF 1 "register_operand" "f")
4472 (match_operand:DF 2 "register_operand" "f")))]
4473 "! TARGET_SOFT_FLOAT"
4475 [(set_attr "type" "fpdivdbl")
4476 (set_attr "length" "4")])
4478 (define_insn "divsf3"
4479 [(set (match_operand:SF 0 "register_operand" "=f")
4480 (div:SF (match_operand:SF 1 "register_operand" "f")
4481 (match_operand:SF 2 "register_operand" "f")))]
4482 "! TARGET_SOFT_FLOAT"
4484 [(set_attr "type" "fpdivsgl")
4485 (set_attr "length" "4")])
4487 (define_insn "negdf2"
4488 [(set (match_operand:DF 0 "register_operand" "=f")
4489 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
4490 "! TARGET_SOFT_FLOAT"
4494 return \"fneg,dbl %1,%0\";
4496 return \"fsub,dbl %%fr0,%1,%0\";
4498 [(set_attr "type" "fpalu")
4499 (set_attr "length" "4")])
4501 (define_insn "negsf2"
4502 [(set (match_operand:SF 0 "register_operand" "=f")
4503 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
4504 "! TARGET_SOFT_FLOAT"
4508 return \"fneg,sgl %1,%0\";
4510 return \"fsub,sgl %%fr0,%1,%0\";
4512 [(set_attr "type" "fpalu")
4513 (set_attr "length" "4")])
4515 (define_insn "absdf2"
4516 [(set (match_operand:DF 0 "register_operand" "=f")
4517 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
4518 "! TARGET_SOFT_FLOAT"
4520 [(set_attr "type" "fpalu")
4521 (set_attr "length" "4")])
4523 (define_insn "abssf2"
4524 [(set (match_operand:SF 0 "register_operand" "=f")
4525 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
4526 "! TARGET_SOFT_FLOAT"
4528 [(set_attr "type" "fpalu")
4529 (set_attr "length" "4")])
4531 (define_insn "sqrtdf2"
4532 [(set (match_operand:DF 0 "register_operand" "=f")
4533 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
4534 "! TARGET_SOFT_FLOAT"
4536 [(set_attr "type" "fpsqrtdbl")
4537 (set_attr "length" "4")])
4539 (define_insn "sqrtsf2"
4540 [(set (match_operand:SF 0 "register_operand" "=f")
4541 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
4542 "! TARGET_SOFT_FLOAT"
4544 [(set_attr "type" "fpsqrtsgl")
4545 (set_attr "length" "4")])
4547 ;; PA 2.0 floating point instructions
4551 [(set (match_operand:DF 0 "register_operand" "=f")
4552 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4553 (match_operand:DF 2 "register_operand" "f"))
4554 (match_operand:DF 3 "register_operand" "f")))]
4555 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4556 "fmpyfadd,dbl %1,%2,%3,%0"
4557 [(set_attr "type" "fpmuldbl")
4558 (set_attr "length" "4")])
4561 [(set (match_operand:DF 0 "register_operand" "=f")
4562 (plus:DF (match_operand:DF 1 "register_operand" "f")
4563 (mult:DF (match_operand:DF 2 "register_operand" "f")
4564 (match_operand:DF 3 "register_operand" "f"))))]
4565 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4566 "fmpyfadd,dbl %2,%3,%1,%0"
4567 [(set_attr "type" "fpmuldbl")
4568 (set_attr "length" "4")])
4571 [(set (match_operand:SF 0 "register_operand" "=f")
4572 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4573 (match_operand:SF 2 "register_operand" "f"))
4574 (match_operand:SF 3 "register_operand" "f")))]
4575 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4576 "fmpyfadd,sgl %1,%2,%3,%0"
4577 [(set_attr "type" "fpmulsgl")
4578 (set_attr "length" "4")])
4581 [(set (match_operand:SF 0 "register_operand" "=f")
4582 (plus:SF (match_operand:SF 1 "register_operand" "f")
4583 (mult:SF (match_operand:SF 2 "register_operand" "f")
4584 (match_operand:SF 3 "register_operand" "f"))))]
4585 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4586 "fmpyfadd,sgl %2,%3,%1,%0"
4587 [(set_attr "type" "fpmulsgl")
4588 (set_attr "length" "4")])
4590 ; fmpynfadd patterns
4592 [(set (match_operand:DF 0 "register_operand" "=f")
4593 (minus:DF (match_operand:DF 1 "register_operand" "f")
4594 (mult:DF (match_operand:DF 2 "register_operand" "f")
4595 (match_operand:DF 3 "register_operand" "f"))))]
4596 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4597 "fmpynfadd,dbl %2,%3,%1,%0"
4598 [(set_attr "type" "fpmuldbl")
4599 (set_attr "length" "4")])
4602 [(set (match_operand:SF 0 "register_operand" "=f")
4603 (minus:SF (match_operand:SF 1 "register_operand" "f")
4604 (mult:SF (match_operand:SF 2 "register_operand" "f")
4605 (match_operand:SF 3 "register_operand" "f"))))]
4606 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4607 "fmpynfadd,sgl %2,%3,%1,%0"
4608 [(set_attr "type" "fpmulsgl")
4609 (set_attr "length" "4")])
4613 [(set (match_operand:DF 0 "register_operand" "=f")
4614 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
4615 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4617 [(set_attr "type" "fpalu")
4618 (set_attr "length" "4")])
4621 [(set (match_operand:SF 0 "register_operand" "=f")
4622 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
4623 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4625 [(set_attr "type" "fpalu")
4626 (set_attr "length" "4")])
4628 ;; Generating a fused multiply sequence is a win for this case as it will
4629 ;; reduce the latency for the fused case without impacting the plain
4632 ;; Similar possibilities exist for fnegabs, shadd and other insns which
4633 ;; perform two operations with the result of the first feeding the second.
4635 [(set (match_operand:DF 0 "register_operand" "=f")
4636 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4637 (match_operand:DF 2 "register_operand" "f"))
4638 (match_operand:DF 3 "register_operand" "f")))
4639 (set (match_operand:DF 4 "register_operand" "=&f")
4640 (mult:DF (match_dup 1) (match_dup 2)))]
4641 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4642 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4643 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4645 [(set_attr "type" "fpmuldbl")
4646 (set_attr "length" "8")])
4648 ;; We want to split this up during scheduling since we want both insns
4649 ;; to schedule independently.
4651 [(set (match_operand:DF 0 "register_operand" "=f")
4652 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4653 (match_operand:DF 2 "register_operand" "f"))
4654 (match_operand:DF 3 "register_operand" "f")))
4655 (set (match_operand:DF 4 "register_operand" "=&f")
4656 (mult:DF (match_dup 1) (match_dup 2)))]
4657 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4658 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4659 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
4664 [(set (match_operand:SF 0 "register_operand" "=f")
4665 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4666 (match_operand:SF 2 "register_operand" "f"))
4667 (match_operand:SF 3 "register_operand" "f")))
4668 (set (match_operand:SF 4 "register_operand" "=&f")
4669 (mult:SF (match_dup 1) (match_dup 2)))]
4670 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4671 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4672 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4674 [(set_attr "type" "fpmuldbl")
4675 (set_attr "length" "8")])
4677 ;; We want to split this up during scheduling since we want both insns
4678 ;; to schedule independently.
4680 [(set (match_operand:SF 0 "register_operand" "=f")
4681 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4682 (match_operand:SF 2 "register_operand" "f"))
4683 (match_operand:SF 3 "register_operand" "f")))
4684 (set (match_operand:SF 4 "register_operand" "=&f")
4685 (mult:SF (match_dup 1) (match_dup 2)))]
4686 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4687 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4688 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
4692 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
4695 [(set (match_operand:DF 0 "register_operand" "=f")
4696 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4697 (match_operand:DF 2 "register_operand" "f"))))]
4698 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4699 "fmpynfadd,dbl %1,%2,%%fr0,%0"
4700 [(set_attr "type" "fpmuldbl")
4701 (set_attr "length" "4")])
4704 [(set (match_operand:SF 0 "register_operand" "=f")
4705 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4706 (match_operand:SF 2 "register_operand" "f"))))]
4707 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4708 "fmpynfadd,sgl %1,%2,%%fr0,%0"
4709 [(set_attr "type" "fpmuldbl")
4710 (set_attr "length" "4")])
4713 [(set (match_operand:DF 0 "register_operand" "=f")
4714 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4715 (match_operand:DF 2 "register_operand" "f"))))
4716 (set (match_operand:DF 3 "register_operand" "=&f")
4717 (mult:DF (match_dup 1) (match_dup 2)))]
4718 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4719 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4720 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4722 [(set_attr "type" "fpmuldbl")
4723 (set_attr "length" "8")])
4726 [(set (match_operand:DF 0 "register_operand" "=f")
4727 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4728 (match_operand:DF 2 "register_operand" "f"))))
4729 (set (match_operand:DF 3 "register_operand" "=&f")
4730 (mult:DF (match_dup 1) (match_dup 2)))]
4731 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4732 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
4733 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
4737 [(set (match_operand:SF 0 "register_operand" "=f")
4738 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4739 (match_operand:SF 2 "register_operand" "f"))))
4740 (set (match_operand:SF 3 "register_operand" "=&f")
4741 (mult:SF (match_dup 1) (match_dup 2)))]
4742 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4743 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4744 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4746 [(set_attr "type" "fpmuldbl")
4747 (set_attr "length" "8")])
4750 [(set (match_operand:SF 0 "register_operand" "=f")
4751 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4752 (match_operand:SF 2 "register_operand" "f"))))
4753 (set (match_operand:SF 3 "register_operand" "=&f")
4754 (mult:SF (match_dup 1) (match_dup 2)))]
4755 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4756 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
4757 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
4760 ;; Now fused multiplies with the result of the multiply negated.
4762 [(set (match_operand:DF 0 "register_operand" "=f")
4763 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4764 (match_operand:DF 2 "register_operand" "f")))
4765 (match_operand:DF 3 "register_operand" "f")))]
4766 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4767 "fmpynfadd,dbl %1,%2,%3,%0"
4768 [(set_attr "type" "fpmuldbl")
4769 (set_attr "length" "4")])
4772 [(set (match_operand:SF 0 "register_operand" "=f")
4773 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4774 (match_operand:SF 2 "register_operand" "f")))
4775 (match_operand:SF 3 "register_operand" "f")))]
4776 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4777 "fmpynfadd,sgl %1,%2,%3,%0"
4778 [(set_attr "type" "fpmuldbl")
4779 (set_attr "length" "4")])
4782 [(set (match_operand:DF 0 "register_operand" "=f")
4783 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4784 (match_operand:DF 2 "register_operand" "f")))
4785 (match_operand:DF 3 "register_operand" "f")))
4786 (set (match_operand:DF 4 "register_operand" "=&f")
4787 (mult:DF (match_dup 1) (match_dup 2)))]
4788 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4789 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4790 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4792 [(set_attr "type" "fpmuldbl")
4793 (set_attr "length" "8")])
4796 [(set (match_operand:DF 0 "register_operand" "=f")
4797 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4798 (match_operand:DF 2 "register_operand" "f")))
4799 (match_operand:DF 3 "register_operand" "f")))
4800 (set (match_operand:DF 4 "register_operand" "=&f")
4801 (mult:DF (match_dup 1) (match_dup 2)))]
4802 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4803 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4804 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
4809 [(set (match_operand:SF 0 "register_operand" "=f")
4810 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4811 (match_operand:SF 2 "register_operand" "f")))
4812 (match_operand:SF 3 "register_operand" "f")))
4813 (set (match_operand:SF 4 "register_operand" "=&f")
4814 (mult:SF (match_dup 1) (match_dup 2)))]
4815 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4816 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4817 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4819 [(set_attr "type" "fpmuldbl")
4820 (set_attr "length" "8")])
4823 [(set (match_operand:SF 0 "register_operand" "=f")
4824 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4825 (match_operand:SF 2 "register_operand" "f")))
4826 (match_operand:SF 3 "register_operand" "f")))
4827 (set (match_operand:SF 4 "register_operand" "=&f")
4828 (mult:SF (match_dup 1) (match_dup 2)))]
4829 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4830 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4831 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
4836 [(set (match_operand:DF 0 "register_operand" "=f")
4837 (minus:DF (match_operand:DF 3 "register_operand" "f")
4838 (mult:DF (match_operand:DF 1 "register_operand" "f")
4839 (match_operand:DF 2 "register_operand" "f"))))
4840 (set (match_operand:DF 4 "register_operand" "=&f")
4841 (mult:DF (match_dup 1) (match_dup 2)))]
4842 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4843 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4844 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4846 [(set_attr "type" "fpmuldbl")
4847 (set_attr "length" "8")])
4850 [(set (match_operand:DF 0 "register_operand" "=f")
4851 (minus:DF (match_operand:DF 3 "register_operand" "f")
4852 (mult:DF (match_operand:DF 1 "register_operand" "f")
4853 (match_operand:DF 2 "register_operand" "f"))))
4854 (set (match_operand:DF 4 "register_operand" "=&f")
4855 (mult:DF (match_dup 1) (match_dup 2)))]
4856 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4857 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4858 (set (match_dup 0) (minus:DF (match_dup 3)
4859 (mult:DF (match_dup 1) (match_dup 2))))]
4863 [(set (match_operand:SF 0 "register_operand" "=f")
4864 (minus:SF (match_operand:SF 3 "register_operand" "f")
4865 (mult:SF (match_operand:SF 1 "register_operand" "f")
4866 (match_operand:SF 2 "register_operand" "f"))))
4867 (set (match_operand:SF 4 "register_operand" "=&f")
4868 (mult:SF (match_dup 1) (match_dup 2)))]
4869 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4870 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4871 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4873 [(set_attr "type" "fpmuldbl")
4874 (set_attr "length" "8")])
4877 [(set (match_operand:SF 0 "register_operand" "=f")
4878 (minus:SF (match_operand:SF 3 "register_operand" "f")
4879 (mult:SF (match_operand:SF 1 "register_operand" "f")
4880 (match_operand:SF 2 "register_operand" "f"))))
4881 (set (match_operand:SF 4 "register_operand" "=&f")
4882 (mult:SF (match_dup 1) (match_dup 2)))]
4883 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4884 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4885 (set (match_dup 0) (minus:SF (match_dup 3)
4886 (mult:SF (match_dup 1) (match_dup 2))))]
4890 [(set (match_operand:DF 0 "register_operand" "=f")
4891 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
4892 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
4893 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4894 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
4896 [(set_attr "type" "fpalu")
4897 (set_attr "length" "8")])
4900 [(set (match_operand:DF 0 "register_operand" "=f")
4901 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
4902 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
4903 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4904 [(set (match_dup 2) (abs:DF (match_dup 1)))
4905 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
4909 [(set (match_operand:SF 0 "register_operand" "=f")
4910 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
4911 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
4912 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4913 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
4915 [(set_attr "type" "fpalu")
4916 (set_attr "length" "8")])
4919 [(set (match_operand:SF 0 "register_operand" "=f")
4920 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
4921 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
4922 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4923 [(set (match_dup 2) (abs:SF (match_dup 1)))
4924 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
4927 ;;- Shift instructions
4929 ;; Optimized special case of shifting.
4932 [(set (match_operand:SI 0 "register_operand" "=r")
4933 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4937 [(set_attr "type" "load")
4938 (set_attr "length" "4")])
4941 [(set (match_operand:SI 0 "register_operand" "=r")
4942 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4946 [(set_attr "type" "load")
4947 (set_attr "length" "4")])
4950 [(set (match_operand:SI 0 "register_operand" "=r")
4951 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
4952 (match_operand:SI 3 "shadd_operand" ""))
4953 (match_operand:SI 1 "register_operand" "r")))]
4955 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
4956 [(set_attr "type" "binary")
4957 (set_attr "length" "4")])
4960 [(set (match_operand:DI 0 "register_operand" "=r")
4961 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
4962 (match_operand:DI 3 "shadd_operand" ""))
4963 (match_operand:DI 1 "register_operand" "r")))]
4965 "shladd,l %2,%O3,%1,%0"
4966 [(set_attr "type" "binary")
4967 (set_attr "length" "4")])
4969 (define_expand "ashlsi3"
4970 [(set (match_operand:SI 0 "register_operand" "")
4971 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
4972 (match_operand:SI 2 "arith32_operand" "")))]
4976 if (GET_CODE (operands[2]) != CONST_INT)
4978 rtx temp = gen_reg_rtx (SImode);
4979 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
4980 if (GET_CODE (operands[1]) == CONST_INT)
4981 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
4983 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
4986 /* Make sure both inputs are not constants,
4987 there are no patterns for that. */
4988 operands[1] = force_reg (SImode, operands[1]);
4992 [(set (match_operand:SI 0 "register_operand" "=r")
4993 (ashift:SI (match_operand:SI 1 "register_operand" "r")
4994 (match_operand:SI 2 "const_int_operand" "n")))]
4996 "{zdep|depw,z} %1,%P2,%L2,%0"
4997 [(set_attr "type" "shift")
4998 (set_attr "length" "4")])
5000 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
5001 ; Doing it like this makes slightly better code since reload can
5002 ; replace a register with a known value in range -16..15 with a
5003 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
5004 ; but since we have no more CONST_OK... characters, that is not
5006 (define_insn "zvdep32"
5007 [(set (match_operand:SI 0 "register_operand" "=r,r")
5008 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
5009 (minus:SI (const_int 31)
5010 (match_operand:SI 2 "register_operand" "q,q"))))]
5013 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
5014 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
5015 [(set_attr "type" "shift,shift")
5016 (set_attr "length" "4,4")])
5018 (define_insn "zvdep_imm32"
5019 [(set (match_operand:SI 0 "register_operand" "=r")
5020 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
5021 (minus:SI (const_int 31)
5022 (match_operand:SI 2 "register_operand" "q"))))]
5026 int x = INTVAL (operands[1]);
5027 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5028 operands[1] = GEN_INT ((x & 0xf) - 0x10);
5029 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
5031 [(set_attr "type" "shift")
5032 (set_attr "length" "4")])
5034 (define_insn "vdepi_ior"
5035 [(set (match_operand:SI 0 "register_operand" "=r")
5036 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
5037 (minus:SI (const_int 31)
5038 (match_operand:SI 2 "register_operand" "q")))
5039 (match_operand:SI 3 "register_operand" "0")))]
5040 ; accept ...0001...1, can this be generalized?
5041 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5044 int x = INTVAL (operands[1]);
5045 operands[2] = GEN_INT (exact_log2 (x + 1));
5046 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
5048 [(set_attr "type" "shift")
5049 (set_attr "length" "4")])
5051 (define_insn "vdepi_and"
5052 [(set (match_operand:SI 0 "register_operand" "=r")
5053 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
5054 (minus:SI (const_int 31)
5055 (match_operand:SI 2 "register_operand" "q")))
5056 (match_operand:SI 3 "register_operand" "0")))]
5057 ; this can be generalized...!
5058 "INTVAL (operands[1]) == -2"
5061 int x = INTVAL (operands[1]);
5062 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5063 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
5065 [(set_attr "type" "shift")
5066 (set_attr "length" "4")])
5068 (define_expand "ashldi3"
5069 [(set (match_operand:DI 0 "register_operand" "")
5070 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
5071 (match_operand:DI 2 "arith32_operand" "")))]
5075 if (GET_CODE (operands[2]) != CONST_INT)
5077 rtx temp = gen_reg_rtx (DImode);
5078 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5079 if (GET_CODE (operands[1]) == CONST_INT)
5080 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
5082 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
5085 /* Make sure both inputs are not constants,
5086 there are no patterns for that. */
5087 operands[1] = force_reg (DImode, operands[1]);
5091 [(set (match_operand:DI 0 "register_operand" "=r")
5092 (ashift:DI (match_operand:DI 1 "register_operand" "r")
5093 (match_operand:DI 2 "const_int_operand" "n")))]
5095 "depd,z %1,%p2,%Q2,%0"
5096 [(set_attr "type" "shift")
5097 (set_attr "length" "4")])
5099 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
5100 ; Doing it like this makes slightly better code since reload can
5101 ; replace a register with a known value in range -16..15 with a
5102 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
5103 ; but since we have no more CONST_OK... characters, that is not
5105 (define_insn "zvdep64"
5106 [(set (match_operand:DI 0 "register_operand" "=r,r")
5107 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
5108 (minus:DI (const_int 63)
5109 (match_operand:DI 2 "register_operand" "q,q"))))]
5112 depd,z %1,%%sar,64,%0
5113 depdi,z %1,%%sar,64,%0"
5114 [(set_attr "type" "shift,shift")
5115 (set_attr "length" "4,4")])
5117 (define_insn "zvdep_imm64"
5118 [(set (match_operand:DI 0 "register_operand" "=r")
5119 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
5120 (minus:DI (const_int 63)
5121 (match_operand:DI 2 "register_operand" "q"))))]
5125 int x = INTVAL (operands[1]);
5126 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5127 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
5128 return \"depdi,z %1,%%sar,%2,%0\";
5130 [(set_attr "type" "shift")
5131 (set_attr "length" "4")])
5134 [(set (match_operand:DI 0 "register_operand" "=r")
5135 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
5136 (minus:DI (const_int 63)
5137 (match_operand:DI 2 "register_operand" "q")))
5138 (match_operand:DI 3 "register_operand" "0")))]
5139 ; accept ...0001...1, can this be generalized?
5140 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5143 int x = INTVAL (operands[1]);
5144 operands[2] = GEN_INT (exact_log2 (x + 1));
5145 return \"depdi -1,%%sar,%2,%0\";
5147 [(set_attr "type" "shift")
5148 (set_attr "length" "4")])
5151 [(set (match_operand:DI 0 "register_operand" "=r")
5152 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
5153 (minus:DI (const_int 63)
5154 (match_operand:DI 2 "register_operand" "q")))
5155 (match_operand:DI 3 "register_operand" "0")))]
5156 ; this can be generalized...!
5157 "TARGET_64BIT && INTVAL (operands[1]) == -2"
5160 int x = INTVAL (operands[1]);
5161 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5162 return \"depdi 0,%%sar,%2,%0\";
5164 [(set_attr "type" "shift")
5165 (set_attr "length" "4")])
5167 (define_expand "ashrsi3"
5168 [(set (match_operand:SI 0 "register_operand" "")
5169 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
5170 (match_operand:SI 2 "arith32_operand" "")))]
5174 if (GET_CODE (operands[2]) != CONST_INT)
5176 rtx temp = gen_reg_rtx (SImode);
5177 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5178 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
5184 [(set (match_operand:SI 0 "register_operand" "=r")
5185 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5186 (match_operand:SI 2 "const_int_operand" "n")))]
5188 "{extrs|extrw,s} %1,%P2,%L2,%0"
5189 [(set_attr "type" "shift")
5190 (set_attr "length" "4")])
5192 (define_insn "vextrs32"
5193 [(set (match_operand:SI 0 "register_operand" "=r")
5194 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5195 (minus:SI (const_int 31)
5196 (match_operand:SI 2 "register_operand" "q"))))]
5198 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
5199 [(set_attr "type" "shift")
5200 (set_attr "length" "4")])
5202 (define_expand "ashrdi3"
5203 [(set (match_operand:DI 0 "register_operand" "")
5204 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5205 (match_operand:DI 2 "arith32_operand" "")))]
5209 if (GET_CODE (operands[2]) != CONST_INT)
5211 rtx temp = gen_reg_rtx (DImode);
5212 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5213 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
5219 [(set (match_operand:DI 0 "register_operand" "=r")
5220 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5221 (match_operand:DI 2 "const_int_operand" "n")))]
5223 "extrd,s %1,%p2,%Q2,%0"
5224 [(set_attr "type" "shift")
5225 (set_attr "length" "4")])
5227 (define_insn "vextrs64"
5228 [(set (match_operand:DI 0 "register_operand" "=r")
5229 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5230 (minus:DI (const_int 63)
5231 (match_operand:DI 2 "register_operand" "q"))))]
5233 "extrd,s %1,%%sar,64,%0"
5234 [(set_attr "type" "shift")
5235 (set_attr "length" "4")])
5237 (define_insn "lshrsi3"
5238 [(set (match_operand:SI 0 "register_operand" "=r,r")
5239 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
5240 (match_operand:SI 2 "arith32_operand" "q,n")))]
5243 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
5244 {extru|extrw,u} %1,%P2,%L2,%0"
5245 [(set_attr "type" "shift")
5246 (set_attr "length" "4")])
5248 (define_insn "lshrdi3"
5249 [(set (match_operand:DI 0 "register_operand" "=r,r")
5250 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
5251 (match_operand:DI 2 "arith32_operand" "q,n")))]
5254 shrpd %%r0,%1,%%sar,%0
5255 extrd,u %1,%p2,%Q2,%0"
5256 [(set_attr "type" "shift")
5257 (set_attr "length" "4")])
5259 (define_insn "rotrsi3"
5260 [(set (match_operand:SI 0 "register_operand" "=r,r")
5261 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
5262 (match_operand:SI 2 "arith32_operand" "q,n")))]
5266 if (GET_CODE (operands[2]) == CONST_INT)
5268 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
5269 return \"{shd|shrpw} %1,%1,%2,%0\";
5272 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
5274 [(set_attr "type" "shift")
5275 (set_attr "length" "4")])
5277 (define_expand "rotlsi3"
5278 [(set (match_operand:SI 0 "register_operand" "")
5279 (rotate:SI (match_operand:SI 1 "register_operand" "")
5280 (match_operand:SI 2 "arith32_operand" "")))]
5284 if (GET_CODE (operands[2]) != CONST_INT)
5286 rtx temp = gen_reg_rtx (SImode);
5287 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
5288 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
5291 /* Else expand normally. */
5295 [(set (match_operand:SI 0 "register_operand" "=r")
5296 (rotate:SI (match_operand:SI 1 "register_operand" "r")
5297 (match_operand:SI 2 "const_int_operand" "n")))]
5301 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
5302 return \"{shd|shrpw} %1,%1,%2,%0\";
5304 [(set_attr "type" "shift")
5305 (set_attr "length" "4")])
5308 [(set (match_operand:SI 0 "register_operand" "=r")
5309 (match_operator:SI 5 "plus_xor_ior_operator"
5310 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
5311 (match_operand:SI 3 "const_int_operand" "n"))
5312 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5313 (match_operand:SI 4 "const_int_operand" "n"))]))]
5314 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5315 "{shd|shrpw} %1,%2,%4,%0"
5316 [(set_attr "type" "shift")
5317 (set_attr "length" "4")])
5320 [(set (match_operand:SI 0 "register_operand" "=r")
5321 (match_operator:SI 5 "plus_xor_ior_operator"
5322 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5323 (match_operand:SI 4 "const_int_operand" "n"))
5324 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5325 (match_operand:SI 3 "const_int_operand" "n"))]))]
5326 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5327 "{shd|shrpw} %1,%2,%4,%0"
5328 [(set_attr "type" "shift")
5329 (set_attr "length" "4")])
5332 [(set (match_operand:SI 0 "register_operand" "=r")
5333 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
5334 (match_operand:SI 2 "const_int_operand" ""))
5335 (match_operand:SI 3 "const_int_operand" "")))]
5336 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
5339 int cnt = INTVAL (operands[2]) & 31;
5340 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
5341 operands[2] = GEN_INT (31 - cnt);
5342 return \"{zdep|depw,z} %1,%2,%3,%0\";
5344 [(set_attr "type" "shift")
5345 (set_attr "length" "4")])
5347 ;; Unconditional and other jump instructions.
5349 (define_insn "return"
5351 "hppa_can_use_return_insn_p ()"
5355 return \"bve%* (%%r2)\";
5356 return \"bv%* %%r0(%%r2)\";
5358 [(set_attr "type" "branch")
5359 (set_attr "length" "4")])
5361 ;; Use a different pattern for functions which have non-trivial
5362 ;; epilogues so as not to confuse jump and reorg.
5363 (define_insn "return_internal"
5370 return \"bve%* (%%r2)\";
5371 return \"bv%* %%r0(%%r2)\";
5373 [(set_attr "type" "branch")
5374 (set_attr "length" "4")])
5376 (define_expand "prologue"
5379 "hppa_expand_prologue ();DONE;")
5381 (define_expand "sibcall_epilogue"
5386 hppa_expand_epilogue ();
5390 (define_expand "epilogue"
5395 /* Try to use the trivial return first. Else use the full
5397 if (hppa_can_use_return_insn_p ())
5398 emit_jump_insn (gen_return ());
5401 hppa_expand_epilogue ();
5402 emit_jump_insn (gen_return_internal ());
5407 ;; Special because we use the value placed in %r2 by the bl instruction
5408 ;; from within its delay slot to set the value for the 2nd parameter to
5410 (define_insn "call_profiler"
5411 [(unspec_volatile [(const_int 0)] 0)
5412 (use (match_operand:SI 0 "const_int_operand" ""))]
5414 "{bl|b,l} _mcount,%%r2\;ldo %0(%%r2),%%r25"
5415 [(set_attr "type" "multi")
5416 (set_attr "length" "8")])
5418 (define_insn "blockage"
5419 [(unspec_volatile [(const_int 2)] 0)]
5422 [(set_attr "length" "0")])
5425 [(set (pc) (label_ref (match_operand 0 "" "")))]
5429 extern int optimize;
5431 if (GET_MODE (insn) == SImode)
5434 /* An unconditional branch which can reach its target. */
5435 if (get_attr_length (insn) != 24
5436 && get_attr_length (insn) != 16)
5439 /* An unconditional branch which can not reach its target.
5441 We need to be able to use %r1 as a scratch register; however,
5442 we can never be sure whether or not it's got a live value in
5443 it. Therefore, we must restore its original value after the
5446 To make matters worse, we don't have a stack slot which we
5447 can always clobber. sp-12/sp-16 shouldn't ever have a live
5448 value during a non-optimizing compilation, so we use those
5449 slots for now. We don't support very long branches when
5450 optimizing -- they should be quite rare when optimizing.
5452 Really the way to go long term is a register scavenger; goto
5453 the target of the jump and find a register which we can use
5454 as a scratch to hold the value in %r1. */
5456 /* We don't know how to register scavenge yet. */
5460 /* First store %r1 into the stack. */
5461 output_asm_insn (\"stw %%r1,-16(%%r30)\", operands);
5463 /* Now load the target address into %r1 and do an indirect jump
5464 to the value specified in %r1. Be careful to generate PIC
5469 xoperands[0] = operands[0];
5470 xoperands[1] = gen_label_rtx ();
5472 output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\",
5474 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5475 CODE_LABEL_NUMBER (xoperands[1]));
5476 output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\\n\\tbv %%r0(%%r1)\",
5480 output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);;
5482 /* And restore the value of %r1 in the delay slot. We're not optimizing,
5483 so we know nothing else can be in the delay slot. */
5484 return \"ldw -16(%%r30),%%r1\";
5486 [(set_attr "type" "uncond_branch")
5487 (set_attr "pa_combine_type" "uncond_branch")
5488 (set (attr "length")
5489 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
5490 (if_then_else (lt (abs (minus (match_dup 0)
5491 (plus (pc) (const_int 8))))
5495 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
5497 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5502 ;; Subroutines of "casesi".
5503 ;; operand 0 is index
5504 ;; operand 1 is the minimum bound
5505 ;; operand 2 is the maximum bound - minimum bound + 1
5506 ;; operand 3 is CODE_LABEL for the table;
5507 ;; operand 4 is the CODE_LABEL to go to if index out of range.
5509 (define_expand "casesi"
5510 [(match_operand:SI 0 "general_operand" "")
5511 (match_operand:SI 1 "const_int_operand" "")
5512 (match_operand:SI 2 "const_int_operand" "")
5513 (match_operand 3 "" "")
5514 (match_operand 4 "" "")]
5518 if (GET_CODE (operands[0]) != REG)
5519 operands[0] = force_reg (SImode, operands[0]);
5521 if (operands[1] != const0_rtx)
5523 rtx reg = gen_reg_rtx (SImode);
5525 operands[1] = GEN_INT (-INTVAL (operands[1]));
5526 if (!INT_14_BITS (operands[1]))
5527 operands[1] = force_reg (SImode, operands[1]);
5528 emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
5533 /* In 64bit mode we must make sure to wipe the upper bits of the register
5534 just in case the addition overflowed or we had random bits in the
5535 high part of the register. */
5538 rtx reg = gen_reg_rtx (DImode);
5539 emit_insn (gen_extendsidi2 (reg, operands[0]));
5540 operands[0] = gen_rtx_SUBREG (SImode, reg, 0);
5543 if (!INT_5_BITS (operands[2]))
5544 operands[2] = force_reg (SImode, operands[2]);
5546 emit_insn (gen_cmpsi (operands[0], operands[2]));
5547 emit_jump_insn (gen_bgtu (operands[4]));
5548 if (TARGET_BIG_SWITCH)
5550 rtx temp = gen_reg_rtx (SImode);
5551 emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
5554 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
5558 (define_insn "casesi0"
5560 (mem:SI (plus:SI (pc)
5561 (match_operand:SI 0 "register_operand" "r")))
5562 (label_ref (match_operand 1 "" ""))))]
5565 [(set_attr "type" "multi")
5566 (set_attr "length" "8")])
5568 ;; Need nops for the calls because execution is supposed to continue
5569 ;; past; we don't want to nullify an instruction that we need.
5570 ;;- jump to subroutine
5572 (define_expand "call"
5573 [(parallel [(call (match_operand:SI 0 "" "")
5574 (match_operand 1 "" ""))
5575 (clobber (reg:SI 2))])]
5582 if (TARGET_PORTABLE_RUNTIME)
5583 op = force_reg (SImode, XEXP (operands[0], 0));
5585 op = XEXP (operands[0], 0);
5588 emit_move_insn (arg_pointer_rtx,
5589 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5592 /* Use two different patterns for calls to explicitly named functions
5593 and calls through function pointers. This is necessary as these two
5594 types of calls use different calling conventions, and CSE might try
5595 to change the named call into an indirect call in some cases (using
5596 two patterns keeps CSE from performing this optimization). */
5597 if (GET_CODE (op) == SYMBOL_REF)
5598 call_insn = emit_call_insn (gen_call_internal_symref (op, operands[1]));
5599 else if (TARGET_64BIT)
5601 rtx tmpreg = force_reg (word_mode, op);
5602 call_insn = emit_call_insn (gen_call_internal_reg_64bit (tmpreg,
5607 rtx tmpreg = gen_rtx_REG (word_mode, 22);
5608 emit_move_insn (tmpreg, force_reg (word_mode, op));
5609 call_insn = emit_call_insn (gen_call_internal_reg (operands[1]));
5614 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
5615 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5616 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5618 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
5620 /* After each call we must restore the PIC register, even if it
5621 doesn't appear to be used.
5623 This will set regs_ever_live for the callee saved register we
5624 stored the PIC register in. */
5625 emit_move_insn (pic_offset_table_rtx,
5626 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5631 (define_insn "call_internal_symref"
5632 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5633 (match_operand 1 "" "i"))
5634 (clobber (reg:SI 2))
5635 (use (const_int 0))]
5636 "! TARGET_PORTABLE_RUNTIME"
5639 output_arg_descriptor (insn);
5640 return output_call (insn, operands[0], 0);
5642 [(set_attr "type" "call")
5643 (set (attr "length")
5644 ;; If we're sure that we can either reach the target or that the
5645 ;; linker can use a long-branch stub, then the length is 4 bytes.
5647 ;; For long-calls the length will be either 52 bytes (non-pic)
5648 ;; or 68 bytes (pic). */
5649 ;; Else we have to use a long-call;
5650 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
5653 (if_then_else (eq (symbol_ref "flag_pic")
5658 (define_insn "call_internal_reg_64bit"
5659 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
5660 (match_operand 1 "" "i"))
5661 (clobber (reg:SI 2))
5662 (use (const_int 1))]
5668 /* ??? Needs more work. Length computation, split into multiple insns,
5669 do not use %r22 directly, expose delay slot. */
5670 return \"ldd 16(%0),%%r2\;ldd 24(%0),%%r27\;bve,l (%%r2),%%r2\;nop\";
5672 [(set_attr "type" "dyncall")
5673 (set (attr "length") (const_int 16))])
5675 (define_insn "call_internal_reg"
5676 [(call (mem:SI (reg:SI 22))
5677 (match_operand 0 "" "i"))
5678 (clobber (reg:SI 2))
5679 (use (const_int 1))]
5685 /* First the special case for kernels, level 0 systems, etc. */
5686 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
5687 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
5689 /* Now the normal case -- we can reach $$dyncall directly or
5690 we're sure that we can get there via a long-branch stub.
5692 No need to check target flags as the length uniquely identifies
5693 the remaining cases. */
5694 if (get_attr_length (insn) == 8)
5695 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
5697 /* Long millicode call, but we are not generating PIC or portable runtime
5699 if (get_attr_length (insn) == 12)
5700 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
5702 /* Long millicode call for portable runtime. */
5703 if (get_attr_length (insn) == 20)
5704 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
5706 /* If we're generating PIC code. */
5707 xoperands[0] = operands[0];
5708 xoperands[1] = gen_label_rtx ();
5709 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
5710 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
5711 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5712 CODE_LABEL_NUMBER (xoperands[1]));
5713 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
5714 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
5715 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
5718 [(set_attr "type" "dyncall")
5719 (set (attr "length")
5721 ;; First NO_SPACE_REGS
5722 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
5726 ;; Target (or stub) within reach
5727 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
5729 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5733 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
5734 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5736 (eq (symbol_ref "flag_pic")
5740 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
5744 ;; Out of range PIC case
5747 (define_expand "call_value"
5748 [(parallel [(set (match_operand 0 "" "")
5749 (call (match_operand:SI 1 "" "")
5750 (match_operand 2 "" "")))
5751 (clobber (reg:SI 2))])]
5758 if (TARGET_PORTABLE_RUNTIME)
5759 op = force_reg (word_mode, XEXP (operands[1], 0));
5761 op = XEXP (operands[1], 0);
5764 emit_move_insn (arg_pointer_rtx,
5765 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5768 /* Use two different patterns for calls to explicitly named functions
5769 and calls through function pointers. This is necessary as these two
5770 types of calls use different calling conventions, and CSE might try
5771 to change the named call into an indirect call in some cases (using
5772 two patterns keeps CSE from performing this optimization). */
5773 if (GET_CODE (op) == SYMBOL_REF)
5774 call_insn = emit_call_insn (gen_call_value_internal_symref (operands[0],
5777 else if (TARGET_64BIT)
5779 rtx tmpreg = force_reg (word_mode, op);
5781 = emit_call_insn (gen_call_value_internal_reg_64bit (operands[0],
5787 rtx tmpreg = gen_rtx_REG (word_mode, 22);
5788 emit_move_insn (tmpreg, force_reg (word_mode, op));
5789 call_insn = emit_call_insn (gen_call_value_internal_reg (operands[0],
5794 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
5795 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5796 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5798 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
5800 /* After each call we must restore the PIC register, even if it
5801 doesn't appear to be used.
5803 This will set regs_ever_live for the callee saved register we
5804 stored the PIC register in. */
5805 emit_move_insn (pic_offset_table_rtx,
5806 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5811 (define_insn "call_value_internal_symref"
5812 [(set (match_operand 0 "" "=rf")
5813 (call (mem:SI (match_operand 1 "call_operand_address" ""))
5814 (match_operand 2 "" "i")))
5815 (clobber (reg:SI 2))
5816 (use (const_int 0))]
5817 ;;- Don't use operand 1 for most machines.
5818 "! TARGET_PORTABLE_RUNTIME"
5821 output_arg_descriptor (insn);
5822 return output_call (insn, operands[1], 0);
5824 [(set_attr "type" "call")
5825 (set (attr "length")
5826 ;; If we're sure that we can either reach the target or that the
5827 ;; linker can use a long-branch stub, then the length is 4 bytes.
5829 ;; For long-calls the length will be either 52 bytes (non-pic)
5830 ;; or 68 bytes (pic). */
5831 ;; Else we have to use a long-call;
5832 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
5835 (if_then_else (eq (symbol_ref "flag_pic")
5840 (define_insn "call_value_internal_reg_64bit"
5841 [(set (match_operand 0 "" "=rf")
5842 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
5843 (match_operand 2 "" "i")))
5844 (clobber (reg:SI 2))
5845 (use (const_int 1))]
5849 /* ??? Needs more work. Length computation, split into multiple insns,
5850 do not use %r22 directly, expose delay slot. */
5851 return \"ldd 16(%1),%%r2\;ldd 24(%1),%%r27\;bve,l (%%r2),%%r2\;nop\";
5853 [(set_attr "type" "dyncall")
5854 (set (attr "length") (const_int 16))])
5856 (define_insn "call_value_internal_reg"
5857 [(set (match_operand 0 "" "=rf")
5858 (call (mem:SI (reg:SI 22))
5859 (match_operand 1 "" "i")))
5860 (clobber (reg:SI 2))
5861 (use (const_int 1))]
5867 /* First the special case for kernels, level 0 systems, etc. */
5868 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
5869 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
5871 /* Now the normal case -- we can reach $$dyncall directly or
5872 we're sure that we can get there via a long-branch stub.
5874 No need to check target flags as the length uniquely identifies
5875 the remaining cases. */
5876 if (get_attr_length (insn) == 8)
5877 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
5879 /* Long millicode call, but we are not generating PIC or portable runtime
5881 if (get_attr_length (insn) == 12)
5882 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
5884 /* Long millicode call for portable runtime. */
5885 if (get_attr_length (insn) == 20)
5886 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
5888 /* If we're generating PIC code. */
5889 xoperands[0] = operands[1];
5890 xoperands[1] = gen_label_rtx ();
5891 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
5892 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
5893 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5894 CODE_LABEL_NUMBER (xoperands[1]));
5895 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
5896 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
5897 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
5900 [(set_attr "type" "dyncall")
5901 (set (attr "length")
5903 ;; First NO_SPACE_REGS
5904 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
5908 ;; Target (or stub) within reach
5909 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
5911 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5915 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
5916 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5918 (eq (symbol_ref "flag_pic")
5922 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
5926 ;; Out of range PIC case
5929 ;; Call subroutine returning any type.
5931 (define_expand "untyped_call"
5932 [(parallel [(call (match_operand 0 "" "")
5934 (match_operand 1 "" "")
5935 (match_operand 2 "" "")])]
5941 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5943 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5945 rtx set = XVECEXP (operands[2], 0, i);
5946 emit_move_insn (SET_DEST (set), SET_SRC (set));
5949 /* The optimizer does not know that the call sets the function value
5950 registers we stored in the result block. We avoid problems by
5951 claiming that all hard registers are used and clobbered at this
5953 emit_insn (gen_blockage ());
5958 (define_expand "sibcall"
5959 [(parallel [(call (match_operand:SI 0 "" "")
5960 (match_operand 1 "" ""))
5961 (clobber (reg:SI 0))])]
5962 "! TARGET_PORTABLE_RUNTIME"
5968 op = XEXP (operands[0], 0);
5970 /* We do not allow indirect sibling calls. */
5971 call_insn = emit_call_insn (gen_sibcall_internal_symref (op, operands[1]));
5975 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
5976 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5977 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5979 /* After each call we must restore the PIC register, even if it
5980 doesn't appear to be used.
5982 This will set regs_ever_live for the callee saved register we
5983 stored the PIC register in. */
5984 emit_move_insn (pic_offset_table_rtx,
5985 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
5990 (define_insn "sibcall_internal_symref"
5991 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5992 (match_operand 1 "" "i"))
5993 (clobber (reg:SI 0))
5995 (use (const_int 0))]
5996 "! TARGET_PORTABLE_RUNTIME"
5999 output_arg_descriptor (insn);
6000 return output_call (insn, operands[0], 1);
6002 [(set_attr "type" "call")
6003 (set (attr "length")
6004 ;; If we're sure that we can either reach the target or that the
6005 ;; linker can use a long-branch stub, then the length is 4 bytes.
6007 ;; For long-calls the length will be either 52 bytes (non-pic)
6008 ;; or 68 bytes (pic). */
6009 ;; Else we have to use a long-call;
6010 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6013 (if_then_else (eq (symbol_ref "flag_pic")
6018 (define_expand "sibcall_value"
6019 [(parallel [(set (match_operand 0 "" "")
6020 (call (match_operand:SI 1 "" "")
6021 (match_operand 2 "" "")))
6022 (clobber (reg:SI 0))])]
6023 "! TARGET_PORTABLE_RUNTIME"
6029 op = XEXP (operands[1], 0);
6031 /* We do not allow indirect sibling calls. */
6032 call_insn = emit_call_insn (gen_sibcall_value_internal_symref (operands[0],
6037 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6038 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6039 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
6041 /* After each call we must restore the PIC register, even if it
6042 doesn't appear to be used.
6044 This will set regs_ever_live for the callee saved register we
6045 stored the PIC register in. */
6046 emit_move_insn (pic_offset_table_rtx,
6047 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
6052 (define_insn "sibcall_value_internal_symref"
6053 [(set (match_operand 0 "" "=rf")
6054 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6055 (match_operand 2 "" "i")))
6056 (clobber (reg:SI 0))
6058 (use (const_int 0))]
6059 ;;- Don't use operand 1 for most machines.
6060 "! TARGET_PORTABLE_RUNTIME"
6063 output_arg_descriptor (insn);
6064 return output_call (insn, operands[1], 1);
6066 [(set_attr "type" "call")
6067 (set (attr "length")
6068 ;; If we're sure that we can either reach the target or that the
6069 ;; linker can use a long-branch stub, then the length is 4 bytes.
6071 ;; For long-calls the length will be either 52 bytes (non-pic)
6072 ;; or 68 bytes (pic). */
6073 ;; Else we have to use a long-call;
6074 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6077 (if_then_else (eq (symbol_ref "flag_pic")
6086 [(set_attr "type" "move")
6087 (set_attr "length" "4")])
6089 ;; These are just placeholders so we know where branch tables
6091 (define_insn "begin_brtab"
6096 /* Only GAS actually supports this pseudo-op. */
6098 return \".begin_brtab\";
6102 [(set_attr "type" "move")
6103 (set_attr "length" "0")])
6105 (define_insn "end_brtab"
6110 /* Only GAS actually supports this pseudo-op. */
6112 return \".end_brtab\";
6116 [(set_attr "type" "move")
6117 (set_attr "length" "0")])
6119 ;;; EH does longjmp's from and within the data section. Thus,
6120 ;;; an interspace branch is required for the longjmp implementation.
6121 ;;; Registers r1 and r2 are not saved in the jmpbuf environment.
6122 ;;; Thus, they can be used as scratch registers for the jump.
6123 (define_expand "interspace_jump"
6125 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6126 (clobber (match_dup 1))])]
6130 operands[1] = gen_rtx_REG (word_mode, 2);
6134 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6135 (clobber (reg:SI 2))]
6137 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6138 [(set_attr "type" "branch")
6139 (set_attr "length" "12")])
6142 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6143 (clobber (reg:DI 2))]
6145 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6146 [(set_attr "type" "branch")
6147 (set_attr "length" "12")])
6149 (define_expand "builtin_longjmp"
6150 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6154 /* The elements of the buffer are, in order: */
6155 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6156 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4));
6157 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6158 rtx pv = gen_rtx_REG (Pmode, 1);
6160 /* This bit is the same as expand_builtin_longjmp. */
6161 emit_move_insn (hard_frame_pointer_rtx, fp);
6162 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6163 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6164 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6166 /* Load the label we are jumping through into r1 so that we know
6167 where to look for it when we get back to setjmp's function for
6168 restoring the gp. */
6169 emit_move_insn (pv, lab);
6170 emit_jump_insn (gen_interspace_jump (pv));
6174 ;;; Hope this is only within a function...
6175 (define_insn "indirect_jump"
6176 [(set (pc) (match_operand 0 "register_operand" "r"))]
6177 "GET_MODE (operands[0]) == word_mode"
6179 [(set_attr "type" "branch")
6180 (set_attr "length" "4")])
6182 (define_expand "extzv"
6183 [(set (match_operand 0 "register_operand" "")
6184 (zero_extract (match_operand 1 "register_operand" "")
6185 (match_operand 2 "uint32_operand" "")
6186 (match_operand 3 "uint32_operand" "")))]
6191 emit_insn (gen_extzv_64 (operands[0], operands[1],
6192 operands[2], operands[3]));
6194 emit_insn (gen_extzv_32 (operands[0], operands[1],
6195 operands[2], operands[3]));
6199 (define_insn "extzv_32"
6200 [(set (match_operand:SI 0 "register_operand" "=r")
6201 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6202 (match_operand:SI 2 "uint5_operand" "")
6203 (match_operand:SI 3 "uint5_operand" "")))]
6205 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
6206 [(set_attr "type" "shift")
6207 (set_attr "length" "4")])
6210 [(set (match_operand:SI 0 "register_operand" "=r")
6211 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6213 (match_operand:SI 2 "register_operand" "q")))]
6215 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
6216 [(set_attr "type" "shift")
6217 (set_attr "length" "4")])
6219 (define_insn "extzv_64"
6220 [(set (match_operand:DI 0 "register_operand" "=r")
6221 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6222 (match_operand:DI 2 "uint32_operand" "")
6223 (match_operand:DI 3 "uint32_operand" "")))]
6225 "extrd,u %1,%3+%2-1,%2,%0"
6226 [(set_attr "type" "shift")
6227 (set_attr "length" "4")])
6230 [(set (match_operand:DI 0 "register_operand" "=r")
6231 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6233 (match_operand:DI 2 "register_operand" "q")))]
6235 "extrd,u %1,%%sar,1,%0"
6236 [(set_attr "type" "shift")
6237 (set_attr "length" "4")])
6239 (define_expand "extv"
6240 [(set (match_operand 0 "register_operand" "")
6241 (sign_extract (match_operand 1 "register_operand" "")
6242 (match_operand 2 "uint32_operand" "")
6243 (match_operand 3 "uint32_operand" "")))]
6248 emit_insn (gen_extv_64 (operands[0], operands[1],
6249 operands[2], operands[3]));
6251 emit_insn (gen_extv_32 (operands[0], operands[1],
6252 operands[2], operands[3]));
6256 (define_insn "extv_32"
6257 [(set (match_operand:SI 0 "register_operand" "=r")
6258 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6259 (match_operand:SI 2 "uint5_operand" "")
6260 (match_operand:SI 3 "uint5_operand" "")))]
6262 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
6263 [(set_attr "type" "shift")
6264 (set_attr "length" "4")])
6267 [(set (match_operand:SI 0 "register_operand" "=r")
6268 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6270 (match_operand:SI 2 "register_operand" "q")))]
6272 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
6273 [(set_attr "type" "shift")
6274 (set_attr "length" "4")])
6276 (define_insn "extv_64"
6277 [(set (match_operand:DI 0 "register_operand" "=r")
6278 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6279 (match_operand:DI 2 "uint32_operand" "")
6280 (match_operand:DI 3 "uint32_operand" "")))]
6282 "extrd,s %1,%3+%2-1,%2,%0"
6283 [(set_attr "type" "shift")
6284 (set_attr "length" "4")])
6287 [(set (match_operand:DI 0 "register_operand" "=r")
6288 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6290 (match_operand:DI 2 "register_operand" "q")))]
6292 "extrd,s %1,%%sar,1,%0"
6293 [(set_attr "type" "shift")
6294 (set_attr "length" "4")])
6296 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
6297 (define_expand "insv"
6298 [(set (zero_extract (match_operand 0 "register_operand" "")
6299 (match_operand 1 "uint32_operand" "")
6300 (match_operand 2 "uint32_operand" ""))
6301 (match_operand 3 "arith5_operand" ""))]
6306 emit_insn (gen_insv_64 (operands[0], operands[1],
6307 operands[2], operands[3]));
6309 emit_insn (gen_insv_32 (operands[0], operands[1],
6310 operands[2], operands[3]));
6314 (define_insn "insv_32"
6315 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
6316 (match_operand:SI 1 "uint5_operand" "")
6317 (match_operand:SI 2 "uint5_operand" ""))
6318 (match_operand:SI 3 "arith5_operand" "r,L"))]
6321 {dep|depw} %3,%2+%1-1,%1,%0
6322 {depi|depwi} %3,%2+%1-1,%1,%0"
6323 [(set_attr "type" "shift,shift")
6324 (set_attr "length" "4,4")])
6326 ;; Optimize insertion of const_int values of type 1...1xxxx.
6328 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
6329 (match_operand:SI 1 "uint5_operand" "")
6330 (match_operand:SI 2 "uint5_operand" ""))
6331 (match_operand:SI 3 "const_int_operand" ""))]
6332 "(INTVAL (operands[3]) & 0x10) != 0 &&
6333 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6336 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6337 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
6339 [(set_attr "type" "shift")
6340 (set_attr "length" "4")])
6342 (define_insn "insv_64"
6343 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
6344 (match_operand:DI 1 "uint32_operand" "")
6345 (match_operand:DI 2 "uint32_operand" ""))
6346 (match_operand:DI 3 "arith32_operand" "r,L"))]
6349 depd %3,%2+%1-1,%1,%0
6350 depdi %3,%2+%1-1,%1,%0"
6351 [(set_attr "type" "shift,shift")
6352 (set_attr "length" "4,4")])
6354 ;; Optimize insertion of const_int values of type 1...1xxxx.
6356 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
6357 (match_operand:DI 1 "uint32_operand" "")
6358 (match_operand:DI 2 "uint32_operand" ""))
6359 (match_operand:DI 3 "const_int_operand" ""))]
6360 "(INTVAL (operands[3]) & 0x10) != 0
6362 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6365 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6366 return \"depdi %3,%2+%1-1,%1,%0\";
6368 [(set_attr "type" "shift")
6369 (set_attr "length" "4")])
6372 [(set (match_operand:DI 0 "register_operand" "=r")
6373 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
6376 "depd,z %1,31,32,%0"
6377 [(set_attr "type" "shift")
6378 (set_attr "length" "4")])
6380 ;; This insn is used for some loop tests, typically loops reversed when
6381 ;; strength reduction is used. It is actually created when the instruction
6382 ;; combination phase combines the special loop test. Since this insn
6383 ;; is both a jump insn and has an output, it must deal with its own
6384 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
6385 ;; to not choose the register alternatives in the event a reload is needed.
6386 (define_insn "decrement_and_branch_until_zero"
6389 (match_operator 2 "comparison_operator"
6390 [(plus:SI (match_operand:SI 0 "register_operand" "+!r,!*f,!*m")
6391 (match_operand:SI 1 "int5_operand" "L,L,L"))
6393 (label_ref (match_operand 3 "" ""))
6396 (plus:SI (match_dup 0) (match_dup 1)))
6397 (clobber (match_scratch:SI 4 "=X,r,r"))]
6399 "* return output_dbra (operands, insn, which_alternative); "
6400 ;; Do not expect to understand this the first time through.
6401 [(set_attr "type" "cbranch,multi,multi")
6402 (set (attr "length")
6403 (if_then_else (eq_attr "alternative" "0")
6404 ;; Loop counter in register case
6405 ;; Short branch has length of 4
6406 ;; Long branch has length of 8
6407 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6412 ;; Loop counter in FP reg case.
6413 ;; Extra goo to deal with additional reload insns.
6414 (if_then_else (eq_attr "alternative" "1")
6415 (if_then_else (lt (match_dup 3) (pc))
6417 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
6422 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6426 ;; Loop counter in memory case.
6427 ;; Extra goo to deal with additional reload insns.
6428 (if_then_else (lt (match_dup 3) (pc))
6430 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6435 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6438 (const_int 16))))))])
6443 (match_operator 2 "movb_comparison_operator"
6444 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6445 (label_ref (match_operand 3 "" ""))
6447 (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
6450 "* return output_movb (operands, insn, which_alternative, 0); "
6451 ;; Do not expect to understand this the first time through.
6452 [(set_attr "type" "cbranch,multi,multi,multi")
6453 (set (attr "length")
6454 (if_then_else (eq_attr "alternative" "0")
6455 ;; Loop counter in register case
6456 ;; Short branch has length of 4
6457 ;; Long branch has length of 8
6458 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6463 ;; Loop counter in FP reg case.
6464 ;; Extra goo to deal with additional reload insns.
6465 (if_then_else (eq_attr "alternative" "1")
6466 (if_then_else (lt (match_dup 3) (pc))
6468 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6473 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6477 ;; Loop counter in memory or sar case.
6478 ;; Extra goo to deal with additional reload insns.
6480 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6483 (const_int 12)))))])
6485 ;; Handle negated branch.
6489 (match_operator 2 "movb_comparison_operator"
6490 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6492 (label_ref (match_operand 3 "" ""))))
6493 (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
6496 "* return output_movb (operands, insn, which_alternative, 1); "
6497 ;; Do not expect to understand this the first time through.
6498 [(set_attr "type" "cbranch,multi,multi,multi")
6499 (set (attr "length")
6500 (if_then_else (eq_attr "alternative" "0")
6501 ;; Loop counter in register case
6502 ;; Short branch has length of 4
6503 ;; Long branch has length of 8
6504 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6509 ;; Loop counter in FP reg case.
6510 ;; Extra goo to deal with additional reload insns.
6511 (if_then_else (eq_attr "alternative" "1")
6512 (if_then_else (lt (match_dup 3) (pc))
6514 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6519 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6523 ;; Loop counter in memory or SAR case.
6524 ;; Extra goo to deal with additional reload insns.
6526 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6529 (const_int 12)))))])
6532 [(set (pc) (label_ref (match_operand 3 "" "" )))
6533 (set (match_operand:SI 0 "ireg_operand" "=r")
6534 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
6535 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
6536 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
6539 return output_parallel_addb (operands, get_attr_length (insn));
6541 [(set_attr "type" "parallel_branch")
6542 (set (attr "length")
6543 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6549 [(set (pc) (label_ref (match_operand 2 "" "" )))
6550 (set (match_operand:SF 0 "ireg_operand" "=r")
6551 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
6555 return output_parallel_movb (operands, get_attr_length (insn));
6557 [(set_attr "type" "parallel_branch")
6558 (set (attr "length")
6559 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6565 [(set (pc) (label_ref (match_operand 2 "" "" )))
6566 (set (match_operand:SI 0 "ireg_operand" "=r")
6567 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
6571 return output_parallel_movb (operands, get_attr_length (insn));
6573 [(set_attr "type" "parallel_branch")
6574 (set (attr "length")
6575 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6581 [(set (pc) (label_ref (match_operand 2 "" "" )))
6582 (set (match_operand:HI 0 "ireg_operand" "=r")
6583 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
6587 return output_parallel_movb (operands, get_attr_length (insn));
6589 [(set_attr "type" "parallel_branch")
6590 (set (attr "length")
6591 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6597 [(set (pc) (label_ref (match_operand 2 "" "" )))
6598 (set (match_operand:QI 0 "ireg_operand" "=r")
6599 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
6603 return output_parallel_movb (operands, get_attr_length (insn));
6605 [(set_attr "type" "parallel_branch")
6606 (set (attr "length")
6607 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6613 [(set (match_operand 0 "register_operand" "=f")
6614 (mult (match_operand 1 "register_operand" "f")
6615 (match_operand 2 "register_operand" "f")))
6616 (set (match_operand 3 "register_operand" "+f")
6617 (plus (match_operand 4 "register_operand" "f")
6618 (match_operand 5 "register_operand" "f")))]
6619 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6620 && reload_completed && fmpyaddoperands (operands)"
6623 if (GET_MODE (operands[0]) == DFmode)
6625 if (rtx_equal_p (operands[3], operands[5]))
6626 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
6628 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
6632 if (rtx_equal_p (operands[3], operands[5]))
6633 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
6635 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
6638 [(set_attr "type" "fpalu")
6639 (set_attr "length" "4")])
6642 [(set (match_operand 3 "register_operand" "+f")
6643 (plus (match_operand 4 "register_operand" "f")
6644 (match_operand 5 "register_operand" "f")))
6645 (set (match_operand 0 "register_operand" "=f")
6646 (mult (match_operand 1 "register_operand" "f")
6647 (match_operand 2 "register_operand" "f")))]
6648 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6649 && reload_completed && fmpyaddoperands (operands)"
6652 if (GET_MODE (operands[0]) == DFmode)
6654 if (rtx_equal_p (operands[3], operands[5]))
6655 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
6657 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
6661 if (rtx_equal_p (operands[3], operands[5]))
6662 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
6664 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
6667 [(set_attr "type" "fpalu")
6668 (set_attr "length" "4")])
6671 [(set (match_operand 0 "register_operand" "=f")
6672 (mult (match_operand 1 "register_operand" "f")
6673 (match_operand 2 "register_operand" "f")))
6674 (set (match_operand 3 "register_operand" "+f")
6675 (minus (match_operand 4 "register_operand" "f")
6676 (match_operand 5 "register_operand" "f")))]
6677 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6678 && reload_completed && fmpysuboperands (operands)"
6681 if (GET_MODE (operands[0]) == DFmode)
6682 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
6684 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
6686 [(set_attr "type" "fpalu")
6687 (set_attr "length" "4")])
6690 [(set (match_operand 3 "register_operand" "+f")
6691 (minus (match_operand 4 "register_operand" "f")
6692 (match_operand 5 "register_operand" "f")))
6693 (set (match_operand 0 "register_operand" "=f")
6694 (mult (match_operand 1 "register_operand" "f")
6695 (match_operand 2 "register_operand" "f")))]
6696 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6697 && reload_completed && fmpysuboperands (operands)"
6700 if (GET_MODE (operands[0]) == DFmode)
6701 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
6703 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
6705 [(set_attr "type" "fpalu")
6706 (set_attr "length" "4")])
6708 ;; Clean up turds left by reload.
6710 [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
6711 (match_operand 1 "register_operand" "fr"))
6712 (set (match_operand 2 "register_operand" "fr")
6714 "! TARGET_SOFT_FLOAT
6715 && GET_CODE (operands[0]) == MEM
6716 && ! MEM_VOLATILE_P (operands[0])
6717 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6718 && GET_MODE (operands[0]) == GET_MODE (operands[2])
6719 && GET_MODE (operands[0]) == DFmode
6720 && GET_CODE (operands[1]) == REG
6721 && GET_CODE (operands[2]) == REG
6722 && ! side_effects_p (XEXP (operands[0], 0))
6723 && REGNO_REG_CLASS (REGNO (operands[1]))
6724 == REGNO_REG_CLASS (REGNO (operands[2]))"
6729 if (FP_REG_P (operands[1]))
6730 output_asm_insn (output_fp_move_double (operands), operands);
6732 output_asm_insn (output_move_double (operands), operands);
6734 if (rtx_equal_p (operands[1], operands[2]))
6737 xoperands[0] = operands[2];
6738 xoperands[1] = operands[1];
6740 if (FP_REG_P (xoperands[1]))
6741 output_asm_insn (output_fp_move_double (xoperands), xoperands);
6743 output_asm_insn (output_move_double (xoperands), xoperands);
6749 [(set (match_operand 0 "register_operand" "fr")
6750 (match_operand 1 "reg_or_nonsymb_mem_operand" ""))
6751 (set (match_operand 2 "register_operand" "fr")
6753 "! TARGET_SOFT_FLOAT
6754 && GET_CODE (operands[1]) == MEM
6755 && ! MEM_VOLATILE_P (operands[1])
6756 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6757 && GET_MODE (operands[0]) == GET_MODE (operands[2])
6758 && GET_MODE (operands[0]) == DFmode
6759 && GET_CODE (operands[0]) == REG
6760 && GET_CODE (operands[2]) == REG
6761 && ! side_effects_p (XEXP (operands[1], 0))
6762 && REGNO_REG_CLASS (REGNO (operands[0]))
6763 == REGNO_REG_CLASS (REGNO (operands[2]))"
6768 if (FP_REG_P (operands[0]))
6769 output_asm_insn (output_fp_move_double (operands), operands);
6771 output_asm_insn (output_move_double (operands), operands);
6773 xoperands[0] = operands[2];
6774 xoperands[1] = operands[0];
6776 if (FP_REG_P (xoperands[1]))
6777 output_asm_insn (output_fp_move_double (xoperands), xoperands);
6779 output_asm_insn (output_move_double (xoperands), xoperands);
6784 ;; Flush the I and D cache line found at the address in operand 0.
6785 ;; This is used by the trampoline code for nested functions.
6786 ;; So long as the trampoline itself is less than 32 bytes this
6789 (define_insn "dcacheflush"
6790 [(unspec_volatile [(const_int 1)] 0)
6791 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
6792 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
6794 "fdc 0(%0)\;fdc 0(%1)\;sync"
6795 [(set_attr "type" "multi")
6796 (set_attr "length" "12")])
6798 (define_insn "icacheflush"
6799 [(unspec_volatile [(const_int 2)] 0)
6800 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
6801 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
6802 (use (match_operand 2 "pmode_register_operand" "r"))
6803 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
6804 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
6806 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
6807 [(set_attr "type" "multi")
6808 (set_attr "length" "52")])
6810 ;; An out-of-line prologue.
6811 (define_insn "outline_prologue_call"
6812 [(unspec_volatile [(const_int 0)] 0)
6813 (clobber (reg:SI 31))
6814 (clobber (reg:SI 22))
6815 (clobber (reg:SI 21))
6816 (clobber (reg:SI 20))
6817 (clobber (reg:SI 19))
6818 (clobber (reg:SI 1))]
6822 extern int frame_pointer_needed;
6824 /* We need two different versions depending on whether or not we
6825 need a frame pointer. Also note that we return to the instruction
6826 immediately after the branch rather than two instructions after the
6827 break as normally is the case. */
6828 if (frame_pointer_needed)
6830 /* Must import the magic millicode routine(s). */
6831 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
6833 if (TARGET_PORTABLE_RUNTIME)
6835 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
6836 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
6840 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
6844 /* Must import the magic millicode routine(s). */
6845 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
6847 if (TARGET_PORTABLE_RUNTIME)
6849 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
6850 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
6853 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
6857 [(set_attr "type" "multi")
6858 (set_attr "length" "8")])
6860 ;; An out-of-line epilogue.
6861 (define_insn "outline_epilogue_call"
6862 [(unspec_volatile [(const_int 1)] 0)
6865 (clobber (reg:SI 31))
6866 (clobber (reg:SI 22))
6867 (clobber (reg:SI 21))
6868 (clobber (reg:SI 20))
6869 (clobber (reg:SI 19))
6870 (clobber (reg:SI 2))
6871 (clobber (reg:SI 1))]
6875 extern int frame_pointer_needed;
6877 /* We need two different versions depending on whether or not we
6878 need a frame pointer. Also note that we return to the instruction
6879 immediately after the branch rather than two instructions after the
6880 break as normally is the case. */
6881 if (frame_pointer_needed)
6883 /* Must import the magic millicode routine. */
6884 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
6886 /* The out-of-line prologue will make sure we return to the right
6888 if (TARGET_PORTABLE_RUNTIME)
6890 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
6891 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
6895 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
6899 /* Must import the magic millicode routine. */
6900 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
6902 /* The out-of-line prologue will make sure we return to the right
6904 if (TARGET_PORTABLE_RUNTIME)
6906 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
6907 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
6910 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
6914 [(set_attr "type" "multi")
6915 (set_attr "length" "8")])
6917 ;; Given a function pointer, canonicalize it so it can be
6918 ;; reliably compared to another function pointer. */
6919 (define_expand "canonicalize_funcptr_for_compare"
6920 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
6921 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
6922 (clobber (match_dup 2))
6923 (clobber (reg:SI 26))
6924 (clobber (reg:SI 22))
6925 (clobber (reg:SI 31))])
6926 (set (match_operand:SI 0 "register_operand" "")
6928 "! TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6931 operands[2] = gen_reg_rtx (SImode);
6932 if (GET_CODE (operands[1]) != REG)
6934 rtx tmp = gen_reg_rtx (Pmode);
6935 emit_move_insn (tmp, operands[1]);
6941 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
6942 (clobber (match_operand:SI 0 "register_operand" "=a"))
6943 (clobber (reg:SI 26))
6944 (clobber (reg:SI 22))
6945 (clobber (reg:SI 31))]
6949 /* Must import the magic millicode routine. */
6950 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
6952 /* This is absolutely amazing.
6954 First, copy our input parameter into %r29 just in case we don't
6955 need to call $$sh_func_adrs. */
6956 output_asm_insn (\"copy %%r26,%%r29\", NULL);
6958 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
6959 we use %r26 unchanged. */
6960 if (get_attr_length (insn) == 32)
6961 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+24\", NULL);
6962 else if (get_attr_length (insn) == 40)
6963 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+32\", NULL);
6964 else if (get_attr_length (insn) == 44)
6965 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+36\", NULL);
6967 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+20\", NULL);
6969 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
6970 4096, then we use %r26 unchanged. */
6971 if (get_attr_length (insn) == 32)
6972 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+16\",
6974 else if (get_attr_length (insn) == 40)
6975 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+24\",
6977 else if (get_attr_length (insn) == 44)
6978 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+28\",
6981 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+12\",
6984 /* Else call $$sh_func_adrs to extract the function's real add24. */
6985 return output_millicode_call (insn,
6986 gen_rtx_SYMBOL_REF (SImode,
6987 \"$$sh_func_adrs\"));
6989 [(set_attr "type" "multi")
6990 (set (attr "length")
6992 ;; Target (or stub) within reach
6993 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
6995 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
7000 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
7004 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
7005 ;; same as NO_SPACE_REGS code
7006 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
7008 (eq (symbol_ref "flag_pic")
7013 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
7017 ;; Out of range and PIC
7020 ;; On the PA, the PIC register is call clobbered, so it must
7021 ;; be saved & restored around calls by the caller. If the call
7022 ;; doesn't return normally (nonlocal goto, or an exception is
7023 ;; thrown), then the code at the exception handler label must
7024 ;; restore the PIC register.
7025 (define_expand "exception_receiver"
7027 "!TARGET_PORTABLE_RUNTIME && flag_pic"
7030 /* Load the PIC register from the stack slot (in our caller's
7032 emit_move_insn (pic_offset_table_rtx,
7033 gen_rtx_MEM (SImode,
7034 plus_constant (stack_pointer_rtx, -32)));
7035 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
7036 emit_insn (gen_blockage ());