1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
32 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
33 (UNSPEC_GOTO 1) ; indirect_goto
34 (UNSPEC_DLTIND14R 2) ;
40 [(UNSPECV_BLOCKAGE 0) ; blockage
41 (UNSPECV_DCACHE 1) ; dcacheflush
42 (UNSPECV_ICACHE 2) ; icacheflush
43 (UNSPECV_OPC 3) ; outline_prologue_call
44 (UNSPECV_OEC 4) ; outline_epilogue_call
45 (UNSPECV_LONGJMP 5) ; builtin_longjmp
48 ;; Insn type. Used to default other attribute values.
50 ;; type "unary" insns have one input operand (1) and one output operand (0)
51 ;; type "binary" insns have two input operands (1,2) and one output (0)
54 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
55 (const_string "binary"))
57 (define_attr "pa_combine_type"
58 "fmpy,faddsub,uncond_branch,addmove,none"
59 (const_string "none"))
61 ;; Processor type (for scheduling, not code generation) -- this attribute
62 ;; must exactly match the processor_type enumeration in pa.h.
64 ;; FIXME: Add 800 scheduling for completeness?
66 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
68 ;; Length (in # of bytes).
69 (define_attr "length" ""
70 (cond [(eq_attr "type" "load,fpload")
71 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
72 (const_int 8) (const_int 4))
74 (eq_attr "type" "store,fpstore")
75 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
76 (const_int 8) (const_int 4))
78 (eq_attr "type" "binary,shift,nullshift")
79 (if_then_else (match_operand 2 "arith_operand" "")
80 (const_int 4) (const_int 12))
82 (eq_attr "type" "move,unary,shift,nullshift")
83 (if_then_else (match_operand 1 "arith_operand" "")
84 (const_int 4) (const_int 8))]
88 (define_asm_attributes
89 [(set_attr "length" "4")
90 (set_attr "type" "multi")])
92 ;; Attributes for instruction and branch scheduling
94 ;; For conditional branches.
95 (define_attr "in_branch_delay" "false,true"
96 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
97 (eq_attr "length" "4"))
99 (const_string "false")))
101 ;; Disallow instructions which use the FPU since they will tie up the FPU
102 ;; even if the instruction is nullified.
103 (define_attr "in_nullified_branch_delay" "false,true"
104 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
105 (eq_attr "length" "4"))
106 (const_string "true")
107 (const_string "false")))
109 ;; For calls and millicode calls. Allow unconditional branches in the
111 (define_attr "in_call_delay" "false,true"
112 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
113 (eq_attr "length" "4"))
114 (const_string "true")
115 (eq_attr "type" "uncond_branch")
116 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
118 (const_string "true")
119 (const_string "false"))]
120 (const_string "false")))
123 ;; Call delay slot description.
124 (define_delay (eq_attr "type" "call")
125 [(eq_attr "in_call_delay" "true") (nil) (nil)])
127 ;; Millicode call delay slot description.
128 (define_delay (eq_attr "type" "milli")
129 [(eq_attr "in_call_delay" "true") (nil) (nil)])
131 ;; Return and other similar instructions.
132 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
133 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
135 ;; Floating point conditional branch delay slot description and
136 (define_delay (eq_attr "type" "fbranch")
137 [(eq_attr "in_branch_delay" "true")
138 (eq_attr "in_nullified_branch_delay" "true")
141 ;; Integer conditional branch delay slot description.
142 ;; Nullification of conditional branches on the PA is dependent on the
143 ;; direction of the branch. Forward branches nullify true and
144 ;; backward branches nullify false. If the direction is unknown
145 ;; then nullification is not allowed.
146 (define_delay (eq_attr "type" "cbranch")
147 [(eq_attr "in_branch_delay" "true")
148 (and (eq_attr "in_nullified_branch_delay" "true")
149 (attr_flag "forward"))
150 (and (eq_attr "in_nullified_branch_delay" "true")
151 (attr_flag "backward"))])
153 (define_delay (and (eq_attr "type" "uncond_branch")
154 (eq (symbol_ref "following_call (insn)")
156 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
158 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
159 ;; load: 2, fpload: 3
160 ;; store, fpstore: 3, no D-cache operations should be scheduled.
162 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
164 ;; Instruction Time Unit Minimum Distance (unit contention)
171 ;; fmpyadd 3 ALU,MPY 2
172 ;; fmpysub 3 ALU,MPY 2
173 ;; fmpycfxt 3 ALU,MPY 2
176 ;; fdiv,sgl 10 MPY 10
177 ;; fdiv,dbl 12 MPY 12
178 ;; fsqrt,sgl 14 MPY 14
179 ;; fsqrt,dbl 18 MPY 18
181 ;; We don't model fmpyadd/fmpysub properly as those instructions
182 ;; keep both the FP ALU and MPY units busy. Given that these
183 ;; processors are obsolete, I'm not going to spend the time to
184 ;; model those instructions correctly.
186 (define_automaton "pa700")
187 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
189 (define_insn_reservation "W0" 4
190 (and (eq_attr "type" "fpcc")
191 (eq_attr "cpu" "700"))
194 (define_insn_reservation "W1" 3
195 (and (eq_attr "type" "fpalu")
196 (eq_attr "cpu" "700"))
199 (define_insn_reservation "W2" 3
200 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
201 (eq_attr "cpu" "700"))
204 (define_insn_reservation "W3" 10
205 (and (eq_attr "type" "fpdivsgl")
206 (eq_attr "cpu" "700"))
209 (define_insn_reservation "W4" 12
210 (and (eq_attr "type" "fpdivdbl")
211 (eq_attr "cpu" "700"))
214 (define_insn_reservation "W5" 14
215 (and (eq_attr "type" "fpsqrtsgl")
216 (eq_attr "cpu" "700"))
219 (define_insn_reservation "W6" 18
220 (and (eq_attr "type" "fpsqrtdbl")
221 (eq_attr "cpu" "700"))
224 (define_insn_reservation "W7" 2
225 (and (eq_attr "type" "load")
226 (eq_attr "cpu" "700"))
229 (define_insn_reservation "W8" 2
230 (and (eq_attr "type" "fpload")
231 (eq_attr "cpu" "700"))
234 (define_insn_reservation "W9" 3
235 (and (eq_attr "type" "store")
236 (eq_attr "cpu" "700"))
239 (define_insn_reservation "W10" 3
240 (and (eq_attr "type" "fpstore")
241 (eq_attr "cpu" "700"))
244 (define_insn_reservation "W11" 1
245 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
246 (eq_attr "cpu" "700"))
249 ;; We have a bypass for all computations in the FP unit which feed an
250 ;; FP store as long as the sizes are the same.
251 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
252 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
253 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
254 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
255 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
257 ;; We have an "anti-bypass" for FP loads which feed an FP store.
258 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
260 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
261 ;; floating point computations with non-floating point computations (fp loads
262 ;; and stores are not fp computations).
264 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
265 ;; take two cycles, during which no Dcache operations should be scheduled.
266 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
267 ;; all have the same memory characteristics if one disregards cache misses.
269 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
270 ;; There's no value in modeling the ALU and MUL separately though
271 ;; since there can never be a functional unit conflict given the
272 ;; latency and issue rates for those units.
275 ;; Instruction Time Unit Minimum Distance (unit contention)
282 ;; fmpyadd 2 ALU,MPY 1
283 ;; fmpysub 2 ALU,MPY 1
284 ;; fmpycfxt 2 ALU,MPY 1
288 ;; fdiv,dbl 15 DIV 15
290 ;; fsqrt,dbl 15 DIV 15
292 (define_automaton "pa7100")
293 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
295 (define_insn_reservation "X0" 2
296 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
297 (eq_attr "cpu" "7100"))
300 (define_insn_reservation "X1" 8
301 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
302 (eq_attr "cpu" "7100"))
303 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
305 (define_insn_reservation "X2" 15
306 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
307 (eq_attr "cpu" "7100"))
308 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
310 (define_insn_reservation "X3" 2
311 (and (eq_attr "type" "load")
312 (eq_attr "cpu" "7100"))
315 (define_insn_reservation "X4" 2
316 (and (eq_attr "type" "fpload")
317 (eq_attr "cpu" "7100"))
320 (define_insn_reservation "X5" 2
321 (and (eq_attr "type" "store")
322 (eq_attr "cpu" "7100"))
323 "i_7100+mem_7100,mem_7100")
325 (define_insn_reservation "X6" 2
326 (and (eq_attr "type" "fpstore")
327 (eq_attr "cpu" "7100"))
328 "i_7100+mem_7100,mem_7100")
330 (define_insn_reservation "X7" 1
331 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
332 (eq_attr "cpu" "7100"))
335 ;; We have a bypass for all computations in the FP unit which feed an
336 ;; FP store as long as the sizes are the same.
337 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
338 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
339 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
341 ;; We have an "anti-bypass" for FP loads which feed an FP store.
342 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
344 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
345 ;; There's no value in modeling the ALU and MUL separately though
346 ;; since there can never be a functional unit conflict that
347 ;; can be avoided given the latency, issue rates and mandatory
348 ;; one cycle cpu-wide lock for a double precision fp multiply.
351 ;; Instruction Time Unit Minimum Distance (unit contention)
358 ;; fmpyadd,sgl 2 ALU,MPY 1
359 ;; fmpyadd,dbl 3 ALU,MPY 2
360 ;; fmpysub,sgl 2 ALU,MPY 1
361 ;; fmpysub,dbl 3 ALU,MPY 2
362 ;; fmpycfxt,sgl 2 ALU,MPY 1
363 ;; fmpycfxt,dbl 3 ALU,MPY 2
368 ;; fdiv,dbl 15 DIV 15
370 ;; fsqrt,dbl 15 DIV 15
372 ;; The PA7200 is just like the PA7100LC except that there is
373 ;; no store-store penalty.
375 ;; The PA7300 is just like the PA7200 except that there is
376 ;; no store-load penalty.
378 ;; Note there are some aspects of the 7100LC we are not modeling
379 ;; at the moment. I'll be reviewing the 7100LC scheduling info
380 ;; shortly and updating this description.
384 ;; other issue modeling
386 (define_automaton "pa7100lc")
387 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
388 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
389 (define_cpu_unit "mem_7100lc" "pa7100lc")
391 ;; Double precision multiplies lock the entire CPU for one
392 ;; cycle. There is no way to avoid this lock and trying to
393 ;; schedule around the lock is pointless and thus there is no
394 ;; value in trying to model this lock.
396 ;; Not modeling the lock allows us to treat fp multiplies just
397 ;; like any other FP alu instruction. It allows for a smaller
398 ;; DFA and may reduce register pressure.
399 (define_insn_reservation "Y0" 2
400 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
401 (eq_attr "cpu" "7100LC,7200,7300"))
402 "f_7100lc,fpmac_7100lc")
404 ;; fp division and sqrt instructions lock the entire CPU for
405 ;; 7 cycles (single precision) or 14 cycles (double precision).
406 ;; There is no way to avoid this lock and trying to schedule
407 ;; around the lock is pointless and thus there is no value in
408 ;; trying to model this lock. Not modeling the lock allows
409 ;; for a smaller DFA and may reduce register pressure.
410 (define_insn_reservation "Y1" 1
411 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
412 (eq_attr "cpu" "7100LC,7200,7300"))
415 (define_insn_reservation "Y2" 2
416 (and (eq_attr "type" "load")
417 (eq_attr "cpu" "7100LC,7200,7300"))
418 "i1_7100lc+mem_7100lc")
420 (define_insn_reservation "Y3" 2
421 (and (eq_attr "type" "fpload")
422 (eq_attr "cpu" "7100LC,7200,7300"))
423 "i1_7100lc+mem_7100lc")
425 (define_insn_reservation "Y4" 2
426 (and (eq_attr "type" "store")
427 (eq_attr "cpu" "7100LC"))
428 "i1_7100lc+mem_7100lc,mem_7100lc")
430 (define_insn_reservation "Y5" 2
431 (and (eq_attr "type" "fpstore")
432 (eq_attr "cpu" "7100LC"))
433 "i1_7100lc+mem_7100lc,mem_7100lc")
435 (define_insn_reservation "Y6" 1
436 (and (eq_attr "type" "shift,nullshift")
437 (eq_attr "cpu" "7100LC,7200,7300"))
440 (define_insn_reservation "Y7" 1
441 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
442 (eq_attr "cpu" "7100LC,7200,7300"))
443 "(i0_7100lc|i1_7100lc)")
445 ;; The 7200 has a store-load penalty
446 (define_insn_reservation "Y8" 2
447 (and (eq_attr "type" "store")
448 (eq_attr "cpu" "7200"))
449 "i1_7100lc,mem_7100lc")
451 (define_insn_reservation "Y9" 2
452 (and (eq_attr "type" "fpstore")
453 (eq_attr "cpu" "7200"))
454 "i1_7100lc,mem_7100lc")
456 ;; The 7300 has no penalty for store-store or store-load
457 (define_insn_reservation "Y10" 2
458 (and (eq_attr "type" "store")
459 (eq_attr "cpu" "7300"))
462 (define_insn_reservation "Y11" 2
463 (and (eq_attr "type" "fpstore")
464 (eq_attr "cpu" "7300"))
467 ;; We have an "anti-bypass" for FP loads which feed an FP store.
468 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
470 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
471 ;; traditional architecture.
473 ;; The PA8000 has a large (56) entry reorder buffer that is split between
474 ;; memory and non-memory operations.
476 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
477 ;; the function units, with the exception of branches and multi-output
478 ;; instructions. The PA8000 can retire two non-memory operations per cycle
479 ;; and two memory operations per cycle, only one of which may be a store.
481 ;; Given the large reorder buffer, the processor can hide most latencies.
482 ;; According to HP, they've got the best results by scheduling for retirement
483 ;; bandwidth with limited latency scheduling for floating point operations.
484 ;; Latency for integer operations and memory references is ignored.
487 ;; We claim floating point operations have a 2 cycle latency and are
488 ;; fully pipelined, except for div and sqrt which are not pipelined and
489 ;; take from 17 to 31 cycles to complete.
491 ;; It's worth noting that there is no way to saturate all the functional
492 ;; units on the PA8000 as there is not enough issue bandwidth.
494 (define_automaton "pa8000")
495 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
496 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
497 (define_cpu_unit "store_8000" "pa8000")
498 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
499 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
500 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
501 (define_reservation "im_8000" "im0_8000 | im1_8000")
502 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
503 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
504 (define_reservation "f_8000" "f0_8000 | f1_8000")
505 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
507 ;; We can issue any two memops per cycle, but we can only retire
508 ;; one memory store per cycle. We assume that the reorder buffer
509 ;; will hide any memory latencies per HP's recommendation.
510 (define_insn_reservation "Z0" 0
512 (eq_attr "type" "load,fpload")
513 (eq_attr "cpu" "8000"))
516 (define_insn_reservation "Z1" 0
518 (eq_attr "type" "store,fpstore")
519 (eq_attr "cpu" "8000"))
520 "im_8000,rm_8000+store_8000")
522 ;; We can issue and retire two non-memory operations per cycle with
523 ;; a few exceptions (branches). This group catches those we want
524 ;; to assume have zero latency.
525 (define_insn_reservation "Z2" 0
527 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
528 (eq_attr "cpu" "8000"))
531 ;; Branches use both slots in the non-memory issue and
533 (define_insn_reservation "Z3" 0
535 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
536 (eq_attr "cpu" "8000"))
537 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
539 ;; We partial latency schedule the floating point units.
540 ;; They can issue/retire two at a time in the non-memory
541 ;; units. We fix their latency at 2 cycles and they
542 ;; are fully pipelined.
543 (define_insn_reservation "Z4" 1
545 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
546 (eq_attr "cpu" "8000"))
547 "inm_8000,f_8000,rnm_8000")
549 ;; The fdivsqrt units are not pipelined and have a very long latency.
550 ;; To keep the DFA from exploding, we do not show all the
551 ;; reservations for the divsqrt unit.
552 (define_insn_reservation "Z5" 17
554 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
555 (eq_attr "cpu" "8000"))
556 "inm_8000,fdivsqrt_8000*6,rnm_8000")
558 (define_insn_reservation "Z6" 31
560 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
561 (eq_attr "cpu" "8000"))
562 "inm_8000,fdivsqrt_8000*6,rnm_8000")
566 ;; Compare instructions.
567 ;; This controls RTL generation and register allocation.
569 ;; We generate RTL for comparisons and branches by having the cmpxx
570 ;; patterns store away the operands. Then, the scc and bcc patterns
571 ;; emit RTL for both the compare and the branch.
574 (define_expand "cmpdi"
576 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
577 (match_operand:DI 1 "register_operand" "")))]
582 hppa_compare_op0 = operands[0];
583 hppa_compare_op1 = operands[1];
584 hppa_branch_type = CMP_SI;
588 (define_expand "cmpsi"
590 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
591 (match_operand:SI 1 "arith5_operand" "")))]
595 hppa_compare_op0 = operands[0];
596 hppa_compare_op1 = operands[1];
597 hppa_branch_type = CMP_SI;
601 (define_expand "cmpsf"
603 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
604 (match_operand:SF 1 "reg_or_0_operand" "")))]
605 "! TARGET_SOFT_FLOAT"
608 hppa_compare_op0 = operands[0];
609 hppa_compare_op1 = operands[1];
610 hppa_branch_type = CMP_SF;
614 (define_expand "cmpdf"
616 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
617 (match_operand:DF 1 "reg_or_0_operand" "")))]
618 "! TARGET_SOFT_FLOAT"
621 hppa_compare_op0 = operands[0];
622 hppa_compare_op1 = operands[1];
623 hppa_branch_type = CMP_DF;
629 (match_operator:CCFP 2 "comparison_operator"
630 [(match_operand:SF 0 "reg_or_0_operand" "fG")
631 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
632 "! TARGET_SOFT_FLOAT"
633 "fcmp,sgl,%Y2 %f0,%f1"
634 [(set_attr "length" "4")
635 (set_attr "type" "fpcc")])
639 (match_operator:CCFP 2 "comparison_operator"
640 [(match_operand:DF 0 "reg_or_0_operand" "fG")
641 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
642 "! TARGET_SOFT_FLOAT"
643 "fcmp,dbl,%Y2 %f0,%f1"
644 [(set_attr "length" "4")
645 (set_attr "type" "fpcc")])
647 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
648 ;; placeholders. This is necessary in rare situations when a
649 ;; placeholder is re-emitted (see PR 8705).
651 (define_expand "movccfp"
653 (match_operand 0 "const_int_operand" ""))]
654 "! TARGET_SOFT_FLOAT"
657 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
661 ;; The following patterns are optimization placeholders. In almost
662 ;; all cases, the user of the condition code will be simplified and the
663 ;; original condition code setting insn should be eliminated.
665 (define_insn "*movccfp0"
668 "! TARGET_SOFT_FLOAT"
669 "fcmp,dbl,= %%fr0,%%fr0"
670 [(set_attr "length" "4")
671 (set_attr "type" "fpcc")])
673 (define_insn "*movccfp1"
676 "! TARGET_SOFT_FLOAT"
677 "fcmp,dbl,!= %%fr0,%%fr0"
678 [(set_attr "length" "4")
679 (set_attr "type" "fpcc")])
684 [(set (match_operand:SI 0 "register_operand" "")
690 /* fp scc patterns rarely match, and are not a win on the PA. */
691 if (hppa_branch_type != CMP_SI)
693 /* set up operands from compare. */
694 operands[1] = hppa_compare_op0;
695 operands[2] = hppa_compare_op1;
696 /* fall through and generate default code */
700 [(set (match_operand:SI 0 "register_operand" "")
706 /* fp scc patterns rarely match, and are not a win on the PA. */
707 if (hppa_branch_type != CMP_SI)
709 operands[1] = hppa_compare_op0;
710 operands[2] = hppa_compare_op1;
714 [(set (match_operand:SI 0 "register_operand" "")
720 /* fp scc patterns rarely match, and are not a win on the PA. */
721 if (hppa_branch_type != CMP_SI)
723 operands[1] = hppa_compare_op0;
724 operands[2] = hppa_compare_op1;
728 [(set (match_operand:SI 0 "register_operand" "")
734 /* fp scc patterns rarely match, and are not a win on the PA. */
735 if (hppa_branch_type != CMP_SI)
737 operands[1] = hppa_compare_op0;
738 operands[2] = hppa_compare_op1;
742 [(set (match_operand:SI 0 "register_operand" "")
748 /* fp scc patterns rarely match, and are not a win on the PA. */
749 if (hppa_branch_type != CMP_SI)
751 operands[1] = hppa_compare_op0;
752 operands[2] = hppa_compare_op1;
756 [(set (match_operand:SI 0 "register_operand" "")
762 /* fp scc patterns rarely match, and are not a win on the PA. */
763 if (hppa_branch_type != CMP_SI)
765 operands[1] = hppa_compare_op0;
766 operands[2] = hppa_compare_op1;
769 (define_expand "sltu"
770 [(set (match_operand:SI 0 "register_operand" "")
771 (ltu:SI (match_dup 1)
776 if (hppa_branch_type != CMP_SI)
778 operands[1] = hppa_compare_op0;
779 operands[2] = hppa_compare_op1;
782 (define_expand "sgtu"
783 [(set (match_operand:SI 0 "register_operand" "")
784 (gtu:SI (match_dup 1)
789 if (hppa_branch_type != CMP_SI)
791 operands[1] = hppa_compare_op0;
792 operands[2] = hppa_compare_op1;
795 (define_expand "sleu"
796 [(set (match_operand:SI 0 "register_operand" "")
797 (leu:SI (match_dup 1)
802 if (hppa_branch_type != CMP_SI)
804 operands[1] = hppa_compare_op0;
805 operands[2] = hppa_compare_op1;
808 (define_expand "sgeu"
809 [(set (match_operand:SI 0 "register_operand" "")
810 (geu:SI (match_dup 1)
815 if (hppa_branch_type != CMP_SI)
817 operands[1] = hppa_compare_op0;
818 operands[2] = hppa_compare_op1;
821 ;; Instruction canonicalization puts immediate operands second, which
822 ;; is the reverse of what we want.
825 [(set (match_operand:SI 0 "register_operand" "=r")
826 (match_operator:SI 3 "comparison_operator"
827 [(match_operand:SI 1 "register_operand" "r")
828 (match_operand:SI 2 "arith11_operand" "rI")]))]
830 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
831 [(set_attr "type" "binary")
832 (set_attr "length" "8")])
835 [(set (match_operand:DI 0 "register_operand" "=r")
836 (match_operator:DI 3 "comparison_operator"
837 [(match_operand:DI 1 "register_operand" "r")
838 (match_operand:DI 2 "arith11_operand" "rI")]))]
840 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
841 [(set_attr "type" "binary")
842 (set_attr "length" "8")])
844 (define_insn "iorscc"
845 [(set (match_operand:SI 0 "register_operand" "=r")
846 (ior:SI (match_operator:SI 3 "comparison_operator"
847 [(match_operand:SI 1 "register_operand" "r")
848 (match_operand:SI 2 "arith11_operand" "rI")])
849 (match_operator:SI 6 "comparison_operator"
850 [(match_operand:SI 4 "register_operand" "r")
851 (match_operand:SI 5 "arith11_operand" "rI")])))]
853 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
854 [(set_attr "type" "binary")
855 (set_attr "length" "12")])
858 [(set (match_operand:DI 0 "register_operand" "=r")
859 (ior:DI (match_operator:DI 3 "comparison_operator"
860 [(match_operand:DI 1 "register_operand" "r")
861 (match_operand:DI 2 "arith11_operand" "rI")])
862 (match_operator:DI 6 "comparison_operator"
863 [(match_operand:DI 4 "register_operand" "r")
864 (match_operand:DI 5 "arith11_operand" "rI")])))]
866 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
867 [(set_attr "type" "binary")
868 (set_attr "length" "12")])
870 ;; Combiner patterns for common operations performed with the output
871 ;; from an scc insn (negscc and incscc).
872 (define_insn "negscc"
873 [(set (match_operand:SI 0 "register_operand" "=r")
874 (neg:SI (match_operator:SI 3 "comparison_operator"
875 [(match_operand:SI 1 "register_operand" "r")
876 (match_operand:SI 2 "arith11_operand" "rI")])))]
878 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
879 [(set_attr "type" "binary")
880 (set_attr "length" "8")])
883 [(set (match_operand:DI 0 "register_operand" "=r")
884 (neg:DI (match_operator:DI 3 "comparison_operator"
885 [(match_operand:DI 1 "register_operand" "r")
886 (match_operand:DI 2 "arith11_operand" "rI")])))]
888 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
889 [(set_attr "type" "binary")
890 (set_attr "length" "8")])
892 ;; Patterns for adding/subtracting the result of a boolean expression from
893 ;; a register. First we have special patterns that make use of the carry
894 ;; bit, and output only two instructions. For the cases we can't in
895 ;; general do in two instructions, the incscc pattern at the end outputs
896 ;; two or three instructions.
899 [(set (match_operand:SI 0 "register_operand" "=r")
900 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
901 (match_operand:SI 3 "arith11_operand" "rI"))
902 (match_operand:SI 1 "register_operand" "r")))]
904 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
905 [(set_attr "type" "binary")
906 (set_attr "length" "8")])
909 [(set (match_operand:DI 0 "register_operand" "=r")
910 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
911 (match_operand:DI 3 "arith11_operand" "rI"))
912 (match_operand:DI 1 "register_operand" "r")))]
914 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
915 [(set_attr "type" "binary")
916 (set_attr "length" "8")])
918 ; This need only accept registers for op3, since canonicalization
919 ; replaces geu with gtu when op3 is an integer.
921 [(set (match_operand:SI 0 "register_operand" "=r")
922 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
923 (match_operand:SI 3 "register_operand" "r"))
924 (match_operand:SI 1 "register_operand" "r")))]
926 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
927 [(set_attr "type" "binary")
928 (set_attr "length" "8")])
931 [(set (match_operand:DI 0 "register_operand" "=r")
932 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
933 (match_operand:DI 3 "register_operand" "r"))
934 (match_operand:DI 1 "register_operand" "r")))]
936 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
937 [(set_attr "type" "binary")
938 (set_attr "length" "8")])
940 ; Match only integers for op3 here. This is used as canonical form of the
941 ; geu pattern when op3 is an integer. Don't match registers since we can't
942 ; make better code than the general incscc pattern.
944 [(set (match_operand:SI 0 "register_operand" "=r")
945 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
946 (match_operand:SI 3 "int11_operand" "I"))
947 (match_operand:SI 1 "register_operand" "r")))]
949 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
950 [(set_attr "type" "binary")
951 (set_attr "length" "8")])
954 [(set (match_operand:DI 0 "register_operand" "=r")
955 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
956 (match_operand:DI 3 "int11_operand" "I"))
957 (match_operand:DI 1 "register_operand" "r")))]
959 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
960 [(set_attr "type" "binary")
961 (set_attr "length" "8")])
963 (define_insn "incscc"
964 [(set (match_operand:SI 0 "register_operand" "=r,r")
965 (plus:SI (match_operator:SI 4 "comparison_operator"
966 [(match_operand:SI 2 "register_operand" "r,r")
967 (match_operand:SI 3 "arith11_operand" "rI,rI")])
968 (match_operand:SI 1 "register_operand" "0,?r")))]
971 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
972 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
973 [(set_attr "type" "binary,binary")
974 (set_attr "length" "8,12")])
977 [(set (match_operand:DI 0 "register_operand" "=r,r")
978 (plus:DI (match_operator:DI 4 "comparison_operator"
979 [(match_operand:DI 2 "register_operand" "r,r")
980 (match_operand:DI 3 "arith11_operand" "rI,rI")])
981 (match_operand:DI 1 "register_operand" "0,?r")))]
984 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
985 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
986 [(set_attr "type" "binary,binary")
987 (set_attr "length" "8,12")])
990 [(set (match_operand:SI 0 "register_operand" "=r")
991 (minus:SI (match_operand:SI 1 "register_operand" "r")
992 (gtu:SI (match_operand:SI 2 "register_operand" "r")
993 (match_operand:SI 3 "arith11_operand" "rI"))))]
995 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
996 [(set_attr "type" "binary")
997 (set_attr "length" "8")])
1000 [(set (match_operand:DI 0 "register_operand" "=r")
1001 (minus:DI (match_operand:DI 1 "register_operand" "r")
1002 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1003 (match_operand:DI 3 "arith11_operand" "rI"))))]
1005 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1006 [(set_attr "type" "binary")
1007 (set_attr "length" "8")])
1010 [(set (match_operand:SI 0 "register_operand" "=r")
1011 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1012 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1013 (match_operand:SI 3 "arith11_operand" "rI")))
1014 (match_operand:SI 4 "register_operand" "r")))]
1016 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1017 [(set_attr "type" "binary")
1018 (set_attr "length" "8")])
1021 [(set (match_operand:DI 0 "register_operand" "=r")
1022 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1023 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1024 (match_operand:DI 3 "arith11_operand" "rI")))
1025 (match_operand:DI 4 "register_operand" "r")))]
1027 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1028 [(set_attr "type" "binary")
1029 (set_attr "length" "8")])
1031 ; This need only accept registers for op3, since canonicalization
1032 ; replaces ltu with leu when op3 is an integer.
1034 [(set (match_operand:SI 0 "register_operand" "=r")
1035 (minus:SI (match_operand:SI 1 "register_operand" "r")
1036 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1037 (match_operand:SI 3 "register_operand" "r"))))]
1039 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1040 [(set_attr "type" "binary")
1041 (set_attr "length" "8")])
1044 [(set (match_operand:DI 0 "register_operand" "=r")
1045 (minus:DI (match_operand:DI 1 "register_operand" "r")
1046 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1047 (match_operand:DI 3 "register_operand" "r"))))]
1049 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1050 [(set_attr "type" "binary")
1051 (set_attr "length" "8")])
1054 [(set (match_operand:SI 0 "register_operand" "=r")
1055 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1056 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1057 (match_operand:SI 3 "register_operand" "r")))
1058 (match_operand:SI 4 "register_operand" "r")))]
1060 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1061 [(set_attr "type" "binary")
1062 (set_attr "length" "8")])
1065 [(set (match_operand:DI 0 "register_operand" "=r")
1066 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1067 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1068 (match_operand:DI 3 "register_operand" "r")))
1069 (match_operand:DI 4 "register_operand" "r")))]
1071 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1072 [(set_attr "type" "binary")
1073 (set_attr "length" "8")])
1075 ; Match only integers for op3 here. This is used as canonical form of the
1076 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1077 ; make better code than the general incscc pattern.
1079 [(set (match_operand:SI 0 "register_operand" "=r")
1080 (minus:SI (match_operand:SI 1 "register_operand" "r")
1081 (leu:SI (match_operand:SI 2 "register_operand" "r")
1082 (match_operand:SI 3 "int11_operand" "I"))))]
1084 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1085 [(set_attr "type" "binary")
1086 (set_attr "length" "8")])
1089 [(set (match_operand:DI 0 "register_operand" "=r")
1090 (minus:DI (match_operand:DI 1 "register_operand" "r")
1091 (leu:DI (match_operand:DI 2 "register_operand" "r")
1092 (match_operand:DI 3 "int11_operand" "I"))))]
1094 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1095 [(set_attr "type" "binary")
1096 (set_attr "length" "8")])
1099 [(set (match_operand:SI 0 "register_operand" "=r")
1100 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1101 (leu:SI (match_operand:SI 2 "register_operand" "r")
1102 (match_operand:SI 3 "int11_operand" "I")))
1103 (match_operand:SI 4 "register_operand" "r")))]
1105 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1106 [(set_attr "type" "binary")
1107 (set_attr "length" "8")])
1110 [(set (match_operand:DI 0 "register_operand" "=r")
1111 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1112 (leu:DI (match_operand:DI 2 "register_operand" "r")
1113 (match_operand:DI 3 "int11_operand" "I")))
1114 (match_operand:DI 4 "register_operand" "r")))]
1116 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1117 [(set_attr "type" "binary")
1118 (set_attr "length" "8")])
1120 (define_insn "decscc"
1121 [(set (match_operand:SI 0 "register_operand" "=r,r")
1122 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1123 (match_operator:SI 4 "comparison_operator"
1124 [(match_operand:SI 2 "register_operand" "r,r")
1125 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1128 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1129 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1130 [(set_attr "type" "binary,binary")
1131 (set_attr "length" "8,12")])
1134 [(set (match_operand:DI 0 "register_operand" "=r,r")
1135 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1136 (match_operator:DI 4 "comparison_operator"
1137 [(match_operand:DI 2 "register_operand" "r,r")
1138 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1141 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1142 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1143 [(set_attr "type" "binary,binary")
1144 (set_attr "length" "8,12")])
1146 ; Patterns for max and min. (There is no need for an earlyclobber in the
1147 ; last alternative since the middle alternative will match if op0 == op1.)
1149 (define_insn "sminsi3"
1150 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1151 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1152 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1155 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1156 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1157 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1158 [(set_attr "type" "multi,multi,multi")
1159 (set_attr "length" "8,8,8")])
1161 (define_insn "smindi3"
1162 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1163 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1164 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1167 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1168 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1169 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1170 [(set_attr "type" "multi,multi,multi")
1171 (set_attr "length" "8,8,8")])
1173 (define_insn "uminsi3"
1174 [(set (match_operand:SI 0 "register_operand" "=r,r")
1175 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1176 (match_operand:SI 2 "arith11_operand" "r,I")))]
1179 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1180 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1181 [(set_attr "type" "multi,multi")
1182 (set_attr "length" "8,8")])
1184 (define_insn "umindi3"
1185 [(set (match_operand:DI 0 "register_operand" "=r,r")
1186 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1187 (match_operand:DI 2 "arith11_operand" "r,I")))]
1190 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1191 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1192 [(set_attr "type" "multi,multi")
1193 (set_attr "length" "8,8")])
1195 (define_insn "smaxsi3"
1196 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1197 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1198 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1201 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1202 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1203 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1204 [(set_attr "type" "multi,multi,multi")
1205 (set_attr "length" "8,8,8")])
1207 (define_insn "smaxdi3"
1208 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1209 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1210 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1213 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1214 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1215 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1216 [(set_attr "type" "multi,multi,multi")
1217 (set_attr "length" "8,8,8")])
1219 (define_insn "umaxsi3"
1220 [(set (match_operand:SI 0 "register_operand" "=r,r")
1221 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1222 (match_operand:SI 2 "arith11_operand" "r,I")))]
1225 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1226 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1227 [(set_attr "type" "multi,multi")
1228 (set_attr "length" "8,8")])
1230 (define_insn "umaxdi3"
1231 [(set (match_operand:DI 0 "register_operand" "=r,r")
1232 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1233 (match_operand:DI 2 "arith11_operand" "r,I")))]
1236 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1237 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1238 [(set_attr "type" "multi,multi")
1239 (set_attr "length" "8,8")])
1241 (define_insn "abssi2"
1242 [(set (match_operand:SI 0 "register_operand" "=r")
1243 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1245 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1246 [(set_attr "type" "multi")
1247 (set_attr "length" "8")])
1249 (define_insn "absdi2"
1250 [(set (match_operand:DI 0 "register_operand" "=r")
1251 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1253 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1254 [(set_attr "type" "multi")
1255 (set_attr "length" "8")])
1257 ;;; Experimental conditional move patterns
1259 (define_expand "movsicc"
1260 [(set (match_operand:SI 0 "register_operand" "")
1262 (match_operator 1 "comparison_operator"
1265 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1266 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1270 enum rtx_code code = GET_CODE (operands[1]);
1272 if (hppa_branch_type != CMP_SI)
1275 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1276 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1279 /* operands[1] is currently the result of compare_from_rtx. We want to
1280 emit a compare of the original operands. */
1281 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1282 operands[4] = hppa_compare_op0;
1283 operands[5] = hppa_compare_op1;
1286 ;; We used to accept any register for op1.
1288 ;; However, it loses sometimes because the compiler will end up using
1289 ;; different registers for op0 and op1 in some critical cases. local-alloc
1290 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1292 ;; If/when global register allocation supports tying we should allow any
1293 ;; register for op1 again.
1295 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1297 (match_operator 2 "comparison_operator"
1298 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1299 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1300 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1304 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1305 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1306 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1307 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1308 [(set_attr "type" "multi,multi,multi,nullshift")
1309 (set_attr "length" "8,8,8,8")])
1312 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1314 (match_operator 5 "comparison_operator"
1315 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1316 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1317 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1318 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1321 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1322 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1323 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1324 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1325 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1326 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1327 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1328 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1329 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1330 (set_attr "length" "8,8,8,8,8,8,8,8")])
1332 (define_expand "movdicc"
1333 [(set (match_operand:DI 0 "register_operand" "")
1335 (match_operator 1 "comparison_operator"
1338 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1339 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1343 enum rtx_code code = GET_CODE (operands[1]);
1345 if (hppa_branch_type != CMP_SI)
1348 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1349 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1352 /* operands[1] is currently the result of compare_from_rtx. We want to
1353 emit a compare of the original operands. */
1354 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1355 operands[4] = hppa_compare_op0;
1356 operands[5] = hppa_compare_op1;
1359 ; We need the first constraint alternative in order to avoid
1360 ; earlyclobbers on all other alternatives.
1362 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1364 (match_operator 2 "comparison_operator"
1365 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1366 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1367 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1371 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1372 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1373 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1374 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1375 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1376 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1377 (set_attr "length" "8,8,8,8,8")])
1380 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1382 (match_operator 5 "comparison_operator"
1383 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1384 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1385 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1386 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1389 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1390 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1391 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1392 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1393 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1394 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1395 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1396 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1397 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1398 (set_attr "length" "8,8,8,8,8,8,8,8")])
1400 ;; Conditional Branches
1402 (define_expand "beq"
1404 (if_then_else (eq (match_dup 1) (match_dup 2))
1405 (label_ref (match_operand 0 "" ""))
1410 if (hppa_branch_type != CMP_SI)
1412 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1413 emit_bcond_fp (NE, operands[0]);
1416 /* set up operands from compare. */
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1419 /* fall through and generate default code */
1422 (define_expand "bne"
1424 (if_then_else (ne (match_dup 1) (match_dup 2))
1425 (label_ref (match_operand 0 "" ""))
1430 if (hppa_branch_type != CMP_SI)
1432 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1433 emit_bcond_fp (NE, operands[0]);
1436 operands[1] = hppa_compare_op0;
1437 operands[2] = hppa_compare_op1;
1440 (define_expand "bgt"
1442 (if_then_else (gt (match_dup 1) (match_dup 2))
1443 (label_ref (match_operand 0 "" ""))
1448 if (hppa_branch_type != CMP_SI)
1450 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1451 emit_bcond_fp (NE, operands[0]);
1454 operands[1] = hppa_compare_op0;
1455 operands[2] = hppa_compare_op1;
1458 (define_expand "blt"
1460 (if_then_else (lt (match_dup 1) (match_dup 2))
1461 (label_ref (match_operand 0 "" ""))
1466 if (hppa_branch_type != CMP_SI)
1468 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1469 emit_bcond_fp (NE, operands[0]);
1472 operands[1] = hppa_compare_op0;
1473 operands[2] = hppa_compare_op1;
1476 (define_expand "bge"
1478 (if_then_else (ge (match_dup 1) (match_dup 2))
1479 (label_ref (match_operand 0 "" ""))
1484 if (hppa_branch_type != CMP_SI)
1486 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1487 emit_bcond_fp (NE, operands[0]);
1490 operands[1] = hppa_compare_op0;
1491 operands[2] = hppa_compare_op1;
1494 (define_expand "ble"
1496 (if_then_else (le (match_dup 1) (match_dup 2))
1497 (label_ref (match_operand 0 "" ""))
1502 if (hppa_branch_type != CMP_SI)
1504 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1505 emit_bcond_fp (NE, operands[0]);
1508 operands[1] = hppa_compare_op0;
1509 operands[2] = hppa_compare_op1;
1512 (define_expand "bgtu"
1514 (if_then_else (gtu (match_dup 1) (match_dup 2))
1515 (label_ref (match_operand 0 "" ""))
1520 if (hppa_branch_type != CMP_SI)
1522 operands[1] = hppa_compare_op0;
1523 operands[2] = hppa_compare_op1;
1526 (define_expand "bltu"
1528 (if_then_else (ltu (match_dup 1) (match_dup 2))
1529 (label_ref (match_operand 0 "" ""))
1534 if (hppa_branch_type != CMP_SI)
1536 operands[1] = hppa_compare_op0;
1537 operands[2] = hppa_compare_op1;
1540 (define_expand "bgeu"
1542 (if_then_else (geu (match_dup 1) (match_dup 2))
1543 (label_ref (match_operand 0 "" ""))
1548 if (hppa_branch_type != CMP_SI)
1550 operands[1] = hppa_compare_op0;
1551 operands[2] = hppa_compare_op1;
1554 (define_expand "bleu"
1556 (if_then_else (leu (match_dup 1) (match_dup 2))
1557 (label_ref (match_operand 0 "" ""))
1562 if (hppa_branch_type != CMP_SI)
1564 operands[1] = hppa_compare_op0;
1565 operands[2] = hppa_compare_op1;
1568 (define_expand "bltgt"
1570 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1571 (label_ref (match_operand 0 "" ""))
1576 if (hppa_branch_type == CMP_SI)
1578 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1579 emit_bcond_fp (NE, operands[0]);
1583 (define_expand "bunle"
1585 (if_then_else (unle (match_dup 1) (match_dup 2))
1586 (label_ref (match_operand 0 "" ""))
1591 if (hppa_branch_type == CMP_SI)
1593 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1594 emit_bcond_fp (NE, operands[0]);
1598 (define_expand "bunlt"
1600 (if_then_else (unlt (match_dup 1) (match_dup 2))
1601 (label_ref (match_operand 0 "" ""))
1606 if (hppa_branch_type == CMP_SI)
1608 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1609 emit_bcond_fp (NE, operands[0]);
1613 (define_expand "bunge"
1615 (if_then_else (unge (match_dup 1) (match_dup 2))
1616 (label_ref (match_operand 0 "" ""))
1621 if (hppa_branch_type == CMP_SI)
1623 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1624 emit_bcond_fp (NE, operands[0]);
1628 (define_expand "bungt"
1630 (if_then_else (ungt (match_dup 1) (match_dup 2))
1631 (label_ref (match_operand 0 "" ""))
1636 if (hppa_branch_type == CMP_SI)
1638 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1639 emit_bcond_fp (NE, operands[0]);
1643 (define_expand "buneq"
1645 (if_then_else (uneq (match_dup 1) (match_dup 2))
1646 (label_ref (match_operand 0 "" ""))
1651 if (hppa_branch_type == CMP_SI)
1653 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1654 emit_bcond_fp (NE, operands[0]);
1658 (define_expand "bunordered"
1660 (if_then_else (unordered (match_dup 1) (match_dup 2))
1661 (label_ref (match_operand 0 "" ""))
1666 if (hppa_branch_type == CMP_SI)
1668 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1669 emit_bcond_fp (NE, operands[0]);
1673 (define_expand "bordered"
1675 (if_then_else (ordered (match_dup 1) (match_dup 2))
1676 (label_ref (match_operand 0 "" ""))
1681 if (hppa_branch_type == CMP_SI)
1683 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1684 emit_bcond_fp (NE, operands[0]);
1688 ;; Match the branch patterns.
1691 ;; Note a long backward conditional branch with an annulled delay slot
1692 ;; has a length of 12.
1696 (match_operator 3 "comparison_operator"
1697 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1698 (match_operand:SI 2 "arith5_operand" "rL")])
1699 (label_ref (match_operand 0 "" ""))
1704 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1705 get_attr_length (insn), 0, insn);
1707 [(set_attr "type" "cbranch")
1708 (set (attr "length")
1709 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1712 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1715 (eq (symbol_ref "flag_pic") (const_int 0))
1719 ;; Match the negated branch.
1724 (match_operator 3 "comparison_operator"
1725 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1726 (match_operand:SI 2 "arith5_operand" "rL")])
1728 (label_ref (match_operand 0 "" ""))))]
1732 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1733 get_attr_length (insn), 1, insn);
1735 [(set_attr "type" "cbranch")
1736 (set (attr "length")
1737 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1740 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1743 (eq (symbol_ref "flag_pic") (const_int 0))
1750 (match_operator 3 "comparison_operator"
1751 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1752 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1753 (label_ref (match_operand 0 "" ""))
1758 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1759 get_attr_length (insn), 0, insn);
1761 [(set_attr "type" "cbranch")
1762 (set (attr "length")
1763 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1766 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1769 (eq (symbol_ref "flag_pic") (const_int 0))
1773 ;; Match the negated branch.
1778 (match_operator 3 "comparison_operator"
1779 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1780 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1782 (label_ref (match_operand 0 "" ""))))]
1786 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1787 get_attr_length (insn), 1, insn);
1789 [(set_attr "type" "cbranch")
1790 (set (attr "length")
1791 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1794 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1797 (eq (symbol_ref "flag_pic") (const_int 0))
1803 (match_operator 3 "cmpib_comparison_operator"
1804 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1805 (match_operand:DI 2 "arith5_operand" "rL")])
1806 (label_ref (match_operand 0 "" ""))
1811 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1812 get_attr_length (insn), 0, insn);
1814 [(set_attr "type" "cbranch")
1815 (set (attr "length")
1816 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1819 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1822 (eq (symbol_ref "flag_pic") (const_int 0))
1826 ;; Match the negated branch.
1831 (match_operator 3 "cmpib_comparison_operator"
1832 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1833 (match_operand:DI 2 "arith5_operand" "rL")])
1835 (label_ref (match_operand 0 "" ""))))]
1839 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1840 get_attr_length (insn), 1, insn);
1842 [(set_attr "type" "cbranch")
1843 (set (attr "length")
1844 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1847 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1850 (eq (symbol_ref "flag_pic") (const_int 0))
1854 ;; Branch on Bit patterns.
1858 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1860 (match_operand:SI 1 "uint5_operand" ""))
1862 (label_ref (match_operand 2 "" ""))
1867 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1868 get_attr_length (insn), 0, insn, 0);
1870 [(set_attr "type" "cbranch")
1871 (set (attr "length")
1872 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1880 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1882 (match_operand:DI 1 "uint32_operand" ""))
1884 (label_ref (match_operand 2 "" ""))
1889 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1890 get_attr_length (insn), 0, insn, 0);
1892 [(set_attr "type" "cbranch")
1893 (set (attr "length")
1894 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1902 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1904 (match_operand:SI 1 "uint5_operand" ""))
1907 (label_ref (match_operand 2 "" ""))))]
1911 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1912 get_attr_length (insn), 1, insn, 0);
1914 [(set_attr "type" "cbranch")
1915 (set (attr "length")
1916 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1924 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1926 (match_operand:DI 1 "uint32_operand" ""))
1929 (label_ref (match_operand 2 "" ""))))]
1933 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1934 get_attr_length (insn), 1, insn, 0);
1936 [(set_attr "type" "cbranch")
1937 (set (attr "length")
1938 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1946 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1948 (match_operand:SI 1 "uint5_operand" ""))
1950 (label_ref (match_operand 2 "" ""))
1955 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1956 get_attr_length (insn), 0, insn, 1);
1958 [(set_attr "type" "cbranch")
1959 (set (attr "length")
1960 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1968 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1970 (match_operand:DI 1 "uint32_operand" ""))
1972 (label_ref (match_operand 2 "" ""))
1977 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1978 get_attr_length (insn), 0, insn, 1);
1980 [(set_attr "type" "cbranch")
1981 (set (attr "length")
1982 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1990 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1992 (match_operand:SI 1 "uint5_operand" ""))
1995 (label_ref (match_operand 2 "" ""))))]
1999 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2000 get_attr_length (insn), 1, insn, 1);
2002 [(set_attr "type" "cbranch")
2003 (set (attr "length")
2004 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2014 (match_operand:DI 1 "uint32_operand" ""))
2017 (label_ref (match_operand 2 "" ""))))]
2021 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2022 get_attr_length (insn), 1, insn, 1);
2024 [(set_attr "type" "cbranch")
2025 (set (attr "length")
2026 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2031 ;; Branch on Variable Bit patterns.
2035 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2037 (match_operand:SI 1 "register_operand" "q"))
2039 (label_ref (match_operand 2 "" ""))
2044 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2045 get_attr_length (insn), 0, insn, 0);
2047 [(set_attr "type" "cbranch")
2048 (set (attr "length")
2049 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2057 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2059 (match_operand:DI 1 "register_operand" "q"))
2061 (label_ref (match_operand 2 "" ""))
2066 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2067 get_attr_length (insn), 0, insn, 0);
2069 [(set_attr "type" "cbranch")
2070 (set (attr "length")
2071 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2079 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2081 (match_operand:SI 1 "register_operand" "q"))
2084 (label_ref (match_operand 2 "" ""))))]
2088 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2089 get_attr_length (insn), 1, insn, 0);
2091 [(set_attr "type" "cbranch")
2092 (set (attr "length")
2093 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2101 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2103 (match_operand:DI 1 "register_operand" "q"))
2106 (label_ref (match_operand 2 "" ""))))]
2110 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2111 get_attr_length (insn), 1, insn, 0);
2113 [(set_attr "type" "cbranch")
2114 (set (attr "length")
2115 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2123 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2125 (match_operand:SI 1 "register_operand" "q"))
2127 (label_ref (match_operand 2 "" ""))
2132 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2133 get_attr_length (insn), 0, insn, 1);
2135 [(set_attr "type" "cbranch")
2136 (set (attr "length")
2137 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2145 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2147 (match_operand:DI 1 "register_operand" "q"))
2149 (label_ref (match_operand 2 "" ""))
2154 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2155 get_attr_length (insn), 0, insn, 1);
2157 [(set_attr "type" "cbranch")
2158 (set (attr "length")
2159 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2167 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2169 (match_operand:SI 1 "register_operand" "q"))
2172 (label_ref (match_operand 2 "" ""))))]
2176 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2177 get_attr_length (insn), 1, insn, 1);
2179 [(set_attr "type" "cbranch")
2180 (set (attr "length")
2181 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2191 (match_operand:DI 1 "register_operand" "q"))
2194 (label_ref (match_operand 2 "" ""))))]
2198 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2199 get_attr_length (insn), 1, insn, 1);
2201 [(set_attr "type" "cbranch")
2202 (set (attr "length")
2203 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2208 ;; Floating point branches
2210 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2211 (label_ref (match_operand 0 "" ""))
2213 "! TARGET_SOFT_FLOAT"
2216 if (INSN_ANNULLED_BRANCH_P (insn))
2217 return \"ftest\;b,n %0\";
2219 return \"ftest\;b%* %0\";
2221 [(set_attr "type" "fbranch")
2222 (set_attr "length" "8")])
2225 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2227 (label_ref (match_operand 0 "" ""))))]
2228 "! TARGET_SOFT_FLOAT"
2231 if (INSN_ANNULLED_BRANCH_P (insn))
2232 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2234 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2236 [(set_attr "type" "fbranch")
2237 (set_attr "length" "12")])
2239 ;; Move instructions
2241 (define_expand "movsi"
2242 [(set (match_operand:SI 0 "general_operand" "")
2243 (match_operand:SI 1 "general_operand" ""))]
2247 if (emit_move_sequence (operands, SImode, 0))
2251 ;; Reloading an SImode or DImode value requires a scratch register if
2252 ;; going in to or out of float point registers.
2254 (define_expand "reload_insi"
2255 [(set (match_operand:SI 0 "register_operand" "=Z")
2256 (match_operand:SI 1 "non_hard_reg_operand" ""))
2257 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2261 if (emit_move_sequence (operands, SImode, operands[2]))
2264 /* We don't want the clobber emitted, so handle this ourselves. */
2265 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2269 (define_expand "reload_outsi"
2270 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2271 (match_operand:SI 1 "register_operand" "Z"))
2272 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2276 if (emit_move_sequence (operands, SImode, operands[2]))
2279 /* We don't want the clobber emitted, so handle this ourselves. */
2280 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2285 [(set (match_operand:SI 0 "move_dest_operand"
2286 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2287 (match_operand:SI 1 "move_src_operand"
2288 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2289 "(register_operand (operands[0], SImode)
2290 || reg_or_0_operand (operands[1], SImode))
2291 && !TARGET_SOFT_FLOAT"
2297 {zdepi|depwi,z} %Z1,%0
2301 {mfctl|mfctl,w} %%sar,%0
2305 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2306 (set_attr "pa_combine_type" "addmove")
2307 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2310 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2311 (match_operand:SI 1 "register_operand" "f"))]
2313 && !TARGET_DISABLE_INDEXING
2314 && reload_completed"
2316 [(set_attr "type" "fpstore")
2317 (set_attr "pa_combine_type" "addmove")
2318 (set_attr "length" "4")])
2320 ; Rewrite RTL using an indexed store. This will allow the insn that
2321 ; computes the address to be deleted if the register it sets is dead.
2323 [(set (match_operand:SI 0 "register_operand" "")
2324 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2326 (match_operand:SI 2 "register_operand" "")))
2327 (set (mem:SI (match_dup 0))
2328 (match_operand:SI 3 "register_operand" ""))]
2330 && !TARGET_DISABLE_INDEXING
2331 && REG_OK_FOR_BASE_P (operands[2])
2332 && FP_REGNO_P (REGNO (operands[3]))"
2333 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2335 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2340 [(set (match_operand:SI 0 "register_operand" "")
2341 (plus:SI (match_operand:SI 2 "register_operand" "")
2342 (mult:SI (match_operand:SI 1 "register_operand" "")
2344 (set (mem:SI (match_dup 0))
2345 (match_operand:SI 3 "register_operand" ""))]
2347 && !TARGET_DISABLE_INDEXING
2348 && REG_OK_FOR_BASE_P (operands[2])
2349 && FP_REGNO_P (REGNO (operands[3]))"
2350 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2352 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2357 [(set (match_operand:DI 0 "register_operand" "")
2358 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2360 (match_operand:DI 2 "register_operand" "")))
2361 (set (mem:SI (match_dup 0))
2362 (match_operand:SI 3 "register_operand" ""))]
2364 && !TARGET_DISABLE_INDEXING
2366 && REG_OK_FOR_BASE_P (operands[2])
2367 && FP_REGNO_P (REGNO (operands[3]))"
2368 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2370 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2375 [(set (match_operand:DI 0 "register_operand" "")
2376 (plus:DI (match_operand:DI 2 "register_operand" "")
2377 (mult:DI (match_operand:DI 1 "register_operand" "")
2379 (set (mem:SI (match_dup 0))
2380 (match_operand:SI 3 "register_operand" ""))]
2382 && !TARGET_DISABLE_INDEXING
2384 && REG_OK_FOR_BASE_P (operands[2])
2385 && FP_REGNO_P (REGNO (operands[3]))"
2386 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2388 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2393 [(set (match_operand:SI 0 "register_operand" "")
2394 (plus:SI (match_operand:SI 1 "register_operand" "")
2395 (match_operand:SI 2 "register_operand" "")))
2396 (set (mem:SI (match_dup 0))
2397 (match_operand:SI 3 "register_operand" ""))]
2399 && !TARGET_DISABLE_INDEXING
2400 && REG_OK_FOR_BASE_P (operands[1])
2401 && (TARGET_NO_SPACE_REGS
2402 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2403 && FP_REGNO_P (REGNO (operands[3]))"
2404 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2406 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2410 [(set (match_operand:SI 0 "register_operand" "")
2411 (plus:SI (match_operand:SI 1 "register_operand" "")
2412 (match_operand:SI 2 "register_operand" "")))
2413 (set (mem:SI (match_dup 0))
2414 (match_operand:SI 3 "register_operand" ""))]
2416 && !TARGET_DISABLE_INDEXING
2417 && REG_OK_FOR_BASE_P (operands[2])
2418 && (TARGET_NO_SPACE_REGS
2419 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2420 && FP_REGNO_P (REGNO (operands[3]))"
2421 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2423 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2427 [(set (match_operand:DI 0 "register_operand" "")
2428 (plus:DI (match_operand:DI 1 "register_operand" "")
2429 (match_operand:DI 2 "register_operand" "")))
2430 (set (mem:SI (match_dup 0))
2431 (match_operand:SI 3 "register_operand" ""))]
2433 && !TARGET_DISABLE_INDEXING
2435 && REG_OK_FOR_BASE_P (operands[1])
2436 && (TARGET_NO_SPACE_REGS
2437 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2438 && FP_REGNO_P (REGNO (operands[3]))"
2439 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2441 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2445 [(set (match_operand:DI 0 "register_operand" "")
2446 (plus:DI (match_operand:DI 1 "register_operand" "")
2447 (match_operand:DI 2 "register_operand" "")))
2448 (set (mem:SI (match_dup 0))
2449 (match_operand:SI 3 "register_operand" ""))]
2451 && !TARGET_DISABLE_INDEXING
2453 && REG_OK_FOR_BASE_P (operands[2])
2454 && (TARGET_NO_SPACE_REGS
2455 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2456 && FP_REGNO_P (REGNO (operands[3]))"
2457 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2459 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2463 [(set (match_operand:SI 0 "move_dest_operand"
2464 "=r,r,r,r,r,r,Q,!*q,!r")
2465 (match_operand:SI 1 "move_src_operand"
2466 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2467 "(register_operand (operands[0], SImode)
2468 || reg_or_0_operand (operands[1], SImode))
2469 && TARGET_SOFT_FLOAT"
2475 {zdepi|depwi,z} %Z1,%0
2479 {mfctl|mfctl,w} %%sar,%0"
2480 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2481 (set_attr "pa_combine_type" "addmove")
2482 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2484 ;; Load or store with base-register modification.
2486 [(set (match_operand:SI 0 "register_operand" "=r")
2487 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2488 (match_operand:DI 2 "int5_operand" "L"))))
2490 (plus:DI (match_dup 1) (match_dup 2)))]
2493 [(set_attr "type" "load")
2494 (set_attr "length" "4")])
2496 ; And a zero extended variant.
2498 [(set (match_operand:DI 0 "register_operand" "=r")
2499 (zero_extend:DI (mem:SI
2501 (match_operand:DI 1 "register_operand" "+r")
2502 (match_operand:DI 2 "int5_operand" "L")))))
2504 (plus:DI (match_dup 1) (match_dup 2)))]
2507 [(set_attr "type" "load")
2508 (set_attr "length" "4")])
2510 (define_expand "pre_load"
2511 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2512 (mem (plus (match_operand 1 "register_operand" "")
2513 (match_operand 2 "pre_cint_operand" ""))))
2515 (plus (match_dup 1) (match_dup 2)))])]
2521 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2524 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2528 (define_insn "pre_ldw"
2529 [(set (match_operand:SI 0 "register_operand" "=r")
2530 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2531 (match_operand:SI 2 "pre_cint_operand" ""))))
2533 (plus:SI (match_dup 1) (match_dup 2)))]
2537 if (INTVAL (operands[2]) < 0)
2538 return \"{ldwm|ldw,mb} %2(%1),%0\";
2539 return \"{ldws|ldw},mb %2(%1),%0\";
2541 [(set_attr "type" "load")
2542 (set_attr "length" "4")])
2544 (define_insn "pre_ldd"
2545 [(set (match_operand:DI 0 "register_operand" "=r")
2546 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2547 (match_operand:DI 2 "pre_cint_operand" ""))))
2549 (plus:DI (match_dup 1) (match_dup 2)))]
2552 [(set_attr "type" "load")
2553 (set_attr "length" "4")])
2556 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2557 (match_operand:SI 1 "pre_cint_operand" "")))
2558 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2560 (plus:SI (match_dup 0) (match_dup 1)))]
2564 if (INTVAL (operands[1]) < 0)
2565 return \"{stwm|stw,mb} %r2,%1(%0)\";
2566 return \"{stws|stw},mb %r2,%1(%0)\";
2568 [(set_attr "type" "store")
2569 (set_attr "length" "4")])
2572 [(set (match_operand:SI 0 "register_operand" "=r")
2573 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2575 (plus:SI (match_dup 1)
2576 (match_operand:SI 2 "post_cint_operand" "")))]
2580 if (INTVAL (operands[2]) > 0)
2581 return \"{ldwm|ldw,ma} %2(%1),%0\";
2582 return \"{ldws|ldw},ma %2(%1),%0\";
2584 [(set_attr "type" "load")
2585 (set_attr "length" "4")])
2587 (define_expand "post_store"
2588 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2589 (match_operand 1 "reg_or_0_operand" ""))
2592 (match_operand 2 "post_cint_operand" "")))])]
2598 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2601 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2605 (define_insn "post_stw"
2606 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2607 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2609 (plus:SI (match_dup 0)
2610 (match_operand:SI 2 "post_cint_operand" "")))]
2614 if (INTVAL (operands[2]) > 0)
2615 return \"{stwm|stw,ma} %r1,%2(%0)\";
2616 return \"{stws|stw},ma %r1,%2(%0)\";
2618 [(set_attr "type" "store")
2619 (set_attr "length" "4")])
2621 (define_insn "post_std"
2622 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2623 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2625 (plus:DI (match_dup 0)
2626 (match_operand:DI 2 "post_cint_operand" "")))]
2629 [(set_attr "type" "store")
2630 (set_attr "length" "4")])
2632 ;; For loading the address of a label while generating PIC code.
2633 ;; Note since this pattern can be created at reload time (via movsi), all
2634 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2636 [(set (match_operand 0 "pmode_register_operand" "=a")
2637 (match_operand 1 "pic_label_operand" ""))]
2643 xoperands[0] = operands[0];
2644 xoperands[1] = operands[1];
2645 xoperands[2] = gen_label_rtx ();
2647 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2648 CODE_LABEL_NUMBER (xoperands[2]));
2649 output_asm_insn (\"mfia %0\", xoperands);
2651 /* If we're trying to load the address of a label that happens to be
2652 close, then we can use a shorter sequence. */
2653 if (GET_CODE (operands[1]) == LABEL_REF
2654 && !LABEL_REF_NONLOCAL_P (operands[1])
2655 && INSN_ADDRESSES_SET_P ()
2656 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2657 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2658 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2661 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2662 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2666 [(set_attr "type" "multi")
2667 (set_attr "length" "12")]) ; 8 or 12
2670 [(set (match_operand 0 "pmode_register_operand" "=a")
2671 (match_operand 1 "pic_label_operand" ""))]
2677 xoperands[0] = operands[0];
2678 xoperands[1] = operands[1];
2679 xoperands[2] = gen_label_rtx ();
2681 output_asm_insn (\"bl .+8,%0\", xoperands);
2682 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2683 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2684 CODE_LABEL_NUMBER (xoperands[2]));
2686 /* If we're trying to load the address of a label that happens to be
2687 close, then we can use a shorter sequence. */
2688 if (GET_CODE (operands[1]) == LABEL_REF
2689 && !LABEL_REF_NONLOCAL_P (operands[1])
2690 && INSN_ADDRESSES_SET_P ()
2691 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2692 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2693 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2696 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2697 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2701 [(set_attr "type" "multi")
2702 (set_attr "length" "16")]) ; 12 or 16
2705 [(set (match_operand:SI 0 "register_operand" "=a")
2706 (plus:SI (match_operand:SI 1 "register_operand" "r")
2707 (high:SI (match_operand 2 "" ""))))]
2708 "symbolic_operand (operands[2], Pmode)
2709 && ! function_label_operand (operands[2], Pmode)
2712 [(set_attr "type" "binary")
2713 (set_attr "length" "4")])
2716 [(set (match_operand:DI 0 "register_operand" "=a")
2717 (plus:DI (match_operand:DI 1 "register_operand" "r")
2718 (high:DI (match_operand 2 "" ""))))]
2719 "symbolic_operand (operands[2], Pmode)
2720 && ! function_label_operand (operands[2], Pmode)
2724 [(set_attr "type" "binary")
2725 (set_attr "length" "4")])
2727 ;; Always use addil rather than ldil;add sequences. This allows the
2728 ;; HP linker to eliminate the dp relocation if the symbolic operand
2729 ;; lives in the TEXT space.
2731 [(set (match_operand:SI 0 "register_operand" "=a")
2732 (high:SI (match_operand 1 "" "")))]
2733 "symbolic_operand (operands[1], Pmode)
2734 && ! function_label_operand (operands[1], Pmode)
2735 && ! read_only_operand (operands[1], Pmode)
2739 if (TARGET_LONG_LOAD_STORE)
2740 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2742 return \"addil LR'%H1,%%r27\";
2744 [(set_attr "type" "binary")
2745 (set (attr "length")
2746 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2751 ;; This is for use in the prologue/epilogue code. We need it
2752 ;; to add large constants to a stack pointer or frame pointer.
2753 ;; Because of the additional %r1 pressure, we probably do not
2754 ;; want to use this in general code, so make it available
2755 ;; only after reload.
2757 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2758 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2759 (high:SI (match_operand 2 "const_int_operand" ""))))]
2763 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2764 [(set_attr "type" "binary,binary")
2765 (set_attr "length" "4,8")])
2768 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2769 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2770 (high:DI (match_operand 2 "const_int_operand" ""))))]
2771 "reload_completed && TARGET_64BIT"
2774 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2775 [(set_attr "type" "binary,binary")
2776 (set_attr "length" "4,8")])
2779 [(set (match_operand:SI 0 "register_operand" "=r")
2780 (high:SI (match_operand 1 "" "")))]
2781 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2782 && !is_function_label_plus_const (operands[1])"
2785 if (symbolic_operand (operands[1], Pmode))
2786 return \"ldil LR'%H1,%0\";
2788 return \"ldil L'%G1,%0\";
2790 [(set_attr "type" "move")
2791 (set_attr "length" "4")])
2794 [(set (match_operand:DI 0 "register_operand" "=r")
2795 (high:DI (match_operand 1 "const_int_operand" "")))]
2798 [(set_attr "type" "move")
2799 (set_attr "length" "4")])
2802 [(set (match_operand:DI 0 "register_operand" "=r")
2803 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2804 (match_operand:DI 2 "const_int_operand" "i")))]
2807 [(set_attr "type" "move")
2808 (set_attr "length" "4")])
2811 [(set (match_operand:SI 0 "register_operand" "=r")
2812 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2813 (match_operand:SI 2 "immediate_operand" "i")))]
2814 "!is_function_label_plus_const (operands[2])"
2817 if (flag_pic && symbolic_operand (operands[2], Pmode))
2819 else if (symbolic_operand (operands[2], Pmode))
2820 return \"ldo RR'%G2(%1),%0\";
2822 return \"ldo R'%G2(%1),%0\";
2824 [(set_attr "type" "move")
2825 (set_attr "length" "4")])
2827 ;; Now that a symbolic_address plus a constant is broken up early
2828 ;; in the compilation phase (for better CSE) we need a special
2829 ;; combiner pattern to load the symbolic address plus the constant
2830 ;; in only 2 instructions. (For cases where the symbolic address
2831 ;; was not a common subexpression.)
2833 [(set (match_operand:SI 0 "register_operand" "")
2834 (match_operand:SI 1 "symbolic_operand" ""))
2835 (clobber (match_operand:SI 2 "register_operand" ""))]
2836 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2837 [(set (match_dup 2) (high:SI (match_dup 1)))
2838 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2841 ;; hppa_legitimize_address goes to a great deal of trouble to
2842 ;; create addresses which use indexing. In some cases, this
2843 ;; is a lose because there isn't any store instructions which
2844 ;; allow indexed addresses (with integer register source).
2846 ;; These define_splits try to turn a 3 insn store into
2847 ;; a 2 insn store with some creative RTL rewriting.
2849 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2850 (match_operand:SI 1 "shadd_operand" ""))
2851 (plus:SI (match_operand:SI 2 "register_operand" "")
2852 (match_operand:SI 3 "const_int_operand" ""))))
2853 (match_operand:SI 4 "register_operand" ""))
2854 (clobber (match_operand:SI 5 "register_operand" ""))]
2856 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2858 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2862 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2863 (match_operand:SI 1 "shadd_operand" ""))
2864 (plus:SI (match_operand:SI 2 "register_operand" "")
2865 (match_operand:SI 3 "const_int_operand" ""))))
2866 (match_operand:HI 4 "register_operand" ""))
2867 (clobber (match_operand:SI 5 "register_operand" ""))]
2869 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2871 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2875 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2876 (match_operand:SI 1 "shadd_operand" ""))
2877 (plus:SI (match_operand:SI 2 "register_operand" "")
2878 (match_operand:SI 3 "const_int_operand" ""))))
2879 (match_operand:QI 4 "register_operand" ""))
2880 (clobber (match_operand:SI 5 "register_operand" ""))]
2882 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2884 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2887 (define_expand "movhi"
2888 [(set (match_operand:HI 0 "general_operand" "")
2889 (match_operand:HI 1 "general_operand" ""))]
2893 if (emit_move_sequence (operands, HImode, 0))
2898 [(set (match_operand:HI 0 "move_dest_operand"
2899 "=r,r,r,r,r,Q,!*q,!r,!*f")
2900 (match_operand:HI 1 "move_src_operand"
2901 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
2902 "register_operand (operands[0], HImode)
2903 || reg_or_0_operand (operands[1], HImode)"
2908 {zdepi|depwi,z} %Z1,%0
2912 {mfctl|mfctl,w} %sar,%0
2914 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
2915 (set_attr "pa_combine_type" "addmove")
2916 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2919 [(set (match_operand:HI 0 "register_operand" "=r")
2920 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2921 (match_operand:SI 2 "int5_operand" "L"))))
2923 (plus:SI (match_dup 1) (match_dup 2)))]
2925 "{ldhs|ldh},mb %2(%1),%0"
2926 [(set_attr "type" "load")
2927 (set_attr "length" "4")])
2930 [(set (match_operand:HI 0 "register_operand" "=r")
2931 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2932 (match_operand:DI 2 "int5_operand" "L"))))
2934 (plus:DI (match_dup 1) (match_dup 2)))]
2937 [(set_attr "type" "load")
2938 (set_attr "length" "4")])
2940 ; And a zero extended variant.
2942 [(set (match_operand:DI 0 "register_operand" "=r")
2943 (zero_extend:DI (mem:HI
2945 (match_operand:DI 1 "register_operand" "+r")
2946 (match_operand:DI 2 "int5_operand" "L")))))
2948 (plus:DI (match_dup 1) (match_dup 2)))]
2951 [(set_attr "type" "load")
2952 (set_attr "length" "4")])
2955 [(set (match_operand:SI 0 "register_operand" "=r")
2956 (zero_extend:SI (mem:HI
2958 (match_operand:SI 1 "register_operand" "+r")
2959 (match_operand:SI 2 "int5_operand" "L")))))
2961 (plus:SI (match_dup 1) (match_dup 2)))]
2963 "{ldhs|ldh},mb %2(%1),%0"
2964 [(set_attr "type" "load")
2965 (set_attr "length" "4")])
2968 [(set (match_operand:SI 0 "register_operand" "=r")
2969 (zero_extend:SI (mem:HI
2971 (match_operand:DI 1 "register_operand" "+r")
2972 (match_operand:DI 2 "int5_operand" "L")))))
2974 (plus:DI (match_dup 1) (match_dup 2)))]
2977 [(set_attr "type" "load")
2978 (set_attr "length" "4")])
2981 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2982 (match_operand:SI 1 "int5_operand" "L")))
2983 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2985 (plus:SI (match_dup 0) (match_dup 1)))]
2987 "{sths|sth},mb %r2,%1(%0)"
2988 [(set_attr "type" "store")
2989 (set_attr "length" "4")])
2992 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2993 (match_operand:DI 1 "int5_operand" "L")))
2994 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2996 (plus:DI (match_dup 0) (match_dup 1)))]
2999 [(set_attr "type" "store")
3000 (set_attr "length" "4")])
3003 [(set (match_operand:HI 0 "register_operand" "=r")
3004 (plus:HI (match_operand:HI 1 "register_operand" "r")
3005 (match_operand 2 "const_int_operand" "J")))]
3008 [(set_attr "type" "binary")
3009 (set_attr "pa_combine_type" "addmove")
3010 (set_attr "length" "4")])
3012 (define_expand "movqi"
3013 [(set (match_operand:QI 0 "general_operand" "")
3014 (match_operand:QI 1 "general_operand" ""))]
3018 if (emit_move_sequence (operands, QImode, 0))
3023 [(set (match_operand:QI 0 "move_dest_operand"
3024 "=r,r,r,r,r,Q,!*q,!r,!*f")
3025 (match_operand:QI 1 "move_src_operand"
3026 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3027 "register_operand (operands[0], QImode)
3028 || reg_or_0_operand (operands[1], QImode)"
3033 {zdepi|depwi,z} %Z1,%0
3037 {mfctl|mfctl,w} %%sar,%0
3039 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
3040 (set_attr "pa_combine_type" "addmove")
3041 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3044 [(set (match_operand:QI 0 "register_operand" "=r")
3045 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3046 (match_operand:SI 2 "int5_operand" "L"))))
3047 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3049 "{ldbs|ldb},mb %2(%1),%0"
3050 [(set_attr "type" "load")
3051 (set_attr "length" "4")])
3054 [(set (match_operand:QI 0 "register_operand" "=r")
3055 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3056 (match_operand:DI 2 "int5_operand" "L"))))
3057 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3060 [(set_attr "type" "load")
3061 (set_attr "length" "4")])
3063 ; Now the same thing with zero extensions.
3065 [(set (match_operand:DI 0 "register_operand" "=r")
3066 (zero_extend:DI (mem:QI (plus:DI
3067 (match_operand:DI 1 "register_operand" "+r")
3068 (match_operand:DI 2 "int5_operand" "L")))))
3069 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3072 [(set_attr "type" "load")
3073 (set_attr "length" "4")])
3076 [(set (match_operand:SI 0 "register_operand" "=r")
3077 (zero_extend:SI (mem:QI (plus:SI
3078 (match_operand:SI 1 "register_operand" "+r")
3079 (match_operand:SI 2 "int5_operand" "L")))))
3080 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3082 "{ldbs|ldb},mb %2(%1),%0"
3083 [(set_attr "type" "load")
3084 (set_attr "length" "4")])
3087 [(set (match_operand:SI 0 "register_operand" "=r")
3088 (zero_extend:SI (mem:QI (plus:DI
3089 (match_operand:DI 1 "register_operand" "+r")
3090 (match_operand:DI 2 "int5_operand" "L")))))
3091 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3094 [(set_attr "type" "load")
3095 (set_attr "length" "4")])
3098 [(set (match_operand:HI 0 "register_operand" "=r")
3099 (zero_extend:HI (mem:QI (plus:SI
3100 (match_operand:SI 1 "register_operand" "+r")
3101 (match_operand:SI 2 "int5_operand" "L")))))
3102 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3104 "{ldbs|ldb},mb %2(%1),%0"
3105 [(set_attr "type" "load")
3106 (set_attr "length" "4")])
3109 [(set (match_operand:HI 0 "register_operand" "=r")
3110 (zero_extend:HI (mem:QI (plus:DI
3111 (match_operand:DI 1 "register_operand" "+r")
3112 (match_operand:DI 2 "int5_operand" "L")))))
3113 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3116 [(set_attr "type" "load")
3117 (set_attr "length" "4")])
3120 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3121 (match_operand:SI 1 "int5_operand" "L")))
3122 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3124 (plus:SI (match_dup 0) (match_dup 1)))]
3126 "{stbs|stb},mb %r2,%1(%0)"
3127 [(set_attr "type" "store")
3128 (set_attr "length" "4")])
3131 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3132 (match_operand:DI 1 "int5_operand" "L")))
3133 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3135 (plus:DI (match_dup 0) (match_dup 1)))]
3138 [(set_attr "type" "store")
3139 (set_attr "length" "4")])
3141 ;; The definition of this insn does not really explain what it does,
3142 ;; but it should suffice that anything generated as this insn will be
3143 ;; recognized as a movmemsi operation, and that it will not successfully
3144 ;; combine with anything.
3145 (define_expand "movmemsi"
3146 [(parallel [(set (match_operand:BLK 0 "" "")
3147 (match_operand:BLK 1 "" ""))
3148 (clobber (match_dup 4))
3149 (clobber (match_dup 5))
3150 (clobber (match_dup 6))
3151 (clobber (match_dup 7))
3152 (clobber (match_dup 8))
3153 (use (match_operand:SI 2 "arith_operand" ""))
3154 (use (match_operand:SI 3 "const_int_operand" ""))])]
3155 "!TARGET_64BIT && optimize > 0"
3160 /* HP provides very fast block move library routine for the PA;
3161 this routine includes:
3163 4x4 byte at a time block moves,
3164 1x4 byte at a time with alignment checked at runtime with
3165 attempts to align the source and destination as needed
3168 With that in mind, here's the heuristics to try and guess when
3169 the inlined block move will be better than the library block
3172 If the size isn't constant, then always use the library routines.
3174 If the size is large in respect to the known alignment, then use
3175 the library routines.
3177 If the size is small in respect to the known alignment, then open
3178 code the copy (since that will lead to better scheduling).
3180 Else use the block move pattern. */
3182 /* Undetermined size, use the library routine. */
3183 if (GET_CODE (operands[2]) != CONST_INT)
3186 size = INTVAL (operands[2]);
3187 align = INTVAL (operands[3]);
3188 align = align > 4 ? 4 : align;
3190 /* If size/alignment is large, then use the library routines. */
3191 if (size / align > 16)
3194 /* This does happen, but not often enough to worry much about. */
3195 if (size / align < MOVE_RATIO)
3198 /* Fall through means we're going to use our block move pattern. */
3200 = replace_equiv_address (operands[0],
3201 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3203 = replace_equiv_address (operands[1],
3204 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3205 operands[4] = gen_reg_rtx (SImode);
3206 operands[5] = gen_reg_rtx (SImode);
3207 operands[6] = gen_reg_rtx (SImode);
3208 operands[7] = gen_reg_rtx (SImode);
3209 operands[8] = gen_reg_rtx (SImode);
3212 ;; The operand constraints are written like this to support both compile-time
3213 ;; and run-time determined byte counts. The expander and output_block_move
3214 ;; only support compile-time determined counts at this time.
3216 ;; If the count is run-time determined, the register with the byte count
3217 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3219 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3220 ;; broke this semantic for pseudo registers. We can't use match_scratch
3221 ;; as this requires two registers in the class R1_REGS when the MEMs for
3222 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3223 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3224 ;; respectively. We then split or peephole optimize after reload.
3225 (define_insn "movmemsi_prereload"
3226 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3227 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3228 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3229 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3230 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3231 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3232 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3233 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3234 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3237 [(set_attr "type" "multi,multi")])
3240 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3241 (match_operand:BLK 1 "memory_operand" ""))
3242 (clobber (match_operand:SI 2 "register_operand" ""))
3243 (clobber (match_operand:SI 3 "register_operand" ""))
3244 (clobber (match_operand:SI 6 "register_operand" ""))
3245 (clobber (match_operand:SI 7 "register_operand" ""))
3246 (clobber (match_operand:SI 8 "register_operand" ""))
3247 (use (match_operand:SI 4 "arith_operand" ""))
3248 (use (match_operand:SI 5 "const_int_operand" ""))])]
3249 "!TARGET_64BIT && reload_completed && !flag_peephole2
3250 && GET_CODE (operands[0]) == MEM
3251 && register_operand (XEXP (operands[0], 0), SImode)
3252 && GET_CODE (operands[1]) == MEM
3253 && register_operand (XEXP (operands[1], 0), SImode)"
3254 [(set (match_dup 7) (match_dup 9))
3255 (set (match_dup 8) (match_dup 10))
3256 (parallel [(set (match_dup 0) (match_dup 1))
3257 (clobber (match_dup 2))
3258 (clobber (match_dup 3))
3259 (clobber (match_dup 6))
3260 (clobber (match_dup 7))
3261 (clobber (match_dup 8))
3267 operands[9] = XEXP (operands[0], 0);
3268 operands[10] = XEXP (operands[1], 0);
3269 operands[0] = replace_equiv_address (operands[0], operands[7]);
3270 operands[1] = replace_equiv_address (operands[1], operands[8]);
3274 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3275 (match_operand:BLK 1 "memory_operand" ""))
3276 (clobber (match_operand:SI 2 "register_operand" ""))
3277 (clobber (match_operand:SI 3 "register_operand" ""))
3278 (clobber (match_operand:SI 6 "register_operand" ""))
3279 (clobber (match_operand:SI 7 "register_operand" ""))
3280 (clobber (match_operand:SI 8 "register_operand" ""))
3281 (use (match_operand:SI 4 "arith_operand" ""))
3282 (use (match_operand:SI 5 "const_int_operand" ""))])]
3284 && GET_CODE (operands[0]) == MEM
3285 && register_operand (XEXP (operands[0], 0), SImode)
3286 && GET_CODE (operands[1]) == MEM
3287 && register_operand (XEXP (operands[1], 0), SImode)"
3288 [(parallel [(set (match_dup 0) (match_dup 1))
3289 (clobber (match_dup 2))
3290 (clobber (match_dup 3))
3291 (clobber (match_dup 6))
3292 (clobber (match_dup 7))
3293 (clobber (match_dup 8))
3299 rtx addr = XEXP (operands[0], 0);
3300 if (dead_or_set_p (curr_insn, addr))
3304 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3305 operands[0] = replace_equiv_address (operands[0], operands[7]);
3308 addr = XEXP (operands[1], 0);
3309 if (dead_or_set_p (curr_insn, addr))
3313 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3314 operands[1] = replace_equiv_address (operands[1], operands[8]);
3318 (define_insn "movmemsi_postreload"
3319 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3320 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3321 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3322 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3323 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3324 (clobber (match_dup 0))
3325 (clobber (match_dup 1))
3326 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3327 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3329 "!TARGET_64BIT && reload_completed"
3330 "* return output_block_move (operands, !which_alternative);"
3331 [(set_attr "type" "multi,multi")])
3333 (define_expand "movmemdi"
3334 [(parallel [(set (match_operand:BLK 0 "" "")
3335 (match_operand:BLK 1 "" ""))
3336 (clobber (match_dup 4))
3337 (clobber (match_dup 5))
3338 (clobber (match_dup 6))
3339 (clobber (match_dup 7))
3340 (clobber (match_dup 8))
3341 (use (match_operand:DI 2 "arith_operand" ""))
3342 (use (match_operand:DI 3 "const_int_operand" ""))])]
3343 "TARGET_64BIT && optimize > 0"
3348 /* HP provides very fast block move library routine for the PA;
3349 this routine includes:
3351 4x4 byte at a time block moves,
3352 1x4 byte at a time with alignment checked at runtime with
3353 attempts to align the source and destination as needed
3356 With that in mind, here's the heuristics to try and guess when
3357 the inlined block move will be better than the library block
3360 If the size isn't constant, then always use the library routines.
3362 If the size is large in respect to the known alignment, then use
3363 the library routines.
3365 If the size is small in respect to the known alignment, then open
3366 code the copy (since that will lead to better scheduling).
3368 Else use the block move pattern. */
3370 /* Undetermined size, use the library routine. */
3371 if (GET_CODE (operands[2]) != CONST_INT)
3374 size = INTVAL (operands[2]);
3375 align = INTVAL (operands[3]);
3376 align = align > 8 ? 8 : align;
3378 /* If size/alignment is large, then use the library routines. */
3379 if (size / align > 16)
3382 /* This does happen, but not often enough to worry much about. */
3383 if (size / align < MOVE_RATIO)
3386 /* Fall through means we're going to use our block move pattern. */
3388 = replace_equiv_address (operands[0],
3389 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3391 = replace_equiv_address (operands[1],
3392 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3393 operands[4] = gen_reg_rtx (DImode);
3394 operands[5] = gen_reg_rtx (DImode);
3395 operands[6] = gen_reg_rtx (DImode);
3396 operands[7] = gen_reg_rtx (DImode);
3397 operands[8] = gen_reg_rtx (DImode);
3400 ;; The operand constraints are written like this to support both compile-time
3401 ;; and run-time determined byte counts. The expander and output_block_move
3402 ;; only support compile-time determined counts at this time.
3404 ;; If the count is run-time determined, the register with the byte count
3405 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3407 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3408 ;; broke this semantic for pseudo registers. We can't use match_scratch
3409 ;; as this requires two registers in the class R1_REGS when the MEMs for
3410 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3411 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3412 ;; respectively. We then split or peephole optimize after reload.
3413 (define_insn "movmemdi_prereload"
3414 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3415 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3416 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3417 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3418 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3419 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3420 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3421 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3422 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3425 [(set_attr "type" "multi,multi")])
3428 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3429 (match_operand:BLK 1 "memory_operand" ""))
3430 (clobber (match_operand:DI 2 "register_operand" ""))
3431 (clobber (match_operand:DI 3 "register_operand" ""))
3432 (clobber (match_operand:DI 6 "register_operand" ""))
3433 (clobber (match_operand:DI 7 "register_operand" ""))
3434 (clobber (match_operand:DI 8 "register_operand" ""))
3435 (use (match_operand:DI 4 "arith_operand" ""))
3436 (use (match_operand:DI 5 "const_int_operand" ""))])]
3437 "TARGET_64BIT && reload_completed && !flag_peephole2
3438 && GET_CODE (operands[0]) == MEM
3439 && register_operand (XEXP (operands[0], 0), DImode)
3440 && GET_CODE (operands[1]) == MEM
3441 && register_operand (XEXP (operands[1], 0), DImode)"
3442 [(set (match_dup 7) (match_dup 9))
3443 (set (match_dup 8) (match_dup 10))
3444 (parallel [(set (match_dup 0) (match_dup 1))
3445 (clobber (match_dup 2))
3446 (clobber (match_dup 3))
3447 (clobber (match_dup 6))
3448 (clobber (match_dup 7))
3449 (clobber (match_dup 8))
3455 operands[9] = XEXP (operands[0], 0);
3456 operands[10] = XEXP (operands[1], 0);
3457 operands[0] = replace_equiv_address (operands[0], operands[7]);
3458 operands[1] = replace_equiv_address (operands[1], operands[8]);
3462 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3463 (match_operand:BLK 1 "memory_operand" ""))
3464 (clobber (match_operand:DI 2 "register_operand" ""))
3465 (clobber (match_operand:DI 3 "register_operand" ""))
3466 (clobber (match_operand:DI 6 "register_operand" ""))
3467 (clobber (match_operand:DI 7 "register_operand" ""))
3468 (clobber (match_operand:DI 8 "register_operand" ""))
3469 (use (match_operand:DI 4 "arith_operand" ""))
3470 (use (match_operand:DI 5 "const_int_operand" ""))])]
3472 && GET_CODE (operands[0]) == MEM
3473 && register_operand (XEXP (operands[0], 0), DImode)
3474 && GET_CODE (operands[1]) == MEM
3475 && register_operand (XEXP (operands[1], 0), DImode)"
3476 [(parallel [(set (match_dup 0) (match_dup 1))
3477 (clobber (match_dup 2))
3478 (clobber (match_dup 3))
3479 (clobber (match_dup 6))
3480 (clobber (match_dup 7))
3481 (clobber (match_dup 8))
3487 rtx addr = XEXP (operands[0], 0);
3488 if (dead_or_set_p (curr_insn, addr))
3492 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3493 operands[0] = replace_equiv_address (operands[0], operands[7]);
3496 addr = XEXP (operands[1], 0);
3497 if (dead_or_set_p (curr_insn, addr))
3501 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3502 operands[1] = replace_equiv_address (operands[1], operands[8]);
3506 (define_insn "movmemdi_postreload"
3507 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3508 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3509 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3510 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3511 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3512 (clobber (match_dup 0))
3513 (clobber (match_dup 1))
3514 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3515 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3517 "TARGET_64BIT && reload_completed"
3518 "* return output_block_move (operands, !which_alternative);"
3519 [(set_attr "type" "multi,multi")])
3521 (define_expand "clrmemsi"
3522 [(parallel [(set (match_operand:BLK 0 "" "")
3524 (clobber (match_dup 3))
3525 (clobber (match_dup 4))
3526 (use (match_operand:SI 1 "arith_operand" ""))
3527 (use (match_operand:SI 2 "const_int_operand" ""))])]
3528 "!TARGET_64BIT && optimize > 0"
3533 /* Undetermined size, use the library routine. */
3534 if (GET_CODE (operands[1]) != CONST_INT)
3537 size = INTVAL (operands[1]);
3538 align = INTVAL (operands[2]);
3539 align = align > 4 ? 4 : align;
3541 /* If size/alignment is large, then use the library routines. */
3542 if (size / align > 16)
3545 /* This does happen, but not often enough to worry much about. */
3546 if (size / align < MOVE_RATIO)
3549 /* Fall through means we're going to use our block clear pattern. */
3551 = replace_equiv_address (operands[0],
3552 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3553 operands[3] = gen_reg_rtx (SImode);
3554 operands[4] = gen_reg_rtx (SImode);
3557 (define_insn "clrmemsi_prereload"
3558 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3560 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3561 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3562 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3563 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3566 [(set_attr "type" "multi,multi")])
3569 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3571 (clobber (match_operand:SI 1 "register_operand" ""))
3572 (clobber (match_operand:SI 4 "register_operand" ""))
3573 (use (match_operand:SI 2 "arith_operand" ""))
3574 (use (match_operand:SI 3 "const_int_operand" ""))])]
3575 "!TARGET_64BIT && reload_completed && !flag_peephole2
3576 && GET_CODE (operands[0]) == MEM
3577 && register_operand (XEXP (operands[0], 0), SImode)"
3578 [(set (match_dup 4) (match_dup 5))
3579 (parallel [(set (match_dup 0) (const_int 0))
3580 (clobber (match_dup 1))
3581 (clobber (match_dup 4))
3587 operands[5] = XEXP (operands[0], 0);
3588 operands[0] = replace_equiv_address (operands[0], operands[4]);
3592 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3594 (clobber (match_operand:SI 1 "register_operand" ""))
3595 (clobber (match_operand:SI 4 "register_operand" ""))
3596 (use (match_operand:SI 2 "arith_operand" ""))
3597 (use (match_operand:SI 3 "const_int_operand" ""))])]
3599 && GET_CODE (operands[0]) == MEM
3600 && register_operand (XEXP (operands[0], 0), SImode)"
3601 [(parallel [(set (match_dup 0) (const_int 0))
3602 (clobber (match_dup 1))
3603 (clobber (match_dup 4))
3609 rtx addr = XEXP (operands[0], 0);
3610 if (dead_or_set_p (curr_insn, addr))
3614 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3615 operands[0] = replace_equiv_address (operands[0], operands[4]);
3619 (define_insn "clrmemsi_postreload"
3620 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3622 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3623 (clobber (match_dup 0))
3624 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3625 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3627 "!TARGET_64BIT && reload_completed"
3628 "* return output_block_clear (operands, !which_alternative);"
3629 [(set_attr "type" "multi,multi")])
3631 (define_expand "clrmemdi"
3632 [(parallel [(set (match_operand:BLK 0 "" "")
3634 (clobber (match_dup 3))
3635 (clobber (match_dup 4))
3636 (use (match_operand:DI 1 "arith_operand" ""))
3637 (use (match_operand:DI 2 "const_int_operand" ""))])]
3638 "TARGET_64BIT && optimize > 0"
3643 /* Undetermined size, use the library routine. */
3644 if (GET_CODE (operands[1]) != CONST_INT)
3647 size = INTVAL (operands[1]);
3648 align = INTVAL (operands[2]);
3649 align = align > 8 ? 8 : align;
3651 /* If size/alignment is large, then use the library routines. */
3652 if (size / align > 16)
3655 /* This does happen, but not often enough to worry much about. */
3656 if (size / align < MOVE_RATIO)
3659 /* Fall through means we're going to use our block clear pattern. */
3661 = replace_equiv_address (operands[0],
3662 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3663 operands[3] = gen_reg_rtx (DImode);
3664 operands[4] = gen_reg_rtx (DImode);
3667 (define_insn "clrmemdi_prereload"
3668 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3670 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3671 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3672 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3673 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3676 [(set_attr "type" "multi,multi")])
3679 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3681 (clobber (match_operand:DI 1 "register_operand" ""))
3682 (clobber (match_operand:DI 4 "register_operand" ""))
3683 (use (match_operand:DI 2 "arith_operand" ""))
3684 (use (match_operand:DI 3 "const_int_operand" ""))])]
3685 "TARGET_64BIT && reload_completed && !flag_peephole2
3686 && GET_CODE (operands[0]) == MEM
3687 && register_operand (XEXP (operands[0], 0), DImode)"
3688 [(set (match_dup 4) (match_dup 5))
3689 (parallel [(set (match_dup 0) (const_int 0))
3690 (clobber (match_dup 1))
3691 (clobber (match_dup 4))
3697 operands[5] = XEXP (operands[0], 0);
3698 operands[0] = replace_equiv_address (operands[0], operands[4]);
3702 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3704 (clobber (match_operand:DI 1 "register_operand" ""))
3705 (clobber (match_operand:DI 4 "register_operand" ""))
3706 (use (match_operand:DI 2 "arith_operand" ""))
3707 (use (match_operand:DI 3 "const_int_operand" ""))])]
3709 && GET_CODE (operands[0]) == MEM
3710 && register_operand (XEXP (operands[0], 0), DImode)"
3711 [(parallel [(set (match_dup 0) (const_int 0))
3712 (clobber (match_dup 1))
3713 (clobber (match_dup 4))
3719 rtx addr = XEXP (operands[0], 0);
3720 if (dead_or_set_p (curr_insn, addr))
3724 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3725 operands[0] = replace_equiv_address (operands[0], operands[4]);
3729 (define_insn "clrmemdi_postreload"
3730 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3732 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3733 (clobber (match_dup 0))
3734 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3735 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3737 "TARGET_64BIT && reload_completed"
3738 "* return output_block_clear (operands, !which_alternative);"
3739 [(set_attr "type" "multi,multi")])
3741 ;; Floating point move insns
3743 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3744 ;; to be reloaded by putting the constant into memory when
3745 ;; reg is a floating point register.
3747 ;; For integer registers we use ldil;ldo to set the appropriate
3750 ;; This must come before the movdf pattern, and it must be present
3751 ;; to handle obscure reloading cases.
3753 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3754 (match_operand:DF 1 "" "?F,m"))]
3755 "GET_CODE (operands[1]) == CONST_DOUBLE
3756 && operands[1] != CONST0_RTX (DFmode)
3758 && !TARGET_SOFT_FLOAT"
3759 "* return (which_alternative == 0 ? output_move_double (operands)
3760 : \"fldd%F1 %1,%0\");"
3761 [(set_attr "type" "move,fpload")
3762 (set_attr "length" "16,4")])
3764 (define_expand "movdf"
3765 [(set (match_operand:DF 0 "general_operand" "")
3766 (match_operand:DF 1 "general_operand" ""))]
3770 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3771 operands[1] = force_const_mem (DFmode, operands[1]);
3773 if (emit_move_sequence (operands, DFmode, 0))
3777 ;; Reloading an SImode or DImode value requires a scratch register if
3778 ;; going in to or out of float point registers.
3780 (define_expand "reload_indf"
3781 [(set (match_operand:DF 0 "register_operand" "=Z")
3782 (match_operand:DF 1 "non_hard_reg_operand" ""))
3783 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3787 if (emit_move_sequence (operands, DFmode, operands[2]))
3790 /* We don't want the clobber emitted, so handle this ourselves. */
3791 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3795 (define_expand "reload_outdf"
3796 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3797 (match_operand:DF 1 "register_operand" "Z"))
3798 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3802 if (emit_move_sequence (operands, DFmode, operands[2]))
3805 /* We don't want the clobber emitted, so handle this ourselves. */
3806 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3811 [(set (match_operand:DF 0 "move_dest_operand"
3812 "=f,*r,Q,?o,?Q,f,*r,*r")
3813 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3814 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3815 "(register_operand (operands[0], DFmode)
3816 || reg_or_0_operand (operands[1], DFmode))
3817 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3818 && GET_CODE (operands[0]) == MEM)
3820 && !TARGET_SOFT_FLOAT"
3823 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3824 || operands[1] == CONST0_RTX (DFmode))
3825 return output_fp_move_double (operands);
3826 return output_move_double (operands);
3828 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3829 (set_attr "length" "4,8,4,8,16,4,8,16")])
3832 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3833 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3835 && !TARGET_DISABLE_INDEXING
3836 && reload_completed"
3838 [(set_attr "type" "fpstore")
3839 (set_attr "pa_combine_type" "addmove")
3840 (set_attr "length" "4")])
3843 [(set (match_operand:SI 0 "register_operand" "")
3844 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3846 (match_operand:SI 2 "register_operand" "")))
3847 (set (mem:DF (match_dup 0))
3848 (match_operand:DF 3 "register_operand" ""))]
3850 && !TARGET_DISABLE_INDEXING
3851 && REG_OK_FOR_BASE_P (operands[2])
3852 && FP_REGNO_P (REGNO (operands[3]))"
3853 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3855 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3860 [(set (match_operand:SI 0 "register_operand" "")
3861 (plus:SI (match_operand:SI 2 "register_operand" "")
3862 (mult:SI (match_operand:SI 1 "register_operand" "")
3864 (set (mem:DF (match_dup 0))
3865 (match_operand:DF 3 "register_operand" ""))]
3867 && !TARGET_DISABLE_INDEXING
3868 && REG_OK_FOR_BASE_P (operands[2])
3869 && FP_REGNO_P (REGNO (operands[3]))"
3870 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3872 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3877 [(set (match_operand:DI 0 "register_operand" "")
3878 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3880 (match_operand:DI 2 "register_operand" "")))
3881 (set (mem:DF (match_dup 0))
3882 (match_operand:DF 3 "register_operand" ""))]
3884 && !TARGET_DISABLE_INDEXING
3886 && REG_OK_FOR_BASE_P (operands[2])
3887 && FP_REGNO_P (REGNO (operands[3]))"
3888 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3890 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3895 [(set (match_operand:DI 0 "register_operand" "")
3896 (plus:DI (match_operand:DI 2 "register_operand" "")
3897 (mult:DI (match_operand:DI 1 "register_operand" "")
3899 (set (mem:DF (match_dup 0))
3900 (match_operand:DF 3 "register_operand" ""))]
3902 && !TARGET_DISABLE_INDEXING
3904 && REG_OK_FOR_BASE_P (operands[2])
3905 && FP_REGNO_P (REGNO (operands[3]))"
3906 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3908 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3913 [(set (match_operand:SI 0 "register_operand" "")
3914 (plus:SI (match_operand:SI 1 "register_operand" "")
3915 (match_operand:SI 2 "register_operand" "")))
3916 (set (mem:DF (match_dup 0))
3917 (match_operand:DF 3 "register_operand" ""))]
3919 && !TARGET_DISABLE_INDEXING
3920 && REG_OK_FOR_BASE_P (operands[1])
3921 && (TARGET_NO_SPACE_REGS
3922 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3923 && FP_REGNO_P (REGNO (operands[3]))"
3924 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3926 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3930 [(set (match_operand:SI 0 "register_operand" "")
3931 (plus:SI (match_operand:SI 1 "register_operand" "")
3932 (match_operand:SI 2 "register_operand" "")))
3933 (set (mem:DF (match_dup 0))
3934 (match_operand:DF 3 "register_operand" ""))]
3936 && !TARGET_DISABLE_INDEXING
3937 && REG_OK_FOR_BASE_P (operands[2])
3938 && (TARGET_NO_SPACE_REGS
3939 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3940 && FP_REGNO_P (REGNO (operands[3]))"
3941 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3943 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3947 [(set (match_operand:DI 0 "register_operand" "")
3948 (plus:DI (match_operand:DI 1 "register_operand" "")
3949 (match_operand:DI 2 "register_operand" "")))
3950 (set (mem:DF (match_dup 0))
3951 (match_operand:DF 3 "register_operand" ""))]
3953 && !TARGET_DISABLE_INDEXING
3955 && REG_OK_FOR_BASE_P (operands[1])
3956 && (TARGET_NO_SPACE_REGS
3957 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3958 && FP_REGNO_P (REGNO (operands[3]))"
3959 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3961 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3965 [(set (match_operand:DI 0 "register_operand" "")
3966 (plus:DI (match_operand:DI 1 "register_operand" "")
3967 (match_operand:DI 2 "register_operand" "")))
3968 (set (mem:DF (match_dup 0))
3969 (match_operand:DF 3 "register_operand" ""))]
3971 && !TARGET_DISABLE_INDEXING
3973 && REG_OK_FOR_BASE_P (operands[2])
3974 && (TARGET_NO_SPACE_REGS
3975 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3976 && FP_REGNO_P (REGNO (operands[3]))"
3977 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3979 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3983 [(set (match_operand:DF 0 "move_dest_operand"
3985 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3987 "(register_operand (operands[0], DFmode)
3988 || reg_or_0_operand (operands[1], DFmode))
3990 && TARGET_SOFT_FLOAT"
3993 return output_move_double (operands);
3995 [(set_attr "type" "move,store,store,load,load")
3996 (set_attr "length" "8,8,16,8,16")])
3999 [(set (match_operand:DF 0 "move_dest_operand"
4000 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4001 (match_operand:DF 1 "move_src_operand"
4002 "!*r,J,N,K,RQ,*rM,fM,RT,f"))]
4003 "(register_operand (operands[0], DFmode)
4004 || reg_or_0_operand (operands[1], DFmode))
4005 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4016 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4017 (set_attr "pa_combine_type" "addmove")
4018 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4021 (define_expand "movdi"
4022 [(set (match_operand:DI 0 "general_operand" "")
4023 (match_operand:DI 1 "general_operand" ""))]
4027 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
4028 operands[1] = force_const_mem (DImode, operands[1]);
4030 if (emit_move_sequence (operands, DImode, 0))
4034 (define_expand "reload_indi"
4035 [(set (match_operand:DI 0 "register_operand" "=Z")
4036 (match_operand:DI 1 "non_hard_reg_operand" ""))
4037 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4041 if (emit_move_sequence (operands, DImode, operands[2]))
4044 /* We don't want the clobber emitted, so handle this ourselves. */
4045 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4049 (define_expand "reload_outdi"
4050 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4051 (match_operand:DI 1 "register_operand" "Z"))
4052 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4056 if (emit_move_sequence (operands, DImode, operands[2]))
4059 /* We don't want the clobber emitted, so handle this ourselves. */
4060 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4065 [(set (match_operand:DI 0 "register_operand" "=r")
4066 (high:DI (match_operand 1 "" "")))]
4070 rtx op0 = operands[0];
4071 rtx op1 = operands[1];
4073 if (GET_CODE (op1) == CONST_INT)
4075 operands[0] = operand_subword (op0, 1, 0, DImode);
4076 output_asm_insn (\"ldil L'%1,%0\", operands);
4078 operands[0] = operand_subword (op0, 0, 0, DImode);
4079 if (INTVAL (op1) < 0)
4080 output_asm_insn (\"ldi -1,%0\", operands);
4082 output_asm_insn (\"ldi 0,%0\", operands);
4085 else if (GET_CODE (op1) == CONST_DOUBLE)
4087 operands[0] = operand_subword (op0, 1, 0, DImode);
4088 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4089 output_asm_insn (\"ldil L'%1,%0\", operands);
4091 operands[0] = operand_subword (op0, 0, 0, DImode);
4092 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4093 output_asm_insn (singlemove_string (operands), operands);
4099 [(set_attr "type" "move")
4100 (set_attr "length" "8")])
4103 [(set (match_operand:DI 0 "move_dest_operand"
4104 "=r,o,Q,r,r,r,*f,*f,T")
4105 (match_operand:DI 1 "general_operand"
4106 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4107 "(register_operand (operands[0], DImode)
4108 || reg_or_0_operand (operands[1], DImode))
4110 && !TARGET_SOFT_FLOAT"
4113 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4114 || (operands[1] == CONST0_RTX (DImode)))
4115 return output_fp_move_double (operands);
4116 return output_move_double (operands);
4118 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4119 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4122 [(set (match_operand:DI 0 "move_dest_operand"
4123 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4124 (match_operand:DI 1 "move_src_operand"
4125 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4126 "(register_operand (operands[0], DImode)
4127 || reg_or_0_operand (operands[1], DImode))
4128 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4138 {mfctl|mfctl,w} %%sar,%0
4142 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4143 (set_attr "pa_combine_type" "addmove")
4144 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4147 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4148 (match_operand:DI 1 "register_operand" "f"))]
4151 && !TARGET_DISABLE_INDEXING
4152 && reload_completed"
4154 [(set_attr "type" "fpstore")
4155 (set_attr "pa_combine_type" "addmove")
4156 (set_attr "length" "4")])
4159 [(set (match_operand:DI 0 "register_operand" "")
4160 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4162 (match_operand:DI 2 "register_operand" "")))
4163 (set (mem:DI (match_dup 0))
4164 (match_operand:DI 3 "register_operand" ""))]
4166 && !TARGET_DISABLE_INDEXING
4168 && REG_OK_FOR_BASE_P (operands[2])
4169 && FP_REGNO_P (REGNO (operands[3]))"
4170 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4172 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4177 [(set (match_operand:DI 0 "register_operand" "")
4178 (plus:DI (match_operand:DI 2 "register_operand" "")
4179 (mult:DI (match_operand:DI 1 "register_operand" "")
4181 (set (mem:DI (match_dup 0))
4182 (match_operand:DI 3 "register_operand" ""))]
4184 && !TARGET_DISABLE_INDEXING
4186 && REG_OK_FOR_BASE_P (operands[2])
4187 && FP_REGNO_P (REGNO (operands[3]))"
4188 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4190 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4195 [(set (match_operand:DI 0 "register_operand" "")
4196 (plus:DI (match_operand:DI 1 "register_operand" "")
4197 (match_operand:DI 2 "register_operand" "")))
4198 (set (mem:DI (match_dup 0))
4199 (match_operand:DI 3 "register_operand" ""))]
4201 && !TARGET_DISABLE_INDEXING
4203 && REG_OK_FOR_BASE_P (operands[1])
4204 && (TARGET_NO_SPACE_REGS
4205 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4206 && FP_REGNO_P (REGNO (operands[3]))"
4207 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4209 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4213 [(set (match_operand:DI 0 "register_operand" "")
4214 (plus:DI (match_operand:DI 1 "register_operand" "")
4215 (match_operand:DI 2 "register_operand" "")))
4216 (set (mem:DI (match_dup 0))
4217 (match_operand:DI 3 "register_operand" ""))]
4219 && !TARGET_DISABLE_INDEXING
4221 && REG_OK_FOR_BASE_P (operands[2])
4222 && (TARGET_NO_SPACE_REGS
4223 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4224 && FP_REGNO_P (REGNO (operands[3]))"
4225 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4227 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4231 [(set (match_operand:DI 0 "move_dest_operand"
4233 (match_operand:DI 1 "general_operand"
4235 "(register_operand (operands[0], DImode)
4236 || reg_or_0_operand (operands[1], DImode))
4238 && TARGET_SOFT_FLOAT"
4241 return output_move_double (operands);
4243 [(set_attr "type" "move,store,store,load,load,multi")
4244 (set_attr "length" "8,8,16,8,16,16")])
4247 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4248 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4249 (match_operand:DI 2 "immediate_operand" "i,i")))]
4253 /* Don't output a 64 bit constant, since we can't trust the assembler to
4254 handle it correctly. */
4255 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4256 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4257 if (which_alternative == 1)
4258 output_asm_insn (\"copy %1,%0\", operands);
4259 return \"ldo R'%G2(%R1),%R0\";
4261 [(set_attr "type" "move,move")
4262 (set_attr "length" "4,8")])
4264 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4265 ;; to be reloaded by putting the constant into memory when
4266 ;; reg is a floating point register.
4268 ;; For integer registers we use ldil;ldo to set the appropriate
4271 ;; This must come before the movsf pattern, and it must be present
4272 ;; to handle obscure reloading cases.
4274 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4275 (match_operand:SF 1 "" "?F,m"))]
4276 "GET_CODE (operands[1]) == CONST_DOUBLE
4277 && operands[1] != CONST0_RTX (SFmode)
4278 && ! TARGET_SOFT_FLOAT"
4279 "* return (which_alternative == 0 ? singlemove_string (operands)
4280 : \" fldw%F1 %1,%0\");"
4281 [(set_attr "type" "move,fpload")
4282 (set_attr "length" "8,4")])
4284 (define_expand "movsf"
4285 [(set (match_operand:SF 0 "general_operand" "")
4286 (match_operand:SF 1 "general_operand" ""))]
4290 if (emit_move_sequence (operands, SFmode, 0))
4294 ;; Reloading an SImode or DImode value requires a scratch register if
4295 ;; going in to or out of float point registers.
4297 (define_expand "reload_insf"
4298 [(set (match_operand:SF 0 "register_operand" "=Z")
4299 (match_operand:SF 1 "non_hard_reg_operand" ""))
4300 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4304 if (emit_move_sequence (operands, SFmode, operands[2]))
4307 /* We don't want the clobber emitted, so handle this ourselves. */
4308 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4312 (define_expand "reload_outsf"
4313 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4314 (match_operand:SF 1 "register_operand" "Z"))
4315 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4319 if (emit_move_sequence (operands, SFmode, operands[2]))
4322 /* We don't want the clobber emitted, so handle this ourselves. */
4323 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4328 [(set (match_operand:SF 0 "move_dest_operand"
4330 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4331 "fG,!*rG,RQ,RQ,f,*rG"))]
4332 "(register_operand (operands[0], SFmode)
4333 || reg_or_0_operand (operands[1], SFmode))
4334 && !TARGET_SOFT_FLOAT"
4342 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4343 (set_attr "pa_combine_type" "addmove")
4344 (set_attr "length" "4,4,4,4,4,4")])
4347 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4348 (match_operand:SF 1 "register_operand" "f"))]
4350 && !TARGET_DISABLE_INDEXING
4351 && reload_completed"
4353 [(set_attr "type" "fpstore")
4354 (set_attr "pa_combine_type" "addmove")
4355 (set_attr "length" "4")])
4358 [(set (match_operand:SI 0 "register_operand" "")
4359 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4361 (match_operand:SI 2 "register_operand" "")))
4362 (set (mem:SF (match_dup 0))
4363 (match_operand:SF 3 "register_operand" ""))]
4365 && !TARGET_DISABLE_INDEXING
4366 && REG_OK_FOR_BASE_P (operands[2])
4367 && FP_REGNO_P (REGNO (operands[3]))"
4368 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4370 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4375 [(set (match_operand:SI 0 "register_operand" "")
4376 (plus:SI (match_operand:SI 2 "register_operand" "")
4377 (mult:SI (match_operand:SI 1 "register_operand" "")
4379 (set (mem:SF (match_dup 0))
4380 (match_operand:SF 3 "register_operand" ""))]
4382 && !TARGET_DISABLE_INDEXING
4383 && REG_OK_FOR_BASE_P (operands[2])
4384 && FP_REGNO_P (REGNO (operands[3]))"
4385 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4387 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4392 [(set (match_operand:DI 0 "register_operand" "")
4393 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4395 (match_operand:DI 2 "register_operand" "")))
4396 (set (mem:SF (match_dup 0))
4397 (match_operand:SF 3 "register_operand" ""))]
4399 && !TARGET_DISABLE_INDEXING
4401 && REG_OK_FOR_BASE_P (operands[2])
4402 && FP_REGNO_P (REGNO (operands[3]))"
4403 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4405 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4410 [(set (match_operand:DI 0 "register_operand" "")
4411 (plus:DI (match_operand:DI 2 "register_operand" "")
4412 (mult:DI (match_operand:DI 1 "register_operand" "")
4414 (set (mem:SF (match_dup 0))
4415 (match_operand:SF 3 "register_operand" ""))]
4417 && !TARGET_DISABLE_INDEXING
4419 && REG_OK_FOR_BASE_P (operands[2])
4420 && FP_REGNO_P (REGNO (operands[3]))"
4421 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4423 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4428 [(set (match_operand:SI 0 "register_operand" "")
4429 (plus:SI (match_operand:SI 1 "register_operand" "")
4430 (match_operand:SI 2 "register_operand" "")))
4431 (set (mem:SF (match_dup 0))
4432 (match_operand:SF 3 "register_operand" ""))]
4434 && !TARGET_DISABLE_INDEXING
4435 && REG_OK_FOR_BASE_P (operands[1])
4436 && (TARGET_NO_SPACE_REGS
4437 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4438 && FP_REGNO_P (REGNO (operands[3]))"
4439 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4441 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4445 [(set (match_operand:SI 0 "register_operand" "")
4446 (plus:SI (match_operand:SI 1 "register_operand" "")
4447 (match_operand:SI 2 "register_operand" "")))
4448 (set (mem:SF (match_dup 0))
4449 (match_operand:SF 3 "register_operand" ""))]
4451 && !TARGET_DISABLE_INDEXING
4452 && REG_OK_FOR_BASE_P (operands[2])
4453 && (TARGET_NO_SPACE_REGS
4454 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4455 && FP_REGNO_P (REGNO (operands[3]))"
4456 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4458 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4462 [(set (match_operand:DI 0 "register_operand" "")
4463 (plus:DI (match_operand:DI 1 "register_operand" "")
4464 (match_operand:DI 2 "register_operand" "")))
4465 (set (mem:SF (match_dup 0))
4466 (match_operand:SF 3 "register_operand" ""))]
4468 && !TARGET_DISABLE_INDEXING
4470 && REG_OK_FOR_BASE_P (operands[1])
4471 && (TARGET_NO_SPACE_REGS
4472 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4473 && FP_REGNO_P (REGNO (operands[3]))"
4474 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4476 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4480 [(set (match_operand:DI 0 "register_operand" "")
4481 (plus:DI (match_operand:DI 1 "register_operand" "")
4482 (match_operand:DI 2 "register_operand" "")))
4483 (set (mem:SF (match_dup 0))
4484 (match_operand:SF 3 "register_operand" ""))]
4486 && !TARGET_DISABLE_INDEXING
4488 && REG_OK_FOR_BASE_P (operands[2])
4489 && (TARGET_NO_SPACE_REGS
4490 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4491 && FP_REGNO_P (REGNO (operands[3]))"
4492 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4494 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4498 [(set (match_operand:SF 0 "move_dest_operand"
4500 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4502 "(register_operand (operands[0], SFmode)
4503 || reg_or_0_operand (operands[1], SFmode))
4504 && TARGET_SOFT_FLOAT"
4509 [(set_attr "type" "move,load,store")
4510 (set_attr "pa_combine_type" "addmove")
4511 (set_attr "length" "4,4,4")])
4515 ;;- zero extension instructions
4516 ;; We have define_expand for zero extension patterns to make sure the
4517 ;; operands get loaded into registers. The define_insns accept
4518 ;; memory operands. This gives us better overall code than just
4519 ;; having a pattern that does or does not accept memory operands.
4521 (define_expand "zero_extendqihi2"
4522 [(set (match_operand:HI 0 "register_operand" "")
4524 (match_operand:QI 1 "register_operand" "")))]
4529 [(set (match_operand:HI 0 "register_operand" "=r,r")
4531 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4532 "GET_CODE (operands[1]) != CONST_INT"
4534 {extru|extrw,u} %1,31,8,%0
4536 [(set_attr "type" "shift,load")
4537 (set_attr "length" "4,4")])
4539 (define_expand "zero_extendqisi2"
4540 [(set (match_operand:SI 0 "register_operand" "")
4542 (match_operand:QI 1 "register_operand" "")))]
4547 [(set (match_operand:SI 0 "register_operand" "=r,r")
4549 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4550 "GET_CODE (operands[1]) != CONST_INT"
4552 {extru|extrw,u} %1,31,8,%0
4554 [(set_attr "type" "shift,load")
4555 (set_attr "length" "4,4")])
4557 (define_expand "zero_extendhisi2"
4558 [(set (match_operand:SI 0 "register_operand" "")
4560 (match_operand:HI 1 "register_operand" "")))]
4565 [(set (match_operand:SI 0 "register_operand" "=r,r")
4567 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4568 "GET_CODE (operands[1]) != CONST_INT"
4570 {extru|extrw,u} %1,31,16,%0
4572 [(set_attr "type" "shift,load")
4573 (set_attr "length" "4,4")])
4575 (define_expand "zero_extendqidi2"
4576 [(set (match_operand:DI 0 "register_operand" "")
4578 (match_operand:QI 1 "register_operand" "")))]
4583 [(set (match_operand:DI 0 "register_operand" "=r,r")
4585 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4586 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4590 [(set_attr "type" "shift,load")
4591 (set_attr "length" "4,4")])
4593 (define_expand "zero_extendhidi2"
4594 [(set (match_operand:DI 0 "register_operand" "")
4596 (match_operand:HI 1 "register_operand" "")))]
4601 [(set (match_operand:DI 0 "register_operand" "=r,r")
4603 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4604 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4608 [(set_attr "type" "shift,load")
4609 (set_attr "length" "4,4")])
4611 (define_expand "zero_extendsidi2"
4612 [(set (match_operand:DI 0 "register_operand" "")
4614 (match_operand:SI 1 "register_operand" "")))]
4619 [(set (match_operand:DI 0 "register_operand" "=r,r")
4621 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4622 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4626 [(set_attr "type" "shift,load")
4627 (set_attr "length" "4,4")])
4629 ;;- sign extension instructions
4631 (define_insn "extendhisi2"
4632 [(set (match_operand:SI 0 "register_operand" "=r")
4633 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4635 "{extrs|extrw,s} %1,31,16,%0"
4636 [(set_attr "type" "shift")
4637 (set_attr "length" "4")])
4639 (define_insn "extendqihi2"
4640 [(set (match_operand:HI 0 "register_operand" "=r")
4641 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4643 "{extrs|extrw,s} %1,31,8,%0"
4644 [(set_attr "type" "shift")
4645 (set_attr "length" "4")])
4647 (define_insn "extendqisi2"
4648 [(set (match_operand:SI 0 "register_operand" "=r")
4649 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4651 "{extrs|extrw,s} %1,31,8,%0"
4652 [(set_attr "type" "shift")
4653 (set_attr "length" "4")])
4655 (define_insn "extendqidi2"
4656 [(set (match_operand:DI 0 "register_operand" "=r")
4657 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4659 "extrd,s %1,63,8,%0"
4660 [(set_attr "type" "shift")
4661 (set_attr "length" "4")])
4663 (define_insn "extendhidi2"
4664 [(set (match_operand:DI 0 "register_operand" "=r")
4665 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4667 "extrd,s %1,63,16,%0"
4668 [(set_attr "type" "shift")
4669 (set_attr "length" "4")])
4671 (define_insn "extendsidi2"
4672 [(set (match_operand:DI 0 "register_operand" "=r")
4673 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4675 "extrd,s %1,63,32,%0"
4676 [(set_attr "type" "shift")
4677 (set_attr "length" "4")])
4680 ;; Conversions between float and double.
4682 (define_insn "extendsfdf2"
4683 [(set (match_operand:DF 0 "register_operand" "=f")
4685 (match_operand:SF 1 "register_operand" "f")))]
4686 "! TARGET_SOFT_FLOAT"
4687 "{fcnvff|fcnv},sgl,dbl %1,%0"
4688 [(set_attr "type" "fpalu")
4689 (set_attr "length" "4")])
4691 (define_insn "truncdfsf2"
4692 [(set (match_operand:SF 0 "register_operand" "=f")
4694 (match_operand:DF 1 "register_operand" "f")))]
4695 "! TARGET_SOFT_FLOAT"
4696 "{fcnvff|fcnv},dbl,sgl %1,%0"
4697 [(set_attr "type" "fpalu")
4698 (set_attr "length" "4")])
4700 ;; Conversion between fixed point and floating point.
4701 ;; Note that among the fix-to-float insns
4702 ;; the ones that start with SImode come first.
4703 ;; That is so that an operand that is a CONST_INT
4704 ;; (and therefore lacks a specific machine mode).
4705 ;; will be recognized as SImode (which is always valid)
4706 ;; rather than as QImode or HImode.
4708 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4709 ;; to be reloaded by putting the constant into memory.
4710 ;; It must come before the more general floatsisf2 pattern.
4712 [(set (match_operand:SF 0 "register_operand" "=f")
4713 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4714 "! TARGET_SOFT_FLOAT"
4715 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4716 [(set_attr "type" "fpalu")
4717 (set_attr "length" "8")])
4719 (define_insn "floatsisf2"
4720 [(set (match_operand:SF 0 "register_operand" "=f")
4721 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4722 "! TARGET_SOFT_FLOAT"
4723 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4724 [(set_attr "type" "fpalu")
4725 (set_attr "length" "4")])
4727 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4728 ;; to be reloaded by putting the constant into memory.
4729 ;; It must come before the more general floatsidf2 pattern.
4731 [(set (match_operand:DF 0 "register_operand" "=f")
4732 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4733 "! TARGET_SOFT_FLOAT"
4734 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4735 [(set_attr "type" "fpalu")
4736 (set_attr "length" "8")])
4738 (define_insn "floatsidf2"
4739 [(set (match_operand:DF 0 "register_operand" "=f")
4740 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4741 "! TARGET_SOFT_FLOAT"
4742 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4743 [(set_attr "type" "fpalu")
4744 (set_attr "length" "4")])
4746 (define_expand "floatunssisf2"
4747 [(set (subreg:SI (match_dup 2) 4)
4748 (match_operand:SI 1 "register_operand" ""))
4749 (set (subreg:SI (match_dup 2) 0)
4751 (set (match_operand:SF 0 "register_operand" "")
4752 (float:SF (match_dup 2)))]
4753 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4758 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4761 operands[2] = gen_reg_rtx (DImode);
4764 (define_expand "floatunssidf2"
4765 [(set (subreg:SI (match_dup 2) 4)
4766 (match_operand:SI 1 "register_operand" ""))
4767 (set (subreg:SI (match_dup 2) 0)
4769 (set (match_operand:DF 0 "register_operand" "")
4770 (float:DF (match_dup 2)))]
4771 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4776 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4779 operands[2] = gen_reg_rtx (DImode);
4782 (define_insn "floatdisf2"
4783 [(set (match_operand:SF 0 "register_operand" "=f")
4784 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4785 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4786 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4787 [(set_attr "type" "fpalu")
4788 (set_attr "length" "4")])
4790 (define_insn "floatdidf2"
4791 [(set (match_operand:DF 0 "register_operand" "=f")
4792 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4793 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4794 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4795 [(set_attr "type" "fpalu")
4796 (set_attr "length" "4")])
4798 ;; Convert a float to an actual integer.
4799 ;; Truncation is performed as part of the conversion.
4801 (define_insn "fix_truncsfsi2"
4802 [(set (match_operand:SI 0 "register_operand" "=f")
4803 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4804 "! TARGET_SOFT_FLOAT"
4805 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4806 [(set_attr "type" "fpalu")
4807 (set_attr "length" "4")])
4809 (define_insn "fix_truncdfsi2"
4810 [(set (match_operand:SI 0 "register_operand" "=f")
4811 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4812 "! TARGET_SOFT_FLOAT"
4813 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4814 [(set_attr "type" "fpalu")
4815 (set_attr "length" "4")])
4817 (define_insn "fix_truncsfdi2"
4818 [(set (match_operand:DI 0 "register_operand" "=f")
4819 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4820 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4821 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4822 [(set_attr "type" "fpalu")
4823 (set_attr "length" "4")])
4825 (define_insn "fix_truncdfdi2"
4826 [(set (match_operand:DI 0 "register_operand" "=f")
4827 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4828 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4829 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4830 [(set_attr "type" "fpalu")
4831 (set_attr "length" "4")])
4833 (define_insn "floatunssidf2_pa20"
4834 [(set (match_operand:DF 0 "register_operand" "=f")
4835 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4836 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4838 [(set_attr "type" "fpalu")
4839 (set_attr "length" "4")])
4841 (define_insn "floatunssisf2_pa20"
4842 [(set (match_operand:SF 0 "register_operand" "=f")
4843 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4844 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4846 [(set_attr "type" "fpalu")
4847 (set_attr "length" "4")])
4849 (define_insn "floatunsdisf2"
4850 [(set (match_operand:SF 0 "register_operand" "=f")
4851 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4852 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4853 "fcnv,udw,sgl %1,%0"
4854 [(set_attr "type" "fpalu")
4855 (set_attr "length" "4")])
4857 (define_insn "floatunsdidf2"
4858 [(set (match_operand:DF 0 "register_operand" "=f")
4859 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4860 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4861 "fcnv,udw,dbl %1,%0"
4862 [(set_attr "type" "fpalu")
4863 (set_attr "length" "4")])
4865 (define_insn "fixuns_truncsfsi2"
4866 [(set (match_operand:SI 0 "register_operand" "=f")
4867 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4868 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4869 "fcnv,t,sgl,uw %1,%0"
4870 [(set_attr "type" "fpalu")
4871 (set_attr "length" "4")])
4873 (define_insn "fixuns_truncdfsi2"
4874 [(set (match_operand:SI 0 "register_operand" "=f")
4875 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4876 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4877 "fcnv,t,dbl,uw %1,%0"
4878 [(set_attr "type" "fpalu")
4879 (set_attr "length" "4")])
4881 (define_insn "fixuns_truncsfdi2"
4882 [(set (match_operand:DI 0 "register_operand" "=f")
4883 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4884 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4885 "fcnv,t,sgl,udw %1,%0"
4886 [(set_attr "type" "fpalu")
4887 (set_attr "length" "4")])
4889 (define_insn "fixuns_truncdfdi2"
4890 [(set (match_operand:DI 0 "register_operand" "=f")
4891 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4892 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4893 "fcnv,t,dbl,udw %1,%0"
4894 [(set_attr "type" "fpalu")
4895 (set_attr "length" "4")])
4897 ;;- arithmetic instructions
4899 (define_expand "adddi3"
4900 [(set (match_operand:DI 0 "register_operand" "")
4901 (plus:DI (match_operand:DI 1 "register_operand" "")
4902 (match_operand:DI 2 "adddi3_operand" "")))]
4907 [(set (match_operand:DI 0 "register_operand" "=r")
4908 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4909 (match_operand:DI 2 "arith11_operand" "rI")))]
4913 if (GET_CODE (operands[2]) == CONST_INT)
4915 if (INTVAL (operands[2]) >= 0)
4916 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4918 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4921 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4923 [(set_attr "type" "binary")
4924 (set_attr "length" "8")])
4927 [(set (match_operand:DI 0 "register_operand" "=r,r")
4928 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4929 (match_operand:DI 2 "arith_operand" "r,J")))]
4934 [(set_attr "type" "binary,binary")
4935 (set_attr "pa_combine_type" "addmove")
4936 (set_attr "length" "4,4")])
4939 [(set (match_operand:DI 0 "register_operand" "=r")
4940 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4941 (match_operand:DI 2 "register_operand" "r")))]
4944 [(set_attr "type" "binary")
4945 (set_attr "length" "4")])
4948 [(set (match_operand:SI 0 "register_operand" "=r")
4949 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4950 (match_operand:SI 2 "register_operand" "r")))]
4953 [(set_attr "type" "binary")
4954 (set_attr "length" "4")])
4956 ;; define_splits to optimize cases of adding a constant integer
4957 ;; to a register when the constant does not fit in 14 bits. */
4959 [(set (match_operand:SI 0 "register_operand" "")
4960 (plus:SI (match_operand:SI 1 "register_operand" "")
4961 (match_operand:SI 2 "const_int_operand" "")))
4962 (clobber (match_operand:SI 4 "register_operand" ""))]
4963 "! cint_ok_for_move (INTVAL (operands[2]))
4964 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4965 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4966 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4969 int val = INTVAL (operands[2]);
4970 int low = (val < 0) ? -0x2000 : 0x1fff;
4971 int rest = val - low;
4973 operands[2] = GEN_INT (rest);
4974 operands[3] = GEN_INT (low);
4978 [(set (match_operand:SI 0 "register_operand" "")
4979 (plus:SI (match_operand:SI 1 "register_operand" "")
4980 (match_operand:SI 2 "const_int_operand" "")))
4981 (clobber (match_operand:SI 4 "register_operand" ""))]
4982 "! cint_ok_for_move (INTVAL (operands[2]))"
4983 [(set (match_dup 4) (match_dup 2))
4984 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4988 HOST_WIDE_INT intval = INTVAL (operands[2]);
4990 /* Try dividing the constant by 2, then 4, and finally 8 to see
4991 if we can get a constant which can be loaded into a register
4992 in a single instruction (cint_ok_for_move).
4994 If that fails, try to negate the constant and subtract it
4995 from our input operand. */
4996 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4998 operands[2] = GEN_INT (intval / 2);
4999 operands[3] = const2_rtx;
5001 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5003 operands[2] = GEN_INT (intval / 4);
5004 operands[3] = GEN_INT (4);
5006 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5008 operands[2] = GEN_INT (intval / 8);
5009 operands[3] = GEN_INT (8);
5011 else if (cint_ok_for_move (-intval))
5013 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5014 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5021 (define_insn "addsi3"
5022 [(set (match_operand:SI 0 "register_operand" "=r,r")
5023 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5024 (match_operand:SI 2 "arith_operand" "r,J")))]
5027 {addl|add,l} %1,%2,%0
5029 [(set_attr "type" "binary,binary")
5030 (set_attr "pa_combine_type" "addmove")
5031 (set_attr "length" "4,4")])
5033 (define_expand "subdi3"
5034 [(set (match_operand:DI 0 "register_operand" "")
5035 (minus:DI (match_operand:DI 1 "register_operand" "")
5036 (match_operand:DI 2 "register_operand" "")))]
5041 [(set (match_operand:DI 0 "register_operand" "=r")
5042 (minus:DI (match_operand:DI 1 "register_operand" "r")
5043 (match_operand:DI 2 "register_operand" "r")))]
5045 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
5046 [(set_attr "type" "binary")
5047 (set_attr "length" "8")])
5050 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5051 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5052 (match_operand:DI 2 "register_operand" "r,r,!r")))]
5058 [(set_attr "type" "binary,binary,move")
5059 (set_attr "length" "4,4,4")])
5061 (define_expand "subsi3"
5062 [(set (match_operand:SI 0 "register_operand" "")
5063 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5064 (match_operand:SI 2 "register_operand" "")))]
5069 [(set (match_operand:SI 0 "register_operand" "=r,r")
5070 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5071 (match_operand:SI 2 "register_operand" "r,r")))]
5076 [(set_attr "type" "binary,binary")
5077 (set_attr "length" "4,4")])
5080 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5081 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5082 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5088 [(set_attr "type" "binary,binary,move")
5089 (set_attr "length" "4,4,4")])
5091 ;; Clobbering a "register_operand" instead of a match_scratch
5092 ;; in operand3 of millicode calls avoids spilling %r1 and
5093 ;; produces better code.
5095 ;; The mulsi3 insns set up registers for the millicode call.
5096 (define_expand "mulsi3"
5097 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5098 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5099 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5100 (clobber (match_dup 3))
5101 (clobber (reg:SI 26))
5102 (clobber (reg:SI 25))
5103 (clobber (match_dup 4))])
5104 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5108 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5109 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5111 rtx scratch = gen_reg_rtx (DImode);
5112 operands[1] = force_reg (SImode, operands[1]);
5113 operands[2] = force_reg (SImode, operands[2]);
5114 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5115 emit_insn (gen_movsi (operands[0],
5116 gen_rtx_SUBREG (SImode, scratch,
5117 GET_MODE_SIZE (SImode))));
5120 operands[3] = gen_reg_rtx (SImode);
5123 (define_insn "umulsidi3"
5124 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5125 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5126 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5127 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5129 [(set_attr "type" "fpmuldbl")
5130 (set_attr "length" "4")])
5133 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5134 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5135 (match_operand:DI 2 "uint32_operand" "f")))]
5136 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5138 [(set_attr "type" "fpmuldbl")
5139 (set_attr "length" "4")])
5142 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5143 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5144 (match_operand:DI 2 "uint32_operand" "f")))]
5145 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5147 [(set_attr "type" "fpmuldbl")
5148 (set_attr "length" "4")])
5151 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5152 (clobber (match_operand:SI 0 "register_operand" "=a"))
5153 (clobber (reg:SI 26))
5154 (clobber (reg:SI 25))
5155 (clobber (reg:SI 31))]
5157 "* return output_mul_insn (0, insn);"
5158 [(set_attr "type" "milli")
5159 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5162 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5163 (clobber (match_operand:SI 0 "register_operand" "=a"))
5164 (clobber (reg:SI 26))
5165 (clobber (reg:SI 25))
5166 (clobber (reg:SI 2))]
5168 "* return output_mul_insn (0, insn);"
5169 [(set_attr "type" "milli")
5170 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5172 (define_expand "muldi3"
5173 [(set (match_operand:DI 0 "register_operand" "")
5174 (mult:DI (match_operand:DI 1 "register_operand" "")
5175 (match_operand:DI 2 "register_operand" "")))]
5176 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5179 rtx low_product = gen_reg_rtx (DImode);
5180 rtx cross_product1 = gen_reg_rtx (DImode);
5181 rtx cross_product2 = gen_reg_rtx (DImode);
5182 rtx cross_scratch = gen_reg_rtx (DImode);
5183 rtx cross_product = gen_reg_rtx (DImode);
5184 rtx op1l, op1r, op2l, op2r;
5185 rtx op1shifted, op2shifted;
5187 op1shifted = gen_reg_rtx (DImode);
5188 op2shifted = gen_reg_rtx (DImode);
5189 op1l = gen_reg_rtx (SImode);
5190 op1r = gen_reg_rtx (SImode);
5191 op2l = gen_reg_rtx (SImode);
5192 op2r = gen_reg_rtx (SImode);
5194 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5196 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5198 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5199 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5200 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5201 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5203 /* Emit multiplies for the cross products. */
5204 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5205 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5207 /* Emit a multiply for the low sub-word. */
5208 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5210 /* Sum the cross products and shift them into proper position. */
5211 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5212 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5214 /* Add the cross product to the low product and store the result
5215 into the output operand . */
5216 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5220 ;;; Division and mod.
5221 (define_expand "divsi3"
5222 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5223 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5224 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5225 (clobber (match_dup 3))
5226 (clobber (match_dup 4))
5227 (clobber (reg:SI 26))
5228 (clobber (reg:SI 25))
5229 (clobber (match_dup 5))])
5230 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5234 operands[3] = gen_reg_rtx (SImode);
5237 operands[5] = gen_rtx_REG (SImode, 2);
5238 operands[4] = operands[5];
5242 operands[5] = gen_rtx_REG (SImode, 31);
5243 operands[4] = gen_reg_rtx (SImode);
5245 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5251 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5252 (clobber (match_operand:SI 1 "register_operand" "=a"))
5253 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5254 (clobber (reg:SI 26))
5255 (clobber (reg:SI 25))
5256 (clobber (reg:SI 31))]
5259 return output_div_insn (operands, 0, insn);"
5260 [(set_attr "type" "milli")
5261 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5265 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5266 (clobber (match_operand:SI 1 "register_operand" "=a"))
5267 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5268 (clobber (reg:SI 26))
5269 (clobber (reg:SI 25))
5270 (clobber (reg:SI 2))]
5273 return output_div_insn (operands, 0, insn);"
5274 [(set_attr "type" "milli")
5275 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5277 (define_expand "udivsi3"
5278 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5279 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5280 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5281 (clobber (match_dup 3))
5282 (clobber (match_dup 4))
5283 (clobber (reg:SI 26))
5284 (clobber (reg:SI 25))
5285 (clobber (match_dup 5))])
5286 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5290 operands[3] = gen_reg_rtx (SImode);
5294 operands[5] = gen_rtx_REG (SImode, 2);
5295 operands[4] = operands[5];
5299 operands[5] = gen_rtx_REG (SImode, 31);
5300 operands[4] = gen_reg_rtx (SImode);
5302 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5308 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5309 (clobber (match_operand:SI 1 "register_operand" "=a"))
5310 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5311 (clobber (reg:SI 26))
5312 (clobber (reg:SI 25))
5313 (clobber (reg:SI 31))]
5316 return output_div_insn (operands, 1, insn);"
5317 [(set_attr "type" "milli")
5318 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5322 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5323 (clobber (match_operand:SI 1 "register_operand" "=a"))
5324 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5325 (clobber (reg:SI 26))
5326 (clobber (reg:SI 25))
5327 (clobber (reg:SI 2))]
5330 return output_div_insn (operands, 1, insn);"
5331 [(set_attr "type" "milli")
5332 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5334 (define_expand "modsi3"
5335 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5336 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5337 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5338 (clobber (match_dup 3))
5339 (clobber (match_dup 4))
5340 (clobber (reg:SI 26))
5341 (clobber (reg:SI 25))
5342 (clobber (match_dup 5))])
5343 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5349 operands[5] = gen_rtx_REG (SImode, 2);
5350 operands[4] = operands[5];
5354 operands[5] = gen_rtx_REG (SImode, 31);
5355 operands[4] = gen_reg_rtx (SImode);
5357 operands[3] = gen_reg_rtx (SImode);
5361 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5362 (clobber (match_operand:SI 0 "register_operand" "=a"))
5363 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5364 (clobber (reg:SI 26))
5365 (clobber (reg:SI 25))
5366 (clobber (reg:SI 31))]
5369 return output_mod_insn (0, insn);"
5370 [(set_attr "type" "milli")
5371 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5374 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5375 (clobber (match_operand:SI 0 "register_operand" "=a"))
5376 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5377 (clobber (reg:SI 26))
5378 (clobber (reg:SI 25))
5379 (clobber (reg:SI 2))]
5382 return output_mod_insn (0, insn);"
5383 [(set_attr "type" "milli")
5384 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5386 (define_expand "umodsi3"
5387 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5388 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5389 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5390 (clobber (match_dup 3))
5391 (clobber (match_dup 4))
5392 (clobber (reg:SI 26))
5393 (clobber (reg:SI 25))
5394 (clobber (match_dup 5))])
5395 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5401 operands[5] = gen_rtx_REG (SImode, 2);
5402 operands[4] = operands[5];
5406 operands[5] = gen_rtx_REG (SImode, 31);
5407 operands[4] = gen_reg_rtx (SImode);
5409 operands[3] = gen_reg_rtx (SImode);
5413 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5414 (clobber (match_operand:SI 0 "register_operand" "=a"))
5415 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5416 (clobber (reg:SI 26))
5417 (clobber (reg:SI 25))
5418 (clobber (reg:SI 31))]
5421 return output_mod_insn (1, insn);"
5422 [(set_attr "type" "milli")
5423 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5426 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5427 (clobber (match_operand:SI 0 "register_operand" "=a"))
5428 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5429 (clobber (reg:SI 26))
5430 (clobber (reg:SI 25))
5431 (clobber (reg:SI 2))]
5434 return output_mod_insn (1, insn);"
5435 [(set_attr "type" "milli")
5436 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5438 ;;- and instructions
5439 ;; We define DImode `and` so with DImode `not` we can get
5440 ;; DImode `andn`. Other combinations are possible.
5442 (define_expand "anddi3"
5443 [(set (match_operand:DI 0 "register_operand" "")
5444 (and:DI (match_operand:DI 1 "and_operand" "")
5445 (match_operand:DI 2 "and_operand" "")))]
5451 /* One operand must be a register operand. */
5452 if (!register_operand (operands[1], DImode)
5453 && !register_operand (operands[2], DImode))
5458 /* Both operands must be register operands. */
5459 if (!register_operand (operands[1], DImode)
5460 || !register_operand (operands[2], DImode))
5466 [(set (match_operand:DI 0 "register_operand" "=r")
5467 (and:DI (match_operand:DI 1 "register_operand" "%r")
5468 (match_operand:DI 2 "register_operand" "r")))]
5470 "and %1,%2,%0\;and %R1,%R2,%R0"
5471 [(set_attr "type" "binary")
5472 (set_attr "length" "8")])
5475 [(set (match_operand:DI 0 "register_operand" "=r,r")
5476 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5477 (match_operand:DI 2 "and_operand" "rO,P")))]
5479 "* return output_64bit_and (operands); "
5480 [(set_attr "type" "binary")
5481 (set_attr "length" "4")])
5483 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5484 ; constant with ldil;ldo.
5485 (define_insn "andsi3"
5486 [(set (match_operand:SI 0 "register_operand" "=r,r")
5487 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5488 (match_operand:SI 2 "and_operand" "rO,P")))]
5490 "* return output_and (operands); "
5491 [(set_attr "type" "binary,shift")
5492 (set_attr "length" "4,4")])
5495 [(set (match_operand:DI 0 "register_operand" "=r")
5496 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5497 (match_operand:DI 2 "register_operand" "r")))]
5499 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5500 [(set_attr "type" "binary")
5501 (set_attr "length" "8")])
5504 [(set (match_operand:DI 0 "register_operand" "=r")
5505 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5506 (match_operand:DI 2 "register_operand" "r")))]
5509 [(set_attr "type" "binary")
5510 (set_attr "length" "4")])
5513 [(set (match_operand:SI 0 "register_operand" "=r")
5514 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5515 (match_operand:SI 2 "register_operand" "r")))]
5518 [(set_attr "type" "binary")
5519 (set_attr "length" "4")])
5521 (define_expand "iordi3"
5522 [(set (match_operand:DI 0 "register_operand" "")
5523 (ior:DI (match_operand:DI 1 "ior_operand" "")
5524 (match_operand:DI 2 "ior_operand" "")))]
5530 /* One operand must be a register operand. */
5531 if (!register_operand (operands[1], DImode)
5532 && !register_operand (operands[2], DImode))
5537 /* Both operands must be register operands. */
5538 if (!register_operand (operands[1], DImode)
5539 || !register_operand (operands[2], DImode))
5545 [(set (match_operand:DI 0 "register_operand" "=r")
5546 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5547 (match_operand:DI 2 "register_operand" "r")))]
5549 "or %1,%2,%0\;or %R1,%R2,%R0"
5550 [(set_attr "type" "binary")
5551 (set_attr "length" "8")])
5554 [(set (match_operand:DI 0 "register_operand" "=r,r")
5555 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5556 (match_operand:DI 2 "ior_operand" "M,i")))]
5558 "* return output_64bit_ior (operands); "
5559 [(set_attr "type" "binary,shift")
5560 (set_attr "length" "4,4")])
5563 [(set (match_operand:DI 0 "register_operand" "=r")
5564 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5565 (match_operand:DI 2 "register_operand" "r")))]
5568 [(set_attr "type" "binary")
5569 (set_attr "length" "4")])
5571 ;; Need a define_expand because we've run out of CONST_OK... characters.
5572 (define_expand "iorsi3"
5573 [(set (match_operand:SI 0 "register_operand" "")
5574 (ior:SI (match_operand:SI 1 "register_operand" "")
5575 (match_operand:SI 2 "arith32_operand" "")))]
5579 if (! (ior_operand (operands[2], SImode)
5580 || register_operand (operands[2], SImode)))
5581 operands[2] = force_reg (SImode, operands[2]);
5585 [(set (match_operand:SI 0 "register_operand" "=r,r")
5586 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5587 (match_operand:SI 2 "ior_operand" "M,i")))]
5589 "* return output_ior (operands); "
5590 [(set_attr "type" "binary,shift")
5591 (set_attr "length" "4,4")])
5594 [(set (match_operand:SI 0 "register_operand" "=r")
5595 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5596 (match_operand:SI 2 "register_operand" "r")))]
5599 [(set_attr "type" "binary")
5600 (set_attr "length" "4")])
5602 (define_expand "xordi3"
5603 [(set (match_operand:DI 0 "register_operand" "")
5604 (xor:DI (match_operand:DI 1 "register_operand" "")
5605 (match_operand:DI 2 "register_operand" "")))]
5612 [(set (match_operand:DI 0 "register_operand" "=r")
5613 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5614 (match_operand:DI 2 "register_operand" "r")))]
5616 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5617 [(set_attr "type" "binary")
5618 (set_attr "length" "8")])
5621 [(set (match_operand:DI 0 "register_operand" "=r")
5622 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5623 (match_operand:DI 2 "register_operand" "r")))]
5626 [(set_attr "type" "binary")
5627 (set_attr "length" "4")])
5629 (define_insn "xorsi3"
5630 [(set (match_operand:SI 0 "register_operand" "=r")
5631 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5632 (match_operand:SI 2 "register_operand" "r")))]
5635 [(set_attr "type" "binary")
5636 (set_attr "length" "4")])
5638 (define_expand "negdi2"
5639 [(set (match_operand:DI 0 "register_operand" "")
5640 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5645 [(set (match_operand:DI 0 "register_operand" "=r")
5646 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5648 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5649 [(set_attr "type" "unary")
5650 (set_attr "length" "8")])
5653 [(set (match_operand:DI 0 "register_operand" "=r")
5654 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5657 [(set_attr "type" "unary")
5658 (set_attr "length" "4")])
5660 (define_insn "negsi2"
5661 [(set (match_operand:SI 0 "register_operand" "=r")
5662 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5665 [(set_attr "type" "unary")
5666 (set_attr "length" "4")])
5668 (define_expand "one_cmpldi2"
5669 [(set (match_operand:DI 0 "register_operand" "")
5670 (not:DI (match_operand:DI 1 "register_operand" "")))]
5677 [(set (match_operand:DI 0 "register_operand" "=r")
5678 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5680 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5681 [(set_attr "type" "unary")
5682 (set_attr "length" "8")])
5685 [(set (match_operand:DI 0 "register_operand" "=r")
5686 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5689 [(set_attr "type" "unary")
5690 (set_attr "length" "4")])
5692 (define_insn "one_cmplsi2"
5693 [(set (match_operand:SI 0 "register_operand" "=r")
5694 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5697 [(set_attr "type" "unary")
5698 (set_attr "length" "4")])
5700 ;; Floating point arithmetic instructions.
5702 (define_insn "adddf3"
5703 [(set (match_operand:DF 0 "register_operand" "=f")
5704 (plus:DF (match_operand:DF 1 "register_operand" "f")
5705 (match_operand:DF 2 "register_operand" "f")))]
5706 "! TARGET_SOFT_FLOAT"
5708 [(set_attr "type" "fpalu")
5709 (set_attr "pa_combine_type" "faddsub")
5710 (set_attr "length" "4")])
5712 (define_insn "addsf3"
5713 [(set (match_operand:SF 0 "register_operand" "=f")
5714 (plus:SF (match_operand:SF 1 "register_operand" "f")
5715 (match_operand:SF 2 "register_operand" "f")))]
5716 "! TARGET_SOFT_FLOAT"
5718 [(set_attr "type" "fpalu")
5719 (set_attr "pa_combine_type" "faddsub")
5720 (set_attr "length" "4")])
5722 (define_insn "subdf3"
5723 [(set (match_operand:DF 0 "register_operand" "=f")
5724 (minus:DF (match_operand:DF 1 "register_operand" "f")
5725 (match_operand:DF 2 "register_operand" "f")))]
5726 "! TARGET_SOFT_FLOAT"
5728 [(set_attr "type" "fpalu")
5729 (set_attr "pa_combine_type" "faddsub")
5730 (set_attr "length" "4")])
5732 (define_insn "subsf3"
5733 [(set (match_operand:SF 0 "register_operand" "=f")
5734 (minus:SF (match_operand:SF 1 "register_operand" "f")
5735 (match_operand:SF 2 "register_operand" "f")))]
5736 "! TARGET_SOFT_FLOAT"
5738 [(set_attr "type" "fpalu")
5739 (set_attr "pa_combine_type" "faddsub")
5740 (set_attr "length" "4")])
5742 (define_insn "muldf3"
5743 [(set (match_operand:DF 0 "register_operand" "=f")
5744 (mult:DF (match_operand:DF 1 "register_operand" "f")
5745 (match_operand:DF 2 "register_operand" "f")))]
5746 "! TARGET_SOFT_FLOAT"
5748 [(set_attr "type" "fpmuldbl")
5749 (set_attr "pa_combine_type" "fmpy")
5750 (set_attr "length" "4")])
5752 (define_insn "mulsf3"
5753 [(set (match_operand:SF 0 "register_operand" "=f")
5754 (mult:SF (match_operand:SF 1 "register_operand" "f")
5755 (match_operand:SF 2 "register_operand" "f")))]
5756 "! TARGET_SOFT_FLOAT"
5758 [(set_attr "type" "fpmulsgl")
5759 (set_attr "pa_combine_type" "fmpy")
5760 (set_attr "length" "4")])
5762 (define_insn "divdf3"
5763 [(set (match_operand:DF 0 "register_operand" "=f")
5764 (div:DF (match_operand:DF 1 "register_operand" "f")
5765 (match_operand:DF 2 "register_operand" "f")))]
5766 "! TARGET_SOFT_FLOAT"
5768 [(set_attr "type" "fpdivdbl")
5769 (set_attr "length" "4")])
5771 (define_insn "divsf3"
5772 [(set (match_operand:SF 0 "register_operand" "=f")
5773 (div:SF (match_operand:SF 1 "register_operand" "f")
5774 (match_operand:SF 2 "register_operand" "f")))]
5775 "! TARGET_SOFT_FLOAT"
5777 [(set_attr "type" "fpdivsgl")
5778 (set_attr "length" "4")])
5780 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5781 ;; negation can be done by subtracting from plus zero. However, this
5782 ;; violates the IEEE standard when negating plus and minus zero.
5783 (define_expand "negdf2"
5784 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5785 (neg:DF (match_operand:DF 1 "register_operand" "")))
5786 (use (match_dup 2))])]
5787 "! TARGET_SOFT_FLOAT"
5789 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5790 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5793 operands[2] = force_reg (DFmode,
5794 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5795 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5800 (define_insn "negdf2_fast"
5801 [(set (match_operand:DF 0 "register_operand" "=f")
5802 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5803 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5807 return \"fneg,dbl %1,%0\";
5809 return \"fsub,dbl %%fr0,%1,%0\";
5811 [(set_attr "type" "fpalu")
5812 (set_attr "length" "4")])
5814 (define_expand "negsf2"
5815 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5816 (neg:SF (match_operand:SF 1 "register_operand" "")))
5817 (use (match_dup 2))])]
5818 "! TARGET_SOFT_FLOAT"
5820 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5821 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5824 operands[2] = force_reg (SFmode,
5825 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5826 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5831 (define_insn "negsf2_fast"
5832 [(set (match_operand:SF 0 "register_operand" "=f")
5833 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5834 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5838 return \"fneg,sgl %1,%0\";
5840 return \"fsub,sgl %%fr0,%1,%0\";
5842 [(set_attr "type" "fpalu")
5843 (set_attr "length" "4")])
5845 (define_insn "absdf2"
5846 [(set (match_operand:DF 0 "register_operand" "=f")
5847 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5848 "! TARGET_SOFT_FLOAT"
5850 [(set_attr "type" "fpalu")
5851 (set_attr "length" "4")])
5853 (define_insn "abssf2"
5854 [(set (match_operand:SF 0 "register_operand" "=f")
5855 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5856 "! TARGET_SOFT_FLOAT"
5858 [(set_attr "type" "fpalu")
5859 (set_attr "length" "4")])
5861 (define_insn "sqrtdf2"
5862 [(set (match_operand:DF 0 "register_operand" "=f")
5863 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5864 "! TARGET_SOFT_FLOAT"
5866 [(set_attr "type" "fpsqrtdbl")
5867 (set_attr "length" "4")])
5869 (define_insn "sqrtsf2"
5870 [(set (match_operand:SF 0 "register_operand" "=f")
5871 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5872 "! TARGET_SOFT_FLOAT"
5874 [(set_attr "type" "fpsqrtsgl")
5875 (set_attr "length" "4")])
5877 ;; PA 2.0 floating point instructions
5881 [(set (match_operand:DF 0 "register_operand" "=f")
5882 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5883 (match_operand:DF 2 "register_operand" "f"))
5884 (match_operand:DF 3 "register_operand" "f")))]
5885 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5886 "fmpyfadd,dbl %1,%2,%3,%0"
5887 [(set_attr "type" "fpmuldbl")
5888 (set_attr "length" "4")])
5891 [(set (match_operand:DF 0 "register_operand" "=f")
5892 (plus:DF (match_operand:DF 1 "register_operand" "f")
5893 (mult:DF (match_operand:DF 2 "register_operand" "f")
5894 (match_operand:DF 3 "register_operand" "f"))))]
5895 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5896 "fmpyfadd,dbl %2,%3,%1,%0"
5897 [(set_attr "type" "fpmuldbl")
5898 (set_attr "length" "4")])
5901 [(set (match_operand:SF 0 "register_operand" "=f")
5902 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5903 (match_operand:SF 2 "register_operand" "f"))
5904 (match_operand:SF 3 "register_operand" "f")))]
5905 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5906 "fmpyfadd,sgl %1,%2,%3,%0"
5907 [(set_attr "type" "fpmulsgl")
5908 (set_attr "length" "4")])
5911 [(set (match_operand:SF 0 "register_operand" "=f")
5912 (plus:SF (match_operand:SF 1 "register_operand" "f")
5913 (mult:SF (match_operand:SF 2 "register_operand" "f")
5914 (match_operand:SF 3 "register_operand" "f"))))]
5915 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5916 "fmpyfadd,sgl %2,%3,%1,%0"
5917 [(set_attr "type" "fpmulsgl")
5918 (set_attr "length" "4")])
5920 ; fmpynfadd patterns
5922 [(set (match_operand:DF 0 "register_operand" "=f")
5923 (minus:DF (match_operand:DF 1 "register_operand" "f")
5924 (mult:DF (match_operand:DF 2 "register_operand" "f")
5925 (match_operand:DF 3 "register_operand" "f"))))]
5926 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5927 "fmpynfadd,dbl %2,%3,%1,%0"
5928 [(set_attr "type" "fpmuldbl")
5929 (set_attr "length" "4")])
5932 [(set (match_operand:SF 0 "register_operand" "=f")
5933 (minus:SF (match_operand:SF 1 "register_operand" "f")
5934 (mult:SF (match_operand:SF 2 "register_operand" "f")
5935 (match_operand:SF 3 "register_operand" "f"))))]
5936 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5937 "fmpynfadd,sgl %2,%3,%1,%0"
5938 [(set_attr "type" "fpmulsgl")
5939 (set_attr "length" "4")])
5943 [(set (match_operand:DF 0 "register_operand" "=f")
5944 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5945 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5947 [(set_attr "type" "fpalu")
5948 (set_attr "length" "4")])
5951 [(set (match_operand:SF 0 "register_operand" "=f")
5952 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5953 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5955 [(set_attr "type" "fpalu")
5956 (set_attr "length" "4")])
5958 ;; Generating a fused multiply sequence is a win for this case as it will
5959 ;; reduce the latency for the fused case without impacting the plain
5962 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5963 ;; perform two operations with the result of the first feeding the second.
5965 [(set (match_operand:DF 0 "register_operand" "=f")
5966 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5967 (match_operand:DF 2 "register_operand" "f"))
5968 (match_operand:DF 3 "register_operand" "f")))
5969 (set (match_operand:DF 4 "register_operand" "=&f")
5970 (mult:DF (match_dup 1) (match_dup 2)))]
5971 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5972 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5973 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5975 [(set_attr "type" "fpmuldbl")
5976 (set_attr "length" "8")])
5978 ;; We want to split this up during scheduling since we want both insns
5979 ;; to schedule independently.
5981 [(set (match_operand:DF 0 "register_operand" "")
5982 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5983 (match_operand:DF 2 "register_operand" ""))
5984 (match_operand:DF 3 "register_operand" "")))
5985 (set (match_operand:DF 4 "register_operand" "")
5986 (mult:DF (match_dup 1) (match_dup 2)))]
5987 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5988 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5989 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5994 [(set (match_operand:SF 0 "register_operand" "=f")
5995 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5996 (match_operand:SF 2 "register_operand" "f"))
5997 (match_operand:SF 3 "register_operand" "f")))
5998 (set (match_operand:SF 4 "register_operand" "=&f")
5999 (mult:SF (match_dup 1) (match_dup 2)))]
6000 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6001 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6002 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6004 [(set_attr "type" "fpmuldbl")
6005 (set_attr "length" "8")])
6007 ;; We want to split this up during scheduling since we want both insns
6008 ;; to schedule independently.
6010 [(set (match_operand:SF 0 "register_operand" "")
6011 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6012 (match_operand:SF 2 "register_operand" ""))
6013 (match_operand:SF 3 "register_operand" "")))
6014 (set (match_operand:SF 4 "register_operand" "")
6015 (mult:SF (match_dup 1) (match_dup 2)))]
6016 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6017 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6018 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6022 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6025 [(set (match_operand:DF 0 "register_operand" "=f")
6026 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6027 (match_operand:DF 2 "register_operand" "f"))))]
6028 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6029 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6030 [(set_attr "type" "fpmuldbl")
6031 (set_attr "length" "4")])
6034 [(set (match_operand:SF 0 "register_operand" "=f")
6035 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6036 (match_operand:SF 2 "register_operand" "f"))))]
6037 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6038 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6039 [(set_attr "type" "fpmuldbl")
6040 (set_attr "length" "4")])
6043 [(set (match_operand:DF 0 "register_operand" "=f")
6044 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6045 (match_operand:DF 2 "register_operand" "f"))))
6046 (set (match_operand:DF 3 "register_operand" "=&f")
6047 (mult:DF (match_dup 1) (match_dup 2)))]
6048 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6049 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6050 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6052 [(set_attr "type" "fpmuldbl")
6053 (set_attr "length" "8")])
6056 [(set (match_operand:DF 0 "register_operand" "")
6057 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6058 (match_operand:DF 2 "register_operand" ""))))
6059 (set (match_operand:DF 3 "register_operand" "")
6060 (mult:DF (match_dup 1) (match_dup 2)))]
6061 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6062 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6063 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6067 [(set (match_operand:SF 0 "register_operand" "=f")
6068 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6069 (match_operand:SF 2 "register_operand" "f"))))
6070 (set (match_operand:SF 3 "register_operand" "=&f")
6071 (mult:SF (match_dup 1) (match_dup 2)))]
6072 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6073 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6074 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6076 [(set_attr "type" "fpmuldbl")
6077 (set_attr "length" "8")])
6080 [(set (match_operand:SF 0 "register_operand" "")
6081 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6082 (match_operand:SF 2 "register_operand" ""))))
6083 (set (match_operand:SF 3 "register_operand" "")
6084 (mult:SF (match_dup 1) (match_dup 2)))]
6085 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6086 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6087 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6090 ;; Now fused multiplies with the result of the multiply negated.
6092 [(set (match_operand:DF 0 "register_operand" "=f")
6093 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6094 (match_operand:DF 2 "register_operand" "f")))
6095 (match_operand:DF 3 "register_operand" "f")))]
6096 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6097 "fmpynfadd,dbl %1,%2,%3,%0"
6098 [(set_attr "type" "fpmuldbl")
6099 (set_attr "length" "4")])
6102 [(set (match_operand:SF 0 "register_operand" "=f")
6103 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6104 (match_operand:SF 2 "register_operand" "f")))
6105 (match_operand:SF 3 "register_operand" "f")))]
6106 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6107 "fmpynfadd,sgl %1,%2,%3,%0"
6108 [(set_attr "type" "fpmuldbl")
6109 (set_attr "length" "4")])
6112 [(set (match_operand:DF 0 "register_operand" "=f")
6113 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6114 (match_operand:DF 2 "register_operand" "f")))
6115 (match_operand:DF 3 "register_operand" "f")))
6116 (set (match_operand:DF 4 "register_operand" "=&f")
6117 (mult:DF (match_dup 1) (match_dup 2)))]
6118 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6119 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6120 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6122 [(set_attr "type" "fpmuldbl")
6123 (set_attr "length" "8")])
6126 [(set (match_operand:DF 0 "register_operand" "")
6127 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6128 (match_operand:DF 2 "register_operand" "")))
6129 (match_operand:DF 3 "register_operand" "")))
6130 (set (match_operand:DF 4 "register_operand" "")
6131 (mult:DF (match_dup 1) (match_dup 2)))]
6132 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6133 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6134 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6139 [(set (match_operand:SF 0 "register_operand" "=f")
6140 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6141 (match_operand:SF 2 "register_operand" "f")))
6142 (match_operand:SF 3 "register_operand" "f")))
6143 (set (match_operand:SF 4 "register_operand" "=&f")
6144 (mult:SF (match_dup 1) (match_dup 2)))]
6145 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6146 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6147 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6149 [(set_attr "type" "fpmuldbl")
6150 (set_attr "length" "8")])
6153 [(set (match_operand:SF 0 "register_operand" "")
6154 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6155 (match_operand:SF 2 "register_operand" "")))
6156 (match_operand:SF 3 "register_operand" "")))
6157 (set (match_operand:SF 4 "register_operand" "")
6158 (mult:SF (match_dup 1) (match_dup 2)))]
6159 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6160 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6161 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6166 [(set (match_operand:DF 0 "register_operand" "=f")
6167 (minus:DF (match_operand:DF 3 "register_operand" "f")
6168 (mult:DF (match_operand:DF 1 "register_operand" "f")
6169 (match_operand:DF 2 "register_operand" "f"))))
6170 (set (match_operand:DF 4 "register_operand" "=&f")
6171 (mult:DF (match_dup 1) (match_dup 2)))]
6172 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6173 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6174 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6176 [(set_attr "type" "fpmuldbl")
6177 (set_attr "length" "8")])
6180 [(set (match_operand:DF 0 "register_operand" "")
6181 (minus:DF (match_operand:DF 3 "register_operand" "")
6182 (mult:DF (match_operand:DF 1 "register_operand" "")
6183 (match_operand:DF 2 "register_operand" ""))))
6184 (set (match_operand:DF 4 "register_operand" "")
6185 (mult:DF (match_dup 1) (match_dup 2)))]
6186 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6187 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6188 (set (match_dup 0) (minus:DF (match_dup 3)
6189 (mult:DF (match_dup 1) (match_dup 2))))]
6193 [(set (match_operand:SF 0 "register_operand" "=f")
6194 (minus:SF (match_operand:SF 3 "register_operand" "f")
6195 (mult:SF (match_operand:SF 1 "register_operand" "f")
6196 (match_operand:SF 2 "register_operand" "f"))))
6197 (set (match_operand:SF 4 "register_operand" "=&f")
6198 (mult:SF (match_dup 1) (match_dup 2)))]
6199 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6200 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6201 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6203 [(set_attr "type" "fpmuldbl")
6204 (set_attr "length" "8")])
6207 [(set (match_operand:SF 0 "register_operand" "")
6208 (minus:SF (match_operand:SF 3 "register_operand" "")
6209 (mult:SF (match_operand:SF 1 "register_operand" "")
6210 (match_operand:SF 2 "register_operand" ""))))
6211 (set (match_operand:SF 4 "register_operand" "")
6212 (mult:SF (match_dup 1) (match_dup 2)))]
6213 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6214 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6215 (set (match_dup 0) (minus:SF (match_dup 3)
6216 (mult:SF (match_dup 1) (match_dup 2))))]
6220 [(set (match_operand:DF 0 "register_operand" "=f")
6221 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6222 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6223 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6224 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6226 [(set_attr "type" "fpalu")
6227 (set_attr "length" "8")])
6230 [(set (match_operand:DF 0 "register_operand" "")
6231 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6232 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6233 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6234 [(set (match_dup 2) (abs:DF (match_dup 1)))
6235 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6239 [(set (match_operand:SF 0 "register_operand" "=f")
6240 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6241 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6242 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6243 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6245 [(set_attr "type" "fpalu")
6246 (set_attr "length" "8")])
6249 [(set (match_operand:SF 0 "register_operand" "")
6250 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6251 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6252 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6253 [(set (match_dup 2) (abs:SF (match_dup 1)))
6254 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6257 ;;- Shift instructions
6259 ;; Optimized special case of shifting.
6262 [(set (match_operand:SI 0 "register_operand" "=r")
6263 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6267 [(set_attr "type" "load")
6268 (set_attr "length" "4")])
6271 [(set (match_operand:SI 0 "register_operand" "=r")
6272 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6276 [(set_attr "type" "load")
6277 (set_attr "length" "4")])
6280 [(set (match_operand:SI 0 "register_operand" "=r")
6281 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6282 (match_operand:SI 3 "shadd_operand" ""))
6283 (match_operand:SI 1 "register_operand" "r")))]
6285 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6286 [(set_attr "type" "binary")
6287 (set_attr "length" "4")])
6290 [(set (match_operand:DI 0 "register_operand" "=r")
6291 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6292 (match_operand:DI 3 "shadd_operand" ""))
6293 (match_operand:DI 1 "register_operand" "r")))]
6295 "shladd,l %2,%O3,%1,%0"
6296 [(set_attr "type" "binary")
6297 (set_attr "length" "4")])
6299 (define_expand "ashlsi3"
6300 [(set (match_operand:SI 0 "register_operand" "")
6301 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6302 (match_operand:SI 2 "arith32_operand" "")))]
6306 if (GET_CODE (operands[2]) != CONST_INT)
6308 rtx temp = gen_reg_rtx (SImode);
6309 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6310 if (GET_CODE (operands[1]) == CONST_INT)
6311 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6313 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6316 /* Make sure both inputs are not constants,
6317 there are no patterns for that. */
6318 operands[1] = force_reg (SImode, operands[1]);
6322 [(set (match_operand:SI 0 "register_operand" "=r")
6323 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6324 (match_operand:SI 2 "const_int_operand" "n")))]
6326 "{zdep|depw,z} %1,%P2,%L2,%0"
6327 [(set_attr "type" "shift")
6328 (set_attr "length" "4")])
6330 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6331 ; Doing it like this makes slightly better code since reload can
6332 ; replace a register with a known value in range -16..15 with a
6333 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6334 ; but since we have no more CONST_OK... characters, that is not
6336 (define_insn "zvdep32"
6337 [(set (match_operand:SI 0 "register_operand" "=r,r")
6338 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6339 (minus:SI (const_int 31)
6340 (match_operand:SI 2 "register_operand" "q,q"))))]
6343 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6344 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6345 [(set_attr "type" "shift,shift")
6346 (set_attr "length" "4,4")])
6348 (define_insn "zvdep_imm32"
6349 [(set (match_operand:SI 0 "register_operand" "=r")
6350 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6351 (minus:SI (const_int 31)
6352 (match_operand:SI 2 "register_operand" "q"))))]
6356 int x = INTVAL (operands[1]);
6357 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6358 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6359 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6361 [(set_attr "type" "shift")
6362 (set_attr "length" "4")])
6364 (define_insn "vdepi_ior"
6365 [(set (match_operand:SI 0 "register_operand" "=r")
6366 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6367 (minus:SI (const_int 31)
6368 (match_operand:SI 2 "register_operand" "q")))
6369 (match_operand:SI 3 "register_operand" "0")))]
6370 ; accept ...0001...1, can this be generalized?
6371 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6374 int x = INTVAL (operands[1]);
6375 operands[2] = GEN_INT (exact_log2 (x + 1));
6376 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6378 [(set_attr "type" "shift")
6379 (set_attr "length" "4")])
6381 (define_insn "vdepi_and"
6382 [(set (match_operand:SI 0 "register_operand" "=r")
6383 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6384 (minus:SI (const_int 31)
6385 (match_operand:SI 2 "register_operand" "q")))
6386 (match_operand:SI 3 "register_operand" "0")))]
6387 ; this can be generalized...!
6388 "INTVAL (operands[1]) == -2"
6391 int x = INTVAL (operands[1]);
6392 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6393 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6395 [(set_attr "type" "shift")
6396 (set_attr "length" "4")])
6398 (define_expand "ashldi3"
6399 [(set (match_operand:DI 0 "register_operand" "")
6400 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6401 (match_operand:DI 2 "arith32_operand" "")))]
6405 if (GET_CODE (operands[2]) != CONST_INT)
6407 rtx temp = gen_reg_rtx (DImode);
6408 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6409 if (GET_CODE (operands[1]) == CONST_INT)
6410 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6412 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6415 /* Make sure both inputs are not constants,
6416 there are no patterns for that. */
6417 operands[1] = force_reg (DImode, operands[1]);
6421 [(set (match_operand:DI 0 "register_operand" "=r")
6422 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6423 (match_operand:DI 2 "const_int_operand" "n")))]
6425 "depd,z %1,%p2,%Q2,%0"
6426 [(set_attr "type" "shift")
6427 (set_attr "length" "4")])
6429 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6430 ; Doing it like this makes slightly better code since reload can
6431 ; replace a register with a known value in range -16..15 with a
6432 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6433 ; but since we have no more CONST_OK... characters, that is not
6435 (define_insn "zvdep64"
6436 [(set (match_operand:DI 0 "register_operand" "=r,r")
6437 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6438 (minus:DI (const_int 63)
6439 (match_operand:DI 2 "register_operand" "q,q"))))]
6442 depd,z %1,%%sar,64,%0
6443 depdi,z %1,%%sar,64,%0"
6444 [(set_attr "type" "shift,shift")
6445 (set_attr "length" "4,4")])
6447 (define_insn "zvdep_imm64"
6448 [(set (match_operand:DI 0 "register_operand" "=r")
6449 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6450 (minus:DI (const_int 63)
6451 (match_operand:DI 2 "register_operand" "q"))))]
6455 int x = INTVAL (operands[1]);
6456 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6457 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6458 return \"depdi,z %1,%%sar,%2,%0\";
6460 [(set_attr "type" "shift")
6461 (set_attr "length" "4")])
6464 [(set (match_operand:DI 0 "register_operand" "=r")
6465 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6466 (minus:DI (const_int 63)
6467 (match_operand:DI 2 "register_operand" "q")))
6468 (match_operand:DI 3 "register_operand" "0")))]
6469 ; accept ...0001...1, can this be generalized?
6470 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6473 int x = INTVAL (operands[1]);
6474 operands[2] = GEN_INT (exact_log2 (x + 1));
6475 return \"depdi -1,%%sar,%2,%0\";
6477 [(set_attr "type" "shift")
6478 (set_attr "length" "4")])
6481 [(set (match_operand:DI 0 "register_operand" "=r")
6482 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6483 (minus:DI (const_int 63)
6484 (match_operand:DI 2 "register_operand" "q")))
6485 (match_operand:DI 3 "register_operand" "0")))]
6486 ; this can be generalized...!
6487 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6490 int x = INTVAL (operands[1]);
6491 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6492 return \"depdi 0,%%sar,%2,%0\";
6494 [(set_attr "type" "shift")
6495 (set_attr "length" "4")])
6497 (define_expand "ashrsi3"
6498 [(set (match_operand:SI 0 "register_operand" "")
6499 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6500 (match_operand:SI 2 "arith32_operand" "")))]
6504 if (GET_CODE (operands[2]) != CONST_INT)
6506 rtx temp = gen_reg_rtx (SImode);
6507 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6508 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6514 [(set (match_operand:SI 0 "register_operand" "=r")
6515 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6516 (match_operand:SI 2 "const_int_operand" "n")))]
6518 "{extrs|extrw,s} %1,%P2,%L2,%0"
6519 [(set_attr "type" "shift")
6520 (set_attr "length" "4")])
6522 (define_insn "vextrs32"
6523 [(set (match_operand:SI 0 "register_operand" "=r")
6524 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6525 (minus:SI (const_int 31)
6526 (match_operand:SI 2 "register_operand" "q"))))]
6528 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6529 [(set_attr "type" "shift")
6530 (set_attr "length" "4")])
6532 (define_expand "ashrdi3"
6533 [(set (match_operand:DI 0 "register_operand" "")
6534 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6535 (match_operand:DI 2 "arith32_operand" "")))]
6539 if (GET_CODE (operands[2]) != CONST_INT)
6541 rtx temp = gen_reg_rtx (DImode);
6542 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6543 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6549 [(set (match_operand:DI 0 "register_operand" "=r")
6550 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6551 (match_operand:DI 2 "const_int_operand" "n")))]
6553 "extrd,s %1,%p2,%Q2,%0"
6554 [(set_attr "type" "shift")
6555 (set_attr "length" "4")])
6557 (define_insn "vextrs64"
6558 [(set (match_operand:DI 0 "register_operand" "=r")
6559 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6560 (minus:DI (const_int 63)
6561 (match_operand:DI 2 "register_operand" "q"))))]
6563 "extrd,s %1,%%sar,64,%0"
6564 [(set_attr "type" "shift")
6565 (set_attr "length" "4")])
6567 (define_insn "lshrsi3"
6568 [(set (match_operand:SI 0 "register_operand" "=r,r")
6569 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6570 (match_operand:SI 2 "arith32_operand" "q,n")))]
6573 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6574 {extru|extrw,u} %1,%P2,%L2,%0"
6575 [(set_attr "type" "shift")
6576 (set_attr "length" "4")])
6578 (define_insn "lshrdi3"
6579 [(set (match_operand:DI 0 "register_operand" "=r,r")
6580 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6581 (match_operand:DI 2 "arith32_operand" "q,n")))]
6584 shrpd %%r0,%1,%%sar,%0
6585 extrd,u %1,%p2,%Q2,%0"
6586 [(set_attr "type" "shift")
6587 (set_attr "length" "4")])
6589 (define_insn "rotrsi3"
6590 [(set (match_operand:SI 0 "register_operand" "=r,r")
6591 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6592 (match_operand:SI 2 "arith32_operand" "q,n")))]
6596 if (GET_CODE (operands[2]) == CONST_INT)
6598 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6599 return \"{shd|shrpw} %1,%1,%2,%0\";
6602 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6604 [(set_attr "type" "shift")
6605 (set_attr "length" "4")])
6607 (define_expand "rotlsi3"
6608 [(set (match_operand:SI 0 "register_operand" "")
6609 (rotate:SI (match_operand:SI 1 "register_operand" "")
6610 (match_operand:SI 2 "arith32_operand" "")))]
6614 if (GET_CODE (operands[2]) != CONST_INT)
6616 rtx temp = gen_reg_rtx (SImode);
6617 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6618 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6621 /* Else expand normally. */
6625 [(set (match_operand:SI 0 "register_operand" "=r")
6626 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6627 (match_operand:SI 2 "const_int_operand" "n")))]
6631 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6632 return \"{shd|shrpw} %1,%1,%2,%0\";
6634 [(set_attr "type" "shift")
6635 (set_attr "length" "4")])
6638 [(set (match_operand:SI 0 "register_operand" "=r")
6639 (match_operator:SI 5 "plus_xor_ior_operator"
6640 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6641 (match_operand:SI 3 "const_int_operand" "n"))
6642 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6643 (match_operand:SI 4 "const_int_operand" "n"))]))]
6644 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6645 "{shd|shrpw} %1,%2,%4,%0"
6646 [(set_attr "type" "shift")
6647 (set_attr "length" "4")])
6650 [(set (match_operand:SI 0 "register_operand" "=r")
6651 (match_operator:SI 5 "plus_xor_ior_operator"
6652 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6653 (match_operand:SI 4 "const_int_operand" "n"))
6654 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6655 (match_operand:SI 3 "const_int_operand" "n"))]))]
6656 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6657 "{shd|shrpw} %1,%2,%4,%0"
6658 [(set_attr "type" "shift")
6659 (set_attr "length" "4")])
6662 [(set (match_operand:SI 0 "register_operand" "=r")
6663 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6664 (match_operand:SI 2 "const_int_operand" ""))
6665 (match_operand:SI 3 "const_int_operand" "")))]
6666 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6669 int cnt = INTVAL (operands[2]) & 31;
6670 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6671 operands[2] = GEN_INT (31 - cnt);
6672 return \"{zdep|depw,z} %1,%2,%3,%0\";
6674 [(set_attr "type" "shift")
6675 (set_attr "length" "4")])
6677 ;; Unconditional and other jump instructions.
6679 ;; This can only be used in a leaf function, so we do
6680 ;; not need to use the PIC register when generating PIC code.
6681 (define_insn "return"
6685 "hppa_can_use_return_insn_p ()"
6689 return \"bve%* (%%r2)\";
6690 return \"bv%* %%r0(%%r2)\";
6692 [(set_attr "type" "branch")
6693 (set_attr "length" "4")])
6695 ;; Emit a different pattern for functions which have non-trivial
6696 ;; epilogues so as not to confuse jump and reorg.
6697 (define_insn "return_internal"
6705 return \"bve%* (%%r2)\";
6706 return \"bv%* %%r0(%%r2)\";
6708 [(set_attr "type" "branch")
6709 (set_attr "length" "4")])
6711 ;; This is used for eh returns which bypass the return stub.
6712 (define_insn "return_external_pic"
6714 (clobber (reg:SI 1))
6716 "!TARGET_NO_SPACE_REGS
6718 && flag_pic && current_function_calls_eh_return"
6719 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6720 [(set_attr "type" "branch")
6721 (set_attr "length" "12")])
6723 (define_expand "prologue"
6726 "hppa_expand_prologue ();DONE;")
6728 (define_expand "sibcall_epilogue"
6733 hppa_expand_epilogue ();
6737 (define_expand "epilogue"
6742 /* Try to use the trivial return first. Else use the full
6744 if (hppa_can_use_return_insn_p ())
6745 emit_jump_insn (gen_return ());
6750 hppa_expand_epilogue ();
6752 /* EH returns bypass the normal return stub. Thus, we must do an
6753 interspace branch to return from functions that call eh_return.
6754 This is only a problem for returns from shared code on ports
6755 using space registers. */
6756 if (!TARGET_NO_SPACE_REGS
6758 && flag_pic && current_function_calls_eh_return)
6759 x = gen_return_external_pic ();
6761 x = gen_return_internal ();
6768 ; Used by hppa_profile_hook to load the starting address of the current
6769 ; function; operand 1 contains the address of the label in operand 3
6770 (define_insn "load_offset_label_address"
6771 [(set (match_operand:SI 0 "register_operand" "=r")
6772 (plus:SI (match_operand:SI 1 "register_operand" "r")
6773 (minus:SI (match_operand:SI 2 "" "")
6774 (label_ref:SI (match_operand 3 "" "")))))]
6777 [(set_attr "type" "multi")
6778 (set_attr "length" "4")])
6780 ; Output a code label and load its address.
6781 (define_insn "lcla1"
6782 [(set (match_operand:SI 0 "register_operand" "=r")
6783 (label_ref:SI (match_operand 1 "" "")))
6788 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6789 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6790 CODE_LABEL_NUMBER (operands[1]));
6793 [(set_attr "type" "multi")
6794 (set_attr "length" "8")])
6796 (define_insn "lcla2"
6797 [(set (match_operand:SI 0 "register_operand" "=r")
6798 (label_ref:SI (match_operand 1 "" "")))
6803 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6804 CODE_LABEL_NUMBER (operands[1]));
6807 [(set_attr "type" "move")
6808 (set_attr "length" "4")])
6810 (define_insn "blockage"
6811 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6814 [(set_attr "length" "0")])
6817 [(set (pc) (label_ref (match_operand 0 "" "")))]
6821 /* An unconditional branch which can reach its target. */
6822 if (get_attr_length (insn) != 24
6823 && get_attr_length (insn) != 16)
6826 return output_lbranch (operands[0], insn);
6828 [(set_attr "type" "uncond_branch")
6829 (set_attr "pa_combine_type" "uncond_branch")
6830 (set (attr "length")
6831 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6832 (if_then_else (lt (abs (minus (match_dup 0)
6833 (plus (pc) (const_int 8))))
6837 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6839 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6844 ;;; Hope this is only within a function...
6845 (define_insn "indirect_jump"
6846 [(set (pc) (match_operand 0 "register_operand" "r"))]
6847 "GET_MODE (operands[0]) == word_mode"
6849 [(set_attr "type" "branch")
6850 (set_attr "length" "4")])
6852 ;;; An indirect jump can be optimized to a direct jump. GAS for the
6853 ;;; SOM target doesn't allow branching to a label inside a function.
6854 ;;; We also don't correctly compute branch distances for labels
6855 ;;; outside the current function. Thus, we use an indirect jump can't
6856 ;;; be optimized to a direct jump for all targets. We assume that
6857 ;;; the branch target is in the same space (i.e., nested function
6858 ;;; jumping to a label in an outer function in the same translation
6860 (define_expand "nonlocal_goto"
6861 [(use (match_operand 0 "general_operand" ""))
6862 (use (match_operand 1 "general_operand" ""))
6863 (use (match_operand 2 "general_operand" ""))
6864 (use (match_operand 3 "general_operand" ""))]
6867 rtx lab = operands[1];
6868 rtx stack = operands[2];
6869 rtx fp = operands[3];
6871 lab = copy_to_reg (lab);
6873 emit_insn (gen_rtx_CLOBBER (VOIDmode,
6874 gen_rtx_MEM (BLKmode,
6875 gen_rtx_SCRATCH (VOIDmode))));
6876 emit_insn (gen_rtx_CLOBBER (VOIDmode,
6877 gen_rtx_MEM (BLKmode,
6878 hard_frame_pointer_rtx)));
6880 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
6881 instead of the hard_frame_pointer_rtx in the save area. As a
6882 result, an extra instruction is needed to adjust for the offset
6883 of the virtual stack variables and the frame pointer. */
6884 if (GET_CODE (fp) != REG)
6885 fp = force_reg (Pmode, fp);
6886 emit_move_insn (virtual_stack_vars_rtx, fp);
6888 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6890 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6891 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6893 /* Nonlocal goto jumps are only used between functions in the same
6894 translation unit. Thus, we can avoid the extra overhead of an
6896 emit_jump_insn (gen_indirect_goto (lab));
6901 (define_insn "indirect_goto"
6902 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
6903 "GET_MODE (operands[0]) == word_mode"
6905 [(set_attr "type" "branch")
6906 (set_attr "length" "4")])
6908 ;;; This jump is used in branch tables where the insn length is fixed.
6909 ;;; The length of this insn is adjusted if the delay slot is not filled.
6910 (define_insn "short_jump"
6911 [(set (pc) (label_ref (match_operand 0 "" "")))
6915 [(set_attr "type" "btable_branch")
6916 (set_attr "length" "4")])
6918 ;; Subroutines of "casesi".
6919 ;; operand 0 is index
6920 ;; operand 1 is the minimum bound
6921 ;; operand 2 is the maximum bound - minimum bound + 1
6922 ;; operand 3 is CODE_LABEL for the table;
6923 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6925 (define_expand "casesi"
6926 [(match_operand:SI 0 "general_operand" "")
6927 (match_operand:SI 1 "const_int_operand" "")
6928 (match_operand:SI 2 "const_int_operand" "")
6929 (match_operand 3 "" "")
6930 (match_operand 4 "" "")]
6934 if (GET_CODE (operands[0]) != REG)
6935 operands[0] = force_reg (SImode, operands[0]);
6937 if (operands[1] != const0_rtx)
6939 rtx index = gen_reg_rtx (SImode);
6941 operands[1] = GEN_INT (-INTVAL (operands[1]));
6942 if (!INT_14_BITS (operands[1]))
6943 operands[1] = force_reg (SImode, operands[1]);
6944 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6945 operands[0] = index;
6948 /* In 64bit mode we must make sure to wipe the upper bits of the register
6949 just in case the addition overflowed or we had random bits in the
6950 high part of the register. */
6953 rtx index = gen_reg_rtx (DImode);
6955 emit_insn (gen_extendsidi2 (index, operands[0]));
6956 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6959 if (!INT_5_BITS (operands[2]))
6960 operands[2] = force_reg (SImode, operands[2]);
6962 /* This branch prevents us finding an insn for the delay slot of the
6963 following vectored branch. It might be possible to use the delay
6964 slot if an index value of -1 was used to transfer to the out-of-range
6965 label. In order to do this, we would have to output the -1 vector
6966 element after the delay insn. The casesi output code would have to
6967 check if the casesi insn is in a delay branch sequence and output
6968 the delay insn if one is found. If this was done, then it might
6969 then be worthwhile to split the casesi patterns to improve scheduling.
6970 However, it's not clear that all this extra complexity is worth
6972 emit_insn (gen_cmpsi (operands[0], operands[2]));
6973 emit_jump_insn (gen_bgtu (operands[4]));
6975 if (TARGET_BIG_SWITCH)
6979 rtx tmp1 = gen_reg_rtx (DImode);
6980 rtx tmp2 = gen_reg_rtx (DImode);
6982 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6987 rtx tmp1 = gen_reg_rtx (SImode);
6991 rtx tmp2 = gen_reg_rtx (SImode);
6993 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6997 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
7001 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7005 ;;; The rtl for this pattern doesn't accurately describe what the insn
7006 ;;; actually does, particularly when case-vector elements are exploded
7007 ;;; in pa_reorg. However, the initial SET in these patterns must show
7008 ;;; the connection of the insn to the following jump table.
7009 (define_insn "casesi0"
7010 [(set (pc) (mem:SI (plus:SI
7011 (mult:SI (match_operand:SI 0 "register_operand" "r")
7013 (label_ref (match_operand 1 "" "")))))]
7015 "blr,n %0,%%r0\;nop"
7016 [(set_attr "type" "multi")
7017 (set_attr "length" "8")])
7019 ;;; 32-bit code, absolute branch table.
7020 (define_insn "casesi32"
7021 [(set (pc) (mem:SI (plus:SI
7022 (mult:SI (match_operand:SI 0 "register_operand" "r")
7024 (label_ref (match_operand 1 "" "")))))
7025 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
7026 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7027 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7028 [(set_attr "type" "multi")
7029 (set_attr "length" "16")])
7031 ;;; 32-bit code, relative branch table.
7032 (define_insn "casesi32p"
7033 [(set (pc) (mem:SI (plus:SI
7034 (mult:SI (match_operand:SI 0 "register_operand" "r")
7036 (label_ref (match_operand 1 "" "")))))
7037 (clobber (match_operand:SI 2 "register_operand" "=&a"))
7038 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
7039 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7040 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7041 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7042 [(set_attr "type" "multi")
7043 (set (attr "length")
7044 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7048 ;;; 64-bit code, 32-bit relative branch table.
7049 (define_insn "casesi64p"
7050 [(set (pc) (mem:DI (plus:DI
7051 (mult:DI (sign_extend:DI
7052 (match_operand:SI 0 "register_operand" "r"))
7054 (label_ref (match_operand 1 "" "")))))
7055 (clobber (match_operand:DI 2 "register_operand" "=&r"))
7056 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
7057 "TARGET_64BIT && TARGET_BIG_SWITCH"
7058 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7059 add,l %2,%3,%3\;bv,n %%r0(%3)"
7060 [(set_attr "type" "multi")
7061 (set_attr "length" "24")])
7065 ;;- jump to subroutine
7067 (define_expand "call"
7068 [(parallel [(call (match_operand:SI 0 "" "")
7069 (match_operand 1 "" ""))
7070 (clobber (reg:SI 2))])]
7075 rtx nb = operands[1];
7077 if (TARGET_PORTABLE_RUNTIME)
7078 op = force_reg (SImode, XEXP (operands[0], 0));
7080 op = XEXP (operands[0], 0);
7084 if (!virtuals_instantiated)
7085 emit_move_insn (arg_pointer_rtx,
7086 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7090 /* The loop pass can generate new libcalls after the virtual
7091 registers are instantiated when fpregs are disabled because
7092 the only method that we have for doing DImode multiplication
7093 is with a libcall. This could be trouble if we haven't
7094 allocated enough space for the outgoing arguments. */
7095 if (INTVAL (nb) > current_function_outgoing_args_size)
7098 emit_move_insn (arg_pointer_rtx,
7099 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7100 GEN_INT (STACK_POINTER_OFFSET + 64)));
7104 /* Use two different patterns for calls to explicitly named functions
7105 and calls through function pointers. This is necessary as these two
7106 types of calls use different calling conventions, and CSE might try
7107 to change the named call into an indirect call in some cases (using
7108 two patterns keeps CSE from performing this optimization).
7110 We now use even more call patterns as there was a subtle bug in
7111 attempting to restore the pic register after a call using a simple
7112 move insn. During reload, a instruction involving a pseudo register
7113 with no explicit dependence on the PIC register can be converted
7114 to an equivalent load from memory using the PIC register. If we
7115 emit a simple move to restore the PIC register in the initial rtl
7116 generation, then it can potentially be repositioned during scheduling.
7117 and an instruction that eventually uses the PIC register may end up
7118 between the call and the PIC register restore.
7120 This only worked because there is a post call group of instructions
7121 that are scheduled with the call. These instructions are included
7122 in the same basic block as the call. However, calls can throw in
7123 C++ code and a basic block has to terminate at the call if the call
7124 can throw. This results in the PIC register restore being scheduled
7125 independently from the call. So, we now hide the save and restore
7126 of the PIC register in the call pattern until after reload. Then,
7127 we split the moves out. A small side benefit is that we now don't
7128 need to have a use of the PIC register in the return pattern and
7129 the final save/restore operation is not needed.
7131 I elected to just clobber %r4 in the PIC patterns and use it instead
7132 of trying to force hppa_pic_save_rtx () to a callee saved register.
7133 This might have required a new register class and constraint. It
7134 was also simpler to just handle the restore from a register than a
7138 if (GET_CODE (op) == SYMBOL_REF)
7139 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7142 op = force_reg (word_mode, op);
7143 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7148 if (GET_CODE (op) == SYMBOL_REF)
7151 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7153 call_insn = emit_call_insn (gen_call_symref (op, nb));
7157 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7159 emit_move_insn (tmpreg, force_reg (word_mode, op));
7161 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7163 call_insn = emit_call_insn (gen_call_reg (nb));
7170 ;; We use function calls to set the attribute length of calls and millicode
7171 ;; calls. This is necessary because of the large variety of call sequences.
7172 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7173 ;; we need the same calculation in several places, maintenance becomes a
7176 ;; However, this has a subtle impact on branch shortening. When the
7177 ;; expression used to set the length attribute of an instruction depends
7178 ;; on a relative address (e.g., pc or a branch address), genattrtab
7179 ;; notes that the insn's length is variable, and attempts to determine a
7180 ;; worst-case default length and code to compute an insn's current length.
7182 ;; The use of a function call hides the variable dependence of our calls
7183 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7184 ;; as variable and it only generates code for the default case using our
7185 ;; function call. Because of this, calls and millicode calls have a fixed
7186 ;; length in the branch shortening pass, and some branches will use a longer
7187 ;; code sequence than necessary. However, the length of any given call
7188 ;; will still reflect its final code location and it may be shorter than
7189 ;; the initial length estimate.
7191 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7192 ;; in the set. However, when genattrtab hits a function call in its attempt
7193 ;; to compute the default length, it marks the result as unknown and sets
7194 ;; the default result to MAX_INT ;-( One possible fix that would allow
7195 ;; calls to participate in branch shortening would be to make the call to
7196 ;; insn_default_length a target option. Then, we could massage unknown
7197 ;; results. Another fix might be to change genattrtab so that it just does
7198 ;; the call in the variable case as it already does for the fixed case.
7200 (define_insn "call_symref"
7201 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7202 (match_operand 1 "" "i"))
7203 (clobber (reg:SI 1))
7204 (clobber (reg:SI 2))
7205 (use (const_int 0))]
7206 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7209 output_arg_descriptor (insn);
7210 return output_call (insn, operands[0], 0);
7212 [(set_attr "type" "call")
7213 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7215 (define_insn "call_symref_pic"
7216 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7217 (match_operand 1 "" "i"))
7218 (clobber (reg:SI 1))
7219 (clobber (reg:SI 2))
7220 (clobber (reg:SI 4))
7222 (use (const_int 0))]
7223 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7226 output_arg_descriptor (insn);
7227 return output_call (insn, operands[0], 0);
7229 [(set_attr "type" "call")
7230 (set (attr "length")
7231 (plus (symbol_ref "attr_length_call (insn, 0)")
7232 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7234 ;; Split out the PIC register save and restore after reload. This is
7235 ;; done only if the function returns. As the split is done after reload,
7236 ;; there are some situations in which we unnecessarily save and restore
7237 ;; %r4. This happens when there is a single call and the PIC register
7238 ;; is "dead" after the call. This isn't easy to fix as the usage of
7239 ;; the PIC register isn't completely determined until the reload pass.
7241 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7242 (match_operand 1 "" ""))
7243 (clobber (reg:SI 1))
7244 (clobber (reg:SI 2))
7245 (clobber (reg:SI 4))
7247 (use (const_int 0))])]
7248 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7250 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7251 [(set (reg:SI 4) (reg:SI 19))
7252 (parallel [(call (mem:SI (match_dup 0))
7254 (clobber (reg:SI 1))
7255 (clobber (reg:SI 2))
7257 (use (const_int 0))])
7258 (set (reg:SI 19) (reg:SI 4))]
7261 ;; Remove the clobber of register 4 when optimizing. This has to be
7262 ;; done with a peephole optimization rather than a split because the
7263 ;; split sequence for a call must be longer than one instruction.
7265 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7266 (match_operand 1 "" ""))
7267 (clobber (reg:SI 1))
7268 (clobber (reg:SI 2))
7269 (clobber (reg:SI 4))
7271 (use (const_int 0))])]
7272 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7273 [(parallel [(call (mem:SI (match_dup 0))
7275 (clobber (reg:SI 1))
7276 (clobber (reg:SI 2))
7278 (use (const_int 0))])]
7281 (define_insn "*call_symref_pic_post_reload"
7282 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7283 (match_operand 1 "" "i"))
7284 (clobber (reg:SI 1))
7285 (clobber (reg:SI 2))
7287 (use (const_int 0))]
7288 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7291 output_arg_descriptor (insn);
7292 return output_call (insn, operands[0], 0);
7294 [(set_attr "type" "call")
7295 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7297 ;; This pattern is split if it is necessary to save and restore the
7299 (define_insn "call_symref_64bit"
7300 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7301 (match_operand 1 "" "i"))
7302 (clobber (reg:DI 1))
7303 (clobber (reg:DI 2))
7304 (clobber (reg:DI 4))
7307 (use (const_int 0))]
7311 output_arg_descriptor (insn);
7312 return output_call (insn, operands[0], 0);
7314 [(set_attr "type" "call")
7315 (set (attr "length")
7316 (plus (symbol_ref "attr_length_call (insn, 0)")
7317 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7319 ;; Split out the PIC register save and restore after reload. This is
7320 ;; done only if the function returns. As the split is done after reload,
7321 ;; there are some situations in which we unnecessarily save and restore
7322 ;; %r4. This happens when there is a single call and the PIC register
7323 ;; is "dead" after the call. This isn't easy to fix as the usage of
7324 ;; the PIC register isn't completely determined until the reload pass.
7326 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7327 (match_operand 1 "" ""))
7328 (clobber (reg:DI 1))
7329 (clobber (reg:DI 2))
7330 (clobber (reg:DI 4))
7333 (use (const_int 0))])]
7336 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7337 [(set (reg:DI 4) (reg:DI 27))
7338 (parallel [(call (mem:SI (match_dup 0))
7340 (clobber (reg:DI 1))
7341 (clobber (reg:DI 2))
7344 (use (const_int 0))])
7345 (set (reg:DI 27) (reg:DI 4))]
7348 ;; Remove the clobber of register 4 when optimizing. This has to be
7349 ;; done with a peephole optimization rather than a split because the
7350 ;; split sequence for a call must be longer than one instruction.
7352 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7353 (match_operand 1 "" ""))
7354 (clobber (reg:DI 1))
7355 (clobber (reg:DI 2))
7356 (clobber (reg:DI 4))
7359 (use (const_int 0))])]
7360 "TARGET_64BIT && reload_completed"
7361 [(parallel [(call (mem:SI (match_dup 0))
7363 (clobber (reg:DI 1))
7364 (clobber (reg:DI 2))
7367 (use (const_int 0))])]
7370 (define_insn "*call_symref_64bit_post_reload"
7371 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7372 (match_operand 1 "" "i"))
7373 (clobber (reg:DI 1))
7374 (clobber (reg:DI 2))
7377 (use (const_int 0))]
7381 output_arg_descriptor (insn);
7382 return output_call (insn, operands[0], 0);
7384 [(set_attr "type" "call")
7385 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7387 (define_insn "call_reg"
7388 [(call (mem:SI (reg:SI 22))
7389 (match_operand 0 "" "i"))
7390 (clobber (reg:SI 1))
7391 (clobber (reg:SI 2))
7392 (use (const_int 1))]
7396 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7398 [(set_attr "type" "dyncall")
7399 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7401 ;; This pattern is split if it is necessary to save and restore the
7403 (define_insn "call_reg_pic"
7404 [(call (mem:SI (reg:SI 22))
7405 (match_operand 0 "" "i"))
7406 (clobber (reg:SI 1))
7407 (clobber (reg:SI 2))
7408 (clobber (reg:SI 4))
7410 (use (const_int 1))]
7414 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7416 [(set_attr "type" "dyncall")
7417 (set (attr "length")
7418 (plus (symbol_ref "attr_length_indirect_call (insn)")
7419 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7421 ;; Split out the PIC register save and restore after reload. This is
7422 ;; done only if the function returns. As the split is done after reload,
7423 ;; there are some situations in which we unnecessarily save and restore
7424 ;; %r4. This happens when there is a single call and the PIC register
7425 ;; is "dead" after the call. This isn't easy to fix as the usage of
7426 ;; the PIC register isn't completely determined until the reload pass.
7428 [(parallel [(call (mem:SI (reg:SI 22))
7429 (match_operand 0 "" ""))
7430 (clobber (reg:SI 1))
7431 (clobber (reg:SI 2))
7432 (clobber (reg:SI 4))
7434 (use (const_int 1))])]
7437 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7438 [(set (reg:SI 4) (reg:SI 19))
7439 (parallel [(call (mem:SI (reg:SI 22))
7441 (clobber (reg:SI 1))
7442 (clobber (reg:SI 2))
7444 (use (const_int 1))])
7445 (set (reg:SI 19) (reg:SI 4))]
7448 ;; Remove the clobber of register 4 when optimizing. This has to be
7449 ;; done with a peephole optimization rather than a split because the
7450 ;; split sequence for a call must be longer than one instruction.
7452 [(parallel [(call (mem:SI (reg:SI 22))
7453 (match_operand 0 "" ""))
7454 (clobber (reg:SI 1))
7455 (clobber (reg:SI 2))
7456 (clobber (reg:SI 4))
7458 (use (const_int 1))])]
7459 "!TARGET_64BIT && reload_completed"
7460 [(parallel [(call (mem:SI (reg:SI 22))
7462 (clobber (reg:SI 1))
7463 (clobber (reg:SI 2))
7465 (use (const_int 1))])]
7468 (define_insn "*call_reg_pic_post_reload"
7469 [(call (mem:SI (reg:SI 22))
7470 (match_operand 0 "" "i"))
7471 (clobber (reg:SI 1))
7472 (clobber (reg:SI 2))
7474 (use (const_int 1))]
7478 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7480 [(set_attr "type" "dyncall")
7481 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7483 ;; This pattern is split if it is necessary to save and restore the
7485 (define_insn "call_reg_64bit"
7486 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7487 (match_operand 1 "" "i"))
7488 (clobber (reg:DI 2))
7489 (clobber (reg:DI 4))
7492 (use (const_int 1))]
7496 return output_indirect_call (insn, operands[0]);
7498 [(set_attr "type" "dyncall")
7499 (set (attr "length")
7500 (plus (symbol_ref "attr_length_indirect_call (insn)")
7501 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7503 ;; Split out the PIC register save and restore after reload. This is
7504 ;; done only if the function returns. As the split is done after reload,
7505 ;; there are some situations in which we unnecessarily save and restore
7506 ;; %r4. This happens when there is a single call and the PIC register
7507 ;; is "dead" after the call. This isn't easy to fix as the usage of
7508 ;; the PIC register isn't completely determined until the reload pass.
7510 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7511 (match_operand 1 "" ""))
7512 (clobber (reg:DI 2))
7513 (clobber (reg:DI 4))
7516 (use (const_int 1))])]
7519 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7520 [(set (reg:DI 4) (reg:DI 27))
7521 (parallel [(call (mem:SI (match_dup 0))
7523 (clobber (reg:DI 2))
7526 (use (const_int 1))])
7527 (set (reg:DI 27) (reg:DI 4))]
7530 ;; Remove the clobber of register 4 when optimizing. This has to be
7531 ;; done with a peephole optimization rather than a split because the
7532 ;; split sequence for a call must be longer than one instruction.
7534 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7535 (match_operand 1 "" ""))
7536 (clobber (reg:DI 2))
7537 (clobber (reg:DI 4))
7540 (use (const_int 1))])]
7541 "TARGET_64BIT && reload_completed"
7542 [(parallel [(call (mem:SI (match_dup 0))
7544 (clobber (reg:DI 2))
7547 (use (const_int 1))])]
7550 (define_insn "*call_reg_64bit_post_reload"
7551 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7552 (match_operand 1 "" "i"))
7553 (clobber (reg:DI 2))
7556 (use (const_int 1))]
7560 return output_indirect_call (insn, operands[0]);
7562 [(set_attr "type" "dyncall")
7563 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7565 (define_expand "call_value"
7566 [(parallel [(set (match_operand 0 "" "")
7567 (call (match_operand:SI 1 "" "")
7568 (match_operand 2 "" "")))
7569 (clobber (reg:SI 2))])]
7574 rtx dst = operands[0];
7575 rtx nb = operands[2];
7577 if (TARGET_PORTABLE_RUNTIME)
7578 op = force_reg (SImode, XEXP (operands[1], 0));
7580 op = XEXP (operands[1], 0);
7584 if (!virtuals_instantiated)
7585 emit_move_insn (arg_pointer_rtx,
7586 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7590 /* The loop pass can generate new libcalls after the virtual
7591 registers are instantiated when fpregs are disabled because
7592 the only method that we have for doing DImode multiplication
7593 is with a libcall. This could be trouble if we haven't
7594 allocated enough space for the outgoing arguments. */
7595 if (INTVAL (nb) > current_function_outgoing_args_size)
7598 emit_move_insn (arg_pointer_rtx,
7599 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7600 GEN_INT (STACK_POINTER_OFFSET + 64)));
7604 /* Use two different patterns for calls to explicitly named functions
7605 and calls through function pointers. This is necessary as these two
7606 types of calls use different calling conventions, and CSE might try
7607 to change the named call into an indirect call in some cases (using
7608 two patterns keeps CSE from performing this optimization).
7610 We now use even more call patterns as there was a subtle bug in
7611 attempting to restore the pic register after a call using a simple
7612 move insn. During reload, a instruction involving a pseudo register
7613 with no explicit dependence on the PIC register can be converted
7614 to an equivalent load from memory using the PIC register. If we
7615 emit a simple move to restore the PIC register in the initial rtl
7616 generation, then it can potentially be repositioned during scheduling.
7617 and an instruction that eventually uses the PIC register may end up
7618 between the call and the PIC register restore.
7620 This only worked because there is a post call group of instructions
7621 that are scheduled with the call. These instructions are included
7622 in the same basic block as the call. However, calls can throw in
7623 C++ code and a basic block has to terminate at the call if the call
7624 can throw. This results in the PIC register restore being scheduled
7625 independently from the call. So, we now hide the save and restore
7626 of the PIC register in the call pattern until after reload. Then,
7627 we split the moves out. A small side benefit is that we now don't
7628 need to have a use of the PIC register in the return pattern and
7629 the final save/restore operation is not needed.
7631 I elected to just clobber %r4 in the PIC patterns and use it instead
7632 of trying to force hppa_pic_save_rtx () to a callee saved register.
7633 This might have required a new register class and constraint. It
7634 was also simpler to just handle the restore from a register than a
7638 if (GET_CODE (op) == SYMBOL_REF)
7639 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7642 op = force_reg (word_mode, op);
7643 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7648 if (GET_CODE (op) == SYMBOL_REF)
7651 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7653 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7657 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7659 emit_move_insn (tmpreg, force_reg (word_mode, op));
7661 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7663 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7670 (define_insn "call_val_symref"
7671 [(set (match_operand 0 "" "")
7672 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7673 (match_operand 2 "" "i")))
7674 (clobber (reg:SI 1))
7675 (clobber (reg:SI 2))
7676 (use (const_int 0))]
7677 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7680 output_arg_descriptor (insn);
7681 return output_call (insn, operands[1], 0);
7683 [(set_attr "type" "call")
7684 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7686 (define_insn "call_val_symref_pic"
7687 [(set (match_operand 0 "" "")
7688 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7689 (match_operand 2 "" "i")))
7690 (clobber (reg:SI 1))
7691 (clobber (reg:SI 2))
7692 (clobber (reg:SI 4))
7694 (use (const_int 0))]
7695 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7698 output_arg_descriptor (insn);
7699 return output_call (insn, operands[1], 0);
7701 [(set_attr "type" "call")
7702 (set (attr "length")
7703 (plus (symbol_ref "attr_length_call (insn, 0)")
7704 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7706 ;; Split out the PIC register save and restore after reload. This is
7707 ;; done only if the function returns. As the split is done after reload,
7708 ;; there are some situations in which we unnecessarily save and restore
7709 ;; %r4. This happens when there is a single call and the PIC register
7710 ;; is "dead" after the call. This isn't easy to fix as the usage of
7711 ;; the PIC register isn't completely determined until the reload pass.
7713 [(parallel [(set (match_operand 0 "" "")
7714 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7715 (match_operand 2 "" "")))
7716 (clobber (reg:SI 1))
7717 (clobber (reg:SI 2))
7718 (clobber (reg:SI 4))
7720 (use (const_int 0))])]
7721 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7723 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7724 [(set (reg:SI 4) (reg:SI 19))
7725 (parallel [(set (match_dup 0)
7726 (call (mem:SI (match_dup 1))
7728 (clobber (reg:SI 1))
7729 (clobber (reg:SI 2))
7731 (use (const_int 0))])
7732 (set (reg:SI 19) (reg:SI 4))]
7735 ;; Remove the clobber of register 4 when optimizing. This has to be
7736 ;; done with a peephole optimization rather than a split because the
7737 ;; split sequence for a call must be longer than one instruction.
7739 [(parallel [(set (match_operand 0 "" "")
7740 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7741 (match_operand 2 "" "")))
7742 (clobber (reg:SI 1))
7743 (clobber (reg:SI 2))
7744 (clobber (reg:SI 4))
7746 (use (const_int 0))])]
7747 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7748 [(parallel [(set (match_dup 0)
7749 (call (mem:SI (match_dup 1))
7751 (clobber (reg:SI 1))
7752 (clobber (reg:SI 2))
7754 (use (const_int 0))])]
7757 (define_insn "*call_val_symref_pic_post_reload"
7758 [(set (match_operand 0 "" "")
7759 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7760 (match_operand 2 "" "i")))
7761 (clobber (reg:SI 1))
7762 (clobber (reg:SI 2))
7764 (use (const_int 0))]
7765 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7768 output_arg_descriptor (insn);
7769 return output_call (insn, operands[1], 0);
7771 [(set_attr "type" "call")
7772 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7774 ;; This pattern is split if it is necessary to save and restore the
7776 (define_insn "call_val_symref_64bit"
7777 [(set (match_operand 0 "" "")
7778 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7779 (match_operand 2 "" "i")))
7780 (clobber (reg:DI 1))
7781 (clobber (reg:DI 2))
7782 (clobber (reg:DI 4))
7785 (use (const_int 0))]
7789 output_arg_descriptor (insn);
7790 return output_call (insn, operands[1], 0);
7792 [(set_attr "type" "call")
7793 (set (attr "length")
7794 (plus (symbol_ref "attr_length_call (insn, 0)")
7795 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7797 ;; Split out the PIC register save and restore after reload. This is
7798 ;; done only if the function returns. As the split is done after reload,
7799 ;; there are some situations in which we unnecessarily save and restore
7800 ;; %r4. This happens when there is a single call and the PIC register
7801 ;; is "dead" after the call. This isn't easy to fix as the usage of
7802 ;; the PIC register isn't completely determined until the reload pass.
7804 [(parallel [(set (match_operand 0 "" "")
7805 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7806 (match_operand 2 "" "")))
7807 (clobber (reg:DI 1))
7808 (clobber (reg:DI 2))
7809 (clobber (reg:DI 4))
7812 (use (const_int 0))])]
7815 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7816 [(set (reg:DI 4) (reg:DI 27))
7817 (parallel [(set (match_dup 0)
7818 (call (mem:SI (match_dup 1))
7820 (clobber (reg:DI 1))
7821 (clobber (reg:DI 2))
7824 (use (const_int 0))])
7825 (set (reg:DI 27) (reg:DI 4))]
7828 ;; Remove the clobber of register 4 when optimizing. This has to be
7829 ;; done with a peephole optimization rather than a split because the
7830 ;; split sequence for a call must be longer than one instruction.
7832 [(parallel [(set (match_operand 0 "" "")
7833 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7834 (match_operand 2 "" "")))
7835 (clobber (reg:DI 1))
7836 (clobber (reg:DI 2))
7837 (clobber (reg:DI 4))
7840 (use (const_int 0))])]
7841 "TARGET_64BIT && reload_completed"
7842 [(parallel [(set (match_dup 0)
7843 (call (mem:SI (match_dup 1))
7845 (clobber (reg:DI 1))
7846 (clobber (reg:DI 2))
7849 (use (const_int 0))])]
7852 (define_insn "*call_val_symref_64bit_post_reload"
7853 [(set (match_operand 0 "" "")
7854 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7855 (match_operand 2 "" "i")))
7856 (clobber (reg:DI 1))
7857 (clobber (reg:DI 2))
7860 (use (const_int 0))]
7864 output_arg_descriptor (insn);
7865 return output_call (insn, operands[1], 0);
7867 [(set_attr "type" "call")
7868 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7870 (define_insn "call_val_reg"
7871 [(set (match_operand 0 "" "")
7872 (call (mem:SI (reg:SI 22))
7873 (match_operand 1 "" "i")))
7874 (clobber (reg:SI 1))
7875 (clobber (reg:SI 2))
7876 (use (const_int 1))]
7880 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7882 [(set_attr "type" "dyncall")
7883 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7885 ;; This pattern is split if it is necessary to save and restore the
7887 (define_insn "call_val_reg_pic"
7888 [(set (match_operand 0 "" "")
7889 (call (mem:SI (reg:SI 22))
7890 (match_operand 1 "" "i")))
7891 (clobber (reg:SI 1))
7892 (clobber (reg:SI 2))
7893 (clobber (reg:SI 4))
7895 (use (const_int 1))]
7899 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7901 [(set_attr "type" "dyncall")
7902 (set (attr "length")
7903 (plus (symbol_ref "attr_length_indirect_call (insn)")
7904 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7906 ;; Split out the PIC register save and restore after reload. This is
7907 ;; done only if the function returns. As the split is done after reload,
7908 ;; there are some situations in which we unnecessarily save and restore
7909 ;; %r4. This happens when there is a single call and the PIC register
7910 ;; is "dead" after the call. This isn't easy to fix as the usage of
7911 ;; the PIC register isn't completely determined until the reload pass.
7913 [(parallel [(set (match_operand 0 "" "")
7914 (call (mem:SI (reg:SI 22))
7915 (match_operand 1 "" "")))
7916 (clobber (reg:SI 1))
7917 (clobber (reg:SI 2))
7918 (clobber (reg:SI 4))
7920 (use (const_int 1))])]
7923 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7924 [(set (reg:SI 4) (reg:SI 19))
7925 (parallel [(set (match_dup 0)
7926 (call (mem:SI (reg:SI 22))
7928 (clobber (reg:SI 1))
7929 (clobber (reg:SI 2))
7931 (use (const_int 1))])
7932 (set (reg:SI 19) (reg:SI 4))]
7935 ;; Remove the clobber of register 4 when optimizing. This has to be
7936 ;; done with a peephole optimization rather than a split because the
7937 ;; split sequence for a call must be longer than one instruction.
7939 [(parallel [(set (match_operand 0 "" "")
7940 (call (mem:SI (reg:SI 22))
7941 (match_operand 1 "" "")))
7942 (clobber (reg:SI 1))
7943 (clobber (reg:SI 2))
7944 (clobber (reg:SI 4))
7946 (use (const_int 1))])]
7947 "!TARGET_64BIT && reload_completed"
7948 [(parallel [(set (match_dup 0)
7949 (call (mem:SI (reg:SI 22))
7951 (clobber (reg:SI 1))
7952 (clobber (reg:SI 2))
7954 (use (const_int 1))])]
7957 (define_insn "*call_val_reg_pic_post_reload"
7958 [(set (match_operand 0 "" "")
7959 (call (mem:SI (reg:SI 22))
7960 (match_operand 1 "" "i")))
7961 (clobber (reg:SI 1))
7962 (clobber (reg:SI 2))
7964 (use (const_int 1))]
7968 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7970 [(set_attr "type" "dyncall")
7971 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7973 ;; This pattern is split if it is necessary to save and restore the
7975 (define_insn "call_val_reg_64bit"
7976 [(set (match_operand 0 "" "")
7977 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7978 (match_operand 2 "" "i")))
7979 (clobber (reg:DI 2))
7980 (clobber (reg:DI 4))
7983 (use (const_int 1))]
7987 return output_indirect_call (insn, operands[1]);
7989 [(set_attr "type" "dyncall")
7990 (set (attr "length")
7991 (plus (symbol_ref "attr_length_indirect_call (insn)")
7992 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7994 ;; Split out the PIC register save and restore after reload. This is
7995 ;; done only if the function returns. As the split is done after reload,
7996 ;; there are some situations in which we unnecessarily save and restore
7997 ;; %r4. This happens when there is a single call and the PIC register
7998 ;; is "dead" after the call. This isn't easy to fix as the usage of
7999 ;; the PIC register isn't completely determined until the reload pass.
8001 [(parallel [(set (match_operand 0 "" "")
8002 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8003 (match_operand 2 "" "")))
8004 (clobber (reg:DI 2))
8005 (clobber (reg:DI 4))
8008 (use (const_int 1))])]
8011 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8012 [(set (reg:DI 4) (reg:DI 27))
8013 (parallel [(set (match_dup 0)
8014 (call (mem:SI (match_dup 1))
8016 (clobber (reg:DI 2))
8019 (use (const_int 1))])
8020 (set (reg:DI 27) (reg:DI 4))]
8023 ;; Remove the clobber of register 4 when optimizing. This has to be
8024 ;; done with a peephole optimization rather than a split because the
8025 ;; split sequence for a call must be longer than one instruction.
8027 [(parallel [(set (match_operand 0 "" "")
8028 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8029 (match_operand 2 "" "")))
8030 (clobber (reg:DI 2))
8031 (clobber (reg:DI 4))
8034 (use (const_int 1))])]
8035 "TARGET_64BIT && reload_completed"
8036 [(parallel [(set (match_dup 0)
8037 (call (mem:SI (match_dup 1))
8039 (clobber (reg:DI 2))
8042 (use (const_int 1))])]
8045 (define_insn "*call_val_reg_64bit_post_reload"
8046 [(set (match_operand 0 "" "")
8047 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8048 (match_operand 2 "" "i")))
8049 (clobber (reg:DI 2))
8052 (use (const_int 1))]
8056 return output_indirect_call (insn, operands[1]);
8058 [(set_attr "type" "dyncall")
8059 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8061 ;; Call subroutine returning any type.
8063 (define_expand "untyped_call"
8064 [(parallel [(call (match_operand 0 "" "")
8066 (match_operand 1 "" "")
8067 (match_operand 2 "" "")])]
8073 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8075 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8077 rtx set = XVECEXP (operands[2], 0, i);
8078 emit_move_insn (SET_DEST (set), SET_SRC (set));
8081 /* The optimizer does not know that the call sets the function value
8082 registers we stored in the result block. We avoid problems by
8083 claiming that all hard registers are used and clobbered at this
8085 emit_insn (gen_blockage ());
8090 (define_expand "sibcall"
8091 [(call (match_operand:SI 0 "" "")
8092 (match_operand 1 "" ""))]
8093 "!TARGET_PORTABLE_RUNTIME"
8097 rtx nb = operands[1];
8099 op = XEXP (operands[0], 0);
8103 if (!virtuals_instantiated)
8104 emit_move_insn (arg_pointer_rtx,
8105 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8109 /* The loop pass can generate new libcalls after the virtual
8110 registers are instantiated when fpregs are disabled because
8111 the only method that we have for doing DImode multiplication
8112 is with a libcall. This could be trouble if we haven't
8113 allocated enough space for the outgoing arguments. */
8114 if (INTVAL (nb) > current_function_outgoing_args_size)
8117 emit_move_insn (arg_pointer_rtx,
8118 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8119 GEN_INT (STACK_POINTER_OFFSET + 64)));
8123 /* Indirect sibling calls are not allowed. */
8125 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8127 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8129 call_insn = emit_call_insn (call_insn);
8132 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8134 /* We don't have to restore the PIC register. */
8136 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8141 (define_insn "sibcall_internal_symref"
8142 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8143 (match_operand 1 "" "i"))
8144 (clobber (reg:SI 1))
8146 (use (const_int 0))]
8147 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8150 output_arg_descriptor (insn);
8151 return output_call (insn, operands[0], 1);
8153 [(set_attr "type" "call")
8154 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8156 (define_insn "sibcall_internal_symref_64bit"
8157 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8158 (match_operand 1 "" "i"))
8159 (clobber (reg:DI 1))
8161 (use (const_int 0))]
8165 output_arg_descriptor (insn);
8166 return output_call (insn, operands[0], 1);
8168 [(set_attr "type" "call")
8169 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8171 (define_expand "sibcall_value"
8172 [(set (match_operand 0 "" "")
8173 (call (match_operand:SI 1 "" "")
8174 (match_operand 2 "" "")))]
8175 "!TARGET_PORTABLE_RUNTIME"
8179 rtx nb = operands[1];
8181 op = XEXP (operands[1], 0);
8185 if (!virtuals_instantiated)
8186 emit_move_insn (arg_pointer_rtx,
8187 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8191 /* The loop pass can generate new libcalls after the virtual
8192 registers are instantiated when fpregs are disabled because
8193 the only method that we have for doing DImode multiplication
8194 is with a libcall. This could be trouble if we haven't
8195 allocated enough space for the outgoing arguments. */
8196 if (INTVAL (nb) > current_function_outgoing_args_size)
8199 emit_move_insn (arg_pointer_rtx,
8200 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8201 GEN_INT (STACK_POINTER_OFFSET + 64)));
8205 /* Indirect sibling calls are not allowed. */
8208 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8211 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8213 call_insn = emit_call_insn (call_insn);
8216 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8218 /* We don't have to restore the PIC register. */
8220 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8225 (define_insn "sibcall_value_internal_symref"
8226 [(set (match_operand 0 "" "")
8227 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8228 (match_operand 2 "" "i")))
8229 (clobber (reg:SI 1))
8231 (use (const_int 0))]
8232 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8235 output_arg_descriptor (insn);
8236 return output_call (insn, operands[1], 1);
8238 [(set_attr "type" "call")
8239 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8241 (define_insn "sibcall_value_internal_symref_64bit"
8242 [(set (match_operand 0 "" "")
8243 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8244 (match_operand 2 "" "i")))
8245 (clobber (reg:DI 1))
8247 (use (const_int 0))]
8251 output_arg_descriptor (insn);
8252 return output_call (insn, operands[1], 1);
8254 [(set_attr "type" "call")
8255 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8261 [(set_attr "type" "move")
8262 (set_attr "length" "4")])
8264 ;; These are just placeholders so we know where branch tables
8266 (define_insn "begin_brtab"
8271 /* Only GAS actually supports this pseudo-op. */
8273 return \".begin_brtab\";
8277 [(set_attr "type" "move")
8278 (set_attr "length" "0")])
8280 (define_insn "end_brtab"
8285 /* Only GAS actually supports this pseudo-op. */
8287 return \".end_brtab\";
8291 [(set_attr "type" "move")
8292 (set_attr "length" "0")])
8294 ;;; EH does longjmp's from and within the data section. Thus,
8295 ;;; an interspace branch is required for the longjmp implementation.
8296 ;;; Registers r1 and r2 are used as scratch registers for the jump
8298 (define_expand "interspace_jump"
8300 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8301 (clobber (match_dup 1))])]
8305 operands[1] = gen_rtx_REG (word_mode, 2);
8309 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8310 (clobber (reg:SI 2))]
8311 "TARGET_PA_20 && !TARGET_64BIT"
8313 [(set_attr "type" "branch")
8314 (set_attr "length" "4")])
8317 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8318 (clobber (reg:SI 2))]
8319 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8321 [(set_attr "type" "branch")
8322 (set_attr "length" "4")])
8325 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8326 (clobber (reg:SI 2))]
8328 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8329 [(set_attr "type" "branch")
8330 (set_attr "length" "12")])
8333 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8334 (clobber (reg:DI 2))]
8337 [(set_attr "type" "branch")
8338 (set_attr "length" "4")])
8340 (define_expand "builtin_longjmp"
8341 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8345 /* The elements of the buffer are, in order: */
8346 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8347 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8348 POINTER_SIZE / BITS_PER_UNIT));
8349 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8350 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8351 rtx pv = gen_rtx_REG (Pmode, 1);
8353 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8354 gen_rtx_MEM (BLKmode,
8355 gen_rtx_SCRATCH (VOIDmode))));
8356 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8357 gen_rtx_MEM (BLKmode,
8358 hard_frame_pointer_rtx)));
8360 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8361 instead of the hard_frame_pointer_rtx in the save area. We need
8362 to adjust for the offset between these two values when we have
8363 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8364 pattern, the receiver performs the adjustment. */
8365 #ifdef HAVE_nonlocal_goto
8366 if (HAVE_nonlocal_goto)
8367 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8370 emit_move_insn (hard_frame_pointer_rtx, fp);
8372 /* This bit is the same as expand_builtin_longjmp. */
8373 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8374 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8375 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8377 /* Load the label we are jumping through into r1 so that we know
8378 where to look for it when we get back to setjmp's function for
8379 restoring the gp. */
8380 emit_move_insn (pv, lab);
8382 /* Prevent the insns above from being scheduled into the delay slot
8383 of the interspace jump because the space register could change. */
8384 emit_insn (gen_blockage ());
8386 emit_jump_insn (gen_interspace_jump (pv));
8391 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8392 (define_expand "extzv"
8393 [(set (match_operand 0 "register_operand" "")
8394 (zero_extract (match_operand 1 "register_operand" "")
8395 (match_operand 2 "uint32_operand" "")
8396 (match_operand 3 "uint32_operand" "")))]
8400 HOST_WIDE_INT len = INTVAL (operands[2]);
8401 HOST_WIDE_INT pos = INTVAL (operands[3]);
8403 /* PA extraction insns don't support zero length bitfields or fields
8404 extending beyond the left or right-most bits. Also, we reject lengths
8405 equal to a word as they are better handled by the move patterns. */
8406 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8409 /* From mips.md: extract_bit_field doesn't verify that our source
8410 matches the predicate, so check it again here. */
8411 if (!register_operand (operands[1], VOIDmode))
8415 emit_insn (gen_extzv_64 (operands[0], operands[1],
8416 operands[2], operands[3]));
8418 emit_insn (gen_extzv_32 (operands[0], operands[1],
8419 operands[2], operands[3]));
8423 (define_insn "extzv_32"
8424 [(set (match_operand:SI 0 "register_operand" "=r")
8425 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8426 (match_operand:SI 2 "uint5_operand" "")
8427 (match_operand:SI 3 "uint5_operand" "")))]
8429 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8430 [(set_attr "type" "shift")
8431 (set_attr "length" "4")])
8434 [(set (match_operand:SI 0 "register_operand" "=r")
8435 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8437 (match_operand:SI 2 "register_operand" "q")))]
8439 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8440 [(set_attr "type" "shift")
8441 (set_attr "length" "4")])
8443 (define_insn "extzv_64"
8444 [(set (match_operand:DI 0 "register_operand" "=r")
8445 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8446 (match_operand:DI 2 "uint32_operand" "")
8447 (match_operand:DI 3 "uint32_operand" "")))]
8449 "extrd,u %1,%3+%2-1,%2,%0"
8450 [(set_attr "type" "shift")
8451 (set_attr "length" "4")])
8454 [(set (match_operand:DI 0 "register_operand" "=r")
8455 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8457 (match_operand:DI 2 "register_operand" "q")))]
8459 "extrd,u %1,%%sar,1,%0"
8460 [(set_attr "type" "shift")
8461 (set_attr "length" "4")])
8463 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8464 (define_expand "extv"
8465 [(set (match_operand 0 "register_operand" "")
8466 (sign_extract (match_operand 1 "register_operand" "")
8467 (match_operand 2 "uint32_operand" "")
8468 (match_operand 3 "uint32_operand" "")))]
8472 HOST_WIDE_INT len = INTVAL (operands[2]);
8473 HOST_WIDE_INT pos = INTVAL (operands[3]);
8475 /* PA extraction insns don't support zero length bitfields or fields
8476 extending beyond the left or right-most bits. Also, we reject lengths
8477 equal to a word as they are better handled by the move patterns. */
8478 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8481 /* From mips.md: extract_bit_field doesn't verify that our source
8482 matches the predicate, so check it again here. */
8483 if (!register_operand (operands[1], VOIDmode))
8487 emit_insn (gen_extv_64 (operands[0], operands[1],
8488 operands[2], operands[3]));
8490 emit_insn (gen_extv_32 (operands[0], operands[1],
8491 operands[2], operands[3]));
8495 (define_insn "extv_32"
8496 [(set (match_operand:SI 0 "register_operand" "=r")
8497 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8498 (match_operand:SI 2 "uint5_operand" "")
8499 (match_operand:SI 3 "uint5_operand" "")))]
8501 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8502 [(set_attr "type" "shift")
8503 (set_attr "length" "4")])
8506 [(set (match_operand:SI 0 "register_operand" "=r")
8507 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8509 (match_operand:SI 2 "register_operand" "q")))]
8511 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8512 [(set_attr "type" "shift")
8513 (set_attr "length" "4")])
8515 (define_insn "extv_64"
8516 [(set (match_operand:DI 0 "register_operand" "=r")
8517 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8518 (match_operand:DI 2 "uint32_operand" "")
8519 (match_operand:DI 3 "uint32_operand" "")))]
8521 "extrd,s %1,%3+%2-1,%2,%0"
8522 [(set_attr "type" "shift")
8523 (set_attr "length" "4")])
8526 [(set (match_operand:DI 0 "register_operand" "=r")
8527 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8529 (match_operand:DI 2 "register_operand" "q")))]
8531 "extrd,s %1,%%sar,1,%0"
8532 [(set_attr "type" "shift")
8533 (set_attr "length" "4")])
8535 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8536 (define_expand "insv"
8537 [(set (zero_extract (match_operand 0 "register_operand" "")
8538 (match_operand 1 "uint32_operand" "")
8539 (match_operand 2 "uint32_operand" ""))
8540 (match_operand 3 "arith5_operand" ""))]
8544 HOST_WIDE_INT len = INTVAL (operands[1]);
8545 HOST_WIDE_INT pos = INTVAL (operands[2]);
8547 /* PA insertion insns don't support zero length bitfields or fields
8548 extending beyond the left or right-most bits. Also, we reject lengths
8549 equal to a word as they are better handled by the move patterns. */
8550 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8553 /* From mips.md: insert_bit_field doesn't verify that our destination
8554 matches the predicate, so check it again here. */
8555 if (!register_operand (operands[0], VOIDmode))
8559 emit_insn (gen_insv_64 (operands[0], operands[1],
8560 operands[2], operands[3]));
8562 emit_insn (gen_insv_32 (operands[0], operands[1],
8563 operands[2], operands[3]));
8567 (define_insn "insv_32"
8568 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8569 (match_operand:SI 1 "uint5_operand" "")
8570 (match_operand:SI 2 "uint5_operand" ""))
8571 (match_operand:SI 3 "arith5_operand" "r,L"))]
8574 {dep|depw} %3,%2+%1-1,%1,%0
8575 {depi|depwi} %3,%2+%1-1,%1,%0"
8576 [(set_attr "type" "shift,shift")
8577 (set_attr "length" "4,4")])
8579 ;; Optimize insertion of const_int values of type 1...1xxxx.
8581 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8582 (match_operand:SI 1 "uint5_operand" "")
8583 (match_operand:SI 2 "uint5_operand" ""))
8584 (match_operand:SI 3 "const_int_operand" ""))]
8585 "(INTVAL (operands[3]) & 0x10) != 0 &&
8586 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8589 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8590 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8592 [(set_attr "type" "shift")
8593 (set_attr "length" "4")])
8595 (define_insn "insv_64"
8596 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8597 (match_operand:DI 1 "uint32_operand" "")
8598 (match_operand:DI 2 "uint32_operand" ""))
8599 (match_operand:DI 3 "arith32_operand" "r,L"))]
8602 depd %3,%2+%1-1,%1,%0
8603 depdi %3,%2+%1-1,%1,%0"
8604 [(set_attr "type" "shift,shift")
8605 (set_attr "length" "4,4")])
8607 ;; Optimize insertion of const_int values of type 1...1xxxx.
8609 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8610 (match_operand:DI 1 "uint32_operand" "")
8611 (match_operand:DI 2 "uint32_operand" ""))
8612 (match_operand:DI 3 "const_int_operand" ""))]
8613 "(INTVAL (operands[3]) & 0x10) != 0
8615 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8618 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8619 return \"depdi %3,%2+%1-1,%1,%0\";
8621 [(set_attr "type" "shift")
8622 (set_attr "length" "4")])
8625 [(set (match_operand:DI 0 "register_operand" "=r")
8626 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8629 "depd,z %1,31,32,%0"
8630 [(set_attr "type" "shift")
8631 (set_attr "length" "4")])
8633 ;; This insn is used for some loop tests, typically loops reversed when
8634 ;; strength reduction is used. It is actually created when the instruction
8635 ;; combination phase combines the special loop test. Since this insn
8636 ;; is both a jump insn and has an output, it must deal with its own
8637 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8638 ;; to not choose the register alternatives in the event a reload is needed.
8639 (define_insn "decrement_and_branch_until_zero"
8642 (match_operator 2 "comparison_operator"
8644 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8645 (match_operand:SI 1 "int5_operand" "L,L,L"))
8647 (label_ref (match_operand 3 "" ""))
8650 (plus:SI (match_dup 0) (match_dup 1)))
8651 (clobber (match_scratch:SI 4 "=X,r,r"))]
8653 "* return output_dbra (operands, insn, which_alternative); "
8654 ;; Do not expect to understand this the first time through.
8655 [(set_attr "type" "cbranch,multi,multi")
8656 (set (attr "length")
8657 (if_then_else (eq_attr "alternative" "0")
8658 ;; Loop counter in register case
8659 ;; Short branch has length of 4
8660 ;; Long branch has length of 8
8661 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8666 ;; Loop counter in FP reg case.
8667 ;; Extra goo to deal with additional reload insns.
8668 (if_then_else (eq_attr "alternative" "1")
8669 (if_then_else (lt (match_dup 3) (pc))
8671 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8676 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8680 ;; Loop counter in memory case.
8681 ;; Extra goo to deal with additional reload insns.
8682 (if_then_else (lt (match_dup 3) (pc))
8684 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8689 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8692 (const_int 16))))))])
8697 (match_operator 2 "movb_comparison_operator"
8698 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8699 (label_ref (match_operand 3 "" ""))
8701 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8704 "* return output_movb (operands, insn, which_alternative, 0); "
8705 ;; Do not expect to understand this the first time through.
8706 [(set_attr "type" "cbranch,multi,multi,multi")
8707 (set (attr "length")
8708 (if_then_else (eq_attr "alternative" "0")
8709 ;; Loop counter in register case
8710 ;; Short branch has length of 4
8711 ;; Long branch has length of 8
8712 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8717 ;; Loop counter in FP reg case.
8718 ;; Extra goo to deal with additional reload insns.
8719 (if_then_else (eq_attr "alternative" "1")
8720 (if_then_else (lt (match_dup 3) (pc))
8722 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8727 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8731 ;; Loop counter in memory or sar case.
8732 ;; Extra goo to deal with additional reload insns.
8734 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8737 (const_int 12)))))])
8739 ;; Handle negated branch.
8743 (match_operator 2 "movb_comparison_operator"
8744 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8746 (label_ref (match_operand 3 "" ""))))
8747 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8750 "* return output_movb (operands, insn, which_alternative, 1); "
8751 ;; Do not expect to understand this the first time through.
8752 [(set_attr "type" "cbranch,multi,multi,multi")
8753 (set (attr "length")
8754 (if_then_else (eq_attr "alternative" "0")
8755 ;; Loop counter in register case
8756 ;; Short branch has length of 4
8757 ;; Long branch has length of 8
8758 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8763 ;; Loop counter in FP reg case.
8764 ;; Extra goo to deal with additional reload insns.
8765 (if_then_else (eq_attr "alternative" "1")
8766 (if_then_else (lt (match_dup 3) (pc))
8768 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8773 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8777 ;; Loop counter in memory or SAR case.
8778 ;; Extra goo to deal with additional reload insns.
8780 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8783 (const_int 12)))))])
8786 [(set (pc) (label_ref (match_operand 3 "" "" )))
8787 (set (match_operand:SI 0 "ireg_operand" "=r")
8788 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8789 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8790 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8793 return output_parallel_addb (operands, get_attr_length (insn));
8795 [(set_attr "type" "parallel_branch")
8796 (set (attr "length")
8797 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8803 [(set (pc) (label_ref (match_operand 2 "" "" )))
8804 (set (match_operand:SF 0 "ireg_operand" "=r")
8805 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8809 return output_parallel_movb (operands, get_attr_length (insn));
8811 [(set_attr "type" "parallel_branch")
8812 (set (attr "length")
8813 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8819 [(set (pc) (label_ref (match_operand 2 "" "" )))
8820 (set (match_operand:SI 0 "ireg_operand" "=r")
8821 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8825 return output_parallel_movb (operands, get_attr_length (insn));
8827 [(set_attr "type" "parallel_branch")
8828 (set (attr "length")
8829 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8835 [(set (pc) (label_ref (match_operand 2 "" "" )))
8836 (set (match_operand:HI 0 "ireg_operand" "=r")
8837 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8841 return output_parallel_movb (operands, get_attr_length (insn));
8843 [(set_attr "type" "parallel_branch")
8844 (set (attr "length")
8845 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8851 [(set (pc) (label_ref (match_operand 2 "" "" )))
8852 (set (match_operand:QI 0 "ireg_operand" "=r")
8853 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8857 return output_parallel_movb (operands, get_attr_length (insn));
8859 [(set_attr "type" "parallel_branch")
8860 (set (attr "length")
8861 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8867 [(set (match_operand 0 "register_operand" "=f")
8868 (mult (match_operand 1 "register_operand" "f")
8869 (match_operand 2 "register_operand" "f")))
8870 (set (match_operand 3 "register_operand" "+f")
8871 (plus (match_operand 4 "register_operand" "f")
8872 (match_operand 5 "register_operand" "f")))]
8873 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8874 && reload_completed && fmpyaddoperands (operands)"
8877 if (GET_MODE (operands[0]) == DFmode)
8879 if (rtx_equal_p (operands[3], operands[5]))
8880 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8882 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8886 if (rtx_equal_p (operands[3], operands[5]))
8887 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8889 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8892 [(set_attr "type" "fpalu")
8893 (set_attr "length" "4")])
8896 [(set (match_operand 3 "register_operand" "+f")
8897 (plus (match_operand 4 "register_operand" "f")
8898 (match_operand 5 "register_operand" "f")))
8899 (set (match_operand 0 "register_operand" "=f")
8900 (mult (match_operand 1 "register_operand" "f")
8901 (match_operand 2 "register_operand" "f")))]
8902 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8903 && reload_completed && fmpyaddoperands (operands)"
8906 if (GET_MODE (operands[0]) == DFmode)
8908 if (rtx_equal_p (operands[3], operands[5]))
8909 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8911 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8915 if (rtx_equal_p (operands[3], operands[5]))
8916 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8918 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8921 [(set_attr "type" "fpalu")
8922 (set_attr "length" "4")])
8925 [(set (match_operand 0 "register_operand" "=f")
8926 (mult (match_operand 1 "register_operand" "f")
8927 (match_operand 2 "register_operand" "f")))
8928 (set (match_operand 3 "register_operand" "+f")
8929 (minus (match_operand 4 "register_operand" "f")
8930 (match_operand 5 "register_operand" "f")))]
8931 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8932 && reload_completed && fmpysuboperands (operands)"
8935 if (GET_MODE (operands[0]) == DFmode)
8936 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8938 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8940 [(set_attr "type" "fpalu")
8941 (set_attr "length" "4")])
8944 [(set (match_operand 3 "register_operand" "+f")
8945 (minus (match_operand 4 "register_operand" "f")
8946 (match_operand 5 "register_operand" "f")))
8947 (set (match_operand 0 "register_operand" "=f")
8948 (mult (match_operand 1 "register_operand" "f")
8949 (match_operand 2 "register_operand" "f")))]
8950 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8951 && reload_completed && fmpysuboperands (operands)"
8954 if (GET_MODE (operands[0]) == DFmode)
8955 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8957 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8959 [(set_attr "type" "fpalu")
8960 (set_attr "length" "4")])
8962 ;; Flush the I and D cache lines from the start address (operand0)
8963 ;; to the end address (operand1). No lines are flushed if the end
8964 ;; address is less than the start address (unsigned).
8966 ;; Because the range of memory flushed is variable and the size of
8967 ;; a MEM can only be a CONST_INT, the patterns specify that they
8968 ;; perform an unspecified volatile operation on all memory.
8970 ;; The address range for an icache flush must lie within a single
8971 ;; space on targets with non-equivalent space registers.
8973 ;; This is used by the trampoline code for nested functions.
8975 ;; Operand 0 contains the start address.
8976 ;; Operand 1 contains the end address.
8977 ;; Operand 2 contains the line length to use.
8978 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
8979 (define_insn "dcacheflush"
8981 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
8982 (use (match_operand 0 "pmode_register_operand" "r"))
8983 (use (match_operand 1 "pmode_register_operand" "r"))
8984 (use (match_operand 2 "pmode_register_operand" "r"))
8985 (clobber (match_scratch 3 "=&0"))]
8990 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8992 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8994 [(set_attr "type" "multi")
8995 (set_attr "length" "12")])
8997 (define_insn "icacheflush"
8999 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9000 (use (match_operand 0 "pmode_register_operand" "r"))
9001 (use (match_operand 1 "pmode_register_operand" "r"))
9002 (use (match_operand 2 "pmode_register_operand" "r"))
9003 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9004 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9005 (clobber (match_scratch 5 "=&0"))]
9010 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9012 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9014 [(set_attr "type" "multi")
9015 (set_attr "length" "52")])
9017 ;; An out-of-line prologue.
9018 (define_insn "outline_prologue_call"
9019 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9020 (clobber (reg:SI 31))
9021 (clobber (reg:SI 22))
9022 (clobber (reg:SI 21))
9023 (clobber (reg:SI 20))
9024 (clobber (reg:SI 19))
9025 (clobber (reg:SI 1))]
9029 extern int frame_pointer_needed;
9031 /* We need two different versions depending on whether or not we
9032 need a frame pointer. Also note that we return to the instruction
9033 immediately after the branch rather than two instructions after the
9034 break as normally is the case. */
9035 if (frame_pointer_needed)
9037 /* Must import the magic millicode routine(s). */
9038 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9040 if (TARGET_PORTABLE_RUNTIME)
9042 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9043 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9047 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9051 /* Must import the magic millicode routine(s). */
9052 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9054 if (TARGET_PORTABLE_RUNTIME)
9056 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9057 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9060 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9064 [(set_attr "type" "multi")
9065 (set_attr "length" "8")])
9067 ;; An out-of-line epilogue.
9068 (define_insn "outline_epilogue_call"
9069 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9072 (clobber (reg:SI 31))
9073 (clobber (reg:SI 22))
9074 (clobber (reg:SI 21))
9075 (clobber (reg:SI 20))
9076 (clobber (reg:SI 19))
9077 (clobber (reg:SI 2))
9078 (clobber (reg:SI 1))]
9082 extern int frame_pointer_needed;
9084 /* We need two different versions depending on whether or not we
9085 need a frame pointer. Also note that we return to the instruction
9086 immediately after the branch rather than two instructions after the
9087 break as normally is the case. */
9088 if (frame_pointer_needed)
9090 /* Must import the magic millicode routine. */
9091 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9093 /* The out-of-line prologue will make sure we return to the right
9095 if (TARGET_PORTABLE_RUNTIME)
9097 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9098 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9102 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9106 /* Must import the magic millicode routine. */
9107 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9109 /* The out-of-line prologue will make sure we return to the right
9111 if (TARGET_PORTABLE_RUNTIME)
9113 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9114 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9117 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9121 [(set_attr "type" "multi")
9122 (set_attr "length" "8")])
9124 ;; Given a function pointer, canonicalize it so it can be
9125 ;; reliably compared to another function pointer. */
9126 (define_expand "canonicalize_funcptr_for_compare"
9127 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9128 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9129 (clobber (match_dup 2))
9130 (clobber (reg:SI 26))
9131 (clobber (reg:SI 22))
9132 (clobber (reg:SI 31))])
9133 (set (match_operand:SI 0 "register_operand" "")
9135 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9140 rtx canonicalize_funcptr_for_compare_libfunc
9141 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9143 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9144 operands[0], LCT_NORMAL, Pmode,
9145 1, operands[1], Pmode);
9149 operands[2] = gen_reg_rtx (SImode);
9150 if (GET_CODE (operands[1]) != REG)
9152 rtx tmp = gen_reg_rtx (Pmode);
9153 emit_move_insn (tmp, operands[1]);
9158 (define_insn "*$$sh_func_adrs"
9159 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9160 (clobber (match_operand:SI 0 "register_operand" "=a"))
9161 (clobber (reg:SI 26))
9162 (clobber (reg:SI 22))
9163 (clobber (reg:SI 31))]
9167 int length = get_attr_length (insn);
9170 xoperands[0] = GEN_INT (length - 8);
9171 xoperands[1] = GEN_INT (length - 16);
9173 /* Must import the magic millicode routine. */
9174 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9176 /* This is absolutely amazing.
9178 First, copy our input parameter into %r29 just in case we don't
9179 need to call $$sh_func_adrs. */
9180 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9181 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9183 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9184 we use %r26 unchanged. */
9185 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9186 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9188 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9189 4096, then again we use %r26 unchanged. */
9190 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9192 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9193 return output_millicode_call (insn,
9194 gen_rtx_SYMBOL_REF (SImode,
9195 \"$$sh_func_adrs\"));
9197 [(set_attr "type" "multi")
9198 (set (attr "length")
9199 (plus (symbol_ref "attr_length_millicode_call (insn)")
9202 ;; On the PA, the PIC register is call clobbered, so it must
9203 ;; be saved & restored around calls by the caller. If the call
9204 ;; doesn't return normally (nonlocal goto, or an exception is
9205 ;; thrown), then the code at the exception handler label must
9206 ;; restore the PIC register.
9207 (define_expand "exception_receiver"
9212 /* On the 64-bit port, we need a blockage because there is
9213 confusion regarding the dependence of the restore on the
9214 frame pointer. As a result, the frame pointer and pic
9215 register restores sometimes are interchanged erroneously. */
9217 emit_insn (gen_blockage ());
9218 /* Restore the PIC register using hppa_pic_save_rtx (). The
9219 PIC register is not saved in the frame in 64-bit ABI. */
9220 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9221 emit_insn (gen_blockage ());
9225 (define_expand "builtin_setjmp_receiver"
9226 [(label_ref (match_operand 0 "" ""))]
9231 emit_insn (gen_blockage ());
9232 /* Restore the PIC register. Hopefully, this will always be from
9233 a stack slot. The only registers that are valid after a
9234 builtin_longjmp are the stack and frame pointers. */
9235 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9236 emit_insn (gen_blockage ());
9240 ;; Allocate new stack space and update the saved stack pointer in the
9241 ;; frame marker. The HP C compilers also copy additional words in the
9242 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9243 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9244 ;; currently don't copy these values.
9246 ;; Since the copy of the frame marker can't be done atomically, I
9247 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9248 ;; The HP compilers appear to raise the stack and copy the frame
9249 ;; marker in a strict instruction sequence. This suggests that the
9250 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9251 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9252 ;; as GAS doesn't support it, or try to keep the instructions emitted
9253 ;; here in strict sequence.
9254 (define_expand "allocate_stack"
9255 [(match_operand 0 "" "")
9256 (match_operand 1 "" "")]
9262 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9263 in operand 0 before adjusting the stack. */
9264 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9265 anti_adjust_stack (operands[1]);
9266 if (TARGET_HPUX_UNWIND_LIBRARY)
9268 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9269 GEN_INT (TARGET_64BIT ? -8 : -4));
9270 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9272 if (!TARGET_64BIT && flag_pic)
9274 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9275 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9280 (define_expand "prefetch"
9281 [(match_operand 0 "address_operand" "")
9282 (match_operand 1 "const_int_operand" "")
9283 (match_operand 2 "const_int_operand" "")]
9286 /* The PA 2.0 prefetch instructions only support short displacements
9287 when a cache control completer needs to be supplied. Thus, we
9288 can't use LO_SUM DLT addresses with the spatial locality completer. */
9289 if (operands[2] == const0_rtx && IS_LO_SUM_DLT_ADDR_P (operands[0]))
9292 /* We change operand0 to a MEM as we don't have the infrastructure to
9293 output all the supported address modes for ldw/ldd but we do have
9295 operands[0] = gen_rtx_MEM (Pmode, operands[0]);
9297 if (!TARGET_NO_SPACE_REGS
9298 && !cse_not_expected
9299 && GET_CODE (XEXP (operands[0], 0)) == PLUS
9300 && REG_P (XEXP (XEXP (operands[0], 0), 0))
9301 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
9303 = replace_equiv_address (operands[0],
9304 copy_to_mode_reg (Pmode,
9305 XEXP (operands[0], 0)));
9308 emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
9310 emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
9314 (define_insn "prefetch_64"
9315 [(prefetch (match_operand:DI 0 "prefetch_operand" "A,RQ")
9316 (match_operand:DI 1 "const_int_operand" "n,n")
9317 (match_operand:DI 2 "const_int_operand" "n,n"))]
9319 && (operands[2] != const0_rtx
9320 || GET_CODE (XEXP (operands[0], 0)) != PLUS
9321 || GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != CONST_INT
9322 || INT_5_BITS (XEXP (XEXP (operands[0], 0), 1)))"
9324 /* The SL completor indicates good spatial locality but poor temporal
9325 locality. The ldw instruction with a target of general register 0
9326 prefetches a cache line for a read. The ldd instruction prefetches
9327 a cache line for a write. */
9328 static const char * const instr[2][2][2] = {
9341 "ldw%M0,sl %0,%%r0",
9345 "ldd%M0,sl %0,%%r0",
9350 int read_or_write = INTVAL (operands[1]);
9351 int locality = INTVAL (operands[2]);
9353 if ((which_alternative != 0 && which_alternative != 1)
9354 || (read_or_write != 0 && read_or_write != 1)
9355 || (locality < 0 || locality > 3))
9358 if (which_alternative == 0 && locality == 0)
9361 return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
9363 [(set_attr "type" "load")
9364 (set_attr "length" "4")])
9366 (define_insn "prefetch_32"
9367 [(prefetch (match_operand:SI 0 "prefetch_operand" "A,RQ")
9368 (match_operand:SI 1 "const_int_operand" "n,n")
9369 (match_operand:SI 2 "const_int_operand" "n,n"))]
9371 && (operands[2] != const0_rtx
9372 || GET_CODE (XEXP (operands[0], 0)) != PLUS
9373 || GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != CONST_INT
9374 || INT_5_BITS (XEXP (XEXP (operands[0], 0), 1)))"
9376 /* The SL completor indicates good spatial locality but poor temporal
9377 locality. The ldw instruction with a target of general register 0
9378 prefetches a cache line for a read. The ldd instruction prefetches
9379 a cache line for a write. */
9380 static const char * const instr[2][2][2] = {
9393 "ldw%M0,sl %0,%%r0",
9397 "ldd%M0,sl %0,%%r0",
9402 int read_or_write = INTVAL (operands[1]);
9403 int locality = INTVAL (operands[2]);
9405 if ((which_alternative != 0 && which_alternative != 1)
9406 || (read_or_write != 0 && read_or_write != 1)
9407 || (locality < 0 || locality > 3))
9410 if (which_alternative == 0 && locality == 0)
9413 return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
9415 [(set_attr "type" "load")
9416 (set_attr "length" "4")])