1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "move_dest_operand"
2267 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
2268 (match_operand:SI 1 "move_src_operand"
2269 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && !TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2285 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2286 (set_attr "pa_combine_type" "addmove")
2287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2290 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2291 (match_operand:SI 1 "register_operand" "f"))]
2293 && !TARGET_DISABLE_INDEXING
2294 && reload_completed"
2296 [(set_attr "type" "fpstore")
2297 (set_attr "pa_combine_type" "addmove")
2298 (set_attr "length" "4")])
2300 ; Rewrite RTL using an indexed store. This will allow the insn that
2301 ; computes the address to be deleted if the register it sets is dead.
2303 [(set (match_operand:SI 0 "register_operand" "")
2304 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2306 (match_operand:SI 2 "register_operand" "")))
2307 (set (mem:SI (match_dup 0))
2308 (match_operand:SI 3 "register_operand" ""))]
2310 && REG_OK_FOR_BASE_P (operands[2])
2311 && FP_REGNO_P (REGNO (operands[3]))"
2312 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2314 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2319 [(set (match_operand:SI 0 "register_operand" "")
2320 (plus:SI (match_operand:SI 2 "register_operand" "")
2321 (mult:SI (match_operand:SI 1 "register_operand" "")
2323 (set (mem:SI (match_dup 0))
2324 (match_operand:SI 3 "register_operand" ""))]
2326 && REG_OK_FOR_BASE_P (operands[2])
2327 && FP_REGNO_P (REGNO (operands[3]))"
2328 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2330 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2335 [(set (match_operand:DI 0 "register_operand" "")
2336 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2338 (match_operand:DI 2 "register_operand" "")))
2339 (set (mem:SI (match_dup 0))
2340 (match_operand:SI 3 "register_operand" ""))]
2343 && REG_OK_FOR_BASE_P (operands[2])
2344 && FP_REGNO_P (REGNO (operands[3]))"
2345 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2347 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2352 [(set (match_operand:DI 0 "register_operand" "")
2353 (plus:DI (match_operand:DI 2 "register_operand" "")
2354 (mult:DI (match_operand:DI 1 "register_operand" "")
2356 (set (mem:SI (match_dup 0))
2357 (match_operand:SI 3 "register_operand" ""))]
2360 && REG_OK_FOR_BASE_P (operands[2])
2361 && FP_REGNO_P (REGNO (operands[3]))"
2362 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2364 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2369 [(set (match_operand:SI 0 "register_operand" "")
2370 (plus:SI (match_operand:SI 1 "register_operand" "")
2371 (match_operand:SI 2 "register_operand" "")))
2372 (set (mem:SI (match_dup 0))
2373 (match_operand:SI 3 "register_operand" ""))]
2375 && REG_OK_FOR_BASE_P (operands[1])
2376 && (TARGET_NO_SPACE_REGS
2377 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2378 && FP_REGNO_P (REGNO (operands[3]))"
2379 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2381 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2385 [(set (match_operand:SI 0 "register_operand" "")
2386 (plus:SI (match_operand:SI 1 "register_operand" "")
2387 (match_operand:SI 2 "register_operand" "")))
2388 (set (mem:SI (match_dup 0))
2389 (match_operand:SI 3 "register_operand" ""))]
2391 && REG_OK_FOR_BASE_P (operands[2])
2392 && (TARGET_NO_SPACE_REGS
2393 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2394 && FP_REGNO_P (REGNO (operands[3]))"
2395 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2397 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2401 [(set (match_operand:DI 0 "register_operand" "")
2402 (plus:DI (match_operand:DI 1 "register_operand" "")
2403 (match_operand:DI 2 "register_operand" "")))
2404 (set (mem:SI (match_dup 0))
2405 (match_operand:SI 3 "register_operand" ""))]
2408 && REG_OK_FOR_BASE_P (operands[1])
2409 && (TARGET_NO_SPACE_REGS
2410 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2411 && FP_REGNO_P (REGNO (operands[3]))"
2412 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2414 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2418 [(set (match_operand:DI 0 "register_operand" "")
2419 (plus:DI (match_operand:DI 1 "register_operand" "")
2420 (match_operand:DI 2 "register_operand" "")))
2421 (set (mem:SI (match_dup 0))
2422 (match_operand:SI 3 "register_operand" ""))]
2425 && REG_OK_FOR_BASE_P (operands[2])
2426 && (TARGET_NO_SPACE_REGS
2427 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2428 && FP_REGNO_P (REGNO (operands[3]))"
2429 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2431 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2435 [(set (match_operand:SI 0 "move_dest_operand"
2436 "=r,r,r,r,r,r,Q,!*q")
2437 (match_operand:SI 1 "move_src_operand"
2438 "A,r,J,N,K,RQ,rM,!rM"))]
2439 "(register_operand (operands[0], SImode)
2440 || reg_or_0_operand (operands[1], SImode))
2441 && TARGET_SOFT_FLOAT"
2447 {zdepi|depwi,z} %Z1,%0
2451 [(set_attr "type" "load,move,move,move,move,load,store,move")
2452 (set_attr "pa_combine_type" "addmove")
2453 (set_attr "length" "4,4,4,4,4,4,4,4")])
2455 ;; Load or store with base-register modification.
2457 [(set (match_operand:SI 0 "register_operand" "=r")
2458 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2459 (match_operand:DI 2 "int5_operand" "L"))))
2461 (plus:DI (match_dup 1) (match_dup 2)))]
2464 [(set_attr "type" "load")
2465 (set_attr "length" "4")])
2467 ; And a zero extended variant.
2469 [(set (match_operand:DI 0 "register_operand" "=r")
2470 (zero_extend:DI (mem:SI
2472 (match_operand:DI 1 "register_operand" "+r")
2473 (match_operand:DI 2 "int5_operand" "L")))))
2475 (plus:DI (match_dup 1) (match_dup 2)))]
2478 [(set_attr "type" "load")
2479 (set_attr "length" "4")])
2481 (define_expand "pre_load"
2482 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2483 (mem (plus (match_operand 1 "register_operand" "")
2484 (match_operand 2 "pre_cint_operand" ""))))
2486 (plus (match_dup 1) (match_dup 2)))])]
2492 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2495 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2499 (define_insn "pre_ldw"
2500 [(set (match_operand:SI 0 "register_operand" "=r")
2501 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2502 (match_operand:SI 2 "pre_cint_operand" ""))))
2504 (plus:SI (match_dup 1) (match_dup 2)))]
2508 if (INTVAL (operands[2]) < 0)
2509 return \"{ldwm|ldw,mb} %2(%1),%0\";
2510 return \"{ldws|ldw},mb %2(%1),%0\";
2512 [(set_attr "type" "load")
2513 (set_attr "length" "4")])
2515 (define_insn "pre_ldd"
2516 [(set (match_operand:DI 0 "register_operand" "=r")
2517 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2518 (match_operand:DI 2 "pre_cint_operand" ""))))
2520 (plus:DI (match_dup 1) (match_dup 2)))]
2523 [(set_attr "type" "load")
2524 (set_attr "length" "4")])
2527 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2528 (match_operand:SI 1 "pre_cint_operand" "")))
2529 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2531 (plus:SI (match_dup 0) (match_dup 1)))]
2535 if (INTVAL (operands[1]) < 0)
2536 return \"{stwm|stw,mb} %r2,%1(%0)\";
2537 return \"{stws|stw},mb %r2,%1(%0)\";
2539 [(set_attr "type" "store")
2540 (set_attr "length" "4")])
2543 [(set (match_operand:SI 0 "register_operand" "=r")
2544 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2546 (plus:SI (match_dup 1)
2547 (match_operand:SI 2 "post_cint_operand" "")))]
2551 if (INTVAL (operands[2]) > 0)
2552 return \"{ldwm|ldw,ma} %2(%1),%0\";
2553 return \"{ldws|ldw},ma %2(%1),%0\";
2555 [(set_attr "type" "load")
2556 (set_attr "length" "4")])
2558 (define_expand "post_store"
2559 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2560 (match_operand 1 "reg_or_0_operand" ""))
2563 (match_operand 2 "post_cint_operand" "")))])]
2569 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2572 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2576 (define_insn "post_stw"
2577 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2578 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2580 (plus:SI (match_dup 0)
2581 (match_operand:SI 2 "post_cint_operand" "")))]
2585 if (INTVAL (operands[2]) > 0)
2586 return \"{stwm|stw,ma} %r1,%2(%0)\";
2587 return \"{stws|stw},ma %r1,%2(%0)\";
2589 [(set_attr "type" "store")
2590 (set_attr "length" "4")])
2592 (define_insn "post_std"
2593 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2594 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2596 (plus:DI (match_dup 0)
2597 (match_operand:DI 2 "post_cint_operand" "")))]
2600 [(set_attr "type" "store")
2601 (set_attr "length" "4")])
2603 ;; For loading the address of a label while generating PIC code.
2604 ;; Note since this pattern can be created at reload time (via movsi), all
2605 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2607 [(set (match_operand 0 "pmode_register_operand" "=a")
2608 (match_operand 1 "pic_label_operand" ""))]
2613 extern FILE *asm_out_file;
2615 xoperands[0] = operands[0];
2616 xoperands[1] = operands[1];
2617 xoperands[2] = gen_label_rtx ();
2619 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2620 CODE_LABEL_NUMBER (xoperands[2]));
2621 output_asm_insn (\"mfia %0\", xoperands);
2623 /* If we're trying to load the address of a label that happens to be
2624 close, then we can use a shorter sequence. */
2625 if (GET_CODE (operands[1]) == LABEL_REF
2626 && INSN_ADDRESSES_SET_P ()
2627 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2628 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2629 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2632 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2633 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2637 [(set_attr "type" "multi")
2638 (set_attr "length" "12")]) ; 8 or 12
2641 [(set (match_operand 0 "pmode_register_operand" "=a")
2642 (match_operand 1 "pic_label_operand" ""))]
2647 extern FILE *asm_out_file;
2649 xoperands[0] = operands[0];
2650 xoperands[1] = operands[1];
2651 xoperands[2] = gen_label_rtx ();
2653 output_asm_insn (\"bl .+8,%0\", xoperands);
2654 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2655 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2656 CODE_LABEL_NUMBER (xoperands[2]));
2658 /* If we're trying to load the address of a label that happens to be
2659 close, then we can use a shorter sequence. */
2660 if (GET_CODE (operands[1]) == LABEL_REF
2661 && INSN_ADDRESSES_SET_P ()
2662 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2663 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2664 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2667 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2668 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2672 [(set_attr "type" "multi")
2673 (set_attr "length" "16")]) ; 12 or 16
2676 [(set (match_operand:SI 0 "register_operand" "=a")
2677 (plus:SI (match_operand:SI 1 "register_operand" "r")
2678 (high:SI (match_operand 2 "" ""))))]
2679 "symbolic_operand (operands[2], Pmode)
2680 && ! function_label_operand (operands[2], Pmode)
2683 [(set_attr "type" "binary")
2684 (set_attr "length" "4")])
2687 [(set (match_operand:DI 0 "register_operand" "=a")
2688 (plus:DI (match_operand:DI 1 "register_operand" "r")
2689 (high:DI (match_operand 2 "" ""))))]
2690 "symbolic_operand (operands[2], Pmode)
2691 && ! function_label_operand (operands[2], Pmode)
2695 [(set_attr "type" "binary")
2696 (set_attr "length" "4")])
2698 ;; Always use addil rather than ldil;add sequences. This allows the
2699 ;; HP linker to eliminate the dp relocation if the symbolic operand
2700 ;; lives in the TEXT space.
2702 [(set (match_operand:SI 0 "register_operand" "=a")
2703 (high:SI (match_operand 1 "" "")))]
2704 "symbolic_operand (operands[1], Pmode)
2705 && ! function_label_operand (operands[1], Pmode)
2706 && ! read_only_operand (operands[1], Pmode)
2710 if (TARGET_LONG_LOAD_STORE)
2711 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2713 return \"addil LR'%H1,%%r27\";
2715 [(set_attr "type" "binary")
2716 (set (attr "length")
2717 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2722 ;; This is for use in the prologue/epilogue code. We need it
2723 ;; to add large constants to a stack pointer or frame pointer.
2724 ;; Because of the additional %r1 pressure, we probably do not
2725 ;; want to use this in general code, so make it available
2726 ;; only after reload.
2728 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2729 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2730 (high:SI (match_operand 2 "const_int_operand" ""))))]
2734 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2735 [(set_attr "type" "binary,binary")
2736 (set_attr "length" "4,8")])
2739 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2740 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2741 (high:DI (match_operand 2 "const_int_operand" ""))))]
2742 "reload_completed && TARGET_64BIT"
2745 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2746 [(set_attr "type" "binary,binary")
2747 (set_attr "length" "4,8")])
2750 [(set (match_operand:SI 0 "register_operand" "=r")
2751 (high:SI (match_operand 1 "" "")))]
2752 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2753 && !is_function_label_plus_const (operands[1])"
2756 if (symbolic_operand (operands[1], Pmode))
2757 return \"ldil LR'%H1,%0\";
2759 return \"ldil L'%G1,%0\";
2761 [(set_attr "type" "move")
2762 (set_attr "length" "4")])
2765 [(set (match_operand:DI 0 "register_operand" "=r")
2766 (high:DI (match_operand 1 "const_int_operand" "")))]
2769 [(set_attr "type" "move")
2770 (set_attr "length" "4")])
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2775 (match_operand:DI 2 "const_int_operand" "i")))]
2778 [(set_attr "type" "move")
2779 (set_attr "length" "4")])
2782 [(set (match_operand:SI 0 "register_operand" "=r")
2783 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2784 (match_operand:SI 2 "immediate_operand" "i")))]
2785 "!is_function_label_plus_const (operands[2])"
2788 if (flag_pic && symbolic_operand (operands[2], Pmode))
2790 else if (symbolic_operand (operands[2], Pmode))
2791 return \"ldo RR'%G2(%1),%0\";
2793 return \"ldo R'%G2(%1),%0\";
2795 [(set_attr "type" "move")
2796 (set_attr "length" "4")])
2798 ;; Now that a symbolic_address plus a constant is broken up early
2799 ;; in the compilation phase (for better CSE) we need a special
2800 ;; combiner pattern to load the symbolic address plus the constant
2801 ;; in only 2 instructions. (For cases where the symbolic address
2802 ;; was not a common subexpression.)
2804 [(set (match_operand:SI 0 "register_operand" "")
2805 (match_operand:SI 1 "symbolic_operand" ""))
2806 (clobber (match_operand:SI 2 "register_operand" ""))]
2807 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2808 [(set (match_dup 2) (high:SI (match_dup 1)))
2809 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2812 ;; hppa_legitimize_address goes to a great deal of trouble to
2813 ;; create addresses which use indexing. In some cases, this
2814 ;; is a lose because there isn't any store instructions which
2815 ;; allow indexed addresses (with integer register source).
2817 ;; These define_splits try to turn a 3 insn store into
2818 ;; a 2 insn store with some creative RTL rewriting.
2820 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2821 (match_operand:SI 1 "shadd_operand" ""))
2822 (plus:SI (match_operand:SI 2 "register_operand" "")
2823 (match_operand:SI 3 "const_int_operand" ""))))
2824 (match_operand:SI 4 "register_operand" ""))
2825 (clobber (match_operand:SI 5 "register_operand" ""))]
2827 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2829 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2833 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2834 (match_operand:SI 1 "shadd_operand" ""))
2835 (plus:SI (match_operand:SI 2 "register_operand" "")
2836 (match_operand:SI 3 "const_int_operand" ""))))
2837 (match_operand:HI 4 "register_operand" ""))
2838 (clobber (match_operand:SI 5 "register_operand" ""))]
2840 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2842 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2846 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2847 (match_operand:SI 1 "shadd_operand" ""))
2848 (plus:SI (match_operand:SI 2 "register_operand" "")
2849 (match_operand:SI 3 "const_int_operand" ""))))
2850 (match_operand:QI 4 "register_operand" ""))
2851 (clobber (match_operand:SI 5 "register_operand" ""))]
2853 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2855 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2858 (define_expand "movhi"
2859 [(set (match_operand:HI 0 "general_operand" "")
2860 (match_operand:HI 1 "general_operand" ""))]
2864 if (emit_move_sequence (operands, HImode, 0))
2869 [(set (match_operand:HI 0 "move_dest_operand"
2870 "=r,r,r,r,r,Q,!*q,!*f")
2871 (match_operand:HI 1 "move_src_operand"
2872 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2873 "register_operand (operands[0], HImode)
2874 || reg_or_0_operand (operands[1], HImode)"
2879 {zdepi|depwi,z} %Z1,%0
2884 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2885 (set_attr "pa_combine_type" "addmove")
2886 (set_attr "length" "4,4,4,4,4,4,4,4")])
2889 [(set (match_operand:HI 0 "register_operand" "=r")
2890 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2891 (match_operand:SI 2 "int5_operand" "L"))))
2893 (plus:SI (match_dup 1) (match_dup 2)))]
2895 "{ldhs|ldh},mb %2(%1),%0"
2896 [(set_attr "type" "load")
2897 (set_attr "length" "4")])
2900 [(set (match_operand:HI 0 "register_operand" "=r")
2901 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2902 (match_operand:DI 2 "int5_operand" "L"))))
2904 (plus:DI (match_dup 1) (match_dup 2)))]
2907 [(set_attr "type" "load")
2908 (set_attr "length" "4")])
2910 ; And a zero extended variant.
2912 [(set (match_operand:DI 0 "register_operand" "=r")
2913 (zero_extend:DI (mem:HI
2915 (match_operand:DI 1 "register_operand" "+r")
2916 (match_operand:DI 2 "int5_operand" "L")))))
2918 (plus:DI (match_dup 1) (match_dup 2)))]
2921 [(set_attr "type" "load")
2922 (set_attr "length" "4")])
2925 [(set (match_operand:SI 0 "register_operand" "=r")
2926 (zero_extend:SI (mem:HI
2928 (match_operand:SI 1 "register_operand" "+r")
2929 (match_operand:SI 2 "int5_operand" "L")))))
2931 (plus:SI (match_dup 1) (match_dup 2)))]
2933 "{ldhs|ldh},mb %2(%1),%0"
2934 [(set_attr "type" "load")
2935 (set_attr "length" "4")])
2938 [(set (match_operand:SI 0 "register_operand" "=r")
2939 (zero_extend:SI (mem:HI
2941 (match_operand:DI 1 "register_operand" "+r")
2942 (match_operand:DI 2 "int5_operand" "L")))))
2944 (plus:DI (match_dup 1) (match_dup 2)))]
2947 [(set_attr "type" "load")
2948 (set_attr "length" "4")])
2951 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2952 (match_operand:SI 1 "int5_operand" "L")))
2953 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2955 (plus:SI (match_dup 0) (match_dup 1)))]
2957 "{sths|sth},mb %r2,%1(%0)"
2958 [(set_attr "type" "store")
2959 (set_attr "length" "4")])
2962 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2963 (match_operand:DI 1 "int5_operand" "L")))
2964 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2966 (plus:DI (match_dup 0) (match_dup 1)))]
2969 [(set_attr "type" "store")
2970 (set_attr "length" "4")])
2973 [(set (match_operand:HI 0 "register_operand" "=r")
2974 (plus:HI (match_operand:HI 1 "register_operand" "r")
2975 (match_operand 2 "const_int_operand" "J")))]
2978 [(set_attr "type" "binary")
2979 (set_attr "pa_combine_type" "addmove")
2980 (set_attr "length" "4")])
2982 (define_expand "movqi"
2983 [(set (match_operand:QI 0 "general_operand" "")
2984 (match_operand:QI 1 "general_operand" ""))]
2988 if (emit_move_sequence (operands, QImode, 0))
2993 [(set (match_operand:QI 0 "move_dest_operand"
2994 "=r,r,r,r,r,Q,!*q,!*f")
2995 (match_operand:QI 1 "move_src_operand"
2996 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2997 "register_operand (operands[0], QImode)
2998 || reg_or_0_operand (operands[1], QImode)"
3003 {zdepi|depwi,z} %Z1,%0
3008 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
3009 (set_attr "pa_combine_type" "addmove")
3010 (set_attr "length" "4,4,4,4,4,4,4,4")])
3013 [(set (match_operand:QI 0 "register_operand" "=r")
3014 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3015 (match_operand:SI 2 "int5_operand" "L"))))
3016 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3018 "{ldbs|ldb},mb %2(%1),%0"
3019 [(set_attr "type" "load")
3020 (set_attr "length" "4")])
3023 [(set (match_operand:QI 0 "register_operand" "=r")
3024 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3025 (match_operand:DI 2 "int5_operand" "L"))))
3026 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3029 [(set_attr "type" "load")
3030 (set_attr "length" "4")])
3032 ; Now the same thing with zero extensions.
3034 [(set (match_operand:DI 0 "register_operand" "=r")
3035 (zero_extend:DI (mem:QI (plus:DI
3036 (match_operand:DI 1 "register_operand" "+r")
3037 (match_operand:DI 2 "int5_operand" "L")))))
3038 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3041 [(set_attr "type" "load")
3042 (set_attr "length" "4")])
3045 [(set (match_operand:SI 0 "register_operand" "=r")
3046 (zero_extend:SI (mem:QI (plus:SI
3047 (match_operand:SI 1 "register_operand" "+r")
3048 (match_operand:SI 2 "int5_operand" "L")))))
3049 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3051 "{ldbs|ldb},mb %2(%1),%0"
3052 [(set_attr "type" "load")
3053 (set_attr "length" "4")])
3056 [(set (match_operand:SI 0 "register_operand" "=r")
3057 (zero_extend:SI (mem:QI (plus:DI
3058 (match_operand:DI 1 "register_operand" "+r")
3059 (match_operand:DI 2 "int5_operand" "L")))))
3060 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3063 [(set_attr "type" "load")
3064 (set_attr "length" "4")])
3067 [(set (match_operand:HI 0 "register_operand" "=r")
3068 (zero_extend:HI (mem:QI (plus:SI
3069 (match_operand:SI 1 "register_operand" "+r")
3070 (match_operand:SI 2 "int5_operand" "L")))))
3071 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3073 "{ldbs|ldb},mb %2(%1),%0"
3074 [(set_attr "type" "load")
3075 (set_attr "length" "4")])
3078 [(set (match_operand:HI 0 "register_operand" "=r")
3079 (zero_extend:HI (mem:QI (plus:DI
3080 (match_operand:DI 1 "register_operand" "+r")
3081 (match_operand:DI 2 "int5_operand" "L")))))
3082 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3085 [(set_attr "type" "load")
3086 (set_attr "length" "4")])
3089 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3090 (match_operand:SI 1 "int5_operand" "L")))
3091 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3093 (plus:SI (match_dup 0) (match_dup 1)))]
3095 "{stbs|stb},mb %r2,%1(%0)"
3096 [(set_attr "type" "store")
3097 (set_attr "length" "4")])
3100 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3101 (match_operand:DI 1 "int5_operand" "L")))
3102 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3104 (plus:DI (match_dup 0) (match_dup 1)))]
3107 [(set_attr "type" "store")
3108 (set_attr "length" "4")])
3110 ;; The definition of this insn does not really explain what it does,
3111 ;; but it should suffice that anything generated as this insn will be
3112 ;; recognized as a movstrsi operation, and that it will not successfully
3113 ;; combine with anything.
3114 (define_expand "movstrsi"
3115 [(parallel [(set (match_operand:BLK 0 "" "")
3116 (match_operand:BLK 1 "" ""))
3117 (clobber (match_dup 4))
3118 (clobber (match_dup 5))
3119 (clobber (match_dup 6))
3120 (clobber (match_dup 7))
3121 (clobber (match_dup 8))
3122 (use (match_operand:SI 2 "arith_operand" ""))
3123 (use (match_operand:SI 3 "const_int_operand" ""))])]
3124 "!TARGET_64BIT && optimize > 0"
3129 /* HP provides very fast block move library routine for the PA;
3130 this routine includes:
3132 4x4 byte at a time block moves,
3133 1x4 byte at a time with alignment checked at runtime with
3134 attempts to align the source and destination as needed
3137 With that in mind, here's the heuristics to try and guess when
3138 the inlined block move will be better than the library block
3141 If the size isn't constant, then always use the library routines.
3143 If the size is large in respect to the known alignment, then use
3144 the library routines.
3146 If the size is small in respect to the known alignment, then open
3147 code the copy (since that will lead to better scheduling).
3149 Else use the block move pattern. */
3151 /* Undetermined size, use the library routine. */
3152 if (GET_CODE (operands[2]) != CONST_INT)
3155 size = INTVAL (operands[2]);
3156 align = INTVAL (operands[3]);
3157 align = align > 4 ? 4 : align;
3159 /* If size/alignment is large, then use the library routines. */
3160 if (size / align > 16)
3163 /* This does happen, but not often enough to worry much about. */
3164 if (size / align < MOVE_RATIO)
3167 /* Fall through means we're going to use our block move pattern. */
3169 = replace_equiv_address (operands[0],
3170 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3172 = replace_equiv_address (operands[1],
3173 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3174 operands[4] = gen_reg_rtx (SImode);
3175 operands[5] = gen_reg_rtx (SImode);
3176 operands[6] = gen_reg_rtx (SImode);
3177 operands[7] = gen_reg_rtx (SImode);
3178 operands[8] = gen_reg_rtx (SImode);
3181 ;; The operand constraints are written like this to support both compile-time
3182 ;; and run-time determined byte counts. The expander and output_block_move
3183 ;; only support compile-time determined counts at this time.
3185 ;; If the count is run-time determined, the register with the byte count
3186 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3188 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3189 ;; broke this semantic for pseudo registers. We can't use match_scratch
3190 ;; as this requires two registers in the class R1_REGS when the MEMs for
3191 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3192 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3193 ;; respectively. We then split or peephole optimize after reload.
3194 (define_insn "movstrsi_prereload"
3195 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3196 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3197 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3198 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3199 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3200 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3201 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3202 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3203 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3206 [(set_attr "type" "multi,multi")])
3209 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3210 (mem:BLK (match_operand:SI 1 "register_operand" "")))
3211 (clobber (match_operand:SI 2 "register_operand" ""))
3212 (clobber (match_operand:SI 3 "register_operand" ""))
3213 (clobber (match_operand:SI 6 "register_operand" ""))
3214 (clobber (match_operand:SI 7 "register_operand" ""))
3215 (clobber (match_operand:SI 8 "register_operand" ""))
3216 (use (match_operand:SI 4 "arith_operand" ""))
3217 (use (match_operand:SI 5 "const_int_operand" ""))])]
3218 "!TARGET_64BIT && reload_completed && !flag_peephole2"
3219 [(set (match_dup 7) (match_dup 0))
3220 (set (match_dup 8) (match_dup 1))
3221 (parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3222 (clobber (match_dup 2))
3223 (clobber (match_dup 3))
3224 (clobber (match_dup 6))
3225 (clobber (match_dup 7))
3226 (clobber (match_dup 8))
3233 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3234 (mem:BLK (match_operand:SI 1 "register_operand" "")))
3235 (clobber (match_operand:SI 2 "register_operand" ""))
3236 (clobber (match_operand:SI 3 "register_operand" ""))
3237 (clobber (match_operand:SI 6 "register_operand" ""))
3238 (clobber (match_operand:SI 7 "register_operand" ""))
3239 (clobber (match_operand:SI 8 "register_operand" ""))
3240 (use (match_operand:SI 4 "arith_operand" ""))
3241 (use (match_operand:SI 5 "const_int_operand" ""))])]
3243 [(parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3244 (clobber (match_dup 2))
3245 (clobber (match_dup 3))
3246 (clobber (match_dup 6))
3247 (clobber (match_dup 7))
3248 (clobber (match_dup 8))
3254 if (dead_or_set_p (curr_insn, operands[0]))
3255 operands[7] = operands[0];
3257 emit_insn (gen_rtx_SET (VOIDmode, operands[7], operands[0]));
3259 if (dead_or_set_p (curr_insn, operands[1]))
3260 operands[8] = operands[1];
3262 emit_insn (gen_rtx_SET (VOIDmode, operands[8], operands[1]));
3265 (define_insn "movstrsi_postreload"
3266 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3267 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3268 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3269 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3270 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3271 (clobber (match_dup 0))
3272 (clobber (match_dup 1))
3273 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3274 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3276 "!TARGET_64BIT && reload_completed"
3277 "* return output_block_move (operands, !which_alternative);"
3278 [(set_attr "type" "multi,multi")])
3280 (define_expand "movstrdi"
3281 [(parallel [(set (match_operand:BLK 0 "" "")
3282 (match_operand:BLK 1 "" ""))
3283 (clobber (match_dup 4))
3284 (clobber (match_dup 5))
3285 (clobber (match_dup 6))
3286 (clobber (match_dup 7))
3287 (clobber (match_dup 8))
3288 (use (match_operand:DI 2 "arith_operand" ""))
3289 (use (match_operand:DI 3 "const_int_operand" ""))])]
3290 "TARGET_64BIT && optimize > 0"
3295 /* HP provides very fast block move library routine for the PA;
3296 this routine includes:
3298 4x4 byte at a time block moves,
3299 1x4 byte at a time with alignment checked at runtime with
3300 attempts to align the source and destination as needed
3303 With that in mind, here's the heuristics to try and guess when
3304 the inlined block move will be better than the library block
3307 If the size isn't constant, then always use the library routines.
3309 If the size is large in respect to the known alignment, then use
3310 the library routines.
3312 If the size is small in respect to the known alignment, then open
3313 code the copy (since that will lead to better scheduling).
3315 Else use the block move pattern. */
3317 /* Undetermined size, use the library routine. */
3318 if (GET_CODE (operands[2]) != CONST_INT)
3321 size = INTVAL (operands[2]);
3322 align = INTVAL (operands[3]);
3323 align = align > 8 ? 8 : align;
3325 /* If size/alignment is large, then use the library routines. */
3326 if (size / align > 16)
3329 /* This does happen, but not often enough to worry much about. */
3330 if (size / align < MOVE_RATIO)
3333 /* Fall through means we're going to use our block move pattern. */
3335 = replace_equiv_address (operands[0],
3336 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3338 = replace_equiv_address (operands[1],
3339 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3340 operands[4] = gen_reg_rtx (DImode);
3341 operands[5] = gen_reg_rtx (DImode);
3342 operands[6] = gen_reg_rtx (DImode);
3343 operands[7] = gen_reg_rtx (DImode);
3344 operands[8] = gen_reg_rtx (DImode);
3347 ;; The operand constraints are written like this to support both compile-time
3348 ;; and run-time determined byte counts. The expander and output_block_move
3349 ;; only support compile-time determined counts at this time.
3351 ;; If the count is run-time determined, the register with the byte count
3352 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3354 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3355 ;; broke this semantic for pseudo registers. We can't use match_scratch
3356 ;; as this requires two registers in the class R1_REGS when the MEMs for
3357 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3358 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3359 ;; respectively. We then split or peephole optimize after reload.
3360 (define_insn "movstrdi_prereload"
3361 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3362 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3363 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3364 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3365 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3366 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3367 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3368 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3369 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3372 [(set_attr "type" "multi,multi")])
3375 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3376 (mem:BLK (match_operand:DI 1 "register_operand" "")))
3377 (clobber (match_operand:DI 2 "register_operand" ""))
3378 (clobber (match_operand:DI 3 "register_operand" ""))
3379 (clobber (match_operand:DI 6 "register_operand" ""))
3380 (clobber (match_operand:DI 7 "register_operand" ""))
3381 (clobber (match_operand:DI 8 "register_operand" ""))
3382 (use (match_operand:DI 4 "arith_operand" ""))
3383 (use (match_operand:DI 5 "const_int_operand" ""))])]
3384 "TARGET_64BIT && reload_completed && !flag_peephole2"
3385 [(set (match_dup 7) (match_dup 0))
3386 (set (match_dup 8) (match_dup 1))
3387 (parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3388 (clobber (match_dup 2))
3389 (clobber (match_dup 3))
3390 (clobber (match_dup 6))
3391 (clobber (match_dup 7))
3392 (clobber (match_dup 8))
3399 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3400 (mem:BLK (match_operand:DI 1 "register_operand" "")))
3401 (clobber (match_operand:DI 2 "register_operand" ""))
3402 (clobber (match_operand:DI 3 "register_operand" ""))
3403 (clobber (match_operand:DI 6 "register_operand" ""))
3404 (clobber (match_operand:DI 7 "register_operand" ""))
3405 (clobber (match_operand:DI 8 "register_operand" ""))
3406 (use (match_operand:DI 4 "arith_operand" ""))
3407 (use (match_operand:DI 5 "const_int_operand" ""))])]
3409 [(parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3410 (clobber (match_dup 2))
3411 (clobber (match_dup 3))
3412 (clobber (match_dup 6))
3413 (clobber (match_dup 7))
3414 (clobber (match_dup 8))
3420 if (dead_or_set_p (curr_insn, operands[0]))
3421 operands[7] = operands[0];
3423 emit_insn (gen_rtx_SET (VOIDmode, operands[7], operands[0]));
3425 if (dead_or_set_p (curr_insn, operands[1]))
3426 operands[8] = operands[1];
3428 emit_insn (gen_rtx_SET (VOIDmode, operands[8], operands[1]));
3431 (define_insn "movstrdi_postreload"
3432 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3433 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3434 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3435 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3436 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3437 (clobber (match_dup 0))
3438 (clobber (match_dup 1))
3439 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3440 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3442 "TARGET_64BIT && reload_completed"
3443 "* return output_block_move (operands, !which_alternative);"
3444 [(set_attr "type" "multi,multi")])
3446 (define_expand "clrstrsi"
3447 [(parallel [(set (match_operand:BLK 0 "" "")
3449 (clobber (match_dup 3))
3450 (clobber (match_dup 4))
3451 (use (match_operand:SI 1 "arith_operand" ""))
3452 (use (match_operand:SI 2 "const_int_operand" ""))])]
3453 "!TARGET_64BIT && optimize > 0"
3458 /* Undetermined size, use the library routine. */
3459 if (GET_CODE (operands[1]) != CONST_INT)
3462 size = INTVAL (operands[1]);
3463 align = INTVAL (operands[2]);
3464 align = align > 4 ? 4 : align;
3466 /* If size/alignment is large, then use the library routines. */
3467 if (size / align > 16)
3470 /* This does happen, but not often enough to worry much about. */
3471 if (size / align < MOVE_RATIO)
3474 /* Fall through means we're going to use our block clear pattern. */
3476 = replace_equiv_address (operands[0],
3477 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3478 operands[3] = gen_reg_rtx (SImode);
3479 operands[4] = gen_reg_rtx (SImode);
3482 (define_insn "clrstrsi_prereload"
3483 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3485 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3486 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3487 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3488 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3491 [(set_attr "type" "multi,multi")])
3494 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3496 (clobber (match_operand:SI 1 "register_operand" ""))
3497 (clobber (match_operand:SI 4 "register_operand" ""))
3498 (use (match_operand:SI 2 "arith_operand" ""))
3499 (use (match_operand:SI 3 "const_int_operand" ""))])]
3500 "!TARGET_64BIT && reload_completed && !flag_peephole2"
3501 [(set (match_dup 4) (match_dup 0))
3502 (parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3503 (clobber (match_dup 1))
3504 (clobber (match_dup 4))
3511 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3513 (clobber (match_operand:SI 1 "register_operand" ""))
3514 (clobber (match_operand:SI 4 "register_operand" ""))
3515 (use (match_operand:SI 2 "arith_operand" ""))
3516 (use (match_operand:SI 3 "const_int_operand" ""))])]
3518 [(parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3519 (clobber (match_dup 1))
3520 (clobber (match_dup 4))
3526 if (dead_or_set_p (curr_insn, operands[0]))
3527 operands[4] = operands[0];
3529 emit_insn (gen_rtx_SET (VOIDmode, operands[4], operands[0]));
3532 (define_insn "clrstrsi_postreload"
3533 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3535 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3536 (clobber (match_dup 0))
3537 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3538 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3540 "!TARGET_64BIT && reload_completed"
3541 "* return output_block_clear (operands, !which_alternative);"
3542 [(set_attr "type" "multi,multi")])
3544 (define_expand "clrstrdi"
3545 [(parallel [(set (match_operand:BLK 0 "" "")
3547 (clobber (match_dup 3))
3548 (clobber (match_dup 4))
3549 (use (match_operand:DI 1 "arith_operand" ""))
3550 (use (match_operand:DI 2 "const_int_operand" ""))])]
3551 "TARGET_64BIT && optimize > 0"
3556 /* Undetermined size, use the library routine. */
3557 if (GET_CODE (operands[1]) != CONST_INT)
3560 size = INTVAL (operands[1]);
3561 align = INTVAL (operands[2]);
3562 align = align > 8 ? 8 : align;
3564 /* If size/alignment is large, then use the library routines. */
3565 if (size / align > 16)
3568 /* This does happen, but not often enough to worry much about. */
3569 if (size / align < MOVE_RATIO)
3572 /* Fall through means we're going to use our block clear pattern. */
3574 = replace_equiv_address (operands[0],
3575 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3576 operands[3] = gen_reg_rtx (DImode);
3577 operands[4] = gen_reg_rtx (DImode);
3580 (define_insn "clrstrdi_prereload"
3581 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3583 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3584 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3585 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3586 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3589 [(set_attr "type" "multi,multi")])
3592 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3594 (clobber (match_operand:DI 1 "register_operand" ""))
3595 (clobber (match_operand:DI 4 "register_operand" ""))
3596 (use (match_operand:DI 2 "arith_operand" ""))
3597 (use (match_operand:DI 3 "const_int_operand" ""))])]
3598 "TARGET_64BIT && reload_completed && !flag_peephole2"
3599 [(set (match_dup 4) (match_dup 0))
3600 (parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3601 (clobber (match_dup 1))
3602 (clobber (match_dup 4))
3609 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3611 (clobber (match_operand:DI 1 "register_operand" ""))
3612 (clobber (match_operand:DI 4 "register_operand" ""))
3613 (use (match_operand:DI 2 "arith_operand" ""))
3614 (use (match_operand:DI 3 "const_int_operand" ""))])]
3616 [(parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3617 (clobber (match_dup 1))
3618 (clobber (match_dup 4))
3624 if (dead_or_set_p (curr_insn, operands[0]))
3625 operands[4] = operands[0];
3627 emit_insn (gen_rtx_SET (VOIDmode, operands[4], operands[0]));
3630 (define_insn "clrstrdi_postreload"
3631 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3633 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3634 (clobber (match_dup 0))
3635 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3636 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3638 "TARGET_64BIT && reload_completed"
3639 "* return output_block_clear (operands, !which_alternative);"
3640 [(set_attr "type" "multi,multi")])
3642 ;; Floating point move insns
3644 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3645 ;; to be reloaded by putting the constant into memory when
3646 ;; reg is a floating point register.
3648 ;; For integer registers we use ldil;ldo to set the appropriate
3651 ;; This must come before the movdf pattern, and it must be present
3652 ;; to handle obscure reloading cases.
3654 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3655 (match_operand:DF 1 "" "?F,m"))]
3656 "GET_CODE (operands[1]) == CONST_DOUBLE
3657 && operands[1] != CONST0_RTX (DFmode)
3659 && !TARGET_SOFT_FLOAT"
3660 "* return (which_alternative == 0 ? output_move_double (operands)
3661 : \"fldd%F1 %1,%0\");"
3662 [(set_attr "type" "move,fpload")
3663 (set_attr "length" "16,4")])
3665 (define_expand "movdf"
3666 [(set (match_operand:DF 0 "general_operand" "")
3667 (match_operand:DF 1 "general_operand" ""))]
3671 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3672 operands[1] = force_const_mem (DFmode, operands[1]);
3674 if (emit_move_sequence (operands, DFmode, 0))
3678 ;; Reloading an SImode or DImode value requires a scratch register if
3679 ;; going in to or out of float point registers.
3681 (define_expand "reload_indf"
3682 [(set (match_operand:DF 0 "register_operand" "=Z")
3683 (match_operand:DF 1 "non_hard_reg_operand" ""))
3684 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3688 if (emit_move_sequence (operands, DFmode, operands[2]))
3691 /* We don't want the clobber emitted, so handle this ourselves. */
3692 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3696 (define_expand "reload_outdf"
3697 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3698 (match_operand:DF 1 "register_operand" "Z"))
3699 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3703 if (emit_move_sequence (operands, DFmode, operands[2]))
3706 /* We don't want the clobber emitted, so handle this ourselves. */
3707 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3712 [(set (match_operand:DF 0 "move_dest_operand"
3713 "=f,*r,Q,?o,?Q,f,*r,*r")
3714 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3715 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3716 "(register_operand (operands[0], DFmode)
3717 || reg_or_0_operand (operands[1], DFmode))
3718 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3719 && GET_CODE (operands[0]) == MEM)
3721 && !TARGET_SOFT_FLOAT"
3724 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3725 || operands[1] == CONST0_RTX (DFmode))
3726 return output_fp_move_double (operands);
3727 return output_move_double (operands);
3729 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3730 (set_attr "length" "4,8,4,8,16,4,8,16")])
3733 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3734 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3736 && !TARGET_DISABLE_INDEXING
3737 && reload_completed"
3739 [(set_attr "type" "fpstore")
3740 (set_attr "pa_combine_type" "addmove")
3741 (set_attr "length" "4")])
3744 [(set (match_operand:SI 0 "register_operand" "")
3745 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3747 (match_operand:SI 2 "register_operand" "")))
3748 (set (mem:DF (match_dup 0))
3749 (match_operand:DF 3 "register_operand" ""))]
3751 && REG_OK_FOR_BASE_P (operands[2])
3752 && FP_REGNO_P (REGNO (operands[3]))"
3753 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3755 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3760 [(set (match_operand:SI 0 "register_operand" "")
3761 (plus:SI (match_operand:SI 2 "register_operand" "")
3762 (mult:SI (match_operand:SI 1 "register_operand" "")
3764 (set (mem:DF (match_dup 0))
3765 (match_operand:DF 3 "register_operand" ""))]
3767 && REG_OK_FOR_BASE_P (operands[2])
3768 && FP_REGNO_P (REGNO (operands[3]))"
3769 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3771 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3776 [(set (match_operand:DI 0 "register_operand" "")
3777 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3779 (match_operand:DI 2 "register_operand" "")))
3780 (set (mem:DF (match_dup 0))
3781 (match_operand:DF 3 "register_operand" ""))]
3784 && REG_OK_FOR_BASE_P (operands[2])
3785 && FP_REGNO_P (REGNO (operands[3]))"
3786 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3788 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3793 [(set (match_operand:DI 0 "register_operand" "")
3794 (plus:DI (match_operand:DI 2 "register_operand" "")
3795 (mult:DI (match_operand:DI 1 "register_operand" "")
3797 (set (mem:DF (match_dup 0))
3798 (match_operand:DF 3 "register_operand" ""))]
3801 && REG_OK_FOR_BASE_P (operands[2])
3802 && FP_REGNO_P (REGNO (operands[3]))"
3803 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3805 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3810 [(set (match_operand:SI 0 "register_operand" "")
3811 (plus:SI (match_operand:SI 1 "register_operand" "")
3812 (match_operand:SI 2 "register_operand" "")))
3813 (set (mem:DF (match_dup 0))
3814 (match_operand:DF 3 "register_operand" ""))]
3816 && REG_OK_FOR_BASE_P (operands[1])
3817 && (TARGET_NO_SPACE_REGS
3818 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3819 && FP_REGNO_P (REGNO (operands[3]))"
3820 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3822 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3826 [(set (match_operand:SI 0 "register_operand" "")
3827 (plus:SI (match_operand:SI 1 "register_operand" "")
3828 (match_operand:SI 2 "register_operand" "")))
3829 (set (mem:DF (match_dup 0))
3830 (match_operand:DF 3 "register_operand" ""))]
3832 && REG_OK_FOR_BASE_P (operands[2])
3833 && (TARGET_NO_SPACE_REGS
3834 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3835 && FP_REGNO_P (REGNO (operands[3]))"
3836 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3838 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3842 [(set (match_operand:DI 0 "register_operand" "")
3843 (plus:DI (match_operand:DI 1 "register_operand" "")
3844 (match_operand:DI 2 "register_operand" "")))
3845 (set (mem:DF (match_dup 0))
3846 (match_operand:DF 3 "register_operand" ""))]
3849 && REG_OK_FOR_BASE_P (operands[1])
3850 && (TARGET_NO_SPACE_REGS
3851 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3852 && FP_REGNO_P (REGNO (operands[3]))"
3853 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3855 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3859 [(set (match_operand:DI 0 "register_operand" "")
3860 (plus:DI (match_operand:DI 1 "register_operand" "")
3861 (match_operand:DI 2 "register_operand" "")))
3862 (set (mem:DF (match_dup 0))
3863 (match_operand:DF 3 "register_operand" ""))]
3866 && REG_OK_FOR_BASE_P (operands[2])
3867 && (TARGET_NO_SPACE_REGS
3868 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3869 && FP_REGNO_P (REGNO (operands[3]))"
3870 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3872 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3876 [(set (match_operand:DF 0 "move_dest_operand"
3878 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3880 "(register_operand (operands[0], DFmode)
3881 || reg_or_0_operand (operands[1], DFmode))
3883 && TARGET_SOFT_FLOAT"
3886 return output_move_double (operands);
3888 [(set_attr "type" "move,store,store,load,load")
3889 (set_attr "length" "8,8,16,8,16")])
3892 [(set (match_operand:DF 0 "move_dest_operand"
3893 "=!*r,*r,*r,*r,*r,Q,!*q,f,f,T")
3894 (match_operand:DF 1 "move_src_operand"
3895 "!*r,J,N,K,RQ,*rM,!*rM,fM,RT,f"))]
3896 "(register_operand (operands[0], DFmode)
3897 || reg_or_0_operand (operands[1], DFmode))
3898 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3910 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3911 (set_attr "pa_combine_type" "addmove")
3912 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3915 (define_expand "movdi"
3916 [(set (match_operand:DI 0 "general_operand" "")
3917 (match_operand:DI 1 "general_operand" ""))]
3921 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3922 operands[1] = force_const_mem (DImode, operands[1]);
3924 if (emit_move_sequence (operands, DImode, 0))
3928 (define_expand "reload_indi"
3929 [(set (match_operand:DI 0 "register_operand" "=Z")
3930 (match_operand:DI 1 "non_hard_reg_operand" ""))
3931 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3935 if (emit_move_sequence (operands, DImode, operands[2]))
3938 /* We don't want the clobber emitted, so handle this ourselves. */
3939 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3943 (define_expand "reload_outdi"
3944 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
3945 (match_operand:DI 1 "register_operand" "Z"))
3946 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3950 if (emit_move_sequence (operands, DImode, operands[2]))
3953 /* We don't want the clobber emitted, so handle this ourselves. */
3954 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3959 [(set (match_operand:DI 0 "register_operand" "=r")
3960 (high:DI (match_operand 1 "" "")))]
3964 rtx op0 = operands[0];
3965 rtx op1 = operands[1];
3967 if (GET_CODE (op1) == CONST_INT)
3969 operands[0] = operand_subword (op0, 1, 0, DImode);
3970 output_asm_insn (\"ldil L'%1,%0\", operands);
3972 operands[0] = operand_subword (op0, 0, 0, DImode);
3973 if (INTVAL (op1) < 0)
3974 output_asm_insn (\"ldi -1,%0\", operands);
3976 output_asm_insn (\"ldi 0,%0\", operands);
3979 else if (GET_CODE (op1) == CONST_DOUBLE)
3981 operands[0] = operand_subword (op0, 1, 0, DImode);
3982 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3983 output_asm_insn (\"ldil L'%1,%0\", operands);
3985 operands[0] = operand_subword (op0, 0, 0, DImode);
3986 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3987 output_asm_insn (singlemove_string (operands), operands);
3993 [(set_attr "type" "move")
3994 (set_attr "length" "8")])
3997 [(set (match_operand:DI 0 "move_dest_operand"
3998 "=r,o,Q,r,r,r,*f,*f,T")
3999 (match_operand:DI 1 "general_operand"
4000 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4001 "(register_operand (operands[0], DImode)
4002 || reg_or_0_operand (operands[1], DImode))
4004 && !TARGET_SOFT_FLOAT"
4007 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4008 || (operands[1] == CONST0_RTX (DImode)))
4009 return output_fp_move_double (operands);
4010 return output_move_double (operands);
4012 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4013 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4016 [(set (match_operand:DI 0 "move_dest_operand"
4017 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
4018 (match_operand:DI 1 "move_src_operand"
4019 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
4020 "(register_operand (operands[0], DImode)
4021 || reg_or_0_operand (operands[1], DImode))
4022 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4035 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
4036 (set_attr "pa_combine_type" "addmove")
4037 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
4040 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4041 (match_operand:DI 1 "register_operand" "f"))]
4044 && !TARGET_DISABLE_INDEXING
4045 && reload_completed"
4047 [(set_attr "type" "fpstore")
4048 (set_attr "pa_combine_type" "addmove")
4049 (set_attr "length" "4")])
4052 [(set (match_operand:DI 0 "register_operand" "")
4053 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4055 (match_operand:DI 2 "register_operand" "")))
4056 (set (mem:DI (match_dup 0))
4057 (match_operand:DI 3 "register_operand" ""))]
4060 && REG_OK_FOR_BASE_P (operands[2])
4061 && FP_REGNO_P (REGNO (operands[3]))"
4062 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4064 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4069 [(set (match_operand:DI 0 "register_operand" "")
4070 (plus:DI (match_operand:DI 2 "register_operand" "")
4071 (mult:DI (match_operand:DI 1 "register_operand" "")
4073 (set (mem:DI (match_dup 0))
4074 (match_operand:DI 3 "register_operand" ""))]
4077 && REG_OK_FOR_BASE_P (operands[2])
4078 && FP_REGNO_P (REGNO (operands[3]))"
4079 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4081 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4086 [(set (match_operand:DI 0 "register_operand" "")
4087 (plus:DI (match_operand:DI 1 "register_operand" "")
4088 (match_operand:DI 2 "register_operand" "")))
4089 (set (mem:DI (match_dup 0))
4090 (match_operand:DI 3 "register_operand" ""))]
4093 && REG_OK_FOR_BASE_P (operands[1])
4094 && (TARGET_NO_SPACE_REGS
4095 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4096 && FP_REGNO_P (REGNO (operands[3]))"
4097 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4099 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4103 [(set (match_operand:DI 0 "register_operand" "")
4104 (plus:DI (match_operand:DI 1 "register_operand" "")
4105 (match_operand:DI 2 "register_operand" "")))
4106 (set (mem:DI (match_dup 0))
4107 (match_operand:DI 3 "register_operand" ""))]
4110 && REG_OK_FOR_BASE_P (operands[2])
4111 && (TARGET_NO_SPACE_REGS
4112 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4113 && FP_REGNO_P (REGNO (operands[3]))"
4114 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4116 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4120 [(set (match_operand:DI 0 "move_dest_operand"
4122 (match_operand:DI 1 "general_operand"
4124 "(register_operand (operands[0], DImode)
4125 || reg_or_0_operand (operands[1], DImode))
4127 && TARGET_SOFT_FLOAT"
4130 return output_move_double (operands);
4132 [(set_attr "type" "move,store,store,load,load,multi")
4133 (set_attr "length" "8,8,16,8,16,16")])
4136 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4137 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4138 (match_operand:DI 2 "immediate_operand" "i,i")))]
4142 /* Don't output a 64 bit constant, since we can't trust the assembler to
4143 handle it correctly. */
4144 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4145 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4146 if (which_alternative == 1)
4147 output_asm_insn (\"copy %1,%0\", operands);
4148 return \"ldo R'%G2(%R1),%R0\";
4150 [(set_attr "type" "move,move")
4151 (set_attr "length" "4,8")])
4153 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4154 ;; to be reloaded by putting the constant into memory when
4155 ;; reg is a floating point register.
4157 ;; For integer registers we use ldil;ldo to set the appropriate
4160 ;; This must come before the movsf pattern, and it must be present
4161 ;; to handle obscure reloading cases.
4163 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4164 (match_operand:SF 1 "" "?F,m"))]
4165 "GET_CODE (operands[1]) == CONST_DOUBLE
4166 && operands[1] != CONST0_RTX (SFmode)
4167 && ! TARGET_SOFT_FLOAT"
4168 "* return (which_alternative == 0 ? singlemove_string (operands)
4169 : \" fldw%F1 %1,%0\");"
4170 [(set_attr "type" "move,fpload")
4171 (set_attr "length" "8,4")])
4173 (define_expand "movsf"
4174 [(set (match_operand:SF 0 "general_operand" "")
4175 (match_operand:SF 1 "general_operand" ""))]
4179 if (emit_move_sequence (operands, SFmode, 0))
4183 ;; Reloading an SImode or DImode value requires a scratch register if
4184 ;; going in to or out of float point registers.
4186 (define_expand "reload_insf"
4187 [(set (match_operand:SF 0 "register_operand" "=Z")
4188 (match_operand:SF 1 "non_hard_reg_operand" ""))
4189 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4193 if (emit_move_sequence (operands, SFmode, operands[2]))
4196 /* We don't want the clobber emitted, so handle this ourselves. */
4197 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4201 (define_expand "reload_outsf"
4202 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4203 (match_operand:SF 1 "register_operand" "Z"))
4204 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4208 if (emit_move_sequence (operands, SFmode, operands[2]))
4211 /* We don't want the clobber emitted, so handle this ourselves. */
4212 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4217 [(set (match_operand:SF 0 "move_dest_operand"
4219 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4220 "fG,!*rG,RQ,RQ,f,*rG"))]
4221 "(register_operand (operands[0], SFmode)
4222 || reg_or_0_operand (operands[1], SFmode))
4223 && !TARGET_SOFT_FLOAT"
4231 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4232 (set_attr "pa_combine_type" "addmove")
4233 (set_attr "length" "4,4,4,4,4,4")])
4236 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4237 (match_operand:SF 1 "register_operand" "f"))]
4239 && !TARGET_DISABLE_INDEXING
4240 && reload_completed"
4242 [(set_attr "type" "fpstore")
4243 (set_attr "pa_combine_type" "addmove")
4244 (set_attr "length" "4")])
4247 [(set (match_operand:SI 0 "register_operand" "")
4248 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4250 (match_operand:SI 2 "register_operand" "")))
4251 (set (mem:SF (match_dup 0))
4252 (match_operand:SF 3 "register_operand" ""))]
4254 && REG_OK_FOR_BASE_P (operands[2])
4255 && FP_REGNO_P (REGNO (operands[3]))"
4256 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4258 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4263 [(set (match_operand:SI 0 "register_operand" "")
4264 (plus:SI (match_operand:SI 2 "register_operand" "")
4265 (mult:SI (match_operand:SI 1 "register_operand" "")
4267 (set (mem:SF (match_dup 0))
4268 (match_operand:SF 3 "register_operand" ""))]
4270 && REG_OK_FOR_BASE_P (operands[2])
4271 && FP_REGNO_P (REGNO (operands[3]))"
4272 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4274 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4279 [(set (match_operand:DI 0 "register_operand" "")
4280 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4282 (match_operand:DI 2 "register_operand" "")))
4283 (set (mem:SF (match_dup 0))
4284 (match_operand:SF 3 "register_operand" ""))]
4287 && REG_OK_FOR_BASE_P (operands[2])
4288 && FP_REGNO_P (REGNO (operands[3]))"
4289 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4291 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4296 [(set (match_operand:DI 0 "register_operand" "")
4297 (plus:DI (match_operand:DI 2 "register_operand" "")
4298 (mult:DI (match_operand:DI 1 "register_operand" "")
4300 (set (mem:SF (match_dup 0))
4301 (match_operand:SF 3 "register_operand" ""))]
4304 && REG_OK_FOR_BASE_P (operands[2])
4305 && FP_REGNO_P (REGNO (operands[3]))"
4306 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4308 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4313 [(set (match_operand:SI 0 "register_operand" "")
4314 (plus:SI (match_operand:SI 1 "register_operand" "")
4315 (match_operand:SI 2 "register_operand" "")))
4316 (set (mem:SF (match_dup 0))
4317 (match_operand:SF 3 "register_operand" ""))]
4319 && REG_OK_FOR_BASE_P (operands[1])
4320 && (TARGET_NO_SPACE_REGS
4321 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4322 && FP_REGNO_P (REGNO (operands[3]))"
4323 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4325 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4329 [(set (match_operand:SI 0 "register_operand" "")
4330 (plus:SI (match_operand:SI 1 "register_operand" "")
4331 (match_operand:SI 2 "register_operand" "")))
4332 (set (mem:SF (match_dup 0))
4333 (match_operand:SF 3 "register_operand" ""))]
4335 && REG_OK_FOR_BASE_P (operands[2])
4336 && (TARGET_NO_SPACE_REGS
4337 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4338 && FP_REGNO_P (REGNO (operands[3]))"
4339 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4341 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4345 [(set (match_operand:DI 0 "register_operand" "")
4346 (plus:DI (match_operand:DI 1 "register_operand" "")
4347 (match_operand:DI 2 "register_operand" "")))
4348 (set (mem:SF (match_dup 0))
4349 (match_operand:SF 3 "register_operand" ""))]
4352 && REG_OK_FOR_BASE_P (operands[1])
4353 && (TARGET_NO_SPACE_REGS
4354 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4355 && FP_REGNO_P (REGNO (operands[3]))"
4356 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4358 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4362 [(set (match_operand:DI 0 "register_operand" "")
4363 (plus:DI (match_operand:DI 1 "register_operand" "")
4364 (match_operand:DI 2 "register_operand" "")))
4365 (set (mem:SF (match_dup 0))
4366 (match_operand:SF 3 "register_operand" ""))]
4369 && REG_OK_FOR_BASE_P (operands[2])
4370 && (TARGET_NO_SPACE_REGS
4371 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4372 && FP_REGNO_P (REGNO (operands[3]))"
4373 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4375 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4379 [(set (match_operand:SF 0 "move_dest_operand"
4381 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4383 "(register_operand (operands[0], SFmode)
4384 || reg_or_0_operand (operands[1], SFmode))
4385 && TARGET_SOFT_FLOAT"
4390 [(set_attr "type" "move,load,store")
4391 (set_attr "pa_combine_type" "addmove")
4392 (set_attr "length" "4,4,4")])
4396 ;;- zero extension instructions
4397 ;; We have define_expand for zero extension patterns to make sure the
4398 ;; operands get loaded into registers. The define_insns accept
4399 ;; memory operands. This gives us better overall code than just
4400 ;; having a pattern that does or does not accept memory operands.
4402 (define_expand "zero_extendqihi2"
4403 [(set (match_operand:HI 0 "register_operand" "")
4405 (match_operand:QI 1 "register_operand" "")))]
4410 [(set (match_operand:HI 0 "register_operand" "=r,r")
4412 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4413 "GET_CODE (operands[1]) != CONST_INT"
4415 {extru|extrw,u} %1,31,8,%0
4417 [(set_attr "type" "shift,load")
4418 (set_attr "length" "4,4")])
4420 (define_expand "zero_extendqisi2"
4421 [(set (match_operand:SI 0 "register_operand" "")
4423 (match_operand:QI 1 "register_operand" "")))]
4428 [(set (match_operand:SI 0 "register_operand" "=r,r")
4430 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4431 "GET_CODE (operands[1]) != CONST_INT"
4433 {extru|extrw,u} %1,31,8,%0
4435 [(set_attr "type" "shift,load")
4436 (set_attr "length" "4,4")])
4438 (define_expand "zero_extendhisi2"
4439 [(set (match_operand:SI 0 "register_operand" "")
4441 (match_operand:HI 1 "register_operand" "")))]
4446 [(set (match_operand:SI 0 "register_operand" "=r,r")
4448 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4449 "GET_CODE (operands[1]) != CONST_INT"
4451 {extru|extrw,u} %1,31,16,%0
4453 [(set_attr "type" "shift,load")
4454 (set_attr "length" "4,4")])
4456 (define_expand "zero_extendqidi2"
4457 [(set (match_operand:DI 0 "register_operand" "")
4459 (match_operand:QI 1 "register_operand" "")))]
4464 [(set (match_operand:DI 0 "register_operand" "=r,r")
4466 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4467 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4471 [(set_attr "type" "shift,load")
4472 (set_attr "length" "4,4")])
4474 (define_expand "zero_extendhidi2"
4475 [(set (match_operand:DI 0 "register_operand" "")
4477 (match_operand:HI 1 "register_operand" "")))]
4482 [(set (match_operand:DI 0 "register_operand" "=r,r")
4484 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4485 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4489 [(set_attr "type" "shift,load")
4490 (set_attr "length" "4,4")])
4492 (define_expand "zero_extendsidi2"
4493 [(set (match_operand:DI 0 "register_operand" "")
4495 (match_operand:SI 1 "register_operand" "")))]
4500 [(set (match_operand:DI 0 "register_operand" "=r,r")
4502 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4503 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4507 [(set_attr "type" "shift,load")
4508 (set_attr "length" "4,4")])
4510 ;;- sign extension instructions
4512 (define_insn "extendhisi2"
4513 [(set (match_operand:SI 0 "register_operand" "=r")
4514 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4516 "{extrs|extrw,s} %1,31,16,%0"
4517 [(set_attr "type" "shift")
4518 (set_attr "length" "4")])
4520 (define_insn "extendqihi2"
4521 [(set (match_operand:HI 0 "register_operand" "=r")
4522 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4524 "{extrs|extrw,s} %1,31,8,%0"
4525 [(set_attr "type" "shift")
4526 (set_attr "length" "4")])
4528 (define_insn "extendqisi2"
4529 [(set (match_operand:SI 0 "register_operand" "=r")
4530 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4532 "{extrs|extrw,s} %1,31,8,%0"
4533 [(set_attr "type" "shift")
4534 (set_attr "length" "4")])
4536 (define_insn "extendqidi2"
4537 [(set (match_operand:DI 0 "register_operand" "=r")
4538 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4540 "extrd,s %1,63,8,%0"
4541 [(set_attr "type" "shift")
4542 (set_attr "length" "4")])
4544 (define_insn "extendhidi2"
4545 [(set (match_operand:DI 0 "register_operand" "=r")
4546 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4548 "extrd,s %1,63,16,%0"
4549 [(set_attr "type" "shift")
4550 (set_attr "length" "4")])
4552 (define_insn "extendsidi2"
4553 [(set (match_operand:DI 0 "register_operand" "=r")
4554 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4556 "extrd,s %1,63,32,%0"
4557 [(set_attr "type" "shift")
4558 (set_attr "length" "4")])
4561 ;; Conversions between float and double.
4563 (define_insn "extendsfdf2"
4564 [(set (match_operand:DF 0 "register_operand" "=f")
4566 (match_operand:SF 1 "register_operand" "f")))]
4567 "! TARGET_SOFT_FLOAT"
4568 "{fcnvff|fcnv},sgl,dbl %1,%0"
4569 [(set_attr "type" "fpalu")
4570 (set_attr "length" "4")])
4572 (define_insn "truncdfsf2"
4573 [(set (match_operand:SF 0 "register_operand" "=f")
4575 (match_operand:DF 1 "register_operand" "f")))]
4576 "! TARGET_SOFT_FLOAT"
4577 "{fcnvff|fcnv},dbl,sgl %1,%0"
4578 [(set_attr "type" "fpalu")
4579 (set_attr "length" "4")])
4581 ;; Conversion between fixed point and floating point.
4582 ;; Note that among the fix-to-float insns
4583 ;; the ones that start with SImode come first.
4584 ;; That is so that an operand that is a CONST_INT
4585 ;; (and therefore lacks a specific machine mode).
4586 ;; will be recognized as SImode (which is always valid)
4587 ;; rather than as QImode or HImode.
4589 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4590 ;; to be reloaded by putting the constant into memory.
4591 ;; It must come before the more general floatsisf2 pattern.
4593 [(set (match_operand:SF 0 "register_operand" "=f")
4594 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4595 "! TARGET_SOFT_FLOAT"
4596 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4597 [(set_attr "type" "fpalu")
4598 (set_attr "length" "8")])
4600 (define_insn "floatsisf2"
4601 [(set (match_operand:SF 0 "register_operand" "=f")
4602 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4603 "! TARGET_SOFT_FLOAT"
4604 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4605 [(set_attr "type" "fpalu")
4606 (set_attr "length" "4")])
4608 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4609 ;; to be reloaded by putting the constant into memory.
4610 ;; It must come before the more general floatsidf2 pattern.
4612 [(set (match_operand:DF 0 "register_operand" "=f")
4613 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4614 "! TARGET_SOFT_FLOAT"
4615 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4616 [(set_attr "type" "fpalu")
4617 (set_attr "length" "8")])
4619 (define_insn "floatsidf2"
4620 [(set (match_operand:DF 0 "register_operand" "=f")
4621 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4622 "! TARGET_SOFT_FLOAT"
4623 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4624 [(set_attr "type" "fpalu")
4625 (set_attr "length" "4")])
4627 (define_expand "floatunssisf2"
4628 [(set (subreg:SI (match_dup 2) 4)
4629 (match_operand:SI 1 "register_operand" ""))
4630 (set (subreg:SI (match_dup 2) 0)
4632 (set (match_operand:SF 0 "register_operand" "")
4633 (float:SF (match_dup 2)))]
4634 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4639 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4642 operands[2] = gen_reg_rtx (DImode);
4645 (define_expand "floatunssidf2"
4646 [(set (subreg:SI (match_dup 2) 4)
4647 (match_operand:SI 1 "register_operand" ""))
4648 (set (subreg:SI (match_dup 2) 0)
4650 (set (match_operand:DF 0 "register_operand" "")
4651 (float:DF (match_dup 2)))]
4652 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4657 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4660 operands[2] = gen_reg_rtx (DImode);
4663 (define_insn "floatdisf2"
4664 [(set (match_operand:SF 0 "register_operand" "=f")
4665 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4666 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4667 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4668 [(set_attr "type" "fpalu")
4669 (set_attr "length" "4")])
4671 (define_insn "floatdidf2"
4672 [(set (match_operand:DF 0 "register_operand" "=f")
4673 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4674 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4675 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4676 [(set_attr "type" "fpalu")
4677 (set_attr "length" "4")])
4679 ;; Convert a float to an actual integer.
4680 ;; Truncation is performed as part of the conversion.
4682 (define_insn "fix_truncsfsi2"
4683 [(set (match_operand:SI 0 "register_operand" "=f")
4684 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4685 "! TARGET_SOFT_FLOAT"
4686 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4687 [(set_attr "type" "fpalu")
4688 (set_attr "length" "4")])
4690 (define_insn "fix_truncdfsi2"
4691 [(set (match_operand:SI 0 "register_operand" "=f")
4692 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4693 "! TARGET_SOFT_FLOAT"
4694 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4695 [(set_attr "type" "fpalu")
4696 (set_attr "length" "4")])
4698 (define_insn "fix_truncsfdi2"
4699 [(set (match_operand:DI 0 "register_operand" "=f")
4700 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4701 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4702 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4703 [(set_attr "type" "fpalu")
4704 (set_attr "length" "4")])
4706 (define_insn "fix_truncdfdi2"
4707 [(set (match_operand:DI 0 "register_operand" "=f")
4708 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4709 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4710 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4711 [(set_attr "type" "fpalu")
4712 (set_attr "length" "4")])
4714 (define_insn "floatunssidf2_pa20"
4715 [(set (match_operand:DF 0 "register_operand" "=f")
4716 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4717 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4719 [(set_attr "type" "fpalu")
4720 (set_attr "length" "4")])
4722 (define_insn "floatunssisf2_pa20"
4723 [(set (match_operand:SF 0 "register_operand" "=f")
4724 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4725 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4727 [(set_attr "type" "fpalu")
4728 (set_attr "length" "4")])
4730 (define_insn "floatunsdisf2"
4731 [(set (match_operand:SF 0 "register_operand" "=f")
4732 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4733 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4734 "fcnv,udw,sgl %1,%0"
4735 [(set_attr "type" "fpalu")
4736 (set_attr "length" "4")])
4738 (define_insn "floatunsdidf2"
4739 [(set (match_operand:DF 0 "register_operand" "=f")
4740 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4741 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4742 "fcnv,udw,dbl %1,%0"
4743 [(set_attr "type" "fpalu")
4744 (set_attr "length" "4")])
4746 (define_insn "fixuns_truncsfsi2"
4747 [(set (match_operand:SI 0 "register_operand" "=f")
4748 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4749 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4750 "fcnv,t,sgl,uw %1,%0"
4751 [(set_attr "type" "fpalu")
4752 (set_attr "length" "4")])
4754 (define_insn "fixuns_truncdfsi2"
4755 [(set (match_operand:SI 0 "register_operand" "=f")
4756 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4757 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4758 "fcnv,t,dbl,uw %1,%0"
4759 [(set_attr "type" "fpalu")
4760 (set_attr "length" "4")])
4762 (define_insn "fixuns_truncsfdi2"
4763 [(set (match_operand:DI 0 "register_operand" "=f")
4764 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4765 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4766 "fcnv,t,sgl,udw %1,%0"
4767 [(set_attr "type" "fpalu")
4768 (set_attr "length" "4")])
4770 (define_insn "fixuns_truncdfdi2"
4771 [(set (match_operand:DI 0 "register_operand" "=f")
4772 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4773 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4774 "fcnv,t,dbl,udw %1,%0"
4775 [(set_attr "type" "fpalu")
4776 (set_attr "length" "4")])
4778 ;;- arithmetic instructions
4780 (define_expand "adddi3"
4781 [(set (match_operand:DI 0 "register_operand" "")
4782 (plus:DI (match_operand:DI 1 "register_operand" "")
4783 (match_operand:DI 2 "adddi3_operand" "")))]
4788 [(set (match_operand:DI 0 "register_operand" "=r")
4789 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4790 (match_operand:DI 2 "arith11_operand" "rI")))]
4794 if (GET_CODE (operands[2]) == CONST_INT)
4796 if (INTVAL (operands[2]) >= 0)
4797 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4799 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4802 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4804 [(set_attr "type" "binary")
4805 (set_attr "length" "8")])
4808 [(set (match_operand:DI 0 "register_operand" "=r,r")
4809 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4810 (match_operand:DI 2 "arith_operand" "r,J")))]
4815 [(set_attr "type" "binary,binary")
4816 (set_attr "pa_combine_type" "addmove")
4817 (set_attr "length" "4,4")])
4820 [(set (match_operand:DI 0 "register_operand" "=r")
4821 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4822 (match_operand:DI 2 "register_operand" "r")))]
4825 [(set_attr "type" "binary")
4826 (set_attr "length" "4")])
4829 [(set (match_operand:SI 0 "register_operand" "=r")
4830 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4831 (match_operand:SI 2 "register_operand" "r")))]
4834 [(set_attr "type" "binary")
4835 (set_attr "length" "4")])
4837 ;; define_splits to optimize cases of adding a constant integer
4838 ;; to a register when the constant does not fit in 14 bits. */
4840 [(set (match_operand:SI 0 "register_operand" "")
4841 (plus:SI (match_operand:SI 1 "register_operand" "")
4842 (match_operand:SI 2 "const_int_operand" "")))
4843 (clobber (match_operand:SI 4 "register_operand" ""))]
4844 "! cint_ok_for_move (INTVAL (operands[2]))
4845 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4846 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4847 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4850 int val = INTVAL (operands[2]);
4851 int low = (val < 0) ? -0x2000 : 0x1fff;
4852 int rest = val - low;
4854 operands[2] = GEN_INT (rest);
4855 operands[3] = GEN_INT (low);
4859 [(set (match_operand:SI 0 "register_operand" "")
4860 (plus:SI (match_operand:SI 1 "register_operand" "")
4861 (match_operand:SI 2 "const_int_operand" "")))
4862 (clobber (match_operand:SI 4 "register_operand" ""))]
4863 "! cint_ok_for_move (INTVAL (operands[2]))"
4864 [(set (match_dup 4) (match_dup 2))
4865 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4869 HOST_WIDE_INT intval = INTVAL (operands[2]);
4871 /* Try dividing the constant by 2, then 4, and finally 8 to see
4872 if we can get a constant which can be loaded into a register
4873 in a single instruction (cint_ok_for_move).
4875 If that fails, try to negate the constant and subtract it
4876 from our input operand. */
4877 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4879 operands[2] = GEN_INT (intval / 2);
4880 operands[3] = const2_rtx;
4882 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
4884 operands[2] = GEN_INT (intval / 4);
4885 operands[3] = GEN_INT (4);
4887 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
4889 operands[2] = GEN_INT (intval / 8);
4890 operands[3] = GEN_INT (8);
4892 else if (cint_ok_for_move (-intval))
4894 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
4895 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
4902 (define_insn "addsi3"
4903 [(set (match_operand:SI 0 "register_operand" "=r,r")
4904 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
4905 (match_operand:SI 2 "arith_operand" "r,J")))]
4908 {addl|add,l} %1,%2,%0
4910 [(set_attr "type" "binary,binary")
4911 (set_attr "pa_combine_type" "addmove")
4912 (set_attr "length" "4,4")])
4914 (define_expand "subdi3"
4915 [(set (match_operand:DI 0 "register_operand" "")
4916 (minus:DI (match_operand:DI 1 "register_operand" "")
4917 (match_operand:DI 2 "register_operand" "")))]
4922 [(set (match_operand:DI 0 "register_operand" "=r")
4923 (minus:DI (match_operand:DI 1 "register_operand" "r")
4924 (match_operand:DI 2 "register_operand" "r")))]
4926 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
4927 [(set_attr "type" "binary")
4928 (set_attr "length" "8")])
4931 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
4932 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
4933 (match_operand:DI 2 "register_operand" "r,r,!r")))]
4939 [(set_attr "type" "binary,binary,move")
4940 (set_attr "length" "4,4,4")])
4942 (define_expand "subsi3"
4943 [(set (match_operand:SI 0 "register_operand" "")
4944 (minus:SI (match_operand:SI 1 "arith11_operand" "")
4945 (match_operand:SI 2 "register_operand" "")))]
4950 [(set (match_operand:SI 0 "register_operand" "=r,r")
4951 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
4952 (match_operand:SI 2 "register_operand" "r,r")))]
4957 [(set_attr "type" "binary,binary")
4958 (set_attr "length" "4,4")])
4961 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
4962 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
4963 (match_operand:SI 2 "register_operand" "r,r,!r")))]
4969 [(set_attr "type" "binary,binary,move")
4970 (set_attr "length" "4,4,4")])
4972 ;; Clobbering a "register_operand" instead of a match_scratch
4973 ;; in operand3 of millicode calls avoids spilling %r1 and
4974 ;; produces better code.
4976 ;; The mulsi3 insns set up registers for the millicode call.
4977 (define_expand "mulsi3"
4978 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
4979 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
4980 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4981 (clobber (match_dup 3))
4982 (clobber (reg:SI 26))
4983 (clobber (reg:SI 25))
4984 (clobber (match_dup 4))])
4985 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4989 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4990 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
4992 rtx scratch = gen_reg_rtx (DImode);
4993 operands[1] = force_reg (SImode, operands[1]);
4994 operands[2] = force_reg (SImode, operands[2]);
4995 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
4996 emit_insn (gen_movsi (operands[0],
4997 gen_rtx_SUBREG (SImode, scratch,
4998 GET_MODE_SIZE (SImode))));
5001 operands[3] = gen_reg_rtx (SImode);
5004 (define_insn "umulsidi3"
5005 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5006 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5007 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5008 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5010 [(set_attr "type" "fpmuldbl")
5011 (set_attr "length" "4")])
5014 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5015 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5016 (match_operand:DI 2 "uint32_operand" "f")))]
5017 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5019 [(set_attr "type" "fpmuldbl")
5020 (set_attr "length" "4")])
5023 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5024 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5025 (match_operand:DI 2 "uint32_operand" "f")))]
5026 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5028 [(set_attr "type" "fpmuldbl")
5029 (set_attr "length" "4")])
5032 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5033 (clobber (match_operand:SI 0 "register_operand" "=a"))
5034 (clobber (reg:SI 26))
5035 (clobber (reg:SI 25))
5036 (clobber (reg:SI 31))]
5038 "* return output_mul_insn (0, insn);"
5039 [(set_attr "type" "milli")
5040 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5043 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5044 (clobber (match_operand:SI 0 "register_operand" "=a"))
5045 (clobber (reg:SI 26))
5046 (clobber (reg:SI 25))
5047 (clobber (reg:SI 2))]
5049 "* return output_mul_insn (0, insn);"
5050 [(set_attr "type" "milli")
5051 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5053 (define_expand "muldi3"
5054 [(set (match_operand:DI 0 "register_operand" "")
5055 (mult:DI (match_operand:DI 1 "register_operand" "")
5056 (match_operand:DI 2 "register_operand" "")))]
5057 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5060 rtx low_product = gen_reg_rtx (DImode);
5061 rtx cross_product1 = gen_reg_rtx (DImode);
5062 rtx cross_product2 = gen_reg_rtx (DImode);
5063 rtx cross_scratch = gen_reg_rtx (DImode);
5064 rtx cross_product = gen_reg_rtx (DImode);
5065 rtx op1l, op1r, op2l, op2r;
5066 rtx op1shifted, op2shifted;
5068 op1shifted = gen_reg_rtx (DImode);
5069 op2shifted = gen_reg_rtx (DImode);
5070 op1l = gen_reg_rtx (SImode);
5071 op1r = gen_reg_rtx (SImode);
5072 op2l = gen_reg_rtx (SImode);
5073 op2r = gen_reg_rtx (SImode);
5075 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5077 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5079 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5080 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5081 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5082 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5084 /* Emit multiplies for the cross products. */
5085 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5086 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5088 /* Emit a multiply for the low sub-word. */
5089 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5091 /* Sum the cross products and shift them into proper position. */
5092 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5093 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5095 /* Add the cross product to the low product and store the result
5096 into the output operand . */
5097 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5101 ;;; Division and mod.
5102 (define_expand "divsi3"
5103 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5104 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5105 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5106 (clobber (match_dup 3))
5107 (clobber (match_dup 4))
5108 (clobber (reg:SI 26))
5109 (clobber (reg:SI 25))
5110 (clobber (match_dup 5))])
5111 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5115 operands[3] = gen_reg_rtx (SImode);
5118 operands[5] = gen_rtx_REG (SImode, 2);
5119 operands[4] = operands[5];
5123 operands[5] = gen_rtx_REG (SImode, 31);
5124 operands[4] = gen_reg_rtx (SImode);
5126 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5132 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5133 (clobber (match_operand:SI 1 "register_operand" "=a"))
5134 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5135 (clobber (reg:SI 26))
5136 (clobber (reg:SI 25))
5137 (clobber (reg:SI 31))]
5140 return output_div_insn (operands, 0, insn);"
5141 [(set_attr "type" "milli")
5142 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5146 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5147 (clobber (match_operand:SI 1 "register_operand" "=a"))
5148 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5149 (clobber (reg:SI 26))
5150 (clobber (reg:SI 25))
5151 (clobber (reg:SI 2))]
5154 return output_div_insn (operands, 0, insn);"
5155 [(set_attr "type" "milli")
5156 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5158 (define_expand "udivsi3"
5159 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5160 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5161 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5162 (clobber (match_dup 3))
5163 (clobber (match_dup 4))
5164 (clobber (reg:SI 26))
5165 (clobber (reg:SI 25))
5166 (clobber (match_dup 5))])
5167 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5171 operands[3] = gen_reg_rtx (SImode);
5175 operands[5] = gen_rtx_REG (SImode, 2);
5176 operands[4] = operands[5];
5180 operands[5] = gen_rtx_REG (SImode, 31);
5181 operands[4] = gen_reg_rtx (SImode);
5183 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5189 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5190 (clobber (match_operand:SI 1 "register_operand" "=a"))
5191 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5192 (clobber (reg:SI 26))
5193 (clobber (reg:SI 25))
5194 (clobber (reg:SI 31))]
5197 return output_div_insn (operands, 1, insn);"
5198 [(set_attr "type" "milli")
5199 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5203 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5204 (clobber (match_operand:SI 1 "register_operand" "=a"))
5205 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5206 (clobber (reg:SI 26))
5207 (clobber (reg:SI 25))
5208 (clobber (reg:SI 2))]
5211 return output_div_insn (operands, 1, insn);"
5212 [(set_attr "type" "milli")
5213 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5215 (define_expand "modsi3"
5216 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5217 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5218 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5219 (clobber (match_dup 3))
5220 (clobber (match_dup 4))
5221 (clobber (reg:SI 26))
5222 (clobber (reg:SI 25))
5223 (clobber (match_dup 5))])
5224 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5230 operands[5] = gen_rtx_REG (SImode, 2);
5231 operands[4] = operands[5];
5235 operands[5] = gen_rtx_REG (SImode, 31);
5236 operands[4] = gen_reg_rtx (SImode);
5238 operands[3] = gen_reg_rtx (SImode);
5242 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5243 (clobber (match_operand:SI 0 "register_operand" "=a"))
5244 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5245 (clobber (reg:SI 26))
5246 (clobber (reg:SI 25))
5247 (clobber (reg:SI 31))]
5250 return output_mod_insn (0, insn);"
5251 [(set_attr "type" "milli")
5252 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5255 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5256 (clobber (match_operand:SI 0 "register_operand" "=a"))
5257 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5258 (clobber (reg:SI 26))
5259 (clobber (reg:SI 25))
5260 (clobber (reg:SI 2))]
5263 return output_mod_insn (0, insn);"
5264 [(set_attr "type" "milli")
5265 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5267 (define_expand "umodsi3"
5268 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5269 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5270 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5271 (clobber (match_dup 3))
5272 (clobber (match_dup 4))
5273 (clobber (reg:SI 26))
5274 (clobber (reg:SI 25))
5275 (clobber (match_dup 5))])
5276 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5282 operands[5] = gen_rtx_REG (SImode, 2);
5283 operands[4] = operands[5];
5287 operands[5] = gen_rtx_REG (SImode, 31);
5288 operands[4] = gen_reg_rtx (SImode);
5290 operands[3] = gen_reg_rtx (SImode);
5294 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5295 (clobber (match_operand:SI 0 "register_operand" "=a"))
5296 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5297 (clobber (reg:SI 26))
5298 (clobber (reg:SI 25))
5299 (clobber (reg:SI 31))]
5302 return output_mod_insn (1, insn);"
5303 [(set_attr "type" "milli")
5304 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5307 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5308 (clobber (match_operand:SI 0 "register_operand" "=a"))
5309 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5310 (clobber (reg:SI 26))
5311 (clobber (reg:SI 25))
5312 (clobber (reg:SI 2))]
5315 return output_mod_insn (1, insn);"
5316 [(set_attr "type" "milli")
5317 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5319 ;;- and instructions
5320 ;; We define DImode `and` so with DImode `not` we can get
5321 ;; DImode `andn`. Other combinations are possible.
5323 (define_expand "anddi3"
5324 [(set (match_operand:DI 0 "register_operand" "")
5325 (and:DI (match_operand:DI 1 "and_operand" "")
5326 (match_operand:DI 2 "and_operand" "")))]
5332 /* One operand must be a register operand. */
5333 if (!register_operand (operands[1], DImode)
5334 && !register_operand (operands[2], DImode))
5339 /* Both operands must be register operands. */
5340 if (!register_operand (operands[1], DImode)
5341 || !register_operand (operands[2], DImode))
5347 [(set (match_operand:DI 0 "register_operand" "=r")
5348 (and:DI (match_operand:DI 1 "register_operand" "%r")
5349 (match_operand:DI 2 "register_operand" "r")))]
5351 "and %1,%2,%0\;and %R1,%R2,%R0"
5352 [(set_attr "type" "binary")
5353 (set_attr "length" "8")])
5356 [(set (match_operand:DI 0 "register_operand" "=r,r")
5357 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5358 (match_operand:DI 2 "and_operand" "rO,P")))]
5360 "* return output_64bit_and (operands); "
5361 [(set_attr "type" "binary")
5362 (set_attr "length" "4")])
5364 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5365 ; constant with ldil;ldo.
5366 (define_insn "andsi3"
5367 [(set (match_operand:SI 0 "register_operand" "=r,r")
5368 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5369 (match_operand:SI 2 "and_operand" "rO,P")))]
5371 "* return output_and (operands); "
5372 [(set_attr "type" "binary,shift")
5373 (set_attr "length" "4,4")])
5376 [(set (match_operand:DI 0 "register_operand" "=r")
5377 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5378 (match_operand:DI 2 "register_operand" "r")))]
5380 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5381 [(set_attr "type" "binary")
5382 (set_attr "length" "8")])
5385 [(set (match_operand:DI 0 "register_operand" "=r")
5386 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5387 (match_operand:DI 2 "register_operand" "r")))]
5390 [(set_attr "type" "binary")
5391 (set_attr "length" "4")])
5394 [(set (match_operand:SI 0 "register_operand" "=r")
5395 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5396 (match_operand:SI 2 "register_operand" "r")))]
5399 [(set_attr "type" "binary")
5400 (set_attr "length" "4")])
5402 (define_expand "iordi3"
5403 [(set (match_operand:DI 0 "register_operand" "")
5404 (ior:DI (match_operand:DI 1 "ior_operand" "")
5405 (match_operand:DI 2 "ior_operand" "")))]
5411 /* One operand must be a register operand. */
5412 if (!register_operand (operands[1], DImode)
5413 && !register_operand (operands[2], DImode))
5418 /* Both operands must be register operands. */
5419 if (!register_operand (operands[1], DImode)
5420 || !register_operand (operands[2], DImode))
5426 [(set (match_operand:DI 0 "register_operand" "=r")
5427 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5428 (match_operand:DI 2 "register_operand" "r")))]
5430 "or %1,%2,%0\;or %R1,%R2,%R0"
5431 [(set_attr "type" "binary")
5432 (set_attr "length" "8")])
5435 [(set (match_operand:DI 0 "register_operand" "=r,r")
5436 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5437 (match_operand:DI 2 "ior_operand" "M,i")))]
5439 "* return output_64bit_ior (operands); "
5440 [(set_attr "type" "binary,shift")
5441 (set_attr "length" "4,4")])
5444 [(set (match_operand:DI 0 "register_operand" "=r")
5445 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5446 (match_operand:DI 2 "register_operand" "r")))]
5449 [(set_attr "type" "binary")
5450 (set_attr "length" "4")])
5452 ;; Need a define_expand because we've run out of CONST_OK... characters.
5453 (define_expand "iorsi3"
5454 [(set (match_operand:SI 0 "register_operand" "")
5455 (ior:SI (match_operand:SI 1 "register_operand" "")
5456 (match_operand:SI 2 "arith32_operand" "")))]
5460 if (! (ior_operand (operands[2], SImode)
5461 || register_operand (operands[2], SImode)))
5462 operands[2] = force_reg (SImode, operands[2]);
5466 [(set (match_operand:SI 0 "register_operand" "=r,r")
5467 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5468 (match_operand:SI 2 "ior_operand" "M,i")))]
5470 "* return output_ior (operands); "
5471 [(set_attr "type" "binary,shift")
5472 (set_attr "length" "4,4")])
5475 [(set (match_operand:SI 0 "register_operand" "=r")
5476 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5477 (match_operand:SI 2 "register_operand" "r")))]
5480 [(set_attr "type" "binary")
5481 (set_attr "length" "4")])
5483 (define_expand "xordi3"
5484 [(set (match_operand:DI 0 "register_operand" "")
5485 (xor:DI (match_operand:DI 1 "register_operand" "")
5486 (match_operand:DI 2 "register_operand" "")))]
5493 [(set (match_operand:DI 0 "register_operand" "=r")
5494 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5495 (match_operand:DI 2 "register_operand" "r")))]
5497 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5498 [(set_attr "type" "binary")
5499 (set_attr "length" "8")])
5502 [(set (match_operand:DI 0 "register_operand" "=r")
5503 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5504 (match_operand:DI 2 "register_operand" "r")))]
5507 [(set_attr "type" "binary")
5508 (set_attr "length" "4")])
5510 (define_insn "xorsi3"
5511 [(set (match_operand:SI 0 "register_operand" "=r")
5512 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5513 (match_operand:SI 2 "register_operand" "r")))]
5516 [(set_attr "type" "binary")
5517 (set_attr "length" "4")])
5519 (define_expand "negdi2"
5520 [(set (match_operand:DI 0 "register_operand" "")
5521 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5526 [(set (match_operand:DI 0 "register_operand" "=r")
5527 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5529 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5530 [(set_attr "type" "unary")
5531 (set_attr "length" "8")])
5534 [(set (match_operand:DI 0 "register_operand" "=r")
5535 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5538 [(set_attr "type" "unary")
5539 (set_attr "length" "4")])
5541 (define_insn "negsi2"
5542 [(set (match_operand:SI 0 "register_operand" "=r")
5543 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5546 [(set_attr "type" "unary")
5547 (set_attr "length" "4")])
5549 (define_expand "one_cmpldi2"
5550 [(set (match_operand:DI 0 "register_operand" "")
5551 (not:DI (match_operand:DI 1 "register_operand" "")))]
5558 [(set (match_operand:DI 0 "register_operand" "=r")
5559 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5561 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5562 [(set_attr "type" "unary")
5563 (set_attr "length" "8")])
5566 [(set (match_operand:DI 0 "register_operand" "=r")
5567 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5570 [(set_attr "type" "unary")
5571 (set_attr "length" "4")])
5573 (define_insn "one_cmplsi2"
5574 [(set (match_operand:SI 0 "register_operand" "=r")
5575 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5578 [(set_attr "type" "unary")
5579 (set_attr "length" "4")])
5581 ;; Floating point arithmetic instructions.
5583 (define_insn "adddf3"
5584 [(set (match_operand:DF 0 "register_operand" "=f")
5585 (plus:DF (match_operand:DF 1 "register_operand" "f")
5586 (match_operand:DF 2 "register_operand" "f")))]
5587 "! TARGET_SOFT_FLOAT"
5589 [(set_attr "type" "fpalu")
5590 (set_attr "pa_combine_type" "faddsub")
5591 (set_attr "length" "4")])
5593 (define_insn "addsf3"
5594 [(set (match_operand:SF 0 "register_operand" "=f")
5595 (plus:SF (match_operand:SF 1 "register_operand" "f")
5596 (match_operand:SF 2 "register_operand" "f")))]
5597 "! TARGET_SOFT_FLOAT"
5599 [(set_attr "type" "fpalu")
5600 (set_attr "pa_combine_type" "faddsub")
5601 (set_attr "length" "4")])
5603 (define_insn "subdf3"
5604 [(set (match_operand:DF 0 "register_operand" "=f")
5605 (minus:DF (match_operand:DF 1 "register_operand" "f")
5606 (match_operand:DF 2 "register_operand" "f")))]
5607 "! TARGET_SOFT_FLOAT"
5609 [(set_attr "type" "fpalu")
5610 (set_attr "pa_combine_type" "faddsub")
5611 (set_attr "length" "4")])
5613 (define_insn "subsf3"
5614 [(set (match_operand:SF 0 "register_operand" "=f")
5615 (minus:SF (match_operand:SF 1 "register_operand" "f")
5616 (match_operand:SF 2 "register_operand" "f")))]
5617 "! TARGET_SOFT_FLOAT"
5619 [(set_attr "type" "fpalu")
5620 (set_attr "pa_combine_type" "faddsub")
5621 (set_attr "length" "4")])
5623 (define_insn "muldf3"
5624 [(set (match_operand:DF 0 "register_operand" "=f")
5625 (mult:DF (match_operand:DF 1 "register_operand" "f")
5626 (match_operand:DF 2 "register_operand" "f")))]
5627 "! TARGET_SOFT_FLOAT"
5629 [(set_attr "type" "fpmuldbl")
5630 (set_attr "pa_combine_type" "fmpy")
5631 (set_attr "length" "4")])
5633 (define_insn "mulsf3"
5634 [(set (match_operand:SF 0 "register_operand" "=f")
5635 (mult:SF (match_operand:SF 1 "register_operand" "f")
5636 (match_operand:SF 2 "register_operand" "f")))]
5637 "! TARGET_SOFT_FLOAT"
5639 [(set_attr "type" "fpmulsgl")
5640 (set_attr "pa_combine_type" "fmpy")
5641 (set_attr "length" "4")])
5643 (define_insn "divdf3"
5644 [(set (match_operand:DF 0 "register_operand" "=f")
5645 (div:DF (match_operand:DF 1 "register_operand" "f")
5646 (match_operand:DF 2 "register_operand" "f")))]
5647 "! TARGET_SOFT_FLOAT"
5649 [(set_attr "type" "fpdivdbl")
5650 (set_attr "length" "4")])
5652 (define_insn "divsf3"
5653 [(set (match_operand:SF 0 "register_operand" "=f")
5654 (div:SF (match_operand:SF 1 "register_operand" "f")
5655 (match_operand:SF 2 "register_operand" "f")))]
5656 "! TARGET_SOFT_FLOAT"
5658 [(set_attr "type" "fpdivsgl")
5659 (set_attr "length" "4")])
5661 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5662 ;; negation can be done by subtracting from plus zero. However, this
5663 ;; violates the IEEE standard when negating plus and minus zero.
5664 (define_expand "negdf2"
5665 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5666 (neg:DF (match_operand:DF 1 "register_operand" "")))
5667 (use (match_dup 2))])]
5668 "! TARGET_SOFT_FLOAT"
5670 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5671 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5674 operands[2] = force_reg (DFmode,
5675 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5676 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5681 (define_insn "negdf2_fast"
5682 [(set (match_operand:DF 0 "register_operand" "=f")
5683 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5684 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5688 return \"fneg,dbl %1,%0\";
5690 return \"fsub,dbl %%fr0,%1,%0\";
5692 [(set_attr "type" "fpalu")
5693 (set_attr "length" "4")])
5695 (define_expand "negsf2"
5696 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5697 (neg:SF (match_operand:SF 1 "register_operand" "")))
5698 (use (match_dup 2))])]
5699 "! TARGET_SOFT_FLOAT"
5701 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5702 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5705 operands[2] = force_reg (SFmode,
5706 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5707 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5712 (define_insn "negsf2_fast"
5713 [(set (match_operand:SF 0 "register_operand" "=f")
5714 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5715 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5719 return \"fneg,sgl %1,%0\";
5721 return \"fsub,sgl %%fr0,%1,%0\";
5723 [(set_attr "type" "fpalu")
5724 (set_attr "length" "4")])
5726 (define_insn "absdf2"
5727 [(set (match_operand:DF 0 "register_operand" "=f")
5728 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5729 "! TARGET_SOFT_FLOAT"
5731 [(set_attr "type" "fpalu")
5732 (set_attr "length" "4")])
5734 (define_insn "abssf2"
5735 [(set (match_operand:SF 0 "register_operand" "=f")
5736 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5737 "! TARGET_SOFT_FLOAT"
5739 [(set_attr "type" "fpalu")
5740 (set_attr "length" "4")])
5742 (define_insn "sqrtdf2"
5743 [(set (match_operand:DF 0 "register_operand" "=f")
5744 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5745 "! TARGET_SOFT_FLOAT"
5747 [(set_attr "type" "fpsqrtdbl")
5748 (set_attr "length" "4")])
5750 (define_insn "sqrtsf2"
5751 [(set (match_operand:SF 0 "register_operand" "=f")
5752 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5753 "! TARGET_SOFT_FLOAT"
5755 [(set_attr "type" "fpsqrtsgl")
5756 (set_attr "length" "4")])
5758 ;; PA 2.0 floating point instructions
5762 [(set (match_operand:DF 0 "register_operand" "=f")
5763 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5764 (match_operand:DF 2 "register_operand" "f"))
5765 (match_operand:DF 3 "register_operand" "f")))]
5766 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5767 "fmpyfadd,dbl %1,%2,%3,%0"
5768 [(set_attr "type" "fpmuldbl")
5769 (set_attr "length" "4")])
5772 [(set (match_operand:DF 0 "register_operand" "=f")
5773 (plus:DF (match_operand:DF 1 "register_operand" "f")
5774 (mult:DF (match_operand:DF 2 "register_operand" "f")
5775 (match_operand:DF 3 "register_operand" "f"))))]
5776 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5777 "fmpyfadd,dbl %2,%3,%1,%0"
5778 [(set_attr "type" "fpmuldbl")
5779 (set_attr "length" "4")])
5782 [(set (match_operand:SF 0 "register_operand" "=f")
5783 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5784 (match_operand:SF 2 "register_operand" "f"))
5785 (match_operand:SF 3 "register_operand" "f")))]
5786 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5787 "fmpyfadd,sgl %1,%2,%3,%0"
5788 [(set_attr "type" "fpmulsgl")
5789 (set_attr "length" "4")])
5792 [(set (match_operand:SF 0 "register_operand" "=f")
5793 (plus:SF (match_operand:SF 1 "register_operand" "f")
5794 (mult:SF (match_operand:SF 2 "register_operand" "f")
5795 (match_operand:SF 3 "register_operand" "f"))))]
5796 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5797 "fmpyfadd,sgl %2,%3,%1,%0"
5798 [(set_attr "type" "fpmulsgl")
5799 (set_attr "length" "4")])
5801 ; fmpynfadd patterns
5803 [(set (match_operand:DF 0 "register_operand" "=f")
5804 (minus:DF (match_operand:DF 1 "register_operand" "f")
5805 (mult:DF (match_operand:DF 2 "register_operand" "f")
5806 (match_operand:DF 3 "register_operand" "f"))))]
5807 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5808 "fmpynfadd,dbl %2,%3,%1,%0"
5809 [(set_attr "type" "fpmuldbl")
5810 (set_attr "length" "4")])
5813 [(set (match_operand:SF 0 "register_operand" "=f")
5814 (minus:SF (match_operand:SF 1 "register_operand" "f")
5815 (mult:SF (match_operand:SF 2 "register_operand" "f")
5816 (match_operand:SF 3 "register_operand" "f"))))]
5817 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5818 "fmpynfadd,sgl %2,%3,%1,%0"
5819 [(set_attr "type" "fpmulsgl")
5820 (set_attr "length" "4")])
5824 [(set (match_operand:DF 0 "register_operand" "=f")
5825 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5826 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5828 [(set_attr "type" "fpalu")
5829 (set_attr "length" "4")])
5832 [(set (match_operand:SF 0 "register_operand" "=f")
5833 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5834 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5836 [(set_attr "type" "fpalu")
5837 (set_attr "length" "4")])
5839 ;; Generating a fused multiply sequence is a win for this case as it will
5840 ;; reduce the latency for the fused case without impacting the plain
5843 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5844 ;; perform two operations with the result of the first feeding the second.
5846 [(set (match_operand:DF 0 "register_operand" "=f")
5847 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5848 (match_operand:DF 2 "register_operand" "f"))
5849 (match_operand:DF 3 "register_operand" "f")))
5850 (set (match_operand:DF 4 "register_operand" "=&f")
5851 (mult:DF (match_dup 1) (match_dup 2)))]
5852 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5853 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5854 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5856 [(set_attr "type" "fpmuldbl")
5857 (set_attr "length" "8")])
5859 ;; We want to split this up during scheduling since we want both insns
5860 ;; to schedule independently.
5862 [(set (match_operand:DF 0 "register_operand" "")
5863 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5864 (match_operand:DF 2 "register_operand" ""))
5865 (match_operand:DF 3 "register_operand" "")))
5866 (set (match_operand:DF 4 "register_operand" "")
5867 (mult:DF (match_dup 1) (match_dup 2)))]
5868 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5869 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5870 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5875 [(set (match_operand:SF 0 "register_operand" "=f")
5876 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5877 (match_operand:SF 2 "register_operand" "f"))
5878 (match_operand:SF 3 "register_operand" "f")))
5879 (set (match_operand:SF 4 "register_operand" "=&f")
5880 (mult:SF (match_dup 1) (match_dup 2)))]
5881 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5882 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5883 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5885 [(set_attr "type" "fpmuldbl")
5886 (set_attr "length" "8")])
5888 ;; We want to split this up during scheduling since we want both insns
5889 ;; to schedule independently.
5891 [(set (match_operand:SF 0 "register_operand" "")
5892 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5893 (match_operand:SF 2 "register_operand" ""))
5894 (match_operand:SF 3 "register_operand" "")))
5895 (set (match_operand:SF 4 "register_operand" "")
5896 (mult:SF (match_dup 1) (match_dup 2)))]
5897 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5898 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5899 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
5903 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
5906 [(set (match_operand:DF 0 "register_operand" "=f")
5907 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5908 (match_operand:DF 2 "register_operand" "f"))))]
5909 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5910 "fmpynfadd,dbl %1,%2,%%fr0,%0"
5911 [(set_attr "type" "fpmuldbl")
5912 (set_attr "length" "4")])
5915 [(set (match_operand:SF 0 "register_operand" "=f")
5916 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5917 (match_operand:SF 2 "register_operand" "f"))))]
5918 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5919 "fmpynfadd,sgl %1,%2,%%fr0,%0"
5920 [(set_attr "type" "fpmuldbl")
5921 (set_attr "length" "4")])
5924 [(set (match_operand:DF 0 "register_operand" "=f")
5925 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5926 (match_operand:DF 2 "register_operand" "f"))))
5927 (set (match_operand:DF 3 "register_operand" "=&f")
5928 (mult:DF (match_dup 1) (match_dup 2)))]
5929 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5930 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5931 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5933 [(set_attr "type" "fpmuldbl")
5934 (set_attr "length" "8")])
5937 [(set (match_operand:DF 0 "register_operand" "")
5938 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5939 (match_operand:DF 2 "register_operand" ""))))
5940 (set (match_operand:DF 3 "register_operand" "")
5941 (mult:DF (match_dup 1) (match_dup 2)))]
5942 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5943 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
5944 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
5948 [(set (match_operand:SF 0 "register_operand" "=f")
5949 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5950 (match_operand:SF 2 "register_operand" "f"))))
5951 (set (match_operand:SF 3 "register_operand" "=&f")
5952 (mult:SF (match_dup 1) (match_dup 2)))]
5953 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5954 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5955 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5957 [(set_attr "type" "fpmuldbl")
5958 (set_attr "length" "8")])
5961 [(set (match_operand:SF 0 "register_operand" "")
5962 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5963 (match_operand:SF 2 "register_operand" ""))))
5964 (set (match_operand:SF 3 "register_operand" "")
5965 (mult:SF (match_dup 1) (match_dup 2)))]
5966 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5967 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
5968 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
5971 ;; Now fused multiplies with the result of the multiply negated.
5973 [(set (match_operand:DF 0 "register_operand" "=f")
5974 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5975 (match_operand:DF 2 "register_operand" "f")))
5976 (match_operand:DF 3 "register_operand" "f")))]
5977 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5978 "fmpynfadd,dbl %1,%2,%3,%0"
5979 [(set_attr "type" "fpmuldbl")
5980 (set_attr "length" "4")])
5983 [(set (match_operand:SF 0 "register_operand" "=f")
5984 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5985 (match_operand:SF 2 "register_operand" "f")))
5986 (match_operand:SF 3 "register_operand" "f")))]
5987 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5988 "fmpynfadd,sgl %1,%2,%3,%0"
5989 [(set_attr "type" "fpmuldbl")
5990 (set_attr "length" "4")])
5993 [(set (match_operand:DF 0 "register_operand" "=f")
5994 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5995 (match_operand:DF 2 "register_operand" "f")))
5996 (match_operand:DF 3 "register_operand" "f")))
5997 (set (match_operand:DF 4 "register_operand" "=&f")
5998 (mult:DF (match_dup 1) (match_dup 2)))]
5999 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6000 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6001 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6003 [(set_attr "type" "fpmuldbl")
6004 (set_attr "length" "8")])
6007 [(set (match_operand:DF 0 "register_operand" "")
6008 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6009 (match_operand:DF 2 "register_operand" "")))
6010 (match_operand:DF 3 "register_operand" "")))
6011 (set (match_operand:DF 4 "register_operand" "")
6012 (mult:DF (match_dup 1) (match_dup 2)))]
6013 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6014 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6015 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6020 [(set (match_operand:SF 0 "register_operand" "=f")
6021 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6022 (match_operand:SF 2 "register_operand" "f")))
6023 (match_operand:SF 3 "register_operand" "f")))
6024 (set (match_operand:SF 4 "register_operand" "=&f")
6025 (mult:SF (match_dup 1) (match_dup 2)))]
6026 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6027 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6028 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6030 [(set_attr "type" "fpmuldbl")
6031 (set_attr "length" "8")])
6034 [(set (match_operand:SF 0 "register_operand" "")
6035 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6036 (match_operand:SF 2 "register_operand" "")))
6037 (match_operand:SF 3 "register_operand" "")))
6038 (set (match_operand:SF 4 "register_operand" "")
6039 (mult:SF (match_dup 1) (match_dup 2)))]
6040 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6041 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6042 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6047 [(set (match_operand:DF 0 "register_operand" "=f")
6048 (minus:DF (match_operand:DF 3 "register_operand" "f")
6049 (mult:DF (match_operand:DF 1 "register_operand" "f")
6050 (match_operand:DF 2 "register_operand" "f"))))
6051 (set (match_operand:DF 4 "register_operand" "=&f")
6052 (mult:DF (match_dup 1) (match_dup 2)))]
6053 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6054 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6055 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6057 [(set_attr "type" "fpmuldbl")
6058 (set_attr "length" "8")])
6061 [(set (match_operand:DF 0 "register_operand" "")
6062 (minus:DF (match_operand:DF 3 "register_operand" "")
6063 (mult:DF (match_operand:DF 1 "register_operand" "")
6064 (match_operand:DF 2 "register_operand" ""))))
6065 (set (match_operand:DF 4 "register_operand" "")
6066 (mult:DF (match_dup 1) (match_dup 2)))]
6067 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6068 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6069 (set (match_dup 0) (minus:DF (match_dup 3)
6070 (mult:DF (match_dup 1) (match_dup 2))))]
6074 [(set (match_operand:SF 0 "register_operand" "=f")
6075 (minus:SF (match_operand:SF 3 "register_operand" "f")
6076 (mult:SF (match_operand:SF 1 "register_operand" "f")
6077 (match_operand:SF 2 "register_operand" "f"))))
6078 (set (match_operand:SF 4 "register_operand" "=&f")
6079 (mult:SF (match_dup 1) (match_dup 2)))]
6080 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6081 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6082 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6084 [(set_attr "type" "fpmuldbl")
6085 (set_attr "length" "8")])
6088 [(set (match_operand:SF 0 "register_operand" "")
6089 (minus:SF (match_operand:SF 3 "register_operand" "")
6090 (mult:SF (match_operand:SF 1 "register_operand" "")
6091 (match_operand:SF 2 "register_operand" ""))))
6092 (set (match_operand:SF 4 "register_operand" "")
6093 (mult:SF (match_dup 1) (match_dup 2)))]
6094 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6095 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6096 (set (match_dup 0) (minus:SF (match_dup 3)
6097 (mult:SF (match_dup 1) (match_dup 2))))]
6101 [(set (match_operand:DF 0 "register_operand" "=f")
6102 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6103 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6104 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6105 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6107 [(set_attr "type" "fpalu")
6108 (set_attr "length" "8")])
6111 [(set (match_operand:DF 0 "register_operand" "")
6112 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6113 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6114 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6115 [(set (match_dup 2) (abs:DF (match_dup 1)))
6116 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6120 [(set (match_operand:SF 0 "register_operand" "=f")
6121 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6122 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6123 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6124 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6126 [(set_attr "type" "fpalu")
6127 (set_attr "length" "8")])
6130 [(set (match_operand:SF 0 "register_operand" "")
6131 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6132 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6133 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6134 [(set (match_dup 2) (abs:SF (match_dup 1)))
6135 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6138 ;;- Shift instructions
6140 ;; Optimized special case of shifting.
6143 [(set (match_operand:SI 0 "register_operand" "=r")
6144 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6148 [(set_attr "type" "load")
6149 (set_attr "length" "4")])
6152 [(set (match_operand:SI 0 "register_operand" "=r")
6153 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6157 [(set_attr "type" "load")
6158 (set_attr "length" "4")])
6161 [(set (match_operand:SI 0 "register_operand" "=r")
6162 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6163 (match_operand:SI 3 "shadd_operand" ""))
6164 (match_operand:SI 1 "register_operand" "r")))]
6166 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6167 [(set_attr "type" "binary")
6168 (set_attr "length" "4")])
6171 [(set (match_operand:DI 0 "register_operand" "=r")
6172 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6173 (match_operand:DI 3 "shadd_operand" ""))
6174 (match_operand:DI 1 "register_operand" "r")))]
6176 "shladd,l %2,%O3,%1,%0"
6177 [(set_attr "type" "binary")
6178 (set_attr "length" "4")])
6180 (define_expand "ashlsi3"
6181 [(set (match_operand:SI 0 "register_operand" "")
6182 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6183 (match_operand:SI 2 "arith32_operand" "")))]
6187 if (GET_CODE (operands[2]) != CONST_INT)
6189 rtx temp = gen_reg_rtx (SImode);
6190 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6191 if (GET_CODE (operands[1]) == CONST_INT)
6192 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6194 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6197 /* Make sure both inputs are not constants,
6198 there are no patterns for that. */
6199 operands[1] = force_reg (SImode, operands[1]);
6203 [(set (match_operand:SI 0 "register_operand" "=r")
6204 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6205 (match_operand:SI 2 "const_int_operand" "n")))]
6207 "{zdep|depw,z} %1,%P2,%L2,%0"
6208 [(set_attr "type" "shift")
6209 (set_attr "length" "4")])
6211 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6212 ; Doing it like this makes slightly better code since reload can
6213 ; replace a register with a known value in range -16..15 with a
6214 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6215 ; but since we have no more CONST_OK... characters, that is not
6217 (define_insn "zvdep32"
6218 [(set (match_operand:SI 0 "register_operand" "=r,r")
6219 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6220 (minus:SI (const_int 31)
6221 (match_operand:SI 2 "register_operand" "q,q"))))]
6224 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6225 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6226 [(set_attr "type" "shift,shift")
6227 (set_attr "length" "4,4")])
6229 (define_insn "zvdep_imm32"
6230 [(set (match_operand:SI 0 "register_operand" "=r")
6231 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6232 (minus:SI (const_int 31)
6233 (match_operand:SI 2 "register_operand" "q"))))]
6237 int x = INTVAL (operands[1]);
6238 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6239 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6240 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6242 [(set_attr "type" "shift")
6243 (set_attr "length" "4")])
6245 (define_insn "vdepi_ior"
6246 [(set (match_operand:SI 0 "register_operand" "=r")
6247 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6248 (minus:SI (const_int 31)
6249 (match_operand:SI 2 "register_operand" "q")))
6250 (match_operand:SI 3 "register_operand" "0")))]
6251 ; accept ...0001...1, can this be generalized?
6252 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6255 int x = INTVAL (operands[1]);
6256 operands[2] = GEN_INT (exact_log2 (x + 1));
6257 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6259 [(set_attr "type" "shift")
6260 (set_attr "length" "4")])
6262 (define_insn "vdepi_and"
6263 [(set (match_operand:SI 0 "register_operand" "=r")
6264 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6265 (minus:SI (const_int 31)
6266 (match_operand:SI 2 "register_operand" "q")))
6267 (match_operand:SI 3 "register_operand" "0")))]
6268 ; this can be generalized...!
6269 "INTVAL (operands[1]) == -2"
6272 int x = INTVAL (operands[1]);
6273 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6274 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6276 [(set_attr "type" "shift")
6277 (set_attr "length" "4")])
6279 (define_expand "ashldi3"
6280 [(set (match_operand:DI 0 "register_operand" "")
6281 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6282 (match_operand:DI 2 "arith32_operand" "")))]
6286 if (GET_CODE (operands[2]) != CONST_INT)
6288 rtx temp = gen_reg_rtx (DImode);
6289 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6290 if (GET_CODE (operands[1]) == CONST_INT)
6291 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6293 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6296 /* Make sure both inputs are not constants,
6297 there are no patterns for that. */
6298 operands[1] = force_reg (DImode, operands[1]);
6302 [(set (match_operand:DI 0 "register_operand" "=r")
6303 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6304 (match_operand:DI 2 "const_int_operand" "n")))]
6306 "depd,z %1,%p2,%Q2,%0"
6307 [(set_attr "type" "shift")
6308 (set_attr "length" "4")])
6310 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6311 ; Doing it like this makes slightly better code since reload can
6312 ; replace a register with a known value in range -16..15 with a
6313 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6314 ; but since we have no more CONST_OK... characters, that is not
6316 (define_insn "zvdep64"
6317 [(set (match_operand:DI 0 "register_operand" "=r,r")
6318 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6319 (minus:DI (const_int 63)
6320 (match_operand:DI 2 "register_operand" "q,q"))))]
6323 depd,z %1,%%sar,64,%0
6324 depdi,z %1,%%sar,64,%0"
6325 [(set_attr "type" "shift,shift")
6326 (set_attr "length" "4,4")])
6328 (define_insn "zvdep_imm64"
6329 [(set (match_operand:DI 0 "register_operand" "=r")
6330 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6331 (minus:DI (const_int 63)
6332 (match_operand:DI 2 "register_operand" "q"))))]
6336 int x = INTVAL (operands[1]);
6337 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6338 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6339 return \"depdi,z %1,%%sar,%2,%0\";
6341 [(set_attr "type" "shift")
6342 (set_attr "length" "4")])
6345 [(set (match_operand:DI 0 "register_operand" "=r")
6346 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6347 (minus:DI (const_int 63)
6348 (match_operand:DI 2 "register_operand" "q")))
6349 (match_operand:DI 3 "register_operand" "0")))]
6350 ; accept ...0001...1, can this be generalized?
6351 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6354 int x = INTVAL (operands[1]);
6355 operands[2] = GEN_INT (exact_log2 (x + 1));
6356 return \"depdi -1,%%sar,%2,%0\";
6358 [(set_attr "type" "shift")
6359 (set_attr "length" "4")])
6362 [(set (match_operand:DI 0 "register_operand" "=r")
6363 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6364 (minus:DI (const_int 63)
6365 (match_operand:DI 2 "register_operand" "q")))
6366 (match_operand:DI 3 "register_operand" "0")))]
6367 ; this can be generalized...!
6368 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6371 int x = INTVAL (operands[1]);
6372 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6373 return \"depdi 0,%%sar,%2,%0\";
6375 [(set_attr "type" "shift")
6376 (set_attr "length" "4")])
6378 (define_expand "ashrsi3"
6379 [(set (match_operand:SI 0 "register_operand" "")
6380 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6381 (match_operand:SI 2 "arith32_operand" "")))]
6385 if (GET_CODE (operands[2]) != CONST_INT)
6387 rtx temp = gen_reg_rtx (SImode);
6388 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6389 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6395 [(set (match_operand:SI 0 "register_operand" "=r")
6396 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6397 (match_operand:SI 2 "const_int_operand" "n")))]
6399 "{extrs|extrw,s} %1,%P2,%L2,%0"
6400 [(set_attr "type" "shift")
6401 (set_attr "length" "4")])
6403 (define_insn "vextrs32"
6404 [(set (match_operand:SI 0 "register_operand" "=r")
6405 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6406 (minus:SI (const_int 31)
6407 (match_operand:SI 2 "register_operand" "q"))))]
6409 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6410 [(set_attr "type" "shift")
6411 (set_attr "length" "4")])
6413 (define_expand "ashrdi3"
6414 [(set (match_operand:DI 0 "register_operand" "")
6415 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6416 (match_operand:DI 2 "arith32_operand" "")))]
6420 if (GET_CODE (operands[2]) != CONST_INT)
6422 rtx temp = gen_reg_rtx (DImode);
6423 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6424 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6430 [(set (match_operand:DI 0 "register_operand" "=r")
6431 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6432 (match_operand:DI 2 "const_int_operand" "n")))]
6434 "extrd,s %1,%p2,%Q2,%0"
6435 [(set_attr "type" "shift")
6436 (set_attr "length" "4")])
6438 (define_insn "vextrs64"
6439 [(set (match_operand:DI 0 "register_operand" "=r")
6440 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6441 (minus:DI (const_int 63)
6442 (match_operand:DI 2 "register_operand" "q"))))]
6444 "extrd,s %1,%%sar,64,%0"
6445 [(set_attr "type" "shift")
6446 (set_attr "length" "4")])
6448 (define_insn "lshrsi3"
6449 [(set (match_operand:SI 0 "register_operand" "=r,r")
6450 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6451 (match_operand:SI 2 "arith32_operand" "q,n")))]
6454 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6455 {extru|extrw,u} %1,%P2,%L2,%0"
6456 [(set_attr "type" "shift")
6457 (set_attr "length" "4")])
6459 (define_insn "lshrdi3"
6460 [(set (match_operand:DI 0 "register_operand" "=r,r")
6461 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6462 (match_operand:DI 2 "arith32_operand" "q,n")))]
6465 shrpd %%r0,%1,%%sar,%0
6466 extrd,u %1,%p2,%Q2,%0"
6467 [(set_attr "type" "shift")
6468 (set_attr "length" "4")])
6470 (define_insn "rotrsi3"
6471 [(set (match_operand:SI 0 "register_operand" "=r,r")
6472 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6473 (match_operand:SI 2 "arith32_operand" "q,n")))]
6477 if (GET_CODE (operands[2]) == CONST_INT)
6479 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6480 return \"{shd|shrpw} %1,%1,%2,%0\";
6483 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6485 [(set_attr "type" "shift")
6486 (set_attr "length" "4")])
6488 (define_expand "rotlsi3"
6489 [(set (match_operand:SI 0 "register_operand" "")
6490 (rotate:SI (match_operand:SI 1 "register_operand" "")
6491 (match_operand:SI 2 "arith32_operand" "")))]
6495 if (GET_CODE (operands[2]) != CONST_INT)
6497 rtx temp = gen_reg_rtx (SImode);
6498 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6499 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6502 /* Else expand normally. */
6506 [(set (match_operand:SI 0 "register_operand" "=r")
6507 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6508 (match_operand:SI 2 "const_int_operand" "n")))]
6512 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6513 return \"{shd|shrpw} %1,%1,%2,%0\";
6515 [(set_attr "type" "shift")
6516 (set_attr "length" "4")])
6519 [(set (match_operand:SI 0 "register_operand" "=r")
6520 (match_operator:SI 5 "plus_xor_ior_operator"
6521 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6522 (match_operand:SI 3 "const_int_operand" "n"))
6523 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6524 (match_operand:SI 4 "const_int_operand" "n"))]))]
6525 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6526 "{shd|shrpw} %1,%2,%4,%0"
6527 [(set_attr "type" "shift")
6528 (set_attr "length" "4")])
6531 [(set (match_operand:SI 0 "register_operand" "=r")
6532 (match_operator:SI 5 "plus_xor_ior_operator"
6533 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6534 (match_operand:SI 4 "const_int_operand" "n"))
6535 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6536 (match_operand:SI 3 "const_int_operand" "n"))]))]
6537 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6538 "{shd|shrpw} %1,%2,%4,%0"
6539 [(set_attr "type" "shift")
6540 (set_attr "length" "4")])
6543 [(set (match_operand:SI 0 "register_operand" "=r")
6544 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6545 (match_operand:SI 2 "const_int_operand" ""))
6546 (match_operand:SI 3 "const_int_operand" "")))]
6547 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6550 int cnt = INTVAL (operands[2]) & 31;
6551 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6552 operands[2] = GEN_INT (31 - cnt);
6553 return \"{zdep|depw,z} %1,%2,%3,%0\";
6555 [(set_attr "type" "shift")
6556 (set_attr "length" "4")])
6558 ;; Unconditional and other jump instructions.
6560 ;; This can only be used in a leaf function, so we do
6561 ;; not need to use the PIC register when generating PIC code.
6562 (define_insn "return"
6566 "hppa_can_use_return_insn_p ()"
6570 return \"bve%* (%%r2)\";
6571 return \"bv%* %%r0(%%r2)\";
6573 [(set_attr "type" "branch")
6574 (set_attr "length" "4")])
6576 ;; Emit a different pattern for functions which have non-trivial
6577 ;; epilogues so as not to confuse jump and reorg.
6578 (define_insn "return_internal"
6586 return \"bve%* (%%r2)\";
6587 return \"bv%* %%r0(%%r2)\";
6589 [(set_attr "type" "branch")
6590 (set_attr "length" "4")])
6592 ;; This is used for eh returns which bypass the return stub.
6593 (define_insn "return_external_pic"
6595 (clobber (reg:SI 1))
6597 "!TARGET_NO_SPACE_REGS
6599 && flag_pic && current_function_calls_eh_return"
6600 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6601 [(set_attr "type" "branch")
6602 (set_attr "length" "12")])
6604 (define_expand "prologue"
6607 "hppa_expand_prologue ();DONE;")
6609 (define_expand "sibcall_epilogue"
6614 hppa_expand_epilogue ();
6618 (define_expand "epilogue"
6623 /* Try to use the trivial return first. Else use the full
6625 if (hppa_can_use_return_insn_p ())
6626 emit_jump_insn (gen_return ());
6631 hppa_expand_epilogue ();
6633 /* EH returns bypass the normal return stub. Thus, we must do an
6634 interspace branch to return from functions that call eh_return.
6635 This is only a problem for returns from shared code on ports
6636 using space registers. */
6637 if (!TARGET_NO_SPACE_REGS
6639 && flag_pic && current_function_calls_eh_return)
6640 x = gen_return_external_pic ();
6642 x = gen_return_internal ();
6649 ; Used by hppa_profile_hook to load the starting address of the current
6650 ; function; operand 1 contains the address of the label in operand 3
6651 (define_insn "load_offset_label_address"
6652 [(set (match_operand:SI 0 "register_operand" "=r")
6653 (plus:SI (match_operand:SI 1 "register_operand" "r")
6654 (minus:SI (match_operand:SI 2 "" "")
6655 (label_ref:SI (match_operand 3 "" "")))))]
6658 [(set_attr "type" "multi")
6659 (set_attr "length" "4")])
6661 ; Output a code label and load its address.
6662 (define_insn "lcla1"
6663 [(set (match_operand:SI 0 "register_operand" "=r")
6664 (label_ref:SI (match_operand 1 "" "")))
6669 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6670 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6671 CODE_LABEL_NUMBER (operands[1]));
6674 [(set_attr "type" "multi")
6675 (set_attr "length" "8")])
6677 (define_insn "lcla2"
6678 [(set (match_operand:SI 0 "register_operand" "=r")
6679 (label_ref:SI (match_operand 1 "" "")))
6684 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6685 CODE_LABEL_NUMBER (operands[1]));
6688 [(set_attr "type" "move")
6689 (set_attr "length" "4")])
6691 (define_insn "blockage"
6692 [(unspec_volatile [(const_int 2)] 0)]
6695 [(set_attr "length" "0")])
6698 [(set (pc) (label_ref (match_operand 0 "" "")))]
6702 /* An unconditional branch which can reach its target. */
6703 if (get_attr_length (insn) != 24
6704 && get_attr_length (insn) != 16)
6707 return output_lbranch (operands[0], insn);
6709 [(set_attr "type" "uncond_branch")
6710 (set_attr "pa_combine_type" "uncond_branch")
6711 (set (attr "length")
6712 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6713 (if_then_else (lt (abs (minus (match_dup 0)
6714 (plus (pc) (const_int 8))))
6718 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6720 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6725 ;;; Hope this is only within a function...
6726 (define_insn "indirect_jump"
6727 [(set (pc) (match_operand 0 "register_operand" "r"))]
6728 "GET_MODE (operands[0]) == word_mode"
6730 [(set_attr "type" "branch")
6731 (set_attr "length" "4")])
6733 ;;; This jump is used in branch tables where the insn length is fixed.
6734 ;;; The length of this insn is adjusted if the delay slot is not filled.
6735 (define_insn "short_jump"
6736 [(set (pc) (label_ref (match_operand 0 "" "")))
6740 [(set_attr "type" "btable_branch")
6741 (set_attr "length" "4")])
6743 ;; Subroutines of "casesi".
6744 ;; operand 0 is index
6745 ;; operand 1 is the minimum bound
6746 ;; operand 2 is the maximum bound - minimum bound + 1
6747 ;; operand 3 is CODE_LABEL for the table;
6748 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6750 (define_expand "casesi"
6751 [(match_operand:SI 0 "general_operand" "")
6752 (match_operand:SI 1 "const_int_operand" "")
6753 (match_operand:SI 2 "const_int_operand" "")
6754 (match_operand 3 "" "")
6755 (match_operand 4 "" "")]
6759 if (GET_CODE (operands[0]) != REG)
6760 operands[0] = force_reg (SImode, operands[0]);
6762 if (operands[1] != const0_rtx)
6764 rtx index = gen_reg_rtx (SImode);
6766 operands[1] = GEN_INT (-INTVAL (operands[1]));
6767 if (!INT_14_BITS (operands[1]))
6768 operands[1] = force_reg (SImode, operands[1]);
6769 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6770 operands[0] = index;
6773 /* In 64bit mode we must make sure to wipe the upper bits of the register
6774 just in case the addition overflowed or we had random bits in the
6775 high part of the register. */
6778 rtx index = gen_reg_rtx (DImode);
6780 emit_insn (gen_extendsidi2 (index, operands[0]));
6781 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6784 if (!INT_5_BITS (operands[2]))
6785 operands[2] = force_reg (SImode, operands[2]);
6787 /* This branch prevents us finding an insn for the delay slot of the
6788 following vectored branch. It might be possible to use the delay
6789 slot if an index value of -1 was used to transfer to the out-of-range
6790 label. In order to do this, we would have to output the -1 vector
6791 element after the delay insn. The casesi output code would have to
6792 check if the casesi insn is in a delay branch sequence and output
6793 the delay insn if one is found. If this was done, then it might
6794 then be worthwhile to split the casesi patterns to improve scheduling.
6795 However, it's not clear that all this extra complexity is worth
6797 emit_insn (gen_cmpsi (operands[0], operands[2]));
6798 emit_jump_insn (gen_bgtu (operands[4]));
6800 if (TARGET_BIG_SWITCH)
6804 rtx tmp1 = gen_reg_rtx (DImode);
6805 rtx tmp2 = gen_reg_rtx (DImode);
6807 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6812 rtx tmp1 = gen_reg_rtx (SImode);
6816 rtx tmp2 = gen_reg_rtx (SImode);
6818 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6822 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
6826 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6830 ;;; The rtl for this pattern doesn't accurately describe what the insn
6831 ;;; actually does, particularly when case-vector elements are exploded
6832 ;;; in pa_reorg. However, the initial SET in these patterns must show
6833 ;;; the connection of the insn to the following jump table.
6834 (define_insn "casesi0"
6835 [(set (pc) (mem:SI (plus:SI
6836 (mult:SI (match_operand:SI 0 "register_operand" "r")
6838 (label_ref (match_operand 1 "" "")))))]
6840 "blr,n %0,%%r0\;nop"
6841 [(set_attr "type" "multi")
6842 (set_attr "length" "8")])
6844 ;;; 32-bit code, absolute branch table.
6845 (define_insn "casesi32"
6846 [(set (pc) (mem:SI (plus:SI
6847 (mult:SI (match_operand:SI 0 "register_operand" "r")
6849 (label_ref (match_operand 1 "" "")))))
6850 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
6851 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6852 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6853 [(set_attr "type" "multi")
6854 (set_attr "length" "16")])
6856 ;;; 32-bit code, relative branch table.
6857 (define_insn "casesi32p"
6858 [(set (pc) (mem:SI (plus:SI
6859 (mult:SI (match_operand:SI 0 "register_operand" "r")
6861 (label_ref (match_operand 1 "" "")))))
6862 (clobber (match_operand:SI 2 "register_operand" "=&a"))
6863 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
6864 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6865 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
6866 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6867 [(set_attr "type" "multi")
6868 (set (attr "length")
6869 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
6873 ;;; 64-bit code, 32-bit relative branch table.
6874 (define_insn "casesi64p"
6875 [(set (pc) (mem:DI (plus:DI
6876 (mult:DI (sign_extend:DI
6877 (match_operand:SI 0 "register_operand" "r"))
6879 (label_ref (match_operand 1 "" "")))))
6880 (clobber (match_operand:DI 2 "register_operand" "=&r"))
6881 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
6882 "TARGET_64BIT && TARGET_BIG_SWITCH"
6883 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6884 add,l %2,%3,%3\;bv,n %%r0(%3)"
6885 [(set_attr "type" "multi")
6886 (set_attr "length" "24")])
6890 ;;- jump to subroutine
6892 (define_expand "call"
6893 [(parallel [(call (match_operand:SI 0 "" "")
6894 (match_operand 1 "" ""))
6895 (clobber (reg:SI 2))])]
6900 rtx nb = operands[1];
6902 if (TARGET_PORTABLE_RUNTIME)
6903 op = force_reg (SImode, XEXP (operands[0], 0));
6905 op = XEXP (operands[0], 0);
6909 if (!virtuals_instantiated)
6910 emit_move_insn (arg_pointer_rtx,
6911 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6915 /* The loop pass can generate new libcalls after the virtual
6916 registers are instantiated when fpregs are disabled because
6917 the only method that we have for doing DImode multiplication
6918 is with a libcall. This could be trouble if we haven't
6919 allocated enough space for the outgoing arguments. */
6920 if (INTVAL (nb) > current_function_outgoing_args_size)
6923 emit_move_insn (arg_pointer_rtx,
6924 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6925 GEN_INT (STACK_POINTER_OFFSET + 64)));
6929 /* Use two different patterns for calls to explicitly named functions
6930 and calls through function pointers. This is necessary as these two
6931 types of calls use different calling conventions, and CSE might try
6932 to change the named call into an indirect call in some cases (using
6933 two patterns keeps CSE from performing this optimization).
6935 We now use even more call patterns as there was a subtle bug in
6936 attempting to restore the pic register after a call using a simple
6937 move insn. During reload, a instruction involving a pseudo register
6938 with no explicit dependence on the PIC register can be converted
6939 to an equivalent load from memory using the PIC register. If we
6940 emit a simple move to restore the PIC register in the initial rtl
6941 generation, then it can potentially be repositioned during scheduling.
6942 and an instruction that eventually uses the PIC register may end up
6943 between the call and the PIC register restore.
6945 This only worked because there is a post call group of instructions
6946 that are scheduled with the call. These instructions are included
6947 in the same basic block as the call. However, calls can throw in
6948 C++ code and a basic block has to terminate at the call if the call
6949 can throw. This results in the PIC register restore being scheduled
6950 independently from the call. So, we now hide the save and restore
6951 of the PIC register in the call pattern until after reload. Then,
6952 we split the moves out. A small side benefit is that we now don't
6953 need to have a use of the PIC register in the return pattern and
6954 the final save/restore operation is not needed.
6956 I elected to just clobber %r4 in the PIC patterns and use it instead
6957 of trying to force hppa_pic_save_rtx () to a callee saved register.
6958 This might have required a new register class and constraint. It
6959 was also simpler to just handle the restore from a register than a
6963 if (GET_CODE (op) == SYMBOL_REF)
6964 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
6967 op = force_reg (word_mode, op);
6968 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
6973 if (GET_CODE (op) == SYMBOL_REF)
6976 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
6978 call_insn = emit_call_insn (gen_call_symref (op, nb));
6982 rtx tmpreg = gen_rtx_REG (word_mode, 22);
6984 emit_move_insn (tmpreg, force_reg (word_mode, op));
6986 call_insn = emit_call_insn (gen_call_reg_pic (nb));
6988 call_insn = emit_call_insn (gen_call_reg (nb));
6995 ;; We use function calls to set the attribute length of calls and millicode
6996 ;; calls. This is necessary because of the large variety of call sequences.
6997 ;; Implementing the calculation in rtl is difficult as well as ugly. As
6998 ;; we need the same calculation in several places, maintenance becomes a
7001 ;; However, this has a subtle impact on branch shortening. When the
7002 ;; expression used to set the length attribute of an instruction depends
7003 ;; on a relative address (e.g., pc or a branch address), genattrtab
7004 ;; notes that the insn's length is variable, and attempts to determine a
7005 ;; worst-case default length and code to compute an insn's current length.
7007 ;; The use of a function call hides the variable dependence of our calls
7008 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7009 ;; as variable and it only generates code for the default case using our
7010 ;; function call. Because of this, calls and millicode calls have a fixed
7011 ;; length in the branch shortening pass, and some branches will use a longer
7012 ;; code sequence than necessary. However, the length of any given call
7013 ;; will still reflect its final code location and it may be shorter than
7014 ;; the initial length estimate.
7016 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7017 ;; in the set. However, when genattrtab hits a function call in its attempt
7018 ;; to compute the default length, it marks the result as unknown and sets
7019 ;; the default result to MAX_INT ;-( One possible fix that would allow
7020 ;; calls to participate in branch shortening would be to make the call to
7021 ;; insn_default_length a target option. Then, we could massage unknown
7022 ;; results. Another fix might be to change genattrtab so that it just does
7023 ;; the call in the variable case as it already does for the fixed case.
7025 (define_insn "call_symref"
7026 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7027 (match_operand 1 "" "i"))
7028 (clobber (reg:SI 1))
7029 (clobber (reg:SI 2))
7030 (use (const_int 0))]
7031 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7034 output_arg_descriptor (insn);
7035 return output_call (insn, operands[0], 0);
7037 [(set_attr "type" "call")
7038 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7040 (define_insn "call_symref_pic"
7041 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7042 (match_operand 1 "" "i"))
7043 (clobber (reg:SI 1))
7044 (clobber (reg:SI 2))
7045 (clobber (reg:SI 4))
7047 (use (const_int 0))]
7048 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7051 output_arg_descriptor (insn);
7052 return output_call (insn, operands[0], 0);
7054 [(set_attr "type" "call")
7055 (set (attr "length")
7056 (plus (symbol_ref "attr_length_call (insn, 0)")
7057 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7059 ;; Split out the PIC register save and restore after reload. This is
7060 ;; done only if the function returns. As the split is done after reload,
7061 ;; there are some situations in which we unnecessarily save and restore
7062 ;; %r4. This happens when there is a single call and the PIC register
7063 ;; is "dead" after the call. This isn't easy to fix as the usage of
7064 ;; the PIC register isn't completely determined until the reload pass.
7066 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7067 (match_operand 1 "" ""))
7068 (clobber (reg:SI 1))
7069 (clobber (reg:SI 2))
7070 (clobber (reg:SI 4))
7072 (use (const_int 0))])]
7073 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7075 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7076 [(set (reg:SI 4) (reg:SI 19))
7077 (parallel [(call (mem:SI (match_dup 0))
7079 (clobber (reg:SI 1))
7080 (clobber (reg:SI 2))
7082 (use (const_int 0))])
7083 (set (reg:SI 19) (reg:SI 4))]
7086 ;; Remove the clobber of register 4 when optimizing. This has to be
7087 ;; done with a peephole optimization rather than a split because the
7088 ;; split sequence for a call must be longer than one instruction.
7090 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7091 (match_operand 1 "" ""))
7092 (clobber (reg:SI 1))
7093 (clobber (reg:SI 2))
7094 (clobber (reg:SI 4))
7096 (use (const_int 0))])]
7097 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7098 [(parallel [(call (mem:SI (match_dup 0))
7100 (clobber (reg:SI 1))
7101 (clobber (reg:SI 2))
7103 (use (const_int 0))])]
7106 (define_insn "*call_symref_pic_post_reload"
7107 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7108 (match_operand 1 "" "i"))
7109 (clobber (reg:SI 1))
7110 (clobber (reg:SI 2))
7112 (use (const_int 0))]
7113 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7116 output_arg_descriptor (insn);
7117 return output_call (insn, operands[0], 0);
7119 [(set_attr "type" "call")
7120 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7122 ;; This pattern is split if it is necessary to save and restore the
7124 (define_insn "call_symref_64bit"
7125 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7126 (match_operand 1 "" "i"))
7127 (clobber (reg:DI 1))
7128 (clobber (reg:DI 2))
7129 (clobber (reg:DI 4))
7132 (use (const_int 0))]
7136 output_arg_descriptor (insn);
7137 return output_call (insn, operands[0], 0);
7139 [(set_attr "type" "call")
7140 (set (attr "length")
7141 (plus (symbol_ref "attr_length_call (insn, 0)")
7142 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7144 ;; Split out the PIC register save and restore after reload. This is
7145 ;; done only if the function returns. As the split is done after reload,
7146 ;; there are some situations in which we unnecessarily save and restore
7147 ;; %r4. This happens when there is a single call and the PIC register
7148 ;; is "dead" after the call. This isn't easy to fix as the usage of
7149 ;; the PIC register isn't completely determined until the reload pass.
7151 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7152 (match_operand 1 "" ""))
7153 (clobber (reg:DI 1))
7154 (clobber (reg:DI 2))
7155 (clobber (reg:DI 4))
7158 (use (const_int 0))])]
7161 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7162 [(set (reg:DI 4) (reg:DI 27))
7163 (parallel [(call (mem:SI (match_dup 0))
7165 (clobber (reg:DI 1))
7166 (clobber (reg:DI 2))
7169 (use (const_int 0))])
7170 (set (reg:DI 27) (reg:DI 4))]
7173 ;; Remove the clobber of register 4 when optimizing. This has to be
7174 ;; done with a peephole optimization rather than a split because the
7175 ;; split sequence for a call must be longer than one instruction.
7177 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7178 (match_operand 1 "" ""))
7179 (clobber (reg:DI 1))
7180 (clobber (reg:DI 2))
7181 (clobber (reg:DI 4))
7184 (use (const_int 0))])]
7185 "TARGET_64BIT && reload_completed"
7186 [(parallel [(call (mem:SI (match_dup 0))
7188 (clobber (reg:DI 1))
7189 (clobber (reg:DI 2))
7192 (use (const_int 0))])]
7195 (define_insn "*call_symref_64bit_post_reload"
7196 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7197 (match_operand 1 "" "i"))
7198 (clobber (reg:DI 1))
7199 (clobber (reg:DI 2))
7202 (use (const_int 0))]
7206 output_arg_descriptor (insn);
7207 return output_call (insn, operands[0], 0);
7209 [(set_attr "type" "call")
7210 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7212 (define_insn "call_reg"
7213 [(call (mem:SI (reg:SI 22))
7214 (match_operand 0 "" "i"))
7215 (clobber (reg:SI 1))
7216 (clobber (reg:SI 2))
7217 (use (const_int 1))]
7221 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7223 [(set_attr "type" "dyncall")
7224 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7226 ;; This pattern is split if it is necessary to save and restore the
7228 (define_insn "call_reg_pic"
7229 [(call (mem:SI (reg:SI 22))
7230 (match_operand 0 "" "i"))
7231 (clobber (reg:SI 1))
7232 (clobber (reg:SI 2))
7233 (clobber (reg:SI 4))
7235 (use (const_int 1))]
7239 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7241 [(set_attr "type" "dyncall")
7242 (set (attr "length")
7243 (plus (symbol_ref "attr_length_indirect_call (insn)")
7244 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7246 ;; Split out the PIC register save and restore after reload. This is
7247 ;; done only if the function returns. As the split is done after reload,
7248 ;; there are some situations in which we unnecessarily save and restore
7249 ;; %r4. This happens when there is a single call and the PIC register
7250 ;; is "dead" after the call. This isn't easy to fix as the usage of
7251 ;; the PIC register isn't completely determined until the reload pass.
7253 [(parallel [(call (mem:SI (reg:SI 22))
7254 (match_operand 0 "" ""))
7255 (clobber (reg:SI 1))
7256 (clobber (reg:SI 2))
7257 (clobber (reg:SI 4))
7259 (use (const_int 1))])]
7262 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7263 [(set (reg:SI 4) (reg:SI 19))
7264 (parallel [(call (mem:SI (reg:SI 22))
7266 (clobber (reg:SI 1))
7267 (clobber (reg:SI 2))
7269 (use (const_int 1))])
7270 (set (reg:SI 19) (reg:SI 4))]
7273 ;; Remove the clobber of register 4 when optimizing. This has to be
7274 ;; done with a peephole optimization rather than a split because the
7275 ;; split sequence for a call must be longer than one instruction.
7277 [(parallel [(call (mem:SI (reg:SI 22))
7278 (match_operand 0 "" ""))
7279 (clobber (reg:SI 1))
7280 (clobber (reg:SI 2))
7281 (clobber (reg:SI 4))
7283 (use (const_int 1))])]
7284 "!TARGET_64BIT && reload_completed"
7285 [(parallel [(call (mem:SI (reg:SI 22))
7287 (clobber (reg:SI 1))
7288 (clobber (reg:SI 2))
7290 (use (const_int 1))])]
7293 (define_insn "*call_reg_pic_post_reload"
7294 [(call (mem:SI (reg:SI 22))
7295 (match_operand 0 "" "i"))
7296 (clobber (reg:SI 1))
7297 (clobber (reg:SI 2))
7299 (use (const_int 1))]
7303 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7305 [(set_attr "type" "dyncall")
7306 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7308 ;; This pattern is split if it is necessary to save and restore the
7310 (define_insn "call_reg_64bit"
7311 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7312 (match_operand 1 "" "i"))
7313 (clobber (reg:DI 2))
7314 (clobber (reg:DI 4))
7317 (use (const_int 1))]
7321 return output_indirect_call (insn, operands[0]);
7323 [(set_attr "type" "dyncall")
7324 (set (attr "length")
7325 (plus (symbol_ref "attr_length_indirect_call (insn)")
7326 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7328 ;; Split out the PIC register save and restore after reload. This is
7329 ;; done only if the function returns. As the split is done after reload,
7330 ;; there are some situations in which we unnecessarily save and restore
7331 ;; %r4. This happens when there is a single call and the PIC register
7332 ;; is "dead" after the call. This isn't easy to fix as the usage of
7333 ;; the PIC register isn't completely determined until the reload pass.
7335 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7336 (match_operand 1 "" ""))
7337 (clobber (reg:DI 2))
7338 (clobber (reg:DI 4))
7341 (use (const_int 1))])]
7344 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7345 [(set (reg:DI 4) (reg:DI 27))
7346 (parallel [(call (mem:SI (match_dup 0))
7348 (clobber (reg:DI 2))
7351 (use (const_int 1))])
7352 (set (reg:DI 27) (reg:DI 4))]
7355 ;; Remove the clobber of register 4 when optimizing. This has to be
7356 ;; done with a peephole optimization rather than a split because the
7357 ;; split sequence for a call must be longer than one instruction.
7359 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7360 (match_operand 1 "" ""))
7361 (clobber (reg:DI 2))
7362 (clobber (reg:DI 4))
7365 (use (const_int 1))])]
7366 "TARGET_64BIT && reload_completed"
7367 [(parallel [(call (mem:SI (match_dup 0))
7369 (clobber (reg:DI 2))
7372 (use (const_int 1))])]
7375 (define_insn "*call_reg_64bit_post_reload"
7376 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7377 (match_operand 1 "" "i"))
7378 (clobber (reg:DI 2))
7381 (use (const_int 1))]
7385 return output_indirect_call (insn, operands[0]);
7387 [(set_attr "type" "dyncall")
7388 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7390 (define_expand "call_value"
7391 [(parallel [(set (match_operand 0 "" "")
7392 (call (match_operand:SI 1 "" "")
7393 (match_operand 2 "" "")))
7394 (clobber (reg:SI 2))])]
7399 rtx dst = operands[0];
7400 rtx nb = operands[2];
7402 if (TARGET_PORTABLE_RUNTIME)
7403 op = force_reg (SImode, XEXP (operands[1], 0));
7405 op = XEXP (operands[1], 0);
7409 if (!virtuals_instantiated)
7410 emit_move_insn (arg_pointer_rtx,
7411 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7415 /* The loop pass can generate new libcalls after the virtual
7416 registers are instantiated when fpregs are disabled because
7417 the only method that we have for doing DImode multiplication
7418 is with a libcall. This could be trouble if we haven't
7419 allocated enough space for the outgoing arguments. */
7420 if (INTVAL (nb) > current_function_outgoing_args_size)
7423 emit_move_insn (arg_pointer_rtx,
7424 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7425 GEN_INT (STACK_POINTER_OFFSET + 64)));
7429 /* Use two different patterns for calls to explicitly named functions
7430 and calls through function pointers. This is necessary as these two
7431 types of calls use different calling conventions, and CSE might try
7432 to change the named call into an indirect call in some cases (using
7433 two patterns keeps CSE from performing this optimization).
7435 We now use even more call patterns as there was a subtle bug in
7436 attempting to restore the pic register after a call using a simple
7437 move insn. During reload, a instruction involving a pseudo register
7438 with no explicit dependence on the PIC register can be converted
7439 to an equivalent load from memory using the PIC register. If we
7440 emit a simple move to restore the PIC register in the initial rtl
7441 generation, then it can potentially be repositioned during scheduling.
7442 and an instruction that eventually uses the PIC register may end up
7443 between the call and the PIC register restore.
7445 This only worked because there is a post call group of instructions
7446 that are scheduled with the call. These instructions are included
7447 in the same basic block as the call. However, calls can throw in
7448 C++ code and a basic block has to terminate at the call if the call
7449 can throw. This results in the PIC register restore being scheduled
7450 independently from the call. So, we now hide the save and restore
7451 of the PIC register in the call pattern until after reload. Then,
7452 we split the moves out. A small side benefit is that we now don't
7453 need to have a use of the PIC register in the return pattern and
7454 the final save/restore operation is not needed.
7456 I elected to just clobber %r4 in the PIC patterns and use it instead
7457 of trying to force hppa_pic_save_rtx () to a callee saved register.
7458 This might have required a new register class and constraint. It
7459 was also simpler to just handle the restore from a register than a
7463 if (GET_CODE (op) == SYMBOL_REF)
7464 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7467 op = force_reg (word_mode, op);
7468 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7473 if (GET_CODE (op) == SYMBOL_REF)
7476 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7478 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7482 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7484 emit_move_insn (tmpreg, force_reg (word_mode, op));
7486 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7488 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7495 (define_insn "call_val_symref"
7496 [(set (match_operand 0 "" "")
7497 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7498 (match_operand 2 "" "i")))
7499 (clobber (reg:SI 1))
7500 (clobber (reg:SI 2))
7501 (use (const_int 0))]
7502 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7505 output_arg_descriptor (insn);
7506 return output_call (insn, operands[1], 0);
7508 [(set_attr "type" "call")
7509 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7511 (define_insn "call_val_symref_pic"
7512 [(set (match_operand 0 "" "")
7513 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7514 (match_operand 2 "" "i")))
7515 (clobber (reg:SI 1))
7516 (clobber (reg:SI 2))
7517 (clobber (reg:SI 4))
7519 (use (const_int 0))]
7520 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7523 output_arg_descriptor (insn);
7524 return output_call (insn, operands[1], 0);
7526 [(set_attr "type" "call")
7527 (set (attr "length")
7528 (plus (symbol_ref "attr_length_call (insn, 0)")
7529 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7531 ;; Split out the PIC register save and restore after reload. This is
7532 ;; done only if the function returns. As the split is done after reload,
7533 ;; there are some situations in which we unnecessarily save and restore
7534 ;; %r4. This happens when there is a single call and the PIC register
7535 ;; is "dead" after the call. This isn't easy to fix as the usage of
7536 ;; the PIC register isn't completely determined until the reload pass.
7538 [(parallel [(set (match_operand 0 "" "")
7539 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7540 (match_operand 2 "" "")))
7541 (clobber (reg:SI 1))
7542 (clobber (reg:SI 2))
7543 (clobber (reg:SI 4))
7545 (use (const_int 0))])]
7546 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7548 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7549 [(set (reg:SI 4) (reg:SI 19))
7550 (parallel [(set (match_dup 0)
7551 (call (mem:SI (match_dup 1))
7553 (clobber (reg:SI 1))
7554 (clobber (reg:SI 2))
7556 (use (const_int 0))])
7557 (set (reg:SI 19) (reg:SI 4))]
7560 ;; Remove the clobber of register 4 when optimizing. This has to be
7561 ;; done with a peephole optimization rather than a split because the
7562 ;; split sequence for a call must be longer than one instruction.
7564 [(parallel [(set (match_operand 0 "" "")
7565 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7566 (match_operand 2 "" "")))
7567 (clobber (reg:SI 1))
7568 (clobber (reg:SI 2))
7569 (clobber (reg:SI 4))
7571 (use (const_int 0))])]
7572 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7573 [(parallel [(set (match_dup 0)
7574 (call (mem:SI (match_dup 1))
7576 (clobber (reg:SI 1))
7577 (clobber (reg:SI 2))
7579 (use (const_int 0))])]
7582 (define_insn "*call_val_symref_pic_post_reload"
7583 [(set (match_operand 0 "" "")
7584 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7585 (match_operand 2 "" "i")))
7586 (clobber (reg:SI 1))
7587 (clobber (reg:SI 2))
7589 (use (const_int 0))]
7590 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7593 output_arg_descriptor (insn);
7594 return output_call (insn, operands[1], 0);
7596 [(set_attr "type" "call")
7597 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7599 ;; This pattern is split if it is necessary to save and restore the
7601 (define_insn "call_val_symref_64bit"
7602 [(set (match_operand 0 "" "")
7603 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7604 (match_operand 2 "" "i")))
7605 (clobber (reg:DI 1))
7606 (clobber (reg:DI 2))
7607 (clobber (reg:DI 4))
7610 (use (const_int 0))]
7614 output_arg_descriptor (insn);
7615 return output_call (insn, operands[1], 0);
7617 [(set_attr "type" "call")
7618 (set (attr "length")
7619 (plus (symbol_ref "attr_length_call (insn, 0)")
7620 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7622 ;; Split out the PIC register save and restore after reload. This is
7623 ;; done only if the function returns. As the split is done after reload,
7624 ;; there are some situations in which we unnecessarily save and restore
7625 ;; %r4. This happens when there is a single call and the PIC register
7626 ;; is "dead" after the call. This isn't easy to fix as the usage of
7627 ;; the PIC register isn't completely determined until the reload pass.
7629 [(parallel [(set (match_operand 0 "" "")
7630 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7631 (match_operand 2 "" "")))
7632 (clobber (reg:DI 1))
7633 (clobber (reg:DI 2))
7634 (clobber (reg:DI 4))
7637 (use (const_int 0))])]
7640 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7641 [(set (reg:DI 4) (reg:DI 27))
7642 (parallel [(set (match_dup 0)
7643 (call (mem:SI (match_dup 1))
7645 (clobber (reg:DI 1))
7646 (clobber (reg:DI 2))
7649 (use (const_int 0))])
7650 (set (reg:DI 27) (reg:DI 4))]
7653 ;; Remove the clobber of register 4 when optimizing. This has to be
7654 ;; done with a peephole optimization rather than a split because the
7655 ;; split sequence for a call must be longer than one instruction.
7657 [(parallel [(set (match_operand 0 "" "")
7658 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7659 (match_operand 2 "" "")))
7660 (clobber (reg:DI 1))
7661 (clobber (reg:DI 2))
7662 (clobber (reg:DI 4))
7665 (use (const_int 0))])]
7666 "TARGET_64BIT && reload_completed"
7667 [(parallel [(set (match_dup 0)
7668 (call (mem:SI (match_dup 1))
7670 (clobber (reg:DI 1))
7671 (clobber (reg:DI 2))
7674 (use (const_int 0))])]
7677 (define_insn "*call_val_symref_64bit_post_reload"
7678 [(set (match_operand 0 "" "")
7679 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7680 (match_operand 2 "" "i")))
7681 (clobber (reg:DI 1))
7682 (clobber (reg:DI 2))
7685 (use (const_int 0))]
7689 output_arg_descriptor (insn);
7690 return output_call (insn, operands[1], 0);
7692 [(set_attr "type" "call")
7693 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7695 (define_insn "call_val_reg"
7696 [(set (match_operand 0 "" "")
7697 (call (mem:SI (reg:SI 22))
7698 (match_operand 1 "" "i")))
7699 (clobber (reg:SI 1))
7700 (clobber (reg:SI 2))
7701 (use (const_int 1))]
7705 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7707 [(set_attr "type" "dyncall")
7708 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7710 ;; This pattern is split if it is necessary to save and restore the
7712 (define_insn "call_val_reg_pic"
7713 [(set (match_operand 0 "" "")
7714 (call (mem:SI (reg:SI 22))
7715 (match_operand 1 "" "i")))
7716 (clobber (reg:SI 1))
7717 (clobber (reg:SI 2))
7718 (clobber (reg:SI 4))
7720 (use (const_int 1))]
7724 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7726 [(set_attr "type" "dyncall")
7727 (set (attr "length")
7728 (plus (symbol_ref "attr_length_indirect_call (insn)")
7729 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7731 ;; Split out the PIC register save and restore after reload. This is
7732 ;; done only if the function returns. As the split is done after reload,
7733 ;; there are some situations in which we unnecessarily save and restore
7734 ;; %r4. This happens when there is a single call and the PIC register
7735 ;; is "dead" after the call. This isn't easy to fix as the usage of
7736 ;; the PIC register isn't completely determined until the reload pass.
7738 [(parallel [(set (match_operand 0 "" "")
7739 (call (mem:SI (reg:SI 22))
7740 (match_operand 1 "" "")))
7741 (clobber (reg:SI 1))
7742 (clobber (reg:SI 2))
7743 (clobber (reg:SI 4))
7745 (use (const_int 1))])]
7748 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7749 [(set (reg:SI 4) (reg:SI 19))
7750 (parallel [(set (match_dup 0)
7751 (call (mem:SI (reg:SI 22))
7753 (clobber (reg:SI 1))
7754 (clobber (reg:SI 2))
7756 (use (const_int 1))])
7757 (set (reg:SI 19) (reg:SI 4))]
7760 ;; Remove the clobber of register 4 when optimizing. This has to be
7761 ;; done with a peephole optimization rather than a split because the
7762 ;; split sequence for a call must be longer than one instruction.
7764 [(parallel [(set (match_operand 0 "" "")
7765 (call (mem:SI (reg:SI 22))
7766 (match_operand 1 "" "")))
7767 (clobber (reg:SI 1))
7768 (clobber (reg:SI 2))
7769 (clobber (reg:SI 4))
7771 (use (const_int 1))])]
7772 "!TARGET_64BIT && reload_completed"
7773 [(parallel [(set (match_dup 0)
7774 (call (mem:SI (reg:SI 22))
7776 (clobber (reg:SI 1))
7777 (clobber (reg:SI 2))
7779 (use (const_int 1))])]
7782 (define_insn "*call_val_reg_pic_post_reload"
7783 [(set (match_operand 0 "" "")
7784 (call (mem:SI (reg:SI 22))
7785 (match_operand 1 "" "i")))
7786 (clobber (reg:SI 1))
7787 (clobber (reg:SI 2))
7789 (use (const_int 1))]
7793 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7795 [(set_attr "type" "dyncall")
7796 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7798 ;; This pattern is split if it is necessary to save and restore the
7800 (define_insn "call_val_reg_64bit"
7801 [(set (match_operand 0 "" "")
7802 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7803 (match_operand 2 "" "i")))
7804 (clobber (reg:DI 2))
7805 (clobber (reg:DI 4))
7808 (use (const_int 1))]
7812 return output_indirect_call (insn, operands[1]);
7814 [(set_attr "type" "dyncall")
7815 (set (attr "length")
7816 (plus (symbol_ref "attr_length_indirect_call (insn)")
7817 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7819 ;; Split out the PIC register save and restore after reload. This is
7820 ;; done only if the function returns. As the split is done after reload,
7821 ;; there are some situations in which we unnecessarily save and restore
7822 ;; %r4. This happens when there is a single call and the PIC register
7823 ;; is "dead" after the call. This isn't easy to fix as the usage of
7824 ;; the PIC register isn't completely determined until the reload pass.
7826 [(parallel [(set (match_operand 0 "" "")
7827 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7828 (match_operand 2 "" "")))
7829 (clobber (reg:DI 2))
7830 (clobber (reg:DI 4))
7833 (use (const_int 1))])]
7836 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7837 [(set (reg:DI 4) (reg:DI 27))
7838 (parallel [(set (match_dup 0)
7839 (call (mem:SI (match_dup 1))
7841 (clobber (reg:DI 2))
7844 (use (const_int 1))])
7845 (set (reg:DI 27) (reg:DI 4))]
7848 ;; Remove the clobber of register 4 when optimizing. This has to be
7849 ;; done with a peephole optimization rather than a split because the
7850 ;; split sequence for a call must be longer than one instruction.
7852 [(parallel [(set (match_operand 0 "" "")
7853 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7854 (match_operand 2 "" "")))
7855 (clobber (reg:DI 2))
7856 (clobber (reg:DI 4))
7859 (use (const_int 1))])]
7860 "TARGET_64BIT && reload_completed"
7861 [(parallel [(set (match_dup 0)
7862 (call (mem:SI (match_dup 1))
7864 (clobber (reg:DI 2))
7867 (use (const_int 1))])]
7870 (define_insn "*call_val_reg_64bit_post_reload"
7871 [(set (match_operand 0 "" "")
7872 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7873 (match_operand 2 "" "i")))
7874 (clobber (reg:DI 2))
7877 (use (const_int 1))]
7881 return output_indirect_call (insn, operands[1]);
7883 [(set_attr "type" "dyncall")
7884 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7886 ;; Call subroutine returning any type.
7888 (define_expand "untyped_call"
7889 [(parallel [(call (match_operand 0 "" "")
7891 (match_operand 1 "" "")
7892 (match_operand 2 "" "")])]
7898 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7900 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7902 rtx set = XVECEXP (operands[2], 0, i);
7903 emit_move_insn (SET_DEST (set), SET_SRC (set));
7906 /* The optimizer does not know that the call sets the function value
7907 registers we stored in the result block. We avoid problems by
7908 claiming that all hard registers are used and clobbered at this
7910 emit_insn (gen_blockage ());
7915 (define_expand "sibcall"
7916 [(call (match_operand:SI 0 "" "")
7917 (match_operand 1 "" ""))]
7918 "!TARGET_PORTABLE_RUNTIME"
7922 rtx nb = operands[1];
7924 op = XEXP (operands[0], 0);
7928 if (!virtuals_instantiated)
7929 emit_move_insn (arg_pointer_rtx,
7930 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7934 /* The loop pass can generate new libcalls after the virtual
7935 registers are instantiated when fpregs are disabled because
7936 the only method that we have for doing DImode multiplication
7937 is with a libcall. This could be trouble if we haven't
7938 allocated enough space for the outgoing arguments. */
7939 if (INTVAL (nb) > current_function_outgoing_args_size)
7942 emit_move_insn (arg_pointer_rtx,
7943 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7944 GEN_INT (STACK_POINTER_OFFSET + 64)));
7948 /* Indirect sibling calls are not allowed. */
7950 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
7952 call_insn = gen_sibcall_internal_symref (op, operands[1]);
7954 call_insn = emit_call_insn (call_insn);
7957 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
7959 /* We don't have to restore the PIC register. */
7961 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
7966 (define_insn "sibcall_internal_symref"
7967 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7968 (match_operand 1 "" "i"))
7969 (clobber (reg:SI 1))
7971 (use (const_int 0))]
7972 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7975 output_arg_descriptor (insn);
7976 return output_call (insn, operands[0], 1);
7978 [(set_attr "type" "call")
7979 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
7981 (define_insn "sibcall_internal_symref_64bit"
7982 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7983 (match_operand 1 "" "i"))
7984 (clobber (reg:DI 1))
7986 (use (const_int 0))]
7990 output_arg_descriptor (insn);
7991 return output_call (insn, operands[0], 1);
7993 [(set_attr "type" "call")
7994 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
7996 (define_expand "sibcall_value"
7997 [(set (match_operand 0 "" "")
7998 (call (match_operand:SI 1 "" "")
7999 (match_operand 2 "" "")))]
8000 "!TARGET_PORTABLE_RUNTIME"
8004 rtx nb = operands[1];
8006 op = XEXP (operands[1], 0);
8010 if (!virtuals_instantiated)
8011 emit_move_insn (arg_pointer_rtx,
8012 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8016 /* The loop pass can generate new libcalls after the virtual
8017 registers are instantiated when fpregs are disabled because
8018 the only method that we have for doing DImode multiplication
8019 is with a libcall. This could be trouble if we haven't
8020 allocated enough space for the outgoing arguments. */
8021 if (INTVAL (nb) > current_function_outgoing_args_size)
8024 emit_move_insn (arg_pointer_rtx,
8025 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8026 GEN_INT (STACK_POINTER_OFFSET + 64)));
8030 /* Indirect sibling calls are not allowed. */
8033 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8036 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8038 call_insn = emit_call_insn (call_insn);
8041 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8043 /* We don't have to restore the PIC register. */
8045 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8050 (define_insn "sibcall_value_internal_symref"
8051 [(set (match_operand 0 "" "")
8052 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8053 (match_operand 2 "" "i")))
8054 (clobber (reg:SI 1))
8056 (use (const_int 0))]
8057 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8060 output_arg_descriptor (insn);
8061 return output_call (insn, operands[1], 1);
8063 [(set_attr "type" "call")
8064 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8066 (define_insn "sibcall_value_internal_symref_64bit"
8067 [(set (match_operand 0 "" "")
8068 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8069 (match_operand 2 "" "i")))
8070 (clobber (reg:DI 1))
8072 (use (const_int 0))]
8076 output_arg_descriptor (insn);
8077 return output_call (insn, operands[1], 1);
8079 [(set_attr "type" "call")
8080 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8086 [(set_attr "type" "move")
8087 (set_attr "length" "4")])
8089 ;; These are just placeholders so we know where branch tables
8091 (define_insn "begin_brtab"
8096 /* Only GAS actually supports this pseudo-op. */
8098 return \".begin_brtab\";
8102 [(set_attr "type" "move")
8103 (set_attr "length" "0")])
8105 (define_insn "end_brtab"
8110 /* Only GAS actually supports this pseudo-op. */
8112 return \".end_brtab\";
8116 [(set_attr "type" "move")
8117 (set_attr "length" "0")])
8119 ;;; EH does longjmp's from and within the data section. Thus,
8120 ;;; an interspace branch is required for the longjmp implementation.
8121 ;;; Registers r1 and r2 are used as scratch registers for the jump
8123 (define_expand "interspace_jump"
8125 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8126 (clobber (match_dup 1))])]
8130 operands[1] = gen_rtx_REG (word_mode, 2);
8134 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8135 (clobber (reg:SI 2))]
8136 "TARGET_PA_20 && !TARGET_64BIT"
8138 [(set_attr "type" "branch")
8139 (set_attr "length" "4")])
8142 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8143 (clobber (reg:SI 2))]
8144 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8146 [(set_attr "type" "branch")
8147 (set_attr "length" "4")])
8150 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8151 (clobber (reg:SI 2))]
8153 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
8154 [(set_attr "type" "branch")
8155 (set_attr "length" "12")])
8158 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8159 (clobber (reg:DI 2))]
8162 [(set_attr "type" "branch")
8163 (set_attr "length" "4")])
8165 (define_expand "builtin_longjmp"
8166 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
8170 /* The elements of the buffer are, in order: */
8171 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8172 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8173 POINTER_SIZE / BITS_PER_UNIT));
8174 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8175 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8176 rtx pv = gen_rtx_REG (Pmode, 1);
8178 /* This bit is the same as expand_builtin_longjmp. */
8179 emit_move_insn (hard_frame_pointer_rtx, fp);
8180 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8181 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8182 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8184 /* Load the label we are jumping through into r1 so that we know
8185 where to look for it when we get back to setjmp's function for
8186 restoring the gp. */
8187 emit_move_insn (pv, lab);
8189 /* Prevent the insns above from being scheduled into the delay slot
8190 of the interspace jump because the space register could change. */
8191 emit_insn (gen_blockage ());
8193 emit_jump_insn (gen_interspace_jump (pv));
8198 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8199 (define_expand "extzv"
8200 [(set (match_operand 0 "register_operand" "")
8201 (zero_extract (match_operand 1 "register_operand" "")
8202 (match_operand 2 "uint32_operand" "")
8203 (match_operand 3 "uint32_operand" "")))]
8207 HOST_WIDE_INT len = INTVAL (operands[2]);
8208 HOST_WIDE_INT pos = INTVAL (operands[3]);
8210 /* PA extraction insns don't support zero length bitfields or fields
8211 extending beyond the left or right-most bits. Also, we reject lengths
8212 equal to a word as they are better handled by the move patterns. */
8213 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8216 /* From mips.md: extract_bit_field doesn't verify that our source
8217 matches the predicate, so check it again here. */
8218 if (!register_operand (operands[1], VOIDmode))
8222 emit_insn (gen_extzv_64 (operands[0], operands[1],
8223 operands[2], operands[3]));
8225 emit_insn (gen_extzv_32 (operands[0], operands[1],
8226 operands[2], operands[3]));
8230 (define_insn "extzv_32"
8231 [(set (match_operand:SI 0 "register_operand" "=r")
8232 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8233 (match_operand:SI 2 "uint5_operand" "")
8234 (match_operand:SI 3 "uint5_operand" "")))]
8236 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8237 [(set_attr "type" "shift")
8238 (set_attr "length" "4")])
8241 [(set (match_operand:SI 0 "register_operand" "=r")
8242 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8244 (match_operand:SI 2 "register_operand" "q")))]
8246 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8247 [(set_attr "type" "shift")
8248 (set_attr "length" "4")])
8250 (define_insn "extzv_64"
8251 [(set (match_operand:DI 0 "register_operand" "=r")
8252 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8253 (match_operand:DI 2 "uint32_operand" "")
8254 (match_operand:DI 3 "uint32_operand" "")))]
8256 "extrd,u %1,%3+%2-1,%2,%0"
8257 [(set_attr "type" "shift")
8258 (set_attr "length" "4")])
8261 [(set (match_operand:DI 0 "register_operand" "=r")
8262 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8264 (match_operand:DI 2 "register_operand" "q")))]
8266 "extrd,u %1,%%sar,1,%0"
8267 [(set_attr "type" "shift")
8268 (set_attr "length" "4")])
8270 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8271 (define_expand "extv"
8272 [(set (match_operand 0 "register_operand" "")
8273 (sign_extract (match_operand 1 "register_operand" "")
8274 (match_operand 2 "uint32_operand" "")
8275 (match_operand 3 "uint32_operand" "")))]
8279 HOST_WIDE_INT len = INTVAL (operands[2]);
8280 HOST_WIDE_INT pos = INTVAL (operands[3]);
8282 /* PA extraction insns don't support zero length bitfields or fields
8283 extending beyond the left or right-most bits. Also, we reject lengths
8284 equal to a word as they are better handled by the move patterns. */
8285 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8288 /* From mips.md: extract_bit_field doesn't verify that our source
8289 matches the predicate, so check it again here. */
8290 if (!register_operand (operands[1], VOIDmode))
8294 emit_insn (gen_extv_64 (operands[0], operands[1],
8295 operands[2], operands[3]));
8297 emit_insn (gen_extv_32 (operands[0], operands[1],
8298 operands[2], operands[3]));
8302 (define_insn "extv_32"
8303 [(set (match_operand:SI 0 "register_operand" "=r")
8304 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8305 (match_operand:SI 2 "uint5_operand" "")
8306 (match_operand:SI 3 "uint5_operand" "")))]
8308 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8309 [(set_attr "type" "shift")
8310 (set_attr "length" "4")])
8313 [(set (match_operand:SI 0 "register_operand" "=r")
8314 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8316 (match_operand:SI 2 "register_operand" "q")))]
8318 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8319 [(set_attr "type" "shift")
8320 (set_attr "length" "4")])
8322 (define_insn "extv_64"
8323 [(set (match_operand:DI 0 "register_operand" "=r")
8324 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8325 (match_operand:DI 2 "uint32_operand" "")
8326 (match_operand:DI 3 "uint32_operand" "")))]
8328 "extrd,s %1,%3+%2-1,%2,%0"
8329 [(set_attr "type" "shift")
8330 (set_attr "length" "4")])
8333 [(set (match_operand:DI 0 "register_operand" "=r")
8334 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8336 (match_operand:DI 2 "register_operand" "q")))]
8338 "extrd,s %1,%%sar,1,%0"
8339 [(set_attr "type" "shift")
8340 (set_attr "length" "4")])
8342 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8343 (define_expand "insv"
8344 [(set (zero_extract (match_operand 0 "register_operand" "")
8345 (match_operand 1 "uint32_operand" "")
8346 (match_operand 2 "uint32_operand" ""))
8347 (match_operand 3 "arith5_operand" ""))]
8351 HOST_WIDE_INT len = INTVAL (operands[1]);
8352 HOST_WIDE_INT pos = INTVAL (operands[2]);
8354 /* PA insertion insns don't support zero length bitfields or fields
8355 extending beyond the left or right-most bits. Also, we reject lengths
8356 equal to a word as they are better handled by the move patterns. */
8357 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8360 /* From mips.md: insert_bit_field doesn't verify that our destination
8361 matches the predicate, so check it again here. */
8362 if (!register_operand (operands[0], VOIDmode))
8366 emit_insn (gen_insv_64 (operands[0], operands[1],
8367 operands[2], operands[3]));
8369 emit_insn (gen_insv_32 (operands[0], operands[1],
8370 operands[2], operands[3]));
8374 (define_insn "insv_32"
8375 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8376 (match_operand:SI 1 "uint5_operand" "")
8377 (match_operand:SI 2 "uint5_operand" ""))
8378 (match_operand:SI 3 "arith5_operand" "r,L"))]
8381 {dep|depw} %3,%2+%1-1,%1,%0
8382 {depi|depwi} %3,%2+%1-1,%1,%0"
8383 [(set_attr "type" "shift,shift")
8384 (set_attr "length" "4,4")])
8386 ;; Optimize insertion of const_int values of type 1...1xxxx.
8388 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8389 (match_operand:SI 1 "uint5_operand" "")
8390 (match_operand:SI 2 "uint5_operand" ""))
8391 (match_operand:SI 3 "const_int_operand" ""))]
8392 "(INTVAL (operands[3]) & 0x10) != 0 &&
8393 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8396 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8397 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8399 [(set_attr "type" "shift")
8400 (set_attr "length" "4")])
8402 (define_insn "insv_64"
8403 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8404 (match_operand:DI 1 "uint32_operand" "")
8405 (match_operand:DI 2 "uint32_operand" ""))
8406 (match_operand:DI 3 "arith32_operand" "r,L"))]
8409 depd %3,%2+%1-1,%1,%0
8410 depdi %3,%2+%1-1,%1,%0"
8411 [(set_attr "type" "shift,shift")
8412 (set_attr "length" "4,4")])
8414 ;; Optimize insertion of const_int values of type 1...1xxxx.
8416 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8417 (match_operand:DI 1 "uint32_operand" "")
8418 (match_operand:DI 2 "uint32_operand" ""))
8419 (match_operand:DI 3 "const_int_operand" ""))]
8420 "(INTVAL (operands[3]) & 0x10) != 0
8422 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8425 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8426 return \"depdi %3,%2+%1-1,%1,%0\";
8428 [(set_attr "type" "shift")
8429 (set_attr "length" "4")])
8432 [(set (match_operand:DI 0 "register_operand" "=r")
8433 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8436 "depd,z %1,31,32,%0"
8437 [(set_attr "type" "shift")
8438 (set_attr "length" "4")])
8440 ;; This insn is used for some loop tests, typically loops reversed when
8441 ;; strength reduction is used. It is actually created when the instruction
8442 ;; combination phase combines the special loop test. Since this insn
8443 ;; is both a jump insn and has an output, it must deal with its own
8444 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8445 ;; to not choose the register alternatives in the event a reload is needed.
8446 (define_insn "decrement_and_branch_until_zero"
8449 (match_operator 2 "comparison_operator"
8451 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8452 (match_operand:SI 1 "int5_operand" "L,L,L"))
8454 (label_ref (match_operand 3 "" ""))
8457 (plus:SI (match_dup 0) (match_dup 1)))
8458 (clobber (match_scratch:SI 4 "=X,r,r"))]
8460 "* return output_dbra (operands, insn, which_alternative); "
8461 ;; Do not expect to understand this the first time through.
8462 [(set_attr "type" "cbranch,multi,multi")
8463 (set (attr "length")
8464 (if_then_else (eq_attr "alternative" "0")
8465 ;; Loop counter in register case
8466 ;; Short branch has length of 4
8467 ;; Long branch has length of 8
8468 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8473 ;; Loop counter in FP reg case.
8474 ;; Extra goo to deal with additional reload insns.
8475 (if_then_else (eq_attr "alternative" "1")
8476 (if_then_else (lt (match_dup 3) (pc))
8478 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8483 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8487 ;; Loop counter in memory case.
8488 ;; Extra goo to deal with additional reload insns.
8489 (if_then_else (lt (match_dup 3) (pc))
8491 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8496 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8499 (const_int 16))))))])
8504 (match_operator 2 "movb_comparison_operator"
8505 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8506 (label_ref (match_operand 3 "" ""))
8508 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8511 "* return output_movb (operands, insn, which_alternative, 0); "
8512 ;; Do not expect to understand this the first time through.
8513 [(set_attr "type" "cbranch,multi,multi,multi")
8514 (set (attr "length")
8515 (if_then_else (eq_attr "alternative" "0")
8516 ;; Loop counter in register case
8517 ;; Short branch has length of 4
8518 ;; Long branch has length of 8
8519 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8524 ;; Loop counter in FP reg case.
8525 ;; Extra goo to deal with additional reload insns.
8526 (if_then_else (eq_attr "alternative" "1")
8527 (if_then_else (lt (match_dup 3) (pc))
8529 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8534 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8538 ;; Loop counter in memory or sar case.
8539 ;; Extra goo to deal with additional reload insns.
8541 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8544 (const_int 12)))))])
8546 ;; Handle negated branch.
8550 (match_operator 2 "movb_comparison_operator"
8551 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8553 (label_ref (match_operand 3 "" ""))))
8554 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8557 "* return output_movb (operands, insn, which_alternative, 1); "
8558 ;; Do not expect to understand this the first time through.
8559 [(set_attr "type" "cbranch,multi,multi,multi")
8560 (set (attr "length")
8561 (if_then_else (eq_attr "alternative" "0")
8562 ;; Loop counter in register case
8563 ;; Short branch has length of 4
8564 ;; Long branch has length of 8
8565 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8570 ;; Loop counter in FP reg case.
8571 ;; Extra goo to deal with additional reload insns.
8572 (if_then_else (eq_attr "alternative" "1")
8573 (if_then_else (lt (match_dup 3) (pc))
8575 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8580 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8584 ;; Loop counter in memory or SAR case.
8585 ;; Extra goo to deal with additional reload insns.
8587 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8590 (const_int 12)))))])
8593 [(set (pc) (label_ref (match_operand 3 "" "" )))
8594 (set (match_operand:SI 0 "ireg_operand" "=r")
8595 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8596 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8597 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8600 return output_parallel_addb (operands, get_attr_length (insn));
8602 [(set_attr "type" "parallel_branch")
8603 (set (attr "length")
8604 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8610 [(set (pc) (label_ref (match_operand 2 "" "" )))
8611 (set (match_operand:SF 0 "ireg_operand" "=r")
8612 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8616 return output_parallel_movb (operands, get_attr_length (insn));
8618 [(set_attr "type" "parallel_branch")
8619 (set (attr "length")
8620 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8626 [(set (pc) (label_ref (match_operand 2 "" "" )))
8627 (set (match_operand:SI 0 "ireg_operand" "=r")
8628 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8632 return output_parallel_movb (operands, get_attr_length (insn));
8634 [(set_attr "type" "parallel_branch")
8635 (set (attr "length")
8636 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8642 [(set (pc) (label_ref (match_operand 2 "" "" )))
8643 (set (match_operand:HI 0 "ireg_operand" "=r")
8644 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8648 return output_parallel_movb (operands, get_attr_length (insn));
8650 [(set_attr "type" "parallel_branch")
8651 (set (attr "length")
8652 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8658 [(set (pc) (label_ref (match_operand 2 "" "" )))
8659 (set (match_operand:QI 0 "ireg_operand" "=r")
8660 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8664 return output_parallel_movb (operands, get_attr_length (insn));
8666 [(set_attr "type" "parallel_branch")
8667 (set (attr "length")
8668 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8674 [(set (match_operand 0 "register_operand" "=f")
8675 (mult (match_operand 1 "register_operand" "f")
8676 (match_operand 2 "register_operand" "f")))
8677 (set (match_operand 3 "register_operand" "+f")
8678 (plus (match_operand 4 "register_operand" "f")
8679 (match_operand 5 "register_operand" "f")))]
8680 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8681 && reload_completed && fmpyaddoperands (operands)"
8684 if (GET_MODE (operands[0]) == DFmode)
8686 if (rtx_equal_p (operands[3], operands[5]))
8687 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8689 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8693 if (rtx_equal_p (operands[3], operands[5]))
8694 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8696 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8699 [(set_attr "type" "fpalu")
8700 (set_attr "length" "4")])
8703 [(set (match_operand 3 "register_operand" "+f")
8704 (plus (match_operand 4 "register_operand" "f")
8705 (match_operand 5 "register_operand" "f")))
8706 (set (match_operand 0 "register_operand" "=f")
8707 (mult (match_operand 1 "register_operand" "f")
8708 (match_operand 2 "register_operand" "f")))]
8709 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8710 && reload_completed && fmpyaddoperands (operands)"
8713 if (GET_MODE (operands[0]) == DFmode)
8715 if (rtx_equal_p (operands[3], operands[5]))
8716 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8718 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8722 if (rtx_equal_p (operands[3], operands[5]))
8723 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8725 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8728 [(set_attr "type" "fpalu")
8729 (set_attr "length" "4")])
8732 [(set (match_operand 0 "register_operand" "=f")
8733 (mult (match_operand 1 "register_operand" "f")
8734 (match_operand 2 "register_operand" "f")))
8735 (set (match_operand 3 "register_operand" "+f")
8736 (minus (match_operand 4 "register_operand" "f")
8737 (match_operand 5 "register_operand" "f")))]
8738 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8739 && reload_completed && fmpysuboperands (operands)"
8742 if (GET_MODE (operands[0]) == DFmode)
8743 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8745 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8747 [(set_attr "type" "fpalu")
8748 (set_attr "length" "4")])
8751 [(set (match_operand 3 "register_operand" "+f")
8752 (minus (match_operand 4 "register_operand" "f")
8753 (match_operand 5 "register_operand" "f")))
8754 (set (match_operand 0 "register_operand" "=f")
8755 (mult (match_operand 1 "register_operand" "f")
8756 (match_operand 2 "register_operand" "f")))]
8757 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8758 && reload_completed && fmpysuboperands (operands)"
8761 if (GET_MODE (operands[0]) == DFmode)
8762 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8764 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8766 [(set_attr "type" "fpalu")
8767 (set_attr "length" "4")])
8769 ;; Clean up turds left by reload.
8771 [(set (match_operand 0 "move_dest_operand" "")
8772 (match_operand 1 "register_operand" "fr"))
8773 (set (match_operand 2 "register_operand" "fr")
8776 && GET_CODE (operands[0]) == MEM
8777 && ! MEM_VOLATILE_P (operands[0])
8778 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8779 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8780 && GET_MODE (operands[0]) == DFmode
8781 && GET_CODE (operands[1]) == REG
8782 && GET_CODE (operands[2]) == REG
8783 && ! side_effects_p (XEXP (operands[0], 0))
8784 && REGNO_REG_CLASS (REGNO (operands[1]))
8785 == REGNO_REG_CLASS (REGNO (operands[2]))"
8790 if (FP_REG_P (operands[1]))
8791 output_asm_insn (output_fp_move_double (operands), operands);
8793 output_asm_insn (output_move_double (operands), operands);
8795 if (rtx_equal_p (operands[1], operands[2]))
8798 xoperands[0] = operands[2];
8799 xoperands[1] = operands[1];
8801 if (FP_REG_P (xoperands[1]))
8802 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8804 output_asm_insn (output_move_double (xoperands), xoperands);
8810 [(set (match_operand 0 "register_operand" "fr")
8811 (match_operand 1 "move_src_operand" ""))
8812 (set (match_operand 2 "register_operand" "fr")
8815 && GET_CODE (operands[1]) == MEM
8816 && ! MEM_VOLATILE_P (operands[1])
8817 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8818 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8819 && GET_MODE (operands[0]) == DFmode
8820 && GET_CODE (operands[0]) == REG
8821 && GET_CODE (operands[2]) == REG
8822 && ! side_effects_p (XEXP (operands[1], 0))
8823 && REGNO_REG_CLASS (REGNO (operands[0]))
8824 == REGNO_REG_CLASS (REGNO (operands[2]))"
8829 if (FP_REG_P (operands[0]))
8830 output_asm_insn (output_fp_move_double (operands), operands);
8832 output_asm_insn (output_move_double (operands), operands);
8834 xoperands[0] = operands[2];
8835 xoperands[1] = operands[0];
8837 if (FP_REG_P (xoperands[1]))
8838 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8840 output_asm_insn (output_move_double (xoperands), xoperands);
8845 ;; Flush the I and D cache lines from the start address (operand0)
8846 ;; to the end address (operand1). No lines are flushed if the end
8847 ;; address is less than the start address (unsigned).
8849 ;; Because the range of memory flushed is variable and the size of
8850 ;; a MEM can only be a CONST_INT, the patterns specify that they
8851 ;; perform an unspecified volatile operation on all memory.
8853 ;; The address range for an icache flush must lie within a single
8854 ;; space on targets with non-equivalent space registers.
8856 ;; This is used by the trampoline code for nested functions.
8858 ;; Operand 0 contains the start address.
8859 ;; Operand 1 contains the end address.
8860 ;; Operand 2 contains the line length to use.
8861 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
8862 (define_insn "dcacheflush"
8864 (unspec_volatile [(mem:BLK (scratch))] 0)
8865 (use (match_operand 0 "pmode_register_operand" "r"))
8866 (use (match_operand 1 "pmode_register_operand" "r"))
8867 (use (match_operand 2 "pmode_register_operand" "r"))
8868 (clobber (match_scratch 3 "=&0"))]
8873 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8875 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8877 [(set_attr "type" "multi")
8878 (set_attr "length" "12")])
8880 (define_insn "icacheflush"
8882 (unspec_volatile [(mem:BLK (scratch))] 0)
8883 (use (match_operand 0 "pmode_register_operand" "r"))
8884 (use (match_operand 1 "pmode_register_operand" "r"))
8885 (use (match_operand 2 "pmode_register_operand" "r"))
8886 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8887 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
8888 (clobber (match_scratch 5 "=&0"))]
8893 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8895 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8897 [(set_attr "type" "multi")
8898 (set_attr "length" "52")])
8900 ;; An out-of-line prologue.
8901 (define_insn "outline_prologue_call"
8902 [(unspec_volatile [(const_int 0)] 0)
8903 (clobber (reg:SI 31))
8904 (clobber (reg:SI 22))
8905 (clobber (reg:SI 21))
8906 (clobber (reg:SI 20))
8907 (clobber (reg:SI 19))
8908 (clobber (reg:SI 1))]
8912 extern int frame_pointer_needed;
8914 /* We need two different versions depending on whether or not we
8915 need a frame pointer. Also note that we return to the instruction
8916 immediately after the branch rather than two instructions after the
8917 break as normally is the case. */
8918 if (frame_pointer_needed)
8920 /* Must import the magic millicode routine(s). */
8921 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
8923 if (TARGET_PORTABLE_RUNTIME)
8925 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
8926 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
8930 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
8934 /* Must import the magic millicode routine(s). */
8935 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
8937 if (TARGET_PORTABLE_RUNTIME)
8939 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
8940 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
8943 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
8947 [(set_attr "type" "multi")
8948 (set_attr "length" "8")])
8950 ;; An out-of-line epilogue.
8951 (define_insn "outline_epilogue_call"
8952 [(unspec_volatile [(const_int 1)] 0)
8955 (clobber (reg:SI 31))
8956 (clobber (reg:SI 22))
8957 (clobber (reg:SI 21))
8958 (clobber (reg:SI 20))
8959 (clobber (reg:SI 19))
8960 (clobber (reg:SI 2))
8961 (clobber (reg:SI 1))]
8965 extern int frame_pointer_needed;
8967 /* We need two different versions depending on whether or not we
8968 need a frame pointer. Also note that we return to the instruction
8969 immediately after the branch rather than two instructions after the
8970 break as normally is the case. */
8971 if (frame_pointer_needed)
8973 /* Must import the magic millicode routine. */
8974 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
8976 /* The out-of-line prologue will make sure we return to the right
8978 if (TARGET_PORTABLE_RUNTIME)
8980 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
8981 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
8985 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
8989 /* Must import the magic millicode routine. */
8990 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
8992 /* The out-of-line prologue will make sure we return to the right
8994 if (TARGET_PORTABLE_RUNTIME)
8996 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
8997 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9000 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9004 [(set_attr "type" "multi")
9005 (set_attr "length" "8")])
9007 ;; Given a function pointer, canonicalize it so it can be
9008 ;; reliably compared to another function pointer. */
9009 (define_expand "canonicalize_funcptr_for_compare"
9010 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9011 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9012 (clobber (match_dup 2))
9013 (clobber (reg:SI 26))
9014 (clobber (reg:SI 22))
9015 (clobber (reg:SI 31))])
9016 (set (match_operand:SI 0 "register_operand" "")
9018 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9023 rtx canonicalize_funcptr_for_compare_libfunc
9024 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9026 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9027 operands[0], LCT_NORMAL, Pmode,
9028 1, operands[1], Pmode);
9032 operands[2] = gen_reg_rtx (SImode);
9033 if (GET_CODE (operands[1]) != REG)
9035 rtx tmp = gen_reg_rtx (Pmode);
9036 emit_move_insn (tmp, operands[1]);
9042 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9043 (clobber (match_operand:SI 0 "register_operand" "=a"))
9044 (clobber (reg:SI 26))
9045 (clobber (reg:SI 22))
9046 (clobber (reg:SI 31))]
9050 int length = get_attr_length (insn);
9053 xoperands[0] = GEN_INT (length - 8);
9054 xoperands[1] = GEN_INT (length - 16);
9056 /* Must import the magic millicode routine. */
9057 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9059 /* This is absolutely amazing.
9061 First, copy our input parameter into %r29 just in case we don't
9062 need to call $$sh_func_adrs. */
9063 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9064 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9066 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9067 we use %r26 unchanged. */
9068 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9069 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9071 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9072 4096, then again we use %r26 unchanged. */
9073 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9075 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9076 return output_millicode_call (insn,
9077 gen_rtx_SYMBOL_REF (SImode,
9078 \"$$sh_func_adrs\"));
9080 [(set_attr "type" "multi")
9081 (set (attr "length")
9082 (plus (symbol_ref "attr_length_millicode_call (insn)")
9085 ;; On the PA, the PIC register is call clobbered, so it must
9086 ;; be saved & restored around calls by the caller. If the call
9087 ;; doesn't return normally (nonlocal goto, or an exception is
9088 ;; thrown), then the code at the exception handler label must
9089 ;; restore the PIC register.
9090 (define_expand "exception_receiver"
9095 /* On the 64-bit port, we need a blockage because there is
9096 confusion regarding the dependence of the restore on the
9097 frame pointer. As a result, the frame pointer and pic
9098 register restores sometimes are interchanged erroneously. */
9100 emit_insn (gen_blockage ());
9101 /* Restore the PIC register using hppa_pic_save_rtx (). The
9102 PIC register is not saved in the frame in 64-bit ABI. */
9103 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9104 emit_insn (gen_blockage ());
9108 (define_expand "builtin_setjmp_receiver"
9109 [(label_ref (match_operand 0 "" ""))]
9114 emit_insn (gen_blockage ());
9115 /* Restore the PIC register. Hopefully, this will always be from
9116 a stack slot. The only registers that are valid after a
9117 builtin_longjmp are the stack and frame pointers. */
9118 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9119 emit_insn (gen_blockage ());
9123 ;; Allocate new stack space and update the saved stack pointer in the
9124 ;; frame marker. The HP C compilers also copy additional words in the
9125 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9126 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9127 ;; currently don't copy these values.
9129 ;; Since the copy of the frame marker can't be done atomically, I
9130 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9131 ;; The HP compilers appear to raise the stack and copy the frame
9132 ;; marker in a strict instruction sequence. This suggests that the
9133 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9134 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9135 ;; as GAS doesn't support it, or try to keep the instructions emitted
9136 ;; here in strict sequence.
9137 (define_expand "allocate_stack"
9138 [(match_operand 0 "" "")
9139 (match_operand 1 "" "")]
9145 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9146 in operand 0 before adjusting the stack. */
9147 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9148 anti_adjust_stack (operands[1]);
9149 if (TARGET_HPUX_UNWIND_LIBRARY)
9151 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9152 GEN_INT (TARGET_64BIT ? -8 : -4));
9153 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9155 if (!TARGET_64BIT && flag_pic)
9157 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9158 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);