1 ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; The following two patterns are optimization placeholders. In almost
629 ;; all cases, the user of the condition code will be simplified and the
630 ;; original condition code setting insn should be eliminated.
632 (define_insn "*setccfp0"
635 "! TARGET_SOFT_FLOAT"
636 "fcmp,dbl,!= %%fr0,%%fr0"
637 [(set_attr "length" "4")
638 (set_attr "type" "fpcc")])
640 (define_insn "*setccfp1"
643 "! TARGET_SOFT_FLOAT"
644 "fcmp,dbl,= %%fr0,%%fr0"
645 [(set_attr "length" "4")
646 (set_attr "type" "fpcc")])
651 [(set (match_operand:SI 0 "register_operand" "")
657 /* fp scc patterns rarely match, and are not a win on the PA. */
658 if (hppa_branch_type != CMP_SI)
660 /* set up operands from compare. */
661 operands[1] = hppa_compare_op0;
662 operands[2] = hppa_compare_op1;
663 /* fall through and generate default code */
667 [(set (match_operand:SI 0 "register_operand" "")
673 /* fp scc patterns rarely match, and are not a win on the PA. */
674 if (hppa_branch_type != CMP_SI)
676 operands[1] = hppa_compare_op0;
677 operands[2] = hppa_compare_op1;
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
736 (define_expand "sltu"
737 [(set (match_operand:SI 0 "register_operand" "")
738 (ltu:SI (match_dup 1)
743 if (hppa_branch_type != CMP_SI)
745 operands[1] = hppa_compare_op0;
746 operands[2] = hppa_compare_op1;
749 (define_expand "sgtu"
750 [(set (match_operand:SI 0 "register_operand" "")
751 (gtu:SI (match_dup 1)
756 if (hppa_branch_type != CMP_SI)
758 operands[1] = hppa_compare_op0;
759 operands[2] = hppa_compare_op1;
762 (define_expand "sleu"
763 [(set (match_operand:SI 0 "register_operand" "")
764 (leu:SI (match_dup 1)
769 if (hppa_branch_type != CMP_SI)
771 operands[1] = hppa_compare_op0;
772 operands[2] = hppa_compare_op1;
775 (define_expand "sgeu"
776 [(set (match_operand:SI 0 "register_operand" "")
777 (geu:SI (match_dup 1)
782 if (hppa_branch_type != CMP_SI)
784 operands[1] = hppa_compare_op0;
785 operands[2] = hppa_compare_op1;
788 ;; Instruction canonicalization puts immediate operands second, which
789 ;; is the reverse of what we want.
792 [(set (match_operand:SI 0 "register_operand" "=r")
793 (match_operator:SI 3 "comparison_operator"
794 [(match_operand:SI 1 "register_operand" "r")
795 (match_operand:SI 2 "arith11_operand" "rI")]))]
797 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
798 [(set_attr "type" "binary")
799 (set_attr "length" "8")])
802 [(set (match_operand:DI 0 "register_operand" "=r")
803 (match_operator:DI 3 "comparison_operator"
804 [(match_operand:DI 1 "register_operand" "r")
805 (match_operand:DI 2 "arith11_operand" "rI")]))]
807 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
808 [(set_attr "type" "binary")
809 (set_attr "length" "8")])
811 (define_insn "iorscc"
812 [(set (match_operand:SI 0 "register_operand" "=r")
813 (ior:SI (match_operator:SI 3 "comparison_operator"
814 [(match_operand:SI 1 "register_operand" "r")
815 (match_operand:SI 2 "arith11_operand" "rI")])
816 (match_operator:SI 6 "comparison_operator"
817 [(match_operand:SI 4 "register_operand" "r")
818 (match_operand:SI 5 "arith11_operand" "rI")])))]
820 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
821 [(set_attr "type" "binary")
822 (set_attr "length" "12")])
825 [(set (match_operand:DI 0 "register_operand" "=r")
826 (ior:DI (match_operator:DI 3 "comparison_operator"
827 [(match_operand:DI 1 "register_operand" "r")
828 (match_operand:DI 2 "arith11_operand" "rI")])
829 (match_operator:DI 6 "comparison_operator"
830 [(match_operand:DI 4 "register_operand" "r")
831 (match_operand:DI 5 "arith11_operand" "rI")])))]
833 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
834 [(set_attr "type" "binary")
835 (set_attr "length" "12")])
837 ;; Combiner patterns for common operations performed with the output
838 ;; from an scc insn (negscc and incscc).
839 (define_insn "negscc"
840 [(set (match_operand:SI 0 "register_operand" "=r")
841 (neg:SI (match_operator:SI 3 "comparison_operator"
842 [(match_operand:SI 1 "register_operand" "r")
843 (match_operand:SI 2 "arith11_operand" "rI")])))]
845 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
846 [(set_attr "type" "binary")
847 (set_attr "length" "8")])
850 [(set (match_operand:DI 0 "register_operand" "=r")
851 (neg:DI (match_operator:DI 3 "comparison_operator"
852 [(match_operand:DI 1 "register_operand" "r")
853 (match_operand:DI 2 "arith11_operand" "rI")])))]
855 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
856 [(set_attr "type" "binary")
857 (set_attr "length" "8")])
859 ;; Patterns for adding/subtracting the result of a boolean expression from
860 ;; a register. First we have special patterns that make use of the carry
861 ;; bit, and output only two instructions. For the cases we can't in
862 ;; general do in two instructions, the incscc pattern at the end outputs
863 ;; two or three instructions.
866 [(set (match_operand:SI 0 "register_operand" "=r")
867 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
868 (match_operand:SI 3 "arith11_operand" "rI"))
869 (match_operand:SI 1 "register_operand" "r")))]
871 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
872 [(set_attr "type" "binary")
873 (set_attr "length" "8")])
876 [(set (match_operand:DI 0 "register_operand" "=r")
877 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
878 (match_operand:DI 3 "arith11_operand" "rI"))
879 (match_operand:DI 1 "register_operand" "r")))]
881 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
882 [(set_attr "type" "binary")
883 (set_attr "length" "8")])
885 ; This need only accept registers for op3, since canonicalization
886 ; replaces geu with gtu when op3 is an integer.
888 [(set (match_operand:SI 0 "register_operand" "=r")
889 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
890 (match_operand:SI 3 "register_operand" "r"))
891 (match_operand:SI 1 "register_operand" "r")))]
893 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
894 [(set_attr "type" "binary")
895 (set_attr "length" "8")])
898 [(set (match_operand:DI 0 "register_operand" "=r")
899 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
900 (match_operand:DI 3 "register_operand" "r"))
901 (match_operand:DI 1 "register_operand" "r")))]
903 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
904 [(set_attr "type" "binary")
905 (set_attr "length" "8")])
907 ; Match only integers for op3 here. This is used as canonical form of the
908 ; geu pattern when op3 is an integer. Don't match registers since we can't
909 ; make better code than the general incscc pattern.
911 [(set (match_operand:SI 0 "register_operand" "=r")
912 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
913 (match_operand:SI 3 "int11_operand" "I"))
914 (match_operand:SI 1 "register_operand" "r")))]
916 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
917 [(set_attr "type" "binary")
918 (set_attr "length" "8")])
921 [(set (match_operand:DI 0 "register_operand" "=r")
922 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
923 (match_operand:DI 3 "int11_operand" "I"))
924 (match_operand:DI 1 "register_operand" "r")))]
926 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
927 [(set_attr "type" "binary")
928 (set_attr "length" "8")])
930 (define_insn "incscc"
931 [(set (match_operand:SI 0 "register_operand" "=r,r")
932 (plus:SI (match_operator:SI 4 "comparison_operator"
933 [(match_operand:SI 2 "register_operand" "r,r")
934 (match_operand:SI 3 "arith11_operand" "rI,rI")])
935 (match_operand:SI 1 "register_operand" "0,?r")))]
938 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
939 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
940 [(set_attr "type" "binary,binary")
941 (set_attr "length" "8,12")])
944 [(set (match_operand:DI 0 "register_operand" "=r,r")
945 (plus:DI (match_operator:DI 4 "comparison_operator"
946 [(match_operand:DI 2 "register_operand" "r,r")
947 (match_operand:DI 3 "arith11_operand" "rI,rI")])
948 (match_operand:DI 1 "register_operand" "0,?r")))]
951 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
952 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
953 [(set_attr "type" "binary,binary")
954 (set_attr "length" "8,12")])
957 [(set (match_operand:SI 0 "register_operand" "=r")
958 (minus:SI (match_operand:SI 1 "register_operand" "r")
959 (gtu:SI (match_operand:SI 2 "register_operand" "r")
960 (match_operand:SI 3 "arith11_operand" "rI"))))]
962 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
963 [(set_attr "type" "binary")
964 (set_attr "length" "8")])
967 [(set (match_operand:DI 0 "register_operand" "=r")
968 (minus:DI (match_operand:DI 1 "register_operand" "r")
969 (gtu:DI (match_operand:DI 2 "register_operand" "r")
970 (match_operand:DI 3 "arith11_operand" "rI"))))]
972 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
973 [(set_attr "type" "binary")
974 (set_attr "length" "8")])
977 [(set (match_operand:SI 0 "register_operand" "=r")
978 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
979 (gtu:SI (match_operand:SI 2 "register_operand" "r")
980 (match_operand:SI 3 "arith11_operand" "rI")))
981 (match_operand:SI 4 "register_operand" "r")))]
983 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
984 [(set_attr "type" "binary")
985 (set_attr "length" "8")])
988 [(set (match_operand:DI 0 "register_operand" "=r")
989 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
990 (gtu:DI (match_operand:DI 2 "register_operand" "r")
991 (match_operand:DI 3 "arith11_operand" "rI")))
992 (match_operand:DI 4 "register_operand" "r")))]
994 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
995 [(set_attr "type" "binary")
996 (set_attr "length" "8")])
998 ; This need only accept registers for op3, since canonicalization
999 ; replaces ltu with leu when op3 is an integer.
1001 [(set (match_operand:SI 0 "register_operand" "=r")
1002 (minus:SI (match_operand:SI 1 "register_operand" "r")
1003 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1004 (match_operand:SI 3 "register_operand" "r"))))]
1006 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1007 [(set_attr "type" "binary")
1008 (set_attr "length" "8")])
1011 [(set (match_operand:DI 0 "register_operand" "=r")
1012 (minus:DI (match_operand:DI 1 "register_operand" "r")
1013 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1014 (match_operand:DI 3 "register_operand" "r"))))]
1016 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1017 [(set_attr "type" "binary")
1018 (set_attr "length" "8")])
1021 [(set (match_operand:SI 0 "register_operand" "=r")
1022 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1023 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1024 (match_operand:SI 3 "register_operand" "r")))
1025 (match_operand:SI 4 "register_operand" "r")))]
1027 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1028 [(set_attr "type" "binary")
1029 (set_attr "length" "8")])
1032 [(set (match_operand:DI 0 "register_operand" "=r")
1033 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1034 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1035 (match_operand:DI 3 "register_operand" "r")))
1036 (match_operand:DI 4 "register_operand" "r")))]
1038 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1039 [(set_attr "type" "binary")
1040 (set_attr "length" "8")])
1042 ; Match only integers for op3 here. This is used as canonical form of the
1043 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1044 ; make better code than the general incscc pattern.
1046 [(set (match_operand:SI 0 "register_operand" "=r")
1047 (minus:SI (match_operand:SI 1 "register_operand" "r")
1048 (leu:SI (match_operand:SI 2 "register_operand" "r")
1049 (match_operand:SI 3 "int11_operand" "I"))))]
1051 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1052 [(set_attr "type" "binary")
1053 (set_attr "length" "8")])
1056 [(set (match_operand:DI 0 "register_operand" "=r")
1057 (minus:DI (match_operand:DI 1 "register_operand" "r")
1058 (leu:DI (match_operand:DI 2 "register_operand" "r")
1059 (match_operand:DI 3 "int11_operand" "I"))))]
1061 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1062 [(set_attr "type" "binary")
1063 (set_attr "length" "8")])
1066 [(set (match_operand:SI 0 "register_operand" "=r")
1067 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1068 (leu:SI (match_operand:SI 2 "register_operand" "r")
1069 (match_operand:SI 3 "int11_operand" "I")))
1070 (match_operand:SI 4 "register_operand" "r")))]
1072 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1073 [(set_attr "type" "binary")
1074 (set_attr "length" "8")])
1077 [(set (match_operand:DI 0 "register_operand" "=r")
1078 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1079 (leu:DI (match_operand:DI 2 "register_operand" "r")
1080 (match_operand:DI 3 "int11_operand" "I")))
1081 (match_operand:DI 4 "register_operand" "r")))]
1083 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1084 [(set_attr "type" "binary")
1085 (set_attr "length" "8")])
1087 (define_insn "decscc"
1088 [(set (match_operand:SI 0 "register_operand" "=r,r")
1089 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1090 (match_operator:SI 4 "comparison_operator"
1091 [(match_operand:SI 2 "register_operand" "r,r")
1092 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1095 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1096 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1097 [(set_attr "type" "binary,binary")
1098 (set_attr "length" "8,12")])
1101 [(set (match_operand:DI 0 "register_operand" "=r,r")
1102 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1103 (match_operator:DI 4 "comparison_operator"
1104 [(match_operand:DI 2 "register_operand" "r,r")
1105 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1108 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1109 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1110 [(set_attr "type" "binary,binary")
1111 (set_attr "length" "8,12")])
1113 ; Patterns for max and min. (There is no need for an earlyclobber in the
1114 ; last alternative since the middle alternative will match if op0 == op1.)
1116 (define_insn "sminsi3"
1117 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1118 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1119 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1122 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1123 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1124 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1125 [(set_attr "type" "multi,multi,multi")
1126 (set_attr "length" "8,8,8")])
1128 (define_insn "smindi3"
1129 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1130 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1131 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1134 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1135 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1136 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1137 [(set_attr "type" "multi,multi,multi")
1138 (set_attr "length" "8,8,8")])
1140 (define_insn "uminsi3"
1141 [(set (match_operand:SI 0 "register_operand" "=r,r")
1142 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1143 (match_operand:SI 2 "arith11_operand" "r,I")))]
1146 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1147 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1148 [(set_attr "type" "multi,multi")
1149 (set_attr "length" "8,8")])
1151 (define_insn "umindi3"
1152 [(set (match_operand:DI 0 "register_operand" "=r,r")
1153 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1154 (match_operand:DI 2 "arith11_operand" "r,I")))]
1157 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1158 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1159 [(set_attr "type" "multi,multi")
1160 (set_attr "length" "8,8")])
1162 (define_insn "smaxsi3"
1163 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1164 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1165 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1168 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1169 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1170 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1171 [(set_attr "type" "multi,multi,multi")
1172 (set_attr "length" "8,8,8")])
1174 (define_insn "smaxdi3"
1175 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1176 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1177 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1180 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1181 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1182 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1183 [(set_attr "type" "multi,multi,multi")
1184 (set_attr "length" "8,8,8")])
1186 (define_insn "umaxsi3"
1187 [(set (match_operand:SI 0 "register_operand" "=r,r")
1188 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1189 (match_operand:SI 2 "arith11_operand" "r,I")))]
1192 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1193 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1194 [(set_attr "type" "multi,multi")
1195 (set_attr "length" "8,8")])
1197 (define_insn "umaxdi3"
1198 [(set (match_operand:DI 0 "register_operand" "=r,r")
1199 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1200 (match_operand:DI 2 "arith11_operand" "r,I")))]
1203 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1204 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1205 [(set_attr "type" "multi,multi")
1206 (set_attr "length" "8,8")])
1208 (define_insn "abssi2"
1209 [(set (match_operand:SI 0 "register_operand" "=r")
1210 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1212 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1213 [(set_attr "type" "multi")
1214 (set_attr "length" "8")])
1216 (define_insn "absdi2"
1217 [(set (match_operand:DI 0 "register_operand" "=r")
1218 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1220 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1221 [(set_attr "type" "multi")
1222 (set_attr "length" "8")])
1224 ;;; Experimental conditional move patterns
1226 (define_expand "movsicc"
1227 [(set (match_operand:SI 0 "register_operand" "")
1229 (match_operator 1 "comparison_operator"
1232 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1233 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1237 enum rtx_code code = GET_CODE (operands[1]);
1239 if (hppa_branch_type != CMP_SI)
1242 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1243 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1246 /* operands[1] is currently the result of compare_from_rtx. We want to
1247 emit a compare of the original operands. */
1248 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1249 operands[4] = hppa_compare_op0;
1250 operands[5] = hppa_compare_op1;
1253 ;; We used to accept any register for op1.
1255 ;; However, it loses sometimes because the compiler will end up using
1256 ;; different registers for op0 and op1 in some critical cases. local-alloc
1257 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1259 ;; If/when global register allocation supports tying we should allow any
1260 ;; register for op1 again.
1262 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1264 (match_operator 2 "comparison_operator"
1265 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1266 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1267 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1271 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1272 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1273 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1274 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1275 [(set_attr "type" "multi,multi,multi,nullshift")
1276 (set_attr "length" "8,8,8,8")])
1279 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1281 (match_operator 5 "comparison_operator"
1282 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1283 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1284 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1285 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1288 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1289 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1290 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1291 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1292 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1293 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1294 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1295 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1296 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1297 (set_attr "length" "8,8,8,8,8,8,8,8")])
1299 (define_expand "movdicc"
1300 [(set (match_operand:DI 0 "register_operand" "")
1302 (match_operator 1 "comparison_operator"
1305 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1306 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1310 enum rtx_code code = GET_CODE (operands[1]);
1312 if (hppa_branch_type != CMP_SI)
1315 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1316 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1319 /* operands[1] is currently the result of compare_from_rtx. We want to
1320 emit a compare of the original operands. */
1321 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1322 operands[4] = hppa_compare_op0;
1323 operands[5] = hppa_compare_op1;
1326 ; We need the first constraint alternative in order to avoid
1327 ; earlyclobbers on all other alternatives.
1329 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1331 (match_operator 2 "comparison_operator"
1332 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1333 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1334 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1338 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1339 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1340 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1341 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1342 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1343 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1344 (set_attr "length" "8,8,8,8,8")])
1347 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1349 (match_operator 5 "comparison_operator"
1350 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1351 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1352 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1353 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1356 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1357 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1358 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1359 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1360 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1361 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1362 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1363 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1364 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1365 (set_attr "length" "8,8,8,8,8,8,8,8")])
1367 ;; Conditional Branches
1369 (define_expand "beq"
1371 (if_then_else (eq (match_dup 1) (match_dup 2))
1372 (label_ref (match_operand 0 "" ""))
1377 if (hppa_branch_type != CMP_SI)
1379 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1380 emit_bcond_fp (NE, operands[0]);
1383 /* set up operands from compare. */
1384 operands[1] = hppa_compare_op0;
1385 operands[2] = hppa_compare_op1;
1386 /* fall through and generate default code */
1389 (define_expand "bne"
1391 (if_then_else (ne (match_dup 1) (match_dup 2))
1392 (label_ref (match_operand 0 "" ""))
1397 if (hppa_branch_type != CMP_SI)
1399 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1400 emit_bcond_fp (NE, operands[0]);
1403 operands[1] = hppa_compare_op0;
1404 operands[2] = hppa_compare_op1;
1407 (define_expand "bgt"
1409 (if_then_else (gt (match_dup 1) (match_dup 2))
1410 (label_ref (match_operand 0 "" ""))
1415 if (hppa_branch_type != CMP_SI)
1417 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1418 emit_bcond_fp (NE, operands[0]);
1421 operands[1] = hppa_compare_op0;
1422 operands[2] = hppa_compare_op1;
1425 (define_expand "blt"
1427 (if_then_else (lt (match_dup 1) (match_dup 2))
1428 (label_ref (match_operand 0 "" ""))
1433 if (hppa_branch_type != CMP_SI)
1435 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1436 emit_bcond_fp (NE, operands[0]);
1439 operands[1] = hppa_compare_op0;
1440 operands[2] = hppa_compare_op1;
1443 (define_expand "bge"
1445 (if_then_else (ge (match_dup 1) (match_dup 2))
1446 (label_ref (match_operand 0 "" ""))
1451 if (hppa_branch_type != CMP_SI)
1453 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1454 emit_bcond_fp (NE, operands[0]);
1457 operands[1] = hppa_compare_op0;
1458 operands[2] = hppa_compare_op1;
1461 (define_expand "ble"
1463 (if_then_else (le (match_dup 1) (match_dup 2))
1464 (label_ref (match_operand 0 "" ""))
1469 if (hppa_branch_type != CMP_SI)
1471 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1472 emit_bcond_fp (NE, operands[0]);
1475 operands[1] = hppa_compare_op0;
1476 operands[2] = hppa_compare_op1;
1479 (define_expand "bgtu"
1481 (if_then_else (gtu (match_dup 1) (match_dup 2))
1482 (label_ref (match_operand 0 "" ""))
1487 if (hppa_branch_type != CMP_SI)
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bltu"
1495 (if_then_else (ltu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bgeu"
1509 (if_then_else (geu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bleu"
1523 (if_then_else (leu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bltgt"
1537 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type == CMP_SI)
1545 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1546 emit_bcond_fp (NE, operands[0]);
1550 (define_expand "bunle"
1552 (if_then_else (unle (match_dup 1) (match_dup 2))
1553 (label_ref (match_operand 0 "" ""))
1558 if (hppa_branch_type == CMP_SI)
1560 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1561 emit_bcond_fp (NE, operands[0]);
1565 (define_expand "bunlt"
1567 (if_then_else (unlt (match_dup 1) (match_dup 2))
1568 (label_ref (match_operand 0 "" ""))
1573 if (hppa_branch_type == CMP_SI)
1575 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1576 emit_bcond_fp (NE, operands[0]);
1580 (define_expand "bunge"
1582 (if_then_else (unge (match_dup 1) (match_dup 2))
1583 (label_ref (match_operand 0 "" ""))
1588 if (hppa_branch_type == CMP_SI)
1590 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1591 emit_bcond_fp (NE, operands[0]);
1595 (define_expand "bungt"
1597 (if_then_else (ungt (match_dup 1) (match_dup 2))
1598 (label_ref (match_operand 0 "" ""))
1603 if (hppa_branch_type == CMP_SI)
1605 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1606 emit_bcond_fp (NE, operands[0]);
1610 (define_expand "buneq"
1612 (if_then_else (uneq (match_dup 1) (match_dup 2))
1613 (label_ref (match_operand 0 "" ""))
1618 if (hppa_branch_type == CMP_SI)
1620 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1621 emit_bcond_fp (NE, operands[0]);
1625 (define_expand "bunordered"
1627 (if_then_else (unordered (match_dup 1) (match_dup 2))
1628 (label_ref (match_operand 0 "" ""))
1633 if (hppa_branch_type == CMP_SI)
1635 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1636 emit_bcond_fp (NE, operands[0]);
1640 (define_expand "bordered"
1642 (if_then_else (ordered (match_dup 1) (match_dup 2))
1643 (label_ref (match_operand 0 "" ""))
1648 if (hppa_branch_type == CMP_SI)
1650 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1651 emit_bcond_fp (NE, operands[0]);
1655 ;; Match the branch patterns.
1658 ;; Note a long backward conditional branch with an annulled delay slot
1659 ;; has a length of 12.
1663 (match_operator 3 "comparison_operator"
1664 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1665 (match_operand:SI 2 "arith5_operand" "rL")])
1666 (label_ref (match_operand 0 "" ""))
1671 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1672 get_attr_length (insn), 0, insn);
1674 [(set_attr "type" "cbranch")
1675 (set (attr "length")
1676 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1679 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1682 (eq (symbol_ref "flag_pic") (const_int 0))
1686 ;; Match the negated branch.
1691 (match_operator 3 "comparison_operator"
1692 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1693 (match_operand:SI 2 "arith5_operand" "rL")])
1695 (label_ref (match_operand 0 "" ""))))]
1699 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1700 get_attr_length (insn), 1, insn);
1702 [(set_attr "type" "cbranch")
1703 (set (attr "length")
1704 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1707 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1710 (eq (symbol_ref "flag_pic") (const_int 0))
1717 (match_operator 3 "comparison_operator"
1718 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1719 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1720 (label_ref (match_operand 0 "" ""))
1725 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1726 get_attr_length (insn), 0, insn);
1728 [(set_attr "type" "cbranch")
1729 (set (attr "length")
1730 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1733 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1736 (eq (symbol_ref "flag_pic") (const_int 0))
1740 ;; Match the negated branch.
1745 (match_operator 3 "comparison_operator"
1746 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1747 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1749 (label_ref (match_operand 0 "" ""))))]
1753 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1754 get_attr_length (insn), 1, insn);
1756 [(set_attr "type" "cbranch")
1757 (set (attr "length")
1758 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1761 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1764 (eq (symbol_ref "flag_pic") (const_int 0))
1770 (match_operator 3 "cmpib_comparison_operator"
1771 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1772 (match_operand:DI 2 "arith5_operand" "rL")])
1773 (label_ref (match_operand 0 "" ""))
1778 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1779 get_attr_length (insn), 0, insn);
1781 [(set_attr "type" "cbranch")
1782 (set (attr "length")
1783 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1786 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1789 (eq (symbol_ref "flag_pic") (const_int 0))
1793 ;; Match the negated branch.
1798 (match_operator 3 "cmpib_comparison_operator"
1799 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1800 (match_operand:DI 2 "arith5_operand" "rL")])
1802 (label_ref (match_operand 0 "" ""))))]
1806 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1807 get_attr_length (insn), 1, insn);
1809 [(set_attr "type" "cbranch")
1810 (set (attr "length")
1811 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1814 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1817 (eq (symbol_ref "flag_pic") (const_int 0))
1821 ;; Branch on Bit patterns.
1825 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1827 (match_operand:SI 1 "uint5_operand" ""))
1829 (label_ref (match_operand 2 "" ""))
1834 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1835 get_attr_length (insn), 0, insn, 0);
1837 [(set_attr "type" "cbranch")
1838 (set (attr "length")
1839 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1847 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1849 (match_operand:DI 1 "uint32_operand" ""))
1851 (label_ref (match_operand 2 "" ""))
1856 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1857 get_attr_length (insn), 0, insn, 0);
1859 [(set_attr "type" "cbranch")
1860 (set (attr "length")
1861 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1869 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1871 (match_operand:SI 1 "uint5_operand" ""))
1874 (label_ref (match_operand 2 "" ""))))]
1878 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1879 get_attr_length (insn), 1, insn, 0);
1881 [(set_attr "type" "cbranch")
1882 (set (attr "length")
1883 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1891 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1893 (match_operand:DI 1 "uint32_operand" ""))
1896 (label_ref (match_operand 2 "" ""))))]
1900 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1901 get_attr_length (insn), 1, insn, 0);
1903 [(set_attr "type" "cbranch")
1904 (set (attr "length")
1905 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1913 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1915 (match_operand:SI 1 "uint5_operand" ""))
1917 (label_ref (match_operand 2 "" ""))
1922 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1923 get_attr_length (insn), 0, insn, 1);
1925 [(set_attr "type" "cbranch")
1926 (set (attr "length")
1927 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1935 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1937 (match_operand:DI 1 "uint32_operand" ""))
1939 (label_ref (match_operand 2 "" ""))
1944 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1945 get_attr_length (insn), 0, insn, 1);
1947 [(set_attr "type" "cbranch")
1948 (set (attr "length")
1949 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1957 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1959 (match_operand:SI 1 "uint5_operand" ""))
1962 (label_ref (match_operand 2 "" ""))))]
1966 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1967 get_attr_length (insn), 1, insn, 1);
1969 [(set_attr "type" "cbranch")
1970 (set (attr "length")
1971 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1979 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1981 (match_operand:DI 1 "uint32_operand" ""))
1984 (label_ref (match_operand 2 "" ""))))]
1988 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1989 get_attr_length (insn), 1, insn, 1);
1991 [(set_attr "type" "cbranch")
1992 (set (attr "length")
1993 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1998 ;; Branch on Variable Bit patterns.
2002 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2004 (match_operand:SI 1 "register_operand" "q"))
2006 (label_ref (match_operand 2 "" ""))
2011 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2012 get_attr_length (insn), 0, insn, 0);
2014 [(set_attr "type" "cbranch")
2015 (set (attr "length")
2016 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2024 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2026 (match_operand:DI 1 "register_operand" "q"))
2028 (label_ref (match_operand 2 "" ""))
2033 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2034 get_attr_length (insn), 0, insn, 0);
2036 [(set_attr "type" "cbranch")
2037 (set (attr "length")
2038 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2046 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2048 (match_operand:SI 1 "register_operand" "q"))
2051 (label_ref (match_operand 2 "" ""))))]
2055 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2056 get_attr_length (insn), 1, insn, 0);
2058 [(set_attr "type" "cbranch")
2059 (set (attr "length")
2060 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2068 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2070 (match_operand:DI 1 "register_operand" "q"))
2073 (label_ref (match_operand 2 "" ""))))]
2077 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2078 get_attr_length (insn), 1, insn, 0);
2080 [(set_attr "type" "cbranch")
2081 (set (attr "length")
2082 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2090 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2092 (match_operand:SI 1 "register_operand" "q"))
2094 (label_ref (match_operand 2 "" ""))
2099 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2100 get_attr_length (insn), 0, insn, 1);
2102 [(set_attr "type" "cbranch")
2103 (set (attr "length")
2104 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2112 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2114 (match_operand:DI 1 "register_operand" "q"))
2116 (label_ref (match_operand 2 "" ""))
2121 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2122 get_attr_length (insn), 0, insn, 1);
2124 [(set_attr "type" "cbranch")
2125 (set (attr "length")
2126 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2134 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2136 (match_operand:SI 1 "register_operand" "q"))
2139 (label_ref (match_operand 2 "" ""))))]
2143 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2144 get_attr_length (insn), 1, insn, 1);
2146 [(set_attr "type" "cbranch")
2147 (set (attr "length")
2148 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2156 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2158 (match_operand:DI 1 "register_operand" "q"))
2161 (label_ref (match_operand 2 "" ""))))]
2165 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2166 get_attr_length (insn), 1, insn, 1);
2168 [(set_attr "type" "cbranch")
2169 (set (attr "length")
2170 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2175 ;; Floating point branches
2177 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2178 (label_ref (match_operand 0 "" ""))
2180 "! TARGET_SOFT_FLOAT"
2183 if (INSN_ANNULLED_BRANCH_P (insn))
2184 return \"ftest\;b,n %0\";
2186 return \"ftest\;b%* %0\";
2188 [(set_attr "type" "fbranch")
2189 (set_attr "length" "8")])
2192 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2194 (label_ref (match_operand 0 "" ""))))]
2195 "! TARGET_SOFT_FLOAT"
2198 if (INSN_ANNULLED_BRANCH_P (insn))
2199 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2201 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2203 [(set_attr "type" "fbranch")
2204 (set_attr "length" "12")])
2206 ;; Move instructions
2208 (define_expand "movsi"
2209 [(set (match_operand:SI 0 "general_operand" "")
2210 (match_operand:SI 1 "general_operand" ""))]
2214 if (emit_move_sequence (operands, SImode, 0))
2218 ;; Reloading an SImode or DImode value requires a scratch register if
2219 ;; going in to or out of float point registers.
2221 (define_expand "reload_insi"
2222 [(set (match_operand:SI 0 "register_operand" "=Z")
2223 (match_operand:SI 1 "non_hard_reg_operand" ""))
2224 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2228 if (emit_move_sequence (operands, SImode, operands[2]))
2231 /* We don't want the clobber emitted, so handle this ourselves. */
2232 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2236 (define_expand "reload_outsi"
2237 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2238 (match_operand:SI 1 "register_operand" "Z"))
2239 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2243 if (emit_move_sequence (operands, SImode, operands[2]))
2246 /* We don't want the clobber emitted, so handle this ourselves. */
2247 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2252 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2253 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
2254 (match_operand:SI 1 "move_operand"
2255 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
2256 "(register_operand (operands[0], SImode)
2257 || reg_or_0_operand (operands[1], SImode))
2258 && ! TARGET_SOFT_FLOAT"
2264 {zdepi|depwi,z} %Z1,%0
2271 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2272 (set_attr "pa_combine_type" "addmove")
2273 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2276 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2277 "=r,r,r,r,r,r,Q,*q")
2278 (match_operand:SI 1 "move_operand"
2279 "A,r,J,N,K,RQ,rM,rM"))]
2280 "(register_operand (operands[0], SImode)
2281 || reg_or_0_operand (operands[1], SImode))
2282 && TARGET_SOFT_FLOAT"
2288 {zdepi|depwi,z} %Z1,%0
2292 [(set_attr "type" "load,move,move,move,move,load,store,move")
2293 (set_attr "pa_combine_type" "addmove")
2294 (set_attr "length" "4,4,4,4,4,4,4,4")])
2297 [(set (match_operand:SI 0 "register_operand" "=r")
2298 (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2299 (match_operand:SI 2 "register_operand" "r"))))]
2300 "! TARGET_DISABLE_INDEXING"
2301 "{ldwx|ldw} %2(%1),%0"
2302 [(set_attr "type" "load")
2303 (set_attr "length" "4")])
2306 [(set (match_operand:SI 0 "register_operand" "=r")
2307 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2308 (match_operand:SI 2 "basereg_operand" "r"))))]
2309 "! TARGET_DISABLE_INDEXING"
2310 "{ldwx|ldw} %1(%2),%0"
2311 [(set_attr "type" "load")
2312 (set_attr "length" "4")])
2314 ;; Load or store with base-register modification.
2316 (define_expand "pre_load"
2317 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2318 (mem (plus (match_operand 1 "register_operand" "")
2319 (match_operand 2 "pre_cint_operand" ""))))
2321 (plus (match_dup 1) (match_dup 2)))])]
2327 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2330 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2334 (define_insn "pre_ldw"
2335 [(set (match_operand:SI 0 "register_operand" "=r")
2336 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2337 (match_operand:SI 2 "pre_cint_operand" ""))))
2339 (plus:SI (match_dup 1) (match_dup 2)))]
2343 if (INTVAL (operands[2]) < 0)
2344 return \"{ldwm|ldw,mb} %2(%1),%0\";
2345 return \"{ldws|ldw},mb %2(%1),%0\";
2347 [(set_attr "type" "load")
2348 (set_attr "length" "4")])
2350 (define_insn "pre_ldd"
2351 [(set (match_operand:DI 0 "register_operand" "=r")
2352 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2353 (match_operand:DI 2 "pre_cint_operand" ""))))
2355 (plus:DI (match_dup 1) (match_dup 2)))]
2358 [(set_attr "type" "load")
2359 (set_attr "length" "4")])
2362 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2363 (match_operand:SI 1 "pre_cint_operand" "")))
2364 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2366 (plus:SI (match_dup 0) (match_dup 1)))]
2370 if (INTVAL (operands[1]) < 0)
2371 return \"{stwm|stw,mb} %r2,%1(%0)\";
2372 return \"{stws|stw},mb %r2,%1(%0)\";
2374 [(set_attr "type" "store")
2375 (set_attr "length" "4")])
2378 [(set (match_operand:SI 0 "register_operand" "=r")
2379 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2381 (plus:SI (match_dup 1)
2382 (match_operand:SI 2 "post_cint_operand" "")))]
2386 if (INTVAL (operands[2]) > 0)
2387 return \"{ldwm|ldw,ma} %2(%1),%0\";
2388 return \"{ldws|ldw},ma %2(%1),%0\";
2390 [(set_attr "type" "load")
2391 (set_attr "length" "4")])
2393 (define_expand "post_store"
2394 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2395 (match_operand 1 "reg_or_0_operand" ""))
2398 (match_operand 2 "post_cint_operand" "")))])]
2404 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2407 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2411 (define_insn "post_stw"
2412 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2413 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2415 (plus:SI (match_dup 0)
2416 (match_operand:SI 2 "post_cint_operand" "")))]
2420 if (INTVAL (operands[2]) > 0)
2421 return \"{stwm|stw,ma} %r1,%2(%0)\";
2422 return \"{stws|stw},ma %r1,%2(%0)\";
2424 [(set_attr "type" "store")
2425 (set_attr "length" "4")])
2427 (define_insn "post_std"
2428 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2429 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2431 (plus:DI (match_dup 0)
2432 (match_operand:DI 2 "post_cint_operand" "")))]
2435 [(set_attr "type" "store")
2436 (set_attr "length" "4")])
2438 ;; For loading the address of a label while generating PIC code.
2439 ;; Note since this pattern can be created at reload time (via movsi), all
2440 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2442 [(set (match_operand 0 "pmode_register_operand" "=a")
2443 (match_operand 1 "pic_label_operand" ""))]
2448 extern FILE *asm_out_file;
2450 xoperands[0] = operands[0];
2451 xoperands[1] = operands[1];
2452 if (TARGET_SOM || ! TARGET_GAS)
2453 xoperands[2] = gen_label_rtx ();
2455 output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
2456 output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
2457 if (TARGET_SOM || ! TARGET_GAS)
2458 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2459 CODE_LABEL_NUMBER (xoperands[2]));
2461 /* If we're trying to load the address of a label that happens to be
2462 close, then we can use a shorter sequence. */
2463 if (GET_CODE (operands[1]) == LABEL_REF
2464 && INSN_ADDRESSES_SET_P ()
2465 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2466 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2468 /* Prefixing with R% here is wrong, it extracts just 11 bits and is
2469 always non-negative. */
2470 if (TARGET_SOM || ! TARGET_GAS)
2471 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2473 output_asm_insn (\"ldo %1-$PIC_pcrel$0+8(%0),%0\", xoperands);
2477 if (TARGET_SOM || ! TARGET_GAS)
2479 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2480 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2484 output_asm_insn (\"addil L%%%1-$PIC_pcrel$0+8,%0\", xoperands);
2485 output_asm_insn (\"ldo R%%%1-$PIC_pcrel$0+12(%0),%0\",
2491 [(set_attr "type" "multi")
2492 (set_attr "length" "16")]) ; 12 or 16
2495 [(set (match_operand:SI 0 "register_operand" "=a")
2496 (plus:SI (match_operand:SI 1 "register_operand" "r")
2497 (high:SI (match_operand 2 "" ""))))]
2498 "symbolic_operand (operands[2], Pmode)
2499 && ! function_label_operand (operands[2], Pmode)
2502 [(set_attr "type" "binary")
2503 (set_attr "length" "4")])
2506 [(set (match_operand:DI 0 "register_operand" "=a")
2507 (plus:DI (match_operand:DI 1 "register_operand" "r")
2508 (high:DI (match_operand 2 "" ""))))]
2509 "symbolic_operand (operands[2], Pmode)
2510 && ! function_label_operand (operands[2], Pmode)
2514 [(set_attr "type" "binary")
2515 (set_attr "length" "4")])
2517 ;; Always use addil rather than ldil;add sequences. This allows the
2518 ;; HP linker to eliminate the dp relocation if the symbolic operand
2519 ;; lives in the TEXT space.
2521 [(set (match_operand:SI 0 "register_operand" "=a")
2522 (high:SI (match_operand 1 "" "")))]
2523 "symbolic_operand (operands[1], Pmode)
2524 && ! function_label_operand (operands[1], Pmode)
2525 && ! read_only_operand (operands[1], Pmode)
2529 if (TARGET_LONG_LOAD_STORE)
2530 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2532 return \"addil LR'%H1,%%r27\";
2534 [(set_attr "type" "binary")
2535 (set (attr "length")
2536 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2541 ;; This is for use in the prologue/epilogue code. We need it
2542 ;; to add large constants to a stack pointer or frame pointer.
2543 ;; Because of the additional %r1 pressure, we probably do not
2544 ;; want to use this in general code, so make it available
2545 ;; only after reload.
2547 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2548 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2549 (high:SI (match_operand 2 "const_int_operand" ""))))]
2553 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2554 [(set_attr "type" "binary,binary")
2555 (set_attr "length" "4,8")])
2558 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2559 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2560 (high:DI (match_operand 2 "const_int_operand" ""))))]
2561 "reload_completed && TARGET_64BIT"
2564 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2565 [(set_attr "type" "binary,binary")
2566 (set_attr "length" "4,8")])
2569 [(set (match_operand:SI 0 "register_operand" "=r")
2570 (high:SI (match_operand 1 "" "")))]
2571 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2572 && !is_function_label_plus_const (operands[1])"
2575 if (symbolic_operand (operands[1], Pmode))
2576 return \"ldil LR'%H1,%0\";
2578 return \"ldil L'%G1,%0\";
2580 [(set_attr "type" "move")
2581 (set_attr "length" "4")])
2584 [(set (match_operand:DI 0 "register_operand" "=r")
2585 (high:DI (match_operand 1 "const_int_operand" "")))]
2588 [(set_attr "type" "move")
2589 (set_attr "length" "4")])
2592 [(set (match_operand:DI 0 "register_operand" "=r")
2593 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2594 (match_operand:DI 2 "const_int_operand" "i")))]
2597 [(set_attr "type" "move")
2598 (set_attr "length" "4")])
2601 [(set (match_operand:SI 0 "register_operand" "=r")
2602 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2603 (match_operand:SI 2 "immediate_operand" "i")))]
2604 "!is_function_label_plus_const (operands[2])"
2607 if (flag_pic && symbolic_operand (operands[2], Pmode))
2609 else if (symbolic_operand (operands[2], Pmode))
2610 return \"ldo RR'%G2(%1),%0\";
2612 return \"ldo R'%G2(%1),%0\";
2614 [(set_attr "type" "move")
2615 (set_attr "length" "4")])
2617 ;; Now that a symbolic_address plus a constant is broken up early
2618 ;; in the compilation phase (for better CSE) we need a special
2619 ;; combiner pattern to load the symbolic address plus the constant
2620 ;; in only 2 instructions. (For cases where the symbolic address
2621 ;; was not a common subexpression.)
2623 [(set (match_operand:SI 0 "register_operand" "")
2624 (match_operand:SI 1 "symbolic_operand" ""))
2625 (clobber (match_operand:SI 2 "register_operand" ""))]
2626 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2627 [(set (match_dup 2) (high:SI (match_dup 1)))
2628 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2631 ;; hppa_legitimize_address goes to a great deal of trouble to
2632 ;; create addresses which use indexing. In some cases, this
2633 ;; is a lose because there isn't any store instructions which
2634 ;; allow indexed addresses (with integer register source).
2636 ;; These define_splits try to turn a 3 insn store into
2637 ;; a 2 insn store with some creative RTL rewriting.
2639 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2640 (match_operand:SI 1 "shadd_operand" ""))
2641 (plus:SI (match_operand:SI 2 "register_operand" "")
2642 (match_operand:SI 3 "const_int_operand" ""))))
2643 (match_operand:SI 4 "register_operand" ""))
2644 (clobber (match_operand:SI 5 "register_operand" ""))]
2646 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2648 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2652 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2653 (match_operand:SI 1 "shadd_operand" ""))
2654 (plus:SI (match_operand:SI 2 "register_operand" "")
2655 (match_operand:SI 3 "const_int_operand" ""))))
2656 (match_operand:HI 4 "register_operand" ""))
2657 (clobber (match_operand:SI 5 "register_operand" ""))]
2659 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2661 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2665 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2666 (match_operand:SI 1 "shadd_operand" ""))
2667 (plus:SI (match_operand:SI 2 "register_operand" "")
2668 (match_operand:SI 3 "const_int_operand" ""))))
2669 (match_operand:QI 4 "register_operand" ""))
2670 (clobber (match_operand:SI 5 "register_operand" ""))]
2672 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2674 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2677 (define_expand "movhi"
2678 [(set (match_operand:HI 0 "general_operand" "")
2679 (match_operand:HI 1 "general_operand" ""))]
2683 if (emit_move_sequence (operands, HImode, 0))
2688 [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2689 (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2690 "register_operand (operands[0], HImode)
2691 || reg_or_0_operand (operands[1], HImode)"
2696 {zdepi|depwi,z} %Z1,%0
2701 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2702 (set_attr "pa_combine_type" "addmove")
2703 (set_attr "length" "4,4,4,4,4,4,4,4")])
2706 [(set (match_operand:HI 0 "register_operand" "=r")
2707 (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2708 (match_operand:SI 2 "register_operand" "r"))))]
2709 "! TARGET_DISABLE_INDEXING"
2710 "{ldhx|ldh} %2(%1),%0"
2711 [(set_attr "type" "load")
2712 (set_attr "length" "4")])
2715 [(set (match_operand:HI 0 "register_operand" "=r")
2716 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
2717 (match_operand:SI 2 "basereg_operand" "r"))))]
2718 "! TARGET_DISABLE_INDEXING"
2719 "{ldhx|ldh} %1(%2),%0"
2720 [(set_attr "type" "load")
2721 (set_attr "length" "4")])
2723 ; Now zero extended variants.
2725 [(set (match_operand:SI 0 "register_operand" "=r")
2726 (zero_extend:SI (mem:HI
2728 (match_operand:SI 1 "basereg_operand" "r")
2729 (match_operand:SI 2 "register_operand" "r")))))]
2730 "! TARGET_DISABLE_INDEXING"
2731 "{ldhx|ldh} %2(%1),%0"
2732 [(set_attr "type" "load")
2733 (set_attr "length" "4")])
2736 [(set (match_operand:SI 0 "register_operand" "=r")
2737 (zero_extend:SI (mem:HI
2739 (match_operand:SI 1 "register_operand" "r")
2740 (match_operand:SI 2 "basereg_operand" "r")))))]
2741 "! TARGET_DISABLE_INDEXING"
2742 "{ldhx|ldh} %1(%2),%0"
2743 [(set_attr "type" "load")
2744 (set_attr "length" "4")])
2747 [(set (match_operand:HI 0 "register_operand" "=r")
2748 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2749 (match_operand:SI 2 "int5_operand" "L"))))
2751 (plus:SI (match_dup 1) (match_dup 2)))]
2753 "{ldhs|ldh},mb %2(%1),%0"
2754 [(set_attr "type" "load")
2755 (set_attr "length" "4")])
2757 ; And a zero extended variant.
2759 [(set (match_operand:SI 0 "register_operand" "=r")
2760 (zero_extend:SI (mem:HI
2762 (match_operand:SI 1 "register_operand" "+r")
2763 (match_operand:SI 2 "int5_operand" "L")))))
2765 (plus:SI (match_dup 1) (match_dup 2)))]
2767 "{ldhs|ldh},mb %2(%1),%0"
2768 [(set_attr "type" "load")
2769 (set_attr "length" "4")])
2772 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2773 (match_operand:SI 1 "int5_operand" "L")))
2774 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2776 (plus:SI (match_dup 0) (match_dup 1)))]
2778 "{sths|sth},mb %r2,%1(%0)"
2779 [(set_attr "type" "store")
2780 (set_attr "length" "4")])
2783 [(set (match_operand:HI 0 "register_operand" "=r")
2784 (plus:HI (match_operand:HI 1 "register_operand" "r")
2785 (match_operand 2 "const_int_operand" "J")))]
2788 [(set_attr "type" "binary")
2789 (set_attr "pa_combine_type" "addmove")
2790 (set_attr "length" "4")])
2792 (define_expand "movqi"
2793 [(set (match_operand:QI 0 "general_operand" "")
2794 (match_operand:QI 1 "general_operand" ""))]
2798 if (emit_move_sequence (operands, QImode, 0))
2803 [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2804 (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2805 "register_operand (operands[0], QImode)
2806 || reg_or_0_operand (operands[1], QImode)"
2811 {zdepi|depwi,z} %Z1,%0
2816 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2817 (set_attr "pa_combine_type" "addmove")
2818 (set_attr "length" "4,4,4,4,4,4,4,4")])
2821 [(set (match_operand:QI 0 "register_operand" "=r")
2822 (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2823 (match_operand:SI 2 "register_operand" "r"))))]
2824 "! TARGET_DISABLE_INDEXING"
2825 "{ldbx|ldb} %2(%1),%0"
2826 [(set_attr "type" "load")
2827 (set_attr "length" "4")])
2830 [(set (match_operand:QI 0 "register_operand" "=r")
2831 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
2832 (match_operand:SI 2 "basereg_operand" "r"))))]
2833 "! TARGET_DISABLE_INDEXING"
2834 "{ldbx|ldb} %1(%2),%0"
2835 [(set_attr "type" "load")
2836 (set_attr "length" "4")])
2838 ; Indexed byte load with zero extension to SImode or HImode.
2840 [(set (match_operand:SI 0 "register_operand" "=r")
2841 (zero_extend:SI (mem:QI
2843 (match_operand:SI 1 "basereg_operand" "r")
2844 (match_operand:SI 2 "register_operand" "r")))))]
2845 "! TARGET_DISABLE_INDEXING"
2846 "{ldbx|ldb} %2(%1),%0"
2847 [(set_attr "type" "load")
2848 (set_attr "length" "4")])
2851 [(set (match_operand:SI 0 "register_operand" "=r")
2852 (zero_extend:SI (mem:QI
2854 (match_operand:SI 1 "register_operand" "r")
2855 (match_operand:SI 2 "basereg_operand" "r")))))]
2856 "! TARGET_DISABLE_INDEXING"
2857 "{ldbx|ldb} %1(%2),%0"
2858 [(set_attr "type" "load")
2859 (set_attr "length" "4")])
2862 [(set (match_operand:HI 0 "register_operand" "=r")
2863 (zero_extend:HI (mem:QI
2865 (match_operand:SI 1 "basereg_operand" "r")
2866 (match_operand:SI 2 "register_operand" "r")))))]
2867 "! TARGET_DISABLE_INDEXING"
2868 "{ldbx|ldb} %2(%1),%0"
2869 [(set_attr "type" "load")
2870 (set_attr "length" "4")])
2873 [(set (match_operand:HI 0 "register_operand" "=r")
2874 (zero_extend:HI (mem:QI
2876 (match_operand:SI 1 "register_operand" "r")
2877 (match_operand:SI 2 "basereg_operand" "r")))))]
2878 "! TARGET_DISABLE_INDEXING"
2879 "{ldbx|ldb} %1(%2),%0"
2880 [(set_attr "type" "load")
2881 (set_attr "length" "4")])
2884 [(set (match_operand:QI 0 "register_operand" "=r")
2885 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2886 (match_operand:SI 2 "int5_operand" "L"))))
2887 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2889 "{ldbs|ldb},mb %2(%1),%0"
2890 [(set_attr "type" "load")
2891 (set_attr "length" "4")])
2893 ; Now the same thing with zero extensions.
2895 [(set (match_operand:SI 0 "register_operand" "=r")
2896 (zero_extend:SI (mem:QI (plus:SI
2897 (match_operand:SI 1 "register_operand" "+r")
2898 (match_operand:SI 2 "int5_operand" "L")))))
2899 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2901 "{ldbs|ldb},mb %2(%1),%0"
2902 [(set_attr "type" "load")
2903 (set_attr "length" "4")])
2906 [(set (match_operand:HI 0 "register_operand" "=r")
2907 (zero_extend:HI (mem:QI (plus:SI
2908 (match_operand:SI 1 "register_operand" "+r")
2909 (match_operand:SI 2 "int5_operand" "L")))))
2910 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2912 "{ldbs|ldb},mb %2(%1),%0"
2913 [(set_attr "type" "load")
2914 (set_attr "length" "4")])
2917 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2918 (match_operand:SI 1 "int5_operand" "L")))
2919 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2921 (plus:SI (match_dup 0) (match_dup 1)))]
2923 "{stbs|stb},mb %r2,%1(%0)"
2924 [(set_attr "type" "store")
2925 (set_attr "length" "4")])
2927 ;; The definition of this insn does not really explain what it does,
2928 ;; but it should suffice
2929 ;; that anything generated as this insn will be recognized as one
2930 ;; and that it will not successfully combine with anything.
2931 (define_expand "movstrsi"
2932 [(parallel [(set (match_operand:BLK 0 "" "")
2933 (match_operand:BLK 1 "" ""))
2934 (clobber (match_dup 7))
2935 (clobber (match_dup 8))
2936 (clobber (match_dup 4))
2937 (clobber (match_dup 5))
2938 (clobber (match_dup 6))
2939 (use (match_operand:SI 2 "arith_operand" ""))
2940 (use (match_operand:SI 3 "const_int_operand" ""))])]
2946 /* HP provides very fast block move library routine for the PA;
2947 this routine includes:
2949 4x4 byte at a time block moves,
2950 1x4 byte at a time with alignment checked at runtime with
2951 attempts to align the source and destination as needed
2954 With that in mind, here's the heuristics to try and guess when
2955 the inlined block move will be better than the library block
2958 If the size isn't constant, then always use the library routines.
2960 If the size is large in respect to the known alignment, then use
2961 the library routines.
2963 If the size is small in repsect to the known alignment, then open
2964 code the copy (since that will lead to better scheduling).
2966 Else use the block move pattern. */
2968 /* Undetermined size, use the library routine. */
2969 if (GET_CODE (operands[2]) != CONST_INT)
2972 size = INTVAL (operands[2]);
2973 align = INTVAL (operands[3]);
2974 align = align > 4 ? 4 : align;
2976 /* If size/alignment > 8 (eg size is large in respect to alignment),
2977 then use the library routines. */
2978 if (size / align > 16)
2981 /* This does happen, but not often enough to worry much about. */
2982 if (size / align < MOVE_RATIO)
2985 /* Fall through means we're going to use our block move pattern. */
2987 = replace_equiv_address (operands[0],
2988 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
2990 = replace_equiv_address (operands[1],
2991 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
2992 operands[4] = gen_reg_rtx (SImode);
2993 operands[5] = gen_reg_rtx (SImode);
2994 operands[6] = gen_reg_rtx (SImode);
2995 operands[7] = XEXP (operands[0], 0);
2996 operands[8] = XEXP (operands[1], 0);
2999 ;; The operand constraints are written like this to support both compile-time
3000 ;; and run-time determined byte count. If the count is run-time determined,
3001 ;; the register with the byte count is clobbered by the copying code, and
3002 ;; therefore it is forced to operand 2. If the count is compile-time
3003 ;; determined, we need two scratch registers for the unrolled code.
3004 (define_insn "movstrsi_internal"
3005 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3006 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3007 (clobber (match_dup 0))
3008 (clobber (match_dup 1))
3009 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
3010 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
3011 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3012 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3013 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3015 "* return output_block_move (operands, !which_alternative);"
3016 [(set_attr "type" "multi,multi")])
3018 ;; Floating point move insns
3020 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3021 ;; to be reloaded by putting the constant into memory when
3022 ;; reg is a floating point register.
3024 ;; For integer registers we use ldil;ldo to set the appropriate
3027 ;; This must come before the movdf pattern, and it must be present
3028 ;; to handle obscure reloading cases.
3030 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3031 (match_operand:DF 1 "" "?F,m"))]
3032 "GET_CODE (operands[1]) == CONST_DOUBLE
3033 && operands[1] != CONST0_RTX (DFmode)
3035 && ! TARGET_SOFT_FLOAT"
3036 "* return (which_alternative == 0 ? output_move_double (operands)
3037 : \"fldd%F1 %1,%0\");"
3038 [(set_attr "type" "move,fpload")
3039 (set_attr "length" "16,4")])
3041 (define_expand "movdf"
3042 [(set (match_operand:DF 0 "general_operand" "")
3043 (match_operand:DF 1 "general_operand" ""))]
3047 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3048 operands[1] = force_const_mem (DFmode, operands[1]);
3050 if (emit_move_sequence (operands, DFmode, 0))
3054 ;; Reloading an SImode or DImode value requires a scratch register if
3055 ;; going in to or out of float point registers.
3057 (define_expand "reload_indf"
3058 [(set (match_operand:DF 0 "register_operand" "=Z")
3059 (match_operand:DF 1 "non_hard_reg_operand" ""))
3060 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3064 if (emit_move_sequence (operands, DFmode, operands[2]))
3067 /* We don't want the clobber emitted, so handle this ourselves. */
3068 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3072 (define_expand "reload_outdf"
3073 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3074 (match_operand:DF 1 "register_operand" "Z"))
3075 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3079 if (emit_move_sequence (operands, DFmode, operands[2]))
3082 /* We don't want the clobber emitted, so handle this ourselves. */
3083 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3088 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3089 "=f,*r,RQ,?o,?Q,f,*r,*r")
3090 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3091 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3092 "(register_operand (operands[0], DFmode)
3093 || reg_or_0_operand (operands[1], DFmode))
3094 && ! (GET_CODE (operands[1]) == CONST_DOUBLE
3095 && GET_CODE (operands[0]) == MEM)
3097 && ! TARGET_SOFT_FLOAT"
3100 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3101 || operands[1] == CONST0_RTX (DFmode))
3102 return output_fp_move_double (operands);
3103 return output_move_double (operands);
3105 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3106 (set_attr "length" "4,8,4,8,16,4,8,16")])
3109 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3111 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3113 "(register_operand (operands[0], DFmode)
3114 || reg_or_0_operand (operands[1], DFmode))
3116 && TARGET_SOFT_FLOAT"
3119 return output_move_double (operands);
3121 [(set_attr "type" "move,store,store,load,load")
3122 (set_attr "length" "8,8,16,8,16")])
3125 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3126 "=r,r,r,r,r,Q,*q,!f,f,*TR")
3127 (match_operand:DF 1 "move_operand"
3128 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3129 "(register_operand (operands[0], DFmode)
3130 || reg_or_0_operand (operands[1], DFmode))
3131 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3143 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3144 (set_attr "pa_combine_type" "addmove")
3145 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3148 [(set (match_operand:DF 0 "register_operand" "=fx")
3149 (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3150 (match_operand:SI 2 "register_operand" "r"))))]
3151 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3152 "{flddx|fldd} %2(%1),%0"
3153 [(set_attr "type" "fpload")
3154 (set_attr "length" "4")])
3157 [(set (match_operand:DF 0 "register_operand" "=fx")
3158 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3159 (match_operand:SI 2 "basereg_operand" "r"))))]
3160 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3161 "{flddx|fldd} %1(%2),%0"
3162 [(set_attr "type" "fpload")
3163 (set_attr "length" "4")])
3166 [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3167 (match_operand:SI 2 "register_operand" "r")))
3168 (match_operand:DF 0 "register_operand" "fx"))]
3169 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3170 "{fstdx|fstd} %0,%2(%1)"
3171 [(set_attr "type" "fpstore")
3172 (set_attr "length" "4")])
3175 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3176 (match_operand:SI 2 "basereg_operand" "r")))
3177 (match_operand:DF 0 "register_operand" "fx"))]
3178 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3179 "{fstdx|fstd} %0,%1(%2)"
3180 [(set_attr "type" "fpstore")
3181 (set_attr "length" "4")])
3183 (define_expand "movdi"
3184 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
3185 (match_operand:DI 1 "general_operand" ""))]
3189 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3190 operands[1] = force_const_mem (DImode, operands[1]);
3192 if (emit_move_sequence (operands, DImode, 0))
3196 (define_expand "reload_indi"
3197 [(set (match_operand:DI 0 "register_operand" "=Z")
3198 (match_operand:DI 1 "non_hard_reg_operand" ""))
3199 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3203 if (emit_move_sequence (operands, DImode, operands[2]))
3206 /* We don't want the clobber emitted, so handle this ourselves. */
3207 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3211 (define_expand "reload_outdi"
3212 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
3213 (match_operand:DI 1 "register_operand" "Z"))
3214 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3218 if (emit_move_sequence (operands, DImode, operands[2]))
3221 /* We don't want the clobber emitted, so handle this ourselves. */
3222 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3227 [(set (match_operand:DI 0 "register_operand" "=r")
3228 (high:DI (match_operand 1 "" "")))]
3232 rtx op0 = operands[0];
3233 rtx op1 = operands[1];
3235 if (GET_CODE (op1) == CONST_INT)
3237 operands[0] = operand_subword (op0, 1, 0, DImode);
3238 output_asm_insn (\"ldil L'%1,%0\", operands);
3240 operands[0] = operand_subword (op0, 0, 0, DImode);
3241 if (INTVAL (op1) < 0)
3242 output_asm_insn (\"ldi -1,%0\", operands);
3244 output_asm_insn (\"ldi 0,%0\", operands);
3247 else if (GET_CODE (op1) == CONST_DOUBLE)
3249 operands[0] = operand_subword (op0, 1, 0, DImode);
3250 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3251 output_asm_insn (\"ldil L'%1,%0\", operands);
3253 operands[0] = operand_subword (op0, 0, 0, DImode);
3254 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3255 output_asm_insn (singlemove_string (operands), operands);
3261 [(set_attr "type" "move")
3262 (set_attr "length" "8")])
3265 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3266 "=r,o,Q,r,r,r,f,f,*TR")
3267 (match_operand:DI 1 "general_operand"
3268 "rM,r,r,o*R,Q,i,fM,*TR,f"))]
3269 "(register_operand (operands[0], DImode)
3270 || reg_or_0_operand (operands[1], DImode))
3272 && ! TARGET_SOFT_FLOAT"
3275 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3276 || (operands[1] == CONST0_RTX (DImode)))
3277 return output_fp_move_double (operands);
3278 return output_move_double (operands);
3280 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
3281 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
3284 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3285 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
3286 (match_operand:DI 1 "move_operand"
3287 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3288 "(register_operand (operands[0], DImode)
3289 || reg_or_0_operand (operands[1], DImode))
3290 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3303 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3304 (set_attr "pa_combine_type" "addmove")
3305 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
3308 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3310 (match_operand:DI 1 "general_operand"
3312 "(register_operand (operands[0], DImode)
3313 || reg_or_0_operand (operands[1], DImode))
3315 && TARGET_SOFT_FLOAT"
3318 return output_move_double (operands);
3320 [(set_attr "type" "move,store,store,load,load,multi")
3321 (set_attr "length" "8,8,16,8,16,16")])
3324 [(set (match_operand:DI 0 "register_operand" "=r,&r")
3325 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
3326 (match_operand:DI 2 "immediate_operand" "i,i")))]
3330 /* Don't output a 64 bit constant, since we can't trust the assembler to
3331 handle it correctly. */
3332 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3333 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3334 if (which_alternative == 1)
3335 output_asm_insn (\"copy %1,%0\", operands);
3336 return \"ldo R'%G2(%R1),%R0\";
3338 [(set_attr "type" "move,move")
3339 (set_attr "length" "4,8")])
3341 ;; This pattern forces (set (reg:SF ...) (const_double ...))
3342 ;; to be reloaded by putting the constant into memory when
3343 ;; reg is a floating point register.
3345 ;; For integer registers we use ldil;ldo to set the appropriate
3348 ;; This must come before the movsf pattern, and it must be present
3349 ;; to handle obscure reloading cases.
3351 [(set (match_operand:SF 0 "register_operand" "=?r,f")
3352 (match_operand:SF 1 "" "?F,m"))]
3353 "GET_CODE (operands[1]) == CONST_DOUBLE
3354 && operands[1] != CONST0_RTX (SFmode)
3355 && ! TARGET_SOFT_FLOAT"
3356 "* return (which_alternative == 0 ? singlemove_string (operands)
3357 : \" fldw%F1 %1,%0\");"
3358 [(set_attr "type" "move,fpload")
3359 (set_attr "length" "8,4")])
3361 (define_expand "movsf"
3362 [(set (match_operand:SF 0 "general_operand" "")
3363 (match_operand:SF 1 "general_operand" ""))]
3367 if (emit_move_sequence (operands, SFmode, 0))
3371 ;; Reloading an SImode or DImode value requires a scratch register if
3372 ;; going in to or out of float point registers.
3374 (define_expand "reload_insf"
3375 [(set (match_operand:SF 0 "register_operand" "=Z")
3376 (match_operand:SF 1 "non_hard_reg_operand" ""))
3377 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3381 if (emit_move_sequence (operands, SFmode, operands[2]))
3384 /* We don't want the clobber emitted, so handle this ourselves. */
3385 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3389 (define_expand "reload_outsf"
3390 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
3391 (match_operand:SF 1 "register_operand" "Z"))
3392 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3396 if (emit_move_sequence (operands, SFmode, operands[2]))
3399 /* We don't want the clobber emitted, so handle this ourselves. */
3400 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3405 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3407 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3408 "fG,rG,RQ,RQ,f,rG"))]
3409 "(register_operand (operands[0], SFmode)
3410 || reg_or_0_operand (operands[1], SFmode))
3411 && ! TARGET_SOFT_FLOAT"
3419 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
3420 (set_attr "pa_combine_type" "addmove")
3421 (set_attr "length" "4,4,4,4,4,4")])
3424 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3426 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3428 "(register_operand (operands[0], SFmode)
3429 || reg_or_0_operand (operands[1], SFmode))
3430 && TARGET_SOFT_FLOAT"
3435 [(set_attr "type" "move,load,store")
3436 (set_attr "pa_combine_type" "addmove")
3437 (set_attr "length" "4,4,4")])
3440 [(set (match_operand:SF 0 "register_operand" "=fx")
3441 (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3442 (match_operand:SI 2 "register_operand" "r"))))]
3443 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3444 "{fldwx|fldw} %2(%1),%0"
3445 [(set_attr "type" "fpload")
3446 (set_attr "length" "4")])
3449 [(set (match_operand:SF 0 "register_operand" "=fx")
3450 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3451 (match_operand:SI 2 "basereg_operand" "r"))))]
3452 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3453 "{fldwx|fldw} %1(%2),%0"
3454 [(set_attr "type" "fpload")
3455 (set_attr "length" "4")])
3458 [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3459 (match_operand:SI 2 "register_operand" "r")))
3460 (match_operand:SF 0 "register_operand" "fx"))]
3461 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3462 "{fstwx|fstw} %0,%2(%1)"
3463 [(set_attr "type" "fpstore")
3464 (set_attr "length" "4")])
3467 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3468 (match_operand:SI 2 "basereg_operand" "r")))
3469 (match_operand:SF 0 "register_operand" "fx"))]
3470 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3471 "{fstwx|fstw} %0,%1(%2)"
3472 [(set_attr "type" "fpstore")
3473 (set_attr "length" "4")])
3476 ;;- zero extension instructions
3477 ;; We have define_expand for zero extension patterns to make sure the
3478 ;; operands get loaded into registers. The define_insns accept
3479 ;; memory operands. This gives us better overall code than just
3480 ;; having a pattern that does or does not accept memory operands.
3482 (define_expand "zero_extendhisi2"
3483 [(set (match_operand:SI 0 "register_operand" "")
3485 (match_operand:HI 1 "register_operand" "")))]
3490 [(set (match_operand:SI 0 "register_operand" "=r,r")
3492 (match_operand:HI 1 "move_operand" "r,RQ")))]
3493 "GET_CODE (operands[1]) != CONST_INT"
3495 {extru|extrw,u} %1,31,16,%0
3497 [(set_attr "type" "shift,load")
3498 (set_attr "length" "4,4")])
3500 (define_expand "zero_extendqihi2"
3501 [(set (match_operand:HI 0 "register_operand" "")
3503 (match_operand:QI 1 "register_operand" "")))]
3508 [(set (match_operand:HI 0 "register_operand" "=r,r")
3510 (match_operand:QI 1 "move_operand" "r,RQ")))]
3511 "GET_CODE (operands[1]) != CONST_INT"
3513 {extru|extrw,u} %1,31,8,%0
3515 [(set_attr "type" "shift,load")
3516 (set_attr "length" "4,4")])
3518 (define_expand "zero_extendqisi2"
3519 [(set (match_operand:SI 0 "register_operand" "")
3521 (match_operand:QI 1 "register_operand" "")))]
3526 [(set (match_operand:SI 0 "register_operand" "=r,r")
3528 (match_operand:QI 1 "move_operand" "r,RQ")))]
3529 "GET_CODE (operands[1]) != CONST_INT"
3531 {extru|extrw,u} %1,31,8,%0
3533 [(set_attr "type" "shift,load")
3534 (set_attr "length" "4,4")])
3536 (define_insn "zero_extendqidi2"
3537 [(set (match_operand:DI 0 "register_operand" "=r")
3538 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3540 "extrd,u %1,63,8,%0"
3541 [(set_attr "type" "shift")
3542 (set_attr "length" "4")])
3544 (define_insn "zero_extendhidi2"
3545 [(set (match_operand:DI 0 "register_operand" "=r")
3546 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3548 "extrd,u %1,63,16,%0"
3549 [(set_attr "type" "shift")
3550 (set_attr "length" "4")])
3552 (define_insn "zero_extendsidi2"
3553 [(set (match_operand:DI 0 "register_operand" "=r")
3554 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3556 "extrd,u %1,63,32,%0"
3557 [(set_attr "type" "shift")
3558 (set_attr "length" "4")])
3560 ;;- sign extension instructions
3562 (define_insn "extendhisi2"
3563 [(set (match_operand:SI 0 "register_operand" "=r")
3564 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
3566 "{extrs|extrw,s} %1,31,16,%0"
3567 [(set_attr "type" "shift")
3568 (set_attr "length" "4")])
3570 (define_insn "extendqihi2"
3571 [(set (match_operand:HI 0 "register_operand" "=r")
3572 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
3574 "{extrs|extrw,s} %1,31,8,%0"
3575 [(set_attr "type" "shift")
3576 (set_attr "length" "4")])
3578 (define_insn "extendqisi2"
3579 [(set (match_operand:SI 0 "register_operand" "=r")
3580 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
3582 "{extrs|extrw,s} %1,31,8,%0"
3583 [(set_attr "type" "shift")
3584 (set_attr "length" "4")])
3586 (define_insn "extendqidi2"
3587 [(set (match_operand:DI 0 "register_operand" "=r")
3588 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3590 "extrd,s %1,63,8,%0"
3591 [(set_attr "type" "shift")
3592 (set_attr "length" "4")])
3594 (define_insn "extendhidi2"
3595 [(set (match_operand:DI 0 "register_operand" "=r")
3596 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3598 "extrd,s %1,63,16,%0"
3599 [(set_attr "type" "shift")
3600 (set_attr "length" "4")])
3602 (define_insn "extendsidi2"
3603 [(set (match_operand:DI 0 "register_operand" "=r")
3604 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3606 "extrd,s %1,63,32,%0"
3607 [(set_attr "type" "shift")
3608 (set_attr "length" "4")])
3611 ;; Conversions between float and double.
3613 (define_insn "extendsfdf2"
3614 [(set (match_operand:DF 0 "register_operand" "=f")
3616 (match_operand:SF 1 "register_operand" "f")))]
3617 "! TARGET_SOFT_FLOAT"
3618 "{fcnvff|fcnv},sgl,dbl %1,%0"
3619 [(set_attr "type" "fpalu")
3620 (set_attr "length" "4")])
3622 (define_insn "truncdfsf2"
3623 [(set (match_operand:SF 0 "register_operand" "=f")
3625 (match_operand:DF 1 "register_operand" "f")))]
3626 "! TARGET_SOFT_FLOAT"
3627 "{fcnvff|fcnv},dbl,sgl %1,%0"
3628 [(set_attr "type" "fpalu")
3629 (set_attr "length" "4")])
3631 ;; Conversion between fixed point and floating point.
3632 ;; Note that among the fix-to-float insns
3633 ;; the ones that start with SImode come first.
3634 ;; That is so that an operand that is a CONST_INT
3635 ;; (and therefore lacks a specific machine mode).
3636 ;; will be recognized as SImode (which is always valid)
3637 ;; rather than as QImode or HImode.
3639 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
3640 ;; to be reloaded by putting the constant into memory.
3641 ;; It must come before the more general floatsisf2 pattern.
3643 [(set (match_operand:SF 0 "register_operand" "=f")
3644 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
3645 "! TARGET_SOFT_FLOAT"
3646 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
3647 [(set_attr "type" "fpalu")
3648 (set_attr "length" "8")])
3650 (define_insn "floatsisf2"
3651 [(set (match_operand:SF 0 "register_operand" "=f")
3652 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3653 "! TARGET_SOFT_FLOAT"
3654 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
3655 [(set_attr "type" "fpalu")
3656 (set_attr "length" "4")])
3658 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
3659 ;; to be reloaded by putting the constant into memory.
3660 ;; It must come before the more general floatsidf2 pattern.
3662 [(set (match_operand:DF 0 "register_operand" "=f")
3663 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
3664 "! TARGET_SOFT_FLOAT"
3665 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
3666 [(set_attr "type" "fpalu")
3667 (set_attr "length" "8")])
3669 (define_insn "floatsidf2"
3670 [(set (match_operand:DF 0 "register_operand" "=f")
3671 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3672 "! TARGET_SOFT_FLOAT"
3673 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
3674 [(set_attr "type" "fpalu")
3675 (set_attr "length" "4")])
3677 (define_expand "floatunssisf2"
3678 [(set (subreg:SI (match_dup 2) 4)
3679 (match_operand:SI 1 "register_operand" ""))
3680 (set (subreg:SI (match_dup 2) 0)
3682 (set (match_operand:SF 0 "register_operand" "")
3683 (float:SF (match_dup 2)))]
3684 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3689 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
3692 operands[2] = gen_reg_rtx (DImode);
3695 (define_expand "floatunssidf2"
3696 [(set (subreg:SI (match_dup 2) 4)
3697 (match_operand:SI 1 "register_operand" ""))
3698 (set (subreg:SI (match_dup 2) 0)
3700 (set (match_operand:DF 0 "register_operand" "")
3701 (float:DF (match_dup 2)))]
3702 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3707 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
3710 operands[2] = gen_reg_rtx (DImode);
3713 (define_insn "floatdisf2"
3714 [(set (match_operand:SF 0 "register_operand" "=f")
3715 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3716 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3717 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
3718 [(set_attr "type" "fpalu")
3719 (set_attr "length" "4")])
3721 (define_insn "floatdidf2"
3722 [(set (match_operand:DF 0 "register_operand" "=f")
3723 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3724 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3725 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
3726 [(set_attr "type" "fpalu")
3727 (set_attr "length" "4")])
3729 ;; Convert a float to an actual integer.
3730 ;; Truncation is performed as part of the conversion.
3732 (define_insn "fix_truncsfsi2"
3733 [(set (match_operand:SI 0 "register_operand" "=f")
3734 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3735 "! TARGET_SOFT_FLOAT"
3736 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
3737 [(set_attr "type" "fpalu")
3738 (set_attr "length" "4")])
3740 (define_insn "fix_truncdfsi2"
3741 [(set (match_operand:SI 0 "register_operand" "=f")
3742 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3743 "! TARGET_SOFT_FLOAT"
3744 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
3745 [(set_attr "type" "fpalu")
3746 (set_attr "length" "4")])
3748 (define_insn "fix_truncsfdi2"
3749 [(set (match_operand:DI 0 "register_operand" "=f")
3750 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3751 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3752 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
3753 [(set_attr "type" "fpalu")
3754 (set_attr "length" "4")])
3756 (define_insn "fix_truncdfdi2"
3757 [(set (match_operand:DI 0 "register_operand" "=f")
3758 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3759 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3760 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
3761 [(set_attr "type" "fpalu")
3762 (set_attr "length" "4")])
3764 (define_insn "floatunssidf2_pa20"
3765 [(set (match_operand:DF 0 "register_operand" "=f")
3766 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
3767 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3769 [(set_attr "type" "fpalu")
3770 (set_attr "length" "4")])
3772 (define_insn "floatunssisf2_pa20"
3773 [(set (match_operand:SF 0 "register_operand" "=f")
3774 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
3775 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3777 [(set_attr "type" "fpalu")
3778 (set_attr "length" "4")])
3780 (define_insn "floatunsdisf2"
3781 [(set (match_operand:SF 0 "register_operand" "=f")
3782 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
3783 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3784 "fcnv,udw,sgl %1,%0"
3785 [(set_attr "type" "fpalu")
3786 (set_attr "length" "4")])
3788 (define_insn "floatunsdidf2"
3789 [(set (match_operand:DF 0 "register_operand" "=f")
3790 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
3791 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3792 "fcnv,udw,dbl %1,%0"
3793 [(set_attr "type" "fpalu")
3794 (set_attr "length" "4")])
3796 (define_insn "fixuns_truncsfsi2"
3797 [(set (match_operand:SI 0 "register_operand" "=f")
3798 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3799 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3800 "fcnv,t,sgl,uw %1,%0"
3801 [(set_attr "type" "fpalu")
3802 (set_attr "length" "4")])
3804 (define_insn "fixuns_truncdfsi2"
3805 [(set (match_operand:SI 0 "register_operand" "=f")
3806 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3807 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3808 "fcnv,t,dbl,uw %1,%0"
3809 [(set_attr "type" "fpalu")
3810 (set_attr "length" "4")])
3812 (define_insn "fixuns_truncsfdi2"
3813 [(set (match_operand:DI 0 "register_operand" "=f")
3814 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3815 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3816 "fcnv,t,sgl,udw %1,%0"
3817 [(set_attr "type" "fpalu")
3818 (set_attr "length" "4")])
3820 (define_insn "fixuns_truncdfdi2"
3821 [(set (match_operand:DI 0 "register_operand" "=f")
3822 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3823 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3824 "fcnv,t,dbl,udw %1,%0"
3825 [(set_attr "type" "fpalu")
3826 (set_attr "length" "4")])
3828 ;;- arithmetic instructions
3830 (define_expand "adddi3"
3831 [(set (match_operand:DI 0 "register_operand" "")
3832 (plus:DI (match_operand:DI 1 "register_operand" "")
3833 (match_operand:DI 2 "adddi3_operand" "")))]
3838 [(set (match_operand:DI 0 "register_operand" "=r")
3839 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3840 (match_operand:DI 2 "arith11_operand" "rI")))]
3844 if (GET_CODE (operands[2]) == CONST_INT)
3846 if (INTVAL (operands[2]) >= 0)
3847 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
3849 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
3852 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
3854 [(set_attr "type" "binary")
3855 (set_attr "length" "8")])
3858 [(set (match_operand:DI 0 "register_operand" "=r,r")
3859 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
3860 (match_operand:DI 2 "arith_operand" "r,J")))]
3863 {addl|add,l} %1,%2,%0
3865 [(set_attr "type" "binary,binary")
3866 (set_attr "pa_combine_type" "addmove")
3867 (set_attr "length" "4,4")])
3870 [(set (match_operand:DI 0 "register_operand" "=r")
3871 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
3872 (match_operand:DI 2 "register_operand" "r")))]
3875 [(set_attr "type" "binary")
3876 (set_attr "length" "4")])
3879 [(set (match_operand:SI 0 "register_operand" "=r")
3880 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3881 (match_operand:SI 2 "register_operand" "r")))]
3884 [(set_attr "type" "binary")
3885 (set_attr "length" "4")])
3887 ;; define_splits to optimize cases of adding a constant integer
3888 ;; to a register when the constant does not fit in 14 bits. */
3890 [(set (match_operand:SI 0 "register_operand" "")
3891 (plus:SI (match_operand:SI 1 "register_operand" "")
3892 (match_operand:SI 2 "const_int_operand" "")))
3893 (clobber (match_operand:SI 4 "register_operand" ""))]
3894 "! cint_ok_for_move (INTVAL (operands[2]))
3895 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
3896 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
3897 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
3900 int val = INTVAL (operands[2]);
3901 int low = (val < 0) ? -0x2000 : 0x1fff;
3902 int rest = val - low;
3904 operands[2] = GEN_INT (rest);
3905 operands[3] = GEN_INT (low);
3909 [(set (match_operand:SI 0 "register_operand" "")
3910 (plus:SI (match_operand:SI 1 "register_operand" "")
3911 (match_operand:SI 2 "const_int_operand" "")))
3912 (clobber (match_operand:SI 4 "register_operand" ""))]
3913 "! cint_ok_for_move (INTVAL (operands[2]))"
3914 [(set (match_dup 4) (match_dup 2))
3915 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
3919 HOST_WIDE_INT intval = INTVAL (operands[2]);
3921 /* Try dividing the constant by 2, then 4, and finally 8 to see
3922 if we can get a constant which can be loaded into a register
3923 in a single instruction (cint_ok_for_move).
3925 If that fails, try to negate the constant and subtract it
3926 from our input operand. */
3927 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
3929 operands[2] = GEN_INT (intval / 2);
3930 operands[3] = GEN_INT (2);
3932 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
3934 operands[2] = GEN_INT (intval / 4);
3935 operands[3] = GEN_INT (4);
3937 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
3939 operands[2] = GEN_INT (intval / 8);
3940 operands[3] = GEN_INT (8);
3942 else if (cint_ok_for_move (-intval))
3944 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
3945 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
3952 (define_insn "addsi3"
3953 [(set (match_operand:SI 0 "register_operand" "=r,r")
3954 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3955 (match_operand:SI 2 "arith_operand" "r,J")))]
3958 {addl|add,l} %1,%2,%0
3960 [(set_attr "type" "binary,binary")
3961 (set_attr "pa_combine_type" "addmove")
3962 (set_attr "length" "4,4")])
3964 (define_expand "subdi3"
3965 [(set (match_operand:DI 0 "register_operand" "")
3966 (minus:DI (match_operand:DI 1 "register_operand" "")
3967 (match_operand:DI 2 "register_operand" "")))]
3972 [(set (match_operand:DI 0 "register_operand" "=r")
3973 (minus:DI (match_operand:DI 1 "register_operand" "r")
3974 (match_operand:DI 2 "register_operand" "r")))]
3976 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
3977 [(set_attr "type" "binary")
3978 (set_attr "length" "8")])
3981 [(set (match_operand:DI 0 "register_operand" "=r,r,q")
3982 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,U")
3983 (match_operand:DI 2 "register_operand" "r,r,r")))]
3989 [(set_attr "type" "binary,binary,move")
3990 (set_attr "length" "4,4,4")])
3992 (define_expand "subsi3"
3993 [(set (match_operand:SI 0 "register_operand" "")
3994 (minus:SI (match_operand:SI 1 "arith11_operand" "")
3995 (match_operand:SI 2 "register_operand" "")))]
4000 [(set (match_operand:SI 0 "register_operand" "=r,r")
4001 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
4002 (match_operand:SI 2 "register_operand" "r,r")))]
4007 [(set_attr "type" "binary,binary")
4008 (set_attr "length" "4,4")])
4011 [(set (match_operand:SI 0 "register_operand" "=r,r,q")
4012 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
4013 (match_operand:SI 2 "register_operand" "r,r,r")))]
4019 [(set_attr "type" "binary,binary,move")
4020 (set_attr "length" "4,4,4")])
4022 ;; Clobbering a "register_operand" instead of a match_scratch
4023 ;; in operand3 of millicode calls avoids spilling %r1 and
4024 ;; produces better code.
4026 ;; The mulsi3 insns set up registers for the millicode call.
4027 (define_expand "mulsi3"
4028 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4029 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4030 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4031 (clobber (match_dup 3))
4032 (clobber (reg:SI 26))
4033 (clobber (reg:SI 25))
4034 (clobber (match_dup 4))])
4035 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4039 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4040 if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
4042 rtx scratch = gen_reg_rtx (DImode);
4043 operands[1] = force_reg (SImode, operands[1]);
4044 operands[2] = force_reg (SImode, operands[2]);
4045 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
4046 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4047 gen_rtx_SUBREG (SImode, scratch, GET_MODE_SIZE (SImode))));
4050 operands[3] = gen_reg_rtx (SImode);
4053 (define_insn "umulsidi3"
4054 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4055 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4056 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
4057 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4059 [(set_attr "type" "fpmuldbl")
4060 (set_attr "length" "4")])
4063 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4064 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4065 (match_operand:DI 2 "uint32_operand" "f")))]
4066 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
4068 [(set_attr "type" "fpmuldbl")
4069 (set_attr "length" "4")])
4072 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4073 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4074 (match_operand:DI 2 "uint32_operand" "f")))]
4075 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
4077 [(set_attr "type" "fpmuldbl")
4078 (set_attr "length" "4")])
4081 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4082 (clobber (match_operand:SI 0 "register_operand" "=a"))
4083 (clobber (reg:SI 26))
4084 (clobber (reg:SI 25))
4085 (clobber (reg:SI 31))]
4087 "* return output_mul_insn (0, insn);"
4088 [(set_attr "type" "milli")
4089 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4092 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4093 (clobber (match_operand:SI 0 "register_operand" "=a"))
4094 (clobber (reg:SI 26))
4095 (clobber (reg:SI 25))
4096 (clobber (reg:SI 2))]
4098 "* return output_mul_insn (0, insn);"
4099 [(set_attr "type" "milli")
4100 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4102 (define_expand "muldi3"
4103 [(set (match_operand:DI 0 "register_operand" "")
4104 (mult:DI (match_operand:DI 1 "register_operand" "")
4105 (match_operand:DI 2 "register_operand" "")))]
4106 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4109 rtx low_product = gen_reg_rtx (DImode);
4110 rtx cross_product1 = gen_reg_rtx (DImode);
4111 rtx cross_product2 = gen_reg_rtx (DImode);
4112 rtx cross_scratch = gen_reg_rtx (DImode);
4113 rtx cross_product = gen_reg_rtx (DImode);
4114 rtx op1l, op1r, op2l, op2r;
4115 rtx op1shifted, op2shifted;
4117 op1shifted = gen_reg_rtx (DImode);
4118 op2shifted = gen_reg_rtx (DImode);
4119 op1l = gen_reg_rtx (SImode);
4120 op1r = gen_reg_rtx (SImode);
4121 op2l = gen_reg_rtx (SImode);
4122 op2r = gen_reg_rtx (SImode);
4124 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
4126 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
4128 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
4129 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
4130 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
4131 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
4133 /* Emit multiplies for the cross products. */
4134 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
4135 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
4137 /* Emit a multiply for the low sub-word. */
4138 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
4140 /* Sum the cross products and shift them into proper position. */
4141 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
4142 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
4144 /* Add the cross product to the low product and store the result
4145 into the output operand . */
4146 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
4150 ;;; Division and mod.
4151 (define_expand "divsi3"
4152 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4153 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4154 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
4155 (clobber (match_dup 3))
4156 (clobber (match_dup 4))
4157 (clobber (reg:SI 26))
4158 (clobber (reg:SI 25))
4159 (clobber (match_dup 5))])
4160 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4164 operands[3] = gen_reg_rtx (SImode);
4167 operands[5] = gen_rtx_REG (SImode, 2);
4168 operands[4] = operands[5];
4172 operands[5] = gen_rtx_REG (SImode, 31);
4173 operands[4] = gen_reg_rtx (SImode);
4175 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
4181 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4182 (clobber (match_operand:SI 1 "register_operand" "=a"))
4183 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4184 (clobber (reg:SI 26))
4185 (clobber (reg:SI 25))
4186 (clobber (reg:SI 31))]
4189 return output_div_insn (operands, 0, insn);"
4190 [(set_attr "type" "milli")
4191 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4195 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4196 (clobber (match_operand:SI 1 "register_operand" "=a"))
4197 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4198 (clobber (reg:SI 26))
4199 (clobber (reg:SI 25))
4200 (clobber (reg:SI 2))]
4203 return output_div_insn (operands, 0, insn);"
4204 [(set_attr "type" "milli")
4205 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4207 (define_expand "udivsi3"
4208 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4209 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4210 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
4211 (clobber (match_dup 3))
4212 (clobber (match_dup 4))
4213 (clobber (reg:SI 26))
4214 (clobber (reg:SI 25))
4215 (clobber (match_dup 5))])
4216 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4220 operands[3] = gen_reg_rtx (SImode);
4224 operands[5] = gen_rtx_REG (SImode, 2);
4225 operands[4] = operands[5];
4229 operands[5] = gen_rtx_REG (SImode, 31);
4230 operands[4] = gen_reg_rtx (SImode);
4232 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
4238 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4239 (clobber (match_operand:SI 1 "register_operand" "=a"))
4240 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4241 (clobber (reg:SI 26))
4242 (clobber (reg:SI 25))
4243 (clobber (reg:SI 31))]
4246 return output_div_insn (operands, 1, insn);"
4247 [(set_attr "type" "milli")
4248 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4252 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4253 (clobber (match_operand:SI 1 "register_operand" "=a"))
4254 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4255 (clobber (reg:SI 26))
4256 (clobber (reg:SI 25))
4257 (clobber (reg:SI 2))]
4260 return output_div_insn (operands, 1, insn);"
4261 [(set_attr "type" "milli")
4262 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4264 (define_expand "modsi3"
4265 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4266 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4267 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4268 (clobber (match_dup 3))
4269 (clobber (match_dup 4))
4270 (clobber (reg:SI 26))
4271 (clobber (reg:SI 25))
4272 (clobber (match_dup 5))])
4273 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4279 operands[5] = gen_rtx_REG (SImode, 2);
4280 operands[4] = operands[5];
4284 operands[5] = gen_rtx_REG (SImode, 31);
4285 operands[4] = gen_reg_rtx (SImode);
4287 operands[3] = gen_reg_rtx (SImode);
4291 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4292 (clobber (match_operand:SI 0 "register_operand" "=a"))
4293 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4294 (clobber (reg:SI 26))
4295 (clobber (reg:SI 25))
4296 (clobber (reg:SI 31))]
4299 return output_mod_insn (0, insn);"
4300 [(set_attr "type" "milli")
4301 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4304 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4305 (clobber (match_operand:SI 0 "register_operand" "=a"))
4306 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4307 (clobber (reg:SI 26))
4308 (clobber (reg:SI 25))
4309 (clobber (reg:SI 2))]
4312 return output_mod_insn (0, insn);"
4313 [(set_attr "type" "milli")
4314 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4316 (define_expand "umodsi3"
4317 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4318 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4319 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4320 (clobber (match_dup 3))
4321 (clobber (match_dup 4))
4322 (clobber (reg:SI 26))
4323 (clobber (reg:SI 25))
4324 (clobber (match_dup 5))])
4325 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4331 operands[5] = gen_rtx_REG (SImode, 2);
4332 operands[4] = operands[5];
4336 operands[5] = gen_rtx_REG (SImode, 31);
4337 operands[4] = gen_reg_rtx (SImode);
4339 operands[3] = gen_reg_rtx (SImode);
4343 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4344 (clobber (match_operand:SI 0 "register_operand" "=a"))
4345 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4346 (clobber (reg:SI 26))
4347 (clobber (reg:SI 25))
4348 (clobber (reg:SI 31))]
4351 return output_mod_insn (1, insn);"
4352 [(set_attr "type" "milli")
4353 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4356 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4357 (clobber (match_operand:SI 0 "register_operand" "=a"))
4358 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4359 (clobber (reg:SI 26))
4360 (clobber (reg:SI 25))
4361 (clobber (reg:SI 2))]
4364 return output_mod_insn (1, insn);"
4365 [(set_attr "type" "milli")
4366 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4368 ;;- and instructions
4369 ;; We define DImode `and` so with DImode `not` we can get
4370 ;; DImode `andn`. Other combinations are possible.
4372 (define_expand "anddi3"
4373 [(set (match_operand:DI 0 "register_operand" "")
4374 (and:DI (match_operand:DI 1 "arith_double_operand" "")
4375 (match_operand:DI 2 "arith_double_operand" "")))]
4379 if (! register_operand (operands[1], DImode)
4380 || ! register_operand (operands[2], DImode))
4381 /* Let GCC break this into word-at-a-time operations. */
4386 [(set (match_operand:DI 0 "register_operand" "=r")
4387 (and:DI (match_operand:DI 1 "register_operand" "%r")
4388 (match_operand:DI 2 "register_operand" "r")))]
4390 "and %1,%2,%0\;and %R1,%R2,%R0"
4391 [(set_attr "type" "binary")
4392 (set_attr "length" "8")])
4395 [(set (match_operand:DI 0 "register_operand" "=r,r")
4396 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
4397 (match_operand:DI 2 "and_operand" "rO,P")))]
4399 "* return output_64bit_and (operands); "
4400 [(set_attr "type" "binary")
4401 (set_attr "length" "4")])
4403 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
4404 ; constant with ldil;ldo.
4405 (define_insn "andsi3"
4406 [(set (match_operand:SI 0 "register_operand" "=r,r")
4407 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
4408 (match_operand:SI 2 "and_operand" "rO,P")))]
4410 "* return output_and (operands); "
4411 [(set_attr "type" "binary,shift")
4412 (set_attr "length" "4,4")])
4415 [(set (match_operand:DI 0 "register_operand" "=r")
4416 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4417 (match_operand:DI 2 "register_operand" "r")))]
4419 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
4420 [(set_attr "type" "binary")
4421 (set_attr "length" "8")])
4424 [(set (match_operand:DI 0 "register_operand" "=r")
4425 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4426 (match_operand:DI 2 "register_operand" "r")))]
4429 [(set_attr "type" "binary")
4430 (set_attr "length" "4")])
4433 [(set (match_operand:SI 0 "register_operand" "=r")
4434 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4435 (match_operand:SI 2 "register_operand" "r")))]
4438 [(set_attr "type" "binary")
4439 (set_attr "length" "4")])
4441 (define_expand "iordi3"
4442 [(set (match_operand:DI 0 "register_operand" "")
4443 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
4444 (match_operand:DI 2 "arith_double_operand" "")))]
4448 if (! register_operand (operands[1], DImode)
4449 || ! register_operand (operands[2], DImode))
4450 /* Let GCC break this into word-at-a-time operations. */
4455 [(set (match_operand:DI 0 "register_operand" "=r")
4456 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4457 (match_operand:DI 2 "register_operand" "r")))]
4459 "or %1,%2,%0\;or %R1,%R2,%R0"
4460 [(set_attr "type" "binary")
4461 (set_attr "length" "8")])
4464 [(set (match_operand:DI 0 "register_operand" "=r,r")
4465 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
4466 (match_operand:DI 2 "ior_operand" "M,i")))]
4468 "* return output_64bit_ior (operands); "
4469 [(set_attr "type" "binary,shift")
4470 (set_attr "length" "4,4")])
4473 [(set (match_operand:DI 0 "register_operand" "=r")
4474 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4475 (match_operand:DI 2 "register_operand" "r")))]
4478 [(set_attr "type" "binary")
4479 (set_attr "length" "4")])
4481 ;; Need a define_expand because we've run out of CONST_OK... characters.
4482 (define_expand "iorsi3"
4483 [(set (match_operand:SI 0 "register_operand" "")
4484 (ior:SI (match_operand:SI 1 "register_operand" "")
4485 (match_operand:SI 2 "arith32_operand" "")))]
4489 if (! (ior_operand (operands[2], SImode)
4490 || register_operand (operands[2], SImode)))
4491 operands[2] = force_reg (SImode, operands[2]);
4495 [(set (match_operand:SI 0 "register_operand" "=r,r")
4496 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
4497 (match_operand:SI 2 "ior_operand" "M,i")))]
4499 "* return output_ior (operands); "
4500 [(set_attr "type" "binary,shift")
4501 (set_attr "length" "4,4")])
4504 [(set (match_operand:SI 0 "register_operand" "=r")
4505 (ior:SI (match_operand:SI 1 "register_operand" "%r")
4506 (match_operand:SI 2 "register_operand" "r")))]
4509 [(set_attr "type" "binary")
4510 (set_attr "length" "4")])
4512 (define_expand "xordi3"
4513 [(set (match_operand:DI 0 "register_operand" "")
4514 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
4515 (match_operand:DI 2 "arith_double_operand" "")))]
4519 if (! register_operand (operands[1], DImode)
4520 || ! register_operand (operands[2], DImode))
4521 /* Let GCC break this into word-at-a-time operations. */
4526 [(set (match_operand:DI 0 "register_operand" "=r")
4527 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4528 (match_operand:DI 2 "register_operand" "r")))]
4530 "xor %1,%2,%0\;xor %R1,%R2,%R0"
4531 [(set_attr "type" "binary")
4532 (set_attr "length" "8")])
4535 [(set (match_operand:DI 0 "register_operand" "=r")
4536 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4537 (match_operand:DI 2 "register_operand" "r")))]
4540 [(set_attr "type" "binary")
4541 (set_attr "length" "4")])
4543 (define_insn "xorsi3"
4544 [(set (match_operand:SI 0 "register_operand" "=r")
4545 (xor:SI (match_operand:SI 1 "register_operand" "%r")
4546 (match_operand:SI 2 "register_operand" "r")))]
4549 [(set_attr "type" "binary")
4550 (set_attr "length" "4")])
4552 (define_expand "negdi2"
4553 [(set (match_operand:DI 0 "register_operand" "")
4554 (neg:DI (match_operand:DI 1 "register_operand" "")))]
4559 [(set (match_operand:DI 0 "register_operand" "=r")
4560 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4562 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
4563 [(set_attr "type" "unary")
4564 (set_attr "length" "8")])
4567 [(set (match_operand:DI 0 "register_operand" "=r")
4568 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4571 [(set_attr "type" "unary")
4572 (set_attr "length" "4")])
4574 (define_insn "negsi2"
4575 [(set (match_operand:SI 0 "register_operand" "=r")
4576 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
4579 [(set_attr "type" "unary")
4580 (set_attr "length" "4")])
4582 (define_expand "one_cmpldi2"
4583 [(set (match_operand:DI 0 "register_operand" "")
4584 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
4588 if (! register_operand (operands[1], DImode))
4593 [(set (match_operand:DI 0 "register_operand" "=r")
4594 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4596 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
4597 [(set_attr "type" "unary")
4598 (set_attr "length" "8")])
4601 [(set (match_operand:DI 0 "register_operand" "=r")
4602 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4605 [(set_attr "type" "unary")
4606 (set_attr "length" "4")])
4608 (define_insn "one_cmplsi2"
4609 [(set (match_operand:SI 0 "register_operand" "=r")
4610 (not:SI (match_operand:SI 1 "register_operand" "r")))]
4613 [(set_attr "type" "unary")
4614 (set_attr "length" "4")])
4616 ;; Floating point arithmetic instructions.
4618 (define_insn "adddf3"
4619 [(set (match_operand:DF 0 "register_operand" "=f")
4620 (plus:DF (match_operand:DF 1 "register_operand" "f")
4621 (match_operand:DF 2 "register_operand" "f")))]
4622 "! TARGET_SOFT_FLOAT"
4624 [(set_attr "type" "fpalu")
4625 (set_attr "pa_combine_type" "faddsub")
4626 (set_attr "length" "4")])
4628 (define_insn "addsf3"
4629 [(set (match_operand:SF 0 "register_operand" "=f")
4630 (plus:SF (match_operand:SF 1 "register_operand" "f")
4631 (match_operand:SF 2 "register_operand" "f")))]
4632 "! TARGET_SOFT_FLOAT"
4634 [(set_attr "type" "fpalu")
4635 (set_attr "pa_combine_type" "faddsub")
4636 (set_attr "length" "4")])
4638 (define_insn "subdf3"
4639 [(set (match_operand:DF 0 "register_operand" "=f")
4640 (minus:DF (match_operand:DF 1 "register_operand" "f")
4641 (match_operand:DF 2 "register_operand" "f")))]
4642 "! TARGET_SOFT_FLOAT"
4644 [(set_attr "type" "fpalu")
4645 (set_attr "pa_combine_type" "faddsub")
4646 (set_attr "length" "4")])
4648 (define_insn "subsf3"
4649 [(set (match_operand:SF 0 "register_operand" "=f")
4650 (minus:SF (match_operand:SF 1 "register_operand" "f")
4651 (match_operand:SF 2 "register_operand" "f")))]
4652 "! TARGET_SOFT_FLOAT"
4654 [(set_attr "type" "fpalu")
4655 (set_attr "pa_combine_type" "faddsub")
4656 (set_attr "length" "4")])
4658 (define_insn "muldf3"
4659 [(set (match_operand:DF 0 "register_operand" "=f")
4660 (mult:DF (match_operand:DF 1 "register_operand" "f")
4661 (match_operand:DF 2 "register_operand" "f")))]
4662 "! TARGET_SOFT_FLOAT"
4664 [(set_attr "type" "fpmuldbl")
4665 (set_attr "pa_combine_type" "fmpy")
4666 (set_attr "length" "4")])
4668 (define_insn "mulsf3"
4669 [(set (match_operand:SF 0 "register_operand" "=f")
4670 (mult:SF (match_operand:SF 1 "register_operand" "f")
4671 (match_operand:SF 2 "register_operand" "f")))]
4672 "! TARGET_SOFT_FLOAT"
4674 [(set_attr "type" "fpmulsgl")
4675 (set_attr "pa_combine_type" "fmpy")
4676 (set_attr "length" "4")])
4678 (define_insn "divdf3"
4679 [(set (match_operand:DF 0 "register_operand" "=f")
4680 (div:DF (match_operand:DF 1 "register_operand" "f")
4681 (match_operand:DF 2 "register_operand" "f")))]
4682 "! TARGET_SOFT_FLOAT"
4684 [(set_attr "type" "fpdivdbl")
4685 (set_attr "length" "4")])
4687 (define_insn "divsf3"
4688 [(set (match_operand:SF 0 "register_operand" "=f")
4689 (div:SF (match_operand:SF 1 "register_operand" "f")
4690 (match_operand:SF 2 "register_operand" "f")))]
4691 "! TARGET_SOFT_FLOAT"
4693 [(set_attr "type" "fpdivsgl")
4694 (set_attr "length" "4")])
4696 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
4697 ;; negation can be done by subtracting from plus zero. However, this
4698 ;; violates the IEEE standard when negating plus and minus zero.
4699 (define_expand "negdf2"
4700 [(parallel [(set (match_operand:DF 0 "register_operand" "")
4701 (neg:DF (match_operand:DF 1 "register_operand" "")))
4702 (use (match_dup 2))])]
4703 "! TARGET_SOFT_FLOAT"
4705 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4706 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
4709 operands[2] = force_reg (DFmode,
4710 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
4711 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
4716 (define_insn "negdf2_fast"
4717 [(set (match_operand:DF 0 "register_operand" "=f")
4718 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
4719 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4723 return \"fneg,dbl %1,%0\";
4725 return \"fsub,dbl %%fr0,%1,%0\";
4727 [(set_attr "type" "fpalu")
4728 (set_attr "length" "4")])
4730 (define_expand "negsf2"
4731 [(parallel [(set (match_operand:SF 0 "register_operand" "")
4732 (neg:SF (match_operand:SF 1 "register_operand" "")))
4733 (use (match_dup 2))])]
4734 "! TARGET_SOFT_FLOAT"
4736 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4737 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
4740 operands[2] = force_reg (SFmode,
4741 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
4742 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
4747 (define_insn "negsf2_fast"
4748 [(set (match_operand:SF 0 "register_operand" "=f")
4749 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
4750 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4754 return \"fneg,sgl %1,%0\";
4756 return \"fsub,sgl %%fr0,%1,%0\";
4758 [(set_attr "type" "fpalu")
4759 (set_attr "length" "4")])
4761 (define_insn "absdf2"
4762 [(set (match_operand:DF 0 "register_operand" "=f")
4763 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
4764 "! TARGET_SOFT_FLOAT"
4766 [(set_attr "type" "fpalu")
4767 (set_attr "length" "4")])
4769 (define_insn "abssf2"
4770 [(set (match_operand:SF 0 "register_operand" "=f")
4771 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
4772 "! TARGET_SOFT_FLOAT"
4774 [(set_attr "type" "fpalu")
4775 (set_attr "length" "4")])
4777 (define_insn "sqrtdf2"
4778 [(set (match_operand:DF 0 "register_operand" "=f")
4779 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
4780 "! TARGET_SOFT_FLOAT"
4782 [(set_attr "type" "fpsqrtdbl")
4783 (set_attr "length" "4")])
4785 (define_insn "sqrtsf2"
4786 [(set (match_operand:SF 0 "register_operand" "=f")
4787 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
4788 "! TARGET_SOFT_FLOAT"
4790 [(set_attr "type" "fpsqrtsgl")
4791 (set_attr "length" "4")])
4793 ;; PA 2.0 floating point instructions
4797 [(set (match_operand:DF 0 "register_operand" "=f")
4798 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4799 (match_operand:DF 2 "register_operand" "f"))
4800 (match_operand:DF 3 "register_operand" "f")))]
4801 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4802 "fmpyfadd,dbl %1,%2,%3,%0"
4803 [(set_attr "type" "fpmuldbl")
4804 (set_attr "length" "4")])
4807 [(set (match_operand:DF 0 "register_operand" "=f")
4808 (plus:DF (match_operand:DF 1 "register_operand" "f")
4809 (mult:DF (match_operand:DF 2 "register_operand" "f")
4810 (match_operand:DF 3 "register_operand" "f"))))]
4811 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4812 "fmpyfadd,dbl %2,%3,%1,%0"
4813 [(set_attr "type" "fpmuldbl")
4814 (set_attr "length" "4")])
4817 [(set (match_operand:SF 0 "register_operand" "=f")
4818 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4819 (match_operand:SF 2 "register_operand" "f"))
4820 (match_operand:SF 3 "register_operand" "f")))]
4821 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4822 "fmpyfadd,sgl %1,%2,%3,%0"
4823 [(set_attr "type" "fpmulsgl")
4824 (set_attr "length" "4")])
4827 [(set (match_operand:SF 0 "register_operand" "=f")
4828 (plus:SF (match_operand:SF 1 "register_operand" "f")
4829 (mult:SF (match_operand:SF 2 "register_operand" "f")
4830 (match_operand:SF 3 "register_operand" "f"))))]
4831 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4832 "fmpyfadd,sgl %2,%3,%1,%0"
4833 [(set_attr "type" "fpmulsgl")
4834 (set_attr "length" "4")])
4836 ; fmpynfadd patterns
4838 [(set (match_operand:DF 0 "register_operand" "=f")
4839 (minus:DF (match_operand:DF 1 "register_operand" "f")
4840 (mult:DF (match_operand:DF 2 "register_operand" "f")
4841 (match_operand:DF 3 "register_operand" "f"))))]
4842 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4843 "fmpynfadd,dbl %2,%3,%1,%0"
4844 [(set_attr "type" "fpmuldbl")
4845 (set_attr "length" "4")])
4848 [(set (match_operand:SF 0 "register_operand" "=f")
4849 (minus:SF (match_operand:SF 1 "register_operand" "f")
4850 (mult:SF (match_operand:SF 2 "register_operand" "f")
4851 (match_operand:SF 3 "register_operand" "f"))))]
4852 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4853 "fmpynfadd,sgl %2,%3,%1,%0"
4854 [(set_attr "type" "fpmulsgl")
4855 (set_attr "length" "4")])
4859 [(set (match_operand:DF 0 "register_operand" "=f")
4860 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
4861 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4863 [(set_attr "type" "fpalu")
4864 (set_attr "length" "4")])
4867 [(set (match_operand:SF 0 "register_operand" "=f")
4868 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
4869 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4871 [(set_attr "type" "fpalu")
4872 (set_attr "length" "4")])
4874 ;; Generating a fused multiply sequence is a win for this case as it will
4875 ;; reduce the latency for the fused case without impacting the plain
4878 ;; Similar possibilities exist for fnegabs, shadd and other insns which
4879 ;; perform two operations with the result of the first feeding the second.
4881 [(set (match_operand:DF 0 "register_operand" "=f")
4882 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4883 (match_operand:DF 2 "register_operand" "f"))
4884 (match_operand:DF 3 "register_operand" "f")))
4885 (set (match_operand:DF 4 "register_operand" "=&f")
4886 (mult:DF (match_dup 1) (match_dup 2)))]
4887 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4888 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4889 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4891 [(set_attr "type" "fpmuldbl")
4892 (set_attr "length" "8")])
4894 ;; We want to split this up during scheduling since we want both insns
4895 ;; to schedule independently.
4897 [(set (match_operand:DF 0 "register_operand" "")
4898 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
4899 (match_operand:DF 2 "register_operand" ""))
4900 (match_operand:DF 3 "register_operand" "")))
4901 (set (match_operand:DF 4 "register_operand" "")
4902 (mult:DF (match_dup 1) (match_dup 2)))]
4903 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4904 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4905 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
4910 [(set (match_operand:SF 0 "register_operand" "=f")
4911 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4912 (match_operand:SF 2 "register_operand" "f"))
4913 (match_operand:SF 3 "register_operand" "f")))
4914 (set (match_operand:SF 4 "register_operand" "=&f")
4915 (mult:SF (match_dup 1) (match_dup 2)))]
4916 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4917 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4918 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4920 [(set_attr "type" "fpmuldbl")
4921 (set_attr "length" "8")])
4923 ;; We want to split this up during scheduling since we want both insns
4924 ;; to schedule independently.
4926 [(set (match_operand:SF 0 "register_operand" "")
4927 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
4928 (match_operand:SF 2 "register_operand" ""))
4929 (match_operand:SF 3 "register_operand" "")))
4930 (set (match_operand:SF 4 "register_operand" "")
4931 (mult:SF (match_dup 1) (match_dup 2)))]
4932 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4933 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4934 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
4938 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
4941 [(set (match_operand:DF 0 "register_operand" "=f")
4942 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4943 (match_operand:DF 2 "register_operand" "f"))))]
4944 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4945 "fmpynfadd,dbl %1,%2,%%fr0,%0"
4946 [(set_attr "type" "fpmuldbl")
4947 (set_attr "length" "4")])
4950 [(set (match_operand:SF 0 "register_operand" "=f")
4951 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4952 (match_operand:SF 2 "register_operand" "f"))))]
4953 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4954 "fmpynfadd,sgl %1,%2,%%fr0,%0"
4955 [(set_attr "type" "fpmuldbl")
4956 (set_attr "length" "4")])
4959 [(set (match_operand:DF 0 "register_operand" "=f")
4960 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4961 (match_operand:DF 2 "register_operand" "f"))))
4962 (set (match_operand:DF 3 "register_operand" "=&f")
4963 (mult:DF (match_dup 1) (match_dup 2)))]
4964 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4965 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4966 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4968 [(set_attr "type" "fpmuldbl")
4969 (set_attr "length" "8")])
4972 [(set (match_operand:DF 0 "register_operand" "")
4973 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
4974 (match_operand:DF 2 "register_operand" ""))))
4975 (set (match_operand:DF 3 "register_operand" "")
4976 (mult:DF (match_dup 1) (match_dup 2)))]
4977 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4978 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
4979 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
4983 [(set (match_operand:SF 0 "register_operand" "=f")
4984 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4985 (match_operand:SF 2 "register_operand" "f"))))
4986 (set (match_operand:SF 3 "register_operand" "=&f")
4987 (mult:SF (match_dup 1) (match_dup 2)))]
4988 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4989 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4990 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4992 [(set_attr "type" "fpmuldbl")
4993 (set_attr "length" "8")])
4996 [(set (match_operand:SF 0 "register_operand" "")
4997 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
4998 (match_operand:SF 2 "register_operand" ""))))
4999 (set (match_operand:SF 3 "register_operand" "")
5000 (mult:SF (match_dup 1) (match_dup 2)))]
5001 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5002 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
5003 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
5006 ;; Now fused multiplies with the result of the multiply negated.
5008 [(set (match_operand:DF 0 "register_operand" "=f")
5009 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5010 (match_operand:DF 2 "register_operand" "f")))
5011 (match_operand:DF 3 "register_operand" "f")))]
5012 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5013 "fmpynfadd,dbl %1,%2,%3,%0"
5014 [(set_attr "type" "fpmuldbl")
5015 (set_attr "length" "4")])
5018 [(set (match_operand:SF 0 "register_operand" "=f")
5019 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5020 (match_operand:SF 2 "register_operand" "f")))
5021 (match_operand:SF 3 "register_operand" "f")))]
5022 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5023 "fmpynfadd,sgl %1,%2,%3,%0"
5024 [(set_attr "type" "fpmuldbl")
5025 (set_attr "length" "4")])
5028 [(set (match_operand:DF 0 "register_operand" "=f")
5029 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5030 (match_operand:DF 2 "register_operand" "f")))
5031 (match_operand:DF 3 "register_operand" "f")))
5032 (set (match_operand:DF 4 "register_operand" "=&f")
5033 (mult:DF (match_dup 1) (match_dup 2)))]
5034 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5035 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5036 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5038 [(set_attr "type" "fpmuldbl")
5039 (set_attr "length" "8")])
5042 [(set (match_operand:DF 0 "register_operand" "")
5043 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5044 (match_operand:DF 2 "register_operand" "")))
5045 (match_operand:DF 3 "register_operand" "")))
5046 (set (match_operand:DF 4 "register_operand" "")
5047 (mult:DF (match_dup 1) (match_dup 2)))]
5048 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5049 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5050 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
5055 [(set (match_operand:SF 0 "register_operand" "=f")
5056 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5057 (match_operand:SF 2 "register_operand" "f")))
5058 (match_operand:SF 3 "register_operand" "f")))
5059 (set (match_operand:SF 4 "register_operand" "=&f")
5060 (mult:SF (match_dup 1) (match_dup 2)))]
5061 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5062 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5063 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5065 [(set_attr "type" "fpmuldbl")
5066 (set_attr "length" "8")])
5069 [(set (match_operand:SF 0 "register_operand" "")
5070 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5071 (match_operand:SF 2 "register_operand" "")))
5072 (match_operand:SF 3 "register_operand" "")))
5073 (set (match_operand:SF 4 "register_operand" "")
5074 (mult:SF (match_dup 1) (match_dup 2)))]
5075 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5076 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5077 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
5082 [(set (match_operand:DF 0 "register_operand" "=f")
5083 (minus:DF (match_operand:DF 3 "register_operand" "f")
5084 (mult:DF (match_operand:DF 1 "register_operand" "f")
5085 (match_operand:DF 2 "register_operand" "f"))))
5086 (set (match_operand:DF 4 "register_operand" "=&f")
5087 (mult:DF (match_dup 1) (match_dup 2)))]
5088 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5089 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5090 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5092 [(set_attr "type" "fpmuldbl")
5093 (set_attr "length" "8")])
5096 [(set (match_operand:DF 0 "register_operand" "")
5097 (minus:DF (match_operand:DF 3 "register_operand" "")
5098 (mult:DF (match_operand:DF 1 "register_operand" "")
5099 (match_operand:DF 2 "register_operand" ""))))
5100 (set (match_operand:DF 4 "register_operand" "")
5101 (mult:DF (match_dup 1) (match_dup 2)))]
5102 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5103 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5104 (set (match_dup 0) (minus:DF (match_dup 3)
5105 (mult:DF (match_dup 1) (match_dup 2))))]
5109 [(set (match_operand:SF 0 "register_operand" "=f")
5110 (minus:SF (match_operand:SF 3 "register_operand" "f")
5111 (mult:SF (match_operand:SF 1 "register_operand" "f")
5112 (match_operand:SF 2 "register_operand" "f"))))
5113 (set (match_operand:SF 4 "register_operand" "=&f")
5114 (mult:SF (match_dup 1) (match_dup 2)))]
5115 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5116 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5117 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5119 [(set_attr "type" "fpmuldbl")
5120 (set_attr "length" "8")])
5123 [(set (match_operand:SF 0 "register_operand" "")
5124 (minus:SF (match_operand:SF 3 "register_operand" "")
5125 (mult:SF (match_operand:SF 1 "register_operand" "")
5126 (match_operand:SF 2 "register_operand" ""))))
5127 (set (match_operand:SF 4 "register_operand" "")
5128 (mult:SF (match_dup 1) (match_dup 2)))]
5129 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5130 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5131 (set (match_dup 0) (minus:SF (match_dup 3)
5132 (mult:SF (match_dup 1) (match_dup 2))))]
5136 [(set (match_operand:DF 0 "register_operand" "=f")
5137 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
5138 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
5139 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5140 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5142 [(set_attr "type" "fpalu")
5143 (set_attr "length" "8")])
5146 [(set (match_operand:DF 0 "register_operand" "")
5147 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
5148 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
5149 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5150 [(set (match_dup 2) (abs:DF (match_dup 1)))
5151 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
5155 [(set (match_operand:SF 0 "register_operand" "=f")
5156 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
5157 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
5158 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5159 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5161 [(set_attr "type" "fpalu")
5162 (set_attr "length" "8")])
5165 [(set (match_operand:SF 0 "register_operand" "")
5166 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
5167 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
5168 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5169 [(set (match_dup 2) (abs:SF (match_dup 1)))
5170 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
5173 ;;- Shift instructions
5175 ;; Optimized special case of shifting.
5178 [(set (match_operand:SI 0 "register_operand" "=r")
5179 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5183 [(set_attr "type" "load")
5184 (set_attr "length" "4")])
5187 [(set (match_operand:SI 0 "register_operand" "=r")
5188 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5192 [(set_attr "type" "load")
5193 (set_attr "length" "4")])
5196 [(set (match_operand:SI 0 "register_operand" "=r")
5197 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
5198 (match_operand:SI 3 "shadd_operand" ""))
5199 (match_operand:SI 1 "register_operand" "r")))]
5201 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
5202 [(set_attr "type" "binary")
5203 (set_attr "length" "4")])
5206 [(set (match_operand:DI 0 "register_operand" "=r")
5207 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
5208 (match_operand:DI 3 "shadd_operand" ""))
5209 (match_operand:DI 1 "register_operand" "r")))]
5211 "shladd,l %2,%O3,%1,%0"
5212 [(set_attr "type" "binary")
5213 (set_attr "length" "4")])
5215 (define_expand "ashlsi3"
5216 [(set (match_operand:SI 0 "register_operand" "")
5217 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
5218 (match_operand:SI 2 "arith32_operand" "")))]
5222 if (GET_CODE (operands[2]) != CONST_INT)
5224 rtx temp = gen_reg_rtx (SImode);
5225 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5226 if (GET_CODE (operands[1]) == CONST_INT)
5227 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
5229 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
5232 /* Make sure both inputs are not constants,
5233 there are no patterns for that. */
5234 operands[1] = force_reg (SImode, operands[1]);
5238 [(set (match_operand:SI 0 "register_operand" "=r")
5239 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5240 (match_operand:SI 2 "const_int_operand" "n")))]
5242 "{zdep|depw,z} %1,%P2,%L2,%0"
5243 [(set_attr "type" "shift")
5244 (set_attr "length" "4")])
5246 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
5247 ; Doing it like this makes slightly better code since reload can
5248 ; replace a register with a known value in range -16..15 with a
5249 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
5250 ; but since we have no more CONST_OK... characters, that is not
5252 (define_insn "zvdep32"
5253 [(set (match_operand:SI 0 "register_operand" "=r,r")
5254 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
5255 (minus:SI (const_int 31)
5256 (match_operand:SI 2 "register_operand" "q,q"))))]
5259 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
5260 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
5261 [(set_attr "type" "shift,shift")
5262 (set_attr "length" "4,4")])
5264 (define_insn "zvdep_imm32"
5265 [(set (match_operand:SI 0 "register_operand" "=r")
5266 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
5267 (minus:SI (const_int 31)
5268 (match_operand:SI 2 "register_operand" "q"))))]
5272 int x = INTVAL (operands[1]);
5273 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5274 operands[1] = GEN_INT ((x & 0xf) - 0x10);
5275 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
5277 [(set_attr "type" "shift")
5278 (set_attr "length" "4")])
5280 (define_insn "vdepi_ior"
5281 [(set (match_operand:SI 0 "register_operand" "=r")
5282 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
5283 (minus:SI (const_int 31)
5284 (match_operand:SI 2 "register_operand" "q")))
5285 (match_operand:SI 3 "register_operand" "0")))]
5286 ; accept ...0001...1, can this be generalized?
5287 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5290 int x = INTVAL (operands[1]);
5291 operands[2] = GEN_INT (exact_log2 (x + 1));
5292 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
5294 [(set_attr "type" "shift")
5295 (set_attr "length" "4")])
5297 (define_insn "vdepi_and"
5298 [(set (match_operand:SI 0 "register_operand" "=r")
5299 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
5300 (minus:SI (const_int 31)
5301 (match_operand:SI 2 "register_operand" "q")))
5302 (match_operand:SI 3 "register_operand" "0")))]
5303 ; this can be generalized...!
5304 "INTVAL (operands[1]) == -2"
5307 int x = INTVAL (operands[1]);
5308 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5309 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
5311 [(set_attr "type" "shift")
5312 (set_attr "length" "4")])
5314 (define_expand "ashldi3"
5315 [(set (match_operand:DI 0 "register_operand" "")
5316 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
5317 (match_operand:DI 2 "arith32_operand" "")))]
5321 if (GET_CODE (operands[2]) != CONST_INT)
5323 rtx temp = gen_reg_rtx (DImode);
5324 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5325 if (GET_CODE (operands[1]) == CONST_INT)
5326 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
5328 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
5331 /* Make sure both inputs are not constants,
5332 there are no patterns for that. */
5333 operands[1] = force_reg (DImode, operands[1]);
5337 [(set (match_operand:DI 0 "register_operand" "=r")
5338 (ashift:DI (match_operand:DI 1 "register_operand" "r")
5339 (match_operand:DI 2 "const_int_operand" "n")))]
5341 "depd,z %1,%p2,%Q2,%0"
5342 [(set_attr "type" "shift")
5343 (set_attr "length" "4")])
5345 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
5346 ; Doing it like this makes slightly better code since reload can
5347 ; replace a register with a known value in range -16..15 with a
5348 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
5349 ; but since we have no more CONST_OK... characters, that is not
5351 (define_insn "zvdep64"
5352 [(set (match_operand:DI 0 "register_operand" "=r,r")
5353 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
5354 (minus:DI (const_int 63)
5355 (match_operand:DI 2 "register_operand" "q,q"))))]
5358 depd,z %1,%%sar,64,%0
5359 depdi,z %1,%%sar,64,%0"
5360 [(set_attr "type" "shift,shift")
5361 (set_attr "length" "4,4")])
5363 (define_insn "zvdep_imm64"
5364 [(set (match_operand:DI 0 "register_operand" "=r")
5365 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
5366 (minus:DI (const_int 63)
5367 (match_operand:DI 2 "register_operand" "q"))))]
5371 int x = INTVAL (operands[1]);
5372 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5373 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
5374 return \"depdi,z %1,%%sar,%2,%0\";
5376 [(set_attr "type" "shift")
5377 (set_attr "length" "4")])
5380 [(set (match_operand:DI 0 "register_operand" "=r")
5381 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
5382 (minus:DI (const_int 63)
5383 (match_operand:DI 2 "register_operand" "q")))
5384 (match_operand:DI 3 "register_operand" "0")))]
5385 ; accept ...0001...1, can this be generalized?
5386 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5389 int x = INTVAL (operands[1]);
5390 operands[2] = GEN_INT (exact_log2 (x + 1));
5391 return \"depdi -1,%%sar,%2,%0\";
5393 [(set_attr "type" "shift")
5394 (set_attr "length" "4")])
5397 [(set (match_operand:DI 0 "register_operand" "=r")
5398 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
5399 (minus:DI (const_int 63)
5400 (match_operand:DI 2 "register_operand" "q")))
5401 (match_operand:DI 3 "register_operand" "0")))]
5402 ; this can be generalized...!
5403 "TARGET_64BIT && INTVAL (operands[1]) == -2"
5406 int x = INTVAL (operands[1]);
5407 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5408 return \"depdi 0,%%sar,%2,%0\";
5410 [(set_attr "type" "shift")
5411 (set_attr "length" "4")])
5413 (define_expand "ashrsi3"
5414 [(set (match_operand:SI 0 "register_operand" "")
5415 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
5416 (match_operand:SI 2 "arith32_operand" "")))]
5420 if (GET_CODE (operands[2]) != CONST_INT)
5422 rtx temp = gen_reg_rtx (SImode);
5423 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5424 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
5430 [(set (match_operand:SI 0 "register_operand" "=r")
5431 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5432 (match_operand:SI 2 "const_int_operand" "n")))]
5434 "{extrs|extrw,s} %1,%P2,%L2,%0"
5435 [(set_attr "type" "shift")
5436 (set_attr "length" "4")])
5438 (define_insn "vextrs32"
5439 [(set (match_operand:SI 0 "register_operand" "=r")
5440 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5441 (minus:SI (const_int 31)
5442 (match_operand:SI 2 "register_operand" "q"))))]
5444 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
5445 [(set_attr "type" "shift")
5446 (set_attr "length" "4")])
5448 (define_expand "ashrdi3"
5449 [(set (match_operand:DI 0 "register_operand" "")
5450 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5451 (match_operand:DI 2 "arith32_operand" "")))]
5455 if (GET_CODE (operands[2]) != CONST_INT)
5457 rtx temp = gen_reg_rtx (DImode);
5458 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5459 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
5465 [(set (match_operand:DI 0 "register_operand" "=r")
5466 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5467 (match_operand:DI 2 "const_int_operand" "n")))]
5469 "extrd,s %1,%p2,%Q2,%0"
5470 [(set_attr "type" "shift")
5471 (set_attr "length" "4")])
5473 (define_insn "vextrs64"
5474 [(set (match_operand:DI 0 "register_operand" "=r")
5475 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5476 (minus:DI (const_int 63)
5477 (match_operand:DI 2 "register_operand" "q"))))]
5479 "extrd,s %1,%%sar,64,%0"
5480 [(set_attr "type" "shift")
5481 (set_attr "length" "4")])
5483 (define_insn "lshrsi3"
5484 [(set (match_operand:SI 0 "register_operand" "=r,r")
5485 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
5486 (match_operand:SI 2 "arith32_operand" "q,n")))]
5489 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
5490 {extru|extrw,u} %1,%P2,%L2,%0"
5491 [(set_attr "type" "shift")
5492 (set_attr "length" "4")])
5494 (define_insn "lshrdi3"
5495 [(set (match_operand:DI 0 "register_operand" "=r,r")
5496 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
5497 (match_operand:DI 2 "arith32_operand" "q,n")))]
5500 shrpd %%r0,%1,%%sar,%0
5501 extrd,u %1,%p2,%Q2,%0"
5502 [(set_attr "type" "shift")
5503 (set_attr "length" "4")])
5505 (define_insn "rotrsi3"
5506 [(set (match_operand:SI 0 "register_operand" "=r,r")
5507 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
5508 (match_operand:SI 2 "arith32_operand" "q,n")))]
5512 if (GET_CODE (operands[2]) == CONST_INT)
5514 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
5515 return \"{shd|shrpw} %1,%1,%2,%0\";
5518 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
5520 [(set_attr "type" "shift")
5521 (set_attr "length" "4")])
5523 (define_expand "rotlsi3"
5524 [(set (match_operand:SI 0 "register_operand" "")
5525 (rotate:SI (match_operand:SI 1 "register_operand" "")
5526 (match_operand:SI 2 "arith32_operand" "")))]
5530 if (GET_CODE (operands[2]) != CONST_INT)
5532 rtx temp = gen_reg_rtx (SImode);
5533 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
5534 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
5537 /* Else expand normally. */
5541 [(set (match_operand:SI 0 "register_operand" "=r")
5542 (rotate:SI (match_operand:SI 1 "register_operand" "r")
5543 (match_operand:SI 2 "const_int_operand" "n")))]
5547 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
5548 return \"{shd|shrpw} %1,%1,%2,%0\";
5550 [(set_attr "type" "shift")
5551 (set_attr "length" "4")])
5554 [(set (match_operand:SI 0 "register_operand" "=r")
5555 (match_operator:SI 5 "plus_xor_ior_operator"
5556 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
5557 (match_operand:SI 3 "const_int_operand" "n"))
5558 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5559 (match_operand:SI 4 "const_int_operand" "n"))]))]
5560 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5561 "{shd|shrpw} %1,%2,%4,%0"
5562 [(set_attr "type" "shift")
5563 (set_attr "length" "4")])
5566 [(set (match_operand:SI 0 "register_operand" "=r")
5567 (match_operator:SI 5 "plus_xor_ior_operator"
5568 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5569 (match_operand:SI 4 "const_int_operand" "n"))
5570 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5571 (match_operand:SI 3 "const_int_operand" "n"))]))]
5572 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5573 "{shd|shrpw} %1,%2,%4,%0"
5574 [(set_attr "type" "shift")
5575 (set_attr "length" "4")])
5578 [(set (match_operand:SI 0 "register_operand" "=r")
5579 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
5580 (match_operand:SI 2 "const_int_operand" ""))
5581 (match_operand:SI 3 "const_int_operand" "")))]
5582 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
5585 int cnt = INTVAL (operands[2]) & 31;
5586 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
5587 operands[2] = GEN_INT (31 - cnt);
5588 return \"{zdep|depw,z} %1,%2,%3,%0\";
5590 [(set_attr "type" "shift")
5591 (set_attr "length" "4")])
5593 ;; Unconditional and other jump instructions.
5595 ;; This can only be used in a leaf function, so we do
5596 ;; not need to use the PIC register when generating PIC code.
5597 (define_insn "return"
5601 "hppa_can_use_return_insn_p ()"
5605 return \"bve%* (%%r2)\";
5606 return \"bv%* %%r0(%%r2)\";
5608 [(set_attr "type" "branch")
5609 (set_attr "length" "4")])
5611 ;; Emit a different pattern for functions which have non-trivial
5612 ;; epilogues so as not to confuse jump and reorg.
5613 (define_insn "return_internal"
5621 return \"bve%* (%%r2)\";
5622 return \"bv%* %%r0(%%r2)\";
5624 [(set_attr "type" "branch")
5625 (set_attr "length" "4")])
5627 ;; This is used for eh returns which bypass the return stub.
5628 (define_insn "return_external_pic"
5630 (clobber (reg:SI 1))
5632 "!TARGET_NO_SPACE_REGS && flag_pic && current_function_calls_eh_return"
5633 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
5634 [(set_attr "type" "branch")
5635 (set_attr "length" "12")])
5637 (define_expand "prologue"
5640 "hppa_expand_prologue ();DONE;")
5642 (define_expand "sibcall_epilogue"
5647 hppa_expand_epilogue ();
5651 (define_expand "epilogue"
5656 /* Try to use the trivial return first. Else use the full
5658 if (hppa_can_use_return_insn_p ())
5659 emit_jump_insn (gen_return ());
5664 hppa_expand_epilogue ();
5666 /* EH returns bypass the normal return stub. Thus, we must do an
5667 interspace branch to return from functions that call eh_return.
5668 This is only a problem for returns from shared code on ports
5669 using space registers. */
5670 if (!TARGET_NO_SPACE_REGS
5671 && flag_pic && current_function_calls_eh_return)
5672 x = gen_return_external_pic ();
5674 x = gen_return_internal ();
5681 ;; Special because we use the value placed in %r2 by the bl instruction
5682 ;; from within its delay slot to set the value for the 2nd parameter to
5684 (define_insn "call_profiler"
5685 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5686 (match_operand 1 "" ""))
5687 (use (match_operand 2 "" ""))
5690 (clobber (reg:SI 2))]
5696 output_arg_descriptor (insn);
5698 xoperands[0] = operands[0];
5699 xoperands[1] = operands[2];
5700 xoperands[2] = gen_label_rtx ();
5701 output_asm_insn (\"{bl|b,l} %0,%%r2\;ldo %1-%2(%%r2),%%r25\", xoperands);
5703 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5704 CODE_LABEL_NUMBER (xoperands[2]));
5707 [(set_attr "type" "multi")
5708 (set_attr "length" "8")])
5710 (define_insn "blockage"
5711 [(unspec_volatile [(const_int 2)] 0)]
5714 [(set_attr "length" "0")])
5717 [(set (pc) (label_ref (match_operand 0 "" "")))]
5721 extern int optimize;
5723 if (GET_MODE (insn) == SImode)
5726 /* An unconditional branch which can reach its target. */
5727 if (get_attr_length (insn) != 24
5728 && get_attr_length (insn) != 16)
5731 /* An unconditional branch which can not reach its target.
5733 We need to be able to use %r1 as a scratch register; however,
5734 we can never be sure whether or not it's got a live value in
5735 it. Therefore, we must restore its original value after the
5738 To make matters worse, we don't have a stack slot which we
5739 can always clobber. sp-12/sp-16 shouldn't ever have a live
5740 value during a non-optimizing compilation, so we use those
5741 slots for now. We don't support very long branches when
5742 optimizing -- they should be quite rare when optimizing.
5744 Really the way to go long term is a register scavenger; goto
5745 the target of the jump and find a register which we can use
5746 as a scratch to hold the value in %r1. */
5748 /* We don't know how to register scavenge yet. */
5752 /* First store %r1 into the stack. */
5753 output_asm_insn (\"stw %%r1,-16(%%r30)\", operands);
5755 /* Now load the target address into %r1 and do an indirect jump
5756 to the value specified in %r1. Be careful to generate PIC
5761 xoperands[0] = operands[0];
5762 if (TARGET_SOM || ! TARGET_GAS)
5764 xoperands[1] = gen_label_rtx ();
5766 output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\",
5768 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5769 CODE_LABEL_NUMBER (xoperands[1]));
5770 output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\", xoperands);
5774 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
5775 output_asm_insn (\"addil L'%l0-$PIC_pcrel$0+4,%%r1\", xoperands);
5776 output_asm_insn (\"ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1\", xoperands);
5778 output_asm_insn (\"bv %%r0(%%r1)\", xoperands);
5781 output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);;
5783 /* And restore the value of %r1 in the delay slot. We're not optimizing,
5784 so we know nothing else can be in the delay slot. */
5785 return \"ldw -16(%%r30),%%r1\";
5787 [(set_attr "type" "uncond_branch")
5788 (set_attr "pa_combine_type" "uncond_branch")
5789 (set (attr "length")
5790 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
5791 (if_then_else (lt (abs (minus (match_dup 0)
5792 (plus (pc) (const_int 8))))
5796 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
5798 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5803 ;; Subroutines of "casesi".
5804 ;; operand 0 is index
5805 ;; operand 1 is the minimum bound
5806 ;; operand 2 is the maximum bound - minimum bound + 1
5807 ;; operand 3 is CODE_LABEL for the table;
5808 ;; operand 4 is the CODE_LABEL to go to if index out of range.
5810 (define_expand "casesi"
5811 [(match_operand:SI 0 "general_operand" "")
5812 (match_operand:SI 1 "const_int_operand" "")
5813 (match_operand:SI 2 "const_int_operand" "")
5814 (match_operand 3 "" "")
5815 (match_operand 4 "" "")]
5819 if (GET_CODE (operands[0]) != REG)
5820 operands[0] = force_reg (SImode, operands[0]);
5822 if (operands[1] != const0_rtx)
5824 rtx reg = gen_reg_rtx (SImode);
5826 operands[1] = GEN_INT (-INTVAL (operands[1]));
5827 if (!INT_14_BITS (operands[1]))
5828 operands[1] = force_reg (SImode, operands[1]);
5829 emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
5834 /* In 64bit mode we must make sure to wipe the upper bits of the register
5835 just in case the addition overflowed or we had random bits in the
5836 high part of the register. */
5839 rtx reg = gen_reg_rtx (DImode);
5840 emit_insn (gen_extendsidi2 (reg, operands[0]));
5841 operands[0] = gen_rtx_SUBREG (SImode, reg, 4);
5844 if (!INT_5_BITS (operands[2]))
5845 operands[2] = force_reg (SImode, operands[2]);
5847 emit_insn (gen_cmpsi (operands[0], operands[2]));
5848 emit_jump_insn (gen_bgtu (operands[4]));
5849 if (TARGET_BIG_SWITCH)
5851 rtx temp = gen_reg_rtx (SImode);
5852 emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
5855 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
5859 (define_insn "casesi0"
5861 (mem:SI (plus:SI (pc)
5862 (match_operand:SI 0 "register_operand" "r")))
5863 (label_ref (match_operand 1 "" ""))))]
5866 [(set_attr "type" "multi")
5867 (set_attr "length" "8")])
5869 ;; Need nops for the calls because execution is supposed to continue
5870 ;; past; we don't want to nullify an instruction that we need.
5871 ;;- jump to subroutine
5873 (define_expand "call"
5874 [(parallel [(call (match_operand:SI 0 "" "")
5875 (match_operand 1 "" ""))
5876 (clobber (reg:SI 2))])]
5881 rtx nb = operands[1];
5883 if (TARGET_PORTABLE_RUNTIME)
5884 op = force_reg (SImode, XEXP (operands[0], 0));
5886 op = XEXP (operands[0], 0);
5889 emit_move_insn (arg_pointer_rtx,
5890 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5893 /* Use two different patterns for calls to explicitly named functions
5894 and calls through function pointers. This is necessary as these two
5895 types of calls use different calling conventions, and CSE might try
5896 to change the named call into an indirect call in some cases (using
5897 two patterns keeps CSE from performing this optimization).
5899 We now use even more call patterns as there was a subtle bug in
5900 attempting to restore the pic register after a call using a simple
5901 move insn. During reload, a instruction involving a pseudo register
5902 with no explicit dependence on the PIC register can be converted
5903 to an equivalent load from memory using the PIC register. If we
5904 emit a simple move to restore the PIC register in the initial rtl
5905 generation, then it can potentially be repositioned during scheduling.
5906 and an instruction that eventually uses the PIC register may end up
5907 between the call and the PIC register restore.
5909 This only worked because there is a post call group of instructions
5910 that are scheduled with the call. These instructions are included
5911 in the same basic block as the call. However, calls can throw in
5912 C++ code and a basic block has to terminate at the call if the call
5913 can throw. This results in the PIC register restore being scheduled
5914 independently from the call. So, we now hide the save and restore
5915 of the PIC register in the call pattern until after reload. Then,
5916 we split the moves out. A small side benefit is that we now don't
5917 need to have a use of the PIC register in the return pattern and
5918 the final save/restore operation is not needed.
5920 I elected to just clobber %r4 in the PIC patterns and use it instead
5921 of trying to force hppa_pic_save_rtx () to a callee saved register.
5922 This might have required a new register class and constraint. It
5923 was also simpler to just handle the restore from a register than a
5927 if (GET_CODE (op) == SYMBOL_REF)
5928 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
5931 op = force_reg (word_mode, op);
5932 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
5937 if (GET_CODE (op) == SYMBOL_REF)
5940 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
5942 call_insn = emit_call_insn (gen_call_symref (op, nb));
5946 rtx tmpreg = gen_rtx_REG (word_mode, 22);
5948 emit_move_insn (tmpreg, force_reg (word_mode, op));
5950 call_insn = emit_call_insn (gen_call_reg_pic (nb));
5952 call_insn = emit_call_insn (gen_call_reg (nb));
5959 ;; We use function calls to set the attribute length of calls and millicode
5960 ;; calls. This is necessary because of the large variety of call sequences.
5961 ;; Implementing the calculation in rtl is difficult as well as ugly. As
5962 ;; we need the same calculation in several places, maintenance becomes a
5965 ;; However, this has a subtle impact on branch shortening. When the
5966 ;; expression used to set the length attribute of an instruction depends
5967 ;; on a relative address (e.g., pc or a branch address), genattrtab
5968 ;; notes that the insn's length is variable, and attempts to determine a
5969 ;; worst-case default length and code to compute an insn's current length.
5971 ;; The use of a function call hides the variable dependence of our calls
5972 ;; and millicode calls. The result is genattrtab doesn't treat the operation
5973 ;; as variable and it only generates code for the default case using our
5974 ;; function call. Because of this, calls and millicode calls have a fixed
5975 ;; length in the branch shortening pass, and some branches will use a longer
5976 ;; code sequence than necessary. However, the length of any given call
5977 ;; will still reflect its final code location and it may be shorter than
5978 ;; the initial length estimate.
5980 ;; It's possible to trick genattrtab by adding an expression involving `pc'
5981 ;; in the set. However, when genattrtab hits a function call in its attempt
5982 ;; to compute the default length, it marks the result as unknown and sets
5983 ;; the default result to MAX_INT ;-( One possible fix that would allow
5984 ;; calls to participate in branch shortening would be to make the call to
5985 ;; insn_default_length a target option. Then, we could massage unknown
5986 ;; results. Another fix might be to change genattrtab so that it just does
5987 ;; the call in the variable case as it already does for the fixed case.
5989 (define_insn "call_symref"
5990 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5991 (match_operand 1 "" "i"))
5992 (clobber (reg:SI 1))
5993 (clobber (reg:SI 2))
5994 (use (const_int 0))]
5995 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
5998 output_arg_descriptor (insn);
5999 return output_call (insn, operands[0], 0);
6001 [(set_attr "type" "call")
6002 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6004 (define_insn "call_symref_pic"
6005 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6006 (match_operand 1 "" "i"))
6007 (clobber (reg:SI 1))
6008 (clobber (reg:SI 2))
6009 (clobber (reg:SI 4))
6011 (use (const_int 0))]
6012 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6015 output_arg_descriptor (insn);
6016 return output_call (insn, operands[0], 0);
6018 [(set_attr "type" "call")
6019 (set (attr "length")
6020 (plus (symbol_ref "attr_length_call (insn, 0)")
6021 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6023 ;; Split out the PIC register save and restore after reload. This is
6024 ;; done if the function doesn't return.
6026 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6027 (match_operand 1 "" ""))
6028 (clobber (reg:SI 1))
6029 (clobber (reg:SI 2))
6030 (clobber (reg:SI 4))
6032 (use (const_int 0))])]
6033 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
6035 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6036 [(set (reg:SI 4) (reg:SI 19))
6037 (parallel [(call (mem:SI (match_dup 0))
6039 (clobber (reg:SI 1))
6040 (clobber (reg:SI 2))
6042 (use (const_int 0))])
6043 (set (reg:SI 19) (reg:SI 4))]
6046 ;; Remove the clobber of register 4 when optimizing. This has to be
6047 ;; done with a peephole optimization rather than a split because the
6048 ;; split sequence for a call must be longer than one instruction.
6050 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6051 (match_operand 1 "" ""))
6052 (clobber (reg:SI 1))
6053 (clobber (reg:SI 2))
6054 (clobber (reg:SI 4))
6056 (use (const_int 0))])]
6057 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
6058 [(parallel [(call (mem:SI (match_dup 0))
6060 (clobber (reg:SI 1))
6061 (clobber (reg:SI 2))
6063 (use (const_int 0))])]
6066 (define_insn "*call_symref_pic_post_reload"
6067 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6068 (match_operand 1 "" "i"))
6069 (clobber (reg:SI 1))
6070 (clobber (reg:SI 2))
6072 (use (const_int 0))]
6073 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6076 output_arg_descriptor (insn);
6077 return output_call (insn, operands[0], 0);
6079 [(set_attr "type" "call")
6080 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6082 ;; This pattern is split if it is necessary to save and restore the
6084 (define_insn "call_symref_64bit"
6085 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6086 (match_operand 1 "" "i"))
6087 (clobber (reg:DI 1))
6088 (clobber (reg:DI 2))
6089 (clobber (reg:DI 4))
6092 (use (const_int 0))]
6096 output_arg_descriptor (insn);
6097 return output_call (insn, operands[0], 0);
6099 [(set_attr "type" "call")
6100 (set (attr "length")
6101 (plus (symbol_ref "attr_length_call (insn, 0)")
6102 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6104 ;; Split out the PIC register save and restore after reload. This is
6105 ;; done if the function doesn't return.
6107 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6108 (match_operand 1 "" ""))
6109 (clobber (reg:DI 1))
6110 (clobber (reg:DI 2))
6111 (clobber (reg:DI 4))
6114 (use (const_int 0))])]
6117 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6118 [(set (reg:DI 4) (reg:DI 27))
6119 (parallel [(call (mem:SI (match_dup 0))
6121 (clobber (reg:DI 1))
6122 (clobber (reg:DI 2))
6125 (use (const_int 0))])
6126 (set (reg:DI 27) (reg:DI 4))]
6129 ;; Remove the clobber of register 4 when optimizing. This has to be
6130 ;; done with a peephole optimization rather than a split because the
6131 ;; split sequence for a call must be longer than one instruction.
6133 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6134 (match_operand 1 "" ""))
6135 (clobber (reg:DI 1))
6136 (clobber (reg:DI 2))
6137 (clobber (reg:DI 4))
6140 (use (const_int 0))])]
6141 "TARGET_64BIT && reload_completed"
6142 [(parallel [(call (mem:SI (match_dup 0))
6144 (clobber (reg:DI 1))
6145 (clobber (reg:DI 2))
6148 (use (const_int 0))])]
6151 (define_insn "*call_symref_64bit_post_reload"
6152 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6153 (match_operand 1 "" "i"))
6154 (clobber (reg:DI 1))
6155 (clobber (reg:DI 2))
6158 (use (const_int 0))]
6162 output_arg_descriptor (insn);
6163 return output_call (insn, operands[0], 0);
6165 [(set_attr "type" "call")
6166 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6168 (define_insn "call_reg"
6169 [(call (mem:SI (reg:SI 22))
6170 (match_operand 0 "" "i"))
6171 (clobber (reg:SI 1))
6172 (clobber (reg:SI 2))
6173 (use (const_int 1))]
6177 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6179 [(set_attr "type" "dyncall")
6180 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6182 ;; This pattern is split if it is necessary to save and restore the
6184 (define_insn "call_reg_pic"
6185 [(call (mem:SI (reg:SI 22))
6186 (match_operand 0 "" "i"))
6187 (clobber (reg:SI 1))
6188 (clobber (reg:SI 2))
6189 (clobber (reg:SI 4))
6191 (use (const_int 1))]
6195 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6197 [(set_attr "type" "dyncall")
6198 (set (attr "length")
6199 (plus (symbol_ref "attr_length_indirect_call (insn)")
6200 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6202 ;; Split out the PIC register save and restore after reload. This is
6203 ;; done if the function doesn't return.
6205 [(parallel [(call (mem:SI (reg:SI 22))
6206 (match_operand 0 "" ""))
6207 (clobber (reg:SI 1))
6208 (clobber (reg:SI 2))
6209 (clobber (reg:SI 4))
6211 (use (const_int 1))])]
6214 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6215 [(set (reg:SI 4) (reg:SI 19))
6216 (parallel [(call (mem:SI (reg:SI 22))
6218 (clobber (reg:SI 1))
6219 (clobber (reg:SI 2))
6221 (use (const_int 1))])
6222 (set (reg:SI 19) (reg:SI 4))]
6225 ;; Remove the clobber of register 4 when optimizing. This has to be
6226 ;; done with a peephole optimization rather than a split because the
6227 ;; split sequence for a call must be longer than one instruction.
6229 [(parallel [(call (mem:SI (reg:SI 22))
6230 (match_operand 0 "" ""))
6231 (clobber (reg:SI 1))
6232 (clobber (reg:SI 2))
6233 (clobber (reg:SI 4))
6235 (use (const_int 1))])]
6236 "!TARGET_64BIT && reload_completed"
6237 [(parallel [(call (mem:SI (reg:SI 22))
6239 (clobber (reg:SI 1))
6240 (clobber (reg:SI 2))
6242 (use (const_int 1))])]
6245 (define_insn "*call_reg_pic_post_reload"
6246 [(call (mem:SI (reg:SI 22))
6247 (match_operand 0 "" "i"))
6248 (clobber (reg:SI 1))
6249 (clobber (reg:SI 2))
6251 (use (const_int 1))]
6255 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6257 [(set_attr "type" "dyncall")
6258 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6260 ;; This pattern is split if it is necessary to save and restore the
6262 (define_insn "call_reg_64bit"
6263 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
6264 (match_operand 1 "" "i"))
6265 (clobber (reg:DI 2))
6266 (clobber (reg:DI 4))
6269 (use (const_int 1))]
6273 return output_indirect_call (insn, operands[0]);
6275 [(set_attr "type" "dyncall")
6276 (set (attr "length")
6277 (plus (symbol_ref "attr_length_indirect_call (insn)")
6278 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6280 ;; Split out the PIC register save and restore after reload. This is
6281 ;; done if the function doesn't return.
6283 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
6284 (match_operand 1 "" ""))
6285 (clobber (reg:DI 2))
6286 (clobber (reg:DI 4))
6289 (use (const_int 1))])]
6292 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6293 [(set (reg:DI 4) (reg:DI 27))
6294 (parallel [(call (mem:SI (match_dup 0))
6296 (clobber (reg:DI 2))
6299 (use (const_int 1))])
6300 (set (reg:DI 27) (reg:DI 4))]
6303 ;; Remove the clobber of register 4 when optimizing. This has to be
6304 ;; done with a peephole optimization rather than a split because the
6305 ;; split sequence for a call must be longer than one instruction.
6307 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
6308 (match_operand 1 "" ""))
6309 (clobber (reg:DI 2))
6310 (clobber (reg:DI 4))
6313 (use (const_int 1))])]
6314 "TARGET_64BIT && reload_completed"
6315 [(parallel [(call (mem:SI (match_dup 0))
6317 (clobber (reg:DI 2))
6320 (use (const_int 1))])]
6323 (define_insn "*call_reg_64bit_post_reload"
6324 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
6325 (match_operand 1 "" "i"))
6326 (clobber (reg:DI 2))
6329 (use (const_int 1))]
6333 return output_indirect_call (insn, operands[0]);
6335 [(set_attr "type" "dyncall")
6336 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6338 (define_expand "call_value"
6339 [(parallel [(set (match_operand 0 "" "")
6340 (call (match_operand:SI 1 "" "")
6341 (match_operand 2 "" "")))
6342 (clobber (reg:SI 2))])]
6347 rtx dst = operands[0];
6348 rtx nb = operands[2];
6350 if (TARGET_PORTABLE_RUNTIME)
6351 op = force_reg (SImode, XEXP (operands[1], 0));
6353 op = XEXP (operands[1], 0);
6356 emit_move_insn (arg_pointer_rtx,
6357 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6360 /* Use two different patterns for calls to explicitly named functions
6361 and calls through function pointers. This is necessary as these two
6362 types of calls use different calling conventions, and CSE might try
6363 to change the named call into an indirect call in some cases (using
6364 two patterns keeps CSE from performing this optimization).
6366 We now use even more call patterns as there was a subtle bug in
6367 attempting to restore the pic register after a call using a simple
6368 move insn. During reload, a instruction involving a pseudo register
6369 with no explicit dependence on the PIC register can be converted
6370 to an equivalent load from memory using the PIC register. If we
6371 emit a simple move to restore the PIC register in the initial rtl
6372 generation, then it can potentially be repositioned during scheduling.
6373 and an instruction that eventually uses the PIC register may end up
6374 between the call and the PIC register restore.
6376 This only worked because there is a post call group of instructions
6377 that are scheduled with the call. These instructions are included
6378 in the same basic block as the call. However, calls can throw in
6379 C++ code and a basic block has to terminate at the call if the call
6380 can throw. This results in the PIC register restore being scheduled
6381 independently from the call. So, we now hide the save and restore
6382 of the PIC register in the call pattern until after reload. Then,
6383 we split the moves out. A small side benefit is that we now don't
6384 need to have a use of the PIC register in the return pattern and
6385 the final save/restore operation is not needed.
6387 I elected to just clobber %r4 in the PIC patterns and use it instead
6388 of trying to force hppa_pic_save_rtx () to a callee saved register.
6389 This might have required a new register class and constraint. It
6390 was also simpler to just handle the restore from a register than a
6394 if (GET_CODE (op) == SYMBOL_REF)
6395 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
6398 op = force_reg (word_mode, op);
6399 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
6404 if (GET_CODE (op) == SYMBOL_REF)
6407 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
6409 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
6413 rtx tmpreg = gen_rtx_REG (word_mode, 22);
6415 emit_move_insn (tmpreg, force_reg (word_mode, op));
6417 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
6419 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
6426 (define_insn "call_val_symref"
6427 [(set (match_operand 0 "" "")
6428 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6429 (match_operand 2 "" "i")))
6430 (clobber (reg:SI 1))
6431 (clobber (reg:SI 2))
6432 (use (const_int 0))]
6433 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6436 output_arg_descriptor (insn);
6437 return output_call (insn, operands[1], 0);
6439 [(set_attr "type" "call")
6440 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6442 (define_insn "call_val_symref_pic"
6443 [(set (match_operand 0 "" "")
6444 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6445 (match_operand 2 "" "i")))
6446 (clobber (reg:SI 1))
6447 (clobber (reg:SI 2))
6448 (clobber (reg:SI 4))
6450 (use (const_int 0))]
6451 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6454 output_arg_descriptor (insn);
6455 return output_call (insn, operands[1], 0);
6457 [(set_attr "type" "call")
6458 (set (attr "length")
6459 (plus (symbol_ref "attr_length_call (insn, 0)")
6460 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6462 ;; Split out the PIC register save and restore after reload. This is
6463 ;; done if the function doesn't return.
6465 [(parallel [(set (match_operand 0 "" "")
6466 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6467 (match_operand 2 "" "")))
6468 (clobber (reg:SI 1))
6469 (clobber (reg:SI 2))
6470 (clobber (reg:SI 4))
6472 (use (const_int 0))])]
6473 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
6475 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6476 [(set (reg:SI 4) (reg:SI 19))
6477 (parallel [(set (match_dup 0)
6478 (call (mem:SI (match_dup 1))
6480 (clobber (reg:SI 1))
6481 (clobber (reg:SI 2))
6483 (use (const_int 0))])
6484 (set (reg:SI 19) (reg:SI 4))]
6487 ;; Remove the clobber of register 4 when optimizing. This has to be
6488 ;; done with a peephole optimization rather than a split because the
6489 ;; split sequence for a call must be longer than one instruction.
6491 [(parallel [(set (match_operand 0 "" "")
6492 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6493 (match_operand 2 "" "")))
6494 (clobber (reg:SI 1))
6495 (clobber (reg:SI 2))
6496 (clobber (reg:SI 4))
6498 (use (const_int 0))])]
6499 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
6500 [(parallel [(set (match_dup 0)
6501 (call (mem:SI (match_dup 1))
6503 (clobber (reg:SI 1))
6504 (clobber (reg:SI 2))
6506 (use (const_int 0))])]
6509 (define_insn "*call_val_symref_pic_post_reload"
6510 [(set (match_operand 0 "" "")
6511 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6512 (match_operand 2 "" "i")))
6513 (clobber (reg:SI 1))
6514 (clobber (reg:SI 2))
6516 (use (const_int 0))]
6517 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6520 output_arg_descriptor (insn);
6521 return output_call (insn, operands[1], 0);
6523 [(set_attr "type" "call")
6524 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6526 ;; This pattern is split if it is necessary to save and restore the
6528 (define_insn "call_val_symref_64bit"
6529 [(set (match_operand 0 "" "")
6530 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6531 (match_operand 2 "" "i")))
6532 (clobber (reg:DI 1))
6533 (clobber (reg:DI 2))
6534 (clobber (reg:DI 4))
6537 (use (const_int 0))]
6541 output_arg_descriptor (insn);
6542 return output_call (insn, operands[1], 0);
6544 [(set_attr "type" "call")
6545 (set (attr "length")
6546 (plus (symbol_ref "attr_length_call (insn, 0)")
6547 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6549 ;; Split out the PIC register save and restore after reload. This is
6550 ;; done if the function doesn't return.
6552 [(parallel [(set (match_operand 0 "" "")
6553 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6554 (match_operand 2 "" "")))
6555 (clobber (reg:DI 1))
6556 (clobber (reg:DI 2))
6557 (clobber (reg:DI 4))
6560 (use (const_int 0))])]
6563 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6564 [(set (reg:DI 4) (reg:DI 27))
6565 (parallel [(set (match_dup 0)
6566 (call (mem:SI (match_dup 1))
6568 (clobber (reg:DI 1))
6569 (clobber (reg:DI 2))
6572 (use (const_int 0))])
6573 (set (reg:DI 27) (reg:DI 4))]
6576 ;; Remove the clobber of register 4 when optimizing. This has to be
6577 ;; done with a peephole optimization rather than a split because the
6578 ;; split sequence for a call must be longer than one instruction.
6580 [(parallel [(set (match_operand 0 "" "")
6581 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6582 (match_operand 2 "" "")))
6583 (clobber (reg:DI 1))
6584 (clobber (reg:DI 2))
6585 (clobber (reg:DI 4))
6588 (use (const_int 0))])]
6589 "TARGET_64BIT && reload_completed"
6590 [(parallel [(set (match_dup 0)
6591 (call (mem:SI (match_dup 1))
6593 (clobber (reg:DI 1))
6594 (clobber (reg:DI 2))
6597 (use (const_int 0))])]
6600 (define_insn "*call_val_symref_64bit_post_reload"
6601 [(set (match_operand 0 "" "")
6602 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6603 (match_operand 2 "" "i")))
6604 (clobber (reg:DI 1))
6605 (clobber (reg:DI 2))
6608 (use (const_int 0))]
6612 output_arg_descriptor (insn);
6613 return output_call (insn, operands[1], 0);
6615 [(set_attr "type" "call")
6616 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6618 (define_insn "call_val_reg"
6619 [(set (match_operand 0 "" "")
6620 (call (mem:SI (reg:SI 22))
6621 (match_operand 1 "" "i")))
6622 (clobber (reg:SI 1))
6623 (clobber (reg:SI 2))
6624 (use (const_int 1))]
6628 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6630 [(set_attr "type" "dyncall")
6631 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6633 ;; This pattern is split if it is necessary to save and restore the
6635 (define_insn "call_val_reg_pic"
6636 [(set (match_operand 0 "" "")
6637 (call (mem:SI (reg:SI 22))
6638 (match_operand 1 "" "i")))
6639 (clobber (reg:SI 1))
6640 (clobber (reg:SI 2))
6641 (clobber (reg:SI 4))
6643 (use (const_int 1))]
6647 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6649 [(set_attr "type" "dyncall")
6650 (set (attr "length")
6651 (plus (symbol_ref "attr_length_indirect_call (insn)")
6652 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6654 ;; Split out the PIC register save and restore after reload. This is
6655 ;; done if the function doesn't return.
6657 [(parallel [(set (match_operand 0 "" "")
6658 (call (mem:SI (reg:SI 22))
6659 (match_operand 1 "" "")))
6660 (clobber (reg:SI 1))
6661 (clobber (reg:SI 2))
6662 (clobber (reg:SI 4))
6664 (use (const_int 1))])]
6667 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6668 [(set (reg:SI 4) (reg:SI 19))
6669 (parallel [(set (match_dup 0)
6670 (call (mem:SI (reg:SI 22))
6672 (clobber (reg:SI 1))
6673 (clobber (reg:SI 2))
6675 (use (const_int 1))])
6676 (set (reg:SI 19) (reg:SI 4))]
6679 ;; Remove the clobber of register 4 when optimizing. This has to be
6680 ;; done with a peephole optimization rather than a split because the
6681 ;; split sequence for a call must be longer than one instruction.
6683 [(parallel [(set (match_operand 0 "" "")
6684 (call (mem:SI (reg:SI 22))
6685 (match_operand 1 "" "")))
6686 (clobber (reg:SI 1))
6687 (clobber (reg:SI 2))
6688 (clobber (reg:SI 4))
6690 (use (const_int 1))])]
6691 "!TARGET_64BIT && reload_completed"
6692 [(parallel [(set (match_dup 0)
6693 (call (mem:SI (reg:SI 22))
6695 (clobber (reg:SI 1))
6696 (clobber (reg:SI 2))
6698 (use (const_int 1))])]
6701 (define_insn "*call_val_reg_pic_post_reload"
6702 [(set (match_operand 0 "" "")
6703 (call (mem:SI (reg:SI 22))
6704 (match_operand 1 "" "i")))
6705 (clobber (reg:SI 1))
6706 (clobber (reg:SI 2))
6708 (use (const_int 1))]
6712 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6714 [(set_attr "type" "dyncall")
6715 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6717 ;; This pattern is split if it is necessary to save and restore the
6719 (define_insn "call_val_reg_64bit"
6720 [(set (match_operand 0 "" "")
6721 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
6722 (match_operand 2 "" "i")))
6723 (clobber (reg:DI 2))
6724 (clobber (reg:DI 4))
6727 (use (const_int 1))]
6731 return output_indirect_call (insn, operands[1]);
6733 [(set_attr "type" "dyncall")
6734 (set (attr "length")
6735 (plus (symbol_ref "attr_length_indirect_call (insn)")
6736 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6738 ;; Split out the PIC register save and restore after reload. This is
6739 ;; done if the function doesn't return.
6741 [(parallel [(set (match_operand 0 "" "")
6742 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
6743 (match_operand 2 "" "")))
6744 (clobber (reg:DI 2))
6745 (clobber (reg:DI 4))
6748 (use (const_int 1))])]
6751 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6752 [(set (reg:DI 4) (reg:DI 27))
6753 (parallel [(set (match_dup 0)
6754 (call (mem:SI (match_dup 1))
6756 (clobber (reg:DI 2))
6759 (use (const_int 1))])
6760 (set (reg:DI 27) (reg:DI 4))]
6763 ;; Remove the clobber of register 4 when optimizing. This has to be
6764 ;; done with a peephole optimization rather than a split because the
6765 ;; split sequence for a call must be longer than one instruction.
6767 [(parallel [(set (match_operand 0 "" "")
6768 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
6769 (match_operand 2 "" "")))
6770 (clobber (reg:DI 2))
6771 (clobber (reg:DI 4))
6774 (use (const_int 1))])]
6775 "TARGET_64BIT && reload_completed"
6776 [(parallel [(set (match_dup 0)
6777 (call (mem:SI (match_dup 1))
6779 (clobber (reg:DI 2))
6782 (use (const_int 1))])]
6785 (define_insn "*call_val_reg_64bit_post_reload"
6786 [(set (match_operand 0 "" "")
6787 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
6788 (match_operand 2 "" "i")))
6789 (clobber (reg:DI 2))
6792 (use (const_int 1))]
6796 return output_indirect_call (insn, operands[1]);
6798 [(set_attr "type" "dyncall")
6799 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6801 ;; Call subroutine returning any type.
6803 (define_expand "untyped_call"
6804 [(parallel [(call (match_operand 0 "" "")
6806 (match_operand 1 "" "")
6807 (match_operand 2 "" "")])]
6813 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6815 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6817 rtx set = XVECEXP (operands[2], 0, i);
6818 emit_move_insn (SET_DEST (set), SET_SRC (set));
6821 /* The optimizer does not know that the call sets the function value
6822 registers we stored in the result block. We avoid problems by
6823 claiming that all hard registers are used and clobbered at this
6825 emit_insn (gen_blockage ());
6830 (define_expand "sibcall"
6831 [(call (match_operand:SI 0 "" "")
6832 (match_operand 1 "" ""))]
6833 "!TARGET_PORTABLE_RUNTIME"
6839 op = XEXP (operands[0], 0);
6842 emit_move_insn (arg_pointer_rtx,
6843 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6846 /* Indirect sibling calls are not allowed. */
6848 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
6850 call_insn = gen_sibcall_internal_symref (op, operands[1]);
6852 call_insn = emit_call_insn (call_insn);
6855 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6857 /* We don't have to restore the PIC register. */
6859 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6864 (define_insn "sibcall_internal_symref"
6865 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6866 (match_operand 1 "" "i"))
6867 (clobber (reg:SI 1))
6869 (use (const_int 0))]
6870 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6873 output_arg_descriptor (insn);
6874 return output_call (insn, operands[0], 1);
6876 [(set_attr "type" "call")
6877 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
6879 (define_insn "sibcall_internal_symref_64bit"
6880 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6881 (match_operand 1 "" "i"))
6882 (clobber (reg:DI 1))
6884 (use (const_int 0))]
6888 output_arg_descriptor (insn);
6889 return output_call (insn, operands[0], 1);
6891 [(set_attr "type" "call")
6892 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
6894 (define_expand "sibcall_value"
6895 [(set (match_operand 0 "" "")
6896 (call (match_operand:SI 1 "" "")
6897 (match_operand 2 "" "")))]
6898 "!TARGET_PORTABLE_RUNTIME"
6904 op = XEXP (operands[1], 0);
6907 emit_move_insn (arg_pointer_rtx,
6908 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6911 /* Indirect sibling calls are not allowed. */
6914 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
6917 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
6919 call_insn = emit_call_insn (call_insn);
6922 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6924 /* We don't have to restore the PIC register. */
6926 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6931 (define_insn "sibcall_value_internal_symref"
6932 [(set (match_operand 0 "" "")
6933 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6934 (match_operand 2 "" "i")))
6935 (clobber (reg:SI 1))
6937 (use (const_int 0))]
6938 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6941 output_arg_descriptor (insn);
6942 return output_call (insn, operands[1], 1);
6944 [(set_attr "type" "call")
6945 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
6947 (define_insn "sibcall_value_internal_symref_64bit"
6948 [(set (match_operand 0 "" "")
6949 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6950 (match_operand 2 "" "i")))
6951 (clobber (reg:DI 1))
6953 (use (const_int 0))]
6957 output_arg_descriptor (insn);
6958 return output_call (insn, operands[1], 1);
6960 [(set_attr "type" "call")
6961 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
6967 [(set_attr "type" "move")
6968 (set_attr "length" "4")])
6970 ;; These are just placeholders so we know where branch tables
6972 (define_insn "begin_brtab"
6977 /* Only GAS actually supports this pseudo-op. */
6979 return \".begin_brtab\";
6983 [(set_attr "type" "move")
6984 (set_attr "length" "0")])
6986 (define_insn "end_brtab"
6991 /* Only GAS actually supports this pseudo-op. */
6993 return \".end_brtab\";
6997 [(set_attr "type" "move")
6998 (set_attr "length" "0")])
7000 ;;; EH does longjmp's from and within the data section. Thus,
7001 ;;; an interspace branch is required for the longjmp implementation.
7002 ;;; Registers r1 and r2 are used as scratch registers for the jump
7004 (define_expand "interspace_jump"
7006 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7007 (clobber (match_dup 1))])]
7011 operands[1] = gen_rtx_REG (word_mode, 2);
7015 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7016 (clobber (reg:SI 2))]
7017 "TARGET_PA_20 && !TARGET_64BIT"
7019 [(set_attr "type" "branch")
7020 (set_attr "length" "4")])
7023 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7024 (clobber (reg:SI 2))]
7025 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
7027 [(set_attr "type" "branch")
7028 (set_attr "length" "4")])
7031 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7032 (clobber (reg:SI 2))]
7034 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
7035 [(set_attr "type" "branch")
7036 (set_attr "length" "12")])
7039 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7040 (clobber (reg:DI 2))]
7043 [(set_attr "type" "branch")
7044 (set_attr "length" "4")])
7046 (define_expand "builtin_longjmp"
7047 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
7051 /* The elements of the buffer are, in order: */
7052 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
7053 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
7054 POINTER_SIZE / BITS_PER_UNIT));
7055 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
7056 (POINTER_SIZE * 2) / BITS_PER_UNIT));
7057 rtx pv = gen_rtx_REG (Pmode, 1);
7059 /* This bit is the same as expand_builtin_longjmp. */
7060 emit_move_insn (hard_frame_pointer_rtx, fp);
7061 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7062 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7063 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7065 /* Load the label we are jumping through into r1 so that we know
7066 where to look for it when we get back to setjmp's function for
7067 restoring the gp. */
7068 emit_move_insn (pv, lab);
7070 /* Prevent the insns above from being scheduled into the delay slot
7071 of the interspace jump because the space register could change. */
7072 emit_insn (gen_blockage ());
7074 emit_jump_insn (gen_interspace_jump (pv));
7079 ;;; Hope this is only within a function...
7080 (define_insn "indirect_jump"
7081 [(set (pc) (match_operand 0 "register_operand" "r"))]
7082 "GET_MODE (operands[0]) == word_mode"
7084 [(set_attr "type" "branch")
7085 (set_attr "length" "4")])
7087 (define_expand "extzv"
7088 [(set (match_operand 0 "register_operand" "")
7089 (zero_extract (match_operand 1 "register_operand" "")
7090 (match_operand 2 "uint32_operand" "")
7091 (match_operand 3 "uint32_operand" "")))]
7096 emit_insn (gen_extzv_64 (operands[0], operands[1],
7097 operands[2], operands[3]));
7100 if (! uint5_operand (operands[2], SImode)
7101 || ! uint5_operand (operands[3], SImode))
7103 emit_insn (gen_extzv_32 (operands[0], operands[1],
7104 operands[2], operands[3]));
7109 (define_insn "extzv_32"
7110 [(set (match_operand:SI 0 "register_operand" "=r")
7111 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
7112 (match_operand:SI 2 "uint5_operand" "")
7113 (match_operand:SI 3 "uint5_operand" "")))]
7115 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
7116 [(set_attr "type" "shift")
7117 (set_attr "length" "4")])
7120 [(set (match_operand:SI 0 "register_operand" "=r")
7121 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
7123 (match_operand:SI 2 "register_operand" "q")))]
7125 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
7126 [(set_attr "type" "shift")
7127 (set_attr "length" "4")])
7129 (define_insn "extzv_64"
7130 [(set (match_operand:DI 0 "register_operand" "=r")
7131 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
7132 (match_operand:DI 2 "uint32_operand" "")
7133 (match_operand:DI 3 "uint32_operand" "")))]
7135 "extrd,u %1,%3+%2-1,%2,%0"
7136 [(set_attr "type" "shift")
7137 (set_attr "length" "4")])
7140 [(set (match_operand:DI 0 "register_operand" "=r")
7141 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
7143 (match_operand:DI 2 "register_operand" "q")))]
7145 "extrd,u %1,%%sar,1,%0"
7146 [(set_attr "type" "shift")
7147 (set_attr "length" "4")])
7149 (define_expand "extv"
7150 [(set (match_operand 0 "register_operand" "")
7151 (sign_extract (match_operand 1 "register_operand" "")
7152 (match_operand 2 "uint32_operand" "")
7153 (match_operand 3 "uint32_operand" "")))]
7158 emit_insn (gen_extv_64 (operands[0], operands[1],
7159 operands[2], operands[3]));
7162 if (! uint5_operand (operands[2], SImode)
7163 || ! uint5_operand (operands[3], SImode))
7165 emit_insn (gen_extv_32 (operands[0], operands[1],
7166 operands[2], operands[3]));
7171 (define_insn "extv_32"
7172 [(set (match_operand:SI 0 "register_operand" "=r")
7173 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
7174 (match_operand:SI 2 "uint5_operand" "")
7175 (match_operand:SI 3 "uint5_operand" "")))]
7177 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
7178 [(set_attr "type" "shift")
7179 (set_attr "length" "4")])
7182 [(set (match_operand:SI 0 "register_operand" "=r")
7183 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
7185 (match_operand:SI 2 "register_operand" "q")))]
7187 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
7188 [(set_attr "type" "shift")
7189 (set_attr "length" "4")])
7191 (define_insn "extv_64"
7192 [(set (match_operand:DI 0 "register_operand" "=r")
7193 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
7194 (match_operand:DI 2 "uint32_operand" "")
7195 (match_operand:DI 3 "uint32_operand" "")))]
7197 "extrd,s %1,%3+%2-1,%2,%0"
7198 [(set_attr "type" "shift")
7199 (set_attr "length" "4")])
7202 [(set (match_operand:DI 0 "register_operand" "=r")
7203 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
7205 (match_operand:DI 2 "register_operand" "q")))]
7207 "extrd,s %1,%%sar,1,%0"
7208 [(set_attr "type" "shift")
7209 (set_attr "length" "4")])
7211 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
7212 (define_expand "insv"
7213 [(set (zero_extract (match_operand 0 "register_operand" "")
7214 (match_operand 1 "uint32_operand" "")
7215 (match_operand 2 "uint32_operand" ""))
7216 (match_operand 3 "arith5_operand" ""))]
7221 emit_insn (gen_insv_64 (operands[0], operands[1],
7222 operands[2], operands[3]));
7225 if (! uint5_operand (operands[2], SImode)
7226 || ! uint5_operand (operands[3], SImode))
7228 emit_insn (gen_insv_32 (operands[0], operands[1],
7229 operands[2], operands[3]));
7234 (define_insn "insv_32"
7235 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
7236 (match_operand:SI 1 "uint5_operand" "")
7237 (match_operand:SI 2 "uint5_operand" ""))
7238 (match_operand:SI 3 "arith5_operand" "r,L"))]
7241 {dep|depw} %3,%2+%1-1,%1,%0
7242 {depi|depwi} %3,%2+%1-1,%1,%0"
7243 [(set_attr "type" "shift,shift")
7244 (set_attr "length" "4,4")])
7246 ;; Optimize insertion of const_int values of type 1...1xxxx.
7248 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
7249 (match_operand:SI 1 "uint5_operand" "")
7250 (match_operand:SI 2 "uint5_operand" ""))
7251 (match_operand:SI 3 "const_int_operand" ""))]
7252 "(INTVAL (operands[3]) & 0x10) != 0 &&
7253 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
7256 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
7257 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
7259 [(set_attr "type" "shift")
7260 (set_attr "length" "4")])
7262 (define_insn "insv_64"
7263 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
7264 (match_operand:DI 1 "uint32_operand" "")
7265 (match_operand:DI 2 "uint32_operand" ""))
7266 (match_operand:DI 3 "arith32_operand" "r,L"))]
7269 depd %3,%2+%1-1,%1,%0
7270 depdi %3,%2+%1-1,%1,%0"
7271 [(set_attr "type" "shift,shift")
7272 (set_attr "length" "4,4")])
7274 ;; Optimize insertion of const_int values of type 1...1xxxx.
7276 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
7277 (match_operand:DI 1 "uint32_operand" "")
7278 (match_operand:DI 2 "uint32_operand" ""))
7279 (match_operand:DI 3 "const_int_operand" ""))]
7280 "(INTVAL (operands[3]) & 0x10) != 0
7282 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
7285 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
7286 return \"depdi %3,%2+%1-1,%1,%0\";
7288 [(set_attr "type" "shift")
7289 (set_attr "length" "4")])
7292 [(set (match_operand:DI 0 "register_operand" "=r")
7293 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
7296 "depd,z %1,31,32,%0"
7297 [(set_attr "type" "shift")
7298 (set_attr "length" "4")])
7300 ;; This insn is used for some loop tests, typically loops reversed when
7301 ;; strength reduction is used. It is actually created when the instruction
7302 ;; combination phase combines the special loop test. Since this insn
7303 ;; is both a jump insn and has an output, it must deal with its own
7304 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
7305 ;; to not choose the register alternatives in the event a reload is needed.
7306 (define_insn "decrement_and_branch_until_zero"
7309 (match_operator 2 "comparison_operator"
7311 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
7312 (match_operand:SI 1 "int5_operand" "L,L,L"))
7314 (label_ref (match_operand 3 "" ""))
7317 (plus:SI (match_dup 0) (match_dup 1)))
7318 (clobber (match_scratch:SI 4 "=X,r,r"))]
7320 "* return output_dbra (operands, insn, which_alternative); "
7321 ;; Do not expect to understand this the first time through.
7322 [(set_attr "type" "cbranch,multi,multi")
7323 (set (attr "length")
7324 (if_then_else (eq_attr "alternative" "0")
7325 ;; Loop counter in register case
7326 ;; Short branch has length of 4
7327 ;; Long branch has length of 8
7328 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7333 ;; Loop counter in FP reg case.
7334 ;; Extra goo to deal with additional reload insns.
7335 (if_then_else (eq_attr "alternative" "1")
7336 (if_then_else (lt (match_dup 3) (pc))
7338 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
7343 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7347 ;; Loop counter in memory case.
7348 ;; Extra goo to deal with additional reload insns.
7349 (if_then_else (lt (match_dup 3) (pc))
7351 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
7356 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7359 (const_int 16))))))])
7364 (match_operator 2 "movb_comparison_operator"
7365 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
7366 (label_ref (match_operand 3 "" ""))
7368 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
7371 "* return output_movb (operands, insn, which_alternative, 0); "
7372 ;; Do not expect to understand this the first time through.
7373 [(set_attr "type" "cbranch,multi,multi,multi")
7374 (set (attr "length")
7375 (if_then_else (eq_attr "alternative" "0")
7376 ;; Loop counter in register case
7377 ;; Short branch has length of 4
7378 ;; Long branch has length of 8
7379 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7384 ;; Loop counter in FP reg case.
7385 ;; Extra goo to deal with additional reload insns.
7386 (if_then_else (eq_attr "alternative" "1")
7387 (if_then_else (lt (match_dup 3) (pc))
7389 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
7394 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7398 ;; Loop counter in memory or sar case.
7399 ;; Extra goo to deal with additional reload insns.
7401 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7404 (const_int 12)))))])
7406 ;; Handle negated branch.
7410 (match_operator 2 "movb_comparison_operator"
7411 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
7413 (label_ref (match_operand 3 "" ""))))
7414 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
7417 "* return output_movb (operands, insn, which_alternative, 1); "
7418 ;; Do not expect to understand this the first time through.
7419 [(set_attr "type" "cbranch,multi,multi,multi")
7420 (set (attr "length")
7421 (if_then_else (eq_attr "alternative" "0")
7422 ;; Loop counter in register case
7423 ;; Short branch has length of 4
7424 ;; Long branch has length of 8
7425 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7430 ;; Loop counter in FP reg case.
7431 ;; Extra goo to deal with additional reload insns.
7432 (if_then_else (eq_attr "alternative" "1")
7433 (if_then_else (lt (match_dup 3) (pc))
7435 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
7440 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7444 ;; Loop counter in memory or SAR case.
7445 ;; Extra goo to deal with additional reload insns.
7447 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7450 (const_int 12)))))])
7453 [(set (pc) (label_ref (match_operand 3 "" "" )))
7454 (set (match_operand:SI 0 "ireg_operand" "=r")
7455 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
7456 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
7457 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
7460 return output_parallel_addb (operands, get_attr_length (insn));
7462 [(set_attr "type" "parallel_branch")
7463 (set (attr "length")
7464 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7470 [(set (pc) (label_ref (match_operand 2 "" "" )))
7471 (set (match_operand:SF 0 "ireg_operand" "=r")
7472 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
7476 return output_parallel_movb (operands, get_attr_length (insn));
7478 [(set_attr "type" "parallel_branch")
7479 (set (attr "length")
7480 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7486 [(set (pc) (label_ref (match_operand 2 "" "" )))
7487 (set (match_operand:SI 0 "ireg_operand" "=r")
7488 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
7492 return output_parallel_movb (operands, get_attr_length (insn));
7494 [(set_attr "type" "parallel_branch")
7495 (set (attr "length")
7496 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7502 [(set (pc) (label_ref (match_operand 2 "" "" )))
7503 (set (match_operand:HI 0 "ireg_operand" "=r")
7504 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
7508 return output_parallel_movb (operands, get_attr_length (insn));
7510 [(set_attr "type" "parallel_branch")
7511 (set (attr "length")
7512 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7518 [(set (pc) (label_ref (match_operand 2 "" "" )))
7519 (set (match_operand:QI 0 "ireg_operand" "=r")
7520 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
7524 return output_parallel_movb (operands, get_attr_length (insn));
7526 [(set_attr "type" "parallel_branch")
7527 (set (attr "length")
7528 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7534 [(set (match_operand 0 "register_operand" "=f")
7535 (mult (match_operand 1 "register_operand" "f")
7536 (match_operand 2 "register_operand" "f")))
7537 (set (match_operand 3 "register_operand" "+f")
7538 (plus (match_operand 4 "register_operand" "f")
7539 (match_operand 5 "register_operand" "f")))]
7540 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7541 && reload_completed && fmpyaddoperands (operands)"
7544 if (GET_MODE (operands[0]) == DFmode)
7546 if (rtx_equal_p (operands[3], operands[5]))
7547 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
7549 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
7553 if (rtx_equal_p (operands[3], operands[5]))
7554 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
7556 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
7559 [(set_attr "type" "fpalu")
7560 (set_attr "length" "4")])
7563 [(set (match_operand 3 "register_operand" "+f")
7564 (plus (match_operand 4 "register_operand" "f")
7565 (match_operand 5 "register_operand" "f")))
7566 (set (match_operand 0 "register_operand" "=f")
7567 (mult (match_operand 1 "register_operand" "f")
7568 (match_operand 2 "register_operand" "f")))]
7569 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7570 && reload_completed && fmpyaddoperands (operands)"
7573 if (GET_MODE (operands[0]) == DFmode)
7575 if (rtx_equal_p (operands[3], operands[5]))
7576 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
7578 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
7582 if (rtx_equal_p (operands[3], operands[5]))
7583 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
7585 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
7588 [(set_attr "type" "fpalu")
7589 (set_attr "length" "4")])
7592 [(set (match_operand 0 "register_operand" "=f")
7593 (mult (match_operand 1 "register_operand" "f")
7594 (match_operand 2 "register_operand" "f")))
7595 (set (match_operand 3 "register_operand" "+f")
7596 (minus (match_operand 4 "register_operand" "f")
7597 (match_operand 5 "register_operand" "f")))]
7598 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7599 && reload_completed && fmpysuboperands (operands)"
7602 if (GET_MODE (operands[0]) == DFmode)
7603 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7605 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7607 [(set_attr "type" "fpalu")
7608 (set_attr "length" "4")])
7611 [(set (match_operand 3 "register_operand" "+f")
7612 (minus (match_operand 4 "register_operand" "f")
7613 (match_operand 5 "register_operand" "f")))
7614 (set (match_operand 0 "register_operand" "=f")
7615 (mult (match_operand 1 "register_operand" "f")
7616 (match_operand 2 "register_operand" "f")))]
7617 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7618 && reload_completed && fmpysuboperands (operands)"
7621 if (GET_MODE (operands[0]) == DFmode)
7622 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7624 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7626 [(set_attr "type" "fpalu")
7627 (set_attr "length" "4")])
7629 ;; Clean up turds left by reload.
7631 [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
7632 (match_operand 1 "register_operand" "fr"))
7633 (set (match_operand 2 "register_operand" "fr")
7635 "! TARGET_SOFT_FLOAT
7636 && GET_CODE (operands[0]) == MEM
7637 && ! MEM_VOLATILE_P (operands[0])
7638 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7639 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7640 && GET_MODE (operands[0]) == DFmode
7641 && GET_CODE (operands[1]) == REG
7642 && GET_CODE (operands[2]) == REG
7643 && ! side_effects_p (XEXP (operands[0], 0))
7644 && REGNO_REG_CLASS (REGNO (operands[1]))
7645 == REGNO_REG_CLASS (REGNO (operands[2]))"
7650 if (FP_REG_P (operands[1]))
7651 output_asm_insn (output_fp_move_double (operands), operands);
7653 output_asm_insn (output_move_double (operands), operands);
7655 if (rtx_equal_p (operands[1], operands[2]))
7658 xoperands[0] = operands[2];
7659 xoperands[1] = operands[1];
7661 if (FP_REG_P (xoperands[1]))
7662 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7664 output_asm_insn (output_move_double (xoperands), xoperands);
7670 [(set (match_operand 0 "register_operand" "fr")
7671 (match_operand 1 "reg_or_nonsymb_mem_operand" ""))
7672 (set (match_operand 2 "register_operand" "fr")
7674 "! TARGET_SOFT_FLOAT
7675 && GET_CODE (operands[1]) == MEM
7676 && ! MEM_VOLATILE_P (operands[1])
7677 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7678 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7679 && GET_MODE (operands[0]) == DFmode
7680 && GET_CODE (operands[0]) == REG
7681 && GET_CODE (operands[2]) == REG
7682 && ! side_effects_p (XEXP (operands[1], 0))
7683 && REGNO_REG_CLASS (REGNO (operands[0]))
7684 == REGNO_REG_CLASS (REGNO (operands[2]))"
7689 if (FP_REG_P (operands[0]))
7690 output_asm_insn (output_fp_move_double (operands), operands);
7692 output_asm_insn (output_move_double (operands), operands);
7694 xoperands[0] = operands[2];
7695 xoperands[1] = operands[0];
7697 if (FP_REG_P (xoperands[1]))
7698 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7700 output_asm_insn (output_move_double (xoperands), xoperands);
7705 ;; Flush the I and D cache line found at the address in operand 0.
7706 ;; This is used by the trampoline code for nested functions.
7707 ;; So long as the trampoline itself is less than 32 bytes this
7710 (define_insn "dcacheflush"
7711 [(unspec_volatile [(const_int 1)] 0)
7712 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7713 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
7715 "fdc 0(%0)\;fdc 0(%1)\;sync"
7716 [(set_attr "type" "multi")
7717 (set_attr "length" "12")])
7719 (define_insn "icacheflush"
7720 [(unspec_volatile [(const_int 2)] 0)
7721 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7722 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
7723 (use (match_operand 2 "pmode_register_operand" "r"))
7724 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
7725 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
7727 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
7728 [(set_attr "type" "multi")
7729 (set_attr "length" "52")])
7731 ;; An out-of-line prologue.
7732 (define_insn "outline_prologue_call"
7733 [(unspec_volatile [(const_int 0)] 0)
7734 (clobber (reg:SI 31))
7735 (clobber (reg:SI 22))
7736 (clobber (reg:SI 21))
7737 (clobber (reg:SI 20))
7738 (clobber (reg:SI 19))
7739 (clobber (reg:SI 1))]
7743 extern int frame_pointer_needed;
7745 /* We need two different versions depending on whether or not we
7746 need a frame pointer. Also note that we return to the instruction
7747 immediately after the branch rather than two instructions after the
7748 break as normally is the case. */
7749 if (frame_pointer_needed)
7751 /* Must import the magic millicode routine(s). */
7752 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
7754 if (TARGET_PORTABLE_RUNTIME)
7756 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
7757 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
7761 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
7765 /* Must import the magic millicode routine(s). */
7766 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
7768 if (TARGET_PORTABLE_RUNTIME)
7770 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
7771 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
7774 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
7778 [(set_attr "type" "multi")
7779 (set_attr "length" "8")])
7781 ;; An out-of-line epilogue.
7782 (define_insn "outline_epilogue_call"
7783 [(unspec_volatile [(const_int 1)] 0)
7786 (clobber (reg:SI 31))
7787 (clobber (reg:SI 22))
7788 (clobber (reg:SI 21))
7789 (clobber (reg:SI 20))
7790 (clobber (reg:SI 19))
7791 (clobber (reg:SI 2))
7792 (clobber (reg:SI 1))]
7796 extern int frame_pointer_needed;
7798 /* We need two different versions depending on whether or not we
7799 need a frame pointer. Also note that we return to the instruction
7800 immediately after the branch rather than two instructions after the
7801 break as normally is the case. */
7802 if (frame_pointer_needed)
7804 /* Must import the magic millicode routine. */
7805 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
7807 /* The out-of-line prologue will make sure we return to the right
7809 if (TARGET_PORTABLE_RUNTIME)
7811 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
7812 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
7816 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
7820 /* Must import the magic millicode routine. */
7821 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
7823 /* The out-of-line prologue will make sure we return to the right
7825 if (TARGET_PORTABLE_RUNTIME)
7827 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
7828 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
7831 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
7835 [(set_attr "type" "multi")
7836 (set_attr "length" "8")])
7838 ;; Given a function pointer, canonicalize it so it can be
7839 ;; reliably compared to another function pointer. */
7840 (define_expand "canonicalize_funcptr_for_compare"
7841 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
7842 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7843 (clobber (match_dup 2))
7844 (clobber (reg:SI 26))
7845 (clobber (reg:SI 22))
7846 (clobber (reg:SI 31))])
7847 (set (match_operand:SI 0 "register_operand" "")
7849 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7854 rtx canonicalize_funcptr_for_compare_libfunc
7855 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
7857 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
7858 operands[0], LCT_NORMAL, Pmode,
7859 1, operands[1], Pmode);
7863 operands[2] = gen_reg_rtx (SImode);
7864 if (GET_CODE (operands[1]) != REG)
7866 rtx tmp = gen_reg_rtx (Pmode);
7867 emit_move_insn (tmp, operands[1]);
7873 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7874 (clobber (match_operand:SI 0 "register_operand" "=a"))
7875 (clobber (reg:SI 26))
7876 (clobber (reg:SI 22))
7877 (clobber (reg:SI 31))]
7881 int length = get_attr_length (insn);
7884 xoperands[0] = GEN_INT (length - 8);
7885 xoperands[1] = GEN_INT (length - 16);
7887 /* Must import the magic millicode routine. */
7888 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
7890 /* This is absolutely amazing.
7892 First, copy our input parameter into %r29 just in case we don't
7893 need to call $$sh_func_adrs. */
7894 output_asm_insn (\"copy %%r26,%%r29\", NULL);
7895 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
7897 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
7898 we use %r26 unchanged. */
7899 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
7900 output_asm_insn (\"ldi 4096,%%r31\", NULL);
7902 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
7903 4096, then again we use %r26 unchanged. */
7904 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
7906 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
7907 return output_millicode_call (insn,
7908 gen_rtx_SYMBOL_REF (SImode,
7909 \"$$sh_func_adrs\"));
7911 [(set_attr "type" "multi")
7912 (set (attr "length")
7913 (plus (symbol_ref "attr_length_millicode_call (insn)")
7916 ;; On the PA, the PIC register is call clobbered, so it must
7917 ;; be saved & restored around calls by the caller. If the call
7918 ;; doesn't return normally (nonlocal goto, or an exception is
7919 ;; thrown), then the code at the exception handler label must
7920 ;; restore the PIC register.
7921 (define_expand "exception_receiver"
7926 /* On the 64-bit port, we need a blockage because there is
7927 confusion regarding the dependence of the restore on the
7928 frame pointer. As a result, the frame pointer and pic
7929 register restores sometimes are interchanged erroneously. */
7931 emit_insn (gen_blockage ());
7932 /* Restore the PIC register using hppa_pic_save_rtx (). The
7933 PIC register is not saved in the frame in 64-bit ABI. */
7934 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
7935 emit_insn (gen_blockage ());
7939 (define_expand "builtin_setjmp_receiver"
7940 [(label_ref (match_operand 0 "" ""))]
7945 emit_insn (gen_blockage ());
7946 /* Restore the PIC register. Hopefully, this will always be from
7947 a stack slot. The only registers that are valid after a
7948 builtin_longjmp are the stack and frame pointers. */
7949 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
7950 emit_insn (gen_blockage ());