1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "move_dest_operand"
2267 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
2268 (match_operand:SI 1 "move_src_operand"
2269 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && !TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2285 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2286 (set_attr "pa_combine_type" "addmove")
2287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2290 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2291 (match_operand:SI 1 "register_operand" "f"))]
2293 && !TARGET_DISABLE_INDEXING
2294 && reload_completed"
2296 [(set_attr "type" "fpstore")
2297 (set_attr "pa_combine_type" "addmove")
2298 (set_attr "length" "4")])
2300 ; Rewrite RTL using an indexed store. This will allow the insn that
2301 ; computes the address to be deleted if the register it sets is dead.
2303 [(set (match_operand:SI 0 "register_operand" "")
2304 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2306 (match_operand:SI 2 "register_operand" "")))
2307 (set (mem:SI (match_dup 0))
2308 (match_operand:SI 3 "register_operand" ""))]
2310 && REG_OK_FOR_BASE_P (operands[2])
2311 && FP_REGNO_P (REGNO (operands[3]))"
2312 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2314 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2319 [(set (match_operand:SI 0 "register_operand" "")
2320 (plus:SI (match_operand:SI 2 "register_operand" "")
2321 (mult:SI (match_operand:SI 1 "register_operand" "")
2323 (set (mem:SI (match_dup 0))
2324 (match_operand:SI 3 "register_operand" ""))]
2326 && REG_OK_FOR_BASE_P (operands[2])
2327 && FP_REGNO_P (REGNO (operands[3]))"
2328 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2330 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2335 [(set (match_operand:DI 0 "register_operand" "")
2336 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2338 (match_operand:DI 2 "register_operand" "")))
2339 (set (mem:SI (match_dup 0))
2340 (match_operand:SI 3 "register_operand" ""))]
2343 && REG_OK_FOR_BASE_P (operands[2])
2344 && FP_REGNO_P (REGNO (operands[3]))"
2345 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2347 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2352 [(set (match_operand:DI 0 "register_operand" "")
2353 (plus:DI (match_operand:DI 2 "register_operand" "")
2354 (mult:DI (match_operand:DI 1 "register_operand" "")
2356 (set (mem:SI (match_dup 0))
2357 (match_operand:SI 3 "register_operand" ""))]
2360 && REG_OK_FOR_BASE_P (operands[2])
2361 && FP_REGNO_P (REGNO (operands[3]))"
2362 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2364 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2369 [(set (match_operand:SI 0 "register_operand" "")
2370 (plus:SI (match_operand:SI 1 "register_operand" "")
2371 (match_operand:SI 2 "register_operand" "")))
2372 (set (mem:SI (match_dup 0))
2373 (match_operand:SI 3 "register_operand" ""))]
2375 && REG_OK_FOR_BASE_P (operands[1])
2376 && (TARGET_NO_SPACE_REGS
2377 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2378 && FP_REGNO_P (REGNO (operands[3]))"
2379 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2381 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2385 [(set (match_operand:SI 0 "register_operand" "")
2386 (plus:SI (match_operand:SI 1 "register_operand" "")
2387 (match_operand:SI 2 "register_operand" "")))
2388 (set (mem:SI (match_dup 0))
2389 (match_operand:SI 3 "register_operand" ""))]
2391 && REG_OK_FOR_BASE_P (operands[2])
2392 && (TARGET_NO_SPACE_REGS
2393 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2394 && FP_REGNO_P (REGNO (operands[3]))"
2395 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2397 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2401 [(set (match_operand:DI 0 "register_operand" "")
2402 (plus:DI (match_operand:DI 1 "register_operand" "")
2403 (match_operand:DI 2 "register_operand" "")))
2404 (set (mem:SI (match_dup 0))
2405 (match_operand:SI 3 "register_operand" ""))]
2408 && REG_OK_FOR_BASE_P (operands[1])
2409 && (TARGET_NO_SPACE_REGS
2410 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2411 && FP_REGNO_P (REGNO (operands[3]))"
2412 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2414 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2418 [(set (match_operand:DI 0 "register_operand" "")
2419 (plus:DI (match_operand:DI 1 "register_operand" "")
2420 (match_operand:DI 2 "register_operand" "")))
2421 (set (mem:SI (match_dup 0))
2422 (match_operand:SI 3 "register_operand" ""))]
2425 && REG_OK_FOR_BASE_P (operands[2])
2426 && (TARGET_NO_SPACE_REGS
2427 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2428 && FP_REGNO_P (REGNO (operands[3]))"
2429 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2431 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2435 [(set (match_operand:SI 0 "move_dest_operand"
2436 "=r,r,r,r,r,r,Q,!*q")
2437 (match_operand:SI 1 "move_src_operand"
2438 "A,r,J,N,K,RQ,rM,!rM"))]
2439 "(register_operand (operands[0], SImode)
2440 || reg_or_0_operand (operands[1], SImode))
2441 && TARGET_SOFT_FLOAT"
2447 {zdepi|depwi,z} %Z1,%0
2451 [(set_attr "type" "load,move,move,move,move,load,store,move")
2452 (set_attr "pa_combine_type" "addmove")
2453 (set_attr "length" "4,4,4,4,4,4,4,4")])
2455 ;; Load or store with base-register modification.
2457 [(set (match_operand:SI 0 "register_operand" "=r")
2458 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2459 (match_operand:DI 2 "int5_operand" "L"))))
2461 (plus:DI (match_dup 1) (match_dup 2)))]
2464 [(set_attr "type" "load")
2465 (set_attr "length" "4")])
2467 ; And a zero extended variant.
2469 [(set (match_operand:DI 0 "register_operand" "=r")
2470 (zero_extend:DI (mem:SI
2472 (match_operand:DI 1 "register_operand" "+r")
2473 (match_operand:DI 2 "int5_operand" "L")))))
2475 (plus:DI (match_dup 1) (match_dup 2)))]
2478 [(set_attr "type" "load")
2479 (set_attr "length" "4")])
2481 (define_expand "pre_load"
2482 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2483 (mem (plus (match_operand 1 "register_operand" "")
2484 (match_operand 2 "pre_cint_operand" ""))))
2486 (plus (match_dup 1) (match_dup 2)))])]
2492 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2495 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2499 (define_insn "pre_ldw"
2500 [(set (match_operand:SI 0 "register_operand" "=r")
2501 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2502 (match_operand:SI 2 "pre_cint_operand" ""))))
2504 (plus:SI (match_dup 1) (match_dup 2)))]
2508 if (INTVAL (operands[2]) < 0)
2509 return \"{ldwm|ldw,mb} %2(%1),%0\";
2510 return \"{ldws|ldw},mb %2(%1),%0\";
2512 [(set_attr "type" "load")
2513 (set_attr "length" "4")])
2515 (define_insn "pre_ldd"
2516 [(set (match_operand:DI 0 "register_operand" "=r")
2517 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2518 (match_operand:DI 2 "pre_cint_operand" ""))))
2520 (plus:DI (match_dup 1) (match_dup 2)))]
2523 [(set_attr "type" "load")
2524 (set_attr "length" "4")])
2527 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2528 (match_operand:SI 1 "pre_cint_operand" "")))
2529 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2531 (plus:SI (match_dup 0) (match_dup 1)))]
2535 if (INTVAL (operands[1]) < 0)
2536 return \"{stwm|stw,mb} %r2,%1(%0)\";
2537 return \"{stws|stw},mb %r2,%1(%0)\";
2539 [(set_attr "type" "store")
2540 (set_attr "length" "4")])
2543 [(set (match_operand:SI 0 "register_operand" "=r")
2544 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2546 (plus:SI (match_dup 1)
2547 (match_operand:SI 2 "post_cint_operand" "")))]
2551 if (INTVAL (operands[2]) > 0)
2552 return \"{ldwm|ldw,ma} %2(%1),%0\";
2553 return \"{ldws|ldw},ma %2(%1),%0\";
2555 [(set_attr "type" "load")
2556 (set_attr "length" "4")])
2558 (define_expand "post_store"
2559 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2560 (match_operand 1 "reg_or_0_operand" ""))
2563 (match_operand 2 "post_cint_operand" "")))])]
2569 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2572 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2576 (define_insn "post_stw"
2577 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2578 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2580 (plus:SI (match_dup 0)
2581 (match_operand:SI 2 "post_cint_operand" "")))]
2585 if (INTVAL (operands[2]) > 0)
2586 return \"{stwm|stw,ma} %r1,%2(%0)\";
2587 return \"{stws|stw},ma %r1,%2(%0)\";
2589 [(set_attr "type" "store")
2590 (set_attr "length" "4")])
2592 (define_insn "post_std"
2593 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2594 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2596 (plus:DI (match_dup 0)
2597 (match_operand:DI 2 "post_cint_operand" "")))]
2600 [(set_attr "type" "store")
2601 (set_attr "length" "4")])
2603 ;; For loading the address of a label while generating PIC code.
2604 ;; Note since this pattern can be created at reload time (via movsi), all
2605 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2607 [(set (match_operand 0 "pmode_register_operand" "=a")
2608 (match_operand 1 "pic_label_operand" ""))]
2613 extern FILE *asm_out_file;
2615 xoperands[0] = operands[0];
2616 xoperands[1] = operands[1];
2617 xoperands[2] = gen_label_rtx ();
2619 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2620 CODE_LABEL_NUMBER (xoperands[2]));
2621 output_asm_insn (\"mfia %0\", xoperands);
2623 /* If we're trying to load the address of a label that happens to be
2624 close, then we can use a shorter sequence. */
2625 if (GET_CODE (operands[1]) == LABEL_REF
2626 && INSN_ADDRESSES_SET_P ()
2627 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2628 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2629 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2632 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2633 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2637 [(set_attr "type" "multi")
2638 (set_attr "length" "12")]) ; 8 or 12
2641 [(set (match_operand 0 "pmode_register_operand" "=a")
2642 (match_operand 1 "pic_label_operand" ""))]
2647 extern FILE *asm_out_file;
2649 xoperands[0] = operands[0];
2650 xoperands[1] = operands[1];
2651 xoperands[2] = gen_label_rtx ();
2653 output_asm_insn (\"bl .+8,%0\", xoperands);
2654 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2655 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2656 CODE_LABEL_NUMBER (xoperands[2]));
2658 /* If we're trying to load the address of a label that happens to be
2659 close, then we can use a shorter sequence. */
2660 if (GET_CODE (operands[1]) == LABEL_REF
2661 && INSN_ADDRESSES_SET_P ()
2662 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2663 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2664 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2667 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2668 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2672 [(set_attr "type" "multi")
2673 (set_attr "length" "16")]) ; 12 or 16
2676 [(set (match_operand:SI 0 "register_operand" "=a")
2677 (plus:SI (match_operand:SI 1 "register_operand" "r")
2678 (high:SI (match_operand 2 "" ""))))]
2679 "symbolic_operand (operands[2], Pmode)
2680 && ! function_label_operand (operands[2], Pmode)
2683 [(set_attr "type" "binary")
2684 (set_attr "length" "4")])
2687 [(set (match_operand:DI 0 "register_operand" "=a")
2688 (plus:DI (match_operand:DI 1 "register_operand" "r")
2689 (high:DI (match_operand 2 "" ""))))]
2690 "symbolic_operand (operands[2], Pmode)
2691 && ! function_label_operand (operands[2], Pmode)
2695 [(set_attr "type" "binary")
2696 (set_attr "length" "4")])
2698 ;; Always use addil rather than ldil;add sequences. This allows the
2699 ;; HP linker to eliminate the dp relocation if the symbolic operand
2700 ;; lives in the TEXT space.
2702 [(set (match_operand:SI 0 "register_operand" "=a")
2703 (high:SI (match_operand 1 "" "")))]
2704 "symbolic_operand (operands[1], Pmode)
2705 && ! function_label_operand (operands[1], Pmode)
2706 && ! read_only_operand (operands[1], Pmode)
2710 if (TARGET_LONG_LOAD_STORE)
2711 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2713 return \"addil LR'%H1,%%r27\";
2715 [(set_attr "type" "binary")
2716 (set (attr "length")
2717 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2722 ;; This is for use in the prologue/epilogue code. We need it
2723 ;; to add large constants to a stack pointer or frame pointer.
2724 ;; Because of the additional %r1 pressure, we probably do not
2725 ;; want to use this in general code, so make it available
2726 ;; only after reload.
2728 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2729 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2730 (high:SI (match_operand 2 "const_int_operand" ""))))]
2734 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2735 [(set_attr "type" "binary,binary")
2736 (set_attr "length" "4,8")])
2739 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2740 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2741 (high:DI (match_operand 2 "const_int_operand" ""))))]
2742 "reload_completed && TARGET_64BIT"
2745 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2746 [(set_attr "type" "binary,binary")
2747 (set_attr "length" "4,8")])
2750 [(set (match_operand:SI 0 "register_operand" "=r")
2751 (high:SI (match_operand 1 "" "")))]
2752 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2753 && !is_function_label_plus_const (operands[1])"
2756 if (symbolic_operand (operands[1], Pmode))
2757 return \"ldil LR'%H1,%0\";
2759 return \"ldil L'%G1,%0\";
2761 [(set_attr "type" "move")
2762 (set_attr "length" "4")])
2765 [(set (match_operand:DI 0 "register_operand" "=r")
2766 (high:DI (match_operand 1 "const_int_operand" "")))]
2769 [(set_attr "type" "move")
2770 (set_attr "length" "4")])
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2775 (match_operand:DI 2 "const_int_operand" "i")))]
2778 [(set_attr "type" "move")
2779 (set_attr "length" "4")])
2782 [(set (match_operand:SI 0 "register_operand" "=r")
2783 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2784 (match_operand:SI 2 "immediate_operand" "i")))]
2785 "!is_function_label_plus_const (operands[2])"
2788 if (flag_pic && symbolic_operand (operands[2], Pmode))
2790 else if (symbolic_operand (operands[2], Pmode))
2791 return \"ldo RR'%G2(%1),%0\";
2793 return \"ldo R'%G2(%1),%0\";
2795 [(set_attr "type" "move")
2796 (set_attr "length" "4")])
2798 ;; Now that a symbolic_address plus a constant is broken up early
2799 ;; in the compilation phase (for better CSE) we need a special
2800 ;; combiner pattern to load the symbolic address plus the constant
2801 ;; in only 2 instructions. (For cases where the symbolic address
2802 ;; was not a common subexpression.)
2804 [(set (match_operand:SI 0 "register_operand" "")
2805 (match_operand:SI 1 "symbolic_operand" ""))
2806 (clobber (match_operand:SI 2 "register_operand" ""))]
2807 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2808 [(set (match_dup 2) (high:SI (match_dup 1)))
2809 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2812 ;; hppa_legitimize_address goes to a great deal of trouble to
2813 ;; create addresses which use indexing. In some cases, this
2814 ;; is a lose because there isn't any store instructions which
2815 ;; allow indexed addresses (with integer register source).
2817 ;; These define_splits try to turn a 3 insn store into
2818 ;; a 2 insn store with some creative RTL rewriting.
2820 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2821 (match_operand:SI 1 "shadd_operand" ""))
2822 (plus:SI (match_operand:SI 2 "register_operand" "")
2823 (match_operand:SI 3 "const_int_operand" ""))))
2824 (match_operand:SI 4 "register_operand" ""))
2825 (clobber (match_operand:SI 5 "register_operand" ""))]
2827 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2829 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2833 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2834 (match_operand:SI 1 "shadd_operand" ""))
2835 (plus:SI (match_operand:SI 2 "register_operand" "")
2836 (match_operand:SI 3 "const_int_operand" ""))))
2837 (match_operand:HI 4 "register_operand" ""))
2838 (clobber (match_operand:SI 5 "register_operand" ""))]
2840 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2842 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2846 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2847 (match_operand:SI 1 "shadd_operand" ""))
2848 (plus:SI (match_operand:SI 2 "register_operand" "")
2849 (match_operand:SI 3 "const_int_operand" ""))))
2850 (match_operand:QI 4 "register_operand" ""))
2851 (clobber (match_operand:SI 5 "register_operand" ""))]
2853 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2855 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2858 (define_expand "movhi"
2859 [(set (match_operand:HI 0 "general_operand" "")
2860 (match_operand:HI 1 "general_operand" ""))]
2864 if (emit_move_sequence (operands, HImode, 0))
2869 [(set (match_operand:HI 0 "move_dest_operand"
2870 "=r,r,r,r,r,Q,!*q,!*f")
2871 (match_operand:HI 1 "move_src_operand"
2872 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2873 "register_operand (operands[0], HImode)
2874 || reg_or_0_operand (operands[1], HImode)"
2879 {zdepi|depwi,z} %Z1,%0
2884 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2885 (set_attr "pa_combine_type" "addmove")
2886 (set_attr "length" "4,4,4,4,4,4,4,4")])
2889 [(set (match_operand:HI 0 "register_operand" "=r")
2890 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2891 (match_operand:SI 2 "int5_operand" "L"))))
2893 (plus:SI (match_dup 1) (match_dup 2)))]
2895 "{ldhs|ldh},mb %2(%1),%0"
2896 [(set_attr "type" "load")
2897 (set_attr "length" "4")])
2900 [(set (match_operand:HI 0 "register_operand" "=r")
2901 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2902 (match_operand:DI 2 "int5_operand" "L"))))
2904 (plus:DI (match_dup 1) (match_dup 2)))]
2907 [(set_attr "type" "load")
2908 (set_attr "length" "4")])
2910 ; And a zero extended variant.
2912 [(set (match_operand:DI 0 "register_operand" "=r")
2913 (zero_extend:DI (mem:HI
2915 (match_operand:DI 1 "register_operand" "+r")
2916 (match_operand:DI 2 "int5_operand" "L")))))
2918 (plus:DI (match_dup 1) (match_dup 2)))]
2921 [(set_attr "type" "load")
2922 (set_attr "length" "4")])
2925 [(set (match_operand:SI 0 "register_operand" "=r")
2926 (zero_extend:SI (mem:HI
2928 (match_operand:SI 1 "register_operand" "+r")
2929 (match_operand:SI 2 "int5_operand" "L")))))
2931 (plus:SI (match_dup 1) (match_dup 2)))]
2933 "{ldhs|ldh},mb %2(%1),%0"
2934 [(set_attr "type" "load")
2935 (set_attr "length" "4")])
2938 [(set (match_operand:SI 0 "register_operand" "=r")
2939 (zero_extend:SI (mem:HI
2941 (match_operand:DI 1 "register_operand" "+r")
2942 (match_operand:DI 2 "int5_operand" "L")))))
2944 (plus:DI (match_dup 1) (match_dup 2)))]
2947 [(set_attr "type" "load")
2948 (set_attr "length" "4")])
2951 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2952 (match_operand:SI 1 "int5_operand" "L")))
2953 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2955 (plus:SI (match_dup 0) (match_dup 1)))]
2957 "{sths|sth},mb %r2,%1(%0)"
2958 [(set_attr "type" "store")
2959 (set_attr "length" "4")])
2962 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2963 (match_operand:DI 1 "int5_operand" "L")))
2964 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2966 (plus:DI (match_dup 0) (match_dup 1)))]
2969 [(set_attr "type" "store")
2970 (set_attr "length" "4")])
2973 [(set (match_operand:HI 0 "register_operand" "=r")
2974 (plus:HI (match_operand:HI 1 "register_operand" "r")
2975 (match_operand 2 "const_int_operand" "J")))]
2978 [(set_attr "type" "binary")
2979 (set_attr "pa_combine_type" "addmove")
2980 (set_attr "length" "4")])
2982 (define_expand "movqi"
2983 [(set (match_operand:QI 0 "general_operand" "")
2984 (match_operand:QI 1 "general_operand" ""))]
2988 if (emit_move_sequence (operands, QImode, 0))
2993 [(set (match_operand:QI 0 "move_dest_operand"
2994 "=r,r,r,r,r,Q,!*q,!*f")
2995 (match_operand:QI 1 "move_src_operand"
2996 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2997 "register_operand (operands[0], QImode)
2998 || reg_or_0_operand (operands[1], QImode)"
3003 {zdepi|depwi,z} %Z1,%0
3008 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
3009 (set_attr "pa_combine_type" "addmove")
3010 (set_attr "length" "4,4,4,4,4,4,4,4")])
3013 [(set (match_operand:QI 0 "register_operand" "=r")
3014 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3015 (match_operand:SI 2 "int5_operand" "L"))))
3016 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3018 "{ldbs|ldb},mb %2(%1),%0"
3019 [(set_attr "type" "load")
3020 (set_attr "length" "4")])
3023 [(set (match_operand:QI 0 "register_operand" "=r")
3024 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3025 (match_operand:DI 2 "int5_operand" "L"))))
3026 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3029 [(set_attr "type" "load")
3030 (set_attr "length" "4")])
3032 ; Now the same thing with zero extensions.
3034 [(set (match_operand:DI 0 "register_operand" "=r")
3035 (zero_extend:DI (mem:QI (plus:DI
3036 (match_operand:DI 1 "register_operand" "+r")
3037 (match_operand:DI 2 "int5_operand" "L")))))
3038 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3041 [(set_attr "type" "load")
3042 (set_attr "length" "4")])
3045 [(set (match_operand:SI 0 "register_operand" "=r")
3046 (zero_extend:SI (mem:QI (plus:SI
3047 (match_operand:SI 1 "register_operand" "+r")
3048 (match_operand:SI 2 "int5_operand" "L")))))
3049 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3051 "{ldbs|ldb},mb %2(%1),%0"
3052 [(set_attr "type" "load")
3053 (set_attr "length" "4")])
3056 [(set (match_operand:SI 0 "register_operand" "=r")
3057 (zero_extend:SI (mem:QI (plus:DI
3058 (match_operand:DI 1 "register_operand" "+r")
3059 (match_operand:DI 2 "int5_operand" "L")))))
3060 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3063 [(set_attr "type" "load")
3064 (set_attr "length" "4")])
3067 [(set (match_operand:HI 0 "register_operand" "=r")
3068 (zero_extend:HI (mem:QI (plus:SI
3069 (match_operand:SI 1 "register_operand" "+r")
3070 (match_operand:SI 2 "int5_operand" "L")))))
3071 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3073 "{ldbs|ldb},mb %2(%1),%0"
3074 [(set_attr "type" "load")
3075 (set_attr "length" "4")])
3078 [(set (match_operand:HI 0 "register_operand" "=r")
3079 (zero_extend:HI (mem:QI (plus:DI
3080 (match_operand:DI 1 "register_operand" "+r")
3081 (match_operand:DI 2 "int5_operand" "L")))))
3082 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3085 [(set_attr "type" "load")
3086 (set_attr "length" "4")])
3089 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3090 (match_operand:SI 1 "int5_operand" "L")))
3091 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3093 (plus:SI (match_dup 0) (match_dup 1)))]
3095 "{stbs|stb},mb %r2,%1(%0)"
3096 [(set_attr "type" "store")
3097 (set_attr "length" "4")])
3100 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3101 (match_operand:DI 1 "int5_operand" "L")))
3102 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3104 (plus:DI (match_dup 0) (match_dup 1)))]
3107 [(set_attr "type" "store")
3108 (set_attr "length" "4")])
3110 ;; The definition of this insn does not really explain what it does,
3111 ;; but it should suffice that anything generated as this insn will be
3112 ;; recognized as a movstrsi operation, and that it will not successfully
3113 ;; combine with anything.
3114 (define_expand "movstrsi"
3115 [(parallel [(set (match_operand:BLK 0 "" "")
3116 (match_operand:BLK 1 "" ""))
3117 (clobber (match_dup 4))
3118 (clobber (match_dup 5))
3119 (clobber (match_dup 6))
3120 (clobber (match_dup 7))
3121 (clobber (match_dup 8))
3122 (use (match_operand:SI 2 "arith_operand" ""))
3123 (use (match_operand:SI 3 "const_int_operand" ""))])]
3124 "!TARGET_64BIT && optimize > 0"
3129 /* HP provides very fast block move library routine for the PA;
3130 this routine includes:
3132 4x4 byte at a time block moves,
3133 1x4 byte at a time with alignment checked at runtime with
3134 attempts to align the source and destination as needed
3137 With that in mind, here's the heuristics to try and guess when
3138 the inlined block move will be better than the library block
3141 If the size isn't constant, then always use the library routines.
3143 If the size is large in respect to the known alignment, then use
3144 the library routines.
3146 If the size is small in respect to the known alignment, then open
3147 code the copy (since that will lead to better scheduling).
3149 Else use the block move pattern. */
3151 /* Undetermined size, use the library routine. */
3152 if (GET_CODE (operands[2]) != CONST_INT)
3155 size = INTVAL (operands[2]);
3156 align = INTVAL (operands[3]);
3157 align = align > 4 ? 4 : align;
3159 /* If size/alignment is large, then use the library routines. */
3160 if (size / align > 16)
3163 /* This does happen, but not often enough to worry much about. */
3164 if (size / align < MOVE_RATIO)
3167 /* Fall through means we're going to use our block move pattern. */
3169 = replace_equiv_address (operands[0],
3170 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3172 = replace_equiv_address (operands[1],
3173 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3174 operands[4] = gen_reg_rtx (SImode);
3175 operands[5] = gen_reg_rtx (SImode);
3176 operands[6] = gen_reg_rtx (SImode);
3177 operands[7] = gen_reg_rtx (SImode);
3178 operands[8] = gen_reg_rtx (SImode);
3181 ;; The operand constraints are written like this to support both compile-time
3182 ;; and run-time determined byte counts. The expander and output_block_move
3183 ;; only support compile-time determined counts at this time.
3185 ;; If the count is run-time determined, the register with the byte count
3186 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3188 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3189 ;; broke this semantic for pseudo registers. We can't use match_scratch
3190 ;; as this requires two registers in the class R1_REGS when the MEMs for
3191 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3192 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3193 ;; respectively. We then split or peephole optimize after reload.
3194 (define_insn "movstrsi_prereload"
3195 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3196 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3197 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3198 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3199 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3200 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3201 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3202 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3203 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3206 [(set_attr "type" "multi,multi")])
3209 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3210 (match_operand:BLK 1 "memory_operand" ""))
3211 (clobber (match_operand:SI 2 "register_operand" ""))
3212 (clobber (match_operand:SI 3 "register_operand" ""))
3213 (clobber (match_operand:SI 6 "register_operand" ""))
3214 (clobber (match_operand:SI 7 "register_operand" ""))
3215 (clobber (match_operand:SI 8 "register_operand" ""))
3216 (use (match_operand:SI 4 "arith_operand" ""))
3217 (use (match_operand:SI 5 "const_int_operand" ""))])]
3218 "!TARGET_64BIT && reload_completed && !flag_peephole2
3219 && GET_CODE (operands[0]) == MEM
3220 && register_operand (XEXP (operands[0], 0), SImode)
3221 && GET_CODE (operands[1]) == MEM
3222 && register_operand (XEXP (operands[1], 0), SImode)"
3223 [(set (match_dup 7) (match_dup 9))
3224 (set (match_dup 8) (match_dup 10))
3225 (parallel [(set (match_dup 0) (match_dup 1))
3226 (clobber (match_dup 2))
3227 (clobber (match_dup 3))
3228 (clobber (match_dup 6))
3229 (clobber (match_dup 7))
3230 (clobber (match_dup 8))
3236 operands[9] = XEXP (operands[0], 0);
3237 operands[10] = XEXP (operands[1], 0);
3238 operands[0] = replace_equiv_address (operands[0], operands[7]);
3239 operands[1] = replace_equiv_address (operands[1], operands[8]);
3243 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3244 (match_operand:BLK 1 "memory_operand" ""))
3245 (clobber (match_operand:SI 2 "register_operand" ""))
3246 (clobber (match_operand:SI 3 "register_operand" ""))
3247 (clobber (match_operand:SI 6 "register_operand" ""))
3248 (clobber (match_operand:SI 7 "register_operand" ""))
3249 (clobber (match_operand:SI 8 "register_operand" ""))
3250 (use (match_operand:SI 4 "arith_operand" ""))
3251 (use (match_operand:SI 5 "const_int_operand" ""))])]
3253 && GET_CODE (operands[0]) == MEM
3254 && register_operand (XEXP (operands[0], 0), SImode)
3255 && GET_CODE (operands[1]) == MEM
3256 && register_operand (XEXP (operands[1], 0), SImode)"
3257 [(parallel [(set (match_dup 0) (match_dup 1))
3258 (clobber (match_dup 2))
3259 (clobber (match_dup 3))
3260 (clobber (match_dup 6))
3261 (clobber (match_dup 7))
3262 (clobber (match_dup 8))
3268 rtx addr = XEXP (operands[0], 0);
3269 if (dead_or_set_p (curr_insn, addr))
3273 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3274 operands[0] = replace_equiv_address (operands[0], operands[7]);
3277 addr = XEXP (operands[1], 0);
3278 if (dead_or_set_p (curr_insn, addr))
3282 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3283 operands[1] = replace_equiv_address (operands[1], operands[8]);
3287 (define_insn "movstrsi_postreload"
3288 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3289 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3290 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3291 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3292 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3293 (clobber (match_dup 0))
3294 (clobber (match_dup 1))
3295 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3296 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3298 "!TARGET_64BIT && reload_completed"
3299 "* return output_block_move (operands, !which_alternative);"
3300 [(set_attr "type" "multi,multi")])
3302 (define_expand "movstrdi"
3303 [(parallel [(set (match_operand:BLK 0 "" "")
3304 (match_operand:BLK 1 "" ""))
3305 (clobber (match_dup 4))
3306 (clobber (match_dup 5))
3307 (clobber (match_dup 6))
3308 (clobber (match_dup 7))
3309 (clobber (match_dup 8))
3310 (use (match_operand:DI 2 "arith_operand" ""))
3311 (use (match_operand:DI 3 "const_int_operand" ""))])]
3312 "TARGET_64BIT && optimize > 0"
3317 /* HP provides very fast block move library routine for the PA;
3318 this routine includes:
3320 4x4 byte at a time block moves,
3321 1x4 byte at a time with alignment checked at runtime with
3322 attempts to align the source and destination as needed
3325 With that in mind, here's the heuristics to try and guess when
3326 the inlined block move will be better than the library block
3329 If the size isn't constant, then always use the library routines.
3331 If the size is large in respect to the known alignment, then use
3332 the library routines.
3334 If the size is small in respect to the known alignment, then open
3335 code the copy (since that will lead to better scheduling).
3337 Else use the block move pattern. */
3339 /* Undetermined size, use the library routine. */
3340 if (GET_CODE (operands[2]) != CONST_INT)
3343 size = INTVAL (operands[2]);
3344 align = INTVAL (operands[3]);
3345 align = align > 8 ? 8 : align;
3347 /* If size/alignment is large, then use the library routines. */
3348 if (size / align > 16)
3351 /* This does happen, but not often enough to worry much about. */
3352 if (size / align < MOVE_RATIO)
3355 /* Fall through means we're going to use our block move pattern. */
3357 = replace_equiv_address (operands[0],
3358 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3360 = replace_equiv_address (operands[1],
3361 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3362 operands[4] = gen_reg_rtx (DImode);
3363 operands[5] = gen_reg_rtx (DImode);
3364 operands[6] = gen_reg_rtx (DImode);
3365 operands[7] = gen_reg_rtx (DImode);
3366 operands[8] = gen_reg_rtx (DImode);
3369 ;; The operand constraints are written like this to support both compile-time
3370 ;; and run-time determined byte counts. The expander and output_block_move
3371 ;; only support compile-time determined counts at this time.
3373 ;; If the count is run-time determined, the register with the byte count
3374 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3376 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3377 ;; broke this semantic for pseudo registers. We can't use match_scratch
3378 ;; as this requires two registers in the class R1_REGS when the MEMs for
3379 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3380 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3381 ;; respectively. We then split or peephole optimize after reload.
3382 (define_insn "movstrdi_prereload"
3383 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3384 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3385 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3386 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3387 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3388 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3389 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3390 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3391 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3394 [(set_attr "type" "multi,multi")])
3397 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3398 (match_operand:BLK 1 "memory_operand" ""))
3399 (clobber (match_operand:DI 2 "register_operand" ""))
3400 (clobber (match_operand:DI 3 "register_operand" ""))
3401 (clobber (match_operand:DI 6 "register_operand" ""))
3402 (clobber (match_operand:DI 7 "register_operand" ""))
3403 (clobber (match_operand:DI 8 "register_operand" ""))
3404 (use (match_operand:DI 4 "arith_operand" ""))
3405 (use (match_operand:DI 5 "const_int_operand" ""))])]
3406 "TARGET_64BIT && reload_completed && !flag_peephole2
3407 && GET_CODE (operands[0]) == MEM
3408 && register_operand (XEXP (operands[0], 0), DImode)
3409 && GET_CODE (operands[1]) == MEM
3410 && register_operand (XEXP (operands[1], 0), DImode)"
3411 [(set (match_dup 7) (match_dup 9))
3412 (set (match_dup 8) (match_dup 10))
3413 (parallel [(set (match_dup 0) (match_dup 1))
3414 (clobber (match_dup 2))
3415 (clobber (match_dup 3))
3416 (clobber (match_dup 6))
3417 (clobber (match_dup 7))
3418 (clobber (match_dup 8))
3424 operands[9] = XEXP (operands[0], 0);
3425 operands[10] = XEXP (operands[1], 0);
3426 operands[0] = replace_equiv_address (operands[0], operands[7]);
3427 operands[1] = replace_equiv_address (operands[1], operands[8]);
3431 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3432 (match_operand:BLK 1 "memory_operand" ""))
3433 (clobber (match_operand:DI 2 "register_operand" ""))
3434 (clobber (match_operand:DI 3 "register_operand" ""))
3435 (clobber (match_operand:DI 6 "register_operand" ""))
3436 (clobber (match_operand:DI 7 "register_operand" ""))
3437 (clobber (match_operand:DI 8 "register_operand" ""))
3438 (use (match_operand:DI 4 "arith_operand" ""))
3439 (use (match_operand:DI 5 "const_int_operand" ""))])]
3441 && GET_CODE (operands[0]) == MEM
3442 && register_operand (XEXP (operands[0], 0), DImode)
3443 && GET_CODE (operands[1]) == MEM
3444 && register_operand (XEXP (operands[1], 0), DImode)"
3445 [(parallel [(set (match_dup 0) (match_dup 1))
3446 (clobber (match_dup 2))
3447 (clobber (match_dup 3))
3448 (clobber (match_dup 6))
3449 (clobber (match_dup 7))
3450 (clobber (match_dup 8))
3456 rtx addr = XEXP (operands[0], 0);
3457 if (dead_or_set_p (curr_insn, addr))
3461 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3462 operands[0] = replace_equiv_address (operands[0], operands[7]);
3465 addr = XEXP (operands[1], 0);
3466 if (dead_or_set_p (curr_insn, addr))
3470 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3471 operands[1] = replace_equiv_address (operands[1], operands[8]);
3475 (define_insn "movstrdi_postreload"
3476 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3477 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3478 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3479 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3480 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3481 (clobber (match_dup 0))
3482 (clobber (match_dup 1))
3483 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3484 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3486 "TARGET_64BIT && reload_completed"
3487 "* return output_block_move (operands, !which_alternative);"
3488 [(set_attr "type" "multi,multi")])
3490 (define_expand "clrstrsi"
3491 [(parallel [(set (match_operand:BLK 0 "" "")
3493 (clobber (match_dup 3))
3494 (clobber (match_dup 4))
3495 (use (match_operand:SI 1 "arith_operand" ""))
3496 (use (match_operand:SI 2 "const_int_operand" ""))])]
3497 "!TARGET_64BIT && optimize > 0"
3502 /* Undetermined size, use the library routine. */
3503 if (GET_CODE (operands[1]) != CONST_INT)
3506 size = INTVAL (operands[1]);
3507 align = INTVAL (operands[2]);
3508 align = align > 4 ? 4 : align;
3510 /* If size/alignment is large, then use the library routines. */
3511 if (size / align > 16)
3514 /* This does happen, but not often enough to worry much about. */
3515 if (size / align < MOVE_RATIO)
3518 /* Fall through means we're going to use our block clear pattern. */
3520 = replace_equiv_address (operands[0],
3521 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3522 operands[3] = gen_reg_rtx (SImode);
3523 operands[4] = gen_reg_rtx (SImode);
3526 (define_insn "clrstrsi_prereload"
3527 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3529 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3530 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3531 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3532 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3535 [(set_attr "type" "multi,multi")])
3538 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3540 (clobber (match_operand:SI 1 "register_operand" ""))
3541 (clobber (match_operand:SI 4 "register_operand" ""))
3542 (use (match_operand:SI 2 "arith_operand" ""))
3543 (use (match_operand:SI 3 "const_int_operand" ""))])]
3544 "!TARGET_64BIT && reload_completed && !flag_peephole2
3545 && GET_CODE (operands[0]) == MEM
3546 && register_operand (XEXP (operands[0], 0), SImode)"
3547 [(set (match_dup 4) (match_dup 5))
3548 (parallel [(set (match_dup 0) (const_int 0))
3549 (clobber (match_dup 1))
3550 (clobber (match_dup 4))
3556 operands[5] = XEXP (operands[0], 0);
3557 operands[0] = replace_equiv_address (operands[0], operands[4]);
3561 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3563 (clobber (match_operand:SI 1 "register_operand" ""))
3564 (clobber (match_operand:SI 4 "register_operand" ""))
3565 (use (match_operand:SI 2 "arith_operand" ""))
3566 (use (match_operand:SI 3 "const_int_operand" ""))])]
3568 && GET_CODE (operands[0]) == MEM
3569 && register_operand (XEXP (operands[0], 0), SImode)"
3570 [(parallel [(set (match_dup 0) (const_int 0))
3571 (clobber (match_dup 1))
3572 (clobber (match_dup 4))
3578 rtx addr = XEXP (operands[0], 0);
3579 if (dead_or_set_p (curr_insn, addr))
3583 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3584 operands[0] = replace_equiv_address (operands[0], operands[4]);
3588 (define_insn "clrstrsi_postreload"
3589 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3591 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3592 (clobber (match_dup 0))
3593 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3594 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3596 "!TARGET_64BIT && reload_completed"
3597 "* return output_block_clear (operands, !which_alternative);"
3598 [(set_attr "type" "multi,multi")])
3600 (define_expand "clrstrdi"
3601 [(parallel [(set (match_operand:BLK 0 "" "")
3603 (clobber (match_dup 3))
3604 (clobber (match_dup 4))
3605 (use (match_operand:DI 1 "arith_operand" ""))
3606 (use (match_operand:DI 2 "const_int_operand" ""))])]
3607 "TARGET_64BIT && optimize > 0"
3612 /* Undetermined size, use the library routine. */
3613 if (GET_CODE (operands[1]) != CONST_INT)
3616 size = INTVAL (operands[1]);
3617 align = INTVAL (operands[2]);
3618 align = align > 8 ? 8 : align;
3620 /* If size/alignment is large, then use the library routines. */
3621 if (size / align > 16)
3624 /* This does happen, but not often enough to worry much about. */
3625 if (size / align < MOVE_RATIO)
3628 /* Fall through means we're going to use our block clear pattern. */
3630 = replace_equiv_address (operands[0],
3631 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3632 operands[3] = gen_reg_rtx (DImode);
3633 operands[4] = gen_reg_rtx (DImode);
3636 (define_insn "clrstrdi_prereload"
3637 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3639 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3640 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3641 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3642 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3645 [(set_attr "type" "multi,multi")])
3648 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3650 (clobber (match_operand:DI 1 "register_operand" ""))
3651 (clobber (match_operand:DI 4 "register_operand" ""))
3652 (use (match_operand:DI 2 "arith_operand" ""))
3653 (use (match_operand:DI 3 "const_int_operand" ""))])]
3654 "TARGET_64BIT && reload_completed && !flag_peephole2
3655 && GET_CODE (operands[0]) == MEM
3656 && register_operand (XEXP (operands[0], 0), DImode)"
3657 [(set (match_dup 4) (match_dup 5))
3658 (parallel [(set (match_dup 0) (const_int 0))
3659 (clobber (match_dup 1))
3660 (clobber (match_dup 4))
3666 operands[5] = XEXP (operands[0], 0);
3667 operands[0] = replace_equiv_address (operands[0], operands[4]);
3671 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3673 (clobber (match_operand:DI 1 "register_operand" ""))
3674 (clobber (match_operand:DI 4 "register_operand" ""))
3675 (use (match_operand:DI 2 "arith_operand" ""))
3676 (use (match_operand:DI 3 "const_int_operand" ""))])]
3678 && GET_CODE (operands[0]) == MEM
3679 && register_operand (XEXP (operands[0], 0), DImode)"
3680 [(parallel [(set (match_dup 0) (const_int 0))
3681 (clobber (match_dup 1))
3682 (clobber (match_dup 4))
3688 rtx addr = XEXP (operands[0], 0);
3689 if (dead_or_set_p (curr_insn, addr))
3693 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3694 operands[0] = replace_equiv_address (operands[0], operands[4]);
3698 (define_insn "clrstrdi_postreload"
3699 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3701 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3702 (clobber (match_dup 0))
3703 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3704 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3706 "TARGET_64BIT && reload_completed"
3707 "* return output_block_clear (operands, !which_alternative);"
3708 [(set_attr "type" "multi,multi")])
3710 ;; Floating point move insns
3712 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3713 ;; to be reloaded by putting the constant into memory when
3714 ;; reg is a floating point register.
3716 ;; For integer registers we use ldil;ldo to set the appropriate
3719 ;; This must come before the movdf pattern, and it must be present
3720 ;; to handle obscure reloading cases.
3722 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3723 (match_operand:DF 1 "" "?F,m"))]
3724 "GET_CODE (operands[1]) == CONST_DOUBLE
3725 && operands[1] != CONST0_RTX (DFmode)
3727 && !TARGET_SOFT_FLOAT"
3728 "* return (which_alternative == 0 ? output_move_double (operands)
3729 : \"fldd%F1 %1,%0\");"
3730 [(set_attr "type" "move,fpload")
3731 (set_attr "length" "16,4")])
3733 (define_expand "movdf"
3734 [(set (match_operand:DF 0 "general_operand" "")
3735 (match_operand:DF 1 "general_operand" ""))]
3739 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3740 operands[1] = force_const_mem (DFmode, operands[1]);
3742 if (emit_move_sequence (operands, DFmode, 0))
3746 ;; Reloading an SImode or DImode value requires a scratch register if
3747 ;; going in to or out of float point registers.
3749 (define_expand "reload_indf"
3750 [(set (match_operand:DF 0 "register_operand" "=Z")
3751 (match_operand:DF 1 "non_hard_reg_operand" ""))
3752 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3756 if (emit_move_sequence (operands, DFmode, operands[2]))
3759 /* We don't want the clobber emitted, so handle this ourselves. */
3760 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3764 (define_expand "reload_outdf"
3765 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3766 (match_operand:DF 1 "register_operand" "Z"))
3767 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3771 if (emit_move_sequence (operands, DFmode, operands[2]))
3774 /* We don't want the clobber emitted, so handle this ourselves. */
3775 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3780 [(set (match_operand:DF 0 "move_dest_operand"
3781 "=f,*r,Q,?o,?Q,f,*r,*r")
3782 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3783 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3784 "(register_operand (operands[0], DFmode)
3785 || reg_or_0_operand (operands[1], DFmode))
3786 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3787 && GET_CODE (operands[0]) == MEM)
3789 && !TARGET_SOFT_FLOAT"
3792 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3793 || operands[1] == CONST0_RTX (DFmode))
3794 return output_fp_move_double (operands);
3795 return output_move_double (operands);
3797 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3798 (set_attr "length" "4,8,4,8,16,4,8,16")])
3801 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3802 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3804 && !TARGET_DISABLE_INDEXING
3805 && reload_completed"
3807 [(set_attr "type" "fpstore")
3808 (set_attr "pa_combine_type" "addmove")
3809 (set_attr "length" "4")])
3812 [(set (match_operand:SI 0 "register_operand" "")
3813 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3815 (match_operand:SI 2 "register_operand" "")))
3816 (set (mem:DF (match_dup 0))
3817 (match_operand:DF 3 "register_operand" ""))]
3819 && REG_OK_FOR_BASE_P (operands[2])
3820 && FP_REGNO_P (REGNO (operands[3]))"
3821 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3823 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3828 [(set (match_operand:SI 0 "register_operand" "")
3829 (plus:SI (match_operand:SI 2 "register_operand" "")
3830 (mult:SI (match_operand:SI 1 "register_operand" "")
3832 (set (mem:DF (match_dup 0))
3833 (match_operand:DF 3 "register_operand" ""))]
3835 && REG_OK_FOR_BASE_P (operands[2])
3836 && FP_REGNO_P (REGNO (operands[3]))"
3837 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3839 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3844 [(set (match_operand:DI 0 "register_operand" "")
3845 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3847 (match_operand:DI 2 "register_operand" "")))
3848 (set (mem:DF (match_dup 0))
3849 (match_operand:DF 3 "register_operand" ""))]
3852 && REG_OK_FOR_BASE_P (operands[2])
3853 && FP_REGNO_P (REGNO (operands[3]))"
3854 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3856 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3861 [(set (match_operand:DI 0 "register_operand" "")
3862 (plus:DI (match_operand:DI 2 "register_operand" "")
3863 (mult:DI (match_operand:DI 1 "register_operand" "")
3865 (set (mem:DF (match_dup 0))
3866 (match_operand:DF 3 "register_operand" ""))]
3869 && REG_OK_FOR_BASE_P (operands[2])
3870 && FP_REGNO_P (REGNO (operands[3]))"
3871 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3873 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3878 [(set (match_operand:SI 0 "register_operand" "")
3879 (plus:SI (match_operand:SI 1 "register_operand" "")
3880 (match_operand:SI 2 "register_operand" "")))
3881 (set (mem:DF (match_dup 0))
3882 (match_operand:DF 3 "register_operand" ""))]
3884 && REG_OK_FOR_BASE_P (operands[1])
3885 && (TARGET_NO_SPACE_REGS
3886 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3887 && FP_REGNO_P (REGNO (operands[3]))"
3888 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3890 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3894 [(set (match_operand:SI 0 "register_operand" "")
3895 (plus:SI (match_operand:SI 1 "register_operand" "")
3896 (match_operand:SI 2 "register_operand" "")))
3897 (set (mem:DF (match_dup 0))
3898 (match_operand:DF 3 "register_operand" ""))]
3900 && REG_OK_FOR_BASE_P (operands[2])
3901 && (TARGET_NO_SPACE_REGS
3902 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3903 && FP_REGNO_P (REGNO (operands[3]))"
3904 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3906 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3910 [(set (match_operand:DI 0 "register_operand" "")
3911 (plus:DI (match_operand:DI 1 "register_operand" "")
3912 (match_operand:DI 2 "register_operand" "")))
3913 (set (mem:DF (match_dup 0))
3914 (match_operand:DF 3 "register_operand" ""))]
3917 && REG_OK_FOR_BASE_P (operands[1])
3918 && (TARGET_NO_SPACE_REGS
3919 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3920 && FP_REGNO_P (REGNO (operands[3]))"
3921 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3923 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3927 [(set (match_operand:DI 0 "register_operand" "")
3928 (plus:DI (match_operand:DI 1 "register_operand" "")
3929 (match_operand:DI 2 "register_operand" "")))
3930 (set (mem:DF (match_dup 0))
3931 (match_operand:DF 3 "register_operand" ""))]
3934 && REG_OK_FOR_BASE_P (operands[2])
3935 && (TARGET_NO_SPACE_REGS
3936 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3937 && FP_REGNO_P (REGNO (operands[3]))"
3938 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3940 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3944 [(set (match_operand:DF 0 "move_dest_operand"
3946 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3948 "(register_operand (operands[0], DFmode)
3949 || reg_or_0_operand (operands[1], DFmode))
3951 && TARGET_SOFT_FLOAT"
3954 return output_move_double (operands);
3956 [(set_attr "type" "move,store,store,load,load")
3957 (set_attr "length" "8,8,16,8,16")])
3960 [(set (match_operand:DF 0 "move_dest_operand"
3961 "=!*r,*r,*r,*r,*r,Q,!*q,f,f,T")
3962 (match_operand:DF 1 "move_src_operand"
3963 "!*r,J,N,K,RQ,*rM,!*rM,fM,RT,f"))]
3964 "(register_operand (operands[0], DFmode)
3965 || reg_or_0_operand (operands[1], DFmode))
3966 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3978 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3979 (set_attr "pa_combine_type" "addmove")
3980 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3983 (define_expand "movdi"
3984 [(set (match_operand:DI 0 "general_operand" "")
3985 (match_operand:DI 1 "general_operand" ""))]
3989 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3990 operands[1] = force_const_mem (DImode, operands[1]);
3992 if (emit_move_sequence (operands, DImode, 0))
3996 (define_expand "reload_indi"
3997 [(set (match_operand:DI 0 "register_operand" "=Z")
3998 (match_operand:DI 1 "non_hard_reg_operand" ""))
3999 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4003 if (emit_move_sequence (operands, DImode, operands[2]))
4006 /* We don't want the clobber emitted, so handle this ourselves. */
4007 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4011 (define_expand "reload_outdi"
4012 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4013 (match_operand:DI 1 "register_operand" "Z"))
4014 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4018 if (emit_move_sequence (operands, DImode, operands[2]))
4021 /* We don't want the clobber emitted, so handle this ourselves. */
4022 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4027 [(set (match_operand:DI 0 "register_operand" "=r")
4028 (high:DI (match_operand 1 "" "")))]
4032 rtx op0 = operands[0];
4033 rtx op1 = operands[1];
4035 if (GET_CODE (op1) == CONST_INT)
4037 operands[0] = operand_subword (op0, 1, 0, DImode);
4038 output_asm_insn (\"ldil L'%1,%0\", operands);
4040 operands[0] = operand_subword (op0, 0, 0, DImode);
4041 if (INTVAL (op1) < 0)
4042 output_asm_insn (\"ldi -1,%0\", operands);
4044 output_asm_insn (\"ldi 0,%0\", operands);
4047 else if (GET_CODE (op1) == CONST_DOUBLE)
4049 operands[0] = operand_subword (op0, 1, 0, DImode);
4050 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4051 output_asm_insn (\"ldil L'%1,%0\", operands);
4053 operands[0] = operand_subword (op0, 0, 0, DImode);
4054 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4055 output_asm_insn (singlemove_string (operands), operands);
4061 [(set_attr "type" "move")
4062 (set_attr "length" "8")])
4065 [(set (match_operand:DI 0 "move_dest_operand"
4066 "=r,o,Q,r,r,r,*f,*f,T")
4067 (match_operand:DI 1 "general_operand"
4068 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4069 "(register_operand (operands[0], DImode)
4070 || reg_or_0_operand (operands[1], DImode))
4072 && !TARGET_SOFT_FLOAT"
4075 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4076 || (operands[1] == CONST0_RTX (DImode)))
4077 return output_fp_move_double (operands);
4078 return output_move_double (operands);
4080 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4081 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4084 [(set (match_operand:DI 0 "move_dest_operand"
4085 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
4086 (match_operand:DI 1 "move_src_operand"
4087 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
4088 "(register_operand (operands[0], DImode)
4089 || reg_or_0_operand (operands[1], DImode))
4090 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4103 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
4104 (set_attr "pa_combine_type" "addmove")
4105 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
4108 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4109 (match_operand:DI 1 "register_operand" "f"))]
4112 && !TARGET_DISABLE_INDEXING
4113 && reload_completed"
4115 [(set_attr "type" "fpstore")
4116 (set_attr "pa_combine_type" "addmove")
4117 (set_attr "length" "4")])
4120 [(set (match_operand:DI 0 "register_operand" "")
4121 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4123 (match_operand:DI 2 "register_operand" "")))
4124 (set (mem:DI (match_dup 0))
4125 (match_operand:DI 3 "register_operand" ""))]
4128 && REG_OK_FOR_BASE_P (operands[2])
4129 && FP_REGNO_P (REGNO (operands[3]))"
4130 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4132 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4137 [(set (match_operand:DI 0 "register_operand" "")
4138 (plus:DI (match_operand:DI 2 "register_operand" "")
4139 (mult:DI (match_operand:DI 1 "register_operand" "")
4141 (set (mem:DI (match_dup 0))
4142 (match_operand:DI 3 "register_operand" ""))]
4145 && REG_OK_FOR_BASE_P (operands[2])
4146 && FP_REGNO_P (REGNO (operands[3]))"
4147 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4149 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4154 [(set (match_operand:DI 0 "register_operand" "")
4155 (plus:DI (match_operand:DI 1 "register_operand" "")
4156 (match_operand:DI 2 "register_operand" "")))
4157 (set (mem:DI (match_dup 0))
4158 (match_operand:DI 3 "register_operand" ""))]
4161 && REG_OK_FOR_BASE_P (operands[1])
4162 && (TARGET_NO_SPACE_REGS
4163 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4164 && FP_REGNO_P (REGNO (operands[3]))"
4165 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4167 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4171 [(set (match_operand:DI 0 "register_operand" "")
4172 (plus:DI (match_operand:DI 1 "register_operand" "")
4173 (match_operand:DI 2 "register_operand" "")))
4174 (set (mem:DI (match_dup 0))
4175 (match_operand:DI 3 "register_operand" ""))]
4178 && REG_OK_FOR_BASE_P (operands[2])
4179 && (TARGET_NO_SPACE_REGS
4180 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4181 && FP_REGNO_P (REGNO (operands[3]))"
4182 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4184 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4188 [(set (match_operand:DI 0 "move_dest_operand"
4190 (match_operand:DI 1 "general_operand"
4192 "(register_operand (operands[0], DImode)
4193 || reg_or_0_operand (operands[1], DImode))
4195 && TARGET_SOFT_FLOAT"
4198 return output_move_double (operands);
4200 [(set_attr "type" "move,store,store,load,load,multi")
4201 (set_attr "length" "8,8,16,8,16,16")])
4204 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4205 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4206 (match_operand:DI 2 "immediate_operand" "i,i")))]
4210 /* Don't output a 64 bit constant, since we can't trust the assembler to
4211 handle it correctly. */
4212 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4213 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4214 if (which_alternative == 1)
4215 output_asm_insn (\"copy %1,%0\", operands);
4216 return \"ldo R'%G2(%R1),%R0\";
4218 [(set_attr "type" "move,move")
4219 (set_attr "length" "4,8")])
4221 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4222 ;; to be reloaded by putting the constant into memory when
4223 ;; reg is a floating point register.
4225 ;; For integer registers we use ldil;ldo to set the appropriate
4228 ;; This must come before the movsf pattern, and it must be present
4229 ;; to handle obscure reloading cases.
4231 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4232 (match_operand:SF 1 "" "?F,m"))]
4233 "GET_CODE (operands[1]) == CONST_DOUBLE
4234 && operands[1] != CONST0_RTX (SFmode)
4235 && ! TARGET_SOFT_FLOAT"
4236 "* return (which_alternative == 0 ? singlemove_string (operands)
4237 : \" fldw%F1 %1,%0\");"
4238 [(set_attr "type" "move,fpload")
4239 (set_attr "length" "8,4")])
4241 (define_expand "movsf"
4242 [(set (match_operand:SF 0 "general_operand" "")
4243 (match_operand:SF 1 "general_operand" ""))]
4247 if (emit_move_sequence (operands, SFmode, 0))
4251 ;; Reloading an SImode or DImode value requires a scratch register if
4252 ;; going in to or out of float point registers.
4254 (define_expand "reload_insf"
4255 [(set (match_operand:SF 0 "register_operand" "=Z")
4256 (match_operand:SF 1 "non_hard_reg_operand" ""))
4257 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4261 if (emit_move_sequence (operands, SFmode, operands[2]))
4264 /* We don't want the clobber emitted, so handle this ourselves. */
4265 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4269 (define_expand "reload_outsf"
4270 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4271 (match_operand:SF 1 "register_operand" "Z"))
4272 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4276 if (emit_move_sequence (operands, SFmode, operands[2]))
4279 /* We don't want the clobber emitted, so handle this ourselves. */
4280 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4285 [(set (match_operand:SF 0 "move_dest_operand"
4287 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4288 "fG,!*rG,RQ,RQ,f,*rG"))]
4289 "(register_operand (operands[0], SFmode)
4290 || reg_or_0_operand (operands[1], SFmode))
4291 && !TARGET_SOFT_FLOAT"
4299 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4300 (set_attr "pa_combine_type" "addmove")
4301 (set_attr "length" "4,4,4,4,4,4")])
4304 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4305 (match_operand:SF 1 "register_operand" "f"))]
4307 && !TARGET_DISABLE_INDEXING
4308 && reload_completed"
4310 [(set_attr "type" "fpstore")
4311 (set_attr "pa_combine_type" "addmove")
4312 (set_attr "length" "4")])
4315 [(set (match_operand:SI 0 "register_operand" "")
4316 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4318 (match_operand:SI 2 "register_operand" "")))
4319 (set (mem:SF (match_dup 0))
4320 (match_operand:SF 3 "register_operand" ""))]
4322 && REG_OK_FOR_BASE_P (operands[2])
4323 && FP_REGNO_P (REGNO (operands[3]))"
4324 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4326 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4331 [(set (match_operand:SI 0 "register_operand" "")
4332 (plus:SI (match_operand:SI 2 "register_operand" "")
4333 (mult:SI (match_operand:SI 1 "register_operand" "")
4335 (set (mem:SF (match_dup 0))
4336 (match_operand:SF 3 "register_operand" ""))]
4338 && REG_OK_FOR_BASE_P (operands[2])
4339 && FP_REGNO_P (REGNO (operands[3]))"
4340 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4342 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4347 [(set (match_operand:DI 0 "register_operand" "")
4348 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4350 (match_operand:DI 2 "register_operand" "")))
4351 (set (mem:SF (match_dup 0))
4352 (match_operand:SF 3 "register_operand" ""))]
4355 && REG_OK_FOR_BASE_P (operands[2])
4356 && FP_REGNO_P (REGNO (operands[3]))"
4357 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4359 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4364 [(set (match_operand:DI 0 "register_operand" "")
4365 (plus:DI (match_operand:DI 2 "register_operand" "")
4366 (mult:DI (match_operand:DI 1 "register_operand" "")
4368 (set (mem:SF (match_dup 0))
4369 (match_operand:SF 3 "register_operand" ""))]
4372 && REG_OK_FOR_BASE_P (operands[2])
4373 && FP_REGNO_P (REGNO (operands[3]))"
4374 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4376 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4381 [(set (match_operand:SI 0 "register_operand" "")
4382 (plus:SI (match_operand:SI 1 "register_operand" "")
4383 (match_operand:SI 2 "register_operand" "")))
4384 (set (mem:SF (match_dup 0))
4385 (match_operand:SF 3 "register_operand" ""))]
4387 && REG_OK_FOR_BASE_P (operands[1])
4388 && (TARGET_NO_SPACE_REGS
4389 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4390 && FP_REGNO_P (REGNO (operands[3]))"
4391 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4393 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4397 [(set (match_operand:SI 0 "register_operand" "")
4398 (plus:SI (match_operand:SI 1 "register_operand" "")
4399 (match_operand:SI 2 "register_operand" "")))
4400 (set (mem:SF (match_dup 0))
4401 (match_operand:SF 3 "register_operand" ""))]
4403 && REG_OK_FOR_BASE_P (operands[2])
4404 && (TARGET_NO_SPACE_REGS
4405 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4406 && FP_REGNO_P (REGNO (operands[3]))"
4407 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4409 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4413 [(set (match_operand:DI 0 "register_operand" "")
4414 (plus:DI (match_operand:DI 1 "register_operand" "")
4415 (match_operand:DI 2 "register_operand" "")))
4416 (set (mem:SF (match_dup 0))
4417 (match_operand:SF 3 "register_operand" ""))]
4420 && REG_OK_FOR_BASE_P (operands[1])
4421 && (TARGET_NO_SPACE_REGS
4422 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4423 && FP_REGNO_P (REGNO (operands[3]))"
4424 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4426 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4430 [(set (match_operand:DI 0 "register_operand" "")
4431 (plus:DI (match_operand:DI 1 "register_operand" "")
4432 (match_operand:DI 2 "register_operand" "")))
4433 (set (mem:SF (match_dup 0))
4434 (match_operand:SF 3 "register_operand" ""))]
4437 && REG_OK_FOR_BASE_P (operands[2])
4438 && (TARGET_NO_SPACE_REGS
4439 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4440 && FP_REGNO_P (REGNO (operands[3]))"
4441 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4443 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4447 [(set (match_operand:SF 0 "move_dest_operand"
4449 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4451 "(register_operand (operands[0], SFmode)
4452 || reg_or_0_operand (operands[1], SFmode))
4453 && TARGET_SOFT_FLOAT"
4458 [(set_attr "type" "move,load,store")
4459 (set_attr "pa_combine_type" "addmove")
4460 (set_attr "length" "4,4,4")])
4464 ;;- zero extension instructions
4465 ;; We have define_expand for zero extension patterns to make sure the
4466 ;; operands get loaded into registers. The define_insns accept
4467 ;; memory operands. This gives us better overall code than just
4468 ;; having a pattern that does or does not accept memory operands.
4470 (define_expand "zero_extendqihi2"
4471 [(set (match_operand:HI 0 "register_operand" "")
4473 (match_operand:QI 1 "register_operand" "")))]
4478 [(set (match_operand:HI 0 "register_operand" "=r,r")
4480 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4481 "GET_CODE (operands[1]) != CONST_INT"
4483 {extru|extrw,u} %1,31,8,%0
4485 [(set_attr "type" "shift,load")
4486 (set_attr "length" "4,4")])
4488 (define_expand "zero_extendqisi2"
4489 [(set (match_operand:SI 0 "register_operand" "")
4491 (match_operand:QI 1 "register_operand" "")))]
4496 [(set (match_operand:SI 0 "register_operand" "=r,r")
4498 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4499 "GET_CODE (operands[1]) != CONST_INT"
4501 {extru|extrw,u} %1,31,8,%0
4503 [(set_attr "type" "shift,load")
4504 (set_attr "length" "4,4")])
4506 (define_expand "zero_extendhisi2"
4507 [(set (match_operand:SI 0 "register_operand" "")
4509 (match_operand:HI 1 "register_operand" "")))]
4514 [(set (match_operand:SI 0 "register_operand" "=r,r")
4516 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4517 "GET_CODE (operands[1]) != CONST_INT"
4519 {extru|extrw,u} %1,31,16,%0
4521 [(set_attr "type" "shift,load")
4522 (set_attr "length" "4,4")])
4524 (define_expand "zero_extendqidi2"
4525 [(set (match_operand:DI 0 "register_operand" "")
4527 (match_operand:QI 1 "register_operand" "")))]
4532 [(set (match_operand:DI 0 "register_operand" "=r,r")
4534 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4535 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4539 [(set_attr "type" "shift,load")
4540 (set_attr "length" "4,4")])
4542 (define_expand "zero_extendhidi2"
4543 [(set (match_operand:DI 0 "register_operand" "")
4545 (match_operand:HI 1 "register_operand" "")))]
4550 [(set (match_operand:DI 0 "register_operand" "=r,r")
4552 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4553 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4557 [(set_attr "type" "shift,load")
4558 (set_attr "length" "4,4")])
4560 (define_expand "zero_extendsidi2"
4561 [(set (match_operand:DI 0 "register_operand" "")
4563 (match_operand:SI 1 "register_operand" "")))]
4568 [(set (match_operand:DI 0 "register_operand" "=r,r")
4570 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4571 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4575 [(set_attr "type" "shift,load")
4576 (set_attr "length" "4,4")])
4578 ;;- sign extension instructions
4580 (define_insn "extendhisi2"
4581 [(set (match_operand:SI 0 "register_operand" "=r")
4582 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4584 "{extrs|extrw,s} %1,31,16,%0"
4585 [(set_attr "type" "shift")
4586 (set_attr "length" "4")])
4588 (define_insn "extendqihi2"
4589 [(set (match_operand:HI 0 "register_operand" "=r")
4590 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4592 "{extrs|extrw,s} %1,31,8,%0"
4593 [(set_attr "type" "shift")
4594 (set_attr "length" "4")])
4596 (define_insn "extendqisi2"
4597 [(set (match_operand:SI 0 "register_operand" "=r")
4598 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4600 "{extrs|extrw,s} %1,31,8,%0"
4601 [(set_attr "type" "shift")
4602 (set_attr "length" "4")])
4604 (define_insn "extendqidi2"
4605 [(set (match_operand:DI 0 "register_operand" "=r")
4606 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4608 "extrd,s %1,63,8,%0"
4609 [(set_attr "type" "shift")
4610 (set_attr "length" "4")])
4612 (define_insn "extendhidi2"
4613 [(set (match_operand:DI 0 "register_operand" "=r")
4614 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4616 "extrd,s %1,63,16,%0"
4617 [(set_attr "type" "shift")
4618 (set_attr "length" "4")])
4620 (define_insn "extendsidi2"
4621 [(set (match_operand:DI 0 "register_operand" "=r")
4622 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4624 "extrd,s %1,63,32,%0"
4625 [(set_attr "type" "shift")
4626 (set_attr "length" "4")])
4629 ;; Conversions between float and double.
4631 (define_insn "extendsfdf2"
4632 [(set (match_operand:DF 0 "register_operand" "=f")
4634 (match_operand:SF 1 "register_operand" "f")))]
4635 "! TARGET_SOFT_FLOAT"
4636 "{fcnvff|fcnv},sgl,dbl %1,%0"
4637 [(set_attr "type" "fpalu")
4638 (set_attr "length" "4")])
4640 (define_insn "truncdfsf2"
4641 [(set (match_operand:SF 0 "register_operand" "=f")
4643 (match_operand:DF 1 "register_operand" "f")))]
4644 "! TARGET_SOFT_FLOAT"
4645 "{fcnvff|fcnv},dbl,sgl %1,%0"
4646 [(set_attr "type" "fpalu")
4647 (set_attr "length" "4")])
4649 ;; Conversion between fixed point and floating point.
4650 ;; Note that among the fix-to-float insns
4651 ;; the ones that start with SImode come first.
4652 ;; That is so that an operand that is a CONST_INT
4653 ;; (and therefore lacks a specific machine mode).
4654 ;; will be recognized as SImode (which is always valid)
4655 ;; rather than as QImode or HImode.
4657 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4658 ;; to be reloaded by putting the constant into memory.
4659 ;; It must come before the more general floatsisf2 pattern.
4661 [(set (match_operand:SF 0 "register_operand" "=f")
4662 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4663 "! TARGET_SOFT_FLOAT"
4664 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4665 [(set_attr "type" "fpalu")
4666 (set_attr "length" "8")])
4668 (define_insn "floatsisf2"
4669 [(set (match_operand:SF 0 "register_operand" "=f")
4670 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4671 "! TARGET_SOFT_FLOAT"
4672 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4673 [(set_attr "type" "fpalu")
4674 (set_attr "length" "4")])
4676 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4677 ;; to be reloaded by putting the constant into memory.
4678 ;; It must come before the more general floatsidf2 pattern.
4680 [(set (match_operand:DF 0 "register_operand" "=f")
4681 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4682 "! TARGET_SOFT_FLOAT"
4683 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4684 [(set_attr "type" "fpalu")
4685 (set_attr "length" "8")])
4687 (define_insn "floatsidf2"
4688 [(set (match_operand:DF 0 "register_operand" "=f")
4689 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4690 "! TARGET_SOFT_FLOAT"
4691 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4692 [(set_attr "type" "fpalu")
4693 (set_attr "length" "4")])
4695 (define_expand "floatunssisf2"
4696 [(set (subreg:SI (match_dup 2) 4)
4697 (match_operand:SI 1 "register_operand" ""))
4698 (set (subreg:SI (match_dup 2) 0)
4700 (set (match_operand:SF 0 "register_operand" "")
4701 (float:SF (match_dup 2)))]
4702 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4707 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4710 operands[2] = gen_reg_rtx (DImode);
4713 (define_expand "floatunssidf2"
4714 [(set (subreg:SI (match_dup 2) 4)
4715 (match_operand:SI 1 "register_operand" ""))
4716 (set (subreg:SI (match_dup 2) 0)
4718 (set (match_operand:DF 0 "register_operand" "")
4719 (float:DF (match_dup 2)))]
4720 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4725 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4728 operands[2] = gen_reg_rtx (DImode);
4731 (define_insn "floatdisf2"
4732 [(set (match_operand:SF 0 "register_operand" "=f")
4733 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4734 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4735 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4736 [(set_attr "type" "fpalu")
4737 (set_attr "length" "4")])
4739 (define_insn "floatdidf2"
4740 [(set (match_operand:DF 0 "register_operand" "=f")
4741 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4742 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4743 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4744 [(set_attr "type" "fpalu")
4745 (set_attr "length" "4")])
4747 ;; Convert a float to an actual integer.
4748 ;; Truncation is performed as part of the conversion.
4750 (define_insn "fix_truncsfsi2"
4751 [(set (match_operand:SI 0 "register_operand" "=f")
4752 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4753 "! TARGET_SOFT_FLOAT"
4754 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4755 [(set_attr "type" "fpalu")
4756 (set_attr "length" "4")])
4758 (define_insn "fix_truncdfsi2"
4759 [(set (match_operand:SI 0 "register_operand" "=f")
4760 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4761 "! TARGET_SOFT_FLOAT"
4762 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4763 [(set_attr "type" "fpalu")
4764 (set_attr "length" "4")])
4766 (define_insn "fix_truncsfdi2"
4767 [(set (match_operand:DI 0 "register_operand" "=f")
4768 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4769 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4770 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4771 [(set_attr "type" "fpalu")
4772 (set_attr "length" "4")])
4774 (define_insn "fix_truncdfdi2"
4775 [(set (match_operand:DI 0 "register_operand" "=f")
4776 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4777 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4778 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4779 [(set_attr "type" "fpalu")
4780 (set_attr "length" "4")])
4782 (define_insn "floatunssidf2_pa20"
4783 [(set (match_operand:DF 0 "register_operand" "=f")
4784 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4785 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4787 [(set_attr "type" "fpalu")
4788 (set_attr "length" "4")])
4790 (define_insn "floatunssisf2_pa20"
4791 [(set (match_operand:SF 0 "register_operand" "=f")
4792 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4793 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4795 [(set_attr "type" "fpalu")
4796 (set_attr "length" "4")])
4798 (define_insn "floatunsdisf2"
4799 [(set (match_operand:SF 0 "register_operand" "=f")
4800 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4801 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4802 "fcnv,udw,sgl %1,%0"
4803 [(set_attr "type" "fpalu")
4804 (set_attr "length" "4")])
4806 (define_insn "floatunsdidf2"
4807 [(set (match_operand:DF 0 "register_operand" "=f")
4808 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4809 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4810 "fcnv,udw,dbl %1,%0"
4811 [(set_attr "type" "fpalu")
4812 (set_attr "length" "4")])
4814 (define_insn "fixuns_truncsfsi2"
4815 [(set (match_operand:SI 0 "register_operand" "=f")
4816 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4817 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4818 "fcnv,t,sgl,uw %1,%0"
4819 [(set_attr "type" "fpalu")
4820 (set_attr "length" "4")])
4822 (define_insn "fixuns_truncdfsi2"
4823 [(set (match_operand:SI 0 "register_operand" "=f")
4824 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4825 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4826 "fcnv,t,dbl,uw %1,%0"
4827 [(set_attr "type" "fpalu")
4828 (set_attr "length" "4")])
4830 (define_insn "fixuns_truncsfdi2"
4831 [(set (match_operand:DI 0 "register_operand" "=f")
4832 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4833 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4834 "fcnv,t,sgl,udw %1,%0"
4835 [(set_attr "type" "fpalu")
4836 (set_attr "length" "4")])
4838 (define_insn "fixuns_truncdfdi2"
4839 [(set (match_operand:DI 0 "register_operand" "=f")
4840 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4841 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4842 "fcnv,t,dbl,udw %1,%0"
4843 [(set_attr "type" "fpalu")
4844 (set_attr "length" "4")])
4846 ;;- arithmetic instructions
4848 (define_expand "adddi3"
4849 [(set (match_operand:DI 0 "register_operand" "")
4850 (plus:DI (match_operand:DI 1 "register_operand" "")
4851 (match_operand:DI 2 "adddi3_operand" "")))]
4856 [(set (match_operand:DI 0 "register_operand" "=r")
4857 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4858 (match_operand:DI 2 "arith11_operand" "rI")))]
4862 if (GET_CODE (operands[2]) == CONST_INT)
4864 if (INTVAL (operands[2]) >= 0)
4865 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4867 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4870 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4872 [(set_attr "type" "binary")
4873 (set_attr "length" "8")])
4876 [(set (match_operand:DI 0 "register_operand" "=r,r")
4877 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4878 (match_operand:DI 2 "arith_operand" "r,J")))]
4883 [(set_attr "type" "binary,binary")
4884 (set_attr "pa_combine_type" "addmove")
4885 (set_attr "length" "4,4")])
4888 [(set (match_operand:DI 0 "register_operand" "=r")
4889 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4890 (match_operand:DI 2 "register_operand" "r")))]
4893 [(set_attr "type" "binary")
4894 (set_attr "length" "4")])
4897 [(set (match_operand:SI 0 "register_operand" "=r")
4898 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4899 (match_operand:SI 2 "register_operand" "r")))]
4902 [(set_attr "type" "binary")
4903 (set_attr "length" "4")])
4905 ;; define_splits to optimize cases of adding a constant integer
4906 ;; to a register when the constant does not fit in 14 bits. */
4908 [(set (match_operand:SI 0 "register_operand" "")
4909 (plus:SI (match_operand:SI 1 "register_operand" "")
4910 (match_operand:SI 2 "const_int_operand" "")))
4911 (clobber (match_operand:SI 4 "register_operand" ""))]
4912 "! cint_ok_for_move (INTVAL (operands[2]))
4913 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4914 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4915 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4918 int val = INTVAL (operands[2]);
4919 int low = (val < 0) ? -0x2000 : 0x1fff;
4920 int rest = val - low;
4922 operands[2] = GEN_INT (rest);
4923 operands[3] = GEN_INT (low);
4927 [(set (match_operand:SI 0 "register_operand" "")
4928 (plus:SI (match_operand:SI 1 "register_operand" "")
4929 (match_operand:SI 2 "const_int_operand" "")))
4930 (clobber (match_operand:SI 4 "register_operand" ""))]
4931 "! cint_ok_for_move (INTVAL (operands[2]))"
4932 [(set (match_dup 4) (match_dup 2))
4933 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4937 HOST_WIDE_INT intval = INTVAL (operands[2]);
4939 /* Try dividing the constant by 2, then 4, and finally 8 to see
4940 if we can get a constant which can be loaded into a register
4941 in a single instruction (cint_ok_for_move).
4943 If that fails, try to negate the constant and subtract it
4944 from our input operand. */
4945 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4947 operands[2] = GEN_INT (intval / 2);
4948 operands[3] = const2_rtx;
4950 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
4952 operands[2] = GEN_INT (intval / 4);
4953 operands[3] = GEN_INT (4);
4955 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
4957 operands[2] = GEN_INT (intval / 8);
4958 operands[3] = GEN_INT (8);
4960 else if (cint_ok_for_move (-intval))
4962 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
4963 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
4970 (define_insn "addsi3"
4971 [(set (match_operand:SI 0 "register_operand" "=r,r")
4972 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
4973 (match_operand:SI 2 "arith_operand" "r,J")))]
4976 {addl|add,l} %1,%2,%0
4978 [(set_attr "type" "binary,binary")
4979 (set_attr "pa_combine_type" "addmove")
4980 (set_attr "length" "4,4")])
4982 (define_expand "subdi3"
4983 [(set (match_operand:DI 0 "register_operand" "")
4984 (minus:DI (match_operand:DI 1 "register_operand" "")
4985 (match_operand:DI 2 "register_operand" "")))]
4990 [(set (match_operand:DI 0 "register_operand" "=r")
4991 (minus:DI (match_operand:DI 1 "register_operand" "r")
4992 (match_operand:DI 2 "register_operand" "r")))]
4994 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
4995 [(set_attr "type" "binary")
4996 (set_attr "length" "8")])
4999 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5000 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5001 (match_operand:DI 2 "register_operand" "r,r,!r")))]
5007 [(set_attr "type" "binary,binary,move")
5008 (set_attr "length" "4,4,4")])
5010 (define_expand "subsi3"
5011 [(set (match_operand:SI 0 "register_operand" "")
5012 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5013 (match_operand:SI 2 "register_operand" "")))]
5018 [(set (match_operand:SI 0 "register_operand" "=r,r")
5019 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5020 (match_operand:SI 2 "register_operand" "r,r")))]
5025 [(set_attr "type" "binary,binary")
5026 (set_attr "length" "4,4")])
5029 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5030 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5031 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5037 [(set_attr "type" "binary,binary,move")
5038 (set_attr "length" "4,4,4")])
5040 ;; Clobbering a "register_operand" instead of a match_scratch
5041 ;; in operand3 of millicode calls avoids spilling %r1 and
5042 ;; produces better code.
5044 ;; The mulsi3 insns set up registers for the millicode call.
5045 (define_expand "mulsi3"
5046 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5047 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5048 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5049 (clobber (match_dup 3))
5050 (clobber (reg:SI 26))
5051 (clobber (reg:SI 25))
5052 (clobber (match_dup 4))])
5053 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5057 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5058 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5060 rtx scratch = gen_reg_rtx (DImode);
5061 operands[1] = force_reg (SImode, operands[1]);
5062 operands[2] = force_reg (SImode, operands[2]);
5063 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5064 emit_insn (gen_movsi (operands[0],
5065 gen_rtx_SUBREG (SImode, scratch,
5066 GET_MODE_SIZE (SImode))));
5069 operands[3] = gen_reg_rtx (SImode);
5072 (define_insn "umulsidi3"
5073 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5074 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5075 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5076 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5078 [(set_attr "type" "fpmuldbl")
5079 (set_attr "length" "4")])
5082 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5083 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5084 (match_operand:DI 2 "uint32_operand" "f")))]
5085 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5087 [(set_attr "type" "fpmuldbl")
5088 (set_attr "length" "4")])
5091 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5092 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5093 (match_operand:DI 2 "uint32_operand" "f")))]
5094 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5096 [(set_attr "type" "fpmuldbl")
5097 (set_attr "length" "4")])
5100 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5101 (clobber (match_operand:SI 0 "register_operand" "=a"))
5102 (clobber (reg:SI 26))
5103 (clobber (reg:SI 25))
5104 (clobber (reg:SI 31))]
5106 "* return output_mul_insn (0, insn);"
5107 [(set_attr "type" "milli")
5108 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5111 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5112 (clobber (match_operand:SI 0 "register_operand" "=a"))
5113 (clobber (reg:SI 26))
5114 (clobber (reg:SI 25))
5115 (clobber (reg:SI 2))]
5117 "* return output_mul_insn (0, insn);"
5118 [(set_attr "type" "milli")
5119 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5121 (define_expand "muldi3"
5122 [(set (match_operand:DI 0 "register_operand" "")
5123 (mult:DI (match_operand:DI 1 "register_operand" "")
5124 (match_operand:DI 2 "register_operand" "")))]
5125 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5128 rtx low_product = gen_reg_rtx (DImode);
5129 rtx cross_product1 = gen_reg_rtx (DImode);
5130 rtx cross_product2 = gen_reg_rtx (DImode);
5131 rtx cross_scratch = gen_reg_rtx (DImode);
5132 rtx cross_product = gen_reg_rtx (DImode);
5133 rtx op1l, op1r, op2l, op2r;
5134 rtx op1shifted, op2shifted;
5136 op1shifted = gen_reg_rtx (DImode);
5137 op2shifted = gen_reg_rtx (DImode);
5138 op1l = gen_reg_rtx (SImode);
5139 op1r = gen_reg_rtx (SImode);
5140 op2l = gen_reg_rtx (SImode);
5141 op2r = gen_reg_rtx (SImode);
5143 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5145 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5147 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5148 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5149 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5150 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5152 /* Emit multiplies for the cross products. */
5153 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5154 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5156 /* Emit a multiply for the low sub-word. */
5157 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5159 /* Sum the cross products and shift them into proper position. */
5160 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5161 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5163 /* Add the cross product to the low product and store the result
5164 into the output operand . */
5165 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5169 ;;; Division and mod.
5170 (define_expand "divsi3"
5171 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5172 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5173 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5174 (clobber (match_dup 3))
5175 (clobber (match_dup 4))
5176 (clobber (reg:SI 26))
5177 (clobber (reg:SI 25))
5178 (clobber (match_dup 5))])
5179 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5183 operands[3] = gen_reg_rtx (SImode);
5186 operands[5] = gen_rtx_REG (SImode, 2);
5187 operands[4] = operands[5];
5191 operands[5] = gen_rtx_REG (SImode, 31);
5192 operands[4] = gen_reg_rtx (SImode);
5194 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5200 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5201 (clobber (match_operand:SI 1 "register_operand" "=a"))
5202 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5203 (clobber (reg:SI 26))
5204 (clobber (reg:SI 25))
5205 (clobber (reg:SI 31))]
5208 return output_div_insn (operands, 0, insn);"
5209 [(set_attr "type" "milli")
5210 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5214 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5215 (clobber (match_operand:SI 1 "register_operand" "=a"))
5216 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5217 (clobber (reg:SI 26))
5218 (clobber (reg:SI 25))
5219 (clobber (reg:SI 2))]
5222 return output_div_insn (operands, 0, insn);"
5223 [(set_attr "type" "milli")
5224 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5226 (define_expand "udivsi3"
5227 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5228 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5229 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5230 (clobber (match_dup 3))
5231 (clobber (match_dup 4))
5232 (clobber (reg:SI 26))
5233 (clobber (reg:SI 25))
5234 (clobber (match_dup 5))])
5235 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5239 operands[3] = gen_reg_rtx (SImode);
5243 operands[5] = gen_rtx_REG (SImode, 2);
5244 operands[4] = operands[5];
5248 operands[5] = gen_rtx_REG (SImode, 31);
5249 operands[4] = gen_reg_rtx (SImode);
5251 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5257 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5258 (clobber (match_operand:SI 1 "register_operand" "=a"))
5259 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5260 (clobber (reg:SI 26))
5261 (clobber (reg:SI 25))
5262 (clobber (reg:SI 31))]
5265 return output_div_insn (operands, 1, insn);"
5266 [(set_attr "type" "milli")
5267 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5271 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5272 (clobber (match_operand:SI 1 "register_operand" "=a"))
5273 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5274 (clobber (reg:SI 26))
5275 (clobber (reg:SI 25))
5276 (clobber (reg:SI 2))]
5279 return output_div_insn (operands, 1, insn);"
5280 [(set_attr "type" "milli")
5281 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5283 (define_expand "modsi3"
5284 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5285 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5286 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5287 (clobber (match_dup 3))
5288 (clobber (match_dup 4))
5289 (clobber (reg:SI 26))
5290 (clobber (reg:SI 25))
5291 (clobber (match_dup 5))])
5292 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5298 operands[5] = gen_rtx_REG (SImode, 2);
5299 operands[4] = operands[5];
5303 operands[5] = gen_rtx_REG (SImode, 31);
5304 operands[4] = gen_reg_rtx (SImode);
5306 operands[3] = gen_reg_rtx (SImode);
5310 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5311 (clobber (match_operand:SI 0 "register_operand" "=a"))
5312 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5313 (clobber (reg:SI 26))
5314 (clobber (reg:SI 25))
5315 (clobber (reg:SI 31))]
5318 return output_mod_insn (0, insn);"
5319 [(set_attr "type" "milli")
5320 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5323 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5324 (clobber (match_operand:SI 0 "register_operand" "=a"))
5325 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5326 (clobber (reg:SI 26))
5327 (clobber (reg:SI 25))
5328 (clobber (reg:SI 2))]
5331 return output_mod_insn (0, insn);"
5332 [(set_attr "type" "milli")
5333 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5335 (define_expand "umodsi3"
5336 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5337 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5338 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5339 (clobber (match_dup 3))
5340 (clobber (match_dup 4))
5341 (clobber (reg:SI 26))
5342 (clobber (reg:SI 25))
5343 (clobber (match_dup 5))])
5344 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5350 operands[5] = gen_rtx_REG (SImode, 2);
5351 operands[4] = operands[5];
5355 operands[5] = gen_rtx_REG (SImode, 31);
5356 operands[4] = gen_reg_rtx (SImode);
5358 operands[3] = gen_reg_rtx (SImode);
5362 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5363 (clobber (match_operand:SI 0 "register_operand" "=a"))
5364 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5365 (clobber (reg:SI 26))
5366 (clobber (reg:SI 25))
5367 (clobber (reg:SI 31))]
5370 return output_mod_insn (1, insn);"
5371 [(set_attr "type" "milli")
5372 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5375 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5376 (clobber (match_operand:SI 0 "register_operand" "=a"))
5377 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5378 (clobber (reg:SI 26))
5379 (clobber (reg:SI 25))
5380 (clobber (reg:SI 2))]
5383 return output_mod_insn (1, insn);"
5384 [(set_attr "type" "milli")
5385 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5387 ;;- and instructions
5388 ;; We define DImode `and` so with DImode `not` we can get
5389 ;; DImode `andn`. Other combinations are possible.
5391 (define_expand "anddi3"
5392 [(set (match_operand:DI 0 "register_operand" "")
5393 (and:DI (match_operand:DI 1 "and_operand" "")
5394 (match_operand:DI 2 "and_operand" "")))]
5400 /* One operand must be a register operand. */
5401 if (!register_operand (operands[1], DImode)
5402 && !register_operand (operands[2], DImode))
5407 /* Both operands must be register operands. */
5408 if (!register_operand (operands[1], DImode)
5409 || !register_operand (operands[2], DImode))
5415 [(set (match_operand:DI 0 "register_operand" "=r")
5416 (and:DI (match_operand:DI 1 "register_operand" "%r")
5417 (match_operand:DI 2 "register_operand" "r")))]
5419 "and %1,%2,%0\;and %R1,%R2,%R0"
5420 [(set_attr "type" "binary")
5421 (set_attr "length" "8")])
5424 [(set (match_operand:DI 0 "register_operand" "=r,r")
5425 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5426 (match_operand:DI 2 "and_operand" "rO,P")))]
5428 "* return output_64bit_and (operands); "
5429 [(set_attr "type" "binary")
5430 (set_attr "length" "4")])
5432 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5433 ; constant with ldil;ldo.
5434 (define_insn "andsi3"
5435 [(set (match_operand:SI 0 "register_operand" "=r,r")
5436 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5437 (match_operand:SI 2 "and_operand" "rO,P")))]
5439 "* return output_and (operands); "
5440 [(set_attr "type" "binary,shift")
5441 (set_attr "length" "4,4")])
5444 [(set (match_operand:DI 0 "register_operand" "=r")
5445 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5446 (match_operand:DI 2 "register_operand" "r")))]
5448 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5449 [(set_attr "type" "binary")
5450 (set_attr "length" "8")])
5453 [(set (match_operand:DI 0 "register_operand" "=r")
5454 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5455 (match_operand:DI 2 "register_operand" "r")))]
5458 [(set_attr "type" "binary")
5459 (set_attr "length" "4")])
5462 [(set (match_operand:SI 0 "register_operand" "=r")
5463 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5464 (match_operand:SI 2 "register_operand" "r")))]
5467 [(set_attr "type" "binary")
5468 (set_attr "length" "4")])
5470 (define_expand "iordi3"
5471 [(set (match_operand:DI 0 "register_operand" "")
5472 (ior:DI (match_operand:DI 1 "ior_operand" "")
5473 (match_operand:DI 2 "ior_operand" "")))]
5479 /* One operand must be a register operand. */
5480 if (!register_operand (operands[1], DImode)
5481 && !register_operand (operands[2], DImode))
5486 /* Both operands must be register operands. */
5487 if (!register_operand (operands[1], DImode)
5488 || !register_operand (operands[2], DImode))
5494 [(set (match_operand:DI 0 "register_operand" "=r")
5495 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5496 (match_operand:DI 2 "register_operand" "r")))]
5498 "or %1,%2,%0\;or %R1,%R2,%R0"
5499 [(set_attr "type" "binary")
5500 (set_attr "length" "8")])
5503 [(set (match_operand:DI 0 "register_operand" "=r,r")
5504 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5505 (match_operand:DI 2 "ior_operand" "M,i")))]
5507 "* return output_64bit_ior (operands); "
5508 [(set_attr "type" "binary,shift")
5509 (set_attr "length" "4,4")])
5512 [(set (match_operand:DI 0 "register_operand" "=r")
5513 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5514 (match_operand:DI 2 "register_operand" "r")))]
5517 [(set_attr "type" "binary")
5518 (set_attr "length" "4")])
5520 ;; Need a define_expand because we've run out of CONST_OK... characters.
5521 (define_expand "iorsi3"
5522 [(set (match_operand:SI 0 "register_operand" "")
5523 (ior:SI (match_operand:SI 1 "register_operand" "")
5524 (match_operand:SI 2 "arith32_operand" "")))]
5528 if (! (ior_operand (operands[2], SImode)
5529 || register_operand (operands[2], SImode)))
5530 operands[2] = force_reg (SImode, operands[2]);
5534 [(set (match_operand:SI 0 "register_operand" "=r,r")
5535 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5536 (match_operand:SI 2 "ior_operand" "M,i")))]
5538 "* return output_ior (operands); "
5539 [(set_attr "type" "binary,shift")
5540 (set_attr "length" "4,4")])
5543 [(set (match_operand:SI 0 "register_operand" "=r")
5544 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5545 (match_operand:SI 2 "register_operand" "r")))]
5548 [(set_attr "type" "binary")
5549 (set_attr "length" "4")])
5551 (define_expand "xordi3"
5552 [(set (match_operand:DI 0 "register_operand" "")
5553 (xor:DI (match_operand:DI 1 "register_operand" "")
5554 (match_operand:DI 2 "register_operand" "")))]
5561 [(set (match_operand:DI 0 "register_operand" "=r")
5562 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5563 (match_operand:DI 2 "register_operand" "r")))]
5565 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5566 [(set_attr "type" "binary")
5567 (set_attr "length" "8")])
5570 [(set (match_operand:DI 0 "register_operand" "=r")
5571 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5572 (match_operand:DI 2 "register_operand" "r")))]
5575 [(set_attr "type" "binary")
5576 (set_attr "length" "4")])
5578 (define_insn "xorsi3"
5579 [(set (match_operand:SI 0 "register_operand" "=r")
5580 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5581 (match_operand:SI 2 "register_operand" "r")))]
5584 [(set_attr "type" "binary")
5585 (set_attr "length" "4")])
5587 (define_expand "negdi2"
5588 [(set (match_operand:DI 0 "register_operand" "")
5589 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5594 [(set (match_operand:DI 0 "register_operand" "=r")
5595 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5597 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5598 [(set_attr "type" "unary")
5599 (set_attr "length" "8")])
5602 [(set (match_operand:DI 0 "register_operand" "=r")
5603 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5606 [(set_attr "type" "unary")
5607 (set_attr "length" "4")])
5609 (define_insn "negsi2"
5610 [(set (match_operand:SI 0 "register_operand" "=r")
5611 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5614 [(set_attr "type" "unary")
5615 (set_attr "length" "4")])
5617 (define_expand "one_cmpldi2"
5618 [(set (match_operand:DI 0 "register_operand" "")
5619 (not:DI (match_operand:DI 1 "register_operand" "")))]
5626 [(set (match_operand:DI 0 "register_operand" "=r")
5627 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5629 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5630 [(set_attr "type" "unary")
5631 (set_attr "length" "8")])
5634 [(set (match_operand:DI 0 "register_operand" "=r")
5635 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5638 [(set_attr "type" "unary")
5639 (set_attr "length" "4")])
5641 (define_insn "one_cmplsi2"
5642 [(set (match_operand:SI 0 "register_operand" "=r")
5643 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5646 [(set_attr "type" "unary")
5647 (set_attr "length" "4")])
5649 ;; Floating point arithmetic instructions.
5651 (define_insn "adddf3"
5652 [(set (match_operand:DF 0 "register_operand" "=f")
5653 (plus:DF (match_operand:DF 1 "register_operand" "f")
5654 (match_operand:DF 2 "register_operand" "f")))]
5655 "! TARGET_SOFT_FLOAT"
5657 [(set_attr "type" "fpalu")
5658 (set_attr "pa_combine_type" "faddsub")
5659 (set_attr "length" "4")])
5661 (define_insn "addsf3"
5662 [(set (match_operand:SF 0 "register_operand" "=f")
5663 (plus:SF (match_operand:SF 1 "register_operand" "f")
5664 (match_operand:SF 2 "register_operand" "f")))]
5665 "! TARGET_SOFT_FLOAT"
5667 [(set_attr "type" "fpalu")
5668 (set_attr "pa_combine_type" "faddsub")
5669 (set_attr "length" "4")])
5671 (define_insn "subdf3"
5672 [(set (match_operand:DF 0 "register_operand" "=f")
5673 (minus:DF (match_operand:DF 1 "register_operand" "f")
5674 (match_operand:DF 2 "register_operand" "f")))]
5675 "! TARGET_SOFT_FLOAT"
5677 [(set_attr "type" "fpalu")
5678 (set_attr "pa_combine_type" "faddsub")
5679 (set_attr "length" "4")])
5681 (define_insn "subsf3"
5682 [(set (match_operand:SF 0 "register_operand" "=f")
5683 (minus:SF (match_operand:SF 1 "register_operand" "f")
5684 (match_operand:SF 2 "register_operand" "f")))]
5685 "! TARGET_SOFT_FLOAT"
5687 [(set_attr "type" "fpalu")
5688 (set_attr "pa_combine_type" "faddsub")
5689 (set_attr "length" "4")])
5691 (define_insn "muldf3"
5692 [(set (match_operand:DF 0 "register_operand" "=f")
5693 (mult:DF (match_operand:DF 1 "register_operand" "f")
5694 (match_operand:DF 2 "register_operand" "f")))]
5695 "! TARGET_SOFT_FLOAT"
5697 [(set_attr "type" "fpmuldbl")
5698 (set_attr "pa_combine_type" "fmpy")
5699 (set_attr "length" "4")])
5701 (define_insn "mulsf3"
5702 [(set (match_operand:SF 0 "register_operand" "=f")
5703 (mult:SF (match_operand:SF 1 "register_operand" "f")
5704 (match_operand:SF 2 "register_operand" "f")))]
5705 "! TARGET_SOFT_FLOAT"
5707 [(set_attr "type" "fpmulsgl")
5708 (set_attr "pa_combine_type" "fmpy")
5709 (set_attr "length" "4")])
5711 (define_insn "divdf3"
5712 [(set (match_operand:DF 0 "register_operand" "=f")
5713 (div:DF (match_operand:DF 1 "register_operand" "f")
5714 (match_operand:DF 2 "register_operand" "f")))]
5715 "! TARGET_SOFT_FLOAT"
5717 [(set_attr "type" "fpdivdbl")
5718 (set_attr "length" "4")])
5720 (define_insn "divsf3"
5721 [(set (match_operand:SF 0 "register_operand" "=f")
5722 (div:SF (match_operand:SF 1 "register_operand" "f")
5723 (match_operand:SF 2 "register_operand" "f")))]
5724 "! TARGET_SOFT_FLOAT"
5726 [(set_attr "type" "fpdivsgl")
5727 (set_attr "length" "4")])
5729 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5730 ;; negation can be done by subtracting from plus zero. However, this
5731 ;; violates the IEEE standard when negating plus and minus zero.
5732 (define_expand "negdf2"
5733 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5734 (neg:DF (match_operand:DF 1 "register_operand" "")))
5735 (use (match_dup 2))])]
5736 "! TARGET_SOFT_FLOAT"
5738 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5739 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5742 operands[2] = force_reg (DFmode,
5743 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5744 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5749 (define_insn "negdf2_fast"
5750 [(set (match_operand:DF 0 "register_operand" "=f")
5751 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5752 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5756 return \"fneg,dbl %1,%0\";
5758 return \"fsub,dbl %%fr0,%1,%0\";
5760 [(set_attr "type" "fpalu")
5761 (set_attr "length" "4")])
5763 (define_expand "negsf2"
5764 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5765 (neg:SF (match_operand:SF 1 "register_operand" "")))
5766 (use (match_dup 2))])]
5767 "! TARGET_SOFT_FLOAT"
5769 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5770 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5773 operands[2] = force_reg (SFmode,
5774 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5775 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5780 (define_insn "negsf2_fast"
5781 [(set (match_operand:SF 0 "register_operand" "=f")
5782 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5783 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5787 return \"fneg,sgl %1,%0\";
5789 return \"fsub,sgl %%fr0,%1,%0\";
5791 [(set_attr "type" "fpalu")
5792 (set_attr "length" "4")])
5794 (define_insn "absdf2"
5795 [(set (match_operand:DF 0 "register_operand" "=f")
5796 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5797 "! TARGET_SOFT_FLOAT"
5799 [(set_attr "type" "fpalu")
5800 (set_attr "length" "4")])
5802 (define_insn "abssf2"
5803 [(set (match_operand:SF 0 "register_operand" "=f")
5804 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5805 "! TARGET_SOFT_FLOAT"
5807 [(set_attr "type" "fpalu")
5808 (set_attr "length" "4")])
5810 (define_insn "sqrtdf2"
5811 [(set (match_operand:DF 0 "register_operand" "=f")
5812 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5813 "! TARGET_SOFT_FLOAT"
5815 [(set_attr "type" "fpsqrtdbl")
5816 (set_attr "length" "4")])
5818 (define_insn "sqrtsf2"
5819 [(set (match_operand:SF 0 "register_operand" "=f")
5820 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5821 "! TARGET_SOFT_FLOAT"
5823 [(set_attr "type" "fpsqrtsgl")
5824 (set_attr "length" "4")])
5826 ;; PA 2.0 floating point instructions
5830 [(set (match_operand:DF 0 "register_operand" "=f")
5831 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5832 (match_operand:DF 2 "register_operand" "f"))
5833 (match_operand:DF 3 "register_operand" "f")))]
5834 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5835 "fmpyfadd,dbl %1,%2,%3,%0"
5836 [(set_attr "type" "fpmuldbl")
5837 (set_attr "length" "4")])
5840 [(set (match_operand:DF 0 "register_operand" "=f")
5841 (plus:DF (match_operand:DF 1 "register_operand" "f")
5842 (mult:DF (match_operand:DF 2 "register_operand" "f")
5843 (match_operand:DF 3 "register_operand" "f"))))]
5844 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5845 "fmpyfadd,dbl %2,%3,%1,%0"
5846 [(set_attr "type" "fpmuldbl")
5847 (set_attr "length" "4")])
5850 [(set (match_operand:SF 0 "register_operand" "=f")
5851 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5852 (match_operand:SF 2 "register_operand" "f"))
5853 (match_operand:SF 3 "register_operand" "f")))]
5854 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5855 "fmpyfadd,sgl %1,%2,%3,%0"
5856 [(set_attr "type" "fpmulsgl")
5857 (set_attr "length" "4")])
5860 [(set (match_operand:SF 0 "register_operand" "=f")
5861 (plus:SF (match_operand:SF 1 "register_operand" "f")
5862 (mult:SF (match_operand:SF 2 "register_operand" "f")
5863 (match_operand:SF 3 "register_operand" "f"))))]
5864 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5865 "fmpyfadd,sgl %2,%3,%1,%0"
5866 [(set_attr "type" "fpmulsgl")
5867 (set_attr "length" "4")])
5869 ; fmpynfadd patterns
5871 [(set (match_operand:DF 0 "register_operand" "=f")
5872 (minus:DF (match_operand:DF 1 "register_operand" "f")
5873 (mult:DF (match_operand:DF 2 "register_operand" "f")
5874 (match_operand:DF 3 "register_operand" "f"))))]
5875 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5876 "fmpynfadd,dbl %2,%3,%1,%0"
5877 [(set_attr "type" "fpmuldbl")
5878 (set_attr "length" "4")])
5881 [(set (match_operand:SF 0 "register_operand" "=f")
5882 (minus:SF (match_operand:SF 1 "register_operand" "f")
5883 (mult:SF (match_operand:SF 2 "register_operand" "f")
5884 (match_operand:SF 3 "register_operand" "f"))))]
5885 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5886 "fmpynfadd,sgl %2,%3,%1,%0"
5887 [(set_attr "type" "fpmulsgl")
5888 (set_attr "length" "4")])
5892 [(set (match_operand:DF 0 "register_operand" "=f")
5893 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5894 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5896 [(set_attr "type" "fpalu")
5897 (set_attr "length" "4")])
5900 [(set (match_operand:SF 0 "register_operand" "=f")
5901 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5902 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5904 [(set_attr "type" "fpalu")
5905 (set_attr "length" "4")])
5907 ;; Generating a fused multiply sequence is a win for this case as it will
5908 ;; reduce the latency for the fused case without impacting the plain
5911 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5912 ;; perform two operations with the result of the first feeding the second.
5914 [(set (match_operand:DF 0 "register_operand" "=f")
5915 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5916 (match_operand:DF 2 "register_operand" "f"))
5917 (match_operand:DF 3 "register_operand" "f")))
5918 (set (match_operand:DF 4 "register_operand" "=&f")
5919 (mult:DF (match_dup 1) (match_dup 2)))]
5920 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5921 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5922 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5924 [(set_attr "type" "fpmuldbl")
5925 (set_attr "length" "8")])
5927 ;; We want to split this up during scheduling since we want both insns
5928 ;; to schedule independently.
5930 [(set (match_operand:DF 0 "register_operand" "")
5931 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5932 (match_operand:DF 2 "register_operand" ""))
5933 (match_operand:DF 3 "register_operand" "")))
5934 (set (match_operand:DF 4 "register_operand" "")
5935 (mult:DF (match_dup 1) (match_dup 2)))]
5936 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5937 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5938 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5943 [(set (match_operand:SF 0 "register_operand" "=f")
5944 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5945 (match_operand:SF 2 "register_operand" "f"))
5946 (match_operand:SF 3 "register_operand" "f")))
5947 (set (match_operand:SF 4 "register_operand" "=&f")
5948 (mult:SF (match_dup 1) (match_dup 2)))]
5949 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5950 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5951 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5953 [(set_attr "type" "fpmuldbl")
5954 (set_attr "length" "8")])
5956 ;; We want to split this up during scheduling since we want both insns
5957 ;; to schedule independently.
5959 [(set (match_operand:SF 0 "register_operand" "")
5960 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5961 (match_operand:SF 2 "register_operand" ""))
5962 (match_operand:SF 3 "register_operand" "")))
5963 (set (match_operand:SF 4 "register_operand" "")
5964 (mult:SF (match_dup 1) (match_dup 2)))]
5965 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5966 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5967 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
5971 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
5974 [(set (match_operand:DF 0 "register_operand" "=f")
5975 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5976 (match_operand:DF 2 "register_operand" "f"))))]
5977 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5978 "fmpynfadd,dbl %1,%2,%%fr0,%0"
5979 [(set_attr "type" "fpmuldbl")
5980 (set_attr "length" "4")])
5983 [(set (match_operand:SF 0 "register_operand" "=f")
5984 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5985 (match_operand:SF 2 "register_operand" "f"))))]
5986 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5987 "fmpynfadd,sgl %1,%2,%%fr0,%0"
5988 [(set_attr "type" "fpmuldbl")
5989 (set_attr "length" "4")])
5992 [(set (match_operand:DF 0 "register_operand" "=f")
5993 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5994 (match_operand:DF 2 "register_operand" "f"))))
5995 (set (match_operand:DF 3 "register_operand" "=&f")
5996 (mult:DF (match_dup 1) (match_dup 2)))]
5997 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5998 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5999 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6001 [(set_attr "type" "fpmuldbl")
6002 (set_attr "length" "8")])
6005 [(set (match_operand:DF 0 "register_operand" "")
6006 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6007 (match_operand:DF 2 "register_operand" ""))))
6008 (set (match_operand:DF 3 "register_operand" "")
6009 (mult:DF (match_dup 1) (match_dup 2)))]
6010 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6011 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6012 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6016 [(set (match_operand:SF 0 "register_operand" "=f")
6017 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6018 (match_operand:SF 2 "register_operand" "f"))))
6019 (set (match_operand:SF 3 "register_operand" "=&f")
6020 (mult:SF (match_dup 1) (match_dup 2)))]
6021 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6022 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6023 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6025 [(set_attr "type" "fpmuldbl")
6026 (set_attr "length" "8")])
6029 [(set (match_operand:SF 0 "register_operand" "")
6030 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6031 (match_operand:SF 2 "register_operand" ""))))
6032 (set (match_operand:SF 3 "register_operand" "")
6033 (mult:SF (match_dup 1) (match_dup 2)))]
6034 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6035 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6036 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6039 ;; Now fused multiplies with the result of the multiply negated.
6041 [(set (match_operand:DF 0 "register_operand" "=f")
6042 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6043 (match_operand:DF 2 "register_operand" "f")))
6044 (match_operand:DF 3 "register_operand" "f")))]
6045 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6046 "fmpynfadd,dbl %1,%2,%3,%0"
6047 [(set_attr "type" "fpmuldbl")
6048 (set_attr "length" "4")])
6051 [(set (match_operand:SF 0 "register_operand" "=f")
6052 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6053 (match_operand:SF 2 "register_operand" "f")))
6054 (match_operand:SF 3 "register_operand" "f")))]
6055 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6056 "fmpynfadd,sgl %1,%2,%3,%0"
6057 [(set_attr "type" "fpmuldbl")
6058 (set_attr "length" "4")])
6061 [(set (match_operand:DF 0 "register_operand" "=f")
6062 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6063 (match_operand:DF 2 "register_operand" "f")))
6064 (match_operand:DF 3 "register_operand" "f")))
6065 (set (match_operand:DF 4 "register_operand" "=&f")
6066 (mult:DF (match_dup 1) (match_dup 2)))]
6067 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6068 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6069 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6071 [(set_attr "type" "fpmuldbl")
6072 (set_attr "length" "8")])
6075 [(set (match_operand:DF 0 "register_operand" "")
6076 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6077 (match_operand:DF 2 "register_operand" "")))
6078 (match_operand:DF 3 "register_operand" "")))
6079 (set (match_operand:DF 4 "register_operand" "")
6080 (mult:DF (match_dup 1) (match_dup 2)))]
6081 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6082 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6083 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6088 [(set (match_operand:SF 0 "register_operand" "=f")
6089 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6090 (match_operand:SF 2 "register_operand" "f")))
6091 (match_operand:SF 3 "register_operand" "f")))
6092 (set (match_operand:SF 4 "register_operand" "=&f")
6093 (mult:SF (match_dup 1) (match_dup 2)))]
6094 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6095 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6096 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6098 [(set_attr "type" "fpmuldbl")
6099 (set_attr "length" "8")])
6102 [(set (match_operand:SF 0 "register_operand" "")
6103 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6104 (match_operand:SF 2 "register_operand" "")))
6105 (match_operand:SF 3 "register_operand" "")))
6106 (set (match_operand:SF 4 "register_operand" "")
6107 (mult:SF (match_dup 1) (match_dup 2)))]
6108 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6109 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6110 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6115 [(set (match_operand:DF 0 "register_operand" "=f")
6116 (minus:DF (match_operand:DF 3 "register_operand" "f")
6117 (mult:DF (match_operand:DF 1 "register_operand" "f")
6118 (match_operand:DF 2 "register_operand" "f"))))
6119 (set (match_operand:DF 4 "register_operand" "=&f")
6120 (mult:DF (match_dup 1) (match_dup 2)))]
6121 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6122 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6123 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6125 [(set_attr "type" "fpmuldbl")
6126 (set_attr "length" "8")])
6129 [(set (match_operand:DF 0 "register_operand" "")
6130 (minus:DF (match_operand:DF 3 "register_operand" "")
6131 (mult:DF (match_operand:DF 1 "register_operand" "")
6132 (match_operand:DF 2 "register_operand" ""))))
6133 (set (match_operand:DF 4 "register_operand" "")
6134 (mult:DF (match_dup 1) (match_dup 2)))]
6135 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6136 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6137 (set (match_dup 0) (minus:DF (match_dup 3)
6138 (mult:DF (match_dup 1) (match_dup 2))))]
6142 [(set (match_operand:SF 0 "register_operand" "=f")
6143 (minus:SF (match_operand:SF 3 "register_operand" "f")
6144 (mult:SF (match_operand:SF 1 "register_operand" "f")
6145 (match_operand:SF 2 "register_operand" "f"))))
6146 (set (match_operand:SF 4 "register_operand" "=&f")
6147 (mult:SF (match_dup 1) (match_dup 2)))]
6148 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6149 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6150 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6152 [(set_attr "type" "fpmuldbl")
6153 (set_attr "length" "8")])
6156 [(set (match_operand:SF 0 "register_operand" "")
6157 (minus:SF (match_operand:SF 3 "register_operand" "")
6158 (mult:SF (match_operand:SF 1 "register_operand" "")
6159 (match_operand:SF 2 "register_operand" ""))))
6160 (set (match_operand:SF 4 "register_operand" "")
6161 (mult:SF (match_dup 1) (match_dup 2)))]
6162 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6163 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6164 (set (match_dup 0) (minus:SF (match_dup 3)
6165 (mult:SF (match_dup 1) (match_dup 2))))]
6169 [(set (match_operand:DF 0 "register_operand" "=f")
6170 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6171 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6172 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6173 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6175 [(set_attr "type" "fpalu")
6176 (set_attr "length" "8")])
6179 [(set (match_operand:DF 0 "register_operand" "")
6180 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6181 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6182 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6183 [(set (match_dup 2) (abs:DF (match_dup 1)))
6184 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6188 [(set (match_operand:SF 0 "register_operand" "=f")
6189 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6190 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6191 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6192 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6194 [(set_attr "type" "fpalu")
6195 (set_attr "length" "8")])
6198 [(set (match_operand:SF 0 "register_operand" "")
6199 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6200 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6201 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6202 [(set (match_dup 2) (abs:SF (match_dup 1)))
6203 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6206 ;;- Shift instructions
6208 ;; Optimized special case of shifting.
6211 [(set (match_operand:SI 0 "register_operand" "=r")
6212 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6216 [(set_attr "type" "load")
6217 (set_attr "length" "4")])
6220 [(set (match_operand:SI 0 "register_operand" "=r")
6221 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6225 [(set_attr "type" "load")
6226 (set_attr "length" "4")])
6229 [(set (match_operand:SI 0 "register_operand" "=r")
6230 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6231 (match_operand:SI 3 "shadd_operand" ""))
6232 (match_operand:SI 1 "register_operand" "r")))]
6234 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6235 [(set_attr "type" "binary")
6236 (set_attr "length" "4")])
6239 [(set (match_operand:DI 0 "register_operand" "=r")
6240 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6241 (match_operand:DI 3 "shadd_operand" ""))
6242 (match_operand:DI 1 "register_operand" "r")))]
6244 "shladd,l %2,%O3,%1,%0"
6245 [(set_attr "type" "binary")
6246 (set_attr "length" "4")])
6248 (define_expand "ashlsi3"
6249 [(set (match_operand:SI 0 "register_operand" "")
6250 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6251 (match_operand:SI 2 "arith32_operand" "")))]
6255 if (GET_CODE (operands[2]) != CONST_INT)
6257 rtx temp = gen_reg_rtx (SImode);
6258 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6259 if (GET_CODE (operands[1]) == CONST_INT)
6260 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6262 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6265 /* Make sure both inputs are not constants,
6266 there are no patterns for that. */
6267 operands[1] = force_reg (SImode, operands[1]);
6271 [(set (match_operand:SI 0 "register_operand" "=r")
6272 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6273 (match_operand:SI 2 "const_int_operand" "n")))]
6275 "{zdep|depw,z} %1,%P2,%L2,%0"
6276 [(set_attr "type" "shift")
6277 (set_attr "length" "4")])
6279 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6280 ; Doing it like this makes slightly better code since reload can
6281 ; replace a register with a known value in range -16..15 with a
6282 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6283 ; but since we have no more CONST_OK... characters, that is not
6285 (define_insn "zvdep32"
6286 [(set (match_operand:SI 0 "register_operand" "=r,r")
6287 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6288 (minus:SI (const_int 31)
6289 (match_operand:SI 2 "register_operand" "q,q"))))]
6292 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6293 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6294 [(set_attr "type" "shift,shift")
6295 (set_attr "length" "4,4")])
6297 (define_insn "zvdep_imm32"
6298 [(set (match_operand:SI 0 "register_operand" "=r")
6299 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6300 (minus:SI (const_int 31)
6301 (match_operand:SI 2 "register_operand" "q"))))]
6305 int x = INTVAL (operands[1]);
6306 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6307 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6308 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6310 [(set_attr "type" "shift")
6311 (set_attr "length" "4")])
6313 (define_insn "vdepi_ior"
6314 [(set (match_operand:SI 0 "register_operand" "=r")
6315 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6316 (minus:SI (const_int 31)
6317 (match_operand:SI 2 "register_operand" "q")))
6318 (match_operand:SI 3 "register_operand" "0")))]
6319 ; accept ...0001...1, can this be generalized?
6320 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6323 int x = INTVAL (operands[1]);
6324 operands[2] = GEN_INT (exact_log2 (x + 1));
6325 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6327 [(set_attr "type" "shift")
6328 (set_attr "length" "4")])
6330 (define_insn "vdepi_and"
6331 [(set (match_operand:SI 0 "register_operand" "=r")
6332 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6333 (minus:SI (const_int 31)
6334 (match_operand:SI 2 "register_operand" "q")))
6335 (match_operand:SI 3 "register_operand" "0")))]
6336 ; this can be generalized...!
6337 "INTVAL (operands[1]) == -2"
6340 int x = INTVAL (operands[1]);
6341 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6342 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6344 [(set_attr "type" "shift")
6345 (set_attr "length" "4")])
6347 (define_expand "ashldi3"
6348 [(set (match_operand:DI 0 "register_operand" "")
6349 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6350 (match_operand:DI 2 "arith32_operand" "")))]
6354 if (GET_CODE (operands[2]) != CONST_INT)
6356 rtx temp = gen_reg_rtx (DImode);
6357 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6358 if (GET_CODE (operands[1]) == CONST_INT)
6359 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6361 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6364 /* Make sure both inputs are not constants,
6365 there are no patterns for that. */
6366 operands[1] = force_reg (DImode, operands[1]);
6370 [(set (match_operand:DI 0 "register_operand" "=r")
6371 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6372 (match_operand:DI 2 "const_int_operand" "n")))]
6374 "depd,z %1,%p2,%Q2,%0"
6375 [(set_attr "type" "shift")
6376 (set_attr "length" "4")])
6378 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6379 ; Doing it like this makes slightly better code since reload can
6380 ; replace a register with a known value in range -16..15 with a
6381 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6382 ; but since we have no more CONST_OK... characters, that is not
6384 (define_insn "zvdep64"
6385 [(set (match_operand:DI 0 "register_operand" "=r,r")
6386 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6387 (minus:DI (const_int 63)
6388 (match_operand:DI 2 "register_operand" "q,q"))))]
6391 depd,z %1,%%sar,64,%0
6392 depdi,z %1,%%sar,64,%0"
6393 [(set_attr "type" "shift,shift")
6394 (set_attr "length" "4,4")])
6396 (define_insn "zvdep_imm64"
6397 [(set (match_operand:DI 0 "register_operand" "=r")
6398 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6399 (minus:DI (const_int 63)
6400 (match_operand:DI 2 "register_operand" "q"))))]
6404 int x = INTVAL (operands[1]);
6405 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6406 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6407 return \"depdi,z %1,%%sar,%2,%0\";
6409 [(set_attr "type" "shift")
6410 (set_attr "length" "4")])
6413 [(set (match_operand:DI 0 "register_operand" "=r")
6414 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6415 (minus:DI (const_int 63)
6416 (match_operand:DI 2 "register_operand" "q")))
6417 (match_operand:DI 3 "register_operand" "0")))]
6418 ; accept ...0001...1, can this be generalized?
6419 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6422 int x = INTVAL (operands[1]);
6423 operands[2] = GEN_INT (exact_log2 (x + 1));
6424 return \"depdi -1,%%sar,%2,%0\";
6426 [(set_attr "type" "shift")
6427 (set_attr "length" "4")])
6430 [(set (match_operand:DI 0 "register_operand" "=r")
6431 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6432 (minus:DI (const_int 63)
6433 (match_operand:DI 2 "register_operand" "q")))
6434 (match_operand:DI 3 "register_operand" "0")))]
6435 ; this can be generalized...!
6436 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6439 int x = INTVAL (operands[1]);
6440 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6441 return \"depdi 0,%%sar,%2,%0\";
6443 [(set_attr "type" "shift")
6444 (set_attr "length" "4")])
6446 (define_expand "ashrsi3"
6447 [(set (match_operand:SI 0 "register_operand" "")
6448 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6449 (match_operand:SI 2 "arith32_operand" "")))]
6453 if (GET_CODE (operands[2]) != CONST_INT)
6455 rtx temp = gen_reg_rtx (SImode);
6456 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6457 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6463 [(set (match_operand:SI 0 "register_operand" "=r")
6464 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6465 (match_operand:SI 2 "const_int_operand" "n")))]
6467 "{extrs|extrw,s} %1,%P2,%L2,%0"
6468 [(set_attr "type" "shift")
6469 (set_attr "length" "4")])
6471 (define_insn "vextrs32"
6472 [(set (match_operand:SI 0 "register_operand" "=r")
6473 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6474 (minus:SI (const_int 31)
6475 (match_operand:SI 2 "register_operand" "q"))))]
6477 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6478 [(set_attr "type" "shift")
6479 (set_attr "length" "4")])
6481 (define_expand "ashrdi3"
6482 [(set (match_operand:DI 0 "register_operand" "")
6483 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6484 (match_operand:DI 2 "arith32_operand" "")))]
6488 if (GET_CODE (operands[2]) != CONST_INT)
6490 rtx temp = gen_reg_rtx (DImode);
6491 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6492 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6498 [(set (match_operand:DI 0 "register_operand" "=r")
6499 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6500 (match_operand:DI 2 "const_int_operand" "n")))]
6502 "extrd,s %1,%p2,%Q2,%0"
6503 [(set_attr "type" "shift")
6504 (set_attr "length" "4")])
6506 (define_insn "vextrs64"
6507 [(set (match_operand:DI 0 "register_operand" "=r")
6508 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6509 (minus:DI (const_int 63)
6510 (match_operand:DI 2 "register_operand" "q"))))]
6512 "extrd,s %1,%%sar,64,%0"
6513 [(set_attr "type" "shift")
6514 (set_attr "length" "4")])
6516 (define_insn "lshrsi3"
6517 [(set (match_operand:SI 0 "register_operand" "=r,r")
6518 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6519 (match_operand:SI 2 "arith32_operand" "q,n")))]
6522 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6523 {extru|extrw,u} %1,%P2,%L2,%0"
6524 [(set_attr "type" "shift")
6525 (set_attr "length" "4")])
6527 (define_insn "lshrdi3"
6528 [(set (match_operand:DI 0 "register_operand" "=r,r")
6529 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6530 (match_operand:DI 2 "arith32_operand" "q,n")))]
6533 shrpd %%r0,%1,%%sar,%0
6534 extrd,u %1,%p2,%Q2,%0"
6535 [(set_attr "type" "shift")
6536 (set_attr "length" "4")])
6538 (define_insn "rotrsi3"
6539 [(set (match_operand:SI 0 "register_operand" "=r,r")
6540 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6541 (match_operand:SI 2 "arith32_operand" "q,n")))]
6545 if (GET_CODE (operands[2]) == CONST_INT)
6547 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6548 return \"{shd|shrpw} %1,%1,%2,%0\";
6551 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6553 [(set_attr "type" "shift")
6554 (set_attr "length" "4")])
6556 (define_expand "rotlsi3"
6557 [(set (match_operand:SI 0 "register_operand" "")
6558 (rotate:SI (match_operand:SI 1 "register_operand" "")
6559 (match_operand:SI 2 "arith32_operand" "")))]
6563 if (GET_CODE (operands[2]) != CONST_INT)
6565 rtx temp = gen_reg_rtx (SImode);
6566 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6567 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6570 /* Else expand normally. */
6574 [(set (match_operand:SI 0 "register_operand" "=r")
6575 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6576 (match_operand:SI 2 "const_int_operand" "n")))]
6580 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6581 return \"{shd|shrpw} %1,%1,%2,%0\";
6583 [(set_attr "type" "shift")
6584 (set_attr "length" "4")])
6587 [(set (match_operand:SI 0 "register_operand" "=r")
6588 (match_operator:SI 5 "plus_xor_ior_operator"
6589 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6590 (match_operand:SI 3 "const_int_operand" "n"))
6591 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6592 (match_operand:SI 4 "const_int_operand" "n"))]))]
6593 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6594 "{shd|shrpw} %1,%2,%4,%0"
6595 [(set_attr "type" "shift")
6596 (set_attr "length" "4")])
6599 [(set (match_operand:SI 0 "register_operand" "=r")
6600 (match_operator:SI 5 "plus_xor_ior_operator"
6601 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6602 (match_operand:SI 4 "const_int_operand" "n"))
6603 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6604 (match_operand:SI 3 "const_int_operand" "n"))]))]
6605 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6606 "{shd|shrpw} %1,%2,%4,%0"
6607 [(set_attr "type" "shift")
6608 (set_attr "length" "4")])
6611 [(set (match_operand:SI 0 "register_operand" "=r")
6612 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6613 (match_operand:SI 2 "const_int_operand" ""))
6614 (match_operand:SI 3 "const_int_operand" "")))]
6615 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6618 int cnt = INTVAL (operands[2]) & 31;
6619 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6620 operands[2] = GEN_INT (31 - cnt);
6621 return \"{zdep|depw,z} %1,%2,%3,%0\";
6623 [(set_attr "type" "shift")
6624 (set_attr "length" "4")])
6626 ;; Unconditional and other jump instructions.
6628 ;; This can only be used in a leaf function, so we do
6629 ;; not need to use the PIC register when generating PIC code.
6630 (define_insn "return"
6634 "hppa_can_use_return_insn_p ()"
6638 return \"bve%* (%%r2)\";
6639 return \"bv%* %%r0(%%r2)\";
6641 [(set_attr "type" "branch")
6642 (set_attr "length" "4")])
6644 ;; Emit a different pattern for functions which have non-trivial
6645 ;; epilogues so as not to confuse jump and reorg.
6646 (define_insn "return_internal"
6654 return \"bve%* (%%r2)\";
6655 return \"bv%* %%r0(%%r2)\";
6657 [(set_attr "type" "branch")
6658 (set_attr "length" "4")])
6660 ;; This is used for eh returns which bypass the return stub.
6661 (define_insn "return_external_pic"
6663 (clobber (reg:SI 1))
6665 "!TARGET_NO_SPACE_REGS
6667 && flag_pic && current_function_calls_eh_return"
6668 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6669 [(set_attr "type" "branch")
6670 (set_attr "length" "12")])
6672 (define_expand "prologue"
6675 "hppa_expand_prologue ();DONE;")
6677 (define_expand "sibcall_epilogue"
6682 hppa_expand_epilogue ();
6686 (define_expand "epilogue"
6691 /* Try to use the trivial return first. Else use the full
6693 if (hppa_can_use_return_insn_p ())
6694 emit_jump_insn (gen_return ());
6699 hppa_expand_epilogue ();
6701 /* EH returns bypass the normal return stub. Thus, we must do an
6702 interspace branch to return from functions that call eh_return.
6703 This is only a problem for returns from shared code on ports
6704 using space registers. */
6705 if (!TARGET_NO_SPACE_REGS
6707 && flag_pic && current_function_calls_eh_return)
6708 x = gen_return_external_pic ();
6710 x = gen_return_internal ();
6717 ; Used by hppa_profile_hook to load the starting address of the current
6718 ; function; operand 1 contains the address of the label in operand 3
6719 (define_insn "load_offset_label_address"
6720 [(set (match_operand:SI 0 "register_operand" "=r")
6721 (plus:SI (match_operand:SI 1 "register_operand" "r")
6722 (minus:SI (match_operand:SI 2 "" "")
6723 (label_ref:SI (match_operand 3 "" "")))))]
6726 [(set_attr "type" "multi")
6727 (set_attr "length" "4")])
6729 ; Output a code label and load its address.
6730 (define_insn "lcla1"
6731 [(set (match_operand:SI 0 "register_operand" "=r")
6732 (label_ref:SI (match_operand 1 "" "")))
6737 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6738 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6739 CODE_LABEL_NUMBER (operands[1]));
6742 [(set_attr "type" "multi")
6743 (set_attr "length" "8")])
6745 (define_insn "lcla2"
6746 [(set (match_operand:SI 0 "register_operand" "=r")
6747 (label_ref:SI (match_operand 1 "" "")))
6752 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6753 CODE_LABEL_NUMBER (operands[1]));
6756 [(set_attr "type" "move")
6757 (set_attr "length" "4")])
6759 (define_insn "blockage"
6760 [(unspec_volatile [(const_int 2)] 0)]
6763 [(set_attr "length" "0")])
6766 [(set (pc) (label_ref (match_operand 0 "" "")))]
6770 /* An unconditional branch which can reach its target. */
6771 if (get_attr_length (insn) != 24
6772 && get_attr_length (insn) != 16)
6775 return output_lbranch (operands[0], insn);
6777 [(set_attr "type" "uncond_branch")
6778 (set_attr "pa_combine_type" "uncond_branch")
6779 (set (attr "length")
6780 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6781 (if_then_else (lt (abs (minus (match_dup 0)
6782 (plus (pc) (const_int 8))))
6786 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6788 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6793 ;;; Hope this is only within a function...
6794 (define_insn "indirect_jump"
6795 [(set (pc) (match_operand 0 "register_operand" "r"))]
6796 "GET_MODE (operands[0]) == word_mode"
6798 [(set_attr "type" "branch")
6799 (set_attr "length" "4")])
6801 ;;; This jump is used in branch tables where the insn length is fixed.
6802 ;;; The length of this insn is adjusted if the delay slot is not filled.
6803 (define_insn "short_jump"
6804 [(set (pc) (label_ref (match_operand 0 "" "")))
6808 [(set_attr "type" "btable_branch")
6809 (set_attr "length" "4")])
6811 ;; Subroutines of "casesi".
6812 ;; operand 0 is index
6813 ;; operand 1 is the minimum bound
6814 ;; operand 2 is the maximum bound - minimum bound + 1
6815 ;; operand 3 is CODE_LABEL for the table;
6816 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6818 (define_expand "casesi"
6819 [(match_operand:SI 0 "general_operand" "")
6820 (match_operand:SI 1 "const_int_operand" "")
6821 (match_operand:SI 2 "const_int_operand" "")
6822 (match_operand 3 "" "")
6823 (match_operand 4 "" "")]
6827 if (GET_CODE (operands[0]) != REG)
6828 operands[0] = force_reg (SImode, operands[0]);
6830 if (operands[1] != const0_rtx)
6832 rtx index = gen_reg_rtx (SImode);
6834 operands[1] = GEN_INT (-INTVAL (operands[1]));
6835 if (!INT_14_BITS (operands[1]))
6836 operands[1] = force_reg (SImode, operands[1]);
6837 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6838 operands[0] = index;
6841 /* In 64bit mode we must make sure to wipe the upper bits of the register
6842 just in case the addition overflowed or we had random bits in the
6843 high part of the register. */
6846 rtx index = gen_reg_rtx (DImode);
6848 emit_insn (gen_extendsidi2 (index, operands[0]));
6849 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6852 if (!INT_5_BITS (operands[2]))
6853 operands[2] = force_reg (SImode, operands[2]);
6855 /* This branch prevents us finding an insn for the delay slot of the
6856 following vectored branch. It might be possible to use the delay
6857 slot if an index value of -1 was used to transfer to the out-of-range
6858 label. In order to do this, we would have to output the -1 vector
6859 element after the delay insn. The casesi output code would have to
6860 check if the casesi insn is in a delay branch sequence and output
6861 the delay insn if one is found. If this was done, then it might
6862 then be worthwhile to split the casesi patterns to improve scheduling.
6863 However, it's not clear that all this extra complexity is worth
6865 emit_insn (gen_cmpsi (operands[0], operands[2]));
6866 emit_jump_insn (gen_bgtu (operands[4]));
6868 if (TARGET_BIG_SWITCH)
6872 rtx tmp1 = gen_reg_rtx (DImode);
6873 rtx tmp2 = gen_reg_rtx (DImode);
6875 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6880 rtx tmp1 = gen_reg_rtx (SImode);
6884 rtx tmp2 = gen_reg_rtx (SImode);
6886 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6890 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
6894 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6898 ;;; The rtl for this pattern doesn't accurately describe what the insn
6899 ;;; actually does, particularly when case-vector elements are exploded
6900 ;;; in pa_reorg. However, the initial SET in these patterns must show
6901 ;;; the connection of the insn to the following jump table.
6902 (define_insn "casesi0"
6903 [(set (pc) (mem:SI (plus:SI
6904 (mult:SI (match_operand:SI 0 "register_operand" "r")
6906 (label_ref (match_operand 1 "" "")))))]
6908 "blr,n %0,%%r0\;nop"
6909 [(set_attr "type" "multi")
6910 (set_attr "length" "8")])
6912 ;;; 32-bit code, absolute branch table.
6913 (define_insn "casesi32"
6914 [(set (pc) (mem:SI (plus:SI
6915 (mult:SI (match_operand:SI 0 "register_operand" "r")
6917 (label_ref (match_operand 1 "" "")))))
6918 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
6919 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6920 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6921 [(set_attr "type" "multi")
6922 (set_attr "length" "16")])
6924 ;;; 32-bit code, relative branch table.
6925 (define_insn "casesi32p"
6926 [(set (pc) (mem:SI (plus:SI
6927 (mult:SI (match_operand:SI 0 "register_operand" "r")
6929 (label_ref (match_operand 1 "" "")))))
6930 (clobber (match_operand:SI 2 "register_operand" "=&a"))
6931 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
6932 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6933 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
6934 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6935 [(set_attr "type" "multi")
6936 (set (attr "length")
6937 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
6941 ;;; 64-bit code, 32-bit relative branch table.
6942 (define_insn "casesi64p"
6943 [(set (pc) (mem:DI (plus:DI
6944 (mult:DI (sign_extend:DI
6945 (match_operand:SI 0 "register_operand" "r"))
6947 (label_ref (match_operand 1 "" "")))))
6948 (clobber (match_operand:DI 2 "register_operand" "=&r"))
6949 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
6950 "TARGET_64BIT && TARGET_BIG_SWITCH"
6951 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6952 add,l %2,%3,%3\;bv,n %%r0(%3)"
6953 [(set_attr "type" "multi")
6954 (set_attr "length" "24")])
6958 ;;- jump to subroutine
6960 (define_expand "call"
6961 [(parallel [(call (match_operand:SI 0 "" "")
6962 (match_operand 1 "" ""))
6963 (clobber (reg:SI 2))])]
6968 rtx nb = operands[1];
6970 if (TARGET_PORTABLE_RUNTIME)
6971 op = force_reg (SImode, XEXP (operands[0], 0));
6973 op = XEXP (operands[0], 0);
6977 if (!virtuals_instantiated)
6978 emit_move_insn (arg_pointer_rtx,
6979 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6983 /* The loop pass can generate new libcalls after the virtual
6984 registers are instantiated when fpregs are disabled because
6985 the only method that we have for doing DImode multiplication
6986 is with a libcall. This could be trouble if we haven't
6987 allocated enough space for the outgoing arguments. */
6988 if (INTVAL (nb) > current_function_outgoing_args_size)
6991 emit_move_insn (arg_pointer_rtx,
6992 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6993 GEN_INT (STACK_POINTER_OFFSET + 64)));
6997 /* Use two different patterns for calls to explicitly named functions
6998 and calls through function pointers. This is necessary as these two
6999 types of calls use different calling conventions, and CSE might try
7000 to change the named call into an indirect call in some cases (using
7001 two patterns keeps CSE from performing this optimization).
7003 We now use even more call patterns as there was a subtle bug in
7004 attempting to restore the pic register after a call using a simple
7005 move insn. During reload, a instruction involving a pseudo register
7006 with no explicit dependence on the PIC register can be converted
7007 to an equivalent load from memory using the PIC register. If we
7008 emit a simple move to restore the PIC register in the initial rtl
7009 generation, then it can potentially be repositioned during scheduling.
7010 and an instruction that eventually uses the PIC register may end up
7011 between the call and the PIC register restore.
7013 This only worked because there is a post call group of instructions
7014 that are scheduled with the call. These instructions are included
7015 in the same basic block as the call. However, calls can throw in
7016 C++ code and a basic block has to terminate at the call if the call
7017 can throw. This results in the PIC register restore being scheduled
7018 independently from the call. So, we now hide the save and restore
7019 of the PIC register in the call pattern until after reload. Then,
7020 we split the moves out. A small side benefit is that we now don't
7021 need to have a use of the PIC register in the return pattern and
7022 the final save/restore operation is not needed.
7024 I elected to just clobber %r4 in the PIC patterns and use it instead
7025 of trying to force hppa_pic_save_rtx () to a callee saved register.
7026 This might have required a new register class and constraint. It
7027 was also simpler to just handle the restore from a register than a
7031 if (GET_CODE (op) == SYMBOL_REF)
7032 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7035 op = force_reg (word_mode, op);
7036 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7041 if (GET_CODE (op) == SYMBOL_REF)
7044 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7046 call_insn = emit_call_insn (gen_call_symref (op, nb));
7050 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7052 emit_move_insn (tmpreg, force_reg (word_mode, op));
7054 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7056 call_insn = emit_call_insn (gen_call_reg (nb));
7063 ;; We use function calls to set the attribute length of calls and millicode
7064 ;; calls. This is necessary because of the large variety of call sequences.
7065 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7066 ;; we need the same calculation in several places, maintenance becomes a
7069 ;; However, this has a subtle impact on branch shortening. When the
7070 ;; expression used to set the length attribute of an instruction depends
7071 ;; on a relative address (e.g., pc or a branch address), genattrtab
7072 ;; notes that the insn's length is variable, and attempts to determine a
7073 ;; worst-case default length and code to compute an insn's current length.
7075 ;; The use of a function call hides the variable dependence of our calls
7076 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7077 ;; as variable and it only generates code for the default case using our
7078 ;; function call. Because of this, calls and millicode calls have a fixed
7079 ;; length in the branch shortening pass, and some branches will use a longer
7080 ;; code sequence than necessary. However, the length of any given call
7081 ;; will still reflect its final code location and it may be shorter than
7082 ;; the initial length estimate.
7084 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7085 ;; in the set. However, when genattrtab hits a function call in its attempt
7086 ;; to compute the default length, it marks the result as unknown and sets
7087 ;; the default result to MAX_INT ;-( One possible fix that would allow
7088 ;; calls to participate in branch shortening would be to make the call to
7089 ;; insn_default_length a target option. Then, we could massage unknown
7090 ;; results. Another fix might be to change genattrtab so that it just does
7091 ;; the call in the variable case as it already does for the fixed case.
7093 (define_insn "call_symref"
7094 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7095 (match_operand 1 "" "i"))
7096 (clobber (reg:SI 1))
7097 (clobber (reg:SI 2))
7098 (use (const_int 0))]
7099 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7102 output_arg_descriptor (insn);
7103 return output_call (insn, operands[0], 0);
7105 [(set_attr "type" "call")
7106 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7108 (define_insn "call_symref_pic"
7109 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7110 (match_operand 1 "" "i"))
7111 (clobber (reg:SI 1))
7112 (clobber (reg:SI 2))
7113 (clobber (reg:SI 4))
7115 (use (const_int 0))]
7116 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7119 output_arg_descriptor (insn);
7120 return output_call (insn, operands[0], 0);
7122 [(set_attr "type" "call")
7123 (set (attr "length")
7124 (plus (symbol_ref "attr_length_call (insn, 0)")
7125 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7127 ;; Split out the PIC register save and restore after reload. This is
7128 ;; done only if the function returns. As the split is done after reload,
7129 ;; there are some situations in which we unnecessarily save and restore
7130 ;; %r4. This happens when there is a single call and the PIC register
7131 ;; is "dead" after the call. This isn't easy to fix as the usage of
7132 ;; the PIC register isn't completely determined until the reload pass.
7134 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7135 (match_operand 1 "" ""))
7136 (clobber (reg:SI 1))
7137 (clobber (reg:SI 2))
7138 (clobber (reg:SI 4))
7140 (use (const_int 0))])]
7141 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7143 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7144 [(set (reg:SI 4) (reg:SI 19))
7145 (parallel [(call (mem:SI (match_dup 0))
7147 (clobber (reg:SI 1))
7148 (clobber (reg:SI 2))
7150 (use (const_int 0))])
7151 (set (reg:SI 19) (reg:SI 4))]
7154 ;; Remove the clobber of register 4 when optimizing. This has to be
7155 ;; done with a peephole optimization rather than a split because the
7156 ;; split sequence for a call must be longer than one instruction.
7158 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7159 (match_operand 1 "" ""))
7160 (clobber (reg:SI 1))
7161 (clobber (reg:SI 2))
7162 (clobber (reg:SI 4))
7164 (use (const_int 0))])]
7165 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7166 [(parallel [(call (mem:SI (match_dup 0))
7168 (clobber (reg:SI 1))
7169 (clobber (reg:SI 2))
7171 (use (const_int 0))])]
7174 (define_insn "*call_symref_pic_post_reload"
7175 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7176 (match_operand 1 "" "i"))
7177 (clobber (reg:SI 1))
7178 (clobber (reg:SI 2))
7180 (use (const_int 0))]
7181 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7184 output_arg_descriptor (insn);
7185 return output_call (insn, operands[0], 0);
7187 [(set_attr "type" "call")
7188 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7190 ;; This pattern is split if it is necessary to save and restore the
7192 (define_insn "call_symref_64bit"
7193 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7194 (match_operand 1 "" "i"))
7195 (clobber (reg:DI 1))
7196 (clobber (reg:DI 2))
7197 (clobber (reg:DI 4))
7200 (use (const_int 0))]
7204 output_arg_descriptor (insn);
7205 return output_call (insn, operands[0], 0);
7207 [(set_attr "type" "call")
7208 (set (attr "length")
7209 (plus (symbol_ref "attr_length_call (insn, 0)")
7210 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7212 ;; Split out the PIC register save and restore after reload. This is
7213 ;; done only if the function returns. As the split is done after reload,
7214 ;; there are some situations in which we unnecessarily save and restore
7215 ;; %r4. This happens when there is a single call and the PIC register
7216 ;; is "dead" after the call. This isn't easy to fix as the usage of
7217 ;; the PIC register isn't completely determined until the reload pass.
7219 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7220 (match_operand 1 "" ""))
7221 (clobber (reg:DI 1))
7222 (clobber (reg:DI 2))
7223 (clobber (reg:DI 4))
7226 (use (const_int 0))])]
7229 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7230 [(set (reg:DI 4) (reg:DI 27))
7231 (parallel [(call (mem:SI (match_dup 0))
7233 (clobber (reg:DI 1))
7234 (clobber (reg:DI 2))
7237 (use (const_int 0))])
7238 (set (reg:DI 27) (reg:DI 4))]
7241 ;; Remove the clobber of register 4 when optimizing. This has to be
7242 ;; done with a peephole optimization rather than a split because the
7243 ;; split sequence for a call must be longer than one instruction.
7245 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7246 (match_operand 1 "" ""))
7247 (clobber (reg:DI 1))
7248 (clobber (reg:DI 2))
7249 (clobber (reg:DI 4))
7252 (use (const_int 0))])]
7253 "TARGET_64BIT && reload_completed"
7254 [(parallel [(call (mem:SI (match_dup 0))
7256 (clobber (reg:DI 1))
7257 (clobber (reg:DI 2))
7260 (use (const_int 0))])]
7263 (define_insn "*call_symref_64bit_post_reload"
7264 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7265 (match_operand 1 "" "i"))
7266 (clobber (reg:DI 1))
7267 (clobber (reg:DI 2))
7270 (use (const_int 0))]
7274 output_arg_descriptor (insn);
7275 return output_call (insn, operands[0], 0);
7277 [(set_attr "type" "call")
7278 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7280 (define_insn "call_reg"
7281 [(call (mem:SI (reg:SI 22))
7282 (match_operand 0 "" "i"))
7283 (clobber (reg:SI 1))
7284 (clobber (reg:SI 2))
7285 (use (const_int 1))]
7289 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7291 [(set_attr "type" "dyncall")
7292 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7294 ;; This pattern is split if it is necessary to save and restore the
7296 (define_insn "call_reg_pic"
7297 [(call (mem:SI (reg:SI 22))
7298 (match_operand 0 "" "i"))
7299 (clobber (reg:SI 1))
7300 (clobber (reg:SI 2))
7301 (clobber (reg:SI 4))
7303 (use (const_int 1))]
7307 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7309 [(set_attr "type" "dyncall")
7310 (set (attr "length")
7311 (plus (symbol_ref "attr_length_indirect_call (insn)")
7312 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7314 ;; Split out the PIC register save and restore after reload. This is
7315 ;; done only if the function returns. As the split is done after reload,
7316 ;; there are some situations in which we unnecessarily save and restore
7317 ;; %r4. This happens when there is a single call and the PIC register
7318 ;; is "dead" after the call. This isn't easy to fix as the usage of
7319 ;; the PIC register isn't completely determined until the reload pass.
7321 [(parallel [(call (mem:SI (reg:SI 22))
7322 (match_operand 0 "" ""))
7323 (clobber (reg:SI 1))
7324 (clobber (reg:SI 2))
7325 (clobber (reg:SI 4))
7327 (use (const_int 1))])]
7330 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7331 [(set (reg:SI 4) (reg:SI 19))
7332 (parallel [(call (mem:SI (reg:SI 22))
7334 (clobber (reg:SI 1))
7335 (clobber (reg:SI 2))
7337 (use (const_int 1))])
7338 (set (reg:SI 19) (reg:SI 4))]
7341 ;; Remove the clobber of register 4 when optimizing. This has to be
7342 ;; done with a peephole optimization rather than a split because the
7343 ;; split sequence for a call must be longer than one instruction.
7345 [(parallel [(call (mem:SI (reg:SI 22))
7346 (match_operand 0 "" ""))
7347 (clobber (reg:SI 1))
7348 (clobber (reg:SI 2))
7349 (clobber (reg:SI 4))
7351 (use (const_int 1))])]
7352 "!TARGET_64BIT && reload_completed"
7353 [(parallel [(call (mem:SI (reg:SI 22))
7355 (clobber (reg:SI 1))
7356 (clobber (reg:SI 2))
7358 (use (const_int 1))])]
7361 (define_insn "*call_reg_pic_post_reload"
7362 [(call (mem:SI (reg:SI 22))
7363 (match_operand 0 "" "i"))
7364 (clobber (reg:SI 1))
7365 (clobber (reg:SI 2))
7367 (use (const_int 1))]
7371 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7373 [(set_attr "type" "dyncall")
7374 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7376 ;; This pattern is split if it is necessary to save and restore the
7378 (define_insn "call_reg_64bit"
7379 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7380 (match_operand 1 "" "i"))
7381 (clobber (reg:DI 2))
7382 (clobber (reg:DI 4))
7385 (use (const_int 1))]
7389 return output_indirect_call (insn, operands[0]);
7391 [(set_attr "type" "dyncall")
7392 (set (attr "length")
7393 (plus (symbol_ref "attr_length_indirect_call (insn)")
7394 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7396 ;; Split out the PIC register save and restore after reload. This is
7397 ;; done only if the function returns. As the split is done after reload,
7398 ;; there are some situations in which we unnecessarily save and restore
7399 ;; %r4. This happens when there is a single call and the PIC register
7400 ;; is "dead" after the call. This isn't easy to fix as the usage of
7401 ;; the PIC register isn't completely determined until the reload pass.
7403 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7404 (match_operand 1 "" ""))
7405 (clobber (reg:DI 2))
7406 (clobber (reg:DI 4))
7409 (use (const_int 1))])]
7412 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7413 [(set (reg:DI 4) (reg:DI 27))
7414 (parallel [(call (mem:SI (match_dup 0))
7416 (clobber (reg:DI 2))
7419 (use (const_int 1))])
7420 (set (reg:DI 27) (reg:DI 4))]
7423 ;; Remove the clobber of register 4 when optimizing. This has to be
7424 ;; done with a peephole optimization rather than a split because the
7425 ;; split sequence for a call must be longer than one instruction.
7427 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7428 (match_operand 1 "" ""))
7429 (clobber (reg:DI 2))
7430 (clobber (reg:DI 4))
7433 (use (const_int 1))])]
7434 "TARGET_64BIT && reload_completed"
7435 [(parallel [(call (mem:SI (match_dup 0))
7437 (clobber (reg:DI 2))
7440 (use (const_int 1))])]
7443 (define_insn "*call_reg_64bit_post_reload"
7444 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7445 (match_operand 1 "" "i"))
7446 (clobber (reg:DI 2))
7449 (use (const_int 1))]
7453 return output_indirect_call (insn, operands[0]);
7455 [(set_attr "type" "dyncall")
7456 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7458 (define_expand "call_value"
7459 [(parallel [(set (match_operand 0 "" "")
7460 (call (match_operand:SI 1 "" "")
7461 (match_operand 2 "" "")))
7462 (clobber (reg:SI 2))])]
7467 rtx dst = operands[0];
7468 rtx nb = operands[2];
7470 if (TARGET_PORTABLE_RUNTIME)
7471 op = force_reg (SImode, XEXP (operands[1], 0));
7473 op = XEXP (operands[1], 0);
7477 if (!virtuals_instantiated)
7478 emit_move_insn (arg_pointer_rtx,
7479 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7483 /* The loop pass can generate new libcalls after the virtual
7484 registers are instantiated when fpregs are disabled because
7485 the only method that we have for doing DImode multiplication
7486 is with a libcall. This could be trouble if we haven't
7487 allocated enough space for the outgoing arguments. */
7488 if (INTVAL (nb) > current_function_outgoing_args_size)
7491 emit_move_insn (arg_pointer_rtx,
7492 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7493 GEN_INT (STACK_POINTER_OFFSET + 64)));
7497 /* Use two different patterns for calls to explicitly named functions
7498 and calls through function pointers. This is necessary as these two
7499 types of calls use different calling conventions, and CSE might try
7500 to change the named call into an indirect call in some cases (using
7501 two patterns keeps CSE from performing this optimization).
7503 We now use even more call patterns as there was a subtle bug in
7504 attempting to restore the pic register after a call using a simple
7505 move insn. During reload, a instruction involving a pseudo register
7506 with no explicit dependence on the PIC register can be converted
7507 to an equivalent load from memory using the PIC register. If we
7508 emit a simple move to restore the PIC register in the initial rtl
7509 generation, then it can potentially be repositioned during scheduling.
7510 and an instruction that eventually uses the PIC register may end up
7511 between the call and the PIC register restore.
7513 This only worked because there is a post call group of instructions
7514 that are scheduled with the call. These instructions are included
7515 in the same basic block as the call. However, calls can throw in
7516 C++ code and a basic block has to terminate at the call if the call
7517 can throw. This results in the PIC register restore being scheduled
7518 independently from the call. So, we now hide the save and restore
7519 of the PIC register in the call pattern until after reload. Then,
7520 we split the moves out. A small side benefit is that we now don't
7521 need to have a use of the PIC register in the return pattern and
7522 the final save/restore operation is not needed.
7524 I elected to just clobber %r4 in the PIC patterns and use it instead
7525 of trying to force hppa_pic_save_rtx () to a callee saved register.
7526 This might have required a new register class and constraint. It
7527 was also simpler to just handle the restore from a register than a
7531 if (GET_CODE (op) == SYMBOL_REF)
7532 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7535 op = force_reg (word_mode, op);
7536 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7541 if (GET_CODE (op) == SYMBOL_REF)
7544 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7546 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7550 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7552 emit_move_insn (tmpreg, force_reg (word_mode, op));
7554 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7556 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7563 (define_insn "call_val_symref"
7564 [(set (match_operand 0 "" "")
7565 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7566 (match_operand 2 "" "i")))
7567 (clobber (reg:SI 1))
7568 (clobber (reg:SI 2))
7569 (use (const_int 0))]
7570 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7573 output_arg_descriptor (insn);
7574 return output_call (insn, operands[1], 0);
7576 [(set_attr "type" "call")
7577 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7579 (define_insn "call_val_symref_pic"
7580 [(set (match_operand 0 "" "")
7581 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7582 (match_operand 2 "" "i")))
7583 (clobber (reg:SI 1))
7584 (clobber (reg:SI 2))
7585 (clobber (reg:SI 4))
7587 (use (const_int 0))]
7588 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7591 output_arg_descriptor (insn);
7592 return output_call (insn, operands[1], 0);
7594 [(set_attr "type" "call")
7595 (set (attr "length")
7596 (plus (symbol_ref "attr_length_call (insn, 0)")
7597 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7599 ;; Split out the PIC register save and restore after reload. This is
7600 ;; done only if the function returns. As the split is done after reload,
7601 ;; there are some situations in which we unnecessarily save and restore
7602 ;; %r4. This happens when there is a single call and the PIC register
7603 ;; is "dead" after the call. This isn't easy to fix as the usage of
7604 ;; the PIC register isn't completely determined until the reload pass.
7606 [(parallel [(set (match_operand 0 "" "")
7607 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7608 (match_operand 2 "" "")))
7609 (clobber (reg:SI 1))
7610 (clobber (reg:SI 2))
7611 (clobber (reg:SI 4))
7613 (use (const_int 0))])]
7614 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7616 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7617 [(set (reg:SI 4) (reg:SI 19))
7618 (parallel [(set (match_dup 0)
7619 (call (mem:SI (match_dup 1))
7621 (clobber (reg:SI 1))
7622 (clobber (reg:SI 2))
7624 (use (const_int 0))])
7625 (set (reg:SI 19) (reg:SI 4))]
7628 ;; Remove the clobber of register 4 when optimizing. This has to be
7629 ;; done with a peephole optimization rather than a split because the
7630 ;; split sequence for a call must be longer than one instruction.
7632 [(parallel [(set (match_operand 0 "" "")
7633 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7634 (match_operand 2 "" "")))
7635 (clobber (reg:SI 1))
7636 (clobber (reg:SI 2))
7637 (clobber (reg:SI 4))
7639 (use (const_int 0))])]
7640 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7641 [(parallel [(set (match_dup 0)
7642 (call (mem:SI (match_dup 1))
7644 (clobber (reg:SI 1))
7645 (clobber (reg:SI 2))
7647 (use (const_int 0))])]
7650 (define_insn "*call_val_symref_pic_post_reload"
7651 [(set (match_operand 0 "" "")
7652 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7653 (match_operand 2 "" "i")))
7654 (clobber (reg:SI 1))
7655 (clobber (reg:SI 2))
7657 (use (const_int 0))]
7658 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7661 output_arg_descriptor (insn);
7662 return output_call (insn, operands[1], 0);
7664 [(set_attr "type" "call")
7665 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7667 ;; This pattern is split if it is necessary to save and restore the
7669 (define_insn "call_val_symref_64bit"
7670 [(set (match_operand 0 "" "")
7671 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7672 (match_operand 2 "" "i")))
7673 (clobber (reg:DI 1))
7674 (clobber (reg:DI 2))
7675 (clobber (reg:DI 4))
7678 (use (const_int 0))]
7682 output_arg_descriptor (insn);
7683 return output_call (insn, operands[1], 0);
7685 [(set_attr "type" "call")
7686 (set (attr "length")
7687 (plus (symbol_ref "attr_length_call (insn, 0)")
7688 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7690 ;; Split out the PIC register save and restore after reload. This is
7691 ;; done only if the function returns. As the split is done after reload,
7692 ;; there are some situations in which we unnecessarily save and restore
7693 ;; %r4. This happens when there is a single call and the PIC register
7694 ;; is "dead" after the call. This isn't easy to fix as the usage of
7695 ;; the PIC register isn't completely determined until the reload pass.
7697 [(parallel [(set (match_operand 0 "" "")
7698 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7699 (match_operand 2 "" "")))
7700 (clobber (reg:DI 1))
7701 (clobber (reg:DI 2))
7702 (clobber (reg:DI 4))
7705 (use (const_int 0))])]
7708 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7709 [(set (reg:DI 4) (reg:DI 27))
7710 (parallel [(set (match_dup 0)
7711 (call (mem:SI (match_dup 1))
7713 (clobber (reg:DI 1))
7714 (clobber (reg:DI 2))
7717 (use (const_int 0))])
7718 (set (reg:DI 27) (reg:DI 4))]
7721 ;; Remove the clobber of register 4 when optimizing. This has to be
7722 ;; done with a peephole optimization rather than a split because the
7723 ;; split sequence for a call must be longer than one instruction.
7725 [(parallel [(set (match_operand 0 "" "")
7726 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7727 (match_operand 2 "" "")))
7728 (clobber (reg:DI 1))
7729 (clobber (reg:DI 2))
7730 (clobber (reg:DI 4))
7733 (use (const_int 0))])]
7734 "TARGET_64BIT && reload_completed"
7735 [(parallel [(set (match_dup 0)
7736 (call (mem:SI (match_dup 1))
7738 (clobber (reg:DI 1))
7739 (clobber (reg:DI 2))
7742 (use (const_int 0))])]
7745 (define_insn "*call_val_symref_64bit_post_reload"
7746 [(set (match_operand 0 "" "")
7747 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7748 (match_operand 2 "" "i")))
7749 (clobber (reg:DI 1))
7750 (clobber (reg:DI 2))
7753 (use (const_int 0))]
7757 output_arg_descriptor (insn);
7758 return output_call (insn, operands[1], 0);
7760 [(set_attr "type" "call")
7761 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7763 (define_insn "call_val_reg"
7764 [(set (match_operand 0 "" "")
7765 (call (mem:SI (reg:SI 22))
7766 (match_operand 1 "" "i")))
7767 (clobber (reg:SI 1))
7768 (clobber (reg:SI 2))
7769 (use (const_int 1))]
7773 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7775 [(set_attr "type" "dyncall")
7776 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7778 ;; This pattern is split if it is necessary to save and restore the
7780 (define_insn "call_val_reg_pic"
7781 [(set (match_operand 0 "" "")
7782 (call (mem:SI (reg:SI 22))
7783 (match_operand 1 "" "i")))
7784 (clobber (reg:SI 1))
7785 (clobber (reg:SI 2))
7786 (clobber (reg:SI 4))
7788 (use (const_int 1))]
7792 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7794 [(set_attr "type" "dyncall")
7795 (set (attr "length")
7796 (plus (symbol_ref "attr_length_indirect_call (insn)")
7797 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7799 ;; Split out the PIC register save and restore after reload. This is
7800 ;; done only if the function returns. As the split is done after reload,
7801 ;; there are some situations in which we unnecessarily save and restore
7802 ;; %r4. This happens when there is a single call and the PIC register
7803 ;; is "dead" after the call. This isn't easy to fix as the usage of
7804 ;; the PIC register isn't completely determined until the reload pass.
7806 [(parallel [(set (match_operand 0 "" "")
7807 (call (mem:SI (reg:SI 22))
7808 (match_operand 1 "" "")))
7809 (clobber (reg:SI 1))
7810 (clobber (reg:SI 2))
7811 (clobber (reg:SI 4))
7813 (use (const_int 1))])]
7816 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7817 [(set (reg:SI 4) (reg:SI 19))
7818 (parallel [(set (match_dup 0)
7819 (call (mem:SI (reg:SI 22))
7821 (clobber (reg:SI 1))
7822 (clobber (reg:SI 2))
7824 (use (const_int 1))])
7825 (set (reg:SI 19) (reg:SI 4))]
7828 ;; Remove the clobber of register 4 when optimizing. This has to be
7829 ;; done with a peephole optimization rather than a split because the
7830 ;; split sequence for a call must be longer than one instruction.
7832 [(parallel [(set (match_operand 0 "" "")
7833 (call (mem:SI (reg:SI 22))
7834 (match_operand 1 "" "")))
7835 (clobber (reg:SI 1))
7836 (clobber (reg:SI 2))
7837 (clobber (reg:SI 4))
7839 (use (const_int 1))])]
7840 "!TARGET_64BIT && reload_completed"
7841 [(parallel [(set (match_dup 0)
7842 (call (mem:SI (reg:SI 22))
7844 (clobber (reg:SI 1))
7845 (clobber (reg:SI 2))
7847 (use (const_int 1))])]
7850 (define_insn "*call_val_reg_pic_post_reload"
7851 [(set (match_operand 0 "" "")
7852 (call (mem:SI (reg:SI 22))
7853 (match_operand 1 "" "i")))
7854 (clobber (reg:SI 1))
7855 (clobber (reg:SI 2))
7857 (use (const_int 1))]
7861 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7863 [(set_attr "type" "dyncall")
7864 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7866 ;; This pattern is split if it is necessary to save and restore the
7868 (define_insn "call_val_reg_64bit"
7869 [(set (match_operand 0 "" "")
7870 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7871 (match_operand 2 "" "i")))
7872 (clobber (reg:DI 2))
7873 (clobber (reg:DI 4))
7876 (use (const_int 1))]
7880 return output_indirect_call (insn, operands[1]);
7882 [(set_attr "type" "dyncall")
7883 (set (attr "length")
7884 (plus (symbol_ref "attr_length_indirect_call (insn)")
7885 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7887 ;; Split out the PIC register save and restore after reload. This is
7888 ;; done only if the function returns. As the split is done after reload,
7889 ;; there are some situations in which we unnecessarily save and restore
7890 ;; %r4. This happens when there is a single call and the PIC register
7891 ;; is "dead" after the call. This isn't easy to fix as the usage of
7892 ;; the PIC register isn't completely determined until the reload pass.
7894 [(parallel [(set (match_operand 0 "" "")
7895 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7896 (match_operand 2 "" "")))
7897 (clobber (reg:DI 2))
7898 (clobber (reg:DI 4))
7901 (use (const_int 1))])]
7904 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7905 [(set (reg:DI 4) (reg:DI 27))
7906 (parallel [(set (match_dup 0)
7907 (call (mem:SI (match_dup 1))
7909 (clobber (reg:DI 2))
7912 (use (const_int 1))])
7913 (set (reg:DI 27) (reg:DI 4))]
7916 ;; Remove the clobber of register 4 when optimizing. This has to be
7917 ;; done with a peephole optimization rather than a split because the
7918 ;; split sequence for a call must be longer than one instruction.
7920 [(parallel [(set (match_operand 0 "" "")
7921 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7922 (match_operand 2 "" "")))
7923 (clobber (reg:DI 2))
7924 (clobber (reg:DI 4))
7927 (use (const_int 1))])]
7928 "TARGET_64BIT && reload_completed"
7929 [(parallel [(set (match_dup 0)
7930 (call (mem:SI (match_dup 1))
7932 (clobber (reg:DI 2))
7935 (use (const_int 1))])]
7938 (define_insn "*call_val_reg_64bit_post_reload"
7939 [(set (match_operand 0 "" "")
7940 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7941 (match_operand 2 "" "i")))
7942 (clobber (reg:DI 2))
7945 (use (const_int 1))]
7949 return output_indirect_call (insn, operands[1]);
7951 [(set_attr "type" "dyncall")
7952 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7954 ;; Call subroutine returning any type.
7956 (define_expand "untyped_call"
7957 [(parallel [(call (match_operand 0 "" "")
7959 (match_operand 1 "" "")
7960 (match_operand 2 "" "")])]
7966 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7968 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7970 rtx set = XVECEXP (operands[2], 0, i);
7971 emit_move_insn (SET_DEST (set), SET_SRC (set));
7974 /* The optimizer does not know that the call sets the function value
7975 registers we stored in the result block. We avoid problems by
7976 claiming that all hard registers are used and clobbered at this
7978 emit_insn (gen_blockage ());
7983 (define_expand "sibcall"
7984 [(call (match_operand:SI 0 "" "")
7985 (match_operand 1 "" ""))]
7986 "!TARGET_PORTABLE_RUNTIME"
7990 rtx nb = operands[1];
7992 op = XEXP (operands[0], 0);
7996 if (!virtuals_instantiated)
7997 emit_move_insn (arg_pointer_rtx,
7998 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8002 /* The loop pass can generate new libcalls after the virtual
8003 registers are instantiated when fpregs are disabled because
8004 the only method that we have for doing DImode multiplication
8005 is with a libcall. This could be trouble if we haven't
8006 allocated enough space for the outgoing arguments. */
8007 if (INTVAL (nb) > current_function_outgoing_args_size)
8010 emit_move_insn (arg_pointer_rtx,
8011 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8012 GEN_INT (STACK_POINTER_OFFSET + 64)));
8016 /* Indirect sibling calls are not allowed. */
8018 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8020 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8022 call_insn = emit_call_insn (call_insn);
8025 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8027 /* We don't have to restore the PIC register. */
8029 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8034 (define_insn "sibcall_internal_symref"
8035 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8036 (match_operand 1 "" "i"))
8037 (clobber (reg:SI 1))
8039 (use (const_int 0))]
8040 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8043 output_arg_descriptor (insn);
8044 return output_call (insn, operands[0], 1);
8046 [(set_attr "type" "call")
8047 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8049 (define_insn "sibcall_internal_symref_64bit"
8050 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8051 (match_operand 1 "" "i"))
8052 (clobber (reg:DI 1))
8054 (use (const_int 0))]
8058 output_arg_descriptor (insn);
8059 return output_call (insn, operands[0], 1);
8061 [(set_attr "type" "call")
8062 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8064 (define_expand "sibcall_value"
8065 [(set (match_operand 0 "" "")
8066 (call (match_operand:SI 1 "" "")
8067 (match_operand 2 "" "")))]
8068 "!TARGET_PORTABLE_RUNTIME"
8072 rtx nb = operands[1];
8074 op = XEXP (operands[1], 0);
8078 if (!virtuals_instantiated)
8079 emit_move_insn (arg_pointer_rtx,
8080 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8084 /* The loop pass can generate new libcalls after the virtual
8085 registers are instantiated when fpregs are disabled because
8086 the only method that we have for doing DImode multiplication
8087 is with a libcall. This could be trouble if we haven't
8088 allocated enough space for the outgoing arguments. */
8089 if (INTVAL (nb) > current_function_outgoing_args_size)
8092 emit_move_insn (arg_pointer_rtx,
8093 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8094 GEN_INT (STACK_POINTER_OFFSET + 64)));
8098 /* Indirect sibling calls are not allowed. */
8101 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8104 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8106 call_insn = emit_call_insn (call_insn);
8109 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8111 /* We don't have to restore the PIC register. */
8113 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8118 (define_insn "sibcall_value_internal_symref"
8119 [(set (match_operand 0 "" "")
8120 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8121 (match_operand 2 "" "i")))
8122 (clobber (reg:SI 1))
8124 (use (const_int 0))]
8125 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8128 output_arg_descriptor (insn);
8129 return output_call (insn, operands[1], 1);
8131 [(set_attr "type" "call")
8132 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8134 (define_insn "sibcall_value_internal_symref_64bit"
8135 [(set (match_operand 0 "" "")
8136 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8137 (match_operand 2 "" "i")))
8138 (clobber (reg:DI 1))
8140 (use (const_int 0))]
8144 output_arg_descriptor (insn);
8145 return output_call (insn, operands[1], 1);
8147 [(set_attr "type" "call")
8148 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8154 [(set_attr "type" "move")
8155 (set_attr "length" "4")])
8157 ;; These are just placeholders so we know where branch tables
8159 (define_insn "begin_brtab"
8164 /* Only GAS actually supports this pseudo-op. */
8166 return \".begin_brtab\";
8170 [(set_attr "type" "move")
8171 (set_attr "length" "0")])
8173 (define_insn "end_brtab"
8178 /* Only GAS actually supports this pseudo-op. */
8180 return \".end_brtab\";
8184 [(set_attr "type" "move")
8185 (set_attr "length" "0")])
8187 ;;; EH does longjmp's from and within the data section. Thus,
8188 ;;; an interspace branch is required for the longjmp implementation.
8189 ;;; Registers r1 and r2 are used as scratch registers for the jump
8191 (define_expand "interspace_jump"
8193 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8194 (clobber (match_dup 1))])]
8198 operands[1] = gen_rtx_REG (word_mode, 2);
8202 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8203 (clobber (reg:SI 2))]
8204 "TARGET_PA_20 && !TARGET_64BIT"
8206 [(set_attr "type" "branch")
8207 (set_attr "length" "4")])
8210 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8211 (clobber (reg:SI 2))]
8212 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8214 [(set_attr "type" "branch")
8215 (set_attr "length" "4")])
8218 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8219 (clobber (reg:SI 2))]
8221 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
8222 [(set_attr "type" "branch")
8223 (set_attr "length" "12")])
8226 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8227 (clobber (reg:DI 2))]
8230 [(set_attr "type" "branch")
8231 (set_attr "length" "4")])
8233 (define_expand "builtin_longjmp"
8234 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
8238 /* The elements of the buffer are, in order: */
8239 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8240 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8241 POINTER_SIZE / BITS_PER_UNIT));
8242 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8243 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8244 rtx pv = gen_rtx_REG (Pmode, 1);
8246 /* This bit is the same as expand_builtin_longjmp. */
8247 emit_move_insn (hard_frame_pointer_rtx, fp);
8248 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8249 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8250 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8252 /* Load the label we are jumping through into r1 so that we know
8253 where to look for it when we get back to setjmp's function for
8254 restoring the gp. */
8255 emit_move_insn (pv, lab);
8257 /* Prevent the insns above from being scheduled into the delay slot
8258 of the interspace jump because the space register could change. */
8259 emit_insn (gen_blockage ());
8261 emit_jump_insn (gen_interspace_jump (pv));
8266 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8267 (define_expand "extzv"
8268 [(set (match_operand 0 "register_operand" "")
8269 (zero_extract (match_operand 1 "register_operand" "")
8270 (match_operand 2 "uint32_operand" "")
8271 (match_operand 3 "uint32_operand" "")))]
8275 HOST_WIDE_INT len = INTVAL (operands[2]);
8276 HOST_WIDE_INT pos = INTVAL (operands[3]);
8278 /* PA extraction insns don't support zero length bitfields or fields
8279 extending beyond the left or right-most bits. Also, we reject lengths
8280 equal to a word as they are better handled by the move patterns. */
8281 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8284 /* From mips.md: extract_bit_field doesn't verify that our source
8285 matches the predicate, so check it again here. */
8286 if (!register_operand (operands[1], VOIDmode))
8290 emit_insn (gen_extzv_64 (operands[0], operands[1],
8291 operands[2], operands[3]));
8293 emit_insn (gen_extzv_32 (operands[0], operands[1],
8294 operands[2], operands[3]));
8298 (define_insn "extzv_32"
8299 [(set (match_operand:SI 0 "register_operand" "=r")
8300 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8301 (match_operand:SI 2 "uint5_operand" "")
8302 (match_operand:SI 3 "uint5_operand" "")))]
8304 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8305 [(set_attr "type" "shift")
8306 (set_attr "length" "4")])
8309 [(set (match_operand:SI 0 "register_operand" "=r")
8310 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8312 (match_operand:SI 2 "register_operand" "q")))]
8314 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8315 [(set_attr "type" "shift")
8316 (set_attr "length" "4")])
8318 (define_insn "extzv_64"
8319 [(set (match_operand:DI 0 "register_operand" "=r")
8320 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8321 (match_operand:DI 2 "uint32_operand" "")
8322 (match_operand:DI 3 "uint32_operand" "")))]
8324 "extrd,u %1,%3+%2-1,%2,%0"
8325 [(set_attr "type" "shift")
8326 (set_attr "length" "4")])
8329 [(set (match_operand:DI 0 "register_operand" "=r")
8330 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8332 (match_operand:DI 2 "register_operand" "q")))]
8334 "extrd,u %1,%%sar,1,%0"
8335 [(set_attr "type" "shift")
8336 (set_attr "length" "4")])
8338 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8339 (define_expand "extv"
8340 [(set (match_operand 0 "register_operand" "")
8341 (sign_extract (match_operand 1 "register_operand" "")
8342 (match_operand 2 "uint32_operand" "")
8343 (match_operand 3 "uint32_operand" "")))]
8347 HOST_WIDE_INT len = INTVAL (operands[2]);
8348 HOST_WIDE_INT pos = INTVAL (operands[3]);
8350 /* PA extraction insns don't support zero length bitfields or fields
8351 extending beyond the left or right-most bits. Also, we reject lengths
8352 equal to a word as they are better handled by the move patterns. */
8353 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8356 /* From mips.md: extract_bit_field doesn't verify that our source
8357 matches the predicate, so check it again here. */
8358 if (!register_operand (operands[1], VOIDmode))
8362 emit_insn (gen_extv_64 (operands[0], operands[1],
8363 operands[2], operands[3]));
8365 emit_insn (gen_extv_32 (operands[0], operands[1],
8366 operands[2], operands[3]));
8370 (define_insn "extv_32"
8371 [(set (match_operand:SI 0 "register_operand" "=r")
8372 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8373 (match_operand:SI 2 "uint5_operand" "")
8374 (match_operand:SI 3 "uint5_operand" "")))]
8376 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8377 [(set_attr "type" "shift")
8378 (set_attr "length" "4")])
8381 [(set (match_operand:SI 0 "register_operand" "=r")
8382 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8384 (match_operand:SI 2 "register_operand" "q")))]
8386 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8387 [(set_attr "type" "shift")
8388 (set_attr "length" "4")])
8390 (define_insn "extv_64"
8391 [(set (match_operand:DI 0 "register_operand" "=r")
8392 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8393 (match_operand:DI 2 "uint32_operand" "")
8394 (match_operand:DI 3 "uint32_operand" "")))]
8396 "extrd,s %1,%3+%2-1,%2,%0"
8397 [(set_attr "type" "shift")
8398 (set_attr "length" "4")])
8401 [(set (match_operand:DI 0 "register_operand" "=r")
8402 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8404 (match_operand:DI 2 "register_operand" "q")))]
8406 "extrd,s %1,%%sar,1,%0"
8407 [(set_attr "type" "shift")
8408 (set_attr "length" "4")])
8410 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8411 (define_expand "insv"
8412 [(set (zero_extract (match_operand 0 "register_operand" "")
8413 (match_operand 1 "uint32_operand" "")
8414 (match_operand 2 "uint32_operand" ""))
8415 (match_operand 3 "arith5_operand" ""))]
8419 HOST_WIDE_INT len = INTVAL (operands[1]);
8420 HOST_WIDE_INT pos = INTVAL (operands[2]);
8422 /* PA insertion insns don't support zero length bitfields or fields
8423 extending beyond the left or right-most bits. Also, we reject lengths
8424 equal to a word as they are better handled by the move patterns. */
8425 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8428 /* From mips.md: insert_bit_field doesn't verify that our destination
8429 matches the predicate, so check it again here. */
8430 if (!register_operand (operands[0], VOIDmode))
8434 emit_insn (gen_insv_64 (operands[0], operands[1],
8435 operands[2], operands[3]));
8437 emit_insn (gen_insv_32 (operands[0], operands[1],
8438 operands[2], operands[3]));
8442 (define_insn "insv_32"
8443 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8444 (match_operand:SI 1 "uint5_operand" "")
8445 (match_operand:SI 2 "uint5_operand" ""))
8446 (match_operand:SI 3 "arith5_operand" "r,L"))]
8449 {dep|depw} %3,%2+%1-1,%1,%0
8450 {depi|depwi} %3,%2+%1-1,%1,%0"
8451 [(set_attr "type" "shift,shift")
8452 (set_attr "length" "4,4")])
8454 ;; Optimize insertion of const_int values of type 1...1xxxx.
8456 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8457 (match_operand:SI 1 "uint5_operand" "")
8458 (match_operand:SI 2 "uint5_operand" ""))
8459 (match_operand:SI 3 "const_int_operand" ""))]
8460 "(INTVAL (operands[3]) & 0x10) != 0 &&
8461 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8464 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8465 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8467 [(set_attr "type" "shift")
8468 (set_attr "length" "4")])
8470 (define_insn "insv_64"
8471 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8472 (match_operand:DI 1 "uint32_operand" "")
8473 (match_operand:DI 2 "uint32_operand" ""))
8474 (match_operand:DI 3 "arith32_operand" "r,L"))]
8477 depd %3,%2+%1-1,%1,%0
8478 depdi %3,%2+%1-1,%1,%0"
8479 [(set_attr "type" "shift,shift")
8480 (set_attr "length" "4,4")])
8482 ;; Optimize insertion of const_int values of type 1...1xxxx.
8484 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8485 (match_operand:DI 1 "uint32_operand" "")
8486 (match_operand:DI 2 "uint32_operand" ""))
8487 (match_operand:DI 3 "const_int_operand" ""))]
8488 "(INTVAL (operands[3]) & 0x10) != 0
8490 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8493 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8494 return \"depdi %3,%2+%1-1,%1,%0\";
8496 [(set_attr "type" "shift")
8497 (set_attr "length" "4")])
8500 [(set (match_operand:DI 0 "register_operand" "=r")
8501 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8504 "depd,z %1,31,32,%0"
8505 [(set_attr "type" "shift")
8506 (set_attr "length" "4")])
8508 ;; This insn is used for some loop tests, typically loops reversed when
8509 ;; strength reduction is used. It is actually created when the instruction
8510 ;; combination phase combines the special loop test. Since this insn
8511 ;; is both a jump insn and has an output, it must deal with its own
8512 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8513 ;; to not choose the register alternatives in the event a reload is needed.
8514 (define_insn "decrement_and_branch_until_zero"
8517 (match_operator 2 "comparison_operator"
8519 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8520 (match_operand:SI 1 "int5_operand" "L,L,L"))
8522 (label_ref (match_operand 3 "" ""))
8525 (plus:SI (match_dup 0) (match_dup 1)))
8526 (clobber (match_scratch:SI 4 "=X,r,r"))]
8528 "* return output_dbra (operands, insn, which_alternative); "
8529 ;; Do not expect to understand this the first time through.
8530 [(set_attr "type" "cbranch,multi,multi")
8531 (set (attr "length")
8532 (if_then_else (eq_attr "alternative" "0")
8533 ;; Loop counter in register case
8534 ;; Short branch has length of 4
8535 ;; Long branch has length of 8
8536 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8541 ;; Loop counter in FP reg case.
8542 ;; Extra goo to deal with additional reload insns.
8543 (if_then_else (eq_attr "alternative" "1")
8544 (if_then_else (lt (match_dup 3) (pc))
8546 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8551 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8555 ;; Loop counter in memory case.
8556 ;; Extra goo to deal with additional reload insns.
8557 (if_then_else (lt (match_dup 3) (pc))
8559 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8564 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8567 (const_int 16))))))])
8572 (match_operator 2 "movb_comparison_operator"
8573 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8574 (label_ref (match_operand 3 "" ""))
8576 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8579 "* return output_movb (operands, insn, which_alternative, 0); "
8580 ;; Do not expect to understand this the first time through.
8581 [(set_attr "type" "cbranch,multi,multi,multi")
8582 (set (attr "length")
8583 (if_then_else (eq_attr "alternative" "0")
8584 ;; Loop counter in register case
8585 ;; Short branch has length of 4
8586 ;; Long branch has length of 8
8587 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8592 ;; Loop counter in FP reg case.
8593 ;; Extra goo to deal with additional reload insns.
8594 (if_then_else (eq_attr "alternative" "1")
8595 (if_then_else (lt (match_dup 3) (pc))
8597 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8602 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8606 ;; Loop counter in memory or sar case.
8607 ;; Extra goo to deal with additional reload insns.
8609 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8612 (const_int 12)))))])
8614 ;; Handle negated branch.
8618 (match_operator 2 "movb_comparison_operator"
8619 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8621 (label_ref (match_operand 3 "" ""))))
8622 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8625 "* return output_movb (operands, insn, which_alternative, 1); "
8626 ;; Do not expect to understand this the first time through.
8627 [(set_attr "type" "cbranch,multi,multi,multi")
8628 (set (attr "length")
8629 (if_then_else (eq_attr "alternative" "0")
8630 ;; Loop counter in register case
8631 ;; Short branch has length of 4
8632 ;; Long branch has length of 8
8633 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8638 ;; Loop counter in FP reg case.
8639 ;; Extra goo to deal with additional reload insns.
8640 (if_then_else (eq_attr "alternative" "1")
8641 (if_then_else (lt (match_dup 3) (pc))
8643 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8648 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8652 ;; Loop counter in memory or SAR case.
8653 ;; Extra goo to deal with additional reload insns.
8655 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8658 (const_int 12)))))])
8661 [(set (pc) (label_ref (match_operand 3 "" "" )))
8662 (set (match_operand:SI 0 "ireg_operand" "=r")
8663 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8664 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8665 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8668 return output_parallel_addb (operands, get_attr_length (insn));
8670 [(set_attr "type" "parallel_branch")
8671 (set (attr "length")
8672 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8678 [(set (pc) (label_ref (match_operand 2 "" "" )))
8679 (set (match_operand:SF 0 "ireg_operand" "=r")
8680 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8684 return output_parallel_movb (operands, get_attr_length (insn));
8686 [(set_attr "type" "parallel_branch")
8687 (set (attr "length")
8688 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8694 [(set (pc) (label_ref (match_operand 2 "" "" )))
8695 (set (match_operand:SI 0 "ireg_operand" "=r")
8696 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8700 return output_parallel_movb (operands, get_attr_length (insn));
8702 [(set_attr "type" "parallel_branch")
8703 (set (attr "length")
8704 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8710 [(set (pc) (label_ref (match_operand 2 "" "" )))
8711 (set (match_operand:HI 0 "ireg_operand" "=r")
8712 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8716 return output_parallel_movb (operands, get_attr_length (insn));
8718 [(set_attr "type" "parallel_branch")
8719 (set (attr "length")
8720 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8726 [(set (pc) (label_ref (match_operand 2 "" "" )))
8727 (set (match_operand:QI 0 "ireg_operand" "=r")
8728 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8732 return output_parallel_movb (operands, get_attr_length (insn));
8734 [(set_attr "type" "parallel_branch")
8735 (set (attr "length")
8736 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8742 [(set (match_operand 0 "register_operand" "=f")
8743 (mult (match_operand 1 "register_operand" "f")
8744 (match_operand 2 "register_operand" "f")))
8745 (set (match_operand 3 "register_operand" "+f")
8746 (plus (match_operand 4 "register_operand" "f")
8747 (match_operand 5 "register_operand" "f")))]
8748 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8749 && reload_completed && fmpyaddoperands (operands)"
8752 if (GET_MODE (operands[0]) == DFmode)
8754 if (rtx_equal_p (operands[3], operands[5]))
8755 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8757 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8761 if (rtx_equal_p (operands[3], operands[5]))
8762 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8764 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8767 [(set_attr "type" "fpalu")
8768 (set_attr "length" "4")])
8771 [(set (match_operand 3 "register_operand" "+f")
8772 (plus (match_operand 4 "register_operand" "f")
8773 (match_operand 5 "register_operand" "f")))
8774 (set (match_operand 0 "register_operand" "=f")
8775 (mult (match_operand 1 "register_operand" "f")
8776 (match_operand 2 "register_operand" "f")))]
8777 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8778 && reload_completed && fmpyaddoperands (operands)"
8781 if (GET_MODE (operands[0]) == DFmode)
8783 if (rtx_equal_p (operands[3], operands[5]))
8784 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8786 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8790 if (rtx_equal_p (operands[3], operands[5]))
8791 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8793 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8796 [(set_attr "type" "fpalu")
8797 (set_attr "length" "4")])
8800 [(set (match_operand 0 "register_operand" "=f")
8801 (mult (match_operand 1 "register_operand" "f")
8802 (match_operand 2 "register_operand" "f")))
8803 (set (match_operand 3 "register_operand" "+f")
8804 (minus (match_operand 4 "register_operand" "f")
8805 (match_operand 5 "register_operand" "f")))]
8806 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8807 && reload_completed && fmpysuboperands (operands)"
8810 if (GET_MODE (operands[0]) == DFmode)
8811 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8813 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8815 [(set_attr "type" "fpalu")
8816 (set_attr "length" "4")])
8819 [(set (match_operand 3 "register_operand" "+f")
8820 (minus (match_operand 4 "register_operand" "f")
8821 (match_operand 5 "register_operand" "f")))
8822 (set (match_operand 0 "register_operand" "=f")
8823 (mult (match_operand 1 "register_operand" "f")
8824 (match_operand 2 "register_operand" "f")))]
8825 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8826 && reload_completed && fmpysuboperands (operands)"
8829 if (GET_MODE (operands[0]) == DFmode)
8830 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8832 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8834 [(set_attr "type" "fpalu")
8835 (set_attr "length" "4")])
8837 ;; Clean up turds left by reload.
8839 [(set (match_operand 0 "move_dest_operand" "")
8840 (match_operand 1 "register_operand" "fr"))
8841 (set (match_operand 2 "register_operand" "fr")
8844 && GET_CODE (operands[0]) == MEM
8845 && ! MEM_VOLATILE_P (operands[0])
8846 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8847 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8848 && GET_MODE (operands[0]) == DFmode
8849 && GET_CODE (operands[1]) == REG
8850 && GET_CODE (operands[2]) == REG
8851 && ! side_effects_p (XEXP (operands[0], 0))
8852 && REGNO_REG_CLASS (REGNO (operands[1]))
8853 == REGNO_REG_CLASS (REGNO (operands[2]))"
8858 if (FP_REG_P (operands[1]))
8859 output_asm_insn (output_fp_move_double (operands), operands);
8861 output_asm_insn (output_move_double (operands), operands);
8863 if (rtx_equal_p (operands[1], operands[2]))
8866 xoperands[0] = operands[2];
8867 xoperands[1] = operands[1];
8869 if (FP_REG_P (xoperands[1]))
8870 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8872 output_asm_insn (output_move_double (xoperands), xoperands);
8878 [(set (match_operand 0 "register_operand" "fr")
8879 (match_operand 1 "move_src_operand" ""))
8880 (set (match_operand 2 "register_operand" "fr")
8883 && GET_CODE (operands[1]) == MEM
8884 && ! MEM_VOLATILE_P (operands[1])
8885 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8886 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8887 && GET_MODE (operands[0]) == DFmode
8888 && GET_CODE (operands[0]) == REG
8889 && GET_CODE (operands[2]) == REG
8890 && ! side_effects_p (XEXP (operands[1], 0))
8891 && REGNO_REG_CLASS (REGNO (operands[0]))
8892 == REGNO_REG_CLASS (REGNO (operands[2]))"
8897 if (FP_REG_P (operands[0]))
8898 output_asm_insn (output_fp_move_double (operands), operands);
8900 output_asm_insn (output_move_double (operands), operands);
8902 xoperands[0] = operands[2];
8903 xoperands[1] = operands[0];
8905 if (FP_REG_P (xoperands[1]))
8906 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8908 output_asm_insn (output_move_double (xoperands), xoperands);
8913 ;; Flush the I and D cache lines from the start address (operand0)
8914 ;; to the end address (operand1). No lines are flushed if the end
8915 ;; address is less than the start address (unsigned).
8917 ;; Because the range of memory flushed is variable and the size of
8918 ;; a MEM can only be a CONST_INT, the patterns specify that they
8919 ;; perform an unspecified volatile operation on all memory.
8921 ;; The address range for an icache flush must lie within a single
8922 ;; space on targets with non-equivalent space registers.
8924 ;; This is used by the trampoline code for nested functions.
8926 ;; Operand 0 contains the start address.
8927 ;; Operand 1 contains the end address.
8928 ;; Operand 2 contains the line length to use.
8929 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
8930 (define_insn "dcacheflush"
8932 (unspec_volatile [(mem:BLK (scratch))] 0)
8933 (use (match_operand 0 "pmode_register_operand" "r"))
8934 (use (match_operand 1 "pmode_register_operand" "r"))
8935 (use (match_operand 2 "pmode_register_operand" "r"))
8936 (clobber (match_scratch 3 "=&0"))]
8941 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8943 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8945 [(set_attr "type" "multi")
8946 (set_attr "length" "12")])
8948 (define_insn "icacheflush"
8950 (unspec_volatile [(mem:BLK (scratch))] 0)
8951 (use (match_operand 0 "pmode_register_operand" "r"))
8952 (use (match_operand 1 "pmode_register_operand" "r"))
8953 (use (match_operand 2 "pmode_register_operand" "r"))
8954 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8955 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
8956 (clobber (match_scratch 5 "=&0"))]
8961 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8963 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8965 [(set_attr "type" "multi")
8966 (set_attr "length" "52")])
8968 ;; An out-of-line prologue.
8969 (define_insn "outline_prologue_call"
8970 [(unspec_volatile [(const_int 0)] 0)
8971 (clobber (reg:SI 31))
8972 (clobber (reg:SI 22))
8973 (clobber (reg:SI 21))
8974 (clobber (reg:SI 20))
8975 (clobber (reg:SI 19))
8976 (clobber (reg:SI 1))]
8980 extern int frame_pointer_needed;
8982 /* We need two different versions depending on whether or not we
8983 need a frame pointer. Also note that we return to the instruction
8984 immediately after the branch rather than two instructions after the
8985 break as normally is the case. */
8986 if (frame_pointer_needed)
8988 /* Must import the magic millicode routine(s). */
8989 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
8991 if (TARGET_PORTABLE_RUNTIME)
8993 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
8994 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
8998 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9002 /* Must import the magic millicode routine(s). */
9003 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9005 if (TARGET_PORTABLE_RUNTIME)
9007 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9008 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9011 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9015 [(set_attr "type" "multi")
9016 (set_attr "length" "8")])
9018 ;; An out-of-line epilogue.
9019 (define_insn "outline_epilogue_call"
9020 [(unspec_volatile [(const_int 1)] 0)
9023 (clobber (reg:SI 31))
9024 (clobber (reg:SI 22))
9025 (clobber (reg:SI 21))
9026 (clobber (reg:SI 20))
9027 (clobber (reg:SI 19))
9028 (clobber (reg:SI 2))
9029 (clobber (reg:SI 1))]
9033 extern int frame_pointer_needed;
9035 /* We need two different versions depending on whether or not we
9036 need a frame pointer. Also note that we return to the instruction
9037 immediately after the branch rather than two instructions after the
9038 break as normally is the case. */
9039 if (frame_pointer_needed)
9041 /* Must import the magic millicode routine. */
9042 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9044 /* The out-of-line prologue will make sure we return to the right
9046 if (TARGET_PORTABLE_RUNTIME)
9048 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9049 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9053 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9057 /* Must import the magic millicode routine. */
9058 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9060 /* The out-of-line prologue will make sure we return to the right
9062 if (TARGET_PORTABLE_RUNTIME)
9064 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9065 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9068 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9072 [(set_attr "type" "multi")
9073 (set_attr "length" "8")])
9075 ;; Given a function pointer, canonicalize it so it can be
9076 ;; reliably compared to another function pointer. */
9077 (define_expand "canonicalize_funcptr_for_compare"
9078 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9079 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9080 (clobber (match_dup 2))
9081 (clobber (reg:SI 26))
9082 (clobber (reg:SI 22))
9083 (clobber (reg:SI 31))])
9084 (set (match_operand:SI 0 "register_operand" "")
9086 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9091 rtx canonicalize_funcptr_for_compare_libfunc
9092 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9094 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9095 operands[0], LCT_NORMAL, Pmode,
9096 1, operands[1], Pmode);
9100 operands[2] = gen_reg_rtx (SImode);
9101 if (GET_CODE (operands[1]) != REG)
9103 rtx tmp = gen_reg_rtx (Pmode);
9104 emit_move_insn (tmp, operands[1]);
9110 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9111 (clobber (match_operand:SI 0 "register_operand" "=a"))
9112 (clobber (reg:SI 26))
9113 (clobber (reg:SI 22))
9114 (clobber (reg:SI 31))]
9118 int length = get_attr_length (insn);
9121 xoperands[0] = GEN_INT (length - 8);
9122 xoperands[1] = GEN_INT (length - 16);
9124 /* Must import the magic millicode routine. */
9125 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9127 /* This is absolutely amazing.
9129 First, copy our input parameter into %r29 just in case we don't
9130 need to call $$sh_func_adrs. */
9131 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9132 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9134 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9135 we use %r26 unchanged. */
9136 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9137 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9139 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9140 4096, then again we use %r26 unchanged. */
9141 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9143 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9144 return output_millicode_call (insn,
9145 gen_rtx_SYMBOL_REF (SImode,
9146 \"$$sh_func_adrs\"));
9148 [(set_attr "type" "multi")
9149 (set (attr "length")
9150 (plus (symbol_ref "attr_length_millicode_call (insn)")
9153 ;; On the PA, the PIC register is call clobbered, so it must
9154 ;; be saved & restored around calls by the caller. If the call
9155 ;; doesn't return normally (nonlocal goto, or an exception is
9156 ;; thrown), then the code at the exception handler label must
9157 ;; restore the PIC register.
9158 (define_expand "exception_receiver"
9163 /* On the 64-bit port, we need a blockage because there is
9164 confusion regarding the dependence of the restore on the
9165 frame pointer. As a result, the frame pointer and pic
9166 register restores sometimes are interchanged erroneously. */
9168 emit_insn (gen_blockage ());
9169 /* Restore the PIC register using hppa_pic_save_rtx (). The
9170 PIC register is not saved in the frame in 64-bit ABI. */
9171 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9172 emit_insn (gen_blockage ());
9176 (define_expand "builtin_setjmp_receiver"
9177 [(label_ref (match_operand 0 "" ""))]
9182 emit_insn (gen_blockage ());
9183 /* Restore the PIC register. Hopefully, this will always be from
9184 a stack slot. The only registers that are valid after a
9185 builtin_longjmp are the stack and frame pointers. */
9186 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9187 emit_insn (gen_blockage ());
9191 ;; Allocate new stack space and update the saved stack pointer in the
9192 ;; frame marker. The HP C compilers also copy additional words in the
9193 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9194 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9195 ;; currently don't copy these values.
9197 ;; Since the copy of the frame marker can't be done atomically, I
9198 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9199 ;; The HP compilers appear to raise the stack and copy the frame
9200 ;; marker in a strict instruction sequence. This suggests that the
9201 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9202 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9203 ;; as GAS doesn't support it, or try to keep the instructions emitted
9204 ;; here in strict sequence.
9205 (define_expand "allocate_stack"
9206 [(match_operand 0 "" "")
9207 (match_operand 1 "" "")]
9213 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9214 in operand 0 before adjusting the stack. */
9215 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9216 anti_adjust_stack (operands[1]);
9217 if (TARGET_HPUX_UNWIND_LIBRARY)
9219 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9220 GEN_INT (TARGET_64BIT ? -8 : -4));
9221 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9223 if (!TARGET_64BIT && flag_pic)
9225 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9226 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);