1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
44 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "langhooks.h"
55 #include "picochip-protos.h"
57 #include "insn-attr.h" /* For DFA state_t. */
58 #include "insn-config.h" /* Required by recog.h */
59 #include "insn-codes.h" /* For CODE_FOR_? */
60 #include "optabs.h" /* For GEN_FCN */
61 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
62 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
63 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
64 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
67 /* Target AE ISA information. */
68 enum picochip_dfa_type picochip_schedule_type
;
70 bool picochip_has_mul_unit
= false;
71 bool picochip_has_mac_unit
= false;
73 /* targetm hook function prototypes. */
75 void picochip_asm_file_start (void);
76 void picochip_asm_file_end (void);
78 void picochip_init_libfuncs (void);
79 void picochip_reorg (void);
81 int picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
,
82 enum machine_mode mode
,
83 tree type
, bool named
);
85 int picochip_sched_lookahead (void);
86 int picochip_sched_issue_rate (void);
87 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
88 rtx dep_insn
, int cost
);
89 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
90 int *n_readyp
, int clock
);
92 void picochip_init_builtins (void);
93 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
95 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int* total
, bool speed
);
96 bool picochip_return_in_memory(const_tree type
,
97 const_tree fntype ATTRIBUTE_UNUSED
);
98 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
99 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
100 enum machine_mode mode
);
101 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
102 int opnum
, int type
, int ind_levels
);
104 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
105 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
106 bool outgoing ATTRIBUTE_UNUSED
);
108 picochip_secondary_reload (bool in_p
,
109 rtx x ATTRIBUTE_UNUSED
,
110 reg_class_t cla ATTRIBUTE_UNUSED
,
111 enum machine_mode mode
,
112 secondary_reload_info
*sri
);
114 picochip_asm_named_section (const char *name
,
115 unsigned int flags ATTRIBUTE_UNUSED
,
116 tree decl ATTRIBUTE_UNUSED
);
118 static rtx
picochip_static_chain (const_tree
, bool);
120 static void picochip_option_override (void);
122 /* Lookup table mapping a register number to the earliest containing
123 class. Used by REGNO_REG_CLASS. */
124 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
126 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
127 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
128 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
129 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
130 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
133 /* picoChip register names. */
134 const char *picochip_regnames
[] = REGISTER_NAMES
;
136 /* Define the maximum number of registers which may be used to pass
137 * parameters to functions. */
138 #define MAX_CALL_PARAMETER_REGS 6
141 /* Target scheduling information. */
143 /* Determine whether we run our final scheduling pass or not. We always
144 avoid the normal second scheduling pass. */
145 int picochip_flag_schedule_insns2
;
147 /* Check if variable tracking needs to be run. */
148 int picochip_flag_var_tracking
;
150 /* This flag indicates whether the next instruction to be output is a
151 VLIW continuation instruction. It is used to communicate between
152 final_prescan_insn and asm_output_opcode. */
153 static int picochip_vliw_continuation
= 0;
155 /* This variable is used to communicate the current instruction
156 between final_prescan_insn and functions such as asm_output_opcode,
157 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
158 current instruction. */
159 static rtx picochip_current_prescan_insn
;
161 static bool picochip_is_delay_slot_pending
= 0;
163 /* When final_prescan_insn is called, it computes information about
164 the current VLIW packet, and stores it in this structure. When
165 instructions are output, this state is used to make sure that the
166 instructions are output in the correct way (e.g., which ALU to use,
167 whether a macro branch was ever previously a real branch, etc.). */
170 int contains_pico_alu_insn
;
171 int contains_non_cc_alu_insn
;
172 int num_alu_insns_so_far
;
174 /* Record how many instructions are contained in the packet. */
175 int num_insns_in_packet
;
177 /* There was a case for this to be more than 1 */
178 int num_cfi_labels_deferred
;
179 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
180 emitted inside a VLIW packet. */
181 char lm_label_name
[256]; /* Used to record the name of an LM label. */
184 struct vliw_state picochip_current_vliw_state
;
186 /* Save/restore recog_data. */
187 static int picochip_saved_which_alternative
;
188 static struct recog_data picochip_saved_recog_data
;
190 /* Determine which ALU to use for the instruction in
191 picochip_current_prescan_insn. */
192 static char picochip_get_vliw_alu_id (void);
194 /* Initialize the GCC target structure. */
196 #undef TARGET_ASM_FUNCTION_PROLOGUE
197 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
199 #undef TARGET_ASM_FUNCTION_EPILOGUE
200 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
202 #undef TARGET_ASM_INTERNAL_LABEL
203 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
205 #undef TARGET_ASM_GLOBALIZE_LABEL
206 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
208 #undef TARGET_ASM_BYTE_OP
209 #define TARGET_ASM_BYTE_OP ".initByte "
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
212 #undef TARGET_ASM_UNALIGNED_HI_OP
213 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
214 #undef TARGET_ASM_ALIGNED_SI_OP
215 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
216 #undef TARGET_ASM_UNALIGNED_SI_OP
217 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
219 #undef TARGET_INIT_BUILTINS
220 #define TARGET_INIT_BUILTINS picochip_init_builtins
222 #undef TARGET_EXPAND_BUILTIN
223 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
225 #undef TARGET_RTX_COSTS
226 #define TARGET_RTX_COSTS picochip_rtx_costs
228 #undef TARGET_SCHED_ISSUE_RATE
229 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
231 #undef TARGET_SCHED_REORDER
232 #define TARGET_SCHED_REORDER picochip_sched_reorder
234 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
235 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
236 picochip_sched_lookahead
238 #undef TARGET_SCHED_ADJUST_COST
239 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
241 #undef TARGET_ASM_NAMED_SECTION
242 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
244 #undef TARGET_HAVE_NAMED_SECTIONS
245 #define TARGET_HAVE_NAMED_SECTIONS 1
247 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
248 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
250 #undef TARGET_INIT_LIBFUNCS
251 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
253 #undef TARGET_ASM_FILE_START
254 #define TARGET_ASM_FILE_START picochip_asm_file_start
256 #undef TARGET_ASM_FILE_END
257 #define TARGET_ASM_FILE_END picochip_asm_file_end
259 #undef TARGET_MACHINE_DEPENDENT_REORG
260 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
262 #undef TARGET_ARG_PARTIAL_BYTES
263 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
265 #undef TARGET_PROMOTE_FUNCTION_MODE
266 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
267 #undef TARGET_PROMOTE_PROTOTYPES
268 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
270 /* Target support for Anchored Addresses optimization */
271 #undef TARGET_MIN_ANCHOR_OFFSET
272 #define TARGET_MIN_ANCHOR_OFFSET 0
273 #undef TARGET_MAX_ANCHOR_OFFSET
274 #define TARGET_MAX_ANCHOR_OFFSET 7
275 #undef TARGET_ASM_OUTPUT_ANCHOR
276 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
278 #undef TARGET_FUNCTION_VALUE
279 #define TARGET_FUNCTION_VALUE picochip_function_value
281 #undef TARGET_LIBGCC_CMP_RETURN_MODE
282 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
285 #undef TARGET_LEGITIMATE_ADDRESS_P
286 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
288 #undef TARGET_LEGITIMIZE_ADDRESS
289 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
291 /* Loading and storing QImode values to and from memory
292 usually requires a scratch register. */
293 #undef TARGET_SECONDARY_RELOAD
294 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
295 #undef DONT_USE_BUILTIN_SETJMP
296 #define DONT_USE_BUILTIN_SETJMP 1
298 /* How Large Values are Returned */
300 #undef TARGET_RETURN_IN_MEMORY
301 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
303 #undef TARGET_STATIC_CHAIN
304 #define TARGET_STATIC_CHAIN picochip_static_chain
306 #undef TARGET_OPTION_OVERRIDE
307 #define TARGET_OPTION_OVERRIDE picochip_option_override
309 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
310 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
312 struct gcc_target targetm
= TARGET_INITIALIZER
;
315 /* Only return a value in memory if it is greater than 4 bytes.
316 int_size_in_bytes returns -1 for variable size objects, which go in
317 memory always. The cast to unsigned makes -1 > 8. */
320 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
322 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
325 /* Allow some options to be overriden. In particular, the 2nd
326 scheduling pass option is switched off, and a machine dependent
327 reorganisation ensures that it is run later on, after the second
328 jump optimisation. */
331 picochip_option_override (void)
333 /* If we are optimizing for stack, dont let inliner to inline functions
334 that could potentially increase stack size.*/
335 if (flag_conserve_stack
)
337 PARAM_VALUE (PARAM_LARGE_STACK_FRAME
) = 0;
338 PARAM_VALUE (PARAM_STACK_FRAME_GROWTH
) = 0;
341 /* Turn off the elimination of unused types. The elaborator
342 generates various interesting types to represent constants,
343 generics, and so on, and it is useful to retain this information
344 in the debug output. The increased size of the debug information
345 is not really an issue for us. */
346 flag_eliminate_unused_debug_types
= 0;
348 /* Even if the user specifies a -fno-omit-frame-pointer on the
349 command line, we still want to go ahead and omit frame pointer
350 usages, since we dont really have a frame pointer register.
351 So, all accesses to FP need to be converted to accesses off
353 flag_omit_frame_pointer
= 1;
355 /* Turning on anchored addresses by default. This is an optimization
356 that could decrease the code size by placing anchors in data and
357 accessing offsets from the anchor for file local data variables.*/
359 flag_section_anchors
= 1;
361 /* Turn off the second scheduling pass, and move it to
362 picochip_reorg, to avoid having the second jump optimisation
363 trash the instruction modes (e.g., instructions are changed to
364 TImode to mark the beginning of cycles). Two types of DFA
365 scheduling are possible: space and speed. In both cases,
366 instructions are reordered to avoid stalls (e.g., memory loads
367 stall for one cycle). Speed scheduling will also enable VLIW
368 instruction packing. VLIW instructions use more code space, so
369 VLIW scheduling is disabled when scheduling for size. */
370 picochip_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
371 flag_schedule_insns_after_reload
= 0;
372 if (picochip_flag_schedule_insns2
)
375 picochip_schedule_type
= DFA_TYPE_SPACE
;
378 picochip_schedule_type
= DFA_TYPE_SPEED
;
379 flag_delayed_branch
= 0;
383 picochip_schedule_type
= DFA_TYPE_NONE
;
385 /* Ensure that the debug level is always at least -g2. The flow
386 analyser works at its best if it always has debug
387 information. DWARF is non-intrusive, so it makes no difference to
388 code quality if debug is always enabled. */
389 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
391 debug_info_level
= DINFO_LEVEL_NORMAL
;
392 write_symbols
= DWARF2_DEBUG
;
395 /* Options of the form -mae=mac, and so on will be substituted by
396 the compiler driver for the appropriate byte access and multiply
397 unit ISA options. Any unrecognised AE types will end up being
398 passed to the compiler, which should reject them as invalid. */
399 if (picochip_ae_type_string
!= NULL
)
400 error ("invalid AE type specified (%s)\n", picochip_ae_type_string
);
402 /* Override any specific capabilities of the instruction set. These
403 take precedence over any capabilities inferred from the AE type,
404 regardless of where the options appear on the command line. */
405 if (picochip_mul_type_string
== NULL
)
407 /* Default to MEM-type multiply, for historical compatibility. */
408 picochip_has_mac_unit
= false;
409 picochip_has_mul_unit
= true;
413 picochip_has_mac_unit
= false;
414 picochip_has_mul_unit
= false;
416 if (strcmp (picochip_mul_type_string
, "mul") == 0)
417 picochip_has_mul_unit
= true;
418 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
419 picochip_has_mac_unit
= true;
420 else if (strcmp (picochip_mul_type_string
, "none") == 0)
421 { /* Do nothing. Unit types already set to false. */ }
423 error ("Invalid mul type specified (%s) - expected mac, mul or none",
424 picochip_mul_type_string
);
430 /* Initialise the library functions to handle arithmetic on some of
433 picochip_init_libfuncs (void)
436 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
437 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
438 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
440 /* 64-bit signed multiplication. */
441 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
443 /* Signed division */
444 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
445 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
448 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
449 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
451 /* 32-bit count leading Zeros*/
452 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
454 /* 64-bit comparison */
455 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
456 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
458 /* 64-bit addition and subtraction*/
459 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
460 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
463 /* Memcpy function */
465 picochip_expand_movmemhi (rtx
*operands
)
467 rtx src_addr_reg
, dst_addr_reg
, count_reg
, src_mem
, dst_mem
, tmp_reg
;
470 src_addr_reg
= gen_reg_rtx(HImode
);
471 dst_addr_reg
= gen_reg_rtx(HImode
);
472 count_reg
= gen_reg_rtx(HImode
);
473 emit_insn (gen_movhi (count_reg
, operands
[2]));
474 emit_insn (gen_movqi (src_addr_reg
, XEXP(operands
[1], 0)));
475 emit_insn (gen_movqi (dst_addr_reg
, XEXP(operands
[0], 0)));
476 gcc_assert (GET_CODE(count_reg
) == REG
);
477 start_label
= gen_label_rtx ();
478 emit_label (start_label
);
480 /* We can specialise the code for different alignments */
481 align
= INTVAL(operands
[3]);
482 size
= INTVAL(operands
[2]);
483 gcc_assert(align
>= 0 && size
>= 0);
486 if (size
% 4 == 0 && align
% 4 == 0)
488 src_mem
= gen_rtx_MEM(SImode
, src_addr_reg
);
489 dst_mem
= gen_rtx_MEM(SImode
, dst_addr_reg
);
490 tmp_reg
= gen_reg_rtx(SImode
);
491 emit_insn (gen_movsi (tmp_reg
, src_mem
));
492 emit_insn (gen_movsi (dst_mem
, tmp_reg
));
493 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, GEN_INT(4)));
494 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, GEN_INT(4)));
495 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-4)));
496 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
497 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
499 else if (size
% 2 == 0 && align
% 2 == 0)
501 src_mem
= gen_rtx_MEM(HImode
, src_addr_reg
);
502 dst_mem
= gen_rtx_MEM(HImode
, dst_addr_reg
);
503 tmp_reg
= gen_reg_rtx(HImode
);
504 emit_insn (gen_movhi (tmp_reg
, src_mem
));
505 emit_insn (gen_movhi (dst_mem
, tmp_reg
));
506 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const2_rtx
));
507 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const2_rtx
));
508 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-2)));
509 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
510 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
514 src_mem
= gen_rtx_MEM(QImode
, src_addr_reg
);
515 dst_mem
= gen_rtx_MEM(QImode
, dst_addr_reg
);
516 tmp_reg
= gen_reg_rtx(QImode
);
517 emit_insn (gen_movqi (tmp_reg
, src_mem
));
518 emit_insn (gen_movqi (dst_mem
, tmp_reg
));
519 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const1_rtx
));
520 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const1_rtx
));
521 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-1)));
522 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
523 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
530 /* Return the register class for letter C. */
532 picochip_reg_class_from_letter (unsigned c
)
550 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
552 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
555 picochip_order_regs_for_local_alloc (void)
557 /* We change the order for leaf functions alone. We put r12 at
558 the end since using it will prevent us to combine stw/ldws to
559 stl/ldl and it gives no benefit. In non-leaf functions, we
560 would anyway saveup/restore r12, so it makes sense to use it.*/
562 if (leaf_function_p())
564 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
565 FIRST_PSEUDO_REGISTER
* sizeof (int));
569 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
570 FIRST_PSEUDO_REGISTER
* sizeof (int));
574 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
576 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
581 case 'I': /* 4 bits signed. */
582 return value
+ 8 < 16;
583 case 'J': /* 4 bits unsigned. */
585 case 'K': /* 8 bits signed. */
586 return value
+ 128 < 256;
587 case 'M': /* 4-bit magnitude. */
588 return abs (value
) < 16;
589 case 'N': /* 10 bits signed. */
590 return value
+ 512 > 1024;
591 case 'O': /* 16 bits signed. */
592 return value
+ 32768 < 65536;
593 default: /* Unknown letter. */
598 /* Stack utility functions. */
600 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
603 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
609 /* Emit a set of parallel register expressions used to store
610 blockmode values to pass to functions. */
612 picochip_emit_register_parallel (int size_in_units
, int offset
)
616 rtx vector
[MAX_CALL_PARAMETER_REGS
];
620 /* Compute the base register, and number of required registers. */
621 base_reg
= offset
/ 2;
622 num_regs
= size_in_units
/ 2;
623 if (size_in_units
% 2 == 1)
626 /* Emit a register for each part of the block mode value to be
627 passed in a register. */
628 for (i
= 0; i
< num_regs
; i
++)
629 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
630 gen_rtx_REG (HImode
, base_reg
+ i
),
632 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
638 /* Emit an instruction to allocate a suitable amount of space on the
639 stack, by decrementing the stack pointer. */
641 picochip_emit_stack_allocate (int adjustment
)
644 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
646 /* Use an addition of a negative value. */
647 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
648 GEN_INT (-adjustment
)));
650 /* Make the instruction frame related. Also add an expression note,
651 so that the correct Dwarf information is generated (see documention
652 for RTX_FRAME_RELATED_P for more details). */
653 RTX_FRAME_RELATED_P (insn
) = 1;
655 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
656 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
657 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
658 GEN_INT (-adjustment
))),
663 /* Emit an instruction to save a register of the given mode. The
664 offset at which to save the register is given relative to the stack
667 picochip_emit_save_register (rtx reg
, int offset
)
669 rtx stack_pointer
, address
, mem
, insn
;
671 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
673 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
675 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
677 insn
= emit_move_insn (mem
, reg
);
678 RTX_FRAME_RELATED_P (insn
) = 1;
680 /* For modes other than HImode, create a note explaining that
681 multiple registers have been saved. This allows the correct DWARF
682 call frame information to be generated. */
683 switch (GET_MODE (reg
))
686 /* The RTL is sufficient to explain HImode register saves. */
690 /* SImode must be broken down into parallel HImode register saves. */
698 gen_rtx_PLUS (Pmode
, stack_pointer
,
700 gen_rtx_REG (HImode
, REGNO (reg
)));
701 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
704 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
709 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
710 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
713 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
714 gen_rtx_PARALLEL (VOIDmode
, p
),
722 ("unexpected mode %s encountered in picochip_emit_save_register\n",
723 GET_MODE_NAME (GET_MODE (reg
)));
728 /* Emit an instruction to restore a register of the given mode. The
729 offset from which to restore the register is given relative to the
732 picochip_emit_restore_register (rtx reg
, int offset
)
734 rtx stack_pointer
, address
, mem
, insn
;
736 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
738 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
740 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
742 insn
= emit_move_insn (reg
, mem
);
746 /* Check that the given byte offset is aligned to the given number of
749 picochip_is_aligned (int byte_offset
, int bit_alignment
)
751 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
752 return (byte_offset
% byte_alignment
) == 0;
755 /*****************************************************************************
758 * The following section contains code which controls how the stack is
761 * The stack is laid out as follows (high addresses first):
764 * Pretend arguments (ARG PTR)
768 * Outgoing arguments (SP)
770 * The (constant) offsets of the different areas must be calculated
771 * relative to the stack area immediately below, and aligned
772 * appropriately. For example, the frame offset is computed by
773 * determining the offset of the special register area, adding the
774 * size of the special register area, and then aligning the resulting
775 * offset correctly. In turn, the special register offset is computed
776 * from the general register offset, and so on. This enables the
777 * different offsets to change size and alignment, without requiring
778 * the code for other offset calculations to be rewritten.
780 * The argument pointer, and the frame pointer are eliminated wherever
781 * possible, by replacing them with a constant offset from the stack
782 * pointer. In the rare cases where constant offsets from the stack
783 * pointer cannot be computed, another register will be allocated to
784 * serve as the argument pointer, or the frame pointer.
786 * The save registers are stored at small offsets from the caller, to
787 * enable the more efficient SP-based ISA instructions to be used.
789 ****************************************************************************/
791 /* Compute the size of an argument in units. */
793 picochip_compute_arg_size (tree type
, enum machine_mode mode
)
795 int type_size_in_units
= 0;
798 type_size_in_units
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
800 type_size_in_units
= GET_MODE_SIZE (mode
);
802 return type_size_in_units
;
806 /* Determine where the next outgoing arg should be placed. */
808 picochip_function_arg (CUMULATIVE_ARGS cum
, int mode
, tree type
,
809 int named ATTRIBUTE_UNUSED
)
812 int type_align_in_units
= 0;
813 int type_size_in_units
;
815 int offset_overflow
= 0;
817 /* VOIDmode is passed when computing the second argument to a `call'
818 pattern. This can be ignored. */
819 if (mode
== VOIDmode
)
822 /* Compute the alignment and size of the parameter. */
823 type_align_in_units
=
824 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
825 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
827 /* Compute the correct offset (i.e., ensure that the offset meets
828 the alignment requirements). */
829 offset_overflow
= cum
% type_align_in_units
;
830 if (offset_overflow
== 0)
833 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
837 printf ("Function arg:\n");
838 printf (" Type valid: %s\n", (type
? "yes" : "no"));
839 printf (" Cumulative Value: %d\n", cum
);
840 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
841 printf (" Type size: %i units\n", type_size_in_units
);
842 printf (" Alignment: %i units\n", type_align_in_units
);
843 printf (" New offset: %i\n", new_offset
);
847 /* If the new offset is outside the register space, return. */
848 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
851 /* If the end of the argument is outside the register space, then
852 the argument must overlap the register space. Return the first
853 available register. */
854 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
855 return gen_rtx_REG (HImode
, new_offset
/ 2);
857 /* Create a register of the required mode to hold the parameter. */
858 reg
= new_offset
/ 2;
873 return gen_rtx_REG ((enum machine_mode
) mode
, reg
);
877 /* Empty blockmode values can be passed as arguments (e.g.,
878 * empty structs). These require no registers
879 * whatsoever. Non-empty blockmode values are passed in a set
880 * of parallel registers. */
881 if (type_size_in_units
== 0)
884 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
889 (0, "Defaulting to stack for %s register creation\n",
890 GET_MODE_NAME (mode
));
898 /* Determine where the next incoming function argument will
899 appear. Normally, this works in exactly the same way as
900 picochip_function_arg, except when the function in question is a
901 varadic function. In this case, the incoming arguments all appear
902 to be passed on the stack (actually, some of the arguments are
903 passed in registers, which are then pushed onto the stack by the
904 function prologue). */
906 picochip_incoming_function_arg (CUMULATIVE_ARGS cum
, int mode
,
907 tree type
, int named
)
913 return picochip_function_arg (cum
, mode
, type
, named
);
917 /* Gives the alignment boundary, in bits, of an argument with the
920 picochip_get_function_arg_boundary (enum machine_mode mode
)
925 align
= STACK_BOUNDARY
;
927 align
= GET_MODE_ALIGNMENT (mode
);
929 if (align
< PARM_BOUNDARY
)
930 align
= PARM_BOUNDARY
;
936 /* Compute partial registers. */
938 picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
, enum machine_mode mode
,
939 tree type
, bool named ATTRIBUTE_UNUSED
)
941 int type_align_in_units
= 0;
942 int type_size_in_units
;
944 int offset_overflow
= 0;
946 unsigned cum
= *((unsigned *) p_cum
);
948 /* VOIDmode is passed when computing the second argument to a `call'
949 pattern. This can be ignored. */
950 if (mode
== VOIDmode
)
953 /* Compute the alignment and size of the parameter. */
954 type_align_in_units
=
955 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
956 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
958 /* Compute the correct offset (i.e., ensure that the offset meets
959 the alignment requirements). */
960 offset_overflow
= cum
% type_align_in_units
;
961 if (offset_overflow
== 0)
964 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
968 printf ("Partial function arg nregs:\n");
969 printf (" Type valid: %s\n", (type
? "yes" : "no"));
970 printf (" Cumulative Value: %d\n", cum
);
971 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
972 printf (" Type size: %i units\n", type_size_in_units
);
973 printf (" Alignment: %i units\n", type_align_in_units
);
974 printf (" New offset: %i\n", new_offset
);
978 /* If the new offset is outside the register space, return. */
979 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
982 /* If the end of the argument is outside the register space, then
983 the argument must overlap the register space. Return the number
984 of bytes which are passed in registers. */
985 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
986 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
992 /* Advance the cumulative args counter, returning the new counter. */
994 picochip_arg_advance (const CUMULATIVE_ARGS cum
, int mode
,
995 tree type
, int named ATTRIBUTE_UNUSED
)
997 int type_align_in_units
= 0;
998 int type_size_in_units
;
1000 int offset_overflow
= 0;
1002 /* VOIDmode is passed when computing the second argument to a `call'
1003 pattern. This can be ignored. */
1004 if (mode
== VOIDmode
)
1007 /* Compute the alignment and size of the parameter. */
1008 type_align_in_units
=
1009 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
1010 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
1012 /* Compute the correct offset (i.e., ensure that the offset meets
1013 the alignment requirements). */
1014 offset_overflow
= cum
% type_align_in_units
;
1015 if (offset_overflow
== 0)
1018 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
1020 /* Advance past the last argument. */
1021 new_offset
+= type_size_in_units
;
1027 /* Determine whether a register needs saving/restoring. It does if it
1028 is live in a function, and isn't a call-used register. */
1030 picochip_reg_needs_saving (int reg_num
)
1032 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
1035 /* Compute and return offset of the main frame. */
1037 picochip_frame_byte_offset (void)
1039 gcc_assert(picochip_is_aligned
1040 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
1042 return crtl
->outgoing_args_size
;
1045 /* Return the size of the main frame. */
1047 picochip_frame_size_in_bytes (void)
1049 int frame_size
= get_frame_size();
1050 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
1051 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
1052 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
1053 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
1057 /* Compute and return the size (in bytes) of the register save/restore
1058 area for the current function. This only includes the general
1059 purpose registers - the special purpose stack pointer and link
1060 registers are not included in this area. */
1062 picochip_save_area_size_in_bytes (void)
1064 int num_regs_to_save
= 0;
1067 /* Read through all the registers, determining which need to be saved. */
1068 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1070 if (picochip_reg_needs_saving (i
))
1071 num_regs_to_save
+= 1;
1074 return num_regs_to_save
* UNITS_PER_WORD
;
1078 /* Compute and return offset of the save area base. */
1080 picochip_save_area_byte_offset (void)
1082 int base_offset
= (picochip_frame_byte_offset () +
1083 picochip_frame_size_in_bytes ());
1085 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1091 /* Compute and return offset of the special register save area. This
1092 area can be found immediately above the normal save area. It must
1093 be aligned, to allow the registers to be saved and restored as a
1096 picochip_special_save_area_byte_offset (void)
1098 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1099 int offset
= (picochip_save_area_byte_offset () +
1100 picochip_save_area_size_in_bytes ());
1102 if ((offset
% byte_alignment
) != 0)
1103 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1109 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1111 picochip_can_eliminate_link_sp_save (void)
1113 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1114 changing during optimizations phases. So, this function returns different
1115 values when called from initial_elimination_offset and then again when it
1116 is called from prologue/epilogue generation. This means that argument
1117 accesses become wrong. This wouldnt happen only if we were not using the
1118 stack at all. The following conditions ensures that.*/
1120 return (current_function_is_leaf
&&
1121 !df_regs_ever_live_p(LINK_REGNUM
) &&
1122 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1123 (picochip_special_save_area_byte_offset() == 0) &&
1124 (crtl
->args
.size
== 0) &&
1125 (crtl
->args
.pretend_args_size
== 0));
1128 /* Compute the size of the special reg save area (SP and LNK). If the
1129 SP/LNK registers don't need to be saved, this area can shrink to
1132 picochip_special_save_area_size_in_bytes (void)
1136 if (picochip_can_eliminate_link_sp_save ())
1139 return 2 * UNITS_PER_WORD
;
1142 /* Return the number of pretend arguments. If this function is
1143 varadic, all the incoming arguments are effectively passed on the
1144 stack. If this function has real pretend arguments (caused by a
1145 value being passed partially on the stack and partially in
1146 registers), then return the number of registers used. */
1148 picochip_pretend_arg_area_size (void)
1151 if (crtl
->args
.pretend_args_size
!= 0)
1153 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1155 return crtl
->args
.pretend_args_size
;
1157 else if (cfun
->stdarg
)
1164 /* Compute and return the offset of the pretend arguments. The pretend
1165 arguments are contiguous with the incoming arguments, and must be
1166 correctly aligned. */
1168 picochip_pretend_arg_area_byte_offset (void)
1170 int base_offset
= 0;
1172 base_offset
= (picochip_special_save_area_byte_offset () +
1173 picochip_special_save_area_size_in_bytes ());
1175 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1176 gcc_assert(picochip_is_aligned
1177 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1183 /* Compute and return the offset of the incoming arguments. If a
1184 static chain is in use, this will be passed just before the other
1185 arguments. This means that the pretend argument mechanism, used in
1186 variadic functions, doesn't work properly. Thus, static chains work
1187 on their own, as do variadic functions, but not the combination of
1188 the two. This isn't really a problem. */
1190 picochip_arg_area_byte_offset (void)
1192 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1193 picochip_pretend_arg_area_size ());
1195 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1196 the alignment on a 32-bit boundary must be maintained. */
1197 if (cfun
->static_chain_decl
!= NULL
)
1199 gcc_assert (!cfun
->stdarg
);
1203 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1210 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, int mode
)
1213 /* Special case - only one register needed. */
1214 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1217 /* We actually do not allocate acc0 ever. But, it seems like we need to
1218 make it look like a allocatable register for the dataflow checks to work
1219 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1224 /* General case - compute how much space in terms of units. */
1225 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1230 picochip_class_max_nregs (int reg_class
, int mode
)
1232 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1234 if (reg_class
== ACC_REGS
)
1237 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1244 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1245 argument pointer) by replacing it with a constant offset from the
1246 main stack register. */
1248 initial_elimination_offset (int from
, int to
)
1250 int offset_from_sp
= 0;
1252 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1253 offset_from_sp
= picochip_frame_byte_offset ();
1254 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1255 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1259 return offset_from_sp
;
1263 /* Compute and return the size of the incoming argument area. */
1265 picochip_arg_area_size_in_bytes (void)
1267 return crtl
->args
.size
;
1270 /* Determine whether the given register is valid. When the strict mode
1271 is used, only hard registers are valid, otherwise any register is
1274 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1277 /* Sanity check - non-registers shouldn't make it here, but... */
1278 if (REG
!= GET_CODE (x
))
1282 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1288 /* Determine whether the given constant is in the range required for
1289 the given base register. */
1291 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1293 HOST_WIDE_INT corrected_offset
;
1295 if (GET_MODE_SIZE (mode
) != 0)
1297 if (GET_MODE_SIZE(mode
) <= 4)
1299 /* We used to allow incorrect offsets if strict is 0. But, this would
1300 then rely on reload doing the right thing. We have had problems
1301 there before, and on > 4.3 compiler, there are no benefits. */
1302 if (offset
% GET_MODE_SIZE (mode
) != 0)
1304 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1308 if (offset
% 4 != 0)
1310 corrected_offset
= offset
/ 4;
1315 /* Default to the byte offset as supplied. */
1316 corrected_offset
= offset
;
1319 /* The offset from the base register can be different depending upon
1320 the base register. The stack/frame/argument pointer offsets can
1321 all be greater than a simple register-based offset. Note that the
1322 frame/argument pointer registers are actually eliminations of the
1323 stack pointer, so a value which is valid for an offset to, for
1324 example, the frame pointer, might be invalid for the stack
1325 pointer once the elimination has occurred. However, there is no
1326 need to handle this special case here, as the stack offset is
1327 always checked after elimination anyway, and the generated code
1328 seems to have identical performance. */
1329 if (regno
== STACK_POINTER_REGNUM
||
1330 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1331 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1333 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1337 /* Determine whether a given rtx is a legitimate address for machine_mode
1338 MODE. STRICT is non-zero if we're being strict - any pseudo that
1339 is not a hard register must be a memory reference. */
1341 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1345 switch (GET_CODE (x
))
1348 valid
= picochip_legitimate_address_register (x
, strict
);
1353 rtx base
= XEXP (x
, 0);
1354 rtx offset
= XEXP (x
, 1);
1355 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1361 valid
= (REG
== GET_CODE (base
) &&
1362 picochip_legitimate_address_register (base
, strict
) &&
1363 CONST_INT
== GET_CODE (offset
) &&
1364 picochip_const_ok_for_base (mode
, REGNO (base
),
1370 /* The user can select whether a symbol can be used as a memory
1371 address. Typically, this will decrease execution time (no
1372 register load is required first), but will increase code size
1373 (because the symbol will be used several times, rather than
1374 loaded once into a register.*/
1375 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1380 /* A constant memory address must be a (plus (symbol_ref)
1381 (const_int)), and is only allowed when the symbols are
1382 permitted addresses. */
1383 rtx inner
= XEXP (x
, 0);
1385 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1386 PLUS
== GET_CODE (inner
) &&
1387 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1388 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1402 /* For all memory operations, picochip allows a uconst4 offset value. It
1403 is hence beneficial to turn an
1404 addr = <reg + long_const>
1409 X = reg + long_const & FFF0
1410 diff = long_const - (long_const & FFF0)
1413 X can be reused in subsequent memory operations.
1416 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1417 enum machine_mode mode
)
1424 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1440 if (GET_CODE (x
) == PLUS
1441 && GET_CODE (XEXP (x
, 0)) == REG
1442 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1444 int high_val
, low_val
, offset
;
1445 offset
= INTVAL (XEXP (x
, 1));
1446 // Ignore cases with negative offsets.
1449 high_val
= offset
& mask_val
;
1450 low_val
= offset
- high_val
;
1453 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1454 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1461 /* For all memory operations, picochip allows a uconst4 offset value. It
1462 is hence beneficial to turn an
1463 addr = <reg + long_const>
1468 X = reg + long_const & FFF0
1469 diff = long_const - (long_const & FFF0)
1472 X can be reused in subsequent memory operations.
1475 picochip_legitimize_reload_address (rtx
*x
,
1476 enum machine_mode mode
,
1477 int opnum
, int type
,
1478 int ind_levels ATTRIBUTE_UNUSED
)
1482 if (picochip_symbol_offset(*x
))
1484 *x
= gen_rtx_CONST(mode
, *x
);
1490 /* We should recognise addresses that we created.*/
1491 if (GET_CODE (*x
) == PLUS
1492 && GET_CODE (XEXP (*x
, 0)) == PLUS
1493 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1494 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1495 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1497 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1498 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1499 opnum
, (enum reload_type
)type
);
1503 // Depending on mode, the offsets allowed are either 16/32/64.
1519 if (GET_CODE (*x
) == PLUS
1520 && GET_CODE (XEXP (*x
, 0)) == REG
1521 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1523 int high_val
, low_val
, offset
;
1524 offset
= INTVAL (XEXP (*x
, 1));
1525 // Ignore cases with negative offsets.
1528 high_val
= offset
& mask_val
;
1529 low_val
= offset
- high_val
;
1532 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1533 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1534 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1535 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1536 opnum
, (enum reload_type
)type
);
1544 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1546 picochip_symbol_offset (rtx operand
)
1549 return (PLUS
== GET_CODE (operand
) &&
1550 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1551 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1555 /* Assembly output. */
1557 /* The format here should match the format used in the output of
1558 symbol_ref's elsewhere in this file. */
1560 picochip_output_label (FILE * stream
, const char name
[])
1562 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1564 /* If VLIW scheduling is in use, any Call Frame Information labels
1565 generated inside a packet must have their output deferred until
1566 the end of the packet. */
1567 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1568 is_cfi_label
&& picochip_vliw_continuation
)
1570 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1572 internal_error ("LCFI labels have already been deferred.");
1574 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1575 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1576 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1580 assemble_name (stream
, name
);
1582 if (strncmp (name
, "picoMark_", 9) == 0)
1583 fprintf (stream
, "=\n");
1585 fprintf (stream
, ":\n");
1591 /* The format here should match the format used in the output of
1592 symbol_ref's elsewhere in this file. */
1594 picochip_output_labelref (FILE * stream
, const char name
[])
1596 fprintf (stream
, "_%s", name
);
1600 picochip_weaken_label (FILE * stream
, const char name
[])
1602 fprintf (stream
, ".weak ");
1603 assemble_name (stream
, name
);
1604 fprintf (stream
, "\n");
1607 /* Return true if the given label (or label prefix) denotes a marker
1608 label which should be emitted in the form LABEL= */
1610 picochip_is_marker_prefix (const char *prefix
)
1612 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1613 && strcmp (prefix
, "LP") != 0);
1617 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1621 /* Emit different types of label, based upon their prefix. They
1622 are handled differently to allow the assembler to ensure that
1623 branch target labels are properly aligned, while other labels
1624 will only serve as code markers, not branch targets. Aligning
1625 labels unnecessarily can result in much code wastage. */
1626 if (picochip_is_marker_prefix (prefix
))
1628 /* Special label marker. If it appears in the middle of a VLIW
1629 packet, defer it until the end of the packet. There has
1630 never been a need to handle more than one lm label at a time. */
1631 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1632 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1634 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1635 internal_error ("LM label has already been deferred.");
1637 sprintf (picochip_current_vliw_state
.lm_label_name
,
1638 "picoMark_%s%ld", prefix
, num
);
1640 else if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1641 (strcmp (prefix
, "LCFI")) == 0 && picochip_vliw_continuation
)
1643 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1645 internal_error ("LCFI labels have already been deferred.");
1647 sprintf(picochip_current_vliw_state
.cfi_label_name
[
1648 picochip_current_vliw_state
.num_cfi_labels_deferred
],
1649 "picoMark_%s%ld", prefix
, num
);
1650 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1655 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1662 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1668 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1670 /* Two types of internal label can be generated: branch target
1671 labels and code marker labels. Branch target labels must always
1672 be aligned (since code will execute at these
1673 points). Differentiate between the two by prepending markers with
1674 a unique prefix, which can later be used in output_label to
1675 figure out which label syntax to use. */
1676 if (picochip_is_marker_prefix (prefix
))
1677 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1679 sprintf (str
, "%s%ld", prefix
, num
);
1684 picochip_asm_output_anchor (rtx symbol
)
1686 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1687 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1691 picochip_output_aligned_common (FILE * stream
, const char *name
,
1692 unsigned size
, unsigned alignment
)
1695 fprintf (stream
, ".commonData ");
1696 assemble_name (stream
, name
);
1697 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1698 picochip_output_global (stream
, name
);
1703 picochip_output_aligned_local (FILE * stream
, const char *name
,
1704 unsigned size
, unsigned alignment
)
1707 fprintf (stream
, ".commonData ");
1708 assemble_name (stream
, name
);
1709 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1714 picochip_output_global (FILE * stream
, const char *name
)
1716 fprintf (stream
, ".global ");
1717 assemble_name (stream
, name
);
1718 fprintf (stream
, "\n");
1721 /* Output an assembly language string. Output as a sequence of decimal
1722 numbers, followed by the literal string to make it obvious what the
1723 numbers represent. */
1725 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1729 fprintf (file
, ".ascii ");
1731 for (i
= 0; i
< length
; ++i
)
1733 fprintf (file
, "16#%x# ", (char) (str
[i
]));
1736 fprintf (file
, " ; ");
1738 for (i
= 0; i
< length
; ++i
)
1745 fprintf (file
, "\\n");
1748 fprintf (file
, "\\t");
1751 fprintf (file
, "\\0");
1754 fprintf (file
, "%c", c
);
1759 fprintf (file
, "\n");
1763 /* Output the beginning of an ASM file. */
1765 picochip_asm_file_start (void)
1767 default_file_start ();
1769 fprintf (asm_out_file
, "// picoChip ASM file\n");
1770 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1772 fprintf (asm_out_file
, "// Has byte access: %s\n",
1773 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1775 if (TARGET_HAS_MUL_UNIT
)
1776 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1777 else if (TARGET_HAS_MAC_UNIT
)
1778 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1780 fprintf (asm_out_file
, "// Has multiply: No\n");
1782 /* Variable tracking should be run after all optimizations which change order
1783 of insns. It also needs a valid CFG. This can't be done in
1784 picochip_option_override, because flag_var_tracking is finalized after
1786 picochip_flag_var_tracking
= flag_var_tracking
;
1787 flag_var_tracking
= 0;
1790 /* Output the end of an ASM file. */
1792 picochip_asm_file_end (void)
1794 /* Include a segment end to make it easy for PERL scripts to grab
1795 segments. This is now done by assembler*/
1797 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1801 /* Output frame debug information to the given stream. */
1803 picochip_output_frame_debug (FILE * file
)
1807 if (current_function_is_leaf
)
1808 fprintf (file
, "\t\t// Leaf function\n");
1810 fprintf (file
, "\t\t// Non-leaf function\n");
1812 if (picochip_can_eliminate_link_sp_save ())
1813 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1815 if (cfun
->static_chain_decl
!= NULL
)
1816 fprintf (file
, "\t\t// Static chain in use\n");
1818 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1819 picochip_arg_area_size_in_bytes ());
1820 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1821 picochip_arg_area_byte_offset ());
1822 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1823 picochip_pretend_arg_area_size ());
1824 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1825 picochip_pretend_arg_area_byte_offset ());
1826 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1827 picochip_special_save_area_size_in_bytes ());
1828 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1829 picochip_special_save_area_byte_offset ());
1831 /* Output which registers are saved. */
1832 fprintf (file
, "\t\t// Saved regs: ");
1833 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1835 if (picochip_reg_needs_saving (i
))
1836 fprintf (file
, "%s ", picochip_regnames
[i
]);
1838 fprintf (file
, "\t\t\n");
1840 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1841 picochip_save_area_size_in_bytes ());
1842 fprintf (file
, "\t\t// Save area offset: %d\n",
1843 picochip_save_area_byte_offset ());
1845 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1846 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1847 picochip_frame_byte_offset ());
1849 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1850 crtl
->outgoing_args_size
);
1854 /* Output picoChip function prologue. This contains human-readable
1855 information about the function. */
1857 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1859 /* Get the function's name, as described by its RTL. This may be
1860 different from the DECL_NAME name used in the source file. The
1861 real declaration name must be used, to ensure that the prologue
1862 emits the right information for the linker. */
1865 x
= DECL_RTL (current_function_decl
);
1866 gcc_assert (MEM_P (x
));
1868 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1869 fnname
= XSTR (x
, 0);
1871 /* Note that the name of the function is given in the &_%s
1872 form. This matches the name of the function as used in labels,
1873 and function calls, and enables processCallGraph to match
1874 function calls to the name of the function, as defined here. */
1875 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1876 fnname
, picochip_arg_area_byte_offset ());
1878 picochip_output_frame_debug (file
);
1879 fprintf (file
, "\n");
1883 /* Output picoChip function epilogue. */
1885 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1890 x
= DECL_RTL (current_function_decl
);
1891 gcc_assert (MEM_P (x
));
1893 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1894 fnname
= XSTR (x
, 0);
1895 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1899 /* Manipulate the asm output. Some machines only execute the code when
1900 there is actually a chance of needing it (e.g., FRV doesn't execute
1901 it if the scheduling pass wasn't used). We always execute it,
1902 simple to ensure that it is exercised more often, and bugs are more
1905 This function's prime reason for existence is to insert the VLIW
1906 separators where appropriate. The separators must be inserted
1907 before any comments which appear at the end of the file.
1911 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1915 /* Flag to specify when a VLIW continuation has been inserted onto
1916 the line. Continuations are either inserted before any comments,
1917 or before the end of the line is reached. The flag ensures that
1918 we don't insert continuations twice (i.e., at the comment and the
1920 int continuation_inserted
= 0;
1922 /* If the instruction uses multiple lines (i.e., a new line
1923 character appears in the opcode), then ensure that no attempt is
1924 made to pack it into a VLIW. */
1925 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1927 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1931 /* If a delay slot is pending, output the directive to the assembler
1932 before the instruction. */
1933 if (picochip_is_delay_slot_pending
)
1935 picochip_is_delay_slot_pending
= 0;
1939 /* Keep going for entire opcode. All substitution performed ourselves. */
1944 /* Determine whether a VLIW continuation must be inserted before
1945 any comments, or the end of the opcode. A flag is set to show
1946 that we have inserted a continuation on this line, so that we
1947 don't try to insert another continuation when the end of the
1948 opcode is reached. The only other case for a continuation
1949 might have been a newline, but these aren't allowed in
1950 conjunction with VLIW continuations (see above code). */
1951 if (picochip_vliw_continuation
&&
1952 !continuation_inserted
&&
1953 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1956 continuation_inserted
= 1;
1959 /* Detect an explicit VLIW separator. */
1960 if (c
== '%' && (*ptr
== '|'))
1965 /* Detect the need for an ALU id operand. */
1966 else if (c
== '%' && (*ptr
== '#'))
1968 fputc (picochip_get_vliw_alu_id (), f
);
1971 printf ("Generated ALU char at %s for insn %d\n", ptr
,
1972 INSN_UID (picochip_current_prescan_insn
));
1974 /* Skip past unwanted # */
1977 /* Detect the need for branch delay slot. */
1978 else if (c
== '%' && (*ptr
== '>'))
1980 /* Only emit delay slots (NOP's, or otherwise) when delay
1981 * slot scheduling has actually been enabled, otherwise VLIW
1982 * scheduling and delay slot scheduling output combine to
1983 * produce nasty effects. */
1984 if (flag_delayed_branch
)
1986 if (dbr_sequence_length () == 0)
1987 fputs ("\n=->\tNOP", f
);
1989 picochip_is_delay_slot_pending
= 1;
1992 /* Skip past unwanted > */
1995 /* Detect any %digit specifiers. */
1996 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
1999 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
2000 while ((c
= *ptr
) >= '0' && c
<= '9')
2003 /* Detect any %letterdigit specifiers. */
2004 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2005 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2007 int letter
= *ptr
++;
2014 output_asm_label (recog_data
.operand
[c
]);
2018 output_address (recog_data
.operand
[c
]);
2022 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
2025 while ((c
= *ptr
) >= '0' && c
<= '9')
2030 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
2036 /* Reached the end of the packet. If any labels were deferred
2037 during output, emit them now. */
2038 if (!picochip_vliw_continuation
)
2040 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
2043 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
2045 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
2048 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
2053 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
2056 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
2061 /* Output an end-of-packet marker if requested. */
2062 if (!picochip_vliw_continuation
&&
2063 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
2064 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
2069 /* Function RTL expansion. */
2071 /* Expand the prologue into RTL. */
2073 picochip_expand_prologue (void)
2075 int stack_adjustment
= 0;
2076 int special_save_offset
= 0;
2077 int general_save_offset
= 0;
2078 int reg_save_offset
= 0;
2081 stack_adjustment
= picochip_arg_area_byte_offset ();
2082 general_save_offset
=
2083 -(stack_adjustment
- picochip_save_area_byte_offset ());
2084 special_save_offset
=
2085 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2087 /* Save the link registers. We could try to save just one register
2088 here. This would reduce the amount of stack space required.
2089 There hasnt been a good reason to do that so far. */
2090 if (!picochip_can_eliminate_link_sp_save ())
2091 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2092 special_save_offset
);
2094 /* Save callee-save registers. */
2095 reg_save_offset
= 0;
2096 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2098 if (picochip_reg_needs_saving (i
))
2101 /* If this register is an even numbered register, and the
2102 next register also needs to be saved, use a SImode save,
2103 which does both in one instruction. Note that a special
2104 check is performed to ensure that the double word aligned
2105 store is valid (e.g., it is possible that r6, r8, r9 need
2106 to be saved, in which case once r6 has been saved, the
2107 stored offset is no longer aligned, and an STL/LDL
2108 instruction becomes invalid). Alternately, we could store all
2109 aligned registers first and then save the single one(s). */
2111 picochip_reg_needs_saving (i
+ 1) &&
2112 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2114 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2115 general_save_offset
+
2117 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2122 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2123 general_save_offset
+
2125 reg_save_offset
+= UNITS_PER_WORD
;
2131 /* Emit a stack adjustment where required. */
2132 if (stack_adjustment
!= 0)
2133 picochip_emit_stack_allocate (stack_adjustment
);
2135 /* If this function uses varadic arguments, write any unnamed
2136 registers to the stack. */
2139 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2141 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2142 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2144 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2145 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2147 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2154 /* Expand the epilogue into RTL. */
2156 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2158 int stack_adjustment
= 0;
2159 int special_save_offset
= 0;
2160 int general_save_offset
= 0;
2161 int reg_save_offset
= 0;
2163 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2166 stack_adjustment
= picochip_arg_area_byte_offset ();
2167 general_save_offset
=
2168 -(stack_adjustment
- picochip_save_area_byte_offset ());
2169 special_save_offset
=
2170 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2172 /* Emit a stack adjustment where required. */
2173 if (stack_adjustment
!= 0)
2175 /* If the link/fp is already being restored, and the offset to
2176 their save location is small enough, don't bother adjusting
2177 the stack explicitly. */
2178 if (picochip_special_save_area_byte_offset () < 512 &&
2179 !picochip_can_eliminate_link_sp_save ())
2180 use_link_fp_restore_stack_adjust
= 1;
2182 /* Explicitly restore the stack. */
2183 picochip_emit_stack_allocate (-stack_adjustment
);
2186 /* Restore the Link/FP registers. Only save the link register? */
2187 if (!picochip_can_eliminate_link_sp_save ())
2189 if (use_link_fp_restore_stack_adjust
)
2190 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2191 picochip_special_save_area_byte_offset
2194 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2195 special_save_offset
);
2198 /* Restore callee-save registers. */
2199 reg_save_offset
= 0;
2200 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2202 if (picochip_reg_needs_saving (i
))
2205 /* If this register is an even numbered register, and the
2206 next register also needs to be saved, use a SImode save,
2207 which does both in one instruction. Note that a special
2208 check is performed to ensure that the double word aligned
2209 store is valid (e.g., it is possible that r6, r8, r9 need
2210 to be saved, in which case once r6 has been saved, the
2211 stored offset is no longer aligned, and an STL/LDL
2212 instruction becomes invalid). We could store all aligned
2213 registers first, and then save the single one(s). */
2215 picochip_reg_needs_saving (i
+ 1) &&
2216 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2218 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2219 general_save_offset
+
2221 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2226 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2227 general_save_offset
+
2229 reg_save_offset
+= UNITS_PER_WORD
;
2235 /* Emit a return instruction, which matches a (parallel
2236 [(return) (use r12)]) */
2239 p
= rtvec_alloc (2);
2241 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
2242 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2243 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2244 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2249 /* Assembly instruction output. */
2251 /* Test whether the given branch instruction is short, or long. Short
2252 * branches are equivalent to real branches, and may be DFA
2253 * scheduled. Long branches expand to a macro which is handled by the
2254 * elaborator, and cannot be scheduled. Occasionally, the branch
2255 * shortening pass, which is run after DFA scheduling, will change the
2256 * code layout and cause the short branch to be reverted into a long
2257 * branch. Instead of having to fix this up by emitting new assembly,
2258 * the short branch is emitted anyway. There is plenty of slack in the
2259 * calculation of long and short branches (10-bit offset, but only
2260 * 9-bits used in computation), so there is enough slack for this to
2263 picochip_is_short_branch (rtx insn
)
2265 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2267 return (isRealShortBranch
||
2268 (!isRealShortBranch
&&
2269 picochip_current_vliw_state
.num_insns_in_packet
> 1));
2272 /* Output a compare-and-branch instruction (matching the cbranch
2275 picochip_output_cbranch (rtx operands
[])
2278 if (HImode
!= GET_MODE (operands
[1]) ||
2279 (HImode
!= GET_MODE (operands
[2]) &&
2280 GET_CODE (operands
[2]) != CONST_INT
))
2282 internal_error ("%s: At least one operand can't be handled",
2286 /* Use the type of comparison to output the appropriate condition
2288 switch (GET_CODE (operands
[0]))
2291 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2294 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2297 /* Reverse the operand order to be GE */
2298 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2301 /* Reverse operand order of GEU. */
2302 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2305 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2308 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2311 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2314 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2317 /* Reversed operand version of LT. */
2318 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2321 /* Reverse an LTU. */
2322 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2329 /* Output a compare-and-branch instruction (matching the cbranch
2330 pattern). This function is current unused since the cbranch
2331 split is disabled. The function is kept around so we can use
2332 it when we understand how to do cbranch split safely. */
2334 picochip_output_compare (rtx operands
[])
2338 if (HImode
!= GET_MODE (operands
[1]) ||
2339 (HImode
!= GET_MODE (operands
[2]) &&
2340 GET_CODE (operands
[2]) != CONST_INT
))
2342 internal_error ("%s: At least one operand can't be handled",
2346 code
= GET_CODE (operands
[0]);
2347 /* Use the type of comparison to output the appropriate condition
2352 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2355 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2358 /* Reverse the operand order to be GE */
2359 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2362 /* Reverse operand order of GEU. */
2363 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2366 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2369 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2372 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2375 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2378 /* Reversed operand version of LT. */
2379 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2382 /* Reverse an LTU. */
2383 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2390 /* Output the branch insn part of a compare-and-branch split. */
2392 picochip_output_branch (rtx operands
[], rtx insn
)
2395 int code
= GET_CODE(operands
[2]);
2396 if (picochip_is_short_branch (insn
))
2398 /* Short branches can be output directly using the
2399 appropriate instruction. */
2403 return ("BNE %l0 %>");
2405 return ("BEQ %l0 %>");
2407 return ("BGE %l0 %>");
2409 return ("BHS %l0 %>");
2411 return ("BGE %l0 %>");
2413 return ("BHS %l0 %>");
2415 return ("BLT %l0 %>");
2417 return ("BLO %l0 %>");
2419 return ("BLT %l0 %>");
2421 return ("BLO %l0 %>");
2423 internal_error ("Unknown short branch in %s (type %d)\n",
2424 __FUNCTION__
, (int) INTVAL (operands
[1]));
2425 return "UNKNOWN_BRANCH";
2430 /* Long branches result in the emission of a special
2431 instruction, which the assembler expands into a suitable long
2434 /* Use the type of comparison to output the appropriate condition
2439 return ("JMPNE %l0 %>");
2441 return ("JMPEQ %l0 %>");
2443 return ("JMPGE %l0 %>");
2445 return ("JMPHS %l0 %>");
2447 return ("JMPGE %l0 %>");
2449 return ("JMPHS %l0 %>");
2451 return ("JMPLT %l0 %>");
2453 return ("JMPLO %l0 %>");
2455 return ("JMPLT %l0 %>");
2457 return ("JMPLO %l0 %>");
2460 internal_error ("Unknown long branch in %s (type %d)\n",
2461 __FUNCTION__
, (int) INTVAL (operands
[1]));
2462 return "UNKNOWN_BRANCH";
2468 /* Output a jump instruction. */
2470 picochip_output_jump (rtx insn
)
2472 if (picochip_is_short_branch (insn
))
2475 return "JMPRA %l0%>";
2479 picochip_output_put_array (int alternative
, rtx operands
[])
2481 /* Local output buffer. */
2484 int portArraySize
= INTVAL(operands
[1]);
2485 int portBaseIndex
= INTVAL(operands
[2]);
2487 if (alternative
== 0)
2489 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2490 portArraySize
, portBaseIndex
);
2491 output_asm_insn (buf
, operands
);
2493 else if (alternative
== 1)
2495 /* Constant port id. Emit a real instruction. */
2496 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2497 if (portIndex
< portBaseIndex
||
2498 portIndex
>= (portBaseIndex
+ portArraySize
))
2500 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2501 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2503 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2504 output_asm_insn (buf
, operands
);
2509 /* Both alternatives output the insn directly. */
2513 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2515 /* Local output buffer. */
2518 int portArraySize
= INTVAL(operands
[1]);
2519 int portBaseIndex
= INTVAL(operands
[2]);
2521 if (alternative
== 0)
2523 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2524 portArraySize
, portBaseIndex
);
2525 output_asm_insn (buf
, operands
);
2527 else if (alternative
== 1)
2529 /* Constant port id. Emit a real instruction. */
2530 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2531 if (portIndex
< portBaseIndex
||
2532 portIndex
>= (portBaseIndex
+ portArraySize
))
2534 error ("GET uses port array index %d, which is out of range [%d..%d)",
2535 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2537 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2538 output_asm_insn (buf
, operands
);
2543 /* Both alternatives output the insn directly. */
2547 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2549 /* Local output buffer. */
2552 int portArraySize
= INTVAL(operands
[2]);
2553 int portBaseIndex
= INTVAL(operands
[3]);
2555 if (alternative
== 0)
2557 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2558 portArraySize
, portBaseIndex
);
2559 output_asm_insn (buf
, operands
);
2561 else if (alternative
== 1)
2563 /* Constant port id. Emit a real instruction. */
2564 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2565 if (portIndex
< portBaseIndex
||
2566 portIndex
>= (portBaseIndex
+ portArraySize
))
2568 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2569 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2571 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2572 output_asm_insn (buf
, operands
);
2577 /* Both alternatives output the insn directly. */
2581 /* Output a comparison operand as a symbol (e.g., >). */
2583 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2588 /* Output just the comparison symbol. */
2589 switch (GET_CODE (operand
))
2592 fprintf (file
, "!=");
2595 fprintf (file
, "==");
2598 fprintf (file
, ">=");
2601 fprintf (file
, ">={U}");
2604 fprintf (file
, "<");
2607 fprintf (file
, "<{U}");
2610 fprintf (file
, "<=");
2613 fprintf (file
, "<={U}");
2616 fprintf (file
, ">");
2619 fprintf (file
, ">{U}");
2627 /* Output the comparison formatted as operand,symbol,operand */
2628 rtx op0
= XEXP (operand
, 0);
2629 rtx op1
= XEXP (operand
, 1);
2631 picochip_print_operand (file
, op0
, 0);
2632 picochip_print_comparison (file
, operand
, 'i');
2633 picochip_print_operand (file
, op1
, 0);
2637 /* This function generates a memory address operand in the given
2638 mode. That is, if the address contains a constant offset, then the
2639 offset is divided by the required mode size to compute the
2640 mode specific offset. By default, picochip_print_operand_address calls
2641 this function using the natural mode of the operand, but special
2642 operand codes can be used to invoke the computation using an
2643 unnatural mode (e.g., compute the HI aligned address of an SI mode
2646 picochip_print_memory_address (FILE * file
, rtx operand
,
2647 enum machine_mode mode
)
2649 rtx address
= XEXP (operand
, 0);
2652 if (MEM
!= GET_CODE (operand
))
2653 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2658 printf ("picochip_print_memory_address: ");
2659 print_rtl (stdout
, operand
);
2663 switch (GET_CODE (address
))
2667 /* Grab the address components. */
2668 rtx base
= XEXP (address
, 0);
2669 rtx offset
= XEXP (address
, 1);
2671 /* Only handle reg+const addresses */
2672 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2674 /* Sanity check. If an FP+offset address is given, ensure
2675 that the offset lies within the given frame, or a lower
2677 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2678 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2681 /* Print the base register - identical for all modes. */
2682 fprintf (file
, "(");
2683 picochip_print_operand (file
, base
, 'r');
2684 fprintf (file
, ")");
2686 /* Print the constant offset with compensation for the mode. */
2690 picochip_print_operand (file
, offset
, 'Q');
2694 picochip_print_operand (file
, offset
, 'H');
2699 picochip_print_operand (file
, offset
, 'S');
2703 picochip_print_operand (file
, offset
, 'D');
2717 picochip_print_operand (file
, address
, 's');
2726 inner
= XEXP (address
, 0);
2728 /* Sanity check - the CONST memory address must be a base+offset. */
2729 gcc_assert (PLUS
== GET_CODE (inner
));
2731 base
= XEXP (inner
, 0);
2732 offset
= XEXP (inner
, 1);
2734 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2740 /* Register operand. Provide a zero offset. */
2741 fprintf (file
, "(");
2742 picochip_print_operand (file
, address
, 'r');
2743 fprintf (file
, ")0");
2752 /* Output an operand. Formatting letters allow particular parts of
2753 the operand to be output. */
2755 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2758 /* Handle special cases. */
2761 /* VLIW continuation, for explicit VLIW sequences. */
2763 fprintf (file
, "\\");
2768 fputc (picochip_get_vliw_alu_id (), file
);
2771 /* Delay slot specifier. */
2773 /* This should be handled in asm_output_opcode. */
2776 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2778 switch (GET_CODE (operand
))
2781 fprintf (file
, "AND");
2784 fprintf (file
, "OR");
2787 fprintf (file
, "XOR");
2790 fprintf (file
, "ADD");
2793 fprintf (file
, "SUB");
2800 /* Symbolic instructions (e.g., lshift becomes <<). */
2802 switch (GET_CODE (operand
))
2805 fprintf (file
, "&");
2808 fprintf (file
, "|");
2811 fprintf (file
, "^");
2814 fprintf (file
, "+");
2817 fprintf (file
, "-");
2820 fprintf (file
, "UNKNOWN_INSN");
2825 default: /* Not a punctuation character - process as normal. */
2829 switch (GET_CODE (operand
))
2835 /* Write a range of registers. */
2836 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2840 /* The upper register of a pair is requested. */
2841 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2845 /* The lower register of a pair is requested. Equivalent to the
2846 default, but included for completeness. */
2847 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2851 /* The 3rd register of a DI mode register. */
2852 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2856 /* The 4th register of a DI mode register. */
2857 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2861 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2866 /* A range of letters can be used to format integers. The
2867 letters Q/H/S are used to divide the constant by the width of
2868 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2869 to obtain the upper and lower 16-bits of a 32-bit
2870 constant. Where possible, signed numbers are used, since
2871 signed representations of numbers may be more compact (e.g.,
2872 65535 can be represented as -1, which fits into a small
2873 constant, whereas 65535 requires a large constant). */
2877 fprintf (file
, "%ld", INTVAL (operand
));
2881 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2885 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2889 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2893 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2897 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2901 fprintf (file
, "%ld", INTVAL (operand
));
2911 if (GET_MODE (operand
) != SFmode
)
2912 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2914 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2915 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2920 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2924 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2932 /* Output a symbol. The output format must match that of
2933 picochip_output_label. */
2935 /* Ensure that the symbol is marked as referenced. Gcc can
2936 occasionally omit the function bodies when it believes them
2937 to be unreferenced. */
2938 if (SYMBOL_REF_DECL (operand
))
2939 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2940 fprintf (file
, "&");
2941 assemble_name (file
, XSTR (operand
, 0));
2945 /* This format must match that of picochip_output_label. */
2946 fprintf (file
, "&");
2947 output_asm_label (operand
);
2952 rtx addr
= XEXP (operand
, 0);
2957 if (PLUS
!= GET_CODE (addr
))
2958 fatal_insn ("Bad address, not (reg+disp):", addr
);
2960 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2964 /* Output a memory address in byte mode notation (i.e., the
2965 constant address (if any) is the actual byte address. */
2966 picochip_print_memory_address (file
, operand
, QImode
);
2969 /* Output a constant offset of the given mode (i.e., divide
2970 the constant by the number of units in the mode to get the
2973 picochip_print_memory_address (file
, operand
, QImode
);
2977 picochip_print_memory_address (file
, operand
, HImode
);
2981 picochip_print_memory_address (file
, operand
, SImode
);
2985 picochip_print_memory_address (file
, operand
, SFmode
);
2989 if (PLUS
!= GET_CODE (addr
))
2990 fatal_insn ("Bad address, not (reg+disp):", addr
);
2992 picochip_print_operand (file
, XEXP (addr
, 0), 0);
2995 /* When the mem operand is (reg + big offset) which cannot
2996 be represented in an instruction as operand, the compiler
2997 automatically generates the instruction to put in (reg +
2998 big offset) into another register. In such cases, it
2999 returns '0' as the character. This needs to be handled
3003 if (REG
!= GET_CODE (addr
))
3004 fatal_insn ("Bad address, not register:", addr
);
3006 picochip_print_operand (file
, addr
, 0);
3010 fprintf (file
, "Unknown mem operand - letter %c ",
3012 print_rtl (file
, operand
);
3020 rtx const_exp
= XEXP (operand
, 0);
3022 /* Handle constant offsets to symbol references. */
3023 if (PLUS
== GET_CODE (const_exp
) &&
3024 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
3025 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
3028 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
3029 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
3030 fprintf (file
, "+");
3031 /* else use the - from the operand (i.e., AP-2)) */
3033 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
3042 /* PLUS expressions are of the form (base + offset). Different
3043 options (analagous to those of memory PLUS expressions) are used
3044 to extract the base and offset components. */
3049 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3053 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3058 /* If the expression is composed entirely of constants,
3059 evaluate the result. This should only occur with the
3060 picoChip specific comms instructions, which are emitted as
3061 base+offset expressions. */
3062 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
3063 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
3065 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
3066 XINT (XEXP (operand
, 1), 0));
3067 fprintf (file
, "%ld", result
);
3071 fprintf (file
, "(");
3072 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3073 fprintf (file
, "+");
3074 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3075 fprintf (file
, ")");
3082 /* Comparison operations. */
3093 picochip_print_comparison (file
, operand
, letter
);
3097 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3098 print_rtl (file
, operand
);
3105 /* Output an operand address */
3107 picochip_print_operand_address (FILE * file
, rtx operand
)
3110 switch (GET_CODE (operand
))
3114 /* This format must match that of picochip_output_label. */
3115 assemble_name (file
, XSTR (operand
, 0));
3119 /* Note this format must match that of picochip_output_label. */
3120 fprintf (file
, "_L%d", XINT (operand
, 5));
3124 /* Pass on to a specialised memory address generator. */
3125 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3136 /* Scheduling functions. */
3138 /* Save some of the contents of recog_data. */
3140 picochip_save_recog_data (void)
3142 picochip_saved_which_alternative
= which_alternative
;
3143 memcpy (&picochip_saved_recog_data
, &recog_data
,
3144 sizeof (struct recog_data
));
3147 /* Restore some of the contents of global variable recog_data. */
3149 picochip_restore_recog_data (void)
3151 which_alternative
= picochip_saved_which_alternative
;
3152 memcpy (&recog_data
, &picochip_saved_recog_data
,
3153 sizeof (struct recog_data
));
3156 /* Ensure that no var tracking notes are emitted in the middle of a
3157 three-instruction bundle. */
3159 reorder_var_tracking_notes (void)
3165 rtx insn
, next
, last_insn
= NULL_RTX
;
3166 rtx vliw_start
= NULL_RTX
;
3167 rtx queue
= NULL_RTX
;
3169 /* Iterate through the bb and find the last non-debug insn */
3170 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= NEXT_INSN(insn
))
3172 if (NONDEBUG_INSN_P(insn
))
3176 /* In all normal cases, queue up notes and emit them just before a TImode
3177 instruction. For the last instruction, emit the queued notes just after
3178 the last instruction. */
3179 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= next
)
3181 next
= NEXT_INSN (insn
);
3183 if (insn
== last_insn
)
3187 rtx next_queue
= PREV_INSN (queue
);
3188 PREV_INSN (NEXT_INSN(insn
)) = queue
;
3189 NEXT_INSN(queue
) = NEXT_INSN(insn
);
3190 PREV_INSN(queue
) = insn
;
3191 NEXT_INSN(insn
) = queue
;
3194 /* There is no more to do for this bb. break*/
3197 else if (NONDEBUG_INSN_P (insn
))
3199 /* Emit queued up notes before the first instruction of a bundle. */
3200 if (GET_MODE (insn
) == TImode
)
3204 rtx next_queue
= PREV_INSN (queue
);
3205 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3206 PREV_INSN (queue
) = PREV_INSN(insn
);
3207 PREV_INSN (insn
) = queue
;
3208 NEXT_INSN (queue
) = insn
;
3213 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
3215 rtx prev
= PREV_INSN (insn
);
3216 PREV_INSN (next
) = prev
;
3217 NEXT_INSN (prev
) = next
;
3218 PREV_INSN (insn
) = queue
;
3222 /* Make sure we are not dropping debug instructions.*/
3223 gcc_assert (queue
== NULL_RTX
);
3227 /* Perform machine dependent operations on the rtl chain INSNS. */
3229 picochip_reorg (void)
3231 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3232 int vliw_insn_location
= 0;
3234 /* We are freeing block_for_insn in the toplev to keep compatibility
3235 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3236 compute_bb_for_insn ();
3241 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3243 timevar_push (TV_SCHED2
);
3245 /* Process the instruction list, computing the sizes of each
3246 instruction, and consequently branch distances. This can
3247 result in some branches becoming short enough to be treated
3248 as a real branch instruction, rather than an assembly branch
3249 macro which may expand into multiple instructions. The
3250 benefit of shortening branches is that real branch
3251 instructions can be properly DFA scheduled, whereas macro
3253 shorten_branches (get_insns ());
3255 /* Do control and data sched analysis again,
3256 and write some more of the results to dump file. */
3262 timevar_pop (TV_SCHED2
);
3266 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3268 /* Whenever a VLIW packet is generated, all instructions in
3269 that packet must appear to come from the same source
3270 location. The following code finds all the VLIW packets,
3271 and tags their instructions with the location of the first
3272 instruction from the packet. Clearly this will result in
3273 strange behaviour when debugging the code, but since
3274 debugging and optimisation are being used in conjunction,
3275 strange behaviour is certain to occur anyway. */
3276 /* Slight bit of change. If the vliw set contains a branch
3277 or call instruction, we pick its location.*/
3278 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3281 /* If this is the first instruction in the VLIW packet,
3282 extract its location. */
3283 if (GET_MODE (insn
) == TImode
)
3286 vliw_insn_location
= INSN_LOCATOR (insn
);
3288 if (JUMP_P (insn
) || CALL_P(insn
))
3290 vliw_insn_location
= INSN_LOCATOR (insn
);
3291 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3292 INSN_LOCATOR (insn1
) = vliw_insn_location
;
3294 /* Tag subsequent instructions with the same location. */
3295 INSN_LOCATOR (insn
) = vliw_insn_location
;
3301 /* Locate the note marking the end of the function's prologue. If
3302 the note appears in the middle of a VLIW packet, move the note to
3303 the end. This avoids unpleasant consequences such as trying to
3304 emit prologue markers (e.g., .loc/.file directives) in the middle
3306 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3308 rtx prologue_end_note
= NULL
;
3309 rtx last_insn_in_packet
= NULL
;
3311 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3313 /* The prologue end must be moved to the end of the VLIW packet. */
3314 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3316 prologue_end_note
= insn
;
3321 /* Find the last instruction in this packet. */
3322 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3324 if (GET_MODE (insn
) == TImode
)
3327 last_insn_in_packet
= insn
;
3330 if (last_insn_in_packet
!= NULL
)
3332 rtx tmp_note
= emit_note_after (NOTE_KIND(prologue_end_note
), last_insn_in_packet
);
3333 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3334 delete_insn (prologue_end_note
);
3337 if (picochip_flag_var_tracking
)
3339 timevar_push (TV_VAR_TRACKING
);
3340 variable_tracking_main ();
3341 /* We also have to deal with variable tracking notes in the middle
3343 reorder_var_tracking_notes();
3344 timevar_pop (TV_VAR_TRACKING
);
3348 /* Return the ALU character identifier for the current
3349 instruction. This will be 0 or 1. */
3351 picochip_get_vliw_alu_id (void)
3355 /* Always use ALU 0 if VLIW scheduling is disabled. */
3356 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3359 /* Get the attribute type of the instruction. Note that this can
3360 ruin the contents of recog_data, so save/restore around the
3362 picochip_save_recog_data ();
3363 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3364 picochip_restore_recog_data ();
3366 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3369 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3370 else it must be the other ALU (either basic or nonCc)
3371 instruction which goes into 1. */
3372 if (attr_type
== TYPE_PICOALU
)
3378 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3380 /* Is this the non CC instruction? If it is, then stuff it into
3381 ALU 1, else it must be a picoAlu or basicAlu, in which case
3382 it goes into ALU 0. */
3383 if (attr_type
== TYPE_NONCCALU
)
3390 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3391 whether an ALU instruction has already been scheduled in this
3393 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3396 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3400 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3404 internal_error ("Too many ALU instructions emitted (%d)\n",
3405 picochip_current_vliw_state
.num_alu_insns_so_far
);
3412 /* Reset any information about the current VLIW packing status. */
3414 picochip_reset_vliw (rtx insn
)
3416 rtx local_insn
= insn
;
3418 /* Nothing to do if VLIW scheduling isn't being used. */
3419 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3423 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3426 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3427 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3428 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3429 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3430 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3431 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3433 /* Read through the VLIW packet, classifying the instructions where
3438 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3440 local_insn
= NEXT_INSN (local_insn
);
3443 else if (!INSN_P (local_insn
))
3447 /* It is an instruction, but is it ours? */
3448 if (INSN_CODE (local_insn
) != -1)
3452 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3454 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3455 get_attr_type function can overwrite the values in
3456 the recog_data global, hence this is saved and
3457 restored around the call. Not doing so results in
3458 asm_output_opcode being called with a different
3459 instruction to final_prescan_insn, which is fatal. */
3460 picochip_save_recog_data ();
3461 attr_type
= get_attr_type (local_insn
);
3462 picochip_restore_recog_data ();
3464 if (attr_type
== TYPE_PICOALU
)
3465 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3466 if (attr_type
== TYPE_NONCCALU
)
3467 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3472 /* Get the next instruction. */
3473 local_insn
= NEXT_INSN (local_insn
);
3475 /* Keep going while the next instruction is part of the same
3476 VLIW packet (i.e., its a valid instruction and doesn't mark
3477 the start of a new VLIW packet. */
3479 while (local_insn
&&
3480 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3485 picochip_sched_reorder (FILE * file
, int verbose
,
3486 rtx
* ready ATTRIBUTE_UNUSED
,
3487 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3491 fprintf (file
, ";;\tClock %d\n", clock
);
3493 return picochip_sched_issue_rate ();
3498 picochip_sched_lookahead (void)
3500 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3506 picochip_sched_issue_rate (void)
3511 /* Adjust the scheduling cost between the two given instructions,
3512 which have the given dependency. */
3514 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3519 printf ("Sched Adjust Cost: %d->%d is %d\n",
3520 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3522 printf (" Dependency type:");
3523 switch (REG_NOTE_KIND (link
))
3531 case REG_DEP_OUTPUT
:
3532 printf ("OUTPUT\n");
3535 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3539 /* Anti-dependencies are used to enforce the ordering between a
3540 * branch, and any subsequent instructions. For example:
3545 * The ADD instruction must execute after the branch, and this is
3546 * enforced using an anti-dependency. Unfortunately, VLIW machines
3547 * are happy to execute anti-dependent instructions in the same
3548 * cycle, which then results in a schedule like the following being
3551 * BNE someLabel \ ADD.0 r0,r1,r2
3553 * The instruction which would normally be conditionally executed
3554 * depending upon the outcome of the branch, is now unconditionally
3555 * executed every time. To prevent this happening, any
3556 * anti-dependencies between a branch and another instruction are
3557 * promoted to become real dependencies.
3559 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3563 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3564 INSN_UID (insn
), INSN_UID (dep_insn
));
3573 /* Return the minimum of the two values */
3575 minimum (int a
, int b
)
3581 /* I dont expect to get to this function with a==b.*/
3586 /* This function checks if the memory of the two stores are just off by 2 bytes.
3587 It returns the lower memory operand's index.*/
3590 memory_just_off (rtx opnd1
, rtx opnd2
)
3592 int offset1
= 0, offset2
= 0;
3595 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3597 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3598 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3602 reg1
= REGNO(XEXP(opnd1
, 0));
3604 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3606 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3607 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3611 reg2
= REGNO(XEXP(opnd2
, 0));
3614 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3615 should be 4 byte aligned. We can currently guarentee that only if the base
3616 address is FP(R13) and the offset is aligned. */
3618 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3619 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3625 registers_just_off (rtx opnd1
, rtx opnd2
)
3628 reg1
= REGNO(opnd1
);
3629 reg2
= REGNO(opnd2
);
3630 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3631 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3635 /* Check to see if the two LDWs can be peepholed together into a LDL
3636 They can be if the registers getting loaded into are contiguous
3637 and the memory addresses are contiguous as well.
3641 can be merged together into
3645 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3646 aligned address. Only FP can be assumed to be 4 byte aligned.
3647 2. The progression of addresses and the register numbers should
3648 be similar. For eg., if you swap r2 and r3 in the above instructions,
3649 the resultant pair cannot be merged.
3653 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3655 int memtest
=0,regtest
=0;
3656 regtest
= registers_just_off(opnd1
,opnd3
);
3660 memtest
= memory_just_off(opnd0
,opnd2
);
3664 if (regtest
== memtest
)
3671 /* Similar to LDW peephole */
3673 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3675 int memtest
=0,regtest
=0;
3676 regtest
= registers_just_off(opnd1
,opnd3
);
3680 memtest
= memory_just_off(opnd0
,opnd2
);
3684 if (regtest
== memtest
)
3692 /* Generate a SImode register with the register number that is the smaller of the two */
3694 gen_min_reg(rtx opnd1
,rtx opnd2
)
3696 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3699 /* Generate a SImode memory with the address that is the smaller of the two */
3701 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3703 int offset1
=0,offset2
=0;
3706 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3708 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3709 reg
= XEXP(XEXP(opnd1
,0),0);
3713 reg
= XEXP(opnd1
,0);
3715 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3717 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3719 address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3720 return gen_rtx_MEM(SImode
,address
);
3724 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3731 /* Need to penalize immediates that need to be encoded as long constants.*/
3732 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3734 *total
= COSTS_N_INSNS(1);
3742 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3747 /* if_then_else come out of cbranch instructions. It will get split into
3748 a condition code generating subtraction and a branch */
3749 *total
= COSTS_N_INSNS (2);
3756 if (GET_MODE(x
) == SImode
)
3757 *total
= COSTS_N_INSNS (2);
3758 if (GET_MODE(x
) == DImode
)
3759 *total
= COSTS_N_INSNS (4);
3763 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3764 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3765 *total
= COSTS_N_INSNS (10);
3767 /* 64-bit accesses have to be done through 2 32-bit access */
3768 if (GET_MODE(x
) == DImode
)
3769 *total
= COSTS_N_INSNS (2);
3775 /* SImode shifts are expensive */
3776 if (GET_MODE(x
) == SImode
)
3777 *total
= COSTS_N_INSNS (10);
3779 /* Register shift by constant is cheap. */
3780 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3781 && GET_CODE(XEXP(x
, 0)) == REG
3782 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3783 *total
= COSTS_N_INSNS (1);
3785 *total
= COSTS_N_INSNS (4);
3792 /* Divisions are more expensive than the default 7*/
3793 if (GET_MODE(x
) == SImode
)
3794 *total
= COSTS_N_INSNS (20);
3796 *total
= COSTS_N_INSNS (12);
3801 /* Look for the simple cases of multiplying register*register or
3802 register*constant. */
3803 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3804 && ((GET_CODE(XEXP(x
, 0)) == REG
3805 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3806 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3807 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3808 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3809 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3812 /* When optimising for size, multiplication by constant
3813 should be discouraged slightly over multiplication by a
3815 if (picochip_has_mac_unit
)
3817 /* Single cycle multiplication, but the result must be
3818 loaded back into a general register afterwards. */
3819 *total
= COSTS_N_INSNS(2);
3822 else if (picochip_has_mul_unit
)
3824 /* Single cycle multiplication. */
3825 *total
= COSTS_N_INSNS(1);
3828 /* Else no multiply available. Use default cost. */
3838 if (localTotal
!= 0)
3840 *total
= localTotal
;
3851 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3852 int num_operands ATTRIBUTE_UNUSED
)
3856 picochip_current_prescan_insn
= insn
;
3859 printf ("Final prescan on INSN %d with mode %s\n",
3860 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3862 /* If this is the start of a new instruction cycle, or no scheduling
3863 is used, then reset the VLIW status. */
3864 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3865 picochip_reset_vliw (insn
);
3867 /* No VLIW scheduling occured, so don't go any further. */
3868 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3871 /* Look for the next printable instruction. This loop terminates on
3872 any recognisable instruction, and on any unrecognisable
3873 instruction with TImode. */
3875 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3876 local_insn
= NEXT_INSN (local_insn
))
3878 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3880 else if (!INSN_P (local_insn
))
3882 else if (GET_MODE (local_insn
) == TImode
3883 || INSN_CODE (local_insn
) != -1)
3887 /* Set the continuation flag if the next instruction can be packed
3888 with the current instruction (i.e., the next instruction is
3889 valid, and isn't the start of a new cycle). */
3890 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3891 (GET_MODE (local_insn
) != TImode
));
3895 /* Builtin functions. */
3896 /* Given a builtin function taking 2 operands (i.e., target + source),
3897 emit the RTL for the underlying instruction. */
3899 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3903 enum machine_mode tmode
, mode0
;
3905 /* Grab the incoming argument and emit its RTL. */
3906 arg0
= CALL_EXPR_ARG (call
, 0);
3907 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3909 /* Determine the modes of the instruction operands. */
3910 tmode
= insn_data
[icode
].operand
[0].mode
;
3911 mode0
= insn_data
[icode
].operand
[1].mode
;
3913 /* Ensure that the incoming argument RTL is in a register of the
3915 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3916 op0
= copy_to_mode_reg (mode0
, op0
);
3918 /* If there isn't a suitable target, emit a target register. */
3920 || GET_MODE (target
) != tmode
3921 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3922 target
= gen_reg_rtx (tmode
);
3924 /* Emit and return the new instruction. */
3925 pat
= GEN_FCN (icode
) (target
, op0
);
3934 /* Given a builtin function taking 3 operands (i.e., target + two
3935 source), emit the RTL for the underlying instruction. */
3937 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3941 enum machine_mode tmode
, mode0
, mode1
;
3943 /* Grab the function's arguments. */
3944 arg0
= CALL_EXPR_ARG (call
, 0);
3945 arg1
= CALL_EXPR_ARG (call
, 1);
3947 /* Emit rtl sequences for the function arguments. */
3948 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3949 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3951 /* Get the mode's of each of the instruction operands. */
3952 tmode
= insn_data
[icode
].operand
[0].mode
;
3953 mode0
= insn_data
[icode
].operand
[1].mode
;
3954 mode1
= insn_data
[icode
].operand
[2].mode
;
3956 /* Ensure that each of the function argument rtl sequences are in a
3957 register of the correct mode. */
3958 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3959 op0
= copy_to_mode_reg (mode0
, op0
);
3960 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3961 op1
= copy_to_mode_reg (mode1
, op1
);
3963 /* If no target has been given, create a register to use as the target. */
3965 || GET_MODE (target
) != tmode
3966 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3967 target
= gen_reg_rtx (tmode
);
3969 /* Emit and return the new instruction. */
3970 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
3979 /* Expand a builtin function which takes two arguments, and returns a void. */
3981 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
3985 enum machine_mode mode0
, mode1
;
3987 /* Grab the function's arguments. */
3988 arg0
= CALL_EXPR_ARG (call
, 0);
3989 arg1
= CALL_EXPR_ARG (call
, 1);
3991 /* Emit rtl sequences for the function arguments. */
3992 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3993 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3995 /* Get the mode's of each of the instruction operands. */
3996 mode0
= insn_data
[icode
].operand
[0].mode
;
3997 mode1
= insn_data
[icode
].operand
[1].mode
;
3999 /* Ensure that each of the function argument rtl sequences are in a
4000 register of the correct mode. */
4001 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
4002 op0
= copy_to_mode_reg (mode0
, op0
);
4003 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
4004 op1
= copy_to_mode_reg (mode1
, op1
);
4006 /* Emit and return the new instruction. */
4007 pat
= GEN_FCN (icode
) (op0
, op1
);
4016 /* Expand an array get into the corresponding RTL. */
4018 picochip_expand_array_get (tree call
, rtx target
)
4020 tree arg0
, arg1
, arg2
;
4021 rtx op0
, op1
, op2
, pat
;
4023 /* Grab the function's arguments. */
4024 arg0
= CALL_EXPR_ARG (call
, 0);
4025 arg1
= CALL_EXPR_ARG (call
, 1);
4026 arg2
= CALL_EXPR_ARG (call
, 2) ;
4028 /* Emit rtl sequences for the function arguments. */
4029 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4030 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4031 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
4033 /* The second and third operands must be constant. Nothing else will
4035 if (CONST_INT
!= GET_CODE (op1
))
4036 internal_error ("%s: Second source operand is not a constant",
4038 if (CONST_INT
!= GET_CODE (op2
))
4039 internal_error ("%s: Third source operand is not a constant",
4042 /* If no target has been given, create a register to use as the target. */
4043 if (target
== 0 || GET_MODE (target
) != SImode
)
4044 target
= gen_reg_rtx (SImode
);
4046 /* The first operand must be a HImode register or a constant. If it
4047 isn't, force it into a HImode register. */
4048 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4049 op0
= copy_to_mode_reg (HImode
, op0
);
4052 /* Emit and return the new instruction. */
4053 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
4060 /* Expand an array put into the corresponding RTL. */
4062 picochip_expand_array_put (tree call
, rtx target
)
4064 tree arg0
, arg1
, arg2
, arg3
;
4065 rtx op0
, op1
, op2
, op3
, pat
;
4067 /* Grab the function's arguments. */
4068 arg0
= CALL_EXPR_ARG (call
, 0);
4069 arg1
= CALL_EXPR_ARG (call
, 1);
4070 arg2
= CALL_EXPR_ARG (call
, 2);
4071 arg3
= CALL_EXPR_ARG (call
, 3);
4073 /* Emit rtl sequences for the function arguments. */
4074 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4075 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4076 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
4077 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
4079 /* The first operand must be an SImode register. */
4080 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
4081 op0
= copy_to_mode_reg (SImode
, op0
);
4083 /* The second (index) operand must be a HImode register, or a
4084 constant. If it isn't, force it into a HImode register. */
4085 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
4086 op1
= copy_to_mode_reg (HImode
, op1
);
4088 /* The remaining operands must be constant. Nothing else will do. */
4089 if (CONST_INT
!= GET_CODE (op2
))
4090 internal_error ("%s: Third source operand is not a constant",
4092 if (CONST_INT
!= GET_CODE (op3
))
4093 internal_error ("%s: Fourth source operand is not a constant",
4096 /* Emit and return the new instruction. */
4097 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
4104 /* Expand an array testport into the corresponding RTL. */
4106 picochip_expand_array_testport (tree call
, rtx target
)
4108 tree arg0
, arg1
, arg2
;
4109 rtx op0
, op1
, op2
, pat
;
4111 /* Grab the function's arguments. */
4112 arg0
= CALL_EXPR_ARG (call
, 0);
4113 arg1
= CALL_EXPR_ARG (call
, 1);
4114 arg2
= CALL_EXPR_ARG (call
, 2);
4116 /* Emit rtl sequences for the function arguments. */
4117 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4118 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4119 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
4121 /* The first operand must be a HImode register, or a constant. If it
4122 isn't, force it into a HImode register. */
4123 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4124 op0
= copy_to_mode_reg (HImode
, op0
);
4126 /* The second and third operands must be constant. Nothing else will
4128 if (CONST_INT
!= GET_CODE (op1
))
4129 internal_error ("%s: Second source operand is not a constant",
4131 if (CONST_INT
!= GET_CODE (op2
))
4132 internal_error ("%s: Third source operand is not a constant",
4135 /* If no target has been given, create a HImode register to use as
4137 if (target
== 0 || GET_MODE (target
) != HImode
)
4138 target
= gen_reg_rtx (HImode
);
4140 /* Emit and return the new instruction. */
4141 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4148 /* Generate a unique HALT instruction by giving the instruction a
4149 unique integer. This integer makes no difference to the assembly
4150 output (other than a comment indicating the supplied id), but the
4151 presence of the unique integer prevents the compiler from combining
4152 several different halt instructions into one instruction. This
4153 means that each use of the halt instruction is unique, which in
4154 turn means that assertions work as expected. */
4156 picochip_generate_halt (void)
4158 static int currentId
= 0;
4160 rtx id
= GEN_INT (currentId
);
4164 emit_insn (gen_halt (id
));
4166 /* A barrier is inserted to prevent the compiler from thinking that
4167 it has to continue execution after the HALT.*/
4170 insns
= get_insns();
4177 /* Initialise the builtin functions. Start by initialising
4178 descriptions of different types of functions (e.g., void fn(int),
4179 int fn(void)), and then use these to define the builtins. */
4181 picochip_init_builtins (void)
4184 tree endlink
= void_list_node
;
4185 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
4186 tree unsigned_endlink
= tree_cons (NULL_TREE
, unsigned_type_node
, endlink
);
4187 tree long_endlink
= tree_cons (NULL_TREE
, long_integer_type_node
, endlink
);
4188 tree int_int_endlink
=
4189 tree_cons (NULL_TREE
, integer_type_node
, int_endlink
);
4190 tree int_int_int_endlink
=
4191 tree_cons (NULL_TREE
, integer_type_node
, int_int_endlink
);
4192 tree int_long_endlink
=
4193 tree_cons (NULL_TREE
, integer_type_node
, long_endlink
);
4194 tree pchar_type_node
= build_pointer_type (char_type_node
);
4195 tree long_int_int_int_endlink
=
4196 tree_cons (NULL_TREE
, long_integer_type_node
, int_int_int_endlink
);
4198 tree int_ftype_void
, int_ftype_int
, int_ftype_int_int
, void_ftype_pchar
;
4199 tree long_ftype_int
, long_ftype_int_int
, long_ftype_int_int_int
;
4200 tree void_ftype_int_long
, int_ftype_int_int_int
,
4201 void_ftype_long_int_int_int
;
4202 tree void_ftype_void
, void_ftype_int
, unsigned_ftype_unsigned
;
4204 /* void func (void) */
4205 void_ftype_void
= build_function_type (void_type_node
, endlink
);
4207 /* void func (void *) */
4209 = build_function_type (void_type_node
,
4210 tree_cons (NULL_TREE
, pchar_type_node
, endlink
));
4212 /* int func (void) */
4213 int_ftype_void
= build_function_type (integer_type_node
, endlink
);
4215 /* void func (int) */
4216 void_ftype_int
= build_function_type (void_type_node
, int_endlink
);
4218 /* int func (int) */
4219 int_ftype_int
= build_function_type (integer_type_node
, int_endlink
);
4221 /* unsigned int func (unsigned int) */
4222 unsigned_ftype_unsigned
= build_function_type (unsigned_type_node
, unsigned_endlink
);
4224 /* int func(int, int) */
4226 = build_function_type (integer_type_node
, int_int_endlink
);
4228 /* long func(int) */
4229 long_ftype_int
= build_function_type (long_integer_type_node
, int_endlink
);
4231 /* long func(int, int) */
4233 = build_function_type (long_integer_type_node
, int_int_endlink
);
4235 /* long func(int, int, int) */
4236 long_ftype_int_int_int
4237 = build_function_type (long_integer_type_node
, int_int_int_endlink
);
4239 /* int func(int, int, int) */
4240 int_ftype_int_int_int
4241 = build_function_type (integer_type_node
, int_int_int_endlink
);
4243 /* void func(int, long) */
4245 = build_function_type (void_type_node
, int_long_endlink
);
4247 /* void func(long, int, int, int) */
4248 void_ftype_long_int_int_int
4249 = build_function_type (void_type_node
, long_int_int_int_endlink
);
4251 /* Initialise the sign-bit-count function. */
4252 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4253 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4255 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4256 BUILT_IN_MD
, NULL
, NULL_TREE
);
4258 /* Initialise the bit reverse function. */
4259 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4260 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4262 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4263 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4266 /* Initialise the byte swap function. */
4267 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4268 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4270 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4271 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4274 /* Initialise the ASRI function (note that while this can be coded
4275 using a signed shift in C, extra scratch registers are required,
4276 which we avoid by having a direct builtin to map to the
4278 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4279 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4282 /* Initialise saturating addition. */
4283 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4284 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4286 add_builtin_function ("picoAdds", int_ftype_int_int
,
4287 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4290 /* Initialise saturating subtraction. */
4291 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4292 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4294 add_builtin_function ("picoSubs", int_ftype_int_int
,
4295 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4298 /* Scalar comms builtins. */
4299 add_builtin_function ("__builtin_get", long_ftype_int
,
4300 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4302 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4303 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4305 add_builtin_function ("__builtin_testport", int_ftype_int
,
4306 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4309 /* Array comms builtins. */
4310 add_builtin_function ("__builtin_put_array",
4311 void_ftype_long_int_int_int
,
4312 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4314 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4315 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4317 add_builtin_function ("__builtin_testport_array",
4318 int_ftype_int_int_int
,
4319 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4322 /* Halt instruction. Note that the builtin function is marked as
4323 having the attribute `noreturn' so that the compiler realises
4324 that the halt stops the program dead. */
4325 noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4326 add_builtin_function ("__builtin_halt", void_ftype_void
,
4327 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4329 add_builtin_function ("picoHalt", void_ftype_void
,
4330 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4335 /* Expand a call to a builtin function. */
4337 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4338 enum machine_mode mode ATTRIBUTE_UNUSED
,
4339 int ignore ATTRIBUTE_UNUSED
)
4341 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4342 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4346 case PICOCHIP_BUILTIN_ASRI
:
4347 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4350 case PICOCHIP_BUILTIN_ADDS
:
4351 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4354 case PICOCHIP_BUILTIN_SUBS
:
4355 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4358 case PICOCHIP_BUILTIN_SBC
:
4359 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4361 case PICOCHIP_BUILTIN_BREV
:
4362 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4364 case PICOCHIP_BUILTIN_BYTESWAP
:
4365 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4367 case PICOCHIP_BUILTIN_GET
:
4368 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4370 case PICOCHIP_BUILTIN_PUT
:
4371 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4373 case PICOCHIP_BUILTIN_TESTPORT
:
4374 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4377 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4378 return picochip_expand_array_put (exp
, target
);
4380 case PICOCHIP_BUILTIN_GET_ARRAY
:
4381 return picochip_expand_array_get (exp
, target
);
4383 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4384 return picochip_expand_array_testport (exp
, target
);
4386 case PICOCHIP_BUILTIN_HALT
:
4387 return picochip_generate_halt ();
4394 /* Should really do something sensible here. */
4398 /* Emit warnings. */
4400 picochip_warn_inefficient (const char *msg
)
4402 if (TARGET_INEFFICIENT_WARNINGS
)
4403 warning (OPT_minefficient_warnings
,
4404 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4408 warn_of_byte_access (void)
4410 static int warned
= 0;
4414 picochip_warn_inefficient
4415 ("byte access is synthesised - consider using MUL AE");
4422 picochip_function_value (const_tree valtype
, const_tree func
,
4423 bool outgoing ATTRIBUTE_UNUSED
)
4425 enum machine_mode mode
= TYPE_MODE (valtype
);
4426 int unsignedp
= TYPE_UNSIGNED (valtype
);
4428 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4429 just as PROMOTE_MODE does. */
4430 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4432 return gen_rtx_REG (mode
, 0);
4436 /* Check that the value of the given mode will fit in the register of
4439 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4442 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4443 return regno
== CC_REGNUM
;
4445 /* If the CC register is being used, then only CC mode values are
4446 allowed (which have already been tested). */
4447 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4450 /* Must be a valid register. */
4454 /* Modes QI and HI may be placed in any register except the CC. */
4455 if (mode
== QImode
|| mode
== HImode
)
4458 /* DI must be in a quad register. */
4460 return (regno
% 4 == 0);
4462 /* All other modes must be placed in a even numbered register. */
4463 return !(regno
& 1);
4467 /* Extract the lower and upper components of a constant value. */
4470 picochip_get_low_const (rtx value
)
4472 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4476 picochip_get_high_const (rtx value
)
4478 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4479 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4483 /* Loading and storing QImode values to and from memory in a machine
4484 without byte access requires might require a scratch
4485 register. However, the scratch register might correspond to the
4486 register in which the value is being loaded. To ensure that a
4487 scratch register is supplied which is definitely different to the
4488 output register, request a register pair. This effectively gives a
4489 choice of two registers to choose from, so that we a guaranteed to
4490 get at least one register which is different to the output
4491 register. This trick is taken from the alpha implementation. */
4493 picochip_secondary_reload (bool in_p
,
4494 rtx x ATTRIBUTE_UNUSED
,
4495 reg_class_t cla ATTRIBUTE_UNUSED
,
4496 enum machine_mode mode
,
4497 secondary_reload_info
*sri
)
4499 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4502 sri
->icode
= CODE_FOR_reload_outqi
;
4504 sri
->icode
= CODE_FOR_reload_inqi
;
4507 /* We dont need to return a register class type when we need only a
4508 scratch register. It realizes the scratch register type by looking
4509 at the instruction definition for sri->icode. We only need to
4510 return the register type when we need intermediaries for copies.*/
4514 /* Return true if the given memory operand can be aligned to a
4515 word+offset memory reference (e.g., FP+3 can be converted into the
4516 memory operand FP+2, with the offset 1). */
4518 picochip_alignable_memory_operand (rtx mem_operand
,
4519 enum machine_mode mode ATTRIBUTE_UNUSED
)
4523 /* Not a mem operand. Refuse immediately. */
4524 if (MEM
!= GET_CODE (mem_operand
))
4527 address
= XEXP (mem_operand
, 0);
4529 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4530 return ((PLUS
== GET_CODE (address
) &&
4531 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4532 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4533 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4534 || (REG
== GET_CODE (address
)
4535 && REGNO (address
) == STACK_POINTER_REGNUM
));
4539 /* Return true if the given memory reference is to a word aligned
4540 address. Currently this means it must be either SP, or
4541 SP+offset. We could replace this function with alignable
4542 memory references in the above function?. */
4544 picochip_word_aligned_memory_reference (rtx operand
)
4548 /* The address must be the SP register, or a constant, aligned
4549 offset from SP which doesn't exceed the FP+offset
4551 return ((PLUS
== GET_CODE (operand
)
4552 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4553 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4554 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4556 || (REG
== GET_CODE (operand
)
4557 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4561 /* Given an alignable memory location, convert the memory location
4562 into a HI mode access, storing the new memory reference in
4563 paligned_mem, and the number of bits by which to shift in pbitnum
4564 (i.e., given a reference to FP+3, this creates an aligned reference
4565 of FP+2, with an 8-bit shift). This code is a modification of that
4566 found in the Alpha port. */
4568 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4571 HOST_WIDE_INT offset
= 0;
4573 gcc_assert (GET_CODE (ref
) == MEM
);
4575 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4577 base
= find_replacement (&XEXP (ref
, 0));
4579 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4583 base
= XEXP (ref
, 0);
4586 if (GET_CODE (base
) == PLUS
)
4588 offset
+= INTVAL (XEXP (base
, 1));
4589 base
= XEXP (base
, 0);
4592 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4599 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4603 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4607 /* Return true if the given operand is an absolute address in memory
4608 (i.e., a symbolic offset). */
4610 picochip_absolute_memory_operand (rtx op
,
4611 enum machine_mode mode ATTRIBUTE_UNUSED
)
4614 if (MEM
== GET_CODE (op
))
4616 rtx address
= XEXP (op
, 0);
4618 /* Symbols are valid absolute addresses. */
4619 if (SYMBOL_REF
== GET_CODE (address
))
4622 /* Constant offsets to symbols are valid absolute addresses. */
4623 if (CONST
== GET_CODE (address
) &&
4624 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4625 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4626 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4633 /* Symbols are valid absolute addresses. */
4634 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4643 picochip_asm_named_section (const char *name
,
4644 unsigned int flags ATTRIBUTE_UNUSED
,
4645 tree decl ATTRIBUTE_UNUSED
)
4647 fprintf (asm_out_file
, ".section %s\n", name
);
4651 /* Check if we can make a conditional copy instruction. This is emitted as an
4652 instruction to set the condition register, followed by an instruction which
4653 uses the condition registers to perform the conditional move. */
4655 picochip_check_conditional_copy (rtx
* operands
)
4658 rtx branch_op_0
= XEXP (operands
[1], 0);
4659 rtx branch_op_1
= XEXP (operands
[1], 1);
4661 /* Only HI mode conditional moves are currently allowed. Can we add
4663 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4666 /* Is the comparison valid? Only allow operands which are registers
4667 if they are HImode. SI mode comparisons against 0 could be
4668 handled using logical operations (e.g., SIreg != 0 when low ||
4669 high). Need to find test cases to provoke this though (fixunssfdi
4670 in libgcc does, but is complicated). */
4671 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4672 GET_MODE(branch_op_0
) != HImode
)
4674 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4675 GET_MODE(branch_op_1
) != HImode
)
4684 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4688 addr
= arg_pointer_rtx
;
4690 addr
= plus_constant (stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4691 return gen_frame_mem (Pmode
, addr
);