1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
44 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "langhooks.h"
55 #include "picochip-protos.h"
57 #include "insn-attr.h" /* For DFA state_t. */
58 #include "insn-config.h" /* Required by recog.h */
59 #include "insn-codes.h" /* For CODE_FOR_? */
60 #include "optabs.h" /* For GEN_FCN */
61 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
62 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
63 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
64 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
67 /* Target AE ISA information. */
68 enum picochip_dfa_type picochip_schedule_type
;
70 bool picochip_has_mul_unit
= false;
71 bool picochip_has_mac_unit
= false;
73 /* targetm hook function prototypes. */
75 void picochip_asm_file_start (void);
76 void picochip_asm_file_end (void);
78 void picochip_init_libfuncs (void);
79 void picochip_reorg (void);
81 int picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
,
82 enum machine_mode mode
,
83 tree type
, bool named
);
84 rtx
picochip_function_arg (CUMULATIVE_ARGS
* p_cum
,
85 enum machine_mode mode
,
86 const_tree type
, bool named
);
87 rtx
picochip_incoming_function_arg (CUMULATIVE_ARGS
* p_cum
,
88 enum machine_mode mode
,
89 const_tree type
, bool named
);
90 void picochip_arg_advance (CUMULATIVE_ARGS
* p_cum
, enum machine_mode mode
,
91 const_tree type
, bool named
);
93 int picochip_sched_lookahead (void);
94 int picochip_sched_issue_rate (void);
95 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
96 rtx dep_insn
, int cost
);
97 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
98 int *n_readyp
, int clock
);
100 void picochip_init_builtins (void);
101 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
103 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int* total
, bool speed
);
104 bool picochip_return_in_memory(const_tree type
,
105 const_tree fntype ATTRIBUTE_UNUSED
);
106 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
107 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
108 enum machine_mode mode
);
109 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
110 int opnum
, int type
, int ind_levels
);
112 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
113 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
114 bool outgoing ATTRIBUTE_UNUSED
);
116 picochip_secondary_reload (bool in_p
,
117 rtx x ATTRIBUTE_UNUSED
,
118 reg_class_t cla ATTRIBUTE_UNUSED
,
119 enum machine_mode mode
,
120 secondary_reload_info
*sri
);
122 picochip_asm_named_section (const char *name
,
123 unsigned int flags ATTRIBUTE_UNUSED
,
124 tree decl ATTRIBUTE_UNUSED
);
126 static rtx
picochip_static_chain (const_tree
, bool);
128 static void picochip_option_override (void);
130 /* Lookup table mapping a register number to the earliest containing
131 class. Used by REGNO_REG_CLASS. */
132 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
134 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
135 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
136 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
137 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
138 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
141 /* picoChip register names. */
142 const char *picochip_regnames
[] = REGISTER_NAMES
;
144 /* Define the maximum number of registers which may be used to pass
145 * parameters to functions. */
146 #define MAX_CALL_PARAMETER_REGS 6
149 /* Target scheduling information. */
151 /* Determine whether we run our final scheduling pass or not. We always
152 avoid the normal second scheduling pass. */
153 int picochip_flag_schedule_insns2
;
155 /* Check if variable tracking needs to be run. */
156 int picochip_flag_var_tracking
;
158 /* This flag indicates whether the next instruction to be output is a
159 VLIW continuation instruction. It is used to communicate between
160 final_prescan_insn and asm_output_opcode. */
161 static int picochip_vliw_continuation
= 0;
163 /* This variable is used to communicate the current instruction
164 between final_prescan_insn and functions such as asm_output_opcode,
165 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
166 current instruction. */
167 static rtx picochip_current_prescan_insn
;
169 static bool picochip_is_delay_slot_pending
= 0;
171 /* When final_prescan_insn is called, it computes information about
172 the current VLIW packet, and stores it in this structure. When
173 instructions are output, this state is used to make sure that the
174 instructions are output in the correct way (e.g., which ALU to use,
175 whether a macro branch was ever previously a real branch, etc.). */
178 int contains_pico_alu_insn
;
179 int contains_non_cc_alu_insn
;
180 int num_alu_insns_so_far
;
182 /* Record how many instructions are contained in the packet. */
183 int num_insns_in_packet
;
185 /* There was a case for this to be more than 1 */
186 int num_cfi_labels_deferred
;
187 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
188 emitted inside a VLIW packet. */
189 char lm_label_name
[256]; /* Used to record the name of an LM label. */
192 struct vliw_state picochip_current_vliw_state
;
194 /* Save/restore recog_data. */
195 static int picochip_saved_which_alternative
;
196 static struct recog_data picochip_saved_recog_data
;
198 /* Determine which ALU to use for the instruction in
199 picochip_current_prescan_insn. */
200 static char picochip_get_vliw_alu_id (void);
202 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
203 static const struct default_options picochip_option_optimization_table
[] =
205 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
206 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
209 /* Initialize the GCC target structure. */
211 #undef TARGET_ASM_FUNCTION_PROLOGUE
212 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
214 #undef TARGET_ASM_FUNCTION_EPILOGUE
215 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
217 #undef TARGET_ASM_INTERNAL_LABEL
218 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
220 #undef TARGET_ASM_GLOBALIZE_LABEL
221 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
223 #undef TARGET_ASM_BYTE_OP
224 #define TARGET_ASM_BYTE_OP ".initByte "
225 #undef TARGET_ASM_ALIGNED_HI_OP
226 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
227 #undef TARGET_ASM_UNALIGNED_HI_OP
228 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
229 #undef TARGET_ASM_ALIGNED_SI_OP
230 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
231 #undef TARGET_ASM_UNALIGNED_SI_OP
232 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
234 #undef TARGET_INIT_BUILTINS
235 #define TARGET_INIT_BUILTINS picochip_init_builtins
237 #undef TARGET_EXPAND_BUILTIN
238 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
240 #undef TARGET_RTX_COSTS
241 #define TARGET_RTX_COSTS picochip_rtx_costs
243 #undef TARGET_SCHED_ISSUE_RATE
244 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
246 #undef TARGET_SCHED_REORDER
247 #define TARGET_SCHED_REORDER picochip_sched_reorder
249 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
250 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
251 picochip_sched_lookahead
253 #undef TARGET_SCHED_ADJUST_COST
254 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
256 #undef TARGET_ASM_NAMED_SECTION
257 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
259 #undef TARGET_HAVE_NAMED_SECTIONS
260 #define TARGET_HAVE_NAMED_SECTIONS 1
262 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
263 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
265 #undef TARGET_INIT_LIBFUNCS
266 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
268 #undef TARGET_ASM_FILE_START
269 #define TARGET_ASM_FILE_START picochip_asm_file_start
271 #undef TARGET_ASM_FILE_END
272 #define TARGET_ASM_FILE_END picochip_asm_file_end
274 #undef TARGET_MACHINE_DEPENDENT_REORG
275 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
277 #undef TARGET_ARG_PARTIAL_BYTES
278 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
280 #undef TARGET_FUNCTION_ARG
281 #define TARGET_FUNCTION_ARG picochip_function_arg
283 #undef TARGET_FUNCTION_INCOMING_ARG
284 #define TARGET_FUNCTION_INCOMING_ARG picochip_incoming_function_arg
286 #undef TARGET_FUNCTION_ARG_ADVANCE
287 #define TARGET_FUNCTION_ARG_ADVANCE picochip_arg_advance
289 #undef TARGET_PROMOTE_FUNCTION_MODE
290 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
291 #undef TARGET_PROMOTE_PROTOTYPES
292 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
294 /* Target support for Anchored Addresses optimization */
295 #undef TARGET_MIN_ANCHOR_OFFSET
296 #define TARGET_MIN_ANCHOR_OFFSET 0
297 #undef TARGET_MAX_ANCHOR_OFFSET
298 #define TARGET_MAX_ANCHOR_OFFSET 7
299 #undef TARGET_ASM_OUTPUT_ANCHOR
300 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
302 #undef TARGET_FUNCTION_VALUE
303 #define TARGET_FUNCTION_VALUE picochip_function_value
305 #undef TARGET_LIBGCC_CMP_RETURN_MODE
306 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
309 #undef TARGET_LEGITIMATE_ADDRESS_P
310 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
312 #undef TARGET_LEGITIMIZE_ADDRESS
313 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
315 /* Loading and storing QImode values to and from memory
316 usually requires a scratch register. */
317 #undef TARGET_SECONDARY_RELOAD
318 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
319 #undef DONT_USE_BUILTIN_SETJMP
320 #define DONT_USE_BUILTIN_SETJMP 1
322 /* How Large Values are Returned */
324 #undef TARGET_RETURN_IN_MEMORY
325 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
327 #undef TARGET_STATIC_CHAIN
328 #define TARGET_STATIC_CHAIN picochip_static_chain
330 #undef TARGET_OPTION_OVERRIDE
331 #define TARGET_OPTION_OVERRIDE picochip_option_override
333 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
334 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
336 #undef TARGET_OPTION_OPTIMIZATION_TABLE
337 #define TARGET_OPTION_OPTIMIZATION_TABLE picochip_option_optimization_table
339 #undef TARGET_EXCEPT_UNWIND_INFO
340 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
342 struct gcc_target targetm
= TARGET_INITIALIZER
;
345 /* Only return a value in memory if it is greater than 4 bytes.
346 int_size_in_bytes returns -1 for variable size objects, which go in
347 memory always. The cast to unsigned makes -1 > 8. */
350 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
352 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
355 /* Allow some options to be overriden. In particular, the 2nd
356 scheduling pass option is switched off, and a machine dependent
357 reorganisation ensures that it is run later on, after the second
358 jump optimisation. */
361 picochip_option_override (void)
363 /* If we are optimizing for stack, dont let inliner to inline functions
364 that could potentially increase stack size.*/
365 if (flag_conserve_stack
)
367 maybe_set_param_value (PARAM_LARGE_STACK_FRAME
, 0,
368 global_options
.x_param_values
,
369 global_options_set
.x_param_values
);
370 maybe_set_param_value (PARAM_STACK_FRAME_GROWTH
, 0,
371 global_options
.x_param_values
,
372 global_options_set
.x_param_values
);
375 /* Turn off the elimination of unused types. The elaborator
376 generates various interesting types to represent constants,
377 generics, and so on, and it is useful to retain this information
378 in the debug output. The increased size of the debug information
379 is not really an issue for us. */
380 flag_eliminate_unused_debug_types
= 0;
382 /* Even if the user specifies a -fno-omit-frame-pointer on the
383 command line, we still want to go ahead and omit frame pointer
384 usages, since we dont really have a frame pointer register.
385 So, all accesses to FP need to be converted to accesses off
387 flag_omit_frame_pointer
= 1;
389 /* Turning on anchored addresses by default. This is an optimization
390 that could decrease the code size by placing anchors in data and
391 accessing offsets from the anchor for file local data variables.*/
393 flag_section_anchors
= 1;
395 /* Turn off the second scheduling pass, and move it to
396 picochip_reorg, to avoid having the second jump optimisation
397 trash the instruction modes (e.g., instructions are changed to
398 TImode to mark the beginning of cycles). Two types of DFA
399 scheduling are possible: space and speed. In both cases,
400 instructions are reordered to avoid stalls (e.g., memory loads
401 stall for one cycle). Speed scheduling will also enable VLIW
402 instruction packing. VLIW instructions use more code space, so
403 VLIW scheduling is disabled when scheduling for size. */
404 picochip_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
405 flag_schedule_insns_after_reload
= 0;
406 if (picochip_flag_schedule_insns2
)
409 picochip_schedule_type
= DFA_TYPE_SPACE
;
412 picochip_schedule_type
= DFA_TYPE_SPEED
;
413 flag_delayed_branch
= 0;
417 picochip_schedule_type
= DFA_TYPE_NONE
;
419 /* Ensure that the debug level is always at least -g2. The flow
420 analyser works at its best if it always has debug
421 information. DWARF is non-intrusive, so it makes no difference to
422 code quality if debug is always enabled. */
423 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
425 debug_info_level
= DINFO_LEVEL_NORMAL
;
426 write_symbols
= DWARF2_DEBUG
;
429 /* Options of the form -mae=mac, and so on will be substituted by
430 the compiler driver for the appropriate byte access and multiply
431 unit ISA options. Any unrecognised AE types will end up being
432 passed to the compiler, which should reject them as invalid. */
433 if (picochip_ae_type_string
!= NULL
)
434 error ("invalid AE type specified (%s)\n", picochip_ae_type_string
);
436 /* Override any specific capabilities of the instruction set. These
437 take precedence over any capabilities inferred from the AE type,
438 regardless of where the options appear on the command line. */
439 if (picochip_mul_type_string
== NULL
)
441 /* Default to MEM-type multiply, for historical compatibility. */
442 picochip_has_mac_unit
= false;
443 picochip_has_mul_unit
= true;
447 picochip_has_mac_unit
= false;
448 picochip_has_mul_unit
= false;
450 if (strcmp (picochip_mul_type_string
, "mul") == 0)
451 picochip_has_mul_unit
= true;
452 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
453 picochip_has_mac_unit
= true;
454 else if (strcmp (picochip_mul_type_string
, "none") == 0)
455 { /* Do nothing. Unit types already set to false. */ }
457 error ("Invalid mul type specified (%s) - expected mac, mul or none",
458 picochip_mul_type_string
);
464 /* Initialise the library functions to handle arithmetic on some of
467 picochip_init_libfuncs (void)
470 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
471 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
472 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
474 /* 64-bit signed multiplication. */
475 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
477 /* Signed division */
478 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
479 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
482 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
483 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
485 /* 32-bit count leading Zeros*/
486 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
488 /* 64-bit comparison */
489 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
490 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
492 /* 64-bit addition and subtraction*/
493 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
494 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
497 /* Memcpy function */
499 picochip_expand_movmemhi (rtx
*operands
)
501 rtx src_addr_reg
, dst_addr_reg
, count_reg
, src_mem
, dst_mem
, tmp_reg
;
504 src_addr_reg
= gen_reg_rtx(HImode
);
505 dst_addr_reg
= gen_reg_rtx(HImode
);
506 count_reg
= gen_reg_rtx(HImode
);
507 emit_insn (gen_movhi (count_reg
, operands
[2]));
508 emit_insn (gen_movqi (src_addr_reg
, XEXP(operands
[1], 0)));
509 emit_insn (gen_movqi (dst_addr_reg
, XEXP(operands
[0], 0)));
510 gcc_assert (GET_CODE(count_reg
) == REG
);
511 start_label
= gen_label_rtx ();
512 emit_label (start_label
);
514 /* We can specialise the code for different alignments */
515 align
= INTVAL(operands
[3]);
516 size
= INTVAL(operands
[2]);
517 gcc_assert(align
>= 0 && size
>= 0);
520 if (size
% 4 == 0 && align
% 4 == 0)
522 src_mem
= gen_rtx_MEM(SImode
, src_addr_reg
);
523 dst_mem
= gen_rtx_MEM(SImode
, dst_addr_reg
);
524 tmp_reg
= gen_reg_rtx(SImode
);
525 emit_insn (gen_movsi (tmp_reg
, src_mem
));
526 emit_insn (gen_movsi (dst_mem
, tmp_reg
));
527 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, GEN_INT(4)));
528 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, GEN_INT(4)));
529 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-4)));
530 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
531 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
533 else if (size
% 2 == 0 && align
% 2 == 0)
535 src_mem
= gen_rtx_MEM(HImode
, src_addr_reg
);
536 dst_mem
= gen_rtx_MEM(HImode
, dst_addr_reg
);
537 tmp_reg
= gen_reg_rtx(HImode
);
538 emit_insn (gen_movhi (tmp_reg
, src_mem
));
539 emit_insn (gen_movhi (dst_mem
, tmp_reg
));
540 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const2_rtx
));
541 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const2_rtx
));
542 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-2)));
543 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
544 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
548 src_mem
= gen_rtx_MEM(QImode
, src_addr_reg
);
549 dst_mem
= gen_rtx_MEM(QImode
, dst_addr_reg
);
550 tmp_reg
= gen_reg_rtx(QImode
);
551 emit_insn (gen_movqi (tmp_reg
, src_mem
));
552 emit_insn (gen_movqi (dst_mem
, tmp_reg
));
553 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const1_rtx
));
554 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const1_rtx
));
555 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-1)));
556 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
557 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
564 /* Return the register class for letter C. */
566 picochip_reg_class_from_letter (unsigned c
)
584 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
586 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
589 picochip_order_regs_for_local_alloc (void)
591 /* We change the order for leaf functions alone. We put r12 at
592 the end since using it will prevent us to combine stw/ldws to
593 stl/ldl and it gives no benefit. In non-leaf functions, we
594 would anyway saveup/restore r12, so it makes sense to use it.*/
596 if (leaf_function_p())
598 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
599 FIRST_PSEUDO_REGISTER
* sizeof (int));
603 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
604 FIRST_PSEUDO_REGISTER
* sizeof (int));
608 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
610 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
615 case 'I': /* 4 bits signed. */
616 return value
+ 8 < 16;
617 case 'J': /* 4 bits unsigned. */
619 case 'K': /* 8 bits signed. */
620 return value
+ 128 < 256;
621 case 'M': /* 4-bit magnitude. */
622 return abs (value
) < 16;
623 case 'N': /* 10 bits signed. */
624 return value
+ 512 > 1024;
625 case 'O': /* 16 bits signed. */
626 return value
+ 32768 < 65536;
627 default: /* Unknown letter. */
632 /* Stack utility functions. */
634 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
637 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
643 /* Emit a set of parallel register expressions used to store
644 blockmode values to pass to functions. */
646 picochip_emit_register_parallel (int size_in_units
, int offset
)
650 rtx vector
[MAX_CALL_PARAMETER_REGS
];
654 /* Compute the base register, and number of required registers. */
655 base_reg
= offset
/ 2;
656 num_regs
= size_in_units
/ 2;
657 if (size_in_units
% 2 == 1)
660 /* Emit a register for each part of the block mode value to be
661 passed in a register. */
662 for (i
= 0; i
< num_regs
; i
++)
663 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
664 gen_rtx_REG (HImode
, base_reg
+ i
),
666 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
672 /* Emit an instruction to allocate a suitable amount of space on the
673 stack, by decrementing the stack pointer. */
675 picochip_emit_stack_allocate (int adjustment
)
678 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
680 /* Use an addition of a negative value. */
681 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
682 GEN_INT (-adjustment
)));
684 /* Make the instruction frame related. Also add an expression note,
685 so that the correct Dwarf information is generated (see documention
686 for RTX_FRAME_RELATED_P for more details). */
687 RTX_FRAME_RELATED_P (insn
) = 1;
688 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
689 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
690 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
691 GEN_INT (-adjustment
))));
695 /* Emit an instruction to save a register of the given mode. The
696 offset at which to save the register is given relative to the stack
699 picochip_emit_save_register (rtx reg
, int offset
)
701 rtx stack_pointer
, address
, mem
, insn
;
703 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
705 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
707 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
709 insn
= emit_move_insn (mem
, reg
);
710 RTX_FRAME_RELATED_P (insn
) = 1;
712 /* For modes other than HImode, create a note explaining that
713 multiple registers have been saved. This allows the correct DWARF
714 call frame information to be generated. */
715 switch (GET_MODE (reg
))
718 /* The RTL is sufficient to explain HImode register saves. */
722 /* SImode must be broken down into parallel HImode register saves. */
730 gen_rtx_PLUS (Pmode
, stack_pointer
,
732 gen_rtx_REG (HImode
, REGNO (reg
)));
733 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
736 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
741 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
742 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
744 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
745 gen_rtx_PARALLEL (VOIDmode
, p
));
752 ("unexpected mode %s encountered in picochip_emit_save_register\n",
753 GET_MODE_NAME (GET_MODE (reg
)));
758 /* Emit an instruction to restore a register of the given mode. The
759 offset from which to restore the register is given relative to the
762 picochip_emit_restore_register (rtx reg
, int offset
)
764 rtx stack_pointer
, address
, mem
;
766 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
768 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
770 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
772 emit_move_insn (reg
, mem
);
776 /* Check that the given byte offset is aligned to the given number of
779 picochip_is_aligned (int byte_offset
, int bit_alignment
)
781 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
782 return (byte_offset
% byte_alignment
) == 0;
785 /*****************************************************************************
788 * The following section contains code which controls how the stack is
791 * The stack is laid out as follows (high addresses first):
794 * Pretend arguments (ARG PTR)
798 * Outgoing arguments (SP)
800 * The (constant) offsets of the different areas must be calculated
801 * relative to the stack area immediately below, and aligned
802 * appropriately. For example, the frame offset is computed by
803 * determining the offset of the special register area, adding the
804 * size of the special register area, and then aligning the resulting
805 * offset correctly. In turn, the special register offset is computed
806 * from the general register offset, and so on. This enables the
807 * different offsets to change size and alignment, without requiring
808 * the code for other offset calculations to be rewritten.
810 * The argument pointer, and the frame pointer are eliminated wherever
811 * possible, by replacing them with a constant offset from the stack
812 * pointer. In the rare cases where constant offsets from the stack
813 * pointer cannot be computed, another register will be allocated to
814 * serve as the argument pointer, or the frame pointer.
816 * The save registers are stored at small offsets from the caller, to
817 * enable the more efficient SP-based ISA instructions to be used.
819 ****************************************************************************/
821 /* Compute the size of an argument in units. */
823 picochip_compute_arg_size (const_tree type
, enum machine_mode mode
)
825 int type_size_in_units
= 0;
828 type_size_in_units
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
830 type_size_in_units
= GET_MODE_SIZE (mode
);
832 return type_size_in_units
;
836 /* Determine where the next outgoing arg should be placed. */
838 picochip_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
839 const_tree type
, bool named ATTRIBUTE_UNUSED
)
842 int type_align_in_units
= 0;
843 int type_size_in_units
;
845 int offset_overflow
= 0;
847 /* VOIDmode is passed when computing the second argument to a `call'
848 pattern. This can be ignored. */
849 if (mode
== VOIDmode
)
852 /* Compute the alignment and size of the parameter. */
853 type_align_in_units
=
854 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
855 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
857 /* Compute the correct offset (i.e., ensure that the offset meets
858 the alignment requirements). */
859 offset_overflow
= *cum
% type_align_in_units
;
860 if (offset_overflow
== 0)
863 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
867 printf ("Function arg:\n");
868 printf (" Type valid: %s\n", (type
? "yes" : "no"));
869 printf (" Cumulative Value: %d\n", *cum
);
870 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
871 printf (" Type size: %i units\n", type_size_in_units
);
872 printf (" Alignment: %i units\n", type_align_in_units
);
873 printf (" New offset: %i\n", new_offset
);
877 /* If the new offset is outside the register space, return. */
878 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
881 /* If the end of the argument is outside the register space, then
882 the argument must overlap the register space. Return the first
883 available register. */
884 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
885 return gen_rtx_REG (HImode
, new_offset
/ 2);
887 /* Create a register of the required mode to hold the parameter. */
888 reg
= new_offset
/ 2;
903 return gen_rtx_REG (mode
, reg
);
907 /* Empty blockmode values can be passed as arguments (e.g.,
908 * empty structs). These require no registers
909 * whatsoever. Non-empty blockmode values are passed in a set
910 * of parallel registers. */
911 if (type_size_in_units
== 0)
914 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
919 (0, "Defaulting to stack for %s register creation\n",
920 GET_MODE_NAME (mode
));
928 /* Determine where the next incoming function argument will
929 appear. Normally, this works in exactly the same way as
930 picochip_function_arg, except when the function in question is a
931 varadic function. In this case, the incoming arguments all appear
932 to be passed on the stack (actually, some of the arguments are
933 passed in registers, which are then pushed onto the stack by the
934 function prologue). */
936 picochip_incoming_function_arg (CUMULATIVE_ARGS
*cum
,
937 enum machine_mode mode
,
938 const_tree type
, bool named
)
944 return picochip_function_arg (cum
, mode
, type
, named
);
948 /* Gives the alignment boundary, in bits, of an argument with the
951 picochip_get_function_arg_boundary (enum machine_mode mode
)
956 align
= STACK_BOUNDARY
;
958 align
= GET_MODE_ALIGNMENT (mode
);
960 if (align
< PARM_BOUNDARY
)
961 align
= PARM_BOUNDARY
;
967 /* Compute partial registers. */
969 picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
, enum machine_mode mode
,
970 tree type
, bool named ATTRIBUTE_UNUSED
)
972 int type_align_in_units
= 0;
973 int type_size_in_units
;
975 int offset_overflow
= 0;
977 unsigned cum
= *((unsigned *) p_cum
);
979 /* VOIDmode is passed when computing the second argument to a `call'
980 pattern. This can be ignored. */
981 if (mode
== VOIDmode
)
984 /* Compute the alignment and size of the parameter. */
985 type_align_in_units
=
986 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
987 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
989 /* Compute the correct offset (i.e., ensure that the offset meets
990 the alignment requirements). */
991 offset_overflow
= cum
% type_align_in_units
;
992 if (offset_overflow
== 0)
995 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
999 printf ("Partial function arg nregs:\n");
1000 printf (" Type valid: %s\n", (type
? "yes" : "no"));
1001 printf (" Cumulative Value: %d\n", cum
);
1002 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
1003 printf (" Type size: %i units\n", type_size_in_units
);
1004 printf (" Alignment: %i units\n", type_align_in_units
);
1005 printf (" New offset: %i\n", new_offset
);
1009 /* If the new offset is outside the register space, return. */
1010 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
1013 /* If the end of the argument is outside the register space, then
1014 the argument must overlap the register space. Return the number
1015 of bytes which are passed in registers. */
1016 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
1017 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
1023 /* Advance the cumulative args counter CUM. */
1025 picochip_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1026 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1028 int type_align_in_units
= 0;
1029 int type_size_in_units
;
1031 int offset_overflow
= 0;
1033 /* VOIDmode is passed when computing the second argument to a `call'
1034 pattern. This can be ignored. */
1035 if (mode
== VOIDmode
)
1038 /* Compute the alignment and size of the parameter. */
1039 type_align_in_units
=
1040 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
1041 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
1043 /* Compute the correct offset (i.e., ensure that the offset meets
1044 the alignment requirements). */
1045 offset_overflow
= *cum
% type_align_in_units
;
1046 if (offset_overflow
== 0)
1049 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
1051 /* Advance past the last argument. */
1052 new_offset
+= type_size_in_units
;
1057 /* Determine whether a register needs saving/restoring. It does if it
1058 is live in a function, and isn't a call-used register. */
1060 picochip_reg_needs_saving (int reg_num
)
1062 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
1065 /* Compute and return offset of the main frame. */
1067 picochip_frame_byte_offset (void)
1069 gcc_assert(picochip_is_aligned
1070 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
1072 return crtl
->outgoing_args_size
;
1075 /* Return the size of the main frame. */
1077 picochip_frame_size_in_bytes (void)
1079 int frame_size
= get_frame_size();
1080 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
1081 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
1082 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
1083 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
1087 /* Compute and return the size (in bytes) of the register save/restore
1088 area for the current function. This only includes the general
1089 purpose registers - the special purpose stack pointer and link
1090 registers are not included in this area. */
1092 picochip_save_area_size_in_bytes (void)
1094 int num_regs_to_save
= 0;
1097 /* Read through all the registers, determining which need to be saved. */
1098 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1100 if (picochip_reg_needs_saving (i
))
1101 num_regs_to_save
+= 1;
1104 return num_regs_to_save
* UNITS_PER_WORD
;
1108 /* Compute and return offset of the save area base. */
1110 picochip_save_area_byte_offset (void)
1112 int base_offset
= (picochip_frame_byte_offset () +
1113 picochip_frame_size_in_bytes ());
1115 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1121 /* Compute and return offset of the special register save area. This
1122 area can be found immediately above the normal save area. It must
1123 be aligned, to allow the registers to be saved and restored as a
1126 picochip_special_save_area_byte_offset (void)
1128 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1129 int offset
= (picochip_save_area_byte_offset () +
1130 picochip_save_area_size_in_bytes ());
1132 if ((offset
% byte_alignment
) != 0)
1133 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1139 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1141 picochip_can_eliminate_link_sp_save (void)
1143 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1144 changing during optimizations phases. So, this function returns different
1145 values when called from initial_elimination_offset and then again when it
1146 is called from prologue/epilogue generation. This means that argument
1147 accesses become wrong. This wouldnt happen only if we were not using the
1148 stack at all. The following conditions ensures that.*/
1150 return (current_function_is_leaf
&&
1151 !df_regs_ever_live_p(LINK_REGNUM
) &&
1152 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1153 (picochip_special_save_area_byte_offset() == 0) &&
1154 (crtl
->args
.size
== 0) &&
1155 (crtl
->args
.pretend_args_size
== 0));
1158 /* Compute the size of the special reg save area (SP and LNK). If the
1159 SP/LNK registers don't need to be saved, this area can shrink to
1162 picochip_special_save_area_size_in_bytes (void)
1166 if (picochip_can_eliminate_link_sp_save ())
1169 return 2 * UNITS_PER_WORD
;
1172 /* Return the number of pretend arguments. If this function is
1173 varadic, all the incoming arguments are effectively passed on the
1174 stack. If this function has real pretend arguments (caused by a
1175 value being passed partially on the stack and partially in
1176 registers), then return the number of registers used. */
1178 picochip_pretend_arg_area_size (void)
1181 if (crtl
->args
.pretend_args_size
!= 0)
1183 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1185 return crtl
->args
.pretend_args_size
;
1187 else if (cfun
->stdarg
)
1194 /* Compute and return the offset of the pretend arguments. The pretend
1195 arguments are contiguous with the incoming arguments, and must be
1196 correctly aligned. */
1198 picochip_pretend_arg_area_byte_offset (void)
1200 int base_offset
= 0;
1202 base_offset
= (picochip_special_save_area_byte_offset () +
1203 picochip_special_save_area_size_in_bytes ());
1205 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1206 gcc_assert(picochip_is_aligned
1207 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1213 /* Compute and return the offset of the incoming arguments. If a
1214 static chain is in use, this will be passed just before the other
1215 arguments. This means that the pretend argument mechanism, used in
1216 variadic functions, doesn't work properly. Thus, static chains work
1217 on their own, as do variadic functions, but not the combination of
1218 the two. This isn't really a problem. */
1220 picochip_arg_area_byte_offset (void)
1222 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1223 picochip_pretend_arg_area_size ());
1225 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1226 the alignment on a 32-bit boundary must be maintained. */
1227 if (cfun
->static_chain_decl
!= NULL
)
1229 gcc_assert (!cfun
->stdarg
);
1233 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1240 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, int mode
)
1243 /* Special case - only one register needed. */
1244 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1247 /* We actually do not allocate acc0 ever. But, it seems like we need to
1248 make it look like a allocatable register for the dataflow checks to work
1249 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1254 /* General case - compute how much space in terms of units. */
1255 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1260 picochip_class_max_nregs (int reg_class
, int mode
)
1262 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1264 if (reg_class
== ACC_REGS
)
1267 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1274 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1275 argument pointer) by replacing it with a constant offset from the
1276 main stack register. */
1278 initial_elimination_offset (int from
, int to
)
1280 int offset_from_sp
= 0;
1282 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1283 offset_from_sp
= picochip_frame_byte_offset ();
1284 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1285 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1289 return offset_from_sp
;
1293 /* Compute and return the size of the incoming argument area. */
1295 picochip_arg_area_size_in_bytes (void)
1297 return crtl
->args
.size
;
1300 /* Determine whether the given register is valid. When the strict mode
1301 is used, only hard registers are valid, otherwise any register is
1304 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1307 /* Sanity check - non-registers shouldn't make it here, but... */
1308 if (REG
!= GET_CODE (x
))
1312 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1318 /* Determine whether the given constant is in the range required for
1319 the given base register. */
1321 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1323 HOST_WIDE_INT corrected_offset
;
1325 if (GET_MODE_SIZE (mode
) != 0)
1327 if (GET_MODE_SIZE(mode
) <= 4)
1329 /* We used to allow incorrect offsets if strict is 0. But, this would
1330 then rely on reload doing the right thing. We have had problems
1331 there before, and on > 4.3 compiler, there are no benefits. */
1332 if (offset
% GET_MODE_SIZE (mode
) != 0)
1334 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1338 if (offset
% 4 != 0)
1340 corrected_offset
= offset
/ 4;
1345 /* Default to the byte offset as supplied. */
1346 corrected_offset
= offset
;
1349 /* The offset from the base register can be different depending upon
1350 the base register. The stack/frame/argument pointer offsets can
1351 all be greater than a simple register-based offset. Note that the
1352 frame/argument pointer registers are actually eliminations of the
1353 stack pointer, so a value which is valid for an offset to, for
1354 example, the frame pointer, might be invalid for the stack
1355 pointer once the elimination has occurred. However, there is no
1356 need to handle this special case here, as the stack offset is
1357 always checked after elimination anyway, and the generated code
1358 seems to have identical performance. */
1359 if (regno
== STACK_POINTER_REGNUM
||
1360 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1361 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1363 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1367 /* Determine whether a given rtx is a legitimate address for machine_mode
1368 MODE. STRICT is non-zero if we're being strict - any pseudo that
1369 is not a hard register must be a memory reference. */
1371 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1375 switch (GET_CODE (x
))
1378 valid
= picochip_legitimate_address_register (x
, strict
);
1383 rtx base
= XEXP (x
, 0);
1384 rtx offset
= XEXP (x
, 1);
1385 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1391 valid
= (REG
== GET_CODE (base
) &&
1392 picochip_legitimate_address_register (base
, strict
) &&
1393 CONST_INT
== GET_CODE (offset
) &&
1394 picochip_const_ok_for_base (mode
, REGNO (base
),
1400 /* The user can select whether a symbol can be used as a memory
1401 address. Typically, this will decrease execution time (no
1402 register load is required first), but will increase code size
1403 (because the symbol will be used several times, rather than
1404 loaded once into a register.*/
1405 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1410 /* A constant memory address must be a (plus (symbol_ref)
1411 (const_int)), and is only allowed when the symbols are
1412 permitted addresses. */
1413 rtx inner
= XEXP (x
, 0);
1415 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1416 PLUS
== GET_CODE (inner
) &&
1417 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1418 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1432 /* For all memory operations, picochip allows a uconst4 offset value. It
1433 is hence beneficial to turn an
1434 addr = <reg + long_const>
1439 X = reg + long_const & FFF0
1440 diff = long_const - (long_const & FFF0)
1443 X can be reused in subsequent memory operations.
1446 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1447 enum machine_mode mode
)
1454 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1470 if (GET_CODE (x
) == PLUS
1471 && GET_CODE (XEXP (x
, 0)) == REG
1472 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1474 int high_val
, low_val
, offset
;
1475 offset
= INTVAL (XEXP (x
, 1));
1476 /* Ignore cases with negative offsets. */
1479 high_val
= offset
& mask_val
;
1480 low_val
= offset
- high_val
;
1483 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1484 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1491 /* For all memory operations, picochip allows a uconst4 offset value. It
1492 is hence beneficial to turn an
1493 addr = <reg + long_const>
1498 X = reg + long_const & FFF0
1499 diff = long_const - (long_const & FFF0)
1502 X can be reused in subsequent memory operations.
1505 picochip_legitimize_reload_address (rtx
*x
,
1506 enum machine_mode mode
,
1507 int opnum
, int type
,
1508 int ind_levels ATTRIBUTE_UNUSED
)
1512 if (picochip_symbol_offset(*x
))
1514 *x
= gen_rtx_CONST(mode
, *x
);
1520 /* We should recognise addresses that we created.*/
1521 if (GET_CODE (*x
) == PLUS
1522 && GET_CODE (XEXP (*x
, 0)) == PLUS
1523 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1524 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1525 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1527 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1528 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1529 opnum
, (enum reload_type
)type
);
1533 /* Depending on mode, the offsets allowed are either 16/32/64. */
1549 if (GET_CODE (*x
) == PLUS
1550 && GET_CODE (XEXP (*x
, 0)) == REG
1551 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1553 int high_val
, low_val
, offset
;
1554 offset
= INTVAL (XEXP (*x
, 1));
1555 /* Ignore cases with negative offsets. */
1558 high_val
= offset
& mask_val
;
1559 low_val
= offset
- high_val
;
1562 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1563 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1564 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1565 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1566 opnum
, (enum reload_type
)type
);
1574 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1576 picochip_symbol_offset (rtx operand
)
1579 return (PLUS
== GET_CODE (operand
) &&
1580 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1581 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1585 /* Assembly output. */
1587 /* The format here should match the format used in the output of
1588 symbol_ref's elsewhere in this file. */
1590 picochip_output_label (FILE * stream
, const char name
[])
1592 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1594 /* If VLIW scheduling is in use, any Call Frame Information labels
1595 generated inside a packet must have their output deferred until
1596 the end of the packet. */
1597 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1598 is_cfi_label
&& picochip_vliw_continuation
)
1600 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1602 internal_error ("LCFI labels have already been deferred.");
1604 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1605 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1606 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1610 assemble_name (stream
, name
);
1612 if (strncmp (name
, "picoMark_", 9) == 0)
1613 fprintf (stream
, "=\n");
1615 fprintf (stream
, ":\n");
1621 /* The format here should match the format used in the output of
1622 symbol_ref's elsewhere in this file. */
1624 picochip_output_labelref (FILE * stream
, const char name
[])
1626 fprintf (stream
, "_%s", name
);
1630 picochip_weaken_label (FILE * stream
, const char name
[])
1632 fprintf (stream
, ".weak ");
1633 assemble_name (stream
, name
);
1634 fprintf (stream
, "\n");
1637 /* Return true if the given label (or label prefix) denotes a marker
1638 label which should be emitted in the form LABEL= */
1640 picochip_is_marker_prefix (const char *prefix
)
1642 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1643 && strcmp (prefix
, "LP") != 0);
1647 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1651 /* Emit different types of label, based upon their prefix. They
1652 are handled differently to allow the assembler to ensure that
1653 branch target labels are properly aligned, while other labels
1654 will only serve as code markers, not branch targets. Aligning
1655 labels unnecessarily can result in much code wastage. */
1656 if (picochip_is_marker_prefix (prefix
))
1658 /* Special label marker. If it appears in the middle of a VLIW
1659 packet, defer it until the end of the packet. There has
1660 never been a need to handle more than one lm label at a time. */
1661 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1662 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1664 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1665 internal_error ("LM label has already been deferred.");
1667 sprintf (picochip_current_vliw_state
.lm_label_name
,
1668 "picoMark_%s%ld", prefix
, num
);
1670 else if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1671 (strcmp (prefix
, "LCFI")) == 0 && picochip_vliw_continuation
)
1673 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1675 internal_error ("LCFI labels have already been deferred.");
1677 sprintf(picochip_current_vliw_state
.cfi_label_name
[
1678 picochip_current_vliw_state
.num_cfi_labels_deferred
],
1679 "picoMark_%s%ld", prefix
, num
);
1680 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1685 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1692 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1698 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1700 /* Two types of internal label can be generated: branch target
1701 labels and code marker labels. Branch target labels must always
1702 be aligned (since code will execute at these
1703 points). Differentiate between the two by prepending markers with
1704 a unique prefix, which can later be used in output_label to
1705 figure out which label syntax to use. */
1706 if (picochip_is_marker_prefix (prefix
))
1707 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1709 sprintf (str
, "%s%ld", prefix
, num
);
1714 picochip_asm_output_anchor (rtx symbol
)
1716 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1717 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1721 picochip_output_aligned_common (FILE * stream
, const char *name
,
1722 unsigned size
, unsigned alignment
)
1725 fprintf (stream
, ".commonData ");
1726 assemble_name (stream
, name
);
1727 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1728 picochip_output_global (stream
, name
);
1733 picochip_output_aligned_local (FILE * stream
, const char *name
,
1734 unsigned size
, unsigned alignment
)
1737 fprintf (stream
, ".commonData ");
1738 assemble_name (stream
, name
);
1739 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1744 picochip_output_global (FILE * stream
, const char *name
)
1746 fprintf (stream
, ".global ");
1747 assemble_name (stream
, name
);
1748 fprintf (stream
, "\n");
1751 /* Output an assembly language string. Output as a sequence of decimal
1752 numbers, followed by the literal string to make it obvious what the
1753 numbers represent. */
1755 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1759 fprintf (file
, ".ascii ");
1761 for (i
= 0; i
< length
; ++i
)
1763 fprintf (file
, "16#%x# ", (char) (str
[i
]));
1766 fprintf (file
, " ; ");
1768 for (i
= 0; i
< length
; ++i
)
1775 fprintf (file
, "\\n");
1778 fprintf (file
, "\\t");
1781 fprintf (file
, "\\0");
1784 fprintf (file
, "%c", c
);
1789 fprintf (file
, "\n");
1793 /* Output the beginning of an ASM file. */
1795 picochip_asm_file_start (void)
1797 default_file_start ();
1799 fprintf (asm_out_file
, "// picoChip ASM file\n");
1800 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1802 fprintf (asm_out_file
, "// Has byte access: %s\n",
1803 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1805 if (TARGET_HAS_MUL_UNIT
)
1806 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1807 else if (TARGET_HAS_MAC_UNIT
)
1808 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1810 fprintf (asm_out_file
, "// Has multiply: No\n");
1812 /* Variable tracking should be run after all optimizations which change order
1813 of insns. It also needs a valid CFG. This can't be done in
1814 picochip_option_override, because flag_var_tracking is finalized after
1816 picochip_flag_var_tracking
= flag_var_tracking
;
1817 flag_var_tracking
= 0;
1820 /* Output the end of an ASM file. */
1822 picochip_asm_file_end (void)
1824 /* Include a segment end to make it easy for PERL scripts to grab
1825 segments. This is now done by assembler*/
1827 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1831 /* Output frame debug information to the given stream. */
1833 picochip_output_frame_debug (FILE * file
)
1837 if (current_function_is_leaf
)
1838 fprintf (file
, "\t\t// Leaf function\n");
1840 fprintf (file
, "\t\t// Non-leaf function\n");
1842 if (picochip_can_eliminate_link_sp_save ())
1843 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1845 if (cfun
->static_chain_decl
!= NULL
)
1846 fprintf (file
, "\t\t// Static chain in use\n");
1848 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1849 picochip_arg_area_size_in_bytes ());
1850 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1851 picochip_arg_area_byte_offset ());
1852 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1853 picochip_pretend_arg_area_size ());
1854 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1855 picochip_pretend_arg_area_byte_offset ());
1856 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1857 picochip_special_save_area_size_in_bytes ());
1858 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1859 picochip_special_save_area_byte_offset ());
1861 /* Output which registers are saved. */
1862 fprintf (file
, "\t\t// Saved regs: ");
1863 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1865 if (picochip_reg_needs_saving (i
))
1866 fprintf (file
, "%s ", picochip_regnames
[i
]);
1868 fprintf (file
, "\t\t\n");
1870 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1871 picochip_save_area_size_in_bytes ());
1872 fprintf (file
, "\t\t// Save area offset: %d\n",
1873 picochip_save_area_byte_offset ());
1875 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1876 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1877 picochip_frame_byte_offset ());
1879 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1880 crtl
->outgoing_args_size
);
1884 /* Output picoChip function prologue. This contains human-readable
1885 information about the function. */
1887 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1889 /* Get the function's name, as described by its RTL. This may be
1890 different from the DECL_NAME name used in the source file. The
1891 real declaration name must be used, to ensure that the prologue
1892 emits the right information for the linker. */
1895 x
= DECL_RTL (current_function_decl
);
1896 gcc_assert (MEM_P (x
));
1898 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1899 fnname
= XSTR (x
, 0);
1901 /* Note that the name of the function is given in the &_%s
1902 form. This matches the name of the function as used in labels,
1903 and function calls, and enables processCallGraph to match
1904 function calls to the name of the function, as defined here. */
1905 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1906 fnname
, picochip_arg_area_byte_offset ());
1908 picochip_output_frame_debug (file
);
1909 fprintf (file
, "\n");
1913 /* Output picoChip function epilogue. */
1915 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1920 x
= DECL_RTL (current_function_decl
);
1921 gcc_assert (MEM_P (x
));
1923 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1924 fnname
= XSTR (x
, 0);
1925 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1929 /* Manipulate the asm output. Some machines only execute the code when
1930 there is actually a chance of needing it (e.g., FRV doesn't execute
1931 it if the scheduling pass wasn't used). We always execute it,
1932 simple to ensure that it is exercised more often, and bugs are more
1935 This function's prime reason for existence is to insert the VLIW
1936 separators where appropriate. The separators must be inserted
1937 before any comments which appear at the end of the file.
1941 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1945 /* Flag to specify when a VLIW continuation has been inserted onto
1946 the line. Continuations are either inserted before any comments,
1947 or before the end of the line is reached. The flag ensures that
1948 we don't insert continuations twice (i.e., at the comment and the
1950 int continuation_inserted
= 0;
1952 /* If the instruction uses multiple lines (i.e., a new line
1953 character appears in the opcode), then ensure that no attempt is
1954 made to pack it into a VLIW. */
1955 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1957 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1961 /* If a delay slot is pending, output the directive to the assembler
1962 before the instruction. */
1963 if (picochip_is_delay_slot_pending
)
1965 picochip_is_delay_slot_pending
= 0;
1969 /* Keep going for entire opcode. All substitution performed ourselves. */
1974 /* Determine whether a VLIW continuation must be inserted before
1975 any comments, or the end of the opcode. A flag is set to show
1976 that we have inserted a continuation on this line, so that we
1977 don't try to insert another continuation when the end of the
1978 opcode is reached. The only other case for a continuation
1979 might have been a newline, but these aren't allowed in
1980 conjunction with VLIW continuations (see above code). */
1981 if (picochip_vliw_continuation
&&
1982 !continuation_inserted
&&
1983 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1986 continuation_inserted
= 1;
1989 /* Detect an explicit VLIW separator. */
1990 if (c
== '%' && (*ptr
== '|'))
1995 /* Detect the need for an ALU id operand. */
1996 else if (c
== '%' && (*ptr
== '#'))
1998 fputc (picochip_get_vliw_alu_id (), f
);
2001 printf ("Generated ALU char at %s for insn %d\n", ptr
,
2002 INSN_UID (picochip_current_prescan_insn
));
2004 /* Skip past unwanted # */
2007 /* Detect the need for branch delay slot. */
2008 else if (c
== '%' && (*ptr
== '>'))
2010 /* Only emit delay slots (NOP's, or otherwise) when delay
2011 * slot scheduling has actually been enabled, otherwise VLIW
2012 * scheduling and delay slot scheduling output combine to
2013 * produce nasty effects. */
2014 if (flag_delayed_branch
)
2016 if (dbr_sequence_length () == 0)
2017 fputs ("\n=->\tNOP", f
);
2019 picochip_is_delay_slot_pending
= 1;
2022 /* Skip past unwanted > */
2025 /* Detect any %digit specifiers. */
2026 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
2029 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
2030 while ((c
= *ptr
) >= '0' && c
<= '9')
2033 /* Detect any %letterdigit specifiers. */
2034 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2035 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2037 int letter
= *ptr
++;
2044 output_asm_label (recog_data
.operand
[c
]);
2048 output_address (recog_data
.operand
[c
]);
2052 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
2055 while ((c
= *ptr
) >= '0' && c
<= '9')
2060 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
2066 /* Reached the end of the packet. If any labels were deferred
2067 during output, emit them now. */
2068 if (!picochip_vliw_continuation
)
2070 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
2073 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
2075 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
2078 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
2083 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
2086 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
2091 /* Output an end-of-packet marker if requested. */
2092 if (!picochip_vliw_continuation
&&
2093 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
2094 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
2099 /* Function RTL expansion. */
2101 /* Expand the prologue into RTL. */
2103 picochip_expand_prologue (void)
2105 int stack_adjustment
= 0;
2106 int special_save_offset
= 0;
2107 int general_save_offset
= 0;
2108 int reg_save_offset
= 0;
2111 stack_adjustment
= picochip_arg_area_byte_offset ();
2112 general_save_offset
=
2113 -(stack_adjustment
- picochip_save_area_byte_offset ());
2114 special_save_offset
=
2115 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2117 /* Save the link registers. We could try to save just one register
2118 here. This would reduce the amount of stack space required.
2119 There hasnt been a good reason to do that so far. */
2120 if (!picochip_can_eliminate_link_sp_save ())
2121 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2122 special_save_offset
);
2124 /* Save callee-save registers. */
2125 reg_save_offset
= 0;
2126 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2128 if (picochip_reg_needs_saving (i
))
2131 /* If this register is an even numbered register, and the
2132 next register also needs to be saved, use a SImode save,
2133 which does both in one instruction. Note that a special
2134 check is performed to ensure that the double word aligned
2135 store is valid (e.g., it is possible that r6, r8, r9 need
2136 to be saved, in which case once r6 has been saved, the
2137 stored offset is no longer aligned, and an STL/LDL
2138 instruction becomes invalid). Alternately, we could store all
2139 aligned registers first and then save the single one(s). */
2141 picochip_reg_needs_saving (i
+ 1) &&
2142 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2144 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2145 general_save_offset
+
2147 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2152 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2153 general_save_offset
+
2155 reg_save_offset
+= UNITS_PER_WORD
;
2161 /* Emit a stack adjustment where required. */
2162 if (stack_adjustment
!= 0)
2163 picochip_emit_stack_allocate (stack_adjustment
);
2165 /* If this function uses varadic arguments, write any unnamed
2166 registers to the stack. */
2169 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2171 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2172 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2174 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2175 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2177 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2184 /* Expand the epilogue into RTL. */
2186 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2188 int stack_adjustment
= 0;
2189 int special_save_offset
= 0;
2190 int general_save_offset
= 0;
2191 int reg_save_offset
= 0;
2193 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2196 stack_adjustment
= picochip_arg_area_byte_offset ();
2197 general_save_offset
=
2198 -(stack_adjustment
- picochip_save_area_byte_offset ());
2199 special_save_offset
=
2200 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2202 /* Emit a stack adjustment where required. */
2203 if (stack_adjustment
!= 0)
2205 /* If the link/fp is already being restored, and the offset to
2206 their save location is small enough, don't bother adjusting
2207 the stack explicitly. */
2208 if (picochip_special_save_area_byte_offset () < 512 &&
2209 !picochip_can_eliminate_link_sp_save ())
2210 use_link_fp_restore_stack_adjust
= 1;
2212 /* Explicitly restore the stack. */
2213 picochip_emit_stack_allocate (-stack_adjustment
);
2216 /* Restore the Link/FP registers. Only save the link register? */
2217 if (!picochip_can_eliminate_link_sp_save ())
2219 if (use_link_fp_restore_stack_adjust
)
2220 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2221 picochip_special_save_area_byte_offset
2224 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2225 special_save_offset
);
2228 /* Restore callee-save registers. */
2229 reg_save_offset
= 0;
2230 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2232 if (picochip_reg_needs_saving (i
))
2235 /* If this register is an even numbered register, and the
2236 next register also needs to be saved, use a SImode save,
2237 which does both in one instruction. Note that a special
2238 check is performed to ensure that the double word aligned
2239 store is valid (e.g., it is possible that r6, r8, r9 need
2240 to be saved, in which case once r6 has been saved, the
2241 stored offset is no longer aligned, and an STL/LDL
2242 instruction becomes invalid). We could store all aligned
2243 registers first, and then save the single one(s). */
2245 picochip_reg_needs_saving (i
+ 1) &&
2246 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2248 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2249 general_save_offset
+
2251 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2256 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2257 general_save_offset
+
2259 reg_save_offset
+= UNITS_PER_WORD
;
2265 /* Emit a return instruction, which matches a (parallel
2266 [(return) (use r12)]) */
2269 p
= rtvec_alloc (2);
2271 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
2272 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2273 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2274 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2279 /* Assembly instruction output. */
2281 /* Test whether the given branch instruction is short, or long. Short
2282 * branches are equivalent to real branches, and may be DFA
2283 * scheduled. Long branches expand to a macro which is handled by the
2284 * elaborator, and cannot be scheduled. Occasionally, the branch
2285 * shortening pass, which is run after DFA scheduling, will change the
2286 * code layout and cause the short branch to be reverted into a long
2287 * branch. Instead of having to fix this up by emitting new assembly,
2288 * the short branch is emitted anyway. There is plenty of slack in the
2289 * calculation of long and short branches (10-bit offset, but only
2290 * 9-bits used in computation), so there is enough slack for this to
2293 picochip_is_short_branch (rtx insn
)
2295 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2297 return (isRealShortBranch
||
2298 picochip_current_vliw_state
.num_insns_in_packet
> 1);
2301 /* Output a compare-and-branch instruction (matching the cbranch
2304 picochip_output_cbranch (rtx operands
[])
2307 if (HImode
!= GET_MODE (operands
[1]) ||
2308 (HImode
!= GET_MODE (operands
[2]) &&
2309 GET_CODE (operands
[2]) != CONST_INT
))
2311 internal_error ("%s: At least one operand can't be handled",
2315 /* Use the type of comparison to output the appropriate condition
2317 switch (GET_CODE (operands
[0]))
2320 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2323 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2326 /* Reverse the operand order to be GE */
2327 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2330 /* Reverse operand order of GEU. */
2331 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2334 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2337 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2340 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2343 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2346 /* Reversed operand version of LT. */
2347 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2350 /* Reverse an LTU. */
2351 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2358 /* Output a compare-and-branch instruction (matching the cbranch
2359 pattern). This function is current unused since the cbranch
2360 split is disabled. The function is kept around so we can use
2361 it when we understand how to do cbranch split safely. */
2363 picochip_output_compare (rtx operands
[])
2367 if (HImode
!= GET_MODE (operands
[1]) ||
2368 (HImode
!= GET_MODE (operands
[2]) &&
2369 GET_CODE (operands
[2]) != CONST_INT
))
2371 internal_error ("%s: At least one operand can't be handled",
2375 code
= GET_CODE (operands
[0]);
2376 /* Use the type of comparison to output the appropriate condition
2381 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2384 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2387 /* Reverse the operand order to be GE */
2388 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2391 /* Reverse operand order of GEU. */
2392 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2395 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2398 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2401 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2404 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2407 /* Reversed operand version of LT. */
2408 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2411 /* Reverse an LTU. */
2412 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2419 /* Output the branch insn part of a compare-and-branch split. */
2421 picochip_output_branch (rtx operands
[], rtx insn
)
2424 int code
= GET_CODE(operands
[2]);
2425 if (picochip_is_short_branch (insn
))
2427 /* Short branches can be output directly using the
2428 appropriate instruction. */
2432 return ("BNE %l0 %>");
2434 return ("BEQ %l0 %>");
2436 return ("BGE %l0 %>");
2438 return ("BHS %l0 %>");
2440 return ("BGE %l0 %>");
2442 return ("BHS %l0 %>");
2444 return ("BLT %l0 %>");
2446 return ("BLO %l0 %>");
2448 return ("BLT %l0 %>");
2450 return ("BLO %l0 %>");
2452 internal_error ("Unknown short branch in %s (type %d)\n",
2453 __FUNCTION__
, (int) INTVAL (operands
[1]));
2454 return "UNKNOWN_BRANCH";
2459 /* Long branches result in the emission of a special
2460 instruction, which the assembler expands into a suitable long
2463 /* Use the type of comparison to output the appropriate condition
2468 return ("JMPNE %l0 %>");
2470 return ("JMPEQ %l0 %>");
2472 return ("JMPGE %l0 %>");
2474 return ("JMPHS %l0 %>");
2476 return ("JMPGE %l0 %>");
2478 return ("JMPHS %l0 %>");
2480 return ("JMPLT %l0 %>");
2482 return ("JMPLO %l0 %>");
2484 return ("JMPLT %l0 %>");
2486 return ("JMPLO %l0 %>");
2489 internal_error ("Unknown long branch in %s (type %d)\n",
2490 __FUNCTION__
, (int) INTVAL (operands
[1]));
2491 return "UNKNOWN_BRANCH";
2497 /* Output a jump instruction. */
2499 picochip_output_jump (rtx insn
)
2501 if (picochip_is_short_branch (insn
))
2504 return "JMPRA %l0%>";
2508 picochip_output_put_array (int alternative
, rtx operands
[])
2510 /* Local output buffer. */
2513 int portArraySize
= INTVAL(operands
[1]);
2514 int portBaseIndex
= INTVAL(operands
[2]);
2516 if (alternative
== 0)
2518 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2519 portArraySize
, portBaseIndex
);
2520 output_asm_insn (buf
, operands
);
2522 else if (alternative
== 1)
2524 /* Constant port id. Emit a real instruction. */
2525 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2526 if (portIndex
< portBaseIndex
||
2527 portIndex
>= (portBaseIndex
+ portArraySize
))
2529 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2530 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2532 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2533 output_asm_insn (buf
, operands
);
2538 /* Both alternatives output the insn directly. */
2542 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2544 /* Local output buffer. */
2547 int portArraySize
= INTVAL(operands
[1]);
2548 int portBaseIndex
= INTVAL(operands
[2]);
2550 if (alternative
== 0)
2552 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2553 portArraySize
, portBaseIndex
);
2554 output_asm_insn (buf
, operands
);
2556 else if (alternative
== 1)
2558 /* Constant port id. Emit a real instruction. */
2559 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2560 if (portIndex
< portBaseIndex
||
2561 portIndex
>= (portBaseIndex
+ portArraySize
))
2563 error ("GET uses port array index %d, which is out of range [%d..%d)",
2564 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2566 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2567 output_asm_insn (buf
, operands
);
2572 /* Both alternatives output the insn directly. */
2576 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2578 /* Local output buffer. */
2581 int portArraySize
= INTVAL(operands
[2]);
2582 int portBaseIndex
= INTVAL(operands
[3]);
2584 if (alternative
== 0)
2586 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2587 portArraySize
, portBaseIndex
);
2588 output_asm_insn (buf
, operands
);
2590 else if (alternative
== 1)
2592 /* Constant port id. Emit a real instruction. */
2593 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2594 if (portIndex
< portBaseIndex
||
2595 portIndex
>= (portBaseIndex
+ portArraySize
))
2597 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2598 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2600 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2601 output_asm_insn (buf
, operands
);
2606 /* Both alternatives output the insn directly. */
2610 /* Output a comparison operand as a symbol (e.g., >). */
2612 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2617 /* Output just the comparison symbol. */
2618 switch (GET_CODE (operand
))
2621 fprintf (file
, "!=");
2624 fprintf (file
, "==");
2627 fprintf (file
, ">=");
2630 fprintf (file
, ">={U}");
2633 fprintf (file
, "<");
2636 fprintf (file
, "<{U}");
2639 fprintf (file
, "<=");
2642 fprintf (file
, "<={U}");
2645 fprintf (file
, ">");
2648 fprintf (file
, ">{U}");
2656 /* Output the comparison formatted as operand,symbol,operand */
2657 rtx op0
= XEXP (operand
, 0);
2658 rtx op1
= XEXP (operand
, 1);
2660 picochip_print_operand (file
, op0
, 0);
2661 picochip_print_comparison (file
, operand
, 'i');
2662 picochip_print_operand (file
, op1
, 0);
2666 /* This function generates a memory address operand in the given
2667 mode. That is, if the address contains a constant offset, then the
2668 offset is divided by the required mode size to compute the
2669 mode specific offset. By default, picochip_print_operand_address calls
2670 this function using the natural mode of the operand, but special
2671 operand codes can be used to invoke the computation using an
2672 unnatural mode (e.g., compute the HI aligned address of an SI mode
2675 picochip_print_memory_address (FILE * file
, rtx operand
,
2676 enum machine_mode mode
)
2678 rtx address
= XEXP (operand
, 0);
2681 if (MEM
!= GET_CODE (operand
))
2682 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2687 printf ("picochip_print_memory_address: ");
2688 print_rtl (stdout
, operand
);
2692 switch (GET_CODE (address
))
2696 /* Grab the address components. */
2697 rtx base
= XEXP (address
, 0);
2698 rtx offset
= XEXP (address
, 1);
2700 /* Only handle reg+const addresses */
2701 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2703 /* Sanity check. If an FP+offset address is given, ensure
2704 that the offset lies within the given frame, or a lower
2706 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2707 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2710 /* Print the base register - identical for all modes. */
2711 fprintf (file
, "(");
2712 picochip_print_operand (file
, base
, 'r');
2713 fprintf (file
, ")");
2715 /* Print the constant offset with compensation for the mode. */
2719 picochip_print_operand (file
, offset
, 'Q');
2723 picochip_print_operand (file
, offset
, 'H');
2728 picochip_print_operand (file
, offset
, 'S');
2732 picochip_print_operand (file
, offset
, 'D');
2746 picochip_print_operand (file
, address
, 's');
2755 inner
= XEXP (address
, 0);
2757 /* Sanity check - the CONST memory address must be a base+offset. */
2758 gcc_assert (PLUS
== GET_CODE (inner
));
2760 base
= XEXP (inner
, 0);
2761 offset
= XEXP (inner
, 1);
2763 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2769 /* Register operand. Provide a zero offset. */
2770 fprintf (file
, "(");
2771 picochip_print_operand (file
, address
, 'r');
2772 fprintf (file
, ")0");
2781 /* Output an operand. Formatting letters allow particular parts of
2782 the operand to be output. */
2784 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2787 /* Handle special cases. */
2790 /* VLIW continuation, for explicit VLIW sequences. */
2792 fprintf (file
, "\\");
2797 fputc (picochip_get_vliw_alu_id (), file
);
2800 /* Delay slot specifier. */
2802 /* This should be handled in asm_output_opcode. */
2805 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2807 switch (GET_CODE (operand
))
2810 fprintf (file
, "AND");
2813 fprintf (file
, "OR");
2816 fprintf (file
, "XOR");
2819 fprintf (file
, "ADD");
2822 fprintf (file
, "SUB");
2829 /* Symbolic instructions (e.g., lshift becomes <<). */
2831 switch (GET_CODE (operand
))
2834 fprintf (file
, "&");
2837 fprintf (file
, "|");
2840 fprintf (file
, "^");
2843 fprintf (file
, "+");
2846 fprintf (file
, "-");
2849 fprintf (file
, "UNKNOWN_INSN");
2854 default: /* Not a punctuation character - process as normal. */
2858 switch (GET_CODE (operand
))
2864 /* Write a range of registers. */
2865 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2869 /* The upper register of a pair is requested. */
2870 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2874 /* The lower register of a pair is requested. Equivalent to the
2875 default, but included for completeness. */
2876 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2880 /* The 3rd register of a DI mode register. */
2881 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2885 /* The 4th register of a DI mode register. */
2886 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2890 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2895 /* A range of letters can be used to format integers. The
2896 letters Q/H/S are used to divide the constant by the width of
2897 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2898 to obtain the upper and lower 16-bits of a 32-bit
2899 constant. Where possible, signed numbers are used, since
2900 signed representations of numbers may be more compact (e.g.,
2901 65535 can be represented as -1, which fits into a small
2902 constant, whereas 65535 requires a large constant). */
2906 fprintf (file
, "%ld", INTVAL (operand
));
2910 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2914 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2918 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2922 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2926 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2930 fprintf (file
, "%ld", INTVAL (operand
));
2940 if (GET_MODE (operand
) != SFmode
)
2941 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2943 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2944 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2949 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2953 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2961 /* Output a symbol. The output format must match that of
2962 picochip_output_label. */
2964 /* Ensure that the symbol is marked as referenced. Gcc can
2965 occasionally omit the function bodies when it believes them
2966 to be unreferenced. */
2967 if (SYMBOL_REF_DECL (operand
))
2968 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2969 fprintf (file
, "&");
2970 assemble_name (file
, XSTR (operand
, 0));
2974 /* This format must match that of picochip_output_label. */
2975 fprintf (file
, "&");
2976 output_asm_label (operand
);
2981 rtx addr
= XEXP (operand
, 0);
2986 if (PLUS
!= GET_CODE (addr
))
2987 fatal_insn ("Bad address, not (reg+disp):", addr
);
2989 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2993 /* Output a memory address in byte mode notation (i.e., the
2994 constant address (if any) is the actual byte address. */
2995 picochip_print_memory_address (file
, operand
, QImode
);
2998 /* Output a constant offset of the given mode (i.e., divide
2999 the constant by the number of units in the mode to get the
3002 picochip_print_memory_address (file
, operand
, QImode
);
3006 picochip_print_memory_address (file
, operand
, HImode
);
3010 picochip_print_memory_address (file
, operand
, SImode
);
3014 picochip_print_memory_address (file
, operand
, SFmode
);
3018 if (PLUS
!= GET_CODE (addr
))
3019 fatal_insn ("Bad address, not (reg+disp):", addr
);
3021 picochip_print_operand (file
, XEXP (addr
, 0), 0);
3024 /* When the mem operand is (reg + big offset) which cannot
3025 be represented in an instruction as operand, the compiler
3026 automatically generates the instruction to put in (reg +
3027 big offset) into another register. In such cases, it
3028 returns '0' as the character. This needs to be handled
3032 if (REG
!= GET_CODE (addr
))
3033 fatal_insn ("Bad address, not register:", addr
);
3035 picochip_print_operand (file
, addr
, 0);
3039 fprintf (file
, "Unknown mem operand - letter %c ",
3041 print_rtl (file
, operand
);
3049 rtx const_exp
= XEXP (operand
, 0);
3051 /* Handle constant offsets to symbol references. */
3052 if (PLUS
== GET_CODE (const_exp
) &&
3053 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
3054 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
3057 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
3058 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
3059 fprintf (file
, "+");
3060 /* else use the - from the operand (i.e., AP-2)) */
3062 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
3071 /* PLUS expressions are of the form (base + offset). Different
3072 options (analagous to those of memory PLUS expressions) are used
3073 to extract the base and offset components. */
3078 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3082 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3087 /* If the expression is composed entirely of constants,
3088 evaluate the result. This should only occur with the
3089 picoChip specific comms instructions, which are emitted as
3090 base+offset expressions. */
3091 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
3092 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
3094 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
3095 XINT (XEXP (operand
, 1), 0));
3096 fprintf (file
, "%ld", result
);
3100 fprintf (file
, "(");
3101 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3102 fprintf (file
, "+");
3103 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3104 fprintf (file
, ")");
3111 /* Comparison operations. */
3122 picochip_print_comparison (file
, operand
, letter
);
3126 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3127 print_rtl (file
, operand
);
3134 /* Output an operand address */
3136 picochip_print_operand_address (FILE * file
, rtx operand
)
3139 switch (GET_CODE (operand
))
3143 /* This format must match that of picochip_output_label. */
3144 assemble_name (file
, XSTR (operand
, 0));
3148 /* Note this format must match that of picochip_output_label. */
3149 fprintf (file
, "_L%d", XINT (operand
, 5));
3153 /* Pass on to a specialised memory address generator. */
3154 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3165 /* Scheduling functions. */
3167 /* Save some of the contents of recog_data. */
3169 picochip_save_recog_data (void)
3171 picochip_saved_which_alternative
= which_alternative
;
3172 memcpy (&picochip_saved_recog_data
, &recog_data
,
3173 sizeof (struct recog_data
));
3176 /* Restore some of the contents of global variable recog_data. */
3178 picochip_restore_recog_data (void)
3180 which_alternative
= picochip_saved_which_alternative
;
3181 memcpy (&recog_data
, &picochip_saved_recog_data
,
3182 sizeof (struct recog_data
));
3185 /* Ensure that no var tracking notes are emitted in the middle of a
3186 three-instruction bundle. */
3188 reorder_var_tracking_notes (void)
3194 rtx insn
, next
, last_insn
= NULL_RTX
;
3195 rtx queue
= NULL_RTX
;
3197 /* Iterate through the bb and find the last non-debug insn */
3198 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= NEXT_INSN(insn
))
3200 if (NONDEBUG_INSN_P(insn
))
3204 /* In all normal cases, queue up notes and emit them just before a TImode
3205 instruction. For the last instruction, emit the queued notes just after
3206 the last instruction. */
3207 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= next
)
3209 next
= NEXT_INSN (insn
);
3211 if (insn
== last_insn
)
3215 rtx next_queue
= PREV_INSN (queue
);
3216 PREV_INSN (NEXT_INSN(insn
)) = queue
;
3217 NEXT_INSN(queue
) = NEXT_INSN(insn
);
3218 PREV_INSN(queue
) = insn
;
3219 NEXT_INSN(insn
) = queue
;
3222 /* There is no more to do for this bb. break*/
3225 else if (NONDEBUG_INSN_P (insn
))
3227 /* Emit queued up notes before the first instruction of a bundle. */
3228 if (GET_MODE (insn
) == TImode
)
3232 rtx next_queue
= PREV_INSN (queue
);
3233 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3234 PREV_INSN (queue
) = PREV_INSN(insn
);
3235 PREV_INSN (insn
) = queue
;
3236 NEXT_INSN (queue
) = insn
;
3241 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
3243 rtx prev
= PREV_INSN (insn
);
3244 PREV_INSN (next
) = prev
;
3245 NEXT_INSN (prev
) = next
;
3246 PREV_INSN (insn
) = queue
;
3250 /* Make sure we are not dropping debug instructions.*/
3251 gcc_assert (queue
== NULL_RTX
);
3255 /* Perform machine dependent operations on the rtl chain INSNS. */
3257 picochip_reorg (void)
3259 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3260 int vliw_insn_location
= 0;
3262 /* We are freeing block_for_insn in the toplev to keep compatibility
3263 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3264 compute_bb_for_insn ();
3269 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3271 timevar_push (TV_SCHED2
);
3273 /* Process the instruction list, computing the sizes of each
3274 instruction, and consequently branch distances. This can
3275 result in some branches becoming short enough to be treated
3276 as a real branch instruction, rather than an assembly branch
3277 macro which may expand into multiple instructions. The
3278 benefit of shortening branches is that real branch
3279 instructions can be properly DFA scheduled, whereas macro
3281 shorten_branches (get_insns ());
3283 /* Do control and data sched analysis again,
3284 and write some more of the results to dump file. */
3290 timevar_pop (TV_SCHED2
);
3294 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3296 /* Whenever a VLIW packet is generated, all instructions in
3297 that packet must appear to come from the same source
3298 location. The following code finds all the VLIW packets,
3299 and tags their instructions with the location of the first
3300 instruction from the packet. Clearly this will result in
3301 strange behaviour when debugging the code, but since
3302 debugging and optimisation are being used in conjunction,
3303 strange behaviour is certain to occur anyway. */
3304 /* Slight bit of change. If the vliw set contains a branch
3305 or call instruction, we pick its location.*/
3306 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3309 /* If this is the first instruction in the VLIW packet,
3310 extract its location. */
3311 if (GET_MODE (insn
) == TImode
)
3314 vliw_insn_location
= INSN_LOCATOR (insn
);
3316 if (JUMP_P (insn
) || CALL_P(insn
))
3318 vliw_insn_location
= INSN_LOCATOR (insn
);
3319 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3320 INSN_LOCATOR (insn1
) = vliw_insn_location
;
3322 /* Tag subsequent instructions with the same location. */
3323 INSN_LOCATOR (insn
) = vliw_insn_location
;
3329 /* Locate the note marking the end of the function's prologue. If
3330 the note appears in the middle of a VLIW packet, move the note to
3331 the end. This avoids unpleasant consequences such as trying to
3332 emit prologue markers (e.g., .loc/.file directives) in the middle
3334 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3336 rtx prologue_end_note
= NULL
;
3337 rtx last_insn_in_packet
= NULL
;
3339 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3341 /* The prologue end must be moved to the end of the VLIW packet. */
3342 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3344 prologue_end_note
= insn
;
3349 /* Find the last instruction in this packet. */
3350 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3352 if (GET_MODE (insn
) == TImode
)
3355 last_insn_in_packet
= insn
;
3358 if (last_insn_in_packet
!= NULL
)
3361 = emit_note_after ((enum insn_note
) NOTE_KIND (prologue_end_note
),
3362 last_insn_in_packet
);
3363 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3364 delete_insn (prologue_end_note
);
3367 if (picochip_flag_var_tracking
)
3369 timevar_push (TV_VAR_TRACKING
);
3370 variable_tracking_main ();
3371 /* We also have to deal with variable tracking notes in the middle
3373 reorder_var_tracking_notes();
3374 timevar_pop (TV_VAR_TRACKING
);
3378 /* Return the ALU character identifier for the current
3379 instruction. This will be 0 or 1. */
3381 picochip_get_vliw_alu_id (void)
3385 /* Always use ALU 0 if VLIW scheduling is disabled. */
3386 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3389 /* Get the attribute type of the instruction. Note that this can
3390 ruin the contents of recog_data, so save/restore around the
3392 picochip_save_recog_data ();
3393 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3394 picochip_restore_recog_data ();
3396 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3399 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3400 else it must be the other ALU (either basic or nonCc)
3401 instruction which goes into 1. */
3402 if (attr_type
== TYPE_PICOALU
)
3408 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3410 /* Is this the non CC instruction? If it is, then stuff it into
3411 ALU 1, else it must be a picoAlu or basicAlu, in which case
3412 it goes into ALU 0. */
3413 if (attr_type
== TYPE_NONCCALU
)
3420 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3421 whether an ALU instruction has already been scheduled in this
3423 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3426 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3430 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3434 internal_error ("Too many ALU instructions emitted (%d)\n",
3435 picochip_current_vliw_state
.num_alu_insns_so_far
);
3442 /* Reset any information about the current VLIW packing status. */
3444 picochip_reset_vliw (rtx insn
)
3446 rtx local_insn
= insn
;
3448 /* Nothing to do if VLIW scheduling isn't being used. */
3449 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3453 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3456 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3457 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3458 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3459 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3460 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3461 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3463 /* Read through the VLIW packet, classifying the instructions where
3468 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3470 local_insn
= NEXT_INSN (local_insn
);
3473 else if (!INSN_P (local_insn
))
3477 /* It is an instruction, but is it ours? */
3478 if (INSN_CODE (local_insn
) != -1)
3482 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3484 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3485 get_attr_type function can overwrite the values in
3486 the recog_data global, hence this is saved and
3487 restored around the call. Not doing so results in
3488 asm_output_opcode being called with a different
3489 instruction to final_prescan_insn, which is fatal. */
3490 picochip_save_recog_data ();
3491 attr_type
= get_attr_type (local_insn
);
3492 picochip_restore_recog_data ();
3494 if (attr_type
== TYPE_PICOALU
)
3495 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3496 if (attr_type
== TYPE_NONCCALU
)
3497 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3502 /* Get the next instruction. */
3503 local_insn
= NEXT_INSN (local_insn
);
3505 /* Keep going while the next instruction is part of the same
3506 VLIW packet (i.e., its a valid instruction and doesn't mark
3507 the start of a new VLIW packet. */
3509 while (local_insn
&&
3510 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3515 picochip_sched_reorder (FILE * file
, int verbose
,
3516 rtx
* ready ATTRIBUTE_UNUSED
,
3517 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3521 fprintf (file
, ";;\tClock %d\n", clock
);
3523 return picochip_sched_issue_rate ();
3528 picochip_sched_lookahead (void)
3530 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3536 picochip_sched_issue_rate (void)
3541 /* Adjust the scheduling cost between the two given instructions,
3542 which have the given dependency. */
3544 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3549 printf ("Sched Adjust Cost: %d->%d is %d\n",
3550 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3552 printf (" Dependency type:");
3553 switch (REG_NOTE_KIND (link
))
3561 case REG_DEP_OUTPUT
:
3562 printf ("OUTPUT\n");
3565 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3569 /* Anti-dependencies are used to enforce the ordering between a
3570 * branch, and any subsequent instructions. For example:
3575 * The ADD instruction must execute after the branch, and this is
3576 * enforced using an anti-dependency. Unfortunately, VLIW machines
3577 * are happy to execute anti-dependent instructions in the same
3578 * cycle, which then results in a schedule like the following being
3581 * BNE someLabel \ ADD.0 r0,r1,r2
3583 * The instruction which would normally be conditionally executed
3584 * depending upon the outcome of the branch, is now unconditionally
3585 * executed every time. To prevent this happening, any
3586 * anti-dependencies between a branch and another instruction are
3587 * promoted to become real dependencies.
3589 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3593 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3594 INSN_UID (insn
), INSN_UID (dep_insn
));
3603 /* Return the minimum of the two values */
3605 minimum (int a
, int b
)
3611 /* I dont expect to get to this function with a==b.*/
3616 /* This function checks if the memory of the two stores are just off by 2 bytes.
3617 It returns the lower memory operand's index.*/
3620 memory_just_off (rtx opnd1
, rtx opnd2
)
3622 int offset1
= 0, offset2
= 0;
3625 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3627 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3628 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3632 reg1
= REGNO(XEXP(opnd1
, 0));
3634 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3636 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3637 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3641 reg2
= REGNO(XEXP(opnd2
, 0));
3644 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3645 should be 4 byte aligned. We can currently guarentee that only if the base
3646 address is FP(R13) and the offset is aligned. */
3648 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3649 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3655 registers_just_off (rtx opnd1
, rtx opnd2
)
3658 reg1
= REGNO(opnd1
);
3659 reg2
= REGNO(opnd2
);
3660 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3661 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3665 /* Check to see if the two LDWs can be peepholed together into a LDL
3666 They can be if the registers getting loaded into are contiguous
3667 and the memory addresses are contiguous as well.
3671 can be merged together into
3675 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3676 aligned address. Only FP can be assumed to be 4 byte aligned.
3677 2. The progression of addresses and the register numbers should
3678 be similar. For eg., if you swap r2 and r3 in the above instructions,
3679 the resultant pair cannot be merged.
3683 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3685 int memtest
=0,regtest
=0;
3686 regtest
= registers_just_off(opnd1
,opnd3
);
3690 memtest
= memory_just_off(opnd0
,opnd2
);
3694 if (regtest
== memtest
)
3701 /* Similar to LDW peephole */
3703 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3705 int memtest
=0,regtest
=0;
3706 regtest
= registers_just_off(opnd1
,opnd3
);
3710 memtest
= memory_just_off(opnd0
,opnd2
);
3714 if (regtest
== memtest
)
3722 /* Generate a SImode register with the register number that is the smaller of the two */
3724 gen_min_reg(rtx opnd1
,rtx opnd2
)
3726 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3729 /* Generate a SImode memory with the address that is the smaller of the two */
3731 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3733 int offset1
=0,offset2
=0;
3736 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3738 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3739 reg
= XEXP(XEXP(opnd1
,0),0);
3743 reg
= XEXP(opnd1
,0);
3745 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3747 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3749 address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3750 return gen_rtx_MEM(SImode
,address
);
3754 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3761 /* Need to penalize immediates that need to be encoded as long constants.*/
3762 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3764 *total
= COSTS_N_INSNS(1);
3772 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3777 /* if_then_else come out of cbranch instructions. It will get split into
3778 a condition code generating subtraction and a branch */
3779 *total
= COSTS_N_INSNS (2);
3786 if (GET_MODE(x
) == SImode
)
3787 *total
= COSTS_N_INSNS (2);
3788 if (GET_MODE(x
) == DImode
)
3789 *total
= COSTS_N_INSNS (4);
3793 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3794 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3795 *total
= COSTS_N_INSNS (10);
3797 /* 64-bit accesses have to be done through 2 32-bit access */
3798 if (GET_MODE(x
) == DImode
)
3799 *total
= COSTS_N_INSNS (2);
3805 /* SImode shifts are expensive */
3806 if (GET_MODE(x
) == SImode
)
3807 *total
= COSTS_N_INSNS (10);
3809 /* Register shift by constant is cheap. */
3810 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3811 && GET_CODE(XEXP(x
, 0)) == REG
3812 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3813 *total
= COSTS_N_INSNS (1);
3815 *total
= COSTS_N_INSNS (4);
3822 /* Divisions are more expensive than the default 7*/
3823 if (GET_MODE(x
) == SImode
)
3824 *total
= COSTS_N_INSNS (20);
3826 *total
= COSTS_N_INSNS (12);
3831 /* Look for the simple cases of multiplying register*register or
3832 register*constant. */
3833 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3834 && ((GET_CODE(XEXP(x
, 0)) == REG
3835 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3836 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3837 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3838 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3839 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3842 /* When optimising for size, multiplication by constant
3843 should be discouraged slightly over multiplication by a
3845 if (picochip_has_mac_unit
)
3847 /* Single cycle multiplication, but the result must be
3848 loaded back into a general register afterwards. */
3849 *total
= COSTS_N_INSNS(2);
3852 else if (picochip_has_mul_unit
)
3854 /* Single cycle multiplication. */
3855 *total
= COSTS_N_INSNS(1);
3858 /* Else no multiply available. Use default cost. */
3868 if (localTotal
!= 0)
3870 *total
= localTotal
;
3881 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3882 int num_operands ATTRIBUTE_UNUSED
)
3886 picochip_current_prescan_insn
= insn
;
3889 printf ("Final prescan on INSN %d with mode %s\n",
3890 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3892 /* If this is the start of a new instruction cycle, or no scheduling
3893 is used, then reset the VLIW status. */
3894 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3895 picochip_reset_vliw (insn
);
3897 /* No VLIW scheduling occured, so don't go any further. */
3898 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3901 /* Look for the next printable instruction. This loop terminates on
3902 any recognisable instruction, and on any unrecognisable
3903 instruction with TImode. */
3905 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3906 local_insn
= NEXT_INSN (local_insn
))
3908 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3910 else if (!INSN_P (local_insn
))
3912 else if (GET_MODE (local_insn
) == TImode
3913 || INSN_CODE (local_insn
) != -1)
3917 /* Set the continuation flag if the next instruction can be packed
3918 with the current instruction (i.e., the next instruction is
3919 valid, and isn't the start of a new cycle). */
3920 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3921 (GET_MODE (local_insn
) != TImode
));
3925 /* Builtin functions. */
3926 /* Given a builtin function taking 2 operands (i.e., target + source),
3927 emit the RTL for the underlying instruction. */
3929 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3933 enum machine_mode tmode
, mode0
;
3935 /* Grab the incoming argument and emit its RTL. */
3936 arg0
= CALL_EXPR_ARG (call
, 0);
3937 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3939 /* Determine the modes of the instruction operands. */
3940 tmode
= insn_data
[icode
].operand
[0].mode
;
3941 mode0
= insn_data
[icode
].operand
[1].mode
;
3943 /* Ensure that the incoming argument RTL is in a register of the
3945 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3946 op0
= copy_to_mode_reg (mode0
, op0
);
3948 /* If there isn't a suitable target, emit a target register. */
3950 || GET_MODE (target
) != tmode
3951 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3952 target
= gen_reg_rtx (tmode
);
3954 /* Emit and return the new instruction. */
3955 pat
= GEN_FCN (icode
) (target
, op0
);
3964 /* Given a builtin function taking 3 operands (i.e., target + two
3965 source), emit the RTL for the underlying instruction. */
3967 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3971 enum machine_mode tmode
, mode0
, mode1
;
3973 /* Grab the function's arguments. */
3974 arg0
= CALL_EXPR_ARG (call
, 0);
3975 arg1
= CALL_EXPR_ARG (call
, 1);
3977 /* Emit rtl sequences for the function arguments. */
3978 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3979 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3981 /* Get the mode's of each of the instruction operands. */
3982 tmode
= insn_data
[icode
].operand
[0].mode
;
3983 mode0
= insn_data
[icode
].operand
[1].mode
;
3984 mode1
= insn_data
[icode
].operand
[2].mode
;
3986 /* Ensure that each of the function argument rtl sequences are in a
3987 register of the correct mode. */
3988 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3989 op0
= copy_to_mode_reg (mode0
, op0
);
3990 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3991 op1
= copy_to_mode_reg (mode1
, op1
);
3993 /* If no target has been given, create a register to use as the target. */
3995 || GET_MODE (target
) != tmode
3996 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3997 target
= gen_reg_rtx (tmode
);
3999 /* Emit and return the new instruction. */
4000 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
4009 /* Expand a builtin function which takes two arguments, and returns a void. */
4011 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
4015 enum machine_mode mode0
, mode1
;
4017 /* Grab the function's arguments. */
4018 arg0
= CALL_EXPR_ARG (call
, 0);
4019 arg1
= CALL_EXPR_ARG (call
, 1);
4021 /* Emit rtl sequences for the function arguments. */
4022 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4023 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4025 /* Get the mode's of each of the instruction operands. */
4026 mode0
= insn_data
[icode
].operand
[0].mode
;
4027 mode1
= insn_data
[icode
].operand
[1].mode
;
4029 /* Ensure that each of the function argument rtl sequences are in a
4030 register of the correct mode. */
4031 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
4032 op0
= copy_to_mode_reg (mode0
, op0
);
4033 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
4034 op1
= copy_to_mode_reg (mode1
, op1
);
4036 /* Emit and return the new instruction. */
4037 pat
= GEN_FCN (icode
) (op0
, op1
);
4046 /* Expand an array get into the corresponding RTL. */
4048 picochip_expand_array_get (tree call
, rtx target
)
4050 tree arg0
, arg1
, arg2
;
4051 rtx op0
, op1
, op2
, pat
;
4053 /* Grab the function's arguments. */
4054 arg0
= CALL_EXPR_ARG (call
, 0);
4055 arg1
= CALL_EXPR_ARG (call
, 1);
4056 arg2
= CALL_EXPR_ARG (call
, 2) ;
4058 /* Emit rtl sequences for the function arguments. */
4059 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4060 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4061 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4063 /* The second and third operands must be constant. Nothing else will
4065 if (CONST_INT
!= GET_CODE (op1
))
4066 internal_error ("%s: Second source operand is not a constant",
4068 if (CONST_INT
!= GET_CODE (op2
))
4069 internal_error ("%s: Third source operand is not a constant",
4072 /* If no target has been given, create a register to use as the target. */
4073 if (target
== 0 || GET_MODE (target
) != SImode
)
4074 target
= gen_reg_rtx (SImode
);
4076 /* The first operand must be a HImode register or a constant. If it
4077 isn't, force it into a HImode register. */
4078 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4079 op0
= copy_to_mode_reg (HImode
, op0
);
4082 /* Emit and return the new instruction. */
4083 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
4090 /* Expand an array put into the corresponding RTL. */
4092 picochip_expand_array_put (tree call
, rtx target
)
4094 tree arg0
, arg1
, arg2
, arg3
;
4095 rtx op0
, op1
, op2
, op3
, pat
;
4097 /* Grab the function's arguments. */
4098 arg0
= CALL_EXPR_ARG (call
, 0);
4099 arg1
= CALL_EXPR_ARG (call
, 1);
4100 arg2
= CALL_EXPR_ARG (call
, 2);
4101 arg3
= CALL_EXPR_ARG (call
, 3);
4103 /* Emit rtl sequences for the function arguments. */
4104 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4105 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4106 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4107 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4109 /* The first operand must be an SImode register. */
4110 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
4111 op0
= copy_to_mode_reg (SImode
, op0
);
4113 /* The second (index) operand must be a HImode register, or a
4114 constant. If it isn't, force it into a HImode register. */
4115 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
4116 op1
= copy_to_mode_reg (HImode
, op1
);
4118 /* The remaining operands must be constant. Nothing else will do. */
4119 if (CONST_INT
!= GET_CODE (op2
))
4120 internal_error ("%s: Third source operand is not a constant",
4122 if (CONST_INT
!= GET_CODE (op3
))
4123 internal_error ("%s: Fourth source operand is not a constant",
4126 /* Emit and return the new instruction. */
4127 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
4134 /* Expand an array testport into the corresponding RTL. */
4136 picochip_expand_array_testport (tree call
, rtx target
)
4138 tree arg0
, arg1
, arg2
;
4139 rtx op0
, op1
, op2
, pat
;
4141 /* Grab the function's arguments. */
4142 arg0
= CALL_EXPR_ARG (call
, 0);
4143 arg1
= CALL_EXPR_ARG (call
, 1);
4144 arg2
= CALL_EXPR_ARG (call
, 2);
4146 /* Emit rtl sequences for the function arguments. */
4147 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4148 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4149 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4151 /* The first operand must be a HImode register, or a constant. If it
4152 isn't, force it into a HImode register. */
4153 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4154 op0
= copy_to_mode_reg (HImode
, op0
);
4156 /* The second and third operands must be constant. Nothing else will
4158 if (CONST_INT
!= GET_CODE (op1
))
4159 internal_error ("%s: Second source operand is not a constant",
4161 if (CONST_INT
!= GET_CODE (op2
))
4162 internal_error ("%s: Third source operand is not a constant",
4165 /* If no target has been given, create a HImode register to use as
4167 if (target
== 0 || GET_MODE (target
) != HImode
)
4168 target
= gen_reg_rtx (HImode
);
4170 /* Emit and return the new instruction. */
4171 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4178 /* Generate a unique HALT instruction by giving the instruction a
4179 unique integer. This integer makes no difference to the assembly
4180 output (other than a comment indicating the supplied id), but the
4181 presence of the unique integer prevents the compiler from combining
4182 several different halt instructions into one instruction. This
4183 means that each use of the halt instruction is unique, which in
4184 turn means that assertions work as expected. */
4186 picochip_generate_halt (void)
4188 static int currentId
= 0;
4190 rtx id
= GEN_INT (currentId
);
4194 emit_insn (gen_halt (id
));
4196 /* A barrier is inserted to prevent the compiler from thinking that
4197 it has to continue execution after the HALT.*/
4200 insns
= get_insns();
4207 /* Initialise the builtin functions. Start by initialising
4208 descriptions of different types of functions (e.g., void fn(int),
4209 int fn(void)), and then use these to define the builtins. */
4211 picochip_init_builtins (void)
4214 tree endlink
= void_list_node
;
4215 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
4216 tree unsigned_endlink
= tree_cons (NULL_TREE
, unsigned_type_node
, endlink
);
4217 tree long_endlink
= tree_cons (NULL_TREE
, long_integer_type_node
, endlink
);
4218 tree int_int_endlink
=
4219 tree_cons (NULL_TREE
, integer_type_node
, int_endlink
);
4220 tree int_int_int_endlink
=
4221 tree_cons (NULL_TREE
, integer_type_node
, int_int_endlink
);
4222 tree int_long_endlink
=
4223 tree_cons (NULL_TREE
, integer_type_node
, long_endlink
);
4224 tree long_int_int_int_endlink
=
4225 tree_cons (NULL_TREE
, long_integer_type_node
, int_int_int_endlink
);
4227 tree int_ftype_int
, int_ftype_int_int
;
4228 tree long_ftype_int
, long_ftype_int_int_int
;
4229 tree void_ftype_int_long
, int_ftype_int_int_int
,
4230 void_ftype_long_int_int_int
;
4231 tree void_ftype_void
, unsigned_ftype_unsigned
;
4233 /* void func (void) */
4234 void_ftype_void
= build_function_type (void_type_node
, endlink
);
4236 /* int func (int) */
4237 int_ftype_int
= build_function_type (integer_type_node
, int_endlink
);
4239 /* unsigned int func (unsigned int) */
4240 unsigned_ftype_unsigned
= build_function_type (unsigned_type_node
, unsigned_endlink
);
4242 /* int func(int, int) */
4244 = build_function_type (integer_type_node
, int_int_endlink
);
4246 /* long func(int) */
4247 long_ftype_int
= build_function_type (long_integer_type_node
, int_endlink
);
4249 /* long func(int, int, int) */
4250 long_ftype_int_int_int
4251 = build_function_type (long_integer_type_node
, int_int_int_endlink
);
4253 /* int func(int, int, int) */
4254 int_ftype_int_int_int
4255 = build_function_type (integer_type_node
, int_int_int_endlink
);
4257 /* void func(int, long) */
4259 = build_function_type (void_type_node
, int_long_endlink
);
4261 /* void func(long, int, int, int) */
4262 void_ftype_long_int_int_int
4263 = build_function_type (void_type_node
, long_int_int_int_endlink
);
4265 /* Initialise the sign-bit-count function. */
4266 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4267 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4269 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4270 BUILT_IN_MD
, NULL
, NULL_TREE
);
4272 /* Initialise the bit reverse function. */
4273 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4274 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4276 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4277 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4280 /* Initialise the byte swap function. */
4281 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4282 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4284 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4285 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4288 /* Initialise the ASRI function (note that while this can be coded
4289 using a signed shift in C, extra scratch registers are required,
4290 which we avoid by having a direct builtin to map to the
4292 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4293 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4296 /* Initialise saturating addition. */
4297 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4298 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4300 add_builtin_function ("picoAdds", int_ftype_int_int
,
4301 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4304 /* Initialise saturating subtraction. */
4305 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4306 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4308 add_builtin_function ("picoSubs", int_ftype_int_int
,
4309 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4312 /* Scalar comms builtins. */
4313 add_builtin_function ("__builtin_get", long_ftype_int
,
4314 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4316 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4317 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4319 add_builtin_function ("__builtin_testport", int_ftype_int
,
4320 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4323 /* Array comms builtins. */
4324 add_builtin_function ("__builtin_put_array",
4325 void_ftype_long_int_int_int
,
4326 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4328 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4329 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4331 add_builtin_function ("__builtin_testport_array",
4332 int_ftype_int_int_int
,
4333 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4336 /* Halt instruction. Note that the builtin function is marked as
4337 having the attribute `noreturn' so that the compiler realises
4338 that the halt stops the program dead. */
4339 noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4340 add_builtin_function ("__builtin_halt", void_ftype_void
,
4341 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4343 add_builtin_function ("picoHalt", void_ftype_void
,
4344 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4349 /* Expand a call to a builtin function. */
4351 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4352 enum machine_mode mode ATTRIBUTE_UNUSED
,
4353 int ignore ATTRIBUTE_UNUSED
)
4355 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4356 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4360 case PICOCHIP_BUILTIN_ASRI
:
4361 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4364 case PICOCHIP_BUILTIN_ADDS
:
4365 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4368 case PICOCHIP_BUILTIN_SUBS
:
4369 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4372 case PICOCHIP_BUILTIN_SBC
:
4373 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4375 case PICOCHIP_BUILTIN_BREV
:
4376 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4378 case PICOCHIP_BUILTIN_BYTESWAP
:
4379 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4381 case PICOCHIP_BUILTIN_GET
:
4382 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4384 case PICOCHIP_BUILTIN_PUT
:
4385 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4387 case PICOCHIP_BUILTIN_TESTPORT
:
4388 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4391 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4392 return picochip_expand_array_put (exp
, target
);
4394 case PICOCHIP_BUILTIN_GET_ARRAY
:
4395 return picochip_expand_array_get (exp
, target
);
4397 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4398 return picochip_expand_array_testport (exp
, target
);
4400 case PICOCHIP_BUILTIN_HALT
:
4401 return picochip_generate_halt ();
4408 /* Should really do something sensible here. */
4412 /* Emit warnings. */
4414 picochip_warn_inefficient (const char *msg
)
4416 if (TARGET_INEFFICIENT_WARNINGS
)
4417 warning (OPT_minefficient_warnings
,
4418 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4422 warn_of_byte_access (void)
4424 static int warned
= 0;
4428 picochip_warn_inefficient
4429 ("byte access is synthesised - consider using MUL AE");
4436 picochip_function_value (const_tree valtype
, const_tree func
,
4437 bool outgoing ATTRIBUTE_UNUSED
)
4439 enum machine_mode mode
= TYPE_MODE (valtype
);
4440 int unsignedp
= TYPE_UNSIGNED (valtype
);
4442 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4443 just as PROMOTE_MODE does. */
4444 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4446 return gen_rtx_REG (mode
, 0);
4450 /* Check that the value of the given mode will fit in the register of
4453 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4456 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4457 return regno
== CC_REGNUM
;
4459 /* If the CC register is being used, then only CC mode values are
4460 allowed (which have already been tested). */
4461 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4464 /* Must be a valid register. */
4468 /* Modes QI and HI may be placed in any register except the CC. */
4469 if (mode
== QImode
|| mode
== HImode
)
4472 /* DI must be in a quad register. */
4474 return (regno
% 4 == 0);
4476 /* All other modes must be placed in a even numbered register. */
4477 return !(regno
& 1);
4481 /* Extract the lower and upper components of a constant value. */
4484 picochip_get_low_const (rtx value
)
4486 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4490 picochip_get_high_const (rtx value
)
4492 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4493 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4497 /* Loading and storing QImode values to and from memory in a machine
4498 without byte access requires might require a scratch
4499 register. However, the scratch register might correspond to the
4500 register in which the value is being loaded. To ensure that a
4501 scratch register is supplied which is definitely different to the
4502 output register, request a register pair. This effectively gives a
4503 choice of two registers to choose from, so that we a guaranteed to
4504 get at least one register which is different to the output
4505 register. This trick is taken from the alpha implementation. */
4507 picochip_secondary_reload (bool in_p
,
4508 rtx x ATTRIBUTE_UNUSED
,
4509 reg_class_t cla ATTRIBUTE_UNUSED
,
4510 enum machine_mode mode
,
4511 secondary_reload_info
*sri
)
4513 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4516 sri
->icode
= CODE_FOR_reload_outqi
;
4518 sri
->icode
= CODE_FOR_reload_inqi
;
4521 /* We dont need to return a register class type when we need only a
4522 scratch register. It realizes the scratch register type by looking
4523 at the instruction definition for sri->icode. We only need to
4524 return the register type when we need intermediaries for copies.*/
4528 /* Return true if the given memory operand can be aligned to a
4529 word+offset memory reference (e.g., FP+3 can be converted into the
4530 memory operand FP+2, with the offset 1). */
4532 picochip_alignable_memory_operand (rtx mem_operand
,
4533 enum machine_mode mode ATTRIBUTE_UNUSED
)
4537 /* Not a mem operand. Refuse immediately. */
4538 if (MEM
!= GET_CODE (mem_operand
))
4541 address
= XEXP (mem_operand
, 0);
4543 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4544 return ((PLUS
== GET_CODE (address
) &&
4545 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4546 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4547 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4548 || (REG
== GET_CODE (address
)
4549 && REGNO (address
) == STACK_POINTER_REGNUM
));
4553 /* Return true if the given memory reference is to a word aligned
4554 address. Currently this means it must be either SP, or
4555 SP+offset. We could replace this function with alignable
4556 memory references in the above function?. */
4558 picochip_word_aligned_memory_reference (rtx operand
)
4562 /* The address must be the SP register, or a constant, aligned
4563 offset from SP which doesn't exceed the FP+offset
4565 return ((PLUS
== GET_CODE (operand
)
4566 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4567 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4568 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4570 || (REG
== GET_CODE (operand
)
4571 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4575 /* Given an alignable memory location, convert the memory location
4576 into a HI mode access, storing the new memory reference in
4577 paligned_mem, and the number of bits by which to shift in pbitnum
4578 (i.e., given a reference to FP+3, this creates an aligned reference
4579 of FP+2, with an 8-bit shift). This code is a modification of that
4580 found in the Alpha port. */
4582 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4585 HOST_WIDE_INT offset
= 0;
4587 gcc_assert (GET_CODE (ref
) == MEM
);
4589 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4591 base
= find_replacement (&XEXP (ref
, 0));
4593 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4597 base
= XEXP (ref
, 0);
4600 if (GET_CODE (base
) == PLUS
)
4602 offset
+= INTVAL (XEXP (base
, 1));
4603 base
= XEXP (base
, 0);
4606 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4613 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4617 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4621 /* Return true if the given operand is an absolute address in memory
4622 (i.e., a symbolic offset). */
4624 picochip_absolute_memory_operand (rtx op
,
4625 enum machine_mode mode ATTRIBUTE_UNUSED
)
4628 if (MEM
== GET_CODE (op
))
4630 rtx address
= XEXP (op
, 0);
4632 /* Symbols are valid absolute addresses. */
4633 if (SYMBOL_REF
== GET_CODE (address
))
4636 /* Constant offsets to symbols are valid absolute addresses. */
4637 if (CONST
== GET_CODE (address
) &&
4638 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4639 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4640 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4647 /* Symbols are valid absolute addresses. */
4648 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4657 picochip_asm_named_section (const char *name
,
4658 unsigned int flags ATTRIBUTE_UNUSED
,
4659 tree decl ATTRIBUTE_UNUSED
)
4661 fprintf (asm_out_file
, ".section %s\n", name
);
4665 /* Check if we can make a conditional copy instruction. This is emitted as an
4666 instruction to set the condition register, followed by an instruction which
4667 uses the condition registers to perform the conditional move. */
4669 picochip_check_conditional_copy (rtx
* operands
)
4672 rtx branch_op_0
= XEXP (operands
[1], 0);
4673 rtx branch_op_1
= XEXP (operands
[1], 1);
4675 /* Only HI mode conditional moves are currently allowed. Can we add
4677 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4680 /* Is the comparison valid? Only allow operands which are registers
4681 if they are HImode. SI mode comparisons against 0 could be
4682 handled using logical operations (e.g., SIreg != 0 when low ||
4683 high). Need to find test cases to provoke this though (fixunssfdi
4684 in libgcc does, but is complicated). */
4685 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4686 GET_MODE(branch_op_0
) != HImode
)
4688 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4689 GET_MODE(branch_op_1
) != HImode
)
4698 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4702 addr
= arg_pointer_rtx
;
4704 addr
= plus_constant (stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4705 return gen_frame_mem (Pmode
, addr
);