1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001,2008, 2009 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
55 #include "picochip-protos.h"
57 #include "insn-attr.h" /* For DFA state_t. */
58 #include "insn-config.h" /* Required by recog.h */
59 #include "insn-codes.h" /* For CODE_FOR_? */
60 #include "optabs.h" /* For GEN_FCN */
61 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
62 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
63 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
64 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
67 /* Target AE ISA information. */
68 enum picochip_dfa_type picochip_schedule_type
;
70 bool picochip_has_mul_unit
= false;
71 bool picochip_has_mac_unit
= false;
73 /* targetm hook function prototypes. */
75 void picochip_asm_file_start (void);
76 void picochip_asm_file_end (void);
78 void picochip_init_libfuncs (void);
79 void picochip_reorg (void);
81 int picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
,
82 enum machine_mode mode
,
83 tree type
, bool named
);
85 int picochip_sched_lookahead (void);
86 int picochip_sched_issue_rate (void);
87 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
88 rtx dep_insn
, int cost
);
89 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
90 int *n_readyp
, int clock
);
92 void picochip_init_builtins (void);
93 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
95 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int* total
, bool speed
);
96 bool picochip_return_in_memory(const_tree type
,
97 const_tree fntype ATTRIBUTE_UNUSED
);
98 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
99 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
100 enum machine_mode mode
);
101 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
102 int opnum
, int type
, int ind_levels
);
104 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
105 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
106 bool outgoing ATTRIBUTE_UNUSED
);
108 picochip_secondary_reload (bool in_p
,
109 rtx x ATTRIBUTE_UNUSED
,
110 enum reg_class cla ATTRIBUTE_UNUSED
,
111 enum machine_mode mode
,
112 secondary_reload_info
*sri
);
114 picochip_asm_named_section (const char *name
,
115 unsigned int flags ATTRIBUTE_UNUSED
,
116 tree decl ATTRIBUTE_UNUSED
);
118 static rtx
picochip_static_chain (const_tree
, bool);
120 /* Lookup table mapping a register number to the earliest containing
121 class. Used by REGNO_REG_CLASS. */
122 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
124 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
125 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
126 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
127 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
128 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
131 /* picoChip register names. */
132 const char *picochip_regnames
[] = REGISTER_NAMES
;
134 /* Define the maximum number of registers which may be used to pass
135 * parameters to functions. */
136 #define MAX_CALL_PARAMETER_REGS 6
139 /* Target scheduling information. */
141 /* Determine whether we run our final scheduling pass or not. We always
142 avoid the normal second scheduling pass. */
143 int picochip_flag_schedule_insns2
;
145 /* Check if variable tracking needs to be run. */
146 int picochip_flag_var_tracking
;
148 /* This flag indicates whether the next instruction to be output is a
149 VLIW continuation instruction. It is used to communicate between
150 final_prescan_insn and asm_output_opcode. */
151 static int picochip_vliw_continuation
= 0;
153 /* This variable is used to communicate the current instruction
154 between final_prescan_insn and functions such as asm_output_opcode,
155 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
156 current instruction. */
157 static rtx picochip_current_prescan_insn
;
159 static bool picochip_is_delay_slot_pending
= 0;
161 /* When final_prescan_insn is called, it computes information about
162 the current VLIW packet, and stores it in this structure. When
163 instructions are output, this state is used to make sure that the
164 instructions are output in the correct way (e.g., which ALU to use,
165 whether a macro branch was ever previously a real branch, etc.). */
168 int contains_pico_alu_insn
;
169 int contains_non_cc_alu_insn
;
170 int num_alu_insns_so_far
;
172 /* Record how many instructions are contained in the packet. */
173 int num_insns_in_packet
;
175 /* There was a case for this to be more than 1 */
176 int num_cfi_labels_deferred
;
177 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
178 emitted inside a VLIW packet. */
179 char lm_label_name
[256]; /* Used to record the name of an LM label. */
182 struct vliw_state picochip_current_vliw_state
;
184 /* Save/restore recog_data. */
185 static int picochip_saved_which_alternative
;
186 static struct recog_data picochip_saved_recog_data
;
188 /* Determine which ALU to use for the instruction in
189 picochip_current_prescan_insn. */
190 static char picochip_get_vliw_alu_id (void);
192 /* Initialize the GCC target structure. */
194 #undef TARGET_ASM_FUNCTION_PROLOGUE
195 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
197 #undef TARGET_ASM_FUNCTION_EPILOGUE
198 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
200 #undef TARGET_ASM_INTERNAL_LABEL
201 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
203 #undef TARGET_ASM_GLOBALIZE_LABEL
204 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
206 #undef TARGET_ASM_BYTE_OP
207 #define TARGET_ASM_BYTE_OP ".initByte "
208 #undef TARGET_ASM_ALIGNED_HI_OP
209 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
210 #undef TARGET_ASM_UNALIGNED_HI_OP
211 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
214 #undef TARGET_ASM_UNALIGNED_SI_OP
215 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
217 #undef TARGET_INIT_BUILTINS
218 #define TARGET_INIT_BUILTINS picochip_init_builtins
220 #undef TARGET_EXPAND_BUILTIN
221 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS picochip_rtx_costs
226 #undef TARGET_SCHED_ISSUE_RATE
227 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
229 #undef TARGET_SCHED_REORDER
230 #define TARGET_SCHED_REORDER picochip_sched_reorder
232 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
233 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
234 picochip_sched_lookahead
236 #undef TARGET_SCHED_ADJUST_COST
237 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
239 #undef TARGET_ASM_NAMED_SECTION
240 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
242 #undef TARGET_HAVE_NAMED_SECTIONS
243 #define TARGET_HAVE_NAMED_SECTIONS 1
245 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
246 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
248 #undef TARGET_INIT_LIBFUNCS
249 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
251 #undef TARGET_ASM_FILE_START
252 #define TARGET_ASM_FILE_START picochip_asm_file_start
254 #undef TARGET_ASM_FILE_END
255 #define TARGET_ASM_FILE_END picochip_asm_file_end
257 #undef TARGET_MACHINE_DEPENDENT_REORG
258 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
260 #undef TARGET_ARG_PARTIAL_BYTES
261 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
263 #undef TARGET_PROMOTE_FUNCTION_MODE
264 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
265 #undef TARGET_PROMOTE_PROTOTYPES
266 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
268 /* Target support for Anchored Addresses optimization */
269 #undef TARGET_MIN_ANCHOR_OFFSET
270 #define TARGET_MIN_ANCHOR_OFFSET 0
271 #undef TARGET_MAX_ANCHOR_OFFSET
272 #define TARGET_MAX_ANCHOR_OFFSET 7
273 #undef TARGET_ASM_OUTPUT_ANCHOR
274 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
276 #undef TARGET_FUNCTION_VALUE
277 #define TARGET_FUNCTION_VALUE picochip_function_value
279 #undef TARGET_LIBGCC_CMP_RETURN_MODE
280 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
283 #undef TARGET_LEGITIMATE_ADDRESS_P
284 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
286 #undef TARGET_LEGITIMIZE_ADDRESS
287 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
289 /* Loading and storing QImode values to and from memory
290 usually requires a scratch register. */
291 #undef TARGET_SECONDARY_RELOAD
292 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
293 #undef DONT_USE_BUILTIN_SETJMP
294 #define DONT_USE_BUILTIN_SETJMP 1
296 /* How Large Values are Returned */
298 #undef TARGET_RETURN_IN_MEMORY
299 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
301 #undef TARGET_STATIC_CHAIN
302 #define TARGET_STATIC_CHAIN picochip_static_chain
304 struct gcc_target targetm
= TARGET_INITIALIZER
;
307 /* Only return a value in memory if it is greater than 4 bytes.
308 int_size_in_bytes returns -1 for variable size objects, which go in
309 memory always. The cast to unsigned makes -1 > 8. */
312 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
314 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
317 /* Allow certain command options to be overriden. */
319 picochip_override_options (void)
321 /* If we are optimizing for stack, dont let inliner to inline functions
322 that could potentially increase stack size.*/
323 if (flag_conserve_stack
)
325 PARAM_VALUE (PARAM_LARGE_STACK_FRAME
) = 0;
326 PARAM_VALUE (PARAM_STACK_FRAME_GROWTH
) = 0;
329 /* Turn off the elimination of unused types. The elaborator
330 generates various interesting types to represent constants,
331 generics, and so on, and it is useful to retain this information
332 in the debug output. The increased size of the debug information
333 is not really an issue for us. */
334 flag_eliminate_unused_debug_types
= 0;
336 /* Even if the user specifies a -fno-omit-frame-pointer on the
337 command line, we still want to go ahead and omit frame pointer
338 usages, since we dont really have a frame pointer register.
339 So, all accesses to FP need to be converted to accesses off
341 flag_omit_frame_pointer
= 1;
343 /* Turning on anchored addresses by default. This is an optimization
344 that could decrease the code size by placing anchors in data and
345 accessing offsets from the anchor for file local data variables.*/
347 flag_section_anchors
= 1;
349 /* Turn off the second scheduling pass, and move it to
350 picochip_reorg, to avoid having the second jump optimisation
351 trash the instruction modes (e.g., instructions are changed to
352 TImode to mark the beginning of cycles). Two types of DFA
353 scheduling are possible: space and speed. In both cases,
354 instructions are reordered to avoid stalls (e.g., memory loads
355 stall for one cycle). Speed scheduling will also enable VLIW
356 instruction packing. VLIW instructions use more code space, so
357 VLIW scheduling is disabled when scheduling for size. */
358 picochip_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
359 flag_schedule_insns_after_reload
= 0;
360 if (picochip_flag_schedule_insns2
)
364 picochip_schedule_type
= DFA_TYPE_SPACE
;
367 picochip_schedule_type
= DFA_TYPE_SPEED
;
368 flag_delayed_branch
= 0;
373 picochip_schedule_type
= DFA_TYPE_NONE
;
375 /* Ensure that the debug level is always at least -g2. The flow
376 analyser works at its best if it always has debug
377 information. DWARF is non-intrusive, so it makes no difference to
378 code quality if debug is always enabled. */
379 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
381 debug_info_level
= DINFO_LEVEL_NORMAL
;
382 write_symbols
= DWARF2_DEBUG
;
385 /* Options of the form -mae=mac, and so on will be substituted by
386 the compiler driver for the appropriate byte access and multiply
387 unit ISA options. Any unrecognised AE types will end up being
388 passed to the compiler, which should reject them as invalid. */
389 if (picochip_ae_type_string
!= NULL
)
390 error ("invalid AE type specified (%s)\n", picochip_ae_type_string
);
392 /* Override any specific capabilities of the instruction set. These
393 take precedence over any capabilities inferred from the AE type,
394 regardless of where the options appear on the command line. */
395 if (picochip_mul_type_string
== NULL
)
397 /* Default to MEM-type multiply, for historical compatibility. */
398 picochip_has_mac_unit
= false;
399 picochip_has_mul_unit
= true;
403 picochip_has_mac_unit
= false;
404 picochip_has_mul_unit
= false;
406 if (strcmp (picochip_mul_type_string
, "mul") == 0)
407 picochip_has_mul_unit
= true;
408 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
409 picochip_has_mac_unit
= true;
410 else if (strcmp (picochip_mul_type_string
, "none") == 0)
411 { /* Do nothing. Unit types already set to false. */ }
413 error ("Invalid mul type specified (%s) - expected mac, mul or none",
414 picochip_mul_type_string
);
420 /* Initialise the library functions to handle arithmetic on some of
423 picochip_init_libfuncs (void)
426 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
427 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
428 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
430 /* 64-bit signed multiplication. */
431 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
433 /* Signed division */
434 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
435 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
438 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
439 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
441 /* 32-bit count leading Zeros*/
442 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
444 /* 64-bit comparison */
445 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
446 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
448 /* 64-bit addition and subtraction*/
449 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
450 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
453 /* Return the register class for letter C. */
455 picochip_reg_class_from_letter (unsigned c
)
473 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
475 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
478 picochip_order_regs_for_local_alloc (void)
480 /* We change the order for leaf functions alone. We put r12 at
481 the end since using it will prevent us to combine stw/ldws to
482 stl/ldl and it gives no benefit. In non-leaf functions, we
483 would anyway saveup/restore r12, so it makes sense to use it.*/
485 if (leaf_function_p())
487 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
488 FIRST_PSEUDO_REGISTER
* sizeof (int));
492 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
493 FIRST_PSEUDO_REGISTER
* sizeof (int));
497 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
499 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
504 case 'I': /* 4 bits signed. */
505 return value
+ 8 < 16;
506 case 'J': /* 4 bits unsigned. */
508 case 'K': /* 8 bits signed. */
509 return value
+ 128 < 256;
510 case 'M': /* 4-bit magnitude. */
511 return abs (value
) < 16;
512 case 'N': /* 10 bits signed. */
513 return value
+ 512 > 1024;
514 case 'O': /* 16 bits signed. */
515 return value
+ 32768 < 65536;
516 default: /* Unknown letter. */
521 /* Stack utility functions. */
523 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
526 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
532 /* Emit a set of parallel register expressions used to store
533 blockmode values to pass to functions. */
535 picochip_emit_register_parallel (int size_in_units
, int offset
)
539 rtx vector
[MAX_CALL_PARAMETER_REGS
];
543 /* Compute the base register, and number of required registers. */
544 base_reg
= offset
/ 2;
545 num_regs
= size_in_units
/ 2;
546 if (size_in_units
% 2 == 1)
549 /* Emit a register for each part of the block mode value to be
550 passed in a register. */
551 for (i
= 0; i
< num_regs
; i
++)
552 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
553 gen_rtx_REG (HImode
, base_reg
+ i
),
555 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
561 /* Emit an instruction to allocate a suitable amount of space on the
562 stack, by decrementing the stack pointer. */
564 picochip_emit_stack_allocate (int adjustment
)
567 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
569 /* Use an addition of a negative value. */
570 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
571 GEN_INT (-adjustment
)));
573 /* Make the instruction frame related. Also add an expression note,
574 so that the correct Dwarf information is generated (see documention
575 for RTX_FRAME_RELATED_P for more details). */
576 RTX_FRAME_RELATED_P (insn
) = 1;
578 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
579 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
580 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
581 GEN_INT (-adjustment
))),
586 /* Emit an instruction to save a register of the given mode. The
587 offset at which to save the register is given relative to the stack
590 picochip_emit_save_register (rtx reg
, int offset
)
592 rtx stack_pointer
, address
, mem
, insn
;
594 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
596 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
598 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
600 insn
= emit_move_insn (mem
, reg
);
601 RTX_FRAME_RELATED_P (insn
) = 1;
603 /* For modes other than HImode, create a note explaining that
604 multiple registers have been saved. This allows the correct DWARF
605 call frame information to be generated. */
606 switch (GET_MODE (reg
))
609 /* The RTL is sufficient to explain HImode register saves. */
613 /* SImode must be broken down into parallel HImode register saves. */
621 gen_rtx_PLUS (Pmode
, stack_pointer
,
623 gen_rtx_REG (HImode
, REGNO (reg
)));
624 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
627 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
632 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
633 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
636 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
637 gen_rtx_PARALLEL (VOIDmode
, p
),
645 ("unexpected mode %s encountered in picochip_emit_save_register\n",
646 GET_MODE_NAME (GET_MODE (reg
)));
651 /* Emit an instruction to restore a register of the given mode. The
652 offset from which to restore the register is given relative to the
655 picochip_emit_restore_register (rtx reg
, int offset
)
657 rtx stack_pointer
, address
, mem
, insn
;
659 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
661 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
663 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
665 insn
= emit_move_insn (reg
, mem
);
669 /* Check that the given byte offset is aligned to the given number of
672 picochip_is_aligned (int byte_offset
, int bit_alignment
)
674 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
675 return (byte_offset
% byte_alignment
) == 0;
678 /*****************************************************************************
681 * The following section contains code which controls how the stack is
684 * The stack is laid out as follows (high addresses first):
687 * Pretend arguments (ARG PTR)
691 * Outgoing arguments (SP)
693 * The (constant) offsets of the different areas must be calculated
694 * relative to the stack area immediately below, and aligned
695 * appropriately. For example, the frame offset is computed by
696 * determining the offset of the special register area, adding the
697 * size of the special register area, and then aligning the resulting
698 * offset correctly. In turn, the special register offset is computed
699 * from the general register offset, and so on. This enables the
700 * different offsets to change size and alignment, without requiring
701 * the code for other offset calculations to be rewritten.
703 * The argument pointer, and the frame pointer are eliminated wherever
704 * possible, by replacing them with a constant offset from the stack
705 * pointer. In the rare cases where constant offsets from the stack
706 * pointer cannot be computed, another register will be allocated to
707 * serve as the argument pointer, or the frame pointer.
709 * The save registers are stored at small offsets from the caller, to
710 * enable the more efficient SP-based ISA instructions to be used.
712 ****************************************************************************/
714 /* Compute the size of an argument in units. */
716 picochip_compute_arg_size (tree type
, enum machine_mode mode
)
718 int type_size_in_units
= 0;
721 type_size_in_units
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
723 type_size_in_units
= GET_MODE_SIZE (mode
);
725 return type_size_in_units
;
729 /* Determine where the next outgoing arg should be placed. */
731 picochip_function_arg (CUMULATIVE_ARGS cum
, int mode
, tree type
,
732 int named ATTRIBUTE_UNUSED
)
735 int type_align_in_units
= 0;
736 int type_size_in_units
;
738 int offset_overflow
= 0;
740 /* VOIDmode is passed when computing the second argument to a `call'
741 pattern. This can be ignored. */
742 if (mode
== VOIDmode
)
745 /* Compute the alignment and size of the parameter. */
746 type_align_in_units
=
747 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
748 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
750 /* Compute the correct offset (i.e., ensure that the offset meets
751 the alignment requirements). */
752 offset_overflow
= cum
% type_align_in_units
;
753 if (offset_overflow
== 0)
756 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
760 printf ("Function arg:\n");
761 printf (" Type valid: %s\n", (type
? "yes" : "no"));
762 printf (" Cumulative Value: %d\n", cum
);
763 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
764 printf (" Type size: %i units\n", type_size_in_units
);
765 printf (" Alignment: %i units\n", type_align_in_units
);
766 printf (" New offset: %i\n", new_offset
);
770 /* If the new offset is outside the register space, return. */
771 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
774 /* If the end of the argument is outside the register space, then
775 the argument must overlap the register space. Return the first
776 available register. */
777 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
778 return gen_rtx_REG (HImode
, new_offset
/ 2);
780 /* Create a register of the required mode to hold the parameter. */
781 reg
= new_offset
/ 2;
796 return gen_rtx_REG ((enum machine_mode
) mode
, reg
);
800 /* Empty blockmode values can be passed as arguments (e.g.,
801 * empty structs). These require no registers
802 * whatsoever. Non-empty blockmode values are passed in a set
803 * of parallel registers. */
804 if (type_size_in_units
== 0)
807 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
812 (0, "Defaulting to stack for %s register creation\n",
813 GET_MODE_NAME (mode
));
821 /* Determine where the next incoming function argument will
822 appear. Normally, this works in exactly the same way as
823 picochip_function_arg, except when the function in question is a
824 varadic function. In this case, the incoming arguments all appear
825 to be passed on the stack (actually, some of the arguments are
826 passed in registers, which are then pushed onto the stack by the
827 function prologue). */
829 picochip_incoming_function_arg (CUMULATIVE_ARGS cum
, int mode
,
830 tree type
, int named
)
836 return picochip_function_arg (cum
, mode
, type
, named
);
840 /* Gives the alignment boundary, in bits, of an argument with the
843 picochip_get_function_arg_boundary (enum machine_mode mode
)
848 align
= STACK_BOUNDARY
;
850 align
= GET_MODE_ALIGNMENT (mode
);
852 if (align
< PARM_BOUNDARY
)
853 align
= PARM_BOUNDARY
;
859 /* Compute partial registers. */
861 picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
, enum machine_mode mode
,
862 tree type
, bool named ATTRIBUTE_UNUSED
)
864 int type_align_in_units
= 0;
865 int type_size_in_units
;
867 int offset_overflow
= 0;
869 unsigned cum
= *((unsigned *) p_cum
);
871 /* VOIDmode is passed when computing the second argument to a `call'
872 pattern. This can be ignored. */
873 if (mode
== VOIDmode
)
876 /* Compute the alignment and size of the parameter. */
877 type_align_in_units
=
878 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
879 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
881 /* Compute the correct offset (i.e., ensure that the offset meets
882 the alignment requirements). */
883 offset_overflow
= cum
% type_align_in_units
;
884 if (offset_overflow
== 0)
887 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
891 printf ("Partial function arg nregs:\n");
892 printf (" Type valid: %s\n", (type
? "yes" : "no"));
893 printf (" Cumulative Value: %d\n", cum
);
894 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
895 printf (" Type size: %i units\n", type_size_in_units
);
896 printf (" Alignment: %i units\n", type_align_in_units
);
897 printf (" New offset: %i\n", new_offset
);
901 /* If the new offset is outside the register space, return. */
902 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
905 /* If the end of the argument is outside the register space, then
906 the argument must overlap the register space. Return the number
907 of bytes which are passed in registers. */
908 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
909 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
915 /* Advance the cumulative args counter, returning the new counter. */
917 picochip_arg_advance (const CUMULATIVE_ARGS cum
, int mode
,
918 tree type
, int named ATTRIBUTE_UNUSED
)
920 int type_align_in_units
= 0;
921 int type_size_in_units
;
923 int offset_overflow
= 0;
925 /* VOIDmode is passed when computing the second argument to a `call'
926 pattern. This can be ignored. */
927 if (mode
== VOIDmode
)
930 /* Compute the alignment and size of the parameter. */
931 type_align_in_units
=
932 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
933 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
935 /* Compute the correct offset (i.e., ensure that the offset meets
936 the alignment requirements). */
937 offset_overflow
= cum
% type_align_in_units
;
938 if (offset_overflow
== 0)
941 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
943 /* Advance past the last argument. */
944 new_offset
+= type_size_in_units
;
950 /* Determine whether a register needs saving/restoring. It does if it
951 is live in a function, and isn't a call-used register. */
953 picochip_reg_needs_saving (int reg_num
)
955 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
958 /* Compute and return offset of the main frame. */
960 picochip_frame_byte_offset (void)
962 gcc_assert(picochip_is_aligned
963 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
965 return crtl
->outgoing_args_size
;
968 /* Return the size of the main frame. */
970 picochip_frame_size_in_bytes (void)
972 int frame_size
= get_frame_size();
973 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
974 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
975 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
976 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
980 /* Compute and return the size (in bytes) of the register save/restore
981 area for the current function. This only includes the general
982 purpose registers - the special purpose stack pointer and link
983 registers are not included in this area. */
985 picochip_save_area_size_in_bytes (void)
987 int num_regs_to_save
= 0;
990 /* Read through all the registers, determining which need to be saved. */
991 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
993 if (picochip_reg_needs_saving (i
))
994 num_regs_to_save
+= 1;
997 return num_regs_to_save
* UNITS_PER_WORD
;
1001 /* Compute and return offset of the save area base. */
1003 picochip_save_area_byte_offset (void)
1005 int base_offset
= (picochip_frame_byte_offset () +
1006 picochip_frame_size_in_bytes ());
1008 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1014 /* Compute and return offset of the special register save area. This
1015 area can be found immediately above the normal save area. It must
1016 be aligned, to allow the registers to be saved and restored as a
1019 picochip_special_save_area_byte_offset (void)
1021 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1022 int offset
= (picochip_save_area_byte_offset () +
1023 picochip_save_area_size_in_bytes ());
1025 if ((offset
% byte_alignment
) != 0)
1026 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1032 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1034 picochip_can_eliminate_link_sp_save (void)
1036 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1037 changing during optimizations phases. So, this function returns different
1038 values when called from initial_elimination_offset and then again when it
1039 is called from prologue/epilogue generation. This means that argument
1040 accesses become wrong. This wouldnt happen only if we were not using the
1041 stack at all. The following conditions ensures that.*/
1043 return (current_function_is_leaf
&&
1044 !df_regs_ever_live_p(LINK_REGNUM
) &&
1045 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1046 (picochip_special_save_area_byte_offset() == 0) &&
1047 (crtl
->args
.size
== 0) &&
1048 (crtl
->args
.pretend_args_size
== 0));
1051 /* Compute the size of the special reg save area (SP and LNK). If the
1052 SP/LNK registers don't need to be saved, this area can shrink to
1055 picochip_special_save_area_size_in_bytes (void)
1059 if (picochip_can_eliminate_link_sp_save ())
1062 return 2 * UNITS_PER_WORD
;
1065 /* Return the number of pretend arguments. If this function is
1066 varadic, all the incoming arguments are effectively passed on the
1067 stack. If this function has real pretend arguments (caused by a
1068 value being passed partially on the stack and partially in
1069 registers), then return the number of registers used. */
1071 picochip_pretend_arg_area_size (void)
1074 if (crtl
->args
.pretend_args_size
!= 0)
1076 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1078 return crtl
->args
.pretend_args_size
;
1080 else if (cfun
->stdarg
)
1087 /* Compute and return the offset of the pretend arguments. The pretend
1088 arguments are contiguous with the incoming arguments, and must be
1089 correctly aligned. */
1091 picochip_pretend_arg_area_byte_offset (void)
1093 int base_offset
= 0;
1095 base_offset
= (picochip_special_save_area_byte_offset () +
1096 picochip_special_save_area_size_in_bytes ());
1098 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1099 gcc_assert(picochip_is_aligned
1100 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1106 /* Compute and return the offset of the incoming arguments. If a
1107 static chain is in use, this will be passed just before the other
1108 arguments. This means that the pretend argument mechanism, used in
1109 variadic functions, doesn't work properly. Thus, static chains work
1110 on their own, as do variadic functions, but not the combination of
1111 the two. This isn't really a problem. */
1113 picochip_arg_area_byte_offset (void)
1115 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1116 picochip_pretend_arg_area_size ());
1118 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1119 the alignment on a 32-bit boundary must be maintained. */
1120 if (cfun
->static_chain_decl
!= NULL
)
1122 gcc_assert (!cfun
->stdarg
);
1126 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1133 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, int mode
)
1136 /* Special case - only one register needed. */
1137 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1140 /* We actually do not allocate acc0 ever. But, it seems like we need to
1141 make it look like a allocatable register for the dataflow checks to work
1142 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1147 /* General case - compute how much space in terms of units. */
1148 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1153 picochip_class_max_nregs (int class, int mode
)
1155 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1157 if (class == ACC_REGS
)
1160 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1167 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1168 argument pointer) by replacing it with a constant offset from the
1169 main stack register. */
1171 initial_elimination_offset (int from
, int to
)
1173 int offset_from_sp
= 0;
1175 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1176 offset_from_sp
= picochip_frame_byte_offset ();
1177 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1178 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1182 return offset_from_sp
;
1186 /* Compute and return the size of the incoming argument area. */
1188 picochip_arg_area_size_in_bytes (void)
1190 return crtl
->args
.size
;
1193 /* Determine whether the given register is valid. When the strict mode
1194 is used, only hard registers are valid, otherwise any register is
1197 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1200 /* Sanity check - non-registers shouldn't make it here, but... */
1201 if (REG
!= GET_CODE (x
))
1205 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1211 /* Determine whether the given constant is in the range required for
1212 the given base register. */
1214 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1216 HOST_WIDE_INT corrected_offset
;
1218 if (GET_MODE_SIZE (mode
) != 0)
1220 if (GET_MODE_SIZE(mode
) <= 4)
1222 /* We used to allow incorrect offsets if strict is 0. But, this would
1223 then rely on reload doing the right thing. We have had problems
1224 there before, and on > 4.3 compiler, there are no benefits. */
1225 if (offset
% GET_MODE_SIZE (mode
) != 0)
1227 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1231 if (offset
% 4 != 0)
1233 corrected_offset
= offset
/ 4;
1238 /* Default to the byte offset as supplied. */
1239 corrected_offset
= offset
;
1242 /* The offset from the base register can be different depending upon
1243 the base register. The stack/frame/argument pointer offsets can
1244 all be greater than a simple register-based offset. Note that the
1245 frame/argument pointer registers are actually eliminations of the
1246 stack pointer, so a value which is valid for an offset to, for
1247 example, the frame pointer, might be invalid for the stack
1248 pointer once the elimination has occurred. However, there is no
1249 need to handle this special case here, as the stack offset is
1250 always checked after elimination anyway, and the generated code
1251 seems to have identical performance. */
1252 if (regno
== STACK_POINTER_REGNUM
||
1253 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1254 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1256 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1260 /* Determine whether a given rtx is a legitimate address for machine_mode
1261 MODE. STRICT is non-zero if we're being strict - any pseudo that
1262 is not a hard register must be a memory reference. */
1264 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1268 switch (GET_CODE (x
))
1271 valid
= picochip_legitimate_address_register (x
, strict
);
1276 rtx base
= XEXP (x
, 0);
1277 rtx offset
= XEXP (x
, 1);
1278 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1284 valid
= (REG
== GET_CODE (base
) &&
1285 picochip_legitimate_address_register (base
, strict
) &&
1286 CONST_INT
== GET_CODE (offset
) &&
1287 picochip_const_ok_for_base (mode
, REGNO (base
),
1293 /* The user can select whether a symbol can be used as a memory
1294 address. Typically, this will decrease execution time (no
1295 register load is required first), but will increase code size
1296 (because the symbol will be used several times, rather than
1297 loaded once into a register.*/
1298 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1303 /* A constant memory address must be a (plus (symbol_ref)
1304 (const_int)), and is only allowed when the symbols are
1305 permitted addresses. */
1306 rtx inner
= XEXP (x
, 0);
1308 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1309 PLUS
== GET_CODE (inner
) &&
1310 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1311 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1325 /* For all memory operations, picochip allows a uconst4 offset value. It
1326 is hence beneficial to turn an
1327 addr = <reg + long_const>
1332 X = reg + long_const & FFF0
1333 diff = long_const - (long_const & FFF0)
1336 X can be reused in subsequent memory operations.
1339 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1340 enum machine_mode mode
)
1346 // Depending on mode, the offsets allowed are either 16/32/64.
1362 if (GET_CODE (x
) == PLUS
1363 && GET_CODE (XEXP (x
, 0)) == REG
1364 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1366 int offset
= INTVAL (XEXP (x
, 1));
1367 // Ignore cases with negative offsets.
1370 int high_val
= offset
& mask_val
;
1371 int low_val
= offset
- high_val
;
1374 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1375 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1382 /* For all memory operations, picochip allows a uconst4 offset value. It
1383 is hence beneficial to turn an
1384 addr = <reg + long_const>
1389 X = reg + long_const & FFF0
1390 diff = long_const - (long_const & FFF0)
1393 X can be reused in subsequent memory operations.
1396 picochip_legitimize_reload_address (rtx
*x
,
1397 enum machine_mode mode
,
1398 int opnum
, int type
,
1399 int ind_levels ATTRIBUTE_UNUSED
)
1401 if (picochip_symbol_offset(*x
))
1403 *x
= gen_rtx_CONST(mode
, *x
);
1409 /* We should recognise addresses that we created.*/
1410 if (GET_CODE (*x
) == PLUS
1411 && GET_CODE (XEXP (*x
, 0)) == PLUS
1412 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1413 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1414 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1416 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1417 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1418 opnum
, (enum reload_type
)type
);
1423 // Depending on mode, the offsets allowed are either 16/32/64.
1439 if (GET_CODE (*x
) == PLUS
1440 && GET_CODE (XEXP (*x
, 0)) == REG
1441 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1443 int offset
= INTVAL (XEXP (*x
, 1));
1444 // Ignore cases with negative offsets.
1447 int high_val
= offset
& mask_val
;
1448 int low_val
= offset
- high_val
;
1451 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1452 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1453 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1454 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1455 opnum
, (enum reload_type
)type
);
1463 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1465 picochip_symbol_offset (rtx operand
)
1468 return (PLUS
== GET_CODE (operand
) &&
1469 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1470 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1474 /* Assembly output. */
1476 /* The format here should match the format used in the output of
1477 symbol_ref's elsewhere in this file. */
1479 picochip_output_label (FILE * stream
, const char name
[])
1481 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1483 /* If VLIW scheduling is in use, any Call Frame Information labels
1484 generated inside a packet must have their output deferred until
1485 the end of the packet. */
1486 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1487 is_cfi_label
&& picochip_vliw_continuation
)
1489 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1491 internal_error ("LCFI labels have already been deferred.");
1493 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1494 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1495 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1499 assemble_name (stream
, name
);
1501 if (strncmp (name
, "picoMark_", 9) == 0)
1502 fprintf (stream
, "=\n");
1504 fprintf (stream
, ":\n");
1510 /* The format here should match the format used in the output of
1511 symbol_ref's elsewhere in this file. */
1513 picochip_output_labelref (FILE * stream
, const char name
[])
1515 fprintf (stream
, "_%s", name
);
1519 picochip_weaken_label (FILE * stream
, const char name
[])
1521 fprintf (stream
, ".weak ");
1522 assemble_name (stream
, name
);
1523 fprintf (stream
, "\n");
1526 /* Return true if the given label (or label prefix) denotes a marker
1527 label which should be emitted in the form LABEL= */
1529 picochip_is_marker_prefix (const char *prefix
)
1531 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1532 && strcmp (prefix
, "LP") != 0);
1536 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1540 /* Emit different types of label, based upon their prefix. They
1541 are handled differently to allow the assembler to ensure that
1542 branch target labels are properly aligned, while other labels
1543 will only serve as code markers, not branch targets. Aligning
1544 labels unnecessarily can result in much code wastage. */
1545 if (picochip_is_marker_prefix (prefix
))
1547 /* Special label marker. If it appears in the middle of a VLIW
1548 packet, defer it until the end of the packet. There has
1549 never been a need to handle more than one lm label at a time. */
1550 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1551 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1553 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1554 internal_error ("LM label has already been deferred.");
1556 sprintf (picochip_current_vliw_state
.lm_label_name
,
1557 "picoMark_%s%ld", prefix
, num
);
1562 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1569 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1575 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1577 /* Two types of internal label can be generated: branch target
1578 labels and code marker labels. Branch target labels must always
1579 be aligned (since code will execute at these
1580 points). Differentiate between the two by prepending markers with
1581 a unique prefix, which can later be used in output_label to
1582 figure out which label syntax to use. */
1583 if (picochip_is_marker_prefix (prefix
))
1584 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1586 sprintf (str
, "%s%ld", prefix
, num
);
1591 picochip_asm_output_anchor (rtx symbol
)
1593 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1594 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1598 picochip_output_aligned_common (FILE * stream
, const char *name
,
1599 unsigned size
, unsigned alignment
)
1602 fprintf (stream
, ".commonData ");
1603 assemble_name (stream
, name
);
1604 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1605 picochip_output_global (stream
, name
);
1610 picochip_output_aligned_local (FILE * stream
, const char *name
,
1611 unsigned size
, unsigned alignment
)
1614 fprintf (stream
, ".commonData ");
1615 assemble_name (stream
, name
);
1616 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1621 picochip_output_global (FILE * stream
, const char *name
)
1623 fprintf (stream
, ".global ");
1624 assemble_name (stream
, name
);
1625 fprintf (stream
, "\n");
1628 /* Output an assembly language string. Output as a sequence of decimal
1629 numbers, followed by the literal string to make it obvious what the
1630 numbers represent. */
1632 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1636 fprintf (file
, ".ascii ");
1638 for (i
= 0; i
< length
; ++i
)
1640 fprintf (file
, "16#%hhx# ", (char) (str
[i
]));
1643 fprintf (file
, " ; ");
1645 for (i
= 0; i
< length
; ++i
)
1652 fprintf (file
, "\\n");
1655 fprintf (file
, "\\t");
1658 fprintf (file
, "\\0");
1661 fprintf (file
, "%c", c
);
1666 fprintf (file
, "\n");
1670 /* Output the beginning of an ASM file. */
1672 picochip_asm_file_start (void)
1674 default_file_start ();
1676 fprintf (asm_out_file
, "// picoChip ASM file\n");
1677 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1679 fprintf (asm_out_file
, "// Has byte access: %s\n",
1680 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1682 if (TARGET_HAS_MUL_UNIT
)
1683 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1684 else if (TARGET_HAS_MAC_UNIT
)
1685 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1687 fprintf (asm_out_file
, "// Has multiply: No\n");
1689 /* Variable tracking should be run after all optimizations which change order
1690 of insns. It also needs a valid CFG. This can't be done in
1691 picochip_override_options, because flag_var_tracking is finalized after
1693 picochip_flag_var_tracking
= flag_var_tracking
;
1694 flag_var_tracking
= 0;
1697 /* Output the end of an ASM file. */
1699 picochip_asm_file_end (void)
1701 /* Include a segment end to make it easy for PERL scripts to grab
1702 segments. This is now done by assembler*/
1704 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1708 /* Output frame debug information to the given stream. */
1710 picochip_output_frame_debug (FILE * file
)
1714 if (current_function_is_leaf
)
1715 fprintf (file
, "\t\t// Leaf function\n");
1717 fprintf (file
, "\t\t// Non-leaf function\n");
1719 if (picochip_can_eliminate_link_sp_save ())
1720 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1722 if (cfun
->static_chain_decl
!= NULL
)
1723 fprintf (file
, "\t\t// Static chain in use\n");
1725 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1726 picochip_arg_area_size_in_bytes ());
1727 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1728 picochip_arg_area_byte_offset ());
1729 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1730 picochip_pretend_arg_area_size ());
1731 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1732 picochip_pretend_arg_area_byte_offset ());
1733 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1734 picochip_special_save_area_size_in_bytes ());
1735 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1736 picochip_special_save_area_byte_offset ());
1738 /* Output which registers are saved. */
1739 fprintf (file
, "\t\t// Saved regs: ");
1740 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1742 if (picochip_reg_needs_saving (i
))
1743 fprintf (file
, "%s ", picochip_regnames
[i
]);
1745 fprintf (file
, "\t\t\n");
1747 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1748 picochip_save_area_size_in_bytes ());
1749 fprintf (file
, "\t\t// Save area offset: %d\n",
1750 picochip_save_area_byte_offset ());
1752 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1753 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1754 picochip_frame_byte_offset ());
1756 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1757 crtl
->outgoing_args_size
);
1761 /* Output picoChip function prologue. This contains human-readable
1762 information about the function. */
1764 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1766 /* Get the function's name, as described by its RTL. This may be
1767 different from the DECL_NAME name used in the source file. The
1768 real declaration name must be used, to ensure that the prologue
1769 emits the right information for the linker. */
1772 x
= DECL_RTL (current_function_decl
);
1773 gcc_assert (MEM_P (x
));
1775 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1776 fnname
= XSTR (x
, 0);
1778 /* Note that the name of the function is given in the &_%s
1779 form. This matches the name of the function as used in labels,
1780 and function calls, and enables processCallGraph to match
1781 function calls to the name of the function, as defined here. */
1782 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1783 fnname
, picochip_arg_area_byte_offset ());
1785 picochip_output_frame_debug (file
);
1786 fprintf (file
, "\n");
1790 /* Output picoChip function epilogue. */
1792 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1797 x
= DECL_RTL (current_function_decl
);
1798 gcc_assert (MEM_P (x
));
1800 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1801 fnname
= XSTR (x
, 0);
1802 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1806 /* Manipulate the asm output. Some machines only execute the code when
1807 there is actually a chance of needing it (e.g., FRV doesn't execute
1808 it if the scheduling pass wasn't used). We always execute it,
1809 simple to ensure that it is exercised more often, and bugs are more
1812 This function's prime reason for existence is to insert the VLIW
1813 separators where appropriate. The separators must be inserted
1814 before any comments which appear at the end of the file.
1818 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1822 /* Flag to specify when a VLIW continuation has been inserted onto
1823 the line. Continuations are either inserted before any comments,
1824 or before the end of the line is reached. The flag ensures that
1825 we don't insert continuations twice (i.e., at the comment and the
1827 int continuation_inserted
= 0;
1829 /* If the instruction uses multiple lines (i.e., a new line
1830 character appears in the opcode), then ensure that no attempt is
1831 made to pack it into a VLIW. */
1832 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1834 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1838 /* If a delay slot is pending, output the directive to the assembler
1839 before the instruction. */
1840 if (picochip_is_delay_slot_pending
)
1842 picochip_is_delay_slot_pending
= 0;
1846 /* Keep going for entire opcode. All substitution performed ourselves. */
1851 /* Determine whether a VLIW continuation must be inserted before
1852 any comments, or the end of the opcode. A flag is set to show
1853 that we have inserted a continuation on this line, so that we
1854 don't try to insert another continuation when the end of the
1855 opcode is reached. The only other case for a continuation
1856 might have been a newline, but these aren't allowed in
1857 conjunction with VLIW continuations (see above code). */
1858 if (picochip_vliw_continuation
&&
1859 !continuation_inserted
&&
1860 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1863 continuation_inserted
= 1;
1866 /* Detect an explicit VLIW separator. */
1867 if (c
== '%' && (*ptr
== '|'))
1872 /* Detect the need for an ALU id operand. */
1873 else if (c
== '%' && (*ptr
== '#'))
1875 fputc (picochip_get_vliw_alu_id (), f
);
1878 printf ("Generated ALU char at %s for insn %d\n", ptr
,
1879 INSN_UID (picochip_current_prescan_insn
));
1881 /* Skip past unwanted # */
1884 /* Detect the need for branch delay slot. */
1885 else if (c
== '%' && (*ptr
== '>'))
1887 /* Only emit delay slots (NOP's, or otherwise) when delay
1888 * slot scheduling has actually been enabled, otherwise VLIW
1889 * scheduling and delay slot scheduling output combine to
1890 * produce nasty effects. */
1891 if (flag_delayed_branch
)
1893 if (dbr_sequence_length () == 0)
1894 fputs ("\n=->\tNOP", f
);
1896 picochip_is_delay_slot_pending
= 1;
1899 /* Skip past unwanted > */
1902 /* Detect any %digit specifiers. */
1903 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
1906 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
1907 while ((c
= *ptr
) >= '0' && c
<= '9')
1910 /* Detect any %letterdigit specifiers. */
1911 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
1912 || (*ptr
>= 'A' && *ptr
<= 'Z')))
1914 int letter
= *ptr
++;
1921 output_asm_label (recog_data
.operand
[c
]);
1925 output_address (recog_data
.operand
[c
]);
1929 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
1932 while ((c
= *ptr
) >= '0' && c
<= '9')
1937 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
1943 /* Reached the end of the packet. If any labels were deferred
1944 during output, emit them now. */
1945 if (!picochip_vliw_continuation
)
1947 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
1950 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
1952 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1955 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
1960 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1963 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
1968 /* Output an end-of-packet marker if requested. */
1969 if (!picochip_vliw_continuation
&&
1970 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
1971 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
1976 /* Function RTL expansion. */
1978 /* Expand the prologue into RTL. */
1980 picochip_expand_prologue (void)
1982 int stack_adjustment
= 0;
1983 int special_save_offset
= 0;
1984 int general_save_offset
= 0;
1985 int reg_save_offset
= 0;
1988 stack_adjustment
= picochip_arg_area_byte_offset ();
1989 general_save_offset
=
1990 -(stack_adjustment
- picochip_save_area_byte_offset ());
1991 special_save_offset
=
1992 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
1994 /* Save the link registers. We could try to save just one register
1995 here. This would reduce the amount of stack space required.
1996 There hasnt been a good reason to do that so far. */
1997 if (!picochip_can_eliminate_link_sp_save ())
1998 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
1999 special_save_offset
);
2001 /* Save callee-save registers. */
2002 reg_save_offset
= 0;
2003 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2005 if (picochip_reg_needs_saving (i
))
2008 /* If this register is an even numbered register, and the
2009 next register also needs to be saved, use a SImode save,
2010 which does both in one instruction. Note that a special
2011 check is performed to ensure that the double word aligned
2012 store is valid (e.g., it is possible that r6, r8, r9 need
2013 to be saved, in which case once r6 has been saved, the
2014 stored offset is no longer aligned, and an STL/LDL
2015 instruction becomes invalid). Alternately, we could store all
2016 aligned registers first and then save the single one(s). */
2018 picochip_reg_needs_saving (i
+ 1) &&
2019 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2021 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2022 general_save_offset
+
2024 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2029 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2030 general_save_offset
+
2032 reg_save_offset
+= UNITS_PER_WORD
;
2038 /* Emit a stack adjustment where required. */
2039 if (stack_adjustment
!= 0)
2040 picochip_emit_stack_allocate (stack_adjustment
);
2042 /* If this function uses varadic arguments, write any unnamed
2043 registers to the stack. */
2046 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2048 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2049 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2051 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2052 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2054 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2061 /* Expand the epilogue into RTL. */
2063 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2065 int stack_adjustment
= 0;
2066 int special_save_offset
= 0;
2067 int general_save_offset
= 0;
2068 int reg_save_offset
= 0;
2070 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2073 stack_adjustment
= picochip_arg_area_byte_offset ();
2074 general_save_offset
=
2075 -(stack_adjustment
- picochip_save_area_byte_offset ());
2076 special_save_offset
=
2077 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2079 /* Emit a stack adjustment where required. */
2080 if (stack_adjustment
!= 0)
2082 /* If the link/fp is already being restored, and the offset to
2083 their save location is small enough, don't bother adjusting
2084 the stack explicitly. */
2085 if (picochip_special_save_area_byte_offset () < 512 &&
2086 !picochip_can_eliminate_link_sp_save ())
2087 use_link_fp_restore_stack_adjust
= 1;
2089 /* Explicitly restore the stack. */
2090 picochip_emit_stack_allocate (-stack_adjustment
);
2093 /* Restore the Link/FP registers. Only save the link register? */
2094 if (!picochip_can_eliminate_link_sp_save ())
2096 if (use_link_fp_restore_stack_adjust
)
2097 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2098 picochip_special_save_area_byte_offset
2101 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2102 special_save_offset
);
2105 /* Restore callee-save registers. */
2106 reg_save_offset
= 0;
2107 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2109 if (picochip_reg_needs_saving (i
))
2112 /* If this register is an even numbered register, and the
2113 next register also needs to be saved, use a SImode save,
2114 which does both in one instruction. Note that a special
2115 check is performed to ensure that the double word aligned
2116 store is valid (e.g., it is possible that r6, r8, r9 need
2117 to be saved, in which case once r6 has been saved, the
2118 stored offset is no longer aligned, and an STL/LDL
2119 instruction becomes invalid). We could store all aligned
2120 registers first, and then save the single one(s). */
2122 picochip_reg_needs_saving (i
+ 1) &&
2123 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2125 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2126 general_save_offset
+
2128 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2133 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2134 general_save_offset
+
2136 reg_save_offset
+= UNITS_PER_WORD
;
2142 /* Emit a return instruction, which matches a (parallel
2143 [(return) (use r12)]) */
2146 p
= rtvec_alloc (2);
2148 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
2149 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2150 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2151 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2156 /* Assembly instruction output. */
2158 /* Test whether the given branch instruction is short, or long. Short
2159 * branches are equivalent to real branches, and may be DFA
2160 * scheduled. Long branches expand to a macro which is handled by the
2161 * elaborator, and cannot be scheduled. Occasionally, the branch
2162 * shortening pass, which is run after DFA scheduling, will change the
2163 * code layout and cause the short branch to be reverted into a long
2164 * branch. Instead of having to fix this up by emitting new assembly,
2165 * the short branch is emitted anyway. There is plenty of slack in the
2166 * calculation of long and short branches (10-bit offset, but only
2167 * 9-bits used in computation), so there is enough slack for this to
2170 picochip_is_short_branch (rtx insn
)
2172 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2174 return (isRealShortBranch
||
2175 (!isRealShortBranch
&&
2176 picochip_current_vliw_state
.num_insns_in_packet
> 1));
2179 /* Output a compare-and-branch instruction (matching the cbranch
2182 picochip_output_cbranch (rtx operands
[])
2185 if (HImode
!= GET_MODE (operands
[1]) ||
2186 (HImode
!= GET_MODE (operands
[2]) &&
2187 GET_CODE (operands
[2]) != CONST_INT
))
2189 internal_error ("%s: At least one operand can't be handled",
2193 /* Use the type of comparison to output the appropriate condition
2195 switch (GET_CODE (operands
[0]))
2198 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2201 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2204 /* Reverse the operand order to be GE */
2205 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2208 /* Reverse operand order of GEU. */
2209 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2212 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2215 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2218 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2221 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2224 /* Reversed operand version of LT. */
2225 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2228 /* Reverse an LTU. */
2229 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2236 /* Output a compare-and-branch instruction (matching the cbranch
2237 pattern). This function is current unused since the cbranch
2238 split is disabled. The function is kept around so we can use
2239 it when we understand how to do cbranch split safely. */
2241 picochip_output_compare (rtx operands
[])
2244 if (HImode
!= GET_MODE (operands
[1]) ||
2245 (HImode
!= GET_MODE (operands
[2]) &&
2246 GET_CODE (operands
[2]) != CONST_INT
))
2248 internal_error ("%s: At least one operand can't be handled",
2252 /* Use the type of comparison to output the appropriate condition
2254 int code
= GET_CODE (operands
[0]);
2258 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2261 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2264 /* Reverse the operand order to be GE */
2265 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2268 /* Reverse operand order of GEU. */
2269 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2272 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2275 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2278 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2281 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2284 /* Reversed operand version of LT. */
2285 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2288 /* Reverse an LTU. */
2289 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2296 /* Output the branch insn part of a compare-and-branch split. */
2298 picochip_output_branch (rtx operands
[], rtx insn
)
2301 int code
= GET_CODE(operands
[2]);
2302 if (picochip_is_short_branch (insn
))
2304 /* Short branches can be output directly using the
2305 appropriate instruction. */
2309 return ("BNE %l0 %>");
2311 return ("BEQ %l0 %>");
2313 return ("BGE %l0 %>");
2315 return ("BHS %l0 %>");
2317 return ("BGE %l0 %>");
2319 return ("BHS %l0 %>");
2321 return ("BLT %l0 %>");
2323 return ("BLO %l0 %>");
2325 return ("BLT %l0 %>");
2327 return ("BLO %l0 %>");
2329 internal_error ("Unknown short branch in %s (type %d)\n",
2330 __FUNCTION__
, (int) INTVAL (operands
[1]));
2331 return "UNKNOWN_BRANCH";
2336 /* Long branches result in the emission of a special
2337 instruction, which the assembler expands into a suitable long
2340 /* Use the type of comparison to output the appropriate condition
2345 return ("JMPNE %l0 %>");
2347 return ("JMPEQ %l0 %>");
2349 return ("JMPGE %l0 %>");
2351 return ("JMPHS %l0 %>");
2353 return ("JMPGE %l0 %>");
2355 return ("JMPHS %l0 %>");
2357 return ("JMPLT %l0 %>");
2359 return ("JMPLO %l0 %>");
2361 return ("JMPLT %l0 %>");
2363 return ("JMPLO %l0 %>");
2366 internal_error ("Unknown long branch in %s (type %d)\n",
2367 __FUNCTION__
, (int) INTVAL (operands
[1]));
2368 return "UNKNOWN_BRANCH";
2374 /* Output a jump instruction. */
2376 picochip_output_jump (rtx insn
)
2378 if (picochip_is_short_branch (insn
))
2381 return "JMPRA %l0%>";
2385 picochip_output_put_array (int alternative
, rtx operands
[])
2387 /* Local output buffer. */
2390 int portArraySize
= INTVAL(operands
[1]);
2391 int portBaseIndex
= INTVAL(operands
[2]);
2393 if (alternative
== 0)
2395 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2396 portArraySize
, portBaseIndex
);
2397 output_asm_insn (buf
, operands
);
2399 else if (alternative
== 1)
2401 /* Constant port id. Emit a real instruction. */
2402 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2403 if (portIndex
< portBaseIndex
||
2404 portIndex
>= (portBaseIndex
+ portArraySize
))
2406 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2407 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2409 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2410 output_asm_insn (buf
, operands
);
2415 /* Both alternatives output the insn directly. */
2419 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2421 /* Local output buffer. */
2424 int portArraySize
= INTVAL(operands
[1]);
2425 int portBaseIndex
= INTVAL(operands
[2]);
2427 if (alternative
== 0)
2429 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2430 portArraySize
, portBaseIndex
);
2431 output_asm_insn (buf
, operands
);
2433 else if (alternative
== 1)
2435 /* Constant port id. Emit a real instruction. */
2436 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2437 if (portIndex
< portBaseIndex
||
2438 portIndex
>= (portBaseIndex
+ portArraySize
))
2440 error ("GET uses port array index %d, which is out of range [%d..%d)",
2441 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2443 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2444 output_asm_insn (buf
, operands
);
2449 /* Both alternatives output the insn directly. */
2453 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2455 /* Local output buffer. */
2458 int portArraySize
= INTVAL(operands
[2]);
2459 int portBaseIndex
= INTVAL(operands
[3]);
2461 if (alternative
== 0)
2463 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2464 portArraySize
, portBaseIndex
);
2465 output_asm_insn (buf
, operands
);
2467 else if (alternative
== 1)
2469 /* Constant port id. Emit a real instruction. */
2470 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2471 if (portIndex
< portBaseIndex
||
2472 portIndex
>= (portBaseIndex
+ portArraySize
))
2474 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2475 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2477 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2478 output_asm_insn (buf
, operands
);
2483 /* Both alternatives output the insn directly. */
2487 /* Output a comparison operand as a symbol (e.g., >). */
2489 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2494 /* Output just the comparison symbol. */
2495 switch (GET_CODE (operand
))
2498 fprintf (file
, "!=");
2501 fprintf (file
, "==");
2504 fprintf (file
, ">=");
2507 fprintf (file
, ">={U}");
2510 fprintf (file
, "<");
2513 fprintf (file
, "<{U}");
2516 fprintf (file
, "<=");
2519 fprintf (file
, "<={U}");
2522 fprintf (file
, ">");
2525 fprintf (file
, ">{U}");
2533 /* Output the comparison formatted as operand,symbol,operand */
2534 rtx op0
= XEXP (operand
, 0);
2535 rtx op1
= XEXP (operand
, 1);
2537 picochip_print_operand (file
, op0
, 0);
2538 picochip_print_comparison (file
, operand
, 'i');
2539 picochip_print_operand (file
, op1
, 0);
2543 /* This function generates a memory address operand in the given
2544 mode. That is, if the address contains a constant offset, then the
2545 offset is divided by the required mode size to compute the
2546 mode specific offset. By default, picochip_print_operand_address calls
2547 this function using the natural mode of the operand, but special
2548 operand codes can be used to invoke the computation using an
2549 unnatural mode (e.g., compute the HI aligned address of an SI mode
2552 picochip_print_memory_address (FILE * file
, rtx operand
,
2553 enum machine_mode mode
)
2555 rtx address
= XEXP (operand
, 0);
2558 if (MEM
!= GET_CODE (operand
))
2559 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2564 printf ("picochip_print_memory_address: ");
2565 print_rtl (stdout
, operand
);
2569 switch (GET_CODE (address
))
2573 /* Grab the address components. */
2574 rtx base
= XEXP (address
, 0);
2575 rtx offset
= XEXP (address
, 1);
2577 /* Only handle reg+const addresses */
2578 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2580 /* Sanity check. If an FP+offset address is given, ensure
2581 that the offset lies within the given frame, or a lower
2583 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2584 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2587 /* Print the base register - identical for all modes. */
2588 fprintf (file
, "(");
2589 picochip_print_operand (file
, base
, 'r');
2590 fprintf (file
, ")");
2592 /* Print the constant offset with compensation for the mode. */
2596 picochip_print_operand (file
, offset
, 'Q');
2600 picochip_print_operand (file
, offset
, 'H');
2605 picochip_print_operand (file
, offset
, 'S');
2609 picochip_print_operand (file
, offset
, 'D');
2623 picochip_print_operand (file
, address
, 's');
2632 inner
= XEXP (address
, 0);
2634 /* Sanity check - the CONST memory address must be a base+offset. */
2635 gcc_assert (PLUS
== GET_CODE (inner
));
2637 base
= XEXP (inner
, 0);
2638 offset
= XEXP (inner
, 1);
2640 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2646 /* Register operand. Provide a zero offset. */
2647 fprintf (file
, "(");
2648 picochip_print_operand (file
, address
, 'r');
2649 fprintf (file
, ")0");
2658 /* Output an operand. Formatting letters allow particular parts of
2659 the operand to be output. */
2661 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2664 /* Handle special cases. */
2667 /* VLIW continuation, for explicit VLIW sequences. */
2669 fprintf (file
, "\\");
2674 fputc (picochip_get_vliw_alu_id (), file
);
2677 /* Delay slot specifier. */
2679 /* This should be handled in asm_output_opcode. */
2682 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2684 switch (GET_CODE (operand
))
2687 fprintf (file
, "AND");
2690 fprintf (file
, "OR");
2693 fprintf (file
, "XOR");
2696 fprintf (file
, "ADD");
2699 fprintf (file
, "SUB");
2706 /* Symbolic instructions (e.g., lshift becomes <<). */
2708 switch (GET_CODE (operand
))
2711 fprintf (file
, "&");
2714 fprintf (file
, "|");
2717 fprintf (file
, "^");
2720 fprintf (file
, "+");
2723 fprintf (file
, "-");
2726 fprintf (file
, "UNKNOWN_INSN");
2731 default: /* Not a punctuation character - process as normal. */
2735 switch (GET_CODE (operand
))
2741 /* Write a range of registers. */
2742 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2746 /* The upper register of a pair is requested. */
2747 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2751 /* The lower register of a pair is requested. Equivalent to the
2752 default, but included for completeness. */
2753 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2757 /* The 3rd register of a DI mode register. */
2758 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2762 /* The 4th register of a DI mode register. */
2763 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2767 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2772 /* A range of letters can be used to format integers. The
2773 letters Q/H/S are used to divide the constant by the width of
2774 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2775 to obtain the upper and lower 16-bits of a 32-bit
2776 constant. Where possible, signed numbers are used, since
2777 signed representations of numbers may be more compact (e.g.,
2778 65535 can be represented as -1, which fits into a small
2779 constant, whereas 65535 requires a large constant). */
2783 fprintf (file
, "%ld", INTVAL (operand
));
2787 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2791 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2795 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2799 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2803 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2807 fprintf (file
, "%ld", INTVAL (operand
));
2817 if (GET_MODE (operand
) != SFmode
)
2818 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2820 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2821 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2826 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2830 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2838 /* Output a symbol. The output format must match that of
2839 picochip_output_label. */
2841 /* Ensure that the symbol is marked as referenced. Gcc can
2842 occasionally omit the function bodies when it believes them
2843 to be unreferenced. */
2844 if (SYMBOL_REF_DECL (operand
))
2845 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2846 fprintf (file
, "&");
2847 assemble_name (file
, XSTR (operand
, 0));
2851 /* This format must match that of picochip_output_label. */
2852 fprintf (file
, "&");
2853 output_asm_label (operand
);
2858 rtx addr
= XEXP (operand
, 0);
2863 if (PLUS
!= GET_CODE (addr
))
2864 fatal_insn ("Bad address, not (reg+disp):", addr
);
2866 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2870 /* Output a memory address in byte mode notation (i.e., the
2871 constant address (if any) is the actual byte address. */
2872 picochip_print_memory_address (file
, operand
, QImode
);
2875 /* Output a constant offset of the given mode (i.e., divide
2876 the constant by the number of units in the mode to get the
2879 picochip_print_memory_address (file
, operand
, QImode
);
2883 picochip_print_memory_address (file
, operand
, HImode
);
2887 picochip_print_memory_address (file
, operand
, SImode
);
2891 picochip_print_memory_address (file
, operand
, SFmode
);
2895 if (PLUS
!= GET_CODE (addr
))
2896 fatal_insn ("Bad address, not (reg+disp):", addr
);
2898 picochip_print_operand (file
, XEXP (addr
, 0), 0);
2901 /* When the mem operand is (reg + big offset) which cannot
2902 be represented in an instruction as operand, the compiler
2903 automatically generates the instruction to put in (reg +
2904 big offset) into another register. In such cases, it
2905 returns '0' as the character. This needs to be handled
2909 if (REG
!= GET_CODE (addr
))
2910 fatal_insn ("Bad address, not register:", addr
);
2912 picochip_print_operand (file
, addr
, 0);
2916 fprintf (file
, "Unknown mem operand - letter %c ",
2918 print_rtl (file
, operand
);
2926 rtx const_exp
= XEXP (operand
, 0);
2928 /* Handle constant offsets to symbol references. */
2929 if (PLUS
== GET_CODE (const_exp
) &&
2930 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
2931 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
2934 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
2935 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
2936 fprintf (file
, "+");
2937 /* else use the - from the operand (i.e., AP-2)) */
2939 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
2948 /* PLUS expressions are of the form (base + offset). Different
2949 options (analagous to those of memory PLUS expressions) are used
2950 to extract the base and offset components. */
2955 picochip_print_operand (file
, XEXP (operand
, 0), 0);
2959 picochip_print_operand (file
, XEXP (operand
, 1), 0);
2964 /* If the expression is composed entirely of constants,
2965 evaluate the result. This should only occur with the
2966 picoChip specific comms instructions, which are emitted as
2967 base+offset expressions. */
2968 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
2969 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
2971 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
2972 XINT (XEXP (operand
, 1), 0));
2973 fprintf (file
, "%ld", result
);
2977 fprintf (file
, "(");
2978 picochip_print_operand (file
, XEXP (operand
, 0), 0);
2979 fprintf (file
, "+");
2980 picochip_print_operand (file
, XEXP (operand
, 1), 0);
2981 fprintf (file
, ")");
2988 /* Comparison operations. */
2999 picochip_print_comparison (file
, operand
, letter
);
3003 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3004 print_rtl (file
, operand
);
3011 /* Output an operand address */
3013 picochip_print_operand_address (FILE * file
, rtx operand
)
3016 switch (GET_CODE (operand
))
3020 /* This format must match that of picochip_output_label. */
3021 assemble_name (file
, XSTR (operand
, 0));
3025 /* Note this format must match that of picochip_output_label. */
3026 fprintf (file
, "_L%d", XINT (operand
, 5));
3030 /* Pass on to a specialised memory address generator. */
3031 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3042 /* Scheduling functions. */
3044 /* Save some of the contents of recog_data. */
3046 picochip_save_recog_data (void)
3048 picochip_saved_which_alternative
= which_alternative
;
3049 memcpy (&picochip_saved_recog_data
, &recog_data
,
3050 sizeof (struct recog_data
));
3053 /* Restore some of the contents of global variable recog_data. */
3055 picochip_restore_recog_data (void)
3057 which_alternative
= picochip_saved_which_alternative
;
3058 memcpy (&recog_data
, &picochip_saved_recog_data
,
3059 sizeof (struct recog_data
));
3062 /* Ensure that no var tracking notes are emitted in the middle of a
3063 three-instruction bundle. */
3065 reorder_var_tracking_notes (void)
3071 rtx queue
= NULL_RTX
;
3073 for (insn
= BB_HEAD (bb
); insn
!= BB_END (bb
); insn
= next
)
3075 next
= NEXT_INSN (insn
);
3077 if (NONDEBUG_INSN_P (insn
))
3079 /* Emit queued up notes before the first instruction of a bundle. */
3080 if (GET_MODE (insn
) == TImode
)
3084 rtx next_queue
= PREV_INSN (queue
);
3085 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3086 PREV_INSN (queue
) = PREV_INSN(insn
);
3087 PREV_INSN (insn
) = queue
;
3088 NEXT_INSN (queue
) = insn
;
3093 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
3095 rtx prev
= PREV_INSN (insn
);
3096 PREV_INSN (next
) = prev
;
3097 NEXT_INSN (prev
) = next
;
3098 PREV_INSN (insn
) = queue
;
3105 /* Perform machine dependent operations on the rtl chain INSNS. */
3107 picochip_reorg (void)
3109 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3110 int vliw_insn_location
= 0;
3112 /* We are freeing block_for_insn in the toplev to keep compatibility
3113 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3114 compute_bb_for_insn ();
3119 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3121 timevar_push (TV_SCHED2
);
3123 /* Process the instruction list, computing the sizes of each
3124 instruction, and consequently branch distances. This can
3125 result in some branches becoming short enough to be treated
3126 as a real branch instruction, rather than an assembly branch
3127 macro which may expand into multiple instructions. The
3128 benefit of shortening branches is that real branch
3129 instructions can be properly DFA scheduled, whereas macro
3131 shorten_branches (get_insns ());
3133 /* Do control and data sched analysis again,
3134 and write some more of the results to dump file. */
3140 timevar_pop (TV_SCHED2
);
3144 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3146 /* Whenever a VLIW packet is generated, all instructions in
3147 that packet must appear to come from the same source
3148 location. The following code finds all the VLIW packets,
3149 and tags their instructions with the location of the first
3150 instruction from the packet. Clearly this will result in
3151 strange behaviour when debugging the code, but since
3152 debugging and optimisation are being used in conjunction,
3153 strange behaviour is certain to occur anyway. */
3154 /* Slight bit of change. If the vliw set contains a branch
3155 or call instruction, we pick its location.*/
3156 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3159 /* If this is the first instruction in the VLIW packet,
3160 extract its location. */
3161 if (GET_MODE (insn
) == TImode
)
3164 vliw_insn_location
= INSN_LOCATOR (insn
);
3166 if (JUMP_P (insn
) || CALL_P(insn
))
3168 vliw_insn_location
= INSN_LOCATOR (insn
);
3169 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3170 INSN_LOCATOR (insn1
) = vliw_insn_location
;
3172 /* Tag subsequent instructions with the same location. */
3173 INSN_LOCATOR (insn
) = vliw_insn_location
;
3179 /* Locate the note marking the end of the function's prologue. If
3180 the note appears in the middle of a VLIW packet, move the note to
3181 the end. This avoids unpleasant consequences such as trying to
3182 emit prologue markers (e.g., .loc/.file directives) in the middle
3184 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3186 rtx prologue_end_note
= NULL
;
3187 rtx last_insn_in_packet
= NULL
;
3189 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3191 /* The prologue end must be moved to the end of the VLIW packet. */
3192 if (NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3194 prologue_end_note
= insn
;
3199 /* Find the last instruction in this packet. */
3200 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3202 if (GET_MODE (insn
) == TImode
)
3205 last_insn_in_packet
= insn
;
3208 if (last_insn_in_packet
!= NULL
)
3210 rtx tmp_note
= emit_note_after (NOTE_KIND(prologue_end_note
), last_insn_in_packet
);
3211 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3212 delete_insn (prologue_end_note
);
3215 if (picochip_flag_var_tracking
)
3217 timevar_push (TV_VAR_TRACKING
);
3218 variable_tracking_main ();
3219 /* We also have to deal with variable tracking notes in the middle
3221 reorder_var_tracking_notes();
3222 timevar_pop (TV_VAR_TRACKING
);
3226 /* Return the ALU character identifier for the current
3227 instruction. This will be 0 or 1. */
3229 picochip_get_vliw_alu_id (void)
3233 /* Always use ALU 0 if VLIW scheduling is disabled. */
3234 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3237 /* Get the attribute type of the instruction. Note that this can
3238 ruin the contents of recog_data, so save/restore around the
3240 picochip_save_recog_data ();
3241 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3242 picochip_restore_recog_data ();
3244 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3247 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3248 else it must be the other ALU (either basic or nonCc)
3249 instruction which goes into 1. */
3250 if (attr_type
== TYPE_PICOALU
)
3256 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3258 /* Is this the non CC instruction? If it is, then stuff it into
3259 ALU 1, else it must be a picoAlu or basicAlu, in which case
3260 it goes into ALU 0. */
3261 if (attr_type
== TYPE_NONCCALU
)
3268 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3269 whether an ALU instruction has already been scheduled in this
3271 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3274 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3278 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3282 internal_error ("Too many ALU instructions emitted (%d)\n",
3283 picochip_current_vliw_state
.num_alu_insns_so_far
);
3290 /* Reset any information about the current VLIW packing status. */
3292 picochip_reset_vliw (rtx insn
)
3294 rtx local_insn
= insn
;
3296 /* Nothing to do if VLIW scheduling isn't being used. */
3297 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3301 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3304 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3305 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3306 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3307 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3308 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3309 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3311 /* Read through the VLIW packet, classifying the instructions where
3316 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3318 local_insn
= NEXT_INSN (local_insn
);
3321 else if (!INSN_P (local_insn
))
3325 /* It is an instruction, but is it ours? */
3326 if (INSN_CODE (local_insn
) != -1)
3330 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3332 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3333 get_attr_type function can overwrite the values in
3334 the recog_data global, hence this is saved and
3335 restored around the call. Not doing so results in
3336 asm_output_opcode being called with a different
3337 instruction to final_prescan_insn, which is fatal. */
3338 picochip_save_recog_data ();
3339 attr_type
= get_attr_type (local_insn
);
3340 picochip_restore_recog_data ();
3342 if (attr_type
== TYPE_PICOALU
)
3343 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3344 if (attr_type
== TYPE_NONCCALU
)
3345 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3350 /* Get the next instruction. */
3351 local_insn
= NEXT_INSN (local_insn
);
3353 /* Keep going while the next instruction is part of the same
3354 VLIW packet (i.e., its a valid instruction and doesn't mark
3355 the start of a new VLIW packet. */
3357 while (local_insn
&&
3358 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3363 picochip_sched_reorder (FILE * file
, int verbose
,
3364 rtx
* ready ATTRIBUTE_UNUSED
,
3365 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3369 fprintf (file
, ";;\tClock %d\n", clock
);
3371 return picochip_sched_issue_rate ();
3376 picochip_sched_lookahead (void)
3378 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3384 picochip_sched_issue_rate (void)
3389 /* Adjust the scheduling cost between the two given instructions,
3390 which have the given dependency. */
3392 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3397 printf ("Sched Adjust Cost: %d->%d is %d\n",
3398 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3400 printf (" Dependency type:");
3401 switch (REG_NOTE_KIND (link
))
3409 case REG_DEP_OUTPUT
:
3410 printf ("OUTPUT\n");
3413 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3417 /* Anti-dependencies are used to enforce the ordering between a
3418 * branch, and any subsequent instructions. For example:
3423 * The ADD instruction must execute after the branch, and this is
3424 * enforced using an anti-dependency. Unfortunately, VLIW machines
3425 * are happy to execute anti-dependent instructions in the same
3426 * cycle, which then results in a schedule like the following being
3429 * BNE someLabel \ ADD.0 r0,r1,r2
3431 * The instruction which would normally be conditionally executed
3432 * depending upon the outcome of the branch, is now unconditionally
3433 * executed every time. To prevent this happening, any
3434 * anti-dependencies between a branch and another instruction are
3435 * promoted to become real dependencies.
3437 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3441 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3442 INSN_UID (insn
), INSN_UID (dep_insn
));
3451 /* Return the minimum of the two values */
3453 minimum (int a
, int b
)
3459 /* I dont expect to get to this function with a==b.*/
3464 /* This function checks if the memory of the two stores are just off by 2 bytes.
3465 It returns the lower memory operand's index.*/
3468 memory_just_off (rtx opnd1
, rtx opnd2
)
3470 int offset1
= 0, offset2
= 0;
3473 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3475 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3476 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3480 reg1
= REGNO(XEXP(opnd1
, 0));
3482 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3484 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3485 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3489 reg2
= REGNO(XEXP(opnd2
, 0));
3492 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3493 should be 4 byte aligned. We can currently guarentee that only if the base
3494 address is FP(R13) and the offset is aligned. */
3496 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3497 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3503 registers_just_off (rtx opnd1
, rtx opnd2
)
3506 reg1
= REGNO(opnd1
);
3507 reg2
= REGNO(opnd2
);
3508 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3509 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3513 /* Check to see if the two LDWs can be peepholed together into a LDL
3514 They can be if the registers getting loaded into are contiguous
3515 and the memory addresses are contiguous as well.
3519 can be merged together into
3523 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3524 aligned address. Only FP can be assumed to be 4 byte aligned.
3525 2. The progression of addresses and the register numbers should
3526 be similar. For eg., if you swap r2 and r3 in the above instructions,
3527 the resultant pair cannot be merged.
3531 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3533 int memtest
=0,regtest
=0;
3534 regtest
= registers_just_off(opnd1
,opnd3
);
3538 memtest
= memory_just_off(opnd0
,opnd2
);
3542 if (regtest
== memtest
)
3549 /* Similar to LDW peephole */
3551 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3553 int memtest
=0,regtest
=0;
3554 regtest
= registers_just_off(opnd1
,opnd3
);
3558 memtest
= memory_just_off(opnd0
,opnd2
);
3562 if (regtest
== memtest
)
3570 /* Generate a SImode register with the register number that is the smaller of the two */
3572 gen_min_reg(rtx opnd1
,rtx opnd2
)
3574 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3577 /* Generate a SImode memory with the address that is the smaller of the two */
3579 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3581 int offset1
=0,offset2
=0;
3583 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3585 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3586 reg
= XEXP(XEXP(opnd1
,0),0);
3590 reg
= XEXP(opnd1
,0);
3592 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3594 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3596 rtx address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3597 return gen_rtx_MEM(SImode
,address
);
3601 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3608 /* Need to penalize immediates that need to be encoded as long constants.*/
3609 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3611 *total
= COSTS_N_INSNS(1);
3619 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3624 /* if_then_else come out of cbranch instructions. It will get split into
3625 a condition code generating subtraction and a branch */
3626 *total
= COSTS_N_INSNS (2);
3633 if (GET_MODE(x
) == SImode
)
3634 *total
= COSTS_N_INSNS (2);
3635 if (GET_MODE(x
) == DImode
)
3636 *total
= COSTS_N_INSNS (4);
3640 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3641 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3642 *total
= COSTS_N_INSNS (10);
3644 /* 64-bit accesses have to be done through 2 32-bit access */
3645 if (GET_MODE(x
) == DImode
)
3646 *total
= COSTS_N_INSNS (2);
3652 /* SImode shifts are expensive */
3653 if (GET_MODE(x
) == SImode
)
3654 *total
= COSTS_N_INSNS (10);
3656 /* Register shift by constant is cheap. */
3657 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3658 && GET_CODE(XEXP(x
, 0)) == REG
3659 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3660 *total
= COSTS_N_INSNS (1);
3662 *total
= COSTS_N_INSNS (4);
3669 /* Divisions are more expensive than the default 7*/
3670 if (GET_MODE(x
) == SImode
)
3671 *total
= COSTS_N_INSNS (20);
3673 *total
= COSTS_N_INSNS (12);
3678 /* Look for the simple cases of multiplying register*register or
3679 register*constant. */
3680 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3681 && ((GET_CODE(XEXP(x
, 0)) == REG
3682 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3683 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3684 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3685 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3686 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3689 /* When optimising for size, multiplication by constant
3690 should be discouraged slightly over multiplication by a
3692 if (picochip_has_mac_unit
)
3694 /* Single cycle multiplication, but the result must be
3695 loaded back into a general register afterwards. */
3696 *total
= COSTS_N_INSNS(2);
3699 else if (picochip_has_mul_unit
)
3701 /* Single cycle multiplication. */
3702 *total
= COSTS_N_INSNS(1);
3705 /* Else no multiply available. Use default cost. */
3715 if (localTotal
!= 0)
3717 *total
= localTotal
;
3728 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3729 int num_operands ATTRIBUTE_UNUSED
)
3733 picochip_current_prescan_insn
= insn
;
3736 printf ("Final prescan on INSN %d with mode %s\n",
3737 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3739 /* If this is the start of a new instruction cycle, or no scheduling
3740 is used, then reset the VLIW status. */
3741 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3742 picochip_reset_vliw (insn
);
3744 /* No VLIW scheduling occured, so don't go any further. */
3745 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3748 /* Look for the next printable instruction. This loop terminates on
3749 any recognisable instruction, and on any unrecognisable
3750 instruction with TImode. */
3752 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3753 local_insn
= NEXT_INSN (local_insn
))
3755 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3757 else if (!INSN_P (local_insn
))
3759 else if (GET_MODE (local_insn
) == TImode
3760 || INSN_CODE (local_insn
) != -1)
3764 /* Set the continuation flag if the next instruction can be packed
3765 with the current instruction (i.e., the next instruction is
3766 valid, and isn't the start of a new cycle). */
3767 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3768 (GET_MODE (local_insn
) != TImode
));
3772 /* Builtin functions. */
3773 /* Given a builtin function taking 2 operands (i.e., target + source),
3774 emit the RTL for the underlying instruction. */
3776 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3780 enum machine_mode tmode
, mode0
;
3782 /* Grab the incoming argument and emit its RTL. */
3783 arg0
= CALL_EXPR_ARG (call
, 0);
3784 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3786 /* Determine the modes of the instruction operands. */
3787 tmode
= insn_data
[icode
].operand
[0].mode
;
3788 mode0
= insn_data
[icode
].operand
[1].mode
;
3790 /* Ensure that the incoming argument RTL is in a register of the
3792 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3793 op0
= copy_to_mode_reg (mode0
, op0
);
3795 /* If there isn't a suitable target, emit a target register. */
3797 || GET_MODE (target
) != tmode
3798 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3799 target
= gen_reg_rtx (tmode
);
3801 /* Emit and return the new instruction. */
3802 pat
= GEN_FCN (icode
) (target
, op0
);
3811 /* Given a builtin function taking 3 operands (i.e., target + two
3812 source), emit the RTL for the underlying instruction. */
3814 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3818 enum machine_mode tmode
, mode0
, mode1
;
3820 /* Grab the function's arguments. */
3821 arg0
= CALL_EXPR_ARG (call
, 0);
3822 arg1
= CALL_EXPR_ARG (call
, 1);
3824 /* Emit rtl sequences for the function arguments. */
3825 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3826 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3828 /* Get the mode's of each of the instruction operands. */
3829 tmode
= insn_data
[icode
].operand
[0].mode
;
3830 mode0
= insn_data
[icode
].operand
[1].mode
;
3831 mode1
= insn_data
[icode
].operand
[2].mode
;
3833 /* Ensure that each of the function argument rtl sequences are in a
3834 register of the correct mode. */
3835 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3836 op0
= copy_to_mode_reg (mode0
, op0
);
3837 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3838 op1
= copy_to_mode_reg (mode1
, op1
);
3840 /* If no target has been given, create a register to use as the target. */
3842 || GET_MODE (target
) != tmode
3843 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3844 target
= gen_reg_rtx (tmode
);
3846 /* Emit and return the new instruction. */
3847 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
3856 /* Expand a builtin function which takes two arguments, and returns a void. */
3858 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
3862 enum machine_mode mode0
, mode1
;
3864 /* Grab the function's arguments. */
3865 arg0
= CALL_EXPR_ARG (call
, 0);
3866 arg1
= CALL_EXPR_ARG (call
, 1);
3868 /* Emit rtl sequences for the function arguments. */
3869 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3870 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3872 /* Get the mode's of each of the instruction operands. */
3873 mode0
= insn_data
[icode
].operand
[0].mode
;
3874 mode1
= insn_data
[icode
].operand
[1].mode
;
3876 /* Ensure that each of the function argument rtl sequences are in a
3877 register of the correct mode. */
3878 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
3879 op0
= copy_to_mode_reg (mode0
, op0
);
3880 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
3881 op1
= copy_to_mode_reg (mode1
, op1
);
3883 /* Emit and return the new instruction. */
3884 pat
= GEN_FCN (icode
) (op0
, op1
);
3893 /* Expand an array get into the corresponding RTL. */
3895 picochip_expand_array_get (tree call
, rtx target
)
3897 tree arg0
, arg1
, arg2
;
3898 rtx op0
, op1
, op2
, pat
;
3900 /* Grab the function's arguments. */
3901 arg0
= CALL_EXPR_ARG (call
, 0);
3902 arg1
= CALL_EXPR_ARG (call
, 1);
3903 arg2
= CALL_EXPR_ARG (call
, 2) ;
3905 /* Emit rtl sequences for the function arguments. */
3906 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3907 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3908 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
3910 /* The second and third operands must be constant. Nothing else will
3912 if (CONST_INT
!= GET_CODE (op1
))
3913 internal_error ("%s: Second source operand is not a constant",
3915 if (CONST_INT
!= GET_CODE (op2
))
3916 internal_error ("%s: Third source operand is not a constant",
3919 /* If no target has been given, create a register to use as the target. */
3920 if (target
== 0 || GET_MODE (target
) != SImode
)
3921 target
= gen_reg_rtx (SImode
);
3923 /* The first operand must be a HImode register or a constant. If it
3924 isn't, force it into a HImode register. */
3925 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
3926 op0
= copy_to_mode_reg (HImode
, op0
);
3929 /* Emit and return the new instruction. */
3930 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
3937 /* Expand an array put into the corresponding RTL. */
3939 picochip_expand_array_put (tree call
, rtx target
)
3941 tree arg0
, arg1
, arg2
, arg3
;
3942 rtx op0
, op1
, op2
, op3
, pat
;
3944 /* Grab the function's arguments. */
3945 arg0
= CALL_EXPR_ARG (call
, 0);
3946 arg1
= CALL_EXPR_ARG (call
, 1);
3947 arg2
= CALL_EXPR_ARG (call
, 2);
3948 arg3
= CALL_EXPR_ARG (call
, 3);
3950 /* Emit rtl sequences for the function arguments. */
3951 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3952 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3953 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
3954 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
3956 /* The first operand must be an SImode register. */
3957 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
3958 op0
= copy_to_mode_reg (SImode
, op0
);
3960 /* The second (index) operand must be a HImode register, or a
3961 constant. If it isn't, force it into a HImode register. */
3962 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
3963 op1
= copy_to_mode_reg (HImode
, op1
);
3965 /* The remaining operands must be constant. Nothing else will do. */
3966 if (CONST_INT
!= GET_CODE (op2
))
3967 internal_error ("%s: Third source operand is not a constant",
3969 if (CONST_INT
!= GET_CODE (op3
))
3970 internal_error ("%s: Fourth source operand is not a constant",
3973 /* Emit and return the new instruction. */
3974 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
3981 /* Expand an array testport into the corresponding RTL. */
3983 picochip_expand_array_testport (tree call
, rtx target
)
3985 tree arg0
, arg1
, arg2
;
3986 rtx op0
, op1
, op2
, pat
;
3988 /* Grab the function's arguments. */
3989 arg0
= CALL_EXPR_ARG (call
, 0);
3990 arg1
= CALL_EXPR_ARG (call
, 1);
3991 arg2
= CALL_EXPR_ARG (call
, 2);
3993 /* Emit rtl sequences for the function arguments. */
3994 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3995 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3996 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
3998 /* The first operand must be a HImode register, or a constant. If it
3999 isn't, force it into a HImode register. */
4000 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4001 op0
= copy_to_mode_reg (HImode
, op0
);
4003 /* The second and third operands must be constant. Nothing else will
4005 if (CONST_INT
!= GET_CODE (op1
))
4006 internal_error ("%s: Second source operand is not a constant",
4008 if (CONST_INT
!= GET_CODE (op2
))
4009 internal_error ("%s: Third source operand is not a constant",
4012 /* If no target has been given, create a HImode register to use as
4014 if (target
== 0 || GET_MODE (target
) != HImode
)
4015 target
= gen_reg_rtx (HImode
);
4017 /* Emit and return the new instruction. */
4018 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4025 /* Generate a unique HALT instruction by giving the instruction a
4026 unique integer. This integer makes no difference to the assembly
4027 output (other than a comment indicating the supplied id), but the
4028 presence of the unique integer prevents the compiler from combining
4029 several different halt instructions into one instruction. This
4030 means that each use of the halt instruction is unique, which in
4031 turn means that assertions work as expected. */
4033 picochip_generate_halt (void)
4035 static int currentId
= 0;
4036 rtx id
= GEN_INT (currentId
);
4040 emit_insn (gen_halt (id
));
4042 /* A barrier is inserted to prevent the compiler from thinking that
4043 it has to continue execution after the HALT.*/
4046 rtx insns
= get_insns();
4053 /* Initialise the builtin functions. Start by initialising
4054 descriptions of different types of functions (e.g., void fn(int),
4055 int fn(void)), and then use these to define the builtins. */
4057 picochip_init_builtins (void)
4059 tree endlink
= void_list_node
;
4060 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
4061 tree unsigned_endlink
= tree_cons (NULL_TREE
, unsigned_type_node
, endlink
);
4062 tree long_endlink
= tree_cons (NULL_TREE
, long_integer_type_node
, endlink
);
4063 tree int_int_endlink
=
4064 tree_cons (NULL_TREE
, integer_type_node
, int_endlink
);
4065 tree int_int_int_endlink
=
4066 tree_cons (NULL_TREE
, integer_type_node
, int_int_endlink
);
4067 tree int_long_endlink
=
4068 tree_cons (NULL_TREE
, integer_type_node
, long_endlink
);
4069 tree pchar_type_node
= build_pointer_type (char_type_node
);
4070 tree long_int_int_int_endlink
=
4071 tree_cons (NULL_TREE
, long_integer_type_node
, int_int_int_endlink
);
4073 tree int_ftype_void
, int_ftype_int
, int_ftype_int_int
, void_ftype_pchar
;
4074 tree long_ftype_int
, long_ftype_int_int
, long_ftype_int_int_int
;
4075 tree void_ftype_int_long
, int_ftype_int_int_int
,
4076 void_ftype_long_int_int_int
;
4077 tree void_ftype_void
, void_ftype_int
, unsigned_ftype_unsigned
;
4079 /* void func (void) */
4080 void_ftype_void
= build_function_type (void_type_node
, endlink
);
4082 /* void func (void *) */
4084 = build_function_type (void_type_node
,
4085 tree_cons (NULL_TREE
, pchar_type_node
, endlink
));
4087 /* int func (void) */
4088 int_ftype_void
= build_function_type (integer_type_node
, endlink
);
4090 /* void func (int) */
4091 void_ftype_int
= build_function_type (void_type_node
, int_endlink
);
4093 /* int func (int) */
4094 int_ftype_int
= build_function_type (integer_type_node
, int_endlink
);
4096 /* unsigned int func (unsigned int) */
4097 unsigned_ftype_unsigned
= build_function_type (unsigned_type_node
, unsigned_endlink
);
4099 /* int func(int, int) */
4101 = build_function_type (integer_type_node
, int_int_endlink
);
4103 /* long func(int) */
4104 long_ftype_int
= build_function_type (long_integer_type_node
, int_endlink
);
4106 /* long func(int, int) */
4108 = build_function_type (long_integer_type_node
, int_int_endlink
);
4110 /* long func(int, int, int) */
4111 long_ftype_int_int_int
4112 = build_function_type (long_integer_type_node
, int_int_int_endlink
);
4114 /* int func(int, int, int) */
4115 int_ftype_int_int_int
4116 = build_function_type (integer_type_node
, int_int_int_endlink
);
4118 /* void func(int, long) */
4120 = build_function_type (void_type_node
, int_long_endlink
);
4122 /* void func(long, int, int, int) */
4123 void_ftype_long_int_int_int
4124 = build_function_type (void_type_node
, long_int_int_int_endlink
);
4126 /* Initialise the sign-bit-count function. */
4127 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4128 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4130 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4131 BUILT_IN_MD
, NULL
, NULL_TREE
);
4133 /* Initialise the bit reverse function. */
4134 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4135 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4137 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4138 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4141 /* Initialise the byte swap function. */
4142 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4143 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4145 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4146 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4149 /* Initialise the ASRI function (note that while this can be coded
4150 using a signed shift in C, extra scratch registers are required,
4151 which we avoid by having a direct builtin to map to the
4153 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4154 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4157 /* Initialise saturating addition. */
4158 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4159 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4161 add_builtin_function ("picoAdds", int_ftype_int_int
,
4162 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4165 /* Initialise saturating subtraction. */
4166 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4167 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4169 add_builtin_function ("picoSubs", int_ftype_int_int
,
4170 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4173 /* Scalar comms builtins. */
4174 add_builtin_function ("__builtin_get", long_ftype_int
,
4175 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4177 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4178 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4180 add_builtin_function ("__builtin_testport", int_ftype_int
,
4181 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4184 /* Array comms builtins. */
4185 add_builtin_function ("__builtin_put_array",
4186 void_ftype_long_int_int_int
,
4187 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4189 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4190 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4192 add_builtin_function ("__builtin_testport_array",
4193 int_ftype_int_int_int
,
4194 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4197 /* Halt instruction. Note that the builtin function is marked as
4198 having the attribute `noreturn' so that the compiler realises
4199 that the halt stops the program dead. */
4200 tree noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4201 add_builtin_function ("__builtin_halt", void_ftype_void
,
4202 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4204 add_builtin_function ("picoHalt", void_ftype_void
,
4205 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4210 /* Expand a call to a builtin function. */
4212 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4213 enum machine_mode mode ATTRIBUTE_UNUSED
,
4214 int ignore ATTRIBUTE_UNUSED
)
4216 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4217 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4221 case PICOCHIP_BUILTIN_ASRI
:
4222 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4225 case PICOCHIP_BUILTIN_ADDS
:
4226 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4229 case PICOCHIP_BUILTIN_SUBS
:
4230 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4233 case PICOCHIP_BUILTIN_SBC
:
4234 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4236 case PICOCHIP_BUILTIN_BREV
:
4237 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4239 case PICOCHIP_BUILTIN_BYTESWAP
:
4240 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4242 case PICOCHIP_BUILTIN_GET
:
4243 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4245 case PICOCHIP_BUILTIN_PUT
:
4246 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4248 case PICOCHIP_BUILTIN_TESTPORT
:
4249 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4252 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4253 return picochip_expand_array_put (exp
, target
);
4255 case PICOCHIP_BUILTIN_GET_ARRAY
:
4256 return picochip_expand_array_get (exp
, target
);
4258 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4259 return picochip_expand_array_testport (exp
, target
);
4261 case PICOCHIP_BUILTIN_HALT
:
4262 return picochip_generate_halt ();
4269 /* Should really do something sensible here. */
4273 /* Emit warnings. */
4275 picochip_warn_inefficient (const char *msg
)
4277 if (TARGET_INEFFICIENT_WARNINGS
)
4278 warning (OPT_minefficient_warnings
,
4279 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4283 warn_of_byte_access (void)
4285 static int warned
= 0;
4289 picochip_warn_inefficient
4290 ("byte access is synthesised - consider using MUL AE");
4297 picochip_function_value (const_tree valtype
, const_tree func
,
4298 bool outgoing ATTRIBUTE_UNUSED
)
4300 enum machine_mode mode
= TYPE_MODE (valtype
);
4301 int unsignedp
= TYPE_UNSIGNED (valtype
);
4303 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4304 just as PROMOTE_MODE does. */
4305 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4307 return gen_rtx_REG (mode
, 0);
4311 /* Check that the value of the given mode will fit in the register of
4314 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4317 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4318 return regno
== CC_REGNUM
;
4320 /* If the CC register is being used, then only CC mode values are
4321 allowed (which have already been tested). */
4322 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4325 /* Must be a valid register. */
4329 /* Modes QI and HI may be placed in any register except the CC. */
4330 if (mode
== QImode
|| mode
== HImode
)
4333 /* DI must be in a quad register. */
4335 return (regno
% 4 == 0);
4337 /* All other modes must be placed in a even numbered register. */
4338 return !(regno
& 1);
4342 /* Extract the lower and upper components of a constant value. */
4345 picochip_get_low_const (rtx value
)
4347 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4351 picochip_get_high_const (rtx value
)
4353 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4354 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4358 /* Loading and storing QImode values to and from memory in a machine
4359 without byte access requires might require a scratch
4360 register. However, the scratch register might correspond to the
4361 register in which the value is being loaded. To ensure that a
4362 scratch register is supplied which is definitely different to the
4363 output register, request a register pair. This effectively gives a
4364 choice of two registers to choose from, so that we a guaranteed to
4365 get at least one register which is different to the output
4366 register. This trick is taken from the alpha implementation. */
4368 picochip_secondary_reload (bool in_p
,
4369 rtx x ATTRIBUTE_UNUSED
,
4370 enum reg_class cla ATTRIBUTE_UNUSED
,
4371 enum machine_mode mode
,
4372 secondary_reload_info
*sri
)
4374 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4377 sri
->icode
= CODE_FOR_reload_outqi
;
4379 sri
->icode
= CODE_FOR_reload_inqi
;
4382 /* We dont need to return a register class type when we need only a
4383 scratch register. It realizes the scratch register type by looking
4384 at the instruction definition for sri->icode. We only need to
4385 return the register type when we need intermediaries for copies.*/
4389 /* Return true if the given memory operand can be aligned to a
4390 word+offset memory reference (e.g., FP+3 can be converted into the
4391 memory operand FP+2, with the offset 1). */
4393 picochip_alignable_memory_operand (rtx mem_operand
,
4394 enum machine_mode mode ATTRIBUTE_UNUSED
)
4398 /* Not a mem operand. Refuse immediately. */
4399 if (MEM
!= GET_CODE (mem_operand
))
4402 address
= XEXP (mem_operand
, 0);
4404 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4405 return ((PLUS
== GET_CODE (address
) &&
4406 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4407 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4408 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4409 || (REG
== GET_CODE (address
)
4410 && REGNO (address
) == STACK_POINTER_REGNUM
));
4414 /* Return true if the given memory reference is to a word aligned
4415 address. Currently this means it must be either SP, or
4416 SP+offset. We could replace this function with alignable
4417 memory references in the above function?. */
4419 picochip_word_aligned_memory_reference (rtx operand
)
4423 /* The address must be the SP register, or a constant, aligned
4424 offset from SP which doesn't exceed the FP+offset
4426 return ((PLUS
== GET_CODE (operand
)
4427 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4428 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4429 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4431 || (REG
== GET_CODE (operand
)
4432 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4436 /* Given an alignable memory location, convert the memory location
4437 into a HI mode access, storing the new memory reference in
4438 paligned_mem, and the number of bits by which to shift in pbitnum
4439 (i.e., given a reference to FP+3, this creates an aligned reference
4440 of FP+2, with an 8-bit shift). This code is a modification of that
4441 found in the Alpha port. */
4443 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4446 HOST_WIDE_INT offset
= 0;
4448 gcc_assert (GET_CODE (ref
) == MEM
);
4450 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4452 base
= find_replacement (&XEXP (ref
, 0));
4454 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4458 base
= XEXP (ref
, 0);
4461 if (GET_CODE (base
) == PLUS
)
4463 offset
+= INTVAL (XEXP (base
, 1));
4464 base
= XEXP (base
, 0);
4467 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4474 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4478 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4482 /* Return true if the given operand is an absolute address in memory
4483 (i.e., a symbolic offset). */
4485 picochip_absolute_memory_operand (rtx op
,
4486 enum machine_mode mode ATTRIBUTE_UNUSED
)
4489 if (MEM
== GET_CODE (op
))
4491 rtx address
= XEXP (op
, 0);
4493 /* Symbols are valid absolute addresses. */
4494 if (SYMBOL_REF
== GET_CODE (address
))
4497 /* Constant offsets to symbols are valid absolute addresses. */
4498 if (CONST
== GET_CODE (address
) &&
4499 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4500 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4501 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4508 /* Symbols are valid absolute addresses. */
4509 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4518 picochip_asm_named_section (const char *name
,
4519 unsigned int flags ATTRIBUTE_UNUSED
,
4520 tree decl ATTRIBUTE_UNUSED
)
4522 fprintf (asm_out_file
, ".section %s\n", name
);
4526 /* Check if we can make a conditional copy instruction. This is emitted as an
4527 instruction to set the condition register, followed by an instruction which
4528 uses the condition registers to perform the conditional move. */
4530 picochip_check_conditional_copy (rtx
* operands
)
4533 rtx branch_op_0
= XEXP (operands
[1], 0);
4534 rtx branch_op_1
= XEXP (operands
[1], 1);
4536 /* Only HI mode conditional moves are currently allowed. Can we add
4538 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4541 /* Is the comparison valid? Only allow operands which are registers
4542 if they are HImode. SI mode comparisons against 0 could be
4543 handled using logical operations (e.g., SIreg != 0 when low ||
4544 high). Need to find test cases to provoke this though (fixunssfdi
4545 in libgcc does, but is complicated). */
4546 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4547 GET_MODE(branch_op_0
) != HImode
)
4549 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4550 GET_MODE(branch_op_1
) != HImode
)
4559 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4563 addr
= arg_pointer_rtx
;
4565 addr
= plus_constant (stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4566 return gen_frame_mem (Pmode
, addr
);