9167cb5c3ecaa9950969fb203164ba9ae6b954d9
[gcc.git] / gcc / config / rs6000 / 40x.md
1 ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
2 ;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 2, or (at your
9 ;; option) any later version.
10
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
15
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to the
18 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19 ;; MA 02110-1301, USA.
20
21 (define_automaton "ppc40x,ppc40xiu")
22 (define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
23 (define_cpu_unit "iu_40x" "ppc40xiu")
24
25 ;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
26 ;; Embedded PowerPC controller
27 ;; In-order execution
28 ;; Max issue two insns/cycle (includes one branch)
29 (define_insn_reservation "ppc403-load" 2
30 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
31 (eq_attr "cpu" "ppc403,ppc405"))
32 "iu_40x")
33
34 (define_insn_reservation "ppc403-store" 1
35 (and (eq_attr "type" "store,store_ux,store_u")
36 (eq_attr "cpu" "ppc403,ppc405"))
37 "iu_40x")
38
39 (define_insn_reservation "ppc403-integer" 1
40 (and (eq_attr "type" "integer,insert_word")
41 (eq_attr "cpu" "ppc403,ppc405"))
42 "iu_40x")
43
44 (define_insn_reservation "ppc403-two" 1
45 (and (eq_attr "type" "two")
46 (eq_attr "cpu" "ppc403,ppc405"))
47 "iu_40x,iu_40x")
48
49 (define_insn_reservation "ppc403-three" 1
50 (and (eq_attr "type" "three")
51 (eq_attr "cpu" "ppc403,ppc405"))
52 "iu_40x,iu_40x,iu_40x")
53
54 (define_insn_reservation "ppc403-compare" 3
55 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
56 (eq_attr "cpu" "ppc403,ppc405"))
57 "iu_40x,nothing,bpu_40x")
58
59 (define_insn_reservation "ppc403-imul" 4
60 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
61 (eq_attr "cpu" "ppc403"))
62 "iu_40x*4")
63
64 (define_insn_reservation "ppc405-imul" 5
65 (and (eq_attr "type" "imul,imul_compare")
66 (eq_attr "cpu" "ppc405"))
67 "iu_40x*4")
68
69 (define_insn_reservation "ppc405-imul2" 3
70 (and (eq_attr "type" "imul2")
71 (eq_attr "cpu" "ppc405"))
72 "iu_40x*2")
73
74 (define_insn_reservation "ppc405-imul3" 2
75 (and (eq_attr "type" "imul3")
76 (eq_attr "cpu" "ppc405"))
77 "iu_40x")
78
79 (define_insn_reservation "ppc403-idiv" 33
80 (and (eq_attr "type" "idiv")
81 (eq_attr "cpu" "ppc403,ppc405"))
82 "iu_40x*33")
83
84 (define_insn_reservation "ppc403-mfcr" 2
85 (and (eq_attr "type" "mfcr")
86 (eq_attr "cpu" "ppc403,ppc405"))
87 "iu_40x")
88
89 (define_insn_reservation "ppc403-mtcr" 3
90 (and (eq_attr "type" "mtcr")
91 (eq_attr "cpu" "ppc403,ppc405"))
92 "iu_40x")
93
94 (define_insn_reservation "ppc403-mtjmpr" 4
95 (and (eq_attr "type" "mtjmpr")
96 (eq_attr "cpu" "ppc403,ppc405"))
97 "iu_40x")
98
99 (define_insn_reservation "ppc403-mfjmpr" 2
100 (and (eq_attr "type" "mfjmpr")
101 (eq_attr "cpu" "ppc403,ppc405"))
102 "iu_40x")
103
104 (define_insn_reservation "ppc403-jmpreg" 1
105 (and (eq_attr "type" "jmpreg,branch")
106 (eq_attr "cpu" "ppc403,ppc405"))
107 "bpu_40x")
108
109 (define_insn_reservation "ppc403-cr" 2
110 (and (eq_attr "type" "cr_logical,delayed_cr")
111 (eq_attr "cpu" "ppc403,ppc405"))
112 "bpu_40x")
113
114 (define_insn_reservation "ppc405-float" 11
115 (and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,fpcompare,fp,dmul,sdiv,ddiv")
116 (eq_attr "cpu" "ppc405"))
117 "fpu_405*10")