1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
53 #include "sched-int.h"
55 #include "tree-flow.h"
58 #include "tm-constrs.h"
60 #include "tree-vectorizer.h"
63 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
66 #include "gstab.h" /* for N_SLINE */
69 #ifndef TARGET_NO_PROTOTYPE
70 #define TARGET_NO_PROTOTYPE 0
73 #define min(A,B) ((A) < (B) ? (A) : (B))
74 #define max(A,B) ((A) > (B) ? (A) : (B))
76 /* Structure used to define the rs6000 stack */
77 typedef struct rs6000_stack
{
78 int reload_completed
; /* stack info won't change from here on */
79 int first_gp_reg_save
; /* first callee saved GP register used */
80 int first_fp_reg_save
; /* first callee saved FP register used */
81 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
82 int lr_save_p
; /* true if the link reg needs to be saved */
83 int cr_save_p
; /* true if the CR reg needs to be saved */
84 unsigned int vrsave_mask
; /* mask of vec registers to save */
85 int push_p
; /* true if we need to allocate stack space */
86 int calls_p
; /* true if the function makes any calls */
87 int world_save_p
; /* true if we're saving *everything*:
88 r13-r31, cr, f14-f31, vrsave, v20-v31 */
89 enum rs6000_abi abi
; /* which ABI to use */
90 int gp_save_offset
; /* offset to save GP regs from initial SP */
91 int fp_save_offset
; /* offset to save FP regs from initial SP */
92 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
93 int lr_save_offset
; /* offset to save LR from initial SP */
94 int cr_save_offset
; /* offset to save CR from initial SP */
95 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
96 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
97 int varargs_save_offset
; /* offset to save the varargs registers */
98 int ehrd_offset
; /* offset to EH return data */
99 int reg_size
; /* register size (4 or 8) */
100 HOST_WIDE_INT vars_size
; /* variable save area size */
101 int parm_size
; /* outgoing parameter size */
102 int save_size
; /* save area size */
103 int fixed_size
; /* fixed size of stack frame */
104 int gp_size
; /* size of saved GP registers */
105 int fp_size
; /* size of saved FP registers */
106 int altivec_size
; /* size of saved AltiVec registers */
107 int cr_size
; /* size to hold CR if not in save_size */
108 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size
; /* size of altivec alignment padding if
111 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size
;
113 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
114 int spe_64bit_regs_used
;
118 /* A C structure for machine-specific, per-function data.
119 This is added to the cfun structure. */
120 typedef struct GTY(()) machine_function
122 /* Some local-dynamic symbol. */
123 const char *some_ld_name
;
124 /* Whether the instruction chain has been scanned already. */
125 int insn_chain_scanned_p
;
126 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
127 int ra_needs_full_frame
;
128 /* Flags if __builtin_return_address (0) was used. */
130 /* Cache lr_save_p after expansion of builtin_eh_return. */
132 /* Whether we need to save the TOC to the reserved stack location in the
133 function prologue. */
134 bool save_toc_in_prologue
;
135 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
136 varargs save area. */
137 HOST_WIDE_INT varargs_save_offset
;
138 /* Temporary stack slot to use for SDmode copies. This slot is
139 64-bits wide and is allocated early enough so that the offset
140 does not overflow the 16-bit load/store offset field. */
141 rtx sdmode_stack_slot
;
144 /* Support targetm.vectorize.builtin_mask_for_load. */
145 static GTY(()) tree altivec_builtin_mask_for_load
;
147 /* Set to nonzero once AIX common-mode calls have been defined. */
148 static GTY(()) int common_mode_defined
;
150 /* Label number of label created for -mrelocatable, to call to so we can
151 get the address of the GOT section */
152 static int rs6000_pic_labelno
;
155 /* Counter for labels which are to be placed in .fixup. */
156 int fixuplabelno
= 0;
159 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
162 /* Specify the machine mode that pointers have. After generation of rtl, the
163 compiler makes no further distinction between pointers and any other objects
164 of this machine mode. The type is unsigned since not all things that
165 include rs6000.h also include machmode.h. */
166 unsigned rs6000_pmode
;
168 /* Width in bits of a pointer. */
169 unsigned rs6000_pointer_size
;
171 #ifdef HAVE_AS_GNU_ATTRIBUTE
172 /* Flag whether floating point values have been passed/returned. */
173 static bool rs6000_passes_float
;
174 /* Flag whether vector values have been passed/returned. */
175 static bool rs6000_passes_vector
;
176 /* Flag whether small (<= 8 byte) structures have been returned. */
177 static bool rs6000_returns_struct
;
180 /* Value is TRUE if register/mode pair is acceptable. */
181 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
183 /* Maximum number of registers needed for a given register class and mode. */
184 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
186 /* How many registers are needed for a given register and mode. */
187 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
189 /* Map register number to register class. */
190 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
192 /* Reload functions based on the type and the vector unit. */
193 static enum insn_code rs6000_vector_reload
[NUM_MACHINE_MODES
][2];
195 static int dbg_cost_ctrl
;
197 /* Built in types. */
198 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
199 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
201 /* Flag to say the TOC is initialized */
203 char toc_label_name
[10];
205 /* Cached value of rs6000_variable_issue. This is cached in
206 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
207 static short cached_can_issue_more
;
209 static GTY(()) section
*read_only_data_section
;
210 static GTY(()) section
*private_data_section
;
211 static GTY(()) section
*tls_data_section
;
212 static GTY(()) section
*tls_private_data_section
;
213 static GTY(()) section
*read_only_private_data_section
;
214 static GTY(()) section
*sdata2_section
;
215 static GTY(()) section
*toc_section
;
217 struct builtin_description
219 const HOST_WIDE_INT mask
;
220 const enum insn_code icode
;
221 const char *const name
;
222 const enum rs6000_builtins code
;
225 /* Describe the vector unit used for modes. */
226 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
227 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
229 /* Register classes for various constraints that are based on the target
231 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
233 /* Describe the alignment of a vector. */
234 int rs6000_vector_align
[NUM_MACHINE_MODES
];
236 /* Map selected modes to types for builtins. */
237 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240 reciprocal sqrt (frsqrte) for. */
241 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
243 /* Masks to determine which reciprocal esitmate instructions to generate
245 enum rs6000_recip_mask
{
246 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
247 RECIP_DF_DIV
= 0x002,
248 RECIP_V4SF_DIV
= 0x004,
249 RECIP_V2DF_DIV
= 0x008,
251 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
252 RECIP_DF_RSQRT
= 0x020,
253 RECIP_V4SF_RSQRT
= 0x040,
254 RECIP_V2DF_RSQRT
= 0x080,
256 /* Various combination of flags for -mrecip=xxx. */
258 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
259 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
260 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
262 RECIP_HIGH_PRECISION
= RECIP_ALL
,
264 /* On low precision machines like the power5, don't enable double precision
265 reciprocal square root estimate, since it isn't accurate enough. */
266 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
269 /* -mrecip options. */
272 const char *string
; /* option name */
273 unsigned int mask
; /* mask bits to set */
274 } recip_options
[] = {
275 { "all", RECIP_ALL
},
276 { "none", RECIP_NONE
},
277 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
279 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
280 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
281 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
282 | RECIP_V2DF_RSQRT
) },
283 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
284 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
287 /* 2 argument gen function typedef. */
288 typedef rtx (*gen_2arg_fn_t
) (rtx
, rtx
, rtx
);
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291 macros that have changed. Languages that don't support the preprocessor
292 don't link in rs6000-c.c, so we can't call it directly. */
293 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
295 /* Simplfy register classes into simpler classifications. We assume
296 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
297 check for standard register classes (gpr/floating/altivec/vsx) and
298 floating/vector classes (float/altivec/vsx). */
300 enum rs6000_reg_type
{
313 /* Map register class to register type. */
314 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
316 /* First/last register type for the 'normal' register types (i.e. general
317 purpose, floating point, altivec, and VSX registers). */
318 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
320 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
322 /* Direct moves to/from vsx/gpr registers that need an additional register to
324 static enum insn_code reload_fpr_gpr
[NUM_MACHINE_MODES
];
325 static enum insn_code reload_gpr_vsx
[NUM_MACHINE_MODES
];
326 static enum insn_code reload_vsx_gpr
[NUM_MACHINE_MODES
];
329 /* Target cpu costs. */
331 struct processor_costs
{
332 const int mulsi
; /* cost of SImode multiplication. */
333 const int mulsi_const
; /* cost of SImode multiplication by constant. */
334 const int mulsi_const9
; /* cost of SImode mult by short constant. */
335 const int muldi
; /* cost of DImode multiplication. */
336 const int divsi
; /* cost of SImode division. */
337 const int divdi
; /* cost of DImode division. */
338 const int fp
; /* cost of simple SFmode and DFmode insns. */
339 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
340 const int sdiv
; /* cost of SFmode division (fdivs). */
341 const int ddiv
; /* cost of DFmode division (fdiv). */
342 const int cache_line_size
; /* cache line size in bytes. */
343 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
344 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
345 const int simultaneous_prefetches
; /* number of parallel prefetch
349 const struct processor_costs
*rs6000_cost
;
351 /* Processor costs (relative to an add) */
353 /* Instruction size costs on 32bit processors. */
355 struct processor_costs size32_cost
= {
356 COSTS_N_INSNS (1), /* mulsi */
357 COSTS_N_INSNS (1), /* mulsi_const */
358 COSTS_N_INSNS (1), /* mulsi_const9 */
359 COSTS_N_INSNS (1), /* muldi */
360 COSTS_N_INSNS (1), /* divsi */
361 COSTS_N_INSNS (1), /* divdi */
362 COSTS_N_INSNS (1), /* fp */
363 COSTS_N_INSNS (1), /* dmul */
364 COSTS_N_INSNS (1), /* sdiv */
365 COSTS_N_INSNS (1), /* ddiv */
372 /* Instruction size costs on 64bit processors. */
374 struct processor_costs size64_cost
= {
375 COSTS_N_INSNS (1), /* mulsi */
376 COSTS_N_INSNS (1), /* mulsi_const */
377 COSTS_N_INSNS (1), /* mulsi_const9 */
378 COSTS_N_INSNS (1), /* muldi */
379 COSTS_N_INSNS (1), /* divsi */
380 COSTS_N_INSNS (1), /* divdi */
381 COSTS_N_INSNS (1), /* fp */
382 COSTS_N_INSNS (1), /* dmul */
383 COSTS_N_INSNS (1), /* sdiv */
384 COSTS_N_INSNS (1), /* ddiv */
391 /* Instruction costs on RS64A processors. */
393 struct processor_costs rs64a_cost
= {
394 COSTS_N_INSNS (20), /* mulsi */
395 COSTS_N_INSNS (12), /* mulsi_const */
396 COSTS_N_INSNS (8), /* mulsi_const9 */
397 COSTS_N_INSNS (34), /* muldi */
398 COSTS_N_INSNS (65), /* divsi */
399 COSTS_N_INSNS (67), /* divdi */
400 COSTS_N_INSNS (4), /* fp */
401 COSTS_N_INSNS (4), /* dmul */
402 COSTS_N_INSNS (31), /* sdiv */
403 COSTS_N_INSNS (31), /* ddiv */
404 128, /* cache line size */
410 /* Instruction costs on MPCCORE processors. */
412 struct processor_costs mpccore_cost
= {
413 COSTS_N_INSNS (2), /* mulsi */
414 COSTS_N_INSNS (2), /* mulsi_const */
415 COSTS_N_INSNS (2), /* mulsi_const9 */
416 COSTS_N_INSNS (2), /* muldi */
417 COSTS_N_INSNS (6), /* divsi */
418 COSTS_N_INSNS (6), /* divdi */
419 COSTS_N_INSNS (4), /* fp */
420 COSTS_N_INSNS (5), /* dmul */
421 COSTS_N_INSNS (10), /* sdiv */
422 COSTS_N_INSNS (17), /* ddiv */
423 32, /* cache line size */
429 /* Instruction costs on PPC403 processors. */
431 struct processor_costs ppc403_cost
= {
432 COSTS_N_INSNS (4), /* mulsi */
433 COSTS_N_INSNS (4), /* mulsi_const */
434 COSTS_N_INSNS (4), /* mulsi_const9 */
435 COSTS_N_INSNS (4), /* muldi */
436 COSTS_N_INSNS (33), /* divsi */
437 COSTS_N_INSNS (33), /* divdi */
438 COSTS_N_INSNS (11), /* fp */
439 COSTS_N_INSNS (11), /* dmul */
440 COSTS_N_INSNS (11), /* sdiv */
441 COSTS_N_INSNS (11), /* ddiv */
442 32, /* cache line size */
448 /* Instruction costs on PPC405 processors. */
450 struct processor_costs ppc405_cost
= {
451 COSTS_N_INSNS (5), /* mulsi */
452 COSTS_N_INSNS (4), /* mulsi_const */
453 COSTS_N_INSNS (3), /* mulsi_const9 */
454 COSTS_N_INSNS (5), /* muldi */
455 COSTS_N_INSNS (35), /* divsi */
456 COSTS_N_INSNS (35), /* divdi */
457 COSTS_N_INSNS (11), /* fp */
458 COSTS_N_INSNS (11), /* dmul */
459 COSTS_N_INSNS (11), /* sdiv */
460 COSTS_N_INSNS (11), /* ddiv */
461 32, /* cache line size */
467 /* Instruction costs on PPC440 processors. */
469 struct processor_costs ppc440_cost
= {
470 COSTS_N_INSNS (3), /* mulsi */
471 COSTS_N_INSNS (2), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (3), /* muldi */
474 COSTS_N_INSNS (34), /* divsi */
475 COSTS_N_INSNS (34), /* divdi */
476 COSTS_N_INSNS (5), /* fp */
477 COSTS_N_INSNS (5), /* dmul */
478 COSTS_N_INSNS (19), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
480 32, /* cache line size */
486 /* Instruction costs on PPC476 processors. */
488 struct processor_costs ppc476_cost
= {
489 COSTS_N_INSNS (4), /* mulsi */
490 COSTS_N_INSNS (4), /* mulsi_const */
491 COSTS_N_INSNS (4), /* mulsi_const9 */
492 COSTS_N_INSNS (4), /* muldi */
493 COSTS_N_INSNS (11), /* divsi */
494 COSTS_N_INSNS (11), /* divdi */
495 COSTS_N_INSNS (6), /* fp */
496 COSTS_N_INSNS (6), /* dmul */
497 COSTS_N_INSNS (19), /* sdiv */
498 COSTS_N_INSNS (33), /* ddiv */
499 32, /* l1 cache line size */
505 /* Instruction costs on PPC601 processors. */
507 struct processor_costs ppc601_cost
= {
508 COSTS_N_INSNS (5), /* mulsi */
509 COSTS_N_INSNS (5), /* mulsi_const */
510 COSTS_N_INSNS (5), /* mulsi_const9 */
511 COSTS_N_INSNS (5), /* muldi */
512 COSTS_N_INSNS (36), /* divsi */
513 COSTS_N_INSNS (36), /* divdi */
514 COSTS_N_INSNS (4), /* fp */
515 COSTS_N_INSNS (5), /* dmul */
516 COSTS_N_INSNS (17), /* sdiv */
517 COSTS_N_INSNS (31), /* ddiv */
518 32, /* cache line size */
524 /* Instruction costs on PPC603 processors. */
526 struct processor_costs ppc603_cost
= {
527 COSTS_N_INSNS (5), /* mulsi */
528 COSTS_N_INSNS (3), /* mulsi_const */
529 COSTS_N_INSNS (2), /* mulsi_const9 */
530 COSTS_N_INSNS (5), /* muldi */
531 COSTS_N_INSNS (37), /* divsi */
532 COSTS_N_INSNS (37), /* divdi */
533 COSTS_N_INSNS (3), /* fp */
534 COSTS_N_INSNS (4), /* dmul */
535 COSTS_N_INSNS (18), /* sdiv */
536 COSTS_N_INSNS (33), /* ddiv */
537 32, /* cache line size */
543 /* Instruction costs on PPC604 processors. */
545 struct processor_costs ppc604_cost
= {
546 COSTS_N_INSNS (4), /* mulsi */
547 COSTS_N_INSNS (4), /* mulsi_const */
548 COSTS_N_INSNS (4), /* mulsi_const9 */
549 COSTS_N_INSNS (4), /* muldi */
550 COSTS_N_INSNS (20), /* divsi */
551 COSTS_N_INSNS (20), /* divdi */
552 COSTS_N_INSNS (3), /* fp */
553 COSTS_N_INSNS (3), /* dmul */
554 COSTS_N_INSNS (18), /* sdiv */
555 COSTS_N_INSNS (32), /* ddiv */
556 32, /* cache line size */
562 /* Instruction costs on PPC604e processors. */
564 struct processor_costs ppc604e_cost
= {
565 COSTS_N_INSNS (2), /* mulsi */
566 COSTS_N_INSNS (2), /* mulsi_const */
567 COSTS_N_INSNS (2), /* mulsi_const9 */
568 COSTS_N_INSNS (2), /* muldi */
569 COSTS_N_INSNS (20), /* divsi */
570 COSTS_N_INSNS (20), /* divdi */
571 COSTS_N_INSNS (3), /* fp */
572 COSTS_N_INSNS (3), /* dmul */
573 COSTS_N_INSNS (18), /* sdiv */
574 COSTS_N_INSNS (32), /* ddiv */
575 32, /* cache line size */
581 /* Instruction costs on PPC620 processors. */
583 struct processor_costs ppc620_cost
= {
584 COSTS_N_INSNS (5), /* mulsi */
585 COSTS_N_INSNS (4), /* mulsi_const */
586 COSTS_N_INSNS (3), /* mulsi_const9 */
587 COSTS_N_INSNS (7), /* muldi */
588 COSTS_N_INSNS (21), /* divsi */
589 COSTS_N_INSNS (37), /* divdi */
590 COSTS_N_INSNS (3), /* fp */
591 COSTS_N_INSNS (3), /* dmul */
592 COSTS_N_INSNS (18), /* sdiv */
593 COSTS_N_INSNS (32), /* ddiv */
594 128, /* cache line size */
600 /* Instruction costs on PPC630 processors. */
602 struct processor_costs ppc630_cost
= {
603 COSTS_N_INSNS (5), /* mulsi */
604 COSTS_N_INSNS (4), /* mulsi_const */
605 COSTS_N_INSNS (3), /* mulsi_const9 */
606 COSTS_N_INSNS (7), /* muldi */
607 COSTS_N_INSNS (21), /* divsi */
608 COSTS_N_INSNS (37), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (17), /* sdiv */
612 COSTS_N_INSNS (21), /* ddiv */
613 128, /* cache line size */
619 /* Instruction costs on Cell processor. */
620 /* COSTS_N_INSNS (1) ~ one add. */
622 struct processor_costs ppccell_cost
= {
623 COSTS_N_INSNS (9/2)+2, /* mulsi */
624 COSTS_N_INSNS (6/2), /* mulsi_const */
625 COSTS_N_INSNS (6/2), /* mulsi_const9 */
626 COSTS_N_INSNS (15/2)+2, /* muldi */
627 COSTS_N_INSNS (38/2), /* divsi */
628 COSTS_N_INSNS (70/2), /* divdi */
629 COSTS_N_INSNS (10/2), /* fp */
630 COSTS_N_INSNS (10/2), /* dmul */
631 COSTS_N_INSNS (74/2), /* sdiv */
632 COSTS_N_INSNS (74/2), /* ddiv */
633 128, /* cache line size */
639 /* Instruction costs on PPC750 and PPC7400 processors. */
641 struct processor_costs ppc750_cost
= {
642 COSTS_N_INSNS (5), /* mulsi */
643 COSTS_N_INSNS (3), /* mulsi_const */
644 COSTS_N_INSNS (2), /* mulsi_const9 */
645 COSTS_N_INSNS (5), /* muldi */
646 COSTS_N_INSNS (17), /* divsi */
647 COSTS_N_INSNS (17), /* divdi */
648 COSTS_N_INSNS (3), /* fp */
649 COSTS_N_INSNS (3), /* dmul */
650 COSTS_N_INSNS (17), /* sdiv */
651 COSTS_N_INSNS (31), /* ddiv */
652 32, /* cache line size */
658 /* Instruction costs on PPC7450 processors. */
660 struct processor_costs ppc7450_cost
= {
661 COSTS_N_INSNS (4), /* mulsi */
662 COSTS_N_INSNS (3), /* mulsi_const */
663 COSTS_N_INSNS (3), /* mulsi_const9 */
664 COSTS_N_INSNS (4), /* muldi */
665 COSTS_N_INSNS (23), /* divsi */
666 COSTS_N_INSNS (23), /* divdi */
667 COSTS_N_INSNS (5), /* fp */
668 COSTS_N_INSNS (5), /* dmul */
669 COSTS_N_INSNS (21), /* sdiv */
670 COSTS_N_INSNS (35), /* ddiv */
671 32, /* cache line size */
677 /* Instruction costs on PPC8540 processors. */
679 struct processor_costs ppc8540_cost
= {
680 COSTS_N_INSNS (4), /* mulsi */
681 COSTS_N_INSNS (4), /* mulsi_const */
682 COSTS_N_INSNS (4), /* mulsi_const9 */
683 COSTS_N_INSNS (4), /* muldi */
684 COSTS_N_INSNS (19), /* divsi */
685 COSTS_N_INSNS (19), /* divdi */
686 COSTS_N_INSNS (4), /* fp */
687 COSTS_N_INSNS (4), /* dmul */
688 COSTS_N_INSNS (29), /* sdiv */
689 COSTS_N_INSNS (29), /* ddiv */
690 32, /* cache line size */
693 1, /* prefetch streams /*/
696 /* Instruction costs on E300C2 and E300C3 cores. */
698 struct processor_costs ppce300c2c3_cost
= {
699 COSTS_N_INSNS (4), /* mulsi */
700 COSTS_N_INSNS (4), /* mulsi_const */
701 COSTS_N_INSNS (4), /* mulsi_const9 */
702 COSTS_N_INSNS (4), /* muldi */
703 COSTS_N_INSNS (19), /* divsi */
704 COSTS_N_INSNS (19), /* divdi */
705 COSTS_N_INSNS (3), /* fp */
706 COSTS_N_INSNS (4), /* dmul */
707 COSTS_N_INSNS (18), /* sdiv */
708 COSTS_N_INSNS (33), /* ddiv */
712 1, /* prefetch streams /*/
715 /* Instruction costs on PPCE500MC processors. */
717 struct processor_costs ppce500mc_cost
= {
718 COSTS_N_INSNS (4), /* mulsi */
719 COSTS_N_INSNS (4), /* mulsi_const */
720 COSTS_N_INSNS (4), /* mulsi_const9 */
721 COSTS_N_INSNS (4), /* muldi */
722 COSTS_N_INSNS (14), /* divsi */
723 COSTS_N_INSNS (14), /* divdi */
724 COSTS_N_INSNS (8), /* fp */
725 COSTS_N_INSNS (10), /* dmul */
726 COSTS_N_INSNS (36), /* sdiv */
727 COSTS_N_INSNS (66), /* ddiv */
728 64, /* cache line size */
731 1, /* prefetch streams /*/
734 /* Instruction costs on PPCE500MC64 processors. */
736 struct processor_costs ppce500mc64_cost
= {
737 COSTS_N_INSNS (4), /* mulsi */
738 COSTS_N_INSNS (4), /* mulsi_const */
739 COSTS_N_INSNS (4), /* mulsi_const9 */
740 COSTS_N_INSNS (4), /* muldi */
741 COSTS_N_INSNS (14), /* divsi */
742 COSTS_N_INSNS (14), /* divdi */
743 COSTS_N_INSNS (4), /* fp */
744 COSTS_N_INSNS (10), /* dmul */
745 COSTS_N_INSNS (36), /* sdiv */
746 COSTS_N_INSNS (66), /* ddiv */
747 64, /* cache line size */
750 1, /* prefetch streams /*/
753 /* Instruction costs on PPCE5500 processors. */
755 struct processor_costs ppce5500_cost
= {
756 COSTS_N_INSNS (5), /* mulsi */
757 COSTS_N_INSNS (5), /* mulsi_const */
758 COSTS_N_INSNS (4), /* mulsi_const9 */
759 COSTS_N_INSNS (5), /* muldi */
760 COSTS_N_INSNS (14), /* divsi */
761 COSTS_N_INSNS (14), /* divdi */
762 COSTS_N_INSNS (7), /* fp */
763 COSTS_N_INSNS (10), /* dmul */
764 COSTS_N_INSNS (36), /* sdiv */
765 COSTS_N_INSNS (66), /* ddiv */
766 64, /* cache line size */
769 1, /* prefetch streams /*/
772 /* Instruction costs on PPCE6500 processors. */
774 struct processor_costs ppce6500_cost
= {
775 COSTS_N_INSNS (5), /* mulsi */
776 COSTS_N_INSNS (5), /* mulsi_const */
777 COSTS_N_INSNS (4), /* mulsi_const9 */
778 COSTS_N_INSNS (5), /* muldi */
779 COSTS_N_INSNS (14), /* divsi */
780 COSTS_N_INSNS (14), /* divdi */
781 COSTS_N_INSNS (7), /* fp */
782 COSTS_N_INSNS (10), /* dmul */
783 COSTS_N_INSNS (36), /* sdiv */
784 COSTS_N_INSNS (66), /* ddiv */
785 64, /* cache line size */
788 1, /* prefetch streams /*/
791 /* Instruction costs on AppliedMicro Titan processors. */
793 struct processor_costs titan_cost
= {
794 COSTS_N_INSNS (5), /* mulsi */
795 COSTS_N_INSNS (5), /* mulsi_const */
796 COSTS_N_INSNS (5), /* mulsi_const9 */
797 COSTS_N_INSNS (5), /* muldi */
798 COSTS_N_INSNS (18), /* divsi */
799 COSTS_N_INSNS (18), /* divdi */
800 COSTS_N_INSNS (10), /* fp */
801 COSTS_N_INSNS (10), /* dmul */
802 COSTS_N_INSNS (46), /* sdiv */
803 COSTS_N_INSNS (72), /* ddiv */
804 32, /* cache line size */
807 1, /* prefetch streams /*/
810 /* Instruction costs on POWER4 and POWER5 processors. */
812 struct processor_costs power4_cost
= {
813 COSTS_N_INSNS (3), /* mulsi */
814 COSTS_N_INSNS (2), /* mulsi_const */
815 COSTS_N_INSNS (2), /* mulsi_const9 */
816 COSTS_N_INSNS (4), /* muldi */
817 COSTS_N_INSNS (18), /* divsi */
818 COSTS_N_INSNS (34), /* divdi */
819 COSTS_N_INSNS (3), /* fp */
820 COSTS_N_INSNS (3), /* dmul */
821 COSTS_N_INSNS (17), /* sdiv */
822 COSTS_N_INSNS (17), /* ddiv */
823 128, /* cache line size */
826 8, /* prefetch streams /*/
829 /* Instruction costs on POWER6 processors. */
831 struct processor_costs power6_cost
= {
832 COSTS_N_INSNS (8), /* mulsi */
833 COSTS_N_INSNS (8), /* mulsi_const */
834 COSTS_N_INSNS (8), /* mulsi_const9 */
835 COSTS_N_INSNS (8), /* muldi */
836 COSTS_N_INSNS (22), /* divsi */
837 COSTS_N_INSNS (28), /* divdi */
838 COSTS_N_INSNS (3), /* fp */
839 COSTS_N_INSNS (3), /* dmul */
840 COSTS_N_INSNS (13), /* sdiv */
841 COSTS_N_INSNS (16), /* ddiv */
842 128, /* cache line size */
845 16, /* prefetch streams */
848 /* Instruction costs on POWER7 processors. */
850 struct processor_costs power7_cost
= {
851 COSTS_N_INSNS (2), /* mulsi */
852 COSTS_N_INSNS (2), /* mulsi_const */
853 COSTS_N_INSNS (2), /* mulsi_const9 */
854 COSTS_N_INSNS (2), /* muldi */
855 COSTS_N_INSNS (18), /* divsi */
856 COSTS_N_INSNS (34), /* divdi */
857 COSTS_N_INSNS (3), /* fp */
858 COSTS_N_INSNS (3), /* dmul */
859 COSTS_N_INSNS (13), /* sdiv */
860 COSTS_N_INSNS (16), /* ddiv */
861 128, /* cache line size */
864 12, /* prefetch streams */
867 /* Instruction costs on POWER8 processors. */
869 struct processor_costs power8_cost
= {
870 COSTS_N_INSNS (3), /* mulsi */
871 COSTS_N_INSNS (3), /* mulsi_const */
872 COSTS_N_INSNS (3), /* mulsi_const9 */
873 COSTS_N_INSNS (3), /* muldi */
874 COSTS_N_INSNS (19), /* divsi */
875 COSTS_N_INSNS (35), /* divdi */
876 COSTS_N_INSNS (3), /* fp */
877 COSTS_N_INSNS (3), /* dmul */
878 COSTS_N_INSNS (14), /* sdiv */
879 COSTS_N_INSNS (17), /* ddiv */
880 128, /* cache line size */
883 12, /* prefetch streams */
886 /* Instruction costs on POWER A2 processors. */
888 struct processor_costs ppca2_cost
= {
889 COSTS_N_INSNS (16), /* mulsi */
890 COSTS_N_INSNS (16), /* mulsi_const */
891 COSTS_N_INSNS (16), /* mulsi_const9 */
892 COSTS_N_INSNS (16), /* muldi */
893 COSTS_N_INSNS (22), /* divsi */
894 COSTS_N_INSNS (28), /* divdi */
895 COSTS_N_INSNS (3), /* fp */
896 COSTS_N_INSNS (3), /* dmul */
897 COSTS_N_INSNS (59), /* sdiv */
898 COSTS_N_INSNS (72), /* ddiv */
902 16, /* prefetch streams */
906 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
907 #undef RS6000_BUILTIN_1
908 #undef RS6000_BUILTIN_2
909 #undef RS6000_BUILTIN_3
910 #undef RS6000_BUILTIN_A
911 #undef RS6000_BUILTIN_D
912 #undef RS6000_BUILTIN_E
913 #undef RS6000_BUILTIN_P
914 #undef RS6000_BUILTIN_Q
915 #undef RS6000_BUILTIN_S
916 #undef RS6000_BUILTIN_X
918 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
919 { NAME, ICODE, MASK, ATTR },
921 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
922 { NAME, ICODE, MASK, ATTR },
924 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
925 { NAME, ICODE, MASK, ATTR },
927 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
928 { NAME, ICODE, MASK, ATTR },
930 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
931 { NAME, ICODE, MASK, ATTR },
933 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
934 { NAME, ICODE, MASK, ATTR },
936 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
937 { NAME, ICODE, MASK, ATTR },
939 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
940 { NAME, ICODE, MASK, ATTR },
942 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
943 { NAME, ICODE, MASK, ATTR },
945 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
946 { NAME, ICODE, MASK, ATTR },
948 struct rs6000_builtin_info_type
{
950 const enum insn_code icode
;
951 const HOST_WIDE_INT mask
;
955 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
957 #include "rs6000-builtin.def"
960 #undef RS6000_BUILTIN_1
961 #undef RS6000_BUILTIN_2
962 #undef RS6000_BUILTIN_3
963 #undef RS6000_BUILTIN_A
964 #undef RS6000_BUILTIN_D
965 #undef RS6000_BUILTIN_E
966 #undef RS6000_BUILTIN_P
967 #undef RS6000_BUILTIN_Q
968 #undef RS6000_BUILTIN_S
969 #undef RS6000_BUILTIN_X
971 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
972 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
975 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
976 static bool spe_func_has_64bit_regs_p (void);
977 static struct machine_function
* rs6000_init_machine_status (void);
978 static int rs6000_ra_ever_killed (void);
979 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
980 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
981 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
982 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
983 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
984 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
985 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
986 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
988 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
989 static bool is_microcoded_insn (rtx
);
990 static bool is_nonpipeline_insn (rtx
);
991 static bool is_cracked_insn (rtx
);
992 static bool is_load_insn (rtx
, rtx
*);
993 static bool is_store_insn (rtx
, rtx
*);
994 static bool set_to_load_agen (rtx
,rtx
);
995 static bool insn_terminates_group_p (rtx
, enum group_termination
);
996 static bool insn_must_be_first_in_group (rtx
);
997 static bool insn_must_be_last_in_group (rtx
);
998 static void altivec_init_builtins (void);
999 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1000 enum machine_mode
, enum machine_mode
,
1001 enum rs6000_builtins
, const char *name
);
1002 static void rs6000_common_init_builtins (void);
1003 static void paired_init_builtins (void);
1004 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1005 static void spe_init_builtins (void);
1006 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1007 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1008 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1009 static rs6000_stack_t
*rs6000_stack_info (void);
1010 static void is_altivec_return_reg (rtx
, void *);
1011 int easy_vector_constant (rtx
, enum machine_mode
);
1012 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1013 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1014 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1015 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1016 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1019 static void macho_branch_islands (void);
1021 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1023 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1025 static bool rs6000_mode_dependent_address (const_rtx
);
1026 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1027 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1028 enum machine_mode
, rtx
);
1029 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1032 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1033 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1035 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1037 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1040 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1043 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1046 static bool rs6000_save_toc_in_prologue_p (void);
1048 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1050 = rs6000_legitimize_reload_address
;
1052 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1053 = rs6000_mode_dependent_address
;
1055 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1056 enum machine_mode
, rtx
)
1057 = rs6000_secondary_reload_class
;
1059 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1060 = rs6000_preferred_reload_class
;
1062 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1064 = rs6000_secondary_memory_needed
;
1066 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1069 = rs6000_cannot_change_mode_class
;
1071 const int INSN_NOT_AVAILABLE
= -1;
1073 static void rs6000_print_isa_options (FILE *, int, const char *,
1075 static void rs6000_print_builtin_options (FILE *, int, const char *,
1078 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1079 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1080 enum rs6000_reg_type
,
1082 secondary_reload_info
*,
1085 /* Hash table stuff for keeping track of TOC entries. */
1087 struct GTY(()) toc_hash_struct
1089 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1090 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1092 enum machine_mode key_mode
;
1096 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1098 /* Hash table to keep track of the argument types for builtin functions. */
1100 struct GTY(()) builtin_hash_struct
1103 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1104 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1107 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1110 /* Default register names. */
1111 char rs6000_reg_names
[][8] =
1113 "0", "1", "2", "3", "4", "5", "6", "7",
1114 "8", "9", "10", "11", "12", "13", "14", "15",
1115 "16", "17", "18", "19", "20", "21", "22", "23",
1116 "24", "25", "26", "27", "28", "29", "30", "31",
1117 "0", "1", "2", "3", "4", "5", "6", "7",
1118 "8", "9", "10", "11", "12", "13", "14", "15",
1119 "16", "17", "18", "19", "20", "21", "22", "23",
1120 "24", "25", "26", "27", "28", "29", "30", "31",
1121 "mq", "lr", "ctr","ap",
1122 "0", "1", "2", "3", "4", "5", "6", "7",
1124 /* AltiVec registers. */
1125 "0", "1", "2", "3", "4", "5", "6", "7",
1126 "8", "9", "10", "11", "12", "13", "14", "15",
1127 "16", "17", "18", "19", "20", "21", "22", "23",
1128 "24", "25", "26", "27", "28", "29", "30", "31",
1130 /* SPE registers. */
1131 "spe_acc", "spefscr",
1132 /* Soft frame pointer. */
1136 #ifdef TARGET_REGNAMES
1137 static const char alt_reg_names
[][8] =
1139 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1140 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1141 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1142 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1143 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1144 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1145 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1146 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1147 "mq", "lr", "ctr", "ap",
1148 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1150 /* AltiVec registers. */
1151 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1152 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1153 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1154 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1156 /* SPE registers. */
1157 "spe_acc", "spefscr",
1158 /* Soft frame pointer. */
1163 /* Table of valid machine attributes. */
1165 static const struct attribute_spec rs6000_attribute_table
[] =
1167 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1168 affects_type_identity } */
1169 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1171 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1173 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1175 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1177 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1179 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1180 SUBTARGET_ATTRIBUTE_TABLE
,
1182 { NULL
, 0, 0, false, false, false, NULL
, false }
1185 #ifndef TARGET_PROFILE_KERNEL
1186 #define TARGET_PROFILE_KERNEL 0
1189 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1190 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1192 /* Initialize the GCC target structure. */
1193 #undef TARGET_ATTRIBUTE_TABLE
1194 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1195 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1196 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1197 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1198 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1200 #undef TARGET_ASM_ALIGNED_DI_OP
1201 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1203 /* Default unaligned ops are only provided for ELF. Find the ops needed
1204 for non-ELF systems. */
1205 #ifndef OBJECT_FORMAT_ELF
1207 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1209 #undef TARGET_ASM_UNALIGNED_HI_OP
1210 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1211 #undef TARGET_ASM_UNALIGNED_SI_OP
1212 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1213 #undef TARGET_ASM_UNALIGNED_DI_OP
1214 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1217 #undef TARGET_ASM_UNALIGNED_HI_OP
1218 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1219 #undef TARGET_ASM_UNALIGNED_SI_OP
1220 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1221 #undef TARGET_ASM_UNALIGNED_DI_OP
1222 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1223 #undef TARGET_ASM_ALIGNED_DI_OP
1224 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1228 /* This hook deals with fixups for relocatable code and DI-mode objects
1230 #undef TARGET_ASM_INTEGER
1231 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1233 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1234 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1235 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1238 #undef TARGET_SET_UP_BY_PROLOGUE
1239 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1241 #undef TARGET_HAVE_TLS
1242 #define TARGET_HAVE_TLS HAVE_AS_TLS
1244 #undef TARGET_CANNOT_FORCE_CONST_MEM
1245 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1247 #undef TARGET_DELEGITIMIZE_ADDRESS
1248 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1250 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1251 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1253 #undef TARGET_ASM_FUNCTION_PROLOGUE
1254 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1255 #undef TARGET_ASM_FUNCTION_EPILOGUE
1256 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1258 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1259 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1261 #undef TARGET_LEGITIMIZE_ADDRESS
1262 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1264 #undef TARGET_SCHED_VARIABLE_ISSUE
1265 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1267 #undef TARGET_SCHED_ISSUE_RATE
1268 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1269 #undef TARGET_SCHED_ADJUST_COST
1270 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1271 #undef TARGET_SCHED_ADJUST_PRIORITY
1272 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1273 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1274 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1275 #undef TARGET_SCHED_INIT
1276 #define TARGET_SCHED_INIT rs6000_sched_init
1277 #undef TARGET_SCHED_FINISH
1278 #define TARGET_SCHED_FINISH rs6000_sched_finish
1279 #undef TARGET_SCHED_REORDER
1280 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1281 #undef TARGET_SCHED_REORDER2
1282 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1284 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1285 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1287 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1288 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1290 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1291 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1292 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1293 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1294 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1295 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1296 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1297 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1299 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1300 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1301 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1302 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1303 rs6000_builtin_support_vector_misalignment
1304 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1305 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1306 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1307 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1308 rs6000_builtin_vectorization_cost
1309 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1310 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1311 rs6000_preferred_simd_mode
1312 #undef TARGET_VECTORIZE_INIT_COST
1313 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1314 #undef TARGET_VECTORIZE_ADD_STMT_COST
1315 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1316 #undef TARGET_VECTORIZE_FINISH_COST
1317 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1318 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1319 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1321 #undef TARGET_INIT_BUILTINS
1322 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1323 #undef TARGET_BUILTIN_DECL
1324 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1326 #undef TARGET_EXPAND_BUILTIN
1327 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1329 #undef TARGET_MANGLE_TYPE
1330 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1332 #undef TARGET_INIT_LIBFUNCS
1333 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1336 #undef TARGET_BINDS_LOCAL_P
1337 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1340 #undef TARGET_MS_BITFIELD_LAYOUT_P
1341 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1343 #undef TARGET_ASM_OUTPUT_MI_THUNK
1344 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1346 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1347 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1349 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1350 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1352 #undef TARGET_REGISTER_MOVE_COST
1353 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1354 #undef TARGET_MEMORY_MOVE_COST
1355 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1356 #undef TARGET_RTX_COSTS
1357 #define TARGET_RTX_COSTS rs6000_rtx_costs
1358 #undef TARGET_ADDRESS_COST
1359 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1361 #undef TARGET_DWARF_REGISTER_SPAN
1362 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1364 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1365 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1367 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1368 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1370 /* On rs6000, function arguments are promoted, as are function return
1372 #undef TARGET_PROMOTE_FUNCTION_MODE
1373 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1375 #undef TARGET_RETURN_IN_MEMORY
1376 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1378 #undef TARGET_SETUP_INCOMING_VARARGS
1379 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1381 /* Always strict argument naming on rs6000. */
1382 #undef TARGET_STRICT_ARGUMENT_NAMING
1383 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1384 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1385 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1386 #undef TARGET_SPLIT_COMPLEX_ARG
1387 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1388 #undef TARGET_MUST_PASS_IN_STACK
1389 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1390 #undef TARGET_PASS_BY_REFERENCE
1391 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1392 #undef TARGET_ARG_PARTIAL_BYTES
1393 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1394 #undef TARGET_FUNCTION_ARG_ADVANCE
1395 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1396 #undef TARGET_FUNCTION_ARG
1397 #define TARGET_FUNCTION_ARG rs6000_function_arg
1398 #undef TARGET_FUNCTION_ARG_BOUNDARY
1399 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1401 #undef TARGET_BUILD_BUILTIN_VA_LIST
1402 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1404 #undef TARGET_EXPAND_BUILTIN_VA_START
1405 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1407 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1408 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1410 #undef TARGET_EH_RETURN_FILTER_MODE
1411 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1413 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1414 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1416 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1417 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1419 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1420 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1422 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1423 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1425 #undef TARGET_OPTION_OVERRIDE
1426 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1428 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1429 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1430 rs6000_builtin_vectorized_function
1433 #undef TARGET_STACK_PROTECT_FAIL
1434 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1437 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1438 The PowerPC architecture requires only weak consistency among
1439 processors--that is, memory accesses between processors need not be
1440 sequentially consistent and memory accesses among processors can occur
1441 in any order. The ability to order memory accesses weakly provides
1442 opportunities for more efficient use of the system bus. Unless a
1443 dependency exists, the 604e allows read operations to precede store
1445 #undef TARGET_RELAXED_ORDERING
1446 #define TARGET_RELAXED_ORDERING true
1449 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1450 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1453 /* Use a 32-bit anchor range. This leads to sequences like:
1455 addis tmp,anchor,high
1458 where tmp itself acts as an anchor, and can be shared between
1459 accesses to the same 64k page. */
1460 #undef TARGET_MIN_ANCHOR_OFFSET
1461 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1462 #undef TARGET_MAX_ANCHOR_OFFSET
1463 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1464 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1465 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1466 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1467 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1469 #undef TARGET_BUILTIN_RECIPROCAL
1470 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1472 #undef TARGET_EXPAND_TO_RTL_HOOK
1473 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1475 #undef TARGET_INSTANTIATE_DECLS
1476 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1478 #undef TARGET_SECONDARY_RELOAD
1479 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1481 #undef TARGET_LEGITIMATE_ADDRESS_P
1482 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1484 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1485 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1487 #undef TARGET_CAN_ELIMINATE
1488 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1490 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1491 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1493 #undef TARGET_TRAMPOLINE_INIT
1494 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1496 #undef TARGET_FUNCTION_VALUE
1497 #define TARGET_FUNCTION_VALUE rs6000_function_value
1499 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1500 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1502 #undef TARGET_OPTION_SAVE
1503 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1505 #undef TARGET_OPTION_RESTORE
1506 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1508 #undef TARGET_OPTION_PRINT
1509 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1511 #undef TARGET_CAN_INLINE_P
1512 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1514 #undef TARGET_SET_CURRENT_FUNCTION
1515 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1517 #undef TARGET_LEGITIMATE_CONSTANT_P
1518 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1520 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1521 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1524 /* Processor table. */
1527 const char *const name
; /* Canonical processor name. */
1528 const enum processor_type processor
; /* Processor type enum value. */
1529 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1532 static struct rs6000_ptt
const processor_target_table
[] =
1534 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1535 #include "rs6000-cpus.def"
1539 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1543 rs6000_cpu_name_lookup (const char *name
)
1549 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1550 if (! strcmp (name
, processor_target_table
[i
].name
))
1558 /* Return number of consecutive hard regs needed starting at reg REGNO
1559 to hold something of mode MODE.
1560 This is ordinarily the length in words of a value of mode MODE
1561 but can be less for certain modes in special long registers.
1563 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1564 scalar instructions. The upper 32 bits are only available to the
1567 POWER and PowerPC GPRs hold 32 bits worth;
1568 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1571 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1573 unsigned HOST_WIDE_INT reg_size
;
1575 /* TF/TD modes are special in that they always take 2 registers. */
1576 if (FP_REGNO_P (regno
))
1577 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1578 ? UNITS_PER_VSX_WORD
1579 : UNITS_PER_FP_WORD
);
1581 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1582 reg_size
= UNITS_PER_SPE_WORD
;
1584 else if (ALTIVEC_REGNO_P (regno
))
1585 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1587 /* The value returned for SCmode in the E500 double case is 2 for
1588 ABI compatibility; storing an SCmode value in a single register
1589 would require function_arg and rs6000_spe_function_arg to handle
1590 SCmode so as to pass the value correctly in a pair of
1592 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1593 && !DECIMAL_FLOAT_MODE_P (mode
))
1594 reg_size
= UNITS_PER_FP_WORD
;
1597 reg_size
= UNITS_PER_WORD
;
1599 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1602 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1605 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1607 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1609 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1610 register combinations, and use PTImode where we need to deal with quad
1611 word memory operations. Don't allow quad words in the argument or frame
1612 pointer registers, just registers 0..31. */
1613 if (mode
== PTImode
)
1614 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1615 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1616 && ((regno
& 1) == 0));
1618 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1619 implementations. Don't allow an item to be split between a FP register
1620 and an Altivec register. */
1621 if (VECTOR_MEM_VSX_P (mode
))
1623 if (FP_REGNO_P (regno
))
1624 return FP_REGNO_P (last_regno
);
1626 if (ALTIVEC_REGNO_P (regno
))
1627 return ALTIVEC_REGNO_P (last_regno
);
1630 /* Allow TImode in all VSX registers if the user asked for it. */
1631 if (mode
== TImode
&& TARGET_VSX_TIMODE
&& VSX_REGNO_P (regno
))
1634 /* The GPRs can hold any mode, but values bigger than one register
1635 cannot go past R31. */
1636 if (INT_REGNO_P (regno
))
1637 return INT_REGNO_P (last_regno
);
1639 /* The float registers (except for VSX vector modes) can only hold floating
1640 modes and DImode. */
1641 if (FP_REGNO_P (regno
))
1643 if (SCALAR_FLOAT_MODE_P (mode
)
1644 && (mode
!= TDmode
|| (regno
% 2) == 0)
1645 && FP_REGNO_P (last_regno
))
1648 if (GET_MODE_CLASS (mode
) == MODE_INT
1649 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1652 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1653 && PAIRED_VECTOR_MODE (mode
))
1659 /* The CR register can only hold CC modes. */
1660 if (CR_REGNO_P (regno
))
1661 return GET_MODE_CLASS (mode
) == MODE_CC
;
1663 if (CA_REGNO_P (regno
))
1664 return mode
== BImode
;
1666 /* AltiVec only in AldyVec registers. */
1667 if (ALTIVEC_REGNO_P (regno
))
1668 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1670 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1671 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1674 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1675 and it must be able to fit within the register set. */
1677 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1680 /* Print interesting facts about registers. */
1682 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1686 for (r
= first_regno
; r
<= last_regno
; ++r
)
1688 const char *comma
= "";
1691 if (first_regno
== last_regno
)
1692 fprintf (stderr
, "%s:\t", reg_name
);
1694 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1697 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1698 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1702 fprintf (stderr
, ",\n\t");
1707 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1708 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1709 rs6000_hard_regno_nregs
[m
][r
]);
1711 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1716 if (call_used_regs
[r
])
1720 fprintf (stderr
, ",\n\t");
1725 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1733 fprintf (stderr
, ",\n\t");
1738 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1744 fprintf (stderr
, ",\n\t");
1748 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1749 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1754 fprintf (stderr
, ",\n\t");
1758 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1762 #define DEBUG_FMT_ID "%-32s= "
1763 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1764 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1765 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1767 /* Print various interesting information with -mdebug=reg. */
1769 rs6000_debug_reg_global (void)
1771 static const char *const tf
[2] = { "false", "true" };
1772 const char *nl
= (const char *)0;
1775 char costly_num
[20];
1777 char flags_buffer
[40];
1778 const char *costly_str
;
1779 const char *nop_str
;
1780 const char *trace_str
;
1781 const char *abi_str
;
1782 const char *cmodel_str
;
1783 struct cl_target_option cl_opts
;
1785 /* Map enum rs6000_vector to string. */
1786 static const char *rs6000_debug_vector_unit
[] = {
1796 /* Modes we want tieable information on. */
1797 static const enum machine_mode print_tieable_modes
[] = {
1831 /* Virtual regs we are interested in. */
1832 const static struct {
1833 int regno
; /* register number. */
1834 const char *name
; /* register name. */
1835 } virtual_regs
[] = {
1836 { STACK_POINTER_REGNUM
, "stack pointer:" },
1837 { TOC_REGNUM
, "toc: " },
1838 { STATIC_CHAIN_REGNUM
, "static chain: " },
1839 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
1840 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
1841 { ARG_POINTER_REGNUM
, "arg pointer: " },
1842 { FRAME_POINTER_REGNUM
, "frame pointer:" },
1843 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
1844 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
1845 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
1846 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
1847 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
1848 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
1849 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
1850 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
1851 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
1854 fputs ("\nHard register information:\n", stderr
);
1855 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
1856 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
1857 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
1860 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
1861 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
1862 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
1863 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
1864 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
1865 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
1866 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
1867 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
1869 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
1870 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
1871 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
1875 "d reg_class = %s\n"
1876 "f reg_class = %s\n"
1877 "v reg_class = %s\n"
1878 "wa reg_class = %s\n"
1879 "wd reg_class = %s\n"
1880 "wf reg_class = %s\n"
1881 "wg reg_class = %s\n"
1882 "wl reg_class = %s\n"
1883 "wm reg_class = %s\n"
1884 "wr reg_class = %s\n"
1885 "ws reg_class = %s\n"
1886 "wt reg_class = %s\n"
1887 "wv reg_class = %s\n"
1888 "wx reg_class = %s\n"
1889 "wz reg_class = %s\n"
1891 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
1892 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
1893 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
1894 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
1895 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
1896 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
1897 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
1898 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
1899 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
1900 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
1901 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
1902 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
1903 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
1904 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
1905 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
1907 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1908 if (rs6000_vector_unit
[m
] || rs6000_vector_mem
[m
]
1909 || (rs6000_vector_reload
[m
][0] != CODE_FOR_nothing
)
1910 || (rs6000_vector_reload
[m
][1] != CODE_FOR_nothing
))
1914 "Vector mode: %-5s arithmetic: %-10s move: %-10s "
1915 "reload-out: %c reload-in: %c\n",
1917 rs6000_debug_vector_unit
[ rs6000_vector_unit
[m
] ],
1918 rs6000_debug_vector_unit
[ rs6000_vector_mem
[m
] ],
1919 (rs6000_vector_reload
[m
][0] != CODE_FOR_nothing
) ? 'y' : 'n',
1920 (rs6000_vector_reload
[m
][1] != CODE_FOR_nothing
) ? 'y' : 'n');
1926 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
1928 enum machine_mode mode1
= print_tieable_modes
[m1
];
1929 bool first_time
= true;
1931 nl
= (const char *)0;
1932 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
1934 enum machine_mode mode2
= print_tieable_modes
[m2
];
1935 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
1939 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
1944 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
1949 fputs ("\n", stderr
);
1955 if (rs6000_recip_control
)
1957 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
1959 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1960 if (rs6000_recip_bits
[m
])
1963 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1965 (RS6000_RECIP_AUTO_RE_P (m
)
1967 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
1968 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
1970 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
1973 fputs ("\n", stderr
);
1976 if (rs6000_cpu_index
>= 0)
1978 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
1980 = processor_target_table
[rs6000_cpu_index
].target_enable
;
1982 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
1983 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
1986 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
1988 if (rs6000_tune_index
>= 0)
1990 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
1992 = processor_target_table
[rs6000_tune_index
].target_enable
;
1994 sprintf (flags_buffer
, "-mtune=%s flags", name
);
1995 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
1998 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2000 cl_target_option_save (&cl_opts
, &global_options
);
2001 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2004 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2005 rs6000_isa_flags_explicit
);
2007 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2008 rs6000_builtin_mask
);
2010 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2012 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2013 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2015 switch (rs6000_sched_costly_dep
)
2017 case max_dep_latency
:
2018 costly_str
= "max_dep_latency";
2022 costly_str
= "no_dep_costly";
2025 case all_deps_costly
:
2026 costly_str
= "all_deps_costly";
2029 case true_store_to_load_dep_costly
:
2030 costly_str
= "true_store_to_load_dep_costly";
2033 case store_to_load_dep_costly
:
2034 costly_str
= "store_to_load_dep_costly";
2038 costly_str
= costly_num
;
2039 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2043 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2045 switch (rs6000_sched_insert_nops
)
2047 case sched_finish_regroup_exact
:
2048 nop_str
= "sched_finish_regroup_exact";
2051 case sched_finish_pad_groups
:
2052 nop_str
= "sched_finish_pad_groups";
2055 case sched_finish_none
:
2056 nop_str
= "sched_finish_none";
2061 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2065 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2067 switch (rs6000_sdata
)
2074 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2078 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2082 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2087 switch (rs6000_traceback
)
2089 case traceback_default
: trace_str
= "default"; break;
2090 case traceback_none
: trace_str
= "none"; break;
2091 case traceback_part
: trace_str
= "part"; break;
2092 case traceback_full
: trace_str
= "full"; break;
2093 default: trace_str
= "unknown"; break;
2096 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2098 switch (rs6000_current_cmodel
)
2100 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2101 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2102 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2103 default: cmodel_str
= "unknown"; break;
2106 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2108 switch (rs6000_current_abi
)
2110 case ABI_NONE
: abi_str
= "none"; break;
2111 case ABI_AIX
: abi_str
= "aix"; break;
2112 case ABI_V4
: abi_str
= "V4"; break;
2113 case ABI_DARWIN
: abi_str
= "darwin"; break;
2114 default: abi_str
= "unknown"; break;
2117 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2119 if (rs6000_altivec_abi
)
2120 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2123 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2125 if (rs6000_darwin64_abi
)
2126 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2128 if (rs6000_float_gprs
)
2129 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2131 if (TARGET_LINK_STACK
)
2132 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2134 if (targetm
.lra_p ())
2135 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2137 if (TARGET_P8_FUSION
)
2138 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2139 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2141 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2142 TARGET_SECURE_PLT
? "secure" : "bss");
2143 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2144 aix_struct_return
? "aix" : "sysv");
2145 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2146 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2147 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2148 tf
[!!rs6000_align_branch_targets
]);
2149 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2150 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2151 rs6000_long_double_type_size
);
2152 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2153 (int)rs6000_sched_restricted_insns_priority
);
2154 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2156 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2157 (int)RS6000_BUILTIN_COUNT
);
2160 /* Initialize the various global tables that are based on register size. */
2162 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2168 /* Precalculate REGNO_REG_CLASS. */
2169 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2170 for (r
= 1; r
< 32; ++r
)
2171 rs6000_regno_regclass
[r
] = BASE_REGS
;
2173 for (r
= 32; r
< 64; ++r
)
2174 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2176 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2177 rs6000_regno_regclass
[r
] = NO_REGS
;
2179 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2180 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2182 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2183 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2184 rs6000_regno_regclass
[r
] = CR_REGS
;
2186 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2187 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2188 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2189 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2190 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2191 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2192 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2193 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2194 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2196 /* Precalculate register class to simpler reload register class. We don't
2197 need all of the register classes that are combinations of different
2198 classes, just the simple ones that have constraint letters. */
2199 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2200 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2202 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2203 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2204 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2205 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2206 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2207 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2208 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2209 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2210 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2211 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2212 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2213 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2217 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2218 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2222 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2223 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2226 /* Precalculate vector information, this must be set up before the
2227 rs6000_hard_regno_nregs_internal below. */
2228 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2230 rs6000_vector_unit
[m
] = rs6000_vector_mem
[m
] = VECTOR_NONE
;
2231 rs6000_vector_reload
[m
][0] = CODE_FOR_nothing
;
2232 rs6000_vector_reload
[m
][1] = CODE_FOR_nothing
;
2235 for (c
= 0; c
< (int)(int)RS6000_CONSTRAINT_MAX
; c
++)
2236 rs6000_constraints
[c
] = NO_REGS
;
2238 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2239 believes it can use native alignment or still uses 128-bit alignment. */
2240 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2251 /* V2DF mode, VSX only. */
2254 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2255 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2256 rs6000_vector_align
[V2DFmode
] = align64
;
2259 /* V4SF mode, either VSX or Altivec. */
2262 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2263 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2264 rs6000_vector_align
[V4SFmode
] = align32
;
2266 else if (TARGET_ALTIVEC
)
2268 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2269 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2270 rs6000_vector_align
[V4SFmode
] = align32
;
2273 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2277 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2278 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2279 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2280 rs6000_vector_align
[V4SImode
] = align32
;
2281 rs6000_vector_align
[V8HImode
] = align32
;
2282 rs6000_vector_align
[V16QImode
] = align32
;
2286 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2287 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2288 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2292 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2293 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2294 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2298 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2299 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2302 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2303 rs6000_vector_unit
[V2DImode
]
2304 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2305 rs6000_vector_align
[V2DImode
] = align64
;
2308 /* DFmode, see if we want to use the VSX unit. */
2309 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2311 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2312 rs6000_vector_mem
[DFmode
]
2313 = (TARGET_VSX_SCALAR_MEMORY
? VECTOR_VSX
: VECTOR_NONE
);
2314 rs6000_vector_align
[DFmode
] = align64
;
2317 /* Allow TImode in VSX register and set the VSX memory macros. */
2318 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2320 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2321 rs6000_vector_align
[TImode
] = align64
;
2324 /* TODO add SPE and paired floating point vector support. */
2326 /* Register class constraints for the constraints that depend on compile
2328 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2329 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2331 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2332 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2336 /* At present, we just use VSX_REGS, but we have different constraints
2337 based on the use, in case we want to fine tune the default register
2338 class used. wa = any VSX register, wf = register class to use for
2339 V4SF, wd = register class to use for V2DF, and ws = register classs to
2340 use for DF scalars. */
2341 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2342 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2343 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2344 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = (TARGET_VSX_SCALAR_MEMORY
2347 if (TARGET_VSX_TIMODE
)
2348 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2351 /* Add conditional constraints based on various options, to allow us to
2352 collapse multiple insn patterns. */
2354 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2357 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2360 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2362 if (TARGET_DIRECT_MOVE
)
2363 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2365 if (TARGET_POWERPC64
)
2366 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2368 if (TARGET_P8_VECTOR
)
2369 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2372 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2375 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2377 /* Setup the direct move combinations. */
2378 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2380 reload_fpr_gpr
[m
] = CODE_FOR_nothing
;
2381 reload_gpr_vsx
[m
] = CODE_FOR_nothing
;
2382 reload_vsx_gpr
[m
] = CODE_FOR_nothing
;
2385 /* Set up the reload helper and direct move functions. */
2386 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2390 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_di_store
;
2391 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_di_load
;
2392 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_di_store
;
2393 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_di_load
;
2394 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_di_store
;
2395 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_di_load
;
2396 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_di_store
;
2397 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_di_load
;
2398 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_di_store
;
2399 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_di_load
;
2400 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_di_store
;
2401 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_di_load
;
2402 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2404 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_di_store
;
2405 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_di_load
;
2406 rs6000_vector_reload
[DDmode
][0] = CODE_FOR_reload_dd_di_store
;
2407 rs6000_vector_reload
[DDmode
][1] = CODE_FOR_reload_dd_di_load
;
2409 if (TARGET_P8_VECTOR
)
2411 rs6000_vector_reload
[SFmode
][0] = CODE_FOR_reload_sf_di_store
;
2412 rs6000_vector_reload
[SFmode
][1] = CODE_FOR_reload_sf_di_load
;
2413 rs6000_vector_reload
[SDmode
][0] = CODE_FOR_reload_sd_di_store
;
2414 rs6000_vector_reload
[SDmode
][1] = CODE_FOR_reload_sd_di_load
;
2416 if (TARGET_VSX_TIMODE
)
2418 rs6000_vector_reload
[TImode
][0] = CODE_FOR_reload_ti_di_store
;
2419 rs6000_vector_reload
[TImode
][1] = CODE_FOR_reload_ti_di_load
;
2421 if (TARGET_DIRECT_MOVE
)
2423 if (TARGET_POWERPC64
)
2425 reload_gpr_vsx
[TImode
] = CODE_FOR_reload_gpr_from_vsxti
;
2426 reload_gpr_vsx
[V2DFmode
] = CODE_FOR_reload_gpr_from_vsxv2df
;
2427 reload_gpr_vsx
[V2DImode
] = CODE_FOR_reload_gpr_from_vsxv2di
;
2428 reload_gpr_vsx
[V4SFmode
] = CODE_FOR_reload_gpr_from_vsxv4sf
;
2429 reload_gpr_vsx
[V4SImode
] = CODE_FOR_reload_gpr_from_vsxv4si
;
2430 reload_gpr_vsx
[V8HImode
] = CODE_FOR_reload_gpr_from_vsxv8hi
;
2431 reload_gpr_vsx
[V16QImode
] = CODE_FOR_reload_gpr_from_vsxv16qi
;
2432 reload_gpr_vsx
[SFmode
] = CODE_FOR_reload_gpr_from_vsxsf
;
2434 reload_vsx_gpr
[TImode
] = CODE_FOR_reload_vsx_from_gprti
;
2435 reload_vsx_gpr
[V2DFmode
] = CODE_FOR_reload_vsx_from_gprv2df
;
2436 reload_vsx_gpr
[V2DImode
] = CODE_FOR_reload_vsx_from_gprv2di
;
2437 reload_vsx_gpr
[V4SFmode
] = CODE_FOR_reload_vsx_from_gprv4sf
;
2438 reload_vsx_gpr
[V4SImode
] = CODE_FOR_reload_vsx_from_gprv4si
;
2439 reload_vsx_gpr
[V8HImode
] = CODE_FOR_reload_vsx_from_gprv8hi
;
2440 reload_vsx_gpr
[V16QImode
] = CODE_FOR_reload_vsx_from_gprv16qi
;
2441 reload_vsx_gpr
[SFmode
] = CODE_FOR_reload_vsx_from_gprsf
;
2445 reload_fpr_gpr
[DImode
] = CODE_FOR_reload_fpr_from_gprdi
;
2446 reload_fpr_gpr
[DDmode
] = CODE_FOR_reload_fpr_from_gprdd
;
2447 reload_fpr_gpr
[DFmode
] = CODE_FOR_reload_fpr_from_gprdf
;
2453 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_si_store
;
2454 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_si_load
;
2455 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_si_store
;
2456 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_si_load
;
2457 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_si_store
;
2458 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_si_load
;
2459 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_si_store
;
2460 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_si_load
;
2461 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_si_store
;
2462 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_si_load
;
2463 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_si_store
;
2464 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_si_load
;
2465 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2467 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_si_store
;
2468 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_si_load
;
2469 rs6000_vector_reload
[DDmode
][0] = CODE_FOR_reload_dd_si_store
;
2470 rs6000_vector_reload
[DDmode
][1] = CODE_FOR_reload_dd_si_load
;
2472 if (TARGET_P8_VECTOR
)
2474 rs6000_vector_reload
[SFmode
][0] = CODE_FOR_reload_sf_si_store
;
2475 rs6000_vector_reload
[SFmode
][1] = CODE_FOR_reload_sf_si_load
;
2476 rs6000_vector_reload
[SDmode
][0] = CODE_FOR_reload_sd_si_store
;
2477 rs6000_vector_reload
[SDmode
][1] = CODE_FOR_reload_sd_si_load
;
2479 if (TARGET_VSX_TIMODE
)
2481 rs6000_vector_reload
[TImode
][0] = CODE_FOR_reload_ti_si_store
;
2482 rs6000_vector_reload
[TImode
][1] = CODE_FOR_reload_ti_si_load
;
2487 /* Precalculate HARD_REGNO_NREGS. */
2488 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2489 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2490 rs6000_hard_regno_nregs
[m
][r
]
2491 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2493 /* Precalculate HARD_REGNO_MODE_OK. */
2494 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2495 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2496 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2497 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2499 /* Precalculate CLASS_MAX_NREGS sizes. */
2500 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2504 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2505 reg_size
= UNITS_PER_VSX_WORD
;
2507 else if (c
== ALTIVEC_REGS
)
2508 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2510 else if (c
== FLOAT_REGS
)
2511 reg_size
= UNITS_PER_FP_WORD
;
2514 reg_size
= UNITS_PER_WORD
;
2516 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2518 int reg_size2
= reg_size
;
2520 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2521 if (m
== TDmode
|| m
== TFmode
)
2522 reg_size2
= UNITS_PER_FP_WORD
;
2524 rs6000_class_max_nregs
[m
][c
]
2525 = (GET_MODE_SIZE (m
) + reg_size2
- 1) / reg_size2
;
2529 if (TARGET_E500_DOUBLE
)
2530 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2532 /* Calculate which modes to automatically generate code to use a the
2533 reciprocal divide and square root instructions. In the future, possibly
2534 automatically generate the instructions even if the user did not specify
2535 -mrecip. The older machines double precision reciprocal sqrt estimate is
2536 not accurate enough. */
2537 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2539 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2541 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2542 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2543 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2544 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2545 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2547 if (TARGET_FRSQRTES
)
2548 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2550 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2551 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2552 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2553 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2554 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2556 if (rs6000_recip_control
)
2558 if (!flag_finite_math_only
)
2559 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2560 if (flag_trapping_math
)
2561 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2562 if (!flag_reciprocal_math
)
2563 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2564 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2566 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2567 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2568 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2570 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2571 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2572 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2574 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2575 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2576 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2578 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2579 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2580 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2582 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2583 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2584 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2586 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2587 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2588 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2590 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2591 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2592 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2594 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2595 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2596 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2600 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2602 if (TARGET_DEBUG_REG
)
2603 rs6000_debug_reg_global ();
2605 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2607 "SImode variable mult cost = %d\n"
2608 "SImode constant mult cost = %d\n"
2609 "SImode short constant mult cost = %d\n"
2610 "DImode multipliciation cost = %d\n"
2611 "SImode division cost = %d\n"
2612 "DImode division cost = %d\n"
2613 "Simple fp operation cost = %d\n"
2614 "DFmode multiplication cost = %d\n"
2615 "SFmode division cost = %d\n"
2616 "DFmode division cost = %d\n"
2617 "cache line size = %d\n"
2618 "l1 cache size = %d\n"
2619 "l2 cache size = %d\n"
2620 "simultaneous prefetches = %d\n"
2623 rs6000_cost
->mulsi_const
,
2624 rs6000_cost
->mulsi_const9
,
2632 rs6000_cost
->cache_line_size
,
2633 rs6000_cost
->l1_cache_size
,
2634 rs6000_cost
->l2_cache_size
,
2635 rs6000_cost
->simultaneous_prefetches
);
2640 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2643 darwin_rs6000_override_options (void)
2645 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2647 rs6000_altivec_abi
= 1;
2648 TARGET_ALTIVEC_VRSAVE
= 1;
2649 rs6000_current_abi
= ABI_DARWIN
;
2651 if (DEFAULT_ABI
== ABI_DARWIN
2653 darwin_one_byte_bool
= 1;
2655 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2657 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2658 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2662 rs6000_default_long_calls
= 1;
2663 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2666 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2668 if (!flag_mkernel
&& !flag_apple_kext
2670 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2671 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2673 /* Unless the user (not the configurer) has explicitly overridden
2674 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2675 G4 unless targeting the kernel. */
2678 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2679 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2680 && ! global_options_set
.x_rs6000_cpu_index
)
2682 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2687 /* If not otherwise specified by a target, make 'long double' equivalent to
2690 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2691 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2694 /* Return the builtin mask of the various options used that could affect which
2695 builtins were used. In the past we used target_flags, but we've run out of
2696 bits, and some options like SPE and PAIRED are no longer in
2700 rs6000_builtin_mask_calculate (void)
2702 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2703 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2704 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2705 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2706 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2707 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2708 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2709 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2710 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2711 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
2712 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
2713 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0));
2716 /* Override command line options. Mostly we process the processor type and
2717 sometimes adjust other TARGET_ options. */
2720 rs6000_option_override_internal (bool global_init_p
)
2723 bool have_cpu
= false;
2725 /* The default cpu requested at configure time, if any. */
2726 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
2728 HOST_WIDE_INT set_masks
;
2731 struct cl_target_option
*main_target_opt
2732 = ((global_init_p
|| target_option_default_node
== NULL
)
2733 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
2735 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2736 library functions, so warn about it. The flag may be useful for
2737 performance studies from time to time though, so don't disable it
2739 if (global_options_set
.x_rs6000_alignment_flags
2740 && rs6000_alignment_flags
== MASK_ALIGN_POWER
2741 && DEFAULT_ABI
== ABI_DARWIN
2743 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2744 " it is incompatible with the installed C and C++ libraries");
2746 /* Numerous experiment shows that IRA based loop pressure
2747 calculation works better for RTL loop invariant motion on targets
2748 with enough (>= 32) registers. It is an expensive optimization.
2749 So it is on only for peak performance. */
2750 if (optimize
>= 3 && global_init_p
)
2751 flag_ira_loop_pressure
= 1;
2753 /* Set the pointer size. */
2756 rs6000_pmode
= (int)DImode
;
2757 rs6000_pointer_size
= 64;
2761 rs6000_pmode
= (int)SImode
;
2762 rs6000_pointer_size
= 32;
2765 /* Some OSs don't support saving the high part of 64-bit registers on context
2766 switch. Other OSs don't support saving Altivec registers. On those OSs,
2767 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
2768 if the user wants either, the user must explicitly specify them and we
2769 won't interfere with the user's specification. */
2771 set_masks
= POWERPC_MASKS
;
2772 #ifdef OS_MISSING_POWERPC64
2773 if (OS_MISSING_POWERPC64
)
2774 set_masks
&= ~OPTION_MASK_POWERPC64
;
2776 #ifdef OS_MISSING_ALTIVEC
2777 if (OS_MISSING_ALTIVEC
)
2778 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
2781 /* Don't override by the processor default if given explicitly. */
2782 set_masks
&= ~rs6000_isa_flags_explicit
;
2784 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2785 the cpu in a target attribute or pragma, but did not specify a tuning
2786 option, use the cpu for the tuning option rather than the option specified
2787 with -mtune on the command line. Process a '--with-cpu' configuration
2788 request as an implicit --cpu. */
2789 if (rs6000_cpu_index
>= 0)
2791 cpu_index
= rs6000_cpu_index
;
2794 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
2796 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
2799 else if (implicit_cpu
)
2801 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
2806 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
2807 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
2811 gcc_assert (cpu_index
>= 0);
2813 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
2814 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
2815 with those from the cpu, except for options that were explicitly set. If
2816 we don't have a cpu, do not override the target bits set in
2820 rs6000_isa_flags
&= ~set_masks
;
2821 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2825 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2826 & ~rs6000_isa_flags_explicit
);
2828 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
2829 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
2830 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
2831 to using rs6000_isa_flags, we need to do the initialization here. */
2833 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
2835 if (rs6000_tune_index
>= 0)
2836 tune_index
= rs6000_tune_index
;
2838 rs6000_tune_index
= tune_index
= cpu_index
;
2842 enum processor_type tune_proc
2843 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
2846 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2847 if (processor_target_table
[i
].processor
== tune_proc
)
2849 rs6000_tune_index
= tune_index
= i
;
2854 gcc_assert (tune_index
>= 0);
2855 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
2857 /* Pick defaults for SPE related control flags. Do this early to make sure
2858 that the TARGET_ macros are representative ASAP. */
2860 int spe_capable_cpu
=
2861 (rs6000_cpu
== PROCESSOR_PPC8540
2862 || rs6000_cpu
== PROCESSOR_PPC8548
);
2864 if (!global_options_set
.x_rs6000_spe_abi
)
2865 rs6000_spe_abi
= spe_capable_cpu
;
2867 if (!global_options_set
.x_rs6000_spe
)
2868 rs6000_spe
= spe_capable_cpu
;
2870 if (!global_options_set
.x_rs6000_float_gprs
)
2872 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
2873 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
2877 if (global_options_set
.x_rs6000_spe_abi
2880 error ("not configured for SPE ABI");
2882 if (global_options_set
.x_rs6000_spe
2885 error ("not configured for SPE instruction set");
2887 if (main_target_opt
!= NULL
2888 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
2889 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
2890 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
2891 error ("target attribute or pragma changes SPE ABI");
2893 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
2894 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
2895 || rs6000_cpu
== PROCESSOR_PPCE5500
)
2898 error ("AltiVec not supported in this target");
2900 error ("SPE not supported in this target");
2902 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
2905 error ("SPE not supported in this target");
2908 /* Disable Cell microcode if we are optimizing for the Cell
2909 and not optimizing for size. */
2910 if (rs6000_gen_cell_microcode
== -1)
2911 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
2914 /* If we are optimizing big endian systems for space and it's OK to
2915 use instructions that would be microcoded on the Cell, use the
2916 load/store multiple and string instructions. */
2917 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
2918 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
2919 | OPTION_MASK_STRING
);
2921 /* Don't allow -mmultiple or -mstring on little endian systems
2922 unless the cpu is a 750, because the hardware doesn't support the
2923 instructions used in little endian mode, and causes an alignment
2924 trap. The 750 does not cause an alignment trap (except when the
2925 target is unaligned). */
2927 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
2929 if (TARGET_MULTIPLE
)
2931 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
2932 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
2933 warning (0, "-mmultiple is not supported on little endian systems");
2938 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
2939 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
2940 warning (0, "-mstring is not supported on little endian systems");
2944 /* Add some warnings for VSX. */
2947 const char *msg
= NULL
;
2948 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
2949 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
2951 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2952 msg
= N_("-mvsx requires hardware floating point");
2954 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2956 else if (TARGET_PAIRED_FLOAT
)
2957 msg
= N_("-mvsx and -mpaired are incompatible");
2958 /* The hardware will allow VSX and little endian, but until we make sure
2959 things like vector select, etc. work don't allow VSX on little endian
2960 systems at this point. */
2961 else if (!BYTES_BIG_ENDIAN
)
2962 msg
= N_("-mvsx used with little endian code");
2963 else if (TARGET_AVOID_XFORM
> 0)
2964 msg
= N_("-mvsx needs indexed addressing");
2965 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
2966 & OPTION_MASK_ALTIVEC
))
2968 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2969 msg
= N_("-mvsx and -mno-altivec are incompatible");
2971 msg
= N_("-mno-altivec disables vsx");
2977 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2978 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
2982 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
2983 silently turn off quad memory mode. */
2984 if (TARGET_QUAD_MEMORY
&& !TARGET_POWERPC64
)
2986 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
2987 warning (0, N_("-mquad-memory requires 64-bit mode"));
2989 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
2992 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
2993 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
2995 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2996 unless the user explicitly used the -mno-<option> to disable the code. */
2997 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
2998 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
2999 else if (TARGET_VSX
)
3000 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3001 else if (TARGET_POPCNTD
)
3002 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3003 else if (TARGET_DFP
)
3004 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3005 else if (TARGET_CMPB
)
3006 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3007 else if (TARGET_FPRND
)
3008 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3009 else if (TARGET_POPCNTB
)
3010 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3011 else if (TARGET_ALTIVEC
)
3012 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3014 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3016 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3017 error ("-mcrypto requires -maltivec");
3018 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3021 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3023 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3024 error ("-mdirect-move requires -mvsx");
3025 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3028 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3030 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3031 error ("-mpower8-vector requires -maltivec");
3032 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3035 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3037 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3038 error ("-mpower8-vector requires -mvsx");
3039 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3042 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3044 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3045 error ("-mvsx-timode requires -mvsx");
3046 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3049 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3050 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3052 /* E500mc does "better" if we inline more aggressively. Respect the
3053 user's opinion, though. */
3054 if (rs6000_block_move_inline_limit
== 0
3055 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3056 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3057 || rs6000_cpu
== PROCESSOR_PPCE5500
3058 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3059 rs6000_block_move_inline_limit
= 128;
3061 /* store_one_arg depends on expand_block_move to handle at least the
3062 size of reg_parm_stack_space. */
3063 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3064 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3068 /* If the appropriate debug option is enabled, replace the target hooks
3069 with debug versions that call the real version and then prints
3070 debugging information. */
3071 if (TARGET_DEBUG_COST
)
3073 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3074 targetm
.address_cost
= rs6000_debug_address_cost
;
3075 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3078 if (TARGET_DEBUG_ADDR
)
3080 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3081 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3082 rs6000_secondary_reload_class_ptr
3083 = rs6000_debug_secondary_reload_class
;
3084 rs6000_secondary_memory_needed_ptr
3085 = rs6000_debug_secondary_memory_needed
;
3086 rs6000_cannot_change_mode_class_ptr
3087 = rs6000_debug_cannot_change_mode_class
;
3088 rs6000_preferred_reload_class_ptr
3089 = rs6000_debug_preferred_reload_class
;
3090 rs6000_legitimize_reload_address_ptr
3091 = rs6000_debug_legitimize_reload_address
;
3092 rs6000_mode_dependent_address_ptr
3093 = rs6000_debug_mode_dependent_address
;
3096 if (rs6000_veclibabi_name
)
3098 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3099 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3102 error ("unknown vectorization library ABI type (%s) for "
3103 "-mveclibabi= switch", rs6000_veclibabi_name
);
3109 if (!global_options_set
.x_rs6000_long_double_type_size
)
3111 if (main_target_opt
!= NULL
3112 && (main_target_opt
->x_rs6000_long_double_type_size
3113 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3114 error ("target attribute or pragma changes long double size");
3116 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3119 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3120 if (!global_options_set
.x_rs6000_ieeequad
)
3121 rs6000_ieeequad
= 1;
3124 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3125 target attribute or pragma which automatically enables both options,
3126 unless the altivec ABI was set. This is set by default for 64-bit, but
3128 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3129 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3130 & ~rs6000_isa_flags_explicit
);
3132 /* Enable Altivec ABI for AIX -maltivec. */
3133 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3135 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3136 error ("target attribute or pragma changes AltiVec ABI");
3138 rs6000_altivec_abi
= 1;
3141 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3142 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3143 be explicitly overridden in either case. */
3146 if (!global_options_set
.x_rs6000_altivec_abi
3147 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3149 if (main_target_opt
!= NULL
&&
3150 !main_target_opt
->x_rs6000_altivec_abi
)
3151 error ("target attribute or pragma changes AltiVec ABI");
3153 rs6000_altivec_abi
= 1;
3157 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3158 So far, the only darwin64 targets are also MACH-O. */
3160 && DEFAULT_ABI
== ABI_DARWIN
3163 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3164 error ("target attribute or pragma changes darwin64 ABI");
3167 rs6000_darwin64_abi
= 1;
3168 /* Default to natural alignment, for better performance. */
3169 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3173 /* Place FP constants in the constant pool instead of TOC
3174 if section anchors enabled. */
3175 if (flag_section_anchors
3176 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3177 TARGET_NO_FP_IN_TOC
= 1;
3179 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3180 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3182 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3183 SUBTARGET_OVERRIDE_OPTIONS
;
3185 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3186 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3188 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3189 SUB3TARGET_OVERRIDE_OPTIONS
;
3192 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3193 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3195 /* For the E500 family of cores, reset the single/double FP flags to let us
3196 check that they remain constant across attributes or pragmas. Also,
3197 clear a possible request for string instructions, not supported and which
3198 we might have silently queried above for -Os.
3200 For other families, clear ISEL in case it was set implicitly.
3205 case PROCESSOR_PPC8540
:
3206 case PROCESSOR_PPC8548
:
3207 case PROCESSOR_PPCE500MC
:
3208 case PROCESSOR_PPCE500MC64
:
3209 case PROCESSOR_PPCE5500
:
3210 case PROCESSOR_PPCE6500
:
3212 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3213 rs6000_double_float
= TARGET_E500_DOUBLE
;
3215 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3221 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3222 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3227 if (main_target_opt
)
3229 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3230 error ("target attribute or pragma changes single precision floating "
3232 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3233 error ("target attribute or pragma changes double precision floating "
3237 /* Detect invalid option combinations with E500. */
3240 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3241 && rs6000_cpu
!= PROCESSOR_POWER5
3242 && rs6000_cpu
!= PROCESSOR_POWER6
3243 && rs6000_cpu
!= PROCESSOR_POWER7
3244 && rs6000_cpu
!= PROCESSOR_POWER8
3245 && rs6000_cpu
!= PROCESSOR_PPCA2
3246 && rs6000_cpu
!= PROCESSOR_CELL
3247 && rs6000_cpu
!= PROCESSOR_PPC476
);
3248 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3249 || rs6000_cpu
== PROCESSOR_POWER5
3250 || rs6000_cpu
== PROCESSOR_POWER7
3251 || rs6000_cpu
== PROCESSOR_POWER8
);
3252 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3253 || rs6000_cpu
== PROCESSOR_POWER5
3254 || rs6000_cpu
== PROCESSOR_POWER6
3255 || rs6000_cpu
== PROCESSOR_POWER7
3256 || rs6000_cpu
== PROCESSOR_POWER8
3257 || rs6000_cpu
== PROCESSOR_PPCE500MC
3258 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3259 || rs6000_cpu
== PROCESSOR_PPCE5500
3260 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3262 /* Allow debug switches to override the above settings. These are set to -1
3263 in rs6000.opt to indicate the user hasn't directly set the switch. */
3264 if (TARGET_ALWAYS_HINT
>= 0)
3265 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3267 if (TARGET_SCHED_GROUPS
>= 0)
3268 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3270 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3271 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3273 rs6000_sched_restricted_insns_priority
3274 = (rs6000_sched_groups
? 1 : 0);
3276 /* Handle -msched-costly-dep option. */
3277 rs6000_sched_costly_dep
3278 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3280 if (rs6000_sched_costly_dep_str
)
3282 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3283 rs6000_sched_costly_dep
= no_dep_costly
;
3284 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3285 rs6000_sched_costly_dep
= all_deps_costly
;
3286 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3287 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3288 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3289 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3291 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3292 atoi (rs6000_sched_costly_dep_str
));
3295 /* Handle -minsert-sched-nops option. */
3296 rs6000_sched_insert_nops
3297 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3299 if (rs6000_sched_insert_nops_str
)
3301 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3302 rs6000_sched_insert_nops
= sched_finish_none
;
3303 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3304 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3305 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3306 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3308 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3309 atoi (rs6000_sched_insert_nops_str
));
3314 #ifdef TARGET_REGNAMES
3315 /* If the user desires alternate register names, copy in the
3316 alternate names now. */
3317 if (TARGET_REGNAMES
)
3318 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3321 /* Set aix_struct_return last, after the ABI is determined.
3322 If -maix-struct-return or -msvr4-struct-return was explicitly
3323 used, don't override with the ABI default. */
3324 if (!global_options_set
.x_aix_struct_return
)
3325 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3328 /* IBM XL compiler defaults to unsigned bitfields. */
3329 if (TARGET_XL_COMPAT
)
3330 flag_signed_bitfields
= 0;
3333 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3334 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3337 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3339 /* We can only guarantee the availability of DI pseudo-ops when
3340 assembling for 64-bit targets. */
3343 targetm
.asm_out
.aligned_op
.di
= NULL
;
3344 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3348 /* Set branch target alignment, if not optimizing for size. */
3351 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3352 aligned 8byte to avoid misprediction by the branch predictor. */
3353 if (rs6000_cpu
== PROCESSOR_TITAN
3354 || rs6000_cpu
== PROCESSOR_CELL
)
3356 if (align_functions
<= 0)
3357 align_functions
= 8;
3358 if (align_jumps
<= 0)
3360 if (align_loops
<= 0)
3363 if (rs6000_align_branch_targets
)
3365 if (align_functions
<= 0)
3366 align_functions
= 16;
3367 if (align_jumps
<= 0)
3369 if (align_loops
<= 0)
3371 can_override_loop_align
= 1;
3375 if (align_jumps_max_skip
<= 0)
3376 align_jumps_max_skip
= 15;
3377 if (align_loops_max_skip
<= 0)
3378 align_loops_max_skip
= 15;
3381 /* Arrange to save and restore machine status around nested functions. */
3382 init_machine_status
= rs6000_init_machine_status
;
3384 /* We should always be splitting complex arguments, but we can't break
3385 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3386 if (DEFAULT_ABI
!= ABI_AIX
)
3387 targetm
.calls
.split_complex_arg
= NULL
;
3390 /* Initialize rs6000_cost with the appropriate target costs. */
3392 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3396 case PROCESSOR_RS64A
:
3397 rs6000_cost
= &rs64a_cost
;
3400 case PROCESSOR_MPCCORE
:
3401 rs6000_cost
= &mpccore_cost
;
3404 case PROCESSOR_PPC403
:
3405 rs6000_cost
= &ppc403_cost
;
3408 case PROCESSOR_PPC405
:
3409 rs6000_cost
= &ppc405_cost
;
3412 case PROCESSOR_PPC440
:
3413 rs6000_cost
= &ppc440_cost
;
3416 case PROCESSOR_PPC476
:
3417 rs6000_cost
= &ppc476_cost
;
3420 case PROCESSOR_PPC601
:
3421 rs6000_cost
= &ppc601_cost
;
3424 case PROCESSOR_PPC603
:
3425 rs6000_cost
= &ppc603_cost
;
3428 case PROCESSOR_PPC604
:
3429 rs6000_cost
= &ppc604_cost
;
3432 case PROCESSOR_PPC604e
:
3433 rs6000_cost
= &ppc604e_cost
;
3436 case PROCESSOR_PPC620
:
3437 rs6000_cost
= &ppc620_cost
;
3440 case PROCESSOR_PPC630
:
3441 rs6000_cost
= &ppc630_cost
;
3444 case PROCESSOR_CELL
:
3445 rs6000_cost
= &ppccell_cost
;
3448 case PROCESSOR_PPC750
:
3449 case PROCESSOR_PPC7400
:
3450 rs6000_cost
= &ppc750_cost
;
3453 case PROCESSOR_PPC7450
:
3454 rs6000_cost
= &ppc7450_cost
;
3457 case PROCESSOR_PPC8540
:
3458 case PROCESSOR_PPC8548
:
3459 rs6000_cost
= &ppc8540_cost
;
3462 case PROCESSOR_PPCE300C2
:
3463 case PROCESSOR_PPCE300C3
:
3464 rs6000_cost
= &ppce300c2c3_cost
;
3467 case PROCESSOR_PPCE500MC
:
3468 rs6000_cost
= &ppce500mc_cost
;
3471 case PROCESSOR_PPCE500MC64
:
3472 rs6000_cost
= &ppce500mc64_cost
;
3475 case PROCESSOR_PPCE5500
:
3476 rs6000_cost
= &ppce5500_cost
;
3479 case PROCESSOR_PPCE6500
:
3480 rs6000_cost
= &ppce6500_cost
;
3483 case PROCESSOR_TITAN
:
3484 rs6000_cost
= &titan_cost
;
3487 case PROCESSOR_POWER4
:
3488 case PROCESSOR_POWER5
:
3489 rs6000_cost
= &power4_cost
;
3492 case PROCESSOR_POWER6
:
3493 rs6000_cost
= &power6_cost
;
3496 case PROCESSOR_POWER7
:
3497 rs6000_cost
= &power7_cost
;
3500 case PROCESSOR_POWER8
:
3501 rs6000_cost
= &power8_cost
;
3504 case PROCESSOR_PPCA2
:
3505 rs6000_cost
= &ppca2_cost
;
3514 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3515 rs6000_cost
->simultaneous_prefetches
,
3516 global_options
.x_param_values
,
3517 global_options_set
.x_param_values
);
3518 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3519 global_options
.x_param_values
,
3520 global_options_set
.x_param_values
);
3521 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3522 rs6000_cost
->cache_line_size
,
3523 global_options
.x_param_values
,
3524 global_options_set
.x_param_values
);
3525 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3526 global_options
.x_param_values
,
3527 global_options_set
.x_param_values
);
3529 /* Increase loop peeling limits based on performance analysis. */
3530 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3531 global_options
.x_param_values
,
3532 global_options_set
.x_param_values
);
3533 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3534 global_options
.x_param_values
,
3535 global_options_set
.x_param_values
);
3537 /* If using typedef char *va_list, signal that
3538 __builtin_va_start (&ap, 0) can be optimized to
3539 ap = __builtin_next_arg (0). */
3540 if (DEFAULT_ABI
!= ABI_V4
)
3541 targetm
.expand_builtin_va_start
= NULL
;
3544 /* Set up single/double float flags.
3545 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3546 then set both flags. */
3547 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3548 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3549 rs6000_single_float
= rs6000_double_float
= 1;
3551 /* If not explicitly specified via option, decide whether to generate indexed
3552 load/store instructions. */
3553 if (TARGET_AVOID_XFORM
== -1)
3554 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3555 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3556 need indexed accesses and the type used is the scalar type of the element
3557 being loaded or stored. */
3558 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3559 && !TARGET_ALTIVEC
);
3561 /* Set the -mrecip options. */
3562 if (rs6000_recip_name
)
3564 char *p
= ASTRDUP (rs6000_recip_name
);
3566 unsigned int mask
, i
;
3569 while ((q
= strtok (p
, ",")) != NULL
)
3580 if (!strcmp (q
, "default"))
3581 mask
= ((TARGET_RECIP_PRECISION
)
3582 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3585 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3586 if (!strcmp (q
, recip_options
[i
].string
))
3588 mask
= recip_options
[i
].mask
;
3592 if (i
== ARRAY_SIZE (recip_options
))
3594 error ("unknown option for -mrecip=%s", q
);
3602 rs6000_recip_control
&= ~mask
;
3604 rs6000_recip_control
|= mask
;
3608 /* Set the builtin mask of the various options used that could affect which
3609 builtins were used. In the past we used target_flags, but we've run out
3610 of bits, and some options like SPE and PAIRED are no longer in
3612 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3613 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3616 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3617 rs6000_builtin_mask
);
3618 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3621 /* Initialize all of the registers. */
3622 rs6000_init_hard_regno_mode_ok (global_init_p
);
3624 /* Save the initial options in case the user does function specific options */
3626 target_option_default_node
= target_option_current_node
3627 = build_target_option_node ();
3629 /* If not explicitly specified via option, decide whether to generate the
3630 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3631 if (TARGET_LINK_STACK
== -1)
3632 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3637 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3638 define the target cpu type. */
3641 rs6000_option_override (void)
3643 (void) rs6000_option_override_internal (true);
3647 /* Implement targetm.vectorize.builtin_mask_for_load. */
3649 rs6000_builtin_mask_for_load (void)
3651 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3652 return altivec_builtin_mask_for_load
;
3657 /* Implement LOOP_ALIGN. */
3659 rs6000_loop_align (rtx label
)
3664 /* Don't override loop alignment if -falign-loops was specified. */
3665 if (!can_override_loop_align
)
3666 return align_loops_log
;
3668 bb
= BLOCK_FOR_INSN (label
);
3669 ninsns
= num_loop_insns(bb
->loop_father
);
3671 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3672 if (ninsns
> 4 && ninsns
<= 8
3673 && (rs6000_cpu
== PROCESSOR_POWER4
3674 || rs6000_cpu
== PROCESSOR_POWER5
3675 || rs6000_cpu
== PROCESSOR_POWER6
3676 || rs6000_cpu
== PROCESSOR_POWER7
3677 || rs6000_cpu
== PROCESSOR_POWER8
))
3680 return align_loops_log
;
3683 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3685 rs6000_loop_align_max_skip (rtx label
)
3687 return (1 << rs6000_loop_align (label
)) - 1;
3690 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3691 after applying N number of iterations. This routine does not determine
3692 how may iterations are required to reach desired alignment. */
3695 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
3702 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
3705 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
3715 /* Assuming that all other types are naturally aligned. CHECKME! */
3720 /* Return true if the vector misalignment factor is supported by the
3723 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
3730 /* Return if movmisalign pattern is not supported for this mode. */
3731 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
3734 if (misalignment
== -1)
3736 /* Misalignment factor is unknown at compile time but we know
3737 it's word aligned. */
3738 if (rs6000_vector_alignment_reachable (type
, is_packed
))
3740 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
3742 if (element_size
== 64 || element_size
== 32)
3749 /* VSX supports word-aligned vector. */
3750 if (misalignment
% 4 == 0)
3756 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3758 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
3759 tree vectype
, int misalign
)
3764 switch (type_of_cost
)
3774 case cond_branch_not_taken
:
3783 case vec_promote_demote
:
3789 case cond_branch_taken
:
3792 case unaligned_load
:
3793 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3795 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3797 /* Double word aligned. */
3805 /* Double word aligned. */
3809 /* Unknown misalignment. */
3822 /* Misaligned loads are not supported. */
3827 case unaligned_store
:
3828 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3830 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3832 /* Double word aligned. */
3840 /* Double word aligned. */
3844 /* Unknown misalignment. */
3857 /* Misaligned stores are not supported. */
3863 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3864 elem_type
= TREE_TYPE (vectype
);
3865 /* 32-bit vectors loaded into registers are stored as double
3866 precision, so we need n/2 converts in addition to the usual
3867 n/2 merges to construct a vector of short floats from them. */
3868 if (SCALAR_FLOAT_TYPE_P (elem_type
)
3869 && TYPE_PRECISION (elem_type
) == 32)
3870 return elements
+ 1;
3872 return elements
/ 2 + 1;
3879 /* Implement targetm.vectorize.preferred_simd_mode. */
3881 static enum machine_mode
3882 rs6000_preferred_simd_mode (enum machine_mode mode
)
3891 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3915 if (TARGET_PAIRED_FLOAT
3921 typedef struct _rs6000_cost_data
3923 struct loop
*loop_info
;
3927 /* Test for likely overcommitment of vector hardware resources. If a
3928 loop iteration is relatively large, and too large a percentage of
3929 instructions in the loop are vectorized, the cost model may not
3930 adequately reflect delays from unavailable vector resources.
3931 Penalize the loop body cost for this case. */
3934 rs6000_density_test (rs6000_cost_data
*data
)
3936 const int DENSITY_PCT_THRESHOLD
= 85;
3937 const int DENSITY_SIZE_THRESHOLD
= 70;
3938 const int DENSITY_PENALTY
= 10;
3939 struct loop
*loop
= data
->loop_info
;
3940 basic_block
*bbs
= get_loop_body (loop
);
3941 int nbbs
= loop
->num_nodes
;
3942 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
3945 for (i
= 0; i
< nbbs
; i
++)
3947 basic_block bb
= bbs
[i
];
3948 gimple_stmt_iterator gsi
;
3950 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
3952 gimple stmt
= gsi_stmt (gsi
);
3953 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
3955 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
3956 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
3962 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
3964 if (density_pct
> DENSITY_PCT_THRESHOLD
3965 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
3967 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
3968 if (dump_enabled_p ())
3969 dump_printf_loc (MSG_NOTE
, vect_location
,
3970 "density %d%%, cost %d exceeds threshold, penalizing "
3971 "loop body cost by %d%%", density_pct
,
3972 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
3976 /* Implement targetm.vectorize.init_cost. */
3979 rs6000_init_cost (struct loop
*loop_info
)
3981 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
3982 data
->loop_info
= loop_info
;
3983 data
->cost
[vect_prologue
] = 0;
3984 data
->cost
[vect_body
] = 0;
3985 data
->cost
[vect_epilogue
] = 0;
3989 /* Implement targetm.vectorize.add_stmt_cost. */
3992 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
3993 struct _stmt_vec_info
*stmt_info
, int misalign
,
3994 enum vect_cost_model_location where
)
3996 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
3997 unsigned retval
= 0;
3999 if (flag_vect_cost_model
)
4001 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4002 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4004 /* Statements in an inner loop relative to the loop being
4005 vectorized are weighted more heavily. The value here is
4006 arbitrary and could potentially be improved with analysis. */
4007 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4008 count
*= 50; /* FIXME. */
4010 retval
= (unsigned) (count
* stmt_cost
);
4011 cost_data
->cost
[where
] += retval
;
4017 /* Implement targetm.vectorize.finish_cost. */
4020 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4021 unsigned *body_cost
, unsigned *epilogue_cost
)
4023 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4025 if (cost_data
->loop_info
)
4026 rs6000_density_test (cost_data
);
4028 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4029 *body_cost
= cost_data
->cost
[vect_body
];
4030 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4033 /* Implement targetm.vectorize.destroy_cost_data. */
4036 rs6000_destroy_cost_data (void *data
)
4041 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4042 library with vectorized intrinsics. */
4045 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4048 const char *suffix
= NULL
;
4049 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4052 enum machine_mode el_mode
, in_mode
;
4055 /* Libmass is suitable for unsafe math only as it does not correctly support
4056 parts of IEEE with the required precision such as denormals. Only support
4057 it if we have VSX to use the simd d2 or f4 functions.
4058 XXX: Add variable length support. */
4059 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4062 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4063 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4064 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4065 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4066 if (el_mode
!= in_mode
4070 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4072 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4075 case BUILT_IN_ATAN2
:
4076 case BUILT_IN_HYPOT
:
4082 case BUILT_IN_ACOSH
:
4084 case BUILT_IN_ASINH
:
4086 case BUILT_IN_ATANH
:
4094 case BUILT_IN_EXPM1
:
4095 case BUILT_IN_LGAMMA
:
4096 case BUILT_IN_LOG10
:
4097 case BUILT_IN_LOG1P
:
4105 bdecl
= builtin_decl_implicit (fn
);
4106 suffix
= "d2"; /* pow -> powd2 */
4107 if (el_mode
!= DFmode
4113 case BUILT_IN_ATAN2F
:
4114 case BUILT_IN_HYPOTF
:
4119 case BUILT_IN_ACOSF
:
4120 case BUILT_IN_ACOSHF
:
4121 case BUILT_IN_ASINF
:
4122 case BUILT_IN_ASINHF
:
4123 case BUILT_IN_ATANF
:
4124 case BUILT_IN_ATANHF
:
4125 case BUILT_IN_CBRTF
:
4127 case BUILT_IN_COSHF
:
4129 case BUILT_IN_ERFCF
:
4130 case BUILT_IN_EXP2F
:
4132 case BUILT_IN_EXPM1F
:
4133 case BUILT_IN_LGAMMAF
:
4134 case BUILT_IN_LOG10F
:
4135 case BUILT_IN_LOG1PF
:
4136 case BUILT_IN_LOG2F
:
4139 case BUILT_IN_SINHF
:
4140 case BUILT_IN_SQRTF
:
4142 case BUILT_IN_TANHF
:
4143 bdecl
= builtin_decl_implicit (fn
);
4144 suffix
= "4"; /* powf -> powf4 */
4145 if (el_mode
!= SFmode
4158 gcc_assert (suffix
!= NULL
);
4159 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4163 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4164 strcat (name
, suffix
);
4167 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4168 else if (n_args
== 2)
4169 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4173 /* Build a function declaration for the vectorized function. */
4174 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4175 FUNCTION_DECL
, get_identifier (name
), fntype
);
4176 TREE_PUBLIC (new_fndecl
) = 1;
4177 DECL_EXTERNAL (new_fndecl
) = 1;
4178 DECL_IS_NOVOPS (new_fndecl
) = 1;
4179 TREE_READONLY (new_fndecl
) = 1;
4184 /* Returns a function decl for a vectorized version of the builtin function
4185 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4186 if it is not available. */
4189 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4192 enum machine_mode in_mode
, out_mode
;
4195 if (TARGET_DEBUG_BUILTIN
)
4196 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4197 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4198 GET_MODE_NAME (TYPE_MODE (type_out
)),
4199 GET_MODE_NAME (TYPE_MODE (type_in
)));
4201 if (TREE_CODE (type_out
) != VECTOR_TYPE
4202 || TREE_CODE (type_in
) != VECTOR_TYPE
4203 || !TARGET_VECTORIZE_BUILTINS
)
4206 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4207 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4208 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4209 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4211 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4213 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4216 case BUILT_IN_CLZIMAX
:
4217 case BUILT_IN_CLZLL
:
4220 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4222 if (out_mode
== QImode
&& out_n
== 16)
4223 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4224 else if (out_mode
== HImode
&& out_n
== 8)
4225 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4226 else if (out_mode
== SImode
&& out_n
== 4)
4227 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4228 else if (out_mode
== DImode
&& out_n
== 2)
4229 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4232 case BUILT_IN_COPYSIGN
:
4233 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4234 && out_mode
== DFmode
&& out_n
== 2
4235 && in_mode
== DFmode
&& in_n
== 2)
4236 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4238 case BUILT_IN_COPYSIGNF
:
4239 if (out_mode
!= SFmode
|| out_n
!= 4
4240 || in_mode
!= SFmode
|| in_n
!= 4)
4242 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4243 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4244 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4245 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4247 case BUILT_IN_POPCOUNTIMAX
:
4248 case BUILT_IN_POPCOUNTLL
:
4249 case BUILT_IN_POPCOUNTL
:
4250 case BUILT_IN_POPCOUNT
:
4251 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4253 if (out_mode
== QImode
&& out_n
== 16)
4254 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4255 else if (out_mode
== HImode
&& out_n
== 8)
4256 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4257 else if (out_mode
== SImode
&& out_n
== 4)
4258 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4259 else if (out_mode
== DImode
&& out_n
== 2)
4260 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4264 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4265 && out_mode
== DFmode
&& out_n
== 2
4266 && in_mode
== DFmode
&& in_n
== 2)
4267 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4269 case BUILT_IN_SQRTF
:
4270 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4271 && out_mode
== SFmode
&& out_n
== 4
4272 && in_mode
== SFmode
&& in_n
== 4)
4273 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4276 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4277 && out_mode
== DFmode
&& out_n
== 2
4278 && in_mode
== DFmode
&& in_n
== 2)
4279 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4281 case BUILT_IN_CEILF
:
4282 if (out_mode
!= SFmode
|| out_n
!= 4
4283 || in_mode
!= SFmode
|| in_n
!= 4)
4285 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4286 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4287 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4288 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4290 case BUILT_IN_FLOOR
:
4291 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4292 && out_mode
== DFmode
&& out_n
== 2
4293 && in_mode
== DFmode
&& in_n
== 2)
4294 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4296 case BUILT_IN_FLOORF
:
4297 if (out_mode
!= SFmode
|| out_n
!= 4
4298 || in_mode
!= SFmode
|| in_n
!= 4)
4300 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4301 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4302 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4303 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4306 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4307 && out_mode
== DFmode
&& out_n
== 2
4308 && in_mode
== DFmode
&& in_n
== 2)
4309 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4312 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4313 && out_mode
== SFmode
&& out_n
== 4
4314 && in_mode
== SFmode
&& in_n
== 4)
4315 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4316 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4317 && out_mode
== SFmode
&& out_n
== 4
4318 && in_mode
== SFmode
&& in_n
== 4)
4319 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4321 case BUILT_IN_TRUNC
:
4322 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4323 && out_mode
== DFmode
&& out_n
== 2
4324 && in_mode
== DFmode
&& in_n
== 2)
4325 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4327 case BUILT_IN_TRUNCF
:
4328 if (out_mode
!= SFmode
|| out_n
!= 4
4329 || in_mode
!= SFmode
|| in_n
!= 4)
4331 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4332 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4333 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4334 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4336 case BUILT_IN_NEARBYINT
:
4337 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4338 && flag_unsafe_math_optimizations
4339 && out_mode
== DFmode
&& out_n
== 2
4340 && in_mode
== DFmode
&& in_n
== 2)
4341 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4343 case BUILT_IN_NEARBYINTF
:
4344 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4345 && flag_unsafe_math_optimizations
4346 && out_mode
== SFmode
&& out_n
== 4
4347 && in_mode
== SFmode
&& in_n
== 4)
4348 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4351 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4352 && !flag_trapping_math
4353 && out_mode
== DFmode
&& out_n
== 2
4354 && in_mode
== DFmode
&& in_n
== 2)
4355 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4357 case BUILT_IN_RINTF
:
4358 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4359 && !flag_trapping_math
4360 && out_mode
== SFmode
&& out_n
== 4
4361 && in_mode
== SFmode
&& in_n
== 4)
4362 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4369 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4371 enum rs6000_builtins fn
4372 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4375 case RS6000_BUILTIN_RSQRTF
:
4376 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4377 && out_mode
== SFmode
&& out_n
== 4
4378 && in_mode
== SFmode
&& in_n
== 4)
4379 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4381 case RS6000_BUILTIN_RSQRT
:
4382 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4383 && out_mode
== DFmode
&& out_n
== 2
4384 && in_mode
== DFmode
&& in_n
== 2)
4385 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4387 case RS6000_BUILTIN_RECIPF
:
4388 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4389 && out_mode
== SFmode
&& out_n
== 4
4390 && in_mode
== SFmode
&& in_n
== 4)
4391 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4393 case RS6000_BUILTIN_RECIP
:
4394 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4395 && out_mode
== DFmode
&& out_n
== 2
4396 && in_mode
== DFmode
&& in_n
== 2)
4397 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4404 /* Generate calls to libmass if appropriate. */
4405 if (rs6000_veclib_handler
)
4406 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4411 /* Default CPU string for rs6000*_file_start functions. */
4412 static const char *rs6000_default_cpu
;
4414 /* Do anything needed at the start of the asm file. */
4417 rs6000_file_start (void)
4420 const char *start
= buffer
;
4421 FILE *file
= asm_out_file
;
4423 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4425 default_file_start ();
4427 if (flag_verbose_asm
)
4429 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4431 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4433 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4437 if (global_options_set
.x_rs6000_cpu_index
)
4439 fprintf (file
, "%s -mcpu=%s", start
,
4440 processor_target_table
[rs6000_cpu_index
].name
);
4444 if (global_options_set
.x_rs6000_tune_index
)
4446 fprintf (file
, "%s -mtune=%s", start
,
4447 processor_target_table
[rs6000_tune_index
].name
);
4451 if (PPC405_ERRATUM77
)
4453 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4457 #ifdef USING_ELFOS_H
4458 switch (rs6000_sdata
)
4460 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4461 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4462 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4463 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4466 if (rs6000_sdata
&& g_switch_value
)
4468 fprintf (file
, "%s -G %d", start
,
4478 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
4480 switch_to_section (toc_section
);
4481 switch_to_section (text_section
);
4486 /* Return nonzero if this function is known to have a null epilogue. */
4489 direct_return (void)
4491 if (reload_completed
)
4493 rs6000_stack_t
*info
= rs6000_stack_info ();
4495 if (info
->first_gp_reg_save
== 32
4496 && info
->first_fp_reg_save
== 64
4497 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4498 && ! info
->lr_save_p
4499 && ! info
->cr_save_p
4500 && info
->vrsave_mask
== 0
4508 /* Return the number of instructions it takes to form a constant in an
4509 integer register. */
4512 num_insns_constant_wide (HOST_WIDE_INT value
)
4514 /* signed constant loadable with addi */
4515 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4518 /* constant loadable with addis */
4519 else if ((value
& 0xffff) == 0
4520 && (value
>> 31 == -1 || value
>> 31 == 0))
4523 else if (TARGET_POWERPC64
)
4525 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4526 HOST_WIDE_INT high
= value
>> 31;
4528 if (high
== 0 || high
== -1)
4534 return num_insns_constant_wide (high
) + 1;
4536 return num_insns_constant_wide (low
) + 1;
4538 return (num_insns_constant_wide (high
)
4539 + num_insns_constant_wide (low
) + 1);
4547 num_insns_constant (rtx op
, enum machine_mode mode
)
4549 HOST_WIDE_INT low
, high
;
4551 switch (GET_CODE (op
))
4554 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4555 && mask64_operand (op
, mode
))
4558 return num_insns_constant_wide (INTVAL (op
));
4561 if (mode
== SFmode
|| mode
== SDmode
)
4566 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4567 if (DECIMAL_FLOAT_MODE_P (mode
))
4568 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4570 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4571 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4577 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4578 if (DECIMAL_FLOAT_MODE_P (mode
))
4579 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4581 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4582 high
= l
[WORDS_BIG_ENDIAN
== 0];
4583 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4586 return (num_insns_constant_wide (low
)
4587 + num_insns_constant_wide (high
));
4590 if ((high
== 0 && low
>= 0)
4591 || (high
== -1 && low
< 0))
4592 return num_insns_constant_wide (low
);
4594 else if (mask64_operand (op
, mode
))
4598 return num_insns_constant_wide (high
) + 1;
4601 return (num_insns_constant_wide (high
)
4602 + num_insns_constant_wide (low
) + 1);
4610 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4611 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4612 corresponding element of the vector, but for V4SFmode and V2SFmode,
4613 the corresponding "float" is interpreted as an SImode integer. */
4616 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4620 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4621 gcc_assert (GET_MODE (op
) != V2DImode
4622 && GET_MODE (op
) != V2DFmode
);
4624 tmp
= CONST_VECTOR_ELT (op
, elt
);
4625 if (GET_MODE (op
) == V4SFmode
4626 || GET_MODE (op
) == V2SFmode
)
4627 tmp
= gen_lowpart (SImode
, tmp
);
4628 return INTVAL (tmp
);
4631 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4632 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4633 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4634 all items are set to the same value and contain COPIES replicas of the
4635 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4636 operand and the others are set to the value of the operand's msb. */
4639 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4641 enum machine_mode mode
= GET_MODE (op
);
4642 enum machine_mode inner
= GET_MODE_INNER (mode
);
4650 HOST_WIDE_INT splat_val
;
4651 HOST_WIDE_INT msb_val
;
4653 if (mode
== V2DImode
|| mode
== V2DFmode
)
4656 nunits
= GET_MODE_NUNITS (mode
);
4657 bitsize
= GET_MODE_BITSIZE (inner
);
4658 mask
= GET_MODE_MASK (inner
);
4660 val
= const_vector_elt_as_int (op
, nunits
- 1);
4662 msb_val
= val
> 0 ? 0 : -1;
4664 /* Construct the value to be splatted, if possible. If not, return 0. */
4665 for (i
= 2; i
<= copies
; i
*= 2)
4667 HOST_WIDE_INT small_val
;
4669 small_val
= splat_val
>> bitsize
;
4671 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4673 splat_val
= small_val
;
4676 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4677 if (EASY_VECTOR_15 (splat_val
))
4680 /* Also check if we can splat, and then add the result to itself. Do so if
4681 the value is positive, of if the splat instruction is using OP's mode;
4682 for splat_val < 0, the splat and the add should use the same mode. */
4683 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
4684 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
4687 /* Also check if are loading up the most significant bit which can be done by
4688 loading up -1 and shifting the value left by -1. */
4689 else if (EASY_VECTOR_MSB (splat_val
, inner
))
4695 /* Check if VAL is present in every STEP-th element, and the
4696 other elements are filled with its most significant bit. */
4697 for (i
= 0; i
< nunits
- 1; ++i
)
4699 HOST_WIDE_INT desired_val
;
4700 if (((i
+ 1) & (step
- 1)) == 0)
4703 desired_val
= msb_val
;
4705 if (desired_val
!= const_vector_elt_as_int (op
, i
))
4713 /* Return true if OP is of the given MODE and can be synthesized
4714 with a vspltisb, vspltish or vspltisw. */
4717 easy_altivec_constant (rtx op
, enum machine_mode mode
)
4719 unsigned step
, copies
;
4721 if (mode
== VOIDmode
)
4722 mode
= GET_MODE (op
);
4723 else if (mode
!= GET_MODE (op
))
4726 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4728 if (mode
== V2DFmode
)
4729 return zero_constant (op
, mode
);
4731 if (mode
== V2DImode
)
4733 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4735 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
4736 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
4739 if (zero_constant (op
, mode
))
4742 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
4743 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
4749 /* Start with a vspltisw. */
4750 step
= GET_MODE_NUNITS (mode
) / 4;
4753 if (vspltis_constant (op
, step
, copies
))
4756 /* Then try with a vspltish. */
4762 if (vspltis_constant (op
, step
, copies
))
4765 /* And finally a vspltisb. */
4771 if (vspltis_constant (op
, step
, copies
))
4777 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4778 result is OP. Abort if it is not possible. */
4781 gen_easy_altivec_constant (rtx op
)
4783 enum machine_mode mode
= GET_MODE (op
);
4784 int nunits
= GET_MODE_NUNITS (mode
);
4785 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
4786 unsigned step
= nunits
/ 4;
4787 unsigned copies
= 1;
4789 /* Start with a vspltisw. */
4790 if (vspltis_constant (op
, step
, copies
))
4791 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
4793 /* Then try with a vspltish. */
4799 if (vspltis_constant (op
, step
, copies
))
4800 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
4802 /* And finally a vspltisb. */
4808 if (vspltis_constant (op
, step
, copies
))
4809 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
4815 output_vec_const_move (rtx
*operands
)
4818 enum machine_mode mode
;
4823 mode
= GET_MODE (dest
);
4827 if (zero_constant (vec
, mode
))
4828 return "xxlxor %x0,%x0,%x0";
4830 if (mode
== V2DImode
4831 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
4832 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
4833 return "vspltisw %0,-1";
4839 if (zero_constant (vec
, mode
))
4840 return "vxor %0,%0,%0";
4842 splat_vec
= gen_easy_altivec_constant (vec
);
4843 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
4844 operands
[1] = XEXP (splat_vec
, 0);
4845 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
4848 switch (GET_MODE (splat_vec
))
4851 return "vspltisw %0,%1";
4854 return "vspltish %0,%1";
4857 return "vspltisb %0,%1";
4864 gcc_assert (TARGET_SPE
);
4866 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4867 pattern of V1DI, V4HI, and V2SF.
4869 FIXME: We should probably return # and add post reload
4870 splitters for these, but this way is so easy ;-). */
4871 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
4872 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
4873 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
4874 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
4876 return "li %0,%1\n\tevmergelo %0,%0,%0";
4878 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4881 /* Initialize TARGET of vector PAIRED to VALS. */
4884 paired_expand_vector_init (rtx target
, rtx vals
)
4886 enum machine_mode mode
= GET_MODE (target
);
4887 int n_elts
= GET_MODE_NUNITS (mode
);
4889 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
4892 for (i
= 0; i
< n_elts
; ++i
)
4894 x
= XVECEXP (vals
, 0, i
);
4895 if (!(CONST_INT_P (x
)
4896 || GET_CODE (x
) == CONST_DOUBLE
4897 || GET_CODE (x
) == CONST_FIXED
))
4902 /* Load from constant pool. */
4903 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
4909 /* The vector is initialized only with non-constants. */
4910 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
4911 XVECEXP (vals
, 0, 1));
4913 emit_move_insn (target
, new_rtx
);
4917 /* One field is non-constant and the other one is a constant. Load the
4918 constant from the constant pool and use ps_merge instruction to
4919 construct the whole vector. */
4920 op1
= XVECEXP (vals
, 0, 0);
4921 op2
= XVECEXP (vals
, 0, 1);
4923 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
4925 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
4926 emit_move_insn (tmp
, constant_op
);
4928 if (CONSTANT_P (op1
))
4929 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
4931 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
4933 emit_move_insn (target
, new_rtx
);
4937 paired_expand_vector_move (rtx operands
[])
4939 rtx op0
= operands
[0], op1
= operands
[1];
4941 emit_move_insn (op0
, op1
);
4944 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4945 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4946 operands for the relation operation COND. This is a recursive
4950 paired_emit_vector_compare (enum rtx_code rcode
,
4951 rtx dest
, rtx op0
, rtx op1
,
4952 rtx cc_op0
, rtx cc_op1
)
4954 rtx tmp
= gen_reg_rtx (V2SFmode
);
4957 gcc_assert (TARGET_PAIRED_FLOAT
);
4958 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
4964 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4968 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4969 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
4973 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
4976 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4979 tmp1
= gen_reg_rtx (V2SFmode
);
4980 max
= gen_reg_rtx (V2SFmode
);
4981 min
= gen_reg_rtx (V2SFmode
);
4982 gen_reg_rtx (V2SFmode
);
4984 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4985 emit_insn (gen_selv2sf4
4986 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4987 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
4988 emit_insn (gen_selv2sf4
4989 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4990 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
4991 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
4994 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4997 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5000 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5003 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5006 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5015 /* Emit vector conditional expression.
5016 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5017 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5020 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5021 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5023 enum rtx_code rcode
= GET_CODE (cond
);
5025 if (!TARGET_PAIRED_FLOAT
)
5028 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5033 /* Initialize vector TARGET to VALS. */
5036 rs6000_expand_vector_init (rtx target
, rtx vals
)
5038 enum machine_mode mode
= GET_MODE (target
);
5039 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5040 int n_elts
= GET_MODE_NUNITS (mode
);
5041 int n_var
= 0, one_var
= -1;
5042 bool all_same
= true, all_const_zero
= true;
5046 for (i
= 0; i
< n_elts
; ++i
)
5048 x
= XVECEXP (vals
, 0, i
);
5049 if (!(CONST_INT_P (x
)
5050 || GET_CODE (x
) == CONST_DOUBLE
5051 || GET_CODE (x
) == CONST_FIXED
))
5052 ++n_var
, one_var
= i
;
5053 else if (x
!= CONST0_RTX (inner_mode
))
5054 all_const_zero
= false;
5056 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5062 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5063 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5064 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5066 /* Zero register. */
5067 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5068 gen_rtx_XOR (mode
, target
, target
)));
5071 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5073 /* Splat immediate. */
5074 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5079 /* Load from constant pool. */
5080 emit_move_insn (target
, const_vec
);
5085 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5086 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5088 rtx op0
= XVECEXP (vals
, 0, 0);
5089 rtx op1
= XVECEXP (vals
, 0, 1);
5092 if (!MEM_P (op0
) && !REG_P (op0
))
5093 op0
= force_reg (inner_mode
, op0
);
5094 if (mode
== V2DFmode
)
5095 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5097 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5101 op0
= force_reg (inner_mode
, op0
);
5102 op1
= force_reg (inner_mode
, op1
);
5103 if (mode
== V2DFmode
)
5104 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5106 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5111 /* With single precision floating point on VSX, know that internally single
5112 precision is actually represented as a double, and either make 2 V2DF
5113 vectors, and convert these vectors to single precision, or do one
5114 conversion, and splat the result to the other elements. */
5115 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5119 rtx freg
= gen_reg_rtx (V4SFmode
);
5120 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5121 rtx cvt
= ((TARGET_XSCVDPSPN
)
5122 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5123 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5126 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
5130 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5131 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5132 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5133 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5134 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5135 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5136 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5137 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5139 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5140 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5141 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5142 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5143 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5148 /* Store value to stack temp. Load vector element. Splat. However, splat
5149 of 64-bit items is not supported on Altivec. */
5150 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5152 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5153 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5154 XVECEXP (vals
, 0, 0));
5155 x
= gen_rtx_UNSPEC (VOIDmode
,
5156 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5157 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5159 gen_rtx_SET (VOIDmode
,
5162 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5163 gen_rtx_PARALLEL (VOIDmode
,
5164 gen_rtvec (1, const0_rtx
)));
5165 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5166 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5170 /* One field is non-constant. Load constant then overwrite
5174 rtx copy
= copy_rtx (vals
);
5176 /* Load constant part of vector, substitute neighboring value for
5178 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5179 rs6000_expand_vector_init (target
, copy
);
5181 /* Insert variable. */
5182 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5186 /* Construct the vector in memory one field at a time
5187 and load the whole vector. */
5188 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5189 for (i
= 0; i
< n_elts
; i
++)
5190 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5191 i
* GET_MODE_SIZE (inner_mode
)),
5192 XVECEXP (vals
, 0, i
));
5193 emit_move_insn (target
, mem
);
5196 /* Set field ELT of TARGET to VAL. */
5199 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5201 enum machine_mode mode
= GET_MODE (target
);
5202 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5203 rtx reg
= gen_reg_rtx (mode
);
5205 int width
= GET_MODE_SIZE (inner_mode
);
5208 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5210 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5211 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5212 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5216 /* Load single variable value. */
5217 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5218 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5219 x
= gen_rtx_UNSPEC (VOIDmode
,
5220 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5221 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5223 gen_rtx_SET (VOIDmode
,
5227 /* Linear sequence. */
5228 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5229 for (i
= 0; i
< 16; ++i
)
5230 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5232 /* Set permute mask to insert element into target. */
5233 for (i
= 0; i
< width
; ++i
)
5234 XVECEXP (mask
, 0, elt
*width
+ i
)
5235 = GEN_INT (i
+ 0x10);
5236 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5237 x
= gen_rtx_UNSPEC (mode
,
5238 gen_rtvec (3, target
, reg
,
5239 force_reg (V16QImode
, x
)),
5241 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5244 /* Extract field ELT from VEC into TARGET. */
5247 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5249 enum machine_mode mode
= GET_MODE (vec
);
5250 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5253 if (VECTOR_MEM_VSX_P (mode
))
5260 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5263 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5266 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5271 /* Allocate mode-sized buffer. */
5272 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5274 emit_move_insn (mem
, vec
);
5276 /* Add offset to field within buffer matching vector element. */
5277 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5279 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5282 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5283 implement ANDing by the mask IN. */
5285 build_mask64_2_operands (rtx in
, rtx
*out
)
5287 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5290 gcc_assert (GET_CODE (in
) == CONST_INT
);
5295 /* Assume c initially something like 0x00fff000000fffff. The idea
5296 is to rotate the word so that the middle ^^^^^^ group of zeros
5297 is at the MS end and can be cleared with an rldicl mask. We then
5298 rotate back and clear off the MS ^^ group of zeros with a
5300 c
= ~c
; /* c == 0xff000ffffff00000 */
5301 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5302 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5303 c
= ~c
; /* c == 0x00fff000000fffff */
5304 c
&= -lsb
; /* c == 0x00fff00000000000 */
5305 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5306 c
= ~c
; /* c == 0xff000fffffffffff */
5307 c
&= -lsb
; /* c == 0xff00000000000000 */
5309 while ((lsb
>>= 1) != 0)
5310 shift
++; /* shift == 44 on exit from loop */
5311 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5312 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5313 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5317 /* Assume c initially something like 0xff000f0000000000. The idea
5318 is to rotate the word so that the ^^^ middle group of zeros
5319 is at the LS end and can be cleared with an rldicr mask. We then
5320 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5322 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5323 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5324 c
= ~c
; /* c == 0x00fff0ffffffffff */
5325 c
&= -lsb
; /* c == 0x00fff00000000000 */
5326 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5327 c
= ~c
; /* c == 0xff000fffffffffff */
5328 c
&= -lsb
; /* c == 0xff00000000000000 */
5330 while ((lsb
>>= 1) != 0)
5331 shift
++; /* shift == 44 on exit from loop */
5332 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5333 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5334 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5337 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5338 masks will be all 1's. We are guaranteed more than one transition. */
5339 out
[0] = GEN_INT (64 - shift
);
5340 out
[1] = GEN_INT (m1
);
5341 out
[2] = GEN_INT (shift
);
5342 out
[3] = GEN_INT (m2
);
5345 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5348 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5350 if (TARGET_E500_DOUBLE
)
5352 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5353 subreg:TI and reg:TF. Decimal float modes are like integer
5354 modes (only low part of each register used) for this
5356 if (GET_CODE (op
) == SUBREG
5357 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5358 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5359 && REG_P (SUBREG_REG (op
))
5360 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5361 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5364 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5366 if (GET_CODE (op
) == SUBREG
5367 && (mode
== DFmode
|| mode
== TFmode
)
5368 && REG_P (SUBREG_REG (op
))
5369 && (GET_MODE (SUBREG_REG (op
)) == DImode
5370 || GET_MODE (SUBREG_REG (op
)) == TImode
5371 || GET_MODE (SUBREG_REG (op
)) == PTImode
5372 || GET_MODE (SUBREG_REG (op
)) == DDmode
5373 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5378 && GET_CODE (op
) == SUBREG
5380 && REG_P (SUBREG_REG (op
))
5381 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5387 /* AIX increases natural record alignment to doubleword if the first
5388 field is an FP double while the FP fields remain word aligned. */
5391 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5392 unsigned int specified
)
5394 unsigned int align
= MAX (computed
, specified
);
5395 tree field
= TYPE_FIELDS (type
);
5397 /* Skip all non field decls */
5398 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5399 field
= DECL_CHAIN (field
);
5401 if (field
!= NULL
&& field
!= type
)
5403 type
= TREE_TYPE (field
);
5404 while (TREE_CODE (type
) == ARRAY_TYPE
)
5405 type
= TREE_TYPE (type
);
5407 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5408 align
= MAX (align
, 64);
5414 /* Darwin increases record alignment to the natural alignment of
5418 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5419 unsigned int specified
)
5421 unsigned int align
= MAX (computed
, specified
);
5423 if (TYPE_PACKED (type
))
5426 /* Find the first field, looking down into aggregates. */
5428 tree field
= TYPE_FIELDS (type
);
5429 /* Skip all non field decls */
5430 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5431 field
= DECL_CHAIN (field
);
5434 /* A packed field does not contribute any extra alignment. */
5435 if (DECL_PACKED (field
))
5437 type
= TREE_TYPE (field
);
5438 while (TREE_CODE (type
) == ARRAY_TYPE
)
5439 type
= TREE_TYPE (type
);
5440 } while (AGGREGATE_TYPE_P (type
));
5442 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5443 align
= MAX (align
, TYPE_ALIGN (type
));
5448 /* Return 1 for an operand in small memory on V.4/eabi. */
5451 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5452 enum machine_mode mode ATTRIBUTE_UNUSED
)
5457 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5460 if (DEFAULT_ABI
!= ABI_V4
)
5463 /* Vector and float memory instructions have a limited offset on the
5464 SPE, so using a vector or float variable directly as an operand is
5467 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5470 if (GET_CODE (op
) == SYMBOL_REF
)
5473 else if (GET_CODE (op
) != CONST
5474 || GET_CODE (XEXP (op
, 0)) != PLUS
5475 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5476 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5481 rtx sum
= XEXP (op
, 0);
5482 HOST_WIDE_INT summand
;
5484 /* We have to be careful here, because it is the referenced address
5485 that must be 32k from _SDA_BASE_, not just the symbol. */
5486 summand
= INTVAL (XEXP (sum
, 1));
5487 if (summand
< 0 || summand
> g_switch_value
)
5490 sym_ref
= XEXP (sum
, 0);
5493 return SYMBOL_REF_SMALL_P (sym_ref
);
5499 /* Return true if either operand is a general purpose register. */
5502 gpr_or_gpr_p (rtx op0
, rtx op1
)
5504 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5505 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5508 /* Return true if this is a move direct operation between GPR registers and
5509 floating point/VSX registers. */
5512 direct_move_p (rtx op0
, rtx op1
)
5516 if (!REG_P (op0
) || !REG_P (op1
))
5519 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
5522 regno0
= REGNO (op0
);
5523 regno1
= REGNO (op1
);
5524 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
5527 if (INT_REGNO_P (regno0
))
5528 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
5530 else if (INT_REGNO_P (regno1
))
5532 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
5535 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
5542 /* Return true if this is a load or store quad operation. */
5545 quad_load_store_p (rtx op0
, rtx op1
)
5549 if (!TARGET_QUAD_MEMORY
)
5552 else if (REG_P (op0
) && MEM_P (op1
))
5553 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
5554 && quad_memory_operand (op1
, GET_MODE (op1
))
5555 && !reg_overlap_mentioned_p (op0
, op1
));
5557 else if (MEM_P (op0
) && REG_P (op1
))
5558 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
5559 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
5564 if (TARGET_DEBUG_ADDR
)
5566 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
5567 ret
? "true" : "false");
5568 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
5574 /* Given an address, return a constant offset term if one exists. */
5577 address_offset (rtx op
)
5579 if (GET_CODE (op
) == PRE_INC
5580 || GET_CODE (op
) == PRE_DEC
)
5582 else if (GET_CODE (op
) == PRE_MODIFY
5583 || GET_CODE (op
) == LO_SUM
)
5586 if (GET_CODE (op
) == CONST
)
5589 if (GET_CODE (op
) == PLUS
)
5592 if (CONST_INT_P (op
))
5598 /* Return true if the MEM operand is a memory operand suitable for use
5599 with a (full width, possibly multiple) gpr load/store. On
5600 powerpc64 this means the offset must be divisible by 4.
5601 Implements 'Y' constraint.
5603 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5604 a constraint function we know the operand has satisfied a suitable
5605 memory predicate. Also accept some odd rtl generated by reload
5606 (see rs6000_legitimize_reload_address for various forms). It is
5607 important that reload rtl be accepted by appropriate constraints
5608 but not by the operand predicate.
5610 Offsetting a lo_sum should not be allowed, except where we know by
5611 alignment that a 32k boundary is not crossed, but see the ???
5612 comment in rs6000_legitimize_reload_address. Note that by
5613 "offsetting" here we mean a further offset to access parts of the
5614 MEM. It's fine to have a lo_sum where the inner address is offset
5615 from a sym, since the same sym+offset will appear in the high part
5616 of the address calculation. */
5619 mem_operand_gpr (rtx op
, enum machine_mode mode
)
5621 unsigned HOST_WIDE_INT offset
;
5623 rtx addr
= XEXP (op
, 0);
5625 op
= address_offset (addr
);
5629 offset
= INTVAL (op
);
5630 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
5633 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
5634 gcc_assert (extra
>= 0);
5636 if (GET_CODE (addr
) == LO_SUM
)
5637 /* For lo_sum addresses, we must allow any offset except one that
5638 causes a wrap, so test only the low 16 bits. */
5639 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
5641 return offset
+ 0x8000 < 0x10000u
- extra
;
5644 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5647 reg_offset_addressing_ok_p (enum machine_mode mode
)
5658 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
5659 TImode is not a vector mode, if we want to use the VSX registers to
5660 move it around, we need to restrict ourselves to reg+reg
5662 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
5670 /* Paired vector modes. Only reg+reg addressing is valid. */
5671 if (TARGET_PAIRED_FLOAT
)
5676 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
5677 addressing for the LFIWZX and STFIWX instructions. */
5678 if (TARGET_NO_SDMODE_STACK
)
5690 virtual_stack_registers_memory_p (rtx op
)
5694 if (GET_CODE (op
) == REG
)
5695 regnum
= REGNO (op
);
5697 else if (GET_CODE (op
) == PLUS
5698 && GET_CODE (XEXP (op
, 0)) == REG
5699 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
5700 regnum
= REGNO (XEXP (op
, 0));
5705 return (regnum
>= FIRST_VIRTUAL_REGISTER
5706 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
5709 /* Return true if a MODE sized memory accesses to OP plus OFFSET
5710 is known to not straddle a 32k boundary. */
5713 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
5714 enum machine_mode mode
)
5717 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
5719 if (GET_CODE (op
) != SYMBOL_REF
)
5722 dsize
= GET_MODE_SIZE (mode
);
5723 decl
= SYMBOL_REF_DECL (op
);
5729 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5730 replacing memory addresses with an anchor plus offset. We
5731 could find the decl by rummaging around in the block->objects
5732 VEC for the given offset but that seems like too much work. */
5733 dalign
= BITS_PER_UNIT
;
5734 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
5735 && SYMBOL_REF_ANCHOR_P (op
)
5736 && SYMBOL_REF_BLOCK (op
) != NULL
)
5738 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
5740 dalign
= block
->alignment
;
5741 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
5743 else if (CONSTANT_POOL_ADDRESS_P (op
))
5745 /* It would be nice to have get_pool_align().. */
5746 enum machine_mode cmode
= get_pool_mode (op
);
5748 dalign
= GET_MODE_ALIGNMENT (cmode
);
5751 else if (DECL_P (decl
))
5753 dalign
= DECL_ALIGN (decl
);
5757 /* Allow BLKmode when the entire object is known to not
5758 cross a 32k boundary. */
5759 if (!DECL_SIZE_UNIT (decl
))
5762 if (!host_integerp (DECL_SIZE_UNIT (decl
), 1))
5765 dsize
= tree_low_cst (DECL_SIZE_UNIT (decl
), 1);
5769 return dalign
/ BITS_PER_UNIT
>= dsize
;
5774 type
= TREE_TYPE (decl
);
5776 dalign
= TYPE_ALIGN (type
);
5777 if (CONSTANT_CLASS_P (decl
))
5778 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
5780 dalign
= DATA_ALIGNMENT (decl
, dalign
);
5784 /* BLKmode, check the entire object. */
5785 if (TREE_CODE (decl
) == STRING_CST
)
5786 dsize
= TREE_STRING_LENGTH (decl
);
5787 else if (TYPE_SIZE_UNIT (type
)
5788 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5789 dsize
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
5795 return dalign
/ BITS_PER_UNIT
>= dsize
;
5799 /* Find how many bits of the alignment we know for this access. */
5800 mask
= dalign
/ BITS_PER_UNIT
- 1;
5801 lsb
= offset
& -offset
;
5805 return dalign
>= dsize
;
5809 constant_pool_expr_p (rtx op
)
5813 split_const (op
, &base
, &offset
);
5814 return (GET_CODE (base
) == SYMBOL_REF
5815 && CONSTANT_POOL_ADDRESS_P (base
)
5816 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
5819 static const_rtx tocrel_base
, tocrel_offset
;
5821 /* Return true if OP is a toc pointer relative address (the output
5822 of create_TOC_reference). If STRICT, do not match high part or
5823 non-split -mcmodel=large/medium toc pointer relative addresses. */
5826 toc_relative_expr_p (const_rtx op
, bool strict
)
5831 if (TARGET_CMODEL
!= CMODEL_SMALL
)
5833 /* Only match the low part. */
5834 if (GET_CODE (op
) == LO_SUM
5835 && REG_P (XEXP (op
, 0))
5836 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
5843 tocrel_offset
= const0_rtx
;
5844 if (GET_CODE (op
) == PLUS
&& CONST_INT_P (XEXP (op
, 1)))
5846 tocrel_base
= XEXP (op
, 0);
5847 tocrel_offset
= XEXP (op
, 1);
5850 return (GET_CODE (tocrel_base
) == UNSPEC
5851 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
5854 /* Return true if X is a constant pool address, and also for cmodel=medium
5855 if X is a toc-relative address known to be offsettable within MODE. */
5858 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
5861 return (toc_relative_expr_p (x
, strict
)
5862 && (TARGET_CMODEL
!= CMODEL_MEDIUM
5863 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
5865 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
5866 INTVAL (tocrel_offset
), mode
)));
5870 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
5872 return (DEFAULT_ABI
== ABI_V4
5873 && !flag_pic
&& !TARGET_TOC
5874 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
5875 && small_data_operand (x
, mode
));
5878 /* SPE offset addressing is limited to 5-bits worth of double words. */
5879 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5882 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
5883 bool strict
, bool worst_case
)
5885 unsigned HOST_WIDE_INT offset
;
5888 if (GET_CODE (x
) != PLUS
)
5890 if (!REG_P (XEXP (x
, 0)))
5892 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5894 if (!reg_offset_addressing_ok_p (mode
))
5895 return virtual_stack_registers_memory_p (x
);
5896 if (legitimate_constant_pool_address_p (x
, mode
, strict
))
5898 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5901 offset
= INTVAL (XEXP (x
, 1));
5909 /* SPE vector modes. */
5910 return SPE_CONST_OFFSET_OK (offset
);
5915 /* On e500v2, we may have:
5917 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5919 Which gets addressed with evldd instructions. */
5920 if (TARGET_E500_DOUBLE
)
5921 return SPE_CONST_OFFSET_OK (offset
);
5923 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5925 if (VECTOR_MEM_VSX_P (mode
))
5930 if (!TARGET_POWERPC64
)
5932 else if (offset
& 3)
5940 if (TARGET_E500_DOUBLE
)
5941 return (SPE_CONST_OFFSET_OK (offset
)
5942 && SPE_CONST_OFFSET_OK (offset
+ 8));
5947 if (!TARGET_POWERPC64
)
5949 else if (offset
& 3)
5958 return offset
< 0x10000 - extra
;
5962 legitimate_indexed_address_p (rtx x
, int strict
)
5966 if (GET_CODE (x
) != PLUS
)
5972 /* Recognize the rtl generated by reload which we know will later be
5973 replaced with proper base and index regs. */
5975 && reload_in_progress
5976 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
5980 return (REG_P (op0
) && REG_P (op1
)
5981 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
5982 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
5983 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
5984 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
5988 avoiding_indexed_address_p (enum machine_mode mode
)
5990 /* Avoid indexed addressing for modes that have non-indexed
5991 load/store instruction forms. */
5992 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
5996 legitimate_indirect_address_p (rtx x
, int strict
)
5998 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6002 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6004 if (!TARGET_MACHO
|| !flag_pic
6005 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6009 if (GET_CODE (x
) != LO_SUM
)
6011 if (GET_CODE (XEXP (x
, 0)) != REG
)
6013 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6017 return CONSTANT_P (x
);
6021 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6023 if (GET_CODE (x
) != LO_SUM
)
6025 if (GET_CODE (XEXP (x
, 0)) != REG
)
6027 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6029 /* Restrict addressing for DI because of our SUBREG hackery. */
6030 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6034 if (TARGET_ELF
|| TARGET_MACHO
)
6036 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
6040 if (GET_MODE_NUNITS (mode
) != 1)
6042 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6043 && !(/* ??? Assume floating point reg based on mode? */
6044 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6045 && (mode
== DFmode
|| mode
== DDmode
)))
6048 return CONSTANT_P (x
);
6055 /* Try machine-dependent ways of modifying an illegitimate address
6056 to be legitimate. If we find one, return the new, valid address.
6057 This is used from only one place: `memory_address' in explow.c.
6059 OLDX is the address as it was before break_out_memory_refs was
6060 called. In some cases it is useful to look at this to decide what
6063 It is always safe for this function to do nothing. It exists to
6064 recognize opportunities to optimize the output.
6066 On RS/6000, first check for the sum of a register with a constant
6067 integer that is out of range. If so, generate code to add the
6068 constant with the low-order 16 bits masked to the register and force
6069 this result into another register (this can be done with `cau').
6070 Then generate an address of REG+(CONST&0xffff), allowing for the
6071 possibility of bit 16 being a one.
6073 Then check for the sum of a register and something not constant, try to
6074 load the other things into a register and return the sum. */
6077 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6078 enum machine_mode mode
)
6082 if (!reg_offset_addressing_ok_p (mode
))
6084 if (virtual_stack_registers_memory_p (x
))
6087 /* In theory we should not be seeing addresses of the form reg+0,
6088 but just in case it is generated, optimize it away. */
6089 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6090 return force_reg (Pmode
, XEXP (x
, 0));
6092 /* For TImode with load/store quad, restrict addresses to just a single
6093 pointer, so it works with both GPRs and VSX registers. */
6094 /* Make sure both operands are registers. */
6095 else if (GET_CODE (x
) == PLUS
6096 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6097 return gen_rtx_PLUS (Pmode
,
6098 force_reg (Pmode
, XEXP (x
, 0)),
6099 force_reg (Pmode
, XEXP (x
, 1)));
6101 return force_reg (Pmode
, x
);
6103 if (GET_CODE (x
) == SYMBOL_REF
)
6105 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6107 return rs6000_legitimize_tls_address (x
, model
);
6117 /* As in legitimate_offset_address_p we do not assume
6118 worst-case. The mode here is just a hint as to the registers
6119 used. A TImode is usually in gprs, but may actually be in
6120 fprs. Leave worst-case scenario for reload to handle via
6121 insn constraints. PTImode is only GPRs. */
6128 if (GET_CODE (x
) == PLUS
6129 && GET_CODE (XEXP (x
, 0)) == REG
6130 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6131 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6133 && !(SPE_VECTOR_MODE (mode
)
6134 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6136 HOST_WIDE_INT high_int
, low_int
;
6138 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6139 if (low_int
>= 0x8000 - extra
)
6141 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6142 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6143 GEN_INT (high_int
)), 0);
6144 return plus_constant (Pmode
, sum
, low_int
);
6146 else if (GET_CODE (x
) == PLUS
6147 && GET_CODE (XEXP (x
, 0)) == REG
6148 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6149 && GET_MODE_NUNITS (mode
) == 1
6150 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6151 || (/* ??? Assume floating point reg based on mode? */
6152 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6153 && (mode
== DFmode
|| mode
== DDmode
)))
6154 && !avoiding_indexed_address_p (mode
))
6156 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6157 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6159 else if (SPE_VECTOR_MODE (mode
)
6160 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6164 /* We accept [reg + reg] and [reg + OFFSET]. */
6166 if (GET_CODE (x
) == PLUS
)
6168 rtx op1
= XEXP (x
, 0);
6169 rtx op2
= XEXP (x
, 1);
6172 op1
= force_reg (Pmode
, op1
);
6174 if (GET_CODE (op2
) != REG
6175 && (GET_CODE (op2
) != CONST_INT
6176 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6177 || (GET_MODE_SIZE (mode
) > 8
6178 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6179 op2
= force_reg (Pmode
, op2
);
6181 /* We can't always do [reg + reg] for these, because [reg +
6182 reg + offset] is not a legitimate addressing mode. */
6183 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6185 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6186 return force_reg (Pmode
, y
);
6191 return force_reg (Pmode
, x
);
6193 else if ((TARGET_ELF
6195 || !MACHO_DYNAMIC_NO_PIC_P
6201 && GET_CODE (x
) != CONST_INT
6202 && GET_CODE (x
) != CONST_DOUBLE
6204 && GET_MODE_NUNITS (mode
) == 1
6205 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6206 || (/* ??? Assume floating point reg based on mode? */
6207 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6208 && (mode
== DFmode
|| mode
== DDmode
))))
6210 rtx reg
= gen_reg_rtx (Pmode
);
6212 emit_insn (gen_elf_high (reg
, x
));
6214 emit_insn (gen_macho_high (reg
, x
));
6215 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6218 && GET_CODE (x
) == SYMBOL_REF
6219 && constant_pool_expr_p (x
)
6220 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6221 return create_TOC_reference (x
, NULL_RTX
);
6226 /* Debug version of rs6000_legitimize_address. */
6228 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6234 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6235 insns
= get_insns ();
6241 "\nrs6000_legitimize_address: mode %s, old code %s, "
6242 "new code %s, modified\n",
6243 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6244 GET_RTX_NAME (GET_CODE (ret
)));
6246 fprintf (stderr
, "Original address:\n");
6249 fprintf (stderr
, "oldx:\n");
6252 fprintf (stderr
, "New address:\n");
6257 fprintf (stderr
, "Insns added:\n");
6258 debug_rtx_list (insns
, 20);
6264 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6265 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6276 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6277 We need to emit DTP-relative relocations. */
6279 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6281 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6286 fputs ("\t.long\t", file
);
6289 fputs (DOUBLE_INT_ASM_OP
, file
);
6294 output_addr_const (file
, x
);
6295 fputs ("@dtprel+0x8000", file
);
6298 /* In the name of slightly smaller debug output, and to cater to
6299 general assembler lossage, recognize various UNSPEC sequences
6300 and turn them back into a direct symbol reference. */
6303 rs6000_delegitimize_address (rtx orig_x
)
6307 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6313 if (TARGET_CMODEL
!= CMODEL_SMALL
6314 && GET_CODE (y
) == LO_SUM
)
6318 if (GET_CODE (y
) == PLUS
6319 && GET_MODE (y
) == Pmode
6320 && CONST_INT_P (XEXP (y
, 1)))
6322 offset
= XEXP (y
, 1);
6326 if (GET_CODE (y
) == UNSPEC
6327 && XINT (y
, 1) == UNSPEC_TOCREL
)
6329 #ifdef ENABLE_CHECKING
6330 if (REG_P (XVECEXP (y
, 0, 1))
6331 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6335 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6337 /* Weirdness alert. df_note_compute can replace r2 with a
6338 debug_expr when this unspec is in a debug_insn.
6339 Seen in gcc.dg/pr51957-1.c */
6347 y
= XVECEXP (y
, 0, 0);
6350 /* Do not associate thread-local symbols with the original
6351 constant pool symbol. */
6353 && GET_CODE (y
) == SYMBOL_REF
6354 && CONSTANT_POOL_ADDRESS_P (y
)
6355 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
6359 if (offset
!= NULL_RTX
)
6360 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6361 if (!MEM_P (orig_x
))
6364 return replace_equiv_address_nv (orig_x
, y
);
6368 && GET_CODE (orig_x
) == LO_SUM
6369 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6371 y
= XEXP (XEXP (orig_x
, 1), 0);
6372 if (GET_CODE (y
) == UNSPEC
6373 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6374 return XVECEXP (y
, 0, 0);
6380 /* Return true if X shouldn't be emitted into the debug info.
6381 The linker doesn't like .toc section references from
6382 .debug_* sections, so reject .toc section symbols. */
6385 rs6000_const_not_ok_for_debug_p (rtx x
)
6387 if (GET_CODE (x
) == SYMBOL_REF
6388 && CONSTANT_POOL_ADDRESS_P (x
))
6390 rtx c
= get_pool_constant (x
);
6391 enum machine_mode cmode
= get_pool_mode (x
);
6392 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6399 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6401 static GTY(()) rtx rs6000_tls_symbol
;
6403 rs6000_tls_get_addr (void)
6405 if (!rs6000_tls_symbol
)
6406 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6408 return rs6000_tls_symbol
;
6411 /* Construct the SYMBOL_REF for TLS GOT references. */
6413 static GTY(()) rtx rs6000_got_symbol
;
6415 rs6000_got_sym (void)
6417 if (!rs6000_got_symbol
)
6419 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6420 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6421 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6424 return rs6000_got_symbol
;
6427 /* AIX Thread-Local Address support. */
6430 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6432 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6436 name
= XSTR (addr
, 0);
6437 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6438 or the symbol will be in TLS private data section. */
6439 if (name
[strlen (name
) - 1] != ']'
6440 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6441 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6443 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6444 strcpy (tlsname
, name
);
6446 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6447 tlsaddr
= copy_rtx (addr
);
6448 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6453 /* Place addr into TOC constant pool. */
6454 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6456 /* Output the TOC entry and create the MEM referencing the value. */
6457 if (constant_pool_expr_p (XEXP (sym
, 0))
6458 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6460 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6461 mem
= gen_const_mem (Pmode
, tocref
);
6462 set_mem_alias_set (mem
, get_TOC_alias_set ());
6467 /* Use global-dynamic for local-dynamic. */
6468 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6469 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6471 /* Create new TOC reference for @m symbol. */
6472 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6473 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6474 strcpy (tlsname
, "*LCM");
6475 strcat (tlsname
, name
+ 3);
6476 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6477 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6478 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6479 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6480 set_mem_alias_set (modmem
, get_TOC_alias_set ());
6482 rtx modreg
= gen_reg_rtx (Pmode
);
6483 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
6485 tmpreg
= gen_reg_rtx (Pmode
);
6486 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6488 dest
= gen_reg_rtx (Pmode
);
6490 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
6492 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
6495 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
6496 else if (TARGET_32BIT
)
6498 tlsreg
= gen_reg_rtx (SImode
);
6499 emit_insn (gen_tls_get_tpointer (tlsreg
));
6502 tlsreg
= gen_rtx_REG (DImode
, 13);
6504 /* Load the TOC value into temporary register. */
6505 tmpreg
= gen_reg_rtx (Pmode
);
6506 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6507 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
6508 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
6510 /* Add TOC symbol value to TLS pointer. */
6511 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
6516 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
6517 this (thread-local) address. */
6520 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6525 return rs6000_legitimize_tls_address_aix (addr
, model
);
6527 dest
= gen_reg_rtx (Pmode
);
6528 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
6534 tlsreg
= gen_rtx_REG (Pmode
, 13);
6535 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
6539 tlsreg
= gen_rtx_REG (Pmode
, 2);
6540 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
6544 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
6548 tmp
= gen_reg_rtx (Pmode
);
6551 tlsreg
= gen_rtx_REG (Pmode
, 13);
6552 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6556 tlsreg
= gen_rtx_REG (Pmode
, 2);
6557 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6561 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6563 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6568 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6570 /* We currently use relocations like @got@tlsgd for tls, which
6571 means the linker will handle allocation of tls entries, placing
6572 them in the .got section. So use a pointer to the .got section,
6573 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6574 or to secondary GOT sections used by 32-bit -fPIC. */
6576 got
= gen_rtx_REG (Pmode
, 2);
6580 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6583 rtx gsym
= rs6000_got_sym ();
6584 got
= gen_reg_rtx (Pmode
);
6586 rs6000_emit_move (got
, gsym
, Pmode
);
6591 tmp1
= gen_reg_rtx (Pmode
);
6592 tmp2
= gen_reg_rtx (Pmode
);
6593 mem
= gen_const_mem (Pmode
, tmp1
);
6594 lab
= gen_label_rtx ();
6595 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6596 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6597 if (TARGET_LINK_STACK
)
6598 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6599 emit_move_insn (tmp2
, mem
);
6600 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
6601 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
6606 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
6608 tga
= rs6000_tls_get_addr ();
6609 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
6610 1, const0_rtx
, Pmode
);
6612 r3
= gen_rtx_REG (Pmode
, 3);
6613 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6614 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
6615 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6616 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
6617 else if (DEFAULT_ABI
== ABI_V4
)
6618 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
6621 call_insn
= last_call_insn ();
6622 PATTERN (call_insn
) = insn
;
6623 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6624 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6625 pic_offset_table_rtx
);
6627 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
6629 tga
= rs6000_tls_get_addr ();
6630 tmp1
= gen_reg_rtx (Pmode
);
6631 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
6632 1, const0_rtx
, Pmode
);
6634 r3
= gen_rtx_REG (Pmode
, 3);
6635 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6636 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
6637 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6638 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
6639 else if (DEFAULT_ABI
== ABI_V4
)
6640 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
6643 call_insn
= last_call_insn ();
6644 PATTERN (call_insn
) = insn
;
6645 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6646 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6647 pic_offset_table_rtx
);
6649 if (rs6000_tls_size
== 16)
6652 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
6654 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
6656 else if (rs6000_tls_size
== 32)
6658 tmp2
= gen_reg_rtx (Pmode
);
6660 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
6662 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
6665 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
6667 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
6671 tmp2
= gen_reg_rtx (Pmode
);
6673 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
6675 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
6677 insn
= gen_rtx_SET (Pmode
, dest
,
6678 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
6684 /* IE, or 64-bit offset LE. */
6685 tmp2
= gen_reg_rtx (Pmode
);
6687 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
6689 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
6692 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
6694 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
6702 /* Return 1 if X contains a thread-local symbol. */
6705 rs6000_tls_referenced_p (rtx x
)
6707 if (! TARGET_HAVE_TLS
)
6710 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
6713 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6716 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
6718 if (GET_CODE (x
) == HIGH
6719 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6722 /* A TLS symbol in the TOC cannot contain a sum. */
6723 if (GET_CODE (x
) == CONST
6724 && GET_CODE (XEXP (x
, 0)) == PLUS
6725 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
6726 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
6729 /* Do not place an ELF TLS symbol in the constant pool. */
6730 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
6733 /* Return 1 if *X is a thread-local symbol. This is the same as
6734 rs6000_tls_symbol_ref except for the type of the unused argument. */
6737 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6739 return RS6000_SYMBOL_REF_TLS_P (*x
);
6742 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
6743 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
6744 can be addressed relative to the toc pointer. */
6747 use_toc_relative_ref (rtx sym
)
6749 return ((constant_pool_expr_p (sym
)
6750 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
6751 get_pool_mode (sym
)))
6752 || (TARGET_CMODEL
== CMODEL_MEDIUM
6753 && SYMBOL_REF_LOCAL_P (sym
)));
6756 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6757 replace the input X, or the original X if no replacement is called for.
6758 The output parameter *WIN is 1 if the calling macro should goto WIN,
6761 For RS/6000, we wish to handle large displacements off a base
6762 register by splitting the addend across an addiu/addis and the mem insn.
6763 This cuts number of extra insns needed from 3 to 1.
6765 On Darwin, we use this to generate code for floating point constants.
6766 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6767 The Darwin code is inside #if TARGET_MACHO because only then are the
6768 machopic_* functions defined. */
6770 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6771 int opnum
, int type
,
6772 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
6774 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6776 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6777 DFmode/DImode MEM. */
6780 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
6781 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
6782 reg_offset_p
= false;
6784 /* We must recognize output that we have already generated ourselves. */
6785 if (GET_CODE (x
) == PLUS
6786 && GET_CODE (XEXP (x
, 0)) == PLUS
6787 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6788 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6789 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6791 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6792 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6793 opnum
, (enum reload_type
) type
);
6798 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6799 if (GET_CODE (x
) == LO_SUM
6800 && GET_CODE (XEXP (x
, 0)) == HIGH
)
6802 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6803 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6804 opnum
, (enum reload_type
) type
);
6810 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
6811 && GET_CODE (x
) == LO_SUM
6812 && GET_CODE (XEXP (x
, 0)) == PLUS
6813 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
6814 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
6815 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
6816 && machopic_operand_p (XEXP (x
, 1)))
6818 /* Result of previous invocation of this function on Darwin
6819 floating point constant. */
6820 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6821 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6822 opnum
, (enum reload_type
) type
);
6828 if (TARGET_CMODEL
!= CMODEL_SMALL
6830 && small_toc_ref (x
, VOIDmode
))
6832 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
6833 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
6834 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6835 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6836 opnum
, (enum reload_type
) type
);
6841 if (GET_CODE (x
) == PLUS
6842 && GET_CODE (XEXP (x
, 0)) == REG
6843 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
6844 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
6845 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6847 && !SPE_VECTOR_MODE (mode
)
6848 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
6849 || mode
== DDmode
|| mode
== TDmode
6851 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
6853 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
6854 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
6856 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6858 /* Check for 32-bit overflow. */
6859 if (high
+ low
!= val
)
6865 /* Reload the high part into a base reg; leave the low part
6866 in the mem directly. */
6868 x
= gen_rtx_PLUS (GET_MODE (x
),
6869 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
6873 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6874 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6875 opnum
, (enum reload_type
) type
);
6880 if (GET_CODE (x
) == SYMBOL_REF
6882 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
6883 && !SPE_VECTOR_MODE (mode
)
6885 && DEFAULT_ABI
== ABI_DARWIN
6886 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
6887 && machopic_symbol_defined_p (x
)
6889 && DEFAULT_ABI
== ABI_V4
6892 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6893 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6895 ??? Assume floating point reg based on mode? This assumption is
6896 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
6897 where reload ends up doing a DFmode load of a constant from
6898 mem using two gprs. Unfortunately, at this point reload
6899 hasn't yet selected regs so poking around in reload data
6900 won't help and even if we could figure out the regs reliably,
6901 we'd still want to allow this transformation when the mem is
6902 naturally aligned. Since we say the address is good here, we
6903 can't disable offsets from LO_SUMs in mem_operand_gpr.
6904 FIXME: Allow offset from lo_sum for other modes too, when
6905 mem is sufficiently aligned. */
6908 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
6910 && (mode
!= DImode
|| TARGET_POWERPC64
)
6911 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
6912 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
6917 rtx offset
= machopic_gen_offset (x
);
6918 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6919 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
6920 gen_rtx_HIGH (Pmode
, offset
)), offset
);
6924 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6925 gen_rtx_HIGH (Pmode
, x
), x
);
6927 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6928 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6929 opnum
, (enum reload_type
) type
);
6934 /* Reload an offset address wrapped by an AND that represents the
6935 masking of the lower bits. Strip the outer AND and let reload
6936 convert the offset address into an indirect address. For VSX,
6937 force reload to create the address with an AND in a separate
6938 register, because we can't guarantee an altivec register will
6940 if (VECTOR_MEM_ALTIVEC_P (mode
)
6941 && GET_CODE (x
) == AND
6942 && GET_CODE (XEXP (x
, 0)) == PLUS
6943 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6944 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6945 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6946 && INTVAL (XEXP (x
, 1)) == -16)
6955 && GET_CODE (x
) == SYMBOL_REF
6956 && use_toc_relative_ref (x
))
6958 x
= create_TOC_reference (x
, NULL_RTX
);
6959 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6960 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6961 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6962 opnum
, (enum reload_type
) type
);
6970 /* Debug version of rs6000_legitimize_reload_address. */
6972 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6973 int opnum
, int type
,
6974 int ind_levels
, int *win
)
6976 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
6979 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6980 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6981 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
6985 fprintf (stderr
, "Same address returned\n");
6987 fprintf (stderr
, "NULL returned\n");
6990 fprintf (stderr
, "New address:\n");
6997 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6998 that is a valid memory address for an instruction.
6999 The MODE argument is the machine mode for the MEM expression
7000 that wants to use this address.
7002 On the RS/6000, there are four valid address: a SYMBOL_REF that
7003 refers to a constant pool entry of an address (or the sum of it
7004 plus a constant), a short (16-bit signed) constant plus a register,
7005 the sum of two registers, or a register indirect, possibly with an
7006 auto-increment. For DFmode, DDmode and DImode with a constant plus
7007 register, we must ensure that both words are addressable or PowerPC64
7008 with offset word aligned.
7010 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7011 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7012 because adjacent memory cells are accessed by adding word-sized offsets
7013 during assembly output. */
7015 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7017 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7019 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7020 if (VECTOR_MEM_ALTIVEC_P (mode
)
7021 && GET_CODE (x
) == AND
7022 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7023 && INTVAL (XEXP (x
, 1)) == -16)
7026 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7028 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7030 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7031 && !ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7032 && !SPE_VECTOR_MODE (mode
)
7037 /* Restrict addressing for DI because of our SUBREG hackery. */
7038 && !(TARGET_E500_DOUBLE
7039 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
7041 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7043 if (virtual_stack_registers_memory_p (x
))
7045 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7048 && legitimate_constant_pool_address_p (x
, mode
, reg_ok_strict
))
7050 /* For TImode, if we have load/store quad, only allow register indirect
7051 addresses. This will allow the values to go in either GPRs or VSX
7052 registers without reloading. The vector types would tend to go into VSX
7053 registers, so we allow REG+REG, while TImode seems somewhat split, in that
7054 some uses are GPR based, and some VSX based. */
7055 if (mode
== TImode
&& TARGET_QUAD_MEMORY
)
7057 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7060 && GET_CODE (x
) == PLUS
7061 && GET_CODE (XEXP (x
, 0)) == REG
7062 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7063 || XEXP (x
, 0) == arg_pointer_rtx
)
7064 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7066 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7070 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7072 || (mode
!= DFmode
&& mode
!= DDmode
)
7073 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7074 && (TARGET_POWERPC64
|| mode
!= DImode
)
7075 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7077 && !avoiding_indexed_address_p (mode
)
7078 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7080 if (GET_CODE (x
) == PRE_MODIFY
7085 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7087 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
7088 && (TARGET_POWERPC64
|| mode
!= DImode
)
7089 && !ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7090 && !SPE_VECTOR_MODE (mode
)
7091 /* Restrict addressing for DI because of our SUBREG hackery. */
7092 && !(TARGET_E500_DOUBLE
7093 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
7095 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7096 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7097 reg_ok_strict
, false)
7098 || (!avoiding_indexed_address_p (mode
)
7099 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7100 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7102 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7107 /* Debug version of rs6000_legitimate_address_p. */
7109 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7112 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7114 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7115 "strict = %d, code = %s\n",
7116 ret
? "true" : "false",
7117 GET_MODE_NAME (mode
),
7119 GET_RTX_NAME (GET_CODE (x
)));
7125 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7128 rs6000_mode_dependent_address_p (const_rtx addr
,
7129 addr_space_t as ATTRIBUTE_UNUSED
)
7131 return rs6000_mode_dependent_address_ptr (addr
);
7134 /* Go to LABEL if ADDR (a legitimate address expression)
7135 has an effect that depends on the machine mode it is used for.
7137 On the RS/6000 this is true of all integral offsets (since AltiVec
7138 and VSX modes don't allow them) or is a pre-increment or decrement.
7140 ??? Except that due to conceptual problems in offsettable_address_p
7141 we can't really report the problems of integral offsets. So leave
7142 this assuming that the adjustable offset must be valid for the
7143 sub-words of a TFmode operand, which is what we had before. */
7146 rs6000_mode_dependent_address (const_rtx addr
)
7148 switch (GET_CODE (addr
))
7151 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7152 is considered a legitimate address before reload, so there
7153 are no offset restrictions in that case. Note that this
7154 condition is safe in strict mode because any address involving
7155 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7156 been rejected as illegitimate. */
7157 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7158 && XEXP (addr
, 0) != arg_pointer_rtx
7159 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7161 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7162 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7167 /* Anything in the constant pool is sufficiently aligned that
7168 all bytes have the same high part address. */
7169 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7171 /* Auto-increment cases are now treated generically in recog.c. */
7173 return TARGET_UPDATE
;
7175 /* AND is only allowed in Altivec loads. */
7186 /* Debug version of rs6000_mode_dependent_address. */
7188 rs6000_debug_mode_dependent_address (const_rtx addr
)
7190 bool ret
= rs6000_mode_dependent_address (addr
);
7192 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7193 ret
? "true" : "false");
7199 /* Implement FIND_BASE_TERM. */
7202 rs6000_find_base_term (rtx op
)
7207 if (GET_CODE (base
) == CONST
)
7208 base
= XEXP (base
, 0);
7209 if (GET_CODE (base
) == PLUS
)
7210 base
= XEXP (base
, 0);
7211 if (GET_CODE (base
) == UNSPEC
)
7212 switch (XINT (base
, 1))
7215 case UNSPEC_MACHOPIC_OFFSET
:
7216 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7217 for aliasing purposes. */
7218 return XVECEXP (base
, 0, 0);
7224 /* More elaborate version of recog's offsettable_memref_p predicate
7225 that works around the ??? note of rs6000_mode_dependent_address.
7226 In particular it accepts
7228 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7230 in 32-bit mode, that the recog predicate rejects. */
7233 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7240 /* First mimic offsettable_memref_p. */
7241 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7244 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7245 the latter predicate knows nothing about the mode of the memory
7246 reference and, therefore, assumes that it is the largest supported
7247 mode (TFmode). As a consequence, legitimate offsettable memory
7248 references are rejected. rs6000_legitimate_offset_address_p contains
7249 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7250 at least with a little bit of help here given that we know the
7251 actual registers used. */
7252 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7253 || GET_MODE_SIZE (reg_mode
) == 4);
7254 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7258 /* Change register usage conditional on target flags. */
7260 rs6000_conditional_register_usage (void)
7264 if (TARGET_DEBUG_TARGET
)
7265 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7267 /* Set MQ register fixed (already call_used) so that it will not be
7271 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7273 fixed_regs
[13] = call_used_regs
[13]
7274 = call_really_used_regs
[13] = 1;
7276 /* Conditionally disable FPRs. */
7277 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7278 for (i
= 32; i
< 64; i
++)
7279 fixed_regs
[i
] = call_used_regs
[i
]
7280 = call_really_used_regs
[i
] = 1;
7282 /* The TOC register is not killed across calls in a way that is
7283 visible to the compiler. */
7284 if (DEFAULT_ABI
== ABI_AIX
)
7285 call_really_used_regs
[2] = 0;
7287 if (DEFAULT_ABI
== ABI_V4
7288 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7290 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7292 if (DEFAULT_ABI
== ABI_V4
7293 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7295 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7296 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7297 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7299 if (DEFAULT_ABI
== ABI_DARWIN
7300 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7301 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7302 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7303 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7305 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7306 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7307 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7311 global_regs
[SPEFSCR_REGNO
] = 1;
7312 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7313 registers in prologues and epilogues. We no longer use r14
7314 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7315 pool for link-compatibility with older versions of GCC. Once
7316 "old" code has died out, we can return r14 to the allocation
7319 = call_used_regs
[14]
7320 = call_really_used_regs
[14] = 1;
7323 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7325 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7326 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7327 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7330 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7331 global_regs
[VSCR_REGNO
] = 1;
7333 if (TARGET_ALTIVEC_ABI
)
7335 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7336 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7338 /* AIX reserves VR20:31 in non-extended ABI mode. */
7340 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7341 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7345 /* Try to output insns to set TARGET equal to the constant C if it can
7346 be done in less than N insns. Do all computations in MODE.
7347 Returns the place where the output has been placed if it can be
7348 done and the insns have been emitted. If it would take more than N
7349 insns, zero is returned and no insns and emitted. */
7352 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7353 rtx source
, int n ATTRIBUTE_UNUSED
)
7355 rtx result
, insn
, set
;
7356 HOST_WIDE_INT c0
, c1
;
7363 dest
= gen_reg_rtx (mode
);
7364 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7368 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7370 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7371 GEN_INT (INTVAL (source
)
7372 & (~ (HOST_WIDE_INT
) 0xffff))));
7373 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7374 gen_rtx_IOR (SImode
, copy_rtx (result
),
7375 GEN_INT (INTVAL (source
) & 0xffff))));
7380 switch (GET_CODE (source
))
7383 c0
= INTVAL (source
);
7391 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7398 insn
= get_last_insn ();
7399 set
= single_set (insn
);
7400 if (! CONSTANT_P (SET_SRC (set
)))
7401 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7406 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7407 fall back to a straight forward decomposition. We do this to avoid
7408 exponential run times encountered when looking for longer sequences
7409 with rs6000_emit_set_const. */
7411 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7413 if (!TARGET_POWERPC64
)
7415 rtx operand1
, operand2
;
7417 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7419 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7421 emit_move_insn (operand1
, GEN_INT (c1
));
7422 emit_move_insn (operand2
, GEN_INT (c2
));
7426 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7429 ud2
= (c1
& 0xffff0000) >> 16;
7432 ud4
= (c2
& 0xffff0000) >> 16;
7434 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7435 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7436 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7438 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7439 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7441 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7444 emit_move_insn (copy_rtx (dest
),
7445 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7448 else if (ud3
== 0 && ud4
== 0)
7450 gcc_assert (ud2
& 0x8000);
7451 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7454 emit_move_insn (copy_rtx (dest
),
7455 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7457 emit_move_insn (copy_rtx (dest
),
7458 gen_rtx_ZERO_EXTEND (DImode
,
7459 gen_lowpart (SImode
,
7462 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7463 || (ud4
== 0 && ! (ud3
& 0x8000)))
7465 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7468 emit_move_insn (copy_rtx (dest
),
7469 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7471 emit_move_insn (copy_rtx (dest
),
7472 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7475 emit_move_insn (copy_rtx (dest
),
7476 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7481 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7484 emit_move_insn (copy_rtx (dest
),
7485 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7488 emit_move_insn (copy_rtx (dest
),
7489 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7492 emit_move_insn (copy_rtx (dest
),
7493 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7494 GEN_INT (ud2
<< 16)));
7496 emit_move_insn (copy_rtx (dest
),
7497 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7504 /* Helper for the following. Get rid of [r+r] memory refs
7505 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
7508 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7510 if (reload_in_progress
)
7513 if (GET_CODE (operands
[0]) == MEM
7514 && GET_CODE (XEXP (operands
[0], 0)) != REG
7515 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7516 GET_MODE (operands
[0]), false))
7518 = replace_equiv_address (operands
[0],
7519 copy_addr_to_reg (XEXP (operands
[0], 0)));
7521 if (GET_CODE (operands
[1]) == MEM
7522 && GET_CODE (XEXP (operands
[1], 0)) != REG
7523 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7524 GET_MODE (operands
[1]), false))
7526 = replace_equiv_address (operands
[1],
7527 copy_addr_to_reg (XEXP (operands
[1], 0)));
7530 /* Emit a move from SOURCE to DEST in mode MODE. */
7532 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
7536 operands
[1] = source
;
7538 if (TARGET_DEBUG_ADDR
)
7541 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
7542 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
7543 GET_MODE_NAME (mode
),
7546 can_create_pseudo_p ());
7548 fprintf (stderr
, "source:\n");
7552 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
7553 if (GET_CODE (operands
[1]) == CONST_DOUBLE
7554 && ! FLOAT_MODE_P (mode
)
7555 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
7557 /* FIXME. This should never happen. */
7558 /* Since it seems that it does, do the safe thing and convert
7560 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
7562 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
7563 || FLOAT_MODE_P (mode
)
7564 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
7565 || CONST_DOUBLE_LOW (operands
[1]) < 0)
7566 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
7567 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
7569 /* Check if GCC is setting up a block move that will end up using FP
7570 registers as temporaries. We must make sure this is acceptable. */
7571 if (GET_CODE (operands
[0]) == MEM
7572 && GET_CODE (operands
[1]) == MEM
7574 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
7575 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
7576 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
7577 ? 32 : MEM_ALIGN (operands
[0])))
7578 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
7580 : MEM_ALIGN (operands
[1]))))
7581 && ! MEM_VOLATILE_P (operands
[0])
7582 && ! MEM_VOLATILE_P (operands
[1]))
7584 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
7585 adjust_address (operands
[1], SImode
, 0));
7586 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
7587 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
7591 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
7592 && !gpc_reg_operand (operands
[1], mode
))
7593 operands
[1] = force_reg (mode
, operands
[1]);
7595 /* Recognize the case where operand[1] is a reference to thread-local
7596 data and load its address to a register. */
7597 if (rs6000_tls_referenced_p (operands
[1]))
7599 enum tls_model model
;
7600 rtx tmp
= operands
[1];
7603 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
7605 addend
= XEXP (XEXP (tmp
, 0), 1);
7606 tmp
= XEXP (XEXP (tmp
, 0), 0);
7609 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
7610 model
= SYMBOL_REF_TLS_MODEL (tmp
);
7611 gcc_assert (model
!= 0);
7613 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
7616 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
7617 tmp
= force_operand (tmp
, operands
[0]);
7622 /* Handle the case where reload calls us with an invalid address. */
7623 if (reload_in_progress
&& mode
== Pmode
7624 && (! general_operand (operands
[1], mode
)
7625 || ! nonimmediate_operand (operands
[0], mode
)))
7628 /* 128-bit constant floating-point values on Darwin should really be
7629 loaded as two parts. */
7630 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
7631 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
7633 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
7634 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
7636 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
7637 GET_MODE_SIZE (DFmode
)),
7638 simplify_gen_subreg (DFmode
, operands
[1], mode
,
7639 GET_MODE_SIZE (DFmode
)),
7644 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
7645 cfun
->machine
->sdmode_stack_slot
=
7646 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
7648 if (reload_in_progress
7650 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
7651 && MEM_P (operands
[0])
7652 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
7653 && REG_P (operands
[1]))
7655 if (FP_REGNO_P (REGNO (operands
[1])))
7657 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
7658 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7659 emit_insn (gen_movsd_store (mem
, operands
[1]));
7661 else if (INT_REGNO_P (REGNO (operands
[1])))
7663 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
7664 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7665 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
7671 if (reload_in_progress
7673 && REG_P (operands
[0])
7674 && MEM_P (operands
[1])
7675 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
7676 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
7678 if (FP_REGNO_P (REGNO (operands
[0])))
7680 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
7681 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7682 emit_insn (gen_movsd_load (operands
[0], mem
));
7684 else if (INT_REGNO_P (REGNO (operands
[0])))
7686 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
7687 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7688 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
7695 /* FIXME: In the long term, this switch statement should go away
7696 and be replaced by a sequence of tests based on things like
7702 if (CONSTANT_P (operands
[1])
7703 && GET_CODE (operands
[1]) != CONST_INT
)
7704 operands
[1] = force_const_mem (mode
, operands
[1]);
7709 rs6000_eliminate_indexed_memrefs (operands
);
7716 if (CONSTANT_P (operands
[1])
7717 && ! easy_fp_constant (operands
[1], mode
))
7718 operands
[1] = force_const_mem (mode
, operands
[1]);
7731 if (CONSTANT_P (operands
[1])
7732 && !easy_vector_constant (operands
[1], mode
))
7733 operands
[1] = force_const_mem (mode
, operands
[1]);
7738 /* Use default pattern for address of ELF small data */
7741 && DEFAULT_ABI
== ABI_V4
7742 && (GET_CODE (operands
[1]) == SYMBOL_REF
7743 || GET_CODE (operands
[1]) == CONST
)
7744 && small_data_operand (operands
[1], mode
))
7746 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7750 if (DEFAULT_ABI
== ABI_V4
7751 && mode
== Pmode
&& mode
== SImode
7752 && flag_pic
== 1 && got_operand (operands
[1], mode
))
7754 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
7758 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
7762 && CONSTANT_P (operands
[1])
7763 && GET_CODE (operands
[1]) != HIGH
7764 && GET_CODE (operands
[1]) != CONST_INT
)
7766 rtx target
= (!can_create_pseudo_p ()
7768 : gen_reg_rtx (mode
));
7770 /* If this is a function address on -mcall-aixdesc,
7771 convert it to the address of the descriptor. */
7772 if (DEFAULT_ABI
== ABI_AIX
7773 && GET_CODE (operands
[1]) == SYMBOL_REF
7774 && XSTR (operands
[1], 0)[0] == '.')
7776 const char *name
= XSTR (operands
[1], 0);
7778 while (*name
== '.')
7780 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
7781 CONSTANT_POOL_ADDRESS_P (new_ref
)
7782 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
7783 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
7784 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
7785 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
7786 operands
[1] = new_ref
;
7789 if (DEFAULT_ABI
== ABI_DARWIN
)
7792 if (MACHO_DYNAMIC_NO_PIC_P
)
7794 /* Take care of any required data indirection. */
7795 operands
[1] = rs6000_machopic_legitimize_pic_address (
7796 operands
[1], mode
, operands
[0]);
7797 if (operands
[0] != operands
[1])
7798 emit_insn (gen_rtx_SET (VOIDmode
,
7799 operands
[0], operands
[1]));
7803 emit_insn (gen_macho_high (target
, operands
[1]));
7804 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
7808 emit_insn (gen_elf_high (target
, operands
[1]));
7809 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
7813 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7814 and we have put it in the TOC, we just need to make a TOC-relative
7817 && GET_CODE (operands
[1]) == SYMBOL_REF
7818 && use_toc_relative_ref (operands
[1]))
7819 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
7820 else if (mode
== Pmode
7821 && CONSTANT_P (operands
[1])
7822 && GET_CODE (operands
[1]) != HIGH
7823 && ((GET_CODE (operands
[1]) != CONST_INT
7824 && ! easy_fp_constant (operands
[1], mode
))
7825 || (GET_CODE (operands
[1]) == CONST_INT
7826 && (num_insns_constant (operands
[1], mode
)
7827 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
7828 || (GET_CODE (operands
[0]) == REG
7829 && FP_REGNO_P (REGNO (operands
[0]))))
7830 && !toc_relative_expr_p (operands
[1], false)
7831 && (TARGET_CMODEL
== CMODEL_SMALL
7832 || can_create_pseudo_p ()
7833 || (REG_P (operands
[0])
7834 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
7838 /* Darwin uses a special PIC legitimizer. */
7839 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
7842 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
7844 if (operands
[0] != operands
[1])
7845 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7850 /* If we are to limit the number of things we put in the TOC and
7851 this is a symbol plus a constant we can add in one insn,
7852 just put the symbol in the TOC and add the constant. Don't do
7853 this if reload is in progress. */
7854 if (GET_CODE (operands
[1]) == CONST
7855 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
7856 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
7857 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
7858 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
7859 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
7860 && ! side_effects_p (operands
[0]))
7863 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
7864 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
7866 sym
= force_reg (mode
, sym
);
7867 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
7871 operands
[1] = force_const_mem (mode
, operands
[1]);
7874 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
7875 && constant_pool_expr_p (XEXP (operands
[1], 0))
7876 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7877 get_pool_constant (XEXP (operands
[1], 0)),
7878 get_pool_mode (XEXP (operands
[1], 0))))
7880 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
7882 operands
[1] = gen_const_mem (mode
, tocref
);
7883 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
7889 if (!VECTOR_MEM_VSX_P (TImode
))
7890 rs6000_eliminate_indexed_memrefs (operands
);
7894 rs6000_eliminate_indexed_memrefs (operands
);
7898 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
7901 /* Above, we may have called force_const_mem which may have returned
7902 an invalid address. If we can, fix this up; otherwise, reload will
7903 have to deal with it. */
7904 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
7905 operands
[1] = validize_mem (operands
[1]);
7908 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7911 /* Return true if a structure, union or array containing FIELD should be
7912 accessed using `BLKMODE'.
7914 For the SPE, simd types are V2SI, and gcc can be tempted to put the
7915 entire thing in a DI and use subregs to access the internals.
7916 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
7917 back-end. Because a single GPR can hold a V2SI, but not a DI, the
7918 best thing to do is set structs to BLKmode and avoid Severe Tire
7921 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
7922 fit into 1, whereas DI still needs two. */
7925 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
7927 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
7928 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
7931 /* Nonzero if we can use a floating-point register to pass this arg. */
7932 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7933 (SCALAR_FLOAT_MODE_P (MODE) \
7934 && (CUM)->fregno <= FP_ARG_MAX_REG \
7935 && TARGET_HARD_FLOAT && TARGET_FPRS)
7937 /* Nonzero if we can use an AltiVec register to pass this arg. */
7938 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7939 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7940 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7941 && TARGET_ALTIVEC_ABI \
7944 /* Return a nonzero value to say to return the function value in
7945 memory, just as large structures are always returned. TYPE will be
7946 the data type of the value, and FNTYPE will be the type of the
7947 function doing the returning, or @code{NULL} for libcalls.
7949 The AIX ABI for the RS/6000 specifies that all structures are
7950 returned in memory. The Darwin ABI does the same.
7952 For the Darwin 64 Bit ABI, a function result can be returned in
7953 registers or in memory, depending on the size of the return data
7954 type. If it is returned in registers, the value occupies the same
7955 registers as it would if it were the first and only function
7956 argument. Otherwise, the function places its result in memory at
7957 the location pointed to by GPR3.
7959 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7960 but a draft put them in memory, and GCC used to implement the draft
7961 instead of the final standard. Therefore, aix_struct_return
7962 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7963 compatibility can change DRAFT_V4_STRUCT_RET to override the
7964 default, and -m switches get the final word. See
7965 rs6000_option_override_internal for more details.
7967 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7968 long double support is enabled. These values are returned in memory.
7970 int_size_in_bytes returns -1 for variable size objects, which go in
7971 memory always. The cast to unsigned makes -1 > 8. */
7974 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7976 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7978 && rs6000_darwin64_abi
7979 && TREE_CODE (type
) == RECORD_TYPE
7980 && int_size_in_bytes (type
) > 0)
7982 CUMULATIVE_ARGS valcum
;
7986 valcum
.fregno
= FP_ARG_MIN_REG
;
7987 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
7988 /* Do a trial code generation as if this were going to be passed
7989 as an argument; if any part goes in memory, we return NULL. */
7990 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
7993 /* Otherwise fall through to more conventional ABI rules. */
7996 if (AGGREGATE_TYPE_P (type
)
7997 && (aix_struct_return
7998 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8001 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8002 modes only exist for GCC vector types if -maltivec. */
8003 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8004 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8007 /* Return synthetic vectors in memory. */
8008 if (TREE_CODE (type
) == VECTOR_TYPE
8009 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8011 static bool warned_for_return_big_vectors
= false;
8012 if (!warned_for_return_big_vectors
)
8014 warning (0, "GCC vector returned by reference: "
8015 "non-standard ABI extension with no compatibility guarantee");
8016 warned_for_return_big_vectors
= true;
8021 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8027 #ifdef HAVE_AS_GNU_ATTRIBUTE
8028 /* Return TRUE if a call to function FNDECL may be one that
8029 potentially affects the function calling ABI of the object file. */
8032 call_ABI_of_interest (tree fndecl
)
8034 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8036 struct cgraph_node
*c_node
;
8038 /* Libcalls are always interesting. */
8039 if (fndecl
== NULL_TREE
)
8042 /* Any call to an external function is interesting. */
8043 if (DECL_EXTERNAL (fndecl
))
8046 /* Interesting functions that we are emitting in this object file. */
8047 c_node
= cgraph_get_node (fndecl
);
8048 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8049 return !cgraph_only_called_directly_p (c_node
);
8055 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8056 for a call to a function whose data type is FNTYPE.
8057 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8059 For incoming args we set the number of arguments in the prototype large
8060 so we never return a PARALLEL. */
8063 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8064 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8065 int libcall
, int n_named_args
,
8066 tree fndecl ATTRIBUTE_UNUSED
,
8067 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8069 static CUMULATIVE_ARGS zero_cumulative
;
8071 *cum
= zero_cumulative
;
8073 cum
->fregno
= FP_ARG_MIN_REG
;
8074 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8075 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8076 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8077 ? CALL_LIBCALL
: CALL_NORMAL
);
8078 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8079 cum
->stdarg
= stdarg_p (fntype
);
8081 cum
->nargs_prototype
= 0;
8082 if (incoming
|| cum
->prototype
)
8083 cum
->nargs_prototype
= n_named_args
;
8085 /* Check for a longcall attribute. */
8086 if ((!fntype
&& rs6000_default_long_calls
)
8088 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
8089 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
8090 cum
->call_cookie
|= CALL_LONG
;
8092 if (TARGET_DEBUG_ARG
)
8094 fprintf (stderr
, "\ninit_cumulative_args:");
8097 tree ret_type
= TREE_TYPE (fntype
);
8098 fprintf (stderr
, " ret code = %s,",
8099 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
8102 if (cum
->call_cookie
& CALL_LONG
)
8103 fprintf (stderr
, " longcall,");
8105 fprintf (stderr
, " proto = %d, nargs = %d\n",
8106 cum
->prototype
, cum
->nargs_prototype
);
8109 #ifdef HAVE_AS_GNU_ATTRIBUTE
8110 if (DEFAULT_ABI
== ABI_V4
)
8112 cum
->escapes
= call_ABI_of_interest (fndecl
);
8119 return_type
= TREE_TYPE (fntype
);
8120 return_mode
= TYPE_MODE (return_type
);
8123 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
8125 if (return_type
!= NULL
)
8127 if (TREE_CODE (return_type
) == RECORD_TYPE
8128 && TYPE_TRANSPARENT_AGGR (return_type
))
8130 return_type
= TREE_TYPE (first_field (return_type
));
8131 return_mode
= TYPE_MODE (return_type
);
8133 if (AGGREGATE_TYPE_P (return_type
)
8134 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
8136 rs6000_returns_struct
= true;
8138 if (SCALAR_FLOAT_MODE_P (return_mode
))
8139 rs6000_passes_float
= true;
8140 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
8141 || SPE_VECTOR_MODE (return_mode
))
8142 rs6000_passes_vector
= true;
8149 && TARGET_ALTIVEC_ABI
8150 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
8152 error ("cannot return value in vector register because"
8153 " altivec instructions are disabled, use -maltivec"
8158 /* Return true if TYPE must be passed on the stack and not in registers. */
8161 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
8163 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
8164 return must_pass_in_stack_var_size (mode
, type
);
8166 return must_pass_in_stack_var_size_or_pad (mode
, type
);
8169 /* If defined, a C expression which determines whether, and in which
8170 direction, to pad out an argument with extra space. The value
8171 should be of type `enum direction': either `upward' to pad above
8172 the argument, `downward' to pad below, or `none' to inhibit
8175 For the AIX ABI structs are always stored left shifted in their
8179 function_arg_padding (enum machine_mode mode
, const_tree type
)
8181 #ifndef AGGREGATE_PADDING_FIXED
8182 #define AGGREGATE_PADDING_FIXED 0
8184 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
8185 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
8188 if (!AGGREGATE_PADDING_FIXED
)
8190 /* GCC used to pass structures of the same size as integer types as
8191 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
8192 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
8193 passed padded downward, except that -mstrict-align further
8194 muddied the water in that multi-component structures of 2 and 4
8195 bytes in size were passed padded upward.
8197 The following arranges for best compatibility with previous
8198 versions of gcc, but removes the -mstrict-align dependency. */
8199 if (BYTES_BIG_ENDIAN
)
8201 HOST_WIDE_INT size
= 0;
8203 if (mode
== BLKmode
)
8205 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
8206 size
= int_size_in_bytes (type
);
8209 size
= GET_MODE_SIZE (mode
);
8211 if (size
== 1 || size
== 2 || size
== 4)
8217 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
8219 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
8223 /* Fall back to the default. */
8224 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8227 /* If defined, a C expression that gives the alignment boundary, in bits,
8228 of an argument with the specified mode and type. If it is not defined,
8229 PARM_BOUNDARY is used for all arguments.
8231 V.4 wants long longs and doubles to be double word aligned. Just
8232 testing the mode size is a boneheaded way to do this as it means
8233 that other types such as complex int are also double word aligned.
8234 However, we're stuck with this because changing the ABI might break
8235 existing library interfaces.
8237 Doubleword align SPE vectors.
8238 Quadword align Altivec/VSX vectors.
8239 Quadword align large synthetic vector types. */
8242 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
8244 if (DEFAULT_ABI
== ABI_V4
8245 && (GET_MODE_SIZE (mode
) == 8
8246 || (TARGET_HARD_FLOAT
8248 && (mode
== TFmode
|| mode
== TDmode
))))
8250 else if (SPE_VECTOR_MODE (mode
)
8251 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8252 && int_size_in_bytes (type
) >= 8
8253 && int_size_in_bytes (type
) < 16))
8255 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8256 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8257 && int_size_in_bytes (type
) >= 16))
8259 else if (TARGET_MACHO
8260 && rs6000_darwin64_abi
8262 && type
&& TYPE_ALIGN (type
) > 64)
8265 return PARM_BOUNDARY
;
8268 /* For a function parm of MODE and TYPE, return the starting word in
8269 the parameter area. NWORDS of the parameter area are already used. */
8272 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
8273 unsigned int nwords
)
8276 unsigned int parm_offset
;
8278 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
8279 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
8280 return nwords
+ (-(parm_offset
+ nwords
) & align
);
8283 /* Compute the size (in words) of a function argument. */
8285 static unsigned long
8286 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
8290 if (mode
!= BLKmode
)
8291 size
= GET_MODE_SIZE (mode
);
8293 size
= int_size_in_bytes (type
);
8296 return (size
+ 3) >> 2;
8298 return (size
+ 7) >> 3;
8301 /* Use this to flush pending int fields. */
8304 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
8305 HOST_WIDE_INT bitpos
, int final
)
8307 unsigned int startbit
, endbit
;
8308 int intregs
, intoffset
;
8309 enum machine_mode mode
;
8311 /* Handle the situations where a float is taking up the first half
8312 of the GPR, and the other half is empty (typically due to
8313 alignment restrictions). We can detect this by a 8-byte-aligned
8314 int field, or by seeing that this is the final flush for this
8315 argument. Count the word and continue on. */
8316 if (cum
->floats_in_gpr
== 1
8317 && (cum
->intoffset
% 64 == 0
8318 || (cum
->intoffset
== -1 && final
)))
8321 cum
->floats_in_gpr
= 0;
8324 if (cum
->intoffset
== -1)
8327 intoffset
= cum
->intoffset
;
8328 cum
->intoffset
= -1;
8329 cum
->floats_in_gpr
= 0;
8331 if (intoffset
% BITS_PER_WORD
!= 0)
8333 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8335 if (mode
== BLKmode
)
8337 /* We couldn't find an appropriate mode, which happens,
8338 e.g., in packed structs when there are 3 bytes to load.
8339 Back intoffset back to the beginning of the word in this
8341 intoffset
= intoffset
& -BITS_PER_WORD
;
8345 startbit
= intoffset
& -BITS_PER_WORD
;
8346 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8347 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8348 cum
->words
+= intregs
;
8349 /* words should be unsigned. */
8350 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
8352 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
8357 /* The darwin64 ABI calls for us to recurse down through structs,
8358 looking for elements passed in registers. Unfortunately, we have
8359 to track int register count here also because of misalignments
8360 in powerpc alignment mode. */
8363 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
8365 HOST_WIDE_INT startbitpos
)
8369 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8370 if (TREE_CODE (f
) == FIELD_DECL
)
8372 HOST_WIDE_INT bitpos
= startbitpos
;
8373 tree ftype
= TREE_TYPE (f
);
8374 enum machine_mode mode
;
8375 if (ftype
== error_mark_node
)
8377 mode
= TYPE_MODE (ftype
);
8379 if (DECL_SIZE (f
) != 0
8380 && host_integerp (bit_position (f
), 1))
8381 bitpos
+= int_bit_position (f
);
8383 /* ??? FIXME: else assume zero offset. */
8385 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8386 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
8387 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8389 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8390 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
8391 cum
->fregno
+= n_fpregs
;
8392 /* Single-precision floats present a special problem for
8393 us, because they are smaller than an 8-byte GPR, and so
8394 the structure-packing rules combined with the standard
8395 varargs behavior mean that we want to pack float/float
8396 and float/int combinations into a single register's
8397 space. This is complicated by the arg advance flushing,
8398 which works on arbitrarily large groups of int-type
8402 if (cum
->floats_in_gpr
== 1)
8404 /* Two floats in a word; count the word and reset
8407 cum
->floats_in_gpr
= 0;
8409 else if (bitpos
% 64 == 0)
8411 /* A float at the beginning of an 8-byte word;
8412 count it and put off adjusting cum->words until
8413 we see if a arg advance flush is going to do it
8415 cum
->floats_in_gpr
++;
8419 /* The float is at the end of a word, preceded
8420 by integer fields, so the arg advance flush
8421 just above has already set cum->words and
8422 everything is taken care of. */
8426 cum
->words
+= n_fpregs
;
8428 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
8430 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
8434 else if (cum
->intoffset
== -1)
8435 cum
->intoffset
= bitpos
;
8439 /* Check for an item that needs to be considered specially under the darwin 64
8440 bit ABI. These are record types where the mode is BLK or the structure is
8443 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
8445 return rs6000_darwin64_abi
8446 && ((mode
== BLKmode
8447 && TREE_CODE (type
) == RECORD_TYPE
8448 && int_size_in_bytes (type
) > 0)
8449 || (type
&& TREE_CODE (type
) == RECORD_TYPE
8450 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
8453 /* Update the data in CUM to advance over an argument
8454 of mode MODE and data type TYPE.
8455 (TYPE is null for libcalls where that information may not be available.)
8457 Note that for args passed by reference, function_arg will be called
8458 with MODE and TYPE set to that of the pointer to the arg, not the arg
8462 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8463 const_tree type
, bool named
, int depth
)
8465 /* Only tick off an argument if we're not recursing. */
8467 cum
->nargs_prototype
--;
8469 #ifdef HAVE_AS_GNU_ATTRIBUTE
8470 if (DEFAULT_ABI
== ABI_V4
8473 if (SCALAR_FLOAT_MODE_P (mode
))
8474 rs6000_passes_float
= true;
8475 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
8476 rs6000_passes_vector
= true;
8477 else if (SPE_VECTOR_MODE (mode
)
8479 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
8480 rs6000_passes_vector
= true;
8484 if (TARGET_ALTIVEC_ABI
8485 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8486 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8487 && int_size_in_bytes (type
) == 16)))
8491 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
8494 if (!TARGET_ALTIVEC
)
8495 error ("cannot pass argument in vector register because"
8496 " altivec instructions are disabled, use -maltivec"
8499 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
8500 even if it is going to be passed in a vector register.
8501 Darwin does the same for variable-argument functions. */
8502 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
8503 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
8513 /* Vector parameters must be 16-byte aligned. This places
8514 them at 2 mod 4 in terms of words in 32-bit mode, since
8515 the parameter save area starts at offset 24 from the
8516 stack. In 64-bit mode, they just have to start on an
8517 even word, since the parameter save area is 16-byte
8518 aligned. Space for GPRs is reserved even if the argument
8519 will be passed in memory. */
8521 align
= (2 - cum
->words
) & 3;
8523 align
= cum
->words
& 1;
8524 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
8526 if (TARGET_DEBUG_ARG
)
8528 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
8530 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
8531 cum
->nargs_prototype
, cum
->prototype
,
8532 GET_MODE_NAME (mode
));
8536 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
8538 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
8541 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8543 int size
= int_size_in_bytes (type
);
8544 /* Variable sized types have size == -1 and are
8545 treated as if consisting entirely of ints.
8546 Pad to 16 byte boundary if needed. */
8547 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8548 && (cum
->words
% 2) != 0)
8550 /* For varargs, we can just go up by the size of the struct. */
8552 cum
->words
+= (size
+ 7) / 8;
8555 /* It is tempting to say int register count just goes up by
8556 sizeof(type)/8, but this is wrong in a case such as
8557 { int; double; int; } [powerpc alignment]. We have to
8558 grovel through the fields for these too. */
8560 cum
->floats_in_gpr
= 0;
8561 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
8562 rs6000_darwin64_record_arg_advance_flush (cum
,
8563 size
* BITS_PER_UNIT
, 1);
8565 if (TARGET_DEBUG_ARG
)
8567 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
8568 cum
->words
, TYPE_ALIGN (type
), size
);
8570 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
8571 cum
->nargs_prototype
, cum
->prototype
,
8572 GET_MODE_NAME (mode
));
8575 else if (DEFAULT_ABI
== ABI_V4
)
8577 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8578 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
8579 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
8580 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
8581 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
8583 /* _Decimal128 must use an even/odd register pair. This assumes
8584 that the register number is odd when fregno is odd. */
8585 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8588 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
8589 <= FP_ARG_V4_MAX_REG
)
8590 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8593 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
8594 if (mode
== DFmode
|| mode
== TFmode
8595 || mode
== DDmode
|| mode
== TDmode
)
8596 cum
->words
+= cum
->words
& 1;
8597 cum
->words
+= rs6000_arg_size (mode
, type
);
8602 int n_words
= rs6000_arg_size (mode
, type
);
8603 int gregno
= cum
->sysv_gregno
;
8605 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8606 (r7,r8) or (r9,r10). As does any other 2 word item such
8607 as complex int due to a historical mistake. */
8609 gregno
+= (1 - gregno
) & 1;
8611 /* Multi-reg args are not split between registers and stack. */
8612 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8614 /* Long long and SPE vectors are aligned on the stack.
8615 So are other 2 word items such as complex int due to
8616 a historical mistake. */
8618 cum
->words
+= cum
->words
& 1;
8619 cum
->words
+= n_words
;
8622 /* Note: continuing to accumulate gregno past when we've started
8623 spilling to the stack indicates the fact that we've started
8624 spilling to the stack to expand_builtin_saveregs. */
8625 cum
->sysv_gregno
= gregno
+ n_words
;
8628 if (TARGET_DEBUG_ARG
)
8630 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8631 cum
->words
, cum
->fregno
);
8632 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
8633 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
8634 fprintf (stderr
, "mode = %4s, named = %d\n",
8635 GET_MODE_NAME (mode
), named
);
8640 int n_words
= rs6000_arg_size (mode
, type
);
8641 int start_words
= cum
->words
;
8642 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
8644 cum
->words
= align_words
+ n_words
;
8646 if (SCALAR_FLOAT_MODE_P (mode
)
8647 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8649 /* _Decimal128 must be passed in an even/odd float register pair.
8650 This assumes that the register number is odd when fregno is
8652 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8654 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8657 if (TARGET_DEBUG_ARG
)
8659 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8660 cum
->words
, cum
->fregno
);
8661 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
8662 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
8663 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
8664 named
, align_words
- start_words
, depth
);
8670 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
8671 const_tree type
, bool named
)
8673 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
8678 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
8685 r1
= gen_rtx_REG (DImode
, gregno
);
8686 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8687 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
8691 r1
= gen_rtx_REG (DImode
, gregno
);
8692 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8693 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8694 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8695 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
8698 r1
= gen_rtx_REG (DImode
, gregno
);
8699 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8700 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8701 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8702 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
8703 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
8704 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
8705 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
8706 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
8713 /* Determine where to put a SIMD argument on the SPE. */
8715 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8718 int gregno
= cum
->sysv_gregno
;
8720 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8721 are passed and returned in a pair of GPRs for ABI compatibility. */
8722 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
8723 || mode
== DCmode
|| mode
== TCmode
))
8725 int n_words
= rs6000_arg_size (mode
, type
);
8727 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8729 gregno
+= (1 - gregno
) & 1;
8731 /* Multi-reg args are not split between registers and stack. */
8732 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8735 return spe_build_register_parallel (mode
, gregno
);
8739 int n_words
= rs6000_arg_size (mode
, type
);
8741 /* SPE vectors are put in odd registers. */
8742 if (n_words
== 2 && (gregno
& 1) == 0)
8745 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
8748 enum machine_mode m
= SImode
;
8750 r1
= gen_rtx_REG (m
, gregno
);
8751 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
8752 r2
= gen_rtx_REG (m
, gregno
+ 1);
8753 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
8754 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
8761 if (gregno
<= GP_ARG_MAX_REG
)
8762 return gen_rtx_REG (mode
, gregno
);
8768 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8769 structure between cum->intoffset and bitpos to integer registers. */
8772 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
8773 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
8775 enum machine_mode mode
;
8777 unsigned int startbit
, endbit
;
8778 int this_regno
, intregs
, intoffset
;
8781 if (cum
->intoffset
== -1)
8784 intoffset
= cum
->intoffset
;
8785 cum
->intoffset
= -1;
8787 /* If this is the trailing part of a word, try to only load that
8788 much into the register. Otherwise load the whole register. Note
8789 that in the latter case we may pick up unwanted bits. It's not a
8790 problem at the moment but may wish to revisit. */
8792 if (intoffset
% BITS_PER_WORD
!= 0)
8794 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8796 if (mode
== BLKmode
)
8798 /* We couldn't find an appropriate mode, which happens,
8799 e.g., in packed structs when there are 3 bytes to load.
8800 Back intoffset back to the beginning of the word in this
8802 intoffset
= intoffset
& -BITS_PER_WORD
;
8809 startbit
= intoffset
& -BITS_PER_WORD
;
8810 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8811 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8812 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
8814 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
8817 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
8821 intoffset
/= BITS_PER_UNIT
;
8824 regno
= GP_ARG_MIN_REG
+ this_regno
;
8825 reg
= gen_rtx_REG (mode
, regno
);
8827 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
8830 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
8834 while (intregs
> 0);
8837 /* Recursive workhorse for the following. */
8840 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
8841 HOST_WIDE_INT startbitpos
, rtx rvec
[],
8846 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8847 if (TREE_CODE (f
) == FIELD_DECL
)
8849 HOST_WIDE_INT bitpos
= startbitpos
;
8850 tree ftype
= TREE_TYPE (f
);
8851 enum machine_mode mode
;
8852 if (ftype
== error_mark_node
)
8854 mode
= TYPE_MODE (ftype
);
8856 if (DECL_SIZE (f
) != 0
8857 && host_integerp (bit_position (f
), 1))
8858 bitpos
+= int_bit_position (f
);
8860 /* ??? FIXME: else assume zero offset. */
8862 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8863 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
8864 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8866 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8870 case SCmode
: mode
= SFmode
; break;
8871 case DCmode
: mode
= DFmode
; break;
8872 case TCmode
: mode
= TFmode
; break;
8876 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8877 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8879 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8880 && (mode
== TFmode
|| mode
== TDmode
));
8881 /* Long double or _Decimal128 split over regs and memory. */
8882 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
8886 = gen_rtx_EXPR_LIST (VOIDmode
,
8887 gen_rtx_REG (mode
, cum
->fregno
++),
8888 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8889 if (mode
== TFmode
|| mode
== TDmode
)
8892 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
8894 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8896 = gen_rtx_EXPR_LIST (VOIDmode
,
8897 gen_rtx_REG (mode
, cum
->vregno
++),
8898 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8900 else if (cum
->intoffset
== -1)
8901 cum
->intoffset
= bitpos
;
8905 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8906 the register(s) to be used for each field and subfield of a struct
8907 being passed by value, along with the offset of where the
8908 register's value may be found in the block. FP fields go in FP
8909 register, vector fields go in vector registers, and everything
8910 else goes in int registers, packed as in memory.
8912 This code is also used for function return values. RETVAL indicates
8913 whether this is the case.
8915 Much of this is taken from the SPARC V9 port, which has a similar
8916 calling convention. */
8919 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
8920 bool named
, bool retval
)
8922 rtx rvec
[FIRST_PSEUDO_REGISTER
];
8923 int k
= 1, kbase
= 1;
8924 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
8925 /* This is a copy; modifications are not visible to our caller. */
8926 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
8927 CUMULATIVE_ARGS
*cum
= ©_cum
;
8929 /* Pad to 16 byte boundary if needed. */
8930 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8931 && (cum
->words
% 2) != 0)
8938 /* Put entries into rvec[] for individual FP and vector fields, and
8939 for the chunks of memory that go in int regs. Note we start at
8940 element 1; 0 is reserved for an indication of using memory, and
8941 may or may not be filled in below. */
8942 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
8943 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
8945 /* If any part of the struct went on the stack put all of it there.
8946 This hack is because the generic code for
8947 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8948 parts of the struct are not at the beginning. */
8952 return NULL_RTX
; /* doesn't go in registers at all */
8954 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8956 if (k
> 1 || cum
->use_stack
)
8957 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
8962 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8965 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
8970 rtx rvec
[GP_ARG_NUM_REG
+ 1];
8972 if (align_words
>= GP_ARG_NUM_REG
)
8975 n_units
= rs6000_arg_size (mode
, type
);
8977 /* Optimize the simple case where the arg fits in one gpr, except in
8978 the case of BLKmode due to assign_parms assuming that registers are
8979 BITS_PER_WORD wide. */
8981 || (n_units
== 1 && mode
!= BLKmode
))
8982 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8985 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
8986 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8987 using a magic NULL_RTX component.
8988 This is not strictly correct. Only some of the arg belongs in
8989 memory, not all of it. However, the normal scheme using
8990 function_arg_partial_nregs can result in unusual subregs, eg.
8991 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8992 store the whole arg to memory is often more efficient than code
8993 to store pieces, and we know that space is available in the right
8994 place for the whole arg. */
8995 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9000 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9001 rtx off
= GEN_INT (i
++ * 4);
9002 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9004 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9006 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9009 /* Determine where to put an argument to a function.
9010 Value is zero to push the argument on the stack,
9011 or a hard register in which to store the argument.
9013 MODE is the argument's machine mode.
9014 TYPE is the data type of the argument (as a tree).
9015 This is null for libcalls where that information may
9017 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9018 the preceding args and about the function being called. It is
9019 not modified in this routine.
9020 NAMED is nonzero if this argument is a named parameter
9021 (otherwise it is an extra parameter matching an ellipsis).
9023 On RS/6000 the first eight words of non-FP are normally in registers
9024 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
9025 Under V.4, the first 8 FP args are in registers.
9027 If this is floating-point and no prototype is specified, we use
9028 both an FP and integer register (or possibly FP reg and stack). Library
9029 functions (when CALL_LIBCALL is set) always have the proper types for args,
9030 so we can pass the FP value just in one register. emit_library_function
9031 doesn't support PARALLEL anyway.
9033 Note that for args passed by reference, function_arg will be called
9034 with MODE and TYPE set to that of the pointer to the arg, not the arg
9038 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
9039 const_tree type
, bool named
)
9041 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9042 enum rs6000_abi abi
= DEFAULT_ABI
;
9044 /* Return a marker to indicate whether CR1 needs to set or clear the
9045 bit that V.4 uses to say fp args were passed in registers.
9046 Assume that we don't need the marker for software floating point,
9047 or compiler generated library calls. */
9048 if (mode
== VOIDmode
)
9051 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
9053 || (cum
->nargs_prototype
< 0
9054 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
9056 /* For the SPE, we need to crxor CR6 always. */
9058 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
9059 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9060 return GEN_INT (cum
->call_cookie
9061 | ((cum
->fregno
== FP_ARG_MIN_REG
)
9062 ? CALL_V4_SET_FP_ARGS
9063 : CALL_V4_CLEAR_FP_ARGS
));
9066 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
9069 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9071 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
9072 if (rslt
!= NULL_RTX
)
9074 /* Else fall through to usual handling. */
9077 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
9078 if (TARGET_64BIT
&& ! cum
->prototype
)
9080 /* Vector parameters get passed in vector register
9081 and also in GPRs or memory, in absence of prototype. */
9084 align_words
= (cum
->words
+ 1) & ~1;
9086 if (align_words
>= GP_ARG_NUM_REG
)
9092 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9094 return gen_rtx_PARALLEL (mode
,
9096 gen_rtx_EXPR_LIST (VOIDmode
,
9098 gen_rtx_EXPR_LIST (VOIDmode
,
9099 gen_rtx_REG (mode
, cum
->vregno
),
9103 return gen_rtx_REG (mode
, cum
->vregno
);
9104 else if (TARGET_ALTIVEC_ABI
9105 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
9106 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9107 && int_size_in_bytes (type
) == 16)))
9109 if (named
|| abi
== ABI_V4
)
9113 /* Vector parameters to varargs functions under AIX or Darwin
9114 get passed in memory and possibly also in GPRs. */
9115 int align
, align_words
, n_words
;
9116 enum machine_mode part_mode
;
9118 /* Vector parameters must be 16-byte aligned. This places them at
9119 2 mod 4 in terms of words in 32-bit mode, since the parameter
9120 save area starts at offset 24 from the stack. In 64-bit mode,
9121 they just have to start on an even word, since the parameter
9122 save area is 16-byte aligned. */
9124 align
= (2 - cum
->words
) & 3;
9126 align
= cum
->words
& 1;
9127 align_words
= cum
->words
+ align
;
9129 /* Out of registers? Memory, then. */
9130 if (align_words
>= GP_ARG_NUM_REG
)
9133 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9134 return rs6000_mixed_function_arg (mode
, type
, align_words
);
9136 /* The vector value goes in GPRs. Only the part of the
9137 value in GPRs is reported here. */
9139 n_words
= rs6000_arg_size (mode
, type
);
9140 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9141 /* Fortunately, there are only two possibilities, the value
9142 is either wholly in GPRs or half in GPRs and half not. */
9145 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
9148 else if (TARGET_SPE_ABI
&& TARGET_SPE
9149 && (SPE_VECTOR_MODE (mode
)
9150 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
9153 || mode
== TCmode
))))
9154 return rs6000_spe_function_arg (cum
, mode
, type
);
9156 else if (abi
== ABI_V4
)
9158 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9159 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9160 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9161 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9162 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9164 /* _Decimal128 must use an even/odd register pair. This assumes
9165 that the register number is odd when fregno is odd. */
9166 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9169 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9170 <= FP_ARG_V4_MAX_REG
)
9171 return gen_rtx_REG (mode
, cum
->fregno
);
9177 int n_words
= rs6000_arg_size (mode
, type
);
9178 int gregno
= cum
->sysv_gregno
;
9180 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9181 (r7,r8) or (r9,r10). As does any other 2 word item such
9182 as complex int due to a historical mistake. */
9184 gregno
+= (1 - gregno
) & 1;
9186 /* Multi-reg args are not split between registers and stack. */
9187 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9190 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9191 return rs6000_mixed_function_arg (mode
, type
,
9192 gregno
- GP_ARG_MIN_REG
);
9193 return gen_rtx_REG (mode
, gregno
);
9198 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
9200 /* _Decimal128 must be passed in an even/odd float register pair.
9201 This assumes that the register number is odd when fregno is odd. */
9202 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9205 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
9207 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9211 enum machine_mode fmode
= mode
;
9212 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9214 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9216 /* Currently, we only ever need one reg here because complex
9217 doubles are split. */
9218 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9219 && (fmode
== TFmode
|| fmode
== TDmode
));
9221 /* Long double or _Decimal128 split over regs and memory. */
9222 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
9225 /* Do we also need to pass this arg in the parameter save
9228 && (cum
->nargs_prototype
<= 0
9229 || (DEFAULT_ABI
== ABI_AIX
9231 && align_words
>= GP_ARG_NUM_REG
)));
9233 if (!needs_psave
&& mode
== fmode
)
9234 return gen_rtx_REG (fmode
, cum
->fregno
);
9239 /* Describe the part that goes in gprs or the stack.
9240 This piece must come first, before the fprs. */
9241 if (align_words
< GP_ARG_NUM_REG
)
9243 unsigned long n_words
= rs6000_arg_size (mode
, type
);
9245 if (align_words
+ n_words
> GP_ARG_NUM_REG
9246 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9248 /* If this is partially on the stack, then we only
9249 include the portion actually in registers here. */
9250 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9253 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9254 /* Not all of the arg fits in gprs. Say that it
9255 goes in memory too, using a magic NULL_RTX
9256 component. Also see comment in
9257 rs6000_mixed_function_arg for why the normal
9258 function_arg_partial_nregs scheme doesn't work
9260 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
9264 r
= gen_rtx_REG (rmode
,
9265 GP_ARG_MIN_REG
+ align_words
);
9266 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9267 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9269 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9273 /* The whole arg fits in gprs. */
9274 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9275 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9279 /* It's entirely in memory. */
9280 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9283 /* Describe where this piece goes in the fprs. */
9284 r
= gen_rtx_REG (fmode
, cum
->fregno
);
9285 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9287 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9289 else if (align_words
< GP_ARG_NUM_REG
)
9291 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9292 return rs6000_mixed_function_arg (mode
, type
, align_words
);
9294 if (mode
== BLKmode
)
9297 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9304 /* For an arg passed partly in registers and partly in memory, this is
9305 the number of bytes passed in registers. For args passed entirely in
9306 registers or entirely in memory, zero. When an arg is described by a
9307 PARALLEL, perhaps using more than one register type, this function
9308 returns the number of bytes used by the first element of the PARALLEL. */
9311 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
9312 tree type
, bool named
)
9314 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9318 if (DEFAULT_ABI
== ABI_V4
)
9321 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
9322 && cum
->nargs_prototype
>= 0)
9325 /* In this complicated case we just disable the partial_nregs code. */
9326 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9329 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
9331 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
9333 /* If we are passing this arg in the fixed parameter save area
9334 (gprs or memory) as well as fprs, then this function should
9335 return the number of partial bytes passed in the parameter
9336 save area rather than partial bytes passed in fprs. */
9338 && (cum
->nargs_prototype
<= 0
9339 || (DEFAULT_ABI
== ABI_AIX
9341 && align_words
>= GP_ARG_NUM_REG
)))
9343 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
9344 > FP_ARG_MAX_REG
+ 1)
9345 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
9346 else if (cum
->nargs_prototype
>= 0)
9350 if (align_words
< GP_ARG_NUM_REG
9351 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
9352 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
9354 if (ret
!= 0 && TARGET_DEBUG_ARG
)
9355 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
9360 /* A C expression that indicates when an argument must be passed by
9361 reference. If nonzero for an argument, a copy of that argument is
9362 made in memory and a pointer to the argument is passed instead of
9363 the argument itself. The pointer is passed in whatever way is
9364 appropriate for passing a pointer to that type.
9366 Under V.4, aggregates and long double are passed by reference.
9368 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
9369 reference unless the AltiVec vector extension ABI is in force.
9371 As an extension to all ABIs, variable sized types are passed by
9375 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
9376 enum machine_mode mode
, const_tree type
,
9377 bool named ATTRIBUTE_UNUSED
)
9379 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
9381 if (TARGET_DEBUG_ARG
)
9382 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
9389 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
9391 if (TARGET_DEBUG_ARG
)
9392 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
9396 if (int_size_in_bytes (type
) < 0)
9398 if (TARGET_DEBUG_ARG
)
9399 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
9403 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9404 modes only exist for GCC vector types if -maltivec. */
9405 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
9407 if (TARGET_DEBUG_ARG
)
9408 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
9412 /* Pass synthetic vectors in memory. */
9413 if (TREE_CODE (type
) == VECTOR_TYPE
9414 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
9416 static bool warned_for_pass_big_vectors
= false;
9417 if (TARGET_DEBUG_ARG
)
9418 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
9419 if (!warned_for_pass_big_vectors
)
9421 warning (0, "GCC vector passed by reference: "
9422 "non-standard ABI extension with no compatibility guarantee");
9423 warned_for_pass_big_vectors
= true;
9432 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
9435 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
9440 for (i
= 0; i
< nregs
; i
++)
9442 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
9443 if (reload_completed
)
9445 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
9448 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
9449 i
* GET_MODE_SIZE (reg_mode
));
9452 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
9456 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
9460 /* Perform any needed actions needed for a function that is receiving a
9461 variable number of arguments.
9465 MODE and TYPE are the mode and type of the current parameter.
9467 PRETEND_SIZE is a variable that should be set to the amount of stack
9468 that must be pushed by the prolog to pretend that our caller pushed
9471 Normally, this macro will push all remaining incoming registers on the
9472 stack and set PRETEND_SIZE to the length of the registers pushed. */
9475 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
9476 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
9479 CUMULATIVE_ARGS next_cum
;
9480 int reg_size
= TARGET_32BIT
? 4 : 8;
9481 rtx save_area
= NULL_RTX
, mem
;
9482 int first_reg_offset
;
9485 /* Skip the last named argument. */
9486 next_cum
= *get_cumulative_args (cum
);
9487 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
9489 if (DEFAULT_ABI
== ABI_V4
)
9491 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
9495 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
9496 HOST_WIDE_INT offset
= 0;
9498 /* Try to optimize the size of the varargs save area.
9499 The ABI requires that ap.reg_save_area is doubleword
9500 aligned, but we don't need to allocate space for all
9501 the bytes, only those to which we actually will save
9503 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
9504 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
9505 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9506 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
9507 && cfun
->va_list_fpr_size
)
9510 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
9511 * UNITS_PER_FP_WORD
;
9512 if (cfun
->va_list_fpr_size
9513 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
9514 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
9516 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
9517 * UNITS_PER_FP_WORD
;
9521 offset
= -((first_reg_offset
* reg_size
) & ~7);
9522 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
9524 gpr_reg_num
= cfun
->va_list_gpr_size
;
9525 if (reg_size
== 4 && (first_reg_offset
& 1))
9528 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
9531 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
9533 - (int) (GP_ARG_NUM_REG
* reg_size
);
9535 if (gpr_size
+ fpr_size
)
9538 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
9539 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
9540 reg_save_area
= XEXP (reg_save_area
, 0);
9541 if (GET_CODE (reg_save_area
) == PLUS
)
9543 gcc_assert (XEXP (reg_save_area
, 0)
9544 == virtual_stack_vars_rtx
);
9545 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
9546 offset
+= INTVAL (XEXP (reg_save_area
, 1));
9549 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
9552 cfun
->machine
->varargs_save_offset
= offset
;
9553 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
9558 first_reg_offset
= next_cum
.words
;
9559 save_area
= virtual_incoming_args_rtx
;
9561 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
9562 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
9565 set
= get_varargs_alias_set ();
9566 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
9567 && cfun
->va_list_gpr_size
)
9569 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
9571 if (va_list_gpr_counter_field
)
9572 /* V4 va_list_gpr_size counts number of registers needed. */
9573 n_gpr
= cfun
->va_list_gpr_size
;
9575 /* char * va_list instead counts number of bytes needed. */
9576 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
9581 mem
= gen_rtx_MEM (BLKmode
,
9582 plus_constant (Pmode
, save_area
,
9583 first_reg_offset
* reg_size
));
9584 MEM_NOTRAP_P (mem
) = 1;
9585 set_mem_alias_set (mem
, set
);
9586 set_mem_align (mem
, BITS_PER_WORD
);
9588 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
9592 /* Save FP registers if needed. */
9593 if (DEFAULT_ABI
== ABI_V4
9594 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9596 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
9597 && cfun
->va_list_fpr_size
)
9599 int fregno
= next_cum
.fregno
, nregs
;
9600 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
9601 rtx lab
= gen_label_rtx ();
9602 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
9603 * UNITS_PER_FP_WORD
);
9606 (gen_rtx_SET (VOIDmode
,
9608 gen_rtx_IF_THEN_ELSE (VOIDmode
,
9609 gen_rtx_NE (VOIDmode
, cr1
,
9611 gen_rtx_LABEL_REF (VOIDmode
, lab
),
9615 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
9616 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
9618 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9620 plus_constant (Pmode
, save_area
, off
));
9621 MEM_NOTRAP_P (mem
) = 1;
9622 set_mem_alias_set (mem
, set
);
9623 set_mem_align (mem
, GET_MODE_ALIGNMENT (
9624 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9625 ? DFmode
: SFmode
));
9626 emit_move_insn (mem
, gen_rtx_REG (
9627 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9628 ? DFmode
: SFmode
, fregno
));
9635 /* Create the va_list data type. */
9638 rs6000_build_builtin_va_list (void)
9640 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
9642 /* For AIX, prefer 'char *' because that's what the system
9643 header files like. */
9644 if (DEFAULT_ABI
!= ABI_V4
)
9645 return build_pointer_type (char_type_node
);
9647 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
9648 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
9649 get_identifier ("__va_list_tag"), record
);
9651 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
9652 unsigned_char_type_node
);
9653 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
9654 unsigned_char_type_node
);
9655 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9657 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9658 get_identifier ("reserved"), short_unsigned_type_node
);
9659 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9660 get_identifier ("overflow_arg_area"),
9662 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9663 get_identifier ("reg_save_area"),
9666 va_list_gpr_counter_field
= f_gpr
;
9667 va_list_fpr_counter_field
= f_fpr
;
9669 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9670 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9671 DECL_FIELD_CONTEXT (f_res
) = record
;
9672 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9673 DECL_FIELD_CONTEXT (f_sav
) = record
;
9675 TYPE_STUB_DECL (record
) = type_decl
;
9676 TYPE_NAME (record
) = type_decl
;
9677 TYPE_FIELDS (record
) = f_gpr
;
9678 DECL_CHAIN (f_gpr
) = f_fpr
;
9679 DECL_CHAIN (f_fpr
) = f_res
;
9680 DECL_CHAIN (f_res
) = f_ovf
;
9681 DECL_CHAIN (f_ovf
) = f_sav
;
9683 layout_type (record
);
9685 /* The correct type is an array type of one element. */
9686 return build_array_type (record
, build_index_type (size_zero_node
));
9689 /* Implement va_start. */
9692 rs6000_va_start (tree valist
, rtx nextarg
)
9694 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
9695 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9696 tree gpr
, fpr
, ovf
, sav
, t
;
9698 /* Only SVR4 needs something special. */
9699 if (DEFAULT_ABI
!= ABI_V4
)
9701 std_expand_builtin_va_start (valist
, nextarg
);
9705 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9706 f_fpr
= DECL_CHAIN (f_gpr
);
9707 f_res
= DECL_CHAIN (f_fpr
);
9708 f_ovf
= DECL_CHAIN (f_res
);
9709 f_sav
= DECL_CHAIN (f_ovf
);
9711 valist
= build_simple_mem_ref (valist
);
9712 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9713 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9715 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9717 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9720 /* Count number of gp and fp argument registers used. */
9721 words
= crtl
->args
.info
.words
;
9722 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
9724 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
9727 if (TARGET_DEBUG_ARG
)
9728 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
9729 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
9730 words
, n_gpr
, n_fpr
);
9732 if (cfun
->va_list_gpr_size
)
9734 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9735 build_int_cst (NULL_TREE
, n_gpr
));
9736 TREE_SIDE_EFFECTS (t
) = 1;
9737 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9740 if (cfun
->va_list_fpr_size
)
9742 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9743 build_int_cst (NULL_TREE
, n_fpr
));
9744 TREE_SIDE_EFFECTS (t
) = 1;
9745 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9747 #ifdef HAVE_AS_GNU_ATTRIBUTE
9748 if (call_ABI_of_interest (cfun
->decl
))
9749 rs6000_passes_float
= true;
9753 /* Find the overflow area. */
9754 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9756 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
9757 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9758 TREE_SIDE_EFFECTS (t
) = 1;
9759 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9761 /* If there were no va_arg invocations, don't set up the register
9763 if (!cfun
->va_list_gpr_size
9764 && !cfun
->va_list_fpr_size
9765 && n_gpr
< GP_ARG_NUM_REG
9766 && n_fpr
< FP_ARG_V4_MAX_REG
)
9769 /* Find the register save area. */
9770 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
9771 if (cfun
->machine
->varargs_save_offset
)
9772 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
9773 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9774 TREE_SIDE_EFFECTS (t
) = 1;
9775 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9778 /* Implement va_arg. */
9781 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9784 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9785 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9786 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
9787 tree lab_false
, lab_over
, addr
;
9789 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9793 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9795 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
9796 return build_va_arg_indirect_ref (t
);
9799 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9800 earlier version of gcc, with the property that it always applied alignment
9801 adjustments to the va-args (even for zero-sized types). The cheapest way
9802 to deal with this is to replicate the effect of the part of
9803 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9805 We don't need to check for pass-by-reference because of the test above.
9806 We can return a simplifed answer, since we know there's no offset to add. */
9809 && rs6000_darwin64_abi
9810 && integer_zerop (TYPE_SIZE (type
)))
9812 unsigned HOST_WIDE_INT align
, boundary
;
9813 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
9814 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
9815 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
9816 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
9817 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
9818 boundary
/= BITS_PER_UNIT
;
9819 if (boundary
> align
)
9822 /* This updates arg ptr by the amount that would be necessary
9823 to align the zero-sized (but not zero-alignment) item. */
9824 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9825 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
9826 gimplify_and_add (t
, pre_p
);
9828 t
= fold_convert (sizetype
, valist_tmp
);
9829 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9830 fold_convert (TREE_TYPE (valist
),
9831 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
9832 size_int (-boundary
))));
9833 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
9834 gimplify_and_add (t
, pre_p
);
9836 /* Since it is zero-sized there's no increment for the item itself. */
9837 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
9838 return build_va_arg_indirect_ref (valist_tmp
);
9841 if (DEFAULT_ABI
!= ABI_V4
)
9843 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
9845 tree elem_type
= TREE_TYPE (type
);
9846 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
9847 int elem_size
= GET_MODE_SIZE (elem_mode
);
9849 if (elem_size
< UNITS_PER_WORD
)
9851 tree real_part
, imag_part
;
9852 gimple_seq post
= NULL
;
9854 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9856 /* Copy the value into a temporary, lest the formal temporary
9857 be reused out from under us. */
9858 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
9859 gimple_seq_add_seq (pre_p
, post
);
9861 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9864 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
9868 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
9871 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9872 f_fpr
= DECL_CHAIN (f_gpr
);
9873 f_res
= DECL_CHAIN (f_fpr
);
9874 f_ovf
= DECL_CHAIN (f_res
);
9875 f_sav
= DECL_CHAIN (f_ovf
);
9877 valist
= build_va_arg_indirect_ref (valist
);
9878 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9879 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9881 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9883 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9886 size
= int_size_in_bytes (type
);
9887 rsize
= (size
+ 3) / 4;
9890 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9891 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
9892 || (TARGET_DOUBLE_FLOAT
9893 && (TYPE_MODE (type
) == DFmode
9894 || TYPE_MODE (type
) == TFmode
9895 || TYPE_MODE (type
) == SDmode
9896 || TYPE_MODE (type
) == DDmode
9897 || TYPE_MODE (type
) == TDmode
))))
9899 /* FP args go in FP registers, if present. */
9901 n_reg
= (size
+ 7) / 8;
9902 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
9903 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
9904 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
9909 /* Otherwise into GP registers. */
9918 /* Pull the value out of the saved registers.... */
9921 addr
= create_tmp_var (ptr_type_node
, "addr");
9923 /* AltiVec vectors never go in registers when -mabi=altivec. */
9924 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9928 lab_false
= create_artificial_label (input_location
);
9929 lab_over
= create_artificial_label (input_location
);
9931 /* Long long and SPE vectors are aligned in the registers.
9932 As are any other 2 gpr item such as complex int due to a
9933 historical mistake. */
9935 if (n_reg
== 2 && reg
== gpr
)
9938 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9939 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
9940 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
9941 unshare_expr (reg
), u
);
9943 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9944 reg number is 0 for f1, so we want to make it odd. */
9945 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
9947 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9948 build_int_cst (TREE_TYPE (reg
), 1));
9949 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
9952 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
9953 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
9954 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9955 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9956 gimplify_and_add (t
, pre_p
);
9960 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9962 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9963 build_int_cst (TREE_TYPE (reg
), n_reg
));
9964 u
= fold_convert (sizetype
, u
);
9965 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
9966 t
= fold_build_pointer_plus (t
, u
);
9968 /* _Decimal32 varargs are located in the second word of the 64-bit
9969 FP register for 32-bit binaries. */
9970 if (!TARGET_POWERPC64
9971 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9972 && TYPE_MODE (type
) == SDmode
)
9973 t
= fold_build_pointer_plus_hwi (t
, size
);
9975 gimplify_assign (addr
, t
, pre_p
);
9977 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9979 stmt
= gimple_build_label (lab_false
);
9980 gimple_seq_add_stmt (pre_p
, stmt
);
9982 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
9984 /* Ensure that we don't find any more args in regs.
9985 Alignment has taken care of for special cases. */
9986 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
9990 /* ... otherwise out of the overflow area. */
9992 /* Care for on-stack alignment if needed. */
9996 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
9997 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
9998 build_int_cst (TREE_TYPE (t
), -align
));
10000 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
10002 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
10004 t
= fold_build_pointer_plus_hwi (t
, size
);
10005 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
10009 stmt
= gimple_build_label (lab_over
);
10010 gimple_seq_add_stmt (pre_p
, stmt
);
10013 if (STRICT_ALIGNMENT
10014 && (TYPE_ALIGN (type
)
10015 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
10017 /* The value (of type complex double, for example) may not be
10018 aligned in memory in the saved registers, so copy via a
10019 temporary. (This is the same code as used for SPARC.) */
10020 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
10021 tree dest_addr
= build_fold_addr_expr (tmp
);
10023 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
10024 3, dest_addr
, addr
, size_int (rsize
* 4));
10026 gimplify_and_add (copy
, pre_p
);
10030 addr
= fold_convert (ptrtype
, addr
);
10031 return build_va_arg_indirect_ref (addr
);
10037 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
10040 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
10041 const char *attr_string
= "";
10043 gcc_assert (name
!= NULL
);
10044 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
10046 if (rs6000_builtin_decls
[(int)code
])
10047 fatal_error ("internal error: builtin function %s already processed", name
);
10049 rs6000_builtin_decls
[(int)code
] = t
=
10050 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10052 /* Set any special attributes. */
10053 if ((classify
& RS6000_BTC_CONST
) != 0)
10055 /* const function, function only depends on the inputs. */
10056 TREE_READONLY (t
) = 1;
10057 TREE_NOTHROW (t
) = 1;
10058 attr_string
= ", pure";
10060 else if ((classify
& RS6000_BTC_PURE
) != 0)
10062 /* pure function, function can read global memory, but does not set any
10064 DECL_PURE_P (t
) = 1;
10065 TREE_NOTHROW (t
) = 1;
10066 attr_string
= ", const";
10068 else if ((classify
& RS6000_BTC_FP
) != 0)
10070 /* Function is a math function. If rounding mode is on, then treat the
10071 function as not reading global memory, but it can have arbitrary side
10072 effects. If it is off, then assume the function is a const function.
10073 This mimics the ATTR_MATHFN_FPROUNDING attribute in
10074 builtin-attribute.def that is used for the math functions. */
10075 TREE_NOTHROW (t
) = 1;
10076 if (flag_rounding_math
)
10078 DECL_PURE_P (t
) = 1;
10079 DECL_IS_NOVOPS (t
) = 1;
10080 attr_string
= ", fp, pure";
10084 TREE_READONLY (t
) = 1;
10085 attr_string
= ", fp, const";
10088 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
10089 gcc_unreachable ();
10091 if (TARGET_DEBUG_BUILTIN
)
10092 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
10093 (int)code
, name
, attr_string
);
10096 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
10098 #undef RS6000_BUILTIN_1
10099 #undef RS6000_BUILTIN_2
10100 #undef RS6000_BUILTIN_3
10101 #undef RS6000_BUILTIN_A
10102 #undef RS6000_BUILTIN_D
10103 #undef RS6000_BUILTIN_E
10104 #undef RS6000_BUILTIN_P
10105 #undef RS6000_BUILTIN_Q
10106 #undef RS6000_BUILTIN_S
10107 #undef RS6000_BUILTIN_X
10109 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10110 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10111 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
10112 { MASK, ICODE, NAME, ENUM },
10114 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10115 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10116 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10117 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10118 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10119 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10120 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10122 static const struct builtin_description bdesc_3arg
[] =
10124 #include "rs6000-builtin.def"
10127 /* DST operations: void foo (void *, const int, const char). */
10129 #undef RS6000_BUILTIN_1
10130 #undef RS6000_BUILTIN_2
10131 #undef RS6000_BUILTIN_3
10132 #undef RS6000_BUILTIN_A
10133 #undef RS6000_BUILTIN_D
10134 #undef RS6000_BUILTIN_E
10135 #undef RS6000_BUILTIN_P
10136 #undef RS6000_BUILTIN_Q
10137 #undef RS6000_BUILTIN_S
10138 #undef RS6000_BUILTIN_X
10140 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10141 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10142 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10143 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10144 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
10145 { MASK, ICODE, NAME, ENUM },
10147 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10148 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10149 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10150 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10151 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10153 static const struct builtin_description bdesc_dst
[] =
10155 #include "rs6000-builtin.def"
10158 /* Simple binary operations: VECc = foo (VECa, VECb). */
10160 #undef RS6000_BUILTIN_1
10161 #undef RS6000_BUILTIN_2
10162 #undef RS6000_BUILTIN_3
10163 #undef RS6000_BUILTIN_A
10164 #undef RS6000_BUILTIN_D
10165 #undef RS6000_BUILTIN_E
10166 #undef RS6000_BUILTIN_P
10167 #undef RS6000_BUILTIN_Q
10168 #undef RS6000_BUILTIN_S
10169 #undef RS6000_BUILTIN_X
10171 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10172 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
10173 { MASK, ICODE, NAME, ENUM },
10175 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10176 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10177 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10178 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10179 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10180 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10181 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10182 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10184 static const struct builtin_description bdesc_2arg
[] =
10186 #include "rs6000-builtin.def"
10189 #undef RS6000_BUILTIN_1
10190 #undef RS6000_BUILTIN_2
10191 #undef RS6000_BUILTIN_3
10192 #undef RS6000_BUILTIN_A
10193 #undef RS6000_BUILTIN_D
10194 #undef RS6000_BUILTIN_E
10195 #undef RS6000_BUILTIN_P
10196 #undef RS6000_BUILTIN_Q
10197 #undef RS6000_BUILTIN_S
10198 #undef RS6000_BUILTIN_X
10200 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10201 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10202 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10203 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10204 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10205 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10206 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
10207 { MASK, ICODE, NAME, ENUM },
10209 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10210 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10211 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10213 /* AltiVec predicates. */
10215 static const struct builtin_description bdesc_altivec_preds
[] =
10217 #include "rs6000-builtin.def"
10220 /* SPE predicates. */
10221 #undef RS6000_BUILTIN_1
10222 #undef RS6000_BUILTIN_2
10223 #undef RS6000_BUILTIN_3
10224 #undef RS6000_BUILTIN_A
10225 #undef RS6000_BUILTIN_D
10226 #undef RS6000_BUILTIN_E
10227 #undef RS6000_BUILTIN_P
10228 #undef RS6000_BUILTIN_Q
10229 #undef RS6000_BUILTIN_S
10230 #undef RS6000_BUILTIN_X
10232 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10233 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10234 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10235 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10236 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10237 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10238 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10239 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10240 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
10241 { MASK, ICODE, NAME, ENUM },
10243 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10245 static const struct builtin_description bdesc_spe_predicates
[] =
10247 #include "rs6000-builtin.def"
10250 /* SPE evsel predicates. */
10251 #undef RS6000_BUILTIN_1
10252 #undef RS6000_BUILTIN_2
10253 #undef RS6000_BUILTIN_3
10254 #undef RS6000_BUILTIN_A
10255 #undef RS6000_BUILTIN_D
10256 #undef RS6000_BUILTIN_E
10257 #undef RS6000_BUILTIN_P
10258 #undef RS6000_BUILTIN_Q
10259 #undef RS6000_BUILTIN_S
10260 #undef RS6000_BUILTIN_X
10262 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10263 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10264 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10265 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10266 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10267 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
10268 { MASK, ICODE, NAME, ENUM },
10270 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10271 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10272 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10273 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10275 static const struct builtin_description bdesc_spe_evsel
[] =
10277 #include "rs6000-builtin.def"
10280 /* PAIRED predicates. */
10281 #undef RS6000_BUILTIN_1
10282 #undef RS6000_BUILTIN_2
10283 #undef RS6000_BUILTIN_3
10284 #undef RS6000_BUILTIN_A
10285 #undef RS6000_BUILTIN_D
10286 #undef RS6000_BUILTIN_E
10287 #undef RS6000_BUILTIN_P
10288 #undef RS6000_BUILTIN_Q
10289 #undef RS6000_BUILTIN_S
10290 #undef RS6000_BUILTIN_X
10292 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10293 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10294 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10295 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10296 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10297 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10298 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10299 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
10300 { MASK, ICODE, NAME, ENUM },
10302 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10303 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10305 static const struct builtin_description bdesc_paired_preds
[] =
10307 #include "rs6000-builtin.def"
10310 /* ABS* operations. */
10312 #undef RS6000_BUILTIN_1
10313 #undef RS6000_BUILTIN_2
10314 #undef RS6000_BUILTIN_3
10315 #undef RS6000_BUILTIN_A
10316 #undef RS6000_BUILTIN_D
10317 #undef RS6000_BUILTIN_E
10318 #undef RS6000_BUILTIN_P
10319 #undef RS6000_BUILTIN_Q
10320 #undef RS6000_BUILTIN_S
10321 #undef RS6000_BUILTIN_X
10323 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10324 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10325 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10326 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
10327 { MASK, ICODE, NAME, ENUM },
10329 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10330 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10331 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10332 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10333 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10334 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10336 static const struct builtin_description bdesc_abs
[] =
10338 #include "rs6000-builtin.def"
10341 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
10344 #undef RS6000_BUILTIN_1
10345 #undef RS6000_BUILTIN_2
10346 #undef RS6000_BUILTIN_3
10347 #undef RS6000_BUILTIN_A
10348 #undef RS6000_BUILTIN_E
10349 #undef RS6000_BUILTIN_D
10350 #undef RS6000_BUILTIN_P
10351 #undef RS6000_BUILTIN_Q
10352 #undef RS6000_BUILTIN_S
10353 #undef RS6000_BUILTIN_X
10355 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
10356 { MASK, ICODE, NAME, ENUM },
10358 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10359 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10360 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10361 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10362 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10363 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10364 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10365 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10366 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10368 static const struct builtin_description bdesc_1arg
[] =
10370 #include "rs6000-builtin.def"
10373 #undef RS6000_BUILTIN_1
10374 #undef RS6000_BUILTIN_2
10375 #undef RS6000_BUILTIN_3
10376 #undef RS6000_BUILTIN_A
10377 #undef RS6000_BUILTIN_D
10378 #undef RS6000_BUILTIN_E
10379 #undef RS6000_BUILTIN_P
10380 #undef RS6000_BUILTIN_Q
10381 #undef RS6000_BUILTIN_S
10382 #undef RS6000_BUILTIN_X
10384 /* Return true if a builtin function is overloaded. */
10386 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
10388 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
10391 /* Expand an expression EXP that calls a builtin without arguments. */
10393 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
10396 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10398 if (icode
== CODE_FOR_nothing
)
10399 /* Builtin not supported on this processor. */
10403 || GET_MODE (target
) != tmode
10404 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10405 target
= gen_reg_rtx (tmode
);
10407 pat
= GEN_FCN (icode
) (target
);
10417 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10420 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10421 rtx op0
= expand_normal (arg0
);
10422 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10423 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10425 if (icode
== CODE_FOR_nothing
)
10426 /* Builtin not supported on this processor. */
10429 /* If we got invalid arguments bail out before generating bad rtl. */
10430 if (arg0
== error_mark_node
)
10433 if (icode
== CODE_FOR_altivec_vspltisb
10434 || icode
== CODE_FOR_altivec_vspltish
10435 || icode
== CODE_FOR_altivec_vspltisw
10436 || icode
== CODE_FOR_spe_evsplatfi
10437 || icode
== CODE_FOR_spe_evsplati
)
10439 /* Only allow 5-bit *signed* literals. */
10440 if (GET_CODE (op0
) != CONST_INT
10441 || INTVAL (op0
) > 15
10442 || INTVAL (op0
) < -16)
10444 error ("argument 1 must be a 5-bit signed literal");
10450 || GET_MODE (target
) != tmode
10451 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10452 target
= gen_reg_rtx (tmode
);
10454 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10455 op0
= copy_to_mode_reg (mode0
, op0
);
10457 pat
= GEN_FCN (icode
) (target
, op0
);
10466 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
10468 rtx pat
, scratch1
, scratch2
;
10469 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10470 rtx op0
= expand_normal (arg0
);
10471 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10472 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10474 /* If we have invalid arguments, bail out before generating bad rtl. */
10475 if (arg0
== error_mark_node
)
10479 || GET_MODE (target
) != tmode
10480 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10481 target
= gen_reg_rtx (tmode
);
10483 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10484 op0
= copy_to_mode_reg (mode0
, op0
);
10486 scratch1
= gen_reg_rtx (mode0
);
10487 scratch2
= gen_reg_rtx (mode0
);
10489 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
10498 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10501 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10502 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10503 rtx op0
= expand_normal (arg0
);
10504 rtx op1
= expand_normal (arg1
);
10505 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10506 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10507 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10509 if (icode
== CODE_FOR_nothing
)
10510 /* Builtin not supported on this processor. */
10513 /* If we got invalid arguments bail out before generating bad rtl. */
10514 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10517 if (icode
== CODE_FOR_altivec_vcfux
10518 || icode
== CODE_FOR_altivec_vcfsx
10519 || icode
== CODE_FOR_altivec_vctsxs
10520 || icode
== CODE_FOR_altivec_vctuxs
10521 || icode
== CODE_FOR_altivec_vspltb
10522 || icode
== CODE_FOR_altivec_vsplth
10523 || icode
== CODE_FOR_altivec_vspltw
10524 || icode
== CODE_FOR_spe_evaddiw
10525 || icode
== CODE_FOR_spe_evldd
10526 || icode
== CODE_FOR_spe_evldh
10527 || icode
== CODE_FOR_spe_evldw
10528 || icode
== CODE_FOR_spe_evlhhesplat
10529 || icode
== CODE_FOR_spe_evlhhossplat
10530 || icode
== CODE_FOR_spe_evlhhousplat
10531 || icode
== CODE_FOR_spe_evlwhe
10532 || icode
== CODE_FOR_spe_evlwhos
10533 || icode
== CODE_FOR_spe_evlwhou
10534 || icode
== CODE_FOR_spe_evlwhsplat
10535 || icode
== CODE_FOR_spe_evlwwsplat
10536 || icode
== CODE_FOR_spe_evrlwi
10537 || icode
== CODE_FOR_spe_evslwi
10538 || icode
== CODE_FOR_spe_evsrwis
10539 || icode
== CODE_FOR_spe_evsubifw
10540 || icode
== CODE_FOR_spe_evsrwiu
)
10542 /* Only allow 5-bit unsigned literals. */
10544 if (TREE_CODE (arg1
) != INTEGER_CST
10545 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
10547 error ("argument 2 must be a 5-bit unsigned literal");
10553 || GET_MODE (target
) != tmode
10554 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10555 target
= gen_reg_rtx (tmode
);
10557 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10558 op0
= copy_to_mode_reg (mode0
, op0
);
10559 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10560 op1
= copy_to_mode_reg (mode1
, op1
);
10562 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
10571 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
10574 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
10575 tree arg0
= CALL_EXPR_ARG (exp
, 1);
10576 tree arg1
= CALL_EXPR_ARG (exp
, 2);
10577 rtx op0
= expand_normal (arg0
);
10578 rtx op1
= expand_normal (arg1
);
10579 enum machine_mode tmode
= SImode
;
10580 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10581 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10584 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
10586 error ("argument 1 of __builtin_altivec_predicate must be a constant");
10590 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
10592 gcc_assert (mode0
== mode1
);
10594 /* If we have invalid arguments, bail out before generating bad rtl. */
10595 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10599 || GET_MODE (target
) != tmode
10600 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10601 target
= gen_reg_rtx (tmode
);
10603 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10604 op0
= copy_to_mode_reg (mode0
, op0
);
10605 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10606 op1
= copy_to_mode_reg (mode1
, op1
);
10608 scratch
= gen_reg_rtx (mode0
);
10610 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
10615 /* The vec_any* and vec_all* predicates use the same opcodes for two
10616 different operations, but the bits in CR6 will be different
10617 depending on what information we want. So we have to play tricks
10618 with CR6 to get the right bits out.
10620 If you think this is disgusting, look at the specs for the
10621 AltiVec predicates. */
10623 switch (cr6_form_int
)
10626 emit_insn (gen_cr6_test_for_zero (target
));
10629 emit_insn (gen_cr6_test_for_zero_reverse (target
));
10632 emit_insn (gen_cr6_test_for_lt (target
));
10635 emit_insn (gen_cr6_test_for_lt_reverse (target
));
10638 error ("argument 1 of __builtin_altivec_predicate is out of range");
10646 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
10649 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10650 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10651 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10652 enum machine_mode mode0
= Pmode
;
10653 enum machine_mode mode1
= Pmode
;
10654 rtx op0
= expand_normal (arg0
);
10655 rtx op1
= expand_normal (arg1
);
10657 if (icode
== CODE_FOR_nothing
)
10658 /* Builtin not supported on this processor. */
10661 /* If we got invalid arguments bail out before generating bad rtl. */
10662 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10666 || GET_MODE (target
) != tmode
10667 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10668 target
= gen_reg_rtx (tmode
);
10670 op1
= copy_to_mode_reg (mode1
, op1
);
10672 if (op0
== const0_rtx
)
10674 addr
= gen_rtx_MEM (tmode
, op1
);
10678 op0
= copy_to_mode_reg (mode0
, op0
);
10679 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10682 pat
= GEN_FCN (icode
) (target
, addr
);
10692 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
10695 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10696 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10697 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10698 enum machine_mode mode0
= Pmode
;
10699 enum machine_mode mode1
= Pmode
;
10700 rtx op0
= expand_normal (arg0
);
10701 rtx op1
= expand_normal (arg1
);
10703 if (icode
== CODE_FOR_nothing
)
10704 /* Builtin not supported on this processor. */
10707 /* If we got invalid arguments bail out before generating bad rtl. */
10708 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10712 || GET_MODE (target
) != tmode
10713 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10714 target
= gen_reg_rtx (tmode
);
10716 op1
= copy_to_mode_reg (mode1
, op1
);
10718 if (op0
== const0_rtx
)
10720 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
10724 op0
= copy_to_mode_reg (mode0
, op0
);
10725 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10728 pat
= GEN_FCN (icode
) (target
, addr
);
10738 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
10740 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10741 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10742 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10743 rtx op0
= expand_normal (arg0
);
10744 rtx op1
= expand_normal (arg1
);
10745 rtx op2
= expand_normal (arg2
);
10747 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
10748 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
10749 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
10751 /* Invalid arguments. Bail before doing anything stoopid! */
10752 if (arg0
== error_mark_node
10753 || arg1
== error_mark_node
10754 || arg2
== error_mark_node
)
10757 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
10758 op0
= copy_to_mode_reg (mode2
, op0
);
10759 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
10760 op1
= copy_to_mode_reg (mode0
, op1
);
10761 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
10762 op2
= copy_to_mode_reg (mode1
, op2
);
10764 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
10771 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
10773 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10774 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10775 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10776 rtx op0
= expand_normal (arg0
);
10777 rtx op1
= expand_normal (arg1
);
10778 rtx op2
= expand_normal (arg2
);
10780 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10781 enum machine_mode mode1
= Pmode
;
10782 enum machine_mode mode2
= Pmode
;
10784 /* Invalid arguments. Bail before doing anything stoopid! */
10785 if (arg0
== error_mark_node
10786 || arg1
== error_mark_node
10787 || arg2
== error_mark_node
)
10790 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
10791 op0
= copy_to_mode_reg (tmode
, op0
);
10793 op2
= copy_to_mode_reg (mode2
, op2
);
10795 if (op1
== const0_rtx
)
10797 addr
= gen_rtx_MEM (tmode
, op2
);
10801 op1
= copy_to_mode_reg (mode1
, op1
);
10802 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10805 pat
= GEN_FCN (icode
) (addr
, op0
);
10812 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
10814 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10815 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10816 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10817 rtx op0
= expand_normal (arg0
);
10818 rtx op1
= expand_normal (arg1
);
10819 rtx op2
= expand_normal (arg2
);
10821 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10822 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
10823 enum machine_mode mode1
= Pmode
;
10824 enum machine_mode mode2
= Pmode
;
10826 /* Invalid arguments. Bail before doing anything stoopid! */
10827 if (arg0
== error_mark_node
10828 || arg1
== error_mark_node
10829 || arg2
== error_mark_node
)
10832 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
10833 op0
= copy_to_mode_reg (smode
, op0
);
10835 op2
= copy_to_mode_reg (mode2
, op2
);
10837 if (op1
== const0_rtx
)
10839 addr
= gen_rtx_MEM (tmode
, op2
);
10843 op1
= copy_to_mode_reg (mode1
, op1
);
10844 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10847 pat
= GEN_FCN (icode
) (addr
, op0
);
10854 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10857 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10858 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10859 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10860 rtx op0
= expand_normal (arg0
);
10861 rtx op1
= expand_normal (arg1
);
10862 rtx op2
= expand_normal (arg2
);
10863 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10864 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10865 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10866 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
10868 if (icode
== CODE_FOR_nothing
)
10869 /* Builtin not supported on this processor. */
10872 /* If we got invalid arguments bail out before generating bad rtl. */
10873 if (arg0
== error_mark_node
10874 || arg1
== error_mark_node
10875 || arg2
== error_mark_node
)
10878 /* Check and prepare argument depending on the instruction code.
10880 Note that a switch statement instead of the sequence of tests
10881 would be incorrect as many of the CODE_FOR values could be
10882 CODE_FOR_nothing and that would yield multiple alternatives
10883 with identical values. We'd never reach here at runtime in
10885 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
10886 || icode
== CODE_FOR_altivec_vsldoi_v4si
10887 || icode
== CODE_FOR_altivec_vsldoi_v8hi
10888 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
10890 /* Only allow 4-bit unsigned literals. */
10892 if (TREE_CODE (arg2
) != INTEGER_CST
10893 || TREE_INT_CST_LOW (arg2
) & ~0xf)
10895 error ("argument 3 must be a 4-bit unsigned literal");
10899 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
10900 || icode
== CODE_FOR_vsx_xxpermdi_v2di
10901 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
10902 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
10903 || icode
== CODE_FOR_vsx_xxsldwi_v4si
10904 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
10905 || icode
== CODE_FOR_vsx_xxsldwi_v2di
10906 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
10908 /* Only allow 2-bit unsigned literals. */
10910 if (TREE_CODE (arg2
) != INTEGER_CST
10911 || TREE_INT_CST_LOW (arg2
) & ~0x3)
10913 error ("argument 3 must be a 2-bit unsigned literal");
10917 else if (icode
== CODE_FOR_vsx_set_v2df
10918 || icode
== CODE_FOR_vsx_set_v2di
)
10920 /* Only allow 1-bit unsigned literals. */
10922 if (TREE_CODE (arg2
) != INTEGER_CST
10923 || TREE_INT_CST_LOW (arg2
) & ~0x1)
10925 error ("argument 3 must be a 1-bit unsigned literal");
10929 else if (icode
== CODE_FOR_crypto_vshasigmaw
10930 || icode
== CODE_FOR_crypto_vshasigmad
)
10932 /* Check whether the 2nd and 3rd arguments are integer constants and in
10933 range and prepare arguments. */
10935 if (TREE_CODE (arg1
) != INTEGER_CST
10936 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
10938 error ("argument 2 must be 0 or 1");
10943 if (TREE_CODE (arg2
) != INTEGER_CST
10944 || !IN_RANGE (TREE_INT_CST_LOW (arg2
), 0, 15))
10946 error ("argument 3 must be in the range 0..15");
10952 || GET_MODE (target
) != tmode
10953 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10954 target
= gen_reg_rtx (tmode
);
10956 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10957 op0
= copy_to_mode_reg (mode0
, op0
);
10958 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10959 op1
= copy_to_mode_reg (mode1
, op1
);
10960 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
10961 op2
= copy_to_mode_reg (mode2
, op2
);
10963 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
10964 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
10966 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
10974 /* Expand the lvx builtins. */
10976 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
10978 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10979 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10981 enum machine_mode tmode
, mode0
;
10983 enum insn_code icode
;
10987 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
10988 icode
= CODE_FOR_vector_altivec_load_v16qi
;
10990 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
10991 icode
= CODE_FOR_vector_altivec_load_v8hi
;
10993 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
10994 icode
= CODE_FOR_vector_altivec_load_v4si
;
10996 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
10997 icode
= CODE_FOR_vector_altivec_load_v4sf
;
10999 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
11000 icode
= CODE_FOR_vector_altivec_load_v2df
;
11002 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
11003 icode
= CODE_FOR_vector_altivec_load_v2di
;
11006 *expandedp
= false;
11012 arg0
= CALL_EXPR_ARG (exp
, 0);
11013 op0
= expand_normal (arg0
);
11014 tmode
= insn_data
[icode
].operand
[0].mode
;
11015 mode0
= insn_data
[icode
].operand
[1].mode
;
11018 || GET_MODE (target
) != tmode
11019 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11020 target
= gen_reg_rtx (tmode
);
11022 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11023 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11025 pat
= GEN_FCN (icode
) (target
, op0
);
11032 /* Expand the stvx builtins. */
11034 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
11037 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11038 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11040 enum machine_mode mode0
, mode1
;
11042 enum insn_code icode
;
11046 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
11047 icode
= CODE_FOR_vector_altivec_store_v16qi
;
11049 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
11050 icode
= CODE_FOR_vector_altivec_store_v8hi
;
11052 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
11053 icode
= CODE_FOR_vector_altivec_store_v4si
;
11055 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
11056 icode
= CODE_FOR_vector_altivec_store_v4sf
;
11058 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
11059 icode
= CODE_FOR_vector_altivec_store_v2df
;
11061 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
11062 icode
= CODE_FOR_vector_altivec_store_v2di
;
11065 *expandedp
= false;
11069 arg0
= CALL_EXPR_ARG (exp
, 0);
11070 arg1
= CALL_EXPR_ARG (exp
, 1);
11071 op0
= expand_normal (arg0
);
11072 op1
= expand_normal (arg1
);
11073 mode0
= insn_data
[icode
].operand
[0].mode
;
11074 mode1
= insn_data
[icode
].operand
[1].mode
;
11076 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11077 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11078 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11079 op1
= copy_to_mode_reg (mode1
, op1
);
11081 pat
= GEN_FCN (icode
) (op0
, op1
);
11089 /* Expand the dst builtins. */
11091 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
11094 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11095 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11096 tree arg0
, arg1
, arg2
;
11097 enum machine_mode mode0
, mode1
;
11098 rtx pat
, op0
, op1
, op2
;
11099 const struct builtin_description
*d
;
11102 *expandedp
= false;
11104 /* Handle DST variants. */
11106 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
11107 if (d
->code
== fcode
)
11109 arg0
= CALL_EXPR_ARG (exp
, 0);
11110 arg1
= CALL_EXPR_ARG (exp
, 1);
11111 arg2
= CALL_EXPR_ARG (exp
, 2);
11112 op0
= expand_normal (arg0
);
11113 op1
= expand_normal (arg1
);
11114 op2
= expand_normal (arg2
);
11115 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
11116 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
11118 /* Invalid arguments, bail out before generating bad rtl. */
11119 if (arg0
== error_mark_node
11120 || arg1
== error_mark_node
11121 || arg2
== error_mark_node
)
11126 if (TREE_CODE (arg2
) != INTEGER_CST
11127 || TREE_INT_CST_LOW (arg2
) & ~0x3)
11129 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
11133 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
11134 op0
= copy_to_mode_reg (Pmode
, op0
);
11135 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
11136 op1
= copy_to_mode_reg (mode1
, op1
);
11138 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
11148 /* Expand vec_init builtin. */
11150 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
11152 enum machine_mode tmode
= TYPE_MODE (type
);
11153 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
11154 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
11155 rtvec v
= rtvec_alloc (n_elt
);
11157 gcc_assert (VECTOR_MODE_P (tmode
));
11158 gcc_assert (n_elt
== call_expr_nargs (exp
));
11160 for (i
= 0; i
< n_elt
; ++i
)
11162 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
11163 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
11166 if (!target
|| !register_operand (target
, tmode
))
11167 target
= gen_reg_rtx (tmode
);
11169 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
11173 /* Return the integer constant in ARG. Constrain it to be in the range
11174 of the subparts of VEC_TYPE; issue an error if not. */
11177 get_element_number (tree vec_type
, tree arg
)
11179 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
11181 if (!host_integerp (arg
, 1)
11182 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
11184 error ("selector must be an integer constant in the range 0..%wi", max
);
11191 /* Expand vec_set builtin. */
11193 altivec_expand_vec_set_builtin (tree exp
)
11195 enum machine_mode tmode
, mode1
;
11196 tree arg0
, arg1
, arg2
;
11200 arg0
= CALL_EXPR_ARG (exp
, 0);
11201 arg1
= CALL_EXPR_ARG (exp
, 1);
11202 arg2
= CALL_EXPR_ARG (exp
, 2);
11204 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
11205 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
11206 gcc_assert (VECTOR_MODE_P (tmode
));
11208 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
11209 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
11210 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
11212 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
11213 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
11215 op0
= force_reg (tmode
, op0
);
11216 op1
= force_reg (mode1
, op1
);
11218 rs6000_expand_vector_set (op0
, op1
, elt
);
11223 /* Expand vec_ext builtin. */
11225 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
11227 enum machine_mode tmode
, mode0
;
11232 arg0
= CALL_EXPR_ARG (exp
, 0);
11233 arg1
= CALL_EXPR_ARG (exp
, 1);
11235 op0
= expand_normal (arg0
);
11236 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
11238 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
11239 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
11240 gcc_assert (VECTOR_MODE_P (mode0
));
11242 op0
= force_reg (mode0
, op0
);
11244 if (optimize
|| !target
|| !register_operand (target
, tmode
))
11245 target
= gen_reg_rtx (tmode
);
11247 rs6000_expand_vector_extract (target
, op0
, elt
);
11252 /* Expand the builtin in EXP and store the result in TARGET. Store
11253 true in *EXPANDEDP if we found a builtin to expand. */
11255 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
11257 const struct builtin_description
*d
;
11259 enum insn_code icode
;
11260 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11263 enum machine_mode tmode
, mode0
;
11264 enum rs6000_builtins fcode
11265 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11267 if (rs6000_overloaded_builtin_p (fcode
))
11270 error ("unresolved overload for Altivec builtin %qF", fndecl
);
11272 /* Given it is invalid, just generate a normal call. */
11273 return expand_call (exp
, target
, false);
11276 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
11280 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
11284 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
11292 case ALTIVEC_BUILTIN_STVX
:
11293 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
11294 case ALTIVEC_BUILTIN_STVEBX
:
11295 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
11296 case ALTIVEC_BUILTIN_STVEHX
:
11297 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
11298 case ALTIVEC_BUILTIN_STVEWX
:
11299 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
11300 case ALTIVEC_BUILTIN_STVXL
:
11301 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
11303 case ALTIVEC_BUILTIN_STVLX
:
11304 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
11305 case ALTIVEC_BUILTIN_STVLXL
:
11306 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
11307 case ALTIVEC_BUILTIN_STVRX
:
11308 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
11309 case ALTIVEC_BUILTIN_STVRXL
:
11310 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
11312 case VSX_BUILTIN_STXVD2X_V2DF
:
11313 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
11314 case VSX_BUILTIN_STXVD2X_V2DI
:
11315 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
11316 case VSX_BUILTIN_STXVW4X_V4SF
:
11317 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
11318 case VSX_BUILTIN_STXVW4X_V4SI
:
11319 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
11320 case VSX_BUILTIN_STXVW4X_V8HI
:
11321 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
11322 case VSX_BUILTIN_STXVW4X_V16QI
:
11323 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
11325 case ALTIVEC_BUILTIN_MFVSCR
:
11326 icode
= CODE_FOR_altivec_mfvscr
;
11327 tmode
= insn_data
[icode
].operand
[0].mode
;
11330 || GET_MODE (target
) != tmode
11331 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11332 target
= gen_reg_rtx (tmode
);
11334 pat
= GEN_FCN (icode
) (target
);
11340 case ALTIVEC_BUILTIN_MTVSCR
:
11341 icode
= CODE_FOR_altivec_mtvscr
;
11342 arg0
= CALL_EXPR_ARG (exp
, 0);
11343 op0
= expand_normal (arg0
);
11344 mode0
= insn_data
[icode
].operand
[0].mode
;
11346 /* If we got invalid arguments bail out before generating bad rtl. */
11347 if (arg0
== error_mark_node
)
11350 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11351 op0
= copy_to_mode_reg (mode0
, op0
);
11353 pat
= GEN_FCN (icode
) (op0
);
11358 case ALTIVEC_BUILTIN_DSSALL
:
11359 emit_insn (gen_altivec_dssall ());
11362 case ALTIVEC_BUILTIN_DSS
:
11363 icode
= CODE_FOR_altivec_dss
;
11364 arg0
= CALL_EXPR_ARG (exp
, 0);
11366 op0
= expand_normal (arg0
);
11367 mode0
= insn_data
[icode
].operand
[0].mode
;
11369 /* If we got invalid arguments bail out before generating bad rtl. */
11370 if (arg0
== error_mark_node
)
11373 if (TREE_CODE (arg0
) != INTEGER_CST
11374 || TREE_INT_CST_LOW (arg0
) & ~0x3)
11376 error ("argument to dss must be a 2-bit unsigned literal");
11380 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11381 op0
= copy_to_mode_reg (mode0
, op0
);
11383 emit_insn (gen_altivec_dss (op0
));
11386 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
11387 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
11388 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
11389 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
11390 case VSX_BUILTIN_VEC_INIT_V2DF
:
11391 case VSX_BUILTIN_VEC_INIT_V2DI
:
11392 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
11394 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
11395 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
11396 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
11397 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
11398 case VSX_BUILTIN_VEC_SET_V2DF
:
11399 case VSX_BUILTIN_VEC_SET_V2DI
:
11400 return altivec_expand_vec_set_builtin (exp
);
11402 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
11403 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
11404 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
11405 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
11406 case VSX_BUILTIN_VEC_EXT_V2DF
:
11407 case VSX_BUILTIN_VEC_EXT_V2DI
:
11408 return altivec_expand_vec_ext_builtin (exp
, target
);
11412 /* Fall through. */
11415 /* Expand abs* operations. */
11417 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
11418 if (d
->code
== fcode
)
11419 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
11421 /* Expand the AltiVec predicates. */
11422 d
= bdesc_altivec_preds
;
11423 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
11424 if (d
->code
== fcode
)
11425 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
11427 /* LV* are funky. We initialized them differently. */
11430 case ALTIVEC_BUILTIN_LVSL
:
11431 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
11432 exp
, target
, false);
11433 case ALTIVEC_BUILTIN_LVSR
:
11434 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
11435 exp
, target
, false);
11436 case ALTIVEC_BUILTIN_LVEBX
:
11437 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
11438 exp
, target
, false);
11439 case ALTIVEC_BUILTIN_LVEHX
:
11440 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
11441 exp
, target
, false);
11442 case ALTIVEC_BUILTIN_LVEWX
:
11443 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
11444 exp
, target
, false);
11445 case ALTIVEC_BUILTIN_LVXL
:
11446 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
11447 exp
, target
, false);
11448 case ALTIVEC_BUILTIN_LVX
:
11449 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
11450 exp
, target
, false);
11451 case ALTIVEC_BUILTIN_LVLX
:
11452 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
11453 exp
, target
, true);
11454 case ALTIVEC_BUILTIN_LVLXL
:
11455 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
11456 exp
, target
, true);
11457 case ALTIVEC_BUILTIN_LVRX
:
11458 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
11459 exp
, target
, true);
11460 case ALTIVEC_BUILTIN_LVRXL
:
11461 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
11462 exp
, target
, true);
11463 case VSX_BUILTIN_LXVD2X_V2DF
:
11464 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
11465 exp
, target
, false);
11466 case VSX_BUILTIN_LXVD2X_V2DI
:
11467 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
11468 exp
, target
, false);
11469 case VSX_BUILTIN_LXVW4X_V4SF
:
11470 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
11471 exp
, target
, false);
11472 case VSX_BUILTIN_LXVW4X_V4SI
:
11473 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
11474 exp
, target
, false);
11475 case VSX_BUILTIN_LXVW4X_V8HI
:
11476 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
11477 exp
, target
, false);
11478 case VSX_BUILTIN_LXVW4X_V16QI
:
11479 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
11480 exp
, target
, false);
11484 /* Fall through. */
11487 *expandedp
= false;
11491 /* Expand the builtin in EXP and store the result in TARGET. Store
11492 true in *EXPANDEDP if we found a builtin to expand. */
11494 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
11496 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11497 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11498 const struct builtin_description
*d
;
11505 case PAIRED_BUILTIN_STX
:
11506 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
11507 case PAIRED_BUILTIN_LX
:
11508 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
11511 /* Fall through. */
11514 /* Expand the paired predicates. */
11515 d
= bdesc_paired_preds
;
11516 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
11517 if (d
->code
== fcode
)
11518 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
11520 *expandedp
= false;
11524 /* Binops that need to be initialized manually, but can be expanded
11525 automagically by rs6000_expand_binop_builtin. */
11526 static const struct builtin_description bdesc_2arg_spe
[] =
11528 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
11529 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
11530 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
11531 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
11532 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
11533 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
11534 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
11535 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
11536 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
11537 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
11538 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
11539 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
11540 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
11541 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
11542 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
11543 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
11544 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
11545 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
11546 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
11547 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
11548 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
11549 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
11552 /* Expand the builtin in EXP and store the result in TARGET. Store
11553 true in *EXPANDEDP if we found a builtin to expand.
11555 This expands the SPE builtins that are not simple unary and binary
11558 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
11560 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11562 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11563 enum insn_code icode
;
11564 enum machine_mode tmode
, mode0
;
11566 const struct builtin_description
*d
;
11571 /* Syntax check for a 5-bit unsigned immediate. */
11574 case SPE_BUILTIN_EVSTDD
:
11575 case SPE_BUILTIN_EVSTDH
:
11576 case SPE_BUILTIN_EVSTDW
:
11577 case SPE_BUILTIN_EVSTWHE
:
11578 case SPE_BUILTIN_EVSTWHO
:
11579 case SPE_BUILTIN_EVSTWWE
:
11580 case SPE_BUILTIN_EVSTWWO
:
11581 arg1
= CALL_EXPR_ARG (exp
, 2);
11582 if (TREE_CODE (arg1
) != INTEGER_CST
11583 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11585 error ("argument 2 must be a 5-bit unsigned literal");
11593 /* The evsplat*i instructions are not quite generic. */
11596 case SPE_BUILTIN_EVSPLATFI
:
11597 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
11599 case SPE_BUILTIN_EVSPLATI
:
11600 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
11606 d
= bdesc_2arg_spe
;
11607 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
11608 if (d
->code
== fcode
)
11609 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
11611 d
= bdesc_spe_predicates
;
11612 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
11613 if (d
->code
== fcode
)
11614 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
11616 d
= bdesc_spe_evsel
;
11617 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
11618 if (d
->code
== fcode
)
11619 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
11623 case SPE_BUILTIN_EVSTDDX
:
11624 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
11625 case SPE_BUILTIN_EVSTDHX
:
11626 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
11627 case SPE_BUILTIN_EVSTDWX
:
11628 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
11629 case SPE_BUILTIN_EVSTWHEX
:
11630 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
11631 case SPE_BUILTIN_EVSTWHOX
:
11632 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
11633 case SPE_BUILTIN_EVSTWWEX
:
11634 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
11635 case SPE_BUILTIN_EVSTWWOX
:
11636 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
11637 case SPE_BUILTIN_EVSTDD
:
11638 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
11639 case SPE_BUILTIN_EVSTDH
:
11640 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
11641 case SPE_BUILTIN_EVSTDW
:
11642 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
11643 case SPE_BUILTIN_EVSTWHE
:
11644 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
11645 case SPE_BUILTIN_EVSTWHO
:
11646 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
11647 case SPE_BUILTIN_EVSTWWE
:
11648 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
11649 case SPE_BUILTIN_EVSTWWO
:
11650 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
11651 case SPE_BUILTIN_MFSPEFSCR
:
11652 icode
= CODE_FOR_spe_mfspefscr
;
11653 tmode
= insn_data
[icode
].operand
[0].mode
;
11656 || GET_MODE (target
) != tmode
11657 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11658 target
= gen_reg_rtx (tmode
);
11660 pat
= GEN_FCN (icode
) (target
);
11665 case SPE_BUILTIN_MTSPEFSCR
:
11666 icode
= CODE_FOR_spe_mtspefscr
;
11667 arg0
= CALL_EXPR_ARG (exp
, 0);
11668 op0
= expand_normal (arg0
);
11669 mode0
= insn_data
[icode
].operand
[0].mode
;
11671 if (arg0
== error_mark_node
)
11674 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11675 op0
= copy_to_mode_reg (mode0
, op0
);
11677 pat
= GEN_FCN (icode
) (op0
);
11685 *expandedp
= false;
11690 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11692 rtx pat
, scratch
, tmp
;
11693 tree form
= CALL_EXPR_ARG (exp
, 0);
11694 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11695 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11696 rtx op0
= expand_normal (arg0
);
11697 rtx op1
= expand_normal (arg1
);
11698 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11699 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11701 enum rtx_code code
;
11703 if (TREE_CODE (form
) != INTEGER_CST
)
11705 error ("argument 1 of __builtin_paired_predicate must be a constant");
11709 form_int
= TREE_INT_CST_LOW (form
);
11711 gcc_assert (mode0
== mode1
);
11713 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11717 || GET_MODE (target
) != SImode
11718 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11719 target
= gen_reg_rtx (SImode
);
11720 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11721 op0
= copy_to_mode_reg (mode0
, op0
);
11722 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11723 op1
= copy_to_mode_reg (mode1
, op1
);
11725 scratch
= gen_reg_rtx (CCFPmode
);
11727 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11749 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11752 error ("argument 1 of __builtin_paired_predicate is out of range");
11756 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11757 emit_move_insn (target
, tmp
);
11762 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11764 rtx pat
, scratch
, tmp
;
11765 tree form
= CALL_EXPR_ARG (exp
, 0);
11766 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11767 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11768 rtx op0
= expand_normal (arg0
);
11769 rtx op1
= expand_normal (arg1
);
11770 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11771 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11773 enum rtx_code code
;
11775 if (TREE_CODE (form
) != INTEGER_CST
)
11777 error ("argument 1 of __builtin_spe_predicate must be a constant");
11781 form_int
= TREE_INT_CST_LOW (form
);
11783 gcc_assert (mode0
== mode1
);
11785 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11789 || GET_MODE (target
) != SImode
11790 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11791 target
= gen_reg_rtx (SImode
);
11793 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11794 op0
= copy_to_mode_reg (mode0
, op0
);
11795 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11796 op1
= copy_to_mode_reg (mode1
, op1
);
11798 scratch
= gen_reg_rtx (CCmode
);
11800 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11805 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11806 _lower_. We use one compare, but look in different bits of the
11807 CR for each variant.
11809 There are 2 elements in each SPE simd type (upper/lower). The CR
11810 bits are set as follows:
11812 BIT0 | BIT 1 | BIT 2 | BIT 3
11813 U | L | (U | L) | (U & L)
11815 So, for an "all" relationship, BIT 3 would be set.
11816 For an "any" relationship, BIT 2 would be set. Etc.
11818 Following traditional nomenclature, these bits map to:
11820 BIT0 | BIT 1 | BIT 2 | BIT 3
11823 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11828 /* All variant. OV bit. */
11830 /* We need to get to the OV bit, which is the ORDERED bit. We
11831 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11832 that's ugly and will make validate_condition_mode die.
11833 So let's just use another pattern. */
11834 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11836 /* Any variant. EQ bit. */
11840 /* Upper variant. LT bit. */
11844 /* Lower variant. GT bit. */
11849 error ("argument 1 of __builtin_spe_predicate is out of range");
11853 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11854 emit_move_insn (target
, tmp
);
11859 /* The evsel builtins look like this:
11861 e = __builtin_spe_evsel_OP (a, b, c, d);
11863 and work like this:
11865 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11866 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11870 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
11873 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11874 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11875 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11876 tree arg3
= CALL_EXPR_ARG (exp
, 3);
11877 rtx op0
= expand_normal (arg0
);
11878 rtx op1
= expand_normal (arg1
);
11879 rtx op2
= expand_normal (arg2
);
11880 rtx op3
= expand_normal (arg3
);
11881 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11882 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11884 gcc_assert (mode0
== mode1
);
11886 if (arg0
== error_mark_node
|| arg1
== error_mark_node
11887 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
11891 || GET_MODE (target
) != mode0
11892 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
11893 target
= gen_reg_rtx (mode0
);
11895 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11896 op0
= copy_to_mode_reg (mode0
, op0
);
11897 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11898 op1
= copy_to_mode_reg (mode0
, op1
);
11899 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11900 op2
= copy_to_mode_reg (mode0
, op2
);
11901 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
11902 op3
= copy_to_mode_reg (mode0
, op3
);
11904 /* Generate the compare. */
11905 scratch
= gen_reg_rtx (CCmode
);
11906 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11911 if (mode0
== V2SImode
)
11912 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
11914 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
11919 /* Raise an error message for a builtin function that is called without the
11920 appropriate target options being set. */
11923 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
11925 size_t uns_fncode
= (size_t)fncode
;
11926 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
11927 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
11929 gcc_assert (name
!= NULL
);
11930 if ((fnmask
& RS6000_BTM_CELL
) != 0)
11931 error ("Builtin function %s is only valid for the cell processor", name
);
11932 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
11933 error ("Builtin function %s requires the -mvsx option", name
);
11934 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
11935 error ("Builtin function %s requires the -maltivec option", name
);
11936 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
11937 error ("Builtin function %s requires the -mpaired option", name
);
11938 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
11939 error ("Builtin function %s requires the -mspe option", name
);
11941 error ("Builtin function %s is not supported with the current options",
11945 /* Expand an expression EXP that calls a built-in function,
11946 with result going to TARGET if that's convenient
11947 (and in mode MODE if that's convenient).
11948 SUBTARGET may be used as the target for computing one of EXP's operands.
11949 IGNORE is nonzero if the value is to be ignored. */
11952 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
11953 enum machine_mode mode ATTRIBUTE_UNUSED
,
11954 int ignore ATTRIBUTE_UNUSED
)
11956 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11957 enum rs6000_builtins fcode
11958 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
11959 size_t uns_fcode
= (size_t)fcode
;
11960 const struct builtin_description
*d
;
11964 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
11965 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
11967 if (TARGET_DEBUG_BUILTIN
)
11969 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
11970 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
11971 const char *name2
= ((icode
!= CODE_FOR_nothing
)
11972 ? get_insn_name ((int)icode
)
11976 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
11978 default: name3
= "unknown"; break;
11979 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
11980 case RS6000_BTC_UNARY
: name3
= "unary"; break;
11981 case RS6000_BTC_BINARY
: name3
= "binary"; break;
11982 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
11983 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
11984 case RS6000_BTC_ABS
: name3
= "abs"; break;
11985 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
11986 case RS6000_BTC_DST
: name3
= "dst"; break;
11991 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11992 (name1
) ? name1
: "---", fcode
,
11993 (name2
) ? name2
: "---", (int)icode
,
11995 func_valid_p
? "" : ", not valid");
12000 rs6000_invalid_builtin (fcode
);
12002 /* Given it is invalid, just generate a normal call. */
12003 return expand_call (exp
, target
, ignore
);
12008 case RS6000_BUILTIN_RECIP
:
12009 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
12011 case RS6000_BUILTIN_RECIPF
:
12012 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
12014 case RS6000_BUILTIN_RSQRTF
:
12015 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
12017 case RS6000_BUILTIN_RSQRT
:
12018 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
12020 case POWER7_BUILTIN_BPERMD
:
12021 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
12022 ? CODE_FOR_bpermd_di
12023 : CODE_FOR_bpermd_si
), exp
, target
);
12025 case RS6000_BUILTIN_GET_TB
:
12026 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
12029 case RS6000_BUILTIN_MFTB
:
12030 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
12031 ? CODE_FOR_rs6000_mftb_di
12032 : CODE_FOR_rs6000_mftb_si
),
12035 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
12036 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
12038 int icode
= (int) CODE_FOR_altivec_lvsr
;
12039 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12040 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
12044 gcc_assert (TARGET_ALTIVEC
);
12046 arg
= CALL_EXPR_ARG (exp
, 0);
12047 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
12048 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
12049 addr
= memory_address (mode
, op
);
12050 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
12054 /* For the load case need to negate the address. */
12055 op
= gen_reg_rtx (GET_MODE (addr
));
12056 emit_insn (gen_rtx_SET (VOIDmode
, op
,
12057 gen_rtx_NEG (GET_MODE (addr
), addr
)));
12059 op
= gen_rtx_MEM (mode
, op
);
12062 || GET_MODE (target
) != tmode
12063 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12064 target
= gen_reg_rtx (tmode
);
12066 /*pat = gen_altivec_lvsr (target, op);*/
12067 pat
= GEN_FCN (icode
) (target
, op
);
12075 case ALTIVEC_BUILTIN_VCFUX
:
12076 case ALTIVEC_BUILTIN_VCFSX
:
12077 case ALTIVEC_BUILTIN_VCTUXS
:
12078 case ALTIVEC_BUILTIN_VCTSXS
:
12079 /* FIXME: There's got to be a nicer way to handle this case than
12080 constructing a new CALL_EXPR. */
12081 if (call_expr_nargs (exp
) == 1)
12083 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
12084 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
12092 if (TARGET_ALTIVEC
)
12094 ret
= altivec_expand_builtin (exp
, target
, &success
);
12101 ret
= spe_expand_builtin (exp
, target
, &success
);
12106 if (TARGET_PAIRED_FLOAT
)
12108 ret
= paired_expand_builtin (exp
, target
, &success
);
12114 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
12116 /* Handle simple unary operations. */
12118 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12119 if (d
->code
== fcode
)
12120 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
12122 /* Handle simple binary operations. */
12124 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12125 if (d
->code
== fcode
)
12126 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
12128 /* Handle simple ternary operations. */
12130 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
12131 if (d
->code
== fcode
)
12132 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
12134 gcc_unreachable ();
12138 rs6000_init_builtins (void)
12142 enum machine_mode mode
;
12144 if (TARGET_DEBUG_BUILTIN
)
12145 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
12146 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
12147 (TARGET_SPE
) ? ", spe" : "",
12148 (TARGET_ALTIVEC
) ? ", altivec" : "",
12149 (TARGET_VSX
) ? ", vsx" : "");
12151 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
12152 V2SF_type_node
= build_vector_type (float_type_node
, 2);
12153 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
12154 V2DF_type_node
= build_vector_type (double_type_node
, 2);
12155 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
12156 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
12157 V4SF_type_node
= build_vector_type (float_type_node
, 4);
12158 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
12159 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
12161 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
12162 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
12163 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
12164 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
12166 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
12167 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
12168 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
12169 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
12171 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
12172 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
12173 'vector unsigned short'. */
12175 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
12176 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
12177 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
12178 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
12179 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
12181 long_integer_type_internal_node
= long_integer_type_node
;
12182 long_unsigned_type_internal_node
= long_unsigned_type_node
;
12183 long_long_integer_type_internal_node
= long_long_integer_type_node
;
12184 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
12185 intQI_type_internal_node
= intQI_type_node
;
12186 uintQI_type_internal_node
= unsigned_intQI_type_node
;
12187 intHI_type_internal_node
= intHI_type_node
;
12188 uintHI_type_internal_node
= unsigned_intHI_type_node
;
12189 intSI_type_internal_node
= intSI_type_node
;
12190 uintSI_type_internal_node
= unsigned_intSI_type_node
;
12191 intDI_type_internal_node
= intDI_type_node
;
12192 uintDI_type_internal_node
= unsigned_intDI_type_node
;
12193 float_type_internal_node
= float_type_node
;
12194 double_type_internal_node
= double_type_node
;
12195 void_type_internal_node
= void_type_node
;
12197 /* Initialize the modes for builtin_function_type, mapping a machine mode to
12199 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
12200 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
12201 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
12202 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
12203 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
12204 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
12205 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
12206 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
12207 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
12208 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
12209 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
12210 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
12211 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
12212 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
12213 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
12214 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
12215 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
12216 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
12217 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
12218 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
12219 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
12221 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
12222 TYPE_NAME (bool_char_type_node
) = tdecl
;
12224 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
12225 TYPE_NAME (bool_short_type_node
) = tdecl
;
12227 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
12228 TYPE_NAME (bool_int_type_node
) = tdecl
;
12230 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
12231 TYPE_NAME (pixel_type_node
) = tdecl
;
12233 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
12234 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
12235 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
12236 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
12237 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
12239 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
12240 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
12242 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
12243 TYPE_NAME (V16QI_type_node
) = tdecl
;
12245 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
12246 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
12248 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
12249 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
12251 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
12252 TYPE_NAME (V8HI_type_node
) = tdecl
;
12254 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
12255 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
12257 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
12258 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
12260 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
12261 TYPE_NAME (V4SI_type_node
) = tdecl
;
12263 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
12264 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
12266 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
12267 TYPE_NAME (V4SF_type_node
) = tdecl
;
12269 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
12270 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
12272 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
12273 TYPE_NAME (V2DF_type_node
) = tdecl
;
12275 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
12276 TYPE_NAME (V2DI_type_node
) = tdecl
;
12278 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
12279 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
12281 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
12282 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
12284 /* Paired and SPE builtins are only available if you build a compiler with
12285 the appropriate options, so only create those builtins with the
12286 appropriate compiler option. Create Altivec and VSX builtins on machines
12287 with at least the general purpose extensions (970 and newer) to allow the
12288 use of the target attribute. */
12289 if (TARGET_PAIRED_FLOAT
)
12290 paired_init_builtins ();
12292 spe_init_builtins ();
12293 if (TARGET_EXTRA_BUILTINS
)
12294 altivec_init_builtins ();
12295 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
12296 rs6000_common_init_builtins ();
12298 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
12299 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
12300 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
12302 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
12303 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
12304 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
12306 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
12307 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
12308 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
12310 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
12311 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
12312 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
12314 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
12315 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
12316 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
12317 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
12319 ftype
= build_function_type_list (unsigned_intDI_type_node
,
12321 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
12324 ftype
= build_function_type_list (unsigned_intDI_type_node
,
12327 ftype
= build_function_type_list (unsigned_intSI_type_node
,
12329 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
12332 /* AIX libm provides clog as __clog. */
12333 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
12334 set_user_assembler_name (tdecl
, "__clog");
12337 #ifdef SUBTARGET_INIT_BUILTINS
12338 SUBTARGET_INIT_BUILTINS
;
12342 /* Returns the rs6000 builtin decl for CODE. */
12345 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
12347 HOST_WIDE_INT fnmask
;
12349 if (code
>= RS6000_BUILTIN_COUNT
)
12350 return error_mark_node
;
12352 fnmask
= rs6000_builtin_info
[code
].mask
;
12353 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
12355 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
12356 return error_mark_node
;
12359 return rs6000_builtin_decls
[code
];
12363 spe_init_builtins (void)
12365 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
12366 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
12367 const struct builtin_description
*d
;
12370 tree v2si_ftype_4_v2si
12371 = build_function_type_list (opaque_V2SI_type_node
,
12372 opaque_V2SI_type_node
,
12373 opaque_V2SI_type_node
,
12374 opaque_V2SI_type_node
,
12375 opaque_V2SI_type_node
,
12378 tree v2sf_ftype_4_v2sf
12379 = build_function_type_list (opaque_V2SF_type_node
,
12380 opaque_V2SF_type_node
,
12381 opaque_V2SF_type_node
,
12382 opaque_V2SF_type_node
,
12383 opaque_V2SF_type_node
,
12386 tree int_ftype_int_v2si_v2si
12387 = build_function_type_list (integer_type_node
,
12389 opaque_V2SI_type_node
,
12390 opaque_V2SI_type_node
,
12393 tree int_ftype_int_v2sf_v2sf
12394 = build_function_type_list (integer_type_node
,
12396 opaque_V2SF_type_node
,
12397 opaque_V2SF_type_node
,
12400 tree void_ftype_v2si_puint_int
12401 = build_function_type_list (void_type_node
,
12402 opaque_V2SI_type_node
,
12407 tree void_ftype_v2si_puint_char
12408 = build_function_type_list (void_type_node
,
12409 opaque_V2SI_type_node
,
12414 tree void_ftype_v2si_pv2si_int
12415 = build_function_type_list (void_type_node
,
12416 opaque_V2SI_type_node
,
12417 opaque_p_V2SI_type_node
,
12421 tree void_ftype_v2si_pv2si_char
12422 = build_function_type_list (void_type_node
,
12423 opaque_V2SI_type_node
,
12424 opaque_p_V2SI_type_node
,
12428 tree void_ftype_int
12429 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
12431 tree int_ftype_void
12432 = build_function_type_list (integer_type_node
, NULL_TREE
);
12434 tree v2si_ftype_pv2si_int
12435 = build_function_type_list (opaque_V2SI_type_node
,
12436 opaque_p_V2SI_type_node
,
12440 tree v2si_ftype_puint_int
12441 = build_function_type_list (opaque_V2SI_type_node
,
12446 tree v2si_ftype_pushort_int
12447 = build_function_type_list (opaque_V2SI_type_node
,
12452 tree v2si_ftype_signed_char
12453 = build_function_type_list (opaque_V2SI_type_node
,
12454 signed_char_type_node
,
12457 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
12459 /* Initialize irregular SPE builtins. */
12461 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
12462 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
12463 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
12464 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
12465 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
12466 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
12467 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
12468 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
12469 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
12470 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
12471 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
12472 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
12473 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
12474 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
12475 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
12476 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
12477 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
12478 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
12481 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
12482 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
12483 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
12484 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
12485 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
12486 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
12487 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
12488 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
12489 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
12490 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
12491 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
12492 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
12493 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
12494 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
12495 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
12496 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
12497 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
12498 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
12499 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
12500 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
12501 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
12502 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
12505 d
= bdesc_spe_predicates
;
12506 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
12510 switch (insn_data
[d
->icode
].operand
[1].mode
)
12513 type
= int_ftype_int_v2si_v2si
;
12516 type
= int_ftype_int_v2sf_v2sf
;
12519 gcc_unreachable ();
12522 def_builtin (d
->name
, type
, d
->code
);
12525 /* Evsel predicates. */
12526 d
= bdesc_spe_evsel
;
12527 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
12531 switch (insn_data
[d
->icode
].operand
[1].mode
)
12534 type
= v2si_ftype_4_v2si
;
12537 type
= v2sf_ftype_4_v2sf
;
12540 gcc_unreachable ();
12543 def_builtin (d
->name
, type
, d
->code
);
12548 paired_init_builtins (void)
12550 const struct builtin_description
*d
;
12553 tree int_ftype_int_v2sf_v2sf
12554 = build_function_type_list (integer_type_node
,
12559 tree pcfloat_type_node
=
12560 build_pointer_type (build_qualified_type
12561 (float_type_node
, TYPE_QUAL_CONST
));
12563 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
12564 long_integer_type_node
,
12567 tree void_ftype_v2sf_long_pcfloat
=
12568 build_function_type_list (void_type_node
,
12570 long_integer_type_node
,
12575 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
12576 PAIRED_BUILTIN_LX
);
12579 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
12580 PAIRED_BUILTIN_STX
);
12583 d
= bdesc_paired_preds
;
12584 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
12588 if (TARGET_DEBUG_BUILTIN
)
12589 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
12590 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
12591 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
12593 switch (insn_data
[d
->icode
].operand
[1].mode
)
12596 type
= int_ftype_int_v2sf_v2sf
;
12599 gcc_unreachable ();
12602 def_builtin (d
->name
, type
, d
->code
);
12607 altivec_init_builtins (void)
12609 const struct builtin_description
*d
;
12614 tree pvoid_type_node
= build_pointer_type (void_type_node
);
12616 tree pcvoid_type_node
12617 = build_pointer_type (build_qualified_type (void_type_node
,
12620 tree int_ftype_opaque
12621 = build_function_type_list (integer_type_node
,
12622 opaque_V4SI_type_node
, NULL_TREE
);
12623 tree opaque_ftype_opaque
12624 = build_function_type_list (integer_type_node
, NULL_TREE
);
12625 tree opaque_ftype_opaque_int
12626 = build_function_type_list (opaque_V4SI_type_node
,
12627 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
12628 tree opaque_ftype_opaque_opaque_int
12629 = build_function_type_list (opaque_V4SI_type_node
,
12630 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
12631 integer_type_node
, NULL_TREE
);
12632 tree int_ftype_int_opaque_opaque
12633 = build_function_type_list (integer_type_node
,
12634 integer_type_node
, opaque_V4SI_type_node
,
12635 opaque_V4SI_type_node
, NULL_TREE
);
12636 tree int_ftype_int_v4si_v4si
12637 = build_function_type_list (integer_type_node
,
12638 integer_type_node
, V4SI_type_node
,
12639 V4SI_type_node
, NULL_TREE
);
12640 tree int_ftype_int_v2di_v2di
12641 = build_function_type_list (integer_type_node
,
12642 integer_type_node
, V2DI_type_node
,
12643 V2DI_type_node
, NULL_TREE
);
12644 tree void_ftype_v4si
12645 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
12646 tree v8hi_ftype_void
12647 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
12648 tree void_ftype_void
12649 = build_function_type_list (void_type_node
, NULL_TREE
);
12650 tree void_ftype_int
12651 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
12653 tree opaque_ftype_long_pcvoid
12654 = build_function_type_list (opaque_V4SI_type_node
,
12655 long_integer_type_node
, pcvoid_type_node
,
12657 tree v16qi_ftype_long_pcvoid
12658 = build_function_type_list (V16QI_type_node
,
12659 long_integer_type_node
, pcvoid_type_node
,
12661 tree v8hi_ftype_long_pcvoid
12662 = build_function_type_list (V8HI_type_node
,
12663 long_integer_type_node
, pcvoid_type_node
,
12665 tree v4si_ftype_long_pcvoid
12666 = build_function_type_list (V4SI_type_node
,
12667 long_integer_type_node
, pcvoid_type_node
,
12669 tree v4sf_ftype_long_pcvoid
12670 = build_function_type_list (V4SF_type_node
,
12671 long_integer_type_node
, pcvoid_type_node
,
12673 tree v2df_ftype_long_pcvoid
12674 = build_function_type_list (V2DF_type_node
,
12675 long_integer_type_node
, pcvoid_type_node
,
12677 tree v2di_ftype_long_pcvoid
12678 = build_function_type_list (V2DI_type_node
,
12679 long_integer_type_node
, pcvoid_type_node
,
12682 tree void_ftype_opaque_long_pvoid
12683 = build_function_type_list (void_type_node
,
12684 opaque_V4SI_type_node
, long_integer_type_node
,
12685 pvoid_type_node
, NULL_TREE
);
12686 tree void_ftype_v4si_long_pvoid
12687 = build_function_type_list (void_type_node
,
12688 V4SI_type_node
, long_integer_type_node
,
12689 pvoid_type_node
, NULL_TREE
);
12690 tree void_ftype_v16qi_long_pvoid
12691 = build_function_type_list (void_type_node
,
12692 V16QI_type_node
, long_integer_type_node
,
12693 pvoid_type_node
, NULL_TREE
);
12694 tree void_ftype_v8hi_long_pvoid
12695 = build_function_type_list (void_type_node
,
12696 V8HI_type_node
, long_integer_type_node
,
12697 pvoid_type_node
, NULL_TREE
);
12698 tree void_ftype_v4sf_long_pvoid
12699 = build_function_type_list (void_type_node
,
12700 V4SF_type_node
, long_integer_type_node
,
12701 pvoid_type_node
, NULL_TREE
);
12702 tree void_ftype_v2df_long_pvoid
12703 = build_function_type_list (void_type_node
,
12704 V2DF_type_node
, long_integer_type_node
,
12705 pvoid_type_node
, NULL_TREE
);
12706 tree void_ftype_v2di_long_pvoid
12707 = build_function_type_list (void_type_node
,
12708 V2DI_type_node
, long_integer_type_node
,
12709 pvoid_type_node
, NULL_TREE
);
12710 tree int_ftype_int_v8hi_v8hi
12711 = build_function_type_list (integer_type_node
,
12712 integer_type_node
, V8HI_type_node
,
12713 V8HI_type_node
, NULL_TREE
);
12714 tree int_ftype_int_v16qi_v16qi
12715 = build_function_type_list (integer_type_node
,
12716 integer_type_node
, V16QI_type_node
,
12717 V16QI_type_node
, NULL_TREE
);
12718 tree int_ftype_int_v4sf_v4sf
12719 = build_function_type_list (integer_type_node
,
12720 integer_type_node
, V4SF_type_node
,
12721 V4SF_type_node
, NULL_TREE
);
12722 tree int_ftype_int_v2df_v2df
12723 = build_function_type_list (integer_type_node
,
12724 integer_type_node
, V2DF_type_node
,
12725 V2DF_type_node
, NULL_TREE
);
12726 tree v2di_ftype_v2di
12727 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
12728 tree v4si_ftype_v4si
12729 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12730 tree v8hi_ftype_v8hi
12731 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12732 tree v16qi_ftype_v16qi
12733 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12734 tree v4sf_ftype_v4sf
12735 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12736 tree v2df_ftype_v2df
12737 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12738 tree void_ftype_pcvoid_int_int
12739 = build_function_type_list (void_type_node
,
12740 pcvoid_type_node
, integer_type_node
,
12741 integer_type_node
, NULL_TREE
);
12743 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
12744 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
12745 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
12746 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
12747 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
12748 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
12749 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
12750 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
12751 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
12752 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
12753 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
12754 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
12755 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
12756 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
12757 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
12758 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
12759 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
12760 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
12761 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
12762 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
12763 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
12764 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
12765 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
12766 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
12767 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
12768 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
12769 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
12770 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
12771 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
12772 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
12774 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
12775 VSX_BUILTIN_LXVD2X_V2DF
);
12776 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
12777 VSX_BUILTIN_LXVD2X_V2DI
);
12778 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
12779 VSX_BUILTIN_LXVW4X_V4SF
);
12780 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
12781 VSX_BUILTIN_LXVW4X_V4SI
);
12782 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
12783 VSX_BUILTIN_LXVW4X_V8HI
);
12784 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
12785 VSX_BUILTIN_LXVW4X_V16QI
);
12786 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
12787 VSX_BUILTIN_STXVD2X_V2DF
);
12788 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
12789 VSX_BUILTIN_STXVD2X_V2DI
);
12790 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
12791 VSX_BUILTIN_STXVW4X_V4SF
);
12792 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
12793 VSX_BUILTIN_STXVW4X_V4SI
);
12794 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
12795 VSX_BUILTIN_STXVW4X_V8HI
);
12796 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
12797 VSX_BUILTIN_STXVW4X_V16QI
);
12798 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
12799 VSX_BUILTIN_VEC_LD
);
12800 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
12801 VSX_BUILTIN_VEC_ST
);
12803 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
12804 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
12805 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
12807 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
12808 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
12809 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
12810 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
12811 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
12812 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
12813 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
12814 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
12815 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
12816 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
12817 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
12818 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
12820 /* Cell builtins. */
12821 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
12822 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
12823 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
12824 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
12826 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
12827 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
12828 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
12829 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
12831 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
12832 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
12833 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
12834 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
12836 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
12837 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
12838 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
12839 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
12841 /* Add the DST variants. */
12843 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12844 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
12846 /* Initialize the predicates. */
12847 d
= bdesc_altivec_preds
;
12848 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12850 enum machine_mode mode1
;
12853 if (rs6000_overloaded_builtin_p (d
->code
))
12856 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12861 type
= int_ftype_int_opaque_opaque
;
12864 type
= int_ftype_int_v2di_v2di
;
12867 type
= int_ftype_int_v4si_v4si
;
12870 type
= int_ftype_int_v8hi_v8hi
;
12873 type
= int_ftype_int_v16qi_v16qi
;
12876 type
= int_ftype_int_v4sf_v4sf
;
12879 type
= int_ftype_int_v2df_v2df
;
12882 gcc_unreachable ();
12885 def_builtin (d
->name
, type
, d
->code
);
12888 /* Initialize the abs* operators. */
12890 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12892 enum machine_mode mode0
;
12895 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12900 type
= v2di_ftype_v2di
;
12903 type
= v4si_ftype_v4si
;
12906 type
= v8hi_ftype_v8hi
;
12909 type
= v16qi_ftype_v16qi
;
12912 type
= v4sf_ftype_v4sf
;
12915 type
= v2df_ftype_v2df
;
12918 gcc_unreachable ();
12921 def_builtin (d
->name
, type
, d
->code
);
12924 /* Initialize target builtin that implements
12925 targetm.vectorize.builtin_mask_for_load. */
12927 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
12928 v16qi_ftype_long_pcvoid
,
12929 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
12930 BUILT_IN_MD
, NULL
, NULL_TREE
);
12931 TREE_READONLY (decl
) = 1;
12932 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12933 altivec_builtin_mask_for_load
= decl
;
12935 /* Access to the vec_init patterns. */
12936 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
12937 integer_type_node
, integer_type_node
,
12938 integer_type_node
, NULL_TREE
);
12939 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
12941 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
12942 short_integer_type_node
,
12943 short_integer_type_node
,
12944 short_integer_type_node
,
12945 short_integer_type_node
,
12946 short_integer_type_node
,
12947 short_integer_type_node
,
12948 short_integer_type_node
, NULL_TREE
);
12949 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
12951 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
12952 char_type_node
, char_type_node
,
12953 char_type_node
, char_type_node
,
12954 char_type_node
, char_type_node
,
12955 char_type_node
, char_type_node
,
12956 char_type_node
, char_type_node
,
12957 char_type_node
, char_type_node
,
12958 char_type_node
, char_type_node
,
12959 char_type_node
, NULL_TREE
);
12960 def_builtin ("__builtin_vec_init_v16qi", ftype
,
12961 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
12963 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
12964 float_type_node
, float_type_node
,
12965 float_type_node
, NULL_TREE
);
12966 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
12968 /* VSX builtins. */
12969 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
12970 double_type_node
, NULL_TREE
);
12971 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
12973 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
12974 intDI_type_node
, NULL_TREE
);
12975 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
12977 /* Access to the vec_set patterns. */
12978 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
12980 integer_type_node
, NULL_TREE
);
12981 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
12983 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
12985 integer_type_node
, NULL_TREE
);
12986 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
12988 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
12990 integer_type_node
, NULL_TREE
);
12991 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
12993 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
12995 integer_type_node
, NULL_TREE
);
12996 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
12998 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
13000 integer_type_node
, NULL_TREE
);
13001 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
13003 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
13005 integer_type_node
, NULL_TREE
);
13006 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
13008 /* Access to the vec_extract patterns. */
13009 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
13010 integer_type_node
, NULL_TREE
);
13011 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
13013 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
13014 integer_type_node
, NULL_TREE
);
13015 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
13017 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
13018 integer_type_node
, NULL_TREE
);
13019 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
13021 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
13022 integer_type_node
, NULL_TREE
);
13023 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
13025 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
13026 integer_type_node
, NULL_TREE
);
13027 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
13029 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
13030 integer_type_node
, NULL_TREE
);
13031 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
13034 /* Hash function for builtin functions with up to 3 arguments and a return
13037 builtin_hash_function (const void *hash_entry
)
13041 const struct builtin_hash_struct
*bh
=
13042 (const struct builtin_hash_struct
*) hash_entry
;
13044 for (i
= 0; i
< 4; i
++)
13046 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
13047 ret
= (ret
* 2) + bh
->uns_p
[i
];
13053 /* Compare builtin hash entries H1 and H2 for equivalence. */
13055 builtin_hash_eq (const void *h1
, const void *h2
)
13057 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
13058 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
13060 return ((p1
->mode
[0] == p2
->mode
[0])
13061 && (p1
->mode
[1] == p2
->mode
[1])
13062 && (p1
->mode
[2] == p2
->mode
[2])
13063 && (p1
->mode
[3] == p2
->mode
[3])
13064 && (p1
->uns_p
[0] == p2
->uns_p
[0])
13065 && (p1
->uns_p
[1] == p2
->uns_p
[1])
13066 && (p1
->uns_p
[2] == p2
->uns_p
[2])
13067 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
13070 /* Map types for builtin functions with an explicit return type and up to 3
13071 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
13072 of the argument. */
13074 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
13075 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
13076 enum rs6000_builtins builtin
, const char *name
)
13078 struct builtin_hash_struct h
;
13079 struct builtin_hash_struct
*h2
;
13083 tree ret_type
= NULL_TREE
;
13084 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
13086 /* Create builtin_hash_table. */
13087 if (builtin_hash_table
== NULL
)
13088 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
13089 builtin_hash_eq
, NULL
);
13091 h
.type
= NULL_TREE
;
13092 h
.mode
[0] = mode_ret
;
13093 h
.mode
[1] = mode_arg0
;
13094 h
.mode
[2] = mode_arg1
;
13095 h
.mode
[3] = mode_arg2
;
13101 /* If the builtin is a type that produces unsigned results or takes unsigned
13102 arguments, and it is returned as a decl for the vectorizer (such as
13103 widening multiplies, permute), make sure the arguments and return value
13104 are type correct. */
13107 /* unsigned 1 argument functions. */
13108 case CRYPTO_BUILTIN_VSBOX
:
13109 case P8V_BUILTIN_VGBBD
:
13114 /* unsigned 2 argument functions. */
13115 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
13116 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
13117 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
13118 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
13119 case CRYPTO_BUILTIN_VCIPHER
:
13120 case CRYPTO_BUILTIN_VCIPHERLAST
:
13121 case CRYPTO_BUILTIN_VNCIPHER
:
13122 case CRYPTO_BUILTIN_VNCIPHERLAST
:
13123 case CRYPTO_BUILTIN_VPMSUMB
:
13124 case CRYPTO_BUILTIN_VPMSUMH
:
13125 case CRYPTO_BUILTIN_VPMSUMW
:
13126 case CRYPTO_BUILTIN_VPMSUMD
:
13127 case CRYPTO_BUILTIN_VPMSUM
:
13133 /* unsigned 3 argument functions. */
13134 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
13135 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
13136 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
13137 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
13138 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
13139 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
13140 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
13141 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
13142 case VSX_BUILTIN_VPERM_16QI_UNS
:
13143 case VSX_BUILTIN_VPERM_8HI_UNS
:
13144 case VSX_BUILTIN_VPERM_4SI_UNS
:
13145 case VSX_BUILTIN_VPERM_2DI_UNS
:
13146 case VSX_BUILTIN_XXSEL_16QI_UNS
:
13147 case VSX_BUILTIN_XXSEL_8HI_UNS
:
13148 case VSX_BUILTIN_XXSEL_4SI_UNS
:
13149 case VSX_BUILTIN_XXSEL_2DI_UNS
:
13150 case CRYPTO_BUILTIN_VPERMXOR
:
13151 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
13152 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
13153 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
13154 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
13155 case CRYPTO_BUILTIN_VSHASIGMAW
:
13156 case CRYPTO_BUILTIN_VSHASIGMAD
:
13157 case CRYPTO_BUILTIN_VSHASIGMA
:
13164 /* signed permute functions with unsigned char mask. */
13165 case ALTIVEC_BUILTIN_VPERM_16QI
:
13166 case ALTIVEC_BUILTIN_VPERM_8HI
:
13167 case ALTIVEC_BUILTIN_VPERM_4SI
:
13168 case ALTIVEC_BUILTIN_VPERM_4SF
:
13169 case ALTIVEC_BUILTIN_VPERM_2DI
:
13170 case ALTIVEC_BUILTIN_VPERM_2DF
:
13171 case VSX_BUILTIN_VPERM_16QI
:
13172 case VSX_BUILTIN_VPERM_8HI
:
13173 case VSX_BUILTIN_VPERM_4SI
:
13174 case VSX_BUILTIN_VPERM_4SF
:
13175 case VSX_BUILTIN_VPERM_2DI
:
13176 case VSX_BUILTIN_VPERM_2DF
:
13180 /* unsigned args, signed return. */
13181 case VSX_BUILTIN_XVCVUXDDP_UNS
:
13182 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
13186 /* signed args, unsigned return. */
13187 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
13188 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
13196 /* Figure out how many args are present. */
13197 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
13201 fatal_error ("internal error: builtin function %s had no type", name
);
13203 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
13204 if (!ret_type
&& h
.uns_p
[0])
13205 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
13208 fatal_error ("internal error: builtin function %s had an unexpected "
13209 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
13211 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
13212 arg_type
[i
] = NULL_TREE
;
13214 for (i
= 0; i
< num_args
; i
++)
13216 int m
= (int) h
.mode
[i
+1];
13217 int uns_p
= h
.uns_p
[i
+1];
13219 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
13220 if (!arg_type
[i
] && uns_p
)
13221 arg_type
[i
] = builtin_mode_to_type
[m
][0];
13224 fatal_error ("internal error: builtin function %s, argument %d "
13225 "had unexpected argument type %s", name
, i
,
13226 GET_MODE_NAME (m
));
13229 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
13230 if (*found
== NULL
)
13232 h2
= ggc_alloc_builtin_hash_struct ();
13234 *found
= (void *)h2
;
13236 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
13237 arg_type
[2], NULL_TREE
);
13240 return ((struct builtin_hash_struct
*)(*found
))->type
;
13244 rs6000_common_init_builtins (void)
13246 const struct builtin_description
*d
;
13249 tree opaque_ftype_opaque
= NULL_TREE
;
13250 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
13251 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
13252 tree v2si_ftype_qi
= NULL_TREE
;
13253 tree v2si_ftype_v2si_qi
= NULL_TREE
;
13254 tree v2si_ftype_int_qi
= NULL_TREE
;
13255 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
13257 if (!TARGET_PAIRED_FLOAT
)
13259 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
13260 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
13263 /* Paired and SPE builtins are only available if you build a compiler with
13264 the appropriate options, so only create those builtins with the
13265 appropriate compiler option. Create Altivec and VSX builtins on machines
13266 with at least the general purpose extensions (970 and newer) to allow the
13267 use of the target attribute.. */
13269 if (TARGET_EXTRA_BUILTINS
)
13270 builtin_mask
|= RS6000_BTM_COMMON
;
13272 /* Add the ternary operators. */
13274 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13277 HOST_WIDE_INT mask
= d
->mask
;
13279 if ((mask
& builtin_mask
) != mask
)
13281 if (TARGET_DEBUG_BUILTIN
)
13282 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
13286 if (rs6000_overloaded_builtin_p (d
->code
))
13288 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
13289 type
= opaque_ftype_opaque_opaque_opaque
13290 = build_function_type_list (opaque_V4SI_type_node
,
13291 opaque_V4SI_type_node
,
13292 opaque_V4SI_type_node
,
13293 opaque_V4SI_type_node
,
13298 enum insn_code icode
= d
->icode
;
13301 if (TARGET_DEBUG_BUILTIN
)
13302 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
13308 if (icode
== CODE_FOR_nothing
)
13310 if (TARGET_DEBUG_BUILTIN
)
13311 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
13317 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
13318 insn_data
[icode
].operand
[1].mode
,
13319 insn_data
[icode
].operand
[2].mode
,
13320 insn_data
[icode
].operand
[3].mode
,
13324 def_builtin (d
->name
, type
, d
->code
);
13327 /* Add the binary operators. */
13329 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13331 enum machine_mode mode0
, mode1
, mode2
;
13333 HOST_WIDE_INT mask
= d
->mask
;
13335 if ((mask
& builtin_mask
) != mask
)
13337 if (TARGET_DEBUG_BUILTIN
)
13338 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
13342 if (rs6000_overloaded_builtin_p (d
->code
))
13344 if (! (type
= opaque_ftype_opaque_opaque
))
13345 type
= opaque_ftype_opaque_opaque
13346 = build_function_type_list (opaque_V4SI_type_node
,
13347 opaque_V4SI_type_node
,
13348 opaque_V4SI_type_node
,
13353 enum insn_code icode
= d
->icode
;
13356 if (TARGET_DEBUG_BUILTIN
)
13357 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
13363 if (icode
== CODE_FOR_nothing
)
13365 if (TARGET_DEBUG_BUILTIN
)
13366 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
13372 mode0
= insn_data
[icode
].operand
[0].mode
;
13373 mode1
= insn_data
[icode
].operand
[1].mode
;
13374 mode2
= insn_data
[icode
].operand
[2].mode
;
13376 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
13378 if (! (type
= v2si_ftype_v2si_qi
))
13379 type
= v2si_ftype_v2si_qi
13380 = build_function_type_list (opaque_V2SI_type_node
,
13381 opaque_V2SI_type_node
,
13386 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
13387 && mode2
== QImode
)
13389 if (! (type
= v2si_ftype_int_qi
))
13390 type
= v2si_ftype_int_qi
13391 = build_function_type_list (opaque_V2SI_type_node
,
13398 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
13402 def_builtin (d
->name
, type
, d
->code
);
13405 /* Add the simple unary operators. */
13407 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13409 enum machine_mode mode0
, mode1
;
13411 HOST_WIDE_INT mask
= d
->mask
;
13413 if ((mask
& builtin_mask
) != mask
)
13415 if (TARGET_DEBUG_BUILTIN
)
13416 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
13420 if (rs6000_overloaded_builtin_p (d
->code
))
13422 if (! (type
= opaque_ftype_opaque
))
13423 type
= opaque_ftype_opaque
13424 = build_function_type_list (opaque_V4SI_type_node
,
13425 opaque_V4SI_type_node
,
13430 enum insn_code icode
= d
->icode
;
13433 if (TARGET_DEBUG_BUILTIN
)
13434 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
13440 if (icode
== CODE_FOR_nothing
)
13442 if (TARGET_DEBUG_BUILTIN
)
13443 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
13449 mode0
= insn_data
[icode
].operand
[0].mode
;
13450 mode1
= insn_data
[icode
].operand
[1].mode
;
13452 if (mode0
== V2SImode
&& mode1
== QImode
)
13454 if (! (type
= v2si_ftype_qi
))
13455 type
= v2si_ftype_qi
13456 = build_function_type_list (opaque_V2SI_type_node
,
13462 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
13466 def_builtin (d
->name
, type
, d
->code
);
13471 rs6000_init_libfuncs (void)
13473 if (!TARGET_IEEEQUAD
)
13474 /* AIX/Darwin/64-bit Linux quad floating point routines. */
13475 if (!TARGET_XL_COMPAT
)
13477 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
13478 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
13479 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
13480 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
13482 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
13484 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
13485 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
13486 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
13487 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
13488 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
13489 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
13490 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
13492 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
13493 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
13494 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
13495 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
13496 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
13497 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
13498 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
13499 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
13502 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
13503 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
13507 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
13508 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
13509 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
13510 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
13514 /* 32-bit SVR4 quad floating point routines. */
13516 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
13517 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
13518 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
13519 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
13520 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
13521 if (TARGET_PPC_GPOPT
)
13522 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
13524 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
13525 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
13526 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
13527 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
13528 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
13529 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
13531 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
13532 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
13533 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
13534 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
13535 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
13536 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
13537 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
13538 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
13543 /* Expand a block clear operation, and return 1 if successful. Return 0
13544 if we should let the compiler generate normal code.
13546 operands[0] is the destination
13547 operands[1] is the length
13548 operands[3] is the alignment */
13551 expand_block_clear (rtx operands
[])
13553 rtx orig_dest
= operands
[0];
13554 rtx bytes_rtx
= operands
[1];
13555 rtx align_rtx
= operands
[3];
13556 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
13557 HOST_WIDE_INT align
;
13558 HOST_WIDE_INT bytes
;
13563 /* If this is not a fixed size move, just call memcpy */
13567 /* This must be a fixed size alignment */
13568 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
13569 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
13571 /* Anything to clear? */
13572 bytes
= INTVAL (bytes_rtx
);
13576 /* Use the builtin memset after a point, to avoid huge code bloat.
13577 When optimize_size, avoid any significant code bloat; calling
13578 memset is about 4 instructions, so allow for one instruction to
13579 load zero and three to do clearing. */
13580 if (TARGET_ALTIVEC
&& align
>= 128)
13582 else if (TARGET_POWERPC64
&& align
>= 32)
13584 else if (TARGET_SPE
&& align
>= 64)
13589 if (optimize_size
&& bytes
> 3 * clear_step
)
13591 if (! optimize_size
&& bytes
> 8 * clear_step
)
13594 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
13596 enum machine_mode mode
= BLKmode
;
13599 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
13604 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
13609 else if (bytes
>= 8 && TARGET_POWERPC64
13610 /* 64-bit loads and stores require word-aligned
13612 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
13617 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
13618 { /* move 4 bytes */
13622 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
13623 { /* move 2 bytes */
13627 else /* move 1 byte at a time */
13633 dest
= adjust_address (orig_dest
, mode
, offset
);
13635 emit_move_insn (dest
, CONST0_RTX (mode
));
13642 /* Expand a block move operation, and return 1 if successful. Return 0
13643 if we should let the compiler generate normal code.
13645 operands[0] is the destination
13646 operands[1] is the source
13647 operands[2] is the length
13648 operands[3] is the alignment */
13650 #define MAX_MOVE_REG 4
13653 expand_block_move (rtx operands
[])
13655 rtx orig_dest
= operands
[0];
13656 rtx orig_src
= operands
[1];
13657 rtx bytes_rtx
= operands
[2];
13658 rtx align_rtx
= operands
[3];
13659 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
13664 rtx stores
[MAX_MOVE_REG
];
13667 /* If this is not a fixed size move, just call memcpy */
13671 /* This must be a fixed size alignment */
13672 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
13673 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
13675 /* Anything to move? */
13676 bytes
= INTVAL (bytes_rtx
);
13680 if (bytes
> rs6000_block_move_inline_limit
)
13683 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
13686 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
13687 rtx (*mov
) (rtx
, rtx
);
13689 enum machine_mode mode
= BLKmode
;
13692 /* Altivec first, since it will be faster than a string move
13693 when it applies, and usually not significantly larger. */
13694 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
13698 gen_func
.mov
= gen_movv4si
;
13700 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
13704 gen_func
.mov
= gen_movv2si
;
13706 else if (TARGET_STRING
13707 && bytes
> 24 /* move up to 32 bytes at a time */
13713 && ! fixed_regs
[10]
13714 && ! fixed_regs
[11]
13715 && ! fixed_regs
[12])
13717 move_bytes
= (bytes
> 32) ? 32 : bytes
;
13718 gen_func
.movmemsi
= gen_movmemsi_8reg
;
13720 else if (TARGET_STRING
13721 && bytes
> 16 /* move up to 24 bytes at a time */
13727 && ! fixed_regs
[10])
13729 move_bytes
= (bytes
> 24) ? 24 : bytes
;
13730 gen_func
.movmemsi
= gen_movmemsi_6reg
;
13732 else if (TARGET_STRING
13733 && bytes
> 8 /* move up to 16 bytes at a time */
13737 && ! fixed_regs
[8])
13739 move_bytes
= (bytes
> 16) ? 16 : bytes
;
13740 gen_func
.movmemsi
= gen_movmemsi_4reg
;
13742 else if (bytes
>= 8 && TARGET_POWERPC64
13743 /* 64-bit loads and stores require word-aligned
13745 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
13749 gen_func
.mov
= gen_movdi
;
13751 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
13752 { /* move up to 8 bytes at a time */
13753 move_bytes
= (bytes
> 8) ? 8 : bytes
;
13754 gen_func
.movmemsi
= gen_movmemsi_2reg
;
13756 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
13757 { /* move 4 bytes */
13760 gen_func
.mov
= gen_movsi
;
13762 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
13763 { /* move 2 bytes */
13766 gen_func
.mov
= gen_movhi
;
13768 else if (TARGET_STRING
&& bytes
> 1)
13769 { /* move up to 4 bytes at a time */
13770 move_bytes
= (bytes
> 4) ? 4 : bytes
;
13771 gen_func
.movmemsi
= gen_movmemsi_1reg
;
13773 else /* move 1 byte at a time */
13777 gen_func
.mov
= gen_movqi
;
13780 src
= adjust_address (orig_src
, mode
, offset
);
13781 dest
= adjust_address (orig_dest
, mode
, offset
);
13783 if (mode
!= BLKmode
)
13785 rtx tmp_reg
= gen_reg_rtx (mode
);
13787 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
13788 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
13791 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
13794 for (i
= 0; i
< num_reg
; i
++)
13795 emit_insn (stores
[i
]);
13799 if (mode
== BLKmode
)
13801 /* Move the address into scratch registers. The movmemsi
13802 patterns require zero offset. */
13803 if (!REG_P (XEXP (src
, 0)))
13805 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
13806 src
= replace_equiv_address (src
, src_reg
);
13808 set_mem_size (src
, move_bytes
);
13810 if (!REG_P (XEXP (dest
, 0)))
13812 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
13813 dest
= replace_equiv_address (dest
, dest_reg
);
13815 set_mem_size (dest
, move_bytes
);
13817 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
13818 GEN_INT (move_bytes
& 31),
13827 /* Return a string to perform a load_multiple operation.
13828 operands[0] is the vector.
13829 operands[1] is the source address.
13830 operands[2] is the first destination register. */
13833 rs6000_output_load_multiple (rtx operands
[3])
13835 /* We have to handle the case where the pseudo used to contain the address
13836 is assigned to one of the output registers. */
13838 int words
= XVECLEN (operands
[0], 0);
13841 if (XVECLEN (operands
[0], 0) == 1)
13842 return "lwz %2,0(%1)";
13844 for (i
= 0; i
< words
; i
++)
13845 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
13846 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
13850 xop
[0] = GEN_INT (4 * (words
-1));
13851 xop
[1] = operands
[1];
13852 xop
[2] = operands
[2];
13853 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
13858 xop
[0] = GEN_INT (4 * (words
-1));
13859 xop
[1] = operands
[1];
13860 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
13861 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
13866 for (j
= 0; j
< words
; j
++)
13869 xop
[0] = GEN_INT (j
* 4);
13870 xop
[1] = operands
[1];
13871 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
13872 output_asm_insn ("lwz %2,%0(%1)", xop
);
13874 xop
[0] = GEN_INT (i
* 4);
13875 xop
[1] = operands
[1];
13876 output_asm_insn ("lwz %1,%0(%1)", xop
);
13881 return "lswi %2,%1,%N0";
13885 /* A validation routine: say whether CODE, a condition code, and MODE
13886 match. The other alternatives either don't make sense or should
13887 never be generated. */
13890 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
13892 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
13893 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
13894 && GET_MODE_CLASS (mode
) == MODE_CC
);
13896 /* These don't make sense. */
13897 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
13898 || mode
!= CCUNSmode
);
13900 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
13901 || mode
== CCUNSmode
);
13903 gcc_assert (mode
== CCFPmode
13904 || (code
!= ORDERED
&& code
!= UNORDERED
13905 && code
!= UNEQ
&& code
!= LTGT
13906 && code
!= UNGT
&& code
!= UNLT
13907 && code
!= UNGE
&& code
!= UNLE
));
13909 /* These should never be generated except for
13910 flag_finite_math_only. */
13911 gcc_assert (mode
!= CCFPmode
13912 || flag_finite_math_only
13913 || (code
!= LE
&& code
!= GE
13914 && code
!= UNEQ
&& code
!= LTGT
13915 && code
!= UNGT
&& code
!= UNLT
));
13917 /* These are invalid; the information is not there. */
13918 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
13922 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13923 mask required to convert the result of a rotate insn into a shift
13924 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13927 includes_lshift_p (rtx shiftop
, rtx andop
)
13929 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13931 shift_mask
<<= INTVAL (shiftop
);
13933 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13936 /* Similar, but for right shift. */
13939 includes_rshift_p (rtx shiftop
, rtx andop
)
13941 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13943 shift_mask
>>= INTVAL (shiftop
);
13945 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13948 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13949 to perform a left shift. It must have exactly SHIFTOP least
13950 significant 0's, then one or more 1's, then zero or more 0's. */
13953 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
13955 if (GET_CODE (andop
) == CONST_INT
)
13957 HOST_WIDE_INT c
, lsb
, shift_mask
;
13959 c
= INTVAL (andop
);
13960 if (c
== 0 || c
== ~0)
13964 shift_mask
<<= INTVAL (shiftop
);
13966 /* Find the least significant one bit. */
13969 /* It must coincide with the LSB of the shift mask. */
13970 if (-lsb
!= shift_mask
)
13973 /* Invert to look for the next transition (if any). */
13976 /* Remove the low group of ones (originally low group of zeros). */
13979 /* Again find the lsb, and check we have all 1's above. */
13987 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13988 to perform a left shift. It must have SHIFTOP or more least
13989 significant 0's, with the remainder of the word 1's. */
13992 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
13994 if (GET_CODE (andop
) == CONST_INT
)
13996 HOST_WIDE_INT c
, lsb
, shift_mask
;
13999 shift_mask
<<= INTVAL (shiftop
);
14000 c
= INTVAL (andop
);
14002 /* Find the least significant one bit. */
14005 /* It must be covered by the shift mask.
14006 This test also rejects c == 0. */
14007 if ((lsb
& shift_mask
) == 0)
14010 /* Check we have all 1's above the transition, and reject all 1's. */
14011 return c
== -lsb
&& lsb
!= 1;
14017 /* Return 1 if operands will generate a valid arguments to rlwimi
14018 instruction for insert with right shift in 64-bit mode. The mask may
14019 not start on the first bit or stop on the last bit because wrap-around
14020 effects of instruction do not correspond to semantics of RTL insn. */
14023 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
14025 if (INTVAL (startop
) > 32
14026 && INTVAL (startop
) < 64
14027 && INTVAL (sizeop
) > 1
14028 && INTVAL (sizeop
) + INTVAL (startop
) < 64
14029 && INTVAL (shiftop
) > 0
14030 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
14031 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
14037 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
14038 for lfq and stfq insns iff the registers are hard registers. */
14041 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
14043 /* We might have been passed a SUBREG. */
14044 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
14047 /* We might have been passed non floating point registers. */
14048 if (!FP_REGNO_P (REGNO (reg1
))
14049 || !FP_REGNO_P (REGNO (reg2
)))
14052 return (REGNO (reg1
) == REGNO (reg2
) - 1);
14055 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
14056 addr1 and addr2 must be in consecutive memory locations
14057 (addr2 == addr1 + 8). */
14060 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
14063 unsigned int reg1
, reg2
;
14064 int offset1
, offset2
;
14066 /* The mems cannot be volatile. */
14067 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
14070 addr1
= XEXP (mem1
, 0);
14071 addr2
= XEXP (mem2
, 0);
14073 /* Extract an offset (if used) from the first addr. */
14074 if (GET_CODE (addr1
) == PLUS
)
14076 /* If not a REG, return zero. */
14077 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
14081 reg1
= REGNO (XEXP (addr1
, 0));
14082 /* The offset must be constant! */
14083 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
14085 offset1
= INTVAL (XEXP (addr1
, 1));
14088 else if (GET_CODE (addr1
) != REG
)
14092 reg1
= REGNO (addr1
);
14093 /* This was a simple (mem (reg)) expression. Offset is 0. */
14097 /* And now for the second addr. */
14098 if (GET_CODE (addr2
) == PLUS
)
14100 /* If not a REG, return zero. */
14101 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
14105 reg2
= REGNO (XEXP (addr2
, 0));
14106 /* The offset must be constant. */
14107 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
14109 offset2
= INTVAL (XEXP (addr2
, 1));
14112 else if (GET_CODE (addr2
) != REG
)
14116 reg2
= REGNO (addr2
);
14117 /* This was a simple (mem (reg)) expression. Offset is 0. */
14121 /* Both of these must have the same base register. */
14125 /* The offset for the second addr must be 8 more than the first addr. */
14126 if (offset2
!= offset1
+ 8)
14129 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
14136 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
14138 static bool eliminated
= false;
14141 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
14142 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
14145 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
14146 gcc_assert (mem
!= NULL_RTX
);
14150 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
14151 cfun
->machine
->sdmode_stack_slot
= mem
;
14157 if (TARGET_DEBUG_ADDR
)
14159 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
14160 GET_MODE_NAME (mode
));
14162 fprintf (stderr
, "\tNULL_RTX\n");
14171 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
14173 /* Don't walk into types. */
14174 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
14176 *walk_subtrees
= 0;
14180 switch (TREE_CODE (*tp
))
14189 case VIEW_CONVERT_EXPR
:
14190 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
14200 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
14201 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
14202 only work on the traditional altivec registers, note if an altivec register
14205 static enum rs6000_reg_type
14206 register_to_reg_type (rtx reg
, bool *is_altivec
)
14208 HOST_WIDE_INT regno
;
14209 enum reg_class rclass
;
14211 if (GET_CODE (reg
) == SUBREG
)
14212 reg
= SUBREG_REG (reg
);
14215 return NO_REG_TYPE
;
14217 regno
= REGNO (reg
);
14218 if (regno
>= FIRST_PSEUDO_REGISTER
)
14220 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
14221 return PSEUDO_REG_TYPE
;
14223 regno
= true_regnum (reg
);
14224 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
14225 return PSEUDO_REG_TYPE
;
14228 gcc_assert (regno
>= 0);
14230 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
14231 *is_altivec
= true;
14233 rclass
= rs6000_regno_regclass
[regno
];
14234 return reg_class_to_reg_type
[(int)rclass
];
14237 /* Helper function for rs6000_secondary_reload to return true if a move to a
14238 different register classe is really a simple move. */
14241 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
14242 enum rs6000_reg_type from_type
,
14243 enum machine_mode mode
)
14247 /* Add support for various direct moves available. In this function, we only
14248 look at cases where we don't need any extra registers, and one or more
14249 simple move insns are issued. At present, 32-bit integers are not allowed
14250 in FPR/VSX registers. Single precision binary floating is not a simple
14251 move because we need to convert to the single precision memory layout.
14252 The 4-byte SDmode can be moved. */
14253 size
= GET_MODE_SIZE (mode
);
14254 if (TARGET_DIRECT_MOVE
14255 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
14256 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14257 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
14260 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
14261 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
14262 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
14265 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
14266 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
14267 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
14273 /* Power8 helper function for rs6000_secondary_reload, handle all of the
14274 special direct moves that involve allocating an extra register, return the
14275 insn code of the helper function if there is such a function or
14276 CODE_FOR_nothing if not. */
14279 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
14280 enum rs6000_reg_type from_type
,
14281 enum machine_mode mode
,
14282 secondary_reload_info
*sri
,
14286 enum insn_code icode
= CODE_FOR_nothing
;
14288 int size
= GET_MODE_SIZE (mode
);
14290 if (TARGET_POWERPC64
)
14294 /* Handle moving 128-bit values from GPRs to VSX point registers on
14295 power8 when running in 64-bit mode using XXPERMDI to glue the two
14296 64-bit values back together. */
14297 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
14299 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
14300 icode
= reload_vsx_gpr
[(int)mode
];
14303 /* Handle moving 128-bit values from VSX point registers to GPRs on
14304 power8 when running in 64-bit mode using XXPERMDI to get access to the
14305 bottom 64-bit value. */
14306 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14308 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
14309 icode
= reload_gpr_vsx
[(int)mode
];
14313 else if (mode
== SFmode
)
14315 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14317 cost
= 3; /* xscvdpspn, mfvsrd, and. */
14318 icode
= reload_gpr_vsx
[(int)mode
];
14321 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
14323 cost
= 2; /* mtvsrz, xscvspdpn. */
14324 icode
= reload_vsx_gpr
[(int)mode
];
14329 if (TARGET_POWERPC64
&& size
== 16)
14331 /* Handle moving 128-bit values from GPRs to VSX point registers on
14332 power8 when running in 64-bit mode using XXPERMDI to glue the two
14333 64-bit values back together. */
14334 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
14336 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
14337 icode
= reload_vsx_gpr
[(int)mode
];
14340 /* Handle moving 128-bit values from VSX point registers to GPRs on
14341 power8 when running in 64-bit mode using XXPERMDI to get access to the
14342 bottom 64-bit value. */
14343 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14345 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
14346 icode
= reload_gpr_vsx
[(int)mode
];
14350 else if (!TARGET_POWERPC64
&& size
== 8)
14352 /* Handle moving 64-bit values from GPRs to floating point registers on
14353 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
14354 values back together. Altivec register classes must be handled
14355 specially since a different instruction is used, and the secondary
14356 reload support requires a single instruction class in the scratch
14357 register constraint. However, right now TFmode is not allowed in
14358 Altivec registers, so the pattern will never match. */
14359 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
14361 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
14362 icode
= reload_fpr_gpr
[(int)mode
];
14366 if (icode
!= CODE_FOR_nothing
)
14371 sri
->icode
= icode
;
14372 sri
->extra_cost
= cost
;
14379 /* Return whether a move between two register classes can be done either
14380 directly (simple move) or via a pattern that uses a single extra temporary
14381 (using power8's direct move in this case. */
14384 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
14385 enum rs6000_reg_type from_type
,
14386 enum machine_mode mode
,
14387 secondary_reload_info
*sri
,
14390 /* Fall back to load/store reloads if either type is not a register. */
14391 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
14394 /* If we haven't allocated registers yet, assume the move can be done for the
14395 standard register types. */
14396 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
14397 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
14398 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
14401 /* Moves to the same set of registers is a simple move for non-specialized
14403 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
14406 /* Check whether a simple move can be done directly. */
14407 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
14411 sri
->icode
= CODE_FOR_nothing
;
14412 sri
->extra_cost
= 0;
14417 /* Now check if we can do it in a few steps. */
14418 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
14422 /* Inform reload about cases where moving X with a mode MODE to a register in
14423 RCLASS requires an extra scratch or immediate register. Return the class
14424 needed for the immediate register.
14426 For VSX and Altivec, we may need a register to convert sp+offset into
14429 For misaligned 64-bit gpr loads and stores we need a register to
14430 convert an offset address to indirect. */
14433 rs6000_secondary_reload (bool in_p
,
14435 reg_class_t rclass_i
,
14436 enum machine_mode mode
,
14437 secondary_reload_info
*sri
)
14439 enum reg_class rclass
= (enum reg_class
) rclass_i
;
14440 reg_class_t ret
= ALL_REGS
;
14441 enum insn_code icode
;
14442 bool default_p
= false;
14444 sri
->icode
= CODE_FOR_nothing
;
14445 icode
= rs6000_vector_reload
[mode
][in_p
!= false];
14447 if (REG_P (x
) || register_operand (x
, mode
))
14449 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
14450 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
14451 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
14455 enum rs6000_reg_type exchange
= to_type
;
14456 to_type
= from_type
;
14457 from_type
= exchange
;
14460 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
14463 icode
= (enum insn_code
)sri
->icode
;
14469 /* Handle vector moves with reload helper functions. */
14470 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
14473 sri
->icode
= CODE_FOR_nothing
;
14474 sri
->extra_cost
= 0;
14476 if (GET_CODE (x
) == MEM
)
14478 rtx addr
= XEXP (x
, 0);
14480 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
14481 an extra register in that case, but it would need an extra
14482 register if the addressing is reg+reg or (reg+reg)&(-16). Special
14483 case load/store quad. */
14484 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
14486 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
14487 && GET_MODE_SIZE (mode
) == 16
14488 && quad_memory_operand (x
, mode
))
14490 sri
->icode
= icode
;
14491 sri
->extra_cost
= 2;
14494 else if (!legitimate_indirect_address_p (addr
, false)
14495 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
14498 sri
->icode
= icode
;
14499 /* account for splitting the loads, and converting the
14500 address from reg+reg to reg. */
14501 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
14502 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
14505 /* Allow scalar loads to/from the traditional floating point
14506 registers, even if VSX memory is set. */
14507 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
14508 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
14509 && (legitimate_indirect_address_p (addr
, false)
14510 || legitimate_indirect_address_p (addr
, false)
14511 || rs6000_legitimate_offset_address_p (mode
, addr
,
14515 /* Loads to and stores from vector registers can only do reg+reg
14516 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
14517 scalar modes loading up the traditional floating point registers
14518 to use offset addresses. */
14519 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
14520 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
14522 if (!VECTOR_MEM_ALTIVEC_P (mode
)
14523 && GET_CODE (addr
) == AND
14524 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
14525 && INTVAL (XEXP (addr
, 1)) == -16
14526 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
14527 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
14529 sri
->icode
= icode
;
14530 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
14533 else if (!legitimate_indirect_address_p (addr
, false)
14534 && (rclass
== NO_REGS
14535 || !legitimate_indexed_address_p (addr
, false)))
14537 sri
->icode
= icode
;
14538 sri
->extra_cost
= 1;
14541 icode
= CODE_FOR_nothing
;
14543 /* Any other loads, including to pseudo registers which haven't been
14544 assigned to a register yet, default to require a scratch
14548 sri
->icode
= icode
;
14549 sri
->extra_cost
= 2;
14552 else if (REG_P (x
))
14554 int regno
= true_regnum (x
);
14556 icode
= CODE_FOR_nothing
;
14557 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
14561 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
14562 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
14563 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
14565 /* If memory is needed, use default_secondary_reload to create the
14567 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
14576 else if (TARGET_POWERPC64
14577 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
14579 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
14581 rtx addr
= XEXP (x
, 0);
14582 rtx off
= address_offset (addr
);
14584 if (off
!= NULL_RTX
)
14586 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
14587 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
14589 /* We need a secondary reload when our legitimate_address_p
14590 says the address is good (as otherwise the entire address
14591 will be reloaded), and the offset is not a multiple of
14592 four or we have an address wrap. Address wrap will only
14593 occur for LO_SUMs since legitimate_offset_address_p
14594 rejects addresses for 16-byte mems that will wrap. */
14595 if (GET_CODE (addr
) == LO_SUM
14596 ? (1 /* legitimate_address_p allows any offset for lo_sum */
14597 && ((offset
& 3) != 0
14598 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
14599 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
14600 && (offset
& 3) != 0))
14603 sri
->icode
= CODE_FOR_reload_di_load
;
14605 sri
->icode
= CODE_FOR_reload_di_store
;
14606 sri
->extra_cost
= 2;
14615 else if (!TARGET_POWERPC64
14616 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
14618 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
14620 rtx addr
= XEXP (x
, 0);
14621 rtx off
= address_offset (addr
);
14623 if (off
!= NULL_RTX
)
14625 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
14626 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
14628 /* We need a secondary reload when our legitimate_address_p
14629 says the address is good (as otherwise the entire address
14630 will be reloaded), and we have a wrap.
14632 legitimate_lo_sum_address_p allows LO_SUM addresses to
14633 have any offset so test for wrap in the low 16 bits.
14635 legitimate_offset_address_p checks for the range
14636 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
14637 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
14638 [0x7ff4,0x7fff] respectively, so test for the
14639 intersection of these ranges, [0x7ffc,0x7fff] and
14640 [0x7ff4,0x7ff7] respectively.
14642 Note that the address we see here may have been
14643 manipulated by legitimize_reload_address. */
14644 if (GET_CODE (addr
) == LO_SUM
14645 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
14646 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
14649 sri
->icode
= CODE_FOR_reload_si_load
;
14651 sri
->icode
= CODE_FOR_reload_si_store
;
14652 sri
->extra_cost
= 2;
14665 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
14667 gcc_assert (ret
!= ALL_REGS
);
14669 if (TARGET_DEBUG_ADDR
)
14672 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
14674 reg_class_names
[ret
],
14675 in_p
? "true" : "false",
14676 reg_class_names
[rclass
],
14677 GET_MODE_NAME (mode
));
14680 fprintf (stderr
, ", default secondary reload");
14682 if (sri
->icode
!= CODE_FOR_nothing
)
14683 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
14684 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
14686 fprintf (stderr
, "\n");
14694 /* Better tracing for rs6000_secondary_reload_inner. */
14697 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
14702 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
14704 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
14705 store_p
? "store" : "load");
14708 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
14710 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
14712 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
14713 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
14717 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
14720 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
14721 gcc_unreachable ();
14724 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
14725 to SP+reg addressing. */
14728 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
14730 int regno
= true_regnum (reg
);
14731 enum machine_mode mode
= GET_MODE (reg
);
14732 enum reg_class rclass
;
14734 rtx and_op2
= NULL_RTX
;
14737 rtx scratch_or_premodify
= scratch
;
14741 if (TARGET_DEBUG_ADDR
)
14742 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
14744 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
14745 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14747 if (GET_CODE (mem
) != MEM
)
14748 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14750 rclass
= REGNO_REG_CLASS (regno
);
14751 addr
= XEXP (mem
, 0);
14755 /* GPRs can handle reg + small constant, all other addresses need to use
14756 the scratch register. */
14759 if (GET_CODE (addr
) == AND
)
14761 and_op2
= XEXP (addr
, 1);
14762 addr
= XEXP (addr
, 0);
14765 if (GET_CODE (addr
) == PRE_MODIFY
)
14767 scratch_or_premodify
= XEXP (addr
, 0);
14768 if (!REG_P (scratch_or_premodify
))
14769 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14771 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
14772 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14774 addr
= XEXP (addr
, 1);
14777 if (GET_CODE (addr
) == PLUS
14778 && (and_op2
!= NULL_RTX
14779 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
14782 addr_op1
= XEXP (addr
, 0);
14783 addr_op2
= XEXP (addr
, 1);
14784 if (!legitimate_indirect_address_p (addr_op1
, false))
14785 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14787 if (!REG_P (addr_op2
)
14788 && (GET_CODE (addr_op2
) != CONST_INT
14789 || !satisfies_constraint_I (addr_op2
)))
14791 if (TARGET_DEBUG_ADDR
)
14794 "\nMove plus addr to register %s, mode = %s: ",
14795 rs6000_reg_names
[REGNO (scratch
)],
14796 GET_MODE_NAME (mode
));
14797 debug_rtx (addr_op2
);
14799 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
14800 addr_op2
= scratch
;
14803 emit_insn (gen_rtx_SET (VOIDmode
,
14804 scratch_or_premodify
,
14805 gen_rtx_PLUS (Pmode
,
14809 addr
= scratch_or_premodify
;
14810 scratch_or_premodify
= scratch
;
14812 else if (!legitimate_indirect_address_p (addr
, false)
14813 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
14816 if (TARGET_DEBUG_ADDR
)
14818 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
14819 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
14820 GET_MODE_NAME (mode
));
14823 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14824 addr
= scratch_or_premodify
;
14825 scratch_or_premodify
= scratch
;
14829 /* Float registers can do offset+reg addressing for scalar types. */
14831 if (legitimate_indirect_address_p (addr
, false) /* reg */
14832 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
14833 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
14834 && and_op2
== NULL_RTX
14835 && scratch_or_premodify
== scratch
14836 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
14839 /* If this isn't a legacy floating point load/store, fall through to the
14842 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
14843 addresses into a scratch register. */
14847 /* With float regs, we need to handle the AND ourselves, since we can't
14848 use the Altivec instruction with an implicit AND -16. Allow scalar
14849 loads to float registers to use reg+offset even if VSX. */
14850 if (GET_CODE (addr
) == AND
14851 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
14852 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
14853 || INTVAL (XEXP (addr
, 1)) != -16
14854 || !VECTOR_MEM_ALTIVEC_P (mode
)))
14856 and_op2
= XEXP (addr
, 1);
14857 addr
= XEXP (addr
, 0);
14860 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
14861 as the address later. */
14862 if (GET_CODE (addr
) == PRE_MODIFY
14863 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
14864 && (rclass
!= FLOAT_REGS
14865 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
14866 || and_op2
!= NULL_RTX
14867 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
14869 scratch_or_premodify
= XEXP (addr
, 0);
14870 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
14871 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14873 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
14874 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14876 addr
= XEXP (addr
, 1);
14879 if (legitimate_indirect_address_p (addr
, false) /* reg */
14880 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
14881 || (GET_CODE (addr
) == AND
/* Altivec memory */
14882 && rclass
== ALTIVEC_REGS
14883 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
14884 && INTVAL (XEXP (addr
, 1)) == -16
14885 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
14886 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
14889 else if (GET_CODE (addr
) == PLUS
)
14891 addr_op1
= XEXP (addr
, 0);
14892 addr_op2
= XEXP (addr
, 1);
14893 if (!REG_P (addr_op1
))
14894 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14896 if (TARGET_DEBUG_ADDR
)
14898 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
14899 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
14900 debug_rtx (addr_op2
);
14902 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
14903 emit_insn (gen_rtx_SET (VOIDmode
,
14904 scratch_or_premodify
,
14905 gen_rtx_PLUS (Pmode
,
14908 addr
= scratch_or_premodify
;
14909 scratch_or_premodify
= scratch
;
14912 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
14913 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
14916 if (TARGET_DEBUG_ADDR
)
14918 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
14919 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
14920 GET_MODE_NAME (mode
));
14924 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14925 addr
= scratch_or_premodify
;
14926 scratch_or_premodify
= scratch
;
14930 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14935 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
14938 /* If the original address involved a pre-modify that we couldn't use the VSX
14939 memory instruction with update, and we haven't taken care of already,
14940 store the address in the pre-modify register and use that as the
14942 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
14944 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
14945 addr
= scratch_or_premodify
;
14948 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
14949 memory instruction, recreate the AND now, including the clobber which is
14950 generated by the general ANDSI3/ANDDI3 patterns for the
14951 andi. instruction. */
14952 if (and_op2
!= NULL_RTX
)
14954 if (! legitimate_indirect_address_p (addr
, false))
14956 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
14960 if (TARGET_DEBUG_ADDR
)
14962 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
14963 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
14964 debug_rtx (and_op2
);
14967 and_rtx
= gen_rtx_SET (VOIDmode
,
14969 gen_rtx_AND (Pmode
,
14973 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
14974 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
14975 gen_rtvec (2, and_rtx
, cc_clobber
)));
14979 /* Adjust the address if it changed. */
14980 if (addr
!= XEXP (mem
, 0))
14982 mem
= replace_equiv_address_nv (mem
, addr
);
14983 if (TARGET_DEBUG_ADDR
)
14984 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14987 /* Now create the move. */
14989 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
14991 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
14996 /* Convert reloads involving 64-bit gprs and misaligned offset
14997 addressing, or multiple 32-bit gprs and offsets that are too large,
14998 to use indirect addressing. */
15001 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
15003 int regno
= true_regnum (reg
);
15004 enum reg_class rclass
;
15006 rtx scratch_or_premodify
= scratch
;
15008 if (TARGET_DEBUG_ADDR
)
15010 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
15011 store_p
? "store" : "load");
15012 fprintf (stderr
, "reg:\n");
15014 fprintf (stderr
, "mem:\n");
15016 fprintf (stderr
, "scratch:\n");
15017 debug_rtx (scratch
);
15020 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
15021 gcc_assert (GET_CODE (mem
) == MEM
);
15022 rclass
= REGNO_REG_CLASS (regno
);
15023 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
15024 addr
= XEXP (mem
, 0);
15026 if (GET_CODE (addr
) == PRE_MODIFY
)
15028 scratch_or_premodify
= XEXP (addr
, 0);
15029 gcc_assert (REG_P (scratch_or_premodify
));
15030 addr
= XEXP (addr
, 1);
15032 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
15034 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
15036 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
15038 /* Now create the move. */
15040 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
15042 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
15047 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
15048 this function has any SDmode references. If we are on a power7 or later, we
15049 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
15050 can load/store the value. */
15053 rs6000_alloc_sdmode_stack_slot (void)
15057 gimple_stmt_iterator gsi
;
15059 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
15061 if (TARGET_NO_SDMODE_STACK
)
15065 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
15067 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
15070 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
15071 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
15077 /* Check for any SDmode parameters of the function. */
15078 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
15080 if (TREE_TYPE (t
) == error_mark_node
)
15083 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
15084 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
15086 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
15087 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
15095 rs6000_instantiate_decls (void)
15097 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
15098 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
15101 /* Given an rtx X being reloaded into a reg required to be
15102 in class CLASS, return the class of reg to actually use.
15103 In general this is just CLASS; but on some machines
15104 in some cases it is preferable to use a more restrictive class.
15106 On the RS/6000, we have to return NO_REGS when we want to reload a
15107 floating-point CONST_DOUBLE to force it to be copied to memory.
15109 We also don't want to reload integer values into floating-point
15110 registers if we can at all help it. In fact, this can
15111 cause reload to die, if it tries to generate a reload of CTR
15112 into a FP register and discovers it doesn't have the memory location
15115 ??? Would it be a good idea to have reload do the converse, that is
15116 try to reload floating modes into FP registers if possible?
15119 static enum reg_class
15120 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
15122 enum machine_mode mode
= GET_MODE (x
);
15124 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
15127 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
15128 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
15129 && easy_vector_constant (x
, mode
))
15130 return ALTIVEC_REGS
;
15132 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
15135 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
15136 return GENERAL_REGS
;
15138 /* For VSX, prefer the traditional registers for 64-bit values because we can
15139 use the non-VSX loads. Prefer the Altivec registers if Altivec is
15140 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
15141 prefer Altivec loads.. */
15142 if (rclass
== VSX_REGS
)
15144 if (GET_MODE_SIZE (mode
) <= 8)
15147 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
15148 return ALTIVEC_REGS
;
15156 /* Debug version of rs6000_preferred_reload_class. */
15157 static enum reg_class
15158 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
15160 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
15163 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
15165 reg_class_names
[ret
], reg_class_names
[rclass
],
15166 GET_MODE_NAME (GET_MODE (x
)));
15172 /* If we are copying between FP or AltiVec registers and anything else, we need
15173 a memory location. The exception is when we are targeting ppc64 and the
15174 move to/from fpr to gpr instructions are available. Also, under VSX, you
15175 can copy vector registers from the FP register set to the Altivec register
15176 set and vice versa. */
15179 rs6000_secondary_memory_needed (enum reg_class from_class
,
15180 enum reg_class to_class
,
15181 enum machine_mode mode
)
15183 enum rs6000_reg_type from_type
, to_type
;
15184 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
15185 || (to_class
== ALTIVEC_REGS
));
15187 /* If a simple/direct move is available, we don't need secondary memory */
15188 from_type
= reg_class_to_reg_type
[(int)from_class
];
15189 to_type
= reg_class_to_reg_type
[(int)to_class
];
15191 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
15192 (secondary_reload_info
*)0, altivec_p
))
15195 /* If we have a floating point or vector register class, we need to use
15196 memory to transfer the data. */
15197 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
15203 /* Debug version of rs6000_secondary_memory_needed. */
15205 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
15206 enum reg_class to_class
,
15207 enum machine_mode mode
)
15209 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
15212 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
15213 "to_class = %s, mode = %s\n",
15214 ret
? "true" : "false",
15215 reg_class_names
[from_class
],
15216 reg_class_names
[to_class
],
15217 GET_MODE_NAME (mode
));
15222 /* Return the register class of a scratch register needed to copy IN into
15223 or out of a register in RCLASS in MODE. If it can be done directly,
15224 NO_REGS is returned. */
15226 static enum reg_class
15227 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
15232 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
15234 && MACHOPIC_INDIRECT
15238 /* We cannot copy a symbolic operand directly into anything
15239 other than BASE_REGS for TARGET_ELF. So indicate that a
15240 register from BASE_REGS is needed as an intermediate
15243 On Darwin, pic addresses require a load from memory, which
15244 needs a base register. */
15245 if (rclass
!= BASE_REGS
15246 && (GET_CODE (in
) == SYMBOL_REF
15247 || GET_CODE (in
) == HIGH
15248 || GET_CODE (in
) == LABEL_REF
15249 || GET_CODE (in
) == CONST
))
15253 if (GET_CODE (in
) == REG
)
15255 regno
= REGNO (in
);
15256 if (regno
>= FIRST_PSEUDO_REGISTER
)
15258 regno
= true_regnum (in
);
15259 if (regno
>= FIRST_PSEUDO_REGISTER
)
15263 else if (GET_CODE (in
) == SUBREG
)
15265 regno
= true_regnum (in
);
15266 if (regno
>= FIRST_PSEUDO_REGISTER
)
15272 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
15274 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
15275 || (regno
>= 0 && INT_REGNO_P (regno
)))
15278 /* Constants, memory, and FP registers can go into FP registers. */
15279 if ((regno
== -1 || FP_REGNO_P (regno
))
15280 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
15281 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
15283 /* Memory, and FP/altivec registers can go into fp/altivec registers under
15284 VSX. However, for scalar variables, use the traditional floating point
15285 registers so that we can use offset+register addressing. */
15287 && (regno
== -1 || VSX_REGNO_P (regno
))
15288 && VSX_REG_CLASS_P (rclass
))
15290 if (GET_MODE_SIZE (mode
) < 16)
15296 /* Memory, and AltiVec registers can go into AltiVec registers. */
15297 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
15298 && rclass
== ALTIVEC_REGS
)
15301 /* We can copy among the CR registers. */
15302 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
15303 && regno
>= 0 && CR_REGNO_P (regno
))
15306 /* Otherwise, we need GENERAL_REGS. */
15307 return GENERAL_REGS
;
15310 /* Debug version of rs6000_secondary_reload_class. */
15311 static enum reg_class
15312 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
15313 enum machine_mode mode
, rtx in
)
15315 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
15317 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
15318 "mode = %s, input rtx:\n",
15319 reg_class_names
[ret
], reg_class_names
[rclass
],
15320 GET_MODE_NAME (mode
));
15326 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
15329 rs6000_cannot_change_mode_class (enum machine_mode from
,
15330 enum machine_mode to
,
15331 enum reg_class rclass
)
15333 unsigned from_size
= GET_MODE_SIZE (from
);
15334 unsigned to_size
= GET_MODE_SIZE (to
);
15336 if (from_size
!= to_size
)
15338 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
15340 if (reg_classes_intersect_p (xclass
, rclass
))
15342 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
15343 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
15345 /* Don't allow 64-bit types to overlap with 128-bit types that take a
15346 single register under VSX because the scalar part of the register
15347 is in the upper 64-bits, and not the lower 64-bits. Types like
15348 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
15349 IEEE floating point can't overlap, and neither can small
15352 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
15355 if (from_size
< 8 || to_size
< 8)
15358 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
15361 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
15370 if (TARGET_E500_DOUBLE
15371 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
15372 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
15373 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
15374 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
15375 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
15378 /* Since the VSX register set includes traditional floating point registers
15379 and altivec registers, just check for the size being different instead of
15380 trying to check whether the modes are vector modes. Otherwise it won't
15381 allow say DF and DI to change classes. For types like TFmode and TDmode
15382 that take 2 64-bit registers, rather than a single 128-bit register, don't
15383 allow subregs of those types to other 128 bit types. */
15384 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
15386 unsigned num_regs
= (from_size
+ 15) / 16;
15387 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
15388 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
15391 return (from_size
!= 8 && from_size
!= 16);
15394 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
15395 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
15398 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
15399 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
15405 /* Debug version of rs6000_cannot_change_mode_class. */
15407 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
15408 enum machine_mode to
,
15409 enum reg_class rclass
)
15411 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
15414 "rs6000_cannot_change_mode_class, return %s, from = %s, "
15415 "to = %s, rclass = %s\n",
15416 ret
? "true" : "false",
15417 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
15418 reg_class_names
[rclass
]);
15423 /* Return a string to do a move operation of 128 bits of data. */
15426 rs6000_output_move_128bit (rtx operands
[])
15428 rtx dest
= operands
[0];
15429 rtx src
= operands
[1];
15430 enum machine_mode mode
= GET_MODE (dest
);
15433 bool dest_gpr_p
, dest_fp_p
, dest_av_p
, dest_vsx_p
;
15434 bool src_gpr_p
, src_fp_p
, src_av_p
, src_vsx_p
;
15438 dest_regno
= REGNO (dest
);
15439 dest_gpr_p
= INT_REGNO_P (dest_regno
);
15440 dest_fp_p
= FP_REGNO_P (dest_regno
);
15441 dest_av_p
= ALTIVEC_REGNO_P (dest_regno
);
15442 dest_vsx_p
= dest_fp_p
| dest_av_p
;
15447 dest_gpr_p
= dest_fp_p
= dest_av_p
= dest_vsx_p
= false;
15452 src_regno
= REGNO (src
);
15453 src_gpr_p
= INT_REGNO_P (src_regno
);
15454 src_fp_p
= FP_REGNO_P (src_regno
);
15455 src_av_p
= ALTIVEC_REGNO_P (src_regno
);
15456 src_vsx_p
= src_fp_p
| src_av_p
;
15461 src_gpr_p
= src_fp_p
= src_av_p
= src_vsx_p
= false;
15464 /* Register moves. */
15465 if (dest_regno
>= 0 && src_regno
>= 0)
15472 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
15476 else if (TARGET_VSX
&& dest_vsx_p
)
15479 return "xxlor %x0,%x1,%x1";
15481 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
15485 else if (TARGET_ALTIVEC
&& dest_av_p
&& src_av_p
)
15486 return "vor %0,%1,%1";
15488 else if (dest_fp_p
&& src_fp_p
)
15493 else if (dest_regno
>= 0 && MEM_P (src
))
15497 if (TARGET_QUAD_MEMORY
&& (dest_regno
& 1) == 0
15498 && quad_memory_operand (src
, mode
)
15499 && !reg_overlap_mentioned_p (dest
, src
))
15501 /* lq/stq only has DQ-form, so avoid X-form that %y produces. */
15502 return REG_P (XEXP (src
, 0)) ? "lq %0,%1" : "lq %0,%y1";
15508 else if (TARGET_ALTIVEC
&& dest_av_p
15509 && altivec_indexed_or_indirect_operand (src
, mode
))
15510 return "lvx %0,%y1";
15512 else if (TARGET_VSX
&& dest_vsx_p
)
15514 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
15515 return "lxvw4x %x0,%y1";
15517 return "lxvd2x %x0,%y1";
15520 else if (TARGET_ALTIVEC
&& dest_av_p
)
15521 return "lvx %0,%y1";
15523 else if (dest_fp_p
)
15528 else if (src_regno
>= 0 && MEM_P (dest
))
15532 if (TARGET_QUAD_MEMORY
&& (src_regno
& 1) == 0
15533 && quad_memory_operand (dest
, mode
))
15535 /* lq/stq only has DQ-form, so avoid X-form that %y produces. */
15536 return REG_P (XEXP (dest
, 0)) ? "stq %1,%0" : "stq %1,%y0";
15542 else if (TARGET_ALTIVEC
&& src_av_p
15543 && altivec_indexed_or_indirect_operand (src
, mode
))
15544 return "stvx %1,%y0";
15546 else if (TARGET_VSX
&& src_vsx_p
)
15548 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
15549 return "stxvw4x %x1,%y0";
15551 return "stxvd2x %x1,%y0";
15554 else if (TARGET_ALTIVEC
&& src_av_p
)
15555 return "stvx %1,%y0";
15562 else if (dest_regno
>= 0
15563 && (GET_CODE (src
) == CONST_INT
15564 || GET_CODE (src
) == CONST_DOUBLE
15565 || GET_CODE (src
) == CONST_VECTOR
))
15570 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
15571 return "xxlxor %x0,%x0,%x0";
15573 else if (TARGET_ALTIVEC
&& dest_av_p
)
15574 return output_vec_const_move (operands
);
15577 if (TARGET_DEBUG_ADDR
)
15579 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
15580 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
15583 gcc_unreachable ();
15587 /* Given a comparison operation, return the bit number in CCR to test. We
15588 know this is a valid comparison.
15590 SCC_P is 1 if this is for an scc. That means that %D will have been
15591 used instead of %C, so the bits will be in different places.
15593 Return -1 if OP isn't a valid comparison for some reason. */
15596 ccr_bit (rtx op
, int scc_p
)
15598 enum rtx_code code
= GET_CODE (op
);
15599 enum machine_mode cc_mode
;
15604 if (!COMPARISON_P (op
))
15607 reg
= XEXP (op
, 0);
15609 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
15611 cc_mode
= GET_MODE (reg
);
15612 cc_regnum
= REGNO (reg
);
15613 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
15615 validate_condition_mode (code
, cc_mode
);
15617 /* When generating a sCOND operation, only positive conditions are
15620 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
15621 || code
== GTU
|| code
== LTU
);
15626 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
15628 return base_bit
+ 2;
15629 case GT
: case GTU
: case UNLE
:
15630 return base_bit
+ 1;
15631 case LT
: case LTU
: case UNGE
:
15633 case ORDERED
: case UNORDERED
:
15634 return base_bit
+ 3;
15637 /* If scc, we will have done a cror to put the bit in the
15638 unordered position. So test that bit. For integer, this is ! LT
15639 unless this is an scc insn. */
15640 return scc_p
? base_bit
+ 3 : base_bit
;
15643 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
15646 gcc_unreachable ();
15650 /* Return the GOT register. */
15653 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
15655 /* The second flow pass currently (June 1999) can't update
15656 regs_ever_live without disturbing other parts of the compiler, so
15657 update it here to make the prolog/epilogue code happy. */
15658 if (!can_create_pseudo_p ()
15659 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
15660 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
15662 crtl
->uses_pic_offset_table
= 1;
15664 return pic_offset_table_rtx
;
15667 static rs6000_stack_t stack_info
;
15669 /* Function to init struct machine_function.
15670 This will be called, via a pointer variable,
15671 from push_function_context. */
15673 static struct machine_function
*
15674 rs6000_init_machine_status (void)
15676 stack_info
.reload_completed
= 0;
15677 return ggc_alloc_cleared_machine_function ();
15680 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
15683 extract_MB (rtx op
)
15686 unsigned long val
= INTVAL (op
);
15688 /* If the high bit is zero, the value is the first 1 bit we find
15690 if ((val
& 0x80000000) == 0)
15692 gcc_assert (val
& 0xffffffff);
15695 while (((val
<<= 1) & 0x80000000) == 0)
15700 /* If the high bit is set and the low bit is not, or the mask is all
15701 1's, the value is zero. */
15702 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
15705 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
15708 while (((val
>>= 1) & 1) != 0)
15715 extract_ME (rtx op
)
15718 unsigned long val
= INTVAL (op
);
15720 /* If the low bit is zero, the value is the first 1 bit we find from
15722 if ((val
& 1) == 0)
15724 gcc_assert (val
& 0xffffffff);
15727 while (((val
>>= 1) & 1) == 0)
15733 /* If the low bit is set and the high bit is not, or the mask is all
15734 1's, the value is 31. */
15735 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
15738 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
15741 while (((val
<<= 1) & 0x80000000) != 0)
15747 /* Locate some local-dynamic symbol still in use by this function
15748 so that we can print its name in some tls_ld pattern. */
15750 static const char *
15751 rs6000_get_some_local_dynamic_name (void)
15755 if (cfun
->machine
->some_ld_name
)
15756 return cfun
->machine
->some_ld_name
;
15758 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15760 && for_each_rtx (&PATTERN (insn
),
15761 rs6000_get_some_local_dynamic_name_1
, 0))
15762 return cfun
->machine
->some_ld_name
;
15764 gcc_unreachable ();
15767 /* Helper function for rs6000_get_some_local_dynamic_name. */
15770 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
15774 if (GET_CODE (x
) == SYMBOL_REF
)
15776 const char *str
= XSTR (x
, 0);
15777 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
15779 cfun
->machine
->some_ld_name
= str
;
15787 /* Write out a function code label. */
15790 rs6000_output_function_entry (FILE *file
, const char *fname
)
15792 if (fname
[0] != '.')
15794 switch (DEFAULT_ABI
)
15797 gcc_unreachable ();
15803 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
15812 RS6000_OUTPUT_BASENAME (file
, fname
);
15815 /* Print an operand. Recognize special options, documented below. */
15818 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
15819 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
15821 #define SMALL_DATA_RELOC "sda21"
15822 #define SMALL_DATA_REG 0
15826 print_operand (FILE *file
, rtx x
, int code
)
15829 unsigned HOST_WIDE_INT uval
;
15833 /* %a is output_address. */
15836 /* If constant, low-order 16 bits of constant, unsigned.
15837 Otherwise, write normally. */
15839 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
15841 print_operand (file
, x
, 0);
15845 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
15846 for 64-bit mask direction. */
15847 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
15850 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
15854 /* Like 'J' but get to the GT bit only. */
15855 gcc_assert (REG_P (x
));
15857 /* Bit 1 is GT bit. */
15858 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
15860 /* Add one for shift count in rlinm for scc. */
15861 fprintf (file
, "%d", i
+ 1);
15865 /* X is a CR register. Print the number of the EQ bit of the CR */
15866 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
15867 output_operand_lossage ("invalid %%E value");
15869 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
15873 /* X is a CR register. Print the shift count needed to move it
15874 to the high-order four bits. */
15875 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
15876 output_operand_lossage ("invalid %%f value");
15878 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
15882 /* Similar, but print the count for the rotate in the opposite
15884 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
15885 output_operand_lossage ("invalid %%F value");
15887 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
15891 /* X is a constant integer. If it is negative, print "m",
15892 otherwise print "z". This is to make an aze or ame insn. */
15893 if (GET_CODE (x
) != CONST_INT
)
15894 output_operand_lossage ("invalid %%G value");
15895 else if (INTVAL (x
) >= 0)
15902 /* If constant, output low-order five bits. Otherwise, write
15905 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
15907 print_operand (file
, x
, 0);
15911 /* If constant, output low-order six bits. Otherwise, write
15914 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
15916 print_operand (file
, x
, 0);
15920 /* Print `i' if this is a constant, else nothing. */
15926 /* Write the bit number in CCR for jump. */
15927 i
= ccr_bit (x
, 0);
15929 output_operand_lossage ("invalid %%j code");
15931 fprintf (file
, "%d", i
);
15935 /* Similar, but add one for shift count in rlinm for scc and pass
15936 scc flag to `ccr_bit'. */
15937 i
= ccr_bit (x
, 1);
15939 output_operand_lossage ("invalid %%J code");
15941 /* If we want bit 31, write a shift count of zero, not 32. */
15942 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
15946 /* X must be a constant. Write the 1's complement of the
15949 output_operand_lossage ("invalid %%k value");
15951 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
15955 /* X must be a symbolic constant on ELF. Write an
15956 expression suitable for an 'addi' that adds in the low 16
15957 bits of the MEM. */
15958 if (GET_CODE (x
) == CONST
)
15960 if (GET_CODE (XEXP (x
, 0)) != PLUS
15961 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
15962 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
15963 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
15964 output_operand_lossage ("invalid %%K value");
15966 print_operand_address (file
, x
);
15967 fputs ("@l", file
);
15970 /* %l is output_asm_label. */
15973 /* Write second word of DImode or DFmode reference. Works on register
15974 or non-indexed memory only. */
15976 fputs (reg_names
[REGNO (x
) + 1], file
);
15977 else if (MEM_P (x
))
15979 /* Handle possible auto-increment. Since it is pre-increment and
15980 we have already done it, we can just use an offset of word. */
15981 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
15982 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15983 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
15985 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15986 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
15989 output_address (XEXP (adjust_address_nv (x
, SImode
,
15993 if (small_data_operand (x
, GET_MODE (x
)))
15994 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15995 reg_names
[SMALL_DATA_REG
]);
16000 /* MB value for a mask operand. */
16001 if (! mask_operand (x
, SImode
))
16002 output_operand_lossage ("invalid %%m value");
16004 fprintf (file
, "%d", extract_MB (x
));
16008 /* ME value for a mask operand. */
16009 if (! mask_operand (x
, SImode
))
16010 output_operand_lossage ("invalid %%M value");
16012 fprintf (file
, "%d", extract_ME (x
));
16015 /* %n outputs the negative of its operand. */
16018 /* Write the number of elements in the vector times 4. */
16019 if (GET_CODE (x
) != PARALLEL
)
16020 output_operand_lossage ("invalid %%N value");
16022 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
16026 /* Similar, but subtract 1 first. */
16027 if (GET_CODE (x
) != PARALLEL
)
16028 output_operand_lossage ("invalid %%O value");
16030 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
16034 /* X is a CONST_INT that is a power of two. Output the logarithm. */
16037 || (i
= exact_log2 (INTVAL (x
))) < 0)
16038 output_operand_lossage ("invalid %%p value");
16040 fprintf (file
, "%d", i
);
16044 /* The operand must be an indirect memory reference. The result
16045 is the register name. */
16046 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
16047 || REGNO (XEXP (x
, 0)) >= 32)
16048 output_operand_lossage ("invalid %%P value");
16050 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
16054 /* This outputs the logical code corresponding to a boolean
16055 expression. The expression may have one or both operands
16056 negated (if one, only the first one). For condition register
16057 logical operations, it will also treat the negated
16058 CR codes as NOTs, but not handle NOTs of them. */
16060 const char *const *t
= 0;
16062 enum rtx_code code
= GET_CODE (x
);
16063 static const char * const tbl
[3][3] = {
16064 { "and", "andc", "nor" },
16065 { "or", "orc", "nand" },
16066 { "xor", "eqv", "xor" } };
16070 else if (code
== IOR
)
16072 else if (code
== XOR
)
16075 output_operand_lossage ("invalid %%q value");
16077 if (GET_CODE (XEXP (x
, 0)) != NOT
)
16081 if (GET_CODE (XEXP (x
, 1)) == NOT
)
16092 if (! TARGET_MFCRF
)
16098 /* X is a CR register. Print the mask for `mtcrf'. */
16099 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16100 output_operand_lossage ("invalid %%R value");
16102 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
16106 /* Low 5 bits of 32 - value */
16108 output_operand_lossage ("invalid %%s value");
16110 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
16114 /* PowerPC64 mask position. All 0's is excluded.
16115 CONST_INT 32-bit mask is considered sign-extended so any
16116 transition must occur within the CONST_INT, not on the boundary. */
16117 if (! mask64_operand (x
, DImode
))
16118 output_operand_lossage ("invalid %%S value");
16122 if (uval
& 1) /* Clear Left */
16124 #if HOST_BITS_PER_WIDE_INT > 64
16125 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
16129 else /* Clear Right */
16132 #if HOST_BITS_PER_WIDE_INT > 64
16133 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
16139 gcc_assert (i
>= 0);
16140 fprintf (file
, "%d", i
);
16144 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
16145 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
16147 /* Bit 3 is OV bit. */
16148 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
16150 /* If we want bit 31, write a shift count of zero, not 32. */
16151 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
16155 /* Print the symbolic name of a branch target register. */
16156 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
16157 && REGNO (x
) != CTR_REGNO
))
16158 output_operand_lossage ("invalid %%T value");
16159 else if (REGNO (x
) == LR_REGNO
)
16160 fputs ("lr", file
);
16162 fputs ("ctr", file
);
16166 /* High-order 16 bits of constant for use in unsigned operand. */
16168 output_operand_lossage ("invalid %%u value");
16170 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
16171 (INTVAL (x
) >> 16) & 0xffff);
16175 /* High-order 16 bits of constant for use in signed operand. */
16177 output_operand_lossage ("invalid %%v value");
16179 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
16180 (INTVAL (x
) >> 16) & 0xffff);
16184 /* Print `u' if this has an auto-increment or auto-decrement. */
16186 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
16187 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
16188 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
16193 /* Print the trap code for this operand. */
16194 switch (GET_CODE (x
))
16197 fputs ("eq", file
); /* 4 */
16200 fputs ("ne", file
); /* 24 */
16203 fputs ("lt", file
); /* 16 */
16206 fputs ("le", file
); /* 20 */
16209 fputs ("gt", file
); /* 8 */
16212 fputs ("ge", file
); /* 12 */
16215 fputs ("llt", file
); /* 2 */
16218 fputs ("lle", file
); /* 6 */
16221 fputs ("lgt", file
); /* 1 */
16224 fputs ("lge", file
); /* 5 */
16227 gcc_unreachable ();
16232 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
16235 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
16236 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
16238 print_operand (file
, x
, 0);
16242 /* MB value for a PowerPC64 rldic operand. */
16243 i
= clz_hwi (INTVAL (x
));
16245 fprintf (file
, "%d", i
);
16249 /* X is a FPR or Altivec register used in a VSX context. */
16250 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
16251 output_operand_lossage ("invalid %%x value");
16254 int reg
= REGNO (x
);
16255 int vsx_reg
= (FP_REGNO_P (reg
)
16257 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
16259 #ifdef TARGET_REGNAMES
16260 if (TARGET_REGNAMES
)
16261 fprintf (file
, "%%vs%d", vsx_reg
);
16264 fprintf (file
, "%d", vsx_reg
);
16270 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
16271 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
16272 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
16277 /* Like 'L', for third word of TImode/PTImode */
16279 fputs (reg_names
[REGNO (x
) + 2], file
);
16280 else if (MEM_P (x
))
16282 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
16283 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16284 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
16285 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16286 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
16288 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
16289 if (small_data_operand (x
, GET_MODE (x
)))
16290 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16291 reg_names
[SMALL_DATA_REG
]);
16296 /* X is a SYMBOL_REF. Write out the name preceded by a
16297 period and without any trailing data in brackets. Used for function
16298 names. If we are configured for System V (or the embedded ABI) on
16299 the PowerPC, do not emit the period, since those systems do not use
16300 TOCs and the like. */
16301 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
16303 /* For macho, check to see if we need a stub. */
16306 const char *name
= XSTR (x
, 0);
16308 if (darwin_emit_branch_islands
16309 && MACHOPIC_INDIRECT
16310 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
16311 name
= machopic_indirection_name (x
, /*stub_p=*/true);
16313 assemble_name (file
, name
);
16315 else if (!DOT_SYMBOLS
)
16316 assemble_name (file
, XSTR (x
, 0));
16318 rs6000_output_function_entry (file
, XSTR (x
, 0));
16322 /* Like 'L', for last word of TImode/PTImode. */
16324 fputs (reg_names
[REGNO (x
) + 3], file
);
16325 else if (MEM_P (x
))
16327 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
16328 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16329 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
16330 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16331 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
16333 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
16334 if (small_data_operand (x
, GET_MODE (x
)))
16335 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16336 reg_names
[SMALL_DATA_REG
]);
16340 /* Print AltiVec or SPE memory operand. */
16345 gcc_assert (MEM_P (x
));
16349 /* Ugly hack because %y is overloaded. */
16350 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
16351 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
16352 || GET_MODE (x
) == TFmode
16353 || GET_MODE (x
) == TImode
16354 || GET_MODE (x
) == PTImode
))
16356 /* Handle [reg]. */
16359 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
16362 /* Handle [reg+UIMM]. */
16363 else if (GET_CODE (tmp
) == PLUS
&&
16364 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
16368 gcc_assert (REG_P (XEXP (tmp
, 0)));
16370 x
= INTVAL (XEXP (tmp
, 1));
16371 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
16375 /* Fall through. Must be [reg+reg]. */
16377 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
16378 && GET_CODE (tmp
) == AND
16379 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
16380 && INTVAL (XEXP (tmp
, 1)) == -16)
16381 tmp
= XEXP (tmp
, 0);
16382 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
16383 && GET_CODE (tmp
) == PRE_MODIFY
)
16384 tmp
= XEXP (tmp
, 1);
16386 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
16389 if (!GET_CODE (tmp
) == PLUS
16390 || !REG_P (XEXP (tmp
, 0))
16391 || !REG_P (XEXP (tmp
, 1)))
16393 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
16397 if (REGNO (XEXP (tmp
, 0)) == 0)
16398 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
16399 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
16401 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
16402 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
16409 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
16410 else if (MEM_P (x
))
16412 /* We need to handle PRE_INC and PRE_DEC here, since we need to
16413 know the width from the mode. */
16414 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
16415 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
16416 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
16417 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16418 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
16419 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
16420 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16421 output_address (XEXP (XEXP (x
, 0), 1));
16423 output_address (XEXP (x
, 0));
16427 if (toc_relative_expr_p (x
, false))
16428 /* This hack along with a corresponding hack in
16429 rs6000_output_addr_const_extra arranges to output addends
16430 where the assembler expects to find them. eg.
16431 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
16432 without this hack would be output as "x@toc+4". We
16434 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
16436 output_addr_const (file
, x
);
16441 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
16445 output_operand_lossage ("invalid %%xn code");
16449 /* Print the address of an operand. */
16452 print_operand_address (FILE *file
, rtx x
)
16455 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
16456 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
16457 || GET_CODE (x
) == LABEL_REF
)
16459 output_addr_const (file
, x
);
16460 if (small_data_operand (x
, GET_MODE (x
)))
16461 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16462 reg_names
[SMALL_DATA_REG
]);
16464 gcc_assert (!TARGET_TOC
);
16466 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
16467 && REG_P (XEXP (x
, 1)))
16469 if (REGNO (XEXP (x
, 0)) == 0)
16470 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
16471 reg_names
[ REGNO (XEXP (x
, 0)) ]);
16473 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
16474 reg_names
[ REGNO (XEXP (x
, 1)) ]);
16476 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
16477 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
16478 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
16479 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
16481 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
16482 && CONSTANT_P (XEXP (x
, 1)))
16484 fprintf (file
, "lo16(");
16485 output_addr_const (file
, XEXP (x
, 1));
16486 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
16490 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
16491 && CONSTANT_P (XEXP (x
, 1)))
16493 output_addr_const (file
, XEXP (x
, 1));
16494 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
16497 else if (toc_relative_expr_p (x
, false))
16499 /* This hack along with a corresponding hack in
16500 rs6000_output_addr_const_extra arranges to output addends
16501 where the assembler expects to find them. eg.
16503 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
16504 without this hack would be output as "x@toc+8@l(9)". We
16505 want "x+8@toc@l(9)". */
16506 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
16507 if (GET_CODE (x
) == LO_SUM
)
16508 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
16510 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
16513 gcc_unreachable ();
16516 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
16519 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
16521 if (GET_CODE (x
) == UNSPEC
)
16522 switch (XINT (x
, 1))
16524 case UNSPEC_TOCREL
:
16525 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
16526 && REG_P (XVECEXP (x
, 0, 1))
16527 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
16528 output_addr_const (file
, XVECEXP (x
, 0, 0));
16529 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
16531 if (INTVAL (tocrel_offset
) >= 0)
16532 fprintf (file
, "+");
16533 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
16535 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
16538 assemble_name (file
, toc_label_name
);
16540 else if (TARGET_ELF
)
16541 fputs ("@toc", file
);
16545 case UNSPEC_MACHOPIC_OFFSET
:
16546 output_addr_const (file
, XVECEXP (x
, 0, 0));
16548 machopic_output_function_base_name (file
);
16555 /* Target hook for assembling integer objects. The PowerPC version has
16556 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
16557 is defined. It also needs to handle DI-mode objects on 64-bit
16561 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
16563 #ifdef RELOCATABLE_NEEDS_FIXUP
16564 /* Special handling for SI values. */
16565 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
16567 static int recurse
= 0;
16569 /* For -mrelocatable, we mark all addresses that need to be fixed up in
16570 the .fixup section. Since the TOC section is already relocated, we
16571 don't need to mark it here. We used to skip the text section, but it
16572 should never be valid for relocated addresses to be placed in the text
16574 if (TARGET_RELOCATABLE
16575 && in_section
!= toc_section
16577 && GET_CODE (x
) != CONST_INT
16578 && GET_CODE (x
) != CONST_DOUBLE
16584 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
16586 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
16587 fprintf (asm_out_file
, "\t.long\t(");
16588 output_addr_const (asm_out_file
, x
);
16589 fprintf (asm_out_file
, ")@fixup\n");
16590 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
16591 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
16592 fprintf (asm_out_file
, "\t.long\t");
16593 assemble_name (asm_out_file
, buf
);
16594 fprintf (asm_out_file
, "\n\t.previous\n");
16598 /* Remove initial .'s to turn a -mcall-aixdesc function
16599 address into the address of the descriptor, not the function
16601 else if (GET_CODE (x
) == SYMBOL_REF
16602 && XSTR (x
, 0)[0] == '.'
16603 && DEFAULT_ABI
== ABI_AIX
)
16605 const char *name
= XSTR (x
, 0);
16606 while (*name
== '.')
16609 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
16613 #endif /* RELOCATABLE_NEEDS_FIXUP */
16614 return default_assemble_integer (x
, size
, aligned_p
);
16617 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
16618 /* Emit an assembler directive to set symbol visibility for DECL to
16619 VISIBILITY_TYPE. */
16622 rs6000_assemble_visibility (tree decl
, int vis
)
16627 /* Functions need to have their entry point symbol visibility set as
16628 well as their descriptor symbol visibility. */
16629 if (DEFAULT_ABI
== ABI_AIX
16631 && TREE_CODE (decl
) == FUNCTION_DECL
)
16633 static const char * const visibility_types
[] = {
16634 NULL
, "internal", "hidden", "protected"
16637 const char *name
, *type
;
16639 name
= ((* targetm
.strip_name_encoding
)
16640 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
16641 type
= visibility_types
[vis
];
16643 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
16644 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
16647 default_assemble_visibility (decl
, vis
);
16652 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
16654 /* Reversal of FP compares takes care -- an ordered compare
16655 becomes an unordered compare and vice versa. */
16656 if (mode
== CCFPmode
16657 && (!flag_finite_math_only
16658 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
16659 || code
== UNEQ
|| code
== LTGT
))
16660 return reverse_condition_maybe_unordered (code
);
16662 return reverse_condition (code
);
16665 /* Generate a compare for CODE. Return a brand-new rtx that
16666 represents the result of the compare. */
16669 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
16671 enum machine_mode comp_mode
;
16672 rtx compare_result
;
16673 enum rtx_code code
= GET_CODE (cmp
);
16674 rtx op0
= XEXP (cmp
, 0);
16675 rtx op1
= XEXP (cmp
, 1);
16677 if (FLOAT_MODE_P (mode
))
16678 comp_mode
= CCFPmode
;
16679 else if (code
== GTU
|| code
== LTU
16680 || code
== GEU
|| code
== LEU
)
16681 comp_mode
= CCUNSmode
;
16682 else if ((code
== EQ
|| code
== NE
)
16683 && unsigned_reg_p (op0
)
16684 && (unsigned_reg_p (op1
)
16685 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
16686 /* These are unsigned values, perhaps there will be a later
16687 ordering compare that can be shared with this one. */
16688 comp_mode
= CCUNSmode
;
16690 comp_mode
= CCmode
;
16692 /* If we have an unsigned compare, make sure we don't have a signed value as
16694 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
16695 && INTVAL (op1
) < 0)
16697 op0
= copy_rtx_if_shared (op0
);
16698 op1
= force_reg (GET_MODE (op0
), op1
);
16699 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
16702 /* First, the compare. */
16703 compare_result
= gen_reg_rtx (comp_mode
);
16705 /* E500 FP compare instructions on the GPRs. Yuck! */
16706 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
16707 && FLOAT_MODE_P (mode
))
16709 rtx cmp
, or_result
, compare_result2
;
16710 enum machine_mode op_mode
= GET_MODE (op0
);
16713 if (op_mode
== VOIDmode
)
16714 op_mode
= GET_MODE (op1
);
16716 /* First reverse the condition codes that aren't directly supported. */
16724 code
= reverse_condition_maybe_unordered (code
);
16737 gcc_unreachable ();
16740 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
16741 This explains the following mess. */
16749 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16750 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
16751 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
16755 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16756 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
16757 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
16761 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16762 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
16763 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
16767 gcc_unreachable ();
16776 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16777 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
16778 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
16782 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16783 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
16784 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
16788 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16789 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
16790 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
16794 gcc_unreachable ();
16803 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16804 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
16805 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
16809 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16810 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
16811 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
16815 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16816 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
16817 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
16821 gcc_unreachable ();
16826 gcc_unreachable ();
16829 /* Synthesize LE and GE from LT/GT || EQ. */
16830 if (code
== LE
|| code
== GE
)
16834 compare_result2
= gen_reg_rtx (CCFPmode
);
16840 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16841 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
16842 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
16846 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16847 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
16848 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
16852 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
16853 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
16854 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
16858 gcc_unreachable ();
16863 /* OR them together. */
16864 or_result
= gen_reg_rtx (CCFPmode
);
16865 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
16867 compare_result
= or_result
;
16870 code
= reverse_p
? NE
: EQ
;
16876 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
16877 CLOBBERs to match cmptf_internal2 pattern. */
16878 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
16879 && GET_MODE (op0
) == TFmode
16880 && !TARGET_IEEEQUAD
16881 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
16882 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
16884 gen_rtx_SET (VOIDmode
,
16886 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
16887 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16888 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16889 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16890 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16891 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16892 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16893 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16894 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
16895 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
16896 else if (GET_CODE (op1
) == UNSPEC
16897 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
16899 rtx op1b
= XVECEXP (op1
, 0, 0);
16900 comp_mode
= CCEQmode
;
16901 compare_result
= gen_reg_rtx (CCEQmode
);
16903 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
16905 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
16908 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
16909 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
16912 /* Some kinds of FP comparisons need an OR operation;
16913 under flag_finite_math_only we don't bother. */
16914 if (FLOAT_MODE_P (mode
)
16915 && !flag_finite_math_only
16916 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
16917 && (code
== LE
|| code
== GE
16918 || code
== UNEQ
|| code
== LTGT
16919 || code
== UNGT
|| code
== UNLT
))
16921 enum rtx_code or1
, or2
;
16922 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
16923 rtx or_result
= gen_reg_rtx (CCEQmode
);
16927 case LE
: or1
= LT
; or2
= EQ
; break;
16928 case GE
: or1
= GT
; or2
= EQ
; break;
16929 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
16930 case LTGT
: or1
= LT
; or2
= GT
; break;
16931 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
16932 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
16933 default: gcc_unreachable ();
16935 validate_condition_mode (or1
, comp_mode
);
16936 validate_condition_mode (or2
, comp_mode
);
16937 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
16938 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
16939 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
16940 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
16942 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
16944 compare_result
= or_result
;
16948 validate_condition_mode (code
, GET_MODE (compare_result
));
16950 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
16954 /* Emit the RTL for an sISEL pattern. */
16957 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
16959 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
16963 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
16966 enum machine_mode op_mode
;
16967 enum rtx_code cond_code
;
16968 rtx result
= operands
[0];
16970 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
16972 rs6000_emit_sISEL (mode
, operands
);
16976 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
16977 cond_code
= GET_CODE (condition_rtx
);
16979 if (FLOAT_MODE_P (mode
)
16980 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
16984 PUT_MODE (condition_rtx
, SImode
);
16985 t
= XEXP (condition_rtx
, 0);
16987 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
16989 if (cond_code
== NE
)
16990 emit_insn (gen_e500_flip_gt_bit (t
, t
));
16992 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
16996 if (cond_code
== NE
16997 || cond_code
== GE
|| cond_code
== LE
16998 || cond_code
== GEU
|| cond_code
== LEU
16999 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
17001 rtx not_result
= gen_reg_rtx (CCEQmode
);
17002 rtx not_op
, rev_cond_rtx
;
17003 enum machine_mode cc_mode
;
17005 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
17007 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
17008 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
17009 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
17010 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
17011 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
17014 op_mode
= GET_MODE (XEXP (operands
[1], 0));
17015 if (op_mode
== VOIDmode
)
17016 op_mode
= GET_MODE (XEXP (operands
[1], 1));
17018 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
17020 PUT_MODE (condition_rtx
, DImode
);
17021 convert_move (result
, condition_rtx
, 0);
17025 PUT_MODE (condition_rtx
, SImode
);
17026 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
17030 /* Emit a branch of kind CODE to location LOC. */
17033 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
17035 rtx condition_rtx
, loc_ref
;
17037 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
17038 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
17039 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
17040 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
17041 loc_ref
, pc_rtx
)));
17044 /* Return the string to output a conditional branch to LABEL, which is
17045 the operand template of the label, or NULL if the branch is really a
17046 conditional return.
17048 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
17049 condition code register and its mode specifies what kind of
17050 comparison we made.
17052 REVERSED is nonzero if we should reverse the sense of the comparison.
17054 INSN is the insn. */
17057 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
17059 static char string
[64];
17060 enum rtx_code code
= GET_CODE (op
);
17061 rtx cc_reg
= XEXP (op
, 0);
17062 enum machine_mode mode
= GET_MODE (cc_reg
);
17063 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
17064 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
17065 int really_reversed
= reversed
^ need_longbranch
;
17071 validate_condition_mode (code
, mode
);
17073 /* Work out which way this really branches. We could use
17074 reverse_condition_maybe_unordered here always but this
17075 makes the resulting assembler clearer. */
17076 if (really_reversed
)
17078 /* Reversal of FP compares takes care -- an ordered compare
17079 becomes an unordered compare and vice versa. */
17080 if (mode
== CCFPmode
)
17081 code
= reverse_condition_maybe_unordered (code
);
17083 code
= reverse_condition (code
);
17086 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
17088 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
17093 /* Opposite of GT. */
17102 gcc_unreachable ();
17108 /* Not all of these are actually distinct opcodes, but
17109 we distinguish them for clarity of the resulting assembler. */
17110 case NE
: case LTGT
:
17111 ccode
= "ne"; break;
17112 case EQ
: case UNEQ
:
17113 ccode
= "eq"; break;
17115 ccode
= "ge"; break;
17116 case GT
: case GTU
: case UNGT
:
17117 ccode
= "gt"; break;
17119 ccode
= "le"; break;
17120 case LT
: case LTU
: case UNLT
:
17121 ccode
= "lt"; break;
17122 case UNORDERED
: ccode
= "un"; break;
17123 case ORDERED
: ccode
= "nu"; break;
17124 case UNGE
: ccode
= "nl"; break;
17125 case UNLE
: ccode
= "ng"; break;
17127 gcc_unreachable ();
17130 /* Maybe we have a guess as to how likely the branch is. */
17132 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
17133 if (note
!= NULL_RTX
)
17135 /* PROB is the difference from 50%. */
17136 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
17138 /* Only hint for highly probable/improbable branches on newer
17139 cpus as static prediction overrides processor dynamic
17140 prediction. For older cpus we may as well always hint, but
17141 assume not taken for branches that are very close to 50% as a
17142 mispredicted taken branch is more expensive than a
17143 mispredicted not-taken branch. */
17144 if (rs6000_always_hint
17145 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
17146 && br_prob_note_reliable_p (note
)))
17148 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
17149 && ((prob
> 0) ^ need_longbranch
))
17157 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
17159 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
17161 /* We need to escape any '%' characters in the reg_names string.
17162 Assume they'd only be the first character.... */
17163 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
17165 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
17169 /* If the branch distance was too far, we may have to use an
17170 unconditional branch to go the distance. */
17171 if (need_longbranch
)
17172 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
17174 s
+= sprintf (s
, ",%s", label
);
17180 /* Return the string to flip the GT bit on a CR. */
17182 output_e500_flip_gt_bit (rtx dst
, rtx src
)
17184 static char string
[64];
17187 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
17188 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
17191 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
17192 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
17194 sprintf (string
, "crnot %d,%d", a
, b
);
17198 /* Return insn for VSX or Altivec comparisons. */
17201 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
17204 enum machine_mode mode
= GET_MODE (op0
);
17212 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
17222 mask
= gen_reg_rtx (mode
);
17223 emit_insn (gen_rtx_SET (VOIDmode
,
17225 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
17232 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
17233 DMODE is expected destination mode. This is a recursive function. */
17236 rs6000_emit_vector_compare (enum rtx_code rcode
,
17238 enum machine_mode dmode
)
17241 bool swap_operands
= false;
17242 bool try_again
= false;
17244 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
17245 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
17247 /* See if the comparison works as is. */
17248 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
17256 swap_operands
= true;
17261 swap_operands
= true;
17269 /* Invert condition and try again.
17270 e.g., A != B becomes ~(A==B). */
17272 enum rtx_code rev_code
;
17273 enum insn_code nor_code
;
17276 rev_code
= reverse_condition_maybe_unordered (rcode
);
17277 if (rev_code
== UNKNOWN
)
17280 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
17281 if (nor_code
== CODE_FOR_nothing
)
17284 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
17288 mask
= gen_reg_rtx (dmode
);
17289 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
17297 /* Try GT/GTU/LT/LTU OR EQ */
17300 enum insn_code ior_code
;
17301 enum rtx_code new_code
;
17322 gcc_unreachable ();
17325 ior_code
= optab_handler (ior_optab
, dmode
);
17326 if (ior_code
== CODE_FOR_nothing
)
17329 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
17333 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
17337 mask
= gen_reg_rtx (dmode
);
17338 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
17356 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
17361 /* You only get two chances. */
17365 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
17366 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
17367 operands for the relation operation COND. */
17370 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
17371 rtx cond
, rtx cc_op0
, rtx cc_op1
)
17373 enum machine_mode dest_mode
= GET_MODE (dest
);
17374 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
17375 enum rtx_code rcode
= GET_CODE (cond
);
17376 enum machine_mode cc_mode
= CCmode
;
17380 bool invert_move
= false;
17382 if (VECTOR_UNIT_NONE_P (dest_mode
))
17385 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
17386 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
17390 /* Swap operands if we can, and fall back to doing the operation as
17391 specified, and doing a NOR to invert the test. */
17397 /* Invert condition and try again.
17398 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
17399 invert_move
= true;
17400 rcode
= reverse_condition_maybe_unordered (rcode
);
17401 if (rcode
== UNKNOWN
)
17405 /* Mark unsigned tests with CCUNSmode. */
17410 cc_mode
= CCUNSmode
;
17417 /* Get the vector mask for the given relational operations. */
17418 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
17426 op_true
= op_false
;
17430 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
17431 CONST0_RTX (dest_mode
));
17432 emit_insn (gen_rtx_SET (VOIDmode
,
17434 gen_rtx_IF_THEN_ELSE (dest_mode
,
17441 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
17442 operands of the last comparison is nonzero/true, FALSE_COND if it
17443 is zero/false. Return 0 if the hardware has no such operation. */
17446 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
17448 enum rtx_code code
= GET_CODE (op
);
17449 rtx op0
= XEXP (op
, 0);
17450 rtx op1
= XEXP (op
, 1);
17451 REAL_VALUE_TYPE c1
;
17452 enum machine_mode compare_mode
= GET_MODE (op0
);
17453 enum machine_mode result_mode
= GET_MODE (dest
);
17455 bool is_against_zero
;
17457 /* These modes should always match. */
17458 if (GET_MODE (op1
) != compare_mode
17459 /* In the isel case however, we can use a compare immediate, so
17460 op1 may be a small constant. */
17461 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
17463 if (GET_MODE (true_cond
) != result_mode
)
17465 if (GET_MODE (false_cond
) != result_mode
)
17468 /* Don't allow using floating point comparisons for integer results for
17470 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
17473 /* First, work out if the hardware can do this at all, or
17474 if it's too slow.... */
17475 if (!FLOAT_MODE_P (compare_mode
))
17478 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
17481 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
17482 && SCALAR_FLOAT_MODE_P (compare_mode
))
17485 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
17487 /* A floating-point subtract might overflow, underflow, or produce
17488 an inexact result, thus changing the floating-point flags, so it
17489 can't be generated if we care about that. It's safe if one side
17490 of the construct is zero, since then no subtract will be
17492 if (SCALAR_FLOAT_MODE_P (compare_mode
)
17493 && flag_trapping_math
&& ! is_against_zero
)
17496 /* Eliminate half of the comparisons by switching operands, this
17497 makes the remaining code simpler. */
17498 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
17499 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
17501 code
= reverse_condition_maybe_unordered (code
);
17503 true_cond
= false_cond
;
17507 /* UNEQ and LTGT take four instructions for a comparison with zero,
17508 it'll probably be faster to use a branch here too. */
17509 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
17512 if (GET_CODE (op1
) == CONST_DOUBLE
)
17513 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
17515 /* We're going to try to implement comparisons by performing
17516 a subtract, then comparing against zero. Unfortunately,
17517 Inf - Inf is NaN which is not zero, and so if we don't
17518 know that the operand is finite and the comparison
17519 would treat EQ different to UNORDERED, we can't do it. */
17520 if (HONOR_INFINITIES (compare_mode
)
17521 && code
!= GT
&& code
!= UNGE
17522 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
17523 /* Constructs of the form (a OP b ? a : b) are safe. */
17524 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
17525 || (! rtx_equal_p (op0
, true_cond
)
17526 && ! rtx_equal_p (op1
, true_cond
))))
17529 /* At this point we know we can use fsel. */
17531 /* Reduce the comparison to a comparison against zero. */
17532 if (! is_against_zero
)
17534 temp
= gen_reg_rtx (compare_mode
);
17535 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
17536 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
17538 op1
= CONST0_RTX (compare_mode
);
17541 /* If we don't care about NaNs we can reduce some of the comparisons
17542 down to faster ones. */
17543 if (! HONOR_NANS (compare_mode
))
17549 true_cond
= false_cond
;
17562 /* Now, reduce everything down to a GE. */
17569 temp
= gen_reg_rtx (compare_mode
);
17570 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
17575 temp
= gen_reg_rtx (compare_mode
);
17576 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
17581 temp
= gen_reg_rtx (compare_mode
);
17582 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
17583 gen_rtx_NEG (compare_mode
,
17584 gen_rtx_ABS (compare_mode
, op0
))));
17589 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
17590 temp
= gen_reg_rtx (result_mode
);
17591 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
17592 gen_rtx_IF_THEN_ELSE (result_mode
,
17593 gen_rtx_GE (VOIDmode
,
17595 true_cond
, false_cond
)));
17596 false_cond
= true_cond
;
17599 temp
= gen_reg_rtx (compare_mode
);
17600 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
17605 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
17606 temp
= gen_reg_rtx (result_mode
);
17607 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
17608 gen_rtx_IF_THEN_ELSE (result_mode
,
17609 gen_rtx_GE (VOIDmode
,
17611 true_cond
, false_cond
)));
17612 true_cond
= false_cond
;
17615 temp
= gen_reg_rtx (compare_mode
);
17616 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
17621 gcc_unreachable ();
17624 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
17625 gen_rtx_IF_THEN_ELSE (result_mode
,
17626 gen_rtx_GE (VOIDmode
,
17628 true_cond
, false_cond
)));
17632 /* Same as above, but for ints (isel). */
17635 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
17637 rtx condition_rtx
, cr
;
17638 enum machine_mode mode
= GET_MODE (dest
);
17639 enum rtx_code cond_code
;
17640 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
17643 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
17646 /* We still have to do the compare, because isel doesn't do a
17647 compare, it just looks at the CRx bits set by a previous compare
17649 condition_rtx
= rs6000_generate_compare (op
, mode
);
17650 cond_code
= GET_CODE (condition_rtx
);
17651 cr
= XEXP (condition_rtx
, 0);
17652 signedp
= GET_MODE (cr
) == CCmode
;
17654 isel_func
= (mode
== SImode
17655 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
17656 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
17660 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
17661 /* isel handles these directly. */
17665 /* We need to swap the sense of the comparison. */
17668 true_cond
= false_cond
;
17670 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
17675 false_cond
= force_reg (mode
, false_cond
);
17676 if (true_cond
!= const0_rtx
)
17677 true_cond
= force_reg (mode
, true_cond
);
17679 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
17685 output_isel (rtx
*operands
)
17687 enum rtx_code code
;
17689 code
= GET_CODE (operands
[1]);
17691 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
17693 gcc_assert (GET_CODE (operands
[2]) == REG
17694 && GET_CODE (operands
[3]) == REG
);
17695 PUT_CODE (operands
[1], reverse_condition (code
));
17696 return "isel %0,%3,%2,%j1";
17699 return "isel %0,%2,%3,%j1";
17703 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
17705 enum machine_mode mode
= GET_MODE (op0
);
17709 /* VSX/altivec have direct min/max insns. */
17710 if ((code
== SMAX
|| code
== SMIN
)
17711 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
17712 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
17714 emit_insn (gen_rtx_SET (VOIDmode
,
17716 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
17720 if (code
== SMAX
|| code
== SMIN
)
17725 if (code
== SMAX
|| code
== UMAX
)
17726 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
17727 op0
, op1
, mode
, 0);
17729 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
17730 op1
, op0
, mode
, 0);
17731 gcc_assert (target
);
17732 if (target
!= dest
)
17733 emit_move_insn (dest
, target
);
17736 /* A subroutine of the atomic operation splitters. Jump to LABEL if
17737 COND is true. Mark the jump as unlikely to be taken. */
17740 emit_unlikely_jump (rtx cond
, rtx label
)
17742 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
17745 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
17746 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
17747 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
17750 /* A subroutine of the atomic operation splitters. Emit a load-locked
17751 instruction in MODE. */
17754 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
17756 rtx (*fn
) (rtx
, rtx
) = NULL
;
17761 fn
= gen_load_lockedsi
;
17764 fn
= gen_load_lockeddi
;
17767 gcc_unreachable ();
17769 emit_insn (fn (reg
, mem
));
17772 /* A subroutine of the atomic operation splitters. Emit a store-conditional
17773 instruction in MODE. */
17776 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
17778 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
17783 fn
= gen_store_conditionalsi
;
17786 fn
= gen_store_conditionaldi
;
17789 gcc_unreachable ();
17792 /* Emit sync before stwcx. to address PPC405 Erratum. */
17793 if (PPC405_ERRATUM77
)
17794 emit_insn (gen_hwsync ());
17796 emit_insn (fn (res
, mem
, val
));
17799 /* Expand barriers before and after a load_locked/store_cond sequence. */
17802 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
17804 rtx addr
= XEXP (mem
, 0);
17805 int strict_p
= (reload_in_progress
|| reload_completed
);
17807 if (!legitimate_indirect_address_p (addr
, strict_p
)
17808 && !legitimate_indexed_address_p (addr
, strict_p
))
17810 addr
= force_reg (Pmode
, addr
);
17811 mem
= replace_equiv_address_nv (mem
, addr
);
17816 case MEMMODEL_RELAXED
:
17817 case MEMMODEL_CONSUME
:
17818 case MEMMODEL_ACQUIRE
:
17820 case MEMMODEL_RELEASE
:
17821 case MEMMODEL_ACQ_REL
:
17822 emit_insn (gen_lwsync ());
17824 case MEMMODEL_SEQ_CST
:
17825 emit_insn (gen_hwsync ());
17828 gcc_unreachable ();
17834 rs6000_post_atomic_barrier (enum memmodel model
)
17838 case MEMMODEL_RELAXED
:
17839 case MEMMODEL_CONSUME
:
17840 case MEMMODEL_RELEASE
:
17842 case MEMMODEL_ACQUIRE
:
17843 case MEMMODEL_ACQ_REL
:
17844 case MEMMODEL_SEQ_CST
:
17845 emit_insn (gen_isync ());
17848 gcc_unreachable ();
17852 /* A subroutine of the various atomic expanders. For sub-word operations,
17853 we must adjust things to operate on SImode. Given the original MEM,
17854 return a new aligned memory. Also build and return the quantities by
17855 which to shift and mask. */
17858 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
17860 rtx addr
, align
, shift
, mask
, mem
;
17861 HOST_WIDE_INT shift_mask
;
17862 enum machine_mode mode
= GET_MODE (orig_mem
);
17864 /* For smaller modes, we have to implement this via SImode. */
17865 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
17867 addr
= XEXP (orig_mem
, 0);
17868 addr
= force_reg (GET_MODE (addr
), addr
);
17870 /* Aligned memory containing subword. Generate a new memory. We
17871 do not want any of the existing MEM_ATTR data, as we're now
17872 accessing memory outside the original object. */
17873 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
17874 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17875 mem
= gen_rtx_MEM (SImode
, align
);
17876 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
17877 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
17878 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
17880 /* Shift amount for subword relative to aligned word. */
17881 shift
= gen_reg_rtx (SImode
);
17882 addr
= gen_lowpart (SImode
, addr
);
17883 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
17884 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
17885 shift
, 1, OPTAB_LIB_WIDEN
);
17888 /* Mask for insertion. */
17889 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
17890 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17896 /* A subroutine of the various atomic expanders. For sub-word operands,
17897 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
17900 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
17904 x
= gen_reg_rtx (SImode
);
17905 emit_insn (gen_rtx_SET (VOIDmode
, x
,
17906 gen_rtx_AND (SImode
,
17907 gen_rtx_NOT (SImode
, mask
),
17910 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
17915 /* A subroutine of the various atomic expanders. For sub-word operands,
17916 extract WIDE to NARROW via SHIFT. */
17919 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
17921 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
17922 wide
, 1, OPTAB_LIB_WIDEN
);
17923 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
17926 /* Expand an atomic compare and swap operation. */
17929 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
17931 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
17932 rtx label1
, label2
, x
, mask
, shift
;
17933 enum machine_mode mode
;
17934 enum memmodel mod_s
, mod_f
;
17937 boolval
= operands
[0];
17938 retval
= operands
[1];
17940 oldval
= operands
[3];
17941 newval
= operands
[4];
17942 is_weak
= (INTVAL (operands
[5]) != 0);
17943 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
17944 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
17945 mode
= GET_MODE (mem
);
17947 mask
= shift
= NULL_RTX
;
17948 if (mode
== QImode
|| mode
== HImode
)
17950 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
17952 /* Shift and mask OLDVAL into position with the word. */
17953 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
17954 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
17955 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17957 /* Shift and mask NEWVAL into position within the word. */
17958 newval
= convert_modes (SImode
, mode
, newval
, 1);
17959 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
17960 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17962 /* Prepare to adjust the return value. */
17963 retval
= gen_reg_rtx (SImode
);
17966 else if (reg_overlap_mentioned_p (retval
, oldval
))
17967 oldval
= copy_to_reg (oldval
);
17969 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
17974 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
17975 emit_label (XEXP (label1
, 0));
17977 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
17979 emit_load_locked (mode
, retval
, mem
);
17984 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
17985 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17988 cond
= gen_reg_rtx (CCmode
);
17989 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
17990 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
17992 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
17993 emit_unlikely_jump (x
, label2
);
17997 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
17999 emit_store_conditional (mode
, cond
, mem
, x
);
18003 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18004 emit_unlikely_jump (x
, label1
);
18007 if (mod_f
!= MEMMODEL_RELAXED
)
18008 emit_label (XEXP (label2
, 0));
18010 rs6000_post_atomic_barrier (mod_s
);
18012 if (mod_f
== MEMMODEL_RELAXED
)
18013 emit_label (XEXP (label2
, 0));
18016 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
18018 /* In all cases, CR0 contains EQ on success, and NE on failure. */
18019 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
18020 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
18023 /* Expand an atomic exchange operation. */
18026 rs6000_expand_atomic_exchange (rtx operands
[])
18028 rtx retval
, mem
, val
, cond
;
18029 enum machine_mode mode
;
18030 enum memmodel model
;
18031 rtx label
, x
, mask
, shift
;
18033 retval
= operands
[0];
18036 model
= (enum memmodel
) INTVAL (operands
[3]);
18037 mode
= GET_MODE (mem
);
18039 mask
= shift
= NULL_RTX
;
18040 if (mode
== QImode
|| mode
== HImode
)
18042 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
18044 /* Shift and mask VAL into position with the word. */
18045 val
= convert_modes (SImode
, mode
, val
, 1);
18046 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
18047 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18049 /* Prepare to adjust the return value. */
18050 retval
= gen_reg_rtx (SImode
);
18054 mem
= rs6000_pre_atomic_barrier (mem
, model
);
18056 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
18057 emit_label (XEXP (label
, 0));
18059 emit_load_locked (mode
, retval
, mem
);
18063 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
18065 cond
= gen_reg_rtx (CCmode
);
18066 emit_store_conditional (mode
, cond
, mem
, x
);
18068 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18069 emit_unlikely_jump (x
, label
);
18071 rs6000_post_atomic_barrier (model
);
18074 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
18077 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
18078 to perform. MEM is the memory on which to operate. VAL is the second
18079 operand of the binary operator. BEFORE and AFTER are optional locations to
18080 return the value of MEM either before of after the operation. MODEL_RTX
18081 is a CONST_INT containing the memory model to use. */
18084 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
18085 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
18087 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
18088 enum machine_mode mode
= GET_MODE (mem
);
18089 rtx label
, x
, cond
, mask
, shift
;
18090 rtx before
= orig_before
, after
= orig_after
;
18092 mask
= shift
= NULL_RTX
;
18093 if (mode
== QImode
|| mode
== HImode
)
18095 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
18097 /* Shift and mask VAL into position with the word. */
18098 val
= convert_modes (SImode
, mode
, val
, 1);
18099 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
18100 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18106 /* We've already zero-extended VAL. That is sufficient to
18107 make certain that it does not affect other bits. */
18112 /* If we make certain that all of the other bits in VAL are
18113 set, that will be sufficient to not affect other bits. */
18114 x
= gen_rtx_NOT (SImode
, mask
);
18115 x
= gen_rtx_IOR (SImode
, x
, val
);
18116 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
18123 /* These will all affect bits outside the field and need
18124 adjustment via MASK within the loop. */
18128 gcc_unreachable ();
18131 /* Prepare to adjust the return value. */
18132 before
= gen_reg_rtx (SImode
);
18134 after
= gen_reg_rtx (SImode
);
18138 mem
= rs6000_pre_atomic_barrier (mem
, model
);
18140 label
= gen_label_rtx ();
18141 emit_label (label
);
18142 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
18144 if (before
== NULL_RTX
)
18145 before
= gen_reg_rtx (mode
);
18147 emit_load_locked (mode
, before
, mem
);
18151 x
= expand_simple_binop (mode
, AND
, before
, val
,
18152 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18153 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
18157 after
= expand_simple_binop (mode
, code
, before
, val
,
18158 after
, 1, OPTAB_LIB_WIDEN
);
18164 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
18165 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18166 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
18169 cond
= gen_reg_rtx (CCmode
);
18170 emit_store_conditional (mode
, cond
, mem
, x
);
18172 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18173 emit_unlikely_jump (x
, label
);
18175 rs6000_post_atomic_barrier (model
);
18180 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
18182 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
18184 else if (orig_after
&& after
!= orig_after
)
18185 emit_move_insn (orig_after
, after
);
18188 /* Emit instructions to move SRC to DST. Called by splitters for
18189 multi-register moves. It will emit at most one instruction for
18190 each register that is accessed; that is, it won't emit li/lis pairs
18191 (or equivalent for 64-bit code). One of SRC or DST must be a hard
18195 rs6000_split_multireg_move (rtx dst
, rtx src
)
18197 /* The register number of the first register being moved. */
18199 /* The mode that is to be moved. */
18200 enum machine_mode mode
;
18201 /* The mode that the move is being done in, and its size. */
18202 enum machine_mode reg_mode
;
18204 /* The number of registers that will be moved. */
18207 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
18208 mode
= GET_MODE (dst
);
18209 nregs
= hard_regno_nregs
[reg
][mode
];
18210 if (FP_REGNO_P (reg
))
18211 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
18212 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
18213 else if (ALTIVEC_REGNO_P (reg
))
18214 reg_mode
= V16QImode
;
18215 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
18218 reg_mode
= word_mode
;
18219 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
18221 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
18223 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
18225 /* Move register range backwards, if we might have destructive
18228 for (i
= nregs
- 1; i
>= 0; i
--)
18229 emit_insn (gen_rtx_SET (VOIDmode
,
18230 simplify_gen_subreg (reg_mode
, dst
, mode
,
18231 i
* reg_mode_size
),
18232 simplify_gen_subreg (reg_mode
, src
, mode
,
18233 i
* reg_mode_size
)));
18239 bool used_update
= false;
18240 rtx restore_basereg
= NULL_RTX
;
18242 if (MEM_P (src
) && INT_REGNO_P (reg
))
18246 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
18247 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
18250 breg
= XEXP (XEXP (src
, 0), 0);
18251 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
18252 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
18253 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
18254 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
18255 src
= replace_equiv_address (src
, breg
);
18257 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
18259 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
18261 rtx basereg
= XEXP (XEXP (src
, 0), 0);
18264 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
18265 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
18266 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
18267 used_update
= true;
18270 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
18271 XEXP (XEXP (src
, 0), 1)));
18272 src
= replace_equiv_address (src
, basereg
);
18276 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
18277 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
18278 src
= replace_equiv_address (src
, basereg
);
18282 breg
= XEXP (src
, 0);
18283 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
18284 breg
= XEXP (breg
, 0);
18286 /* If the base register we are using to address memory is
18287 also a destination reg, then change that register last. */
18289 && REGNO (breg
) >= REGNO (dst
)
18290 && REGNO (breg
) < REGNO (dst
) + nregs
)
18291 j
= REGNO (breg
) - REGNO (dst
);
18293 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
18297 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
18298 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
18301 breg
= XEXP (XEXP (dst
, 0), 0);
18302 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
18303 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
18304 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
18306 /* We have to update the breg before doing the store.
18307 Use store with update, if available. */
18311 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
18312 emit_insn (TARGET_32BIT
18313 ? (TARGET_POWERPC64
18314 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
18315 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
18316 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
18317 used_update
= true;
18320 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
18321 dst
= replace_equiv_address (dst
, breg
);
18323 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
18324 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
18326 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
18328 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
18331 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
18332 emit_insn (gen_rtx_SET (VOIDmode
,
18333 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
18334 used_update
= true;
18337 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
18338 XEXP (XEXP (dst
, 0), 1)));
18339 dst
= replace_equiv_address (dst
, basereg
);
18343 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
18344 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
18345 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
18347 && REG_P (offsetreg
)
18348 && REGNO (basereg
) != REGNO (offsetreg
));
18349 if (REGNO (basereg
) == 0)
18351 rtx tmp
= offsetreg
;
18352 offsetreg
= basereg
;
18355 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
18356 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
18357 dst
= replace_equiv_address (dst
, basereg
);
18360 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
18361 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
18364 for (i
= 0; i
< nregs
; i
++)
18366 /* Calculate index to next subword. */
18371 /* If compiler already emitted move of first word by
18372 store with update, no need to do anything. */
18373 if (j
== 0 && used_update
)
18376 emit_insn (gen_rtx_SET (VOIDmode
,
18377 simplify_gen_subreg (reg_mode
, dst
, mode
,
18378 j
* reg_mode_size
),
18379 simplify_gen_subreg (reg_mode
, src
, mode
,
18380 j
* reg_mode_size
)));
18382 if (restore_basereg
!= NULL_RTX
)
18383 emit_insn (restore_basereg
);
18388 /* This page contains routines that are used to determine what the
18389 function prologue and epilogue code will do and write them out. */
18394 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
18397 /* Return the first fixed-point register that is required to be
18398 saved. 32 if none. */
18401 first_reg_to_save (void)
18405 /* Find lowest numbered live register. */
18406 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
18407 if (save_reg_p (first_reg
))
18410 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
18411 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
18412 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
18413 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
18414 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
18415 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
18419 && crtl
->uses_pic_offset_table
18420 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
18421 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
18427 /* Similar, for FP regs. */
18430 first_fp_reg_to_save (void)
18434 /* Find lowest numbered live register. */
18435 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
18436 if (save_reg_p (first_reg
))
18442 /* Similar, for AltiVec regs. */
18445 first_altivec_reg_to_save (void)
18449 /* Stack frame remains as is unless we are in AltiVec ABI. */
18450 if (! TARGET_ALTIVEC_ABI
)
18451 return LAST_ALTIVEC_REGNO
+ 1;
18453 /* On Darwin, the unwind routines are compiled without
18454 TARGET_ALTIVEC, and use save_world to save/restore the
18455 altivec registers when necessary. */
18456 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
18457 && ! TARGET_ALTIVEC
)
18458 return FIRST_ALTIVEC_REGNO
+ 20;
18460 /* Find lowest numbered live register. */
18461 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
18462 if (save_reg_p (i
))
18468 /* Return a 32-bit mask of the AltiVec registers we need to set in
18469 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
18470 the 32-bit word is 0. */
18472 static unsigned int
18473 compute_vrsave_mask (void)
18475 unsigned int i
, mask
= 0;
18477 /* On Darwin, the unwind routines are compiled without
18478 TARGET_ALTIVEC, and use save_world to save/restore the
18479 call-saved altivec registers when necessary. */
18480 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
18481 && ! TARGET_ALTIVEC
)
18484 /* First, find out if we use _any_ altivec registers. */
18485 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
18486 if (df_regs_ever_live_p (i
))
18487 mask
|= ALTIVEC_REG_BIT (i
);
18492 /* Next, remove the argument registers from the set. These must
18493 be in the VRSAVE mask set by the caller, so we don't need to add
18494 them in again. More importantly, the mask we compute here is
18495 used to generate CLOBBERs in the set_vrsave insn, and we do not
18496 wish the argument registers to die. */
18497 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
18498 mask
&= ~ALTIVEC_REG_BIT (i
);
18500 /* Similarly, remove the return value from the set. */
18503 diddle_return_value (is_altivec_return_reg
, &yes
);
18505 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
18511 /* For a very restricted set of circumstances, we can cut down the
18512 size of prologues/epilogues by calling our own save/restore-the-world
18516 compute_save_world_info (rs6000_stack_t
*info_ptr
)
18518 info_ptr
->world_save_p
= 1;
18519 info_ptr
->world_save_p
18520 = (WORLD_SAVE_P (info_ptr
)
18521 && DEFAULT_ABI
== ABI_DARWIN
18522 && !cfun
->has_nonlocal_label
18523 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
18524 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
18525 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
18526 && info_ptr
->cr_save_p
);
18528 /* This will not work in conjunction with sibcalls. Make sure there
18529 are none. (This check is expensive, but seldom executed.) */
18530 if (WORLD_SAVE_P (info_ptr
))
18533 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
18534 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
18536 info_ptr
->world_save_p
= 0;
18541 if (WORLD_SAVE_P (info_ptr
))
18543 /* Even if we're not touching VRsave, make sure there's room on the
18544 stack for it, if it looks like we're calling SAVE_WORLD, which
18545 will attempt to save it. */
18546 info_ptr
->vrsave_size
= 4;
18548 /* If we are going to save the world, we need to save the link register too. */
18549 info_ptr
->lr_save_p
= 1;
18551 /* "Save" the VRsave register too if we're saving the world. */
18552 if (info_ptr
->vrsave_mask
== 0)
18553 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
18555 /* Because the Darwin register save/restore routines only handle
18556 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
18558 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
18559 && (info_ptr
->first_altivec_reg_save
18560 >= FIRST_SAVED_ALTIVEC_REGNO
));
18567 is_altivec_return_reg (rtx reg
, void *xyes
)
18569 bool *yes
= (bool *) xyes
;
18570 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
18575 /* Look for user-defined global regs in the range FIRST to LAST-1.
18576 We should not restore these, and so cannot use lmw or out-of-line
18577 restore functions if there are any. We also can't save them
18578 (well, emit frame notes for them), because frame unwinding during
18579 exception handling will restore saved registers. */
18582 global_regs_p (unsigned first
, unsigned last
)
18584 while (first
< last
)
18585 if (global_regs
[first
++])
18590 /* Determine the strategy for savings/restoring registers. */
18593 SAVRES_MULTIPLE
= 0x1,
18594 SAVE_INLINE_FPRS
= 0x2,
18595 SAVE_INLINE_GPRS
= 0x4,
18596 REST_INLINE_FPRS
= 0x8,
18597 REST_INLINE_GPRS
= 0x10,
18598 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
18599 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
18600 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
18601 SAVE_INLINE_VRS
= 0x100,
18602 REST_INLINE_VRS
= 0x200
18606 rs6000_savres_strategy (rs6000_stack_t
*info
,
18607 bool using_static_chain_p
)
18612 if (TARGET_MULTIPLE
18613 && !TARGET_POWERPC64
18614 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
18615 && info
->first_gp_reg_save
< 31
18616 && !global_regs_p (info
->first_gp_reg_save
, 32))
18617 strategy
|= SAVRES_MULTIPLE
;
18619 if (crtl
->calls_eh_return
18620 || cfun
->machine
->ra_need_lr
)
18621 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
18622 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
18623 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
18625 if (info
->first_fp_reg_save
== 64
18626 /* The out-of-line FP routines use double-precision stores;
18627 we can't use those routines if we don't have such stores. */
18628 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
18629 || global_regs_p (info
->first_fp_reg_save
, 64))
18630 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
18632 if (info
->first_gp_reg_save
== 32
18633 || (!(strategy
& SAVRES_MULTIPLE
)
18634 && global_regs_p (info
->first_gp_reg_save
, 32)))
18635 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
18637 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
18638 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
18639 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
18641 /* Define cutoff for using out-of-line functions to save registers. */
18642 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
18644 if (!optimize_size
)
18646 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
18647 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
18648 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
18652 /* Prefer out-of-line restore if it will exit. */
18653 if (info
->first_fp_reg_save
> 61)
18654 strategy
|= SAVE_INLINE_FPRS
;
18655 if (info
->first_gp_reg_save
> 29)
18657 if (info
->first_fp_reg_save
== 64)
18658 strategy
|= SAVE_INLINE_GPRS
;
18660 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
18662 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
18663 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
18666 else if (DEFAULT_ABI
== ABI_DARWIN
)
18668 if (info
->first_fp_reg_save
> 60)
18669 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
18670 if (info
->first_gp_reg_save
> 29)
18671 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
18672 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
18676 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
);
18677 if (info
->first_fp_reg_save
> 61)
18678 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
18679 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
18680 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
18683 /* Don't bother to try to save things out-of-line if r11 is occupied
18684 by the static chain. It would require too much fiddling and the
18685 static chain is rarely used anyway. FPRs are saved w.r.t the stack
18686 pointer on Darwin, and AIX uses r1 or r12. */
18687 if (using_static_chain_p
&& DEFAULT_ABI
!= ABI_AIX
)
18688 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
18690 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
18692 /* We can only use the out-of-line routines to restore if we've
18693 saved all the registers from first_fp_reg_save in the prologue.
18694 Otherwise, we risk loading garbage. */
18695 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
18699 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
18700 if (!save_reg_p (i
))
18702 strategy
|= REST_INLINE_FPRS
;
18707 /* If we are going to use store multiple, then don't even bother
18708 with the out-of-line routines, since the store-multiple
18709 instruction will always be smaller. */
18710 if ((strategy
& SAVRES_MULTIPLE
))
18711 strategy
|= SAVE_INLINE_GPRS
;
18713 /* info->lr_save_p isn't yet set if the only reason lr needs to be
18714 saved is an out-of-line save or restore. Set up the value for
18715 the next test (excluding out-of-line gpr restore). */
18716 lr_save_p
= (info
->lr_save_p
18717 || !(strategy
& SAVE_INLINE_GPRS
)
18718 || !(strategy
& SAVE_INLINE_FPRS
)
18719 || !(strategy
& SAVE_INLINE_VRS
)
18720 || !(strategy
& REST_INLINE_FPRS
)
18721 || !(strategy
& REST_INLINE_VRS
));
18723 /* The situation is more complicated with load multiple. We'd
18724 prefer to use the out-of-line routines for restores, since the
18725 "exit" out-of-line routines can handle the restore of LR and the
18726 frame teardown. However if doesn't make sense to use the
18727 out-of-line routine if that is the only reason we'd need to save
18728 LR, and we can't use the "exit" out-of-line gpr restore if we
18729 have saved some fprs; In those cases it is advantageous to use
18730 load multiple when available. */
18731 if ((strategy
& SAVRES_MULTIPLE
)
18733 || info
->first_fp_reg_save
!= 64))
18734 strategy
|= REST_INLINE_GPRS
;
18736 /* Saving CR interferes with the exit routines used on the SPE, so
18739 && info
->spe_64bit_regs_used
18740 && info
->cr_save_p
)
18741 strategy
|= REST_INLINE_GPRS
;
18743 /* We can only use load multiple or the out-of-line routines to
18744 restore if we've used store multiple or out-of-line routines
18745 in the prologue, i.e. if we've saved all the registers from
18746 first_gp_reg_save. Otherwise, we risk loading garbage. */
18747 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
18748 == SAVE_INLINE_GPRS
)
18752 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
18753 if (!save_reg_p (i
))
18755 strategy
|= REST_INLINE_GPRS
;
18760 if (TARGET_ELF
&& TARGET_64BIT
)
18762 if (!(strategy
& SAVE_INLINE_FPRS
))
18763 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
18764 else if (!(strategy
& SAVE_INLINE_GPRS
)
18765 && info
->first_fp_reg_save
== 64)
18766 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
18768 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
18769 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
18771 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
18772 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
18777 /* Calculate the stack information for the current function. This is
18778 complicated by having two separate calling sequences, the AIX calling
18779 sequence and the V.4 calling sequence.
18781 AIX (and Darwin/Mac OS X) stack frames look like:
18783 SP----> +---------------------------------------+
18784 | back chain to caller | 0 0
18785 +---------------------------------------+
18786 | saved CR | 4 8 (8-11)
18787 +---------------------------------------+
18789 +---------------------------------------+
18790 | reserved for compilers | 12 24
18791 +---------------------------------------+
18792 | reserved for binders | 16 32
18793 +---------------------------------------+
18794 | saved TOC pointer | 20 40
18795 +---------------------------------------+
18796 | Parameter save area (P) | 24 48
18797 +---------------------------------------+
18798 | Alloca space (A) | 24+P etc.
18799 +---------------------------------------+
18800 | Local variable space (L) | 24+P+A
18801 +---------------------------------------+
18802 | Float/int conversion temporary (X) | 24+P+A+L
18803 +---------------------------------------+
18804 | Save area for AltiVec registers (W) | 24+P+A+L+X
18805 +---------------------------------------+
18806 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
18807 +---------------------------------------+
18808 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
18809 +---------------------------------------+
18810 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
18811 +---------------------------------------+
18812 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
18813 +---------------------------------------+
18814 old SP->| back chain to caller's caller |
18815 +---------------------------------------+
18817 The required alignment for AIX configurations is two words (i.e., 8
18821 V.4 stack frames look like:
18823 SP----> +---------------------------------------+
18824 | back chain to caller | 0
18825 +---------------------------------------+
18826 | caller's saved LR | 4
18827 +---------------------------------------+
18828 | Parameter save area (P) | 8
18829 +---------------------------------------+
18830 | Alloca space (A) | 8+P
18831 +---------------------------------------+
18832 | Varargs save area (V) | 8+P+A
18833 +---------------------------------------+
18834 | Local variable space (L) | 8+P+A+V
18835 +---------------------------------------+
18836 | Float/int conversion temporary (X) | 8+P+A+V+L
18837 +---------------------------------------+
18838 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
18839 +---------------------------------------+
18840 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
18841 +---------------------------------------+
18842 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
18843 +---------------------------------------+
18844 | SPE: area for 64-bit GP registers |
18845 +---------------------------------------+
18846 | SPE alignment padding |
18847 +---------------------------------------+
18848 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
18849 +---------------------------------------+
18850 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
18851 +---------------------------------------+
18852 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
18853 +---------------------------------------+
18854 old SP->| back chain to caller's caller |
18855 +---------------------------------------+
18857 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
18858 given. (But note below and in sysv4.h that we require only 8 and
18859 may round up the size of our stack frame anyways. The historical
18860 reason is early versions of powerpc-linux which didn't properly
18861 align the stack at program startup. A happy side-effect is that
18862 -mno-eabi libraries can be used with -meabi programs.)
18864 The EABI configuration defaults to the V.4 layout. However,
18865 the stack alignment requirements may differ. If -mno-eabi is not
18866 given, the required stack alignment is 8 bytes; if -mno-eabi is
18867 given, the required alignment is 16 bytes. (But see V.4 comment
18870 #ifndef ABI_STACK_BOUNDARY
18871 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
18874 static rs6000_stack_t
*
18875 rs6000_stack_info (void)
18877 rs6000_stack_t
*info_ptr
= &stack_info
;
18878 int reg_size
= TARGET_32BIT
? 4 : 8;
18882 HOST_WIDE_INT non_fixed_size
;
18883 bool using_static_chain_p
;
18885 if (reload_completed
&& info_ptr
->reload_completed
)
18888 memset (info_ptr
, 0, sizeof (*info_ptr
));
18889 info_ptr
->reload_completed
= reload_completed
;
18893 /* Cache value so we don't rescan instruction chain over and over. */
18894 if (cfun
->machine
->insn_chain_scanned_p
== 0)
18895 cfun
->machine
->insn_chain_scanned_p
18896 = spe_func_has_64bit_regs_p () + 1;
18897 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
18900 /* Select which calling sequence. */
18901 info_ptr
->abi
= DEFAULT_ABI
;
18903 /* Calculate which registers need to be saved & save area size. */
18904 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
18905 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
18906 even if it currently looks like we won't. Reload may need it to
18907 get at a constant; if so, it will have already created a constant
18908 pool entry for it. */
18909 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
18910 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
18911 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
18912 && crtl
->uses_const_pool
18913 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
18914 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
18916 first_gp
= info_ptr
->first_gp_reg_save
;
18918 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
18920 /* For the SPE, we have an additional upper 32-bits on each GPR.
18921 Ideally we should save the entire 64-bits only when the upper
18922 half is used in SIMD instructions. Since we only record
18923 registers live (not the size they are used in), this proves
18924 difficult because we'd have to traverse the instruction chain at
18925 the right time, taking reload into account. This is a real pain,
18926 so we opt to save the GPRs in 64-bits always if but one register
18927 gets used in 64-bits. Otherwise, all the registers in the frame
18928 get saved in 32-bits.
18930 So... since when we save all GPRs (except the SP) in 64-bits, the
18931 traditional GP save area will be empty. */
18932 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
18933 info_ptr
->gp_size
= 0;
18935 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
18936 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
18938 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
18939 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
18940 - info_ptr
->first_altivec_reg_save
);
18942 /* Does this function call anything? */
18943 info_ptr
->calls_p
= (! crtl
->is_leaf
18944 || cfun
->machine
->ra_needs_full_frame
);
18946 /* Determine if we need to save the condition code registers. */
18947 if (df_regs_ever_live_p (CR2_REGNO
)
18948 || df_regs_ever_live_p (CR3_REGNO
)
18949 || df_regs_ever_live_p (CR4_REGNO
))
18951 info_ptr
->cr_save_p
= 1;
18952 if (DEFAULT_ABI
== ABI_V4
)
18953 info_ptr
->cr_size
= reg_size
;
18956 /* If the current function calls __builtin_eh_return, then we need
18957 to allocate stack space for registers that will hold data for
18958 the exception handler. */
18959 if (crtl
->calls_eh_return
)
18962 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
18965 /* SPE saves EH registers in 64-bits. */
18966 ehrd_size
= i
* (TARGET_SPE_ABI
18967 && info_ptr
->spe_64bit_regs_used
!= 0
18968 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
18973 /* Determine various sizes. */
18974 info_ptr
->reg_size
= reg_size
;
18975 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
18976 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
18977 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
18978 TARGET_ALTIVEC
? 16 : 8);
18979 if (FRAME_GROWS_DOWNWARD
)
18980 info_ptr
->vars_size
18981 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
18982 + info_ptr
->parm_size
,
18983 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
18984 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
18985 + info_ptr
->parm_size
);
18987 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
18988 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
18990 info_ptr
->spe_gp_size
= 0;
18992 if (TARGET_ALTIVEC_ABI
)
18993 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
18995 info_ptr
->vrsave_mask
= 0;
18997 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
18998 info_ptr
->vrsave_size
= 4;
19000 info_ptr
->vrsave_size
= 0;
19002 compute_save_world_info (info_ptr
);
19004 /* Calculate the offsets. */
19005 switch (DEFAULT_ABI
)
19009 gcc_unreachable ();
19013 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
19014 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
19016 if (TARGET_ALTIVEC_ABI
)
19018 info_ptr
->vrsave_save_offset
19019 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
19021 /* Align stack so vector save area is on a quadword boundary.
19022 The padding goes above the vectors. */
19023 if (info_ptr
->altivec_size
!= 0)
19024 info_ptr
->altivec_padding_size
19025 = info_ptr
->vrsave_save_offset
& 0xF;
19027 info_ptr
->altivec_padding_size
= 0;
19029 info_ptr
->altivec_save_offset
19030 = info_ptr
->vrsave_save_offset
19031 - info_ptr
->altivec_padding_size
19032 - info_ptr
->altivec_size
;
19033 gcc_assert (info_ptr
->altivec_size
== 0
19034 || info_ptr
->altivec_save_offset
% 16 == 0);
19036 /* Adjust for AltiVec case. */
19037 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
19040 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
19041 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
19042 info_ptr
->lr_save_offset
= 2*reg_size
;
19046 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
19047 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
19048 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
19050 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
19052 /* Align stack so SPE GPR save area is aligned on a
19053 double-word boundary. */
19054 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
19055 info_ptr
->spe_padding_size
19056 = 8 - (-info_ptr
->cr_save_offset
% 8);
19058 info_ptr
->spe_padding_size
= 0;
19060 info_ptr
->spe_gp_save_offset
19061 = info_ptr
->cr_save_offset
19062 - info_ptr
->spe_padding_size
19063 - info_ptr
->spe_gp_size
;
19065 /* Adjust for SPE case. */
19066 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
19068 else if (TARGET_ALTIVEC_ABI
)
19070 info_ptr
->vrsave_save_offset
19071 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
19073 /* Align stack so vector save area is on a quadword boundary. */
19074 if (info_ptr
->altivec_size
!= 0)
19075 info_ptr
->altivec_padding_size
19076 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
19078 info_ptr
->altivec_padding_size
= 0;
19080 info_ptr
->altivec_save_offset
19081 = info_ptr
->vrsave_save_offset
19082 - info_ptr
->altivec_padding_size
19083 - info_ptr
->altivec_size
;
19085 /* Adjust for AltiVec case. */
19086 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
19089 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
19090 info_ptr
->ehrd_offset
-= ehrd_size
;
19091 info_ptr
->lr_save_offset
= reg_size
;
19095 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
19096 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
19097 + info_ptr
->gp_size
19098 + info_ptr
->altivec_size
19099 + info_ptr
->altivec_padding_size
19100 + info_ptr
->spe_gp_size
19101 + info_ptr
->spe_padding_size
19103 + info_ptr
->cr_size
19104 + info_ptr
->vrsave_size
,
19107 non_fixed_size
= (info_ptr
->vars_size
19108 + info_ptr
->parm_size
19109 + info_ptr
->save_size
);
19111 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
19112 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
19114 /* Determine if we need to save the link register. */
19115 if (info_ptr
->calls_p
19116 || (DEFAULT_ABI
== ABI_AIX
19118 && !TARGET_PROFILE_KERNEL
)
19119 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
19120 #ifdef TARGET_RELOCATABLE
19121 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
19123 || rs6000_ra_ever_killed ())
19124 info_ptr
->lr_save_p
= 1;
19126 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
19127 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
19128 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
19129 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
19130 using_static_chain_p
);
19132 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
19133 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
19134 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
19135 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
19136 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
19137 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
19138 info_ptr
->lr_save_p
= 1;
19140 if (info_ptr
->lr_save_p
)
19141 df_set_regs_ever_live (LR_REGNO
, true);
19143 /* Determine if we need to allocate any stack frame:
19145 For AIX we need to push the stack if a frame pointer is needed
19146 (because the stack might be dynamically adjusted), if we are
19147 debugging, if we make calls, or if the sum of fp_save, gp_save,
19148 and local variables are more than the space needed to save all
19149 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
19150 + 18*8 = 288 (GPR13 reserved).
19152 For V.4 we don't have the stack cushion that AIX uses, but assume
19153 that the debugger can handle stackless frames. */
19155 if (info_ptr
->calls_p
)
19156 info_ptr
->push_p
= 1;
19158 else if (DEFAULT_ABI
== ABI_V4
)
19159 info_ptr
->push_p
= non_fixed_size
!= 0;
19161 else if (frame_pointer_needed
)
19162 info_ptr
->push_p
= 1;
19164 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
19165 info_ptr
->push_p
= 1;
19168 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
19170 /* Zero offsets if we're not saving those registers. */
19171 if (info_ptr
->fp_size
== 0)
19172 info_ptr
->fp_save_offset
= 0;
19174 if (info_ptr
->gp_size
== 0)
19175 info_ptr
->gp_save_offset
= 0;
19177 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
19178 info_ptr
->altivec_save_offset
= 0;
19180 /* Zero VRSAVE offset if not saved and restored. */
19181 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
19182 info_ptr
->vrsave_save_offset
= 0;
19184 if (! TARGET_SPE_ABI
19185 || info_ptr
->spe_64bit_regs_used
== 0
19186 || info_ptr
->spe_gp_size
== 0)
19187 info_ptr
->spe_gp_save_offset
= 0;
19189 if (! info_ptr
->lr_save_p
)
19190 info_ptr
->lr_save_offset
= 0;
19192 if (! info_ptr
->cr_save_p
)
19193 info_ptr
->cr_save_offset
= 0;
19198 /* Return true if the current function uses any GPRs in 64-bit SIMD
19202 spe_func_has_64bit_regs_p (void)
19206 /* Functions that save and restore all the call-saved registers will
19207 need to save/restore the registers in 64-bits. */
19208 if (crtl
->calls_eh_return
19209 || cfun
->calls_setjmp
19210 || crtl
->has_nonlocal_goto
)
19213 insns
= get_insns ();
19215 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
19221 /* FIXME: This should be implemented with attributes...
19223 (set_attr "spe64" "true")....then,
19224 if (get_spe64(insn)) return true;
19226 It's the only reliable way to do the stuff below. */
19228 i
= PATTERN (insn
);
19229 if (GET_CODE (i
) == SET
)
19231 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
19233 if (SPE_VECTOR_MODE (mode
))
19235 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
19245 debug_stack_info (rs6000_stack_t
*info
)
19247 const char *abi_string
;
19250 info
= rs6000_stack_info ();
19252 fprintf (stderr
, "\nStack information for function %s:\n",
19253 ((current_function_decl
&& DECL_NAME (current_function_decl
))
19254 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
19259 default: abi_string
= "Unknown"; break;
19260 case ABI_NONE
: abi_string
= "NONE"; break;
19261 case ABI_AIX
: abi_string
= "AIX"; break;
19262 case ABI_DARWIN
: abi_string
= "Darwin"; break;
19263 case ABI_V4
: abi_string
= "V.4"; break;
19266 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
19268 if (TARGET_ALTIVEC_ABI
)
19269 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
19271 if (TARGET_SPE_ABI
)
19272 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
19274 if (info
->first_gp_reg_save
!= 32)
19275 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
19277 if (info
->first_fp_reg_save
!= 64)
19278 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
19280 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
19281 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
19282 info
->first_altivec_reg_save
);
19284 if (info
->lr_save_p
)
19285 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
19287 if (info
->cr_save_p
)
19288 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
19290 if (info
->vrsave_mask
)
19291 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
19294 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
19297 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
19299 if (info
->gp_save_offset
)
19300 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
19302 if (info
->fp_save_offset
)
19303 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
19305 if (info
->altivec_save_offset
)
19306 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
19307 info
->altivec_save_offset
);
19309 if (info
->spe_gp_save_offset
)
19310 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
19311 info
->spe_gp_save_offset
);
19313 if (info
->vrsave_save_offset
)
19314 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
19315 info
->vrsave_save_offset
);
19317 if (info
->lr_save_offset
)
19318 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
19320 if (info
->cr_save_offset
)
19321 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
19323 if (info
->varargs_save_offset
)
19324 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
19326 if (info
->total_size
)
19327 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
19330 if (info
->vars_size
)
19331 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
19334 if (info
->parm_size
)
19335 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
19337 if (info
->fixed_size
)
19338 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
19341 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
19343 if (info
->spe_gp_size
)
19344 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
19347 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
19349 if (info
->altivec_size
)
19350 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
19352 if (info
->vrsave_size
)
19353 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
19355 if (info
->altivec_padding_size
)
19356 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
19357 info
->altivec_padding_size
);
19359 if (info
->spe_padding_size
)
19360 fprintf (stderr
, "\tspe_padding_size = %5d\n",
19361 info
->spe_padding_size
);
19364 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
19366 if (info
->save_size
)
19367 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
19369 if (info
->reg_size
!= 4)
19370 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
19372 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
19374 fprintf (stderr
, "\n");
19378 rs6000_return_addr (int count
, rtx frame
)
19380 /* Currently we don't optimize very well between prolog and body
19381 code and for PIC code the code can be actually quite bad, so
19382 don't try to be too clever here. */
19383 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
19385 cfun
->machine
->ra_needs_full_frame
= 1;
19392 plus_constant (Pmode
,
19394 (gen_rtx_MEM (Pmode
,
19395 memory_address (Pmode
, frame
))),
19396 RETURN_ADDRESS_OFFSET
)));
19399 cfun
->machine
->ra_need_lr
= 1;
19400 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
19403 /* Say whether a function is a candidate for sibcall handling or not. */
19406 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
19411 fntype
= TREE_TYPE (decl
);
19413 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
19415 /* We can't do it if the called function has more vector parameters
19416 than the current function; there's nowhere to put the VRsave code. */
19417 if (TARGET_ALTIVEC_ABI
19418 && TARGET_ALTIVEC_VRSAVE
19419 && !(decl
&& decl
== current_function_decl
))
19421 function_args_iterator args_iter
;
19425 /* Functions with vector parameters are required to have a
19426 prototype, so the argument type info must be available
19428 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
19429 if (TREE_CODE (type
) == VECTOR_TYPE
19430 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
19433 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
19434 if (TREE_CODE (type
) == VECTOR_TYPE
19435 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
19442 /* Under the AIX ABI we can't allow calls to non-local functions,
19443 because the callee may have a different TOC pointer to the
19444 caller and there's no way to ensure we restore the TOC when we
19445 return. With the secure-plt SYSV ABI we can't make non-local
19446 calls when -fpic/PIC because the plt call stubs use r30. */
19447 if (DEFAULT_ABI
== ABI_DARWIN
19448 || (DEFAULT_ABI
== ABI_AIX
19450 && !DECL_EXTERNAL (decl
)
19451 && (*targetm
.binds_local_p
) (decl
))
19452 || (DEFAULT_ABI
== ABI_V4
19453 && (!TARGET_SECURE_PLT
19456 && (*targetm
.binds_local_p
) (decl
)))))
19458 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
19460 if (!lookup_attribute ("longcall", attr_list
)
19461 || lookup_attribute ("shortcall", attr_list
))
19469 rs6000_ra_ever_killed (void)
19475 if (cfun
->is_thunk
)
19478 if (cfun
->machine
->lr_save_state
)
19479 return cfun
->machine
->lr_save_state
- 1;
19481 /* regs_ever_live has LR marked as used if any sibcalls are present,
19482 but this should not force saving and restoring in the
19483 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
19484 clobbers LR, so that is inappropriate. */
19486 /* Also, the prologue can generate a store into LR that
19487 doesn't really count, like this:
19490 bcl to set PIC register
19494 When we're called from the epilogue, we need to avoid counting
19495 this as a store. */
19497 push_topmost_sequence ();
19498 top
= get_insns ();
19499 pop_topmost_sequence ();
19500 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
19502 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
19508 if (!SIBLING_CALL_P (insn
))
19511 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
19513 else if (set_of (reg
, insn
) != NULL_RTX
19514 && !prologue_epilogue_contains (insn
))
19521 /* Emit instructions needed to load the TOC register.
19522 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
19523 a constant pool; or for SVR4 -fpic. */
19526 rs6000_emit_load_toc_table (int fromprolog
)
19529 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
19531 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
19534 rtx lab
, tmp1
, tmp2
, got
;
19536 lab
= gen_label_rtx ();
19537 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
19538 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
19540 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
19542 got
= rs6000_got_sym ();
19543 tmp1
= tmp2
= dest
;
19546 tmp1
= gen_reg_rtx (Pmode
);
19547 tmp2
= gen_reg_rtx (Pmode
);
19549 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
19550 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
19551 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
19552 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
19554 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
19556 emit_insn (gen_load_toc_v4_pic_si ());
19557 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
19559 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
19562 rtx temp0
= (fromprolog
19563 ? gen_rtx_REG (Pmode
, 0)
19564 : gen_reg_rtx (Pmode
));
19570 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
19571 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
19573 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
19574 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
19576 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
19577 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
19578 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
19584 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
19585 lab
= gen_label_rtx ();
19586 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
19587 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
19588 if (TARGET_LINK_STACK
)
19589 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
19590 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
19592 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
19594 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
19596 /* This is for AIX code running in non-PIC ELF32. */
19599 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
19600 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
19602 emit_insn (gen_elf_high (dest
, realsym
));
19603 emit_insn (gen_elf_low (dest
, dest
, realsym
));
19607 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
19610 emit_insn (gen_load_toc_aix_si (dest
));
19612 emit_insn (gen_load_toc_aix_di (dest
));
19616 /* Emit instructions to restore the link register after determining where
19617 its value has been stored. */
19620 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
19622 rs6000_stack_t
*info
= rs6000_stack_info ();
19625 operands
[0] = source
;
19626 operands
[1] = scratch
;
19628 if (info
->lr_save_p
)
19630 rtx frame_rtx
= stack_pointer_rtx
;
19631 HOST_WIDE_INT sp_offset
= 0;
19634 if (frame_pointer_needed
19635 || cfun
->calls_alloca
19636 || info
->total_size
> 32767)
19638 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
19639 emit_move_insn (operands
[1], tmp
);
19640 frame_rtx
= operands
[1];
19642 else if (info
->push_p
)
19643 sp_offset
= info
->total_size
;
19645 tmp
= plus_constant (Pmode
, frame_rtx
,
19646 info
->lr_save_offset
+ sp_offset
);
19647 tmp
= gen_frame_mem (Pmode
, tmp
);
19648 emit_move_insn (tmp
, operands
[0]);
19651 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
19653 /* Freeze lr_save_p. We've just emitted rtl that depends on the
19654 state of lr_save_p so any change from here on would be a bug. In
19655 particular, stop rs6000_ra_ever_killed from considering the SET
19656 of lr we may have added just above. */
19657 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
19660 static GTY(()) alias_set_type set
= -1;
19663 get_TOC_alias_set (void)
19666 set
= new_alias_set ();
19670 /* This returns nonzero if the current function uses the TOC. This is
19671 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
19672 is generated by the ABI_V4 load_toc_* patterns. */
19679 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
19682 rtx pat
= PATTERN (insn
);
19685 if (GET_CODE (pat
) == PARALLEL
)
19686 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19688 rtx sub
= XVECEXP (pat
, 0, i
);
19689 if (GET_CODE (sub
) == USE
)
19691 sub
= XEXP (sub
, 0);
19692 if (GET_CODE (sub
) == UNSPEC
19693 && XINT (sub
, 1) == UNSPEC_TOC
)
19703 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
19705 rtx tocrel
, tocreg
, hi
;
19707 if (TARGET_DEBUG_ADDR
)
19709 if (GET_CODE (symbol
) == SYMBOL_REF
)
19710 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
19714 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
19715 GET_RTX_NAME (GET_CODE (symbol
)));
19716 debug_rtx (symbol
);
19720 if (!can_create_pseudo_p ())
19721 df_set_regs_ever_live (TOC_REGISTER
, true);
19723 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
19724 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
19725 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
19728 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
19729 if (largetoc_reg
!= NULL
)
19731 emit_move_insn (largetoc_reg
, hi
);
19734 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
19737 /* Issue assembly directives that create a reference to the given DWARF
19738 FRAME_TABLE_LABEL from the current function section. */
19740 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
19742 fprintf (asm_out_file
, "\t.ref %s\n",
19743 (* targetm
.strip_name_encoding
) (frame_table_label
));
19746 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
19747 and the change to the stack pointer. */
19750 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
19757 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
19758 if (hard_frame_needed
)
19759 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
19760 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
19761 || (hard_frame_needed
19762 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
19765 p
= rtvec_alloc (i
);
19768 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
19769 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
19772 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
19775 /* Emit the correct code for allocating stack space, as insns.
19776 If COPY_REG, make sure a copy of the old frame is left there.
19777 The generated code may use hard register 0 as a temporary. */
19780 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
19783 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
19784 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
19785 rtx todec
= gen_int_mode (-size
, Pmode
);
19788 if (INTVAL (todec
) != -size
)
19790 warning (0, "stack frame too large");
19791 emit_insn (gen_trap ());
19795 if (crtl
->limit_stack
)
19797 if (REG_P (stack_limit_rtx
)
19798 && REGNO (stack_limit_rtx
) > 1
19799 && REGNO (stack_limit_rtx
) <= 31)
19801 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
19802 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
19805 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
19807 && DEFAULT_ABI
== ABI_V4
)
19809 rtx toload
= gen_rtx_CONST (VOIDmode
,
19810 gen_rtx_PLUS (Pmode
,
19814 emit_insn (gen_elf_high (tmp_reg
, toload
));
19815 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
19816 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
19820 warning (0, "stack limit expression is not supported");
19826 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
19828 emit_move_insn (copy_reg
, stack_reg
);
19833 /* Need a note here so that try_split doesn't get confused. */
19834 if (get_last_insn () == NULL_RTX
)
19835 emit_note (NOTE_INSN_DELETED
);
19836 insn
= emit_move_insn (tmp_reg
, todec
);
19837 try_split (PATTERN (insn
), insn
, 0);
19841 insn
= emit_insn (TARGET_32BIT
19842 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
19844 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
19845 todec
, stack_reg
));
19846 /* Since we didn't use gen_frame_mem to generate the MEM, grab
19847 it now and set the alias set/attributes. The above gen_*_update
19848 calls will generate a PARALLEL with the MEM set being the first
19850 par
= PATTERN (insn
);
19851 gcc_assert (GET_CODE (par
) == PARALLEL
);
19852 set
= XVECEXP (par
, 0, 0);
19853 gcc_assert (GET_CODE (set
) == SET
);
19854 mem
= SET_DEST (set
);
19855 gcc_assert (MEM_P (mem
));
19856 MEM_NOTRAP_P (mem
) = 1;
19857 set_mem_alias_set (mem
, get_frame_alias_set ());
19859 RTX_FRAME_RELATED_P (insn
) = 1;
19860 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
19861 gen_rtx_SET (VOIDmode
, stack_reg
,
19862 gen_rtx_PLUS (Pmode
, stack_reg
,
19863 GEN_INT (-size
))));
19866 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
19868 #if PROBE_INTERVAL > 32768
19869 #error Cannot use indexed addressing mode for stack probing
19872 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
19873 inclusive. These are offsets from the current stack pointer. */
19876 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
19878 /* See if we have a constant small number of probes to generate. If so,
19879 that's the easy case. */
19880 if (first
+ size
<= 32768)
19884 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
19885 it exceeds SIZE. If only one probe is needed, this will not
19886 generate any code. Then probe at FIRST + SIZE. */
19887 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
19888 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
19891 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
19895 /* Otherwise, do the same as above, but in a loop. Note that we must be
19896 extra careful with variables wrapping around because we might be at
19897 the very top (or the very bottom) of the address space and we have
19898 to be able to handle this case properly; in particular, we use an
19899 equality test for the loop condition. */
19902 HOST_WIDE_INT rounded_size
;
19903 rtx r12
= gen_rtx_REG (Pmode
, 12);
19904 rtx r0
= gen_rtx_REG (Pmode
, 0);
19906 /* Sanity check for the addressing mode we're going to use. */
19907 gcc_assert (first
<= 32768);
19909 /* Step 1: round SIZE to the previous multiple of the interval. */
19911 rounded_size
= size
& -PROBE_INTERVAL
;
19914 /* Step 2: compute initial and final value of the loop counter. */
19916 /* TEST_ADDR = SP + FIRST. */
19917 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
19918 plus_constant (Pmode
, stack_pointer_rtx
,
19921 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
19922 if (rounded_size
> 32768)
19924 emit_move_insn (r0
, GEN_INT (-rounded_size
));
19925 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
19926 gen_rtx_PLUS (Pmode
, r12
, r0
)));
19929 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
19930 plus_constant (Pmode
, r12
, -rounded_size
)));
19933 /* Step 3: the loop
19935 while (TEST_ADDR != LAST_ADDR)
19937 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
19941 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
19942 until it is equal to ROUNDED_SIZE. */
19945 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
19947 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
19950 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
19951 that SIZE is equal to ROUNDED_SIZE. */
19953 if (size
!= rounded_size
)
19954 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
19958 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
19959 absolute addresses. */
19962 output_probe_stack_range (rtx reg1
, rtx reg2
)
19964 static int labelno
= 0;
19965 char loop_lab
[32], end_lab
[32];
19968 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
19969 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
19971 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
19973 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
19977 output_asm_insn ("cmpd 0,%0,%1", xops
);
19979 output_asm_insn ("cmpw 0,%0,%1", xops
);
19981 fputs ("\tbeq 0,", asm_out_file
);
19982 assemble_name_raw (asm_out_file
, end_lab
);
19983 fputc ('\n', asm_out_file
);
19985 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
19986 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
19987 output_asm_insn ("addi %0,%0,%1", xops
);
19989 /* Probe at TEST_ADDR and branch. */
19990 xops
[1] = gen_rtx_REG (Pmode
, 0);
19991 output_asm_insn ("stw %1,0(%0)", xops
);
19992 fprintf (asm_out_file
, "\tb ");
19993 assemble_name_raw (asm_out_file
, loop_lab
);
19994 fputc ('\n', asm_out_file
);
19996 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
20001 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
20002 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
20003 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
20004 deduce these equivalences by itself so it wasn't necessary to hold
20005 its hand so much. Don't be tempted to always supply d2_f_d_e with
20006 the actual cfa register, ie. r31 when we are using a hard frame
20007 pointer. That fails when saving regs off r1, and sched moves the
20008 r31 setup past the reg saves. */
20011 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
20012 rtx reg2
, rtx rreg
)
20016 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
20018 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
20021 gcc_checking_assert (val
== 0);
20022 real
= PATTERN (insn
);
20023 if (GET_CODE (real
) == PARALLEL
)
20024 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
20025 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
20027 rtx set
= XVECEXP (real
, 0, i
);
20029 RTX_FRAME_RELATED_P (set
) = 1;
20031 RTX_FRAME_RELATED_P (insn
) = 1;
20035 /* copy_rtx will not make unique copies of registers, so we need to
20036 ensure we don't have unwanted sharing here. */
20038 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
20041 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
20043 real
= copy_rtx (PATTERN (insn
));
20045 if (reg2
!= NULL_RTX
)
20046 real
= replace_rtx (real
, reg2
, rreg
);
20048 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
20049 gcc_checking_assert (val
== 0);
20051 real
= replace_rtx (real
, reg
,
20052 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
20053 STACK_POINTER_REGNUM
),
20056 /* We expect that 'real' is either a SET or a PARALLEL containing
20057 SETs (and possibly other stuff). In a PARALLEL, all the SETs
20058 are important so they all have to be marked RTX_FRAME_RELATED_P. */
20060 if (GET_CODE (real
) == SET
)
20064 temp
= simplify_rtx (SET_SRC (set
));
20066 SET_SRC (set
) = temp
;
20067 temp
= simplify_rtx (SET_DEST (set
));
20069 SET_DEST (set
) = temp
;
20070 if (GET_CODE (SET_DEST (set
)) == MEM
)
20072 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
20074 XEXP (SET_DEST (set
), 0) = temp
;
20081 gcc_assert (GET_CODE (real
) == PARALLEL
);
20082 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
20083 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
20085 rtx set
= XVECEXP (real
, 0, i
);
20087 temp
= simplify_rtx (SET_SRC (set
));
20089 SET_SRC (set
) = temp
;
20090 temp
= simplify_rtx (SET_DEST (set
));
20092 SET_DEST (set
) = temp
;
20093 if (GET_CODE (SET_DEST (set
)) == MEM
)
20095 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
20097 XEXP (SET_DEST (set
), 0) = temp
;
20099 RTX_FRAME_RELATED_P (set
) = 1;
20103 RTX_FRAME_RELATED_P (insn
) = 1;
20104 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
20109 /* Returns an insn that has a vrsave set operation with the
20110 appropriate CLOBBERs. */
20113 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
20116 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
20117 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
20120 = gen_rtx_SET (VOIDmode
,
20122 gen_rtx_UNSPEC_VOLATILE (SImode
,
20123 gen_rtvec (2, reg
, vrsave
),
20124 UNSPECV_SET_VRSAVE
));
20128 /* We need to clobber the registers in the mask so the scheduler
20129 does not move sets to VRSAVE before sets of AltiVec registers.
20131 However, if the function receives nonlocal gotos, reload will set
20132 all call saved registers live. We will end up with:
20134 (set (reg 999) (mem))
20135 (parallel [ (set (reg vrsave) (unspec blah))
20136 (clobber (reg 999))])
20138 The clobber will cause the store into reg 999 to be dead, and
20139 flow will attempt to delete an epilogue insn. In this case, we
20140 need an unspec use/set of the register. */
20142 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20143 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20145 if (!epiloguep
|| call_used_regs
[i
])
20146 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
20147 gen_rtx_REG (V4SImode
, i
));
20150 rtx reg
= gen_rtx_REG (V4SImode
, i
);
20153 = gen_rtx_SET (VOIDmode
,
20155 gen_rtx_UNSPEC (V4SImode
,
20156 gen_rtvec (1, reg
), 27));
20160 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
20162 for (i
= 0; i
< nclobs
; ++i
)
20163 XVECEXP (insn
, 0, i
) = clobs
[i
];
20169 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
20173 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
20174 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
20175 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
20179 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
20181 return gen_frame_set (reg
, frame_reg
, offset
, false);
20185 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
20187 return gen_frame_set (reg
, frame_reg
, offset
, true);
20190 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
20191 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
20194 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
20195 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
20199 /* Some cases that need register indexed addressing. */
20200 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
20201 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
20202 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
20204 && SPE_VECTOR_MODE (mode
)
20205 && !SPE_CONST_OFFSET_OK (offset
))));
20207 reg
= gen_rtx_REG (mode
, regno
);
20208 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
20209 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
20210 NULL_RTX
, NULL_RTX
);
20213 /* Emit an offset memory reference suitable for a frame store, while
20214 converting to a valid addressing mode. */
20217 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
20219 rtx int_rtx
, offset_rtx
;
20221 int_rtx
= GEN_INT (offset
);
20223 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
20224 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
20226 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
20227 emit_move_insn (offset_rtx
, int_rtx
);
20230 offset_rtx
= int_rtx
;
20232 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
20235 #ifndef TARGET_FIX_AND_CONTINUE
20236 #define TARGET_FIX_AND_CONTINUE 0
20239 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
20240 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
20241 #define LAST_SAVRES_REGISTER 31
20242 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
20253 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
20255 /* Temporary holding space for an out-of-line register save/restore
20257 static char savres_routine_name
[30];
20259 /* Return the name for an out-of-line register save/restore routine.
20260 We are saving/restoring GPRs if GPR is true. */
20263 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
20265 const char *prefix
= "";
20266 const char *suffix
= "";
20268 /* Different targets are supposed to define
20269 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
20270 routine name could be defined with:
20272 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
20274 This is a nice idea in practice, but in reality, things are
20275 complicated in several ways:
20277 - ELF targets have save/restore routines for GPRs.
20279 - SPE targets use different prefixes for 32/64-bit registers, and
20280 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
20282 - PPC64 ELF targets have routines for save/restore of GPRs that
20283 differ in what they do with the link register, so having a set
20284 prefix doesn't work. (We only use one of the save routines at
20285 the moment, though.)
20287 - PPC32 elf targets have "exit" versions of the restore routines
20288 that restore the link register and can save some extra space.
20289 These require an extra suffix. (There are also "tail" versions
20290 of the restore routines and "GOT" versions of the save routines,
20291 but we don't generate those at present. Same problems apply,
20294 We deal with all this by synthesizing our own prefix/suffix and
20295 using that for the simple sprintf call shown above. */
20298 /* No floating point saves on the SPE. */
20299 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
20301 if ((sel
& SAVRES_SAVE
))
20302 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
20304 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
20306 if ((sel
& SAVRES_LR
))
20309 else if (DEFAULT_ABI
== ABI_V4
)
20314 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
20315 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
20316 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
20317 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
20318 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
20319 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
20323 if ((sel
& SAVRES_LR
))
20326 else if (DEFAULT_ABI
== ABI_AIX
)
20328 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
20329 /* No out-of-line save/restore routines for GPRs on AIX. */
20330 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
20334 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
20335 prefix
= ((sel
& SAVRES_SAVE
)
20336 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
20337 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
20338 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
20340 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
20341 if ((sel
& SAVRES_LR
))
20342 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
20346 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
20347 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
20350 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
20351 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
20356 if (DEFAULT_ABI
== ABI_DARWIN
)
20358 /* The Darwin approach is (slightly) different, in order to be
20359 compatible with code generated by the system toolchain. There is a
20360 single symbol for the start of save sequence, and the code here
20361 embeds an offset into that code on the basis of the first register
20363 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
20364 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
20365 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
20366 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
20367 (regno
- 13) * 4, prefix
, regno
);
20368 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
20369 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
20370 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
20371 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
20372 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
20373 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
20378 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
20380 return savres_routine_name
;
20383 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
20384 We are saving/restoring GPRs if GPR is true. */
20387 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
20389 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
20390 ? info
->first_gp_reg_save
20391 : (sel
& SAVRES_REG
) == SAVRES_FPR
20392 ? info
->first_fp_reg_save
- 32
20393 : (sel
& SAVRES_REG
) == SAVRES_VR
20394 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
20399 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
20400 versions of the gpr routines. */
20401 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
20402 && info
->spe_64bit_regs_used
)
20403 select
^= SAVRES_FPR
^ SAVRES_GPR
;
20405 /* Don't generate bogus routine names. */
20406 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
20407 && regno
<= LAST_SAVRES_REGISTER
20408 && select
>= 0 && select
<= 12);
20410 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
20416 name
= rs6000_savres_routine_name (info
, regno
, sel
);
20418 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
20419 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
20420 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
20426 /* Emit a sequence of insns, including a stack tie if needed, for
20427 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
20428 reset the stack pointer, but move the base of the frame into
20429 reg UPDT_REGNO for use by out-of-line register restore routines. */
20432 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
20433 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
20434 unsigned updt_regno
)
20438 /* This blockage is needed so that sched doesn't decide to move
20439 the sp change before the register restores. */
20440 if (DEFAULT_ABI
== ABI_V4
20442 && info
->spe_64bit_regs_used
!= 0
20443 && info
->first_gp_reg_save
!= 32))
20444 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
20446 /* If we are restoring registers out-of-line, we will be using the
20447 "exit" variants of the restore routines, which will reset the
20448 stack for us. But we do need to point updt_reg into the
20449 right place for those routines. */
20450 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
20452 if (frame_off
!= 0)
20453 return emit_insn (gen_add3_insn (updt_reg_rtx
,
20454 frame_reg_rtx
, GEN_INT (frame_off
)));
20455 else if (REGNO (frame_reg_rtx
) != updt_regno
)
20456 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
20461 /* Return the register number used as a pointer by out-of-line
20462 save/restore functions. */
20464 static inline unsigned
20465 ptr_regno_for_savres (int sel
)
20467 if (DEFAULT_ABI
== ABI_AIX
)
20468 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
20469 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
20472 /* Construct a parallel rtx describing the effect of a call to an
20473 out-of-line register save/restore routine, and emit the insn
20474 or jump_insn as appropriate. */
20477 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
20478 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
20479 enum machine_mode reg_mode
, int sel
)
20482 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
20483 int reg_size
= GET_MODE_SIZE (reg_mode
);
20489 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
20490 ? info
->first_gp_reg_save
20491 : (sel
& SAVRES_REG
) == SAVRES_FPR
20492 ? info
->first_fp_reg_save
20493 : (sel
& SAVRES_REG
) == SAVRES_VR
20494 ? info
->first_altivec_reg_save
20496 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
20498 : (sel
& SAVRES_REG
) == SAVRES_FPR
20500 : (sel
& SAVRES_REG
) == SAVRES_VR
20501 ? LAST_ALTIVEC_REGNO
+ 1
20503 n_regs
= end_reg
- start_reg
;
20504 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
20505 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
20508 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
20509 RTVEC_ELT (p
, offset
++) = ret_rtx
;
20511 RTVEC_ELT (p
, offset
++)
20512 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
20514 sym
= rs6000_savres_routine_sym (info
, sel
);
20515 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
20517 use_reg
= ptr_regno_for_savres (sel
);
20518 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
20520 /* Vector regs are saved/restored using [reg+reg] addressing. */
20521 RTVEC_ELT (p
, offset
++)
20522 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
20523 RTVEC_ELT (p
, offset
++)
20524 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
20527 RTVEC_ELT (p
, offset
++)
20528 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
20530 for (i
= 0; i
< end_reg
- start_reg
; i
++)
20531 RTVEC_ELT (p
, i
+ offset
)
20532 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
20533 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
20534 (sel
& SAVRES_SAVE
) != 0);
20536 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
20537 RTVEC_ELT (p
, i
+ offset
)
20538 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
20540 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
20542 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
20544 insn
= emit_jump_insn (par
);
20545 JUMP_LABEL (insn
) = ret_rtx
;
20548 insn
= emit_insn (par
);
20552 /* Determine whether the gp REG is really used. */
20555 rs6000_reg_live_or_pic_offset_p (int reg
)
20557 /* If the function calls eh_return, claim used all the registers that would
20558 be checked for liveness otherwise. This is required for the PIC offset
20559 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
20560 register allocation purposes in this case. */
20562 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
20563 && (!call_used_regs
[reg
]
20564 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
20565 && !TARGET_SINGLE_PIC_BASE
20566 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
20567 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
20568 && !TARGET_SINGLE_PIC_BASE
20569 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
20570 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
20573 /* Emit function prologue as insns. */
20576 rs6000_emit_prologue (void)
20578 rs6000_stack_t
*info
= rs6000_stack_info ();
20579 enum machine_mode reg_mode
= Pmode
;
20580 int reg_size
= TARGET_32BIT
? 4 : 8;
20581 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
20582 rtx frame_reg_rtx
= sp_reg_rtx
;
20583 unsigned int cr_save_regno
;
20584 rtx cr_save_rtx
= NULL_RTX
;
20587 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
20588 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
20589 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
20590 /* Offset to top of frame for frame_reg and sp respectively. */
20591 HOST_WIDE_INT frame_off
= 0;
20592 HOST_WIDE_INT sp_off
= 0;
20594 #ifdef ENABLE_CHECKING
20595 /* Track and check usage of r0, r11, r12. */
20596 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
20597 #define START_USE(R) do \
20599 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
20600 reg_inuse |= 1 << (R); \
20602 #define END_USE(R) do \
20604 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
20605 reg_inuse &= ~(1 << (R)); \
20607 #define NOT_INUSE(R) do \
20609 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
20612 #define START_USE(R) do {} while (0)
20613 #define END_USE(R) do {} while (0)
20614 #define NOT_INUSE(R) do {} while (0)
20617 if (flag_stack_usage_info
)
20618 current_function_static_stack_size
= info
->total_size
;
20620 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& info
->total_size
)
20621 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, info
->total_size
);
20623 if (TARGET_FIX_AND_CONTINUE
)
20625 /* gdb on darwin arranges to forward a function from the old
20626 address by modifying the first 5 instructions of the function
20627 to branch to the overriding function. This is necessary to
20628 permit function pointers that point to the old function to
20629 actually forward to the new function. */
20630 emit_insn (gen_nop ());
20631 emit_insn (gen_nop ());
20632 emit_insn (gen_nop ());
20633 emit_insn (gen_nop ());
20634 emit_insn (gen_nop ());
20637 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
20639 reg_mode
= V2SImode
;
20643 /* Handle world saves specially here. */
20644 if (WORLD_SAVE_P (info
))
20651 /* save_world expects lr in r0. */
20652 reg0
= gen_rtx_REG (Pmode
, 0);
20653 if (info
->lr_save_p
)
20655 insn
= emit_move_insn (reg0
,
20656 gen_rtx_REG (Pmode
, LR_REGNO
));
20657 RTX_FRAME_RELATED_P (insn
) = 1;
20660 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
20661 assumptions about the offsets of various bits of the stack
20663 gcc_assert (info
->gp_save_offset
== -220
20664 && info
->fp_save_offset
== -144
20665 && info
->lr_save_offset
== 8
20666 && info
->cr_save_offset
== 4
20669 && (!crtl
->calls_eh_return
20670 || info
->ehrd_offset
== -432)
20671 && info
->vrsave_save_offset
== -224
20672 && info
->altivec_save_offset
== -416);
20674 treg
= gen_rtx_REG (SImode
, 11);
20675 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
20677 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
20678 in R11. It also clobbers R12, so beware! */
20680 /* Preserve CR2 for save_world prologues */
20682 sz
+= 32 - info
->first_gp_reg_save
;
20683 sz
+= 64 - info
->first_fp_reg_save
;
20684 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
20685 p
= rtvec_alloc (sz
);
20687 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
20688 gen_rtx_REG (SImode
,
20690 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
20691 gen_rtx_SYMBOL_REF (Pmode
,
20693 /* We do floats first so that the instruction pattern matches
20695 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
20697 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
20699 info
->first_fp_reg_save
+ i
),
20701 info
->fp_save_offset
+ frame_off
+ 8 * i
);
20702 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
20704 = gen_frame_store (gen_rtx_REG (V4SImode
,
20705 info
->first_altivec_reg_save
+ i
),
20707 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
20708 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20710 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
20712 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
20714 /* CR register traditionally saved as CR2. */
20716 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
20717 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
20718 /* Explain about use of R0. */
20719 if (info
->lr_save_p
)
20721 = gen_frame_store (reg0
,
20722 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
20723 /* Explain what happens to the stack pointer. */
20725 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
20726 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
20729 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20730 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
20731 treg
, GEN_INT (-info
->total_size
));
20732 sp_off
= frame_off
= info
->total_size
;
20735 strategy
= info
->savres_strategy
;
20737 /* For V.4, update stack before we do any saving and set back pointer. */
20738 if (! WORLD_SAVE_P (info
)
20740 && (DEFAULT_ABI
== ABI_V4
20741 || crtl
->calls_eh_return
))
20743 bool need_r11
= (TARGET_SPE
20744 ? (!(strategy
& SAVE_INLINE_GPRS
)
20745 && info
->spe_64bit_regs_used
== 0)
20746 : (!(strategy
& SAVE_INLINE_FPRS
)
20747 || !(strategy
& SAVE_INLINE_GPRS
)
20748 || !(strategy
& SAVE_INLINE_VRS
)));
20749 int ptr_regno
= -1;
20750 rtx ptr_reg
= NULL_RTX
;
20753 if (info
->total_size
< 32767)
20754 frame_off
= info
->total_size
;
20757 else if (info
->cr_save_p
20759 || info
->first_fp_reg_save
< 64
20760 || info
->first_gp_reg_save
< 32
20761 || info
->altivec_size
!= 0
20762 || info
->vrsave_mask
!= 0
20763 || crtl
->calls_eh_return
)
20767 /* The prologue won't be saving any regs so there is no need
20768 to set up a frame register to access any frame save area.
20769 We also won't be using frame_off anywhere below, but set
20770 the correct value anyway to protect against future
20771 changes to this function. */
20772 frame_off
= info
->total_size
;
20774 if (ptr_regno
!= -1)
20776 /* Set up the frame offset to that needed by the first
20777 out-of-line save function. */
20778 START_USE (ptr_regno
);
20779 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
20780 frame_reg_rtx
= ptr_reg
;
20781 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
20782 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
20783 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
20784 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
20785 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
20786 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
20787 frame_off
= -ptr_off
;
20789 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
20790 sp_off
= info
->total_size
;
20791 if (frame_reg_rtx
!= sp_reg_rtx
)
20792 rs6000_emit_stack_tie (frame_reg_rtx
, false);
20795 /* If we use the link register, get it into r0. */
20796 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
20798 rtx addr
, reg
, mem
;
20800 reg
= gen_rtx_REG (Pmode
, 0);
20802 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
20803 RTX_FRAME_RELATED_P (insn
) = 1;
20805 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
20806 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
20808 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20809 GEN_INT (info
->lr_save_offset
+ frame_off
));
20810 mem
= gen_rtx_MEM (Pmode
, addr
);
20811 /* This should not be of rs6000_sr_alias_set, because of
20812 __builtin_return_address. */
20814 insn
= emit_move_insn (mem
, reg
);
20815 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
20816 NULL_RTX
, NULL_RTX
);
20821 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
20822 r12 will be needed by out-of-line gpr restore. */
20823 cr_save_regno
= (DEFAULT_ABI
== ABI_AIX
20824 && !(strategy
& (SAVE_INLINE_GPRS
20825 | SAVE_NOINLINE_GPRS_SAVES_LR
))
20827 if (!WORLD_SAVE_P (info
)
20829 && REGNO (frame_reg_rtx
) != cr_save_regno
20830 && !(using_static_chain_p
&& cr_save_regno
== 11))
20834 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
20835 START_USE (cr_save_regno
);
20836 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
20837 RTX_FRAME_RELATED_P (insn
) = 1;
20838 /* Now, there's no way that dwarf2out_frame_debug_expr is going
20839 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
20840 But that's OK. All we have to do is specify that _one_ condition
20841 code register is saved in this stack slot. The thrower's epilogue
20842 will then restore all the call-saved registers.
20843 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
20844 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
20845 gen_rtx_REG (SImode
, CR2_REGNO
));
20846 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
20849 /* Do any required saving of fpr's. If only one or two to save, do
20850 it ourselves. Otherwise, call function. */
20851 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
20854 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
20855 if (save_reg_p (info
->first_fp_reg_save
+ i
))
20856 emit_frame_save (frame_reg_rtx
,
20857 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
20858 ? DFmode
: SFmode
),
20859 info
->first_fp_reg_save
+ i
,
20860 info
->fp_save_offset
+ frame_off
+ 8 * i
,
20861 sp_off
- frame_off
);
20863 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
20865 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
20866 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
20867 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
20868 rtx ptr_reg
= frame_reg_rtx
;
20870 if (REGNO (frame_reg_rtx
) == ptr_regno
)
20871 gcc_checking_assert (frame_off
== 0);
20874 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
20875 NOT_INUSE (ptr_regno
);
20876 emit_insn (gen_add3_insn (ptr_reg
,
20877 frame_reg_rtx
, GEN_INT (frame_off
)));
20879 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
20880 info
->fp_save_offset
,
20881 info
->lr_save_offset
,
20883 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
20884 NULL_RTX
, NULL_RTX
);
20889 /* Save GPRs. This is done as a PARALLEL if we are using
20890 the store-multiple instructions. */
20891 if (!WORLD_SAVE_P (info
)
20893 && info
->spe_64bit_regs_used
!= 0
20894 && info
->first_gp_reg_save
!= 32)
20897 rtx spe_save_area_ptr
;
20898 HOST_WIDE_INT save_off
;
20899 int ool_adjust
= 0;
20901 /* Determine whether we can address all of the registers that need
20902 to be saved with an offset from frame_reg_rtx that fits in
20903 the small const field for SPE memory instructions. */
20904 int spe_regs_addressable
20905 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
20906 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
20907 && (strategy
& SAVE_INLINE_GPRS
));
20909 if (spe_regs_addressable
)
20911 spe_save_area_ptr
= frame_reg_rtx
;
20912 save_off
= frame_off
;
20916 /* Make r11 point to the start of the SPE save area. We need
20917 to be careful here if r11 is holding the static chain. If
20918 it is, then temporarily save it in r0. */
20919 HOST_WIDE_INT offset
;
20921 if (!(strategy
& SAVE_INLINE_GPRS
))
20922 ool_adjust
= 8 * (info
->first_gp_reg_save
20923 - (FIRST_SAVRES_REGISTER
+ 1));
20924 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
20925 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
20926 save_off
= frame_off
- offset
;
20928 if (using_static_chain_p
)
20930 rtx r0
= gen_rtx_REG (Pmode
, 0);
20933 gcc_assert (info
->first_gp_reg_save
> 11);
20935 emit_move_insn (r0
, spe_save_area_ptr
);
20937 else if (REGNO (frame_reg_rtx
) != 11)
20940 emit_insn (gen_addsi3 (spe_save_area_ptr
,
20941 frame_reg_rtx
, GEN_INT (offset
)));
20942 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
20943 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
20946 if ((strategy
& SAVE_INLINE_GPRS
))
20948 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20949 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
20950 emit_frame_save (spe_save_area_ptr
, reg_mode
,
20951 info
->first_gp_reg_save
+ i
,
20952 (info
->spe_gp_save_offset
+ save_off
20954 sp_off
- save_off
);
20958 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
20959 info
->spe_gp_save_offset
+ save_off
,
20961 SAVRES_SAVE
| SAVRES_GPR
);
20963 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
20964 NULL_RTX
, NULL_RTX
);
20967 /* Move the static chain pointer back. */
20968 if (!spe_regs_addressable
)
20970 if (using_static_chain_p
)
20972 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
20975 else if (REGNO (frame_reg_rtx
) != 11)
20979 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
20981 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
20982 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
20983 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
20984 rtx ptr_reg
= frame_reg_rtx
;
20985 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
20986 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
20990 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
20992 /* Need to adjust r11 (r12) if we saved any FPRs. */
20993 if (end_save
+ frame_off
!= 0)
20995 rtx offset
= GEN_INT (end_save
+ frame_off
);
20998 frame_off
= -end_save
;
21000 NOT_INUSE (ptr_regno
);
21001 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
21003 else if (!ptr_set_up
)
21005 NOT_INUSE (ptr_regno
);
21006 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21008 ptr_off
= -end_save
;
21009 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
21010 info
->gp_save_offset
+ ptr_off
,
21011 info
->lr_save_offset
+ ptr_off
,
21013 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
21014 NULL_RTX
, NULL_RTX
);
21018 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
21022 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
21023 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21025 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21027 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
21028 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21029 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21030 NULL_RTX
, NULL_RTX
);
21032 else if (!WORLD_SAVE_P (info
))
21035 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21036 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21037 emit_frame_save (frame_reg_rtx
, reg_mode
,
21038 info
->first_gp_reg_save
+ i
,
21039 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
21040 sp_off
- frame_off
);
21043 if (crtl
->calls_eh_return
)
21050 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
21051 if (regno
== INVALID_REGNUM
)
21055 p
= rtvec_alloc (i
);
21059 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
21060 if (regno
== INVALID_REGNUM
)
21064 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
21066 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
21067 RTVEC_ELT (p
, i
) = insn
;
21068 RTX_FRAME_RELATED_P (insn
) = 1;
21071 insn
= emit_insn (gen_blockage ());
21072 RTX_FRAME_RELATED_P (insn
) = 1;
21073 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
21076 /* In AIX ABI we need to make sure r2 is really saved. */
21077 if (TARGET_AIX
&& crtl
->calls_eh_return
)
21079 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
21080 rtx save_insn
, join_insn
, note
;
21081 long toc_restore_insn
;
21083 tmp_reg
= gen_rtx_REG (Pmode
, 11);
21084 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
21085 if (using_static_chain_p
)
21088 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
21092 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
21093 /* Peek at instruction to which this function returns. If it's
21094 restoring r2, then we know we've already saved r2. We can't
21095 unconditionally save r2 because the value we have will already
21096 be updated if we arrived at this function via a plt call or
21097 toc adjusting stub. */
21098 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
21099 toc_restore_insn
= TARGET_32BIT
? 0x80410014 : 0xE8410028;
21100 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
21101 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
21102 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
21103 validate_condition_mode (EQ
, CCUNSmode
);
21104 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
21105 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
21106 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
21107 toc_save_done
= gen_label_rtx ();
21108 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
21109 gen_rtx_EQ (VOIDmode
, compare_result
,
21111 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
21113 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
21114 JUMP_LABEL (jump
) = toc_save_done
;
21115 LABEL_NUSES (toc_save_done
) += 1;
21117 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
21118 TOC_REGNUM
, frame_off
+ 5 * reg_size
,
21119 sp_off
- frame_off
);
21121 emit_label (toc_save_done
);
21123 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
21124 have a CFG that has different saves along different paths.
21125 Move the note to a dummy blockage insn, which describes that
21126 R2 is unconditionally saved after the label. */
21127 /* ??? An alternate representation might be a special insn pattern
21128 containing both the branch and the store. That might let the
21129 code that minimizes the number of DW_CFA_advance opcodes better
21130 freedom in placing the annotations. */
21131 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
21133 remove_note (save_insn
, note
);
21135 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
21136 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
21137 RTX_FRAME_RELATED_P (save_insn
) = 0;
21139 join_insn
= emit_insn (gen_blockage ());
21140 REG_NOTES (join_insn
) = note
;
21141 RTX_FRAME_RELATED_P (join_insn
) = 1;
21143 if (using_static_chain_p
)
21145 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
21152 /* Save CR if we use any that must be preserved. */
21153 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
21155 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
21156 GEN_INT (info
->cr_save_offset
+ frame_off
));
21157 rtx mem
= gen_frame_mem (SImode
, addr
);
21158 /* See the large comment above about why CR2_REGNO is used. */
21159 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
21161 /* If we didn't copy cr before, do so now using r0. */
21162 if (cr_save_rtx
== NULL_RTX
)
21167 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
21168 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
21169 RTX_FRAME_RELATED_P (insn
) = 1;
21170 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
21171 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
21173 insn
= emit_move_insn (mem
, cr_save_rtx
);
21174 END_USE (REGNO (cr_save_rtx
));
21176 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21177 NULL_RTX
, NULL_RTX
);
21180 /* Update stack and set back pointer unless this is V.4,
21181 for which it was done previously. */
21182 if (!WORLD_SAVE_P (info
) && info
->push_p
21183 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
21185 rtx ptr_reg
= NULL
;
21188 /* If saving altivec regs we need to be able to address all save
21189 locations using a 16-bit offset. */
21190 if ((strategy
& SAVE_INLINE_VRS
) == 0
21191 || (info
->altivec_size
!= 0
21192 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
21193 + info
->total_size
- frame_off
) > 32767)
21194 || (info
->vrsave_size
!= 0
21195 && (info
->vrsave_save_offset
21196 + info
->total_size
- frame_off
) > 32767))
21198 int sel
= SAVRES_SAVE
| SAVRES_VR
;
21199 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
21201 if (using_static_chain_p
21202 && ptr_regno
== STATIC_CHAIN_REGNUM
)
21204 if (REGNO (frame_reg_rtx
) != ptr_regno
)
21205 START_USE (ptr_regno
);
21206 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21207 frame_reg_rtx
= ptr_reg
;
21208 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
21209 frame_off
= -ptr_off
;
21211 else if (REGNO (frame_reg_rtx
) == 1)
21212 frame_off
= info
->total_size
;
21213 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
21214 sp_off
= info
->total_size
;
21215 if (frame_reg_rtx
!= sp_reg_rtx
)
21216 rs6000_emit_stack_tie (frame_reg_rtx
, false);
21219 /* Set frame pointer, if needed. */
21220 if (frame_pointer_needed
)
21222 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
21224 RTX_FRAME_RELATED_P (insn
) = 1;
21227 /* Save AltiVec registers if needed. Save here because the red zone does
21228 not always include AltiVec registers. */
21229 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
21230 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
21232 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
21234 /* Oddly, the vector save/restore functions point r0 at the end
21235 of the save area, then use r11 or r12 to load offsets for
21236 [reg+reg] addressing. */
21237 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
21238 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
21239 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
21241 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
21243 if (end_save
+ frame_off
!= 0)
21245 rtx offset
= GEN_INT (end_save
+ frame_off
);
21247 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
21250 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21252 ptr_off
= -end_save
;
21253 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
21254 info
->altivec_save_offset
+ ptr_off
,
21255 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
21256 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
21257 NULL_RTX
, NULL_RTX
);
21258 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
21260 /* The oddity mentioned above clobbered our frame reg. */
21261 emit_move_insn (frame_reg_rtx
, ptr_reg
);
21262 frame_off
= ptr_off
;
21265 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
21266 && info
->altivec_size
!= 0)
21270 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21271 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21273 rtx areg
, savereg
, mem
;
21276 offset
= (info
->altivec_save_offset
+ frame_off
21277 + 16 * (i
- info
->first_altivec_reg_save
));
21279 savereg
= gen_rtx_REG (V4SImode
, i
);
21282 areg
= gen_rtx_REG (Pmode
, 0);
21283 emit_move_insn (areg
, GEN_INT (offset
));
21285 /* AltiVec addressing mode is [reg+reg]. */
21286 mem
= gen_frame_mem (V4SImode
,
21287 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
21289 insn
= emit_move_insn (mem
, savereg
);
21291 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21292 areg
, GEN_INT (offset
));
21296 /* VRSAVE is a bit vector representing which AltiVec registers
21297 are used. The OS uses this to determine which vector
21298 registers to save on a context switch. We need to save
21299 VRSAVE on the stack frame, add whatever AltiVec registers we
21300 used in this function, and do the corresponding magic in the
21303 if (!WORLD_SAVE_P (info
)
21305 && TARGET_ALTIVEC_VRSAVE
21306 && info
->vrsave_mask
!= 0)
21312 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
21313 be using r12 as frame_reg_rtx and r11 as the static chain
21314 pointer for nested functions. */
21316 if (DEFAULT_ABI
== ABI_AIX
&& !using_static_chain_p
)
21318 else if (REGNO (frame_reg_rtx
) == 12)
21321 if (using_static_chain_p
)
21325 NOT_INUSE (save_regno
);
21326 reg
= gen_rtx_REG (SImode
, save_regno
);
21327 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
21329 emit_insn (gen_get_vrsave_internal (reg
));
21331 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
21334 offset
= info
->vrsave_save_offset
+ frame_off
;
21335 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
21337 /* Include the registers in the mask. */
21338 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
21340 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
21343 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
21344 if (!TARGET_SINGLE_PIC_BASE
21345 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
21346 || (DEFAULT_ABI
== ABI_V4
21347 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
21348 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
21350 /* If emit_load_toc_table will use the link register, we need to save
21351 it. We use R12 for this purpose because emit_load_toc_table
21352 can use register 0. This allows us to use a plain 'blr' to return
21353 from the procedure more often. */
21354 int save_LR_around_toc_setup
= (TARGET_ELF
21355 && DEFAULT_ABI
!= ABI_AIX
21357 && ! info
->lr_save_p
21358 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
21359 if (save_LR_around_toc_setup
)
21361 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
21362 rtx tmp
= gen_rtx_REG (Pmode
, 12);
21364 insn
= emit_move_insn (tmp
, lr
);
21365 RTX_FRAME_RELATED_P (insn
) = 1;
21367 rs6000_emit_load_toc_table (TRUE
);
21369 insn
= emit_move_insn (lr
, tmp
);
21370 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
21371 RTX_FRAME_RELATED_P (insn
) = 1;
21374 rs6000_emit_load_toc_table (TRUE
);
21378 if (!TARGET_SINGLE_PIC_BASE
21379 && DEFAULT_ABI
== ABI_DARWIN
21380 && flag_pic
&& crtl
->uses_pic_offset_table
)
21382 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
21383 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
21385 /* Save and restore LR locally around this call (in R0). */
21386 if (!info
->lr_save_p
)
21387 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
21389 emit_insn (gen_load_macho_picbase (src
));
21391 emit_move_insn (gen_rtx_REG (Pmode
,
21392 RS6000_PIC_OFFSET_TABLE_REGNUM
),
21395 if (!info
->lr_save_p
)
21396 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
21400 /* If we need to, save the TOC register after doing the stack setup.
21401 Do not emit eh frame info for this save. The unwinder wants info,
21402 conceptually attached to instructions in this function, about
21403 register values in the caller of this function. This R2 may have
21404 already been changed from the value in the caller.
21405 We don't attempt to write accurate DWARF EH frame info for R2
21406 because code emitted by gcc for a (non-pointer) function call
21407 doesn't save and restore R2. Instead, R2 is managed out-of-line
21408 by a linker generated plt call stub when the function resides in
21409 a shared library. This behaviour is costly to describe in DWARF,
21410 both in terms of the size of DWARF info and the time taken in the
21411 unwinder to interpret it. R2 changes, apart from the
21412 calls_eh_return case earlier in this function, are handled by
21413 linux-unwind.h frob_update_context. */
21414 if (rs6000_save_toc_in_prologue_p ())
21416 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
21417 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, 5 * reg_size
));
21421 /* Write function prologue. */
21424 rs6000_output_function_prologue (FILE *file
,
21425 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
21427 rs6000_stack_t
*info
= rs6000_stack_info ();
21429 if (TARGET_DEBUG_STACK
)
21430 debug_stack_info (info
);
21432 /* Write .extern for any function we will call to save and restore
21434 if (info
->first_fp_reg_save
< 64
21439 int regno
= info
->first_fp_reg_save
- 32;
21441 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
21443 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
21444 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21445 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21446 fprintf (file
, "\t.extern %s\n", name
);
21448 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
21450 bool lr
= (info
->savres_strategy
21451 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
21452 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21453 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21454 fprintf (file
, "\t.extern %s\n", name
);
21458 rs6000_pic_labelno
++;
21461 /* Non-zero if vmx regs are restored before the frame pop, zero if
21462 we restore after the pop when possible. */
21463 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
21465 /* Restoring cr is a two step process: loading a reg from the frame
21466 save, then moving the reg to cr. For ABI_V4 we must let the
21467 unwinder know that the stack location is no longer valid at or
21468 before the stack deallocation, but we can't emit a cfa_restore for
21469 cr at the stack deallocation like we do for other registers.
21470 The trouble is that it is possible for the move to cr to be
21471 scheduled after the stack deallocation. So say exactly where cr
21472 is located on each of the two insns. */
21475 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
21477 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
21478 rtx reg
= gen_rtx_REG (SImode
, regno
);
21479 rtx insn
= emit_move_insn (reg
, mem
);
21481 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
21483 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
21484 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
21486 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
21487 RTX_FRAME_RELATED_P (insn
) = 1;
21492 /* Reload CR from REG. */
21495 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
21500 if (using_mfcr_multiple
)
21502 for (i
= 0; i
< 8; i
++)
21503 if (save_reg_p (CR0_REGNO
+ i
))
21505 gcc_assert (count
);
21508 if (using_mfcr_multiple
&& count
> 1)
21513 p
= rtvec_alloc (count
);
21516 for (i
= 0; i
< 8; i
++)
21517 if (save_reg_p (CR0_REGNO
+ i
))
21519 rtvec r
= rtvec_alloc (2);
21520 RTVEC_ELT (r
, 0) = reg
;
21521 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
21522 RTVEC_ELT (p
, ndx
) =
21523 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
21524 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
21527 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21528 gcc_assert (ndx
== count
);
21531 for (i
= 0; i
< 8; i
++)
21532 if (save_reg_p (CR0_REGNO
+ i
))
21533 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
21536 if (!exit_func
&& (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
21538 rtx insn
= get_last_insn ();
21539 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
21541 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
21542 RTX_FRAME_RELATED_P (insn
) = 1;
21546 /* Like cr, the move to lr instruction can be scheduled after the
21547 stack deallocation, but unlike cr, its stack frame save is still
21548 valid. So we only need to emit the cfa_restore on the correct
21552 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
21554 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
21555 rtx reg
= gen_rtx_REG (Pmode
, regno
);
21557 emit_move_insn (reg
, mem
);
21561 restore_saved_lr (int regno
, bool exit_func
)
21563 rtx reg
= gen_rtx_REG (Pmode
, regno
);
21564 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
21565 rtx insn
= emit_move_insn (lr
, reg
);
21567 if (!exit_func
&& flag_shrink_wrap
)
21569 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
21570 RTX_FRAME_RELATED_P (insn
) = 1;
21575 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
21577 if (info
->cr_save_p
)
21578 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
21579 gen_rtx_REG (SImode
, CR2_REGNO
),
21581 if (info
->lr_save_p
)
21582 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
21583 gen_rtx_REG (Pmode
, LR_REGNO
),
21585 return cfa_restores
;
21588 /* Return true if OFFSET from stack pointer can be clobbered by signals.
21589 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
21590 below stack pointer not cloberred by signals. */
21593 offset_below_red_zone_p (HOST_WIDE_INT offset
)
21595 return offset
< (DEFAULT_ABI
== ABI_V4
21597 : TARGET_32BIT
? -220 : -288);
21600 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
21603 emit_cfa_restores (rtx cfa_restores
)
21605 rtx insn
= get_last_insn ();
21606 rtx
*loc
= ®_NOTES (insn
);
21609 loc
= &XEXP (*loc
, 1);
21610 *loc
= cfa_restores
;
21611 RTX_FRAME_RELATED_P (insn
) = 1;
21614 /* Emit function epilogue as insns. */
21617 rs6000_emit_epilogue (int sibcall
)
21619 rs6000_stack_t
*info
;
21620 int restoring_GPRs_inline
;
21621 int restoring_FPRs_inline
;
21622 int using_load_multiple
;
21623 int using_mtcr_multiple
;
21624 int use_backchain_to_restore_sp
;
21627 HOST_WIDE_INT frame_off
= 0;
21628 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
21629 rtx frame_reg_rtx
= sp_reg_rtx
;
21630 rtx cfa_restores
= NULL_RTX
;
21632 rtx cr_save_reg
= NULL_RTX
;
21633 enum machine_mode reg_mode
= Pmode
;
21634 int reg_size
= TARGET_32BIT
? 4 : 8;
21637 unsigned ptr_regno
;
21639 info
= rs6000_stack_info ();
21641 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
21643 reg_mode
= V2SImode
;
21647 strategy
= info
->savres_strategy
;
21648 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
21649 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
21650 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
21651 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
21652 || rs6000_cpu
== PROCESSOR_PPC603
21653 || rs6000_cpu
== PROCESSOR_PPC750
21655 /* Restore via the backchain when we have a large frame, since this
21656 is more efficient than an addis, addi pair. The second condition
21657 here will not trigger at the moment; We don't actually need a
21658 frame pointer for alloca, but the generic parts of the compiler
21659 give us one anyway. */
21660 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
21661 || (cfun
->calls_alloca
21662 && !frame_pointer_needed
));
21663 restore_lr
= (info
->lr_save_p
21664 && (restoring_FPRs_inline
21665 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
21666 && (restoring_GPRs_inline
21667 || info
->first_fp_reg_save
< 64));
21669 if (WORLD_SAVE_P (info
))
21673 const char *alloc_rname
;
21676 /* eh_rest_world_r10 will return to the location saved in the LR
21677 stack slot (which is not likely to be our caller.)
21678 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
21679 rest_world is similar, except any R10 parameter is ignored.
21680 The exception-handling stuff that was here in 2.95 is no
21681 longer necessary. */
21685 + 32 - info
->first_gp_reg_save
21686 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
21687 + 63 + 1 - info
->first_fp_reg_save
);
21689 strcpy (rname
, ((crtl
->calls_eh_return
) ?
21690 "*eh_rest_world_r10" : "*rest_world"));
21691 alloc_rname
= ggc_strdup (rname
);
21694 RTVEC_ELT (p
, j
++) = ret_rtx
;
21695 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
21696 gen_rtx_REG (Pmode
,
21699 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
21700 /* The instruction pattern requires a clobber here;
21701 it is shared with the restVEC helper. */
21703 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
21706 /* CR register traditionally saved as CR2. */
21707 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
21709 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
21710 if (flag_shrink_wrap
)
21712 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
21713 gen_rtx_REG (Pmode
, LR_REGNO
),
21715 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21719 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21721 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
21723 = gen_frame_load (reg
,
21724 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
21725 if (flag_shrink_wrap
)
21726 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21728 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
21730 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
21732 = gen_frame_load (reg
,
21733 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
21734 if (flag_shrink_wrap
)
21735 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21737 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
21739 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
21740 ? DFmode
: SFmode
),
21741 info
->first_fp_reg_save
+ i
);
21743 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
21744 if (flag_shrink_wrap
)
21745 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21748 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
21750 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
21752 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
21754 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
21756 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
21757 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21759 if (flag_shrink_wrap
)
21761 REG_NOTES (insn
) = cfa_restores
;
21762 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
21763 RTX_FRAME_RELATED_P (insn
) = 1;
21768 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
21770 frame_off
= info
->total_size
;
21772 /* Restore AltiVec registers if we must do so before adjusting the
21774 if (TARGET_ALTIVEC_ABI
21775 && info
->altivec_size
!= 0
21776 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21777 || (DEFAULT_ABI
!= ABI_V4
21778 && offset_below_red_zone_p (info
->altivec_save_offset
))))
21781 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
21783 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
21784 if (use_backchain_to_restore_sp
)
21786 int frame_regno
= 11;
21788 if ((strategy
& REST_INLINE_VRS
) == 0)
21790 /* Of r11 and r12, select the one not clobbered by an
21791 out-of-line restore function for the frame register. */
21792 frame_regno
= 11 + 12 - scratch_regno
;
21794 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
21795 emit_move_insn (frame_reg_rtx
,
21796 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
21799 else if (frame_pointer_needed
)
21800 frame_reg_rtx
= hard_frame_pointer_rtx
;
21802 if ((strategy
& REST_INLINE_VRS
) == 0)
21804 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
21806 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
21807 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
21809 if (end_save
+ frame_off
!= 0)
21811 rtx offset
= GEN_INT (end_save
+ frame_off
);
21813 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
21816 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21818 ptr_off
= -end_save
;
21819 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
21820 info
->altivec_save_offset
+ ptr_off
,
21821 0, V4SImode
, SAVRES_VR
);
21825 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21826 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21828 rtx addr
, areg
, mem
, reg
;
21830 areg
= gen_rtx_REG (Pmode
, 0);
21832 (areg
, GEN_INT (info
->altivec_save_offset
21834 + 16 * (i
- info
->first_altivec_reg_save
)));
21836 /* AltiVec addressing mode is [reg+reg]. */
21837 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
21838 mem
= gen_frame_mem (V4SImode
, addr
);
21840 reg
= gen_rtx_REG (V4SImode
, i
);
21841 emit_move_insn (reg
, mem
);
21845 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21846 if (((strategy
& REST_INLINE_VRS
) == 0
21847 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
21848 && (flag_shrink_wrap
21849 || (offset_below_red_zone_p
21850 (info
->altivec_save_offset
21851 + 16 * (i
- info
->first_altivec_reg_save
)))))
21853 rtx reg
= gen_rtx_REG (V4SImode
, i
);
21854 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
21858 /* Restore VRSAVE if we must do so before adjusting the stack. */
21860 && TARGET_ALTIVEC_VRSAVE
21861 && info
->vrsave_mask
!= 0
21862 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21863 || (DEFAULT_ABI
!= ABI_V4
21864 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
21868 if (frame_reg_rtx
== sp_reg_rtx
)
21870 if (use_backchain_to_restore_sp
)
21872 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
21873 emit_move_insn (frame_reg_rtx
,
21874 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
21877 else if (frame_pointer_needed
)
21878 frame_reg_rtx
= hard_frame_pointer_rtx
;
21881 reg
= gen_rtx_REG (SImode
, 12);
21882 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
21883 info
->vrsave_save_offset
+ frame_off
));
21885 emit_insn (generate_set_vrsave (reg
, info
, 1));
21889 /* If we have a large stack frame, restore the old stack pointer
21890 using the backchain. */
21891 if (use_backchain_to_restore_sp
)
21893 if (frame_reg_rtx
== sp_reg_rtx
)
21895 /* Under V.4, don't reset the stack pointer until after we're done
21896 loading the saved registers. */
21897 if (DEFAULT_ABI
== ABI_V4
)
21898 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
21900 insn
= emit_move_insn (frame_reg_rtx
,
21901 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
21904 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21905 && DEFAULT_ABI
== ABI_V4
)
21906 /* frame_reg_rtx has been set up by the altivec restore. */
21910 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
21911 frame_reg_rtx
= sp_reg_rtx
;
21914 /* If we have a frame pointer, we can restore the old stack pointer
21916 else if (frame_pointer_needed
)
21918 frame_reg_rtx
= sp_reg_rtx
;
21919 if (DEFAULT_ABI
== ABI_V4
)
21920 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
21921 /* Prevent reordering memory accesses against stack pointer restore. */
21922 else if (cfun
->calls_alloca
21923 || offset_below_red_zone_p (-info
->total_size
))
21924 rs6000_emit_stack_tie (frame_reg_rtx
, true);
21926 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
21927 GEN_INT (info
->total_size
)));
21930 else if (info
->push_p
21931 && DEFAULT_ABI
!= ABI_V4
21932 && !crtl
->calls_eh_return
)
21934 /* Prevent reordering memory accesses against stack pointer restore. */
21935 if (cfun
->calls_alloca
21936 || offset_below_red_zone_p (-info
->total_size
))
21937 rs6000_emit_stack_tie (frame_reg_rtx
, false);
21938 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
21939 GEN_INT (info
->total_size
)));
21942 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
21946 REG_NOTES (insn
) = cfa_restores
;
21947 cfa_restores
= NULL_RTX
;
21949 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
21950 RTX_FRAME_RELATED_P (insn
) = 1;
21953 /* Restore AltiVec registers if we have not done so already. */
21954 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21955 && TARGET_ALTIVEC_ABI
21956 && info
->altivec_size
!= 0
21957 && (DEFAULT_ABI
== ABI_V4
21958 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
21962 if ((strategy
& REST_INLINE_VRS
) == 0)
21964 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
21966 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
21967 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
21968 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
21970 if (end_save
+ frame_off
!= 0)
21972 rtx offset
= GEN_INT (end_save
+ frame_off
);
21974 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
21977 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21979 ptr_off
= -end_save
;
21980 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
21981 info
->altivec_save_offset
+ ptr_off
,
21982 0, V4SImode
, SAVRES_VR
);
21983 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
21985 /* Frame reg was clobbered by out-of-line save. Restore it
21986 from ptr_reg, and if we are calling out-of-line gpr or
21987 fpr restore set up the correct pointer and offset. */
21988 unsigned newptr_regno
= 1;
21989 if (!restoring_GPRs_inline
)
21991 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
21992 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
21993 newptr_regno
= ptr_regno_for_savres (sel
);
21994 end_save
= info
->gp_save_offset
+ info
->gp_size
;
21996 else if (!restoring_FPRs_inline
)
21998 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
21999 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22000 newptr_regno
= ptr_regno_for_savres (sel
);
22001 end_save
= info
->gp_save_offset
+ info
->gp_size
;
22004 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
22005 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
22007 if (end_save
+ ptr_off
!= 0)
22009 rtx offset
= GEN_INT (end_save
+ ptr_off
);
22011 frame_off
= -end_save
;
22012 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
22016 frame_off
= ptr_off
;
22017 emit_move_insn (frame_reg_rtx
, ptr_reg
);
22023 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22024 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22026 rtx addr
, areg
, mem
, reg
;
22028 areg
= gen_rtx_REG (Pmode
, 0);
22030 (areg
, GEN_INT (info
->altivec_save_offset
22032 + 16 * (i
- info
->first_altivec_reg_save
)));
22034 /* AltiVec addressing mode is [reg+reg]. */
22035 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
22036 mem
= gen_frame_mem (V4SImode
, addr
);
22038 reg
= gen_rtx_REG (V4SImode
, i
);
22039 emit_move_insn (reg
, mem
);
22043 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22044 if (((strategy
& REST_INLINE_VRS
) == 0
22045 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
22046 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
22048 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22049 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22053 /* Restore VRSAVE if we have not done so already. */
22054 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22056 && TARGET_ALTIVEC_VRSAVE
22057 && info
->vrsave_mask
!= 0
22058 && (DEFAULT_ABI
== ABI_V4
22059 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
22063 reg
= gen_rtx_REG (SImode
, 12);
22064 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22065 info
->vrsave_save_offset
+ frame_off
));
22067 emit_insn (generate_set_vrsave (reg
, info
, 1));
22070 /* If we exit by an out-of-line restore function on ABI_V4 then that
22071 function will deallocate the stack, so we don't need to worry
22072 about the unwinder restoring cr from an invalid stack frame
22074 exit_func
= (!restoring_FPRs_inline
22075 || (!restoring_GPRs_inline
22076 && info
->first_fp_reg_save
== 64));
22078 /* Get the old lr if we saved it. If we are restoring registers
22079 out-of-line, then the out-of-line routines can do this for us. */
22080 if (restore_lr
&& restoring_GPRs_inline
)
22081 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22083 /* Get the old cr if we saved it. */
22084 if (info
->cr_save_p
)
22086 unsigned cr_save_regno
= 12;
22088 if (!restoring_GPRs_inline
)
22090 /* Ensure we don't use the register used by the out-of-line
22091 gpr register restore below. */
22092 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
22093 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
22094 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
22096 if (gpr_ptr_regno
== 12)
22097 cr_save_regno
= 11;
22098 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
22100 else if (REGNO (frame_reg_rtx
) == 12)
22101 cr_save_regno
= 11;
22103 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
22104 info
->cr_save_offset
+ frame_off
,
22108 /* Set LR here to try to overlap restores below. */
22109 if (restore_lr
&& restoring_GPRs_inline
)
22110 restore_saved_lr (0, exit_func
);
22112 /* Load exception handler data registers, if needed. */
22113 if (crtl
->calls_eh_return
)
22115 unsigned int i
, regno
;
22119 rtx reg
= gen_rtx_REG (reg_mode
, 2);
22120 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22121 frame_off
+ 5 * reg_size
));
22128 regno
= EH_RETURN_DATA_REGNO (i
);
22129 if (regno
== INVALID_REGNUM
)
22132 /* Note: possible use of r0 here to address SPE regs. */
22133 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
22134 info
->ehrd_offset
+ frame_off
22135 + reg_size
* (int) i
);
22137 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
22141 /* Restore GPRs. This is done as a PARALLEL if we are using
22142 the load-multiple instructions. */
22144 && info
->spe_64bit_regs_used
22145 && info
->first_gp_reg_save
!= 32)
22147 /* Determine whether we can address all of the registers that need
22148 to be saved with an offset from frame_reg_rtx that fits in
22149 the small const field for SPE memory instructions. */
22150 int spe_regs_addressable
22151 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
22152 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
22153 && restoring_GPRs_inline
);
22155 if (!spe_regs_addressable
)
22157 int ool_adjust
= 0;
22158 rtx old_frame_reg_rtx
= frame_reg_rtx
;
22159 /* Make r11 point to the start of the SPE save area. We worried about
22160 not clobbering it when we were saving registers in the prologue.
22161 There's no need to worry here because the static chain is passed
22162 anew to every function. */
22164 if (!restoring_GPRs_inline
)
22165 ool_adjust
= 8 * (info
->first_gp_reg_save
22166 - (FIRST_SAVRES_REGISTER
+ 1));
22167 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22168 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
22169 GEN_INT (info
->spe_gp_save_offset
22172 /* Keep the invariant that frame_reg_rtx + frame_off points
22173 at the top of the stack frame. */
22174 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
22177 if (restoring_GPRs_inline
)
22179 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
22181 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22182 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22184 rtx offset
, addr
, mem
, reg
;
22186 /* We're doing all this to ensure that the immediate offset
22187 fits into the immediate field of 'evldd'. */
22188 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
22190 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
22191 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
22192 mem
= gen_rtx_MEM (V2SImode
, addr
);
22193 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
22195 emit_move_insn (reg
, mem
);
22199 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
22200 info
->spe_gp_save_offset
+ frame_off
,
22201 info
->lr_save_offset
+ frame_off
,
22203 SAVRES_GPR
| SAVRES_LR
);
22205 else if (!restoring_GPRs_inline
)
22207 /* We are jumping to an out-of-line function. */
22209 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
22210 bool can_use_exit
= end_save
== 0;
22211 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
22214 /* Emit stack reset code if we need it. */
22215 ptr_regno
= ptr_regno_for_savres (sel
);
22216 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22218 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
22219 else if (end_save
+ frame_off
!= 0)
22220 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
22221 GEN_INT (end_save
+ frame_off
)));
22222 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
22223 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22224 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22225 frame_off
= -end_save
;
22227 if (can_use_exit
&& info
->cr_save_p
)
22228 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
22230 ptr_off
= -end_save
;
22231 rs6000_emit_savres_rtx (info
, ptr_reg
,
22232 info
->gp_save_offset
+ ptr_off
,
22233 info
->lr_save_offset
+ ptr_off
,
22236 else if (using_load_multiple
)
22239 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
22240 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22242 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22244 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22245 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22249 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22250 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22251 emit_insn (gen_frame_load
22252 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22254 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
22257 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
22259 /* If the frame pointer was used then we can't delay emitting
22260 a REG_CFA_DEF_CFA note. This must happen on the insn that
22261 restores the frame pointer, r31. We may have already emitted
22262 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
22263 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
22264 be harmless if emitted. */
22265 if (frame_pointer_needed
)
22267 insn
= get_last_insn ();
22268 add_reg_note (insn
, REG_CFA_DEF_CFA
,
22269 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
22270 RTX_FRAME_RELATED_P (insn
) = 1;
22273 /* Set up cfa_restores. We always need these when
22274 shrink-wrapping. If not shrink-wrapping then we only need
22275 the cfa_restore when the stack location is no longer valid.
22276 The cfa_restores must be emitted on or before the insn that
22277 invalidates the stack, and of course must not be emitted
22278 before the insn that actually does the restore. The latter
22279 is why it is a bad idea to emit the cfa_restores as a group
22280 on the last instruction here that actually does a restore:
22281 That insn may be reordered with respect to others doing
22283 if (flag_shrink_wrap
22284 && !restoring_GPRs_inline
22285 && info
->first_fp_reg_save
== 64)
22286 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
22288 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
22289 if (!restoring_GPRs_inline
22290 || using_load_multiple
22291 || rs6000_reg_live_or_pic_offset_p (i
))
22293 rtx reg
= gen_rtx_REG (reg_mode
, i
);
22295 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22299 if (!restoring_GPRs_inline
22300 && info
->first_fp_reg_save
== 64)
22302 /* We are jumping to an out-of-line function. */
22304 emit_cfa_restores (cfa_restores
);
22308 if (restore_lr
&& !restoring_GPRs_inline
)
22310 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22311 restore_saved_lr (0, exit_func
);
22314 /* Restore fpr's if we need to do it without calling a function. */
22315 if (restoring_FPRs_inline
)
22316 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22317 if (save_reg_p (info
->first_fp_reg_save
+ i
))
22319 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22320 ? DFmode
: SFmode
),
22321 info
->first_fp_reg_save
+ i
);
22322 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22323 info
->fp_save_offset
+ frame_off
+ 8 * i
));
22324 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
22325 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22328 /* If we saved cr, restore it here. Just those that were used. */
22329 if (info
->cr_save_p
)
22330 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
22332 /* If this is V.4, unwind the stack pointer after all of the loads
22333 have been done, or set up r11 if we are restoring fp out of line. */
22335 if (!restoring_FPRs_inline
)
22337 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
22338 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22339 ptr_regno
= ptr_regno_for_savres (sel
);
22342 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
22343 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22346 if (insn
&& restoring_FPRs_inline
)
22350 REG_NOTES (insn
) = cfa_restores
;
22351 cfa_restores
= NULL_RTX
;
22353 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
22354 RTX_FRAME_RELATED_P (insn
) = 1;
22357 if (crtl
->calls_eh_return
)
22359 rtx sa
= EH_RETURN_STACKADJ_RTX
;
22360 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
22366 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
22367 if (! restoring_FPRs_inline
)
22369 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
22370 RTVEC_ELT (p
, 0) = ret_rtx
;
22376 /* We can't hang the cfa_restores off a simple return,
22377 since the shrink-wrap code sometimes uses an existing
22378 return. This means there might be a path from
22379 pre-prologue code to this return, and dwarf2cfi code
22380 wants the eh_frame unwinder state to be the same on
22381 all paths to any point. So we need to emit the
22382 cfa_restores before the return. For -m64 we really
22383 don't need epilogue cfa_restores at all, except for
22384 this irritating dwarf2cfi with shrink-wrap
22385 requirement; The stack red-zone means eh_frame info
22386 from the prologue telling the unwinder to restore
22387 from the stack is perfectly good right to the end of
22389 emit_insn (gen_blockage ());
22390 emit_cfa_restores (cfa_restores
);
22391 cfa_restores
= NULL_RTX
;
22393 p
= rtvec_alloc (2);
22394 RTVEC_ELT (p
, 0) = simple_return_rtx
;
22397 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
22398 ? gen_rtx_USE (VOIDmode
,
22399 gen_rtx_REG (Pmode
, LR_REGNO
))
22400 : gen_rtx_CLOBBER (VOIDmode
,
22401 gen_rtx_REG (Pmode
, LR_REGNO
)));
22403 /* If we have to restore more than two FP registers, branch to the
22404 restore function. It will return to our caller. */
22405 if (! restoring_FPRs_inline
)
22410 if (flag_shrink_wrap
)
22411 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
22413 sym
= rs6000_savres_routine_sym (info
,
22414 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
22415 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
22416 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
22417 gen_rtx_REG (Pmode
,
22418 DEFAULT_ABI
== ABI_AIX
22420 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22422 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
22424 RTVEC_ELT (p
, i
+ 4)
22425 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
22426 if (flag_shrink_wrap
)
22427 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
22432 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22438 /* Ensure the cfa_restores are hung off an insn that won't
22439 be reordered above other restores. */
22440 emit_insn (gen_blockage ());
22442 emit_cfa_restores (cfa_restores
);
22446 /* Write function epilogue. */
22449 rs6000_output_function_epilogue (FILE *file
,
22450 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
22453 macho_branch_islands ();
22454 /* Mach-O doesn't support labels at the end of objects, so if
22455 it looks like we might want one, insert a NOP. */
22457 rtx insn
= get_last_insn ();
22458 rtx deleted_debug_label
= NULL_RTX
;
22461 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
22463 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
22464 notes only, instead set their CODE_LABEL_NUMBER to -1,
22465 otherwise there would be code generation differences
22466 in between -g and -g0. */
22467 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
22468 deleted_debug_label
= insn
;
22469 insn
= PREV_INSN (insn
);
22474 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
22475 fputs ("\tnop\n", file
);
22476 else if (deleted_debug_label
)
22477 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
22478 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
22479 CODE_LABEL_NUMBER (insn
) = -1;
22483 /* Output a traceback table here. See /usr/include/sys/debug.h for info
22486 We don't output a traceback table if -finhibit-size-directive was
22487 used. The documentation for -finhibit-size-directive reads
22488 ``don't output a @code{.size} assembler directive, or anything
22489 else that would cause trouble if the function is split in the
22490 middle, and the two halves are placed at locations far apart in
22491 memory.'' The traceback table has this property, since it
22492 includes the offset from the start of the function to the
22493 traceback table itself.
22495 System V.4 Powerpc's (and the embedded ABI derived from it) use a
22496 different traceback table. */
22497 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
22498 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
22500 const char *fname
= NULL
;
22501 const char *language_string
= lang_hooks
.name
;
22502 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
22504 int optional_tbtab
;
22505 rs6000_stack_t
*info
= rs6000_stack_info ();
22507 if (rs6000_traceback
== traceback_full
)
22508 optional_tbtab
= 1;
22509 else if (rs6000_traceback
== traceback_part
)
22510 optional_tbtab
= 0;
22512 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
22514 if (optional_tbtab
)
22516 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
22517 while (*fname
== '.') /* V.4 encodes . in the name */
22520 /* Need label immediately before tbtab, so we can compute
22521 its offset from the function start. */
22522 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
22523 ASM_OUTPUT_LABEL (file
, fname
);
22526 /* The .tbtab pseudo-op can only be used for the first eight
22527 expressions, since it can't handle the possibly variable
22528 length fields that follow. However, if you omit the optional
22529 fields, the assembler outputs zeros for all optional fields
22530 anyways, giving each variable length field is minimum length
22531 (as defined in sys/debug.h). Thus we can not use the .tbtab
22532 pseudo-op at all. */
22534 /* An all-zero word flags the start of the tbtab, for debuggers
22535 that have to find it by searching forward from the entry
22536 point or from the current pc. */
22537 fputs ("\t.long 0\n", file
);
22539 /* Tbtab format type. Use format type 0. */
22540 fputs ("\t.byte 0,", file
);
22542 /* Language type. Unfortunately, there does not seem to be any
22543 official way to discover the language being compiled, so we
22544 use language_string.
22545 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
22546 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
22547 a number, so for now use 9. LTO and Go aren't assigned numbers
22548 either, so for now use 0. */
22549 if (! strcmp (language_string
, "GNU C")
22550 || ! strcmp (language_string
, "GNU GIMPLE")
22551 || ! strcmp (language_string
, "GNU Go"))
22553 else if (! strcmp (language_string
, "GNU F77")
22554 || ! strcmp (language_string
, "GNU Fortran"))
22556 else if (! strcmp (language_string
, "GNU Pascal"))
22558 else if (! strcmp (language_string
, "GNU Ada"))
22560 else if (! strcmp (language_string
, "GNU C++")
22561 || ! strcmp (language_string
, "GNU Objective-C++"))
22563 else if (! strcmp (language_string
, "GNU Java"))
22565 else if (! strcmp (language_string
, "GNU Objective-C"))
22568 gcc_unreachable ();
22569 fprintf (file
, "%d,", i
);
22571 /* 8 single bit fields: global linkage (not set for C extern linkage,
22572 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
22573 from start of procedure stored in tbtab, internal function, function
22574 has controlled storage, function has no toc, function uses fp,
22575 function logs/aborts fp operations. */
22576 /* Assume that fp operations are used if any fp reg must be saved. */
22577 fprintf (file
, "%d,",
22578 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
22580 /* 6 bitfields: function is interrupt handler, name present in
22581 proc table, function calls alloca, on condition directives
22582 (controls stack walks, 3 bits), saves condition reg, saves
22584 /* The `function calls alloca' bit seems to be set whenever reg 31 is
22585 set up as a frame pointer, even when there is no alloca call. */
22586 fprintf (file
, "%d,",
22587 ((optional_tbtab
<< 6)
22588 | ((optional_tbtab
& frame_pointer_needed
) << 5)
22589 | (info
->cr_save_p
<< 1)
22590 | (info
->lr_save_p
)));
22592 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
22594 fprintf (file
, "%d,",
22595 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
22597 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
22598 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
22600 if (optional_tbtab
)
22602 /* Compute the parameter info from the function decl argument
22605 int next_parm_info_bit
= 31;
22607 for (decl
= DECL_ARGUMENTS (current_function_decl
);
22608 decl
; decl
= DECL_CHAIN (decl
))
22610 rtx parameter
= DECL_INCOMING_RTL (decl
);
22611 enum machine_mode mode
= GET_MODE (parameter
);
22613 if (GET_CODE (parameter
) == REG
)
22615 if (SCALAR_FLOAT_MODE_P (mode
))
22636 gcc_unreachable ();
22639 /* If only one bit will fit, don't or in this entry. */
22640 if (next_parm_info_bit
> 0)
22641 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
22642 next_parm_info_bit
-= 2;
22646 fixed_parms
+= ((GET_MODE_SIZE (mode
)
22647 + (UNITS_PER_WORD
- 1))
22649 next_parm_info_bit
-= 1;
22655 /* Number of fixed point parameters. */
22656 /* This is actually the number of words of fixed point parameters; thus
22657 an 8 byte struct counts as 2; and thus the maximum value is 8. */
22658 fprintf (file
, "%d,", fixed_parms
);
22660 /* 2 bitfields: number of floating point parameters (7 bits), parameters
22662 /* This is actually the number of fp registers that hold parameters;
22663 and thus the maximum value is 13. */
22664 /* Set parameters on stack bit if parameters are not in their original
22665 registers, regardless of whether they are on the stack? Xlc
22666 seems to set the bit when not optimizing. */
22667 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
22669 if (! optional_tbtab
)
22672 /* Optional fields follow. Some are variable length. */
22674 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
22675 11 double float. */
22676 /* There is an entry for each parameter in a register, in the order that
22677 they occur in the parameter list. Any intervening arguments on the
22678 stack are ignored. If the list overflows a long (max possible length
22679 34 bits) then completely leave off all elements that don't fit. */
22680 /* Only emit this long if there was at least one parameter. */
22681 if (fixed_parms
|| float_parms
)
22682 fprintf (file
, "\t.long %d\n", parm_info
);
22684 /* Offset from start of code to tb table. */
22685 fputs ("\t.long ", file
);
22686 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
22687 RS6000_OUTPUT_BASENAME (file
, fname
);
22689 rs6000_output_function_entry (file
, fname
);
22692 /* Interrupt handler mask. */
22693 /* Omit this long, since we never set the interrupt handler bit
22696 /* Number of CTL (controlled storage) anchors. */
22697 /* Omit this long, since the has_ctl bit is never set above. */
22699 /* Displacement into stack of each CTL anchor. */
22700 /* Omit this list of longs, because there are no CTL anchors. */
22702 /* Length of function name. */
22705 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
22707 /* Function name. */
22708 assemble_string (fname
, strlen (fname
));
22710 /* Register for alloca automatic storage; this is always reg 31.
22711 Only emit this if the alloca bit was set above. */
22712 if (frame_pointer_needed
)
22713 fputs ("\t.byte 31\n", file
);
22715 fputs ("\t.align 2\n", file
);
22719 /* A C compound statement that outputs the assembler code for a thunk
22720 function, used to implement C++ virtual function calls with
22721 multiple inheritance. The thunk acts as a wrapper around a virtual
22722 function, adjusting the implicit object parameter before handing
22723 control off to the real function.
22725 First, emit code to add the integer DELTA to the location that
22726 contains the incoming first argument. Assume that this argument
22727 contains a pointer, and is the one used to pass the `this' pointer
22728 in C++. This is the incoming argument *before* the function
22729 prologue, e.g. `%o0' on a sparc. The addition must preserve the
22730 values of all other incoming arguments.
22732 After the addition, emit code to jump to FUNCTION, which is a
22733 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
22734 not touch the return address. Hence returning from FUNCTION will
22735 return to whoever called the current `thunk'.
22737 The effect must be as if FUNCTION had been called directly with the
22738 adjusted first argument. This macro is responsible for emitting
22739 all of the code for a thunk function; output_function_prologue()
22740 and output_function_epilogue() are not invoked.
22742 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
22743 been extracted from it.) It might possibly be useful on some
22744 targets, but probably not.
22746 If you do not define this macro, the target-independent code in the
22747 C++ frontend will generate a less efficient heavyweight thunk that
22748 calls FUNCTION instead of jumping to it. The generic approach does
22749 not support varargs. */
22752 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
22753 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
22756 rtx this_rtx
, insn
, funexp
;
22758 reload_completed
= 1;
22759 epilogue_completed
= 1;
22761 /* Mark the end of the (empty) prologue. */
22762 emit_note (NOTE_INSN_PROLOGUE_END
);
22764 /* Find the "this" pointer. If the function returns a structure,
22765 the structure return pointer is in r3. */
22766 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
22767 this_rtx
= gen_rtx_REG (Pmode
, 4);
22769 this_rtx
= gen_rtx_REG (Pmode
, 3);
22771 /* Apply the constant offset, if required. */
22773 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
22775 /* Apply the offset from the vtable, if required. */
22778 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
22779 rtx tmp
= gen_rtx_REG (Pmode
, 12);
22781 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
22782 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
22784 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
22785 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
22789 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
22791 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
22793 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
22796 /* Generate a tail call to the target function. */
22797 if (!TREE_USED (function
))
22799 assemble_external (function
);
22800 TREE_USED (function
) = 1;
22802 funexp
= XEXP (DECL_RTL (function
), 0);
22803 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
22806 if (MACHOPIC_INDIRECT
)
22807 funexp
= machopic_indirect_call_target (funexp
);
22810 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
22811 generate sibcall RTL explicitly. */
22812 insn
= emit_call_insn (
22813 gen_rtx_PARALLEL (VOIDmode
,
22815 gen_rtx_CALL (VOIDmode
,
22816 funexp
, const0_rtx
),
22817 gen_rtx_USE (VOIDmode
, const0_rtx
),
22818 gen_rtx_USE (VOIDmode
,
22819 gen_rtx_REG (SImode
,
22821 simple_return_rtx
)));
22822 SIBLING_CALL_P (insn
) = 1;
22825 /* Run just enough of rest_of_compilation to get the insns emitted.
22826 There's not really enough bulk here to make other passes such as
22827 instruction scheduling worth while. Note that use_thunk calls
22828 assemble_start_function and assemble_end_function. */
22829 insn
= get_insns ();
22830 shorten_branches (insn
);
22831 final_start_function (insn
, file
, 1);
22832 final (insn
, file
, 1);
22833 final_end_function ();
22835 reload_completed
= 0;
22836 epilogue_completed
= 0;
22839 /* A quick summary of the various types of 'constant-pool tables'
22842 Target Flags Name One table per
22843 AIX (none) AIX TOC object file
22844 AIX -mfull-toc AIX TOC object file
22845 AIX -mminimal-toc AIX minimal TOC translation unit
22846 SVR4/EABI (none) SVR4 SDATA object file
22847 SVR4/EABI -fpic SVR4 pic object file
22848 SVR4/EABI -fPIC SVR4 PIC translation unit
22849 SVR4/EABI -mrelocatable EABI TOC function
22850 SVR4/EABI -maix AIX TOC object file
22851 SVR4/EABI -maix -mminimal-toc
22852 AIX minimal TOC translation unit
22854 Name Reg. Set by entries contains:
22855 made by addrs? fp? sum?
22857 AIX TOC 2 crt0 as Y option option
22858 AIX minimal TOC 30 prolog gcc Y Y option
22859 SVR4 SDATA 13 crt0 gcc N Y N
22860 SVR4 pic 30 prolog ld Y not yet N
22861 SVR4 PIC 30 prolog gcc Y option option
22862 EABI TOC 30 prolog gcc Y option option
22866 /* Hash functions for the hash table. */
22869 rs6000_hash_constant (rtx k
)
22871 enum rtx_code code
= GET_CODE (k
);
22872 enum machine_mode mode
= GET_MODE (k
);
22873 unsigned result
= (code
<< 3) ^ mode
;
22874 const char *format
;
22877 format
= GET_RTX_FORMAT (code
);
22878 flen
= strlen (format
);
22884 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
22887 if (mode
!= VOIDmode
)
22888 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
22900 for (; fidx
< flen
; fidx
++)
22901 switch (format
[fidx
])
22906 const char *str
= XSTR (k
, fidx
);
22907 len
= strlen (str
);
22908 result
= result
* 613 + len
;
22909 for (i
= 0; i
< len
; i
++)
22910 result
= result
* 613 + (unsigned) str
[i
];
22915 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
22919 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
22922 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
22923 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
22927 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
22928 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
22935 gcc_unreachable ();
22942 toc_hash_function (const void *hash_entry
)
22944 const struct toc_hash_struct
*thc
=
22945 (const struct toc_hash_struct
*) hash_entry
;
22946 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
22949 /* Compare H1 and H2 for equivalence. */
22952 toc_hash_eq (const void *h1
, const void *h2
)
22954 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
22955 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
22957 if (((const struct toc_hash_struct
*) h1
)->key_mode
22958 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
22961 return rtx_equal_p (r1
, r2
);
22964 /* These are the names given by the C++ front-end to vtables, and
22965 vtable-like objects. Ideally, this logic should not be here;
22966 instead, there should be some programmatic way of inquiring as
22967 to whether or not an object is a vtable. */
22969 #define VTABLE_NAME_P(NAME) \
22970 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
22971 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
22972 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
22973 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
22974 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
22976 #ifdef NO_DOLLAR_IN_LABEL
22977 /* Return a GGC-allocated character string translating dollar signs in
22978 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
22981 rs6000_xcoff_strip_dollar (const char *name
)
22987 q
= (const char *) strchr (name
, '$');
22989 if (q
== 0 || q
== name
)
22992 len
= strlen (name
);
22993 strip
= XALLOCAVEC (char, len
+ 1);
22994 strcpy (strip
, name
);
22995 p
= strip
+ (q
- name
);
22999 p
= strchr (p
+ 1, '$');
23002 return ggc_alloc_string (strip
, len
);
23007 rs6000_output_symbol_ref (FILE *file
, rtx x
)
23009 /* Currently C++ toc references to vtables can be emitted before it
23010 is decided whether the vtable is public or private. If this is
23011 the case, then the linker will eventually complain that there is
23012 a reference to an unknown section. Thus, for vtables only,
23013 we emit the TOC reference to reference the symbol and not the
23015 const char *name
= XSTR (x
, 0);
23017 if (VTABLE_NAME_P (name
))
23019 RS6000_OUTPUT_BASENAME (file
, name
);
23022 assemble_name (file
, name
);
23025 /* Output a TOC entry. We derive the entry name from what is being
23029 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
23032 const char *name
= buf
;
23034 HOST_WIDE_INT offset
= 0;
23036 gcc_assert (!TARGET_NO_TOC
);
23038 /* When the linker won't eliminate them, don't output duplicate
23039 TOC entries (this happens on AIX if there is any kind of TOC,
23040 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
23042 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
23044 struct toc_hash_struct
*h
;
23047 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
23048 time because GGC is not initialized at that point. */
23049 if (toc_hash_table
== NULL
)
23050 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
23051 toc_hash_eq
, NULL
);
23053 h
= ggc_alloc_toc_hash_struct ();
23055 h
->key_mode
= mode
;
23056 h
->labelno
= labelno
;
23058 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
23059 if (*found
== NULL
)
23061 else /* This is indeed a duplicate.
23062 Set this label equal to that label. */
23064 fputs ("\t.set ", file
);
23065 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
23066 fprintf (file
, "%d,", labelno
);
23067 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
23068 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
23072 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
23073 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
23074 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
23076 fputs ("\t.set ", file
);
23077 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
23078 fprintf (file
, "%d,", labelno
);
23079 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
23080 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
23088 /* If we're going to put a double constant in the TOC, make sure it's
23089 aligned properly when strict alignment is on. */
23090 if (GET_CODE (x
) == CONST_DOUBLE
23091 && STRICT_ALIGNMENT
23092 && GET_MODE_BITSIZE (mode
) >= 64
23093 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
23094 ASM_OUTPUT_ALIGN (file
, 3);
23097 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
23099 /* Handle FP constants specially. Note that if we have a minimal
23100 TOC, things we put here aren't actually in the TOC, so we can allow
23102 if (GET_CODE (x
) == CONST_DOUBLE
&&
23103 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
23105 REAL_VALUE_TYPE rv
;
23108 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
23109 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
23110 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
23112 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
23116 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23117 fputs (DOUBLE_INT_ASM_OP
, file
);
23119 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
23120 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
23121 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
23122 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
23123 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
23124 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
23125 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
23126 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
23131 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23132 fputs ("\t.long ", file
);
23134 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
23135 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
23136 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
23137 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
23138 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
23139 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
23143 else if (GET_CODE (x
) == CONST_DOUBLE
&&
23144 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
23146 REAL_VALUE_TYPE rv
;
23149 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
23151 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
23152 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
23154 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
23158 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23159 fputs (DOUBLE_INT_ASM_OP
, file
);
23161 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
23162 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
23163 fprintf (file
, "0x%lx%08lx\n",
23164 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
23165 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
23170 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23171 fputs ("\t.long ", file
);
23173 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
23174 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
23175 fprintf (file
, "0x%lx,0x%lx\n",
23176 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
23180 else if (GET_CODE (x
) == CONST_DOUBLE
&&
23181 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
23183 REAL_VALUE_TYPE rv
;
23186 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
23187 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
23188 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
23190 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
23194 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23195 fputs (DOUBLE_INT_ASM_OP
, file
);
23197 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
23198 if (WORDS_BIG_ENDIAN
)
23199 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
23201 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
23206 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23207 fputs ("\t.long ", file
);
23209 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
23210 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
23214 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
23216 unsigned HOST_WIDE_INT low
;
23217 HOST_WIDE_INT high
;
23219 low
= INTVAL (x
) & 0xffffffff;
23220 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
23222 /* TOC entries are always Pmode-sized, so when big-endian
23223 smaller integer constants in the TOC need to be padded.
23224 (This is still a win over putting the constants in
23225 a separate constant pool, because then we'd have
23226 to have both a TOC entry _and_ the actual constant.)
23228 For a 32-bit target, CONST_INT values are loaded and shifted
23229 entirely within `low' and can be stored in one TOC entry. */
23231 /* It would be easy to make this work, but it doesn't now. */
23232 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
23234 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
23237 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
23238 high
= (HOST_WIDE_INT
) low
>> 32;
23244 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23245 fputs (DOUBLE_INT_ASM_OP
, file
);
23247 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
23248 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23249 fprintf (file
, "0x%lx%08lx\n",
23250 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23255 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
23257 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23258 fputs ("\t.long ", file
);
23260 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
23261 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23262 fprintf (file
, "0x%lx,0x%lx\n",
23263 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23267 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23268 fputs ("\t.long ", file
);
23270 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
23271 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
23277 if (GET_CODE (x
) == CONST
)
23279 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
23280 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
23282 base
= XEXP (XEXP (x
, 0), 0);
23283 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
23286 switch (GET_CODE (base
))
23289 name
= XSTR (base
, 0);
23293 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
23294 CODE_LABEL_NUMBER (XEXP (base
, 0)));
23298 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
23302 gcc_unreachable ();
23305 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23306 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
23309 fputs ("\t.tc ", file
);
23310 RS6000_OUTPUT_BASENAME (file
, name
);
23313 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
23315 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
23317 /* Mark large TOC symbols on AIX with [TE] so they are mapped
23318 after other TOC symbols, reducing overflow of small TOC access
23319 to [TC] symbols. */
23320 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
23321 ? "[TE]," : "[TC],", file
);
23324 /* Currently C++ toc references to vtables can be emitted before it
23325 is decided whether the vtable is public or private. If this is
23326 the case, then the linker will eventually complain that there is
23327 a TOC reference to an unknown section. Thus, for vtables only,
23328 we emit the TOC reference to reference the symbol and not the
23330 if (VTABLE_NAME_P (name
))
23332 RS6000_OUTPUT_BASENAME (file
, name
);
23334 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
23335 else if (offset
> 0)
23336 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
23339 output_addr_const (file
, x
);
23342 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
23343 && SYMBOL_REF_TLS_MODEL (base
) != 0)
23345 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
23346 fputs ("@le", file
);
23347 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
23348 fputs ("@ie", file
);
23349 /* Use global-dynamic for local-dynamic. */
23350 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
23351 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
23354 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
23355 fputs ("\t.tc .", file
);
23356 RS6000_OUTPUT_BASENAME (file
, name
);
23357 fputs ("[TC],", file
);
23358 output_addr_const (file
, x
);
23359 fputs ("@m", file
);
23367 /* Output an assembler pseudo-op to write an ASCII string of N characters
23368 starting at P to FILE.
23370 On the RS/6000, we have to do this using the .byte operation and
23371 write out special characters outside the quoted string.
23372 Also, the assembler is broken; very long strings are truncated,
23373 so we must artificially break them up early. */
23376 output_ascii (FILE *file
, const char *p
, int n
)
23379 int i
, count_string
;
23380 const char *for_string
= "\t.byte \"";
23381 const char *for_decimal
= "\t.byte ";
23382 const char *to_close
= NULL
;
23385 for (i
= 0; i
< n
; i
++)
23388 if (c
>= ' ' && c
< 0177)
23391 fputs (for_string
, file
);
23394 /* Write two quotes to get one. */
23402 for_decimal
= "\"\n\t.byte ";
23406 if (count_string
>= 512)
23408 fputs (to_close
, file
);
23410 for_string
= "\t.byte \"";
23411 for_decimal
= "\t.byte ";
23419 fputs (for_decimal
, file
);
23420 fprintf (file
, "%d", c
);
23422 for_string
= "\n\t.byte \"";
23423 for_decimal
= ", ";
23429 /* Now close the string if we have written one. Then end the line. */
23431 fputs (to_close
, file
);
23434 /* Generate a unique section name for FILENAME for a section type
23435 represented by SECTION_DESC. Output goes into BUF.
23437 SECTION_DESC can be any string, as long as it is different for each
23438 possible section type.
23440 We name the section in the same manner as xlc. The name begins with an
23441 underscore followed by the filename (after stripping any leading directory
23442 names) with the last period replaced by the string SECTION_DESC. If
23443 FILENAME does not contain a period, SECTION_DESC is appended to the end of
23447 rs6000_gen_section_name (char **buf
, const char *filename
,
23448 const char *section_desc
)
23450 const char *q
, *after_last_slash
, *last_period
= 0;
23454 after_last_slash
= filename
;
23455 for (q
= filename
; *q
; q
++)
23458 after_last_slash
= q
+ 1;
23459 else if (*q
== '.')
23463 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
23464 *buf
= (char *) xmalloc (len
);
23469 for (q
= after_last_slash
; *q
; q
++)
23471 if (q
== last_period
)
23473 strcpy (p
, section_desc
);
23474 p
+= strlen (section_desc
);
23478 else if (ISALNUM (*q
))
23482 if (last_period
== 0)
23483 strcpy (p
, section_desc
);
23488 /* Emit profile function. */
23491 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
23493 /* Non-standard profiling for kernels, which just saves LR then calls
23494 _mcount without worrying about arg saves. The idea is to change
23495 the function prologue as little as possible as it isn't easy to
23496 account for arg save/restore code added just for _mcount. */
23497 if (TARGET_PROFILE_KERNEL
)
23500 if (DEFAULT_ABI
== ABI_AIX
)
23502 #ifndef NO_PROFILE_COUNTERS
23503 # define NO_PROFILE_COUNTERS 0
23505 if (NO_PROFILE_COUNTERS
)
23506 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
23507 LCT_NORMAL
, VOIDmode
, 0);
23511 const char *label_name
;
23514 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
23515 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
23516 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
23518 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
23519 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
23522 else if (DEFAULT_ABI
== ABI_DARWIN
)
23524 const char *mcount_name
= RS6000_MCOUNT
;
23525 int caller_addr_regno
= LR_REGNO
;
23527 /* Be conservative and always set this, at least for now. */
23528 crtl
->uses_pic_offset_table
= 1;
23531 /* For PIC code, set up a stub and collect the caller's address
23532 from r0, which is where the prologue puts it. */
23533 if (MACHOPIC_INDIRECT
23534 && crtl
->uses_pic_offset_table
)
23535 caller_addr_regno
= 0;
23537 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
23538 LCT_NORMAL
, VOIDmode
, 1,
23539 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
23543 /* Write function profiler code. */
23546 output_function_profiler (FILE *file
, int labelno
)
23550 switch (DEFAULT_ABI
)
23553 gcc_unreachable ();
23558 warning (0, "no profiling of 64-bit code for this ABI");
23561 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
23562 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23563 if (NO_PROFILE_COUNTERS
)
23565 asm_fprintf (file
, "\tstw %s,4(%s)\n",
23566 reg_names
[0], reg_names
[1]);
23568 else if (TARGET_SECURE_PLT
&& flag_pic
)
23570 if (TARGET_LINK_STACK
)
23573 get_ppc476_thunk_name (name
);
23574 asm_fprintf (file
, "\tbl %s\n", name
);
23577 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
23578 asm_fprintf (file
, "\tstw %s,4(%s)\n",
23579 reg_names
[0], reg_names
[1]);
23580 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
23581 asm_fprintf (file
, "\taddis %s,%s,",
23582 reg_names
[12], reg_names
[12]);
23583 assemble_name (file
, buf
);
23584 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
23585 assemble_name (file
, buf
);
23586 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
23588 else if (flag_pic
== 1)
23590 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
23591 asm_fprintf (file
, "\tstw %s,4(%s)\n",
23592 reg_names
[0], reg_names
[1]);
23593 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
23594 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
23595 assemble_name (file
, buf
);
23596 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
23598 else if (flag_pic
> 1)
23600 asm_fprintf (file
, "\tstw %s,4(%s)\n",
23601 reg_names
[0], reg_names
[1]);
23602 /* Now, we need to get the address of the label. */
23603 if (TARGET_LINK_STACK
)
23606 get_ppc476_thunk_name (name
);
23607 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
23608 assemble_name (file
, buf
);
23609 fputs ("-.\n1:", file
);
23610 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
23611 asm_fprintf (file
, "\taddi %s,%s,4\n",
23612 reg_names
[11], reg_names
[11]);
23616 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
23617 assemble_name (file
, buf
);
23618 fputs ("-.\n1:", file
);
23619 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
23621 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
23622 reg_names
[0], reg_names
[11]);
23623 asm_fprintf (file
, "\tadd %s,%s,%s\n",
23624 reg_names
[0], reg_names
[0], reg_names
[11]);
23628 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
23629 assemble_name (file
, buf
);
23630 fputs ("@ha\n", file
);
23631 asm_fprintf (file
, "\tstw %s,4(%s)\n",
23632 reg_names
[0], reg_names
[1]);
23633 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
23634 assemble_name (file
, buf
);
23635 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
23638 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
23639 fprintf (file
, "\tbl %s%s\n",
23640 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
23645 if (!TARGET_PROFILE_KERNEL
)
23647 /* Don't do anything, done in output_profile_hook (). */
23651 gcc_assert (!TARGET_32BIT
);
23653 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23654 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23656 if (cfun
->static_chain_decl
!= NULL
)
23658 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23659 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23660 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23661 asm_fprintf (file
, "\tld %s,24(%s)\n",
23662 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23665 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23673 /* The following variable value is the last issued insn. */
23675 static rtx last_scheduled_insn
;
23677 /* The following variable helps to balance issuing of load and
23678 store instructions */
23680 static int load_store_pendulum
;
23682 /* Power4 load update and store update instructions are cracked into a
23683 load or store and an integer insn which are executed in the same cycle.
23684 Branches have their own dispatch slot which does not count against the
23685 GCC issue rate, but it changes the program flow so there are no other
23686 instructions to issue in this cycle. */
23689 rs6000_variable_issue_1 (rtx insn
, int more
)
23691 last_scheduled_insn
= insn
;
23692 if (GET_CODE (PATTERN (insn
)) == USE
23693 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23695 cached_can_issue_more
= more
;
23696 return cached_can_issue_more
;
23699 if (insn_terminates_group_p (insn
, current_group
))
23701 cached_can_issue_more
= 0;
23702 return cached_can_issue_more
;
23705 /* If no reservation, but reach here */
23706 if (recog_memoized (insn
) < 0)
23709 if (rs6000_sched_groups
)
23711 if (is_microcoded_insn (insn
))
23712 cached_can_issue_more
= 0;
23713 else if (is_cracked_insn (insn
))
23714 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
23716 cached_can_issue_more
= more
- 1;
23718 return cached_can_issue_more
;
23721 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
23724 cached_can_issue_more
= more
- 1;
23725 return cached_can_issue_more
;
23729 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
23731 int r
= rs6000_variable_issue_1 (insn
, more
);
23733 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
23737 /* Adjust the cost of a scheduling dependency. Return the new cost of
23738 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
23741 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
23743 enum attr_type attr_type
;
23745 if (! recog_memoized (insn
))
23748 switch (REG_NOTE_KIND (link
))
23752 /* Data dependency; DEP_INSN writes a register that INSN reads
23753 some cycles later. */
23755 /* Separate a load from a narrower, dependent store. */
23756 if (rs6000_sched_groups
23757 && GET_CODE (PATTERN (insn
)) == SET
23758 && GET_CODE (PATTERN (dep_insn
)) == SET
23759 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
23760 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
23761 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
23762 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
23765 attr_type
= get_attr_type (insn
);
23770 /* Tell the first scheduling pass about the latency between
23771 a mtctr and bctr (and mtlr and br/blr). The first
23772 scheduling pass will not know about this latency since
23773 the mtctr instruction, which has the latency associated
23774 to it, will be generated by reload. */
23777 /* Leave some extra cycles between a compare and its
23778 dependent branch, to inhibit expensive mispredicts. */
23779 if ((rs6000_cpu_attr
== CPU_PPC603
23780 || rs6000_cpu_attr
== CPU_PPC604
23781 || rs6000_cpu_attr
== CPU_PPC604E
23782 || rs6000_cpu_attr
== CPU_PPC620
23783 || rs6000_cpu_attr
== CPU_PPC630
23784 || rs6000_cpu_attr
== CPU_PPC750
23785 || rs6000_cpu_attr
== CPU_PPC7400
23786 || rs6000_cpu_attr
== CPU_PPC7450
23787 || rs6000_cpu_attr
== CPU_PPCE5500
23788 || rs6000_cpu_attr
== CPU_PPCE6500
23789 || rs6000_cpu_attr
== CPU_POWER4
23790 || rs6000_cpu_attr
== CPU_POWER5
23791 || rs6000_cpu_attr
== CPU_POWER7
23792 || rs6000_cpu_attr
== CPU_POWER8
23793 || rs6000_cpu_attr
== CPU_CELL
)
23794 && recog_memoized (dep_insn
)
23795 && (INSN_CODE (dep_insn
) >= 0))
23797 switch (get_attr_type (dep_insn
))
23801 case TYPE_DELAYED_COMPARE
:
23802 case TYPE_IMUL_COMPARE
:
23803 case TYPE_LMUL_COMPARE
:
23804 case TYPE_FPCOMPARE
:
23805 case TYPE_CR_LOGICAL
:
23806 case TYPE_DELAYED_CR
:
23815 case TYPE_STORE_UX
:
23817 case TYPE_FPSTORE_U
:
23818 case TYPE_FPSTORE_UX
:
23819 if ((rs6000_cpu
== PROCESSOR_POWER6
)
23820 && recog_memoized (dep_insn
)
23821 && (INSN_CODE (dep_insn
) >= 0))
23824 if (GET_CODE (PATTERN (insn
)) != SET
)
23825 /* If this happens, we have to extend this to schedule
23826 optimally. Return default for now. */
23829 /* Adjust the cost for the case where the value written
23830 by a fixed point operation is used as the address
23831 gen value on a store. */
23832 switch (get_attr_type (dep_insn
))
23839 if (! store_data_bypass_p (dep_insn
, insn
))
23843 case TYPE_LOAD_EXT
:
23844 case TYPE_LOAD_EXT_U
:
23845 case TYPE_LOAD_EXT_UX
:
23846 case TYPE_VAR_SHIFT_ROTATE
:
23847 case TYPE_VAR_DELAYED_COMPARE
:
23849 if (! store_data_bypass_p (dep_insn
, insn
))
23855 case TYPE_FAST_COMPARE
:
23858 case TYPE_INSERT_WORD
:
23859 case TYPE_INSERT_DWORD
:
23860 case TYPE_FPLOAD_U
:
23861 case TYPE_FPLOAD_UX
:
23863 case TYPE_STORE_UX
:
23864 case TYPE_FPSTORE_U
:
23865 case TYPE_FPSTORE_UX
:
23867 if (! store_data_bypass_p (dep_insn
, insn
))
23875 case TYPE_IMUL_COMPARE
:
23876 case TYPE_LMUL_COMPARE
:
23878 if (! store_data_bypass_p (dep_insn
, insn
))
23884 if (! store_data_bypass_p (dep_insn
, insn
))
23890 if (! store_data_bypass_p (dep_insn
, insn
))
23903 case TYPE_LOAD_EXT
:
23904 case TYPE_LOAD_EXT_U
:
23905 case TYPE_LOAD_EXT_UX
:
23906 if ((rs6000_cpu
== PROCESSOR_POWER6
)
23907 && recog_memoized (dep_insn
)
23908 && (INSN_CODE (dep_insn
) >= 0))
23911 /* Adjust the cost for the case where the value written
23912 by a fixed point instruction is used within the address
23913 gen portion of a subsequent load(u)(x) */
23914 switch (get_attr_type (dep_insn
))
23921 if (set_to_load_agen (dep_insn
, insn
))
23925 case TYPE_LOAD_EXT
:
23926 case TYPE_LOAD_EXT_U
:
23927 case TYPE_LOAD_EXT_UX
:
23928 case TYPE_VAR_SHIFT_ROTATE
:
23929 case TYPE_VAR_DELAYED_COMPARE
:
23931 if (set_to_load_agen (dep_insn
, insn
))
23937 case TYPE_FAST_COMPARE
:
23940 case TYPE_INSERT_WORD
:
23941 case TYPE_INSERT_DWORD
:
23942 case TYPE_FPLOAD_U
:
23943 case TYPE_FPLOAD_UX
:
23945 case TYPE_STORE_UX
:
23946 case TYPE_FPSTORE_U
:
23947 case TYPE_FPSTORE_UX
:
23949 if (set_to_load_agen (dep_insn
, insn
))
23957 case TYPE_IMUL_COMPARE
:
23958 case TYPE_LMUL_COMPARE
:
23960 if (set_to_load_agen (dep_insn
, insn
))
23966 if (set_to_load_agen (dep_insn
, insn
))
23972 if (set_to_load_agen (dep_insn
, insn
))
23983 if ((rs6000_cpu
== PROCESSOR_POWER6
)
23984 && recog_memoized (dep_insn
)
23985 && (INSN_CODE (dep_insn
) >= 0)
23986 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
23993 /* Fall out to return default cost. */
23997 case REG_DEP_OUTPUT
:
23998 /* Output dependency; DEP_INSN writes a register that INSN writes some
24000 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24001 && recog_memoized (dep_insn
)
24002 && (INSN_CODE (dep_insn
) >= 0))
24004 attr_type
= get_attr_type (insn
);
24009 if (get_attr_type (dep_insn
) == TYPE_FP
)
24013 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
24021 /* Anti dependency; DEP_INSN reads a register that INSN writes some
24026 gcc_unreachable ();
24032 /* Debug version of rs6000_adjust_cost. */
24035 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
24037 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
24043 switch (REG_NOTE_KIND (link
))
24045 default: dep
= "unknown depencency"; break;
24046 case REG_DEP_TRUE
: dep
= "data dependency"; break;
24047 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
24048 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
24052 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
24053 "%s, insn:\n", ret
, cost
, dep
);
24061 /* The function returns a true if INSN is microcoded.
24062 Return false otherwise. */
24065 is_microcoded_insn (rtx insn
)
24067 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24068 || GET_CODE (PATTERN (insn
)) == USE
24069 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24072 if (rs6000_cpu_attr
== CPU_CELL
)
24073 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
24075 if (rs6000_sched_groups
)
24077 enum attr_type type
= get_attr_type (insn
);
24078 if (type
== TYPE_LOAD_EXT_U
24079 || type
== TYPE_LOAD_EXT_UX
24080 || type
== TYPE_LOAD_UX
24081 || type
== TYPE_STORE_UX
24082 || type
== TYPE_MFCR
)
24089 /* The function returns true if INSN is cracked into 2 instructions
24090 by the processor (and therefore occupies 2 issue slots). */
24093 is_cracked_insn (rtx insn
)
24095 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24096 || GET_CODE (PATTERN (insn
)) == USE
24097 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24100 if (rs6000_sched_groups
)
24102 enum attr_type type
= get_attr_type (insn
);
24103 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
24104 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
24105 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
24106 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
24107 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
24108 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
24109 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
24110 || type
== TYPE_INSERT_WORD
)
24117 /* The function returns true if INSN can be issued only from
24118 the branch slot. */
24121 is_branch_slot_insn (rtx insn
)
24123 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24124 || GET_CODE (PATTERN (insn
)) == USE
24125 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24128 if (rs6000_sched_groups
)
24130 enum attr_type type
= get_attr_type (insn
);
24131 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
24139 /* The function returns true if out_inst sets a value that is
24140 used in the address generation computation of in_insn */
24142 set_to_load_agen (rtx out_insn
, rtx in_insn
)
24144 rtx out_set
, in_set
;
24146 /* For performance reasons, only handle the simple case where
24147 both loads are a single_set. */
24148 out_set
= single_set (out_insn
);
24151 in_set
= single_set (in_insn
);
24153 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
24159 /* Try to determine base/offset/size parts of the given MEM.
24160 Return true if successful, false if all the values couldn't
24163 This function only looks for REG or REG+CONST address forms.
24164 REG+REG address form will return false. */
24167 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
24168 HOST_WIDE_INT
*size
)
24171 if MEM_SIZE_KNOWN_P (mem
)
24172 *size
= MEM_SIZE (mem
);
24176 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
24177 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
24179 addr_rtx
= (XEXP (mem
, 0));
24181 if (GET_CODE (addr_rtx
) == REG
)
24186 else if (GET_CODE (addr_rtx
) == PLUS
24187 && CONST_INT_P (XEXP (addr_rtx
, 1)))
24189 *base
= XEXP (addr_rtx
, 0);
24190 *offset
= INTVAL (XEXP (addr_rtx
, 1));
24198 /* The function returns true if the target storage location of
24199 mem1 is adjacent to the target storage location of mem2 */
24200 /* Return 1 if memory locations are adjacent. */
24203 adjacent_mem_locations (rtx mem1
, rtx mem2
)
24206 HOST_WIDE_INT off1
, size1
, off2
, size2
;
24208 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
24209 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
24210 return ((REGNO (reg1
) == REGNO (reg2
))
24211 && ((off1
+ size1
== off2
)
24212 || (off2
+ size2
== off1
)));
24217 /* This function returns true if it can be determined that the two MEM
24218 locations overlap by at least 1 byte based on base reg/offset/size. */
24221 mem_locations_overlap (rtx mem1
, rtx mem2
)
24224 HOST_WIDE_INT off1
, size1
, off2
, size2
;
24226 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
24227 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
24228 return ((REGNO (reg1
) == REGNO (reg2
))
24229 && (((off1
<= off2
) && (off1
+ size1
> off2
))
24230 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
24235 /* A C statement (sans semicolon) to update the integer scheduling
24236 priority INSN_PRIORITY (INSN). Increase the priority to execute the
24237 INSN earlier, reduce the priority to execute INSN later. Do not
24238 define this macro if you do not need to adjust the scheduling
24239 priorities of insns. */
24242 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
24244 rtx load_mem
, str_mem
;
24245 /* On machines (like the 750) which have asymmetric integer units,
24246 where one integer unit can do multiply and divides and the other
24247 can't, reduce the priority of multiply/divide so it is scheduled
24248 before other integer operations. */
24251 if (! INSN_P (insn
))
24254 if (GET_CODE (PATTERN (insn
)) == USE
)
24257 switch (rs6000_cpu_attr
) {
24259 switch (get_attr_type (insn
))
24266 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
24267 priority
, priority
);
24268 if (priority
>= 0 && priority
< 0x01000000)
24275 if (insn_must_be_first_in_group (insn
)
24276 && reload_completed
24277 && current_sched_info
->sched_max_insns_priority
24278 && rs6000_sched_restricted_insns_priority
)
24281 /* Prioritize insns that can be dispatched only in the first
24283 if (rs6000_sched_restricted_insns_priority
== 1)
24284 /* Attach highest priority to insn. This means that in
24285 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
24286 precede 'priority' (critical path) considerations. */
24287 return current_sched_info
->sched_max_insns_priority
;
24288 else if (rs6000_sched_restricted_insns_priority
== 2)
24289 /* Increase priority of insn by a minimal amount. This means that in
24290 haifa-sched.c:ready_sort(), only 'priority' (critical path)
24291 considerations precede dispatch-slot restriction considerations. */
24292 return (priority
+ 1);
24295 if (rs6000_cpu
== PROCESSOR_POWER6
24296 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
24297 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
24298 /* Attach highest priority to insn if the scheduler has just issued two
24299 stores and this instruction is a load, or two loads and this instruction
24300 is a store. Power6 wants loads and stores scheduled alternately
24302 return current_sched_info
->sched_max_insns_priority
;
24307 /* Return true if the instruction is nonpipelined on the Cell. */
24309 is_nonpipeline_insn (rtx insn
)
24311 enum attr_type type
;
24312 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24313 || GET_CODE (PATTERN (insn
)) == USE
24314 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24317 type
= get_attr_type (insn
);
24318 if (type
== TYPE_IMUL
24319 || type
== TYPE_IMUL2
24320 || type
== TYPE_IMUL3
24321 || type
== TYPE_LMUL
24322 || type
== TYPE_IDIV
24323 || type
== TYPE_LDIV
24324 || type
== TYPE_SDIV
24325 || type
== TYPE_DDIV
24326 || type
== TYPE_SSQRT
24327 || type
== TYPE_DSQRT
24328 || type
== TYPE_MFCR
24329 || type
== TYPE_MFCRF
24330 || type
== TYPE_MFJMPR
)
24338 /* Return how many instructions the machine can issue per cycle. */
24341 rs6000_issue_rate (void)
24343 /* Unless scheduling for register pressure, use issue rate of 1 for
24344 first scheduling pass to decrease degradation. */
24345 if (!reload_completed
&& !flag_sched_pressure
)
24348 switch (rs6000_cpu_attr
) {
24350 case CPU_PPC601
: /* ? */
24360 case CPU_PPCE300C2
:
24361 case CPU_PPCE300C3
:
24362 case CPU_PPCE500MC
:
24363 case CPU_PPCE500MC64
:
24386 /* Return how many instructions to look ahead for better insn
24390 rs6000_use_sched_lookahead (void)
24392 switch (rs6000_cpu_attr
)
24399 return (reload_completed
? 8 : 0);
24406 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
24408 rs6000_use_sched_lookahead_guard (rtx insn
)
24410 if (rs6000_cpu_attr
!= CPU_CELL
)
24413 if (insn
== NULL_RTX
|| !INSN_P (insn
))
24416 if (!reload_completed
24417 || is_nonpipeline_insn (insn
)
24418 || is_microcoded_insn (insn
))
24424 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
24425 and return true. */
24428 find_mem_ref (rtx pat
, rtx
*mem_ref
)
24433 /* stack_tie does not produce any real memory traffic. */
24434 if (tie_operand (pat
, VOIDmode
))
24437 if (GET_CODE (pat
) == MEM
)
24443 /* Recursively process the pattern. */
24444 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
24446 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
24450 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
24453 else if (fmt
[i
] == 'E')
24454 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
24456 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
24464 /* Determine if PAT is a PATTERN of a load insn. */
24467 is_load_insn1 (rtx pat
, rtx
*load_mem
)
24469 if (!pat
|| pat
== NULL_RTX
)
24472 if (GET_CODE (pat
) == SET
)
24473 return find_mem_ref (SET_SRC (pat
), load_mem
);
24475 if (GET_CODE (pat
) == PARALLEL
)
24479 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
24480 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
24487 /* Determine if INSN loads from memory. */
24490 is_load_insn (rtx insn
, rtx
*load_mem
)
24492 if (!insn
|| !INSN_P (insn
))
24498 return is_load_insn1 (PATTERN (insn
), load_mem
);
24501 /* Determine if PAT is a PATTERN of a store insn. */
24504 is_store_insn1 (rtx pat
, rtx
*str_mem
)
24506 if (!pat
|| pat
== NULL_RTX
)
24509 if (GET_CODE (pat
) == SET
)
24510 return find_mem_ref (SET_DEST (pat
), str_mem
);
24512 if (GET_CODE (pat
) == PARALLEL
)
24516 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
24517 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
24524 /* Determine if INSN stores to memory. */
24527 is_store_insn (rtx insn
, rtx
*str_mem
)
24529 if (!insn
|| !INSN_P (insn
))
24532 return is_store_insn1 (PATTERN (insn
), str_mem
);
24535 /* Returns whether the dependence between INSN and NEXT is considered
24536 costly by the given target. */
24539 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
24543 rtx load_mem
, str_mem
;
24545 /* If the flag is not enabled - no dependence is considered costly;
24546 allow all dependent insns in the same group.
24547 This is the most aggressive option. */
24548 if (rs6000_sched_costly_dep
== no_dep_costly
)
24551 /* If the flag is set to 1 - a dependence is always considered costly;
24552 do not allow dependent instructions in the same group.
24553 This is the most conservative option. */
24554 if (rs6000_sched_costly_dep
== all_deps_costly
)
24557 insn
= DEP_PRO (dep
);
24558 next
= DEP_CON (dep
);
24560 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
24561 && is_load_insn (next
, &load_mem
)
24562 && is_store_insn (insn
, &str_mem
))
24563 /* Prevent load after store in the same group. */
24566 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
24567 && is_load_insn (next
, &load_mem
)
24568 && is_store_insn (insn
, &str_mem
)
24569 && DEP_TYPE (dep
) == REG_DEP_TRUE
24570 && mem_locations_overlap(str_mem
, load_mem
))
24571 /* Prevent load after store in the same group if it is a true
24575 /* The flag is set to X; dependences with latency >= X are considered costly,
24576 and will not be scheduled in the same group. */
24577 if (rs6000_sched_costly_dep
<= max_dep_latency
24578 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
24584 /* Return the next insn after INSN that is found before TAIL is reached,
24585 skipping any "non-active" insns - insns that will not actually occupy
24586 an issue slot. Return NULL_RTX if such an insn is not found. */
24589 get_next_active_insn (rtx insn
, rtx tail
)
24591 if (insn
== NULL_RTX
|| insn
== tail
)
24596 insn
= NEXT_INSN (insn
);
24597 if (insn
== NULL_RTX
|| insn
== tail
)
24601 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
24602 || (NONJUMP_INSN_P (insn
)
24603 && GET_CODE (PATTERN (insn
)) != USE
24604 && GET_CODE (PATTERN (insn
)) != CLOBBER
24605 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
24611 /* We are about to begin issuing insns for this clock cycle. */
24614 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
24615 rtx
*ready ATTRIBUTE_UNUSED
,
24616 int *pn_ready ATTRIBUTE_UNUSED
,
24617 int clock_var ATTRIBUTE_UNUSED
)
24619 int n_ready
= *pn_ready
;
24622 fprintf (dump
, "// rs6000_sched_reorder :\n");
24624 /* Reorder the ready list, if the second to last ready insn
24625 is a nonepipeline insn. */
24626 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
24628 if (is_nonpipeline_insn (ready
[n_ready
- 1])
24629 && (recog_memoized (ready
[n_ready
- 2]) > 0))
24630 /* Simply swap first two insns. */
24632 rtx tmp
= ready
[n_ready
- 1];
24633 ready
[n_ready
- 1] = ready
[n_ready
- 2];
24634 ready
[n_ready
- 2] = tmp
;
24638 if (rs6000_cpu
== PROCESSOR_POWER6
)
24639 load_store_pendulum
= 0;
24641 return rs6000_issue_rate ();
24644 /* Like rs6000_sched_reorder, but called after issuing each insn. */
24647 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
24648 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
24651 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
24653 /* For Power6, we need to handle some special cases to try and keep the
24654 store queue from overflowing and triggering expensive flushes.
24656 This code monitors how load and store instructions are being issued
24657 and skews the ready list one way or the other to increase the likelihood
24658 that a desired instruction is issued at the proper time.
24660 A couple of things are done. First, we maintain a "load_store_pendulum"
24661 to track the current state of load/store issue.
24663 - If the pendulum is at zero, then no loads or stores have been
24664 issued in the current cycle so we do nothing.
24666 - If the pendulum is 1, then a single load has been issued in this
24667 cycle and we attempt to locate another load in the ready list to
24670 - If the pendulum is -2, then two stores have already been
24671 issued in this cycle, so we increase the priority of the first load
24672 in the ready list to increase it's likelihood of being chosen first
24675 - If the pendulum is -1, then a single store has been issued in this
24676 cycle and we attempt to locate another store in the ready list to
24677 issue with it, preferring a store to an adjacent memory location to
24678 facilitate store pairing in the store queue.
24680 - If the pendulum is 2, then two loads have already been
24681 issued in this cycle, so we increase the priority of the first store
24682 in the ready list to increase it's likelihood of being chosen first
24685 - If the pendulum < -2 or > 2, then do nothing.
24687 Note: This code covers the most common scenarios. There exist non
24688 load/store instructions which make use of the LSU and which
24689 would need to be accounted for to strictly model the behavior
24690 of the machine. Those instructions are currently unaccounted
24691 for to help minimize compile time overhead of this code.
24693 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
24697 rtx tmp
, load_mem
, str_mem
;
24699 if (is_store_insn (last_scheduled_insn
, &str_mem
))
24700 /* Issuing a store, swing the load_store_pendulum to the left */
24701 load_store_pendulum
--;
24702 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
24703 /* Issuing a load, swing the load_store_pendulum to the right */
24704 load_store_pendulum
++;
24706 return cached_can_issue_more
;
24708 /* If the pendulum is balanced, or there is only one instruction on
24709 the ready list, then all is well, so return. */
24710 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
24711 return cached_can_issue_more
;
24713 if (load_store_pendulum
== 1)
24715 /* A load has been issued in this cycle. Scan the ready list
24716 for another load to issue with it */
24721 if (is_load_insn (ready
[pos
], &load_mem
))
24723 /* Found a load. Move it to the head of the ready list,
24724 and adjust it's priority so that it is more likely to
24727 for (i
=pos
; i
<*pn_ready
-1; i
++)
24728 ready
[i
] = ready
[i
+ 1];
24729 ready
[*pn_ready
-1] = tmp
;
24731 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
24732 INSN_PRIORITY (tmp
)++;
24738 else if (load_store_pendulum
== -2)
24740 /* Two stores have been issued in this cycle. Increase the
24741 priority of the first load in the ready list to favor it for
24742 issuing in the next cycle. */
24747 if (is_load_insn (ready
[pos
], &load_mem
)
24749 && INSN_PRIORITY_KNOWN (ready
[pos
]))
24751 INSN_PRIORITY (ready
[pos
])++;
24753 /* Adjust the pendulum to account for the fact that a load
24754 was found and increased in priority. This is to prevent
24755 increasing the priority of multiple loads */
24756 load_store_pendulum
--;
24763 else if (load_store_pendulum
== -1)
24765 /* A store has been issued in this cycle. Scan the ready list for
24766 another store to issue with it, preferring a store to an adjacent
24768 int first_store_pos
= -1;
24774 if (is_store_insn (ready
[pos
], &str_mem
))
24777 /* Maintain the index of the first store found on the
24779 if (first_store_pos
== -1)
24780 first_store_pos
= pos
;
24782 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
24783 && adjacent_mem_locations (str_mem
, str_mem2
))
24785 /* Found an adjacent store. Move it to the head of the
24786 ready list, and adjust it's priority so that it is
24787 more likely to stay there */
24789 for (i
=pos
; i
<*pn_ready
-1; i
++)
24790 ready
[i
] = ready
[i
+ 1];
24791 ready
[*pn_ready
-1] = tmp
;
24793 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
24794 INSN_PRIORITY (tmp
)++;
24796 first_store_pos
= -1;
24804 if (first_store_pos
>= 0)
24806 /* An adjacent store wasn't found, but a non-adjacent store was,
24807 so move the non-adjacent store to the front of the ready
24808 list, and adjust its priority so that it is more likely to
24810 tmp
= ready
[first_store_pos
];
24811 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
24812 ready
[i
] = ready
[i
+ 1];
24813 ready
[*pn_ready
-1] = tmp
;
24814 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
24815 INSN_PRIORITY (tmp
)++;
24818 else if (load_store_pendulum
== 2)
24820 /* Two loads have been issued in this cycle. Increase the priority
24821 of the first store in the ready list to favor it for issuing in
24827 if (is_store_insn (ready
[pos
], &str_mem
)
24829 && INSN_PRIORITY_KNOWN (ready
[pos
]))
24831 INSN_PRIORITY (ready
[pos
])++;
24833 /* Adjust the pendulum to account for the fact that a store
24834 was found and increased in priority. This is to prevent
24835 increasing the priority of multiple stores */
24836 load_store_pendulum
++;
24845 return cached_can_issue_more
;
24848 /* Return whether the presence of INSN causes a dispatch group termination
24849 of group WHICH_GROUP.
24851 If WHICH_GROUP == current_group, this function will return true if INSN
24852 causes the termination of the current group (i.e, the dispatch group to
24853 which INSN belongs). This means that INSN will be the last insn in the
24854 group it belongs to.
24856 If WHICH_GROUP == previous_group, this function will return true if INSN
24857 causes the termination of the previous group (i.e, the dispatch group that
24858 precedes the group to which INSN belongs). This means that INSN will be
24859 the first insn in the group it belongs to). */
24862 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
24869 first
= insn_must_be_first_in_group (insn
);
24870 last
= insn_must_be_last_in_group (insn
);
24875 if (which_group
== current_group
)
24877 else if (which_group
== previous_group
)
24885 insn_must_be_first_in_group (rtx insn
)
24887 enum attr_type type
;
24891 || DEBUG_INSN_P (insn
)
24892 || GET_CODE (PATTERN (insn
)) == USE
24893 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24896 switch (rs6000_cpu
)
24898 case PROCESSOR_POWER5
:
24899 if (is_cracked_insn (insn
))
24901 case PROCESSOR_POWER4
:
24902 if (is_microcoded_insn (insn
))
24905 if (!rs6000_sched_groups
)
24908 type
= get_attr_type (insn
);
24915 case TYPE_DELAYED_CR
:
24916 case TYPE_CR_LOGICAL
:
24930 case PROCESSOR_POWER6
:
24931 type
= get_attr_type (insn
);
24935 case TYPE_INSERT_DWORD
:
24939 case TYPE_VAR_SHIFT_ROTATE
:
24946 case TYPE_INSERT_WORD
:
24947 case TYPE_DELAYED_COMPARE
:
24948 case TYPE_IMUL_COMPARE
:
24949 case TYPE_LMUL_COMPARE
:
24950 case TYPE_FPCOMPARE
:
24961 case TYPE_LOAD_EXT_UX
:
24963 case TYPE_STORE_UX
:
24964 case TYPE_FPLOAD_U
:
24965 case TYPE_FPLOAD_UX
:
24966 case TYPE_FPSTORE_U
:
24967 case TYPE_FPSTORE_UX
:
24973 case PROCESSOR_POWER7
:
24974 case PROCESSOR_POWER8
: /* FIXME */
24975 type
= get_attr_type (insn
);
24979 case TYPE_CR_LOGICAL
:
24986 case TYPE_DELAYED_COMPARE
:
24987 case TYPE_VAR_DELAYED_COMPARE
:
24993 case TYPE_LOAD_EXT
:
24994 case TYPE_LOAD_EXT_U
:
24995 case TYPE_LOAD_EXT_UX
:
24997 case TYPE_STORE_UX
:
24998 case TYPE_FPLOAD_U
:
24999 case TYPE_FPLOAD_UX
:
25000 case TYPE_FPSTORE_U
:
25001 case TYPE_FPSTORE_UX
:
25017 insn_must_be_last_in_group (rtx insn
)
25019 enum attr_type type
;
25023 || DEBUG_INSN_P (insn
)
25024 || GET_CODE (PATTERN (insn
)) == USE
25025 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25028 switch (rs6000_cpu
) {
25029 case PROCESSOR_POWER4
:
25030 case PROCESSOR_POWER5
:
25031 if (is_microcoded_insn (insn
))
25034 if (is_branch_slot_insn (insn
))
25038 case PROCESSOR_POWER6
:
25039 type
= get_attr_type (insn
);
25046 case TYPE_VAR_SHIFT_ROTATE
:
25053 case TYPE_DELAYED_COMPARE
:
25054 case TYPE_IMUL_COMPARE
:
25055 case TYPE_LMUL_COMPARE
:
25056 case TYPE_FPCOMPARE
:
25070 case PROCESSOR_POWER7
:
25071 case PROCESSOR_POWER8
: /* FIXME */
25072 type
= get_attr_type (insn
);
25080 case TYPE_LOAD_EXT_U
:
25081 case TYPE_LOAD_EXT_UX
:
25082 case TYPE_STORE_UX
:
25095 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
25096 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
25099 is_costly_group (rtx
*group_insns
, rtx next_insn
)
25102 int issue_rate
= rs6000_issue_rate ();
25104 for (i
= 0; i
< issue_rate
; i
++)
25106 sd_iterator_def sd_it
;
25108 rtx insn
= group_insns
[i
];
25113 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
25115 rtx next
= DEP_CON (dep
);
25117 if (next
== next_insn
25118 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
25126 /* Utility of the function redefine_groups.
25127 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
25128 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
25129 to keep it "far" (in a separate group) from GROUP_INSNS, following
25130 one of the following schemes, depending on the value of the flag
25131 -minsert_sched_nops = X:
25132 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
25133 in order to force NEXT_INSN into a separate group.
25134 (2) X < sched_finish_regroup_exact: insert exactly X nops.
25135 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
25136 insertion (has a group just ended, how many vacant issue slots remain in the
25137 last group, and how many dispatch groups were encountered so far). */
25140 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
25141 rtx next_insn
, bool *group_end
, int can_issue_more
,
25146 int issue_rate
= rs6000_issue_rate ();
25147 bool end
= *group_end
;
25150 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
25151 return can_issue_more
;
25153 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
25154 return can_issue_more
;
25156 force
= is_costly_group (group_insns
, next_insn
);
25158 return can_issue_more
;
25160 if (sched_verbose
> 6)
25161 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
25162 *group_count
,can_issue_more
);
25164 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
25167 can_issue_more
= 0;
25169 /* Since only a branch can be issued in the last issue_slot, it is
25170 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
25171 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
25172 in this case the last nop will start a new group and the branch
25173 will be forced to the new group. */
25174 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
25177 /* Power6 and Power7 have special group ending nop. */
25178 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
25179 || rs6000_cpu_attr
== CPU_POWER8
)
25181 nop
= gen_group_ending_nop ();
25182 emit_insn_before (nop
, next_insn
);
25183 can_issue_more
= 0;
25186 while (can_issue_more
> 0)
25189 emit_insn_before (nop
, next_insn
);
25197 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
25199 int n_nops
= rs6000_sched_insert_nops
;
25201 /* Nops can't be issued from the branch slot, so the effective
25202 issue_rate for nops is 'issue_rate - 1'. */
25203 if (can_issue_more
== 0)
25204 can_issue_more
= issue_rate
;
25206 if (can_issue_more
== 0)
25208 can_issue_more
= issue_rate
- 1;
25211 for (i
= 0; i
< issue_rate
; i
++)
25213 group_insns
[i
] = 0;
25220 emit_insn_before (nop
, next_insn
);
25221 if (can_issue_more
== issue_rate
- 1) /* new group begins */
25224 if (can_issue_more
== 0)
25226 can_issue_more
= issue_rate
- 1;
25229 for (i
= 0; i
< issue_rate
; i
++)
25231 group_insns
[i
] = 0;
25237 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
25240 /* Is next_insn going to start a new group? */
25243 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
25244 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
25245 || (can_issue_more
< issue_rate
&&
25246 insn_terminates_group_p (next_insn
, previous_group
)));
25247 if (*group_end
&& end
)
25250 if (sched_verbose
> 6)
25251 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
25252 *group_count
, can_issue_more
);
25253 return can_issue_more
;
25256 return can_issue_more
;
25259 /* This function tries to synch the dispatch groups that the compiler "sees"
25260 with the dispatch groups that the processor dispatcher is expected to
25261 form in practice. It tries to achieve this synchronization by forcing the
25262 estimated processor grouping on the compiler (as opposed to the function
25263 'pad_goups' which tries to force the scheduler's grouping on the processor).
25265 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
25266 examines the (estimated) dispatch groups that will be formed by the processor
25267 dispatcher. It marks these group boundaries to reflect the estimated
25268 processor grouping, overriding the grouping that the scheduler had marked.
25269 Depending on the value of the flag '-minsert-sched-nops' this function can
25270 force certain insns into separate groups or force a certain distance between
25271 them by inserting nops, for example, if there exists a "costly dependence"
25274 The function estimates the group boundaries that the processor will form as
25275 follows: It keeps track of how many vacant issue slots are available after
25276 each insn. A subsequent insn will start a new group if one of the following
25278 - no more vacant issue slots remain in the current dispatch group.
25279 - only the last issue slot, which is the branch slot, is vacant, but the next
25280 insn is not a branch.
25281 - only the last 2 or less issue slots, including the branch slot, are vacant,
25282 which means that a cracked insn (which occupies two issue slots) can't be
25283 issued in this group.
25284 - less than 'issue_rate' slots are vacant, and the next insn always needs to
25285 start a new group. */
25288 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
25290 rtx insn
, next_insn
;
25292 int can_issue_more
;
25295 int group_count
= 0;
25299 issue_rate
= rs6000_issue_rate ();
25300 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
25301 for (i
= 0; i
< issue_rate
; i
++)
25303 group_insns
[i
] = 0;
25305 can_issue_more
= issue_rate
;
25307 insn
= get_next_active_insn (prev_head_insn
, tail
);
25310 while (insn
!= NULL_RTX
)
25312 slot
= (issue_rate
- can_issue_more
);
25313 group_insns
[slot
] = insn
;
25315 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
25316 if (insn_terminates_group_p (insn
, current_group
))
25317 can_issue_more
= 0;
25319 next_insn
= get_next_active_insn (insn
, tail
);
25320 if (next_insn
== NULL_RTX
)
25321 return group_count
+ 1;
25323 /* Is next_insn going to start a new group? */
25325 = (can_issue_more
== 0
25326 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
25327 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
25328 || (can_issue_more
< issue_rate
&&
25329 insn_terminates_group_p (next_insn
, previous_group
)));
25331 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
25332 next_insn
, &group_end
, can_issue_more
,
25338 can_issue_more
= 0;
25339 for (i
= 0; i
< issue_rate
; i
++)
25341 group_insns
[i
] = 0;
25345 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
25346 PUT_MODE (next_insn
, VOIDmode
);
25347 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
25348 PUT_MODE (next_insn
, TImode
);
25351 if (can_issue_more
== 0)
25352 can_issue_more
= issue_rate
;
25355 return group_count
;
25358 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
25359 dispatch group boundaries that the scheduler had marked. Pad with nops
25360 any dispatch groups which have vacant issue slots, in order to force the
25361 scheduler's grouping on the processor dispatcher. The function
25362 returns the number of dispatch groups found. */
25365 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
25367 rtx insn
, next_insn
;
25370 int can_issue_more
;
25372 int group_count
= 0;
25374 /* Initialize issue_rate. */
25375 issue_rate
= rs6000_issue_rate ();
25376 can_issue_more
= issue_rate
;
25378 insn
= get_next_active_insn (prev_head_insn
, tail
);
25379 next_insn
= get_next_active_insn (insn
, tail
);
25381 while (insn
!= NULL_RTX
)
25384 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
25386 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
25388 if (next_insn
== NULL_RTX
)
25393 /* If the scheduler had marked group termination at this location
25394 (between insn and next_insn), and neither insn nor next_insn will
25395 force group termination, pad the group with nops to force group
25398 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
25399 && !insn_terminates_group_p (insn
, current_group
)
25400 && !insn_terminates_group_p (next_insn
, previous_group
))
25402 if (!is_branch_slot_insn (next_insn
))
25405 while (can_issue_more
)
25408 emit_insn_before (nop
, next_insn
);
25413 can_issue_more
= issue_rate
;
25418 next_insn
= get_next_active_insn (insn
, tail
);
25421 return group_count
;
25424 /* We're beginning a new block. Initialize data structures as necessary. */
25427 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
25428 int sched_verbose ATTRIBUTE_UNUSED
,
25429 int max_ready ATTRIBUTE_UNUSED
)
25431 last_scheduled_insn
= NULL_RTX
;
25432 load_store_pendulum
= 0;
25435 /* The following function is called at the end of scheduling BB.
25436 After reload, it inserts nops at insn group bundling. */
25439 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
25444 fprintf (dump
, "=== Finishing schedule.\n");
25446 if (reload_completed
&& rs6000_sched_groups
)
25448 /* Do not run sched_finish hook when selective scheduling enabled. */
25449 if (sel_sched_p ())
25452 if (rs6000_sched_insert_nops
== sched_finish_none
)
25455 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
25456 n_groups
= pad_groups (dump
, sched_verbose
,
25457 current_sched_info
->prev_head
,
25458 current_sched_info
->next_tail
);
25460 n_groups
= redefine_groups (dump
, sched_verbose
,
25461 current_sched_info
->prev_head
,
25462 current_sched_info
->next_tail
);
25464 if (sched_verbose
>= 6)
25466 fprintf (dump
, "ngroups = %d\n", n_groups
);
25467 print_rtl (dump
, current_sched_info
->prev_head
);
25468 fprintf (dump
, "Done finish_sched\n");
25473 struct _rs6000_sched_context
25475 short cached_can_issue_more
;
25476 rtx last_scheduled_insn
;
25477 int load_store_pendulum
;
25480 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
25481 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
25483 /* Allocate store for new scheduling context. */
25485 rs6000_alloc_sched_context (void)
25487 return xmalloc (sizeof (rs6000_sched_context_def
));
25490 /* If CLEAN_P is true then initializes _SC with clean data,
25491 and from the global context otherwise. */
25493 rs6000_init_sched_context (void *_sc
, bool clean_p
)
25495 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
25499 sc
->cached_can_issue_more
= 0;
25500 sc
->last_scheduled_insn
= NULL_RTX
;
25501 sc
->load_store_pendulum
= 0;
25505 sc
->cached_can_issue_more
= cached_can_issue_more
;
25506 sc
->last_scheduled_insn
= last_scheduled_insn
;
25507 sc
->load_store_pendulum
= load_store_pendulum
;
25511 /* Sets the global scheduling context to the one pointed to by _SC. */
25513 rs6000_set_sched_context (void *_sc
)
25515 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
25517 gcc_assert (sc
!= NULL
);
25519 cached_can_issue_more
= sc
->cached_can_issue_more
;
25520 last_scheduled_insn
= sc
->last_scheduled_insn
;
25521 load_store_pendulum
= sc
->load_store_pendulum
;
25526 rs6000_free_sched_context (void *_sc
)
25528 gcc_assert (_sc
!= NULL
);
25534 /* Length in units of the trampoline for entering a nested function. */
25537 rs6000_trampoline_size (void)
25541 switch (DEFAULT_ABI
)
25544 gcc_unreachable ();
25547 ret
= (TARGET_32BIT
) ? 12 : 24;
25552 ret
= (TARGET_32BIT
) ? 40 : 48;
25559 /* Emit RTL insns to initialize the variable parts of a trampoline.
25560 FNADDR is an RTX for the address of the function's pure code.
25561 CXT is an RTX for the static chain value for the function. */
25564 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
25566 int regsize
= (TARGET_32BIT
) ? 4 : 8;
25567 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
25568 rtx ctx_reg
= force_reg (Pmode
, cxt
);
25569 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
25571 switch (DEFAULT_ABI
)
25574 gcc_unreachable ();
25576 /* Under AIX, just build the 3 word function descriptor */
25579 rtx fnmem
, fn_reg
, toc_reg
;
25581 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
25582 error ("You cannot take the address of a nested function if you use "
25583 "the -mno-pointers-to-nested-functions option.");
25585 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
25586 fn_reg
= gen_reg_rtx (Pmode
);
25587 toc_reg
= gen_reg_rtx (Pmode
);
25589 /* Macro to shorten the code expansions below. */
25590 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
25592 m_tramp
= replace_equiv_address (m_tramp
, addr
);
25594 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
25595 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
25596 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
25597 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
25598 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
25604 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
25607 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
25608 LCT_NORMAL
, VOIDmode
, 4,
25610 GEN_INT (rs6000_trampoline_size ()), SImode
,
25618 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
25619 identifier as an argument, so the front end shouldn't look it up. */
25622 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
25624 return is_attribute_p ("altivec", attr_id
);
25627 /* Handle the "altivec" attribute. The attribute may have
25628 arguments as follows:
25630 __attribute__((altivec(vector__)))
25631 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
25632 __attribute__((altivec(bool__))) (always followed by 'unsigned')
25634 and may appear more than once (e.g., 'vector bool char') in a
25635 given declaration. */
25638 rs6000_handle_altivec_attribute (tree
*node
,
25639 tree name ATTRIBUTE_UNUSED
,
25641 int flags ATTRIBUTE_UNUSED
,
25642 bool *no_add_attrs
)
25644 tree type
= *node
, result
= NULL_TREE
;
25645 enum machine_mode mode
;
25648 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
25649 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
25650 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
25653 while (POINTER_TYPE_P (type
)
25654 || TREE_CODE (type
) == FUNCTION_TYPE
25655 || TREE_CODE (type
) == METHOD_TYPE
25656 || TREE_CODE (type
) == ARRAY_TYPE
)
25657 type
= TREE_TYPE (type
);
25659 mode
= TYPE_MODE (type
);
25661 /* Check for invalid AltiVec type qualifiers. */
25662 if (type
== long_double_type_node
)
25663 error ("use of %<long double%> in AltiVec types is invalid");
25664 else if (type
== boolean_type_node
)
25665 error ("use of boolean types in AltiVec types is invalid");
25666 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
25667 error ("use of %<complex%> in AltiVec types is invalid");
25668 else if (DECIMAL_FLOAT_MODE_P (mode
))
25669 error ("use of decimal floating point types in AltiVec types is invalid");
25670 else if (!TARGET_VSX
)
25672 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
25675 error ("use of %<long%> in AltiVec types is invalid for "
25676 "64-bit code without -mvsx");
25677 else if (rs6000_warn_altivec_long
)
25678 warning (0, "use of %<long%> in AltiVec types is deprecated; "
25681 else if (type
== long_long_unsigned_type_node
25682 || type
== long_long_integer_type_node
)
25683 error ("use of %<long long%> in AltiVec types is invalid without "
25685 else if (type
== double_type_node
)
25686 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
25689 switch (altivec_type
)
25692 unsigned_p
= TYPE_UNSIGNED (type
);
25696 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
25699 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
25702 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
25705 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
25707 case SFmode
: result
= V4SF_type_node
; break;
25708 case DFmode
: result
= V2DF_type_node
; break;
25709 /* If the user says 'vector int bool', we may be handed the 'bool'
25710 attribute _before_ the 'vector' attribute, and so select the
25711 proper type in the 'b' case below. */
25712 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
25713 case V2DImode
: case V2DFmode
:
25721 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
25722 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
25723 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
25724 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
25731 case V8HImode
: result
= pixel_V8HI_type_node
;
25737 /* Propagate qualifiers attached to the element type
25738 onto the vector type. */
25739 if (result
&& result
!= type
&& TYPE_QUALS (type
))
25740 result
= build_qualified_type (result
, TYPE_QUALS (type
));
25742 *no_add_attrs
= true; /* No need to hang on to the attribute. */
25745 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
25750 /* AltiVec defines four built-in scalar types that serve as vector
25751 elements; we must teach the compiler how to mangle them. */
25753 static const char *
25754 rs6000_mangle_type (const_tree type
)
25756 type
= TYPE_MAIN_VARIANT (type
);
25758 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
25759 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
25762 if (type
== bool_char_type_node
) return "U6__boolc";
25763 if (type
== bool_short_type_node
) return "U6__bools";
25764 if (type
== pixel_type_node
) return "u7__pixel";
25765 if (type
== bool_int_type_node
) return "U6__booli";
25766 if (type
== bool_long_type_node
) return "U6__booll";
25768 /* Mangle IBM extended float long double as `g' (__float128) on
25769 powerpc*-linux where long-double-64 previously was the default. */
25770 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
25772 && TARGET_LONG_DOUBLE_128
25773 && !TARGET_IEEEQUAD
)
25776 /* For all other types, use normal C++ mangling. */
25780 /* Handle a "longcall" or "shortcall" attribute; arguments as in
25781 struct attribute_spec.handler. */
25784 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
25785 tree args ATTRIBUTE_UNUSED
,
25786 int flags ATTRIBUTE_UNUSED
,
25787 bool *no_add_attrs
)
25789 if (TREE_CODE (*node
) != FUNCTION_TYPE
25790 && TREE_CODE (*node
) != FIELD_DECL
25791 && TREE_CODE (*node
) != TYPE_DECL
)
25793 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
25795 *no_add_attrs
= true;
25801 /* Set longcall attributes on all functions declared when
25802 rs6000_default_long_calls is true. */
25804 rs6000_set_default_type_attributes (tree type
)
25806 if (rs6000_default_long_calls
25807 && (TREE_CODE (type
) == FUNCTION_TYPE
25808 || TREE_CODE (type
) == METHOD_TYPE
))
25809 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
25811 TYPE_ATTRIBUTES (type
));
25814 darwin_set_default_type_attributes (type
);
25818 /* Return a reference suitable for calling a function with the
25819 longcall attribute. */
25822 rs6000_longcall_ref (rtx call_ref
)
25824 const char *call_name
;
25827 if (GET_CODE (call_ref
) != SYMBOL_REF
)
25830 /* System V adds '.' to the internal name, so skip them. */
25831 call_name
= XSTR (call_ref
, 0);
25832 if (*call_name
== '.')
25834 while (*call_name
== '.')
25837 node
= get_identifier (call_name
);
25838 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
25841 return force_reg (Pmode
, call_ref
);
25844 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
25845 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
25848 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
25849 struct attribute_spec.handler. */
25851 rs6000_handle_struct_attribute (tree
*node
, tree name
,
25852 tree args ATTRIBUTE_UNUSED
,
25853 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
25856 if (DECL_P (*node
))
25858 if (TREE_CODE (*node
) == TYPE_DECL
)
25859 type
= &TREE_TYPE (*node
);
25864 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
25865 || TREE_CODE (*type
) == UNION_TYPE
)))
25867 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
25868 *no_add_attrs
= true;
25871 else if ((is_attribute_p ("ms_struct", name
)
25872 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
25873 || ((is_attribute_p ("gcc_struct", name
)
25874 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
25876 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
25878 *no_add_attrs
= true;
25885 rs6000_ms_bitfield_layout_p (const_tree record_type
)
25887 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
25888 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
25889 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
25892 #ifdef USING_ELFOS_H
25894 /* A get_unnamed_section callback, used for switching to toc_section. */
25897 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
25899 if (DEFAULT_ABI
== ABI_AIX
25900 && TARGET_MINIMAL_TOC
25901 && !TARGET_RELOCATABLE
)
25903 if (!toc_initialized
)
25905 toc_initialized
= 1;
25906 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
25907 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
25908 fprintf (asm_out_file
, "\t.tc ");
25909 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
25910 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
25911 fprintf (asm_out_file
, "\n");
25913 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
25914 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
25915 fprintf (asm_out_file
, " = .+32768\n");
25918 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
25920 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
25921 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
25924 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
25925 if (!toc_initialized
)
25927 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
25928 fprintf (asm_out_file
, " = .+32768\n");
25929 toc_initialized
= 1;
25934 /* Implement TARGET_ASM_INIT_SECTIONS. */
25937 rs6000_elf_asm_init_sections (void)
25940 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
25943 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
25944 SDATA2_SECTION_ASM_OP
);
25947 /* Implement TARGET_SELECT_RTX_SECTION. */
25950 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
25951 unsigned HOST_WIDE_INT align
)
25953 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
25954 return toc_section
;
25956 return default_elf_select_rtx_section (mode
, x
, align
);
25959 /* For a SYMBOL_REF, set generic flags and then perform some
25960 target-specific processing.
25962 When the AIX ABI is requested on a non-AIX system, replace the
25963 function name with the real name (with a leading .) rather than the
25964 function descriptor name. This saves a lot of overriding code to
25965 read the prefixes. */
25967 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
25969 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
25971 default_encode_section_info (decl
, rtl
, first
);
25974 && TREE_CODE (decl
) == FUNCTION_DECL
25976 && DEFAULT_ABI
== ABI_AIX
)
25978 rtx sym_ref
= XEXP (rtl
, 0);
25979 size_t len
= strlen (XSTR (sym_ref
, 0));
25980 char *str
= XALLOCAVEC (char, len
+ 2);
25982 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
25983 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
25988 compare_section_name (const char *section
, const char *templ
)
25992 len
= strlen (templ
);
25993 return (strncmp (section
, templ
, len
) == 0
25994 && (section
[len
] == 0 || section
[len
] == '.'));
25998 rs6000_elf_in_small_data_p (const_tree decl
)
26000 if (rs6000_sdata
== SDATA_NONE
)
26003 /* We want to merge strings, so we never consider them small data. */
26004 if (TREE_CODE (decl
) == STRING_CST
)
26007 /* Functions are never in the small data area. */
26008 if (TREE_CODE (decl
) == FUNCTION_DECL
)
26011 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
26013 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
26014 if (compare_section_name (section
, ".sdata")
26015 || compare_section_name (section
, ".sdata2")
26016 || compare_section_name (section
, ".gnu.linkonce.s")
26017 || compare_section_name (section
, ".sbss")
26018 || compare_section_name (section
, ".sbss2")
26019 || compare_section_name (section
, ".gnu.linkonce.sb")
26020 || strcmp (section
, ".PPC.EMB.sdata0") == 0
26021 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
26026 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
26029 && size
<= g_switch_value
26030 /* If it's not public, and we're not going to reference it there,
26031 there's no need to put it in the small data section. */
26032 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
26039 #endif /* USING_ELFOS_H */
26041 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
26044 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
26046 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
26049 /* Do not place thread-local symbols refs in the object blocks. */
26052 rs6000_use_blocks_for_decl_p (const_tree decl
)
26054 return !DECL_THREAD_LOCAL_P (decl
);
26057 /* Return a REG that occurs in ADDR with coefficient 1.
26058 ADDR can be effectively incremented by incrementing REG.
26060 r0 is special and we must not select it as an address
26061 register by this routine since our caller will try to
26062 increment the returned register via an "la" instruction. */
26065 find_addr_reg (rtx addr
)
26067 while (GET_CODE (addr
) == PLUS
)
26069 if (GET_CODE (XEXP (addr
, 0)) == REG
26070 && REGNO (XEXP (addr
, 0)) != 0)
26071 addr
= XEXP (addr
, 0);
26072 else if (GET_CODE (XEXP (addr
, 1)) == REG
26073 && REGNO (XEXP (addr
, 1)) != 0)
26074 addr
= XEXP (addr
, 1);
26075 else if (CONSTANT_P (XEXP (addr
, 0)))
26076 addr
= XEXP (addr
, 1);
26077 else if (CONSTANT_P (XEXP (addr
, 1)))
26078 addr
= XEXP (addr
, 0);
26080 gcc_unreachable ();
26082 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
26087 rs6000_fatal_bad_address (rtx op
)
26089 fatal_insn ("bad address", op
);
26094 typedef struct branch_island_d
{
26095 tree function_name
;
26101 static vec
<branch_island
, va_gc
> *branch_islands
;
26103 /* Remember to generate a branch island for far calls to the given
26107 add_compiler_branch_island (tree label_name
, tree function_name
,
26110 branch_island bi
= {function_name
, label_name
, line_number
};
26111 vec_safe_push (branch_islands
, bi
);
26114 /* Generate far-jump branch islands for everything recorded in
26115 branch_islands. Invoked immediately after the last instruction of
26116 the epilogue has been emitted; the branch islands must be appended
26117 to, and contiguous with, the function body. Mach-O stubs are
26118 generated in machopic_output_stub(). */
26121 macho_branch_islands (void)
26125 while (!vec_safe_is_empty (branch_islands
))
26127 branch_island
*bi
= &branch_islands
->last ();
26128 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
26129 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
26130 char name_buf
[512];
26131 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
26132 if (name
[0] == '*' || name
[0] == '&')
26133 strcpy (name_buf
, name
+1);
26137 strcpy (name_buf
+1, name
);
26139 strcpy (tmp_buf
, "\n");
26140 strcat (tmp_buf
, label
);
26141 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
26142 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
26143 dbxout_stabd (N_SLINE
, bi
->line_number
);
26144 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
26147 if (TARGET_LINK_STACK
)
26150 get_ppc476_thunk_name (name
);
26151 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
26152 strcat (tmp_buf
, name
);
26153 strcat (tmp_buf
, "\n");
26154 strcat (tmp_buf
, label
);
26155 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
26159 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
26160 strcat (tmp_buf
, label
);
26161 strcat (tmp_buf
, "_pic\n");
26162 strcat (tmp_buf
, label
);
26163 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
26166 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
26167 strcat (tmp_buf
, name_buf
);
26168 strcat (tmp_buf
, " - ");
26169 strcat (tmp_buf
, label
);
26170 strcat (tmp_buf
, "_pic)\n");
26172 strcat (tmp_buf
, "\tmtlr r0\n");
26174 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
26175 strcat (tmp_buf
, name_buf
);
26176 strcat (tmp_buf
, " - ");
26177 strcat (tmp_buf
, label
);
26178 strcat (tmp_buf
, "_pic)\n");
26180 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
26184 strcat (tmp_buf
, ":\nlis r12,hi16(");
26185 strcat (tmp_buf
, name_buf
);
26186 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
26187 strcat (tmp_buf
, name_buf
);
26188 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
26190 output_asm_insn (tmp_buf
, 0);
26191 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
26192 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
26193 dbxout_stabd (N_SLINE
, bi
->line_number
);
26194 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
26195 branch_islands
->pop ();
26199 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
26200 already there or not. */
26203 no_previous_def (tree function_name
)
26208 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
26209 if (function_name
== bi
->function_name
)
26214 /* GET_PREV_LABEL gets the label name from the previous definition of
26218 get_prev_label (tree function_name
)
26223 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
26224 if (function_name
== bi
->function_name
)
26225 return bi
->label_name
;
26229 /* INSN is either a function call or a millicode call. It may have an
26230 unconditional jump in its delay slot.
26232 CALL_DEST is the routine we are calling. */
26235 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
26236 int cookie_operand_number
)
26238 static char buf
[256];
26239 if (darwin_emit_branch_islands
26240 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
26241 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
26244 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
26246 if (no_previous_def (funname
))
26248 rtx label_rtx
= gen_label_rtx ();
26249 char *label_buf
, temp_buf
[256];
26250 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
26251 CODE_LABEL_NUMBER (label_rtx
));
26252 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
26253 labelname
= get_identifier (label_buf
);
26254 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
26257 labelname
= get_prev_label (funname
);
26259 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
26260 instruction will reach 'foo', otherwise link as 'bl L42'".
26261 "L42" should be a 'branch island', that will do a far jump to
26262 'foo'. Branch islands are generated in
26263 macho_branch_islands(). */
26264 sprintf (buf
, "jbsr %%z%d,%.246s",
26265 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
26268 sprintf (buf
, "bl %%z%d", dest_operand_number
);
26272 /* Generate PIC and indirect symbol stubs. */
26275 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
26277 unsigned int length
;
26278 char *symbol_name
, *lazy_ptr_name
;
26279 char *local_label_0
;
26280 static int label
= 0;
26282 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26283 symb
= (*targetm
.strip_name_encoding
) (symb
);
26286 length
= strlen (symb
);
26287 symbol_name
= XALLOCAVEC (char, length
+ 32);
26288 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
26290 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
26291 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
26294 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
26296 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
26300 fprintf (file
, "\t.align 5\n");
26302 fprintf (file
, "%s:\n", stub
);
26303 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
26306 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
26307 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
26309 fprintf (file
, "\tmflr r0\n");
26310 if (TARGET_LINK_STACK
)
26313 get_ppc476_thunk_name (name
);
26314 fprintf (file
, "\tbl %s\n", name
);
26315 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
26319 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
26320 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
26322 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
26323 lazy_ptr_name
, local_label_0
);
26324 fprintf (file
, "\tmtlr r0\n");
26325 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
26326 (TARGET_64BIT
? "ldu" : "lwzu"),
26327 lazy_ptr_name
, local_label_0
);
26328 fprintf (file
, "\tmtctr r12\n");
26329 fprintf (file
, "\tbctr\n");
26333 fprintf (file
, "\t.align 4\n");
26335 fprintf (file
, "%s:\n", stub
);
26336 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
26338 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
26339 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
26340 (TARGET_64BIT
? "ldu" : "lwzu"),
26342 fprintf (file
, "\tmtctr r12\n");
26343 fprintf (file
, "\tbctr\n");
26346 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
26347 fprintf (file
, "%s:\n", lazy_ptr_name
);
26348 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
26349 fprintf (file
, "%sdyld_stub_binding_helper\n",
26350 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
26353 /* Legitimize PIC addresses. If the address is already
26354 position-independent, we return ORIG. Newly generated
26355 position-independent addresses go into a reg. This is REG if non
26356 zero, otherwise we allocate register(s) as necessary. */
26358 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
26361 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
26366 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
26367 reg
= gen_reg_rtx (Pmode
);
26369 if (GET_CODE (orig
) == CONST
)
26373 if (GET_CODE (XEXP (orig
, 0)) == PLUS
26374 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
26377 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
26379 /* Use a different reg for the intermediate value, as
26380 it will be marked UNCHANGING. */
26381 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
26382 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
26385 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
26388 if (GET_CODE (offset
) == CONST_INT
)
26390 if (SMALL_INT (offset
))
26391 return plus_constant (Pmode
, base
, INTVAL (offset
));
26392 else if (! reload_in_progress
&& ! reload_completed
)
26393 offset
= force_reg (Pmode
, offset
);
26396 rtx mem
= force_const_mem (Pmode
, orig
);
26397 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
26400 return gen_rtx_PLUS (Pmode
, base
, offset
);
26403 /* Fall back on generic machopic code. */
26404 return machopic_legitimize_pic_address (orig
, mode
, reg
);
26407 /* Output a .machine directive for the Darwin assembler, and call
26408 the generic start_file routine. */
26411 rs6000_darwin_file_start (void)
26413 static const struct
26417 HOST_WIDE_INT if_set
;
26419 { "ppc64", "ppc64", MASK_64BIT
},
26420 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
26421 { "power4", "ppc970", 0 },
26422 { "G5", "ppc970", 0 },
26423 { "7450", "ppc7450", 0 },
26424 { "7400", "ppc7400", MASK_ALTIVEC
},
26425 { "G4", "ppc7400", 0 },
26426 { "750", "ppc750", 0 },
26427 { "740", "ppc750", 0 },
26428 { "G3", "ppc750", 0 },
26429 { "604e", "ppc604e", 0 },
26430 { "604", "ppc604", 0 },
26431 { "603e", "ppc603", 0 },
26432 { "603", "ppc603", 0 },
26433 { "601", "ppc601", 0 },
26434 { NULL
, "ppc", 0 } };
26435 const char *cpu_id
= "";
26438 rs6000_file_start ();
26439 darwin_file_start ();
26441 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
26443 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
26444 cpu_id
= rs6000_default_cpu
;
26446 if (global_options_set
.x_rs6000_cpu_index
)
26447 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
26449 /* Look through the mapping array. Pick the first name that either
26450 matches the argument, has a bit set in IF_SET that is also set
26451 in the target flags, or has a NULL name. */
26454 while (mapping
[i
].arg
!= NULL
26455 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
26456 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
26459 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
26462 #endif /* TARGET_MACHO */
26466 rs6000_elf_reloc_rw_mask (void)
26470 else if (DEFAULT_ABI
== ABI_AIX
)
26476 /* Record an element in the table of global constructors. SYMBOL is
26477 a SYMBOL_REF of the function to be called; PRIORITY is a number
26478 between 0 and MAX_INIT_PRIORITY.
26480 This differs from default_named_section_asm_out_constructor in
26481 that we have special handling for -mrelocatable. */
26483 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
26485 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
26487 const char *section
= ".ctors";
26490 if (priority
!= DEFAULT_INIT_PRIORITY
)
26492 sprintf (buf
, ".ctors.%.5u",
26493 /* Invert the numbering so the linker puts us in the proper
26494 order; constructors are run from right to left, and the
26495 linker sorts in increasing order. */
26496 MAX_INIT_PRIORITY
- priority
);
26500 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
26501 assemble_align (POINTER_SIZE
);
26503 if (TARGET_RELOCATABLE
)
26505 fputs ("\t.long (", asm_out_file
);
26506 output_addr_const (asm_out_file
, symbol
);
26507 fputs (")@fixup\n", asm_out_file
);
26510 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
26513 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
26515 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
26517 const char *section
= ".dtors";
26520 if (priority
!= DEFAULT_INIT_PRIORITY
)
26522 sprintf (buf
, ".dtors.%.5u",
26523 /* Invert the numbering so the linker puts us in the proper
26524 order; constructors are run from right to left, and the
26525 linker sorts in increasing order. */
26526 MAX_INIT_PRIORITY
- priority
);
26530 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
26531 assemble_align (POINTER_SIZE
);
26533 if (TARGET_RELOCATABLE
)
26535 fputs ("\t.long (", asm_out_file
);
26536 output_addr_const (asm_out_file
, symbol
);
26537 fputs (")@fixup\n", asm_out_file
);
26540 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
26544 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
26548 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
26549 ASM_OUTPUT_LABEL (file
, name
);
26550 fputs (DOUBLE_INT_ASM_OP
, file
);
26551 rs6000_output_function_entry (file
, name
);
26552 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
26555 fputs ("\t.size\t", file
);
26556 assemble_name (file
, name
);
26557 fputs (",24\n\t.type\t.", file
);
26558 assemble_name (file
, name
);
26559 fputs (",@function\n", file
);
26560 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
26562 fputs ("\t.globl\t.", file
);
26563 assemble_name (file
, name
);
26568 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
26569 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
26570 rs6000_output_function_entry (file
, name
);
26571 fputs (":\n", file
);
26575 if (TARGET_RELOCATABLE
26576 && !TARGET_SECURE_PLT
26577 && (get_pool_size () != 0 || crtl
->profile
)
26582 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
26584 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
26585 fprintf (file
, "\t.long ");
26586 assemble_name (file
, buf
);
26588 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
26589 assemble_name (file
, buf
);
26593 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
26594 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
26596 if (DEFAULT_ABI
== ABI_AIX
)
26598 const char *desc_name
, *orig_name
;
26600 orig_name
= (*targetm
.strip_name_encoding
) (name
);
26601 desc_name
= orig_name
;
26602 while (*desc_name
== '.')
26605 if (TREE_PUBLIC (decl
))
26606 fprintf (file
, "\t.globl %s\n", desc_name
);
26608 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
26609 fprintf (file
, "%s:\n", desc_name
);
26610 fprintf (file
, "\t.long %s\n", orig_name
);
26611 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
26612 if (DEFAULT_ABI
== ABI_AIX
)
26613 fputs ("\t.long 0\n", file
);
26614 fprintf (file
, "\t.previous\n");
26616 ASM_OUTPUT_LABEL (file
, name
);
26619 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
26621 rs6000_elf_file_end (void)
26623 #ifdef HAVE_AS_GNU_ATTRIBUTE
26624 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
26626 if (rs6000_passes_float
)
26627 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
26628 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
26629 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
26631 if (rs6000_passes_vector
)
26632 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
26633 (TARGET_ALTIVEC_ABI
? 2
26634 : TARGET_SPE_ABI
? 3
26636 if (rs6000_returns_struct
)
26637 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
26638 aix_struct_return
? 2 : 1);
26641 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26643 file_end_indicate_exec_stack ();
26650 rs6000_xcoff_asm_output_anchor (rtx symbol
)
26654 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
26655 SYMBOL_REF_BLOCK_OFFSET (symbol
));
26656 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
26660 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
26662 fputs (GLOBAL_ASM_OP
, stream
);
26663 RS6000_OUTPUT_BASENAME (stream
, name
);
26664 putc ('\n', stream
);
26667 /* A get_unnamed_decl callback, used for read-only sections. PTR
26668 points to the section string variable. */
26671 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
26673 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
26674 *(const char *const *) directive
,
26675 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
26678 /* Likewise for read-write sections. */
26681 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
26683 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
26684 *(const char *const *) directive
,
26685 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
26689 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
26691 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
26692 *(const char *const *) directive
,
26693 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
26696 /* A get_unnamed_section callback, used for switching to toc_section. */
26699 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
26701 if (TARGET_MINIMAL_TOC
)
26703 /* toc_section is always selected at least once from
26704 rs6000_xcoff_file_start, so this is guaranteed to
26705 always be defined once and only once in each file. */
26706 if (!toc_initialized
)
26708 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
26709 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
26710 toc_initialized
= 1;
26712 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
26713 (TARGET_32BIT
? "" : ",3"));
26716 fputs ("\t.toc\n", asm_out_file
);
26719 /* Implement TARGET_ASM_INIT_SECTIONS. */
26722 rs6000_xcoff_asm_init_sections (void)
26724 read_only_data_section
26725 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
26726 &xcoff_read_only_section_name
);
26728 private_data_section
26729 = get_unnamed_section (SECTION_WRITE
,
26730 rs6000_xcoff_output_readwrite_section_asm_op
,
26731 &xcoff_private_data_section_name
);
26734 = get_unnamed_section (SECTION_TLS
,
26735 rs6000_xcoff_output_tls_section_asm_op
,
26736 &xcoff_tls_data_section_name
);
26738 tls_private_data_section
26739 = get_unnamed_section (SECTION_TLS
,
26740 rs6000_xcoff_output_tls_section_asm_op
,
26741 &xcoff_private_data_section_name
);
26743 read_only_private_data_section
26744 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
26745 &xcoff_private_data_section_name
);
26748 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
26750 readonly_data_section
= read_only_data_section
;
26751 exception_section
= data_section
;
26755 rs6000_xcoff_reloc_rw_mask (void)
26761 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
26762 tree decl ATTRIBUTE_UNUSED
)
26765 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
26767 if (flags
& SECTION_CODE
)
26769 else if (flags
& SECTION_TLS
)
26771 else if (flags
& SECTION_WRITE
)
26776 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
26777 (flags
& SECTION_CODE
) ? "." : "",
26778 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
26782 rs6000_xcoff_select_section (tree decl
, int reloc
,
26783 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
26785 if (decl_readonly_section (decl
, reloc
))
26787 if (TREE_PUBLIC (decl
))
26788 return read_only_data_section
;
26790 return read_only_private_data_section
;
26795 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
26797 if (TREE_PUBLIC (decl
))
26798 return tls_data_section
;
26799 else if (bss_initializer_p (decl
))
26801 /* Convert to COMMON to emit in BSS. */
26802 DECL_COMMON (decl
) = 1;
26803 return tls_comm_section
;
26806 return tls_private_data_section
;
26810 if (TREE_PUBLIC (decl
))
26811 return data_section
;
26813 return private_data_section
;
26818 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
26822 /* Use select_section for private and uninitialized data. */
26823 if (!TREE_PUBLIC (decl
)
26824 || DECL_COMMON (decl
)
26825 || DECL_INITIAL (decl
) == NULL_TREE
26826 || DECL_INITIAL (decl
) == error_mark_node
26827 || (flag_zero_initialized_in_bss
26828 && initializer_zerop (DECL_INITIAL (decl
))))
26831 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
26832 name
= (*targetm
.strip_name_encoding
) (name
);
26833 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
26836 /* Select section for constant in constant pool.
26838 On RS/6000, all constants are in the private read-only data area.
26839 However, if this is being placed in the TOC it must be output as a
26843 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
26844 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
26846 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
26847 return toc_section
;
26849 return read_only_private_data_section
;
26852 /* Remove any trailing [DS] or the like from the symbol name. */
26854 static const char *
26855 rs6000_xcoff_strip_name_encoding (const char *name
)
26860 len
= strlen (name
);
26861 if (name
[len
- 1] == ']')
26862 return ggc_alloc_string (name
, len
- 4);
26867 /* Section attributes. AIX is always PIC. */
26869 static unsigned int
26870 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
26872 unsigned int align
;
26873 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
26875 /* Align to at least UNIT size. */
26876 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
26877 align
= MIN_UNITS_PER_WORD
;
26879 /* Increase alignment of large objects if not already stricter. */
26880 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
26881 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
26882 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
26884 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
26887 /* Output at beginning of assembler file.
26889 Initialize the section names for the RS/6000 at this point.
26891 Specify filename, including full path, to assembler.
26893 We want to go into the TOC section so at least one .toc will be emitted.
26894 Also, in order to output proper .bs/.es pairs, we need at least one static
26895 [RW] section emitted.
26897 Finally, declare mcount when profiling to make the assembler happy. */
26900 rs6000_xcoff_file_start (void)
26902 rs6000_gen_section_name (&xcoff_bss_section_name
,
26903 main_input_filename
, ".bss_");
26904 rs6000_gen_section_name (&xcoff_private_data_section_name
,
26905 main_input_filename
, ".rw_");
26906 rs6000_gen_section_name (&xcoff_read_only_section_name
,
26907 main_input_filename
, ".ro_");
26908 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
26909 main_input_filename
, ".tls_");
26910 rs6000_gen_section_name (&xcoff_tbss_section_name
,
26911 main_input_filename
, ".tbss_[UL]");
26913 fputs ("\t.file\t", asm_out_file
);
26914 output_quoted_string (asm_out_file
, main_input_filename
);
26915 fputc ('\n', asm_out_file
);
26916 if (write_symbols
!= NO_DEBUG
)
26917 switch_to_section (private_data_section
);
26918 switch_to_section (text_section
);
26920 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
26921 rs6000_file_start ();
26924 /* Output at end of assembler file.
26925 On the RS/6000, referencing data should automatically pull in text. */
26928 rs6000_xcoff_file_end (void)
26930 switch_to_section (text_section
);
26931 fputs ("_section_.text:\n", asm_out_file
);
26932 switch_to_section (data_section
);
26933 fputs (TARGET_32BIT
26934 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
26940 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
26945 default_encode_section_info (decl
, rtl
, first
);
26947 /* Careful not to prod global register variables. */
26950 symbol
= XEXP (rtl
, 0);
26951 if (GET_CODE (symbol
) != SYMBOL_REF
)
26954 flags
= SYMBOL_REF_FLAGS (symbol
);
26956 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
26957 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
26959 SYMBOL_REF_FLAGS (symbol
) = flags
;
26961 #endif /* HAVE_AS_TLS */
26962 #endif /* TARGET_XCOFF */
26964 /* Compute a (partial) cost for rtx X. Return true if the complete
26965 cost has been computed, and false if subexpressions should be
26966 scanned. In either case, *TOTAL contains the cost result. */
26969 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
26970 int *total
, bool speed
)
26972 enum machine_mode mode
= GET_MODE (x
);
26976 /* On the RS/6000, if it is valid in the insn, it is free. */
26978 if (((outer_code
== SET
26979 || outer_code
== PLUS
26980 || outer_code
== MINUS
)
26981 && (satisfies_constraint_I (x
)
26982 || satisfies_constraint_L (x
)))
26983 || (outer_code
== AND
26984 && (satisfies_constraint_K (x
)
26986 ? satisfies_constraint_L (x
)
26987 : satisfies_constraint_J (x
))
26988 || mask_operand (x
, mode
)
26990 && mask64_operand (x
, DImode
))))
26991 || ((outer_code
== IOR
|| outer_code
== XOR
)
26992 && (satisfies_constraint_K (x
)
26994 ? satisfies_constraint_L (x
)
26995 : satisfies_constraint_J (x
))))
26996 || outer_code
== ASHIFT
26997 || outer_code
== ASHIFTRT
26998 || outer_code
== LSHIFTRT
26999 || outer_code
== ROTATE
27000 || outer_code
== ROTATERT
27001 || outer_code
== ZERO_EXTRACT
27002 || (outer_code
== MULT
27003 && satisfies_constraint_I (x
))
27004 || ((outer_code
== DIV
|| outer_code
== UDIV
27005 || outer_code
== MOD
|| outer_code
== UMOD
)
27006 && exact_log2 (INTVAL (x
)) >= 0)
27007 || (outer_code
== COMPARE
27008 && (satisfies_constraint_I (x
)
27009 || satisfies_constraint_K (x
)))
27010 || ((outer_code
== EQ
|| outer_code
== NE
)
27011 && (satisfies_constraint_I (x
)
27012 || satisfies_constraint_K (x
)
27014 ? satisfies_constraint_L (x
)
27015 : satisfies_constraint_J (x
))))
27016 || (outer_code
== GTU
27017 && satisfies_constraint_I (x
))
27018 || (outer_code
== LTU
27019 && satisfies_constraint_P (x
)))
27024 else if ((outer_code
== PLUS
27025 && reg_or_add_cint_operand (x
, VOIDmode
))
27026 || (outer_code
== MINUS
27027 && reg_or_sub_cint_operand (x
, VOIDmode
))
27028 || ((outer_code
== SET
27029 || outer_code
== IOR
27030 || outer_code
== XOR
)
27032 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
27034 *total
= COSTS_N_INSNS (1);
27044 /* When optimizing for size, MEM should be slightly more expensive
27045 than generating address, e.g., (plus (reg) (const)).
27046 L1 cache latency is about two instructions. */
27047 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
27056 if (FLOAT_MODE_P (mode
))
27057 *total
= rs6000_cost
->fp
;
27059 *total
= COSTS_N_INSNS (1);
27063 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
27064 && satisfies_constraint_I (XEXP (x
, 1)))
27066 if (INTVAL (XEXP (x
, 1)) >= -256
27067 && INTVAL (XEXP (x
, 1)) <= 255)
27068 *total
= rs6000_cost
->mulsi_const9
;
27070 *total
= rs6000_cost
->mulsi_const
;
27072 else if (mode
== SFmode
)
27073 *total
= rs6000_cost
->fp
;
27074 else if (FLOAT_MODE_P (mode
))
27075 *total
= rs6000_cost
->dmul
;
27076 else if (mode
== DImode
)
27077 *total
= rs6000_cost
->muldi
;
27079 *total
= rs6000_cost
->mulsi
;
27083 if (mode
== SFmode
)
27084 *total
= rs6000_cost
->fp
;
27086 *total
= rs6000_cost
->dmul
;
27091 if (FLOAT_MODE_P (mode
))
27093 *total
= mode
== DFmode
? rs6000_cost
->ddiv
27094 : rs6000_cost
->sdiv
;
27101 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
27102 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
27104 if (code
== DIV
|| code
== MOD
)
27106 *total
= COSTS_N_INSNS (2);
27109 *total
= COSTS_N_INSNS (1);
27113 if (GET_MODE (XEXP (x
, 1)) == DImode
)
27114 *total
= rs6000_cost
->divdi
;
27116 *total
= rs6000_cost
->divsi
;
27118 /* Add in shift and subtract for MOD. */
27119 if (code
== MOD
|| code
== UMOD
)
27120 *total
+= COSTS_N_INSNS (2);
27125 *total
= COSTS_N_INSNS (4);
27129 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
27133 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
27137 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
27149 *total
= COSTS_N_INSNS (1);
27157 /* Handle mul_highpart. */
27158 if (outer_code
== TRUNCATE
27159 && GET_CODE (XEXP (x
, 0)) == MULT
)
27161 if (mode
== DImode
)
27162 *total
= rs6000_cost
->muldi
;
27164 *total
= rs6000_cost
->mulsi
;
27167 else if (outer_code
== AND
)
27170 *total
= COSTS_N_INSNS (1);
27175 if (GET_CODE (XEXP (x
, 0)) == MEM
)
27178 *total
= COSTS_N_INSNS (1);
27184 if (!FLOAT_MODE_P (mode
))
27186 *total
= COSTS_N_INSNS (1);
27192 case UNSIGNED_FLOAT
:
27195 case FLOAT_TRUNCATE
:
27196 *total
= rs6000_cost
->fp
;
27200 if (mode
== DFmode
)
27203 *total
= rs6000_cost
->fp
;
27207 switch (XINT (x
, 1))
27210 *total
= rs6000_cost
->fp
;
27222 *total
= COSTS_N_INSNS (1);
27225 else if (FLOAT_MODE_P (mode
)
27226 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27228 *total
= rs6000_cost
->fp
;
27236 /* Carry bit requires mode == Pmode.
27237 NEG or PLUS already counted so only add one. */
27239 && (outer_code
== NEG
|| outer_code
== PLUS
))
27241 *total
= COSTS_N_INSNS (1);
27244 if (outer_code
== SET
)
27246 if (XEXP (x
, 1) == const0_rtx
)
27248 if (TARGET_ISEL
&& !TARGET_MFCRF
)
27249 *total
= COSTS_N_INSNS (8);
27251 *total
= COSTS_N_INSNS (2);
27254 else if (mode
== Pmode
)
27256 *total
= COSTS_N_INSNS (3);
27265 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
27267 if (TARGET_ISEL
&& !TARGET_MFCRF
)
27268 *total
= COSTS_N_INSNS (8);
27270 *total
= COSTS_N_INSNS (2);
27274 if (outer_code
== COMPARE
)
27288 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
27291 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
27294 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
27297 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
27298 "opno = %d, total = %d, speed = %s, x:\n",
27299 ret
? "complete" : "scan inner",
27300 GET_RTX_NAME (code
),
27301 GET_RTX_NAME (outer_code
),
27304 speed
? "true" : "false");
27311 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
27314 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
27315 addr_space_t as
, bool speed
)
27317 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
27319 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
27320 ret
, speed
? "true" : "false");
27327 /* A C expression returning the cost of moving data from a register of class
27328 CLASS1 to one of CLASS2. */
27331 rs6000_register_move_cost (enum machine_mode mode
,
27332 reg_class_t from
, reg_class_t to
)
27336 if (TARGET_DEBUG_COST
)
27339 /* Moves from/to GENERAL_REGS. */
27340 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
27341 || reg_classes_intersect_p (from
, GENERAL_REGS
))
27343 reg_class_t rclass
= from
;
27345 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
27348 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
27349 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
27350 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
27352 /* It's more expensive to move CR_REGS than CR0_REGS because of the
27354 else if (rclass
== CR_REGS
)
27357 /* For those processors that have slow LR/CTR moves, make them more
27358 expensive than memory in order to bias spills to memory .*/
27359 else if ((rs6000_cpu
== PROCESSOR_POWER6
27360 || rs6000_cpu
== PROCESSOR_POWER7
27361 || rs6000_cpu
== PROCESSOR_POWER8
)
27362 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
27363 ret
= 6 * hard_regno_nregs
[0][mode
];
27366 /* A move will cost one instruction per GPR moved. */
27367 ret
= 2 * hard_regno_nregs
[0][mode
];
27370 /* If we have VSX, we can easily move between FPR or Altivec registers. */
27371 else if (VECTOR_MEM_VSX_P (mode
)
27372 && reg_classes_intersect_p (to
, VSX_REGS
)
27373 && reg_classes_intersect_p (from
, VSX_REGS
))
27374 ret
= 2 * hard_regno_nregs
[32][mode
];
27376 /* Moving between two similar registers is just one instruction. */
27377 else if (reg_classes_intersect_p (to
, from
))
27378 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
27380 /* Everything else has to go through GENERAL_REGS. */
27382 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
27383 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
27385 if (TARGET_DEBUG_COST
)
27387 if (dbg_cost_ctrl
== 1)
27389 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
27390 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
27391 reg_class_names
[to
]);
27398 /* A C expressions returning the cost of moving data of MODE from a register to
27402 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
27403 bool in ATTRIBUTE_UNUSED
)
27407 if (TARGET_DEBUG_COST
)
27410 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
27411 ret
= 4 * hard_regno_nregs
[0][mode
];
27412 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
27413 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
27414 ret
= 4 * hard_regno_nregs
[32][mode
];
27415 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
27416 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
27418 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
27420 if (TARGET_DEBUG_COST
)
27422 if (dbg_cost_ctrl
== 1)
27424 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
27425 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
27432 /* Returns a code for a target-specific builtin that implements
27433 reciprocal of the function, or NULL_TREE if not available. */
27436 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
27437 bool sqrt ATTRIBUTE_UNUSED
)
27439 if (optimize_insn_for_size_p ())
27445 case VSX_BUILTIN_XVSQRTDP
:
27446 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
27449 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
27451 case VSX_BUILTIN_XVSQRTSP
:
27452 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
27455 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
27464 case BUILT_IN_SQRT
:
27465 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
27468 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
27470 case BUILT_IN_SQRTF
:
27471 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
27474 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
27481 /* Load up a constant. If the mode is a vector mode, splat the value across
27482 all of the vector elements. */
27485 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
27489 if (mode
== SFmode
|| mode
== DFmode
)
27491 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
27492 reg
= force_reg (mode
, d
);
27494 else if (mode
== V4SFmode
)
27496 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
27497 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
27498 reg
= gen_reg_rtx (mode
);
27499 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
27501 else if (mode
== V2DFmode
)
27503 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
27504 rtvec v
= gen_rtvec (2, d
, d
);
27505 reg
= gen_reg_rtx (mode
);
27506 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
27509 gcc_unreachable ();
27514 /* Generate an FMA instruction. */
27517 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
27519 enum machine_mode mode
= GET_MODE (target
);
27522 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
27523 gcc_assert (dst
!= NULL
);
27526 emit_move_insn (target
, dst
);
27529 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
27532 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
27534 enum machine_mode mode
= GET_MODE (target
);
27537 /* Altivec does not support fms directly;
27538 generate in terms of fma in that case. */
27539 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
27540 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
27543 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
27544 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
27546 gcc_assert (dst
!= NULL
);
27549 emit_move_insn (target
, dst
);
27552 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
27555 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
27557 enum machine_mode mode
= GET_MODE (dst
);
27560 /* This is a tad more complicated, since the fnma_optab is for
27561 a different expression: fma(-m1, m2, a), which is the same
27562 thing except in the case of signed zeros.
27564 Fortunately we know that if FMA is supported that FNMSUB is
27565 also supported in the ISA. Just expand it directly. */
27567 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
27569 r
= gen_rtx_NEG (mode
, a
);
27570 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
27571 r
= gen_rtx_NEG (mode
, r
);
27572 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
27575 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
27576 add a reg_note saying that this was a division. Support both scalar and
27577 vector divide. Assumes no trapping math and finite arguments. */
27580 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
27582 enum machine_mode mode
= GET_MODE (dst
);
27583 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
27586 /* Low precision estimates guarantee 5 bits of accuracy. High
27587 precision estimates guarantee 14 bits of accuracy. SFmode
27588 requires 23 bits of accuracy. DFmode requires 52 bits of
27589 accuracy. Each pass at least doubles the accuracy, leading
27590 to the following. */
27591 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
27592 if (mode
== DFmode
|| mode
== V2DFmode
)
27595 enum insn_code code
= optab_handler (smul_optab
, mode
);
27596 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
27598 gcc_assert (code
!= CODE_FOR_nothing
);
27600 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
27602 /* x0 = 1./d estimate */
27603 x0
= gen_reg_rtx (mode
);
27604 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
27605 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
27608 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
27611 /* e0 = 1. - d * x0 */
27612 e0
= gen_reg_rtx (mode
);
27613 rs6000_emit_nmsub (e0
, d
, x0
, one
);
27615 /* x1 = x0 + e0 * x0 */
27616 x1
= gen_reg_rtx (mode
);
27617 rs6000_emit_madd (x1
, e0
, x0
, x0
);
27619 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
27620 ++i
, xprev
= xnext
, eprev
= enext
) {
27622 /* enext = eprev * eprev */
27623 enext
= gen_reg_rtx (mode
);
27624 emit_insn (gen_mul (enext
, eprev
, eprev
));
27626 /* xnext = xprev + enext * xprev */
27627 xnext
= gen_reg_rtx (mode
);
27628 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
27634 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
27636 /* u = n * xprev */
27637 u
= gen_reg_rtx (mode
);
27638 emit_insn (gen_mul (u
, n
, xprev
));
27640 /* v = n - (d * u) */
27641 v
= gen_reg_rtx (mode
);
27642 rs6000_emit_nmsub (v
, d
, u
, n
);
27644 /* dst = (v * xprev) + u */
27645 rs6000_emit_madd (dst
, v
, xprev
, u
);
27648 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
27651 /* Newton-Raphson approximation of single/double-precision floating point
27652 rsqrt. Assumes no trapping math and finite arguments. */
27655 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
27657 enum machine_mode mode
= GET_MODE (src
);
27658 rtx x0
= gen_reg_rtx (mode
);
27659 rtx y
= gen_reg_rtx (mode
);
27661 /* Low precision estimates guarantee 5 bits of accuracy. High
27662 precision estimates guarantee 14 bits of accuracy. SFmode
27663 requires 23 bits of accuracy. DFmode requires 52 bits of
27664 accuracy. Each pass at least doubles the accuracy, leading
27665 to the following. */
27666 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
27667 if (mode
== DFmode
|| mode
== V2DFmode
)
27670 REAL_VALUE_TYPE dconst3_2
;
27673 enum insn_code code
= optab_handler (smul_optab
, mode
);
27674 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
27676 gcc_assert (code
!= CODE_FOR_nothing
);
27678 /* Load up the constant 1.5 either as a scalar, or as a vector. */
27679 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
27680 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
27682 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
27684 /* x0 = rsqrt estimate */
27685 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
27686 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
27689 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
27690 rs6000_emit_msub (y
, src
, halfthree
, src
);
27692 for (i
= 0; i
< passes
; i
++)
27694 rtx x1
= gen_reg_rtx (mode
);
27695 rtx u
= gen_reg_rtx (mode
);
27696 rtx v
= gen_reg_rtx (mode
);
27698 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
27699 emit_insn (gen_mul (u
, x0
, x0
));
27700 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
27701 emit_insn (gen_mul (x1
, x0
, v
));
27705 emit_move_insn (dst
, x0
);
27709 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
27710 (Power7) targets. DST is the target, and SRC is the argument operand. */
27713 rs6000_emit_popcount (rtx dst
, rtx src
)
27715 enum machine_mode mode
= GET_MODE (dst
);
27718 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
27719 if (TARGET_POPCNTD
)
27721 if (mode
== SImode
)
27722 emit_insn (gen_popcntdsi2 (dst
, src
));
27724 emit_insn (gen_popcntddi2 (dst
, src
));
27728 tmp1
= gen_reg_rtx (mode
);
27730 if (mode
== SImode
)
27732 emit_insn (gen_popcntbsi2 (tmp1
, src
));
27733 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
27735 tmp2
= force_reg (SImode
, tmp2
);
27736 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
27740 emit_insn (gen_popcntbdi2 (tmp1
, src
));
27741 tmp2
= expand_mult (DImode
, tmp1
,
27742 GEN_INT ((HOST_WIDE_INT
)
27743 0x01010101 << 32 | 0x01010101),
27745 tmp2
= force_reg (DImode
, tmp2
);
27746 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
27751 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
27752 target, and SRC is the argument operand. */
27755 rs6000_emit_parity (rtx dst
, rtx src
)
27757 enum machine_mode mode
= GET_MODE (dst
);
27760 tmp
= gen_reg_rtx (mode
);
27762 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
27765 if (mode
== SImode
)
27767 emit_insn (gen_popcntbsi2 (tmp
, src
));
27768 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
27772 emit_insn (gen_popcntbdi2 (tmp
, src
));
27773 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
27778 if (mode
== SImode
)
27780 /* Is mult+shift >= shift+xor+shift+xor? */
27781 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
27783 rtx tmp1
, tmp2
, tmp3
, tmp4
;
27785 tmp1
= gen_reg_rtx (SImode
);
27786 emit_insn (gen_popcntbsi2 (tmp1
, src
));
27788 tmp2
= gen_reg_rtx (SImode
);
27789 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
27790 tmp3
= gen_reg_rtx (SImode
);
27791 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
27793 tmp4
= gen_reg_rtx (SImode
);
27794 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
27795 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
27798 rs6000_emit_popcount (tmp
, src
);
27799 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
27803 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
27804 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
27806 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
27808 tmp1
= gen_reg_rtx (DImode
);
27809 emit_insn (gen_popcntbdi2 (tmp1
, src
));
27811 tmp2
= gen_reg_rtx (DImode
);
27812 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
27813 tmp3
= gen_reg_rtx (DImode
);
27814 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
27816 tmp4
= gen_reg_rtx (DImode
);
27817 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
27818 tmp5
= gen_reg_rtx (DImode
);
27819 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
27821 tmp6
= gen_reg_rtx (DImode
);
27822 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
27823 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
27826 rs6000_emit_popcount (tmp
, src
);
27827 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
27831 /* Expand an Altivec constant permutation. Return true if we match
27832 an efficient implementation; false to fall back to VPERM. */
27835 altivec_expand_vec_perm_const (rtx operands
[4])
27837 struct altivec_perm_insn
{
27838 HOST_WIDE_INT mask
;
27839 enum insn_code impl
;
27840 unsigned char perm
[16];
27842 static const struct altivec_perm_insn patterns
[] = {
27843 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
,
27844 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
27845 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
,
27846 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
27847 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
,
27848 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
27849 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
,
27850 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
27851 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
,
27852 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
27853 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
,
27854 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
27855 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
,
27856 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
27857 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
,
27858 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
27859 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
27860 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
27861 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
27862 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
27865 unsigned int i
, j
, elt
, which
;
27866 unsigned char perm
[16];
27867 rtx target
, op0
, op1
, sel
, x
;
27870 target
= operands
[0];
27875 /* Unpack the constant selector. */
27876 for (i
= which
= 0; i
< 16; ++i
)
27878 rtx e
= XVECEXP (sel
, 0, i
);
27879 elt
= INTVAL (e
) & 31;
27880 which
|= (elt
< 16 ? 1 : 2);
27884 /* Simplify the constant selector based on operands. */
27888 gcc_unreachable ();
27892 if (!rtx_equal_p (op0
, op1
))
27897 for (i
= 0; i
< 16; ++i
)
27909 /* Look for splat patterns. */
27914 for (i
= 0; i
< 16; ++i
)
27915 if (perm
[i
] != elt
)
27919 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
27925 for (i
= 0; i
< 16; i
+= 2)
27926 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
27930 x
= gen_reg_rtx (V8HImode
);
27931 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
27932 GEN_INT (elt
/ 2)));
27933 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
27940 for (i
= 0; i
< 16; i
+= 4)
27942 || perm
[i
+ 1] != elt
+ 1
27943 || perm
[i
+ 2] != elt
+ 2
27944 || perm
[i
+ 3] != elt
+ 3)
27948 x
= gen_reg_rtx (V4SImode
);
27949 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
27950 GEN_INT (elt
/ 4)));
27951 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
27957 /* Look for merge and pack patterns. */
27958 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
27962 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
27965 elt
= patterns
[j
].perm
[0];
27966 if (perm
[0] == elt
)
27968 else if (perm
[0] == elt
+ 16)
27972 for (i
= 1; i
< 16; ++i
)
27974 elt
= patterns
[j
].perm
[i
];
27976 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
27977 else if (one_vec
&& elt
>= 16)
27979 if (perm
[i
] != elt
)
27984 enum insn_code icode
= patterns
[j
].impl
;
27985 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
27986 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
27989 x
= op0
, op0
= op1
, op1
= x
;
27990 if (imode
!= V16QImode
)
27992 op0
= gen_lowpart (imode
, op0
);
27993 op1
= gen_lowpart (imode
, op1
);
27995 if (omode
== V16QImode
)
27998 x
= gen_reg_rtx (omode
);
27999 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
28000 if (omode
!= V16QImode
)
28001 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
28009 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
28010 Return true if we match an efficient implementation. */
28013 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
28014 unsigned char perm0
, unsigned char perm1
)
28018 /* If both selectors come from the same operand, fold to single op. */
28019 if ((perm0
& 2) == (perm1
& 2))
28026 /* If both operands are equal, fold to simpler permutation. */
28027 if (rtx_equal_p (op0
, op1
))
28030 perm1
= (perm1
& 1) + 2;
28032 /* If the first selector comes from the second operand, swap. */
28033 else if (perm0
& 2)
28039 x
= op0
, op0
= op1
, op1
= x
;
28041 /* If the second selector does not come from the second operand, fail. */
28042 else if ((perm1
& 2) == 0)
28046 if (target
!= NULL
)
28048 enum machine_mode vmode
, dmode
;
28051 vmode
= GET_MODE (target
);
28052 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
28053 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
28055 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
28056 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
28057 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
28058 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
28064 rs6000_expand_vec_perm_const (rtx operands
[4])
28066 rtx target
, op0
, op1
, sel
;
28067 unsigned char perm0
, perm1
;
28069 target
= operands
[0];
28074 /* Unpack the constant selector. */
28075 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
28076 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
28078 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
28081 /* Test whether a constant permutation is supported. */
28084 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
28085 const unsigned char *sel
)
28087 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
28088 if (TARGET_ALTIVEC
)
28091 /* Check for ps_merge* or evmerge* insns. */
28092 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
28093 || (TARGET_SPE
&& vmode
== V2SImode
))
28095 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
28096 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
28097 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
28103 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
28106 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
28107 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
28109 enum machine_mode imode
;
28113 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
28115 imode
= GET_MODE_INNER (vmode
);
28116 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
28117 imode
= mode_for_vector (imode
, nelt
);
28120 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
28121 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
28123 emit_move_insn (target
, x
);
28126 /* Expand an extract even operation. */
28129 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
28131 enum machine_mode vmode
= GET_MODE (target
);
28132 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
28135 for (i
= 0; i
< nelt
; i
++)
28136 perm
[i
] = GEN_INT (i
* 2);
28138 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
28141 /* Expand a vector interleave operation. */
28144 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
28146 enum machine_mode vmode
= GET_MODE (target
);
28147 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
28150 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
28151 for (i
= 0; i
< nelt
/ 2; i
++)
28153 perm
[i
* 2] = GEN_INT (i
+ high
);
28154 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
28157 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
28160 /* Return an RTX representing where to find the function value of a
28161 function returning MODE. */
28163 rs6000_complex_function_value (enum machine_mode mode
)
28165 unsigned int regno
;
28167 enum machine_mode inner
= GET_MODE_INNER (mode
);
28168 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
28170 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28171 regno
= FP_ARG_RETURN
;
28174 regno
= GP_ARG_RETURN
;
28176 /* 32-bit is OK since it'll go in r3/r4. */
28177 if (TARGET_32BIT
&& inner_bytes
>= 4)
28178 return gen_rtx_REG (mode
, regno
);
28181 if (inner_bytes
>= 8)
28182 return gen_rtx_REG (mode
, regno
);
28184 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
28186 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
28187 GEN_INT (inner_bytes
));
28188 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
28191 /* Target hook for TARGET_FUNCTION_VALUE.
28193 On the SPE, both FPs and vectors are returned in r3.
28195 On RS/6000 an integer value is in r3 and a floating-point value is in
28196 fp1, unless -msoft-float. */
28199 rs6000_function_value (const_tree valtype
,
28200 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
28201 bool outgoing ATTRIBUTE_UNUSED
)
28203 enum machine_mode mode
;
28204 unsigned int regno
;
28206 /* Special handling for structs in darwin64. */
28208 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
28210 CUMULATIVE_ARGS valcum
;
28214 valcum
.fregno
= FP_ARG_MIN_REG
;
28215 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
28216 /* Do a trial code generation as if this were going to be passed as
28217 an argument; if any part goes in memory, we return NULL. */
28218 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
28221 /* Otherwise fall through to standard ABI rules. */
28224 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
28226 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
28227 return gen_rtx_PARALLEL (DImode
,
28229 gen_rtx_EXPR_LIST (VOIDmode
,
28230 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
28232 gen_rtx_EXPR_LIST (VOIDmode
,
28233 gen_rtx_REG (SImode
,
28234 GP_ARG_RETURN
+ 1),
28237 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
28239 return gen_rtx_PARALLEL (DCmode
,
28241 gen_rtx_EXPR_LIST (VOIDmode
,
28242 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
28244 gen_rtx_EXPR_LIST (VOIDmode
,
28245 gen_rtx_REG (SImode
,
28246 GP_ARG_RETURN
+ 1),
28248 gen_rtx_EXPR_LIST (VOIDmode
,
28249 gen_rtx_REG (SImode
,
28250 GP_ARG_RETURN
+ 2),
28252 gen_rtx_EXPR_LIST (VOIDmode
,
28253 gen_rtx_REG (SImode
,
28254 GP_ARG_RETURN
+ 3),
28258 mode
= TYPE_MODE (valtype
);
28259 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
28260 || POINTER_TYPE_P (valtype
))
28261 mode
= TARGET_32BIT
? SImode
: DImode
;
28263 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28264 /* _Decimal128 must use an even/odd register pair. */
28265 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
28266 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
28267 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
28268 regno
= FP_ARG_RETURN
;
28269 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
28270 && targetm
.calls
.split_complex_arg
)
28271 return rs6000_complex_function_value (mode
);
28272 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
28273 return register is used in both cases, and we won't see V2DImode/V2DFmode
28274 for pure altivec, combine the two cases. */
28275 else if (TREE_CODE (valtype
) == VECTOR_TYPE
28276 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
28277 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
28278 regno
= ALTIVEC_ARG_RETURN
;
28279 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
28280 && (mode
== DFmode
|| mode
== DCmode
28281 || mode
== TFmode
|| mode
== TCmode
))
28282 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
28284 regno
= GP_ARG_RETURN
;
28286 return gen_rtx_REG (mode
, regno
);
28289 /* Define how to find the value returned by a library function
28290 assuming the value has mode MODE. */
28292 rs6000_libcall_value (enum machine_mode mode
)
28294 unsigned int regno
;
28296 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
28298 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
28299 return gen_rtx_PARALLEL (DImode
,
28301 gen_rtx_EXPR_LIST (VOIDmode
,
28302 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
28304 gen_rtx_EXPR_LIST (VOIDmode
,
28305 gen_rtx_REG (SImode
,
28306 GP_ARG_RETURN
+ 1),
28310 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28311 /* _Decimal128 must use an even/odd register pair. */
28312 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
28313 else if (SCALAR_FLOAT_MODE_P (mode
)
28314 && TARGET_HARD_FLOAT
&& TARGET_FPRS
28315 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
28316 regno
= FP_ARG_RETURN
;
28317 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
28318 return register is used in both cases, and we won't see V2DImode/V2DFmode
28319 for pure altivec, combine the two cases. */
28320 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
28321 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
28322 regno
= ALTIVEC_ARG_RETURN
;
28323 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
28324 return rs6000_complex_function_value (mode
);
28325 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
28326 && (mode
== DFmode
|| mode
== DCmode
28327 || mode
== TFmode
|| mode
== TCmode
))
28328 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
28330 regno
= GP_ARG_RETURN
;
28332 return gen_rtx_REG (mode
, regno
);
28336 /* Given FROM and TO register numbers, say whether this elimination is allowed.
28337 Frame pointer elimination is automatically handled.
28339 For the RS/6000, if frame pointer elimination is being done, we would like
28340 to convert ap into fp, not sp.
28342 We need r30 if -mminimal-toc was specified, and there are constant pool
28346 rs6000_can_eliminate (const int from
, const int to
)
28348 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
28349 ? ! frame_pointer_needed
28350 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
28351 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
28355 /* Define the offset between two registers, FROM to be eliminated and its
28356 replacement TO, at the start of a routine. */
28358 rs6000_initial_elimination_offset (int from
, int to
)
28360 rs6000_stack_t
*info
= rs6000_stack_info ();
28361 HOST_WIDE_INT offset
;
28363 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
28364 offset
= info
->push_p
? 0 : -info
->total_size
;
28365 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
28367 offset
= info
->push_p
? 0 : -info
->total_size
;
28368 if (FRAME_GROWS_DOWNWARD
)
28369 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
28371 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
28372 offset
= FRAME_GROWS_DOWNWARD
28373 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
28375 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
28376 offset
= info
->total_size
;
28377 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
28378 offset
= info
->push_p
? info
->total_size
: 0;
28379 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
28382 gcc_unreachable ();
28388 rs6000_dwarf_register_span (rtx reg
)
28392 unsigned regno
= REGNO (reg
);
28393 enum machine_mode mode
= GET_MODE (reg
);
28397 && (SPE_VECTOR_MODE (GET_MODE (reg
))
28398 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
28399 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
28404 regno
= REGNO (reg
);
28406 /* The duality of the SPE register size wreaks all kinds of havoc.
28407 This is a way of distinguishing r0 in 32-bits from r0 in
28409 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
28410 gcc_assert (words
<= 4);
28411 for (i
= 0; i
< words
; i
++, regno
++)
28413 if (BYTES_BIG_ENDIAN
)
28415 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
28416 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
28420 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
28421 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
28425 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
28428 /* Fill in sizes for SPE register high parts in table used by unwinder. */
28431 rs6000_init_dwarf_reg_sizes_extra (tree address
)
28436 enum machine_mode mode
= TYPE_MODE (char_type_node
);
28437 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
28438 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
28439 rtx value
= gen_int_mode (4, mode
);
28441 for (i
= 1201; i
< 1232; i
++)
28443 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
28444 HOST_WIDE_INT offset
28445 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
28447 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
28452 /* Map internal gcc register numbers to DWARF2 register numbers. */
28455 rs6000_dbx_register_number (unsigned int regno
)
28457 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
28459 if (regno
== LR_REGNO
)
28461 if (regno
== CTR_REGNO
)
28463 if (CR_REGNO_P (regno
))
28464 return regno
- CR0_REGNO
+ 86;
28465 if (regno
== CA_REGNO
)
28466 return 101; /* XER */
28467 if (ALTIVEC_REGNO_P (regno
))
28468 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
28469 if (regno
== VRSAVE_REGNO
)
28471 if (regno
== VSCR_REGNO
)
28473 if (regno
== SPE_ACC_REGNO
)
28475 if (regno
== SPEFSCR_REGNO
)
28477 /* SPE high reg number. We get these values of regno from
28478 rs6000_dwarf_register_span. */
28479 gcc_assert (regno
>= 1200 && regno
< 1232);
28483 /* target hook eh_return_filter_mode */
28484 static enum machine_mode
28485 rs6000_eh_return_filter_mode (void)
28487 return TARGET_32BIT
? SImode
: word_mode
;
28490 /* Target hook for scalar_mode_supported_p. */
28492 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
28494 if (DECIMAL_FLOAT_MODE_P (mode
))
28495 return default_decimal_float_supported_p ();
28497 return default_scalar_mode_supported_p (mode
);
28500 /* Target hook for vector_mode_supported_p. */
28502 rs6000_vector_mode_supported_p (enum machine_mode mode
)
28505 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
28508 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
28511 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
28518 /* Target hook for invalid_arg_for_unprototyped_fn. */
28519 static const char *
28520 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
28522 return (!rs6000_darwin64_abi
28524 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
28525 && (funcdecl
== NULL_TREE
28526 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
28527 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
28528 ? N_("AltiVec argument passed to unprototyped function")
28532 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
28533 setup by using __stack_chk_fail_local hidden function instead of
28534 calling __stack_chk_fail directly. Otherwise it is better to call
28535 __stack_chk_fail directly. */
28537 static tree ATTRIBUTE_UNUSED
28538 rs6000_stack_protect_fail (void)
28540 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
28541 ? default_hidden_stack_protect_fail ()
28542 : default_external_stack_protect_fail ();
28546 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
28547 int num_operands ATTRIBUTE_UNUSED
)
28549 if (rs6000_warn_cell_microcode
)
28552 int insn_code_number
= recog_memoized (insn
);
28553 location_t location
= INSN_LOCATION (insn
);
28555 /* Punt on insns we cannot recognize. */
28556 if (insn_code_number
< 0)
28559 temp
= get_insn_template (insn_code_number
, insn
);
28561 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
28562 warning_at (location
, OPT_mwarn_cell_microcode
,
28563 "emitting microcode insn %s\t[%s] #%d",
28564 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
28565 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
28566 warning_at (location
, OPT_mwarn_cell_microcode
,
28567 "emitting conditional microcode insn %s\t[%s] #%d",
28568 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
28572 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
28575 static unsigned HOST_WIDE_INT
28576 rs6000_asan_shadow_offset (void)
28578 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
28582 /* Mask options that we want to support inside of attribute((target)) and
28583 #pragma GCC target operations. Note, we do not include things like
28584 64/32-bit, endianess, hard/soft floating point, etc. that would have
28585 different calling sequences. */
28587 struct rs6000_opt_mask
{
28588 const char *name
; /* option name */
28589 HOST_WIDE_INT mask
; /* mask to set */
28590 bool invert
; /* invert sense of mask */
28591 bool valid_target
; /* option is a target option */
28594 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
28596 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
28597 { "cmpb", OPTION_MASK_CMPB
, false, true },
28598 { "crypto", OPTION_MASK_CRYPTO
, false, true },
28599 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
28600 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
28601 { "fprnd", OPTION_MASK_FPRND
, false, true },
28602 { "hard-dfp", OPTION_MASK_DFP
, false, true },
28603 { "isel", OPTION_MASK_ISEL
, false, true },
28604 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
28605 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
28606 { "mulhw", OPTION_MASK_MULHW
, false, true },
28607 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
28608 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
28609 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
28610 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
28611 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
28612 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
28613 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
28614 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
28615 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
28616 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
28617 { "string", OPTION_MASK_STRING
, false, true },
28618 { "update", OPTION_MASK_NO_UPDATE
, true , true },
28619 { "vsx", OPTION_MASK_VSX
, false, true },
28620 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
28621 #ifdef OPTION_MASK_64BIT
28623 { "aix64", OPTION_MASK_64BIT
, false, false },
28624 { "aix32", OPTION_MASK_64BIT
, true, false },
28626 { "64", OPTION_MASK_64BIT
, false, false },
28627 { "32", OPTION_MASK_64BIT
, true, false },
28630 #ifdef OPTION_MASK_EABI
28631 { "eabi", OPTION_MASK_EABI
, false, false },
28633 #ifdef OPTION_MASK_LITTLE_ENDIAN
28634 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
28635 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
28637 #ifdef OPTION_MASK_RELOCATABLE
28638 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
28640 #ifdef OPTION_MASK_STRICT_ALIGN
28641 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
28643 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
28644 { "string", OPTION_MASK_STRING
, false, false },
28647 /* Builtin mask mapping for printing the flags. */
28648 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
28650 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
28651 { "vsx", RS6000_BTM_VSX
, false, false },
28652 { "spe", RS6000_BTM_SPE
, false, false },
28653 { "paired", RS6000_BTM_PAIRED
, false, false },
28654 { "fre", RS6000_BTM_FRE
, false, false },
28655 { "fres", RS6000_BTM_FRES
, false, false },
28656 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
28657 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
28658 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
28659 { "cell", RS6000_BTM_CELL
, false, false },
28660 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
28661 { "crypto", RS6000_BTM_CRYPTO
, false, false },
28664 /* Option variables that we want to support inside attribute((target)) and
28665 #pragma GCC target operations. */
28667 struct rs6000_opt_var
{
28668 const char *name
; /* option name */
28669 size_t global_offset
; /* offset of the option in global_options. */
28670 size_t target_offset
; /* offset of the option in target optiosn. */
28673 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
28676 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
28677 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
28678 { "avoid-indexed-addresses",
28679 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
28680 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
28682 offsetof (struct gcc_options
, x_rs6000_paired_float
),
28683 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
28685 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
28686 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
28689 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
28690 parsing. Return true if there were no errors. */
28693 rs6000_inner_target_options (tree args
, bool attr_p
)
28697 if (args
== NULL_TREE
)
28700 else if (TREE_CODE (args
) == STRING_CST
)
28702 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
28705 while ((q
= strtok (p
, ",")) != NULL
)
28707 bool error_p
= false;
28708 bool not_valid_p
= false;
28709 const char *cpu_opt
= NULL
;
28712 if (strncmp (q
, "cpu=", 4) == 0)
28714 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
28715 if (cpu_index
>= 0)
28716 rs6000_cpu_index
= cpu_index
;
28723 else if (strncmp (q
, "tune=", 5) == 0)
28725 int tune_index
= rs6000_cpu_name_lookup (q
+5);
28726 if (tune_index
>= 0)
28727 rs6000_tune_index
= tune_index
;
28737 bool invert
= false;
28741 if (strncmp (r
, "no-", 3) == 0)
28747 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
28748 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
28750 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
28752 if (!rs6000_opt_masks
[i
].valid_target
)
28753 not_valid_p
= true;
28757 rs6000_isa_flags_explicit
|= mask
;
28759 /* VSX needs altivec, so -mvsx automagically sets
28761 if (mask
== OPTION_MASK_VSX
&& !invert
)
28762 mask
|= OPTION_MASK_ALTIVEC
;
28764 if (rs6000_opt_masks
[i
].invert
)
28768 rs6000_isa_flags
&= ~mask
;
28770 rs6000_isa_flags
|= mask
;
28775 if (error_p
&& !not_valid_p
)
28777 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
28778 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
28780 size_t j
= rs6000_opt_vars
[i
].global_offset
;
28781 *((int *) ((char *)&global_options
+ j
)) = !invert
;
28790 const char *eprefix
, *esuffix
;
28795 eprefix
= "__attribute__((__target__(";
28800 eprefix
= "#pragma GCC target ";
28805 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
28807 else if (not_valid_p
)
28808 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
28810 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
28815 else if (TREE_CODE (args
) == TREE_LIST
)
28819 tree value
= TREE_VALUE (args
);
28822 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
28826 args
= TREE_CHAIN (args
);
28828 while (args
!= NULL_TREE
);
28832 gcc_unreachable ();
28837 /* Print out the target options as a list for -mdebug=target. */
28840 rs6000_debug_target_options (tree args
, const char *prefix
)
28842 if (args
== NULL_TREE
)
28843 fprintf (stderr
, "%s<NULL>", prefix
);
28845 else if (TREE_CODE (args
) == STRING_CST
)
28847 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
28850 while ((q
= strtok (p
, ",")) != NULL
)
28853 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
28858 else if (TREE_CODE (args
) == TREE_LIST
)
28862 tree value
= TREE_VALUE (args
);
28865 rs6000_debug_target_options (value
, prefix
);
28868 args
= TREE_CHAIN (args
);
28870 while (args
!= NULL_TREE
);
28874 gcc_unreachable ();
28880 /* Hook to validate attribute((target("..."))). */
28883 rs6000_valid_attribute_p (tree fndecl
,
28884 tree
ARG_UNUSED (name
),
28888 struct cl_target_option cur_target
;
28890 tree old_optimize
= build_optimization_node ();
28891 tree new_target
, new_optimize
;
28892 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
28894 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
28896 if (TARGET_DEBUG_TARGET
)
28898 tree tname
= DECL_NAME (fndecl
);
28899 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
28901 fprintf (stderr
, "function: %.*s\n",
28902 (int) IDENTIFIER_LENGTH (tname
),
28903 IDENTIFIER_POINTER (tname
));
28905 fprintf (stderr
, "function: unknown\n");
28907 fprintf (stderr
, "args:");
28908 rs6000_debug_target_options (args
, " ");
28909 fprintf (stderr
, "\n");
28912 fprintf (stderr
, "flags: 0x%x\n", flags
);
28914 fprintf (stderr
, "--------------------\n");
28917 old_optimize
= build_optimization_node ();
28918 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
28920 /* If the function changed the optimization levels as well as setting target
28921 options, start with the optimizations specified. */
28922 if (func_optimize
&& func_optimize
!= old_optimize
)
28923 cl_optimization_restore (&global_options
,
28924 TREE_OPTIMIZATION (func_optimize
));
28926 /* The target attributes may also change some optimization flags, so update
28927 the optimization options if necessary. */
28928 cl_target_option_save (&cur_target
, &global_options
);
28929 rs6000_cpu_index
= rs6000_tune_index
= -1;
28930 ret
= rs6000_inner_target_options (args
, true);
28932 /* Set up any additional state. */
28935 ret
= rs6000_option_override_internal (false);
28936 new_target
= build_target_option_node ();
28941 new_optimize
= build_optimization_node ();
28948 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
28950 if (old_optimize
!= new_optimize
)
28951 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
28954 cl_target_option_restore (&global_options
, &cur_target
);
28956 if (old_optimize
!= new_optimize
)
28957 cl_optimization_restore (&global_options
,
28958 TREE_OPTIMIZATION (old_optimize
));
28964 /* Hook to validate the current #pragma GCC target and set the state, and
28965 update the macros based on what was changed. If ARGS is NULL, then
28966 POP_TARGET is used to reset the options. */
28969 rs6000_pragma_target_parse (tree args
, tree pop_target
)
28971 tree prev_tree
= build_target_option_node ();
28973 struct cl_target_option
*prev_opt
, *cur_opt
;
28974 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
28975 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
28977 if (TARGET_DEBUG_TARGET
)
28979 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
28980 fprintf (stderr
, "args:");
28981 rs6000_debug_target_options (args
, " ");
28982 fprintf (stderr
, "\n");
28986 fprintf (stderr
, "pop_target:\n");
28987 debug_tree (pop_target
);
28990 fprintf (stderr
, "pop_target: <NULL>\n");
28992 fprintf (stderr
, "--------------------\n");
28997 cur_tree
= ((pop_target
)
28999 : target_option_default_node
);
29000 cl_target_option_restore (&global_options
,
29001 TREE_TARGET_OPTION (cur_tree
));
29005 rs6000_cpu_index
= rs6000_tune_index
= -1;
29006 if (!rs6000_inner_target_options (args
, false)
29007 || !rs6000_option_override_internal (false)
29008 || (cur_tree
= build_target_option_node ()) == NULL_TREE
)
29010 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
29011 fprintf (stderr
, "invalid pragma\n");
29017 target_option_current_node
= cur_tree
;
29019 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
29020 change the macros that are defined. */
29021 if (rs6000_target_modify_macros_ptr
)
29023 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
29024 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
29025 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
29027 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
29028 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
29029 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
29031 diff_bumask
= (prev_bumask
^ cur_bumask
);
29032 diff_flags
= (prev_flags
^ cur_flags
);
29034 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
29036 /* Delete old macros. */
29037 rs6000_target_modify_macros_ptr (false,
29038 prev_flags
& diff_flags
,
29039 prev_bumask
& diff_bumask
);
29041 /* Define new macros. */
29042 rs6000_target_modify_macros_ptr (true,
29043 cur_flags
& diff_flags
,
29044 cur_bumask
& diff_bumask
);
29052 /* Remember the last target of rs6000_set_current_function. */
29053 static GTY(()) tree rs6000_previous_fndecl
;
29055 /* Establish appropriate back-end context for processing the function
29056 FNDECL. The argument might be NULL to indicate processing at top
29057 level, outside of any function scope. */
29059 rs6000_set_current_function (tree fndecl
)
29061 tree old_tree
= (rs6000_previous_fndecl
29062 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
29065 tree new_tree
= (fndecl
29066 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
29069 if (TARGET_DEBUG_TARGET
)
29071 bool print_final
= false;
29072 fprintf (stderr
, "\n==================== rs6000_set_current_function");
29075 fprintf (stderr
, ", fndecl %s (%p)",
29076 (DECL_NAME (fndecl
)
29077 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
29078 : "<unknown>"), (void *)fndecl
);
29080 if (rs6000_previous_fndecl
)
29081 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
29083 fprintf (stderr
, "\n");
29086 fprintf (stderr
, "\nnew fndecl target specific options:\n");
29087 debug_tree (new_tree
);
29088 print_final
= true;
29093 fprintf (stderr
, "\nold fndecl target specific options:\n");
29094 debug_tree (old_tree
);
29095 print_final
= true;
29099 fprintf (stderr
, "--------------------\n");
29102 /* Only change the context if the function changes. This hook is called
29103 several times in the course of compiling a function, and we don't want to
29104 slow things down too much or call target_reinit when it isn't safe. */
29105 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
29107 rs6000_previous_fndecl
= fndecl
;
29108 if (old_tree
== new_tree
)
29113 cl_target_option_restore (&global_options
,
29114 TREE_TARGET_OPTION (new_tree
));
29120 struct cl_target_option
*def
29121 = TREE_TARGET_OPTION (target_option_current_node
);
29123 cl_target_option_restore (&global_options
, def
);
29130 /* Save the current options */
29133 rs6000_function_specific_save (struct cl_target_option
*ptr
)
29135 ptr
->x_rs6000_isa_flags
= rs6000_isa_flags
;
29136 ptr
->x_rs6000_isa_flags_explicit
= rs6000_isa_flags_explicit
;
29139 /* Restore the current options */
29142 rs6000_function_specific_restore (struct cl_target_option
*ptr
)
29144 rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
29145 rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
29146 (void) rs6000_option_override_internal (false);
29149 /* Print the current options */
29152 rs6000_function_specific_print (FILE *file
, int indent
,
29153 struct cl_target_option
*ptr
)
29155 rs6000_print_isa_options (file
, indent
, "Isa options set",
29156 ptr
->x_rs6000_isa_flags
);
29158 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
29159 ptr
->x_rs6000_isa_flags_explicit
);
29162 /* Helper function to print the current isa or misc options on a line. */
29165 rs6000_print_options_internal (FILE *file
,
29167 const char *string
,
29168 HOST_WIDE_INT flags
,
29169 const char *prefix
,
29170 const struct rs6000_opt_mask
*opts
,
29171 size_t num_elements
)
29174 size_t start_column
= 0;
29176 size_t max_column
= 76;
29177 const char *comma
= "";
29178 const char *nl
= "\n";
29181 start_column
+= fprintf (file
, "%*s", indent
, "");
29185 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
29189 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
29191 /* Print the various mask options. */
29192 cur_column
= start_column
;
29193 for (i
= 0; i
< num_elements
; i
++)
29195 if ((flags
& opts
[i
].mask
) != 0)
29197 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
29198 size_t len
= (strlen (comma
)
29201 + strlen (rs6000_opt_masks
[i
].name
));
29204 if (cur_column
> max_column
)
29206 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
29207 cur_column
= start_column
+ len
;
29212 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
29213 rs6000_opt_masks
[i
].name
);
29214 flags
&= ~ opts
[i
].mask
;
29222 /* Helper function to print the current isa options on a line. */
29225 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
29226 HOST_WIDE_INT flags
)
29228 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
29229 &rs6000_opt_masks
[0],
29230 ARRAY_SIZE (rs6000_opt_masks
));
29234 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
29235 HOST_WIDE_INT flags
)
29237 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
29238 &rs6000_builtin_mask_names
[0],
29239 ARRAY_SIZE (rs6000_builtin_mask_names
));
29243 /* Hook to determine if one function can safely inline another. */
29246 rs6000_can_inline_p (tree caller
, tree callee
)
29249 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
29250 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
29252 /* If callee has no option attributes, then it is ok to inline. */
29256 /* If caller has no option attributes, but callee does then it is not ok to
29258 else if (!caller_tree
)
29263 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
29264 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
29266 /* Callee's options should a subset of the caller's, i.e. a vsx function
29267 can inline an altivec function but a non-vsx function can't inline a
29269 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
29270 == callee_opts
->x_rs6000_isa_flags
)
29274 if (TARGET_DEBUG_TARGET
)
29275 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
29276 (DECL_NAME (caller
)
29277 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
29279 (DECL_NAME (callee
)
29280 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
29282 (ret
? "can" : "cannot"));
29287 /* Allocate a stack temp and fixup the address so it meets the particular
29288 memory requirements (either offetable or REG+REG addressing). */
29291 rs6000_allocate_stack_temp (enum machine_mode mode
,
29292 bool offsettable_p
,
29295 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
29296 rtx addr
= XEXP (stack
, 0);
29297 int strict_p
= (reload_in_progress
|| reload_completed
);
29299 if (!legitimate_indirect_address_p (addr
, strict_p
))
29302 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
29303 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
29305 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
29306 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
29312 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
29313 to such a form to deal with memory reference instructions like STFIWX that
29314 only take reg+reg addressing. */
29317 rs6000_address_for_fpconvert (rtx x
)
29319 int strict_p
= (reload_in_progress
|| reload_completed
);
29322 gcc_assert (MEM_P (x
));
29323 addr
= XEXP (x
, 0);
29324 if (! legitimate_indirect_address_p (addr
, strict_p
)
29325 && ! legitimate_indexed_address_p (addr
, strict_p
))
29327 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
29329 rtx reg
= XEXP (addr
, 0);
29330 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
29331 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
29332 gcc_assert (REG_P (reg
));
29333 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
29336 else if (GET_CODE (addr
) == PRE_MODIFY
)
29338 rtx reg
= XEXP (addr
, 0);
29339 rtx expr
= XEXP (addr
, 1);
29340 gcc_assert (REG_P (reg
));
29341 gcc_assert (GET_CODE (expr
) == PLUS
);
29342 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
29346 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
29352 /* Given a memory reference, if it is not in the form for altivec memory
29353 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
29354 convert to the altivec format. */
29357 rs6000_address_for_altivec (rtx x
)
29359 gcc_assert (MEM_P (x
));
29360 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
29362 rtx addr
= XEXP (x
, 0);
29363 int strict_p
= (reload_in_progress
|| reload_completed
);
29365 if (!legitimate_indexed_address_p (addr
, strict_p
)
29366 && !legitimate_indirect_address_p (addr
, strict_p
))
29367 addr
= copy_to_mode_reg (Pmode
, addr
);
29369 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
29370 x
= change_address (x
, GET_MODE (x
), addr
);
29376 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
29378 On the RS/6000, all integer constants are acceptable, most won't be valid
29379 for particular insns, though. Only easy FP constants are acceptable. */
29382 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
29384 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
29387 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
29388 || GET_MODE (x
) == VOIDmode
29389 || (TARGET_POWERPC64
&& mode
== DImode
)
29390 || easy_fp_constant (x
, mode
)
29391 || easy_vector_constant (x
, mode
));
29395 /* A function pointer under AIX is a pointer to a data area whose first word
29396 contains the actual address of the function, whose second word contains a
29397 pointer to its TOC, and whose third word contains a value to place in the
29398 static chain register (r11). Note that if we load the static chain, our
29399 "trampoline" need not have any executable code. */
29402 rs6000_call_indirect_aix (rtx value
, rtx func_desc
, rtx flag
)
29408 rtx stack_toc_offset
;
29410 rtx func_toc_offset
;
29412 rtx func_sc_offset
;
29415 rtx (*call_func
) (rtx
, rtx
, rtx
, rtx
);
29416 rtx (*call_value_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
29418 stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29419 toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
29421 /* Load up address of the actual function. */
29422 func_desc
= force_reg (Pmode
, func_desc
);
29423 func_addr
= gen_reg_rtx (Pmode
);
29424 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
29429 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_32BIT
);
29430 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_32BIT
);
29431 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_32BIT
);
29432 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
29434 call_func
= gen_call_indirect_aix32bit
;
29435 call_value_func
= gen_call_value_indirect_aix32bit
;
29439 call_func
= gen_call_indirect_aix32bit_nor11
;
29440 call_value_func
= gen_call_value_indirect_aix32bit_nor11
;
29445 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_64BIT
);
29446 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_64BIT
);
29447 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_64BIT
);
29448 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
29450 call_func
= gen_call_indirect_aix64bit
;
29451 call_value_func
= gen_call_value_indirect_aix64bit
;
29455 call_func
= gen_call_indirect_aix64bit_nor11
;
29456 call_value_func
= gen_call_value_indirect_aix64bit_nor11
;
29460 /* Reserved spot to store the TOC. */
29461 stack_toc_mem
= gen_frame_mem (Pmode
,
29462 gen_rtx_PLUS (Pmode
,
29464 stack_toc_offset
));
29467 gcc_assert (cfun
->machine
);
29469 /* Can we optimize saving the TOC in the prologue or do we need to do it at
29471 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
29472 cfun
->machine
->save_toc_in_prologue
= true;
29476 MEM_VOLATILE_P (stack_toc_mem
) = 1;
29477 emit_move_insn (stack_toc_mem
, toc_reg
);
29480 /* Calculate the address to load the TOC of the called function. We don't
29481 actually load this until the split after reload. */
29482 func_toc_mem
= gen_rtx_MEM (Pmode
,
29483 gen_rtx_PLUS (Pmode
,
29487 /* If we have a static chain, load it up. */
29488 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
29490 func_sc_mem
= gen_rtx_MEM (Pmode
,
29491 gen_rtx_PLUS (Pmode
,
29495 sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
29496 emit_move_insn (sc_reg
, func_sc_mem
);
29499 /* Create the call. */
29501 insn
= call_value_func (value
, func_addr
, flag
, func_toc_mem
,
29504 insn
= call_func (func_addr
, flag
, func_toc_mem
, stack_toc_mem
);
29506 emit_call_insn (insn
);
29509 /* Return whether we need to always update the saved TOC pointer when we update
29510 the stack pointer. */
29513 rs6000_save_toc_in_prologue_p (void)
29515 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
29518 #ifdef HAVE_GAS_HIDDEN
29519 # define USE_HIDDEN_LINKONCE 1
29521 # define USE_HIDDEN_LINKONCE 0
29524 /* Fills in the label name that should be used for a 476 link stack thunk. */
29527 get_ppc476_thunk_name (char name
[32])
29529 gcc_assert (TARGET_LINK_STACK
);
29531 if (USE_HIDDEN_LINKONCE
)
29532 sprintf (name
, "__ppc476.get_thunk");
29534 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
29537 /* This function emits the simple thunk routine that is used to preserve
29538 the link stack on the 476 cpu. */
29540 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
29542 rs6000_code_end (void)
29547 if (!TARGET_LINK_STACK
)
29550 get_ppc476_thunk_name (name
);
29552 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
29553 build_function_type_list (void_type_node
, NULL_TREE
));
29554 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
29555 NULL_TREE
, void_type_node
);
29556 TREE_PUBLIC (decl
) = 1;
29557 TREE_STATIC (decl
) = 1;
29560 if (USE_HIDDEN_LINKONCE
)
29562 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
29563 targetm
.asm_out
.unique_section (decl
, 0);
29564 switch_to_section (get_named_section (decl
, NULL
, 0));
29565 DECL_WEAK (decl
) = 1;
29566 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
29567 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
29568 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
29569 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
29574 switch_to_section (text_section
);
29575 ASM_OUTPUT_LABEL (asm_out_file
, name
);
29578 DECL_INITIAL (decl
) = make_node (BLOCK
);
29579 current_function_decl
= decl
;
29580 init_function_start (decl
);
29581 first_function_block_is_cold
= false;
29582 /* Make sure unwind info is emitted for the thunk if needed. */
29583 final_start_function (emit_barrier (), asm_out_file
, 1);
29585 fputs ("\tblr\n", asm_out_file
);
29587 final_end_function ();
29588 init_insn_lengths ();
29589 free_after_compilation (cfun
);
29591 current_function_decl
= NULL
;
29594 /* Add r30 to hard reg set if the prologue sets it up and it is not
29595 pic_offset_table_rtx. */
29598 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
29600 if (!TARGET_SINGLE_PIC_BASE
29602 && TARGET_MINIMAL_TOC
29603 && get_pool_size () != 0)
29604 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
29607 struct gcc_target targetm
= TARGET_INITIALIZER
;
29609 #include "gt-rs6000.h"