gcc/config/rs6000/rs6000.c

   1 /* Subroutines used for code generation on IBM RS/6000.
   2    Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
   4    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 2, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  21    MA 02111-1307, USA.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "tm.h"
  27 #include "rtl.h"
  28 #include "regs.h"
  29 #include "hard-reg-set.h"
  30 #include "real.h"
  31 #include "insn-config.h"
  32 #include "conditions.h"
  33 #include "insn-attr.h"
  34 #include "flags.h"
  35 #include "recog.h"
  36 #include "obstack.h"
  37 #include "tree.h"
  38 #include "expr.h"
  39 #include "optabs.h"
  40 #include "except.h"
  41 #include "function.h"
  42 #include "output.h"
  43 #include "basic-block.h"
  44 #include "integrate.h"
  45 #include "toplev.h"
  46 #include "ggc.h"
  47 #include "hashtab.h"
  48 #include "tm_p.h"
  49 #include "target.h"
  50 #include "target-def.h"
  51 #include "langhooks.h"
  52 #include "reload.h"
  53 #include "cfglayout.h"
  54 #include "sched-int.h"
  55 #if TARGET_XCOFF
  56 #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
  57 #endif
  58
  59 #ifndef TARGET_NO_PROTOTYPE
  60 #define TARGET_NO_PROTOTYPE 0
  61 #endif
  62
  63 #define EASY_VECTOR_15(n, x, y) ((n) >= -16 && (n) <= 15 \
  64                                  && easy_vector_same (x, y))
  65
  66 #define EASY_VECTOR_15_ADD_SELF(n, x, y) ((n) >= 0x10 && (n) <= 0x1e \
  67                                           && !((n) & 1)              \
  68                                           && easy_vector_same (x, y))
  69
  70 #define min(A,B)        ((A) < (B) ? (A) : (B))
  71 #define max(A,B)        ((A) > (B) ? (A) : (B))
  72
  73 /* Structure used to define the rs6000 stack */
  74 typedef struct rs6000_stack {
  75   int first_gp_reg_save;        /* first callee saved GP register used */
  76   int first_fp_reg_save;        /* first callee saved FP register used */
  77   int first_altivec_reg_save;   /* first callee saved AltiVec register used */
  78   int lr_save_p;                /* true if the link reg needs to be saved */
  79   int cr_save_p;                /* true if the CR reg needs to be saved */
  80   unsigned int vrsave_mask;     /* mask of vec registers to save */
  81   int toc_save_p;               /* true if the TOC needs to be saved */
  82   int push_p;                   /* true if we need to allocate stack space */
  83   int calls_p;                  /* true if the function makes any calls */
  84   enum rs6000_abi abi;          /* which ABI to use */
  85   int gp_save_offset;           /* offset to save GP regs from initial SP */
  86   int fp_save_offset;           /* offset to save FP regs from initial SP */
  87   int altivec_save_offset;      /* offset to save AltiVec regs from initial SP */
  88   int lr_save_offset;           /* offset to save LR from initial SP */
  89   int cr_save_offset;           /* offset to save CR from initial SP */
  90   int vrsave_save_offset;       /* offset to save VRSAVE from initial SP */
  91   int spe_gp_save_offset;       /* offset to save spe 64-bit gprs  */
  92   int toc_save_offset;          /* offset to save the TOC pointer */
  93   int varargs_save_offset;      /* offset to save the varargs registers */
  94   int ehrd_offset;              /* offset to EH return data */
  95   int reg_size;                 /* register size (4 or 8) */
  96   int varargs_size;             /* size to hold V.4 args passed in regs */
  97   HOST_WIDE_INT vars_size;      /* variable save area size */
  98   int parm_size;                /* outgoing parameter size */
  99   int save_size;                /* save area size */
 100   int fixed_size;               /* fixed size of stack frame */
 101   int gp_size;                  /* size of saved GP registers */
 102   int fp_size;                  /* size of saved FP registers */
 103   int altivec_size;             /* size of saved AltiVec registers */
 104   int cr_size;                  /* size to hold CR if not in save_size */
 105   int lr_size;                  /* size to hold LR if not in save_size */
 106   int vrsave_size;              /* size to hold VRSAVE if not in save_size */
 107   int altivec_padding_size;     /* size of altivec alignment padding if
 108                                    not in save_size */
 109   int spe_gp_size;              /* size of 64-bit GPR save size for SPE */
 110   int spe_padding_size;
 111   int toc_size;                 /* size to hold TOC if not in save_size */
 112   HOST_WIDE_INT total_size;     /* total bytes allocated for stack */
 113   int spe_64bit_regs_used;
 114 } rs6000_stack_t;
 115
 116 /* Target cpu type */
 117
 118 enum processor_type rs6000_cpu;
 119 struct rs6000_cpu_select rs6000_select[3] =
 120 {
 121   /* switch             name,                   tune    arch */
 122   { (const char *)0,    "--with-cpu=",          1,      1 },
 123   { (const char *)0,    "-mcpu=",               1,      1 },
 124   { (const char *)0,    "-mtune=",              1,      0 },
 125 };
 126
 127 /* Support adjust_priority scheduler hook
 128    and -mprioritize-restricted-insns= option.  */
 129 const char *rs6000_sched_restricted_insns_priority_str;
 130 int rs6000_sched_restricted_insns_priority;
 131
 132 /* Support for -msched-costly-dep option.  */
 133 const char *rs6000_sched_costly_dep_str;
 134 enum rs6000_dependence_cost rs6000_sched_costly_dep;
 135
 136 /* Support for -minsert-sched-nops option.  */
 137 const char *rs6000_sched_insert_nops_str;
 138 enum rs6000_nop_insertion rs6000_sched_insert_nops;
 139
 140 /* Size of long double */
 141 const char *rs6000_long_double_size_string;
 142 int rs6000_long_double_type_size;
 143
 144 /* Whether -mabi=altivec has appeared */
 145 int rs6000_altivec_abi;
 146
 147 /* Whether VRSAVE instructions should be generated.  */
 148 int rs6000_altivec_vrsave;
 149
 150 /* String from -mvrsave= option.  */
 151 const char *rs6000_altivec_vrsave_string;
 152
 153 /* Nonzero if we want SPE ABI extensions.  */
 154 int rs6000_spe_abi;
 155
 156 /* Whether isel instructions should be generated.  */
 157 int rs6000_isel;
 158
 159 /* Whether SPE simd instructions should be generated.  */
 160 int rs6000_spe;
 161
 162 /* Nonzero if floating point operations are done in the GPRs.  */
 163 int rs6000_float_gprs = 0;
 164
 165 /* String from -mfloat-gprs=.  */
 166 const char *rs6000_float_gprs_string;
 167
 168 /* String from -misel=.  */
 169 const char *rs6000_isel_string;
 170
 171 /* String from -mspe=.  */
 172 const char *rs6000_spe_string;
 173
 174 /* Set to nonzero once AIX common-mode calls have been defined.  */
 175 static GTY(()) int common_mode_defined;
 176
 177 /* Save information from a "cmpxx" operation until the branch or scc is
 178    emitted.  */
 179 rtx rs6000_compare_op0, rs6000_compare_op1;
 180 int rs6000_compare_fp_p;
 181
 182 /* Label number of label created for -mrelocatable, to call to so we can
 183    get the address of the GOT section */
 184 int rs6000_pic_labelno;
 185
 186 #ifdef USING_ELFOS_H
 187 /* Which abi to adhere to */
 188 const char *rs6000_abi_name;
 189
 190 /* Semantics of the small data area */
 191 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
 192
 193 /* Which small data model to use */
 194 const char *rs6000_sdata_name = (char *)0;
 195
 196 /* Counter for labels which are to be placed in .fixup.  */
 197 int fixuplabelno = 0;
 198 #endif
 199
 200 /* Bit size of immediate TLS offsets and string from which it is decoded.  */
 201 int rs6000_tls_size = 32;
 202 const char *rs6000_tls_size_string;
 203
 204 /* ABI enumeration available for subtarget to use.  */
 205 enum rs6000_abi rs6000_current_abi;
 206
 207 /* ABI string from -mabi= option.  */
 208 const char *rs6000_abi_string;
 209
 210 /* Debug flags */
 211 const char *rs6000_debug_name;
 212 int rs6000_debug_stack;         /* debug stack applications */
 213 int rs6000_debug_arg;           /* debug argument handling */
 214
 215 /* Opaque types.  */
 216 static GTY(()) tree opaque_V2SI_type_node;
 217 static GTY(()) tree opaque_V2SF_type_node;
 218 static GTY(()) tree opaque_p_V2SI_type_node;
 219
 220 const char *rs6000_traceback_name;
 221 static enum {
 222   traceback_default = 0,
 223   traceback_none,
 224   traceback_part,
 225   traceback_full
 226 } rs6000_traceback;
 227
 228 /* Flag to say the TOC is initialized */
 229 int toc_initialized;
 230 char toc_label_name[10];
 231
 232 /* Alias set for saves and restores from the rs6000 stack.  */
 233 static int rs6000_sr_alias_set;
 234
 235 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
 236    The only place that looks at this is rs6000_set_default_type_attributes;
 237    everywhere else should rely on the presence or absence of a longcall
 238    attribute on the function declaration.  */
 239 int rs6000_default_long_calls;
 240 const char *rs6000_longcall_switch;
 241
 242 /* Control alignment for fields within structures.  */
 243 /* String from -malign-XXXXX.  */
 244 const char *rs6000_alignment_string;
 245 int rs6000_alignment_flags;
 246
 247 struct builtin_description
 248 {
 249   /* mask is not const because we're going to alter it below.  This
 250      nonsense will go away when we rewrite the -march infrastructure
 251      to give us more target flag bits.  */
 252   unsigned int mask;
 253   const enum insn_code icode;
 254   const char *const name;
 255   const enum rs6000_builtins code;
 256 };
 257
 258 static bool rs6000_function_ok_for_sibcall (tree, tree);
 259 static int num_insns_constant_wide (HOST_WIDE_INT);
 260 static void validate_condition_mode (enum rtx_code, enum machine_mode);
 261 static rtx rs6000_generate_compare (enum rtx_code);
 262 static void rs6000_maybe_dead (rtx);
 263 static void rs6000_emit_stack_tie (void);
 264 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
 265 static rtx spe_synthesize_frame_save (rtx);
 266 static bool spe_func_has_64bit_regs_p (void);
 267 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
 268                              int, HOST_WIDE_INT);
 269 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
 270 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
 271 static unsigned rs6000_hash_constant (rtx);
 272 static unsigned toc_hash_function (const void *);
 273 static int toc_hash_eq (const void *, const void *);
 274 static int constant_pool_expr_1 (rtx, int *, int *);
 275 static bool constant_pool_expr_p (rtx);
 276 static bool toc_relative_expr_p (rtx);
 277 static bool legitimate_small_data_p (enum machine_mode, rtx);
 278 static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
 279 static bool legitimate_indexed_address_p (rtx, int);
 280 static bool legitimate_indirect_address_p (rtx, int);
 281 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
 282 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
 283 static struct machine_function * rs6000_init_machine_status (void);
 284 static bool rs6000_assemble_integer (rtx, unsigned int, int);
 285 #ifdef HAVE_GAS_HIDDEN
 286 static void rs6000_assemble_visibility (tree, int);
 287 #endif
 288 static int rs6000_ra_ever_killed (void);
 289 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
 290 extern const struct attribute_spec rs6000_attribute_table[];
 291 static void rs6000_set_default_type_attributes (tree);
 292 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
 293 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
 294 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
 295                                     tree);
 296 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 297 static bool rs6000_return_in_memory (tree, tree);
 298 static void rs6000_file_start (void);
 299 #if TARGET_ELF
 300 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
 301 static void rs6000_elf_asm_out_constructor (rtx, int);
 302 static void rs6000_elf_asm_out_destructor (rtx, int);
 303 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
 304 static void rs6000_elf_unique_section (tree, int);
 305 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
 306                                            unsigned HOST_WIDE_INT);
 307 static void rs6000_elf_encode_section_info (tree, rtx, int)
 308      ATTRIBUTE_UNUSED;
 309 static bool rs6000_elf_in_small_data_p (tree);
 310 #endif
 311 #if TARGET_XCOFF
 312 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
 313 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
 314 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
 315 static void rs6000_xcoff_unique_section (tree, int);
 316 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
 317                                              unsigned HOST_WIDE_INT);
 318 static const char * rs6000_xcoff_strip_name_encoding (const char *);
 319 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
 320 static void rs6000_xcoff_file_start (void);
 321 static void rs6000_xcoff_file_end (void);
 322 #endif
 323 #if TARGET_MACHO
 324 static bool rs6000_binds_local_p (tree);
 325 #endif
 326 static int rs6000_use_dfa_pipeline_interface (void);
 327 static int rs6000_variable_issue (FILE *, int, rtx, int);
 328 static bool rs6000_rtx_costs (rtx, int, int, int *);
 329 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
 330 static bool is_microcoded_insn (rtx);
 331 static int is_dispatch_slot_restricted (rtx);
 332 static bool is_cracked_insn (rtx);
 333 static bool is_branch_slot_insn (rtx);
 334 static int rs6000_adjust_priority (rtx, int);
 335 static int rs6000_issue_rate (void);
 336 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
 337 static rtx get_next_active_insn (rtx, rtx);
 338 static bool insn_terminates_group_p (rtx , enum group_termination);
 339 static bool is_costly_group (rtx *, rtx);
 340 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
 341 static int redefine_groups (FILE *, int, rtx, rtx);
 342 static int pad_groups (FILE *, int, rtx, rtx);
 343 static void rs6000_sched_finish (FILE *, int);
 344 static int rs6000_use_sched_lookahead (void);
 345
 346 static void rs6000_init_builtins (void);
 347 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
 348 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
 349 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
 350 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
 351 static void altivec_init_builtins (void);
 352 static void rs6000_common_init_builtins (void);
 353 static void rs6000_init_libfuncs (void);
 354
 355 static void enable_mask_for_builtins (struct builtin_description *, int,
 356                                       enum rs6000_builtins,
 357                                       enum rs6000_builtins);
 358 static void spe_init_builtins (void);
 359 static rtx spe_expand_builtin (tree, rtx, bool *);
 360 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
 361 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
 362 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
 363 static rs6000_stack_t *rs6000_stack_info (void);
 364 static void debug_stack_info (rs6000_stack_t *);
 365
 366 static rtx altivec_expand_builtin (tree, rtx, bool *);
 367 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
 368 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
 369 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
 370 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
 371 static rtx altivec_expand_predicate_builtin (enum insn_code,
 372                                             const char *, tree, rtx);
 373 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
 374 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
 375 static void rs6000_parse_abi_options (void);
 376 static void rs6000_parse_alignment_option (void);
 377 static void rs6000_parse_tls_size_option (void);
 378 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
 379 static int first_altivec_reg_to_save (void);
 380 static unsigned int compute_vrsave_mask (void);
 381 static void is_altivec_return_reg (rtx, void *);
 382 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
 383 int easy_vector_constant (rtx, enum machine_mode);
 384 static int easy_vector_same (rtx, enum machine_mode);
 385 static bool is_ev64_opaque_type (tree);
 386 static rtx rs6000_dwarf_register_span (rtx);
 387 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
 388 static rtx rs6000_tls_get_addr (void);
 389 static rtx rs6000_got_sym (void);
 390 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
 391 static const char *rs6000_get_some_local_dynamic_name (void);
 392 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
 393 static rtx rs6000_complex_function_value (enum machine_mode);
 394 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
 395                                     enum machine_mode, tree);
 396 static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *,
 397                                       enum machine_mode, tree, int);
 398 static void rs6000_move_block_from_reg(int regno, rtx x, int nregs);
 399 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
 400                                     enum machine_mode, tree,
 401                                     int *, int);
 402 #if TARGET_MACHO
 403 static void macho_branch_islands (void);
 404 static void add_compiler_branch_island (tree, tree, int);
 405 static int no_previous_def (tree function_name);
 406 static tree get_prev_label (tree function_name);
 407 #endif
 408
 409 static tree rs6000_build_builtin_va_list (void);
 410
 411 /* Hash table stuff for keeping track of TOC entries.  */
 412
 413 struct toc_hash_struct GTY(())
 414 {
 415   /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
 416      ASM_OUTPUT_SPECIAL_POOL_ENTRY_P.  */
 417   rtx key;
 418   enum machine_mode key_mode;
 419   int labelno;
 420 };
 421
 422 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
 423 \f
 424 /* Default register names.  */
 425 char rs6000_reg_names[][8] =
 426 {
 427       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 428       "8",  "9", "10", "11", "12", "13", "14", "15",
 429      "16", "17", "18", "19", "20", "21", "22", "23",
 430      "24", "25", "26", "27", "28", "29", "30", "31",
 431       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 432       "8",  "9", "10", "11", "12", "13", "14", "15",
 433      "16", "17", "18", "19", "20", "21", "22", "23",
 434      "24", "25", "26", "27", "28", "29", "30", "31",
 435      "mq", "lr", "ctr","ap",
 436       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 437       "xer",
 438       /* AltiVec registers.  */
 439       "0",  "1",  "2",  "3",  "4",  "5",  "6", "7",
 440       "8",  "9",  "10", "11", "12", "13", "14", "15",
 441       "16", "17", "18", "19", "20", "21", "22", "23",
 442       "24", "25", "26", "27", "28", "29", "30", "31",
 443       "vrsave", "vscr",
 444       /* SPE registers.  */
 445       "spe_acc", "spefscr"
 446 };
 447
 448 #ifdef TARGET_REGNAMES
 449 static const char alt_reg_names[][8] =
 450 {
 451    "%r0",   "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
 452    "%r8",   "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
 453   "%r16",  "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
 454   "%r24",  "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
 455    "%f0",   "%f1",  "%f2",  "%f3",  "%f4",  "%f5",  "%f6",  "%f7",
 456    "%f8",   "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
 457   "%f16",  "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
 458   "%f24",  "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
 459     "mq",    "lr",  "ctr",   "ap",
 460   "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
 461    "xer",
 462   /* AltiVec registers.  */
 463    "%v0",  "%v1",  "%v2",  "%v3",  "%v4",  "%v5",  "%v6", "%v7",
 464    "%v8",  "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
 465   "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
 466   "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
 467   "vrsave", "vscr",
 468   /* SPE registers.  */
 469   "spe_acc", "spefscr"
 470 };
 471 #endif
 472 \f
 473 #ifndef MASK_STRICT_ALIGN
 474 #define MASK_STRICT_ALIGN 0
 475 #endif
 476 #ifndef TARGET_PROFILE_KERNEL
 477 #define TARGET_PROFILE_KERNEL 0
 478 #endif
 479
 480 /* The VRSAVE bitmask puts bit %v0 as the most significant bit.  */
 481 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
 482
 483 /* Return 1 for a symbol ref for a thread-local storage symbol.  */
 484 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
 485   (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
 486 \f
 487 /* Initialize the GCC target structure.  */
 488 #undef TARGET_ATTRIBUTE_TABLE
 489 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
 490 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
 491 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
 492
 493 #undef TARGET_ASM_ALIGNED_DI_OP
 494 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
 495
 496 /* Default unaligned ops are only provided for ELF.  Find the ops needed
 497    for non-ELF systems.  */
 498 #ifndef OBJECT_FORMAT_ELF
 499 #if TARGET_XCOFF
 500 /* For XCOFF.  rs6000_assemble_integer will handle unaligned DIs on
 501    64-bit targets.  */
 502 #undef TARGET_ASM_UNALIGNED_HI_OP
 503 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
 504 #undef TARGET_ASM_UNALIGNED_SI_OP
 505 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
 506 #undef TARGET_ASM_UNALIGNED_DI_OP
 507 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
 508 #else
 509 /* For Darwin.  */
 510 #undef TARGET_ASM_UNALIGNED_HI_OP
 511 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
 512 #undef TARGET_ASM_UNALIGNED_SI_OP
 513 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
 514 #endif
 515 #endif
 516
 517 /* This hook deals with fixups for relocatable code and DI-mode objects
 518    in 64-bit code.  */
 519 #undef TARGET_ASM_INTEGER
 520 #define TARGET_ASM_INTEGER rs6000_assemble_integer
 521
 522 #ifdef HAVE_GAS_HIDDEN
 523 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
 524 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
 525 #endif
 526
 527 #undef TARGET_HAVE_TLS
 528 #define TARGET_HAVE_TLS HAVE_AS_TLS
 529
 530 #undef TARGET_CANNOT_FORCE_CONST_MEM
 531 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
 532
 533 #undef TARGET_ASM_FUNCTION_PROLOGUE
 534 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
 535 #undef TARGET_ASM_FUNCTION_EPILOGUE
 536 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
 537
 538 #undef  TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
 539 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
 540 #undef  TARGET_SCHED_VARIABLE_ISSUE
 541 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
 542
 543 #undef TARGET_SCHED_ISSUE_RATE
 544 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
 545 #undef TARGET_SCHED_ADJUST_COST
 546 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
 547 #undef TARGET_SCHED_ADJUST_PRIORITY
 548 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
 549 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
 550 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
 551 #undef TARGET_SCHED_FINISH
 552 #define TARGET_SCHED_FINISH rs6000_sched_finish
 553
 554 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
 555 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
 556
 557 #undef TARGET_INIT_BUILTINS
 558 #define TARGET_INIT_BUILTINS rs6000_init_builtins
 559
 560 #undef TARGET_EXPAND_BUILTIN
 561 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
 562
 563 #undef TARGET_INIT_LIBFUNCS
 564 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
 565
 566 #if TARGET_MACHO
 567 #undef TARGET_BINDS_LOCAL_P
 568 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
 569 #endif
 570
 571 #undef TARGET_ASM_OUTPUT_MI_THUNK
 572 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
 573
 574 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
 575 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
 576
 577 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 578 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
 579
 580 #undef TARGET_RTX_COSTS
 581 #define TARGET_RTX_COSTS rs6000_rtx_costs
 582 #undef TARGET_ADDRESS_COST
 583 #define TARGET_ADDRESS_COST hook_int_rtx_0
 584
 585 #undef TARGET_VECTOR_OPAQUE_P
 586 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
 587
 588 #undef TARGET_DWARF_REGISTER_SPAN
 589 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
 590
 591 /* On rs6000, function arguments are promoted, as are function return
 592    values.  */
 593 #undef TARGET_PROMOTE_FUNCTION_ARGS
 594 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
 595 #undef TARGET_PROMOTE_FUNCTION_RETURN
 596 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
 597
 598 /* Structure return values are passed as an extra parameter.  */
 599 #undef TARGET_STRUCT_VALUE_RTX
 600 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
 601
 602 #undef TARGET_RETURN_IN_MEMORY
 603 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
 604
 605 #undef TARGET_SETUP_INCOMING_VARARGS
 606 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
 607
 608 /* Always strict argument naming on rs6000.  */
 609 #undef TARGET_STRICT_ARGUMENT_NAMING
 610 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
 611 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
 612 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
 613
 614 #undef TARGET_BUILD_BUILTIN_VA_LIST
 615 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
 616
 617 struct gcc_target targetm = TARGET_INITIALIZER;
 618 \f
 619 /* Override command line options.  Mostly we process the processor
 620    type and sometimes adjust other TARGET_ options.  */
 621
 622 void
 623 rs6000_override_options (const char *default_cpu)
 624 {
 625   size_t i, j;
 626   struct rs6000_cpu_select *ptr;
 627   int set_masks;
 628
 629   /* Simplifications for entries below.  */
 630
 631   enum {
 632     POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
 633     POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
 634   };
 635
 636   /* This table occasionally claims that a processor does not support
 637      a particular feature even though it does, but the feature is slower
 638      than the alternative.  Thus, it shouldn't be relied on as a
 639      complete description of the processor's support.
 640
 641      Please keep this list in order, and don't forget to update the
 642      documentation in invoke.texi when adding a new processor or
 643      flag.  */
 644   static struct ptt
 645     {
 646       const char *const name;           /* Canonical processor name.  */
 647       const enum processor_type processor; /* Processor type enum value.  */
 648       const int target_enable;  /* Target flags to enable.  */
 649     } const processor_target_table[]
 650       = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 651          {"403", PROCESSOR_PPC403,
 652           POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
 653          {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 654          {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
 655          {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 656          {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
 657          {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
 658          {"601", PROCESSOR_PPC601,
 659           MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
 660          {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 661          {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 662          {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 663          {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 664          {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 665          {"620", PROCESSOR_PPC620,
 666           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 667          {"630", PROCESSOR_PPC630,
 668           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 669          {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 670          {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
 671          {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
 672          {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 673          {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 674          {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 675          {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 676          {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 677          {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 678          {"970", PROCESSOR_POWER4,
 679           POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
 680          {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
 681          {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 682          {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 683          {"G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK},
 684          {"G5", PROCESSOR_POWER4,
 685           POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
 686          {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 687          {"power2", PROCESSOR_POWER,
 688           MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
 689          {"power3", PROCESSOR_PPC630,
 690           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 691          {"power4", PROCESSOR_POWER4,
 692           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 693          {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
 694          {"powerpc64", PROCESSOR_POWERPC64,
 695           POWERPC_BASE_MASK | MASK_POWERPC64},
 696          {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 697          {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 698          {"rios2", PROCESSOR_RIOS2,
 699           MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
 700          {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 701          {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 702          {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
 703       };
 704
 705   const size_t ptt_size = ARRAY_SIZE (processor_target_table);
 706
 707   /* Save current -mmultiple/-mno-multiple status.  */
 708   int multiple = TARGET_MULTIPLE;
 709   /* Save current -mstring/-mno-string status.  */
 710   int string = TARGET_STRING;
 711
 712   /* Some OSs don't support saving the high part of 64-bit registers on
 713      context switch.  Other OSs don't support saving Altivec registers.
 714      On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
 715      settings; if the user wants either, the user must explicitly specify
 716      them and we won't interfere with the user's specification.  */
 717
 718   enum {
 719     POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
 720     POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
 721                      | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
 722                      | MASK_MFCRF)
 723   };
 724  set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
 725 #ifdef OS_MISSING_POWERPC64
 726   if (OS_MISSING_POWERPC64)
 727     set_masks &= ~MASK_POWERPC64;
 728 #endif
 729 #ifdef OS_MISSING_ALTIVEC
 730   if (OS_MISSING_ALTIVEC)
 731     set_masks &= ~MASK_ALTIVEC;
 732 #endif
 733
 734   /* Identify the processor type.  */
 735   rs6000_select[0].string = default_cpu;
 736   rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
 737
 738   for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
 739     {
 740       ptr = &rs6000_select[i];
 741       if (ptr->string != (char *)0 && ptr->string[0] != '\0')
 742         {
 743           for (j = 0; j < ptt_size; j++)
 744             if (! strcmp (ptr->string, processor_target_table[j].name))
 745               {
 746                 if (ptr->set_tune_p)
 747                   rs6000_cpu = processor_target_table[j].processor;
 748
 749                 if (ptr->set_arch_p)
 750                   {
 751                     target_flags &= ~set_masks;
 752                     target_flags |= (processor_target_table[j].target_enable
 753                                      & set_masks);
 754                   }
 755                 break;
 756               }
 757
 758           if (j == ptt_size)
 759             error ("bad value (%s) for %s switch", ptr->string, ptr->name);
 760         }
 761     }
 762
 763   if (TARGET_E500)
 764     rs6000_isel = 1;
 765
 766   /* If we are optimizing big endian systems for space, use the load/store
 767      multiple and string instructions.  */
 768   if (BYTES_BIG_ENDIAN && optimize_size)
 769     target_flags |= MASK_MULTIPLE | MASK_STRING;
 770
 771   /* If -mmultiple or -mno-multiple was explicitly used, don't
 772      override with the processor default */
 773   if ((target_flags_explicit & MASK_MULTIPLE) != 0)
 774     target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
 775
 776   /* If -mstring or -mno-string was explicitly used, don't override
 777      with the processor default.  */
 778   if ((target_flags_explicit & MASK_STRING) != 0)
 779     target_flags = (target_flags & ~MASK_STRING) | string;
 780
 781   /* Don't allow -mmultiple or -mstring on little endian systems
 782      unless the cpu is a 750, because the hardware doesn't support the
 783      instructions used in little endian mode, and causes an alignment
 784      trap.  The 750 does not cause an alignment trap (except when the
 785      target is unaligned).  */
 786
 787   if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
 788     {
 789       if (TARGET_MULTIPLE)
 790         {
 791           target_flags &= ~MASK_MULTIPLE;
 792           if ((target_flags_explicit & MASK_MULTIPLE) != 0)
 793             warning ("-mmultiple is not supported on little endian systems");
 794         }
 795
 796       if (TARGET_STRING)
 797         {
 798           target_flags &= ~MASK_STRING;
 799           if ((target_flags_explicit & MASK_STRING) != 0)
 800             warning ("-mstring is not supported on little endian systems");
 801         }
 802     }
 803
 804   /* Set debug flags */
 805   if (rs6000_debug_name)
 806     {
 807       if (! strcmp (rs6000_debug_name, "all"))
 808         rs6000_debug_stack = rs6000_debug_arg = 1;
 809       else if (! strcmp (rs6000_debug_name, "stack"))
 810         rs6000_debug_stack = 1;
 811       else if (! strcmp (rs6000_debug_name, "arg"))
 812         rs6000_debug_arg = 1;
 813       else
 814         error ("unknown -mdebug-%s switch", rs6000_debug_name);
 815     }
 816
 817   if (rs6000_traceback_name)
 818     {
 819       if (! strncmp (rs6000_traceback_name, "full", 4))
 820         rs6000_traceback = traceback_full;
 821       else if (! strncmp (rs6000_traceback_name, "part", 4))
 822         rs6000_traceback = traceback_part;
 823       else if (! strncmp (rs6000_traceback_name, "no", 2))
 824         rs6000_traceback = traceback_none;
 825       else
 826         error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
 827                rs6000_traceback_name);
 828     }
 829
 830   /* Set size of long double */
 831   rs6000_long_double_type_size = 64;
 832   if (rs6000_long_double_size_string)
 833     {
 834       char *tail;
 835       int size = strtol (rs6000_long_double_size_string, &tail, 10);
 836       if (*tail != '\0' || (size != 64 && size != 128))
 837         error ("Unknown switch -mlong-double-%s",
 838                rs6000_long_double_size_string);
 839       else
 840         rs6000_long_double_type_size = size;
 841     }
 842
 843   /* Handle -mabi= options.  */
 844   rs6000_parse_abi_options ();
 845
 846   /* Handle -malign-XXXXX option.  */
 847   rs6000_parse_alignment_option ();
 848
 849   /* Handle generic -mFOO=YES/NO options.  */
 850   rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
 851                               &rs6000_altivec_vrsave);
 852   rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
 853                               &rs6000_isel);
 854   rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
 855   rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
 856                               &rs6000_float_gprs);
 857
 858   /* Handle -mtls-size option.  */
 859   rs6000_parse_tls_size_option ();
 860
 861 #ifdef SUBTARGET_OVERRIDE_OPTIONS
 862   SUBTARGET_OVERRIDE_OPTIONS;
 863 #endif
 864 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
 865   SUBSUBTARGET_OVERRIDE_OPTIONS;
 866 #endif
 867
 868   if (TARGET_E500)
 869     {
 870       /* The e500 does not have string instructions, and we set
 871          MASK_STRING above when optimizing for size.  */
 872       if ((target_flags & MASK_STRING) != 0)
 873         target_flags = target_flags & ~MASK_STRING;
 874
 875       /* No SPE means 64-bit long doubles, even if an E500.  */
 876       if (rs6000_spe_string != 0
 877           && !strcmp (rs6000_spe_string, "no"))
 878         rs6000_long_double_type_size = 64;
 879     }
 880   else if (rs6000_select[1].string != NULL)
 881     {
 882       /* For the powerpc-eabispe configuration, we set all these by
 883          default, so let's unset them if we manually set another
 884          CPU that is not the E500.  */
 885       if (rs6000_abi_string == 0)
 886         rs6000_spe_abi = 0;
 887       if (rs6000_spe_string == 0)
 888         rs6000_spe = 0;
 889       if (rs6000_float_gprs_string == 0)
 890         rs6000_float_gprs = 0;
 891       if (rs6000_isel_string == 0)
 892         rs6000_isel = 0;
 893       if (rs6000_long_double_size_string == 0)
 894         rs6000_long_double_type_size = 64;
 895     }
 896
 897   /* Handle -m(no-)longcall option.  This is a bit of a cheap hack,
 898      using TARGET_OPTIONS to handle a toggle switch, but we're out of
 899      bits in target_flags so TARGET_SWITCHES cannot be used.
 900      Assumption here is that rs6000_longcall_switch points into the
 901      text of the complete option, rather than being a copy, so we can
 902      scan back for the presence or absence of the no- modifier.  */
 903   if (rs6000_longcall_switch)
 904     {
 905       const char *base = rs6000_longcall_switch;
 906       while (base[-1] != 'm') base--;
 907
 908       if (*rs6000_longcall_switch != '\0')
 909         error ("invalid option `%s'", base);
 910       rs6000_default_long_calls = (base[0] != 'n');
 911     }
 912
 913   /* Handle -mprioritize-restricted-insns option.  */
 914   rs6000_sched_restricted_insns_priority = DEFAULT_RESTRICTED_INSNS_PRIORITY;
 915   if (rs6000_sched_restricted_insns_priority_str)
 916     rs6000_sched_restricted_insns_priority =
 917       atoi (rs6000_sched_restricted_insns_priority_str);
 918
 919   /* Handle -msched-costly-dep option.  */
 920   rs6000_sched_costly_dep = DEFAULT_SCHED_COSTLY_DEP;
 921   if (rs6000_sched_costly_dep_str)
 922     {
 923       if (! strcmp (rs6000_sched_costly_dep_str, "no"))
 924         rs6000_sched_costly_dep = no_dep_costly;
 925       else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
 926         rs6000_sched_costly_dep = all_deps_costly;
 927       else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
 928         rs6000_sched_costly_dep = true_store_to_load_dep_costly;
 929       else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
 930         rs6000_sched_costly_dep = store_to_load_dep_costly;
 931       else
 932         rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
 933     }
 934
 935   /* Handle -minsert-sched-nops option.  */
 936   rs6000_sched_insert_nops = DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME;
 937   if (rs6000_sched_insert_nops_str)
 938     {
 939       if (! strcmp (rs6000_sched_insert_nops_str, "no"))
 940         rs6000_sched_insert_nops = sched_finish_none;
 941       else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
 942         rs6000_sched_insert_nops = sched_finish_pad_groups;
 943       else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
 944         rs6000_sched_insert_nops = sched_finish_regroup_exact;
 945       else
 946         rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
 947     }
 948
 949 #ifdef TARGET_REGNAMES
 950   /* If the user desires alternate register names, copy in the
 951      alternate names now.  */
 952   if (TARGET_REGNAMES)
 953     memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
 954 #endif
 955
 956   /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
 957      If -maix-struct-return or -msvr4-struct-return was explicitly
 958      used, don't override with the ABI default.  */
 959   if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
 960     {
 961       if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
 962         target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
 963       else
 964         target_flags |= MASK_AIX_STRUCT_RET;
 965     }
 966
 967   if (TARGET_LONG_DOUBLE_128
 968       && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
 969     REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
 970
 971   /* Allocate an alias set for register saves & restores from stack.  */
 972   rs6000_sr_alias_set = new_alias_set ();
 973
 974   if (TARGET_TOC)
 975     ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
 976
 977   /* We can only guarantee the availability of DI pseudo-ops when
 978      assembling for 64-bit targets.  */
 979   if (!TARGET_64BIT)
 980     {
 981       targetm.asm_out.aligned_op.di = NULL;
 982       targetm.asm_out.unaligned_op.di = NULL;
 983     }
 984
 985   /* Set maximum branch target alignment at two instructions, eight bytes.  */
 986   align_jumps_max_skip = 8;
 987   align_loops_max_skip = 8;
 988
 989   /* Arrange to save and restore machine status around nested functions.  */
 990   init_machine_status = rs6000_init_machine_status;
 991 }
 992
 993 /* Handle generic options of the form -mfoo=yes/no.
 994    NAME is the option name.
 995    VALUE is the option value.
 996    FLAG is the pointer to the flag where to store a 1 or 0, depending on
 997    whether the option value is 'yes' or 'no' respectively.  */
 998 static void
 999 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1000 {
1001   if (value == 0)
1002     return;
1003   else if (!strcmp (value, "yes"))
1004     *flag = 1;
1005   else if (!strcmp (value, "no"))
1006     *flag = 0;
1007   else
1008     error ("unknown -m%s= option specified: '%s'", name, value);
1009 }
1010
1011 /* Handle -mabi= options.  */
1012 static void
1013 rs6000_parse_abi_options (void)
1014 {
1015   if (rs6000_abi_string == 0)
1016     return;
1017   else if (! strcmp (rs6000_abi_string, "altivec"))
1018     rs6000_altivec_abi = 1;
1019   else if (! strcmp (rs6000_abi_string, "no-altivec"))
1020     rs6000_altivec_abi = 0;
1021   else if (! strcmp (rs6000_abi_string, "spe"))
1022     {
1023       rs6000_spe_abi = 1;
1024       if (!TARGET_SPE_ABI)
1025         error ("not configured for ABI: '%s'", rs6000_abi_string);
1026     }
1027
1028   else if (! strcmp (rs6000_abi_string, "no-spe"))
1029     rs6000_spe_abi = 0;
1030   else
1031     error ("unknown ABI specified: '%s'", rs6000_abi_string);
1032 }
1033
1034 /* Handle -malign-XXXXXX options.  */
1035 static void
1036 rs6000_parse_alignment_option (void)
1037 {
1038   if (rs6000_alignment_string == 0)
1039     return;
1040   else if (! strcmp (rs6000_alignment_string, "power"))
1041     rs6000_alignment_flags = MASK_ALIGN_POWER;
1042   else if (! strcmp (rs6000_alignment_string, "natural"))
1043     rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1044   else
1045     error ("unknown -malign-XXXXX option specified: '%s'",
1046            rs6000_alignment_string);
1047 }
1048
1049 /* Validate and record the size specified with the -mtls-size option.  */
1050
1051 static void
1052 rs6000_parse_tls_size_option (void)
1053 {
1054   if (rs6000_tls_size_string == 0)
1055     return;
1056   else if (strcmp (rs6000_tls_size_string, "16") == 0)
1057     rs6000_tls_size = 16;
1058   else if (strcmp (rs6000_tls_size_string, "32") == 0)
1059     rs6000_tls_size = 32;
1060   else if (strcmp (rs6000_tls_size_string, "64") == 0)
1061     rs6000_tls_size = 64;
1062   else
1063     error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1064 }
1065
1066 void
1067 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1068 {
1069 }
1070 \f
1071 /* Do anything needed at the start of the asm file.  */
1072
1073 static void
1074 rs6000_file_start (void)
1075 {
1076   size_t i;
1077   char buffer[80];
1078   const char *start = buffer;
1079   struct rs6000_cpu_select *ptr;
1080   const char *default_cpu = TARGET_CPU_DEFAULT;
1081   FILE *file = asm_out_file;
1082
1083   default_file_start ();
1084
1085 #ifdef TARGET_BI_ARCH
1086   if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1087     default_cpu = 0;
1088 #endif
1089
1090   if (flag_verbose_asm)
1091     {
1092       sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1093       rs6000_select[0].string = default_cpu;
1094
1095       for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1096         {
1097           ptr = &rs6000_select[i];
1098           if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1099             {
1100               fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1101               start = "";
1102             }
1103         }
1104
1105 #ifdef USING_ELFOS_H
1106       switch (rs6000_sdata)
1107         {
1108         case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1109         case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1110         case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1111         case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1112         }
1113
1114       if (rs6000_sdata && g_switch_value)
1115         {
1116           fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1117                    g_switch_value);
1118           start = "";
1119         }
1120 #endif
1121
1122       if (*start == '\0')
1123         putc ('\n', file);
1124     }
1125 }
1126 \f
1127 /* Return nonzero if this function is known to have a null epilogue.  */
1128
1129 int
1130 direct_return (void)
1131 {
1132   if (reload_completed)
1133     {
1134       rs6000_stack_t *info = rs6000_stack_info ();
1135
1136       if (info->first_gp_reg_save == 32
1137           && info->first_fp_reg_save == 64
1138           && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1139           && ! info->lr_save_p
1140           && ! info->cr_save_p
1141           && info->vrsave_mask == 0
1142           && ! info->push_p)
1143         return 1;
1144     }
1145
1146   return 0;
1147 }
1148
1149 /* Returns 1 always.  */
1150
1151 int
1152 any_operand (rtx op ATTRIBUTE_UNUSED,
1153              enum machine_mode mode ATTRIBUTE_UNUSED)
1154 {
1155   return 1;
1156 }
1157
1158 /* Returns 1 if op is the count register.  */
1159 int
1160 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1161 {
1162   if (GET_CODE (op) != REG)
1163     return 0;
1164
1165   if (REGNO (op) == COUNT_REGISTER_REGNUM)
1166     return 1;
1167
1168   if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1169     return 1;
1170
1171   return 0;
1172 }
1173
1174 /* Returns 1 if op is an altivec register.  */
1175 int
1176 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1177 {
1178
1179   return (register_operand (op, mode)
1180           && (GET_CODE (op) != REG
1181               || REGNO (op) > FIRST_PSEUDO_REGISTER
1182               || ALTIVEC_REGNO_P (REGNO (op))));
1183 }
1184
1185 int
1186 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1187 {
1188   if (GET_CODE (op) != REG)
1189     return 0;
1190
1191   if (XER_REGNO_P (REGNO (op)))
1192     return 1;
1193
1194   return 0;
1195 }
1196
1197 /* Return 1 if OP is a signed 8-bit constant.  Int multiplication
1198    by such constants completes more quickly.  */
1199
1200 int
1201 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1202 {
1203   return ( GET_CODE (op) == CONST_INT
1204           && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1205 }
1206
1207 /* Return 1 if OP is a constant that can fit in a D field.  */
1208
1209 int
1210 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1211 {
1212   return (GET_CODE (op) == CONST_INT
1213           && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1214 }
1215
1216 /* Similar for an unsigned D field.  */
1217
1218 int
1219 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1220 {
1221   return (GET_CODE (op) == CONST_INT
1222           && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1223 }
1224
1225 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field.  */
1226
1227 int
1228 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1229 {
1230   return (GET_CODE (op) == CONST_INT
1231           && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1232 }
1233
1234 /* Returns 1 if OP is a CONST_INT that is a positive value
1235    and an exact power of 2.  */
1236
1237 int
1238 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1239 {
1240   return (GET_CODE (op) == CONST_INT
1241           && INTVAL (op) > 0
1242           && exact_log2 (INTVAL (op)) >= 0);
1243 }
1244
1245 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1246    ctr, or lr).  */
1247
1248 int
1249 gpc_reg_operand (rtx op, enum machine_mode mode)
1250 {
1251   return (register_operand (op, mode)
1252           && (GET_CODE (op) != REG
1253               || (REGNO (op) >= ARG_POINTER_REGNUM
1254                   && !XER_REGNO_P (REGNO (op)))
1255               || REGNO (op) < MQ_REGNO));
1256 }
1257
1258 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1259    CR field.  */
1260
1261 int
1262 cc_reg_operand (rtx op, enum machine_mode mode)
1263 {
1264   return (register_operand (op, mode)
1265           && (GET_CODE (op) != REG
1266               || REGNO (op) >= FIRST_PSEUDO_REGISTER
1267               || CR_REGNO_P (REGNO (op))));
1268 }
1269
1270 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1271    CR field that isn't CR0.  */
1272
1273 int
1274 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1275 {
1276   return (register_operand (op, mode)
1277           && (GET_CODE (op) != REG
1278               || REGNO (op) >= FIRST_PSEUDO_REGISTER
1279               || CR_REGNO_NOT_CR0_P (REGNO (op))));
1280 }
1281
1282 /* Returns 1 if OP is either a constant integer valid for a D-field or
1283    a non-special register.  If a register, it must be in the proper
1284    mode unless MODE is VOIDmode.  */
1285
1286 int
1287 reg_or_short_operand (rtx op, enum machine_mode mode)
1288 {
1289   return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1290 }
1291
1292 /* Similar, except check if the negation of the constant would be
1293    valid for a D-field.  */
1294
1295 int
1296 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1297 {
1298   if (GET_CODE (op) == CONST_INT)
1299     return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1300
1301   return gpc_reg_operand (op, mode);
1302 }
1303
1304 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1305    a non-special register.  If a register, it must be in the proper
1306    mode unless MODE is VOIDmode.  */
1307
1308 int
1309 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1310 {
1311   if (gpc_reg_operand (op, mode))
1312     return 1;
1313   else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1314     return 1;
1315
1316   return 0;
1317 }
1318
1319
1320 /* Return 1 if the operand is either a register or an integer whose
1321    high-order 16 bits are zero.  */
1322
1323 int
1324 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1325 {
1326   return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1327 }
1328
1329 /* Return 1 is the operand is either a non-special register or ANY
1330    constant integer.  */
1331
1332 int
1333 reg_or_cint_operand (rtx op, enum machine_mode mode)
1334 {
1335   return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1336 }
1337
1338 /* Return 1 is the operand is either a non-special register or ANY
1339    32-bit signed constant integer.  */
1340
1341 int
1342 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1343 {
1344   return (gpc_reg_operand (op, mode)
1345           || (GET_CODE (op) == CONST_INT
1346 #if HOST_BITS_PER_WIDE_INT != 32
1347               && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1348                   < (unsigned HOST_WIDE_INT) 0x100000000ll)
1349 #endif
1350               ));
1351 }
1352
1353 /* Return 1 is the operand is either a non-special register or a 32-bit
1354    signed constant integer valid for 64-bit addition.  */
1355
1356 int
1357 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1358 {
1359   return (gpc_reg_operand (op, mode)
1360           || (GET_CODE (op) == CONST_INT
1361 #if HOST_BITS_PER_WIDE_INT == 32
1362               && INTVAL (op) < 0x7fff8000
1363 #else
1364               && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1365                   < 0x100000000ll)
1366 #endif
1367               ));
1368 }
1369
1370 /* Return 1 is the operand is either a non-special register or a 32-bit
1371    signed constant integer valid for 64-bit subtraction.  */
1372
1373 int
1374 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1375 {
1376   return (gpc_reg_operand (op, mode)
1377           || (GET_CODE (op) == CONST_INT
1378 #if HOST_BITS_PER_WIDE_INT == 32
1379               && (- INTVAL (op)) < 0x7fff8000
1380 #else
1381               && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1382                   < 0x100000000ll)
1383 #endif
1384               ));
1385 }
1386
1387 /* Return 1 is the operand is either a non-special register or ANY
1388    32-bit unsigned constant integer.  */
1389
1390 int
1391 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1392 {
1393   if (GET_CODE (op) == CONST_INT)
1394     {
1395       if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1396         {
1397           if (GET_MODE_BITSIZE (mode) <= 32)
1398             abort ();
1399
1400           if (INTVAL (op) < 0)
1401             return 0;
1402         }
1403
1404       return ((INTVAL (op) & GET_MODE_MASK (mode)
1405                & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1406     }
1407   else if (GET_CODE (op) == CONST_DOUBLE)
1408     {
1409       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1410           || mode != DImode)
1411         abort ();
1412
1413       return CONST_DOUBLE_HIGH (op) == 0;
1414     }
1415   else
1416     return gpc_reg_operand (op, mode);
1417 }
1418
1419 /* Return 1 if the operand is an operand that can be loaded via the GOT.  */
1420
1421 int
1422 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1423 {
1424   return (GET_CODE (op) == SYMBOL_REF
1425           || GET_CODE (op) == CONST
1426           || GET_CODE (op) == LABEL_REF);
1427 }
1428
1429 /* Return 1 if the operand is a simple references that can be loaded via
1430    the GOT (labels involving addition aren't allowed).  */
1431
1432 int
1433 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1434 {
1435   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1436 }
1437
1438 /* Return the number of instructions it takes to form a constant in an
1439    integer register.  */
1440
1441 static int
1442 num_insns_constant_wide (HOST_WIDE_INT value)
1443 {
1444   /* signed constant loadable with {cal|addi} */
1445   if (CONST_OK_FOR_LETTER_P (value, 'I'))
1446     return 1;
1447
1448   /* constant loadable with {cau|addis} */
1449   else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1450     return 1;
1451
1452 #if HOST_BITS_PER_WIDE_INT == 64
1453   else if (TARGET_POWERPC64)
1454     {
1455       HOST_WIDE_INT low  = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1456       HOST_WIDE_INT high = value >> 31;
1457
1458       if (high == 0 || high == -1)
1459         return 2;
1460
1461       high >>= 1;
1462
1463       if (low == 0)
1464         return num_insns_constant_wide (high) + 1;
1465       else
1466         return (num_insns_constant_wide (high)
1467                 + num_insns_constant_wide (low) + 1);
1468     }
1469 #endif
1470
1471   else
1472     return 2;
1473 }
1474
1475 int
1476 num_insns_constant (rtx op, enum machine_mode mode)
1477 {
1478   if (GET_CODE (op) == CONST_INT)
1479     {
1480 #if HOST_BITS_PER_WIDE_INT == 64
1481       if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1482           && mask64_operand (op, mode))
1483             return 2;
1484       else
1485 #endif
1486         return num_insns_constant_wide (INTVAL (op));
1487     }
1488
1489   else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1490     {
1491       long l;
1492       REAL_VALUE_TYPE rv;
1493
1494       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1495       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1496       return num_insns_constant_wide ((HOST_WIDE_INT) l);
1497     }
1498
1499   else if (GET_CODE (op) == CONST_DOUBLE)
1500     {
1501       HOST_WIDE_INT low;
1502       HOST_WIDE_INT high;
1503       long l[2];
1504       REAL_VALUE_TYPE rv;
1505       int endian = (WORDS_BIG_ENDIAN == 0);
1506
1507       if (mode == VOIDmode || mode == DImode)
1508         {
1509           high = CONST_DOUBLE_HIGH (op);
1510           low  = CONST_DOUBLE_LOW (op);
1511         }
1512       else
1513         {
1514           REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1515           REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1516           high = l[endian];
1517           low  = l[1 - endian];
1518         }
1519
1520       if (TARGET_32BIT)
1521         return (num_insns_constant_wide (low)
1522                 + num_insns_constant_wide (high));
1523
1524       else
1525         {
1526           if (high == 0 && low >= 0)
1527             return num_insns_constant_wide (low);
1528
1529           else if (high == -1 && low < 0)
1530             return num_insns_constant_wide (low);
1531
1532           else if (mask64_operand (op, mode))
1533             return 2;
1534
1535           else if (low == 0)
1536             return num_insns_constant_wide (high) + 1;
1537
1538           else
1539             return (num_insns_constant_wide (high)
1540                     + num_insns_constant_wide (low) + 1);
1541         }
1542     }
1543
1544   else
1545     abort ();
1546 }
1547
1548 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1549    register with one instruction per word.  We only do this if we can
1550    safely read CONST_DOUBLE_{LOW,HIGH}.  */
1551
1552 int
1553 easy_fp_constant (rtx op, enum machine_mode mode)
1554 {
1555   if (GET_CODE (op) != CONST_DOUBLE
1556       || GET_MODE (op) != mode
1557       || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1558     return 0;
1559
1560   /* Consider all constants with -msoft-float to be easy.  */
1561   if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1562       && mode != DImode)
1563     return 1;
1564
1565   /* If we are using V.4 style PIC, consider all constants to be hard.  */
1566   if (flag_pic && DEFAULT_ABI == ABI_V4)
1567     return 0;
1568
1569 #ifdef TARGET_RELOCATABLE
1570   /* Similarly if we are using -mrelocatable, consider all constants
1571      to be hard.  */
1572   if (TARGET_RELOCATABLE)
1573     return 0;
1574 #endif
1575
1576   if (mode == TFmode)
1577     {
1578       long k[4];
1579       REAL_VALUE_TYPE rv;
1580
1581       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1582       REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1583
1584       return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1585               && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1586               && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1587               && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1588     }
1589
1590   else if (mode == DFmode)
1591     {
1592       long k[2];
1593       REAL_VALUE_TYPE rv;
1594
1595       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1596       REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1597
1598       return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1599               && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1600     }
1601
1602   else if (mode == SFmode)
1603     {
1604       long l;
1605       REAL_VALUE_TYPE rv;
1606
1607       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1608       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1609
1610       return num_insns_constant_wide (l) == 1;
1611     }
1612
1613   else if (mode == DImode)
1614     return ((TARGET_POWERPC64
1615              && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1616             || (num_insns_constant (op, DImode) <= 2));
1617
1618   else if (mode == SImode)
1619     return 1;
1620   else
1621     abort ();
1622 }
1623
1624 /* Return nonzero if all elements of a vector have the same value.  */
1625
1626 static int
1627 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1628 {
1629   int units, i, cst;
1630
1631   units = CONST_VECTOR_NUNITS (op);
1632
1633   cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1634   for (i = 1; i < units; ++i)
1635     if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1636       break;
1637   if (i == units)
1638     return 1;
1639   return 0;
1640 }
1641
1642 /* Return 1 if the operand is a CONST_INT and can be put into a
1643    register without using memory.  */
1644
1645 int
1646 easy_vector_constant (rtx op, enum machine_mode mode)
1647 {
1648   int cst, cst2;
1649
1650   if (GET_CODE (op) != CONST_VECTOR
1651       || (!TARGET_ALTIVEC
1652           && !TARGET_SPE))
1653     return 0;
1654
1655   if (zero_constant (op, mode)
1656       && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
1657           || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
1658     return 1;
1659
1660   if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
1661     return 0;
1662
1663   if (TARGET_SPE && mode == V1DImode)
1664     return 0;
1665
1666   cst  = INTVAL (CONST_VECTOR_ELT (op, 0));
1667   cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
1668
1669   /* Limit SPE vectors to 15 bits signed.  These we can generate with:
1670        li r0, CONSTANT1
1671        evmergelo r0, r0, r0
1672        li r0, CONSTANT2
1673
1674      I don't know how efficient it would be to allow bigger constants,
1675      considering we'll have an extra 'ori' for every 'li'.  I doubt 5
1676      instructions is better than a 64-bit memory load, but I don't
1677      have the e500 timing specs.  */
1678   if (TARGET_SPE && mode == V2SImode
1679       && cst  >= -0x7fff && cst <= 0x7fff
1680       && cst2 >= -0x7fff && cst2 <= 0x7fff)
1681     return 1;
1682
1683   if (TARGET_ALTIVEC)
1684     switch (mode)
1685       {
1686       case V4SImode:
1687         if (EASY_VECTOR_15 (cst, op, mode))
1688           return 1;
1689         if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1690           break;
1691         cst = cst >> 16;
1692       case V8HImode:
1693         if (EASY_VECTOR_15 (cst, op, mode))
1694           return 1;
1695         if ((cst & 0xff) != ((cst >> 8) & 0xff))
1696           break;
1697         cst = cst >> 8;
1698       case V16QImode:
1699         if (EASY_VECTOR_15 (cst, op, mode))
1700           return 1;
1701       default:
1702         break;
1703       }
1704
1705   if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode))
1706     return 1;
1707
1708   return 0;
1709 }
1710
1711 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.  */
1712
1713 int
1714 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
1715 {
1716   int cst;
1717
1718   if (!easy_vector_constant (op, mode))
1719     return 0;
1720
1721   cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1722
1723   return TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode);
1724 }
1725
1726 const char *
1727 output_vec_const_move (rtx *operands)
1728 {
1729   int cst, cst2;
1730   enum machine_mode mode;
1731   rtx dest, vec;
1732
1733   dest = operands[0];
1734   vec = operands[1];
1735
1736   cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1737   cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1738   mode = GET_MODE (dest);
1739
1740   if (TARGET_ALTIVEC)
1741     {
1742       if (zero_constant (vec, mode))
1743         return "vxor %0,%0,%0";
1744       else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
1745         return "#";
1746       else if (easy_vector_constant (vec, mode))
1747         {
1748           operands[1] = GEN_INT (cst);
1749           switch (mode)
1750             {
1751             case V4SImode:
1752               if (EASY_VECTOR_15 (cst, vec, mode))
1753                 {
1754                   operands[1] = GEN_INT (cst);
1755                   return "vspltisw %0,%1";
1756                 }
1757               cst = cst >> 16;
1758             case V8HImode:
1759               if (EASY_VECTOR_15 (cst, vec, mode))
1760                 {
1761                   operands[1] = GEN_INT (cst);
1762                   return "vspltish %0,%1";
1763                 }
1764               cst = cst >> 8;
1765             case V16QImode:
1766               if (EASY_VECTOR_15 (cst, vec, mode))
1767                 {
1768                   operands[1] = GEN_INT (cst);
1769                   return "vspltisb %0,%1";
1770                 }
1771             default:
1772               abort ();
1773             }
1774         }
1775       else
1776         abort ();
1777     }
1778
1779   if (TARGET_SPE)
1780     {
1781       /* Vector constant 0 is handled as a splitter of V2SI, and in the
1782          pattern of V1DI, V4HI, and V2SF.
1783
1784          FIXME: We should probably return # and add post reload
1785          splitters for these, but this way is so easy ;-).
1786       */
1787       operands[1] = GEN_INT (cst);
1788       operands[2] = GEN_INT (cst2);
1789       if (cst == cst2)
1790         return "li %0,%1\n\tevmergelo %0,%0,%0";
1791       else
1792         return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
1793     }
1794
1795   abort ();
1796 }
1797
1798 /* Return 1 if the operand is the constant 0.  This works for scalars
1799    as well as vectors.  */
1800 int
1801 zero_constant (rtx op, enum machine_mode mode)
1802 {
1803   return op == CONST0_RTX (mode);
1804 }
1805
1806 /* Return 1 if the operand is 0.0.  */
1807 int
1808 zero_fp_constant (rtx op, enum machine_mode mode)
1809 {
1810   return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1811 }
1812
1813 /* Return 1 if the operand is in volatile memory.  Note that during
1814    the RTL generation phase, memory_operand does not return TRUE for
1815    volatile memory references.  So this function allows us to
1816    recognize volatile references where its safe.  */
1817
1818 int
1819 volatile_mem_operand (rtx op, enum machine_mode mode)
1820 {
1821   if (GET_CODE (op) != MEM)
1822     return 0;
1823
1824   if (!MEM_VOLATILE_P (op))
1825     return 0;
1826
1827   if (mode != GET_MODE (op))
1828     return 0;
1829
1830   if (reload_completed)
1831     return memory_operand (op, mode);
1832
1833   if (reload_in_progress)
1834     return strict_memory_address_p (mode, XEXP (op, 0));
1835
1836   return memory_address_p (mode, XEXP (op, 0));
1837 }
1838
1839 /* Return 1 if the operand is an offsettable memory operand.  */
1840
1841 int
1842 offsettable_mem_operand (rtx op, enum machine_mode mode)
1843 {
1844   return ((GET_CODE (op) == MEM)
1845           && offsettable_address_p (reload_completed || reload_in_progress,
1846                                     mode, XEXP (op, 0)));
1847 }
1848
1849 /* Return 1 if the operand is either an easy FP constant (see above) or
1850    memory.  */
1851
1852 int
1853 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
1854 {
1855   return memory_operand (op, mode) || easy_fp_constant (op, mode);
1856 }
1857
1858 /* Return 1 if the operand is either a non-special register or an item
1859    that can be used as the operand of a `mode' add insn.  */
1860
1861 int
1862 add_operand (rtx op, enum machine_mode mode)
1863 {
1864   if (GET_CODE (op) == CONST_INT)
1865     return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1866             || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1867
1868   return gpc_reg_operand (op, mode);
1869 }
1870
1871 /* Return 1 if OP is a constant but not a valid add_operand.  */
1872
1873 int
1874 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1875 {
1876   return (GET_CODE (op) == CONST_INT
1877           && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1878           && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1879 }
1880
1881 /* Return 1 if the operand is a non-special register or a constant that
1882    can be used as the operand of an OR or XOR insn on the RS/6000.  */
1883
1884 int
1885 logical_operand (rtx op, enum machine_mode mode)
1886 {
1887   HOST_WIDE_INT opl, oph;
1888
1889   if (gpc_reg_operand (op, mode))
1890     return 1;
1891
1892   if (GET_CODE (op) == CONST_INT)
1893     {
1894       opl = INTVAL (op) & GET_MODE_MASK (mode);
1895
1896 #if HOST_BITS_PER_WIDE_INT <= 32
1897       if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1898         return 0;
1899 #endif
1900     }
1901   else if (GET_CODE (op) == CONST_DOUBLE)
1902     {
1903       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1904         abort ();
1905
1906       opl = CONST_DOUBLE_LOW (op);
1907       oph = CONST_DOUBLE_HIGH (op);
1908       if (oph != 0)
1909         return 0;
1910     }
1911   else
1912     return 0;
1913
1914   return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1915           || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
1916 }
1917
1918 /* Return 1 if C is a constant that is not a logical operand (as
1919    above), but could be split into one.  */
1920
1921 int
1922 non_logical_cint_operand (rtx op, enum machine_mode mode)
1923 {
1924   return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1925           && ! logical_operand (op, mode)
1926           && reg_or_logical_cint_operand (op, mode));
1927 }
1928
1929 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
1930    RS/6000.  It is if there are no more than two 1->0 or 0->1 transitions.
1931    Reject all ones and all zeros, since these should have been optimized
1932    away and confuse the making of MB and ME.  */
1933
1934 int
1935 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1936 {
1937   HOST_WIDE_INT c, lsb;
1938
1939   if (GET_CODE (op) != CONST_INT)
1940     return 0;
1941
1942   c = INTVAL (op);
1943
1944   /* Fail in 64-bit mode if the mask wraps around because the upper
1945      32-bits of the mask will all be 1s, contrary to GCC's internal view.  */
1946   if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
1947     return 0;
1948
1949   /* We don't change the number of transitions by inverting,
1950      so make sure we start with the LS bit zero.  */
1951   if (c & 1)
1952     c = ~c;
1953
1954   /* Reject all zeros or all ones.  */
1955   if (c == 0)
1956     return 0;
1957
1958   /* Find the first transition.  */
1959   lsb = c & -c;
1960
1961   /* Invert to look for a second transition.  */
1962   c = ~c;
1963
1964   /* Erase first transition.  */
1965   c &= -lsb;
1966
1967   /* Find the second transition (if any).  */
1968   lsb = c & -c;
1969
1970   /* Match if all the bits above are 1's (or c is zero).  */
1971   return c == -lsb;
1972 }
1973
1974 /* Return 1 for the PowerPC64 rlwinm corner case.  */
1975
1976 int
1977 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1978 {
1979   HOST_WIDE_INT c, lsb;
1980
1981   if (GET_CODE (op) != CONST_INT)
1982     return 0;
1983
1984   c = INTVAL (op);
1985
1986   if ((c & 0x80000001) != 0x80000001)
1987     return 0;
1988
1989   c = ~c;
1990   if (c == 0)
1991     return 0;
1992
1993   lsb = c & -c;
1994   c = ~c;
1995   c &= -lsb;
1996   lsb = c & -c;
1997   return c == -lsb;
1998 }
1999
2000 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2001    It is if there are no more than one 1->0 or 0->1 transitions.
2002    Reject all zeros, since zero should have been optimized away and
2003    confuses the making of MB and ME.  */
2004
2005 int
2006 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2007 {
2008   if (GET_CODE (op) == CONST_INT)
2009     {
2010       HOST_WIDE_INT c, lsb;
2011
2012       c = INTVAL (op);
2013
2014       /* Reject all zeros.  */
2015       if (c == 0)
2016         return 0;
2017
2018       /* We don't change the number of transitions by inverting,
2019          so make sure we start with the LS bit zero.  */
2020       if (c & 1)
2021         c = ~c;
2022
2023       /* Find the transition, and check that all bits above are 1's.  */
2024       lsb = c & -c;
2025
2026       /* Match if all the bits above are 1's (or c is zero).  */
2027       return c == -lsb;
2028     }
2029   return 0;
2030 }
2031
2032 /* Like mask64_operand, but allow up to three transitions.  This
2033    predicate is used by insn patterns that generate two rldicl or
2034    rldicr machine insns.  */
2035
2036 int
2037 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2038 {
2039   if (GET_CODE (op) == CONST_INT)
2040     {
2041       HOST_WIDE_INT c, lsb;
2042
2043       c = INTVAL (op);
2044
2045       /* Disallow all zeros.  */
2046       if (c == 0)
2047         return 0;
2048
2049       /* We don't change the number of transitions by inverting,
2050          so make sure we start with the LS bit zero.  */
2051       if (c & 1)
2052         c = ~c;
2053
2054       /* Find the first transition.  */
2055       lsb = c & -c;
2056
2057       /* Invert to look for a second transition.  */
2058       c = ~c;
2059
2060       /* Erase first transition.  */
2061       c &= -lsb;
2062
2063       /* Find the second transition.  */
2064       lsb = c & -c;
2065
2066       /* Invert to look for a third transition.  */
2067       c = ~c;
2068
2069       /* Erase second transition.  */
2070       c &= -lsb;
2071
2072       /* Find the third transition (if any).  */
2073       lsb = c & -c;
2074
2075       /* Match if all the bits above are 1's (or c is zero).  */
2076       return c == -lsb;
2077     }
2078   return 0;
2079 }
2080
2081 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2082    implement ANDing by the mask IN.  */
2083 void
2084 build_mask64_2_operands (rtx in, rtx *out)
2085 {
2086 #if HOST_BITS_PER_WIDE_INT >= 64
2087   unsigned HOST_WIDE_INT c, lsb, m1, m2;
2088   int shift;
2089
2090   if (GET_CODE (in) != CONST_INT)
2091     abort ();
2092
2093   c = INTVAL (in);
2094   if (c & 1)
2095     {
2096       /* Assume c initially something like 0x00fff000000fffff.  The idea
2097          is to rotate the word so that the middle ^^^^^^ group of zeros
2098          is at the MS end and can be cleared with an rldicl mask.  We then
2099          rotate back and clear off the MS    ^^ group of zeros with a
2100          second rldicl.  */
2101       c = ~c;                   /*   c == 0xff000ffffff00000 */
2102       lsb = c & -c;             /* lsb == 0x0000000000100000 */
2103       m1 = -lsb;                /*  m1 == 0xfffffffffff00000 */
2104       c = ~c;                   /*   c == 0x00fff000000fffff */
2105       c &= -lsb;                /*   c == 0x00fff00000000000 */
2106       lsb = c & -c;             /* lsb == 0x0000100000000000 */
2107       c = ~c;                   /*   c == 0xff000fffffffffff */
2108       c &= -lsb;                /*   c == 0xff00000000000000 */
2109       shift = 0;
2110       while ((lsb >>= 1) != 0)
2111         shift++;                /* shift == 44 on exit from loop */
2112       m1 <<= 64 - shift;        /*  m1 == 0xffffff0000000000 */
2113       m1 = ~m1;                 /*  m1 == 0x000000ffffffffff */
2114       m2 = ~c;                  /*  m2 == 0x00ffffffffffffff */
2115     }
2116   else
2117     {
2118       /* Assume c initially something like 0xff000f0000000000.  The idea
2119          is to rotate the word so that the     ^^^  middle group of zeros
2120          is at the LS end and can be cleared with an rldicr mask.  We then
2121          rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2122          a second rldicr.  */
2123       lsb = c & -c;             /* lsb == 0x0000010000000000 */
2124       m2 = -lsb;                /*  m2 == 0xffffff0000000000 */
2125       c = ~c;                   /*   c == 0x00fff0ffffffffff */
2126       c &= -lsb;                /*   c == 0x00fff00000000000 */
2127       lsb = c & -c;             /* lsb == 0x0000100000000000 */
2128       c = ~c;                   /*   c == 0xff000fffffffffff */
2129       c &= -lsb;                /*   c == 0xff00000000000000 */
2130       shift = 0;
2131       while ((lsb >>= 1) != 0)
2132         shift++;                /* shift == 44 on exit from loop */
2133       m1 = ~c;                  /*  m1 == 0x00ffffffffffffff */
2134       m1 >>= shift;             /*  m1 == 0x0000000000000fff */
2135       m1 = ~m1;                 /*  m1 == 0xfffffffffffff000 */
2136     }
2137
2138   /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2139      masks will be all 1's.  We are guaranteed more than one transition.  */
2140   out[0] = GEN_INT (64 - shift);
2141   out[1] = GEN_INT (m1);
2142   out[2] = GEN_INT (shift);
2143   out[3] = GEN_INT (m2);
2144 #else
2145   (void)in;
2146   (void)out;
2147   abort ();
2148 #endif
2149 }
2150
2151 /* Return 1 if the operand is either a non-special register or a constant
2152    that can be used as the operand of a PowerPC64 logical AND insn.  */
2153
2154 int
2155 and64_operand (rtx op, enum machine_mode mode)
2156 {
2157   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2158     return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2159
2160   return (logical_operand (op, mode) || mask64_operand (op, mode));
2161 }
2162
2163 /* Like the above, but also match constants that can be implemented
2164    with two rldicl or rldicr insns.  */
2165
2166 int
2167 and64_2_operand (rtx op, enum machine_mode mode)
2168 {
2169   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2170     return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2171
2172   return logical_operand (op, mode) || mask64_2_operand (op, mode);
2173 }
2174
2175 /* Return 1 if the operand is either a non-special register or a
2176    constant that can be used as the operand of an RS/6000 logical AND insn.  */
2177
2178 int
2179 and_operand (rtx op, enum machine_mode mode)
2180 {
2181   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2182     return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2183
2184   return (logical_operand (op, mode) || mask_operand (op, mode));
2185 }
2186
2187 /* Return 1 if the operand is a general register or memory operand.  */
2188
2189 int
2190 reg_or_mem_operand (rtx op, enum machine_mode mode)
2191 {
2192   return (gpc_reg_operand (op, mode)
2193           || memory_operand (op, mode)
2194           || macho_lo_sum_memory_operand (op, mode)
2195           || volatile_mem_operand (op, mode));
2196 }
2197
2198 /* Return 1 if the operand is a general register or memory operand without
2199    pre_inc or pre_dec which produces invalid form of PowerPC lwa
2200    instruction.  */
2201
2202 int
2203 lwa_operand (rtx op, enum machine_mode mode)
2204 {
2205   rtx inner = op;
2206
2207   if (reload_completed && GET_CODE (inner) == SUBREG)
2208     inner = SUBREG_REG (inner);
2209
2210   return gpc_reg_operand (inner, mode)
2211     || (memory_operand (inner, mode)
2212         && GET_CODE (XEXP (inner, 0)) != PRE_INC
2213         && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2214         && (GET_CODE (XEXP (inner, 0)) != PLUS
2215             || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2216             || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2217 }
2218
2219 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.  */
2220
2221 int
2222 symbol_ref_operand (rtx op, enum machine_mode mode)
2223 {
2224   if (mode != VOIDmode && GET_MODE (op) != mode)
2225     return 0;
2226
2227   return (GET_CODE (op) == SYMBOL_REF
2228           && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2229 }
2230
2231 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2232    to CALL.  This is a SYMBOL_REF, a pseudo-register, LR or CTR.  */
2233
2234 int
2235 call_operand (rtx op, enum machine_mode mode)
2236 {
2237   if (mode != VOIDmode && GET_MODE (op) != mode)
2238     return 0;
2239
2240   return (GET_CODE (op) == SYMBOL_REF
2241           || (GET_CODE (op) == REG
2242               && (REGNO (op) == LINK_REGISTER_REGNUM
2243                   || REGNO (op) == COUNT_REGISTER_REGNUM
2244                   || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2245 }
2246
2247 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2248    this file.  */
2249
2250 int
2251 current_file_function_operand (rtx op,
2252                               enum machine_mode mode ATTRIBUTE_UNUSED)
2253 {
2254   return (GET_CODE (op) == SYMBOL_REF
2255           && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2256           && (SYMBOL_REF_LOCAL_P (op)
2257               || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2258 }
2259
2260 /* Return 1 if this operand is a valid input for a move insn.  */
2261
2262 int
2263 input_operand (rtx op, enum machine_mode mode)
2264 {
2265   /* Memory is always valid.  */
2266   if (memory_operand (op, mode))
2267     return 1;
2268
2269   /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary.  */
2270   if (GET_CODE (op) == CONSTANT_P_RTX)
2271     return 1;
2272
2273   /* For floating-point, easy constants are valid.  */
2274   if (GET_MODE_CLASS (mode) == MODE_FLOAT
2275       && CONSTANT_P (op)
2276       && easy_fp_constant (op, mode))
2277     return 1;
2278
2279   /* Allow any integer constant.  */
2280   if (GET_MODE_CLASS (mode) == MODE_INT
2281       && (GET_CODE (op) == CONST_INT
2282           || GET_CODE (op) == CONST_DOUBLE))
2283     return 1;
2284
2285   /* Allow easy vector constants.  */
2286   if (GET_CODE (op) == CONST_VECTOR
2287       && easy_vector_constant (op, mode))
2288     return 1;
2289
2290   /* For floating-point or multi-word mode, the only remaining valid type
2291      is a register.  */
2292   if (GET_MODE_CLASS (mode) == MODE_FLOAT
2293       || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2294     return register_operand (op, mode);
2295
2296   /* The only cases left are integral modes one word or smaller (we
2297      do not get called for MODE_CC values).  These can be in any
2298      register.  */
2299   if (register_operand (op, mode))
2300     return 1;
2301
2302   /* A SYMBOL_REF referring to the TOC is valid.  */
2303   if (legitimate_constant_pool_address_p (op))
2304     return 1;
2305
2306   /* A constant pool expression (relative to the TOC) is valid */
2307   if (toc_relative_expr_p (op))
2308     return 1;
2309
2310   /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2311      to be valid.  */
2312   if (DEFAULT_ABI == ABI_V4
2313       && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2314       && small_data_operand (op, Pmode))
2315     return 1;
2316
2317   return 0;
2318 }
2319
2320 /* Return 1 for an operand in small memory on V.4/eabi.  */
2321
2322 int
2323 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2324                     enum machine_mode mode ATTRIBUTE_UNUSED)
2325 {
2326 #if TARGET_ELF
2327   rtx sym_ref;
2328
2329   if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2330     return 0;
2331
2332   if (DEFAULT_ABI != ABI_V4)
2333     return 0;
2334
2335   if (GET_CODE (op) == SYMBOL_REF)
2336     sym_ref = op;
2337
2338   else if (GET_CODE (op) != CONST
2339            || GET_CODE (XEXP (op, 0)) != PLUS
2340            || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2341            || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2342     return 0;
2343
2344   else
2345     {
2346       rtx sum = XEXP (op, 0);
2347       HOST_WIDE_INT summand;
2348
2349       /* We have to be careful here, because it is the referenced address
2350         that must be 32k from _SDA_BASE_, not just the symbol.  */
2351       summand = INTVAL (XEXP (sum, 1));
2352       if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2353        return 0;
2354
2355       sym_ref = XEXP (sum, 0);
2356     }
2357
2358   return SYMBOL_REF_SMALL_P (sym_ref);
2359 #else
2360   return 0;
2361 #endif
2362 }
2363
2364 /* Return true, if operand is a memory operand and has a
2365    displacement divisible by 4.  */
2366
2367 int
2368 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2369 {
2370   rtx addr;
2371   int off = 0;
2372
2373   if (!memory_operand (op, mode))
2374     return 0;
2375
2376   addr = XEXP (op, 0);
2377   if (GET_CODE (addr) == PLUS
2378       && GET_CODE (XEXP (addr, 0)) == REG
2379       && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2380     off = INTVAL (XEXP (addr, 1));
2381
2382   return (off % 4) == 0;
2383 }
2384
2385 /* Return true if either operand is a general purpose register.  */
2386
2387 bool
2388 gpr_or_gpr_p (rtx op0, rtx op1)
2389 {
2390   return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2391           || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2392 }
2393
2394 \f
2395 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address.  */
2396
2397 static int
2398 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2399 {
2400   switch (GET_CODE(op))
2401     {
2402     case SYMBOL_REF:
2403       if (RS6000_SYMBOL_REF_TLS_P (op))
2404         return 0;
2405       else if (CONSTANT_POOL_ADDRESS_P (op))
2406         {
2407           if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2408             {
2409               *have_sym = 1;
2410               return 1;
2411             }
2412           else
2413             return 0;
2414         }
2415       else if (! strcmp (XSTR (op, 0), toc_label_name))
2416         {
2417           *have_toc = 1;
2418           return 1;
2419         }
2420       else
2421         return 0;
2422     case PLUS:
2423     case MINUS:
2424       return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2425               && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2426     case CONST:
2427       return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2428     case CONST_INT:
2429       return 1;
2430     default:
2431       return 0;
2432     }
2433 }
2434
2435 static bool
2436 constant_pool_expr_p (rtx op)
2437 {
2438   int have_sym = 0;
2439   int have_toc = 0;
2440   return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2441 }
2442
2443 static bool
2444 toc_relative_expr_p (rtx op)
2445 {
2446   int have_sym = 0;
2447   int have_toc = 0;
2448   return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2449 }
2450
2451 /* SPE offset addressing is limited to 5-bits worth of double words.  */
2452 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2453
2454 bool
2455 legitimate_constant_pool_address_p (rtx x)
2456 {
2457   return (TARGET_TOC
2458           && GET_CODE (x) == PLUS
2459           && GET_CODE (XEXP (x, 0)) == REG
2460           && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2461           && constant_pool_expr_p (XEXP (x, 1)));
2462 }
2463
2464 static bool
2465 legitimate_small_data_p (enum machine_mode mode, rtx x)
2466 {
2467   return (DEFAULT_ABI == ABI_V4
2468           && !flag_pic && !TARGET_TOC
2469           && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2470           && small_data_operand (x, mode));
2471 }
2472
2473 static bool
2474 legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2475 {
2476   unsigned HOST_WIDE_INT offset, extra;
2477
2478   if (GET_CODE (x) != PLUS)
2479     return false;
2480   if (GET_CODE (XEXP (x, 0)) != REG)
2481     return false;
2482   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2483     return false;
2484   if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2485     return false;
2486
2487   offset = INTVAL (XEXP (x, 1));
2488   extra = 0;
2489   switch (mode)
2490     {
2491     case V16QImode:
2492     case V8HImode:
2493     case V4SFmode:
2494     case V4SImode:
2495       /* AltiVec vector modes.  Only reg+reg addressing is valid here,
2496          which leaves the only valid constant offset of zero, which by
2497          canonicalization rules is also invalid.  */
2498       return false;
2499
2500     case V4HImode:
2501     case V2SImode:
2502     case V1DImode:
2503     case V2SFmode:
2504       /* SPE vector modes.  */
2505       return SPE_CONST_OFFSET_OK (offset);
2506
2507     case DFmode:
2508     case DImode:
2509       if (mode == DFmode || !TARGET_POWERPC64)
2510         extra = 4;
2511       else if (offset & 3)
2512         return false;
2513       break;
2514
2515     case TFmode:
2516     case TImode:
2517       if (mode == TFmode || !TARGET_POWERPC64)
2518         extra = 12;
2519       else if (offset & 3)
2520         return false;
2521       else
2522         extra = 8;
2523       break;
2524
2525     default:
2526       break;
2527     }
2528
2529   return (offset + extra >= offset) && (offset + extra + 0x8000 < 0x10000);
2530 }
2531
2532 static bool
2533 legitimate_indexed_address_p (rtx x, int strict)
2534 {
2535   rtx op0, op1;
2536
2537   if (GET_CODE (x) != PLUS)
2538     return false;
2539   op0 = XEXP (x, 0);
2540   op1 = XEXP (x, 1);
2541
2542   if (!REG_P (op0) || !REG_P (op1))
2543     return false;
2544
2545   return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2546            && INT_REG_OK_FOR_INDEX_P (op1, strict))
2547           || (INT_REG_OK_FOR_BASE_P (op1, strict)
2548               && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2549 }
2550
2551 static inline bool
2552 legitimate_indirect_address_p (rtx x, int strict)
2553 {
2554   return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2555 }
2556
2557 static bool
2558 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2559 {
2560     if (!TARGET_MACHO || !flag_pic
2561         || mode != SImode || GET_CODE(x) != MEM)
2562       return false;
2563     x = XEXP (x, 0);
2564
2565   if (GET_CODE (x) != LO_SUM)
2566     return false;
2567   if (GET_CODE (XEXP (x, 0)) != REG)
2568     return false;
2569   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2570     return false;
2571   x = XEXP (x, 1);
2572
2573   return CONSTANT_P (x);
2574 }
2575
2576 static bool
2577 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2578 {
2579   if (GET_CODE (x) != LO_SUM)
2580     return false;
2581   if (GET_CODE (XEXP (x, 0)) != REG)
2582     return false;
2583   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2584     return false;
2585   x = XEXP (x, 1);
2586
2587   if (TARGET_ELF || TARGET_MACHO)
2588     {
2589       if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2590         return false;
2591       if (TARGET_TOC)
2592         return false;
2593       if (GET_MODE_NUNITS (mode) != 1)
2594         return false;
2595       if (GET_MODE_BITSIZE (mode) > 32
2596           && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))
2597         return false;
2598
2599       return CONSTANT_P (x);
2600     }
2601
2602   return false;
2603 }
2604
2605
2606 /* Try machine-dependent ways of modifying an illegitimate address
2607    to be legitimate.  If we find one, return the new, valid address.
2608    This is used from only one place: `memory_address' in explow.c.
2609
2610    OLDX is the address as it was before break_out_memory_refs was
2611    called.  In some cases it is useful to look at this to decide what
2612    needs to be done.
2613
2614    MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2615
2616    It is always safe for this function to do nothing.  It exists to
2617    recognize opportunities to optimize the output.
2618
2619    On RS/6000, first check for the sum of a register with a constant
2620    integer that is out of range.  If so, generate code to add the
2621    constant with the low-order 16 bits masked to the register and force
2622    this result into another register (this can be done with `cau').
2623    Then generate an address of REG+(CONST&0xffff), allowing for the
2624    possibility of bit 16 being a one.
2625
2626    Then check for the sum of a register and something not constant, try to
2627    load the other things into a register and return the sum.  */
2628
2629 rtx
2630 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2631                            enum machine_mode mode)
2632 {
2633   if (GET_CODE (x) == SYMBOL_REF)
2634     {
2635       enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2636       if (model != 0)
2637         return rs6000_legitimize_tls_address (x, model);
2638     }
2639
2640   if (GET_CODE (x) == PLUS
2641       && GET_CODE (XEXP (x, 0)) == REG
2642       && GET_CODE (XEXP (x, 1)) == CONST_INT
2643       && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2644     {
2645       HOST_WIDE_INT high_int, low_int;
2646       rtx sum;
2647       low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2648       high_int = INTVAL (XEXP (x, 1)) - low_int;
2649       sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2650                                          GEN_INT (high_int)), 0);
2651       return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2652     }
2653   else if (GET_CODE (x) == PLUS
2654            && GET_CODE (XEXP (x, 0)) == REG
2655            && GET_CODE (XEXP (x, 1)) != CONST_INT
2656            && GET_MODE_NUNITS (mode) == 1
2657            && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2658                || TARGET_POWERPC64
2659                || (mode != DFmode && mode != TFmode))
2660            && (TARGET_POWERPC64 || mode != DImode)
2661            && mode != TImode)
2662     {
2663       return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2664                            force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2665     }
2666   else if (ALTIVEC_VECTOR_MODE (mode))
2667     {
2668       rtx reg;
2669
2670       /* Make sure both operands are registers.  */
2671       if (GET_CODE (x) == PLUS)
2672         return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2673                              force_reg (Pmode, XEXP (x, 1)));
2674
2675       reg = force_reg (Pmode, x);
2676       return reg;
2677     }
2678   else if (SPE_VECTOR_MODE (mode))
2679     {
2680       /* We accept [reg + reg] and [reg + OFFSET].  */
2681
2682       if (GET_CODE (x) == PLUS)
2683       {
2684         rtx op1 = XEXP (x, 0);
2685         rtx op2 = XEXP (x, 1);
2686
2687         op1 = force_reg (Pmode, op1);
2688
2689         if (GET_CODE (op2) != REG
2690             && (GET_CODE (op2) != CONST_INT
2691                 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2692           op2 = force_reg (Pmode, op2);
2693
2694         return gen_rtx_PLUS (Pmode, op1, op2);
2695       }
2696
2697       return force_reg (Pmode, x);
2698     }
2699   else if (TARGET_ELF
2700            && TARGET_32BIT
2701            && TARGET_NO_TOC
2702            && ! flag_pic
2703            && GET_CODE (x) != CONST_INT
2704            && GET_CODE (x) != CONST_DOUBLE
2705            && CONSTANT_P (x)
2706            && GET_MODE_NUNITS (mode) == 1
2707            && (GET_MODE_BITSIZE (mode) <= 32
2708                || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2709     {
2710       rtx reg = gen_reg_rtx (Pmode);
2711       emit_insn (gen_elf_high (reg, x));
2712       return gen_rtx_LO_SUM (Pmode, reg, x);
2713     }
2714   else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2715            && ! flag_pic
2716 #if TARGET_MACHO
2717            && ! MACHO_DYNAMIC_NO_PIC_P
2718 #endif
2719            && GET_CODE (x) != CONST_INT
2720            && GET_CODE (x) != CONST_DOUBLE
2721            && CONSTANT_P (x)
2722            && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2723            && mode != DImode
2724            && mode != TImode)
2725     {
2726       rtx reg = gen_reg_rtx (Pmode);
2727       emit_insn (gen_macho_high (reg, x));
2728       return gen_rtx_LO_SUM (Pmode, reg, x);
2729     }
2730   else if (TARGET_TOC
2731            && constant_pool_expr_p (x)
2732            && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2733     {
2734       return create_TOC_reference (x);
2735     }
2736   else
2737     return NULL_RTX;
2738 }
2739
2740 /* Construct the SYMBOL_REF for the tls_get_addr function.  */
2741
2742 static GTY(()) rtx rs6000_tls_symbol;
2743 static rtx
2744 rs6000_tls_get_addr (void)
2745 {
2746   if (!rs6000_tls_symbol)
2747     rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2748
2749   return rs6000_tls_symbol;
2750 }
2751
2752 /* Construct the SYMBOL_REF for TLS GOT references.  */
2753
2754 static GTY(()) rtx rs6000_got_symbol;
2755 static rtx
2756 rs6000_got_sym (void)
2757 {
2758   if (!rs6000_got_symbol)
2759     {
2760       rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2761       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2762       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2763     }
2764
2765   return rs6000_got_symbol;
2766 }
2767
2768 /* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
2769    this (thread-local) address.  */
2770
2771 static rtx
2772 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2773 {
2774   rtx dest, insn;
2775
2776   dest = gen_reg_rtx (Pmode);
2777   if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2778     {
2779       rtx tlsreg;
2780
2781       if (TARGET_64BIT)
2782         {
2783           tlsreg = gen_rtx_REG (Pmode, 13);
2784           insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2785         }
2786       else
2787         {
2788           tlsreg = gen_rtx_REG (Pmode, 2);
2789           insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2790         }
2791       emit_insn (insn);
2792     }
2793   else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2794     {
2795       rtx tlsreg, tmp;
2796
2797       tmp = gen_reg_rtx (Pmode);
2798       if (TARGET_64BIT)
2799         {
2800           tlsreg = gen_rtx_REG (Pmode, 13);
2801           insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2802         }
2803       else
2804         {
2805           tlsreg = gen_rtx_REG (Pmode, 2);
2806           insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2807         }
2808       emit_insn (insn);
2809       if (TARGET_64BIT)
2810         insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2811       else
2812         insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2813       emit_insn (insn);
2814     }
2815   else
2816     {
2817       rtx r3, got, tga, tmp1, tmp2, eqv;
2818
2819       if (TARGET_64BIT)
2820         got = gen_rtx_REG (Pmode, TOC_REGISTER);
2821       else
2822         {
2823           if (flag_pic == 1)
2824             got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2825           else
2826             {
2827               rtx gsym = rs6000_got_sym ();
2828               got = gen_reg_rtx (Pmode);
2829               if (flag_pic == 0)
2830                 rs6000_emit_move (got, gsym, Pmode);
2831               else
2832                 {
2833                   char buf[30];
2834                   static int tls_got_labelno = 0;
2835                   rtx tempLR, lab, tmp3, mem;
2836                   rtx first, last;
2837
2838                   ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2839                   lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2840                   tempLR = gen_reg_rtx (Pmode);
2841                   tmp1 = gen_reg_rtx (Pmode);
2842                   tmp2 = gen_reg_rtx (Pmode);
2843                   tmp3 = gen_reg_rtx (Pmode);
2844                   mem = gen_rtx_MEM (Pmode, tmp1);
2845                   RTX_UNCHANGING_P (mem) = 1;
2846
2847                   first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2848                                                              gsym));
2849                   emit_move_insn (tmp1, tempLR);
2850                   emit_move_insn (tmp2, mem);
2851                   emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2852                   last = emit_move_insn (got, tmp3);
2853                   REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2854                                                         REG_NOTES (last));
2855                   REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2856                                                          REG_NOTES (first));
2857                   REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2858                                                         REG_NOTES (last));
2859                 }
2860             }
2861         }
2862
2863       if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2864         {
2865           r3 = gen_rtx_REG (Pmode, 3);
2866           if (TARGET_64BIT)
2867             insn = gen_tls_gd_64 (r3, got, addr);
2868           else
2869             insn = gen_tls_gd_32 (r3, got, addr);
2870           start_sequence ();
2871           emit_insn (insn);
2872           tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2873           insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2874           insn = emit_call_insn (insn);
2875           CONST_OR_PURE_CALL_P (insn) = 1;
2876           use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2877           insn = get_insns ();
2878           end_sequence ();
2879           emit_libcall_block (insn, dest, r3, addr);
2880         }
2881       else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2882         {
2883           r3 = gen_rtx_REG (Pmode, 3);
2884           if (TARGET_64BIT)
2885             insn = gen_tls_ld_64 (r3, got);
2886           else
2887             insn = gen_tls_ld_32 (r3, got);
2888           start_sequence ();
2889           emit_insn (insn);
2890           tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2891           insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2892           insn = emit_call_insn (insn);
2893           CONST_OR_PURE_CALL_P (insn) = 1;
2894           use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2895           insn = get_insns ();
2896           end_sequence ();
2897           tmp1 = gen_reg_rtx (Pmode);
2898           eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2899                                 UNSPEC_TLSLD);
2900           emit_libcall_block (insn, tmp1, r3, eqv);
2901           if (rs6000_tls_size == 16)
2902             {
2903               if (TARGET_64BIT)
2904                 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2905               else
2906                 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2907             }
2908           else if (rs6000_tls_size == 32)
2909             {
2910               tmp2 = gen_reg_rtx (Pmode);
2911               if (TARGET_64BIT)
2912                 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2913               else
2914                 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2915               emit_insn (insn);
2916               if (TARGET_64BIT)
2917                 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2918               else
2919                 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2920             }
2921           else
2922             {
2923               tmp2 = gen_reg_rtx (Pmode);
2924               if (TARGET_64BIT)
2925                 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2926               else
2927                 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2928               emit_insn (insn);
2929               insn = gen_rtx_SET (Pmode, dest,
2930                                   gen_rtx_PLUS (Pmode, tmp2, tmp1));
2931             }
2932           emit_insn (insn);
2933         }
2934       else
2935         {
2936           /* IE, or 64 bit offset LE.  */
2937           tmp2 = gen_reg_rtx (Pmode);
2938           if (TARGET_64BIT)
2939             insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2940           else
2941             insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2942           emit_insn (insn);
2943           if (TARGET_64BIT)
2944             insn = gen_tls_tls_64 (dest, tmp2, addr);
2945           else
2946             insn = gen_tls_tls_32 (dest, tmp2, addr);
2947           emit_insn (insn);
2948         }
2949     }
2950
2951   return dest;
2952 }
2953
2954 /* Return 1 if X is a SYMBOL_REF for a TLS symbol.  This is used in
2955    instruction definitions.  */
2956
2957 int
2958 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2959 {
2960   return RS6000_SYMBOL_REF_TLS_P (x);
2961 }
2962
2963 /* Return 1 if X contains a thread-local symbol.  */
2964
2965 bool
2966 rs6000_tls_referenced_p (rtx x)
2967 {
2968   if (! TARGET_HAVE_TLS)
2969     return false;
2970
2971   return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2972 }
2973
2974 /* Return 1 if *X is a thread-local symbol.  This is the same as
2975    rs6000_tls_symbol_ref except for the type of the unused argument.  */
2976
2977 static inline int
2978 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2979 {
2980   return RS6000_SYMBOL_REF_TLS_P (*x);
2981 }
2982
2983 /* The convention appears to be to define this wherever it is used.
2984    With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2985    is now used here.  */
2986 #ifndef REG_MODE_OK_FOR_BASE_P
2987 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2988 #endif
2989
2990 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS.  Returns a value to
2991    replace the input X, or the original X if no replacement is called for.
2992    The output parameter *WIN is 1 if the calling macro should goto WIN,
2993    0 if it should not.
2994
2995    For RS/6000, we wish to handle large displacements off a base
2996    register by splitting the addend across an addiu/addis and the mem insn.
2997    This cuts number of extra insns needed from 3 to 1.
2998
2999    On Darwin, we use this to generate code for floating point constants.
3000    A movsf_low is generated so we wind up with 2 instructions rather than 3.
3001    The Darwin code is inside #if TARGET_MACHO because only then is
3002    machopic_function_base_name() defined.  */
3003 rtx
3004 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3005         int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
3006 {
3007   /* We must recognize output that we have already generated ourselves.  */
3008   if (GET_CODE (x) == PLUS
3009       && GET_CODE (XEXP (x, 0)) == PLUS
3010       && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3011       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3012       && GET_CODE (XEXP (x, 1)) == CONST_INT)
3013     {
3014       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3015                    BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3016                    opnum, (enum reload_type)type);
3017       *win = 1;
3018       return x;
3019     }
3020
3021 #if TARGET_MACHO
3022   if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3023       && GET_CODE (x) == LO_SUM
3024       && GET_CODE (XEXP (x, 0)) == PLUS
3025       && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3026       && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3027       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3028       && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3029       && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3030       && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3031       && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3032     {
3033       /* Result of previous invocation of this function on Darwin
3034          floating point constant.  */
3035       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3036                 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3037                 opnum, (enum reload_type)type);
3038       *win = 1;
3039       return x;
3040     }
3041 #endif
3042   if (GET_CODE (x) == PLUS
3043       && GET_CODE (XEXP (x, 0)) == REG
3044       && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3045       && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3046       && GET_CODE (XEXP (x, 1)) == CONST_INT
3047       && !SPE_VECTOR_MODE (mode)
3048       && !ALTIVEC_VECTOR_MODE (mode))
3049     {
3050       HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3051       HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3052       HOST_WIDE_INT high
3053         = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3054
3055       /* Check for 32-bit overflow.  */
3056       if (high + low != val)
3057         {
3058           *win = 0;
3059           return x;
3060         }
3061
3062       /* Reload the high part into a base reg; leave the low part
3063          in the mem directly.  */
3064
3065       x = gen_rtx_PLUS (GET_MODE (x),
3066                         gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3067                                       GEN_INT (high)),
3068                         GEN_INT (low));
3069
3070       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3071                    BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3072                    opnum, (enum reload_type)type);
3073       *win = 1;
3074       return x;
3075     }
3076 #if TARGET_MACHO
3077   if (GET_CODE (x) == SYMBOL_REF
3078       && DEFAULT_ABI == ABI_DARWIN
3079       && !ALTIVEC_VECTOR_MODE (mode)
3080       && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3081       /* Don't do this for TFmode, since the result isn't offsettable.  */
3082       && mode != TFmode)
3083     {
3084       if (flag_pic)
3085         {
3086           rtx offset = gen_rtx_CONST (Pmode,
3087                          gen_rtx_MINUS (Pmode, x,
3088                            gen_rtx_SYMBOL_REF (Pmode,
3089                              machopic_function_base_name ())));
3090           x = gen_rtx_LO_SUM (GET_MODE (x),
3091                 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3092                   gen_rtx_HIGH (Pmode, offset)), offset);
3093         }
3094       else
3095         x = gen_rtx_LO_SUM (GET_MODE (x),
3096               gen_rtx_HIGH (Pmode, x), x);
3097
3098       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3099                    BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3100                    opnum, (enum reload_type)type);
3101       *win = 1;
3102       return x;
3103     }
3104 #endif
3105   if (TARGET_TOC
3106       && constant_pool_expr_p (x)
3107       && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3108     {
3109       (x) = create_TOC_reference (x);
3110       *win = 1;
3111       return x;
3112     }
3113   *win = 0;
3114   return x;
3115 }
3116
3117 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3118    that is a valid memory address for an instruction.
3119    The MODE argument is the machine mode for the MEM expression
3120    that wants to use this address.
3121
3122    On the RS/6000, there are four valid address: a SYMBOL_REF that
3123    refers to a constant pool entry of an address (or the sum of it
3124    plus a constant), a short (16-bit signed) constant plus a register,
3125    the sum of two registers, or a register indirect, possibly with an
3126    auto-increment.  For DFmode and DImode with a constant plus register,
3127    we must ensure that both words are addressable or PowerPC64 with offset
3128    word aligned.
3129
3130    For modes spanning multiple registers (DFmode in 32-bit GPRs,
3131    32-bit DImode, TImode), indexed addressing cannot be used because
3132    adjacent memory cells are accessed by adding word-sized offsets
3133    during assembly output.  */
3134 int
3135 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3136 {
3137   if (RS6000_SYMBOL_REF_TLS_P (x))
3138     return 0;
3139   if (legitimate_indirect_address_p (x, reg_ok_strict))
3140     return 1;
3141   if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3142       && !ALTIVEC_VECTOR_MODE (mode)
3143       && !SPE_VECTOR_MODE (mode)
3144       && TARGET_UPDATE
3145       && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3146     return 1;
3147   if (legitimate_small_data_p (mode, x))
3148     return 1;
3149   if (legitimate_constant_pool_address_p (x))
3150     return 1;
3151   /* If not REG_OK_STRICT (before reload) let pass any stack offset.  */
3152   if (! reg_ok_strict
3153       && GET_CODE (x) == PLUS
3154       && GET_CODE (XEXP (x, 0)) == REG
3155       && XEXP (x, 0) == virtual_stack_vars_rtx
3156       && GET_CODE (XEXP (x, 1)) == CONST_INT)
3157     return 1;
3158   if (legitimate_offset_address_p (mode, x, reg_ok_strict))
3159     return 1;
3160   if (mode != TImode
3161       && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3162           || TARGET_POWERPC64
3163           || (mode != DFmode && mode != TFmode))
3164       && (TARGET_POWERPC64 || mode != DImode)
3165       && legitimate_indexed_address_p (x, reg_ok_strict))
3166     return 1;
3167   if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3168     return 1;
3169   return 0;
3170 }
3171
3172 /* Go to LABEL if ADDR (a legitimate address expression)
3173    has an effect that depends on the machine mode it is used for.
3174
3175    On the RS/6000 this is true of all integral offsets (since AltiVec
3176    modes don't allow them) or is a pre-increment or decrement.
3177
3178    ??? Except that due to conceptual problems in offsettable_address_p
3179    we can't really report the problems of integral offsets.  So leave
3180    this assuming that the adjustable offset must be valid for the
3181    sub-words of a TFmode operand, which is what we had before.  */
3182
3183 bool
3184 rs6000_mode_dependent_address (rtx addr)
3185 {
3186   switch (GET_CODE (addr))
3187     {
3188     case PLUS:
3189       if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3190         {
3191           unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3192           return val + 12 + 0x8000 >= 0x10000;
3193         }
3194       break;
3195
3196     case LO_SUM:
3197       return true;
3198
3199     case PRE_INC:
3200     case PRE_DEC:
3201       return TARGET_UPDATE;
3202
3203     default:
3204       break;
3205     }
3206
3207   return false;
3208 }
3209 \f
3210 /* Try to output insns to set TARGET equal to the constant C if it can
3211    be done in less than N insns.  Do all computations in MODE.
3212    Returns the place where the output has been placed if it can be
3213    done and the insns have been emitted.  If it would take more than N
3214    insns, zero is returned and no insns and emitted.  */
3215
3216 rtx
3217 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3218                        rtx source, int n ATTRIBUTE_UNUSED)
3219 {
3220   rtx result, insn, set;
3221   HOST_WIDE_INT c0, c1;
3222
3223   if (mode == QImode || mode == HImode)
3224     {
3225       if (dest == NULL)
3226         dest = gen_reg_rtx (mode);
3227       emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3228       return dest;
3229     }
3230   else if (mode == SImode)
3231     {
3232       result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3233
3234       emit_insn (gen_rtx_SET (VOIDmode, result,
3235                               GEN_INT (INTVAL (source)
3236                                        & (~ (HOST_WIDE_INT) 0xffff))));
3237       emit_insn (gen_rtx_SET (VOIDmode, dest,
3238                               gen_rtx_IOR (SImode, result,
3239                                            GEN_INT (INTVAL (source) & 0xffff))));
3240       result = dest;
3241     }
3242   else if (mode == DImode)
3243     {
3244       if (GET_CODE (source) == CONST_INT)
3245         {
3246           c0 = INTVAL (source);
3247           c1 = -(c0 < 0);
3248         }
3249       else if (GET_CODE (source) == CONST_DOUBLE)
3250         {
3251 #if HOST_BITS_PER_WIDE_INT >= 64
3252           c0 = CONST_DOUBLE_LOW (source);
3253           c1 = -(c0 < 0);
3254 #else
3255           c0 = CONST_DOUBLE_LOW (source);
3256           c1 = CONST_DOUBLE_HIGH (source);
3257 #endif
3258         }
3259       else
3260         abort ();
3261
3262       result = rs6000_emit_set_long_const (dest, c0, c1);
3263     }
3264   else
3265     abort ();
3266
3267   insn = get_last_insn ();
3268   set = single_set (insn);
3269   if (! CONSTANT_P (SET_SRC (set)))
3270     set_unique_reg_note (insn, REG_EQUAL, source);
3271
3272   return result;
3273 }
3274
3275 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3276    fall back to a straight forward decomposition.  We do this to avoid
3277    exponential run times encountered when looking for longer sequences
3278    with rs6000_emit_set_const.  */
3279 static rtx
3280 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3281 {
3282   if (!TARGET_POWERPC64)
3283     {
3284       rtx operand1, operand2;
3285
3286       operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3287                                         DImode);
3288       operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3289                                         DImode);
3290       emit_move_insn (operand1, GEN_INT (c1));
3291       emit_move_insn (operand2, GEN_INT (c2));
3292     }
3293   else
3294     {
3295       HOST_WIDE_INT ud1, ud2, ud3, ud4;
3296
3297       ud1 = c1 & 0xffff;
3298       ud2 = (c1 & 0xffff0000) >> 16;
3299 #if HOST_BITS_PER_WIDE_INT >= 64
3300       c2 = c1 >> 32;
3301 #endif
3302       ud3 = c2 & 0xffff;
3303       ud4 = (c2 & 0xffff0000) >> 16;
3304
3305       if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3306           || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3307         {
3308           if (ud1 & 0x8000)
3309             emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) -  0x8000)));
3310           else
3311             emit_move_insn (dest, GEN_INT (ud1));
3312         }
3313
3314       else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3315                || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3316         {
3317           if (ud2 & 0x8000)
3318             emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3319                                            - 0x80000000));
3320           else
3321             emit_move_insn (dest, GEN_INT (ud2 << 16));
3322           if (ud1 != 0)
3323             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3324         }
3325       else if ((ud4 == 0xffff && (ud3 & 0x8000))
3326                || (ud4 == 0 && ! (ud3 & 0x8000)))
3327         {
3328           if (ud3 & 0x8000)
3329             emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3330                                            - 0x80000000));
3331           else
3332             emit_move_insn (dest, GEN_INT (ud3 << 16));
3333
3334           if (ud2 != 0)
3335             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3336           emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3337           if (ud1 != 0)
3338             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3339         }
3340       else
3341         {
3342           if (ud4 & 0x8000)
3343             emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3344                                            - 0x80000000));
3345           else
3346             emit_move_insn (dest, GEN_INT (ud4 << 16));
3347
3348           if (ud3 != 0)
3349             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3350
3351           emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3352           if (ud2 != 0)
3353             emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3354                                                GEN_INT (ud2 << 16)));
3355           if (ud1 != 0)
3356             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3357         }
3358     }
3359   return dest;
3360 }
3361
3362 /* Emit a move from SOURCE to DEST in mode MODE.  */
3363 void
3364 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3365 {
3366   rtx operands[2];
3367   operands[0] = dest;
3368   operands[1] = source;
3369
3370   /* Sanity checks.  Check that we get CONST_DOUBLE only when we should.  */
3371   if (GET_CODE (operands[1]) == CONST_DOUBLE
3372       && ! FLOAT_MODE_P (mode)
3373       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3374     {
3375       /* FIXME.  This should never happen.  */
3376       /* Since it seems that it does, do the safe thing and convert
3377          to a CONST_INT.  */
3378       operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3379     }
3380   if (GET_CODE (operands[1]) == CONST_DOUBLE
3381       && ! FLOAT_MODE_P (mode)
3382       && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3383            && CONST_DOUBLE_LOW (operands[1]) >= 0)
3384           || (CONST_DOUBLE_HIGH (operands[1]) == -1
3385               && CONST_DOUBLE_LOW (operands[1]) < 0)))
3386     abort ();
3387
3388   /* Check if GCC is setting up a block move that will end up using FP
3389      registers as temporaries.  We must make sure this is acceptable.  */
3390   if (GET_CODE (operands[0]) == MEM
3391       && GET_CODE (operands[1]) == MEM
3392       && mode == DImode
3393       && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3394           || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3395       && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3396                                             ? 32 : MEM_ALIGN (operands[0])))
3397             || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3398                                                ? 32
3399                                                : MEM_ALIGN (operands[1]))))
3400       && ! MEM_VOLATILE_P (operands [0])
3401       && ! MEM_VOLATILE_P (operands [1]))
3402     {
3403       emit_move_insn (adjust_address (operands[0], SImode, 0),
3404                       adjust_address (operands[1], SImode, 0));
3405       emit_move_insn (adjust_address (operands[0], SImode, 4),
3406                       adjust_address (operands[1], SImode, 4));
3407       return;
3408     }
3409
3410   if (!no_new_pseudos)
3411     {
3412       if (GET_CODE (operands[1]) == MEM && optimize > 0
3413           && (mode == QImode || mode == HImode || mode == SImode)
3414           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
3415         {
3416           rtx reg = gen_reg_rtx (word_mode);
3417
3418           emit_insn (gen_rtx_SET (word_mode, reg,
3419                                   gen_rtx_ZERO_EXTEND (word_mode,
3420                                                        operands[1])));
3421           operands[1] = gen_lowpart (mode, reg);
3422         }
3423       if (GET_CODE (operands[0]) != REG)
3424         operands[1] = force_reg (mode, operands[1]);
3425     }
3426
3427   if (mode == SFmode && ! TARGET_POWERPC
3428       && TARGET_HARD_FLOAT && TARGET_FPRS
3429       && GET_CODE (operands[0]) == MEM)
3430     {
3431       int regnum;
3432
3433       if (reload_in_progress || reload_completed)
3434         regnum = true_regnum (operands[1]);
3435       else if (GET_CODE (operands[1]) == REG)
3436         regnum = REGNO (operands[1]);
3437       else
3438         regnum = -1;
3439
3440       /* If operands[1] is a register, on POWER it may have
3441          double-precision data in it, so truncate it to single
3442          precision.  */
3443       if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3444         {
3445           rtx newreg;
3446           newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3447           emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3448           operands[1] = newreg;
3449         }
3450     }
3451
3452   /* Recognize the case where operand[1] is a reference to thread-local
3453      data and load its address to a register.  */
3454   if (GET_CODE (operands[1]) == SYMBOL_REF)
3455     {
3456       enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3457       if (model != 0)
3458         operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3459     }
3460
3461   /* Handle the case where reload calls us with an invalid address.  */
3462   if (reload_in_progress && mode == Pmode
3463       && (! general_operand (operands[1], mode)
3464           || ! nonimmediate_operand (operands[0], mode)))
3465     goto emit_set;
3466
3467   /* Handle the case of CONSTANT_P_RTX.  */
3468   if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
3469     goto emit_set;
3470
3471   /* 128-bit constant floating-point values on Darwin should really be
3472      loaded as two parts.  */
3473   if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3474       && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3475       && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3476     {
3477       /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3478          know how to get a DFmode SUBREG of a TFmode.  */
3479       rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3480                         simplify_gen_subreg (DImode, operands[1], mode, 0),
3481                         DImode);
3482       rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3483                                              GET_MODE_SIZE (DImode)),
3484                         simplify_gen_subreg (DImode, operands[1], mode,
3485                                              GET_MODE_SIZE (DImode)),
3486                         DImode);
3487       return;
3488     }
3489
3490   /* FIXME:  In the long term, this switch statement should go away
3491      and be replaced by a sequence of tests based on things like
3492      mode == Pmode.  */
3493   switch (mode)
3494     {
3495     case HImode:
3496     case QImode:
3497       if (CONSTANT_P (operands[1])
3498           && GET_CODE (operands[1]) != CONST_INT)
3499         operands[1] = force_const_mem (mode, operands[1]);
3500       break;
3501
3502     case TFmode:
3503     case DFmode:
3504     case SFmode:
3505       if (CONSTANT_P (operands[1])
3506           && ! easy_fp_constant (operands[1], mode))
3507         operands[1] = force_const_mem (mode, operands[1]);
3508       break;
3509
3510     case V16QImode:
3511     case V8HImode:
3512     case V4SFmode:
3513     case V4SImode:
3514     case V4HImode:
3515     case V2SFmode:
3516     case V2SImode:
3517     case V1DImode:
3518       if (CONSTANT_P (operands[1])
3519           && !easy_vector_constant (operands[1], mode))
3520         operands[1] = force_const_mem (mode, operands[1]);
3521       break;
3522
3523     case SImode:
3524     case DImode:
3525       /* Use default pattern for address of ELF small data */
3526       if (TARGET_ELF
3527           && mode == Pmode
3528           && DEFAULT_ABI == ABI_V4
3529           && (GET_CODE (operands[1]) == SYMBOL_REF
3530               || GET_CODE (operands[1]) == CONST)
3531           && small_data_operand (operands[1], mode))
3532         {
3533           emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3534           return;
3535         }
3536
3537       if (DEFAULT_ABI == ABI_V4
3538           && mode == Pmode && mode == SImode
3539           && flag_pic == 1 && got_operand (operands[1], mode))
3540         {
3541           emit_insn (gen_movsi_got (operands[0], operands[1]));
3542           return;
3543         }
3544
3545       if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3546           && TARGET_NO_TOC
3547           && ! flag_pic
3548           && mode == Pmode
3549           && CONSTANT_P (operands[1])
3550           && GET_CODE (operands[1]) != HIGH
3551           && GET_CODE (operands[1]) != CONST_INT)
3552         {
3553           rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3554
3555           /* If this is a function address on -mcall-aixdesc,
3556              convert it to the address of the descriptor.  */
3557           if (DEFAULT_ABI == ABI_AIX
3558               && GET_CODE (operands[1]) == SYMBOL_REF
3559               && XSTR (operands[1], 0)[0] == '.')
3560             {
3561               const char *name = XSTR (operands[1], 0);
3562               rtx new_ref;
3563               while (*name == '.')
3564                 name++;
3565               new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3566               CONSTANT_POOL_ADDRESS_P (new_ref)
3567                 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3568               SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3569               SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3570               SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3571               operands[1] = new_ref;
3572             }
3573
3574           if (DEFAULT_ABI == ABI_DARWIN)
3575             {
3576 #if TARGET_MACHO
3577               if (MACHO_DYNAMIC_NO_PIC_P)
3578                 {
3579                   /* Take care of any required data indirection.  */
3580                   operands[1] = rs6000_machopic_legitimize_pic_address (
3581                                   operands[1], mode, operands[0]);
3582                   if (operands[0] != operands[1])
3583                     emit_insn (gen_rtx_SET (VOIDmode,
3584                                             operands[0], operands[1]));
3585                   return;
3586                 }
3587 #endif
3588               emit_insn (gen_macho_high (target, operands[1]));
3589               emit_insn (gen_macho_low (operands[0], target, operands[1]));
3590               return;
3591             }
3592
3593           emit_insn (gen_elf_high (target, operands[1]));
3594           emit_insn (gen_elf_low (operands[0], target, operands[1]));
3595           return;
3596         }
3597
3598       /* If this is a SYMBOL_REF that refers to a constant pool entry,
3599          and we have put it in the TOC, we just need to make a TOC-relative
3600          reference to it.  */
3601       if (TARGET_TOC
3602           && GET_CODE (operands[1]) == SYMBOL_REF
3603           && constant_pool_expr_p (operands[1])
3604           && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3605                                               get_pool_mode (operands[1])))
3606         {
3607           operands[1] = create_TOC_reference (operands[1]);
3608         }
3609       else if (mode == Pmode
3610                && CONSTANT_P (operands[1])
3611                && ((GET_CODE (operands[1]) != CONST_INT
3612                     && ! easy_fp_constant (operands[1], mode))
3613                    || (GET_CODE (operands[1]) == CONST_INT
3614                        && num_insns_constant (operands[1], mode) > 2)
3615                    || (GET_CODE (operands[0]) == REG
3616                        && FP_REGNO_P (REGNO (operands[0]))))
3617                && GET_CODE (operands[1]) != HIGH
3618                && ! legitimate_constant_pool_address_p (operands[1])
3619                && ! toc_relative_expr_p (operands[1]))
3620         {
3621           /* Emit a USE operation so that the constant isn't deleted if
3622              expensive optimizations are turned on because nobody
3623              references it.  This should only be done for operands that
3624              contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3625              This should not be done for operands that contain LABEL_REFs.
3626              For now, we just handle the obvious case.  */
3627           if (GET_CODE (operands[1]) != LABEL_REF)
3628             emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3629
3630 #if TARGET_MACHO
3631           /* Darwin uses a special PIC legitimizer.  */
3632           if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3633             {
3634               operands[1] =
3635                 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3636                                                         operands[0]);
3637               if (operands[0] != operands[1])
3638                 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3639               return;
3640             }
3641 #endif
3642
3643           /* If we are to limit the number of things we put in the TOC and
3644              this is a symbol plus a constant we can add in one insn,
3645              just put the symbol in the TOC and add the constant.  Don't do
3646              this if reload is in progress.  */
3647           if (GET_CODE (operands[1]) == CONST
3648               && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3649               && GET_CODE (XEXP (operands[1], 0)) == PLUS
3650               && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3651               && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3652                   || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3653               && ! side_effects_p (operands[0]))
3654             {
3655               rtx sym =
3656                 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3657               rtx other = XEXP (XEXP (operands[1], 0), 1);
3658
3659               sym = force_reg (mode, sym);
3660               if (mode == SImode)
3661                 emit_insn (gen_addsi3 (operands[0], sym, other));
3662               else
3663                 emit_insn (gen_adddi3 (operands[0], sym, other));
3664               return;
3665             }
3666
3667           operands[1] = force_const_mem (mode, operands[1]);
3668
3669           if (TARGET_TOC
3670               && constant_pool_expr_p (XEXP (operands[1], 0))
3671               && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3672                         get_pool_constant (XEXP (operands[1], 0)),
3673                         get_pool_mode (XEXP (operands[1], 0))))
3674             {
3675               operands[1]
3676                 = gen_rtx_MEM (mode,
3677                                create_TOC_reference (XEXP (operands[1], 0)));
3678               set_mem_alias_set (operands[1], get_TOC_alias_set ());
3679               RTX_UNCHANGING_P (operands[1]) = 1;
3680             }
3681         }
3682       break;
3683
3684     case TImode:
3685       if (GET_CODE (operands[0]) == MEM
3686           && GET_CODE (XEXP (operands[0], 0)) != REG
3687           && ! reload_in_progress)
3688         operands[0]
3689           = replace_equiv_address (operands[0],
3690                                    copy_addr_to_reg (XEXP (operands[0], 0)));
3691
3692       if (GET_CODE (operands[1]) == MEM
3693           && GET_CODE (XEXP (operands[1], 0)) != REG
3694           && ! reload_in_progress)
3695         operands[1]
3696           = replace_equiv_address (operands[1],
3697                                    copy_addr_to_reg (XEXP (operands[1], 0)));
3698       if (TARGET_POWER)
3699         {
3700           emit_insn (gen_rtx_PARALLEL (VOIDmode,
3701                        gen_rtvec (2,
3702                                   gen_rtx_SET (VOIDmode,
3703                                                operands[0], operands[1]),
3704                                   gen_rtx_CLOBBER (VOIDmode,
3705                                                    gen_rtx_SCRATCH (SImode)))));
3706           return;
3707         }
3708       break;
3709
3710     default:
3711       abort ();
3712     }
3713
3714   /* Above, we may have called force_const_mem which may have returned
3715      an invalid address.  If we can, fix this up; otherwise, reload will
3716      have to deal with it.  */
3717   if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3718     operands[1] = validize_mem (operands[1]);
3719
3720  emit_set:
3721   emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3722 }
3723 \f
3724 /* Nonzero if we can use a floating-point register to pass this arg.  */
3725 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE)         \
3726   (GET_MODE_CLASS (MODE) == MODE_FLOAT          \
3727    && (CUM)->fregno <= FP_ARG_MAX_REG           \
3728    && TARGET_HARD_FLOAT && TARGET_FPRS)
3729
3730 /* Nonzero if we can use an AltiVec register to pass this arg.  */
3731 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED)      \
3732   (ALTIVEC_VECTOR_MODE (MODE)                           \
3733    && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG              \
3734    && TARGET_ALTIVEC_ABI                                \
3735    && (NAMED))
3736
3737 /* Return a nonzero value to say to return the function value in
3738    memory, just as large structures are always returned.  TYPE will be
3739    the data type of the value, and FNTYPE will be the type of the
3740    function doing the returning, or @code{NULL} for libcalls.
3741
3742    The AIX ABI for the RS/6000 specifies that all structures are
3743    returned in memory.  The Darwin ABI does the same.  The SVR4 ABI
3744    specifies that structures <= 8 bytes are returned in r3/r4, but a
3745    draft put them in memory, and GCC used to implement the draft
3746    instead of the final standard.  Therefore, TARGET_AIX_STRUCT_RET
3747    controls this instead of DEFAULT_ABI; V.4 targets needing backward
3748    compatibility can change DRAFT_V4_STRUCT_RET to override the
3749    default, and -m switches get the final word.  See
3750    rs6000_override_options for more details.
3751
3752    The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3753    long double support is enabled.  These values are returned in memory.
3754
3755    int_size_in_bytes returns -1 for variable size objects, which go in
3756    memory always.  The cast to unsigned makes -1 > 8.  */
3757
3758 static bool
3759 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3760 {
3761   if (AGGREGATE_TYPE_P (type)
3762       && (TARGET_AIX_STRUCT_RET
3763           || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3764     return true;
3765   if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3766     return true;
3767   return false;
3768 }
3769
3770 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3771    for a call to a function whose data type is FNTYPE.
3772    For a library call, FNTYPE is 0.
3773
3774    For incoming args we set the number of arguments in the prototype large
3775    so we never return a PARALLEL.  */
3776
3777 void
3778 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3779         rtx libname ATTRIBUTE_UNUSED, int incoming, int libcall)
3780 {
3781   static CUMULATIVE_ARGS zero_cumulative;
3782
3783   *cum = zero_cumulative;
3784   cum->words = 0;
3785   cum->fregno = FP_ARG_MIN_REG;
3786   cum->vregno = ALTIVEC_ARG_MIN_REG;
3787   cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3788   cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3789                       ? CALL_LIBCALL : CALL_NORMAL);
3790   cum->sysv_gregno = GP_ARG_MIN_REG;
3791   cum->stdarg = fntype
3792     && (TYPE_ARG_TYPES (fntype) != 0
3793         && (TREE_VALUE (tree_last  (TYPE_ARG_TYPES (fntype)))
3794             != void_type_node));
3795
3796   if (incoming)
3797     cum->nargs_prototype = 1000;                /* don't return a PARALLEL */
3798
3799   else if (cum->prototype)
3800     cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
3801                             + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
3802                                || rs6000_return_in_memory (TREE_TYPE (fntype),
3803                                                            fntype)));
3804
3805   else
3806     cum->nargs_prototype = 0;
3807
3808   /* Check for a longcall attribute.  */
3809   if (fntype
3810       && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3811       && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
3812     cum->call_cookie = CALL_LONG;
3813
3814   if (TARGET_DEBUG_ARG)
3815     {
3816       fprintf (stderr, "\ninit_cumulative_args:");
3817       if (fntype)
3818         {
3819           tree ret_type = TREE_TYPE (fntype);
3820           fprintf (stderr, " ret code = %s,",
3821                    tree_code_name[ (int)TREE_CODE (ret_type) ]);
3822         }
3823
3824       if (cum->call_cookie & CALL_LONG)
3825         fprintf (stderr, " longcall,");
3826
3827       fprintf (stderr, " proto = %d, nargs = %d\n",
3828                cum->prototype, cum->nargs_prototype);
3829     }
3830 }
3831 \f
3832 /* If defined, a C expression which determines whether, and in which
3833    direction, to pad out an argument with extra space.  The value
3834    should be of type `enum direction': either `upward' to pad above
3835    the argument, `downward' to pad below, or `none' to inhibit
3836    padding.
3837
3838    For the AIX ABI structs are always stored left shifted in their
3839    argument slot.  */
3840
3841 enum direction
3842 function_arg_padding (enum machine_mode mode, tree type)
3843 {
3844 #ifndef AGGREGATE_PADDING_FIXED
3845 #define AGGREGATE_PADDING_FIXED 0
3846 #endif
3847 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3848 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3849 #endif
3850
3851   if (!AGGREGATE_PADDING_FIXED)
3852     {
3853       /* GCC used to pass structures of the same size as integer types as
3854          if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3855          ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3856          passed padded downward, except that -mstrict-align further
3857          muddied the water in that multi-component structures of 2 and 4
3858          bytes in size were passed padded upward.
3859
3860          The following arranges for best compatibility with previous
3861          versions of gcc, but removes the -mstrict-align dependency.  */
3862       if (BYTES_BIG_ENDIAN)
3863         {
3864           HOST_WIDE_INT size = 0;
3865
3866           if (mode == BLKmode)
3867             {
3868               if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3869                 size = int_size_in_bytes (type);
3870             }
3871           else
3872             size = GET_MODE_SIZE (mode);
3873
3874           if (size == 1 || size == 2 || size == 4)
3875             return downward;
3876         }
3877       return upward;
3878     }
3879
3880   if (AGGREGATES_PAD_UPWARD_ALWAYS)
3881     {
3882       if (type != 0 && AGGREGATE_TYPE_P (type))
3883         return upward;
3884     }
3885
3886   /* Fall back to the default.  */
3887   return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
3888 }
3889
3890 /* If defined, a C expression that gives the alignment boundary, in bits,
3891    of an argument with the specified mode and type.  If it is not defined,
3892    PARM_BOUNDARY is used for all arguments.
3893
3894    V.4 wants long longs to be double word aligned.  */
3895
3896 int
3897 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
3898 {
3899   if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
3900     return 64;
3901    else if (SPE_VECTOR_MODE (mode))
3902      return 64;
3903   else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3904     return 128;
3905   else
3906     return PARM_BOUNDARY;
3907 }
3908 \f
3909 /* Update the data in CUM to advance over an argument
3910    of mode MODE and data type TYPE.
3911    (TYPE is null for libcalls where that information may not be available.)  */
3912
3913 void
3914 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3915                       tree type, int named)
3916 {
3917   cum->nargs_prototype--;
3918
3919   if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3920     {
3921       if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
3922         cum->vregno++;
3923
3924       /* In variable-argument functions, vector arguments get GPRs allocated
3925          even if they are going to be passed in a vector register.  */
3926       if (cum->stdarg && DEFAULT_ABI != ABI_V4)
3927         {
3928           int align;
3929
3930           /* Vector parameters must be 16-byte aligned.  This places
3931              them at 2 mod 4 in terms of words in 32-bit mode, since
3932              the parameter save area starts at offset 24 from the
3933              stack.  In 64-bit mode, they just have to start on an
3934              even word, since the parameter save area is 16-byte
3935              aligned.  Space for GPRs is reserved even if the argument
3936              will be passed in memory.  */
3937           if (TARGET_32BIT)
3938             align = ((6 - (cum->words & 3)) & 3);
3939           else
3940             align = cum->words & 1;
3941           cum->words += align + RS6000_ARG_SIZE (mode, type);
3942
3943           if (TARGET_DEBUG_ARG)
3944             {
3945               fprintf (stderr, "function_adv: words = %2d, align=%d, ",
3946                        cum->words, align);
3947               fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
3948                        cum->nargs_prototype, cum->prototype,
3949                        GET_MODE_NAME (mode));
3950             }
3951         }
3952     }
3953   else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
3954            && !cum->stdarg
3955            && cum->sysv_gregno <= GP_ARG_MAX_REG)
3956     cum->sysv_gregno++;
3957   else if (DEFAULT_ABI == ABI_V4)
3958     {
3959       if (TARGET_HARD_FLOAT && TARGET_FPRS
3960           && (mode == SFmode || mode == DFmode))
3961         {
3962           if (cum->fregno <= FP_ARG_V4_MAX_REG)
3963             cum->fregno++;
3964           else
3965             {
3966               if (mode == DFmode)
3967                 cum->words += cum->words & 1;
3968               cum->words += RS6000_ARG_SIZE (mode, type);
3969             }
3970         }
3971       else
3972         {
3973           int n_words;
3974           int gregno = cum->sysv_gregno;
3975
3976           /* Aggregates and IEEE quad get passed by reference.  */
3977           if ((type && AGGREGATE_TYPE_P (type))
3978               || mode == TFmode)
3979             n_words = 1;
3980           else
3981             n_words = RS6000_ARG_SIZE (mode, type);
3982
3983           /* Long long and SPE vectors are put in odd registers.  */
3984           if (n_words == 2 && (gregno & 1) == 0)
3985             gregno += 1;
3986
3987           /* Long long and SPE vectors are not split between registers
3988              and stack.  */
3989           if (gregno + n_words - 1 > GP_ARG_MAX_REG)
3990             {
3991               /* Long long is aligned on the stack.  */
3992               if (n_words == 2)
3993                 cum->words += cum->words & 1;
3994               cum->words += n_words;
3995             }
3996
3997           /* Note: continuing to accumulate gregno past when we've started
3998              spilling to the stack indicates the fact that we've started
3999              spilling to the stack to expand_builtin_saveregs.  */
4000           cum->sysv_gregno = gregno + n_words;
4001         }
4002
4003       if (TARGET_DEBUG_ARG)
4004         {
4005           fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4006                    cum->words, cum->fregno);
4007           fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4008                    cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4009           fprintf (stderr, "mode = %4s, named = %d\n",
4010                    GET_MODE_NAME (mode), named);
4011         }
4012     }
4013   else
4014     {
4015       int align = (TARGET_32BIT && (cum->words & 1) != 0
4016                    && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4017
4018       cum->words += align + RS6000_ARG_SIZE (mode, type);
4019
4020       if (GET_MODE_CLASS (mode) == MODE_FLOAT
4021           && TARGET_HARD_FLOAT && TARGET_FPRS)
4022         cum->fregno += (mode == TFmode ? 2 : 1);
4023
4024       if (TARGET_DEBUG_ARG)
4025         {
4026           fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4027                    cum->words, cum->fregno);
4028           fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4029                    cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4030           fprintf (stderr, "named = %d, align = %d\n", named, align);
4031         }
4032     }
4033 }
4034
4035 /* Determine where to put a SIMD argument on the SPE.  */
4036
4037 static rtx
4038 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4039                          tree type)
4040 {
4041   if (cum->stdarg)
4042     {
4043       int gregno = cum->sysv_gregno;
4044       int n_words = RS6000_ARG_SIZE (mode, type);
4045
4046       /* SPE vectors are put in odd registers.  */
4047       if (n_words == 2 && (gregno & 1) == 0)
4048         gregno += 1;
4049
4050       if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4051         {
4052           rtx r1, r2;
4053           enum machine_mode m = SImode;
4054
4055           r1 = gen_rtx_REG (m, gregno);
4056           r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4057           r2 = gen_rtx_REG (m, gregno + 1);
4058           r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4059           return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4060         }
4061       else
4062         return NULL_RTX;
4063     }
4064   else
4065     {
4066       if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4067         return gen_rtx_REG (mode, cum->sysv_gregno);
4068       else
4069         return NULL_RTX;
4070     }
4071 }
4072
4073 /* Determine where to place an argument in 64-bit mode with 32-bit ABI.  */
4074
4075 static rtx
4076 rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4077                            tree type, int align_words)
4078 {
4079   if (mode == DFmode)
4080     {
4081       /* -mpowerpc64 with 32bit ABI splits up a DFmode argument
4082          in vararg list into zero, one or two GPRs */
4083       if (align_words >= GP_ARG_NUM_REG)
4084         return gen_rtx_PARALLEL (DFmode,
4085                  gen_rtvec (2,
4086                             gen_rtx_EXPR_LIST (VOIDmode,
4087                                                NULL_RTX, const0_rtx),
4088                             gen_rtx_EXPR_LIST (VOIDmode,
4089                                                gen_rtx_REG (mode,
4090                                                             cum->fregno),
4091                                                const0_rtx)));
4092       else if (align_words + RS6000_ARG_SIZE (mode, type)
4093                > GP_ARG_NUM_REG)
4094         /* If this is partially on the stack, then we only
4095            include the portion actually in registers here.  */
4096         return gen_rtx_PARALLEL (DFmode,
4097                  gen_rtvec (2,
4098                             gen_rtx_EXPR_LIST (VOIDmode,
4099                                                gen_rtx_REG (SImode,
4100                                                             GP_ARG_MIN_REG
4101                                                             + align_words),
4102                                                const0_rtx),
4103                             gen_rtx_EXPR_LIST (VOIDmode,
4104                                                gen_rtx_REG (mode,
4105                                                             cum->fregno),
4106                                                const0_rtx)));
4107
4108       /* split a DFmode arg into two GPRs */
4109       return gen_rtx_PARALLEL (DFmode,
4110                gen_rtvec (3,
4111                           gen_rtx_EXPR_LIST (VOIDmode,
4112                                              gen_rtx_REG (SImode,
4113                                                           GP_ARG_MIN_REG
4114                                                           + align_words),
4115                                              const0_rtx),
4116                           gen_rtx_EXPR_LIST (VOIDmode,
4117                                              gen_rtx_REG (SImode,
4118                                                           GP_ARG_MIN_REG
4119                                                           + align_words + 1),
4120                                              GEN_INT (4)),
4121                           gen_rtx_EXPR_LIST (VOIDmode,
4122                                              gen_rtx_REG (mode, cum->fregno),
4123                                              const0_rtx)));
4124     }
4125   /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one
4126      or two GPRs */
4127   else if (mode == DImode)
4128     {
4129       if (align_words < GP_ARG_NUM_REG - 1)
4130         return gen_rtx_PARALLEL (DImode,
4131                  gen_rtvec (2,
4132                             gen_rtx_EXPR_LIST (VOIDmode,
4133                                                gen_rtx_REG (SImode,
4134                                                             GP_ARG_MIN_REG
4135                                                             + align_words),
4136                                                const0_rtx),
4137                             gen_rtx_EXPR_LIST (VOIDmode,
4138                                                gen_rtx_REG (SImode,
4139                                                             GP_ARG_MIN_REG
4140                                                             + align_words + 1),
4141                                                GEN_INT (4))));
4142       else if (align_words == GP_ARG_NUM_REG - 1)
4143           return gen_rtx_PARALLEL (DImode,
4144                    gen_rtvec (2,
4145                               gen_rtx_EXPR_LIST (VOIDmode,
4146                                                  NULL_RTX, const0_rtx),
4147                               gen_rtx_EXPR_LIST (VOIDmode,
4148                                                  gen_rtx_REG (SImode,
4149                                                               GP_ARG_MIN_REG
4150                                                               + align_words),
4151                                                  const0_rtx)));
4152     }
4153   else if (mode == BLKmode && align_words <= (GP_ARG_NUM_REG - 1))
4154     {
4155       int k;
4156       int size = int_size_in_bytes (type);
4157       int no_units = ((size - 1) / 4) + 1;
4158       int max_no_words = GP_ARG_NUM_REG - align_words;
4159       int rtlvec_len = no_units < max_no_words ? no_units : max_no_words;
4160       rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx));
4161
4162       memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx));
4163
4164       for (k=0; k < rtlvec_len; k++)
4165         rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode,
4166                                        gen_rtx_REG (SImode,
4167                                                     GP_ARG_MIN_REG
4168                                                     + align_words + k),
4169                                        k == 0 ? const0_rtx : GEN_INT (k*4));
4170
4171       return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k, rtlvec));
4172   }
4173
4174   return NULL_RTX;
4175 }
4176
4177 /* Determine where to put an argument to a function.
4178    Value is zero to push the argument on the stack,
4179    or a hard register in which to store the argument.
4180
4181    MODE is the argument's machine mode.
4182    TYPE is the data type of the argument (as a tree).
4183     This is null for libcalls where that information may
4184     not be available.
4185    CUM is a variable of type CUMULATIVE_ARGS which gives info about
4186     the preceding args and about the function being called.
4187    NAMED is nonzero if this argument is a named parameter
4188     (otherwise it is an extra parameter matching an ellipsis).
4189
4190    On RS/6000 the first eight words of non-FP are normally in registers
4191    and the rest are pushed.  Under AIX, the first 13 FP args are in registers.
4192    Under V.4, the first 8 FP args are in registers.
4193
4194    If this is floating-point and no prototype is specified, we use
4195    both an FP and integer register (or possibly FP reg and stack).  Library
4196    functions (when CALL_LIBCALL is set) always have the proper types for args,
4197    so we can pass the FP value just in one register.  emit_library_function
4198    doesn't support PARALLEL anyway.  */
4199
4200 struct rtx_def *
4201 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4202               tree type, int named)
4203 {
4204   enum rs6000_abi abi = DEFAULT_ABI;
4205
4206   /* Return a marker to indicate whether CR1 needs to set or clear the
4207      bit that V.4 uses to say fp args were passed in registers.
4208      Assume that we don't need the marker for software floating point,
4209      or compiler generated library calls.  */
4210   if (mode == VOIDmode)
4211     {
4212       if (abi == ABI_V4
4213           && cum->nargs_prototype < 0
4214           && (cum->call_cookie & CALL_LIBCALL) == 0
4215           && (cum->prototype || TARGET_NO_PROTOTYPE))
4216         {
4217           /* For the SPE, we need to crxor CR6 always.  */
4218           if (TARGET_SPE_ABI)
4219             return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4220           else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4221             return GEN_INT (cum->call_cookie
4222                             | ((cum->fregno == FP_ARG_MIN_REG)
4223                                ? CALL_V4_SET_FP_ARGS
4224                                : CALL_V4_CLEAR_FP_ARGS));
4225         }
4226
4227       return GEN_INT (cum->call_cookie);
4228     }
4229
4230   if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4231     return gen_rtx_REG (mode, cum->vregno);
4232   else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4233     {
4234       if (named || abi == ABI_V4)
4235         return NULL_RTX;
4236       else
4237         {
4238           /* Vector parameters to varargs functions under AIX or Darwin
4239              get passed in memory and possibly also in GPRs.  */
4240           int align, align_words;
4241           enum machine_mode part_mode = mode;
4242
4243           /* Vector parameters must be 16-byte aligned.  This places them at
4244              2 mod 4 in terms of words in 32-bit mode, since the parameter
4245              save area starts at offset 24 from the stack.  In 64-bit mode,
4246              they just have to start on an even word, since the parameter
4247              save area is 16-byte aligned.  */
4248           if (TARGET_32BIT)
4249             align = ((6 - (cum->words & 3)) & 3);
4250           else
4251             align = cum->words & 1;
4252           align_words = cum->words + align;
4253
4254           /* Out of registers?  Memory, then.  */
4255           if (align_words >= GP_ARG_NUM_REG)
4256             return NULL_RTX;
4257
4258           /* The vector value goes in GPRs.  Only the part of the
4259              value in GPRs is reported here.  */
4260           if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
4261               > GP_ARG_NUM_REG)
4262             /* Fortunately, there are only two possibilities, the value
4263                is either wholly in GPRs or half in GPRs and half not.  */
4264             part_mode = DImode;
4265
4266           return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4267         }
4268     }
4269   else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
4270     return rs6000_spe_function_arg (cum, mode, type);
4271   else if (abi == ABI_V4)
4272     {
4273       if (TARGET_HARD_FLOAT && TARGET_FPRS
4274           && (mode == SFmode || mode == DFmode))
4275         {
4276           if (cum->fregno <= FP_ARG_V4_MAX_REG)
4277             return gen_rtx_REG (mode, cum->fregno);
4278           else
4279             return NULL_RTX;
4280         }
4281       else
4282         {
4283           int n_words;
4284           int gregno = cum->sysv_gregno;
4285
4286           /* Aggregates and IEEE quad get passed by reference.  */
4287           if ((type && AGGREGATE_TYPE_P (type))
4288               || mode == TFmode)
4289             n_words = 1;
4290           else
4291             n_words = RS6000_ARG_SIZE (mode, type);
4292
4293           /* Long long and SPE vectors are put in odd registers.  */
4294           if (n_words == 2 && (gregno & 1) == 0)
4295             gregno += 1;
4296
4297           /* Long long do not split between registers and stack.  */
4298           if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4299             return gen_rtx_REG (mode, gregno);
4300           else
4301             return NULL_RTX;
4302         }
4303     }
4304   else
4305     {
4306       int align = (TARGET_32BIT && (cum->words & 1) != 0
4307                    && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4308       int align_words = cum->words + align;
4309
4310       if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
4311         return NULL_RTX;
4312
4313       if (TARGET_32BIT && TARGET_POWERPC64
4314           && (mode == DFmode || mode == DImode || mode == BLKmode))
4315         return rs6000_mixed_function_arg (cum, mode, type, align_words);
4316
4317       if (USE_FP_FOR_ARG_P (cum, mode, type))
4318         {
4319           if (! type
4320               || ((cum->nargs_prototype > 0)
4321                   /* IBM AIX extended its linkage convention definition always
4322                      to require FP args after register save area hole on the
4323                      stack.  */
4324                   && (DEFAULT_ABI != ABI_AIX
4325                       || ! TARGET_XL_CALL
4326                       || (align_words < GP_ARG_NUM_REG))))
4327             return gen_rtx_REG (mode, cum->fregno);
4328
4329           return gen_rtx_PARALLEL (mode,
4330             gen_rtvec (2,
4331                        gen_rtx_EXPR_LIST (VOIDmode,
4332                                 ((align_words >= GP_ARG_NUM_REG)
4333                                  ? NULL_RTX
4334                                  : (align_words
4335                                     + RS6000_ARG_SIZE (mode, type)
4336                                     > GP_ARG_NUM_REG
4337                                     /* If this is partially on the stack, then
4338                                        we only include the portion actually
4339                                        in registers here.  */
4340                                     ? gen_rtx_REG (SImode,
4341                                                GP_ARG_MIN_REG + align_words)
4342                                     : gen_rtx_REG (mode,
4343                                                GP_ARG_MIN_REG + align_words))),
4344                                 const0_rtx),
4345                        gen_rtx_EXPR_LIST (VOIDmode,
4346                                 gen_rtx_REG (mode, cum->fregno),
4347                                 const0_rtx)));
4348         }
4349       else if (align_words < GP_ARG_NUM_REG)
4350         return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4351       else
4352         return NULL_RTX;
4353     }
4354 }
4355 \f
4356 /* For an arg passed partly in registers and partly in memory,
4357    this is the number of registers used.
4358    For args passed entirely in registers or entirely in memory, zero.  */
4359
4360 int
4361 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4362                             tree type, int named)
4363 {
4364   if (DEFAULT_ABI == ABI_V4)
4365     return 0;
4366
4367   if (USE_FP_FOR_ARG_P (cum, mode, type)
4368       || USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4369     {
4370       if (cum->nargs_prototype >= 0)
4371         return 0;
4372     }
4373
4374   if (cum->words < GP_ARG_NUM_REG
4375       && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
4376     {
4377       int ret = GP_ARG_NUM_REG - cum->words;
4378       if (ret && TARGET_DEBUG_ARG)
4379         fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
4380
4381       return ret;
4382     }
4383
4384   return 0;
4385 }
4386 \f
4387 /* A C expression that indicates when an argument must be passed by
4388    reference.  If nonzero for an argument, a copy of that argument is
4389    made in memory and a pointer to the argument is passed instead of
4390    the argument itself.  The pointer is passed in whatever way is
4391    appropriate for passing a pointer to that type.
4392
4393    Under V.4, structures and unions are passed by reference.
4394
4395    As an extension to all ABIs, variable sized types are passed by
4396    reference.  */
4397
4398 int
4399 function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4400                                 enum machine_mode mode ATTRIBUTE_UNUSED,
4401                                 tree type, int named ATTRIBUTE_UNUSED)
4402 {
4403   if (DEFAULT_ABI == ABI_V4
4404       && ((type && AGGREGATE_TYPE_P (type))
4405           || mode == TFmode))
4406     {
4407       if (TARGET_DEBUG_ARG)
4408         fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
4409
4410       return 1;
4411     }
4412   return type && int_size_in_bytes (type) < 0;
4413 }
4414
4415 static void
4416 rs6000_move_block_from_reg(int regno, rtx x, int nregs)
4417 {
4418   int i;
4419   enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
4420
4421   if (nregs == 0)
4422     return;
4423
4424     for (i = 0; i < nregs; i++)
4425     {
4426       rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
4427       if (reload_completed)
4428       {
4429         if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
4430           tem = NULL_RTX;
4431         else
4432           tem = simplify_gen_subreg (reg_mode, x, BLKmode,
4433                                      i * GET_MODE_SIZE(reg_mode));
4434       }
4435       else
4436         tem = replace_equiv_address (tem, XEXP (tem, 0));
4437
4438       if (tem == NULL_RTX)
4439         abort ();
4440
4441       emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
4442     }
4443 }
4444
4445 \f
4446 /* Perform any needed actions needed for a function that is receiving a
4447    variable number of arguments.
4448
4449    CUM is as above.
4450
4451    MODE and TYPE are the mode and type of the current parameter.
4452
4453    PRETEND_SIZE is a variable that should be set to the amount of stack
4454    that must be pushed by the prolog to pretend that our caller pushed
4455    it.
4456
4457    Normally, this macro will push all remaining incoming registers on the
4458    stack and set PRETEND_SIZE to the length of the registers pushed.  */
4459
4460 static void
4461 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4462                 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
4463 {
4464   CUMULATIVE_ARGS next_cum;
4465   int reg_size = TARGET_32BIT ? 4 : 8;
4466   rtx save_area = NULL_RTX, mem;
4467   int first_reg_offset, set;
4468
4469   /* Skip the last named argument.  */
4470   next_cum = *cum;
4471   function_arg_advance (&next_cum, mode, type, 1);
4472
4473   if (DEFAULT_ABI == ABI_V4)
4474     {
4475       /* Indicate to allocate space on the stack for varargs save area.  */
4476       cfun->machine->sysv_varargs_p = 1;
4477       if (! no_rtl)
4478         save_area = plus_constant (virtual_stack_vars_rtx,
4479                                    - RS6000_VARARGS_SIZE);
4480
4481       first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4482     }
4483   else
4484     {
4485       first_reg_offset = next_cum.words;
4486       save_area = virtual_incoming_args_rtx;
4487       cfun->machine->sysv_varargs_p = 0;
4488
4489       if (MUST_PASS_IN_STACK (mode, type))
4490         first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
4491     }
4492
4493   set = get_varargs_alias_set ();
4494   if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4495     {
4496       mem = gen_rtx_MEM (BLKmode,
4497                          plus_constant (save_area,
4498                                         first_reg_offset * reg_size)),
4499       set_mem_alias_set (mem, set);
4500       set_mem_align (mem, BITS_PER_WORD);
4501
4502       rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
4503                                   GP_ARG_NUM_REG - first_reg_offset);
4504     }
4505
4506   /* Save FP registers if needed.  */
4507   if (DEFAULT_ABI == ABI_V4
4508       && TARGET_HARD_FLOAT && TARGET_FPRS
4509       && ! no_rtl
4510       && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4511     {
4512       int fregno = next_cum.fregno;
4513       rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4514       rtx lab = gen_label_rtx ();
4515       int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4516
4517       emit_jump_insn (gen_rtx_SET (VOIDmode,
4518                                    pc_rtx,
4519                                    gen_rtx_IF_THEN_ELSE (VOIDmode,
4520                                             gen_rtx_NE (VOIDmode, cr1,
4521                                                         const0_rtx),
4522                                             gen_rtx_LABEL_REF (VOIDmode, lab),
4523                                             pc_rtx)));
4524
4525       while (fregno <= FP_ARG_V4_MAX_REG)
4526         {
4527           mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
4528           set_mem_alias_set (mem, set);
4529           emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4530           fregno++;
4531           off += 8;
4532         }
4533
4534       emit_label (lab);
4535     }
4536 }
4537
4538 /* Create the va_list data type.  */
4539
4540 static tree
4541 rs6000_build_builtin_va_list (void)
4542 {
4543   tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4544
4545   /* For AIX, prefer 'char *' because that's what the system
4546      header files like.  */
4547   if (DEFAULT_ABI != ABI_V4)
4548     return build_pointer_type (char_type_node);
4549
4550   record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4551   type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4552
4553   f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
4554                       unsigned_char_type_node);
4555   f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
4556                       unsigned_char_type_node);
4557   /* Give the two bytes of padding a name, so that -Wpadded won't warn on
4558      every user file.  */
4559   f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
4560                       short_unsigned_type_node);
4561   f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4562                       ptr_type_node);
4563   f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4564                       ptr_type_node);
4565
4566   DECL_FIELD_CONTEXT (f_gpr) = record;
4567   DECL_FIELD_CONTEXT (f_fpr) = record;
4568   DECL_FIELD_CONTEXT (f_res) = record;
4569   DECL_FIELD_CONTEXT (f_ovf) = record;
4570   DECL_FIELD_CONTEXT (f_sav) = record;
4571
4572   TREE_CHAIN (record) = type_decl;
4573   TYPE_NAME (record) = type_decl;
4574   TYPE_FIELDS (record) = f_gpr;
4575   TREE_CHAIN (f_gpr) = f_fpr;
4576   TREE_CHAIN (f_fpr) = f_res;
4577   TREE_CHAIN (f_res) = f_ovf;
4578   TREE_CHAIN (f_ovf) = f_sav;
4579
4580   layout_type (record);
4581
4582   /* The correct type is an array type of one element.  */
4583   return build_array_type (record, build_index_type (size_zero_node));
4584 }
4585
4586 /* Implement va_start.  */
4587
4588 void
4589 rs6000_va_start (tree valist, rtx nextarg)
4590 {
4591   HOST_WIDE_INT words, n_gpr, n_fpr;
4592   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4593   tree gpr, fpr, ovf, sav, t;
4594
4595   /* Only SVR4 needs something special.  */
4596   if (DEFAULT_ABI != ABI_V4)
4597     {
4598       std_expand_builtin_va_start (valist, nextarg);
4599       return;
4600     }
4601
4602   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4603   f_fpr = TREE_CHAIN (f_gpr);
4604   f_res = TREE_CHAIN (f_fpr);
4605   f_ovf = TREE_CHAIN (f_res);
4606   f_sav = TREE_CHAIN (f_ovf);
4607
4608   valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4609   gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4610   fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4611   ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4612   sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4613
4614   /* Count number of gp and fp argument registers used.  */
4615   words = current_function_args_info.words;
4616   n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
4617   n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
4618
4619   if (TARGET_DEBUG_ARG)
4620     fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
4621              HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
4622              words, n_gpr, n_fpr);
4623
4624   t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
4625   TREE_SIDE_EFFECTS (t) = 1;
4626   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4627
4628   t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
4629   TREE_SIDE_EFFECTS (t) = 1;
4630   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4631
4632   /* Find the overflow area.  */
4633   t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4634   if (words != 0)
4635     t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
4636                build_int_2 (words * UNITS_PER_WORD, 0));
4637   t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4638   TREE_SIDE_EFFECTS (t) = 1;
4639   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4640
4641   /* Find the register save area.  */
4642   t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
4643   t = build (PLUS_EXPR, TREE_TYPE (sav), t,
4644              build_int_2 (-RS6000_VARARGS_SIZE, -1));
4645   t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4646   TREE_SIDE_EFFECTS (t) = 1;
4647   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4648 }
4649
4650 /* Implement va_arg.  */
4651
4652 rtx
4653 rs6000_va_arg (tree valist, tree type)
4654 {
4655   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4656   tree gpr, fpr, ovf, sav, reg, t, u;
4657   int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
4658   rtx lab_false, lab_over, addr_rtx, r;
4659
4660   if (DEFAULT_ABI != ABI_V4)
4661     {
4662       /* Variable sized types are passed by reference.  */
4663       if (int_size_in_bytes (type) < 0)
4664         {
4665           u = build_pointer_type (type);
4666
4667           /* Args grow upward.  */
4668           t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
4669                      build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4670           TREE_SIDE_EFFECTS (t) = 1;
4671
4672           t = build1 (NOP_EXPR, build_pointer_type (u), t);
4673           TREE_SIDE_EFFECTS (t) = 1;
4674
4675           t = build1 (INDIRECT_REF, u, t);
4676           TREE_SIDE_EFFECTS (t) = 1;
4677
4678           return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4679         }
4680       else
4681         {
4682           /* Altivec arguments must be aligned to a 128-bit boundary.  */
4683           if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4684             {
4685               tree vtype = TREE_TYPE (valist);
4686               tree new_valist, modify;
4687
4688               /* Round address up to multiple of 16.  Computes
4689                  (addr+15)&~0xf.  */
4690               new_valist = fold (build (BIT_AND_EXPR, vtype,
4691                                         fold (build (PLUS_EXPR, vtype, valist,
4692                                                      build_int_2 (15, 0))),
4693                                         build_int_2 (~15, -1)));
4694
4695               /* Update valist.  */
4696               modify = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
4697                               new_valist);
4698               TREE_SIDE_EFFECTS (modify) = 1;
4699               expand_expr (modify, const0_rtx, VOIDmode, EXPAND_NORMAL);
4700             }
4701
4702           return std_expand_builtin_va_arg (valist, type);
4703         }
4704     }
4705
4706   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4707   f_fpr = TREE_CHAIN (f_gpr);
4708   f_res = TREE_CHAIN (f_fpr);
4709   f_ovf = TREE_CHAIN (f_res);
4710   f_sav = TREE_CHAIN (f_ovf);
4711
4712   valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4713   gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4714   fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4715   ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4716   sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4717
4718   size = int_size_in_bytes (type);
4719   rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4720
4721   if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
4722     {
4723       /* Aggregates and long doubles are passed by reference.  */
4724       indirect_p = 1;
4725       reg = gpr;
4726       n_reg = 1;
4727       sav_ofs = 0;
4728       sav_scale = 4;
4729       size = UNITS_PER_WORD;
4730       rsize = 1;
4731     }
4732   else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
4733     {
4734       /* FP args go in FP registers, if present.  */
4735       indirect_p = 0;
4736       reg = fpr;
4737       n_reg = 1;
4738       sav_ofs = 8*4;
4739       sav_scale = 8;
4740     }
4741   else
4742     {
4743       /* Otherwise into GP registers.  */
4744       indirect_p = 0;
4745       reg = gpr;
4746       n_reg = rsize;
4747       sav_ofs = 0;
4748       sav_scale = 4;
4749     }
4750
4751   /* Pull the value out of the saved registers....  */
4752
4753   lab_false = gen_label_rtx ();
4754   lab_over = gen_label_rtx ();
4755   addr_rtx = gen_reg_rtx (Pmode);
4756
4757   /*  AltiVec vectors never go in registers.  */
4758   if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
4759     {
4760       TREE_THIS_VOLATILE (reg) = 1;
4761       emit_cmp_and_jump_insns
4762         (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
4763          GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
4764          lab_false);
4765
4766       /* Long long is aligned in the registers.  */
4767       if (n_reg > 1)
4768         {
4769           u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
4770                      build_int_2 (n_reg - 1, 0));
4771           u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
4772           u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
4773           TREE_SIDE_EFFECTS (u) = 1;
4774           expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
4775         }
4776
4777       if (sav_ofs)
4778         t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
4779       else
4780         t = sav;
4781
4782       u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
4783                  build_int_2 (n_reg, 0));
4784       TREE_SIDE_EFFECTS (u) = 1;
4785
4786       u = build1 (CONVERT_EXPR, integer_type_node, u);
4787       TREE_SIDE_EFFECTS (u) = 1;
4788
4789       u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
4790       TREE_SIDE_EFFECTS (u) = 1;
4791
4792       t = build (PLUS_EXPR, ptr_type_node, t, u);
4793       TREE_SIDE_EFFECTS (t) = 1;
4794
4795       r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4796       if (r != addr_rtx)
4797         emit_move_insn (addr_rtx, r);
4798
4799       emit_jump_insn (gen_jump (lab_over));
4800       emit_barrier ();
4801     }
4802
4803   emit_label (lab_false);
4804
4805   /* ... otherwise out of the overflow area.  */
4806
4807   /* Make sure we don't find reg 7 for the next int arg.
4808
4809      All AltiVec vectors go in the overflow area.  So in the AltiVec
4810      case we need to get the vectors from the overflow area, but
4811      remember where the GPRs and FPRs are.  */
4812   if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
4813                     || !TARGET_ALTIVEC))
4814     {
4815       t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
4816       TREE_SIDE_EFFECTS (t) = 1;
4817       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4818     }
4819
4820   /* Care for on-stack alignment if needed.  */
4821   if (rsize <= 1)
4822     t = ovf;
4823   else
4824     {
4825       int align;
4826
4827       /* AltiVec vectors are 16 byte aligned.  */
4828       if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
4829         align = 15;
4830       else
4831         align = 7;
4832
4833       t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
4834       t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
4835     }
4836   t = save_expr (t);
4837
4838   r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4839   if (r != addr_rtx)
4840     emit_move_insn (addr_rtx, r);
4841
4842   t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
4843   t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4844   TREE_SIDE_EFFECTS (t) = 1;
4845   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4846
4847   emit_label (lab_over);
4848
4849   if (indirect_p)
4850     {
4851       r = gen_rtx_MEM (Pmode, addr_rtx);
4852       set_mem_alias_set (r, get_varargs_alias_set ());
4853       emit_move_insn (addr_rtx, r);
4854     }
4855
4856   return addr_rtx;
4857 }
4858
4859 /* Builtins.  */
4860
4861 #define def_builtin(MASK, NAME, TYPE, CODE)                     \
4862 do {                                                            \
4863   if ((MASK) & target_flags)                                    \
4864     builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD,      \
4865                       NULL, NULL_TREE);                         \
4866 } while (0)
4867
4868 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc).  */
4869
4870 static const struct builtin_description bdesc_3arg[] =
4871 {
4872   { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
4873   { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
4874   { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
4875   { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
4876   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
4877   { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
4878   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
4879   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
4880   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
4881   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
4882   { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
4883   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
4884   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
4885   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
4886   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
4887   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
4888   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
4889   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
4890   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
4891   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
4892   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
4893   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
4894   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
4895 };
4896
4897 /* DST operations: void foo (void *, const int, const char).  */
4898
4899 static const struct builtin_description bdesc_dst[] =
4900 {
4901   { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
4902   { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
4903   { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
4904   { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
4905 };
4906
4907 /* Simple binary operations: VECc = foo (VECa, VECb).  */
4908
4909 static struct builtin_description bdesc_2arg[] =
4910 {
4911   { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
4912   { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
4913   { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
4914   { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
4915   { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
4916   { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
4917   { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
4918   { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
4919   { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
4920   { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
4921   { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
4922   { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
4923   { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
4924   { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
4925   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
4926   { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
4927   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
4928   { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
4929   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
4930   { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
4931   { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
4932   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
4933   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
4934   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
4935   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
4936   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
4937   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
4938   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
4939   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
4940   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
4941   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
4942   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
4943   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
4944   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
4945   { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
4946   { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
4947   { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
4948   { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
4949   { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
4950   { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
4951   { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
4952   { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
4953   { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
4954   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
4955   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
4956   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
4957   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
4958   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
4959   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
4960   { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
4961   { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
4962   { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
4963   { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
4964   { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
4965   { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
4966   { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
4967   { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
4968   { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
4969   { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
4970   { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
4971   { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
4972   { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
4973   { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
4974   { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
4975   { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
4976   { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
4977   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
4978   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
4979   { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
4980   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
4981   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
4982   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
4983   { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
4984   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
4985   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
4986   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
4987   { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
4988   { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
4989   { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
4990   { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
4991   { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
4992   { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
4993   { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
4994   { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
4995   { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
4996   { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
4997   { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
4998   { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
4999   { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5000   { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5001   { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5002   { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5003   { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5004   { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5005   { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5006   { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5007   { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5008   { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5009   { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5010   { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5011   { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5012   { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5013   { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5014   { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5015   { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5016   { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5017   { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5018   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5019   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5020   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5021   { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5022   { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5023   { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5024
5025   /* Place holder, leave as first spe builtin.  */
5026   { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5027   { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5028   { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5029   { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5030   { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5031   { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5032   { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5033   { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5034   { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5035   { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5036   { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5037   { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5038   { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5039   { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5040   { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5041   { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5042   { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5043   { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5044   { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5045   { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5046   { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5047   { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5048   { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5049   { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5050   { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5051   { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5052   { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5053   { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5054   { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5055   { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5056   { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5057   { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5058   { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5059   { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5060   { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5061   { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5062   { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5063   { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5064   { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5065   { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5066   { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5067   { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5068   { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5069   { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5070   { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5071   { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5072   { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5073   { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5074   { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5075   { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5076   { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5077   { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5078   { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5079   { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5080   { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5081   { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5082   { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5083   { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5084   { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5085   { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5086   { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5087   { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5088   { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5089   { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5090   { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5091   { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5092   { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5093   { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5094   { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5095   { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5096   { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5097   { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5098   { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5099   { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5100   { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5101   { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5102   { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5103   { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5104   { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5105   { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5106   { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5107   { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5108   { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5109   { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5110   { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5111   { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5112   { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5113   { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5114   { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5115   { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5116   { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5117   { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5118   { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5119   { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5120   { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5121   { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5122   { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5123   { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5124   { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5125   { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5126   { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5127   { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5128   { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5129   { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5130   { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5131   { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5132   { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5133   { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5134   { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5135
5136   /* SPE binary operations expecting a 5-bit unsigned literal.  */
5137   { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5138
5139   { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5140   { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5141   { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5142   { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5143   { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5144   { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5145   { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5146   { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5147   { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5148   { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5149   { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5150   { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5151   { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5152   { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5153   { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5154   { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5155   { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5156   { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5157   { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5158   { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5159   { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5160   { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5161   { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5162   { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5163   { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5164   { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5165
5166   /* Place-holder.  Leave as last binary SPE builtin.  */
5167   { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5168 };
5169
5170 /* AltiVec predicates.  */
5171
5172 struct builtin_description_predicates
5173 {
5174   const unsigned int mask;
5175   const enum insn_code icode;
5176   const char *opcode;
5177   const char *const name;
5178   const enum rs6000_builtins code;
5179 };
5180
5181 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5182 {
5183   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5184   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5185   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5186   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5187   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5188   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5189   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5190   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5191   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5192   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5193   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5194   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5195   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5196 };
5197
5198 /* SPE predicates.  */
5199 static struct builtin_description bdesc_spe_predicates[] =
5200 {
5201   /* Place-holder.  Leave as first.  */
5202   { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5203   { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5204   { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5205   { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5206   { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5207   { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5208   { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5209   { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5210   { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5211   { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5212   /* Place-holder.  Leave as last.  */
5213   { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5214 };
5215
5216 /* SPE evsel predicates.  */
5217 static struct builtin_description bdesc_spe_evsel[] =
5218 {
5219   /* Place-holder.  Leave as first.  */
5220   { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5221   { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5222   { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5223   { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5224   { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5225   { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5226   { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5227   { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5228   { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5229   { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5230   /* Place-holder.  Leave as last.  */
5231   { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5232 };
5233
5234 /* ABS* operations.  */
5235
5236 static const struct builtin_description bdesc_abs[] =
5237 {
5238   { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5239   { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5240   { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5241   { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5242   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5243   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5244   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5245 };
5246
5247 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5248    foo (VECa).  */
5249
5250 static struct builtin_description bdesc_1arg[] =
5251 {
5252   { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5253   { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5254   { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5255   { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5256   { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5257   { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5258   { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5259   { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5260   { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5261   { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5262   { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5263   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5264   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5265   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5266   { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5267   { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5268   { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5269
5270   /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5271      end with SPE_BUILTIN_EVSUBFUSIAAW.  */
5272   { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5273   { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5274   { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5275   { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5276   { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5277   { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5278   { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5279   { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5280   { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5281   { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5282   { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5283   { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5284   { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5285   { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5286   { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5287   { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5288   { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5289   { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5290   { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5291   { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5292   { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5293   { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5294   { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5295   { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5296   { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5297   { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5298   { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5299   { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5300
5301   /* Place-holder.  Leave as last unary SPE builtin.  */
5302   { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5303 };
5304
5305 static rtx
5306 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5307 {
5308   rtx pat;
5309   tree arg0 = TREE_VALUE (arglist);
5310   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5311   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5312   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5313
5314   if (icode == CODE_FOR_nothing)
5315     /* Builtin not supported on this processor.  */
5316     return 0;
5317
5318   /* If we got invalid arguments bail out before generating bad rtl.  */
5319   if (arg0 == error_mark_node)
5320     return const0_rtx;
5321
5322   if (icode == CODE_FOR_altivec_vspltisb
5323       || icode == CODE_FOR_altivec_vspltish
5324       || icode == CODE_FOR_altivec_vspltisw
5325       || icode == CODE_FOR_spe_evsplatfi
5326       || icode == CODE_FOR_spe_evsplati)
5327     {
5328       /* Only allow 5-bit *signed* literals.  */
5329       if (GET_CODE (op0) != CONST_INT
5330           || INTVAL (op0) > 0x1f
5331           || INTVAL (op0) < -0x1f)
5332         {
5333           error ("argument 1 must be a 5-bit signed literal");
5334           return const0_rtx;
5335         }
5336     }
5337
5338   if (target == 0
5339       || GET_MODE (target) != tmode
5340       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5341     target = gen_reg_rtx (tmode);
5342
5343   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5344     op0 = copy_to_mode_reg (mode0, op0);
5345
5346   pat = GEN_FCN (icode) (target, op0);
5347   if (! pat)
5348     return 0;
5349   emit_insn (pat);
5350
5351   return target;
5352 }
5353
5354 static rtx
5355 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5356 {
5357   rtx pat, scratch1, scratch2;
5358   tree arg0 = TREE_VALUE (arglist);
5359   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5360   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5361   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5362
5363   /* If we have invalid arguments, bail out before generating bad rtl.  */
5364   if (arg0 == error_mark_node)
5365     return const0_rtx;
5366
5367   if (target == 0
5368       || GET_MODE (target) != tmode
5369       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5370     target = gen_reg_rtx (tmode);
5371
5372   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5373     op0 = copy_to_mode_reg (mode0, op0);
5374
5375   scratch1 = gen_reg_rtx (mode0);
5376   scratch2 = gen_reg_rtx (mode0);
5377
5378   pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5379   if (! pat)
5380     return 0;
5381   emit_insn (pat);
5382
5383   return target;
5384 }
5385
5386 static rtx
5387 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5388 {
5389   rtx pat;
5390   tree arg0 = TREE_VALUE (arglist);
5391   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5392   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5393   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5394   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5395   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5396   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5397
5398   if (icode == CODE_FOR_nothing)
5399     /* Builtin not supported on this processor.  */
5400     return 0;
5401
5402   /* If we got invalid arguments bail out before generating bad rtl.  */
5403   if (arg0 == error_mark_node || arg1 == error_mark_node)
5404     return const0_rtx;
5405
5406   if (icode == CODE_FOR_altivec_vcfux
5407       || icode == CODE_FOR_altivec_vcfsx
5408       || icode == CODE_FOR_altivec_vctsxs
5409       || icode == CODE_FOR_altivec_vctuxs
5410       || icode == CODE_FOR_altivec_vspltb
5411       || icode == CODE_FOR_altivec_vsplth
5412       || icode == CODE_FOR_altivec_vspltw
5413       || icode == CODE_FOR_spe_evaddiw
5414       || icode == CODE_FOR_spe_evldd
5415       || icode == CODE_FOR_spe_evldh
5416       || icode == CODE_FOR_spe_evldw
5417       || icode == CODE_FOR_spe_evlhhesplat
5418       || icode == CODE_FOR_spe_evlhhossplat
5419       || icode == CODE_FOR_spe_evlhhousplat
5420       || icode == CODE_FOR_spe_evlwhe
5421       || icode == CODE_FOR_spe_evlwhos
5422       || icode == CODE_FOR_spe_evlwhou
5423       || icode == CODE_FOR_spe_evlwhsplat
5424       || icode == CODE_FOR_spe_evlwwsplat
5425       || icode == CODE_FOR_spe_evrlwi
5426       || icode == CODE_FOR_spe_evslwi
5427       || icode == CODE_FOR_spe_evsrwis
5428       || icode == CODE_FOR_spe_evsubifw
5429       || icode == CODE_FOR_spe_evsrwiu)
5430     {
5431       /* Only allow 5-bit unsigned literals.  */
5432       if (TREE_CODE (arg1) != INTEGER_CST
5433           || TREE_INT_CST_LOW (arg1) & ~0x1f)
5434         {
5435           error ("argument 2 must be a 5-bit unsigned literal");
5436           return const0_rtx;
5437         }
5438     }
5439
5440   if (target == 0
5441       || GET_MODE (target) != tmode
5442       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5443     target = gen_reg_rtx (tmode);
5444
5445   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5446     op0 = copy_to_mode_reg (mode0, op0);
5447   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5448     op1 = copy_to_mode_reg (mode1, op1);
5449
5450   pat = GEN_FCN (icode) (target, op0, op1);
5451   if (! pat)
5452     return 0;
5453   emit_insn (pat);
5454
5455   return target;
5456 }
5457
5458 static rtx
5459 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
5460                                   tree arglist, rtx target)
5461 {
5462   rtx pat, scratch;
5463   tree cr6_form = TREE_VALUE (arglist);
5464   tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
5465   tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5466   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5467   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5468   enum machine_mode tmode = SImode;
5469   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5470   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5471   int cr6_form_int;
5472
5473   if (TREE_CODE (cr6_form) != INTEGER_CST)
5474     {
5475       error ("argument 1 of __builtin_altivec_predicate must be a constant");
5476       return const0_rtx;
5477     }
5478   else
5479     cr6_form_int = TREE_INT_CST_LOW (cr6_form);
5480
5481   if (mode0 != mode1)
5482     abort ();
5483
5484   /* If we have invalid arguments, bail out before generating bad rtl.  */
5485   if (arg0 == error_mark_node || arg1 == error_mark_node)
5486     return const0_rtx;
5487
5488   if (target == 0
5489       || GET_MODE (target) != tmode
5490       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5491     target = gen_reg_rtx (tmode);
5492
5493   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5494     op0 = copy_to_mode_reg (mode0, op0);
5495   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5496     op1 = copy_to_mode_reg (mode1, op1);
5497
5498   scratch = gen_reg_rtx (mode0);
5499
5500   pat = GEN_FCN (icode) (scratch, op0, op1,
5501                          gen_rtx (SYMBOL_REF, Pmode, opcode));
5502   if (! pat)
5503     return 0;
5504   emit_insn (pat);
5505
5506   /* The vec_any* and vec_all* predicates use the same opcodes for two
5507      different operations, but the bits in CR6 will be different
5508      depending on what information we want.  So we have to play tricks
5509      with CR6 to get the right bits out.
5510
5511      If you think this is disgusting, look at the specs for the
5512      AltiVec predicates.  */
5513
5514      switch (cr6_form_int)
5515        {
5516        case 0:
5517          emit_insn (gen_cr6_test_for_zero (target));
5518          break;
5519        case 1:
5520          emit_insn (gen_cr6_test_for_zero_reverse (target));
5521          break;
5522        case 2:
5523          emit_insn (gen_cr6_test_for_lt (target));
5524          break;
5525        case 3:
5526          emit_insn (gen_cr6_test_for_lt_reverse (target));
5527          break;
5528        default:
5529          error ("argument 1 of __builtin_altivec_predicate is out of range");
5530          break;
5531        }
5532
5533   return target;
5534 }
5535
5536 static rtx
5537 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
5538 {
5539   rtx pat, addr;
5540   tree arg0 = TREE_VALUE (arglist);
5541   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5542   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5543   enum machine_mode mode0 = Pmode;
5544   enum machine_mode mode1 = Pmode;
5545   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5546   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5547
5548   if (icode == CODE_FOR_nothing)
5549     /* Builtin not supported on this processor.  */
5550     return 0;
5551
5552   /* If we got invalid arguments bail out before generating bad rtl.  */
5553   if (arg0 == error_mark_node || arg1 == error_mark_node)
5554     return const0_rtx;
5555
5556   if (target == 0
5557       || GET_MODE (target) != tmode
5558       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5559     target = gen_reg_rtx (tmode);
5560
5561   op1 = copy_to_mode_reg (mode1, op1);
5562
5563   if (op0 == const0_rtx)
5564     {
5565       addr = gen_rtx_MEM (tmode, op1);
5566     }
5567   else
5568     {
5569       op0 = copy_to_mode_reg (mode0, op0);
5570       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
5571     }
5572
5573   pat = GEN_FCN (icode) (target, addr);
5574
5575   if (! pat)
5576     return 0;
5577   emit_insn (pat);
5578
5579   return target;
5580 }
5581
5582 static rtx
5583 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
5584 {
5585   tree arg0 = TREE_VALUE (arglist);
5586   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5587   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5588   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5589   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5590   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5591   rtx pat, addr;
5592   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5593   enum machine_mode mode1 = Pmode;
5594   enum machine_mode mode2 = Pmode;
5595
5596   /* Invalid arguments.  Bail before doing anything stoopid!  */
5597   if (arg0 == error_mark_node
5598       || arg1 == error_mark_node
5599       || arg2 == error_mark_node)
5600     return const0_rtx;
5601
5602   if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
5603     op0 = copy_to_mode_reg (tmode, op0);
5604
5605   op2 = copy_to_mode_reg (mode2, op2);
5606
5607   if (op1 == const0_rtx)
5608     {
5609       addr = gen_rtx_MEM (tmode, op2);
5610     }
5611   else
5612     {
5613       op1 = copy_to_mode_reg (mode1, op1);
5614       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
5615     }
5616
5617   pat = GEN_FCN (icode) (addr, op0);
5618   if (pat)
5619     emit_insn (pat);
5620   return NULL_RTX;
5621 }
5622
5623 static rtx
5624 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
5625 {
5626   rtx pat;
5627   tree arg0 = TREE_VALUE (arglist);
5628   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5629   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5630   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5631   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5632   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5633   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5634   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5635   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5636   enum machine_mode mode2 = insn_data[icode].operand[3].mode;
5637
5638   if (icode == CODE_FOR_nothing)
5639     /* Builtin not supported on this processor.  */
5640     return 0;
5641
5642   /* If we got invalid arguments bail out before generating bad rtl.  */
5643   if (arg0 == error_mark_node
5644       || arg1 == error_mark_node
5645       || arg2 == error_mark_node)
5646     return const0_rtx;
5647
5648   if (icode == CODE_FOR_altivec_vsldoi_4sf
5649       || icode == CODE_FOR_altivec_vsldoi_4si
5650       || icode == CODE_FOR_altivec_vsldoi_8hi
5651       || icode == CODE_FOR_altivec_vsldoi_16qi)
5652     {
5653       /* Only allow 4-bit unsigned literals.  */
5654       if (TREE_CODE (arg2) != INTEGER_CST
5655           || TREE_INT_CST_LOW (arg2) & ~0xf)
5656         {
5657           error ("argument 3 must be a 4-bit unsigned literal");
5658           return const0_rtx;
5659         }
5660     }
5661
5662   if (target == 0
5663       || GET_MODE (target) != tmode
5664       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5665     target = gen_reg_rtx (tmode);
5666
5667   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5668     op0 = copy_to_mode_reg (mode0, op0);
5669   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5670     op1 = copy_to_mode_reg (mode1, op1);
5671   if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
5672     op2 = copy_to_mode_reg (mode2, op2);
5673
5674   pat = GEN_FCN (icode) (target, op0, op1, op2);
5675   if (! pat)
5676     return 0;
5677   emit_insn (pat);
5678
5679   return target;
5680 }
5681
5682 /* Expand the lvx builtins.  */
5683 static rtx
5684 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
5685 {
5686   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5687   tree arglist = TREE_OPERAND (exp, 1);
5688   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5689   tree arg0;
5690   enum machine_mode tmode, mode0;
5691   rtx pat, op0;
5692   enum insn_code icode;
5693
5694   switch (fcode)
5695     {
5696     case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
5697       icode = CODE_FOR_altivec_lvx_16qi;
5698       break;
5699     case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
5700       icode = CODE_FOR_altivec_lvx_8hi;
5701       break;
5702     case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
5703       icode = CODE_FOR_altivec_lvx_4si;
5704       break;
5705     case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
5706       icode = CODE_FOR_altivec_lvx_4sf;
5707       break;
5708     default:
5709       *expandedp = false;
5710       return NULL_RTX;
5711     }
5712
5713   *expandedp = true;
5714
5715   arg0 = TREE_VALUE (arglist);
5716   op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5717   tmode = insn_data[icode].operand[0].mode;
5718   mode0 = insn_data[icode].operand[1].mode;
5719
5720   if (target == 0
5721       || GET_MODE (target) != tmode
5722       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5723     target = gen_reg_rtx (tmode);
5724
5725   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5726     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5727
5728   pat = GEN_FCN (icode) (target, op0);
5729   if (! pat)
5730     return 0;
5731   emit_insn (pat);
5732   return target;
5733 }
5734
5735 /* Expand the stvx builtins.  */
5736 static rtx
5737 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5738                            bool *expandedp)
5739 {
5740   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5741   tree arglist = TREE_OPERAND (exp, 1);
5742   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5743   tree arg0, arg1;
5744   enum machine_mode mode0, mode1;
5745   rtx pat, op0, op1;
5746   enum insn_code icode;
5747
5748   switch (fcode)
5749     {
5750     case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
5751       icode = CODE_FOR_altivec_stvx_16qi;
5752       break;
5753     case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
5754       icode = CODE_FOR_altivec_stvx_8hi;
5755       break;
5756     case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
5757       icode = CODE_FOR_altivec_stvx_4si;
5758       break;
5759     case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
5760       icode = CODE_FOR_altivec_stvx_4sf;
5761       break;
5762     default:
5763       *expandedp = false;
5764       return NULL_RTX;
5765     }
5766
5767   arg0 = TREE_VALUE (arglist);
5768   arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5769   op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5770   op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5771   mode0 = insn_data[icode].operand[0].mode;
5772   mode1 = insn_data[icode].operand[1].mode;
5773
5774   if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5775     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5776   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
5777     op1 = copy_to_mode_reg (mode1, op1);
5778
5779   pat = GEN_FCN (icode) (op0, op1);
5780   if (pat)
5781     emit_insn (pat);
5782
5783   *expandedp = true;
5784   return NULL_RTX;
5785 }
5786
5787 /* Expand the dst builtins.  */
5788 static rtx
5789 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5790                             bool *expandedp)
5791 {
5792   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5793   tree arglist = TREE_OPERAND (exp, 1);
5794   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5795   tree arg0, arg1, arg2;
5796   enum machine_mode mode0, mode1, mode2;
5797   rtx pat, op0, op1, op2;
5798   struct builtin_description *d;
5799   size_t i;
5800
5801   *expandedp = false;
5802
5803   /* Handle DST variants.  */
5804   d = (struct builtin_description *) bdesc_dst;
5805   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
5806     if (d->code == fcode)
5807       {
5808         arg0 = TREE_VALUE (arglist);
5809         arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5810         arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5811         op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5812         op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5813         op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5814         mode0 = insn_data[d->icode].operand[0].mode;
5815         mode1 = insn_data[d->icode].operand[1].mode;
5816         mode2 = insn_data[d->icode].operand[2].mode;
5817
5818         /* Invalid arguments, bail out before generating bad rtl.  */
5819         if (arg0 == error_mark_node
5820             || arg1 == error_mark_node
5821             || arg2 == error_mark_node)
5822           return const0_rtx;
5823
5824         if (TREE_CODE (arg2) != INTEGER_CST
5825             || TREE_INT_CST_LOW (arg2) & ~0x3)
5826           {
5827             error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
5828             return const0_rtx;
5829           }
5830
5831         if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
5832           op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5833         if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
5834           op1 = copy_to_mode_reg (mode1, op1);
5835
5836         pat = GEN_FCN (d->icode) (op0, op1, op2);
5837         if (pat != 0)
5838           emit_insn (pat);
5839
5840         *expandedp = true;
5841         return NULL_RTX;
5842       }
5843
5844   return NULL_RTX;
5845 }
5846
5847 /* Expand the builtin in EXP and store the result in TARGET.  Store
5848    true in *EXPANDEDP if we found a builtin to expand.  */
5849 static rtx
5850 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
5851 {
5852   struct builtin_description *d;
5853   struct builtin_description_predicates *dp;
5854   size_t i;
5855   enum insn_code icode;
5856   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5857   tree arglist = TREE_OPERAND (exp, 1);
5858   tree arg0;
5859   rtx op0, pat;
5860   enum machine_mode tmode, mode0;
5861   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5862
5863   target = altivec_expand_ld_builtin (exp, target, expandedp);
5864   if (*expandedp)
5865     return target;
5866
5867   target = altivec_expand_st_builtin (exp, target, expandedp);
5868   if (*expandedp)
5869     return target;
5870
5871   target = altivec_expand_dst_builtin (exp, target, expandedp);
5872   if (*expandedp)
5873     return target;
5874
5875   *expandedp = true;
5876
5877   switch (fcode)
5878     {
5879     case ALTIVEC_BUILTIN_STVX:
5880       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
5881     case ALTIVEC_BUILTIN_STVEBX:
5882       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
5883     case ALTIVEC_BUILTIN_STVEHX:
5884       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
5885     case ALTIVEC_BUILTIN_STVEWX:
5886       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
5887     case ALTIVEC_BUILTIN_STVXL:
5888       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
5889
5890     case ALTIVEC_BUILTIN_MFVSCR:
5891       icode = CODE_FOR_altivec_mfvscr;
5892       tmode = insn_data[icode].operand[0].mode;
5893
5894       if (target == 0
5895           || GET_MODE (target) != tmode
5896           || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5897         target = gen_reg_rtx (tmode);
5898
5899       pat = GEN_FCN (icode) (target);
5900       if (! pat)
5901         return 0;
5902       emit_insn (pat);
5903       return target;
5904
5905     case ALTIVEC_BUILTIN_MTVSCR:
5906       icode = CODE_FOR_altivec_mtvscr;
5907       arg0 = TREE_VALUE (arglist);
5908       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5909       mode0 = insn_data[icode].operand[0].mode;
5910
5911       /* If we got invalid arguments bail out before generating bad rtl.  */
5912       if (arg0 == error_mark_node)
5913         return const0_rtx;
5914
5915       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5916         op0 = copy_to_mode_reg (mode0, op0);
5917
5918       pat = GEN_FCN (icode) (op0);
5919       if (pat)
5920         emit_insn (pat);
5921       return NULL_RTX;
5922
5923     case ALTIVEC_BUILTIN_DSSALL:
5924       emit_insn (gen_altivec_dssall ());
5925       return NULL_RTX;
5926
5927     case ALTIVEC_BUILTIN_DSS:
5928       icode = CODE_FOR_altivec_dss;
5929       arg0 = TREE_VALUE (arglist);
5930       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5931       mode0 = insn_data[icode].operand[0].mode;
5932
5933       /* If we got invalid arguments bail out before generating bad rtl.  */
5934       if (arg0 == error_mark_node)
5935         return const0_rtx;
5936
5937       if (TREE_CODE (arg0) != INTEGER_CST
5938           || TREE_INT_CST_LOW (arg0) & ~0x3)
5939         {
5940           error ("argument to dss must be a 2-bit unsigned literal");
5941           return const0_rtx;
5942         }
5943
5944       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5945         op0 = copy_to_mode_reg (mode0, op0);
5946
5947       emit_insn (gen_altivec_dss (op0));
5948       return NULL_RTX;
5949     }
5950
5951   /* Expand abs* operations.  */
5952   d = (struct builtin_description *) bdesc_abs;
5953   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
5954     if (d->code == fcode)
5955       return altivec_expand_abs_builtin (d->icode, arglist, target);
5956
5957   /* Expand the AltiVec predicates.  */
5958   dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
5959   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
5960     if (dp->code == fcode)
5961       return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
5962
5963   /* LV* are funky.  We initialized them differently.  */
5964   switch (fcode)
5965     {
5966     case ALTIVEC_BUILTIN_LVSL:
5967       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
5968                                            arglist, target);
5969     case ALTIVEC_BUILTIN_LVSR:
5970       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
5971                                           arglist, target);
5972     case ALTIVEC_BUILTIN_LVEBX:
5973       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
5974                                           arglist, target);
5975     case ALTIVEC_BUILTIN_LVEHX:
5976       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
5977                                           arglist, target);
5978     case ALTIVEC_BUILTIN_LVEWX:
5979       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
5980                                           arglist, target);
5981     case ALTIVEC_BUILTIN_LVXL:
5982       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
5983                                           arglist, target);
5984     case ALTIVEC_BUILTIN_LVX:
5985       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
5986                                           arglist, target);
5987     default:
5988       break;
5989       /* Fall through.  */
5990     }
5991
5992   *expandedp = false;
5993   return NULL_RTX;
5994 }
5995
5996 /* Binops that need to be initialized manually, but can be expanded
5997    automagically by rs6000_expand_binop_builtin.  */
5998 static struct builtin_description bdesc_2arg_spe[] =
5999 {
6000   { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6001   { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6002   { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6003   { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6004   { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6005   { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6006   { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6007   { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6008   { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6009   { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6010   { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6011   { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6012   { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6013   { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6014   { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6015   { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6016   { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6017   { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6018   { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6019   { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6020   { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6021   { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6022 };
6023
6024 /* Expand the builtin in EXP and store the result in TARGET.  Store
6025    true in *EXPANDEDP if we found a builtin to expand.
6026
6027    This expands the SPE builtins that are not simple unary and binary
6028    operations.  */
6029 static rtx
6030 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6031 {
6032   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6033   tree arglist = TREE_OPERAND (exp, 1);
6034   tree arg1, arg0;
6035   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6036   enum insn_code icode;
6037   enum machine_mode tmode, mode0;
6038   rtx pat, op0;
6039   struct builtin_description *d;
6040   size_t i;
6041
6042   *expandedp = true;
6043
6044   /* Syntax check for a 5-bit unsigned immediate.  */
6045   switch (fcode)
6046     {
6047     case SPE_BUILTIN_EVSTDD:
6048     case SPE_BUILTIN_EVSTDH:
6049     case SPE_BUILTIN_EVSTDW:
6050     case SPE_BUILTIN_EVSTWHE:
6051     case SPE_BUILTIN_EVSTWHO:
6052     case SPE_BUILTIN_EVSTWWE:
6053     case SPE_BUILTIN_EVSTWWO:
6054       arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6055       if (TREE_CODE (arg1) != INTEGER_CST
6056           || TREE_INT_CST_LOW (arg1) & ~0x1f)
6057         {
6058           error ("argument 2 must be a 5-bit unsigned literal");
6059           return const0_rtx;
6060         }
6061       break;
6062     default:
6063       break;
6064     }
6065
6066   /* The evsplat*i instructions are not quite generic.  */
6067   switch (fcode)
6068     {
6069     case SPE_BUILTIN_EVSPLATFI:
6070       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6071                                          arglist, target);
6072     case SPE_BUILTIN_EVSPLATI:
6073       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6074                                          arglist, target);
6075     default:
6076       break;
6077     }
6078
6079   d = (struct builtin_description *) bdesc_2arg_spe;
6080   for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6081     if (d->code == fcode)
6082       return rs6000_expand_binop_builtin (d->icode, arglist, target);
6083
6084   d = (struct builtin_description *) bdesc_spe_predicates;
6085   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6086     if (d->code == fcode)
6087       return spe_expand_predicate_builtin (d->icode, arglist, target);
6088
6089   d = (struct builtin_description *) bdesc_spe_evsel;
6090   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6091     if (d->code == fcode)
6092       return spe_expand_evsel_builtin (d->icode, arglist, target);
6093
6094   switch (fcode)
6095     {
6096     case SPE_BUILTIN_EVSTDDX:
6097       return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6098     case SPE_BUILTIN_EVSTDHX:
6099       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6100     case SPE_BUILTIN_EVSTDWX:
6101       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6102     case SPE_BUILTIN_EVSTWHEX:
6103       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6104     case SPE_BUILTIN_EVSTWHOX:
6105       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6106     case SPE_BUILTIN_EVSTWWEX:
6107       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6108     case SPE_BUILTIN_EVSTWWOX:
6109       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6110     case SPE_BUILTIN_EVSTDD:
6111       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6112     case SPE_BUILTIN_EVSTDH:
6113       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6114     case SPE_BUILTIN_EVSTDW:
6115       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6116     case SPE_BUILTIN_EVSTWHE:
6117       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6118     case SPE_BUILTIN_EVSTWHO:
6119       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6120     case SPE_BUILTIN_EVSTWWE:
6121       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6122     case SPE_BUILTIN_EVSTWWO:
6123       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6124     case SPE_BUILTIN_MFSPEFSCR:
6125       icode = CODE_FOR_spe_mfspefscr;
6126       tmode = insn_data[icode].operand[0].mode;
6127
6128       if (target == 0
6129           || GET_MODE (target) != tmode
6130           || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6131         target = gen_reg_rtx (tmode);
6132
6133       pat = GEN_FCN (icode) (target);
6134       if (! pat)
6135         return 0;
6136       emit_insn (pat);
6137       return target;
6138     case SPE_BUILTIN_MTSPEFSCR:
6139       icode = CODE_FOR_spe_mtspefscr;
6140       arg0 = TREE_VALUE (arglist);
6141       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6142       mode0 = insn_data[icode].operand[0].mode;
6143
6144       if (arg0 == error_mark_node)
6145         return const0_rtx;
6146
6147       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6148         op0 = copy_to_mode_reg (mode0, op0);
6149
6150       pat = GEN_FCN (icode) (op0);
6151       if (pat)
6152         emit_insn (pat);
6153       return NULL_RTX;
6154     default:
6155       break;
6156     }
6157
6158   *expandedp = false;
6159   return NULL_RTX;
6160 }
6161
6162 static rtx
6163 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6164 {
6165   rtx pat, scratch, tmp;
6166   tree form = TREE_VALUE (arglist);
6167   tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6168   tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6169   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6170   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6171   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6172   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6173   int form_int;
6174   enum rtx_code code;
6175
6176   if (TREE_CODE (form) != INTEGER_CST)
6177     {
6178       error ("argument 1 of __builtin_spe_predicate must be a constant");
6179       return const0_rtx;
6180     }
6181   else
6182     form_int = TREE_INT_CST_LOW (form);
6183
6184   if (mode0 != mode1)
6185     abort ();
6186
6187   if (arg0 == error_mark_node || arg1 == error_mark_node)
6188     return const0_rtx;
6189
6190   if (target == 0
6191       || GET_MODE (target) != SImode
6192       || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6193     target = gen_reg_rtx (SImode);
6194
6195   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6196     op0 = copy_to_mode_reg (mode0, op0);
6197   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6198     op1 = copy_to_mode_reg (mode1, op1);
6199
6200   scratch = gen_reg_rtx (CCmode);
6201
6202   pat = GEN_FCN (icode) (scratch, op0, op1);
6203   if (! pat)
6204     return const0_rtx;
6205   emit_insn (pat);
6206
6207   /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6208      _lower_.  We use one compare, but look in different bits of the
6209      CR for each variant.
6210
6211      There are 2 elements in each SPE simd type (upper/lower).  The CR
6212      bits are set as follows:
6213
6214      BIT0  | BIT 1  | BIT 2   | BIT 3
6215      U     |   L    | (U | L) | (U & L)
6216
6217      So, for an "all" relationship, BIT 3 would be set.
6218      For an "any" relationship, BIT 2 would be set.  Etc.
6219
6220      Following traditional nomenclature, these bits map to:
6221
6222      BIT0  | BIT 1  | BIT 2   | BIT 3
6223      LT    | GT     | EQ      | OV
6224
6225      Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6226   */
6227
6228   switch (form_int)
6229     {
6230       /* All variant.  OV bit.  */
6231     case 0:
6232       /* We need to get to the OV bit, which is the ORDERED bit.  We
6233          could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6234          that's ugly and will trigger a validate_condition_mode abort.
6235          So let's just use another pattern.  */
6236       emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6237       return target;
6238       /* Any variant.  EQ bit.  */
6239     case 1:
6240       code = EQ;
6241       break;
6242       /* Upper variant.  LT bit.  */
6243     case 2:
6244       code = LT;
6245       break;
6246       /* Lower variant.  GT bit.  */
6247     case 3:
6248       code = GT;
6249       break;
6250     default:
6251       error ("argument 1 of __builtin_spe_predicate is out of range");
6252       return const0_rtx;
6253     }
6254
6255   tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6256   emit_move_insn (target, tmp);
6257
6258   return target;
6259 }
6260
6261 /* The evsel builtins look like this:
6262
6263      e = __builtin_spe_evsel_OP (a, b, c, d);
6264
6265    and work like this:
6266
6267      e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6268      e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6269 */
6270
6271 static rtx
6272 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6273 {
6274   rtx pat, scratch;
6275   tree arg0 = TREE_VALUE (arglist);
6276   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6277   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6278   tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6279   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6280   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6281   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6282   rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6283   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6284   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6285
6286   if (mode0 != mode1)
6287     abort ();
6288
6289   if (arg0 == error_mark_node || arg1 == error_mark_node
6290       || arg2 == error_mark_node || arg3 == error_mark_node)
6291     return const0_rtx;
6292
6293   if (target == 0
6294       || GET_MODE (target) != mode0
6295       || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6296     target = gen_reg_rtx (mode0);
6297
6298   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6299     op0 = copy_to_mode_reg (mode0, op0);
6300   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6301     op1 = copy_to_mode_reg (mode0, op1);
6302   if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6303     op2 = copy_to_mode_reg (mode0, op2);
6304   if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6305     op3 = copy_to_mode_reg (mode0, op3);
6306
6307   /* Generate the compare.  */
6308   scratch = gen_reg_rtx (CCmode);
6309   pat = GEN_FCN (icode) (scratch, op0, op1);
6310   if (! pat)
6311     return const0_rtx;
6312   emit_insn (pat);
6313
6314   if (mode0 == V2SImode)
6315     emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6316   else
6317     emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6318
6319   return target;
6320 }
6321
6322 /* Expand an expression EXP that calls a built-in function,
6323    with result going to TARGET if that's convenient
6324    (and in mode MODE if that's convenient).
6325    SUBTARGET may be used as the target for computing one of EXP's operands.
6326    IGNORE is nonzero if the value is to be ignored.  */
6327
6328 static rtx
6329 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6330                       enum machine_mode mode ATTRIBUTE_UNUSED,
6331                       int ignore ATTRIBUTE_UNUSED)
6332 {
6333   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6334   tree arglist = TREE_OPERAND (exp, 1);
6335   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6336   struct builtin_description *d;
6337   size_t i;
6338   rtx ret;
6339   bool success;
6340
6341   if (TARGET_ALTIVEC)
6342     {
6343       ret = altivec_expand_builtin (exp, target, &success);
6344
6345       if (success)
6346         return ret;
6347     }
6348   if (TARGET_SPE)
6349     {
6350       ret = spe_expand_builtin (exp, target, &success);
6351
6352       if (success)
6353         return ret;
6354     }
6355
6356   if (TARGET_ALTIVEC || TARGET_SPE)
6357     {
6358       /* Handle simple unary operations.  */
6359       d = (struct builtin_description *) bdesc_1arg;
6360       for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
6361         if (d->code == fcode)
6362           return rs6000_expand_unop_builtin (d->icode, arglist, target);
6363
6364       /* Handle simple binary operations.  */
6365       d = (struct builtin_description *) bdesc_2arg;
6366       for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
6367         if (d->code == fcode)
6368           return rs6000_expand_binop_builtin (d->icode, arglist, target);
6369
6370       /* Handle simple ternary operations.  */
6371       d = (struct builtin_description *) bdesc_3arg;
6372       for (i = 0; i < ARRAY_SIZE  (bdesc_3arg); i++, d++)
6373         if (d->code == fcode)
6374           return rs6000_expand_ternop_builtin (d->icode, arglist, target);
6375     }
6376
6377   abort ();
6378   return NULL_RTX;
6379 }
6380
6381 static void
6382 rs6000_init_builtins (void)
6383 {
6384   opaque_V2SI_type_node = copy_node (V2SI_type_node);
6385   opaque_V2SF_type_node = copy_node (V2SF_type_node);
6386   opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
6387
6388   if (TARGET_SPE)
6389     spe_init_builtins ();
6390   if (TARGET_ALTIVEC)
6391     altivec_init_builtins ();
6392   if (TARGET_ALTIVEC || TARGET_SPE)
6393     rs6000_common_init_builtins ();
6394 }
6395
6396 /* Search through a set of builtins and enable the mask bits.
6397    DESC is an array of builtins.
6398    SIZE is the total number of builtins.
6399    START is the builtin enum at which to start.
6400    END is the builtin enum at which to end.  */
6401 static void
6402 enable_mask_for_builtins (struct builtin_description *desc, int size,
6403                           enum rs6000_builtins start,
6404                           enum rs6000_builtins end)
6405 {
6406   int i;
6407
6408   for (i = 0; i < size; ++i)
6409     if (desc[i].code == start)
6410       break;
6411
6412   if (i == size)
6413     return;
6414
6415   for (; i < size; ++i)
6416     {
6417       /* Flip all the bits on.  */
6418       desc[i].mask = target_flags;
6419       if (desc[i].code == end)
6420         break;
6421     }
6422 }
6423
6424 static void
6425 spe_init_builtins (void)
6426 {
6427   tree endlink = void_list_node;
6428   tree puint_type_node = build_pointer_type (unsigned_type_node);
6429   tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
6430   struct builtin_description *d;
6431   size_t i;
6432
6433   tree v2si_ftype_4_v2si
6434     = build_function_type
6435     (opaque_V2SI_type_node,
6436      tree_cons (NULL_TREE, opaque_V2SI_type_node,
6437                 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6438                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6439                                       tree_cons (NULL_TREE, opaque_V2SI_type_node,
6440                                                  endlink)))));
6441
6442   tree v2sf_ftype_4_v2sf
6443     = build_function_type
6444     (opaque_V2SF_type_node,
6445      tree_cons (NULL_TREE, opaque_V2SF_type_node,
6446                 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6447                            tree_cons (NULL_TREE, opaque_V2SF_type_node,
6448                                       tree_cons (NULL_TREE, opaque_V2SF_type_node,
6449                                                  endlink)))));
6450
6451   tree int_ftype_int_v2si_v2si
6452     = build_function_type
6453     (integer_type_node,
6454      tree_cons (NULL_TREE, integer_type_node,
6455                 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6456                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6457                                       endlink))));
6458
6459   tree int_ftype_int_v2sf_v2sf
6460     = build_function_type
6461     (integer_type_node,
6462      tree_cons (NULL_TREE, integer_type_node,
6463                 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6464                            tree_cons (NULL_TREE, opaque_V2SF_type_node,
6465                                       endlink))));
6466
6467   tree void_ftype_v2si_puint_int
6468     = build_function_type (void_type_node,
6469                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6470                                       tree_cons (NULL_TREE, puint_type_node,
6471                                                  tree_cons (NULL_TREE,
6472                                                             integer_type_node,
6473                                                             endlink))));
6474
6475   tree void_ftype_v2si_puint_char
6476     = build_function_type (void_type_node,
6477                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6478                                       tree_cons (NULL_TREE, puint_type_node,
6479                                                  tree_cons (NULL_TREE,
6480                                                             char_type_node,
6481                                                             endlink))));
6482
6483   tree void_ftype_v2si_pv2si_int
6484     = build_function_type (void_type_node,
6485                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6486                                       tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6487                                                  tree_cons (NULL_TREE,
6488                                                             integer_type_node,
6489                                                             endlink))));
6490
6491   tree void_ftype_v2si_pv2si_char
6492     = build_function_type (void_type_node,
6493                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6494                                       tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6495                                                  tree_cons (NULL_TREE,
6496                                                             char_type_node,
6497                                                             endlink))));
6498
6499   tree void_ftype_int
6500     = build_function_type (void_type_node,
6501                            tree_cons (NULL_TREE, integer_type_node, endlink));
6502
6503   tree int_ftype_void
6504     = build_function_type (integer_type_node, endlink);
6505
6506   tree v2si_ftype_pv2si_int
6507     = build_function_type (opaque_V2SI_type_node,
6508                            tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6509                                       tree_cons (NULL_TREE, integer_type_node,
6510                                                  endlink)));
6511
6512   tree v2si_ftype_puint_int
6513     = build_function_type (opaque_V2SI_type_node,
6514                            tree_cons (NULL_TREE, puint_type_node,
6515                                       tree_cons (NULL_TREE, integer_type_node,
6516                                                  endlink)));
6517
6518   tree v2si_ftype_pushort_int
6519     = build_function_type (opaque_V2SI_type_node,
6520                            tree_cons (NULL_TREE, pushort_type_node,
6521                                       tree_cons (NULL_TREE, integer_type_node,
6522                                                  endlink)));
6523
6524   tree v2si_ftype_signed_char
6525     = build_function_type (opaque_V2SI_type_node,
6526                            tree_cons (NULL_TREE, signed_char_type_node,
6527                                       endlink));
6528
6529   /* The initialization of the simple binary and unary builtins is
6530      done in rs6000_common_init_builtins, but we have to enable the
6531      mask bits here manually because we have run out of `target_flags'
6532      bits.  We really need to redesign this mask business.  */
6533
6534   enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
6535                             ARRAY_SIZE (bdesc_2arg),
6536                             SPE_BUILTIN_EVADDW,
6537                             SPE_BUILTIN_EVXOR);
6538   enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
6539                             ARRAY_SIZE (bdesc_1arg),
6540                             SPE_BUILTIN_EVABS,
6541                             SPE_BUILTIN_EVSUBFUSIAAW);
6542   enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
6543                             ARRAY_SIZE (bdesc_spe_predicates),
6544                             SPE_BUILTIN_EVCMPEQ,
6545                             SPE_BUILTIN_EVFSTSTLT);
6546   enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
6547                             ARRAY_SIZE (bdesc_spe_evsel),
6548                             SPE_BUILTIN_EVSEL_CMPGTS,
6549                             SPE_BUILTIN_EVSEL_FSTSTEQ);
6550
6551   (*lang_hooks.decls.pushdecl)
6552     (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
6553                  opaque_V2SI_type_node));
6554
6555   /* Initialize irregular SPE builtins.  */
6556
6557   def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
6558   def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
6559   def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
6560   def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
6561   def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
6562   def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
6563   def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
6564   def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
6565   def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
6566   def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
6567   def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
6568   def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
6569   def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
6570   def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
6571   def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
6572   def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
6573   def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
6574   def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
6575
6576   /* Loads.  */
6577   def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
6578   def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
6579   def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
6580   def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
6581   def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
6582   def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
6583   def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
6584   def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
6585   def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
6586   def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
6587   def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
6588   def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
6589   def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
6590   def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
6591   def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
6592   def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
6593   def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
6594   def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
6595   def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
6596   def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
6597   def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
6598   def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
6599
6600   /* Predicates.  */
6601   d = (struct builtin_description *) bdesc_spe_predicates;
6602   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
6603     {
6604       tree type;
6605
6606       switch (insn_data[d->icode].operand[1].mode)
6607         {
6608         case V2SImode:
6609           type = int_ftype_int_v2si_v2si;
6610           break;
6611         case V2SFmode:
6612           type = int_ftype_int_v2sf_v2sf;
6613           break;
6614         default:
6615           abort ();
6616         }
6617
6618       def_builtin (d->mask, d->name, type, d->code);
6619     }
6620
6621   /* Evsel predicates.  */
6622   d = (struct builtin_description *) bdesc_spe_evsel;
6623   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
6624     {
6625       tree type;
6626
6627       switch (insn_data[d->icode].operand[1].mode)
6628         {
6629         case V2SImode:
6630           type = v2si_ftype_4_v2si;
6631           break;
6632         case V2SFmode:
6633           type = v2sf_ftype_4_v2sf;
6634           break;
6635         default:
6636           abort ();
6637         }
6638
6639       def_builtin (d->mask, d->name, type, d->code);
6640     }
6641 }
6642
6643 static void
6644 altivec_init_builtins (void)
6645 {
6646   struct builtin_description *d;
6647   struct builtin_description_predicates *dp;
6648   size_t i;
6649   tree pfloat_type_node = build_pointer_type (float_type_node);
6650   tree pint_type_node = build_pointer_type (integer_type_node);
6651   tree pshort_type_node = build_pointer_type (short_integer_type_node);
6652   tree pchar_type_node = build_pointer_type (char_type_node);
6653
6654   tree pvoid_type_node = build_pointer_type (void_type_node);
6655
6656   tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
6657   tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
6658   tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
6659   tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
6660
6661   tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
6662
6663   tree int_ftype_int_v4si_v4si
6664     = build_function_type_list (integer_type_node,
6665                                 integer_type_node, V4SI_type_node,
6666                                 V4SI_type_node, NULL_TREE);
6667   tree v4sf_ftype_pcfloat
6668     = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
6669   tree void_ftype_pfloat_v4sf
6670     = build_function_type_list (void_type_node,
6671                                 pfloat_type_node, V4SF_type_node, NULL_TREE);
6672   tree v4si_ftype_pcint
6673     = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
6674   tree void_ftype_pint_v4si
6675     = build_function_type_list (void_type_node,
6676                                 pint_type_node, V4SI_type_node, NULL_TREE);
6677   tree v8hi_ftype_pcshort
6678     = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
6679   tree void_ftype_pshort_v8hi
6680     = build_function_type_list (void_type_node,
6681                                 pshort_type_node, V8HI_type_node, NULL_TREE);
6682   tree v16qi_ftype_pcchar
6683     = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
6684   tree void_ftype_pchar_v16qi
6685     = build_function_type_list (void_type_node,
6686                                 pchar_type_node, V16QI_type_node, NULL_TREE);
6687   tree void_ftype_v4si
6688     = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
6689   tree v8hi_ftype_void
6690     = build_function_type (V8HI_type_node, void_list_node);
6691   tree void_ftype_void
6692     = build_function_type (void_type_node, void_list_node);
6693   tree void_ftype_qi
6694     = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
6695
6696   tree v16qi_ftype_long_pcvoid
6697     = build_function_type_list (V16QI_type_node,
6698                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6699   tree v8hi_ftype_long_pcvoid
6700     = build_function_type_list (V8HI_type_node,
6701                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6702   tree v4si_ftype_long_pcvoid
6703     = build_function_type_list (V4SI_type_node,
6704                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6705
6706   tree void_ftype_v4si_long_pvoid
6707     = build_function_type_list (void_type_node,
6708                                 V4SI_type_node, long_integer_type_node,
6709                                 pvoid_type_node, NULL_TREE);
6710   tree void_ftype_v16qi_long_pvoid
6711     = build_function_type_list (void_type_node,
6712                                 V16QI_type_node, long_integer_type_node,
6713                                 pvoid_type_node, NULL_TREE);
6714   tree void_ftype_v8hi_long_pvoid
6715     = build_function_type_list (void_type_node,
6716                                 V8HI_type_node, long_integer_type_node,
6717                                 pvoid_type_node, NULL_TREE);
6718   tree int_ftype_int_v8hi_v8hi
6719     = build_function_type_list (integer_type_node,
6720                                 integer_type_node, V8HI_type_node,
6721                                 V8HI_type_node, NULL_TREE);
6722   tree int_ftype_int_v16qi_v16qi
6723     = build_function_type_list (integer_type_node,
6724                                 integer_type_node, V16QI_type_node,
6725                                 V16QI_type_node, NULL_TREE);
6726   tree int_ftype_int_v4sf_v4sf
6727     = build_function_type_list (integer_type_node,
6728                                 integer_type_node, V4SF_type_node,
6729                                 V4SF_type_node, NULL_TREE);
6730   tree v4si_ftype_v4si
6731     = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
6732   tree v8hi_ftype_v8hi
6733     = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
6734   tree v16qi_ftype_v16qi
6735     = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
6736   tree v4sf_ftype_v4sf
6737     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6738   tree void_ftype_pcvoid_int_char
6739     = build_function_type_list (void_type_node,
6740                                 pcvoid_type_node, integer_type_node,
6741                                 char_type_node, NULL_TREE);
6742
6743   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
6744                ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
6745   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
6746                ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
6747   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
6748                ALTIVEC_BUILTIN_LD_INTERNAL_4si);
6749   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
6750                ALTIVEC_BUILTIN_ST_INTERNAL_4si);
6751   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
6752                ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
6753   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
6754                ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
6755   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
6756                ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
6757   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
6758                ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
6759   def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
6760   def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
6761   def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
6762   def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
6763   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
6764   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
6765   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
6766   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
6767   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
6768   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
6769   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
6770   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
6771   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
6772   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
6773   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
6774   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
6775
6776   /* Add the DST variants.  */
6777   d = (struct builtin_description *) bdesc_dst;
6778   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6779     def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code);
6780
6781   /* Initialize the predicates.  */
6782   dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6783   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6784     {
6785       enum machine_mode mode1;
6786       tree type;
6787
6788       mode1 = insn_data[dp->icode].operand[1].mode;
6789
6790       switch (mode1)
6791         {
6792         case V4SImode:
6793           type = int_ftype_int_v4si_v4si;
6794           break;
6795         case V8HImode:
6796           type = int_ftype_int_v8hi_v8hi;
6797           break;
6798         case V16QImode:
6799           type = int_ftype_int_v16qi_v16qi;
6800           break;
6801         case V4SFmode:
6802           type = int_ftype_int_v4sf_v4sf;
6803           break;
6804         default:
6805           abort ();
6806         }
6807
6808       def_builtin (dp->mask, dp->name, type, dp->code);
6809     }
6810
6811   /* Initialize the abs* operators.  */
6812   d = (struct builtin_description *) bdesc_abs;
6813   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6814     {
6815       enum machine_mode mode0;
6816       tree type;
6817
6818       mode0 = insn_data[d->icode].operand[0].mode;
6819
6820       switch (mode0)
6821         {
6822         case V4SImode:
6823           type = v4si_ftype_v4si;
6824           break;
6825         case V8HImode:
6826           type = v8hi_ftype_v8hi;
6827           break;
6828         case V16QImode:
6829           type = v16qi_ftype_v16qi;
6830           break;
6831         case V4SFmode:
6832           type = v4sf_ftype_v4sf;
6833           break;
6834         default:
6835           abort ();
6836         }
6837
6838       def_builtin (d->mask, d->name, type, d->code);
6839     }
6840 }
6841
6842 static void
6843 rs6000_common_init_builtins (void)
6844 {
6845   struct builtin_description *d;
6846   size_t i;
6847
6848   tree v4sf_ftype_v4sf_v4sf_v16qi
6849     = build_function_type_list (V4SF_type_node,
6850                                 V4SF_type_node, V4SF_type_node,
6851                                 V16QI_type_node, NULL_TREE);
6852   tree v4si_ftype_v4si_v4si_v16qi
6853     = build_function_type_list (V4SI_type_node,
6854                                 V4SI_type_node, V4SI_type_node,
6855                                 V16QI_type_node, NULL_TREE);
6856   tree v8hi_ftype_v8hi_v8hi_v16qi
6857     = build_function_type_list (V8HI_type_node,
6858                                 V8HI_type_node, V8HI_type_node,
6859                                 V16QI_type_node, NULL_TREE);
6860   tree v16qi_ftype_v16qi_v16qi_v16qi
6861     = build_function_type_list (V16QI_type_node,
6862                                 V16QI_type_node, V16QI_type_node,
6863                                 V16QI_type_node, NULL_TREE);
6864   tree v4si_ftype_char
6865     = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE);
6866   tree v8hi_ftype_char
6867     = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE);
6868   tree v16qi_ftype_char
6869     = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE);
6870   tree v8hi_ftype_v16qi
6871     = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
6872   tree v4sf_ftype_v4sf
6873     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6874
6875   tree v2si_ftype_v2si_v2si
6876     = build_function_type_list (opaque_V2SI_type_node,
6877                                 opaque_V2SI_type_node,
6878                                 opaque_V2SI_type_node, NULL_TREE);
6879
6880   tree v2sf_ftype_v2sf_v2sf
6881     = build_function_type_list (opaque_V2SF_type_node,
6882                                 opaque_V2SF_type_node,
6883                                 opaque_V2SF_type_node, NULL_TREE);
6884
6885   tree v2si_ftype_int_int
6886     = build_function_type_list (opaque_V2SI_type_node,
6887                                 integer_type_node, integer_type_node,
6888                                 NULL_TREE);
6889
6890   tree v2si_ftype_v2si
6891     = build_function_type_list (opaque_V2SI_type_node,
6892                                 opaque_V2SI_type_node, NULL_TREE);
6893
6894   tree v2sf_ftype_v2sf
6895     = build_function_type_list (opaque_V2SF_type_node,
6896                                 opaque_V2SF_type_node, NULL_TREE);
6897
6898   tree v2sf_ftype_v2si
6899     = build_function_type_list (opaque_V2SF_type_node,
6900                                 opaque_V2SI_type_node, NULL_TREE);
6901
6902   tree v2si_ftype_v2sf
6903     = build_function_type_list (opaque_V2SI_type_node,
6904                                 opaque_V2SF_type_node, NULL_TREE);
6905
6906   tree v2si_ftype_v2si_char
6907     = build_function_type_list (opaque_V2SI_type_node,
6908                                 opaque_V2SI_type_node,
6909                                 char_type_node, NULL_TREE);
6910
6911   tree v2si_ftype_int_char
6912     = build_function_type_list (opaque_V2SI_type_node,
6913                                 integer_type_node, char_type_node, NULL_TREE);
6914
6915   tree v2si_ftype_char
6916     = build_function_type_list (opaque_V2SI_type_node,
6917                                 char_type_node, NULL_TREE);
6918
6919   tree int_ftype_int_int
6920     = build_function_type_list (integer_type_node,
6921                                 integer_type_node, integer_type_node,
6922                                 NULL_TREE);
6923
6924   tree v4si_ftype_v4si_v4si
6925     = build_function_type_list (V4SI_type_node,
6926                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
6927   tree v4sf_ftype_v4si_char
6928     = build_function_type_list (V4SF_type_node,
6929                                 V4SI_type_node, char_type_node, NULL_TREE);
6930   tree v4si_ftype_v4sf_char
6931     = build_function_type_list (V4SI_type_node,
6932                                 V4SF_type_node, char_type_node, NULL_TREE);
6933   tree v4si_ftype_v4si_char
6934     = build_function_type_list (V4SI_type_node,
6935                                 V4SI_type_node, char_type_node, NULL_TREE);
6936   tree v8hi_ftype_v8hi_char
6937     = build_function_type_list (V8HI_type_node,
6938                                 V8HI_type_node, char_type_node, NULL_TREE);
6939   tree v16qi_ftype_v16qi_char
6940     = build_function_type_list (V16QI_type_node,
6941                                 V16QI_type_node, char_type_node, NULL_TREE);
6942   tree v16qi_ftype_v16qi_v16qi_char
6943     = build_function_type_list (V16QI_type_node,
6944                                 V16QI_type_node, V16QI_type_node,
6945                                 char_type_node, NULL_TREE);
6946   tree v8hi_ftype_v8hi_v8hi_char
6947     = build_function_type_list (V8HI_type_node,
6948                                 V8HI_type_node, V8HI_type_node,
6949                                 char_type_node, NULL_TREE);
6950   tree v4si_ftype_v4si_v4si_char
6951     = build_function_type_list (V4SI_type_node,
6952                                 V4SI_type_node, V4SI_type_node,
6953                                 char_type_node, NULL_TREE);
6954   tree v4sf_ftype_v4sf_v4sf_char
6955     = build_function_type_list (V4SF_type_node,
6956                                 V4SF_type_node, V4SF_type_node,
6957                                 char_type_node, NULL_TREE);
6958   tree v4sf_ftype_v4sf_v4sf
6959     = build_function_type_list (V4SF_type_node,
6960                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
6961   tree v4sf_ftype_v4sf_v4sf_v4si
6962     = build_function_type_list (V4SF_type_node,
6963                                 V4SF_type_node, V4SF_type_node,
6964                                 V4SI_type_node, NULL_TREE);
6965   tree v4sf_ftype_v4sf_v4sf_v4sf
6966     = build_function_type_list (V4SF_type_node,
6967                                 V4SF_type_node, V4SF_type_node,
6968                                 V4SF_type_node, NULL_TREE);
6969   tree v4si_ftype_v4si_v4si_v4si
6970     = build_function_type_list (V4SI_type_node,
6971                                 V4SI_type_node, V4SI_type_node,
6972                                 V4SI_type_node, NULL_TREE);
6973   tree v8hi_ftype_v8hi_v8hi
6974     = build_function_type_list (V8HI_type_node,
6975                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
6976   tree v8hi_ftype_v8hi_v8hi_v8hi
6977     = build_function_type_list (V8HI_type_node,
6978                                 V8HI_type_node, V8HI_type_node,
6979                                 V8HI_type_node, NULL_TREE);
6980  tree v4si_ftype_v8hi_v8hi_v4si
6981     = build_function_type_list (V4SI_type_node,
6982                                 V8HI_type_node, V8HI_type_node,
6983                                 V4SI_type_node, NULL_TREE);
6984  tree v4si_ftype_v16qi_v16qi_v4si
6985     = build_function_type_list (V4SI_type_node,
6986                                 V16QI_type_node, V16QI_type_node,
6987                                 V4SI_type_node, NULL_TREE);
6988   tree v16qi_ftype_v16qi_v16qi
6989     = build_function_type_list (V16QI_type_node,
6990                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
6991   tree v4si_ftype_v4sf_v4sf
6992     = build_function_type_list (V4SI_type_node,
6993                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
6994   tree v8hi_ftype_v16qi_v16qi
6995     = build_function_type_list (V8HI_type_node,
6996                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
6997   tree v4si_ftype_v8hi_v8hi
6998     = build_function_type_list (V4SI_type_node,
6999                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7000   tree v8hi_ftype_v4si_v4si
7001     = build_function_type_list (V8HI_type_node,
7002                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7003   tree v16qi_ftype_v8hi_v8hi
7004     = build_function_type_list (V16QI_type_node,
7005                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7006   tree v4si_ftype_v16qi_v4si
7007     = build_function_type_list (V4SI_type_node,
7008                                 V16QI_type_node, V4SI_type_node, NULL_TREE);
7009   tree v4si_ftype_v16qi_v16qi
7010     = build_function_type_list (V4SI_type_node,
7011                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7012   tree v4si_ftype_v8hi_v4si
7013     = build_function_type_list (V4SI_type_node,
7014                                 V8HI_type_node, V4SI_type_node, NULL_TREE);
7015   tree v4si_ftype_v8hi
7016     = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7017   tree int_ftype_v4si_v4si
7018     = build_function_type_list (integer_type_node,
7019                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7020   tree int_ftype_v4sf_v4sf
7021     = build_function_type_list (integer_type_node,
7022                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
7023   tree int_ftype_v16qi_v16qi
7024     = build_function_type_list (integer_type_node,
7025                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7026   tree int_ftype_v8hi_v8hi
7027     = build_function_type_list (integer_type_node,
7028                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7029
7030   /* Add the simple ternary operators.  */
7031   d = (struct builtin_description *) bdesc_3arg;
7032   for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7033     {
7034
7035       enum machine_mode mode0, mode1, mode2, mode3;
7036       tree type;
7037
7038       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7039         continue;
7040
7041       mode0 = insn_data[d->icode].operand[0].mode;
7042       mode1 = insn_data[d->icode].operand[1].mode;
7043       mode2 = insn_data[d->icode].operand[2].mode;
7044       mode3 = insn_data[d->icode].operand[3].mode;
7045
7046       /* When all four are of the same mode.  */
7047       if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7048         {
7049           switch (mode0)
7050             {
7051             case V4SImode:
7052               type = v4si_ftype_v4si_v4si_v4si;
7053               break;
7054             case V4SFmode:
7055               type = v4sf_ftype_v4sf_v4sf_v4sf;
7056               break;
7057             case V8HImode:
7058               type = v8hi_ftype_v8hi_v8hi_v8hi;
7059               break;
7060             case V16QImode:
7061               type = v16qi_ftype_v16qi_v16qi_v16qi;
7062               break;
7063             default:
7064               abort();
7065             }
7066         }
7067       else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7068         {
7069           switch (mode0)
7070             {
7071             case V4SImode:
7072               type = v4si_ftype_v4si_v4si_v16qi;
7073               break;
7074             case V4SFmode:
7075               type = v4sf_ftype_v4sf_v4sf_v16qi;
7076               break;
7077             case V8HImode:
7078               type = v8hi_ftype_v8hi_v8hi_v16qi;
7079               break;
7080             case V16QImode:
7081               type = v16qi_ftype_v16qi_v16qi_v16qi;
7082               break;
7083             default:
7084               abort();
7085             }
7086         }
7087       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7088                && mode3 == V4SImode)
7089         type = v4si_ftype_v16qi_v16qi_v4si;
7090       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7091                && mode3 == V4SImode)
7092         type = v4si_ftype_v8hi_v8hi_v4si;
7093       else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7094                && mode3 == V4SImode)
7095         type = v4sf_ftype_v4sf_v4sf_v4si;
7096
7097       /* vchar, vchar, vchar, 4 bit literal.  */
7098       else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7099                && mode3 == QImode)
7100         type = v16qi_ftype_v16qi_v16qi_char;
7101
7102       /* vshort, vshort, vshort, 4 bit literal.  */
7103       else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7104                && mode3 == QImode)
7105         type = v8hi_ftype_v8hi_v8hi_char;
7106
7107       /* vint, vint, vint, 4 bit literal.  */
7108       else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7109                && mode3 == QImode)
7110         type = v4si_ftype_v4si_v4si_char;
7111
7112       /* vfloat, vfloat, vfloat, 4 bit literal.  */
7113       else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7114                && mode3 == QImode)
7115         type = v4sf_ftype_v4sf_v4sf_char;
7116
7117       else
7118         abort ();
7119
7120       def_builtin (d->mask, d->name, type, d->code);
7121     }
7122
7123   /* Add the simple binary operators.  */
7124   d = (struct builtin_description *) bdesc_2arg;
7125   for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7126     {
7127       enum machine_mode mode0, mode1, mode2;
7128       tree type;
7129
7130       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7131         continue;
7132
7133       mode0 = insn_data[d->icode].operand[0].mode;
7134       mode1 = insn_data[d->icode].operand[1].mode;
7135       mode2 = insn_data[d->icode].operand[2].mode;
7136
7137       /* When all three operands are of the same mode.  */
7138       if (mode0 == mode1 && mode1 == mode2)
7139         {
7140           switch (mode0)
7141             {
7142             case V4SFmode:
7143               type = v4sf_ftype_v4sf_v4sf;
7144               break;
7145             case V4SImode:
7146               type = v4si_ftype_v4si_v4si;
7147               break;
7148             case V16QImode:
7149               type = v16qi_ftype_v16qi_v16qi;
7150               break;
7151             case V8HImode:
7152               type = v8hi_ftype_v8hi_v8hi;
7153               break;
7154             case V2SImode:
7155               type = v2si_ftype_v2si_v2si;
7156               break;
7157             case V2SFmode:
7158               type = v2sf_ftype_v2sf_v2sf;
7159               break;
7160             case SImode:
7161               type = int_ftype_int_int;
7162               break;
7163             default:
7164               abort ();
7165             }
7166         }
7167
7168       /* A few other combos we really don't want to do manually.  */
7169
7170       /* vint, vfloat, vfloat.  */
7171       else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7172         type = v4si_ftype_v4sf_v4sf;
7173
7174       /* vshort, vchar, vchar.  */
7175       else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7176         type = v8hi_ftype_v16qi_v16qi;
7177
7178       /* vint, vshort, vshort.  */
7179       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7180         type = v4si_ftype_v8hi_v8hi;
7181
7182       /* vshort, vint, vint.  */
7183       else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7184         type = v8hi_ftype_v4si_v4si;
7185
7186       /* vchar, vshort, vshort.  */
7187       else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7188         type = v16qi_ftype_v8hi_v8hi;
7189
7190       /* vint, vchar, vint.  */
7191       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7192         type = v4si_ftype_v16qi_v4si;
7193
7194       /* vint, vchar, vchar.  */
7195       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7196         type = v4si_ftype_v16qi_v16qi;
7197
7198       /* vint, vshort, vint.  */
7199       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7200         type = v4si_ftype_v8hi_v4si;
7201
7202       /* vint, vint, 5 bit literal.  */
7203       else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7204         type = v4si_ftype_v4si_char;
7205
7206       /* vshort, vshort, 5 bit literal.  */
7207       else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
7208         type = v8hi_ftype_v8hi_char;
7209
7210       /* vchar, vchar, 5 bit literal.  */
7211       else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
7212         type = v16qi_ftype_v16qi_char;
7213
7214       /* vfloat, vint, 5 bit literal.  */
7215       else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
7216         type = v4sf_ftype_v4si_char;
7217
7218       /* vint, vfloat, 5 bit literal.  */
7219       else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
7220         type = v4si_ftype_v4sf_char;
7221
7222       else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
7223         type = v2si_ftype_int_int;
7224
7225       else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
7226         type = v2si_ftype_v2si_char;
7227
7228       else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
7229         type = v2si_ftype_int_char;
7230
7231       /* int, x, x.  */
7232       else if (mode0 == SImode)
7233         {
7234           switch (mode1)
7235             {
7236             case V4SImode:
7237               type = int_ftype_v4si_v4si;
7238               break;
7239             case V4SFmode:
7240               type = int_ftype_v4sf_v4sf;
7241               break;
7242             case V16QImode:
7243               type = int_ftype_v16qi_v16qi;
7244               break;
7245             case V8HImode:
7246               type = int_ftype_v8hi_v8hi;
7247               break;
7248             default:
7249               abort ();
7250             }
7251         }
7252
7253       else
7254         abort ();
7255
7256       def_builtin (d->mask, d->name, type, d->code);
7257     }
7258
7259   /* Add the simple unary operators.  */
7260   d = (struct builtin_description *) bdesc_1arg;
7261   for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7262     {
7263       enum machine_mode mode0, mode1;
7264       tree type;
7265
7266       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7267         continue;
7268
7269       mode0 = insn_data[d->icode].operand[0].mode;
7270       mode1 = insn_data[d->icode].operand[1].mode;
7271
7272       if (mode0 == V4SImode && mode1 == QImode)
7273         type = v4si_ftype_char;
7274       else if (mode0 == V8HImode && mode1 == QImode)
7275         type = v8hi_ftype_char;
7276       else if (mode0 == V16QImode && mode1 == QImode)
7277         type = v16qi_ftype_char;
7278       else if (mode0 == V4SFmode && mode1 == V4SFmode)
7279         type = v4sf_ftype_v4sf;
7280       else if (mode0 == V8HImode && mode1 == V16QImode)
7281         type = v8hi_ftype_v16qi;
7282       else if (mode0 == V4SImode && mode1 == V8HImode)
7283         type = v4si_ftype_v8hi;
7284       else if (mode0 == V2SImode && mode1 == V2SImode)
7285         type = v2si_ftype_v2si;
7286       else if (mode0 == V2SFmode && mode1 == V2SFmode)
7287         type = v2sf_ftype_v2sf;
7288       else if (mode0 == V2SFmode && mode1 == V2SImode)
7289         type = v2sf_ftype_v2si;
7290       else if (mode0 == V2SImode && mode1 == V2SFmode)
7291         type = v2si_ftype_v2sf;
7292       else if (mode0 == V2SImode && mode1 == QImode)
7293         type = v2si_ftype_char;
7294       else
7295         abort ();
7296
7297       def_builtin (d->mask, d->name, type, d->code);
7298     }
7299 }
7300
7301 static void
7302 rs6000_init_libfuncs (void)
7303 {
7304   if (!TARGET_HARD_FLOAT)
7305     return;
7306
7307   if (DEFAULT_ABI != ABI_V4)
7308     {
7309       if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
7310         {
7311           /* AIX library routines for float->int conversion.  */
7312           set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
7313           set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
7314           set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
7315           set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
7316         }
7317
7318       /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines.  */
7319       set_optab_libfunc (add_optab, TFmode, "_xlqadd");
7320       set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
7321       set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
7322       set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
7323     }
7324   else
7325     {
7326       /* 32-bit SVR4 quad floating point routines.  */
7327
7328       set_optab_libfunc (add_optab, TFmode, "_q_add");
7329       set_optab_libfunc (sub_optab, TFmode, "_q_sub");
7330       set_optab_libfunc (neg_optab, TFmode, "_q_neg");
7331       set_optab_libfunc (smul_optab, TFmode, "_q_mul");
7332       set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
7333       if (TARGET_PPC_GPOPT || TARGET_POWER2)
7334         set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
7335
7336       set_optab_libfunc (eq_optab, TFmode, "_q_feq");
7337       set_optab_libfunc (ne_optab, TFmode, "_q_fne");
7338       set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
7339       set_optab_libfunc (ge_optab, TFmode, "_q_fge");
7340       set_optab_libfunc (lt_optab, TFmode, "_q_flt");
7341       set_optab_libfunc (le_optab, TFmode, "_q_fle");
7342
7343       set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
7344       set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
7345       set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
7346       set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
7347       set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
7348       set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
7349       set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
7350     }
7351 }
7352 \f
7353 /* Expand a block move operation, and return 1 if successful.  Return 0
7354    if we should let the compiler generate normal code.
7355
7356    operands[0] is the destination
7357    operands[1] is the source
7358    operands[2] is the length
7359    operands[3] is the alignment */
7360
7361 #define MAX_MOVE_REG 4
7362
7363 int
7364 expand_block_move (rtx operands[])
7365 {
7366   rtx orig_dest = operands[0];
7367   rtx orig_src  = operands[1];
7368   rtx bytes_rtx = operands[2];
7369   rtx align_rtx = operands[3];
7370   int constp    = (GET_CODE (bytes_rtx) == CONST_INT);
7371   int align;
7372   int bytes;
7373   int offset;
7374   int move_bytes;
7375   rtx stores[MAX_MOVE_REG];
7376   int num_reg = 0;
7377
7378   /* If this is not a fixed size move, just call memcpy */
7379   if (! constp)
7380     return 0;
7381
7382   /* If this is not a fixed size alignment, abort */
7383   if (GET_CODE (align_rtx) != CONST_INT)
7384     abort ();
7385   align = INTVAL (align_rtx);
7386
7387   /* Anything to move? */
7388   bytes = INTVAL (bytes_rtx);
7389   if (bytes <= 0)
7390     return 1;
7391
7392   /* store_one_arg depends on expand_block_move to handle at least the size of
7393      reg_parm_stack_space.  */
7394   if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7395     return 0;
7396
7397   for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7398     {
7399       union {
7400         rtx (*movstrsi) (rtx, rtx, rtx, rtx);
7401         rtx (*mov) (rtx, rtx);
7402       } gen_func;
7403       enum machine_mode mode = BLKmode;
7404       rtx src, dest;
7405
7406       if (TARGET_STRING
7407           && bytes > 24         /* move up to 32 bytes at a time */
7408           && ! fixed_regs[5]
7409           && ! fixed_regs[6]
7410           && ! fixed_regs[7]
7411           && ! fixed_regs[8]
7412           && ! fixed_regs[9]
7413           && ! fixed_regs[10]
7414           && ! fixed_regs[11]
7415           && ! fixed_regs[12])
7416         {
7417           move_bytes = (bytes > 32) ? 32 : bytes;
7418           gen_func.movstrsi = gen_movstrsi_8reg;
7419         }
7420       else if (TARGET_STRING
7421                && bytes > 16    /* move up to 24 bytes at a time */
7422                && ! fixed_regs[5]
7423                && ! fixed_regs[6]
7424                && ! fixed_regs[7]
7425                && ! fixed_regs[8]
7426                && ! fixed_regs[9]
7427                && ! fixed_regs[10])
7428         {
7429           move_bytes = (bytes > 24) ? 24 : bytes;
7430           gen_func.movstrsi = gen_movstrsi_6reg;
7431         }
7432       else if (TARGET_STRING
7433                && bytes > 8     /* move up to 16 bytes at a time */
7434                && ! fixed_regs[5]
7435                && ! fixed_regs[6]
7436                && ! fixed_regs[7]
7437                && ! fixed_regs[8])
7438         {
7439           move_bytes = (bytes > 16) ? 16 : bytes;
7440           gen_func.movstrsi = gen_movstrsi_4reg;
7441         }
7442       else if (bytes >= 8 && TARGET_POWERPC64
7443                /* 64-bit loads and stores require word-aligned
7444                   displacements.  */
7445                && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
7446         {
7447           move_bytes = 8;
7448           mode = DImode;
7449           gen_func.mov = gen_movdi;
7450         }
7451       else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
7452         {                       /* move up to 8 bytes at a time */
7453           move_bytes = (bytes > 8) ? 8 : bytes;
7454           gen_func.movstrsi = gen_movstrsi_2reg;
7455         }
7456       else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
7457         {                       /* move 4 bytes */
7458           move_bytes = 4;
7459           mode = SImode;
7460           gen_func.mov = gen_movsi;
7461         }
7462       else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
7463         {                       /* move 2 bytes */
7464           move_bytes = 2;
7465           mode = HImode;
7466           gen_func.mov = gen_movhi;
7467         }
7468       else if (TARGET_STRING && bytes > 1)
7469         {                       /* move up to 4 bytes at a time */
7470           move_bytes = (bytes > 4) ? 4 : bytes;
7471           gen_func.movstrsi = gen_movstrsi_1reg;
7472         }
7473       else /* move 1 byte at a time */
7474         {
7475           move_bytes = 1;
7476           mode = QImode;
7477           gen_func.mov = gen_movqi;
7478         }
7479
7480       src = adjust_address (orig_src, mode, offset);
7481       dest = adjust_address (orig_dest, mode, offset);
7482
7483       if (mode != BLKmode)
7484         {
7485           rtx tmp_reg = gen_reg_rtx (mode);
7486
7487           emit_insn ((*gen_func.mov) (tmp_reg, src));
7488           stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
7489         }
7490
7491       if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
7492         {
7493           int i;
7494           for (i = 0; i < num_reg; i++)
7495             emit_insn (stores[i]);
7496           num_reg = 0;
7497         }
7498
7499       if (mode == BLKmode)
7500         {
7501           /* Move the address into scratch registers.  The movstrsi
7502              patterns require zero offset.  */
7503           if (!REG_P (XEXP (src, 0)))
7504             {
7505               rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
7506               src = replace_equiv_address (src, src_reg);
7507             }
7508           set_mem_size (src, GEN_INT (move_bytes));
7509
7510           if (!REG_P (XEXP (dest, 0)))
7511             {
7512               rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
7513               dest = replace_equiv_address (dest, dest_reg);
7514             }
7515           set_mem_size (dest, GEN_INT (move_bytes));
7516
7517           emit_insn ((*gen_func.movstrsi) (dest, src,
7518                                            GEN_INT (move_bytes & 31),
7519                                            align_rtx));
7520         }
7521     }
7522
7523   return 1;
7524 }
7525
7526 \f
7527 /* Return 1 if OP is a load multiple operation.  It is known to be a
7528    PARALLEL and the first section will be tested.  */
7529
7530 int
7531 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7532 {
7533   int count = XVECLEN (op, 0);
7534   unsigned int dest_regno;
7535   rtx src_addr;
7536   int i;
7537
7538   /* Perform a quick check so we don't blow up below.  */
7539   if (count <= 1
7540       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7541       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7542       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7543     return 0;
7544
7545   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7546   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7547
7548   for (i = 1; i < count; i++)
7549     {
7550       rtx elt = XVECEXP (op, 0, i);
7551
7552       if (GET_CODE (elt) != SET
7553           || GET_CODE (SET_DEST (elt)) != REG
7554           || GET_MODE (SET_DEST (elt)) != SImode
7555           || REGNO (SET_DEST (elt)) != dest_regno + i
7556           || GET_CODE (SET_SRC (elt)) != MEM
7557           || GET_MODE (SET_SRC (elt)) != SImode
7558           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
7559           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
7560           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
7561           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
7562         return 0;
7563     }
7564
7565   return 1;
7566 }
7567
7568 /* Similar, but tests for store multiple.  Here, the second vector element
7569    is a CLOBBER.  It will be tested later.  */
7570
7571 int
7572 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7573 {
7574   int count = XVECLEN (op, 0) - 1;
7575   unsigned int src_regno;
7576   rtx dest_addr;
7577   int i;
7578
7579   /* Perform a quick check so we don't blow up below.  */
7580   if (count <= 1
7581       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7582       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7583       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7584     return 0;
7585
7586   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7587   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7588
7589   for (i = 1; i < count; i++)
7590     {
7591       rtx elt = XVECEXP (op, 0, i + 1);
7592
7593       if (GET_CODE (elt) != SET
7594           || GET_CODE (SET_SRC (elt)) != REG
7595           || GET_MODE (SET_SRC (elt)) != SImode
7596           || REGNO (SET_SRC (elt)) != src_regno + i
7597           || GET_CODE (SET_DEST (elt)) != MEM
7598           || GET_MODE (SET_DEST (elt)) != SImode
7599           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
7600           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
7601           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
7602           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
7603         return 0;
7604     }
7605
7606   return 1;
7607 }
7608
7609 /* Return a string to perform a load_multiple operation.
7610    operands[0] is the vector.
7611    operands[1] is the source address.
7612    operands[2] is the first destination register.  */
7613
7614 const char *
7615 rs6000_output_load_multiple (rtx operands[3])
7616 {
7617   /* We have to handle the case where the pseudo used to contain the address
7618      is assigned to one of the output registers.  */
7619   int i, j;
7620   int words = XVECLEN (operands[0], 0);
7621   rtx xop[10];
7622
7623   if (XVECLEN (operands[0], 0) == 1)
7624     return "{l|lwz} %2,0(%1)";
7625
7626   for (i = 0; i < words; i++)
7627     if (refers_to_regno_p (REGNO (operands[2]) + i,
7628                            REGNO (operands[2]) + i + 1, operands[1], 0))
7629       {
7630         if (i == words-1)
7631           {
7632             xop[0] = GEN_INT (4 * (words-1));
7633             xop[1] = operands[1];
7634             xop[2] = operands[2];
7635             output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
7636             return "";
7637           }
7638         else if (i == 0)
7639           {
7640             xop[0] = GEN_INT (4 * (words-1));
7641             xop[1] = operands[1];
7642             xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7643             output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
7644             return "";
7645           }
7646         else
7647           {
7648             for (j = 0; j < words; j++)
7649               if (j != i)
7650                 {
7651                   xop[0] = GEN_INT (j * 4);
7652                   xop[1] = operands[1];
7653                   xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
7654                   output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
7655                 }
7656             xop[0] = GEN_INT (i * 4);
7657             xop[1] = operands[1];
7658             output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
7659             return "";
7660           }
7661       }
7662
7663   return "{lsi|lswi} %2,%1,%N0";
7664 }
7665
7666 /* Return 1 for a parallel vrsave operation.  */
7667
7668 int
7669 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7670 {
7671   int count = XVECLEN (op, 0);
7672   unsigned int dest_regno, src_regno;
7673   int i;
7674
7675   if (count <= 1
7676       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7677       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7678       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
7679     return 0;
7680
7681   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7682   src_regno  = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7683
7684   if (dest_regno != VRSAVE_REGNO
7685       && src_regno != VRSAVE_REGNO)
7686     return 0;
7687
7688   for (i = 1; i < count; i++)
7689     {
7690       rtx elt = XVECEXP (op, 0, i);
7691
7692       if (GET_CODE (elt) != CLOBBER
7693           && GET_CODE (elt) != SET)
7694         return 0;
7695     }
7696
7697   return 1;
7698 }
7699
7700 /* Return 1 for an PARALLEL suitable for mfcr.  */
7701
7702 int
7703 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7704 {
7705   int count = XVECLEN (op, 0);
7706   int i;
7707
7708   /* Perform a quick check so we don't blow up below.  */
7709   if (count < 1
7710       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7711       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7712       || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7713     return 0;
7714
7715   for (i = 0; i < count; i++)
7716     {
7717       rtx exp = XVECEXP (op, 0, i);
7718       rtx unspec;
7719       int maskval;
7720       rtx src_reg;
7721
7722       src_reg = XVECEXP (SET_SRC (exp), 0, 0);
7723
7724       if (GET_CODE (src_reg) != REG
7725           || GET_MODE (src_reg) != CCmode
7726           || ! CR_REGNO_P (REGNO (src_reg)))
7727         return 0;
7728
7729       if (GET_CODE (exp) != SET
7730           || GET_CODE (SET_DEST (exp)) != REG
7731           || GET_MODE (SET_DEST (exp)) != SImode
7732           || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
7733         return 0;
7734       unspec = SET_SRC (exp);
7735       maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
7736
7737       if (GET_CODE (unspec) != UNSPEC
7738           || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
7739           || XVECLEN (unspec, 0) != 2
7740           || XVECEXP (unspec, 0, 0) != src_reg
7741           || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7742           || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7743         return 0;
7744     }
7745   return 1;
7746 }
7747
7748 /* Return 1 for an PARALLEL suitable for mtcrf.  */
7749
7750 int
7751 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7752 {
7753   int count = XVECLEN (op, 0);
7754   int i;
7755   rtx src_reg;
7756
7757   /* Perform a quick check so we don't blow up below.  */
7758   if (count < 1
7759       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7760       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7761       || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7762     return 0;
7763   src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
7764
7765   if (GET_CODE (src_reg) != REG
7766       || GET_MODE (src_reg) != SImode
7767       || ! INT_REGNO_P (REGNO (src_reg)))
7768     return 0;
7769
7770   for (i = 0; i < count; i++)
7771     {
7772       rtx exp = XVECEXP (op, 0, i);
7773       rtx unspec;
7774       int maskval;
7775
7776       if (GET_CODE (exp) != SET
7777           || GET_CODE (SET_DEST (exp)) != REG
7778           || GET_MODE (SET_DEST (exp)) != CCmode
7779           || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
7780         return 0;
7781       unspec = SET_SRC (exp);
7782       maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
7783
7784       if (GET_CODE (unspec) != UNSPEC
7785           || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
7786           || XVECLEN (unspec, 0) != 2
7787           || XVECEXP (unspec, 0, 0) != src_reg
7788           || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7789           || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7790         return 0;
7791     }
7792   return 1;
7793 }
7794
7795 /* Return 1 for an PARALLEL suitable for lmw.  */
7796
7797 int
7798 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7799 {
7800   int count = XVECLEN (op, 0);
7801   unsigned int dest_regno;
7802   rtx src_addr;
7803   unsigned int base_regno;
7804   HOST_WIDE_INT offset;
7805   int i;
7806
7807   /* Perform a quick check so we don't blow up below.  */
7808   if (count <= 1
7809       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7810       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7811       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7812     return 0;
7813
7814   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7815   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7816
7817   if (dest_regno > 31
7818       || count != 32 - (int) dest_regno)
7819     return 0;
7820
7821   if (legitimate_indirect_address_p (src_addr, 0))
7822     {
7823       offset = 0;
7824       base_regno = REGNO (src_addr);
7825       if (base_regno == 0)
7826         return 0;
7827     }
7828   else if (legitimate_offset_address_p (SImode, src_addr, 0))
7829     {
7830       offset = INTVAL (XEXP (src_addr, 1));
7831       base_regno = REGNO (XEXP (src_addr, 0));
7832     }
7833   else
7834     return 0;
7835
7836   for (i = 0; i < count; i++)
7837     {
7838       rtx elt = XVECEXP (op, 0, i);
7839       rtx newaddr;
7840       rtx addr_reg;
7841       HOST_WIDE_INT newoffset;
7842
7843       if (GET_CODE (elt) != SET
7844           || GET_CODE (SET_DEST (elt)) != REG
7845           || GET_MODE (SET_DEST (elt)) != SImode
7846           || REGNO (SET_DEST (elt)) != dest_regno + i
7847           || GET_CODE (SET_SRC (elt)) != MEM
7848           || GET_MODE (SET_SRC (elt)) != SImode)
7849         return 0;
7850       newaddr = XEXP (SET_SRC (elt), 0);
7851       if (legitimate_indirect_address_p (newaddr, 0))
7852         {
7853           newoffset = 0;
7854           addr_reg = newaddr;
7855         }
7856       else if (legitimate_offset_address_p (SImode, newaddr, 0))
7857         {
7858           addr_reg = XEXP (newaddr, 0);
7859           newoffset = INTVAL (XEXP (newaddr, 1));
7860         }
7861       else
7862         return 0;
7863       if (REGNO (addr_reg) != base_regno
7864           || newoffset != offset + 4 * i)
7865         return 0;
7866     }
7867
7868   return 1;
7869 }
7870
7871 /* Return 1 for an PARALLEL suitable for stmw.  */
7872
7873 int
7874 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7875 {
7876   int count = XVECLEN (op, 0);
7877   unsigned int src_regno;
7878   rtx dest_addr;
7879   unsigned int base_regno;
7880   HOST_WIDE_INT offset;
7881   int i;
7882
7883   /* Perform a quick check so we don't blow up below.  */
7884   if (count <= 1
7885       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7886       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7887       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7888     return 0;
7889
7890   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7891   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7892
7893   if (src_regno > 31
7894       || count != 32 - (int) src_regno)
7895     return 0;
7896
7897   if (legitimate_indirect_address_p (dest_addr, 0))
7898     {
7899       offset = 0;
7900       base_regno = REGNO (dest_addr);
7901       if (base_regno == 0)
7902         return 0;
7903     }
7904   else if (legitimate_offset_address_p (SImode, dest_addr, 0))
7905     {
7906       offset = INTVAL (XEXP (dest_addr, 1));
7907       base_regno = REGNO (XEXP (dest_addr, 0));
7908     }
7909   else
7910     return 0;
7911
7912   for (i = 0; i < count; i++)
7913     {
7914       rtx elt = XVECEXP (op, 0, i);
7915       rtx newaddr;
7916       rtx addr_reg;
7917       HOST_WIDE_INT newoffset;
7918
7919       if (GET_CODE (elt) != SET
7920           || GET_CODE (SET_SRC (elt)) != REG
7921           || GET_MODE (SET_SRC (elt)) != SImode
7922           || REGNO (SET_SRC (elt)) != src_regno + i
7923           || GET_CODE (SET_DEST (elt)) != MEM
7924           || GET_MODE (SET_DEST (elt)) != SImode)
7925         return 0;
7926       newaddr = XEXP (SET_DEST (elt), 0);
7927       if (legitimate_indirect_address_p (newaddr, 0))
7928         {
7929           newoffset = 0;
7930           addr_reg = newaddr;
7931         }
7932       else if (legitimate_offset_address_p (SImode, newaddr, 0))
7933         {
7934           addr_reg = XEXP (newaddr, 0);
7935           newoffset = INTVAL (XEXP (newaddr, 1));
7936         }
7937       else
7938         return 0;
7939       if (REGNO (addr_reg) != base_regno
7940           || newoffset != offset + 4 * i)
7941         return 0;
7942     }
7943
7944   return 1;
7945 }
7946 \f
7947 /* A validation routine: say whether CODE, a condition code, and MODE
7948    match.  The other alternatives either don't make sense or should
7949    never be generated.  */
7950
7951 static void
7952 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
7953 {
7954   if (GET_RTX_CLASS (code) != '<'
7955       || GET_MODE_CLASS (mode) != MODE_CC)
7956     abort ();
7957
7958   /* These don't make sense.  */
7959   if ((code == GT || code == LT || code == GE || code == LE)
7960       && mode == CCUNSmode)
7961     abort ();
7962
7963   if ((code == GTU || code == LTU || code == GEU || code == LEU)
7964       && mode != CCUNSmode)
7965     abort ();
7966
7967   if (mode != CCFPmode
7968       && (code == ORDERED || code == UNORDERED
7969           || code == UNEQ || code == LTGT
7970           || code == UNGT || code == UNLT
7971           || code == UNGE || code == UNLE))
7972     abort ();
7973
7974   /* These should never be generated except for
7975      flag_finite_math_only.  */
7976   if (mode == CCFPmode
7977       && ! flag_finite_math_only
7978       && (code == LE || code == GE
7979           || code == UNEQ || code == LTGT
7980           || code == UNGT || code == UNLT))
7981     abort ();
7982
7983   /* These are invalid; the information is not there.  */
7984   if (mode == CCEQmode
7985       && code != EQ && code != NE)
7986     abort ();
7987 }
7988
7989 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
7990    We only check the opcode against the mode of the CC value here.  */
7991
7992 int
7993 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7994 {
7995   enum rtx_code code = GET_CODE (op);
7996   enum machine_mode cc_mode;
7997
7998   if (GET_RTX_CLASS (code) != '<')
7999     return 0;
8000
8001   cc_mode = GET_MODE (XEXP (op, 0));
8002   if (GET_MODE_CLASS (cc_mode) != MODE_CC)
8003     return 0;
8004
8005   validate_condition_mode (code, cc_mode);
8006
8007   return 1;
8008 }
8009
8010 /* Return 1 if OP is a comparison operation that is valid for a branch
8011    insn and which is true if the corresponding bit in the CC register
8012    is set.  */
8013
8014 int
8015 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
8016 {
8017   enum rtx_code code;
8018
8019   if (! branch_comparison_operator (op, mode))
8020     return 0;
8021
8022   code = GET_CODE (op);
8023   return (code == EQ || code == LT || code == GT
8024           || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
8025           || code == LTU || code == GTU
8026           || code == UNORDERED);
8027 }
8028
8029 /* Return 1 if OP is a comparison operation that is valid for an scc
8030    insn: it must be a positive comparison.  */
8031
8032 int
8033 scc_comparison_operator (rtx op, enum machine_mode mode)
8034 {
8035   return branch_positive_comparison_operator (op, mode);
8036 }
8037
8038 int
8039 trap_comparison_operator (rtx op, enum machine_mode mode)
8040 {
8041   if (mode != VOIDmode && mode != GET_MODE (op))
8042     return 0;
8043   return GET_RTX_CLASS (GET_CODE (op)) == '<';
8044 }
8045
8046 int
8047 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8048 {
8049   enum rtx_code code = GET_CODE (op);
8050   return (code == AND || code == IOR || code == XOR);
8051 }
8052
8053 int
8054 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8055 {
8056   enum rtx_code code = GET_CODE (op);
8057   return (code == IOR || code == XOR);
8058 }
8059
8060 int
8061 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8062 {
8063   enum rtx_code code = GET_CODE (op);
8064   return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
8065 }
8066 \f
8067 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8068    mask required to convert the result of a rotate insn into a shift
8069    left insn of SHIFTOP bits.  Both are known to be SImode CONST_INT.  */
8070
8071 int
8072 includes_lshift_p (rtx shiftop, rtx andop)
8073 {
8074   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8075
8076   shift_mask <<= INTVAL (shiftop);
8077
8078   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8079 }
8080
8081 /* Similar, but for right shift.  */
8082
8083 int
8084 includes_rshift_p (rtx shiftop, rtx andop)
8085 {
8086   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8087
8088   shift_mask >>= INTVAL (shiftop);
8089
8090   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8091 }
8092
8093 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8094    to perform a left shift.  It must have exactly SHIFTOP least
8095    significant 0's, then one or more 1's, then zero or more 0's.  */
8096
8097 int
8098 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8099 {
8100   if (GET_CODE (andop) == CONST_INT)
8101     {
8102       HOST_WIDE_INT c, lsb, shift_mask;
8103
8104       c = INTVAL (andop);
8105       if (c == 0 || c == ~0)
8106         return 0;
8107
8108       shift_mask = ~0;
8109       shift_mask <<= INTVAL (shiftop);
8110
8111       /* Find the least significant one bit.  */
8112       lsb = c & -c;
8113
8114       /* It must coincide with the LSB of the shift mask.  */
8115       if (-lsb != shift_mask)
8116         return 0;
8117
8118       /* Invert to look for the next transition (if any).  */
8119       c = ~c;
8120
8121       /* Remove the low group of ones (originally low group of zeros).  */
8122       c &= -lsb;
8123
8124       /* Again find the lsb, and check we have all 1's above.  */
8125       lsb = c & -c;
8126       return c == -lsb;
8127     }
8128   else if (GET_CODE (andop) == CONST_DOUBLE
8129            && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8130     {
8131       HOST_WIDE_INT low, high, lsb;
8132       HOST_WIDE_INT shift_mask_low, shift_mask_high;
8133
8134       low = CONST_DOUBLE_LOW (andop);
8135       if (HOST_BITS_PER_WIDE_INT < 64)
8136         high = CONST_DOUBLE_HIGH (andop);
8137
8138       if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8139           || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8140         return 0;
8141
8142       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8143         {
8144           shift_mask_high = ~0;
8145           if (INTVAL (shiftop) > 32)
8146             shift_mask_high <<= INTVAL (shiftop) - 32;
8147
8148           lsb = high & -high;
8149
8150           if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8151             return 0;
8152
8153           high = ~high;
8154           high &= -lsb;
8155
8156           lsb = high & -high;
8157           return high == -lsb;
8158         }
8159
8160       shift_mask_low = ~0;
8161       shift_mask_low <<= INTVAL (shiftop);
8162
8163       lsb = low & -low;
8164
8165       if (-lsb != shift_mask_low)
8166         return 0;
8167
8168       if (HOST_BITS_PER_WIDE_INT < 64)
8169         high = ~high;
8170       low = ~low;
8171       low &= -lsb;
8172
8173       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8174         {
8175           lsb = high & -high;
8176           return high == -lsb;
8177         }
8178
8179       lsb = low & -low;
8180       return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8181     }
8182   else
8183     return 0;
8184 }
8185
8186 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8187    to perform a left shift.  It must have SHIFTOP or more least
8188    significant 0's, with the remainder of the word 1's.  */
8189
8190 int
8191 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8192 {
8193   if (GET_CODE (andop) == CONST_INT)
8194     {
8195       HOST_WIDE_INT c, lsb, shift_mask;
8196
8197       shift_mask = ~0;
8198       shift_mask <<= INTVAL (shiftop);
8199       c = INTVAL (andop);
8200
8201       /* Find the least significant one bit.  */
8202       lsb = c & -c;
8203
8204       /* It must be covered by the shift mask.
8205          This test also rejects c == 0.  */
8206       if ((lsb & shift_mask) == 0)
8207         return 0;
8208
8209       /* Check we have all 1's above the transition, and reject all 1's.  */
8210       return c == -lsb && lsb != 1;
8211     }
8212   else if (GET_CODE (andop) == CONST_DOUBLE
8213            && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8214     {
8215       HOST_WIDE_INT low, lsb, shift_mask_low;
8216
8217       low = CONST_DOUBLE_LOW (andop);
8218
8219       if (HOST_BITS_PER_WIDE_INT < 64)
8220         {
8221           HOST_WIDE_INT high, shift_mask_high;
8222
8223           high = CONST_DOUBLE_HIGH (andop);
8224
8225           if (low == 0)
8226             {
8227               shift_mask_high = ~0;
8228               if (INTVAL (shiftop) > 32)
8229                 shift_mask_high <<= INTVAL (shiftop) - 32;
8230
8231               lsb = high & -high;
8232
8233               if ((lsb & shift_mask_high) == 0)
8234                 return 0;
8235
8236               return high == -lsb;
8237             }
8238           if (high != ~0)
8239             return 0;
8240         }
8241
8242       shift_mask_low = ~0;
8243       shift_mask_low <<= INTVAL (shiftop);
8244
8245       lsb = low & -low;
8246
8247       if ((lsb & shift_mask_low) == 0)
8248         return 0;
8249
8250       return low == -lsb && lsb != 1;
8251     }
8252   else
8253     return 0;
8254 }
8255
8256 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8257    for lfq and stfq insns.
8258
8259    Note reg1 and reg2 *must* be hard registers.  To be sure we will
8260    abort if we are passed pseudo registers.  */
8261
8262 int
8263 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8264 {
8265   /* We might have been passed a SUBREG.  */
8266   if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8267     return 0;
8268
8269   return (REGNO (reg1) == REGNO (reg2) - 1);
8270 }
8271
8272 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8273    addr1 and addr2 must be in consecutive memory locations
8274    (addr2 == addr1 + 8).  */
8275
8276 int
8277 addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
8278 {
8279   unsigned int reg1;
8280   int offset1;
8281
8282   /* Extract an offset (if used) from the first addr.  */
8283   if (GET_CODE (addr1) == PLUS)
8284     {
8285       /* If not a REG, return zero.  */
8286       if (GET_CODE (XEXP (addr1, 0)) != REG)
8287         return 0;
8288       else
8289         {
8290           reg1 = REGNO (XEXP (addr1, 0));
8291           /* The offset must be constant!  */
8292           if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8293             return 0;
8294           offset1 = INTVAL (XEXP (addr1, 1));
8295         }
8296     }
8297   else if (GET_CODE (addr1) != REG)
8298     return 0;
8299   else
8300     {
8301       reg1 = REGNO (addr1);
8302       /* This was a simple (mem (reg)) expression.  Offset is 0.  */
8303       offset1 = 0;
8304     }
8305
8306   /* Make sure the second address is a (mem (plus (reg) (const_int)))
8307       or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8308       register as addr1.  */
8309   if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8310    return 1;
8311   if (GET_CODE (addr2) != PLUS)
8312     return 0;
8313
8314   if (GET_CODE (XEXP (addr2, 0)) != REG
8315       || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8316     return 0;
8317
8318   if (reg1 != REGNO (XEXP (addr2, 0)))
8319     return 0;
8320
8321   /* The offset for the second addr must be 8 more than the first addr.  */
8322   if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8323     return 0;
8324
8325   /* All the tests passed.  addr1 and addr2 are valid for lfq or stfq
8326      instructions.  */
8327   return 1;
8328 }
8329 \f
8330 /* Return the register class of a scratch register needed to copy IN into
8331    or out of a register in CLASS in MODE.  If it can be done directly,
8332    NO_REGS is returned.  */
8333
8334 enum reg_class
8335 secondary_reload_class (enum reg_class class,
8336                         enum machine_mode mode ATTRIBUTE_UNUSED,
8337                         rtx in)
8338 {
8339   int regno;
8340
8341   if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8342 #if TARGET_MACHO
8343                     && MACHOPIC_INDIRECT
8344 #endif
8345                     ))
8346     {
8347       /* We cannot copy a symbolic operand directly into anything
8348          other than BASE_REGS for TARGET_ELF.  So indicate that a
8349          register from BASE_REGS is needed as an intermediate
8350          register.
8351
8352          On Darwin, pic addresses require a load from memory, which
8353          needs a base register.  */
8354       if (class != BASE_REGS
8355           && (GET_CODE (in) == SYMBOL_REF
8356               || GET_CODE (in) == HIGH
8357               || GET_CODE (in) == LABEL_REF
8358               || GET_CODE (in) == CONST))
8359         return BASE_REGS;
8360     }
8361
8362   if (GET_CODE (in) == REG)
8363     {
8364       regno = REGNO (in);
8365       if (regno >= FIRST_PSEUDO_REGISTER)
8366         {
8367           regno = true_regnum (in);
8368           if (regno >= FIRST_PSEUDO_REGISTER)
8369             regno = -1;
8370         }
8371     }
8372   else if (GET_CODE (in) == SUBREG)
8373     {
8374       regno = true_regnum (in);
8375       if (regno >= FIRST_PSEUDO_REGISTER)
8376         regno = -1;
8377     }
8378   else
8379     regno = -1;
8380
8381   /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8382      into anything.  */
8383   if (class == GENERAL_REGS || class == BASE_REGS
8384       || (regno >= 0 && INT_REGNO_P (regno)))
8385     return NO_REGS;
8386
8387   /* Constants, memory, and FP registers can go into FP registers.  */
8388   if ((regno == -1 || FP_REGNO_P (regno))
8389       && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8390     return NO_REGS;
8391
8392   /* Memory, and AltiVec registers can go into AltiVec registers.  */
8393   if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8394       && class == ALTIVEC_REGS)
8395     return NO_REGS;
8396
8397   /* We can copy among the CR registers.  */
8398   if ((class == CR_REGS || class == CR0_REGS)
8399       && regno >= 0 && CR_REGNO_P (regno))
8400     return NO_REGS;
8401
8402   /* Otherwise, we need GENERAL_REGS.  */
8403   return GENERAL_REGS;
8404 }
8405 \f
8406 /* Given a comparison operation, return the bit number in CCR to test.  We
8407    know this is a valid comparison.
8408
8409    SCC_P is 1 if this is for an scc.  That means that %D will have been
8410    used instead of %C, so the bits will be in different places.
8411
8412    Return -1 if OP isn't a valid comparison for some reason.  */
8413
8414 int
8415 ccr_bit (rtx op, int scc_p)
8416 {
8417   enum rtx_code code = GET_CODE (op);
8418   enum machine_mode cc_mode;
8419   int cc_regnum;
8420   int base_bit;
8421   rtx reg;
8422
8423   if (GET_RTX_CLASS (code) != '<')
8424     return -1;
8425
8426   reg = XEXP (op, 0);
8427
8428   if (GET_CODE (reg) != REG
8429       || ! CR_REGNO_P (REGNO (reg)))
8430     abort ();
8431
8432   cc_mode = GET_MODE (reg);
8433   cc_regnum = REGNO (reg);
8434   base_bit = 4 * (cc_regnum - CR0_REGNO);
8435
8436   validate_condition_mode (code, cc_mode);
8437
8438   /* When generating a sCOND operation, only positive conditions are
8439      allowed.  */
8440   if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8441       && code != GTU && code != LTU)
8442     abort ();
8443
8444   switch (code)
8445     {
8446     case NE:
8447       if (TARGET_E500 && !TARGET_FPRS
8448           && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8449         return base_bit + 1;
8450       return scc_p ? base_bit + 3 : base_bit + 2;
8451     case EQ:
8452       if (TARGET_E500 && !TARGET_FPRS
8453           && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8454         return base_bit + 1;
8455       return base_bit + 2;
8456     case GT:  case GTU:  case UNLE:
8457       return base_bit + 1;
8458     case LT:  case LTU:  case UNGE:
8459       return base_bit;
8460     case ORDERED:  case UNORDERED:
8461       return base_bit + 3;
8462
8463     case GE:  case GEU:
8464       /* If scc, we will have done a cror to put the bit in the
8465          unordered position.  So test that bit.  For integer, this is ! LT
8466          unless this is an scc insn.  */
8467       return scc_p ? base_bit + 3 : base_bit;
8468
8469     case LE:  case LEU:
8470       return scc_p ? base_bit + 3 : base_bit + 1;
8471
8472     default:
8473       abort ();
8474     }
8475 }
8476 \f
8477 /* Return the GOT register.  */
8478
8479 struct rtx_def *
8480 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8481 {
8482   /* The second flow pass currently (June 1999) can't update
8483      regs_ever_live without disturbing other parts of the compiler, so
8484      update it here to make the prolog/epilogue code happy.  */
8485   if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8486     regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8487
8488   current_function_uses_pic_offset_table = 1;
8489
8490   return pic_offset_table_rtx;
8491 }
8492 \f
8493 /* Function to init struct machine_function.
8494    This will be called, via a pointer variable,
8495    from push_function_context.  */
8496
8497 static struct machine_function *
8498 rs6000_init_machine_status (void)
8499 {
8500   return ggc_alloc_cleared (sizeof (machine_function));
8501 }
8502 \f
8503 /* These macros test for integers and extract the low-order bits.  */
8504 #define INT_P(X)  \
8505 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)    \
8506  && GET_MODE (X) == VOIDmode)
8507
8508 #define INT_LOWPART(X) \
8509   (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8510
8511 int
8512 extract_MB (rtx op)
8513 {
8514   int i;
8515   unsigned long val = INT_LOWPART (op);
8516
8517   /* If the high bit is zero, the value is the first 1 bit we find
8518      from the left.  */
8519   if ((val & 0x80000000) == 0)
8520     {
8521       if ((val & 0xffffffff) == 0)
8522         abort ();
8523
8524       i = 1;
8525       while (((val <<= 1) & 0x80000000) == 0)
8526         ++i;
8527       return i;
8528     }
8529
8530   /* If the high bit is set and the low bit is not, or the mask is all
8531      1's, the value is zero.  */
8532   if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
8533     return 0;
8534
8535   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
8536      from the right.  */
8537   i = 31;
8538   while (((val >>= 1) & 1) != 0)
8539     --i;
8540
8541   return i;
8542 }
8543
8544 int
8545 extract_ME (rtx op)
8546 {
8547   int i;
8548   unsigned long val = INT_LOWPART (op);
8549
8550   /* If the low bit is zero, the value is the first 1 bit we find from
8551      the right.  */
8552   if ((val & 1) == 0)
8553     {
8554       if ((val & 0xffffffff) == 0)
8555         abort ();
8556
8557       i = 30;
8558       while (((val >>= 1) & 1) == 0)
8559         --i;
8560
8561       return i;
8562     }
8563
8564   /* If the low bit is set and the high bit is not, or the mask is all
8565      1's, the value is 31.  */
8566   if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
8567     return 31;
8568
8569   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
8570      from the left.  */
8571   i = 0;
8572   while (((val <<= 1) & 0x80000000) != 0)
8573     ++i;
8574
8575   return i;
8576 }
8577
8578 /* Locate some local-dynamic symbol still in use by this function
8579    so that we can print its name in some tls_ld pattern.  */
8580
8581 static const char *
8582 rs6000_get_some_local_dynamic_name (void)
8583 {
8584   rtx insn;
8585
8586   if (cfun->machine->some_ld_name)
8587     return cfun->machine->some_ld_name;
8588
8589   for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8590     if (INSN_P (insn)
8591         && for_each_rtx (&PATTERN (insn),
8592                          rs6000_get_some_local_dynamic_name_1, 0))
8593       return cfun->machine->some_ld_name;
8594
8595   abort ();
8596 }
8597
8598 /* Helper function for rs6000_get_some_local_dynamic_name.  */
8599
8600 static int
8601 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8602 {
8603   rtx x = *px;
8604
8605   if (GET_CODE (x) == SYMBOL_REF)
8606     {
8607       const char *str = XSTR (x, 0);
8608       if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8609         {
8610           cfun->machine->some_ld_name = str;
8611           return 1;
8612         }
8613     }
8614
8615   return 0;
8616 }
8617
8618 /* Print an operand.  Recognize special options, documented below.  */
8619
8620 #if TARGET_ELF
8621 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8622 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
8623 #else
8624 #define SMALL_DATA_RELOC "sda21"
8625 #define SMALL_DATA_REG 0
8626 #endif
8627
8628 void
8629 print_operand (FILE *file, rtx x, int code)
8630 {
8631   int i;
8632   HOST_WIDE_INT val;
8633   unsigned HOST_WIDE_INT uval;
8634
8635   switch (code)
8636     {
8637     case '.':
8638       /* Write out an instruction after the call which may be replaced
8639          with glue code by the loader.  This depends on the AIX version.  */
8640       asm_fprintf (file, RS6000_CALL_GLUE);
8641       return;
8642
8643       /* %a is output_address.  */
8644
8645     case 'A':
8646       /* If X is a constant integer whose low-order 5 bits are zero,
8647          write 'l'.  Otherwise, write 'r'.  This is a kludge to fix a bug
8648          in the AIX assembler where "sri" with a zero shift count
8649          writes a trash instruction.  */
8650       if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
8651         putc ('l', file);
8652       else
8653         putc ('r', file);
8654       return;
8655
8656     case 'b':
8657       /* If constant, low-order 16 bits of constant, unsigned.
8658          Otherwise, write normally.  */
8659       if (INT_P (x))
8660         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
8661       else
8662         print_operand (file, x, 0);
8663       return;
8664
8665     case 'B':
8666       /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
8667          for 64-bit mask direction.  */
8668       putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
8669       return;
8670
8671       /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
8672          output_operand.  */
8673
8674     case 'E':
8675       /* X is a CR register.  Print the number of the EQ bit of the CR */
8676       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8677         output_operand_lossage ("invalid %%E value");
8678       else
8679         fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
8680       return;
8681
8682     case 'f':
8683       /* X is a CR register.  Print the shift count needed to move it
8684          to the high-order four bits.  */
8685       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8686         output_operand_lossage ("invalid %%f value");
8687       else
8688         fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
8689       return;
8690
8691     case 'F':
8692       /* Similar, but print the count for the rotate in the opposite
8693          direction.  */
8694       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8695         output_operand_lossage ("invalid %%F value");
8696       else
8697         fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
8698       return;
8699
8700     case 'G':
8701       /* X is a constant integer.  If it is negative, print "m",
8702          otherwise print "z".  This is to make an aze or ame insn.  */
8703       if (GET_CODE (x) != CONST_INT)
8704         output_operand_lossage ("invalid %%G value");
8705       else if (INTVAL (x) >= 0)
8706         putc ('z', file);
8707       else
8708         putc ('m', file);
8709       return;
8710
8711     case 'h':
8712       /* If constant, output low-order five bits.  Otherwise, write
8713          normally.  */
8714       if (INT_P (x))
8715         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
8716       else
8717         print_operand (file, x, 0);
8718       return;
8719
8720     case 'H':
8721       /* If constant, output low-order six bits.  Otherwise, write
8722          normally.  */
8723       if (INT_P (x))
8724         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
8725       else
8726         print_operand (file, x, 0);
8727       return;
8728
8729     case 'I':
8730       /* Print `i' if this is a constant, else nothing.  */
8731       if (INT_P (x))
8732         putc ('i', file);
8733       return;
8734
8735     case 'j':
8736       /* Write the bit number in CCR for jump.  */
8737       i = ccr_bit (x, 0);
8738       if (i == -1)
8739         output_operand_lossage ("invalid %%j code");
8740       else
8741         fprintf (file, "%d", i);
8742       return;
8743
8744     case 'J':
8745       /* Similar, but add one for shift count in rlinm for scc and pass
8746          scc flag to `ccr_bit'.  */
8747       i = ccr_bit (x, 1);
8748       if (i == -1)
8749         output_operand_lossage ("invalid %%J code");
8750       else
8751         /* If we want bit 31, write a shift count of zero, not 32.  */
8752         fprintf (file, "%d", i == 31 ? 0 : i + 1);
8753       return;
8754
8755     case 'k':
8756       /* X must be a constant.  Write the 1's complement of the
8757          constant.  */
8758       if (! INT_P (x))
8759         output_operand_lossage ("invalid %%k value");
8760       else
8761         fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
8762       return;
8763
8764     case 'K':
8765       /* X must be a symbolic constant on ELF.  Write an
8766          expression suitable for an 'addi' that adds in the low 16
8767          bits of the MEM.  */
8768       if (GET_CODE (x) != CONST)
8769         {
8770           print_operand_address (file, x);
8771           fputs ("@l", file);
8772         }
8773       else
8774         {
8775           if (GET_CODE (XEXP (x, 0)) != PLUS
8776               || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
8777                   && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
8778               || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
8779             output_operand_lossage ("invalid %%K value");
8780           print_operand_address (file, XEXP (XEXP (x, 0), 0));
8781           fputs ("@l", file);
8782           /* For GNU as, there must be a non-alphanumeric character
8783              between 'l' and the number.  The '-' is added by
8784              print_operand() already.  */
8785           if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
8786             fputs ("+", file);
8787           print_operand (file, XEXP (XEXP (x, 0), 1), 0);
8788         }
8789       return;
8790
8791       /* %l is output_asm_label.  */
8792
8793     case 'L':
8794       /* Write second word of DImode or DFmode reference.  Works on register
8795          or non-indexed memory only.  */
8796       if (GET_CODE (x) == REG)
8797         fprintf (file, "%s", reg_names[REGNO (x) + 1]);
8798       else if (GET_CODE (x) == MEM)
8799         {
8800           /* Handle possible auto-increment.  Since it is pre-increment and
8801              we have already done it, we can just use an offset of word.  */
8802           if (GET_CODE (XEXP (x, 0)) == PRE_INC
8803               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
8804             output_address (plus_constant (XEXP (XEXP (x, 0), 0),
8805                                            UNITS_PER_WORD));
8806           else
8807             output_address (XEXP (adjust_address_nv (x, SImode,
8808                                                      UNITS_PER_WORD),
8809                                   0));
8810
8811           if (small_data_operand (x, GET_MODE (x)))
8812             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
8813                      reg_names[SMALL_DATA_REG]);
8814         }
8815       return;
8816
8817     case 'm':
8818       /* MB value for a mask operand.  */
8819       if (! mask_operand (x, SImode))
8820         output_operand_lossage ("invalid %%m value");
8821
8822       fprintf (file, "%d", extract_MB (x));
8823       return;
8824
8825     case 'M':
8826       /* ME value for a mask operand.  */
8827       if (! mask_operand (x, SImode))
8828         output_operand_lossage ("invalid %%M value");
8829
8830       fprintf (file, "%d", extract_ME (x));
8831       return;
8832
8833       /* %n outputs the negative of its operand.  */
8834
8835     case 'N':
8836       /* Write the number of elements in the vector times 4.  */
8837       if (GET_CODE (x) != PARALLEL)
8838         output_operand_lossage ("invalid %%N value");
8839       else
8840         fprintf (file, "%d", XVECLEN (x, 0) * 4);
8841       return;
8842
8843     case 'O':
8844       /* Similar, but subtract 1 first.  */
8845       if (GET_CODE (x) != PARALLEL)
8846         output_operand_lossage ("invalid %%O value");
8847       else
8848         fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
8849       return;
8850
8851     case 'p':
8852       /* X is a CONST_INT that is a power of two.  Output the logarithm.  */
8853       if (! INT_P (x)
8854           || INT_LOWPART (x) < 0
8855           || (i = exact_log2 (INT_LOWPART (x))) < 0)
8856         output_operand_lossage ("invalid %%p value");
8857       else
8858         fprintf (file, "%d", i);
8859       return;
8860
8861     case 'P':
8862       /* The operand must be an indirect memory reference.  The result
8863          is the register number.  */
8864       if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
8865           || REGNO (XEXP (x, 0)) >= 32)
8866         output_operand_lossage ("invalid %%P value");
8867       else
8868         fprintf (file, "%d", REGNO (XEXP (x, 0)));
8869       return;
8870
8871     case 'q':
8872       /* This outputs the logical code corresponding to a boolean
8873          expression.  The expression may have one or both operands
8874          negated (if one, only the first one).  For condition register
8875          logical operations, it will also treat the negated
8876          CR codes as NOTs, but not handle NOTs of them.  */
8877       {
8878         const char *const *t = 0;
8879         const char *s;
8880         enum rtx_code code = GET_CODE (x);
8881         static const char * const tbl[3][3] = {
8882           { "and", "andc", "nor" },
8883           { "or", "orc", "nand" },
8884           { "xor", "eqv", "xor" } };
8885
8886         if (code == AND)
8887           t = tbl[0];
8888         else if (code == IOR)
8889           t = tbl[1];
8890         else if (code == XOR)
8891           t = tbl[2];
8892         else
8893           output_operand_lossage ("invalid %%q value");
8894
8895         if (GET_CODE (XEXP (x, 0)) != NOT)
8896           s = t[0];
8897         else
8898           {
8899             if (GET_CODE (XEXP (x, 1)) == NOT)
8900               s = t[2];
8901             else
8902               s = t[1];
8903           }
8904
8905         fputs (s, file);
8906       }
8907       return;
8908
8909     case 'Q':
8910       if (TARGET_MFCRF)
8911         fputc (',',file);
8912         /* FALLTHRU */
8913       else
8914         return;
8915
8916     case 'R':
8917       /* X is a CR register.  Print the mask for `mtcrf'.  */
8918       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8919         output_operand_lossage ("invalid %%R value");
8920       else
8921         fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
8922       return;
8923
8924     case 's':
8925       /* Low 5 bits of 32 - value */
8926       if (! INT_P (x))
8927         output_operand_lossage ("invalid %%s value");
8928       else
8929         fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
8930       return;
8931
8932     case 'S':
8933       /* PowerPC64 mask position.  All 0's is excluded.
8934          CONST_INT 32-bit mask is considered sign-extended so any
8935          transition must occur within the CONST_INT, not on the boundary.  */
8936       if (! mask64_operand (x, DImode))
8937         output_operand_lossage ("invalid %%S value");
8938
8939       uval = INT_LOWPART (x);
8940
8941       if (uval & 1)     /* Clear Left */
8942         {
8943 #if HOST_BITS_PER_WIDE_INT > 64
8944           uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8945 #endif
8946           i = 64;
8947         }
8948       else              /* Clear Right */
8949         {
8950           uval = ~uval;
8951 #if HOST_BITS_PER_WIDE_INT > 64
8952           uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8953 #endif
8954           i = 63;
8955         }
8956       while (uval != 0)
8957         --i, uval >>= 1;
8958       if (i < 0)
8959         abort ();
8960       fprintf (file, "%d", i);
8961       return;
8962
8963     case 't':
8964       /* Like 'J' but get to the OVERFLOW/UNORDERED bit.  */
8965       if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
8966         abort ();
8967
8968       /* Bit 3 is OV bit.  */
8969       i = 4 * (REGNO (x) - CR0_REGNO) + 3;
8970
8971       /* If we want bit 31, write a shift count of zero, not 32.  */
8972       fprintf (file, "%d", i == 31 ? 0 : i + 1);
8973       return;
8974
8975     case 'T':
8976       /* Print the symbolic name of a branch target register.  */
8977       if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
8978                                   && REGNO (x) != COUNT_REGISTER_REGNUM))
8979         output_operand_lossage ("invalid %%T value");
8980       else if (REGNO (x) == LINK_REGISTER_REGNUM)
8981         fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
8982       else
8983         fputs ("ctr", file);
8984       return;
8985
8986     case 'u':
8987       /* High-order 16 bits of constant for use in unsigned operand.  */
8988       if (! INT_P (x))
8989         output_operand_lossage ("invalid %%u value");
8990       else
8991         fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8992                  (INT_LOWPART (x) >> 16) & 0xffff);
8993       return;
8994
8995     case 'v':
8996       /* High-order 16 bits of constant for use in signed operand.  */
8997       if (! INT_P (x))
8998         output_operand_lossage ("invalid %%v value");
8999       else
9000         fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9001                  (INT_LOWPART (x) >> 16) & 0xffff);
9002       return;
9003
9004     case 'U':
9005       /* Print `u' if this has an auto-increment or auto-decrement.  */
9006       if (GET_CODE (x) == MEM
9007           && (GET_CODE (XEXP (x, 0)) == PRE_INC
9008               || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9009         putc ('u', file);
9010       return;
9011
9012     case 'V':
9013       /* Print the trap code for this operand.  */
9014       switch (GET_CODE (x))
9015         {
9016         case EQ:
9017           fputs ("eq", file);   /* 4 */
9018           break;
9019         case NE:
9020           fputs ("ne", file);   /* 24 */
9021           break;
9022         case LT:
9023           fputs ("lt", file);   /* 16 */
9024           break;
9025         case LE:
9026           fputs ("le", file);   /* 20 */
9027           break;
9028         case GT:
9029           fputs ("gt", file);   /* 8 */
9030           break;
9031         case GE:
9032           fputs ("ge", file);   /* 12 */
9033           break;
9034         case LTU:
9035           fputs ("llt", file);  /* 2 */
9036           break;
9037         case LEU:
9038           fputs ("lle", file);  /* 6 */
9039           break;
9040         case GTU:
9041           fputs ("lgt", file);  /* 1 */
9042           break;
9043         case GEU:
9044           fputs ("lge", file);  /* 5 */
9045           break;
9046         default:
9047           abort ();
9048         }
9049       break;
9050
9051     case 'w':
9052       /* If constant, low-order 16 bits of constant, signed.  Otherwise, write
9053          normally.  */
9054       if (INT_P (x))
9055         fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9056                  ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9057       else
9058         print_operand (file, x, 0);
9059       return;
9060
9061     case 'W':
9062       /* MB value for a PowerPC64 rldic operand.  */
9063       val = (GET_CODE (x) == CONST_INT
9064              ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9065
9066       if (val < 0)
9067         i = -1;
9068       else
9069         for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9070           if ((val <<= 1) < 0)
9071             break;
9072
9073 #if HOST_BITS_PER_WIDE_INT == 32
9074       if (GET_CODE (x) == CONST_INT && i >= 0)
9075         i += 32;  /* zero-extend high-part was all 0's */
9076       else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9077         {
9078           val = CONST_DOUBLE_LOW (x);
9079
9080           if (val == 0)
9081             abort ();
9082           else if (val < 0)
9083             --i;
9084           else
9085             for ( ; i < 64; i++)
9086               if ((val <<= 1) < 0)
9087                 break;
9088         }
9089 #endif
9090
9091       fprintf (file, "%d", i + 1);
9092       return;
9093
9094     case 'X':
9095       if (GET_CODE (x) == MEM
9096           && legitimate_indexed_address_p (XEXP (x, 0), 0))
9097         putc ('x', file);
9098       return;
9099
9100     case 'Y':
9101       /* Like 'L', for third word of TImode  */
9102       if (GET_CODE (x) == REG)
9103         fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9104       else if (GET_CODE (x) == MEM)
9105         {
9106           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9107               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9108             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9109           else
9110             output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9111           if (small_data_operand (x, GET_MODE (x)))
9112             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9113                      reg_names[SMALL_DATA_REG]);
9114         }
9115       return;
9116
9117     case 'z':
9118       /* X is a SYMBOL_REF.  Write out the name preceded by a
9119          period and without any trailing data in brackets.  Used for function
9120          names.  If we are configured for System V (or the embedded ABI) on
9121          the PowerPC, do not emit the period, since those systems do not use
9122          TOCs and the like.  */
9123       if (GET_CODE (x) != SYMBOL_REF)
9124         abort ();
9125
9126       if (XSTR (x, 0)[0] != '.')
9127         {
9128           switch (DEFAULT_ABI)
9129             {
9130             default:
9131               abort ();
9132
9133             case ABI_AIX:
9134               putc ('.', file);
9135               break;
9136
9137             case ABI_V4:
9138             case ABI_DARWIN:
9139               break;
9140             }
9141         }
9142       if (TARGET_AIX)
9143         RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
9144       else
9145         assemble_name (file, XSTR (x, 0));
9146       return;
9147
9148     case 'Z':
9149       /* Like 'L', for last word of TImode.  */
9150       if (GET_CODE (x) == REG)
9151         fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9152       else if (GET_CODE (x) == MEM)
9153         {
9154           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9155               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9156             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9157           else
9158             output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9159           if (small_data_operand (x, GET_MODE (x)))
9160             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9161                      reg_names[SMALL_DATA_REG]);
9162         }
9163       return;
9164
9165       /* Print AltiVec or SPE memory operand.  */
9166     case 'y':
9167       {
9168         rtx tmp;
9169
9170         if (GET_CODE (x) != MEM)
9171           abort ();
9172
9173         tmp = XEXP (x, 0);
9174
9175         if (TARGET_E500)
9176           {
9177             /* Handle [reg].  */
9178             if (GET_CODE (tmp) == REG)
9179               {
9180                 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9181                 break;
9182               }
9183             /* Handle [reg+UIMM].  */
9184             else if (GET_CODE (tmp) == PLUS &&
9185                      GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9186               {
9187                 int x;
9188
9189                 if (GET_CODE (XEXP (tmp, 0)) != REG)
9190                   abort ();
9191
9192                 x = INTVAL (XEXP (tmp, 1));
9193                 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9194                 break;
9195               }
9196
9197             /* Fall through.  Must be [reg+reg].  */
9198           }
9199         if (GET_CODE (tmp) == REG)
9200           fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9201         else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9202           {
9203             if (REGNO (XEXP (tmp, 0)) == 0)
9204               fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9205                        reg_names[ REGNO (XEXP (tmp, 0)) ]);
9206             else
9207               fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9208                        reg_names[ REGNO (XEXP (tmp, 1)) ]);
9209           }
9210         else
9211           abort ();
9212         break;
9213       }
9214
9215     case 0:
9216       if (GET_CODE (x) == REG)
9217         fprintf (file, "%s", reg_names[REGNO (x)]);
9218       else if (GET_CODE (x) == MEM)
9219         {
9220           /* We need to handle PRE_INC and PRE_DEC here, since we need to
9221              know the width from the mode.  */
9222           if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9223             fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9224                      reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9225           else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9226             fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9227                      reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9228           else
9229             output_address (XEXP (x, 0));
9230         }
9231       else
9232         output_addr_const (file, x);
9233       return;
9234
9235     case '&':
9236       assemble_name (file, rs6000_get_some_local_dynamic_name ());
9237       return;
9238
9239     default:
9240       output_operand_lossage ("invalid %%xn code");
9241     }
9242 }
9243 \f
9244 /* Print the address of an operand.  */
9245
9246 void
9247 print_operand_address (FILE *file, rtx x)
9248 {
9249   if (GET_CODE (x) == REG)
9250     fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9251   else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9252            || GET_CODE (x) == LABEL_REF)
9253     {
9254       output_addr_const (file, x);
9255       if (small_data_operand (x, GET_MODE (x)))
9256         fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9257                  reg_names[SMALL_DATA_REG]);
9258       else if (TARGET_TOC)
9259         abort ();
9260     }
9261   else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9262     {
9263       if (REGNO (XEXP (x, 0)) == 0)
9264         fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9265                  reg_names[ REGNO (XEXP (x, 0)) ]);
9266       else
9267         fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9268                  reg_names[ REGNO (XEXP (x, 1)) ]);
9269     }
9270   else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9271     fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9272              INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9273 #if TARGET_ELF
9274   else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9275            && CONSTANT_P (XEXP (x, 1)))
9276     {
9277       output_addr_const (file, XEXP (x, 1));
9278       fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9279     }
9280 #endif
9281 #if TARGET_MACHO
9282   else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9283            && CONSTANT_P (XEXP (x, 1)))
9284     {
9285       fprintf (file, "lo16(");
9286       output_addr_const (file, XEXP (x, 1));
9287       fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9288     }
9289 #endif
9290   else if (legitimate_constant_pool_address_p (x))
9291     {
9292       if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9293         {
9294           rtx contains_minus = XEXP (x, 1);
9295           rtx minus, symref;
9296           const char *name;
9297
9298           /* Find the (minus (sym) (toc)) buried in X, and temporarily
9299              turn it into (sym) for output_addr_const.  */
9300           while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9301             contains_minus = XEXP (contains_minus, 0);
9302
9303           minus = XEXP (contains_minus, 0);
9304           symref = XEXP (minus, 0);
9305           XEXP (contains_minus, 0) = symref;
9306           if (TARGET_ELF)
9307             {
9308               char *newname;
9309
9310               name = XSTR (symref, 0);
9311               newname = alloca (strlen (name) + sizeof ("@toc"));
9312               strcpy (newname, name);
9313               strcat (newname, "@toc");
9314               XSTR (symref, 0) = newname;
9315             }
9316           output_addr_const (file, XEXP (x, 1));
9317           if (TARGET_ELF)
9318             XSTR (symref, 0) = name;
9319           XEXP (contains_minus, 0) = minus;
9320         }
9321       else
9322         output_addr_const (file, XEXP (x, 1));
9323
9324       fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9325     }
9326   else
9327     abort ();
9328 }
9329 \f
9330 /* Target hook for assembling integer objects.  The PowerPC version has
9331    to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9332    is defined.  It also needs to handle DI-mode objects on 64-bit
9333    targets.  */
9334
9335 static bool
9336 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9337 {
9338 #ifdef RELOCATABLE_NEEDS_FIXUP
9339   /* Special handling for SI values.  */
9340   if (size == 4 && aligned_p)
9341     {
9342       extern int in_toc_section (void);
9343       static int recurse = 0;
9344
9345       /* For -mrelocatable, we mark all addresses that need to be fixed up
9346          in the .fixup section.  */
9347       if (TARGET_RELOCATABLE
9348           && !in_toc_section ()
9349           && !in_text_section ()
9350           && !recurse
9351           && GET_CODE (x) != CONST_INT
9352           && GET_CODE (x) != CONST_DOUBLE
9353           && CONSTANT_P (x))
9354         {
9355           char buf[256];
9356
9357           recurse = 1;
9358           ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9359           fixuplabelno++;
9360           ASM_OUTPUT_LABEL (asm_out_file, buf);
9361           fprintf (asm_out_file, "\t.long\t(");
9362           output_addr_const (asm_out_file, x);
9363           fprintf (asm_out_file, ")@fixup\n");
9364           fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9365           ASM_OUTPUT_ALIGN (asm_out_file, 2);
9366           fprintf (asm_out_file, "\t.long\t");
9367           assemble_name (asm_out_file, buf);
9368           fprintf (asm_out_file, "\n\t.previous\n");
9369           recurse = 0;
9370           return true;
9371         }
9372       /* Remove initial .'s to turn a -mcall-aixdesc function
9373          address into the address of the descriptor, not the function
9374          itself.  */
9375       else if (GET_CODE (x) == SYMBOL_REF
9376                && XSTR (x, 0)[0] == '.'
9377                && DEFAULT_ABI == ABI_AIX)
9378         {
9379           const char *name = XSTR (x, 0);
9380           while (*name == '.')
9381             name++;
9382
9383           fprintf (asm_out_file, "\t.long\t%s\n", name);
9384           return true;
9385         }
9386     }
9387 #endif /* RELOCATABLE_NEEDS_FIXUP */
9388   return default_assemble_integer (x, size, aligned_p);
9389 }
9390
9391 #ifdef HAVE_GAS_HIDDEN
9392 /* Emit an assembler directive to set symbol visibility for DECL to
9393    VISIBILITY_TYPE.  */
9394
9395 static void
9396 rs6000_assemble_visibility (tree decl, int vis)
9397 {
9398   /* Functions need to have their entry point symbol visibility set as
9399      well as their descriptor symbol visibility.  */
9400   if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
9401     {
9402       static const char * const visibility_types[] = {
9403         NULL, "internal", "hidden", "protected"
9404       };
9405
9406       const char *name, *type;
9407
9408       name = ((* targetm.strip_name_encoding)
9409               (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9410       type = visibility_types[vis];
9411
9412       fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9413       fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9414     }
9415   else
9416     default_assemble_visibility (decl, vis);
9417 }
9418 #endif
9419 \f
9420 enum rtx_code
9421 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9422 {
9423   /* Reversal of FP compares takes care -- an ordered compare
9424      becomes an unordered compare and vice versa.  */
9425   if (mode == CCFPmode
9426       && (!flag_finite_math_only
9427           || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9428           || code == UNEQ || code == LTGT))
9429     return reverse_condition_maybe_unordered (code);
9430   else
9431     return reverse_condition (code);
9432 }
9433
9434 /* Generate a compare for CODE.  Return a brand-new rtx that
9435    represents the result of the compare.  */
9436
9437 static rtx
9438 rs6000_generate_compare (enum rtx_code code)
9439 {
9440   enum machine_mode comp_mode;
9441   rtx compare_result;
9442
9443   if (rs6000_compare_fp_p)
9444     comp_mode = CCFPmode;
9445   else if (code == GTU || code == LTU
9446           || code == GEU || code == LEU)
9447     comp_mode = CCUNSmode;
9448   else
9449     comp_mode = CCmode;
9450
9451   /* First, the compare.  */
9452   compare_result = gen_reg_rtx (comp_mode);
9453
9454   /* SPE FP compare instructions on the GPRs.  Yuck!  */
9455   if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
9456       && rs6000_compare_fp_p)
9457     {
9458       rtx cmp, or1, or2, or_result, compare_result2;
9459
9460       switch (code)
9461         {
9462         case EQ:
9463         case UNEQ:
9464         case NE:
9465         case LTGT:
9466           cmp = flag_finite_math_only
9467             ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
9468                                rs6000_compare_op1)
9469             : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
9470                                rs6000_compare_op1);
9471           break;
9472         case GT:
9473         case GTU:
9474         case UNGT:
9475         case UNGE:
9476         case GE:
9477         case GEU:
9478           cmp = flag_finite_math_only
9479             ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
9480                                rs6000_compare_op1)
9481             : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
9482                                rs6000_compare_op1);
9483           break;
9484         case LT:
9485         case LTU:
9486         case UNLT:
9487         case UNLE:
9488         case LE:
9489         case LEU:
9490           cmp = flag_finite_math_only
9491             ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
9492                                rs6000_compare_op1)
9493             : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
9494                                rs6000_compare_op1);
9495           break;
9496         default:
9497           abort ();
9498         }
9499
9500       /* Synthesize LE and GE from LT/GT || EQ.  */
9501       if (code == LE || code == GE || code == LEU || code == GEU)
9502         {
9503           /* Synthesize GE/LE frome GT/LT || EQ.  */
9504
9505           emit_insn (cmp);
9506
9507           switch (code)
9508             {
9509             case LE: code = LT; break;
9510             case GE: code = GT; break;
9511             case LEU: code = LT; break;
9512             case GEU: code = GT; break;
9513             default: abort ();
9514             }
9515
9516           or1 = gen_reg_rtx (SImode);
9517           or2 = gen_reg_rtx (SImode);
9518           or_result = gen_reg_rtx (CCEQmode);
9519           compare_result2 = gen_reg_rtx (CCFPmode);
9520
9521           /* Do the EQ.  */
9522           cmp = flag_finite_math_only
9523             ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
9524                                rs6000_compare_op1)
9525             : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
9526                                rs6000_compare_op1);
9527           emit_insn (cmp);
9528
9529           /* The MC8540 FP compare instructions set the CR bits
9530              differently than other PPC compare instructions.  For
9531              that matter, there is no generic test instruction, but a
9532              testgt, testlt, and testeq.  For a true condition, bit 2
9533              is set (x1xx) in the CR.  Following the traditional CR
9534              values:
9535
9536              LT    GT    EQ    OV
9537              bit3  bit2  bit1  bit0
9538
9539              ... bit 2 would be a GT CR alias, so later on we
9540              look in the GT bits for the branch instructions.
9541              However, we must be careful to emit correct RTL in
9542              the meantime, so optimizations don't get confused.  */
9543
9544           or1 = gen_rtx (NE, SImode, compare_result, const0_rtx);
9545           or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx);
9546
9547           /* OR them together.  */
9548           cmp = gen_rtx_SET (VOIDmode, or_result,
9549                              gen_rtx_COMPARE (CCEQmode,
9550                                               gen_rtx_IOR (SImode, or1, or2),
9551                                               const_true_rtx));
9552           compare_result = or_result;
9553           code = EQ;
9554         }
9555       else
9556         {
9557           /* We only care about 1 bit (x1xx), so map everything to NE to
9558              maintain rtl sanity.  We'll get to the right bit (x1xx) at
9559              code output time.  */
9560           if (code == NE || code == LTGT)
9561             /* Do the inverse here because we have no cmpne
9562                instruction.  We use the cmpeq instruction and expect
9563                to get a 0 instead.  */
9564             code = EQ;
9565           else
9566             code = NE;
9567         }
9568
9569       emit_insn (cmp);
9570     }
9571   else
9572     emit_insn (gen_rtx_SET (VOIDmode, compare_result,
9573                             gen_rtx_COMPARE (comp_mode,
9574                                              rs6000_compare_op0,
9575                                              rs6000_compare_op1)));
9576
9577   /* Some kinds of FP comparisons need an OR operation;
9578      under flag_finite_math_only we don't bother.  */
9579   if (rs6000_compare_fp_p
9580       && ! flag_finite_math_only
9581       && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
9582       && (code == LE || code == GE
9583           || code == UNEQ || code == LTGT
9584           || code == UNGT || code == UNLT))
9585     {
9586       enum rtx_code or1, or2;
9587       rtx or1_rtx, or2_rtx, compare2_rtx;
9588       rtx or_result = gen_reg_rtx (CCEQmode);
9589
9590       switch (code)
9591         {
9592         case LE: or1 = LT;  or2 = EQ;  break;
9593         case GE: or1 = GT;  or2 = EQ;  break;
9594         case UNEQ: or1 = UNORDERED;  or2 = EQ;  break;
9595         case LTGT: or1 = LT;  or2 = GT;  break;
9596         case UNGT: or1 = UNORDERED;  or2 = GT;  break;
9597         case UNLT: or1 = UNORDERED;  or2 = LT;  break;
9598         default:  abort ();
9599         }
9600       validate_condition_mode (or1, comp_mode);
9601       validate_condition_mode (or2, comp_mode);
9602       or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
9603       or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
9604       compare2_rtx = gen_rtx_COMPARE (CCEQmode,
9605                                       gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
9606                                       const_true_rtx);
9607       emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
9608
9609       compare_result = or_result;
9610       code = EQ;
9611     }
9612
9613   validate_condition_mode (code, GET_MODE (compare_result));
9614
9615   return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
9616 }
9617
9618
9619 /* Emit the RTL for an sCOND pattern.  */
9620
9621 void
9622 rs6000_emit_sCOND (enum rtx_code code, rtx result)
9623 {
9624   rtx condition_rtx;
9625   enum machine_mode op_mode;
9626   enum rtx_code cond_code;
9627
9628   condition_rtx = rs6000_generate_compare (code);
9629   cond_code = GET_CODE (condition_rtx);
9630
9631   if (cond_code == NE
9632       || cond_code == GE || cond_code == LE
9633       || cond_code == GEU || cond_code == LEU
9634       || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
9635     {
9636       rtx not_result = gen_reg_rtx (CCEQmode);
9637       rtx not_op, rev_cond_rtx;
9638       enum machine_mode cc_mode;
9639
9640       cc_mode = GET_MODE (XEXP (condition_rtx, 0));
9641
9642       rev_cond_rtx = gen_rtx (rs6000_reverse_condition (cc_mode, cond_code),
9643                               SImode, XEXP (condition_rtx, 0), const0_rtx);
9644       not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
9645       emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
9646       condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
9647     }
9648
9649   op_mode = GET_MODE (rs6000_compare_op0);
9650   if (op_mode == VOIDmode)
9651     op_mode = GET_MODE (rs6000_compare_op1);
9652
9653   if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
9654     {
9655       PUT_MODE (condition_rtx, DImode);
9656       convert_move (result, condition_rtx, 0);
9657     }
9658   else
9659     {
9660       PUT_MODE (condition_rtx, SImode);
9661       emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
9662     }
9663 }
9664
9665 /* Emit a branch of kind CODE to location LOC.  */
9666
9667 void
9668 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
9669 {
9670   rtx condition_rtx, loc_ref;
9671
9672   condition_rtx = rs6000_generate_compare (code);
9673   loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
9674   emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
9675                                gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
9676                                                      loc_ref, pc_rtx)));
9677 }
9678
9679 /* Return the string to output a conditional branch to LABEL, which is
9680    the operand number of the label, or -1 if the branch is really a
9681    conditional return.
9682
9683    OP is the conditional expression.  XEXP (OP, 0) is assumed to be a
9684    condition code register and its mode specifies what kind of
9685    comparison we made.
9686
9687    REVERSED is nonzero if we should reverse the sense of the comparison.
9688
9689    INSN is the insn.  */
9690
9691 char *
9692 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
9693 {
9694   static char string[64];
9695   enum rtx_code code = GET_CODE (op);
9696   rtx cc_reg = XEXP (op, 0);
9697   enum machine_mode mode = GET_MODE (cc_reg);
9698   int cc_regno = REGNO (cc_reg) - CR0_REGNO;
9699   int need_longbranch = label != NULL && get_attr_length (insn) == 8;
9700   int really_reversed = reversed ^ need_longbranch;
9701   char *s = string;
9702   const char *ccode;
9703   const char *pred;
9704   rtx note;
9705
9706   validate_condition_mode (code, mode);
9707
9708   /* Work out which way this really branches.  We could use
9709      reverse_condition_maybe_unordered here always but this
9710      makes the resulting assembler clearer.  */
9711   if (really_reversed)
9712     {
9713       /* Reversal of FP compares takes care -- an ordered compare
9714          becomes an unordered compare and vice versa.  */
9715       if (mode == CCFPmode)
9716         code = reverse_condition_maybe_unordered (code);
9717       else
9718         code = reverse_condition (code);
9719     }
9720
9721   if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
9722     {
9723       /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
9724          to the GT bit.  */
9725       if (code == EQ)
9726         /* Opposite of GT.  */
9727         code = UNLE;
9728       else if (code == NE)
9729         code = GT;
9730       else
9731         abort ();
9732     }
9733
9734   switch (code)
9735     {
9736       /* Not all of these are actually distinct opcodes, but
9737          we distinguish them for clarity of the resulting assembler.  */
9738     case NE: case LTGT:
9739       ccode = "ne"; break;
9740     case EQ: case UNEQ:
9741       ccode = "eq"; break;
9742     case GE: case GEU:
9743       ccode = "ge"; break;
9744     case GT: case GTU: case UNGT:
9745       ccode = "gt"; break;
9746     case LE: case LEU:
9747       ccode = "le"; break;
9748     case LT: case LTU: case UNLT:
9749       ccode = "lt"; break;
9750     case UNORDERED: ccode = "un"; break;
9751     case ORDERED: ccode = "nu"; break;
9752     case UNGE: ccode = "nl"; break;
9753     case UNLE: ccode = "ng"; break;
9754     default:
9755       abort ();
9756     }
9757
9758   /* Maybe we have a guess as to how likely the branch is.
9759      The old mnemonics don't have a way to specify this information.  */
9760   pred = "";
9761   note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
9762   if (note != NULL_RTX)
9763     {
9764       /* PROB is the difference from 50%.  */
9765       int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
9766       bool always_hint = rs6000_cpu != PROCESSOR_POWER4;
9767
9768       /* Only hint for highly probable/improbable branches on newer
9769          cpus as static prediction overrides processor dynamic
9770          prediction.  For older cpus we may as well always hint, but
9771          assume not taken for branches that are very close to 50% as a
9772          mispredicted taken branch is more expensive than a
9773          mispredicted not-taken branch.  */
9774       if (always_hint
9775           || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
9776         {
9777           if (abs (prob) > REG_BR_PROB_BASE / 20
9778               && ((prob > 0) ^ need_longbranch))
9779               pred = "+";
9780           else
9781             pred = "-";
9782         }
9783     }
9784
9785   if (label == NULL)
9786     s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
9787   else
9788     s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
9789
9790   /* We need to escape any '%' characters in the reg_names string.
9791      Assume they'd only be the first character....  */
9792   if (reg_names[cc_regno + CR0_REGNO][0] == '%')
9793     *s++ = '%';
9794   s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
9795
9796   if (label != NULL)
9797     {
9798       /* If the branch distance was too far, we may have to use an
9799          unconditional branch to go the distance.  */
9800       if (need_longbranch)
9801         s += sprintf (s, ",$+8\n\tb %s", label);
9802       else
9803         s += sprintf (s, ",%s", label);
9804     }
9805
9806   return string;
9807 }
9808
9809 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
9810    operands of the last comparison is nonzero/true, FALSE_COND if it
9811    is zero/false.  Return 0 if the hardware has no such operation.  */
9812
9813 int
9814 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9815 {
9816   enum rtx_code code = GET_CODE (op);
9817   rtx op0 = rs6000_compare_op0;
9818   rtx op1 = rs6000_compare_op1;
9819   REAL_VALUE_TYPE c1;
9820   enum machine_mode compare_mode = GET_MODE (op0);
9821   enum machine_mode result_mode = GET_MODE (dest);
9822   rtx temp;
9823
9824   /* These modes should always match.  */
9825   if (GET_MODE (op1) != compare_mode
9826       /* In the isel case however, we can use a compare immediate, so
9827          op1 may be a small constant.  */
9828       && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
9829     return 0;
9830   if (GET_MODE (true_cond) != result_mode)
9831     return 0;
9832   if (GET_MODE (false_cond) != result_mode)
9833     return 0;
9834
9835   /* First, work out if the hardware can do this at all, or
9836      if it's too slow....  */
9837   if (! rs6000_compare_fp_p)
9838     {
9839       if (TARGET_ISEL)
9840         return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
9841       return 0;
9842     }
9843
9844   /* Eliminate half of the comparisons by switching operands, this
9845      makes the remaining code simpler.  */
9846   if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
9847       || code == LTGT || code == LT || code == UNLE)
9848     {
9849       code = reverse_condition_maybe_unordered (code);
9850       temp = true_cond;
9851       true_cond = false_cond;
9852       false_cond = temp;
9853     }
9854
9855   /* UNEQ and LTGT take four instructions for a comparison with zero,
9856      it'll probably be faster to use a branch here too.  */
9857   if (code == UNEQ && HONOR_NANS (compare_mode))
9858     return 0;
9859
9860   if (GET_CODE (op1) == CONST_DOUBLE)
9861     REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
9862
9863   /* We're going to try to implement comparisons by performing
9864      a subtract, then comparing against zero.  Unfortunately,
9865      Inf - Inf is NaN which is not zero, and so if we don't
9866      know that the operand is finite and the comparison
9867      would treat EQ different to UNORDERED, we can't do it.  */
9868   if (HONOR_INFINITIES (compare_mode)
9869       && code != GT && code != UNGE
9870       && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
9871       /* Constructs of the form (a OP b ? a : b) are safe.  */
9872       && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
9873           || (! rtx_equal_p (op0, true_cond)
9874               && ! rtx_equal_p (op1, true_cond))))
9875     return 0;
9876   /* At this point we know we can use fsel.  */
9877
9878   /* Reduce the comparison to a comparison against zero.  */
9879   temp = gen_reg_rtx (compare_mode);
9880   emit_insn (gen_rtx_SET (VOIDmode, temp,
9881                           gen_rtx_MINUS (compare_mode, op0, op1)));
9882   op0 = temp;
9883   op1 = CONST0_RTX (compare_mode);
9884
9885   /* If we don't care about NaNs we can reduce some of the comparisons
9886      down to faster ones.  */
9887   if (! HONOR_NANS (compare_mode))
9888     switch (code)
9889       {
9890       case GT:
9891         code = LE;
9892         temp = true_cond;
9893         true_cond = false_cond;
9894         false_cond = temp;
9895         break;
9896       case UNGE:
9897         code = GE;
9898         break;
9899       case UNEQ:
9900         code = EQ;
9901         break;
9902       default:
9903         break;
9904       }
9905
9906   /* Now, reduce everything down to a GE.  */
9907   switch (code)
9908     {
9909     case GE:
9910       break;
9911
9912     case LE:
9913       temp = gen_reg_rtx (compare_mode);
9914       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9915       op0 = temp;
9916       break;
9917
9918     case ORDERED:
9919       temp = gen_reg_rtx (compare_mode);
9920       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
9921       op0 = temp;
9922       break;
9923
9924     case EQ:
9925       temp = gen_reg_rtx (compare_mode);
9926       emit_insn (gen_rtx_SET (VOIDmode, temp,
9927                               gen_rtx_NEG (compare_mode,
9928                                            gen_rtx_ABS (compare_mode, op0))));
9929       op0 = temp;
9930       break;
9931
9932     case UNGE:
9933       /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
9934       temp = gen_reg_rtx (result_mode);
9935       emit_insn (gen_rtx_SET (VOIDmode, temp,
9936                               gen_rtx_IF_THEN_ELSE (result_mode,
9937                                                     gen_rtx_GE (VOIDmode,
9938                                                                 op0, op1),
9939                                                     true_cond, false_cond)));
9940       false_cond = true_cond;
9941       true_cond = temp;
9942
9943       temp = gen_reg_rtx (compare_mode);
9944       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9945       op0 = temp;
9946       break;
9947
9948     case GT:
9949       /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
9950       temp = gen_reg_rtx (result_mode);
9951       emit_insn (gen_rtx_SET (VOIDmode, temp,
9952                               gen_rtx_IF_THEN_ELSE (result_mode,
9953                                                     gen_rtx_GE (VOIDmode,
9954                                                                 op0, op1),
9955                                                     true_cond, false_cond)));
9956       true_cond = false_cond;
9957       false_cond = temp;
9958
9959       temp = gen_reg_rtx (compare_mode);
9960       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9961       op0 = temp;
9962       break;
9963
9964     default:
9965       abort ();
9966     }
9967
9968   emit_insn (gen_rtx_SET (VOIDmode, dest,
9969                           gen_rtx_IF_THEN_ELSE (result_mode,
9970                                                 gen_rtx_GE (VOIDmode,
9971                                                             op0, op1),
9972                                                 true_cond, false_cond)));
9973   return 1;
9974 }
9975
9976 /* Same as above, but for ints (isel).  */
9977
9978 static int
9979 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9980 {
9981   rtx condition_rtx, cr;
9982
9983   /* All isel implementations thus far are 32-bits.  */
9984   if (GET_MODE (rs6000_compare_op0) != SImode)
9985     return 0;
9986
9987   /* We still have to do the compare, because isel doesn't do a
9988      compare, it just looks at the CRx bits set by a previous compare
9989      instruction.  */
9990   condition_rtx = rs6000_generate_compare (GET_CODE (op));
9991   cr = XEXP (condition_rtx, 0);
9992
9993   if (GET_MODE (cr) == CCmode)
9994     emit_insn (gen_isel_signed (dest, condition_rtx,
9995                                 true_cond, false_cond, cr));
9996   else
9997     emit_insn (gen_isel_unsigned (dest, condition_rtx,
9998                                   true_cond, false_cond, cr));
9999
10000   return 1;
10001 }
10002
10003 const char *
10004 output_isel (rtx *operands)
10005 {
10006   enum rtx_code code;
10007
10008   code = GET_CODE (operands[1]);
10009   if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10010     {
10011       PUT_CODE (operands[1], reverse_condition (code));
10012       return "isel %0,%3,%2,%j1";
10013     }
10014   else
10015     return "isel %0,%2,%3,%j1";
10016 }
10017
10018 void
10019 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10020 {
10021   enum machine_mode mode = GET_MODE (op0);
10022   enum rtx_code c;
10023   rtx target;
10024
10025   if (code == SMAX || code == SMIN)
10026     c = GE;
10027   else
10028     c = GEU;
10029
10030   if (code == SMAX || code == UMAX)
10031     target = emit_conditional_move (dest, c, op0, op1, mode,
10032                                     op0, op1, mode, 0);
10033   else
10034     target = emit_conditional_move (dest, c, op0, op1, mode,
10035                                     op1, op0, mode, 0);
10036   if (target == NULL_RTX)
10037     abort ();
10038   if (target != dest)
10039     emit_move_insn (dest, target);
10040 }
10041
10042 /* Emit instructions to move SRC to DST.  Called by splitters for
10043    multi-register moves.  It will emit at most one instruction for
10044    each register that is accessed; that is, it won't emit li/lis pairs
10045    (or equivalent for 64-bit code).  One of SRC or DST must be a hard
10046    register.  */
10047
10048 void
10049 rs6000_split_multireg_move (rtx dst, rtx src)
10050 {
10051   /* The register number of the first register being moved.  */
10052   int reg;
10053   /* The mode that is to be moved.  */
10054   enum machine_mode mode;
10055   /* The mode that the move is being done in, and its size.  */
10056   enum machine_mode reg_mode;
10057   int reg_mode_size;
10058   /* The number of registers that will be moved.  */
10059   int nregs;
10060
10061   reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10062   mode = GET_MODE (dst);
10063   nregs = HARD_REGNO_NREGS (reg, mode);
10064   if (FP_REGNO_P (reg))
10065     reg_mode = DFmode;
10066   else if (ALTIVEC_REGNO_P (reg))
10067     reg_mode = V16QImode;
10068   else
10069     reg_mode = word_mode;
10070   reg_mode_size = GET_MODE_SIZE (reg_mode);
10071
10072   if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10073     abort ();
10074
10075   if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10076     {
10077       /* Move register range backwards, if we might have destructive
10078          overlap.  */
10079       int i;
10080       for (i = nregs - 1; i >= 0; i--)
10081         emit_insn (gen_rtx_SET (VOIDmode,
10082                                 simplify_gen_subreg (reg_mode, dst, mode,
10083                                                      i * reg_mode_size),
10084                                 simplify_gen_subreg (reg_mode, src, mode,
10085                                                      i * reg_mode_size)));
10086     }
10087   else
10088     {
10089       int i;
10090       int j = -1;
10091       bool used_update = false;
10092
10093       if (GET_CODE (src) == MEM && INT_REGNO_P (reg))
10094         {
10095           rtx breg;
10096
10097           if (GET_CODE (XEXP (src, 0)) == PRE_INC
10098               || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10099             {
10100               rtx delta_rtx;
10101               breg = XEXP (XEXP (src, 0), 0);
10102               delta_rtx =  GET_CODE (XEXP (src, 0)) == PRE_INC
10103                   ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10104                   : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
10105               emit_insn (TARGET_32BIT
10106                          ? gen_addsi3 (breg, breg, delta_rtx)
10107                          : gen_adddi3 (breg, breg, delta_rtx));
10108               src = gen_rtx_MEM (mode, breg);
10109             }
10110
10111           /* We have now address involving an base register only.
10112              If we use one of the registers to address memory,
10113              we have change that register last.  */
10114
10115           breg = (GET_CODE (XEXP (src, 0)) == PLUS
10116                   ? XEXP (XEXP (src, 0), 0)
10117                   : XEXP (src, 0));
10118
10119           if (!REG_P (breg))
10120               abort();
10121
10122           if (REGNO (breg) >= REGNO (dst)
10123               && REGNO (breg) < REGNO (dst) + nregs)
10124             j = REGNO (breg) - REGNO (dst);
10125         }
10126
10127       if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
10128         {
10129           rtx breg;
10130
10131           if (GET_CODE (XEXP (dst, 0)) == PRE_INC
10132               || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
10133             {
10134               rtx delta_rtx;
10135               breg = XEXP (XEXP (dst, 0), 0);
10136               delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
10137                 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
10138                 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
10139
10140               /* We have to update the breg before doing the store.
10141                  Use store with update, if available.  */
10142
10143               if (TARGET_UPDATE)
10144                 {
10145                   rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
10146                   emit_insn (TARGET_32BIT
10147                              ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
10148                              : gen_movdi_update (breg, breg, delta_rtx, nsrc));
10149                   used_update = true;
10150                 }
10151               else
10152                 emit_insn (TARGET_32BIT
10153                            ? gen_addsi3 (breg, breg, delta_rtx)
10154                            : gen_adddi3 (breg, breg, delta_rtx));
10155               dst = gen_rtx_MEM (mode, breg);
10156             }
10157         }
10158
10159       for (i = 0; i < nregs; i++)
10160         {
10161           /* Calculate index to next subword.  */
10162           ++j;
10163           if (j == nregs)
10164             j = 0;
10165
10166           /* If compiler already emited move of first word by
10167              store with update, no need to do anything.  */
10168           if (j == 0 && used_update)
10169             continue;
10170
10171           emit_insn (gen_rtx_SET (VOIDmode,
10172                                   simplify_gen_subreg (reg_mode, dst, mode,
10173                                                        j * reg_mode_size),
10174                                   simplify_gen_subreg (reg_mode, src, mode,
10175                                                        j * reg_mode_size)));
10176         }
10177     }
10178 }
10179
10180 \f
10181 /* This page contains routines that are used to determine what the
10182    function prologue and epilogue code will do and write them out.  */
10183
10184 /* Return the first fixed-point register that is required to be
10185    saved. 32 if none.  */
10186
10187 int
10188 first_reg_to_save (void)
10189 {
10190   int first_reg;
10191
10192   /* Find lowest numbered live register.  */
10193   for (first_reg = 13; first_reg <= 31; first_reg++)
10194     if (regs_ever_live[first_reg]
10195         && (! call_used_regs[first_reg]
10196             || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
10197                 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
10198                     || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
10199       break;
10200
10201 #if TARGET_MACHO
10202   if (flag_pic
10203       && current_function_uses_pic_offset_table
10204       && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
10205     return RS6000_PIC_OFFSET_TABLE_REGNUM;
10206 #endif
10207
10208   return first_reg;
10209 }
10210
10211 /* Similar, for FP regs.  */
10212
10213 int
10214 first_fp_reg_to_save (void)
10215 {
10216   int first_reg;
10217
10218   /* Find lowest numbered live register.  */
10219   for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
10220     if (regs_ever_live[first_reg])
10221       break;
10222
10223   return first_reg;
10224 }
10225
10226 /* Similar, for AltiVec regs.  */
10227
10228 static int
10229 first_altivec_reg_to_save (void)
10230 {
10231   int i;
10232
10233   /* Stack frame remains as is unless we are in AltiVec ABI.  */
10234   if (! TARGET_ALTIVEC_ABI)
10235     return LAST_ALTIVEC_REGNO + 1;
10236
10237   /* Find lowest numbered live register.  */
10238   for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
10239     if (regs_ever_live[i])
10240       break;
10241
10242   return i;
10243 }
10244
10245 /* Return a 32-bit mask of the AltiVec registers we need to set in
10246    VRSAVE.  Bit n of the return value is 1 if Vn is live.  The MSB in
10247    the 32-bit word is 0.  */
10248
10249 static unsigned int
10250 compute_vrsave_mask (void)
10251 {
10252   unsigned int i, mask = 0;
10253
10254   /* First, find out if we use _any_ altivec registers.  */
10255   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10256     if (regs_ever_live[i])
10257       mask |= ALTIVEC_REG_BIT (i);
10258
10259   if (mask == 0)
10260     return mask;
10261
10262   /* Next, remove the argument registers from the set.  These must
10263      be in the VRSAVE mask set by the caller, so we don't need to add
10264      them in again.  More importantly, the mask we compute here is
10265      used to generate CLOBBERs in the set_vrsave insn, and we do not
10266      wish the argument registers to die.  */
10267   for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
10268     mask &= ~ALTIVEC_REG_BIT (i);
10269
10270   /* Similarly, remove the return value from the set.  */
10271   {
10272     bool yes = false;
10273     diddle_return_value (is_altivec_return_reg, &yes);
10274     if (yes)
10275       mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
10276   }
10277
10278   return mask;
10279 }
10280
10281 static void
10282 is_altivec_return_reg (rtx reg, void *xyes)
10283 {
10284   bool *yes = (bool *) xyes;
10285   if (REGNO (reg) == ALTIVEC_ARG_RETURN)
10286     *yes = true;
10287 }
10288
10289 \f
10290 /* Calculate the stack information for the current function.  This is
10291    complicated by having two separate calling sequences, the AIX calling
10292    sequence and the V.4 calling sequence.
10293
10294    AIX (and Darwin/Mac OS X) stack frames look like:
10295                                                           32-bit  64-bit
10296         SP----> +---------------------------------------+
10297                 | back chain to caller                  | 0       0
10298                 +---------------------------------------+
10299                 | saved CR                              | 4       8 (8-11)
10300                 +---------------------------------------+
10301                 | saved LR                              | 8       16
10302                 +---------------------------------------+
10303                 | reserved for compilers                | 12      24
10304                 +---------------------------------------+
10305                 | reserved for binders                  | 16      32
10306                 +---------------------------------------+
10307                 | saved TOC pointer                     | 20      40
10308                 +---------------------------------------+
10309                 | Parameter save area (P)               | 24      48
10310                 +---------------------------------------+
10311                 | Alloca space (A)                      | 24+P    etc.
10312                 +---------------------------------------+
10313                 | Local variable space (L)              | 24+P+A
10314                 +---------------------------------------+
10315                 | Float/int conversion temporary (X)    | 24+P+A+L
10316                 +---------------------------------------+
10317                 | Save area for AltiVec registers (W)   | 24+P+A+L+X
10318                 +---------------------------------------+
10319                 | AltiVec alignment padding (Y)         | 24+P+A+L+X+W
10320                 +---------------------------------------+
10321                 | Save area for VRSAVE register (Z)     | 24+P+A+L+X+W+Y
10322                 +---------------------------------------+
10323                 | Save area for GP registers (G)        | 24+P+A+X+L+X+W+Y+Z
10324                 +---------------------------------------+
10325                 | Save area for FP registers (F)        | 24+P+A+X+L+X+W+Y+Z+G
10326                 +---------------------------------------+
10327         old SP->| back chain to caller's caller         |
10328                 +---------------------------------------+
10329
10330    The required alignment for AIX configurations is two words (i.e., 8
10331    or 16 bytes).
10332
10333
10334    V.4 stack frames look like:
10335
10336         SP----> +---------------------------------------+
10337                 | back chain to caller                  | 0
10338                 +---------------------------------------+
10339                 | caller's saved LR                     | 4
10340                 +---------------------------------------+
10341                 | Parameter save area (P)               | 8
10342                 +---------------------------------------+
10343                 | Alloca space (A)                      | 8+P
10344                 +---------------------------------------+
10345                 | Varargs save area (V)                 | 8+P+A
10346                 +---------------------------------------+
10347                 | Local variable space (L)              | 8+P+A+V
10348                 +---------------------------------------+
10349                 | Float/int conversion temporary (X)    | 8+P+A+V+L
10350                 +---------------------------------------+
10351                 | Save area for AltiVec registers (W)   | 8+P+A+V+L+X
10352                 +---------------------------------------+
10353                 | AltiVec alignment padding (Y)         | 8+P+A+V+L+X+W
10354                 +---------------------------------------+
10355                 | Save area for VRSAVE register (Z)     | 8+P+A+V+L+X+W+Y
10356                 +---------------------------------------+
10357                 | SPE: area for 64-bit GP registers     |
10358                 +---------------------------------------+
10359                 | SPE alignment padding                 |
10360                 +---------------------------------------+
10361                 | saved CR (C)                          | 8+P+A+V+L+X+W+Y+Z
10362                 +---------------------------------------+
10363                 | Save area for GP registers (G)        | 8+P+A+V+L+X+W+Y+Z+C
10364                 +---------------------------------------+
10365                 | Save area for FP registers (F)        | 8+P+A+V+L+X+W+Y+Z+C+G
10366                 +---------------------------------------+
10367         old SP->| back chain to caller's caller         |
10368                 +---------------------------------------+
10369
10370    The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
10371    given.  (But note below and in sysv4.h that we require only 8 and
10372    may round up the size of our stack frame anyways.  The historical
10373    reason is early versions of powerpc-linux which didn't properly
10374    align the stack at program startup.  A happy side-effect is that
10375    -mno-eabi libraries can be used with -meabi programs.)
10376
10377    The EABI configuration defaults to the V.4 layout.  However,
10378    the stack alignment requirements may differ.  If -mno-eabi is not
10379    given, the required stack alignment is 8 bytes; if -mno-eabi is
10380    given, the required alignment is 16 bytes.  (But see V.4 comment
10381    above.)  */
10382
10383 #ifndef ABI_STACK_BOUNDARY
10384 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
10385 #endif
10386
10387 static rs6000_stack_t *
10388 rs6000_stack_info (void)
10389 {
10390   static rs6000_stack_t info, zero_info;
10391   rs6000_stack_t *info_ptr = &info;
10392   int reg_size = TARGET_POWERPC64 ? 8 : 4;
10393   int ehrd_size;
10394   HOST_WIDE_INT total_raw_size;
10395
10396   /* Zero all fields portably.  */
10397   info = zero_info;
10398
10399   if (TARGET_SPE)
10400     {
10401       /* Cache value so we don't rescan instruction chain over and over.  */
10402       if (cfun->machine->insn_chain_scanned_p == 0)
10403         {
10404           cfun->machine->insn_chain_scanned_p = 1;
10405           info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
10406         }
10407     }
10408
10409   /* Select which calling sequence.  */
10410   info_ptr->abi = DEFAULT_ABI;
10411
10412   /* Calculate which registers need to be saved & save area size.  */
10413   info_ptr->first_gp_reg_save = first_reg_to_save ();
10414   /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
10415      even if it currently looks like we won't.  */
10416   if (((TARGET_TOC && TARGET_MINIMAL_TOC)
10417        || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
10418        || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
10419       && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
10420     info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
10421   else
10422     info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
10423
10424   /* For the SPE, we have an additional upper 32-bits on each GPR.
10425      Ideally we should save the entire 64-bits only when the upper
10426      half is used in SIMD instructions.  Since we only record
10427      registers live (not the size they are used in), this proves
10428      difficult because we'd have to traverse the instruction chain at
10429      the right time, taking reload into account.  This is a real pain,
10430      so we opt to save the GPRs in 64-bits always if but one register
10431      gets used in 64-bits.  Otherwise, all the registers in the frame
10432      get saved in 32-bits.
10433
10434      So... since when we save all GPRs (except the SP) in 64-bits, the
10435      traditional GP save area will be empty.  */
10436   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10437     info_ptr->gp_size = 0;
10438
10439   info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
10440   info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
10441
10442   info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
10443   info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
10444                                  - info_ptr->first_altivec_reg_save);
10445
10446   /* Does this function call anything?  */
10447   info_ptr->calls_p = (! current_function_is_leaf
10448                        || cfun->machine->ra_needs_full_frame);
10449
10450   /* Determine if we need to save the link register.  */
10451   if (rs6000_ra_ever_killed ()
10452       || (DEFAULT_ABI == ABI_AIX
10453           && current_function_profile
10454           && !TARGET_PROFILE_KERNEL)
10455 #ifdef TARGET_RELOCATABLE
10456       || (TARGET_RELOCATABLE && (get_pool_size () != 0))
10457 #endif
10458       || (info_ptr->first_fp_reg_save != 64
10459           && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
10460       || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
10461       || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
10462       || (DEFAULT_ABI == ABI_DARWIN
10463           && flag_pic
10464           && current_function_uses_pic_offset_table)
10465       || info_ptr->calls_p)
10466     {
10467       info_ptr->lr_save_p = 1;
10468       regs_ever_live[LINK_REGISTER_REGNUM] = 1;
10469     }
10470
10471   /* Determine if we need to save the condition code registers.  */
10472   if (regs_ever_live[CR2_REGNO]
10473       || regs_ever_live[CR3_REGNO]
10474       || regs_ever_live[CR4_REGNO])
10475     {
10476       info_ptr->cr_save_p = 1;
10477       if (DEFAULT_ABI == ABI_V4)
10478         info_ptr->cr_size = reg_size;
10479     }
10480
10481   /* If the current function calls __builtin_eh_return, then we need
10482      to allocate stack space for registers that will hold data for
10483      the exception handler.  */
10484   if (current_function_calls_eh_return)
10485     {
10486       unsigned int i;
10487       for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
10488         continue;
10489
10490       /* SPE saves EH registers in 64-bits.  */
10491       ehrd_size = i * (TARGET_SPE_ABI
10492                        && info_ptr->spe_64bit_regs_used != 0
10493                        ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
10494     }
10495   else
10496     ehrd_size = 0;
10497
10498   /* Determine various sizes.  */
10499   info_ptr->reg_size     = reg_size;
10500   info_ptr->fixed_size   = RS6000_SAVE_AREA;
10501   info_ptr->varargs_size = RS6000_VARARGS_AREA;
10502   info_ptr->vars_size    = RS6000_ALIGN (get_frame_size (), 8);
10503   info_ptr->parm_size    = RS6000_ALIGN (current_function_outgoing_args_size,
10504                                          8);
10505
10506   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10507     info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
10508   else
10509     info_ptr->spe_gp_size = 0;
10510
10511   if (TARGET_ALTIVEC_ABI)
10512     info_ptr->vrsave_mask = compute_vrsave_mask ();
10513   else
10514     info_ptr->vrsave_mask = 0;
10515
10516   if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
10517     info_ptr->vrsave_size  = 4;
10518   else
10519     info_ptr->vrsave_size  = 0;
10520
10521   /* Calculate the offsets.  */
10522   switch (DEFAULT_ABI)
10523     {
10524     case ABI_NONE:
10525     default:
10526       abort ();
10527
10528     case ABI_AIX:
10529     case ABI_DARWIN:
10530       info_ptr->fp_save_offset   = - info_ptr->fp_size;
10531       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
10532
10533       if (TARGET_ALTIVEC_ABI)
10534         {
10535           info_ptr->vrsave_save_offset
10536             = info_ptr->gp_save_offset - info_ptr->vrsave_size;
10537
10538           /* Align stack so vector save area is on a quadword boundary.  */
10539           if (info_ptr->altivec_size != 0)
10540             info_ptr->altivec_padding_size
10541               = 16 - (-info_ptr->vrsave_save_offset % 16);
10542           else
10543             info_ptr->altivec_padding_size = 0;
10544
10545           info_ptr->altivec_save_offset
10546             = info_ptr->vrsave_save_offset
10547             - info_ptr->altivec_padding_size
10548             - info_ptr->altivec_size;
10549
10550           /* Adjust for AltiVec case.  */
10551           info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
10552         }
10553       else
10554         info_ptr->ehrd_offset      = info_ptr->gp_save_offset - ehrd_size;
10555       info_ptr->cr_save_offset   = reg_size; /* first word when 64-bit.  */
10556       info_ptr->lr_save_offset   = 2*reg_size;
10557       break;
10558
10559     case ABI_V4:
10560       info_ptr->fp_save_offset   = - info_ptr->fp_size;
10561       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
10562       info_ptr->cr_save_offset   = info_ptr->gp_save_offset - info_ptr->cr_size;
10563
10564       if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10565       {
10566         /* Align stack so SPE GPR save area is aligned on a
10567            double-word boundary.  */
10568         if (info_ptr->spe_gp_size != 0)
10569           info_ptr->spe_padding_size
10570             = 8 - (-info_ptr->cr_save_offset % 8);
10571         else
10572           info_ptr->spe_padding_size = 0;
10573
10574         info_ptr->spe_gp_save_offset
10575           = info_ptr->cr_save_offset
10576           - info_ptr->spe_padding_size
10577           - info_ptr->spe_gp_size;
10578
10579         /* Adjust for SPE case.  */
10580         info_ptr->toc_save_offset
10581           = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
10582       }
10583       else if (TARGET_ALTIVEC_ABI)
10584         {
10585           info_ptr->vrsave_save_offset
10586             = info_ptr->cr_save_offset - info_ptr->vrsave_size;
10587
10588           /* Align stack so vector save area is on a quadword boundary.  */
10589           if (info_ptr->altivec_size != 0)
10590             info_ptr->altivec_padding_size
10591               = 16 - (-info_ptr->vrsave_save_offset % 16);
10592           else
10593             info_ptr->altivec_padding_size = 0;
10594
10595           info_ptr->altivec_save_offset
10596             = info_ptr->vrsave_save_offset
10597             - info_ptr->altivec_padding_size
10598             - info_ptr->altivec_size;
10599
10600           /* Adjust for AltiVec case.  */
10601           info_ptr->toc_save_offset
10602             = info_ptr->altivec_save_offset - info_ptr->toc_size;
10603         }
10604       else
10605         info_ptr->toc_save_offset  = info_ptr->cr_save_offset - info_ptr->toc_size;
10606       info_ptr->ehrd_offset      = info_ptr->toc_save_offset - ehrd_size;
10607       info_ptr->lr_save_offset   = reg_size;
10608       break;
10609     }
10610
10611   info_ptr->save_size    = RS6000_ALIGN (info_ptr->fp_size
10612                                          + info_ptr->gp_size
10613                                          + info_ptr->altivec_size
10614                                          + info_ptr->altivec_padding_size
10615                                          + info_ptr->spe_gp_size
10616                                          + info_ptr->spe_padding_size
10617                                          + ehrd_size
10618                                          + info_ptr->cr_size
10619                                          + info_ptr->lr_size
10620                                          + info_ptr->vrsave_size
10621                                          + info_ptr->toc_size,
10622                                          (TARGET_ALTIVEC_ABI || ABI_DARWIN)
10623                                          ? 16 : 8);
10624
10625   total_raw_size         = (info_ptr->vars_size
10626                             + info_ptr->parm_size
10627                             + info_ptr->save_size
10628                             + info_ptr->varargs_size
10629                             + info_ptr->fixed_size);
10630
10631   info_ptr->total_size =
10632     RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
10633
10634   /* Determine if we need to allocate any stack frame:
10635
10636      For AIX we need to push the stack if a frame pointer is needed
10637      (because the stack might be dynamically adjusted), if we are
10638      debugging, if we make calls, or if the sum of fp_save, gp_save,
10639      and local variables are more than the space needed to save all
10640      non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
10641      + 18*8 = 288 (GPR13 reserved).
10642
10643      For V.4 we don't have the stack cushion that AIX uses, but assume
10644      that the debugger can handle stackless frames.  */
10645
10646   if (info_ptr->calls_p)
10647     info_ptr->push_p = 1;
10648
10649   else if (DEFAULT_ABI == ABI_V4)
10650     info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
10651
10652   else if (frame_pointer_needed)
10653     info_ptr->push_p = 1;
10654
10655   else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
10656     info_ptr->push_p = 1;
10657
10658   else
10659     info_ptr->push_p
10660       = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288);
10661
10662   /* Zero offsets if we're not saving those registers.  */
10663   if (info_ptr->fp_size == 0)
10664     info_ptr->fp_save_offset = 0;
10665
10666   if (info_ptr->gp_size == 0)
10667     info_ptr->gp_save_offset = 0;
10668
10669   if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
10670     info_ptr->altivec_save_offset = 0;
10671
10672   if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
10673     info_ptr->vrsave_save_offset = 0;
10674
10675   if (! TARGET_SPE_ABI
10676       || info_ptr->spe_64bit_regs_used == 0
10677       || info_ptr->spe_gp_size == 0)
10678     info_ptr->spe_gp_save_offset = 0;
10679
10680   if (! info_ptr->lr_save_p)
10681     info_ptr->lr_save_offset = 0;
10682
10683   if (! info_ptr->cr_save_p)
10684     info_ptr->cr_save_offset = 0;
10685
10686   if (! info_ptr->toc_save_p)
10687     info_ptr->toc_save_offset = 0;
10688
10689   return info_ptr;
10690 }
10691
10692 /* Return true if the current function uses any GPRs in 64-bit SIMD
10693    mode.  */
10694
10695 static bool
10696 spe_func_has_64bit_regs_p (void)
10697 {
10698   rtx insns, insn;
10699
10700   /* Functions that save and restore all the call-saved registers will
10701      need to save/restore the registers in 64-bits.  */
10702   if (current_function_calls_eh_return
10703       || current_function_calls_setjmp
10704       || current_function_has_nonlocal_goto)
10705     return true;
10706
10707   insns = get_insns ();
10708
10709   for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
10710     {
10711       if (INSN_P (insn))
10712         {
10713           rtx i;
10714
10715           i = PATTERN (insn);
10716           if (GET_CODE (i) == SET
10717               && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
10718             return true;
10719         }
10720     }
10721
10722   return false;
10723 }
10724
10725 static void
10726 debug_stack_info (rs6000_stack_t *info)
10727 {
10728   const char *abi_string;
10729
10730   if (! info)
10731     info = rs6000_stack_info ();
10732
10733   fprintf (stderr, "\nStack information for function %s:\n",
10734            ((current_function_decl && DECL_NAME (current_function_decl))
10735             ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
10736             : "<unknown>"));
10737
10738   switch (info->abi)
10739     {
10740     default:             abi_string = "Unknown";        break;
10741     case ABI_NONE:       abi_string = "NONE";           break;
10742     case ABI_AIX:        abi_string = "AIX";            break;
10743     case ABI_DARWIN:     abi_string = "Darwin";         break;
10744     case ABI_V4:         abi_string = "V.4";            break;
10745     }
10746
10747   fprintf (stderr, "\tABI                 = %5s\n", abi_string);
10748
10749   if (TARGET_ALTIVEC_ABI)
10750     fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
10751
10752   if (TARGET_SPE_ABI)
10753     fprintf (stderr, "\tSPE ABI extensions enabled.\n");
10754
10755   if (info->first_gp_reg_save != 32)
10756     fprintf (stderr, "\tfirst_gp_reg_save   = %5d\n", info->first_gp_reg_save);
10757
10758   if (info->first_fp_reg_save != 64)
10759     fprintf (stderr, "\tfirst_fp_reg_save   = %5d\n", info->first_fp_reg_save);
10760
10761   if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
10762     fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
10763              info->first_altivec_reg_save);
10764
10765   if (info->lr_save_p)
10766     fprintf (stderr, "\tlr_save_p           = %5d\n", info->lr_save_p);
10767
10768   if (info->cr_save_p)
10769     fprintf (stderr, "\tcr_save_p           = %5d\n", info->cr_save_p);
10770
10771   if (info->toc_save_p)
10772     fprintf (stderr, "\ttoc_save_p          = %5d\n", info->toc_save_p);
10773
10774   if (info->vrsave_mask)
10775     fprintf (stderr, "\tvrsave_mask         = 0x%x\n", info->vrsave_mask);
10776
10777   if (info->push_p)
10778     fprintf (stderr, "\tpush_p              = %5d\n", info->push_p);
10779
10780   if (info->calls_p)
10781     fprintf (stderr, "\tcalls_p             = %5d\n", info->calls_p);
10782
10783   if (info->gp_save_offset)
10784     fprintf (stderr, "\tgp_save_offset      = %5d\n", info->gp_save_offset);
10785
10786   if (info->fp_save_offset)
10787     fprintf (stderr, "\tfp_save_offset      = %5d\n", info->fp_save_offset);
10788
10789   if (info->altivec_save_offset)
10790     fprintf (stderr, "\taltivec_save_offset = %5d\n",
10791              info->altivec_save_offset);
10792
10793   if (info->spe_gp_save_offset)
10794     fprintf (stderr, "\tspe_gp_save_offset  = %5d\n",
10795              info->spe_gp_save_offset);
10796
10797   if (info->vrsave_save_offset)
10798     fprintf (stderr, "\tvrsave_save_offset  = %5d\n",
10799              info->vrsave_save_offset);
10800
10801   if (info->lr_save_offset)
10802     fprintf (stderr, "\tlr_save_offset      = %5d\n", info->lr_save_offset);
10803
10804   if (info->cr_save_offset)
10805     fprintf (stderr, "\tcr_save_offset      = %5d\n", info->cr_save_offset);
10806
10807   if (info->toc_save_offset)
10808     fprintf (stderr, "\ttoc_save_offset     = %5d\n", info->toc_save_offset);
10809
10810   if (info->varargs_save_offset)
10811     fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
10812
10813   if (info->total_size)
10814     fprintf (stderr, "\ttotal_size          = "HOST_WIDE_INT_PRINT_DEC"\n",
10815              info->total_size);
10816
10817   if (info->varargs_size)
10818     fprintf (stderr, "\tvarargs_size        = %5d\n", info->varargs_size);
10819
10820   if (info->vars_size)
10821     fprintf (stderr, "\tvars_size           = "HOST_WIDE_INT_PRINT_DEC"\n",
10822              info->vars_size);
10823
10824   if (info->parm_size)
10825     fprintf (stderr, "\tparm_size           = %5d\n", info->parm_size);
10826
10827   if (info->fixed_size)
10828     fprintf (stderr, "\tfixed_size          = %5d\n", info->fixed_size);
10829
10830   if (info->gp_size)
10831     fprintf (stderr, "\tgp_size             = %5d\n", info->gp_size);
10832
10833   if (info->spe_gp_size)
10834     fprintf (stderr, "\tspe_gp_size         = %5d\n", info->spe_gp_size);
10835
10836   if (info->fp_size)
10837     fprintf (stderr, "\tfp_size             = %5d\n", info->fp_size);
10838
10839   if (info->altivec_size)
10840     fprintf (stderr, "\taltivec_size        = %5d\n", info->altivec_size);
10841
10842   if (info->vrsave_size)
10843     fprintf (stderr, "\tvrsave_size         = %5d\n", info->vrsave_size);
10844
10845   if (info->altivec_padding_size)
10846     fprintf (stderr, "\taltivec_padding_size= %5d\n",
10847              info->altivec_padding_size);
10848
10849   if (info->spe_padding_size)
10850     fprintf (stderr, "\tspe_padding_size    = %5d\n",
10851              info->spe_padding_size);
10852
10853   if (info->lr_size)
10854     fprintf (stderr, "\tlr_size             = %5d\n", info->lr_size);
10855
10856   if (info->cr_size)
10857     fprintf (stderr, "\tcr_size             = %5d\n", info->cr_size);
10858
10859   if (info->toc_size)
10860     fprintf (stderr, "\ttoc_size            = %5d\n", info->toc_size);
10861
10862   if (info->save_size)
10863     fprintf (stderr, "\tsave_size           = %5d\n", info->save_size);
10864
10865   if (info->reg_size != 4)
10866     fprintf (stderr, "\treg_size            = %5d\n", info->reg_size);
10867
10868   fprintf (stderr, "\n");
10869 }
10870
10871 rtx
10872 rs6000_return_addr (int count, rtx frame)
10873 {
10874   /* Currently we don't optimize very well between prolog and body
10875      code and for PIC code the code can be actually quite bad, so
10876      don't try to be too clever here.  */
10877   if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
10878     {
10879       cfun->machine->ra_needs_full_frame = 1;
10880
10881       return
10882         gen_rtx_MEM
10883           (Pmode,
10884            memory_address
10885            (Pmode,
10886             plus_constant (copy_to_reg
10887                            (gen_rtx_MEM (Pmode,
10888                                          memory_address (Pmode, frame))),
10889                            RETURN_ADDRESS_OFFSET)));
10890     }
10891
10892   cfun->machine->ra_need_lr = 1;
10893   return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
10894 }
10895
10896 /* Say whether a function is a candidate for sibcall handling or not.
10897    We do not allow indirect calls to be optimized into sibling calls.
10898    Also, we can't do it if there are any vector parameters; there's
10899    nowhere to put the VRsave code so it works; note that functions with
10900    vector parameters are required to have a prototype, so the argument
10901    type info must be available here.  (The tail recursion case can work
10902    with vector parameters, but there's no way to distinguish here.) */
10903 static bool
10904 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10905 {
10906   tree type;
10907   if (decl)
10908     {
10909       if (TARGET_ALTIVEC_VRSAVE)
10910         {
10911           for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
10912                type; type = TREE_CHAIN (type))
10913             {
10914               if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
10915                 return false;
10916             }
10917         }
10918       if (DEFAULT_ABI == ABI_DARWIN
10919           || (*targetm.binds_local_p) (decl))
10920         {
10921           tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
10922
10923           if (!lookup_attribute ("longcall", attr_list)
10924               || lookup_attribute ("shortcall", attr_list))
10925             return true;
10926         }
10927     }
10928   return false;
10929 }
10930
10931 static int
10932 rs6000_ra_ever_killed (void)
10933 {
10934   rtx top;
10935   rtx reg;
10936   rtx insn;
10937
10938   /* Irritatingly, there are two kinds of thunks -- those created with
10939      TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
10940      through the regular part of the compiler.  This is a very hacky
10941      way to tell them apart.  */
10942   if (current_function_is_thunk && !no_new_pseudos)
10943     return 0;
10944
10945   /* regs_ever_live has LR marked as used if any sibcalls are present,
10946      but this should not force saving and restoring in the
10947      pro/epilogue.  Likewise, reg_set_between_p thinks a sibcall
10948      clobbers LR, so that is inappropriate.  */
10949
10950   /* Also, the prologue can generate a store into LR that
10951      doesn't really count, like this:
10952
10953         move LR->R0
10954         bcl to set PIC register
10955         move LR->R31
10956         move R0->LR
10957
10958      When we're called from the epilogue, we need to avoid counting
10959      this as a store.  */
10960
10961   push_topmost_sequence ();
10962   top = get_insns ();
10963   pop_topmost_sequence ();
10964   reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
10965
10966   for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
10967     {
10968       if (INSN_P (insn))
10969         {
10970           if (FIND_REG_INC_NOTE (insn, reg))
10971             return 1;
10972           else if (GET_CODE (insn) == CALL_INSN
10973                    && !SIBLING_CALL_P (insn))
10974             return 1;
10975           else if (set_of (reg, insn) != NULL_RTX
10976                    && !prologue_epilogue_contains (insn))
10977             return 1;
10978         }
10979     }
10980   return 0;
10981 }
10982 \f
10983 /* Add a REG_MAYBE_DEAD note to the insn.  */
10984 static void
10985 rs6000_maybe_dead (rtx insn)
10986 {
10987   REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
10988                                         const0_rtx,
10989                                         REG_NOTES (insn));
10990 }
10991
10992 /* Emit instructions needed to load the TOC register.
10993    This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
10994    a constant pool; or for SVR4 -fpic.  */
10995
10996 void
10997 rs6000_emit_load_toc_table (int fromprolog)
10998 {
10999   rtx dest, insn;
11000   dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11001
11002   if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11003     {
11004       rtx temp = (fromprolog
11005                   ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11006                   : gen_reg_rtx (Pmode));
11007       insn = emit_insn (gen_load_toc_v4_pic_si (temp));
11008       if (fromprolog)
11009         rs6000_maybe_dead (insn);
11010       insn = emit_move_insn (dest, temp);
11011       if (fromprolog)
11012         rs6000_maybe_dead (insn);
11013     }
11014   else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
11015     {
11016       char buf[30];
11017       rtx tempLR = (fromprolog
11018                     ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11019                     : gen_reg_rtx (Pmode));
11020       rtx temp0 = (fromprolog
11021                    ? gen_rtx_REG (Pmode, 0)
11022                    : gen_reg_rtx (Pmode));
11023       rtx symF;
11024
11025       /* possibly create the toc section */
11026       if (! toc_initialized)
11027         {
11028           toc_section ();
11029           function_section (current_function_decl);
11030         }
11031
11032       if (fromprolog)
11033         {
11034           rtx symL;
11035
11036           ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
11037           symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11038
11039           ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
11040           symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11041
11042           rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
11043                                                                symF)));
11044           rs6000_maybe_dead (emit_move_insn (dest, tempLR));
11045           rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
11046                                                                symL,
11047                                                                symF)));
11048         }
11049       else
11050         {
11051           rtx tocsym;
11052           static int reload_toc_labelno = 0;
11053
11054           tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
11055
11056           ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
11057           symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11058
11059           emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
11060           emit_move_insn (dest, tempLR);
11061           emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
11062         }
11063       insn = emit_insn (gen_addsi3 (dest, temp0, dest));
11064       if (fromprolog)
11065         rs6000_maybe_dead (insn);
11066     }
11067   else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
11068     {
11069       /* This is for AIX code running in non-PIC ELF32.  */
11070       char buf[30];
11071       rtx realsym;
11072       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
11073       realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11074
11075       insn = emit_insn (gen_elf_high (dest, realsym));
11076       if (fromprolog)
11077         rs6000_maybe_dead (insn);
11078       insn = emit_insn (gen_elf_low (dest, dest, realsym));
11079       if (fromprolog)
11080         rs6000_maybe_dead (insn);
11081     }
11082   else if (DEFAULT_ABI == ABI_AIX)
11083     {
11084       if (TARGET_32BIT)
11085         insn = emit_insn (gen_load_toc_aix_si (dest));
11086       else
11087         insn = emit_insn (gen_load_toc_aix_di (dest));
11088       if (fromprolog)
11089         rs6000_maybe_dead (insn);
11090     }
11091   else
11092     abort ();
11093 }
11094
11095 /* Emit instructions to restore the link register after determining where
11096    its value has been stored.  */
11097
11098 void
11099 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
11100 {
11101   rs6000_stack_t *info = rs6000_stack_info ();
11102   rtx operands[2];
11103
11104   operands[0] = source;
11105   operands[1] = scratch;
11106
11107   if (info->lr_save_p)
11108     {
11109       rtx frame_rtx = stack_pointer_rtx;
11110       HOST_WIDE_INT sp_offset = 0;
11111       rtx tmp;
11112
11113       if (frame_pointer_needed
11114           || current_function_calls_alloca
11115           || info->total_size > 32767)
11116         {
11117           emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
11118           frame_rtx = operands[1];
11119         }
11120       else if (info->push_p)
11121         sp_offset = info->total_size;
11122
11123       tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
11124       tmp = gen_rtx_MEM (Pmode, tmp);
11125       emit_move_insn (tmp, operands[0]);
11126     }
11127   else
11128     emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
11129 }
11130
11131 int
11132 get_TOC_alias_set (void)
11133 {
11134     static int set = -1;
11135     if (set == -1)
11136       set = new_alias_set ();
11137     return set;
11138 }
11139
11140 /* This returns nonzero if the current function uses the TOC.  This is
11141    determined by the presence of (use (unspec ... UNSPEC_TOC)), which
11142    is generated by the ABI_V4 load_toc_* patterns.  */
11143
11144 static int
11145 uses_TOC (void)
11146 {
11147   rtx insn;
11148
11149   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11150     if (INSN_P (insn))
11151       {
11152         rtx pat = PATTERN (insn);
11153         int i;
11154
11155         if (GET_CODE (pat) == PARALLEL)
11156           for (i = 0; i < XVECLEN (pat, 0); i++)
11157             {
11158               rtx sub = XVECEXP (pat, 0, i);
11159               if (GET_CODE (sub) == USE)
11160                 {
11161                   sub = XEXP (sub, 0);
11162                   if (GET_CODE (sub) == UNSPEC
11163                       && XINT (sub, 1) == UNSPEC_TOC)
11164                     return 1;
11165                 }
11166             }
11167       }
11168   return 0;
11169 }
11170
11171 rtx
11172 create_TOC_reference (rtx symbol)
11173 {
11174   return gen_rtx_PLUS (Pmode,
11175            gen_rtx_REG (Pmode, TOC_REGISTER),
11176              gen_rtx_CONST (Pmode,
11177                gen_rtx_MINUS (Pmode, symbol,
11178                  gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
11179 }
11180
11181 /* If _Unwind_* has been called from within the same module,
11182    toc register is not guaranteed to be saved to 40(1) on function
11183    entry.  Save it there in that case.  */
11184
11185 void
11186 rs6000_aix_emit_builtin_unwind_init (void)
11187 {
11188   rtx mem;
11189   rtx stack_top = gen_reg_rtx (Pmode);
11190   rtx opcode_addr = gen_reg_rtx (Pmode);
11191   rtx opcode = gen_reg_rtx (SImode);
11192   rtx tocompare = gen_reg_rtx (SImode);
11193   rtx no_toc_save_needed = gen_label_rtx ();
11194
11195   mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
11196   emit_move_insn (stack_top, mem);
11197
11198   mem = gen_rtx_MEM (Pmode,
11199                      gen_rtx_PLUS (Pmode, stack_top,
11200                                    GEN_INT (2 * GET_MODE_SIZE (Pmode))));
11201   emit_move_insn (opcode_addr, mem);
11202   emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
11203   emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
11204                                            : 0xE8410028, SImode));
11205
11206   do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
11207                            SImode, NULL_RTX, NULL_RTX,
11208                            no_toc_save_needed);
11209
11210   mem = gen_rtx_MEM (Pmode,
11211                      gen_rtx_PLUS (Pmode, stack_top,
11212                                    GEN_INT (5 * GET_MODE_SIZE (Pmode))));
11213   emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
11214   emit_label (no_toc_save_needed);
11215 }
11216 \f
11217 /* This ties together stack memory (MEM with an alias set of
11218    rs6000_sr_alias_set) and the change to the stack pointer.  */
11219
11220 static void
11221 rs6000_emit_stack_tie (void)
11222 {
11223   rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
11224
11225   set_mem_alias_set (mem, rs6000_sr_alias_set);
11226   emit_insn (gen_stack_tie (mem));
11227 }
11228
11229 /* Emit the correct code for allocating stack space, as insns.
11230    If COPY_R12, make sure a copy of the old frame is left in r12.
11231    The generated code may use hard register 0 as a temporary.  */
11232
11233 static void
11234 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
11235 {
11236   rtx insn;
11237   rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11238   rtx tmp_reg = gen_rtx_REG (Pmode, 0);
11239   rtx todec = GEN_INT (-size);
11240
11241   if (current_function_limit_stack)
11242     {
11243       if (REG_P (stack_limit_rtx)
11244           && REGNO (stack_limit_rtx) > 1
11245           && REGNO (stack_limit_rtx) <= 31)
11246         {
11247           emit_insn (TARGET_32BIT
11248                      ? gen_addsi3 (tmp_reg,
11249                                    stack_limit_rtx,
11250                                    GEN_INT (size))
11251                      : gen_adddi3 (tmp_reg,
11252                                    stack_limit_rtx,
11253                                    GEN_INT (size)));
11254
11255           emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11256                                     const0_rtx));
11257         }
11258       else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
11259                && TARGET_32BIT
11260                && DEFAULT_ABI == ABI_V4)
11261         {
11262           rtx toload = gen_rtx_CONST (VOIDmode,
11263                                       gen_rtx_PLUS (Pmode,
11264                                                     stack_limit_rtx,
11265                                                     GEN_INT (size)));
11266
11267           emit_insn (gen_elf_high (tmp_reg, toload));
11268           emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
11269           emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11270                                     const0_rtx));
11271         }
11272       else
11273         warning ("stack limit expression is not supported");
11274     }
11275
11276   if (copy_r12 || ! TARGET_UPDATE)
11277     emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
11278
11279   if (TARGET_UPDATE)
11280     {
11281       if (size > 32767)
11282         {
11283           /* Need a note here so that try_split doesn't get confused.  */
11284           if (get_last_insn() == NULL_RTX)
11285             emit_note (NOTE_INSN_DELETED);
11286           insn = emit_move_insn (tmp_reg, todec);
11287           try_split (PATTERN (insn), insn, 0);
11288           todec = tmp_reg;
11289         }
11290
11291       insn = emit_insn (TARGET_32BIT
11292                         ? gen_movsi_update (stack_reg, stack_reg,
11293                                             todec, stack_reg)
11294                         : gen_movdi_update (stack_reg, stack_reg,
11295                                             todec, stack_reg));
11296     }
11297   else
11298     {
11299       insn = emit_insn (TARGET_32BIT
11300                         ? gen_addsi3 (stack_reg, stack_reg, todec)
11301                         : gen_adddi3 (stack_reg, stack_reg, todec));
11302       emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
11303                       gen_rtx_REG (Pmode, 12));
11304     }
11305
11306   RTX_FRAME_RELATED_P (insn) = 1;
11307   REG_NOTES (insn) =
11308     gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11309                        gen_rtx_SET (VOIDmode, stack_reg,
11310                                     gen_rtx_PLUS (Pmode, stack_reg,
11311                                                   GEN_INT (-size))),
11312                        REG_NOTES (insn));
11313 }
11314
11315 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
11316    with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
11317    is not NULL.  It would be nice if dwarf2out_frame_debug_expr could
11318    deduce these equivalences by itself so it wasn't necessary to hold
11319    its hand so much.  */
11320
11321 static void
11322 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
11323                       rtx reg2, rtx rreg)
11324 {
11325   rtx real, temp;
11326
11327   /* copy_rtx will not make unique copies of registers, so we need to
11328      ensure we don't have unwanted sharing here.  */
11329   if (reg == reg2)
11330     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11331
11332   if (reg == rreg)
11333     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11334
11335   real = copy_rtx (PATTERN (insn));
11336
11337   if (reg2 != NULL_RTX)
11338     real = replace_rtx (real, reg2, rreg);
11339
11340   real = replace_rtx (real, reg,
11341                       gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
11342                                                         STACK_POINTER_REGNUM),
11343                                     GEN_INT (val)));
11344
11345   /* We expect that 'real' is either a SET or a PARALLEL containing
11346      SETs (and possibly other stuff).  In a PARALLEL, all the SETs
11347      are important so they all have to be marked RTX_FRAME_RELATED_P.  */
11348
11349   if (GET_CODE (real) == SET)
11350     {
11351       rtx set = real;
11352
11353       temp = simplify_rtx (SET_SRC (set));
11354       if (temp)
11355         SET_SRC (set) = temp;
11356       temp = simplify_rtx (SET_DEST (set));
11357       if (temp)
11358         SET_DEST (set) = temp;
11359       if (GET_CODE (SET_DEST (set)) == MEM)
11360         {
11361           temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11362           if (temp)
11363             XEXP (SET_DEST (set), 0) = temp;
11364         }
11365     }
11366   else if (GET_CODE (real) == PARALLEL)
11367     {
11368       int i;
11369       for (i = 0; i < XVECLEN (real, 0); i++)
11370         if (GET_CODE (XVECEXP (real, 0, i)) == SET)
11371           {
11372             rtx set = XVECEXP (real, 0, i);
11373
11374             temp = simplify_rtx (SET_SRC (set));
11375             if (temp)
11376               SET_SRC (set) = temp;
11377             temp = simplify_rtx (SET_DEST (set));
11378             if (temp)
11379               SET_DEST (set) = temp;
11380             if (GET_CODE (SET_DEST (set)) == MEM)
11381               {
11382                 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11383                 if (temp)
11384                   XEXP (SET_DEST (set), 0) = temp;
11385               }
11386             RTX_FRAME_RELATED_P (set) = 1;
11387           }
11388     }
11389   else
11390     abort ();
11391
11392   if (TARGET_SPE)
11393     real = spe_synthesize_frame_save (real);
11394
11395   RTX_FRAME_RELATED_P (insn) = 1;
11396   REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11397                                         real,
11398                                         REG_NOTES (insn));
11399 }
11400
11401 /* Given an SPE frame note, return a PARALLEL of SETs with the
11402    original note, plus a synthetic register save.  */
11403
11404 static rtx
11405 spe_synthesize_frame_save (rtx real)
11406 {
11407   rtx synth, offset, reg, real2;
11408
11409   if (GET_CODE (real) != SET
11410       || GET_MODE (SET_SRC (real)) != V2SImode)
11411     return real;
11412
11413   /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
11414      frame related note.  The parallel contains a set of the register
11415      being saved, and another set to a synthetic register (n+1200).
11416      This is so we can differentiate between 64-bit and 32-bit saves.
11417      Words cannot describe this nastiness.  */
11418
11419   if (GET_CODE (SET_DEST (real)) != MEM
11420       || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
11421       || GET_CODE (SET_SRC (real)) != REG)
11422     abort ();
11423
11424   /* Transform:
11425        (set (mem (plus (reg x) (const y)))
11426             (reg z))
11427      into:
11428        (set (mem (plus (reg x) (const y+4)))
11429             (reg z+1200))
11430   */
11431
11432   real2 = copy_rtx (real);
11433   PUT_MODE (SET_DEST (real2), SImode);
11434   reg = SET_SRC (real2);
11435   real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
11436   synth = copy_rtx (real2);
11437
11438   if (BYTES_BIG_ENDIAN)
11439     {
11440       offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
11441       real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
11442     }
11443
11444   reg = SET_SRC (synth);
11445
11446   synth = replace_rtx (synth, reg,
11447                        gen_rtx_REG (SImode, REGNO (reg) + 1200));
11448
11449   offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
11450   synth = replace_rtx (synth, offset,
11451                        GEN_INT (INTVAL (offset)
11452                                 + (BYTES_BIG_ENDIAN ? 0 : 4)));
11453
11454   RTX_FRAME_RELATED_P (synth) = 1;
11455   RTX_FRAME_RELATED_P (real2) = 1;
11456   if (BYTES_BIG_ENDIAN)
11457     real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
11458   else
11459     real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
11460
11461   return real;
11462 }
11463
11464 /* Returns an insn that has a vrsave set operation with the
11465    appropriate CLOBBERs.  */
11466
11467 static rtx
11468 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
11469 {
11470   int nclobs, i;
11471   rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
11472   rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11473
11474   clobs[0]
11475     = gen_rtx_SET (VOIDmode,
11476                    vrsave,
11477                    gen_rtx_UNSPEC_VOLATILE (SImode,
11478                                             gen_rtvec (2, reg, vrsave),
11479                                             30));
11480
11481   nclobs = 1;
11482
11483   /* We need to clobber the registers in the mask so the scheduler
11484      does not move sets to VRSAVE before sets of AltiVec registers.
11485
11486      However, if the function receives nonlocal gotos, reload will set
11487      all call saved registers live.  We will end up with:
11488
11489         (set (reg 999) (mem))
11490         (parallel [ (set (reg vrsave) (unspec blah))
11491                     (clobber (reg 999))])
11492
11493      The clobber will cause the store into reg 999 to be dead, and
11494      flow will attempt to delete an epilogue insn.  In this case, we
11495      need an unspec use/set of the register.  */
11496
11497   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11498     if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
11499       {
11500         if (!epiloguep || call_used_regs [i])
11501           clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
11502                                              gen_rtx_REG (V4SImode, i));
11503         else
11504           {
11505             rtx reg = gen_rtx_REG (V4SImode, i);
11506
11507             clobs[nclobs++]
11508               = gen_rtx_SET (VOIDmode,
11509                              reg,
11510                              gen_rtx_UNSPEC (V4SImode,
11511                                              gen_rtvec (1, reg), 27));
11512           }
11513       }
11514
11515   insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
11516
11517   for (i = 0; i < nclobs; ++i)
11518     XVECEXP (insn, 0, i) = clobs[i];
11519
11520   return insn;
11521 }
11522
11523 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
11524    Save REGNO into [FRAME_REG + OFFSET] in mode MODE.  */
11525
11526 static void
11527 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
11528                  unsigned int regno, int offset, HOST_WIDE_INT total_size)
11529 {
11530   rtx reg, offset_rtx, insn, mem, addr, int_rtx;
11531   rtx replacea, replaceb;
11532
11533   int_rtx = GEN_INT (offset);
11534
11535   /* Some cases that need register indexed addressing.  */
11536   if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11537       || (TARGET_SPE_ABI
11538           && SPE_VECTOR_MODE (mode)
11539           && !SPE_CONST_OFFSET_OK (offset)))
11540     {
11541       /* Whomever calls us must make sure r11 is available in the
11542          flow path of instructions in the prologue.  */
11543       offset_rtx = gen_rtx_REG (Pmode, 11);
11544       emit_move_insn (offset_rtx, int_rtx);
11545
11546       replacea = offset_rtx;
11547       replaceb = int_rtx;
11548     }
11549   else
11550     {
11551       offset_rtx = int_rtx;
11552       replacea = NULL_RTX;
11553       replaceb = NULL_RTX;
11554     }
11555
11556   reg = gen_rtx_REG (mode, regno);
11557   addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
11558   mem = gen_rtx_MEM (mode, addr);
11559   set_mem_alias_set (mem, rs6000_sr_alias_set);
11560
11561   insn = emit_move_insn (mem, reg);
11562
11563   rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
11564 }
11565
11566 /* Emit an offset memory reference suitable for a frame store, while
11567    converting to a valid addressing mode.  */
11568
11569 static rtx
11570 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
11571 {
11572   rtx int_rtx, offset_rtx;
11573
11574   int_rtx = GEN_INT (offset);
11575
11576   if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
11577     {
11578       offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11579       emit_move_insn (offset_rtx, int_rtx);
11580     }
11581   else
11582     offset_rtx = int_rtx;
11583
11584   return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
11585 }
11586
11587 /* Emit function prologue as insns.  */
11588
11589 void
11590 rs6000_emit_prologue (void)
11591 {
11592   rs6000_stack_t *info = rs6000_stack_info ();
11593   enum machine_mode reg_mode = Pmode;
11594   int reg_size = UNITS_PER_WORD;
11595   rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11596   rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
11597   rtx frame_reg_rtx = sp_reg_rtx;
11598   rtx cr_save_rtx = NULL_RTX;
11599   rtx insn;
11600   int saving_FPRs_inline;
11601   int using_store_multiple;
11602   HOST_WIDE_INT sp_offset = 0;
11603
11604    if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11605      {
11606        reg_mode = V2SImode;
11607        reg_size = 8;
11608      }
11609
11610   using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
11611                           && (!TARGET_SPE_ABI
11612                               || info->spe_64bit_regs_used == 0)
11613                           && info->first_gp_reg_save < 31);
11614   saving_FPRs_inline = (info->first_fp_reg_save == 64
11615                         || FP_SAVE_INLINE (info->first_fp_reg_save)
11616                         || current_function_calls_eh_return
11617                         || cfun->machine->ra_need_lr);
11618
11619   /* For V.4, update stack before we do any saving and set back pointer.  */
11620   if (info->push_p
11621       && (DEFAULT_ABI == ABI_V4
11622           || current_function_calls_eh_return))
11623     {
11624       if (info->total_size < 32767)
11625         sp_offset = info->total_size;
11626       else
11627         frame_reg_rtx = frame_ptr_rtx;
11628       rs6000_emit_allocate_stack (info->total_size,
11629                                   (frame_reg_rtx != sp_reg_rtx
11630                                    && (info->cr_save_p
11631                                        || info->lr_save_p
11632                                        || info->first_fp_reg_save < 64
11633                                        || info->first_gp_reg_save < 32
11634                                        )));
11635       if (frame_reg_rtx != sp_reg_rtx)
11636         rs6000_emit_stack_tie ();
11637     }
11638
11639   /* Save AltiVec registers if needed.  */
11640   if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
11641     {
11642       int i;
11643
11644       /* There should be a non inline version of this, for when we
11645          are saving lots of vector registers.  */
11646       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
11647         if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
11648           {
11649             rtx areg, savereg, mem;
11650             int offset;
11651
11652             offset = info->altivec_save_offset + sp_offset
11653               + 16 * (i - info->first_altivec_reg_save);
11654
11655             savereg = gen_rtx_REG (V4SImode, i);
11656
11657             areg = gen_rtx_REG (Pmode, 0);
11658             emit_move_insn (areg, GEN_INT (offset));
11659
11660             /* AltiVec addressing mode is [reg+reg].  */
11661             mem = gen_rtx_MEM (V4SImode,
11662                                gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
11663
11664             set_mem_alias_set (mem, rs6000_sr_alias_set);
11665
11666             insn = emit_move_insn (mem, savereg);
11667
11668             rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11669                                   areg, GEN_INT (offset));
11670           }
11671     }
11672
11673   /* VRSAVE is a bit vector representing which AltiVec registers
11674      are used.  The OS uses this to determine which vector
11675      registers to save on a context switch.  We need to save
11676      VRSAVE on the stack frame, add whatever AltiVec registers we
11677      used in this function, and do the corresponding magic in the
11678      epilogue.  */
11679
11680   if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
11681       && info->vrsave_mask != 0)
11682     {
11683       rtx reg, mem, vrsave;
11684       int offset;
11685
11686       /* Get VRSAVE onto a GPR.  */
11687       reg = gen_rtx_REG (SImode, 12);
11688       vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11689       if (TARGET_MACHO)
11690         emit_insn (gen_get_vrsave_internal (reg));
11691       else
11692         emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
11693
11694       /* Save VRSAVE.  */
11695       offset = info->vrsave_save_offset + sp_offset;
11696       mem
11697         = gen_rtx_MEM (SImode,
11698                        gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
11699       set_mem_alias_set (mem, rs6000_sr_alias_set);
11700       insn = emit_move_insn (mem, reg);
11701
11702       /* Include the registers in the mask.  */
11703       emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
11704
11705       insn = emit_insn (generate_set_vrsave (reg, info, 0));
11706     }
11707
11708   /* If we use the link register, get it into r0.  */
11709   if (info->lr_save_p)
11710     emit_move_insn (gen_rtx_REG (Pmode, 0),
11711                     gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11712
11713   /* If we need to save CR, put it into r12.  */
11714   if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
11715     {
11716       cr_save_rtx = gen_rtx_REG (SImode, 12);
11717       emit_insn (gen_movesi_from_cr (cr_save_rtx));
11718     }
11719
11720   /* Do any required saving of fpr's.  If only one or two to save, do
11721      it ourselves.  Otherwise, call function.  */
11722   if (saving_FPRs_inline)
11723     {
11724       int i;
11725       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11726         if ((regs_ever_live[info->first_fp_reg_save+i]
11727              && ! call_used_regs[info->first_fp_reg_save+i]))
11728           emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
11729                            info->first_fp_reg_save + i,
11730                            info->fp_save_offset + sp_offset + 8 * i,
11731                            info->total_size);
11732     }
11733   else if (info->first_fp_reg_save != 64)
11734     {
11735       int i;
11736       char rname[30];
11737       const char *alloc_rname;
11738       rtvec p;
11739       p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
11740
11741       RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
11742                                           gen_rtx_REG (Pmode,
11743                                                        LINK_REGISTER_REGNUM));
11744       sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
11745                info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
11746       alloc_rname = ggc_strdup (rname);
11747       RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
11748                                       gen_rtx_SYMBOL_REF (Pmode,
11749                                                           alloc_rname));
11750       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11751         {
11752           rtx addr, reg, mem;
11753           reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
11754           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11755                                GEN_INT (info->fp_save_offset
11756                                         + sp_offset + 8*i));
11757           mem = gen_rtx_MEM (DFmode, addr);
11758           set_mem_alias_set (mem, rs6000_sr_alias_set);
11759
11760           RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
11761         }
11762       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11763       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11764                             NULL_RTX, NULL_RTX);
11765     }
11766
11767   /* Save GPRs.  This is done as a PARALLEL if we are using
11768      the store-multiple instructions.  */
11769   if (using_store_multiple)
11770     {
11771       rtvec p;
11772       int i;
11773       p = rtvec_alloc (32 - info->first_gp_reg_save);
11774       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11775         {
11776           rtx addr, reg, mem;
11777           reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11778           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11779                                GEN_INT (info->gp_save_offset
11780                                         + sp_offset
11781                                         + reg_size * i));
11782           mem = gen_rtx_MEM (reg_mode, addr);
11783           set_mem_alias_set (mem, rs6000_sr_alias_set);
11784
11785           RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
11786         }
11787       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11788       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11789                             NULL_RTX, NULL_RTX);
11790     }
11791   else
11792     {
11793       int i;
11794       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11795         if ((regs_ever_live[info->first_gp_reg_save+i]
11796              && ! call_used_regs[info->first_gp_reg_save+i])
11797             || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
11798                 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11799                     || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
11800           {
11801             rtx addr, reg, mem;
11802             reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11803
11804             if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11805               {
11806                 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
11807                 rtx b;
11808
11809                 if (!SPE_CONST_OFFSET_OK (offset))
11810                   {
11811                     b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11812                     emit_move_insn (b, GEN_INT (offset));
11813                   }
11814                 else
11815                   b = GEN_INT (offset);
11816
11817                 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
11818                 mem = gen_rtx_MEM (V2SImode, addr);
11819                 set_mem_alias_set (mem, rs6000_sr_alias_set);
11820                 insn = emit_move_insn (mem, reg);
11821
11822                 if (GET_CODE (b) == CONST_INT)
11823                   rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11824                                         NULL_RTX, NULL_RTX);
11825                 else
11826                   rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11827                                         b, GEN_INT (offset));
11828               }
11829             else
11830               {
11831                 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11832                                      GEN_INT (info->gp_save_offset
11833                                               + sp_offset
11834                                               + reg_size * i));
11835                 mem = gen_rtx_MEM (reg_mode, addr);
11836                 set_mem_alias_set (mem, rs6000_sr_alias_set);
11837
11838                 insn = emit_move_insn (mem, reg);
11839                 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11840                                       NULL_RTX, NULL_RTX);
11841               }
11842           }
11843     }
11844
11845   /* ??? There's no need to emit actual instructions here, but it's the
11846      easiest way to get the frame unwind information emitted.  */
11847   if (current_function_calls_eh_return)
11848     {
11849       unsigned int i, regno;
11850
11851       /* In AIX ABI we need to pretend we save r2 here.  */
11852       if (TARGET_AIX)
11853         {
11854           rtx addr, reg, mem;
11855
11856           reg = gen_rtx_REG (reg_mode, 2);
11857           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11858                                GEN_INT (sp_offset + 5 * reg_size));
11859           mem = gen_rtx_MEM (reg_mode, addr);
11860           set_mem_alias_set (mem, rs6000_sr_alias_set);
11861
11862           insn = emit_move_insn (mem, reg);
11863           rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11864                                 NULL_RTX, NULL_RTX);
11865           PATTERN (insn) = gen_blockage ();
11866         }
11867
11868       for (i = 0; ; ++i)
11869         {
11870           regno = EH_RETURN_DATA_REGNO (i);
11871           if (regno == INVALID_REGNUM)
11872             break;
11873
11874           emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
11875                            info->ehrd_offset + sp_offset
11876                            + reg_size * (int) i,
11877                            info->total_size);
11878         }
11879     }
11880
11881   /* Save lr if we used it.  */
11882   if (info->lr_save_p)
11883     {
11884       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11885                                GEN_INT (info->lr_save_offset + sp_offset));
11886       rtx reg = gen_rtx_REG (Pmode, 0);
11887       rtx mem = gen_rtx_MEM (Pmode, addr);
11888       /* This should not be of rs6000_sr_alias_set, because of
11889          __builtin_return_address.  */
11890
11891       insn = emit_move_insn (mem, reg);
11892       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11893                             reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11894     }
11895
11896   /* Save CR if we use any that must be preserved.  */
11897   if (info->cr_save_p)
11898     {
11899       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11900                                GEN_INT (info->cr_save_offset + sp_offset));
11901       rtx mem = gen_rtx_MEM (SImode, addr);
11902
11903       set_mem_alias_set (mem, rs6000_sr_alias_set);
11904
11905       /* If r12 was used to hold the original sp, copy cr into r0 now
11906          that it's free.  */
11907       if (REGNO (frame_reg_rtx) == 12)
11908         {
11909           cr_save_rtx = gen_rtx_REG (SImode, 0);
11910           emit_insn (gen_movesi_from_cr (cr_save_rtx));
11911         }
11912       insn = emit_move_insn (mem, cr_save_rtx);
11913
11914       /* Now, there's no way that dwarf2out_frame_debug_expr is going
11915          to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
11916          But that's OK.  All we have to do is specify that _one_ condition
11917          code register is saved in this stack slot.  The thrower's epilogue
11918          will then restore all the call-saved registers.
11919          We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux.  */
11920       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11921                             cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
11922     }
11923
11924   /* Update stack and set back pointer unless this is V.4,
11925      for which it was done previously.  */
11926   if (info->push_p
11927       && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
11928     rs6000_emit_allocate_stack (info->total_size, FALSE);
11929
11930   /* Set frame pointer, if needed.  */
11931   if (frame_pointer_needed)
11932     {
11933       insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
11934                              sp_reg_rtx);
11935       RTX_FRAME_RELATED_P (insn) = 1;
11936     }
11937
11938   /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up.  */
11939   if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
11940       || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
11941           && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
11942   {
11943     /* If emit_load_toc_table will use the link register, we need to save
11944        it.  We use R12 for this purpose because emit_load_toc_table
11945        can use register 0.  This allows us to use a plain 'blr' to return
11946        from the procedure more often.  */
11947     int save_LR_around_toc_setup = (TARGET_ELF
11948                                     && DEFAULT_ABI != ABI_AIX
11949                                     && flag_pic
11950                                     && ! info->lr_save_p
11951                                     && EXIT_BLOCK_PTR->pred != NULL);
11952     if (save_LR_around_toc_setup)
11953       {
11954         rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11955         rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr));
11956         rs6000_emit_load_toc_table (TRUE);
11957         rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx));
11958       }
11959     else
11960       rs6000_emit_load_toc_table (TRUE);
11961   }
11962
11963 #if TARGET_MACHO
11964   if (DEFAULT_ABI == ABI_DARWIN
11965       && flag_pic && current_function_uses_pic_offset_table)
11966     {
11967       rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11968       const char *picbase = machopic_function_base_name ();
11969       rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase);
11970
11971       rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
11972
11973       rs6000_maybe_dead (
11974         emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
11975                         gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
11976     }
11977 #endif
11978 }
11979
11980 /* Write function prologue.  */
11981
11982 static void
11983 rs6000_output_function_prologue (FILE *file,
11984                                  HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11985 {
11986   rs6000_stack_t *info = rs6000_stack_info ();
11987
11988   if (TARGET_DEBUG_STACK)
11989     debug_stack_info (info);
11990
11991   /* Write .extern for any function we will call to save and restore
11992      fp values.  */
11993   if (info->first_fp_reg_save < 64
11994       && !FP_SAVE_INLINE (info->first_fp_reg_save))
11995     fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
11996              SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
11997              RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
11998              RESTORE_FP_SUFFIX);
11999
12000   /* Write .extern for AIX common mode routines, if needed.  */
12001   if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
12002     {
12003       fputs ("\t.extern __mulh\n", file);
12004       fputs ("\t.extern __mull\n", file);
12005       fputs ("\t.extern __divss\n", file);
12006       fputs ("\t.extern __divus\n", file);
12007       fputs ("\t.extern __quoss\n", file);
12008       fputs ("\t.extern __quous\n", file);
12009       common_mode_defined = 1;
12010     }
12011
12012   if (! HAVE_prologue)
12013     {
12014       start_sequence ();
12015
12016       /* A NOTE_INSN_DELETED is supposed to be at the start and end of
12017          the "toplevel" insn chain.  */
12018       emit_note (NOTE_INSN_DELETED);
12019       rs6000_emit_prologue ();
12020       emit_note (NOTE_INSN_DELETED);
12021
12022       /* Expand INSN_ADDRESSES so final() doesn't crash.  */
12023       {
12024         rtx insn;
12025         unsigned addr = 0;
12026         for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12027           {
12028             INSN_ADDRESSES_NEW (insn, addr);
12029             addr += 4;
12030           }
12031       }
12032
12033       if (TARGET_DEBUG_STACK)
12034         debug_rtx_list (get_insns (), 100);
12035       final (get_insns (), file, FALSE, FALSE);
12036       end_sequence ();
12037     }
12038
12039   rs6000_pic_labelno++;
12040 }
12041
12042 /* Emit function epilogue as insns.
12043
12044    At present, dwarf2out_frame_debug_expr doesn't understand
12045    register restores, so we don't bother setting RTX_FRAME_RELATED_P
12046    anywhere in the epilogue.  Most of the insns below would in any case
12047    need special notes to explain where r11 is in relation to the stack.  */
12048
12049 void
12050 rs6000_emit_epilogue (int sibcall)
12051 {
12052   rs6000_stack_t *info;
12053   int restoring_FPRs_inline;
12054   int using_load_multiple;
12055   int using_mfcr_multiple;
12056   int use_backchain_to_restore_sp;
12057   int sp_offset = 0;
12058   rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
12059   rtx frame_reg_rtx = sp_reg_rtx;
12060   enum machine_mode reg_mode = Pmode;
12061   int reg_size = UNITS_PER_WORD;
12062   int i;
12063
12064   info = rs6000_stack_info ();
12065
12066   if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12067     {
12068       reg_mode = V2SImode;
12069       reg_size = 8;
12070     }
12071
12072   using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12073                          && (!TARGET_SPE_ABI
12074                              || info->spe_64bit_regs_used == 0)
12075                          && info->first_gp_reg_save < 31);
12076   restoring_FPRs_inline = (sibcall
12077                            || current_function_calls_eh_return
12078                            || info->first_fp_reg_save == 64
12079                            || FP_SAVE_INLINE (info->first_fp_reg_save));
12080   use_backchain_to_restore_sp = (frame_pointer_needed
12081                                  || current_function_calls_alloca
12082                                  || info->total_size > 32767);
12083   using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
12084                          || rs6000_cpu == PROCESSOR_PPC603
12085                          || rs6000_cpu == PROCESSOR_PPC750
12086                          || optimize_size);
12087
12088   /* If we have a frame pointer, a call to alloca,  or a large stack
12089      frame, restore the old stack pointer using the backchain.  Otherwise,
12090      we know what size to update it with.  */
12091   if (use_backchain_to_restore_sp)
12092     {
12093       /* Under V.4, don't reset the stack pointer until after we're done
12094          loading the saved registers.  */
12095       if (DEFAULT_ABI == ABI_V4)
12096         frame_reg_rtx = gen_rtx_REG (Pmode, 11);
12097
12098       emit_move_insn (frame_reg_rtx,
12099                       gen_rtx_MEM (Pmode, sp_reg_rtx));
12100
12101     }
12102   else if (info->push_p)
12103     {
12104       if (DEFAULT_ABI == ABI_V4
12105           || current_function_calls_eh_return)
12106         sp_offset = info->total_size;
12107       else
12108         {
12109           emit_insn (TARGET_32BIT
12110                      ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12111                                    GEN_INT (info->total_size))
12112                      : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12113                                    GEN_INT (info->total_size)));
12114         }
12115     }
12116
12117   /* Restore AltiVec registers if needed.  */
12118   if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12119     {
12120       int i;
12121
12122       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12123         if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12124           {
12125             rtx addr, areg, mem;
12126
12127             areg = gen_rtx_REG (Pmode, 0);
12128             emit_move_insn
12129               (areg, GEN_INT (info->altivec_save_offset
12130                               + sp_offset
12131                               + 16 * (i - info->first_altivec_reg_save)));
12132
12133             /* AltiVec addressing mode is [reg+reg].  */
12134             addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
12135             mem = gen_rtx_MEM (V4SImode, addr);
12136             set_mem_alias_set (mem, rs6000_sr_alias_set);
12137
12138             emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
12139           }
12140     }
12141
12142   /* Restore VRSAVE if needed.  */
12143   if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE
12144       && info->vrsave_mask != 0)
12145     {
12146       rtx addr, mem, reg;
12147
12148       addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12149                            GEN_INT (info->vrsave_save_offset + sp_offset));
12150       mem = gen_rtx_MEM (SImode, addr);
12151       set_mem_alias_set (mem, rs6000_sr_alias_set);
12152       reg = gen_rtx_REG (SImode, 12);
12153       emit_move_insn (reg, mem);
12154
12155       emit_insn (generate_set_vrsave (reg, info, 1));
12156     }
12157
12158   /* Get the old lr if we saved it.  */
12159   if (info->lr_save_p)
12160     {
12161       rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
12162                                       info->lr_save_offset + sp_offset);
12163
12164       set_mem_alias_set (mem, rs6000_sr_alias_set);
12165
12166       emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
12167     }
12168
12169   /* Get the old cr if we saved it.  */
12170   if (info->cr_save_p)
12171     {
12172       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12173                                GEN_INT (info->cr_save_offset + sp_offset));
12174       rtx mem = gen_rtx_MEM (SImode, addr);
12175
12176       set_mem_alias_set (mem, rs6000_sr_alias_set);
12177
12178       emit_move_insn (gen_rtx_REG (SImode, 12), mem);
12179     }
12180
12181   /* Set LR here to try to overlap restores below.  */
12182   if (info->lr_save_p)
12183     emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
12184                     gen_rtx_REG (Pmode, 0));
12185
12186   /* Load exception handler data registers, if needed.  */
12187   if (current_function_calls_eh_return)
12188     {
12189       unsigned int i, regno;
12190
12191       if (TARGET_AIX)
12192         {
12193           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12194                                    GEN_INT (sp_offset + 5 * reg_size));
12195           rtx mem = gen_rtx_MEM (reg_mode, addr);
12196
12197           set_mem_alias_set (mem, rs6000_sr_alias_set);
12198
12199           emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
12200         }
12201
12202       for (i = 0; ; ++i)
12203         {
12204           rtx mem;
12205
12206           regno = EH_RETURN_DATA_REGNO (i);
12207           if (regno == INVALID_REGNUM)
12208             break;
12209
12210           mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
12211                                       info->ehrd_offset + sp_offset
12212                                       + reg_size * (int) i);
12213           set_mem_alias_set (mem, rs6000_sr_alias_set);
12214
12215           emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
12216         }
12217     }
12218
12219   /* Restore GPRs.  This is done as a PARALLEL if we are using
12220      the load-multiple instructions.  */
12221   if (using_load_multiple)
12222     {
12223       rtvec p;
12224       p = rtvec_alloc (32 - info->first_gp_reg_save);
12225       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12226         {
12227           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12228                                    GEN_INT (info->gp_save_offset
12229                                             + sp_offset
12230                                             + reg_size * i));
12231           rtx mem = gen_rtx_MEM (reg_mode, addr);
12232
12233           set_mem_alias_set (mem, rs6000_sr_alias_set);
12234
12235           RTVEC_ELT (p, i) =
12236             gen_rtx_SET (VOIDmode,
12237                          gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
12238                          mem);
12239         }
12240       emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12241     }
12242   else
12243     for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12244       if ((regs_ever_live[info->first_gp_reg_save+i]
12245            && ! call_used_regs[info->first_gp_reg_save+i])
12246           || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12247               && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12248                   || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12249         {
12250           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12251                                    GEN_INT (info->gp_save_offset
12252                                             + sp_offset
12253                                             + reg_size * i));
12254           rtx mem = gen_rtx_MEM (reg_mode, addr);
12255
12256           /* Restore 64-bit quantities for SPE.  */
12257           if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12258             {
12259               int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12260               rtx b;
12261
12262               if (!SPE_CONST_OFFSET_OK (offset))
12263                 {
12264                   b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12265                   emit_move_insn (b, GEN_INT (offset));
12266                 }
12267               else
12268                 b = GEN_INT (offset);
12269
12270               addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12271               mem = gen_rtx_MEM (V2SImode, addr);
12272             }
12273
12274           set_mem_alias_set (mem, rs6000_sr_alias_set);
12275
12276           emit_move_insn (gen_rtx_REG (reg_mode,
12277                                        info->first_gp_reg_save + i), mem);
12278         }
12279
12280   /* Restore fpr's if we need to do it without calling a function.  */
12281   if (restoring_FPRs_inline)
12282     for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12283       if ((regs_ever_live[info->first_fp_reg_save+i]
12284            && ! call_used_regs[info->first_fp_reg_save+i]))
12285         {
12286           rtx addr, mem;
12287           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12288                                GEN_INT (info->fp_save_offset
12289                                         + sp_offset
12290                                         + 8 * i));
12291           mem = gen_rtx_MEM (DFmode, addr);
12292           set_mem_alias_set (mem, rs6000_sr_alias_set);
12293
12294           emit_move_insn (gen_rtx_REG (DFmode,
12295                                        info->first_fp_reg_save + i),
12296                           mem);
12297         }
12298
12299   /* If we saved cr, restore it here.  Just those that were used.  */
12300   if (info->cr_save_p)
12301     {
12302       rtx r12_rtx = gen_rtx_REG (SImode, 12);
12303       int count = 0;
12304
12305       if (using_mfcr_multiple)
12306         {
12307           for (i = 0; i < 8; i++)
12308             if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12309               count++;
12310           if (count == 0)
12311             abort ();
12312         }
12313
12314       if (using_mfcr_multiple && count > 1)
12315         {
12316           rtvec p;
12317           int ndx;
12318
12319           p = rtvec_alloc (count);
12320
12321           ndx = 0;
12322           for (i = 0; i < 8; i++)
12323             if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12324               {
12325                 rtvec r = rtvec_alloc (2);
12326                 RTVEC_ELT (r, 0) = r12_rtx;
12327                 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
12328                 RTVEC_ELT (p, ndx) =
12329                   gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
12330                                gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
12331                 ndx++;
12332               }
12333           emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12334           if (ndx != count)
12335             abort ();
12336         }
12337       else
12338         for (i = 0; i < 8; i++)
12339           if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12340             {
12341               emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
12342                                                            CR0_REGNO+i),
12343                                               r12_rtx));
12344             }
12345     }
12346
12347   /* If this is V.4, unwind the stack pointer after all of the loads
12348      have been done.  We need to emit a block here so that sched
12349      doesn't decide to move the sp change before the register restores
12350      (which may not have any obvious dependency on the stack).  This
12351      doesn't hurt performance, because there is no scheduling that can
12352      be done after this point.  */
12353   if (DEFAULT_ABI == ABI_V4
12354       || current_function_calls_eh_return)
12355     {
12356       if (frame_reg_rtx != sp_reg_rtx)
12357           rs6000_emit_stack_tie ();
12358
12359       if (use_backchain_to_restore_sp)
12360         {
12361           emit_move_insn (sp_reg_rtx, frame_reg_rtx);
12362         }
12363       else if (sp_offset != 0)
12364         {
12365           emit_insn (TARGET_32BIT
12366                      ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12367                                    GEN_INT (sp_offset))
12368                      : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12369                                    GEN_INT (sp_offset)));
12370         }
12371     }
12372
12373   if (current_function_calls_eh_return)
12374     {
12375       rtx sa = EH_RETURN_STACKADJ_RTX;
12376       emit_insn (TARGET_32BIT
12377                  ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
12378                  : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
12379     }
12380
12381   if (!sibcall)
12382     {
12383       rtvec p;
12384       if (! restoring_FPRs_inline)
12385         p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
12386       else
12387         p = rtvec_alloc (2);
12388
12389       RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
12390       RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12391                                       gen_rtx_REG (Pmode,
12392                                                    LINK_REGISTER_REGNUM));
12393
12394       /* If we have to restore more than two FP registers, branch to the
12395          restore function.  It will return to our caller.  */
12396       if (! restoring_FPRs_inline)
12397         {
12398           int i;
12399           char rname[30];
12400           const char *alloc_rname;
12401
12402           sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
12403                    info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
12404           alloc_rname = ggc_strdup (rname);
12405           RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
12406                                           gen_rtx_SYMBOL_REF (Pmode,
12407                                                               alloc_rname));
12408
12409           for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12410             {
12411               rtx addr, mem;
12412               addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
12413                                    GEN_INT (info->fp_save_offset + 8*i));
12414               mem = gen_rtx_MEM (DFmode, addr);
12415               set_mem_alias_set (mem, rs6000_sr_alias_set);
12416
12417               RTVEC_ELT (p, i+3) =
12418                 gen_rtx_SET (VOIDmode,
12419                              gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
12420                              mem);
12421             }
12422         }
12423
12424       emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
12425     }
12426 }
12427
12428 /* Write function epilogue.  */
12429
12430 static void
12431 rs6000_output_function_epilogue (FILE *file,
12432                                  HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12433 {
12434   rs6000_stack_t *info = rs6000_stack_info ();
12435
12436   if (! HAVE_epilogue)
12437     {
12438       rtx insn = get_last_insn ();
12439       /* If the last insn was a BARRIER, we don't have to write anything except
12440          the trace table.  */
12441       if (GET_CODE (insn) == NOTE)
12442         insn = prev_nonnote_insn (insn);
12443       if (insn == 0 ||  GET_CODE (insn) != BARRIER)
12444         {
12445           /* This is slightly ugly, but at least we don't have two
12446              copies of the epilogue-emitting code.  */
12447           start_sequence ();
12448
12449           /* A NOTE_INSN_DELETED is supposed to be at the start
12450              and end of the "toplevel" insn chain.  */
12451           emit_note (NOTE_INSN_DELETED);
12452           rs6000_emit_epilogue (FALSE);
12453           emit_note (NOTE_INSN_DELETED);
12454
12455           /* Expand INSN_ADDRESSES so final() doesn't crash.  */
12456           {
12457             rtx insn;
12458             unsigned addr = 0;
12459             for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12460               {
12461                 INSN_ADDRESSES_NEW (insn, addr);
12462                 addr += 4;
12463               }
12464           }
12465
12466           if (TARGET_DEBUG_STACK)
12467             debug_rtx_list (get_insns (), 100);
12468           final (get_insns (), file, FALSE, FALSE);
12469           end_sequence ();
12470         }
12471     }
12472
12473 #if TARGET_MACHO
12474   macho_branch_islands ();
12475   /* Mach-O doesn't support labels at the end of objects, so if
12476      it looks like we might want one, insert a NOP.  */
12477   {
12478     rtx insn = get_last_insn ();
12479     while (insn
12480            && NOTE_P (insn)
12481            && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
12482       insn = PREV_INSN (insn);
12483     if (insn
12484         && (LABEL_P (insn)
12485             || (NOTE_P (insn)
12486                 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
12487       fputs ("\tnop\n", file);
12488   }
12489 #endif
12490
12491   /* Output a traceback table here.  See /usr/include/sys/debug.h for info
12492      on its format.
12493
12494      We don't output a traceback table if -finhibit-size-directive was
12495      used.  The documentation for -finhibit-size-directive reads
12496      ``don't output a @code{.size} assembler directive, or anything
12497      else that would cause trouble if the function is split in the
12498      middle, and the two halves are placed at locations far apart in
12499      memory.''  The traceback table has this property, since it
12500      includes the offset from the start of the function to the
12501      traceback table itself.
12502
12503      System V.4 Powerpc's (and the embedded ABI derived from it) use a
12504      different traceback table.  */
12505   if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
12506       && rs6000_traceback != traceback_none)
12507     {
12508       const char *fname = NULL;
12509       const char *language_string = lang_hooks.name;
12510       int fixed_parms = 0, float_parms = 0, parm_info = 0;
12511       int i;
12512       int optional_tbtab;
12513
12514       if (rs6000_traceback == traceback_full)
12515         optional_tbtab = 1;
12516       else if (rs6000_traceback == traceback_part)
12517         optional_tbtab = 0;
12518       else
12519         optional_tbtab = !optimize_size && !TARGET_ELF;
12520
12521       if (optional_tbtab)
12522         {
12523           fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12524           while (*fname == '.') /* V.4 encodes . in the name */
12525             fname++;
12526
12527           /* Need label immediately before tbtab, so we can compute
12528              its offset from the function start.  */
12529           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12530           ASM_OUTPUT_LABEL (file, fname);
12531         }
12532
12533       /* The .tbtab pseudo-op can only be used for the first eight
12534          expressions, since it can't handle the possibly variable
12535          length fields that follow.  However, if you omit the optional
12536          fields, the assembler outputs zeros for all optional fields
12537          anyways, giving each variable length field is minimum length
12538          (as defined in sys/debug.h).  Thus we can not use the .tbtab
12539          pseudo-op at all.  */
12540
12541       /* An all-zero word flags the start of the tbtab, for debuggers
12542          that have to find it by searching forward from the entry
12543          point or from the current pc.  */
12544       fputs ("\t.long 0\n", file);
12545
12546       /* Tbtab format type.  Use format type 0.  */
12547       fputs ("\t.byte 0,", file);
12548
12549       /* Language type.  Unfortunately, there does not seem to be any
12550          official way to discover the language being compiled, so we
12551          use language_string.
12552          C is 0.  Fortran is 1.  Pascal is 2.  Ada is 3.  C++ is 9.
12553          Java is 13.  Objective-C is 14.  */
12554       if (! strcmp (language_string, "GNU C"))
12555         i = 0;
12556       else if (! strcmp (language_string, "GNU F77"))
12557         i = 1;
12558       else if (! strcmp (language_string, "GNU Pascal"))
12559         i = 2;
12560       else if (! strcmp (language_string, "GNU Ada"))
12561         i = 3;
12562       else if (! strcmp (language_string, "GNU C++"))
12563         i = 9;
12564       else if (! strcmp (language_string, "GNU Java"))
12565         i = 13;
12566       else if (! strcmp (language_string, "GNU Objective-C"))
12567         i = 14;
12568       else
12569         abort ();
12570       fprintf (file, "%d,", i);
12571
12572       /* 8 single bit fields: global linkage (not set for C extern linkage,
12573          apparently a PL/I convention?), out-of-line epilogue/prologue, offset
12574          from start of procedure stored in tbtab, internal function, function
12575          has controlled storage, function has no toc, function uses fp,
12576          function logs/aborts fp operations.  */
12577       /* Assume that fp operations are used if any fp reg must be saved.  */
12578       fprintf (file, "%d,",
12579                (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
12580
12581       /* 6 bitfields: function is interrupt handler, name present in
12582          proc table, function calls alloca, on condition directives
12583          (controls stack walks, 3 bits), saves condition reg, saves
12584          link reg.  */
12585       /* The `function calls alloca' bit seems to be set whenever reg 31 is
12586          set up as a frame pointer, even when there is no alloca call.  */
12587       fprintf (file, "%d,",
12588                ((optional_tbtab << 6)
12589                 | ((optional_tbtab & frame_pointer_needed) << 5)
12590                 | (info->cr_save_p << 1)
12591                 | (info->lr_save_p)));
12592
12593       /* 3 bitfields: saves backchain, fixup code, number of fpr saved
12594          (6 bits).  */
12595       fprintf (file, "%d,",
12596                (info->push_p << 7) | (64 - info->first_fp_reg_save));
12597
12598       /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits).  */
12599       fprintf (file, "%d,", (32 - first_reg_to_save ()));
12600
12601       if (optional_tbtab)
12602         {
12603           /* Compute the parameter info from the function decl argument
12604              list.  */
12605           tree decl;
12606           int next_parm_info_bit = 31;
12607
12608           for (decl = DECL_ARGUMENTS (current_function_decl);
12609                decl; decl = TREE_CHAIN (decl))
12610             {
12611               rtx parameter = DECL_INCOMING_RTL (decl);
12612               enum machine_mode mode = GET_MODE (parameter);
12613
12614               if (GET_CODE (parameter) == REG)
12615                 {
12616                   if (GET_MODE_CLASS (mode) == MODE_FLOAT)
12617                     {
12618                       int bits;
12619
12620                       float_parms++;
12621
12622                       if (mode == SFmode)
12623                         bits = 0x2;
12624                       else if (mode == DFmode || mode == TFmode)
12625                         bits = 0x3;
12626                       else
12627                         abort ();
12628
12629                       /* If only one bit will fit, don't or in this entry.  */
12630                       if (next_parm_info_bit > 0)
12631                         parm_info |= (bits << (next_parm_info_bit - 1));
12632                       next_parm_info_bit -= 2;
12633                     }
12634                   else
12635                     {
12636                       fixed_parms += ((GET_MODE_SIZE (mode)
12637                                        + (UNITS_PER_WORD - 1))
12638                                       / UNITS_PER_WORD);
12639                       next_parm_info_bit -= 1;
12640                     }
12641                 }
12642             }
12643         }
12644
12645       /* Number of fixed point parameters.  */
12646       /* This is actually the number of words of fixed point parameters; thus
12647          an 8 byte struct counts as 2; and thus the maximum value is 8.  */
12648       fprintf (file, "%d,", fixed_parms);
12649
12650       /* 2 bitfields: number of floating point parameters (7 bits), parameters
12651          all on stack.  */
12652       /* This is actually the number of fp registers that hold parameters;
12653          and thus the maximum value is 13.  */
12654       /* Set parameters on stack bit if parameters are not in their original
12655          registers, regardless of whether they are on the stack?  Xlc
12656          seems to set the bit when not optimizing.  */
12657       fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
12658
12659       if (! optional_tbtab)
12660         return;
12661
12662       /* Optional fields follow.  Some are variable length.  */
12663
12664       /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
12665          11 double float.  */
12666       /* There is an entry for each parameter in a register, in the order that
12667          they occur in the parameter list.  Any intervening arguments on the
12668          stack are ignored.  If the list overflows a long (max possible length
12669          34 bits) then completely leave off all elements that don't fit.  */
12670       /* Only emit this long if there was at least one parameter.  */
12671       if (fixed_parms || float_parms)
12672         fprintf (file, "\t.long %d\n", parm_info);
12673
12674       /* Offset from start of code to tb table.  */
12675       fputs ("\t.long ", file);
12676       ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12677 #if TARGET_AIX
12678       RS6000_OUTPUT_BASENAME (file, fname);
12679 #else
12680       assemble_name (file, fname);
12681 #endif
12682       fputs ("-.", file);
12683 #if TARGET_AIX
12684       RS6000_OUTPUT_BASENAME (file, fname);
12685 #else
12686       assemble_name (file, fname);
12687 #endif
12688       putc ('\n', file);
12689
12690       /* Interrupt handler mask.  */
12691       /* Omit this long, since we never set the interrupt handler bit
12692          above.  */
12693
12694       /* Number of CTL (controlled storage) anchors.  */
12695       /* Omit this long, since the has_ctl bit is never set above.  */
12696
12697       /* Displacement into stack of each CTL anchor.  */
12698       /* Omit this list of longs, because there are no CTL anchors.  */
12699
12700       /* Length of function name.  */
12701       if (*fname == '*')
12702         ++fname;
12703       fprintf (file, "\t.short %d\n", (int) strlen (fname));
12704
12705       /* Function name.  */
12706       assemble_string (fname, strlen (fname));
12707
12708       /* Register for alloca automatic storage; this is always reg 31.
12709          Only emit this if the alloca bit was set above.  */
12710       if (frame_pointer_needed)
12711         fputs ("\t.byte 31\n", file);
12712
12713       fputs ("\t.align 2\n", file);
12714     }
12715 }
12716 \f
12717 /* A C compound statement that outputs the assembler code for a thunk
12718    function, used to implement C++ virtual function calls with
12719    multiple inheritance.  The thunk acts as a wrapper around a virtual
12720    function, adjusting the implicit object parameter before handing
12721    control off to the real function.
12722
12723    First, emit code to add the integer DELTA to the location that
12724    contains the incoming first argument.  Assume that this argument
12725    contains a pointer, and is the one used to pass the `this' pointer
12726    in C++.  This is the incoming argument *before* the function
12727    prologue, e.g. `%o0' on a sparc.  The addition must preserve the
12728    values of all other incoming arguments.
12729
12730    After the addition, emit code to jump to FUNCTION, which is a
12731    `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does
12732    not touch the return address.  Hence returning from FUNCTION will
12733    return to whoever called the current `thunk'.
12734
12735    The effect must be as if FUNCTION had been called directly with the
12736    adjusted first argument.  This macro is responsible for emitting
12737    all of the code for a thunk function; output_function_prologue()
12738    and output_function_epilogue() are not invoked.
12739
12740    The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already
12741    been extracted from it.)  It might possibly be useful on some
12742    targets, but probably not.
12743
12744    If you do not define this macro, the target-independent code in the
12745    C++ frontend will generate a less efficient heavyweight thunk that
12746    calls FUNCTION instead of jumping to it.  The generic approach does
12747    not support varargs.  */
12748
12749 static void
12750 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
12751                         HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
12752                         tree function)
12753 {
12754   rtx this, insn, funexp;
12755
12756   reload_completed = 1;
12757   epilogue_completed = 1;
12758   no_new_pseudos = 1;
12759
12760   /* Mark the end of the (empty) prologue.  */
12761   emit_note (NOTE_INSN_PROLOGUE_END);
12762
12763   /* Find the "this" pointer.  If the function returns a structure,
12764      the structure return pointer is in r3.  */
12765   if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
12766     this = gen_rtx_REG (Pmode, 4);
12767   else
12768     this = gen_rtx_REG (Pmode, 3);
12769
12770   /* Apply the constant offset, if required.  */
12771   if (delta)
12772     {
12773       rtx delta_rtx = GEN_INT (delta);
12774       emit_insn (TARGET_32BIT
12775                  ? gen_addsi3 (this, this, delta_rtx)
12776                  : gen_adddi3 (this, this, delta_rtx));
12777     }
12778
12779   /* Apply the offset from the vtable, if required.  */
12780   if (vcall_offset)
12781     {
12782       rtx vcall_offset_rtx = GEN_INT (vcall_offset);
12783       rtx tmp = gen_rtx_REG (Pmode, 12);
12784
12785       emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
12786       if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
12787         {
12788           emit_insn (TARGET_32BIT
12789                      ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
12790                      : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
12791           emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
12792         }
12793       else
12794         {
12795           rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
12796
12797           emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
12798         }
12799       emit_insn (TARGET_32BIT
12800                  ? gen_addsi3 (this, this, tmp)
12801                  : gen_adddi3 (this, this, tmp));
12802     }
12803
12804   /* Generate a tail call to the target function.  */
12805   if (!TREE_USED (function))
12806     {
12807       assemble_external (function);
12808       TREE_USED (function) = 1;
12809     }
12810   funexp = XEXP (DECL_RTL (function), 0);
12811   funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
12812
12813 #if TARGET_MACHO
12814   if (MACHOPIC_INDIRECT)
12815     funexp = machopic_indirect_call_target (funexp);
12816 #endif
12817
12818   /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
12819      generate sibcall RTL explicitly to avoid constraint abort.  */
12820   insn = emit_call_insn (
12821            gen_rtx_PARALLEL (VOIDmode,
12822              gen_rtvec (4,
12823                         gen_rtx_CALL (VOIDmode,
12824                                       funexp, const0_rtx),
12825                         gen_rtx_USE (VOIDmode, const0_rtx),
12826                         gen_rtx_USE (VOIDmode,
12827                                      gen_rtx_REG (SImode,
12828                                                   LINK_REGISTER_REGNUM)),
12829                         gen_rtx_RETURN (VOIDmode))));
12830   SIBLING_CALL_P (insn) = 1;
12831   emit_barrier ();
12832
12833   /* Run just enough of rest_of_compilation to get the insns emitted.
12834      There's not really enough bulk here to make other passes such as
12835      instruction scheduling worth while.  Note that use_thunk calls
12836      assemble_start_function and assemble_end_function.  */
12837   insn = get_insns ();
12838   insn_locators_initialize ();
12839   shorten_branches (insn);
12840   final_start_function (insn, file, 1);
12841   final (insn, file, 1, 0);
12842   final_end_function ();
12843
12844   reload_completed = 0;
12845   epilogue_completed = 0;
12846   no_new_pseudos = 0;
12847 }
12848 \f
12849 /* A quick summary of the various types of 'constant-pool tables'
12850    under PowerPC:
12851
12852    Target       Flags           Name            One table per
12853    AIX          (none)          AIX TOC         object file
12854    AIX          -mfull-toc      AIX TOC         object file
12855    AIX          -mminimal-toc   AIX minimal TOC translation unit
12856    SVR4/EABI    (none)          SVR4 SDATA      object file
12857    SVR4/EABI    -fpic           SVR4 pic        object file
12858    SVR4/EABI    -fPIC           SVR4 PIC        translation unit
12859    SVR4/EABI    -mrelocatable   EABI TOC        function
12860    SVR4/EABI    -maix           AIX TOC         object file
12861    SVR4/EABI    -maix -mminimal-toc
12862                                 AIX minimal TOC translation unit
12863
12864    Name                 Reg.    Set by  entries       contains:
12865                                         made by  addrs? fp?     sum?
12866
12867    AIX TOC              2       crt0    as       Y      option  option
12868    AIX minimal TOC      30      prolog  gcc      Y      Y       option
12869    SVR4 SDATA           13      crt0    gcc      N      Y       N
12870    SVR4 pic             30      prolog  ld       Y      not yet N
12871    SVR4 PIC             30      prolog  gcc      Y      option  option
12872    EABI TOC             30      prolog  gcc      Y      option  option
12873
12874 */
12875
12876 /* Hash functions for the hash table.  */
12877
12878 static unsigned
12879 rs6000_hash_constant (rtx k)
12880 {
12881   enum rtx_code code = GET_CODE (k);
12882   enum machine_mode mode = GET_MODE (k);
12883   unsigned result = (code << 3) ^ mode;
12884   const char *format;
12885   int flen, fidx;
12886
12887   format = GET_RTX_FORMAT (code);
12888   flen = strlen (format);
12889   fidx = 0;
12890
12891   switch (code)
12892     {
12893     case LABEL_REF:
12894       return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
12895
12896     case CONST_DOUBLE:
12897       if (mode != VOIDmode)
12898         return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
12899       flen = 2;
12900       break;
12901
12902     case CODE_LABEL:
12903       fidx = 3;
12904       break;
12905
12906     default:
12907       break;
12908     }
12909
12910   for (; fidx < flen; fidx++)
12911     switch (format[fidx])
12912       {
12913       case 's':
12914         {
12915           unsigned i, len;
12916           const char *str = XSTR (k, fidx);
12917           len = strlen (str);
12918           result = result * 613 + len;
12919           for (i = 0; i < len; i++)
12920             result = result * 613 + (unsigned) str[i];
12921           break;
12922         }
12923       case 'u':
12924       case 'e':
12925         result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
12926         break;
12927       case 'i':
12928       case 'n':
12929         result = result * 613 + (unsigned) XINT (k, fidx);
12930         break;
12931       case 'w':
12932         if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
12933           result = result * 613 + (unsigned) XWINT (k, fidx);
12934         else
12935           {
12936             size_t i;
12937             for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
12938               result = result * 613 + (unsigned) (XWINT (k, fidx)
12939                                                   >> CHAR_BIT * i);
12940           }
12941         break;
12942       case '0':
12943         break;
12944       default:
12945         abort ();
12946       }
12947
12948   return result;
12949 }
12950
12951 static unsigned
12952 toc_hash_function (const void *hash_entry)
12953 {
12954   const struct toc_hash_struct *thc =
12955     (const struct toc_hash_struct *) hash_entry;
12956   return rs6000_hash_constant (thc->key) ^ thc->key_mode;
12957 }
12958
12959 /* Compare H1 and H2 for equivalence.  */
12960
12961 static int
12962 toc_hash_eq (const void *h1, const void *h2)
12963 {
12964   rtx r1 = ((const struct toc_hash_struct *) h1)->key;
12965   rtx r2 = ((const struct toc_hash_struct *) h2)->key;
12966
12967   if (((const struct toc_hash_struct *) h1)->key_mode
12968       != ((const struct toc_hash_struct *) h2)->key_mode)
12969     return 0;
12970
12971   return rtx_equal_p (r1, r2);
12972 }
12973
12974 /* These are the names given by the C++ front-end to vtables, and
12975    vtable-like objects.  Ideally, this logic should not be here;
12976    instead, there should be some programmatic way of inquiring as
12977    to whether or not an object is a vtable.  */
12978
12979 #define VTABLE_NAME_P(NAME)                             \
12980   (strncmp ("_vt.", name, strlen("_vt.")) == 0          \
12981   || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0       \
12982   || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0       \
12983   || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
12984
12985 void
12986 rs6000_output_symbol_ref (FILE *file, rtx x)
12987 {
12988   /* Currently C++ toc references to vtables can be emitted before it
12989      is decided whether the vtable is public or private.  If this is
12990      the case, then the linker will eventually complain that there is
12991      a reference to an unknown section.  Thus, for vtables only,
12992      we emit the TOC reference to reference the symbol and not the
12993      section.  */
12994   const char *name = XSTR (x, 0);
12995
12996   if (VTABLE_NAME_P (name))
12997     {
12998       RS6000_OUTPUT_BASENAME (file, name);
12999     }
13000   else
13001     assemble_name (file, name);
13002 }
13003
13004 /* Output a TOC entry.  We derive the entry name from what is being
13005    written.  */
13006
13007 void
13008 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
13009 {
13010   char buf[256];
13011   const char *name = buf;
13012   const char *real_name;
13013   rtx base = x;
13014   int offset = 0;
13015
13016   if (TARGET_NO_TOC)
13017     abort ();
13018
13019   /* When the linker won't eliminate them, don't output duplicate
13020      TOC entries (this happens on AIX if there is any kind of TOC,
13021      and on SVR4 under -fPIC or -mrelocatable).  Don't do this for
13022      CODE_LABELs.  */
13023   if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
13024     {
13025       struct toc_hash_struct *h;
13026       void * * found;
13027
13028       /* Create toc_hash_table.  This can't be done at OVERRIDE_OPTIONS
13029          time because GGC is not initialized at that point.  */
13030       if (toc_hash_table == NULL)
13031         toc_hash_table = htab_create_ggc (1021, toc_hash_function,
13032                                           toc_hash_eq, NULL);
13033
13034       h = ggc_alloc (sizeof (*h));
13035       h->key = x;
13036       h->key_mode = mode;
13037       h->labelno = labelno;
13038
13039       found = htab_find_slot (toc_hash_table, h, 1);
13040       if (*found == NULL)
13041         *found = h;
13042       else  /* This is indeed a duplicate.
13043                Set this label equal to that label.  */
13044         {
13045           fputs ("\t.set ", file);
13046           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13047           fprintf (file, "%d,", labelno);
13048           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13049           fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
13050                                               found)->labelno));
13051           return;
13052         }
13053     }
13054
13055   /* If we're going to put a double constant in the TOC, make sure it's
13056      aligned properly when strict alignment is on.  */
13057   if (GET_CODE (x) == CONST_DOUBLE
13058       && STRICT_ALIGNMENT
13059       && GET_MODE_BITSIZE (mode) >= 64
13060       && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
13061     ASM_OUTPUT_ALIGN (file, 3);
13062   }
13063
13064   (*targetm.asm_out.internal_label) (file, "LC", labelno);
13065
13066   /* Handle FP constants specially.  Note that if we have a minimal
13067      TOC, things we put here aren't actually in the TOC, so we can allow
13068      FP constants.  */
13069   if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
13070     {
13071       REAL_VALUE_TYPE rv;
13072       long k[4];
13073
13074       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13075       REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
13076
13077       if (TARGET_64BIT)
13078         {
13079           if (TARGET_MINIMAL_TOC)
13080             fputs (DOUBLE_INT_ASM_OP, file);
13081           else
13082             fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13083                      k[0] & 0xffffffff, k[1] & 0xffffffff,
13084                      k[2] & 0xffffffff, k[3] & 0xffffffff);
13085           fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
13086                    k[0] & 0xffffffff, k[1] & 0xffffffff,
13087                    k[2] & 0xffffffff, k[3] & 0xffffffff);
13088           return;
13089         }
13090       else
13091         {
13092           if (TARGET_MINIMAL_TOC)
13093             fputs ("\t.long ", file);
13094           else
13095             fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13096                      k[0] & 0xffffffff, k[1] & 0xffffffff,
13097                      k[2] & 0xffffffff, k[3] & 0xffffffff);
13098           fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
13099                    k[0] & 0xffffffff, k[1] & 0xffffffff,
13100                    k[2] & 0xffffffff, k[3] & 0xffffffff);
13101           return;
13102         }
13103     }
13104   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
13105     {
13106       REAL_VALUE_TYPE rv;
13107       long k[2];
13108
13109       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13110       REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
13111
13112       if (TARGET_64BIT)
13113         {
13114           if (TARGET_MINIMAL_TOC)
13115             fputs (DOUBLE_INT_ASM_OP, file);
13116           else
13117             fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13118                      k[0] & 0xffffffff, k[1] & 0xffffffff);
13119           fprintf (file, "0x%lx%08lx\n",
13120                    k[0] & 0xffffffff, k[1] & 0xffffffff);
13121           return;
13122         }
13123       else
13124         {
13125           if (TARGET_MINIMAL_TOC)
13126             fputs ("\t.long ", file);
13127           else
13128             fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13129                      k[0] & 0xffffffff, k[1] & 0xffffffff);
13130           fprintf (file, "0x%lx,0x%lx\n",
13131                    k[0] & 0xffffffff, k[1] & 0xffffffff);
13132           return;
13133         }
13134     }
13135   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
13136     {
13137       REAL_VALUE_TYPE rv;
13138       long l;
13139
13140       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13141       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
13142
13143       if (TARGET_64BIT)
13144         {
13145           if (TARGET_MINIMAL_TOC)
13146             fputs (DOUBLE_INT_ASM_OP, file);
13147           else
13148             fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13149           fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
13150           return;
13151         }
13152       else
13153         {
13154           if (TARGET_MINIMAL_TOC)
13155             fputs ("\t.long ", file);
13156           else
13157             fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13158           fprintf (file, "0x%lx\n", l & 0xffffffff);
13159           return;
13160         }
13161     }
13162   else if (GET_MODE (x) == VOIDmode
13163            && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
13164     {
13165       unsigned HOST_WIDE_INT low;
13166       HOST_WIDE_INT high;
13167
13168       if (GET_CODE (x) == CONST_DOUBLE)
13169         {
13170           low = CONST_DOUBLE_LOW (x);
13171           high = CONST_DOUBLE_HIGH (x);
13172         }
13173       else
13174 #if HOST_BITS_PER_WIDE_INT == 32
13175         {
13176           low = INTVAL (x);
13177           high = (low & 0x80000000) ? ~0 : 0;
13178         }
13179 #else
13180         {
13181           low = INTVAL (x) & 0xffffffff;
13182           high = (HOST_WIDE_INT) INTVAL (x) >> 32;
13183         }
13184 #endif
13185
13186       /* TOC entries are always Pmode-sized, but since this
13187          is a bigendian machine then if we're putting smaller
13188          integer constants in the TOC we have to pad them.
13189          (This is still a win over putting the constants in
13190          a separate constant pool, because then we'd have
13191          to have both a TOC entry _and_ the actual constant.)
13192
13193          For a 32-bit target, CONST_INT values are loaded and shifted
13194          entirely within `low' and can be stored in one TOC entry.  */
13195
13196       if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
13197         abort ();/* It would be easy to make this work, but it doesn't now.  */
13198
13199       if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
13200         {
13201 #if HOST_BITS_PER_WIDE_INT == 32
13202           lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
13203                          POINTER_SIZE, &low, &high, 0);
13204 #else
13205           low |= high << 32;
13206           low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
13207           high = (HOST_WIDE_INT) low >> 32;
13208           low &= 0xffffffff;
13209 #endif
13210         }
13211
13212       if (TARGET_64BIT)
13213         {
13214           if (TARGET_MINIMAL_TOC)
13215             fputs (DOUBLE_INT_ASM_OP, file);
13216           else
13217             fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13218                      (long) high & 0xffffffff, (long) low & 0xffffffff);
13219           fprintf (file, "0x%lx%08lx\n",
13220                    (long) high & 0xffffffff, (long) low & 0xffffffff);
13221           return;
13222         }
13223       else
13224         {
13225           if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
13226             {
13227               if (TARGET_MINIMAL_TOC)
13228                 fputs ("\t.long ", file);
13229               else
13230                 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13231                          (long) high & 0xffffffff, (long) low & 0xffffffff);
13232               fprintf (file, "0x%lx,0x%lx\n",
13233                        (long) high & 0xffffffff, (long) low & 0xffffffff);
13234             }
13235           else
13236             {
13237               if (TARGET_MINIMAL_TOC)
13238                 fputs ("\t.long ", file);
13239               else
13240                 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
13241               fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
13242             }
13243           return;
13244         }
13245     }
13246
13247   if (GET_CODE (x) == CONST)
13248     {
13249       if (GET_CODE (XEXP (x, 0)) != PLUS)
13250         abort ();
13251
13252       base = XEXP (XEXP (x, 0), 0);
13253       offset = INTVAL (XEXP (XEXP (x, 0), 1));
13254     }
13255
13256   if (GET_CODE (base) == SYMBOL_REF)
13257     name = XSTR (base, 0);
13258   else if (GET_CODE (base) == LABEL_REF)
13259     ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
13260   else if (GET_CODE (base) == CODE_LABEL)
13261     ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
13262   else
13263     abort ();
13264
13265   real_name = (*targetm.strip_name_encoding) (name);
13266   if (TARGET_MINIMAL_TOC)
13267     fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
13268   else
13269     {
13270       fprintf (file, "\t.tc %s", real_name);
13271
13272       if (offset < 0)
13273         fprintf (file, ".N%d", - offset);
13274       else if (offset)
13275         fprintf (file, ".P%d", offset);
13276
13277       fputs ("[TC],", file);
13278     }
13279
13280   /* Currently C++ toc references to vtables can be emitted before it
13281      is decided whether the vtable is public or private.  If this is
13282      the case, then the linker will eventually complain that there is
13283      a TOC reference to an unknown section.  Thus, for vtables only,
13284      we emit the TOC reference to reference the symbol and not the
13285      section.  */
13286   if (VTABLE_NAME_P (name))
13287     {
13288       RS6000_OUTPUT_BASENAME (file, name);
13289       if (offset < 0)
13290         fprintf (file, "%d", offset);
13291       else if (offset > 0)
13292         fprintf (file, "+%d", offset);
13293     }
13294   else
13295     output_addr_const (file, x);
13296   putc ('\n', file);
13297 }
13298 \f
13299 /* Output an assembler pseudo-op to write an ASCII string of N characters
13300    starting at P to FILE.
13301
13302    On the RS/6000, we have to do this using the .byte operation and
13303    write out special characters outside the quoted string.
13304    Also, the assembler is broken; very long strings are truncated,
13305    so we must artificially break them up early.  */
13306
13307 void
13308 output_ascii (FILE *file, const char *p, int n)
13309 {
13310   char c;
13311   int i, count_string;
13312   const char *for_string = "\t.byte \"";
13313   const char *for_decimal = "\t.byte ";
13314   const char *to_close = NULL;
13315
13316   count_string = 0;
13317   for (i = 0; i < n; i++)
13318     {
13319       c = *p++;
13320       if (c >= ' ' && c < 0177)
13321         {
13322           if (for_string)
13323             fputs (for_string, file);
13324           putc (c, file);
13325
13326           /* Write two quotes to get one.  */
13327           if (c == '"')
13328             {
13329               putc (c, file);
13330               ++count_string;
13331             }
13332
13333           for_string = NULL;
13334           for_decimal = "\"\n\t.byte ";
13335           to_close = "\"\n";
13336           ++count_string;
13337
13338           if (count_string >= 512)
13339             {
13340               fputs (to_close, file);
13341
13342               for_string = "\t.byte \"";
13343               for_decimal = "\t.byte ";
13344               to_close = NULL;
13345               count_string = 0;
13346             }
13347         }
13348       else
13349         {
13350           if (for_decimal)
13351             fputs (for_decimal, file);
13352           fprintf (file, "%d", c);
13353
13354           for_string = "\n\t.byte \"";
13355           for_decimal = ", ";
13356           to_close = "\n";
13357           count_string = 0;
13358         }
13359     }
13360
13361   /* Now close the string if we have written one.  Then end the line.  */
13362   if (to_close)
13363     fputs (to_close, file);
13364 }
13365 \f
13366 /* Generate a unique section name for FILENAME for a section type
13367    represented by SECTION_DESC.  Output goes into BUF.
13368
13369    SECTION_DESC can be any string, as long as it is different for each
13370    possible section type.
13371
13372    We name the section in the same manner as xlc.  The name begins with an
13373    underscore followed by the filename (after stripping any leading directory
13374    names) with the last period replaced by the string SECTION_DESC.  If
13375    FILENAME does not contain a period, SECTION_DESC is appended to the end of
13376    the name.  */
13377
13378 void
13379 rs6000_gen_section_name (char **buf, const char *filename,
13380                          const char *section_desc)
13381 {
13382   const char *q, *after_last_slash, *last_period = 0;
13383   char *p;
13384   int len;
13385
13386   after_last_slash = filename;
13387   for (q = filename; *q; q++)
13388     {
13389       if (*q == '/')
13390         after_last_slash = q + 1;
13391       else if (*q == '.')
13392         last_period = q;
13393     }
13394
13395   len = strlen (after_last_slash) + strlen (section_desc) + 2;
13396   *buf = (char *) xmalloc (len);
13397
13398   p = *buf;
13399   *p++ = '_';
13400
13401   for (q = after_last_slash; *q; q++)
13402     {
13403       if (q == last_period)
13404         {
13405           strcpy (p, section_desc);
13406           p += strlen (section_desc);
13407           break;
13408         }
13409
13410       else if (ISALNUM (*q))
13411         *p++ = *q;
13412     }
13413
13414   if (last_period == 0)
13415     strcpy (p, section_desc);
13416   else
13417     *p = '\0';
13418 }
13419 \f
13420 /* Emit profile function.  */
13421
13422 void
13423 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
13424 {
13425   if (TARGET_PROFILE_KERNEL)
13426     return;
13427
13428   if (DEFAULT_ABI == ABI_AIX)
13429     {
13430 #ifndef NO_PROFILE_COUNTERS
13431 # define NO_PROFILE_COUNTERS 0
13432 #endif
13433       if (NO_PROFILE_COUNTERS)
13434         emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
13435       else
13436         {
13437           char buf[30];
13438           const char *label_name;
13439           rtx fun;
13440
13441           ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13442           label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
13443           fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
13444
13445           emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
13446                              fun, Pmode);
13447         }
13448     }
13449   else if (DEFAULT_ABI == ABI_DARWIN)
13450     {
13451       const char *mcount_name = RS6000_MCOUNT;
13452       int caller_addr_regno = LINK_REGISTER_REGNUM;
13453
13454       /* Be conservative and always set this, at least for now.  */
13455       current_function_uses_pic_offset_table = 1;
13456
13457 #if TARGET_MACHO
13458       /* For PIC code, set up a stub and collect the caller's address
13459          from r0, which is where the prologue puts it.  */
13460       if (MACHOPIC_INDIRECT)
13461         {
13462           mcount_name = machopic_stub_name (mcount_name);
13463           if (current_function_uses_pic_offset_table)
13464             caller_addr_regno = 0;
13465         }
13466 #endif
13467       emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
13468                          0, VOIDmode, 1,
13469                          gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
13470     }
13471 }
13472
13473 /* Write function profiler code.  */
13474
13475 void
13476 output_function_profiler (FILE *file, int labelno)
13477 {
13478   char buf[100];
13479   int save_lr = 8;
13480
13481   switch (DEFAULT_ABI)
13482     {
13483     default:
13484       abort ();
13485
13486     case ABI_V4:
13487       save_lr = 4;
13488       if (!TARGET_32BIT)
13489         {
13490           warning ("no profiling of 64-bit code for this ABI");
13491           return;
13492         }
13493       ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13494       fprintf (file, "\tmflr %s\n", reg_names[0]);
13495       if (flag_pic == 1)
13496         {
13497           fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
13498           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13499                        reg_names[0], save_lr, reg_names[1]);
13500           asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
13501           asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
13502           assemble_name (file, buf);
13503           asm_fprintf (file, "@got(%s)\n", reg_names[12]);
13504         }
13505       else if (flag_pic > 1)
13506         {
13507           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13508                        reg_names[0], save_lr, reg_names[1]);
13509           /* Now, we need to get the address of the label.  */
13510           fputs ("\tbl 1f\n\t.long ", file);
13511           assemble_name (file, buf);
13512           fputs ("-.\n1:", file);
13513           asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
13514           asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
13515                        reg_names[0], reg_names[11]);
13516           asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
13517                        reg_names[0], reg_names[0], reg_names[11]);
13518         }
13519       else
13520         {
13521           asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
13522           assemble_name (file, buf);
13523           fputs ("@ha\n", file);
13524           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13525                        reg_names[0], save_lr, reg_names[1]);
13526           asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
13527           assemble_name (file, buf);
13528           asm_fprintf (file, "@l(%s)\n", reg_names[12]);
13529         }
13530
13531       /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH.  */
13532       fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13533       break;
13534
13535     case ABI_AIX:
13536     case ABI_DARWIN:
13537       if (!TARGET_PROFILE_KERNEL)
13538         {
13539           /* Don't do anything, done in output_profile_hook ().  */
13540         }
13541       else
13542         {
13543           if (TARGET_32BIT)
13544             abort ();
13545
13546           asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
13547           asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
13548
13549           if (current_function_needs_context)
13550             {
13551               asm_fprintf (file, "\tstd %s,24(%s)\n",
13552                            reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13553               fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13554               asm_fprintf (file, "\tld %s,24(%s)\n",
13555                            reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13556             }
13557           else
13558             fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13559         }
13560       break;
13561     }
13562 }
13563
13564 \f
13565 static int
13566 rs6000_use_dfa_pipeline_interface (void)
13567 {
13568   return 1;
13569 }
13570
13571 /* Power4 load update and store update instructions are cracked into a
13572    load or store and an integer insn which are executed in the same cycle.
13573    Branches have their own dispatch slot which does not count against the
13574    GCC issue rate, but it changes the program flow so there are no other
13575    instructions to issue in this cycle.  */
13576
13577 static int
13578 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
13579                        int verbose ATTRIBUTE_UNUSED,
13580                        rtx insn, int more)
13581 {
13582   if (GET_CODE (PATTERN (insn)) == USE
13583       || GET_CODE (PATTERN (insn)) == CLOBBER)
13584     return more;
13585
13586   if (rs6000_cpu == PROCESSOR_POWER4)
13587     {
13588       if (is_microcoded_insn (insn))
13589         return 0;
13590       else if (is_cracked_insn (insn))
13591         return more > 2 ? more - 2 : 0;
13592     }
13593
13594   return more - 1;
13595 }
13596
13597 /* Adjust the cost of a scheduling dependency.  Return the new cost of
13598    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
13599
13600 static int
13601 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
13602                     int cost)
13603 {
13604   if (! recog_memoized (insn))
13605     return 0;
13606
13607   if (REG_NOTE_KIND (link) != 0)
13608     return 0;
13609
13610   if (REG_NOTE_KIND (link) == 0)
13611     {
13612       /* Data dependency; DEP_INSN writes a register that INSN reads
13613          some cycles later.  */
13614       switch (get_attr_type (insn))
13615         {
13616         case TYPE_JMPREG:
13617           /* Tell the first scheduling pass about the latency between
13618              a mtctr and bctr (and mtlr and br/blr).  The first
13619              scheduling pass will not know about this latency since
13620              the mtctr instruction, which has the latency associated
13621              to it, will be generated by reload.  */
13622           return TARGET_POWER ? 5 : 4;
13623         case TYPE_BRANCH:
13624           /* Leave some extra cycles between a compare and its
13625              dependent branch, to inhibit expensive mispredicts.  */
13626           if ((rs6000_cpu_attr == CPU_PPC603
13627                || rs6000_cpu_attr == CPU_PPC604
13628                || rs6000_cpu_attr == CPU_PPC604E
13629                || rs6000_cpu_attr == CPU_PPC620
13630                || rs6000_cpu_attr == CPU_PPC630
13631                || rs6000_cpu_attr == CPU_PPC750
13632                || rs6000_cpu_attr == CPU_PPC7400
13633                || rs6000_cpu_attr == CPU_PPC7450
13634                || rs6000_cpu_attr == CPU_POWER4)
13635               && recog_memoized (dep_insn)
13636               && (INSN_CODE (dep_insn) >= 0)
13637               && (get_attr_type (dep_insn) == TYPE_CMP
13638                   || get_attr_type (dep_insn) == TYPE_COMPARE
13639                   || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
13640                   || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
13641                   || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
13642                   || get_attr_type (dep_insn) == TYPE_FPCOMPARE
13643                   || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
13644                   || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
13645             return cost + 2;
13646         default:
13647           break;
13648         }
13649       /* Fall out to return default cost.  */
13650     }
13651
13652   return cost;
13653 }
13654
13655 /* The function returns a true if INSN is microcoded.
13656    Return false otherwise.  */
13657
13658 static bool
13659 is_microcoded_insn (rtx insn)
13660 {
13661   if (!insn || !INSN_P (insn)
13662       || GET_CODE (PATTERN (insn)) == USE
13663       || GET_CODE (PATTERN (insn)) == CLOBBER)
13664     return false;
13665
13666   if (rs6000_cpu == PROCESSOR_POWER4)
13667     {
13668       enum attr_type type = get_attr_type (insn);
13669       if (type == TYPE_LOAD_EXT_U
13670           || type == TYPE_LOAD_EXT_UX
13671           || type == TYPE_LOAD_UX
13672           || type == TYPE_STORE_UX
13673           || type == TYPE_MFCR)
13674         return true;
13675     }
13676
13677   return false;
13678 }
13679
13680 /* The function returns a nonzero value if INSN can be scheduled only
13681    as the first insn in a dispatch group ("dispatch-slot restricted").
13682    In this case, the returned value indicates how many dispatch slots
13683    the insn occupies (at the beginning of the group).
13684    Return 0 otherwise.  */
13685
13686 static int
13687 is_dispatch_slot_restricted (rtx insn)
13688 {
13689   enum attr_type type;
13690
13691   if (rs6000_cpu != PROCESSOR_POWER4)
13692     return 0;
13693
13694   if (!insn
13695       || insn == NULL_RTX
13696       || GET_CODE (insn) == NOTE
13697       || GET_CODE (PATTERN (insn)) == USE
13698       || GET_CODE (PATTERN (insn)) == CLOBBER)
13699     return 0;
13700
13701   type = get_attr_type (insn);
13702
13703   switch (type){
13704   case TYPE_MFCR:
13705   case TYPE_MFCRF:
13706   case TYPE_MTCR:
13707   case TYPE_DELAYED_CR:
13708   case TYPE_CR_LOGICAL:
13709   case TYPE_MTJMPR:
13710   case TYPE_MFJMPR:
13711     return 1;
13712   case TYPE_IDIV:
13713   case TYPE_LDIV:
13714     return 2;
13715   default:
13716     return 0;
13717   }
13718 }
13719
13720 /* The function returns true if INSN is cracked into 2 instructions
13721    by the processor (and therefore occupies 2 issue slots).  */
13722
13723 static bool
13724 is_cracked_insn (rtx insn)
13725 {
13726   if (!insn || !INSN_P (insn)
13727       || GET_CODE (PATTERN (insn)) == USE
13728       || GET_CODE (PATTERN (insn)) == CLOBBER)
13729     return false;
13730
13731   if (rs6000_cpu == PROCESSOR_POWER4)
13732     {
13733       enum attr_type type = get_attr_type (insn);
13734       if (type == TYPE_LOAD_U || type == TYPE_STORE_U
13735                || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
13736                || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
13737                || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
13738                || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
13739                || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
13740                || type == TYPE_IDIV || type == TYPE_LDIV
13741                || type == TYPE_INSERT_WORD)
13742         return true;
13743     }
13744
13745   return false;
13746 }
13747
13748 /* The function returns true if INSN can be issued only from
13749    the branch slot.  */
13750
13751 static bool
13752 is_branch_slot_insn (rtx insn)
13753 {
13754   if (!insn || !INSN_P (insn)
13755       || GET_CODE (PATTERN (insn)) == USE
13756       || GET_CODE (PATTERN (insn)) == CLOBBER)
13757     return false;
13758
13759   if (rs6000_cpu == PROCESSOR_POWER4)
13760     {
13761       enum attr_type type = get_attr_type (insn);
13762       if (type == TYPE_BRANCH || type == TYPE_JMPREG)
13763         return true;
13764       return false;
13765     }
13766
13767   return false;
13768 }
13769
13770 /* A C statement (sans semicolon) to update the integer scheduling
13771    priority INSN_PRIORITY (INSN). Increase the priority to execute the
13772    INSN earlier, reduce the priority to execute INSN later.  Do not
13773    define this macro if you do not need to adjust the scheduling
13774    priorities of insns.  */
13775
13776 static int
13777 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
13778 {
13779   /* On machines (like the 750) which have asymmetric integer units,
13780      where one integer unit can do multiply and divides and the other
13781      can't, reduce the priority of multiply/divide so it is scheduled
13782      before other integer operations.  */
13783
13784 #if 0
13785   if (! INSN_P (insn))
13786     return priority;
13787
13788   if (GET_CODE (PATTERN (insn)) == USE)
13789     return priority;
13790
13791   switch (rs6000_cpu_attr) {
13792   case CPU_PPC750:
13793     switch (get_attr_type (insn))
13794       {
13795       default:
13796         break;
13797
13798       case TYPE_IMUL:
13799       case TYPE_IDIV:
13800         fprintf (stderr, "priority was %#x (%d) before adjustment\n",
13801                  priority, priority);
13802         if (priority >= 0 && priority < 0x01000000)
13803           priority >>= 3;
13804         break;
13805       }
13806   }
13807 #endif
13808
13809   if (is_dispatch_slot_restricted (insn)
13810       && reload_completed
13811       && current_sched_info->sched_max_insns_priority
13812       && rs6000_sched_restricted_insns_priority)
13813     {
13814
13815       /* Prioritize insns that can be dispatched only in the first dispatch slot.  */
13816       if (rs6000_sched_restricted_insns_priority == 1)
13817         /* Attach highest priority to insn. This means that in
13818            haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
13819            precede 'priority' (critical path) considerations.  */
13820         return current_sched_info->sched_max_insns_priority;
13821       else if (rs6000_sched_restricted_insns_priority == 2)
13822         /* Increase priority of insn by a minimal amount. This means that in
13823            haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
13824            precede dispatch-slot restriction considerations.  */
13825         return (priority + 1);
13826     }
13827
13828   return priority;
13829 }
13830
13831 /* Return how many instructions the machine can issue per cycle.  */
13832
13833 static int
13834 rs6000_issue_rate (void)
13835 {
13836   /* Use issue rate of 1 for first scheduling pass to decrease degradation.  */
13837   if (!reload_completed)
13838     return 1;
13839
13840   switch (rs6000_cpu_attr) {
13841   case CPU_RIOS1:  /* ? */
13842   case CPU_RS64A:
13843   case CPU_PPC601: /* ? */
13844   case CPU_PPC7450:
13845     return 3;
13846   case CPU_PPC440:
13847   case CPU_PPC603:
13848   case CPU_PPC750:
13849   case CPU_PPC7400:
13850   case CPU_PPC8540:
13851     return 2;
13852   case CPU_RIOS2:
13853   case CPU_PPC604:
13854   case CPU_PPC604E:
13855   case CPU_PPC620:
13856   case CPU_PPC630:
13857     return 4;
13858   case CPU_POWER4:
13859     return 5;
13860   default:
13861     return 1;
13862   }
13863 }
13864
13865 /* Return how many instructions to look ahead for better insn
13866    scheduling.  */
13867
13868 static int
13869 rs6000_use_sched_lookahead (void)
13870 {
13871   if (rs6000_cpu_attr == CPU_PPC8540)
13872     return 4;
13873   return 0;
13874 }
13875
13876 /* Determine is PAT refers to memory.  */
13877
13878 static bool
13879 is_mem_ref (rtx pat)
13880 {
13881   const char * fmt;
13882   int i, j;
13883   bool ret = false;
13884
13885   if (GET_CODE (pat) == MEM)
13886     return true;
13887
13888   /* Recursively process the pattern.  */
13889   fmt = GET_RTX_FORMAT (GET_CODE (pat));
13890
13891   for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
13892     {
13893       if (fmt[i] == 'e')
13894         ret |= is_mem_ref (XEXP (pat, i));
13895       else if (fmt[i] == 'E')
13896         for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
13897           ret |= is_mem_ref (XVECEXP (pat, i, j));
13898     }
13899
13900   return ret;
13901 }
13902
13903 /* Determine if PAT is a PATTERN of a load insn.  */
13904
13905 static bool
13906 is_load_insn1 (rtx pat)
13907 {
13908   if (!pat || pat == NULL_RTX)
13909     return false;
13910
13911   if (GET_CODE (pat) == SET)
13912     return is_mem_ref (SET_SRC (pat));
13913
13914   if (GET_CODE (pat) == PARALLEL)
13915     {
13916       int i;
13917
13918       for (i = 0; i < XVECLEN (pat, 0); i++)
13919         if (is_load_insn1 (XVECEXP (pat, 0, i)))
13920           return true;
13921     }
13922
13923   return false;
13924 }
13925
13926 /* Determine if INSN loads from memory.  */
13927
13928 static bool
13929 is_load_insn (rtx insn)
13930 {
13931   if (!insn || !INSN_P (insn))
13932     return false;
13933
13934   if (GET_CODE (insn) == CALL_INSN)
13935     return false;
13936
13937   return is_load_insn1 (PATTERN (insn));
13938 }
13939
13940 /* Determine if PAT is a PATTERN of a store insn.  */
13941
13942 static bool
13943 is_store_insn1 (rtx pat)
13944 {
13945   if (!pat || pat == NULL_RTX)
13946     return false;
13947
13948   if (GET_CODE (pat) == SET)
13949     return is_mem_ref (SET_DEST (pat));
13950
13951   if (GET_CODE (pat) == PARALLEL)
13952     {
13953       int i;
13954
13955       for (i = 0; i < XVECLEN (pat, 0); i++)
13956         if (is_store_insn1 (XVECEXP (pat, 0, i)))
13957           return true;
13958     }
13959
13960   return false;
13961 }
13962
13963 /* Determine if INSN stores to memory.  */
13964
13965 static bool
13966 is_store_insn (rtx insn)
13967 {
13968   if (!insn || !INSN_P (insn))
13969     return false;
13970
13971   return is_store_insn1 (PATTERN (insn));
13972 }
13973
13974 /* Returns whether the dependence between INSN and NEXT is considered
13975    costly by the given target.  */
13976
13977 static bool
13978 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
13979 {
13980   /* If the flag is not enbled - no dependence is considered costly;
13981      allow all dependent insns in the same group.
13982      This is the most aggressive option.  */
13983   if (rs6000_sched_costly_dep == no_dep_costly)
13984     return false;
13985
13986   /* If the flag is set to 1 - a dependence is always considered costly;
13987      do not allow dependent instructions in the same group.
13988      This is the most conservative option.  */
13989   if (rs6000_sched_costly_dep == all_deps_costly)
13990     return true;
13991
13992   if (rs6000_sched_costly_dep == store_to_load_dep_costly
13993       && is_load_insn (next)
13994       && is_store_insn (insn))
13995     /* Prevent load after store in the same group.  */
13996     return true;
13997
13998   if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
13999       && is_load_insn (next)
14000       && is_store_insn (insn)
14001       && (!link || (int) REG_NOTE_KIND (link) == 0))
14002      /* Prevent load after store in the same group if it is a true dependence.  */
14003      return true;
14004
14005   /* The flag is set to X; dependences with latency >= X are considered costly,
14006      and will not be scheduled in the same group.  */
14007   if (rs6000_sched_costly_dep <= max_dep_latency
14008       && ((cost - distance) >= (int)rs6000_sched_costly_dep))
14009     return true;
14010
14011   return false;
14012 }
14013
14014 /* Return the next insn after INSN that is found before TAIL is reached,
14015    skipping any "non-active" insns - insns that will not actually occupy
14016    an issue slot.  Return NULL_RTX if such an insn is not found.  */
14017
14018 static rtx
14019 get_next_active_insn (rtx insn, rtx tail)
14020 {
14021   rtx next_insn;
14022
14023   if (!insn || insn == tail)
14024     return NULL_RTX;
14025
14026   next_insn = NEXT_INSN (insn);
14027
14028   while (next_insn
14029          && next_insn != tail
14030          && (GET_CODE(next_insn) == NOTE
14031              || GET_CODE (PATTERN (next_insn)) == USE
14032              || GET_CODE (PATTERN (next_insn)) == CLOBBER))
14033     {
14034       next_insn = NEXT_INSN (next_insn);
14035     }
14036
14037   if (!next_insn || next_insn == tail)
14038     return NULL_RTX;
14039
14040   return next_insn;
14041 }
14042
14043 /* Return whether the presence of INSN causes a dispatch group termination
14044    of group WHICH_GROUP.
14045
14046    If WHICH_GROUP == current_group, this function will return true if INSN
14047    causes the termination of the current group (i.e, the dispatch group to
14048    which INSN belongs). This means that INSN will be the last insn in the
14049    group it belongs to.
14050
14051    If WHICH_GROUP == previous_group, this function will return true if INSN
14052    causes the termination of the previous group (i.e, the dispatch group that
14053    precedes the group to which INSN belongs).  This means that INSN will be
14054    the first insn in the group it belongs to).  */
14055
14056 static bool
14057 insn_terminates_group_p (rtx insn, enum group_termination which_group)
14058 {
14059   enum attr_type type;
14060
14061   if (! insn)
14062     return false;
14063
14064   type = get_attr_type (insn);
14065
14066   if (is_microcoded_insn (insn))
14067     return true;
14068
14069   if (which_group == current_group)
14070     {
14071       if (is_branch_slot_insn (insn))
14072         return true;
14073       return false;
14074     }
14075   else if (which_group == previous_group)
14076     {
14077       if (is_dispatch_slot_restricted (insn))
14078         return true;
14079       return false;
14080     }
14081
14082   return false;
14083 }
14084
14085 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
14086    dispatch group) from the insns in GROUP_INSNS.  Return false otherwise.  */
14087
14088 static bool
14089 is_costly_group (rtx *group_insns, rtx next_insn)
14090 {
14091   int i;
14092   rtx link;
14093   int cost;
14094   int issue_rate = rs6000_issue_rate ();
14095
14096   for (i = 0; i < issue_rate; i++)
14097     {
14098       rtx insn = group_insns[i];
14099       if (!insn)
14100         continue;
14101       for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
14102         {
14103           rtx next = XEXP (link, 0);
14104           if (next == next_insn)
14105             {
14106               cost = insn_cost (insn, link, next_insn);
14107               if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
14108                 return true;
14109             }
14110         }
14111     }
14112
14113   return false;
14114 }
14115
14116 /* Utility of the function redefine_groups.
14117    Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
14118    in the same dispatch group.  If so, insert nops before NEXT_INSN, in order
14119    to keep it "far" (in a separate group) from GROUP_INSNS, following
14120    one of the following schemes, depending on the value of the flag
14121    -minsert_sched_nops = X:
14122    (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
14123        in order to force NEXT_INSN into a separate group.
14124    (2) X < sched_finish_regroup_exact: insert exactly X nops.
14125    GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
14126    insertion (has a group just ended, how many vacant issue slots remain in the
14127    last group, and how many dispatch groups were encountered so far).  */
14128
14129 static int
14130 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
14131                  bool *group_end, int can_issue_more, int *group_count)
14132 {
14133   rtx nop;
14134   bool force;
14135   int issue_rate = rs6000_issue_rate ();
14136   bool end = *group_end;
14137   int i;
14138
14139   if (next_insn == NULL_RTX)
14140     return can_issue_more;
14141
14142   if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
14143     return can_issue_more;
14144
14145   force = is_costly_group (group_insns, next_insn);
14146   if (!force)
14147     return can_issue_more;
14148
14149   if (sched_verbose > 6)
14150     fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
14151                         *group_count ,can_issue_more);
14152
14153   if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
14154     {
14155       if (*group_end)
14156         can_issue_more = 0;
14157
14158       /* Since only a branch can be issued in the last issue_slot, it is
14159          sufficient to insert 'can_issue_more - 1' nops if next_insn is not
14160          a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
14161          in this case the last nop will start a new group and the branch will be
14162          forced to the new group.  */
14163       if (can_issue_more && !is_branch_slot_insn (next_insn))
14164         can_issue_more--;
14165
14166       while (can_issue_more > 0)
14167         {
14168           nop = gen_nop();
14169           emit_insn_before (nop, next_insn);
14170           can_issue_more--;
14171         }
14172
14173       *group_end = true;
14174       return 0;
14175     }
14176
14177   if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
14178     {
14179       int n_nops = rs6000_sched_insert_nops;
14180
14181       /* Nops can't be issued from the branch slot, so the effective
14182          issue_rate for nops is 'issue_rate - 1'.  */
14183       if (can_issue_more == 0)
14184         can_issue_more = issue_rate;
14185       can_issue_more--;
14186       if (can_issue_more == 0)
14187         {
14188           can_issue_more = issue_rate - 1;
14189           (*group_count)++;
14190           end = true;
14191           for (i = 0; i < issue_rate; i++)
14192             {
14193               group_insns[i] = 0;
14194             }
14195         }
14196
14197       while (n_nops > 0)
14198         {
14199           nop = gen_nop ();
14200           emit_insn_before (nop, next_insn);
14201           if (can_issue_more == issue_rate - 1) /* new group begins */
14202             end = false;
14203           can_issue_more--;
14204           if (can_issue_more == 0)
14205             {
14206               can_issue_more = issue_rate - 1;
14207               (*group_count)++;
14208               end = true;
14209               for (i = 0; i < issue_rate; i++)
14210                 {
14211                   group_insns[i] = 0;
14212                 }
14213             }
14214           n_nops--;
14215         }
14216
14217       /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1').  */
14218       can_issue_more++;
14219
14220       *group_end = /* Is next_insn going to start a new group?  */
14221           (end
14222            || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14223            || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14224            || (can_issue_more < issue_rate &&
14225               insn_terminates_group_p (next_insn, previous_group)));
14226       if (*group_end && end)
14227         (*group_count)--;
14228
14229       if (sched_verbose > 6)
14230         fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
14231                         *group_count, can_issue_more);
14232       return can_issue_more;
14233     }
14234
14235   return can_issue_more;
14236 }
14237
14238 /* This function tries to synch the dispatch groups that the compiler "sees"
14239    with the dispatch groups that the processor dispatcher is expected to
14240    form in practice.  It tries to achieve this synchronization by forcing the
14241    estimated processor grouping on the compiler (as opposed to the function
14242    'pad_goups' which tries to force the scheduler's grouping on the processor).
14243
14244    The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
14245    examines the (estimated) dispatch groups that will be formed by the processor
14246    dispatcher.  It marks these group boundaries to reflect the estimated
14247    processor grouping, overriding the grouping that the scheduler had marked.
14248    Depending on the value of the flag '-minsert-sched-nops' this function can
14249    force certain insns into separate groups or force a certain distance between
14250    them by inserting nops, for example, if there exists a "costly dependence"
14251    between the insns.
14252
14253    The function estimates the group boundaries that the processor will form as
14254    folllows:  It keeps track of how many vacant issue slots are available after
14255    each insn.  A subsequent insn will start a new group if one of the following
14256    4 cases applies:
14257    - no more vacant issue slots remain in the current dispatch group.
14258    - only the last issue slot, which is the branch slot, is vacant, but the next
14259      insn is not a branch.
14260    - only the last 2 or less issue slots, including the branch slot, are vacant,
14261      which means that a cracked insn (which occupies two issue slots) can't be
14262      issued in this group.
14263    - less than 'issue_rate' slots are vacant, and the next insn always needs to
14264      start a new group.  */
14265
14266 static int
14267 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14268 {
14269   rtx insn, next_insn;
14270   int issue_rate;
14271   int can_issue_more;
14272   int slot, i;
14273   bool group_end;
14274   int group_count = 0;
14275   rtx *group_insns;
14276
14277   /* Initialize.  */
14278   issue_rate = rs6000_issue_rate ();
14279   group_insns = alloca (issue_rate * sizeof (rtx));
14280   for (i = 0; i < issue_rate; i++)
14281     {
14282       group_insns[i] = 0;
14283     }
14284   can_issue_more = issue_rate;
14285   slot = 0;
14286   insn = get_next_active_insn (prev_head_insn, tail);
14287   group_end = false;
14288
14289   while (insn != NULL_RTX)
14290     {
14291       slot = (issue_rate - can_issue_more);
14292       group_insns[slot] = insn;
14293       can_issue_more =
14294         rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14295       if (insn_terminates_group_p (insn, current_group))
14296         can_issue_more = 0;
14297
14298       next_insn = get_next_active_insn (insn, tail);
14299       if (next_insn == NULL_RTX)
14300         return group_count + 1;
14301
14302       group_end = /* Is next_insn going to start a new group?  */
14303         (can_issue_more == 0
14304          || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14305          || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14306          || (can_issue_more < issue_rate &&
14307              insn_terminates_group_p (next_insn, previous_group)));
14308
14309       can_issue_more = force_new_group (sched_verbose, dump, group_insns,
14310                         next_insn, &group_end, can_issue_more, &group_count);
14311
14312       if (group_end)
14313         {
14314           group_count++;
14315           can_issue_more = 0;
14316           for (i = 0; i < issue_rate; i++)
14317             {
14318               group_insns[i] = 0;
14319             }
14320         }
14321
14322       if (GET_MODE (next_insn) == TImode && can_issue_more)
14323         PUT_MODE(next_insn, VOIDmode);
14324       else if (!can_issue_more && GET_MODE (next_insn) != TImode)
14325         PUT_MODE (next_insn, TImode);
14326
14327       insn = next_insn;
14328       if (can_issue_more == 0)
14329         can_issue_more = issue_rate;
14330    } /* while */
14331
14332   return group_count;
14333 }
14334
14335 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
14336    dispatch group boundaries that the scheduler had marked.  Pad with nops
14337    any dispatch groups which have vacant issue slots, in order to force the
14338    scheduler's grouping on the processor dispatcher.  The function
14339    returns the number of dispatch groups found.  */
14340
14341 static int
14342 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14343 {
14344   rtx insn, next_insn;
14345   rtx nop;
14346   int issue_rate;
14347   int can_issue_more;
14348   int group_end;
14349   int group_count = 0;
14350
14351   /* Initialize issue_rate.  */
14352   issue_rate = rs6000_issue_rate ();
14353   can_issue_more = issue_rate;
14354
14355   insn = get_next_active_insn (prev_head_insn, tail);
14356   next_insn = get_next_active_insn (insn, tail);
14357
14358   while (insn != NULL_RTX)
14359     {
14360       can_issue_more =
14361         rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14362
14363       group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
14364
14365       if (next_insn == NULL_RTX)
14366         break;
14367
14368       if (group_end)
14369         {
14370           /* If the scheduler had marked group termination at this location
14371              (between insn and next_indn), and neither insn nor next_insn will
14372              force group termination, pad the group with nops to force group
14373              termination.  */
14374           if (can_issue_more
14375               && (rs6000_sched_insert_nops == sched_finish_pad_groups)
14376               && !insn_terminates_group_p (insn, current_group)
14377               && !insn_terminates_group_p (next_insn, previous_group))
14378             {
14379               if (!is_branch_slot_insn(next_insn))
14380                 can_issue_more--;
14381
14382               while (can_issue_more)
14383                 {
14384                   nop = gen_nop ();
14385                   emit_insn_before (nop, next_insn);
14386                   can_issue_more--;
14387                 }
14388             }
14389
14390           can_issue_more = issue_rate;
14391           group_count++;
14392         }
14393
14394       insn = next_insn;
14395       next_insn = get_next_active_insn (insn, tail);
14396     }
14397
14398   return group_count;
14399 }
14400
14401 /* The following function is called at the end of scheduling BB.
14402    After reload, it inserts nops at insn group bundling.  */
14403
14404 static void
14405 rs6000_sched_finish (FILE *dump, int sched_verbose)
14406 {
14407   int n_groups;
14408
14409   if (sched_verbose)
14410     fprintf (dump, "=== Finishing schedule.\n");
14411
14412   if (reload_completed && rs6000_cpu == PROCESSOR_POWER4)
14413     {
14414       if (rs6000_sched_insert_nops == sched_finish_none)
14415         return;
14416
14417       if (rs6000_sched_insert_nops == sched_finish_pad_groups)
14418         n_groups = pad_groups (dump, sched_verbose,
14419                                 current_sched_info->prev_head,
14420                                 current_sched_info->next_tail);
14421       else
14422         n_groups = redefine_groups (dump, sched_verbose,
14423                                 current_sched_info->prev_head,
14424                                 current_sched_info->next_tail);
14425
14426       if (sched_verbose >= 6)
14427         {
14428           fprintf (dump, "ngroups = %d\n", n_groups);
14429           print_rtl (dump, current_sched_info->prev_head);
14430           fprintf (dump, "Done finish_sched\n");
14431         }
14432     }
14433 }
14434 \f
14435 /* Length in units of the trampoline for entering a nested function.  */
14436
14437 int
14438 rs6000_trampoline_size (void)
14439 {
14440   int ret = 0;
14441
14442   switch (DEFAULT_ABI)
14443     {
14444     default:
14445       abort ();
14446
14447     case ABI_AIX:
14448       ret = (TARGET_32BIT) ? 12 : 24;
14449       break;
14450
14451     case ABI_DARWIN:
14452     case ABI_V4:
14453       ret = (TARGET_32BIT) ? 40 : 48;
14454       break;
14455     }
14456
14457   return ret;
14458 }
14459
14460 /* Emit RTL insns to initialize the variable parts of a trampoline.
14461    FNADDR is an RTX for the address of the function's pure code.
14462    CXT is an RTX for the static chain value for the function.  */
14463
14464 void
14465 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
14466 {
14467   enum machine_mode pmode = Pmode;
14468   int regsize = (TARGET_32BIT) ? 4 : 8;
14469   rtx ctx_reg = force_reg (pmode, cxt);
14470
14471   switch (DEFAULT_ABI)
14472     {
14473     default:
14474       abort ();
14475
14476 /* Macros to shorten the code expansions below.  */
14477 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
14478 #define MEM_PLUS(addr,offset) \
14479   gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
14480
14481     /* Under AIX, just build the 3 word function descriptor */
14482     case ABI_AIX:
14483       {
14484         rtx fn_reg = gen_reg_rtx (pmode);
14485         rtx toc_reg = gen_reg_rtx (pmode);
14486         emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
14487         emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
14488         emit_move_insn (MEM_DEREF (addr), fn_reg);
14489         emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
14490         emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
14491       }
14492       break;
14493
14494     /* Under V.4/eabi/darwin, __trampoline_setup does the real work.  */
14495     case ABI_DARWIN:
14496     case ABI_V4:
14497       emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
14498                          FALSE, VOIDmode, 4,
14499                          addr, pmode,
14500                          GEN_INT (rs6000_trampoline_size ()), SImode,
14501                          fnaddr, pmode,
14502                          ctx_reg, pmode);
14503       break;
14504     }
14505
14506   return;
14507 }
14508
14509 \f
14510 /* Table of valid machine attributes.  */
14511
14512 const struct attribute_spec rs6000_attribute_table[] =
14513 {
14514   /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14515   { "longcall",  0, 0, false, true,  true,  rs6000_handle_longcall_attribute },
14516   { "shortcall", 0, 0, false, true,  true,  rs6000_handle_longcall_attribute },
14517   { NULL,        0, 0, false, false, false, NULL }
14518 };
14519
14520 /* Handle a "longcall" or "shortcall" attribute; arguments as in
14521    struct attribute_spec.handler.  */
14522
14523 static tree
14524 rs6000_handle_longcall_attribute (tree *node, tree name,
14525                                   tree args ATTRIBUTE_UNUSED,
14526                                   int flags ATTRIBUTE_UNUSED,
14527                                   bool *no_add_attrs)
14528 {
14529   if (TREE_CODE (*node) != FUNCTION_TYPE
14530       && TREE_CODE (*node) != FIELD_DECL
14531       && TREE_CODE (*node) != TYPE_DECL)
14532     {
14533       warning ("`%s' attribute only applies to functions",
14534                IDENTIFIER_POINTER (name));
14535       *no_add_attrs = true;
14536     }
14537
14538   return NULL_TREE;
14539 }
14540
14541 /* Set longcall attributes on all functions declared when
14542    rs6000_default_long_calls is true.  */
14543 static void
14544 rs6000_set_default_type_attributes (tree type)
14545 {
14546   if (rs6000_default_long_calls
14547       && (TREE_CODE (type) == FUNCTION_TYPE
14548           || TREE_CODE (type) == METHOD_TYPE))
14549     TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
14550                                         NULL_TREE,
14551                                         TYPE_ATTRIBUTES (type));
14552 }
14553
14554 /* Return a reference suitable for calling a function with the
14555    longcall attribute.  */
14556
14557 struct rtx_def *
14558 rs6000_longcall_ref (rtx call_ref)
14559 {
14560   const char *call_name;
14561   tree node;
14562
14563   if (GET_CODE (call_ref) != SYMBOL_REF)
14564     return call_ref;
14565
14566   /* System V adds '.' to the internal name, so skip them.  */
14567   call_name = XSTR (call_ref, 0);
14568   if (*call_name == '.')
14569     {
14570       while (*call_name == '.')
14571         call_name++;
14572
14573       node = get_identifier (call_name);
14574       call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
14575     }
14576
14577   return force_reg (Pmode, call_ref);
14578 }
14579 \f
14580 #ifdef USING_ELFOS_H
14581
14582 /* A C statement or statements to switch to the appropriate section
14583    for output of RTX in mode MODE.  You can assume that RTX is some
14584    kind of constant in RTL.  The argument MODE is redundant except in
14585    the case of a `const_int' rtx.  Select the section by calling
14586    `text_section' or one of the alternatives for other sections.
14587
14588    Do not define this macro if you put all constants in the read-only
14589    data section.  */
14590
14591 static void
14592 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
14593                                unsigned HOST_WIDE_INT align)
14594 {
14595   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
14596     toc_section ();
14597   else
14598     default_elf_select_rtx_section (mode, x, align);
14599 }
14600
14601 /* A C statement or statements to switch to the appropriate
14602    section for output of DECL.  DECL is either a `VAR_DECL' node
14603    or a constant of some sort.  RELOC indicates whether forming
14604    the initial value of DECL requires link-time relocations.  */
14605
14606 static void
14607 rs6000_elf_select_section (tree decl, int reloc,
14608                            unsigned HOST_WIDE_INT align)
14609 {
14610   /* Pretend that we're always building for a shared library when
14611      ABI_AIX, because otherwise we end up with dynamic relocations
14612      in read-only sections.  This happens for function pointers,
14613      references to vtables in typeinfo, and probably other cases.  */
14614   default_elf_select_section_1 (decl, reloc, align,
14615                                 flag_pic || DEFAULT_ABI == ABI_AIX);
14616 }
14617
14618 /* A C statement to build up a unique section name, expressed as a
14619    STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
14620    RELOC indicates whether the initial value of EXP requires
14621    link-time relocations.  If you do not define this macro, GCC will use
14622    the symbol name prefixed by `.' as the section name.  Note - this
14623    macro can now be called for uninitialized data items as well as
14624    initialized data and functions.  */
14625
14626 static void
14627 rs6000_elf_unique_section (tree decl, int reloc)
14628 {
14629   /* As above, pretend that we're always building for a shared library
14630      when ABI_AIX, to avoid dynamic relocations in read-only sections.  */
14631   default_unique_section_1 (decl, reloc,
14632                             flag_pic || DEFAULT_ABI == ABI_AIX);
14633 }
14634 \f
14635 /* For a SYMBOL_REF, set generic flags and then perform some
14636    target-specific processing.
14637
14638    When the AIX ABI is requested on a non-AIX system, replace the
14639    function name with the real name (with a leading .) rather than the
14640    function descriptor name.  This saves a lot of overriding code to
14641    read the prefixes.  */
14642
14643 static void
14644 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
14645 {
14646   default_encode_section_info (decl, rtl, first);
14647
14648   if (first
14649       && TREE_CODE (decl) == FUNCTION_DECL
14650       && !TARGET_AIX
14651       && DEFAULT_ABI == ABI_AIX)
14652     {
14653       rtx sym_ref = XEXP (rtl, 0);
14654       size_t len = strlen (XSTR (sym_ref, 0));
14655       char *str = alloca (len + 2);
14656       str[0] = '.';
14657       memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
14658       XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
14659     }
14660 }
14661
14662 static bool
14663 rs6000_elf_in_small_data_p (tree decl)
14664 {
14665   if (rs6000_sdata == SDATA_NONE)
14666     return false;
14667
14668   if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
14669     {
14670       const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
14671       if (strcmp (section, ".sdata") == 0
14672           || strcmp (section, ".sdata2") == 0
14673           || strcmp (section, ".sbss") == 0
14674           || strcmp (section, ".sbss2") == 0
14675           || strcmp (section, ".PPC.EMB.sdata0") == 0
14676           || strcmp (section, ".PPC.EMB.sbss0") == 0)
14677         return true;
14678     }
14679   else
14680     {
14681       HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
14682
14683       if (size > 0
14684           && (unsigned HOST_WIDE_INT) size <= g_switch_value
14685           /* If it's not public, and we're not going to reference it there,
14686              there's no need to put it in the small data section.  */
14687           && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
14688         return true;
14689     }
14690
14691   return false;
14692 }
14693
14694 #endif /* USING_ELFOS_H */
14695
14696 \f
14697 /* Return a REG that occurs in ADDR with coefficient 1.
14698    ADDR can be effectively incremented by incrementing REG.
14699
14700    r0 is special and we must not select it as an address
14701    register by this routine since our caller will try to
14702    increment the returned register via an "la" instruction.  */
14703
14704 struct rtx_def *
14705 find_addr_reg (rtx addr)
14706 {
14707   while (GET_CODE (addr) == PLUS)
14708     {
14709       if (GET_CODE (XEXP (addr, 0)) == REG
14710           && REGNO (XEXP (addr, 0)) != 0)
14711         addr = XEXP (addr, 0);
14712       else if (GET_CODE (XEXP (addr, 1)) == REG
14713                && REGNO (XEXP (addr, 1)) != 0)
14714         addr = XEXP (addr, 1);
14715       else if (CONSTANT_P (XEXP (addr, 0)))
14716         addr = XEXP (addr, 1);
14717       else if (CONSTANT_P (XEXP (addr, 1)))
14718         addr = XEXP (addr, 0);
14719       else
14720         abort ();
14721     }
14722   if (GET_CODE (addr) == REG && REGNO (addr) != 0)
14723     return addr;
14724   abort ();
14725 }
14726
14727 void
14728 rs6000_fatal_bad_address (rtx op)
14729 {
14730   fatal_insn ("bad address", op);
14731 }
14732
14733 #if TARGET_MACHO
14734
14735 #if 0
14736 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
14737    reference and a constant.  */
14738
14739 int
14740 symbolic_operand (rtx op)
14741 {
14742   switch (GET_CODE (op))
14743     {
14744     case SYMBOL_REF:
14745     case LABEL_REF:
14746       return 1;
14747     case CONST:
14748       op = XEXP (op, 0);
14749       return (GET_CODE (op) == SYMBOL_REF ||
14750               (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
14751                || GET_CODE (XEXP (op, 0)) == LABEL_REF)
14752               && GET_CODE (XEXP (op, 1)) == CONST_INT);
14753     default:
14754       return 0;
14755     }
14756 }
14757 #endif
14758
14759 #if TARGET_MACHO
14760
14761 static tree branch_island_list = 0;
14762
14763 /* Remember to generate a branch island for far calls to the given
14764    function.  */
14765
14766 static void
14767 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
14768 {
14769   tree branch_island = build_tree_list (function_name, label_name);
14770   TREE_TYPE (branch_island) = build_int_2 (line_number, 0);
14771   TREE_CHAIN (branch_island) = branch_island_list;
14772   branch_island_list = branch_island;
14773 }
14774
14775 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND)     TREE_VALUE (BRANCH_ISLAND)
14776 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND)  TREE_PURPOSE (BRANCH_ISLAND)
14777 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND)    \
14778                 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
14779
14780 /* Generate far-jump branch islands for everything on the
14781    branch_island_list.  Invoked immediately after the last instruction
14782    of the epilogue has been emitted; the branch-islands must be
14783    appended to, and contiguous with, the function body.  Mach-O stubs
14784    are generated in machopic_output_stub().  */
14785
14786 static void
14787 macho_branch_islands (void)
14788 {
14789   char tmp_buf[512];
14790   tree branch_island;
14791
14792   for (branch_island = branch_island_list;
14793        branch_island;
14794        branch_island = TREE_CHAIN (branch_island))
14795     {
14796       const char *label =
14797         IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
14798       const char *name  =
14799         darwin_strip_name_encoding (
14800           IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)));
14801       char name_buf[512];
14802       /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF().  */
14803       if (name[0] == '*' || name[0] == '&')
14804         strcpy (name_buf, name+1);
14805       else
14806         {
14807           name_buf[0] = '_';
14808           strcpy (name_buf+1, name);
14809         }
14810       strcpy (tmp_buf, "\n");
14811       strcat (tmp_buf, label);
14812 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14813       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14814         fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14815                  BRANCH_ISLAND_LINE_NUMBER(branch_island));
14816 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14817       if (flag_pic)
14818         {
14819           strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
14820           strcat (tmp_buf, label);
14821           strcat (tmp_buf, "_pic\n");
14822           strcat (tmp_buf, label);
14823           strcat (tmp_buf, "_pic:\n\tmflr r11\n");
14824
14825           strcat (tmp_buf, "\taddis r11,r11,ha16(");
14826           strcat (tmp_buf, name_buf);
14827           strcat (tmp_buf, " - ");
14828           strcat (tmp_buf, label);
14829           strcat (tmp_buf, "_pic)\n");
14830
14831           strcat (tmp_buf, "\tmtlr r0\n");
14832
14833           strcat (tmp_buf, "\taddi r12,r11,lo16(");
14834           strcat (tmp_buf, name_buf);
14835           strcat (tmp_buf, " - ");
14836           strcat (tmp_buf, label);
14837           strcat (tmp_buf, "_pic)\n");
14838
14839           strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
14840         }
14841       else
14842         {
14843           strcat (tmp_buf, ":\nlis r12,hi16(");
14844           strcat (tmp_buf, name_buf);
14845           strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
14846           strcat (tmp_buf, name_buf);
14847           strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
14848         }
14849       output_asm_insn (tmp_buf, 0);
14850 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14851       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14852         fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14853                 BRANCH_ISLAND_LINE_NUMBER (branch_island));
14854 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14855     }
14856
14857   branch_island_list = 0;
14858 }
14859
14860 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
14861    already there or not.  */
14862
14863 static int
14864 no_previous_def (tree function_name)
14865 {
14866   tree branch_island;
14867   for (branch_island = branch_island_list;
14868        branch_island;
14869        branch_island = TREE_CHAIN (branch_island))
14870     if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14871       return 0;
14872   return 1;
14873 }
14874
14875 /* GET_PREV_LABEL gets the label name from the previous definition of
14876    the function.  */
14877
14878 static tree
14879 get_prev_label (tree function_name)
14880 {
14881   tree branch_island;
14882   for (branch_island = branch_island_list;
14883        branch_island;
14884        branch_island = TREE_CHAIN (branch_island))
14885     if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14886       return BRANCH_ISLAND_LABEL_NAME (branch_island);
14887   return 0;
14888 }
14889
14890 /* INSN is either a function call or a millicode call.  It may have an
14891    unconditional jump in its delay slot.
14892
14893    CALL_DEST is the routine we are calling.  */
14894
14895 char *
14896 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
14897 {
14898   static char buf[256];
14899   if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
14900       && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
14901     {
14902       tree labelname;
14903       tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
14904
14905       if (no_previous_def (funname))
14906         {
14907           int line_number = 0;
14908           rtx label_rtx = gen_label_rtx ();
14909           char *label_buf, temp_buf[256];
14910           ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
14911                                        CODE_LABEL_NUMBER (label_rtx));
14912           label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
14913           labelname = get_identifier (label_buf);
14914           for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
14915           if (insn)
14916             line_number = NOTE_LINE_NUMBER (insn);
14917           add_compiler_branch_island (labelname, funname, line_number);
14918         }
14919       else
14920         labelname = get_prev_label (funname);
14921
14922       /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
14923          instruction will reach 'foo', otherwise link as 'bl L42'".
14924          "L42" should be a 'branch island', that will do a far jump to
14925          'foo'.  Branch islands are generated in
14926          macho_branch_islands().  */
14927       sprintf (buf, "jbsr %%z%d,%.246s",
14928                dest_operand_number, IDENTIFIER_POINTER (labelname));
14929     }
14930   else
14931     sprintf (buf, "bl %%z%d", dest_operand_number);
14932   return buf;
14933 }
14934
14935 #endif /* TARGET_MACHO */
14936
14937 /* Generate PIC and indirect symbol stubs.  */
14938
14939 void
14940 machopic_output_stub (FILE *file, const char *symb, const char *stub)
14941 {
14942   unsigned int length;
14943   char *symbol_name, *lazy_ptr_name;
14944   char *local_label_0;
14945   static int label = 0;
14946
14947   /* Lose our funky encoding stuff so it doesn't contaminate the stub.  */
14948   symb = (*targetm.strip_name_encoding) (symb);
14949
14950
14951   length = strlen (symb);
14952   symbol_name = alloca (length + 32);
14953   GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
14954
14955   lazy_ptr_name = alloca (length + 32);
14956   GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
14957
14958   if (flag_pic == 2)
14959     machopic_picsymbol_stub1_section ();
14960   else
14961     machopic_symbol_stub1_section ();
14962   fprintf (file, "\t.align 2\n");
14963
14964   fprintf (file, "%s:\n", stub);
14965   fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14966
14967   if (flag_pic == 2)
14968     {
14969       label++;
14970       local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
14971       sprintf (local_label_0, "\"L%011d$spb\"", label);
14972
14973       fprintf (file, "\tmflr r0\n");
14974       fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
14975       fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
14976       fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
14977                lazy_ptr_name, local_label_0);
14978       fprintf (file, "\tmtlr r0\n");
14979       fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
14980                lazy_ptr_name, local_label_0);
14981       fprintf (file, "\tmtctr r12\n");
14982       fprintf (file, "\tbctr\n");
14983     }
14984   else
14985    {
14986      fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
14987      fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
14988      fprintf (file, "\tmtctr r12\n");
14989      fprintf (file, "\tbctr\n");
14990    }
14991
14992   machopic_lazy_symbol_ptr_section ();
14993   fprintf (file, "%s:\n", lazy_ptr_name);
14994   fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14995   fprintf (file, "\t.long dyld_stub_binding_helper\n");
14996 }
14997
14998 /* Legitimize PIC addresses.  If the address is already
14999    position-independent, we return ORIG.  Newly generated
15000    position-independent addresses go into a reg.  This is REG if non
15001    zero, otherwise we allocate register(s) as necessary.  */
15002
15003 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
15004
15005 rtx
15006 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
15007                                         rtx reg)
15008 {
15009   rtx base, offset;
15010
15011   if (reg == NULL && ! reload_in_progress && ! reload_completed)
15012     reg = gen_reg_rtx (Pmode);
15013
15014   if (GET_CODE (orig) == CONST)
15015     {
15016       if (GET_CODE (XEXP (orig, 0)) == PLUS
15017           && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
15018         return orig;
15019
15020       if (GET_CODE (XEXP (orig, 0)) == PLUS)
15021         {
15022           /* Use a different reg for the intermediate value, as
15023              it will be marked UNCHANGING.  */
15024           rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
15025
15026           base =
15027             rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
15028                                                     Pmode, reg_temp);
15029           offset =
15030             rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
15031                                                     Pmode, reg);
15032         }
15033       else
15034         abort ();
15035
15036       if (GET_CODE (offset) == CONST_INT)
15037         {
15038           if (SMALL_INT (offset))
15039             return plus_constant (base, INTVAL (offset));
15040           else if (! reload_in_progress && ! reload_completed)
15041             offset = force_reg (Pmode, offset);
15042           else
15043             {
15044               rtx mem = force_const_mem (Pmode, orig);
15045               return machopic_legitimize_pic_address (mem, Pmode, reg);
15046             }
15047         }
15048       return gen_rtx (PLUS, Pmode, base, offset);
15049     }
15050
15051   /* Fall back on generic machopic code.  */
15052   return machopic_legitimize_pic_address (orig, mode, reg);
15053 }
15054
15055 /* This is just a placeholder to make linking work without having to
15056    add this to the generic Darwin EXTRA_SECTIONS.  If -mcall-aix is
15057    ever needed for Darwin (not too likely!) this would have to get a
15058    real definition.  */
15059
15060 void
15061 toc_section (void)
15062 {
15063 }
15064
15065 #endif /* TARGET_MACHO */
15066
15067 #if TARGET_ELF
15068 static unsigned int
15069 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
15070 {
15071   return default_section_type_flags_1 (decl, name, reloc,
15072                                        flag_pic || DEFAULT_ABI == ABI_AIX);
15073 }
15074
15075 /* Record an element in the table of global constructors.  SYMBOL is
15076    a SYMBOL_REF of the function to be called; PRIORITY is a number
15077    between 0 and MAX_INIT_PRIORITY.
15078
15079    This differs from default_named_section_asm_out_constructor in
15080    that we have special handling for -mrelocatable.  */
15081
15082 static void
15083 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
15084 {
15085   const char *section = ".ctors";
15086   char buf[16];
15087
15088   if (priority != DEFAULT_INIT_PRIORITY)
15089     {
15090       sprintf (buf, ".ctors.%.5u",
15091                /* Invert the numbering so the linker puts us in the proper
15092                   order; constructors are run from right to left, and the
15093                   linker sorts in increasing order.  */
15094                MAX_INIT_PRIORITY - priority);
15095       section = buf;
15096     }
15097
15098   named_section_flags (section, SECTION_WRITE);
15099   assemble_align (POINTER_SIZE);
15100
15101   if (TARGET_RELOCATABLE)
15102     {
15103       fputs ("\t.long (", asm_out_file);
15104       output_addr_const (asm_out_file, symbol);
15105       fputs (")@fixup\n", asm_out_file);
15106     }
15107   else
15108     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15109 }
15110
15111 static void
15112 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
15113 {
15114   const char *section = ".dtors";
15115   char buf[16];
15116
15117   if (priority != DEFAULT_INIT_PRIORITY)
15118     {
15119       sprintf (buf, ".dtors.%.5u",
15120                /* Invert the numbering so the linker puts us in the proper
15121                   order; constructors are run from right to left, and the
15122                   linker sorts in increasing order.  */
15123                MAX_INIT_PRIORITY - priority);
15124       section = buf;
15125     }
15126
15127   named_section_flags (section, SECTION_WRITE);
15128   assemble_align (POINTER_SIZE);
15129
15130   if (TARGET_RELOCATABLE)
15131     {
15132       fputs ("\t.long (", asm_out_file);
15133       output_addr_const (asm_out_file, symbol);
15134       fputs (")@fixup\n", asm_out_file);
15135     }
15136   else
15137     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15138 }
15139
15140 void
15141 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
15142 {
15143   if (TARGET_64BIT)
15144     {
15145       fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
15146       ASM_OUTPUT_LABEL (file, name);
15147       fputs (DOUBLE_INT_ASM_OP, file);
15148       putc ('.', file);
15149       assemble_name (file, name);
15150       fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file);
15151       assemble_name (file, name);
15152       fputs (",24\n\t.type\t.", file);
15153       assemble_name (file, name);
15154       fputs (",@function\n", file);
15155       if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
15156         {
15157           fputs ("\t.globl\t.", file);
15158           assemble_name (file, name);
15159           putc ('\n', file);
15160         }
15161       ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15162       putc ('.', file);
15163       ASM_OUTPUT_LABEL (file, name);
15164       return;
15165     }
15166
15167   if (TARGET_RELOCATABLE
15168       && (get_pool_size () != 0 || current_function_profile)
15169       && uses_TOC ())
15170     {
15171       char buf[256];
15172
15173       (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
15174
15175       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15176       fprintf (file, "\t.long ");
15177       assemble_name (file, buf);
15178       putc ('-', file);
15179       ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15180       assemble_name (file, buf);
15181       putc ('\n', file);
15182     }
15183
15184   ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
15185   ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15186
15187   if (DEFAULT_ABI == ABI_AIX)
15188     {
15189       const char *desc_name, *orig_name;
15190
15191       orig_name = (*targetm.strip_name_encoding) (name);
15192       desc_name = orig_name;
15193       while (*desc_name == '.')
15194         desc_name++;
15195
15196       if (TREE_PUBLIC (decl))
15197         fprintf (file, "\t.globl %s\n", desc_name);
15198
15199       fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
15200       fprintf (file, "%s:\n", desc_name);
15201       fprintf (file, "\t.long %s\n", orig_name);
15202       fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
15203       if (DEFAULT_ABI == ABI_AIX)
15204         fputs ("\t.long 0\n", file);
15205       fprintf (file, "\t.previous\n");
15206     }
15207   ASM_OUTPUT_LABEL (file, name);
15208 }
15209 #endif
15210
15211 #if TARGET_XCOFF
15212 static void
15213 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
15214 {
15215   fputs (GLOBAL_ASM_OP, stream);
15216   RS6000_OUTPUT_BASENAME (stream, name);
15217   putc ('\n', stream);
15218 }
15219
15220 static void
15221 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
15222 {
15223   int smclass;
15224   static const char * const suffix[3] = { "PR", "RO", "RW" };
15225
15226   if (flags & SECTION_CODE)
15227     smclass = 0;
15228   else if (flags & SECTION_WRITE)
15229     smclass = 2;
15230   else
15231     smclass = 1;
15232
15233   fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
15234            (flags & SECTION_CODE) ? "." : "",
15235            name, suffix[smclass], flags & SECTION_ENTSIZE);
15236 }
15237
15238 static void
15239 rs6000_xcoff_select_section (tree decl, int reloc,
15240                             unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15241 {
15242   if (decl_readonly_section_1 (decl, reloc, 1))
15243     {
15244       if (TREE_PUBLIC (decl))
15245         read_only_data_section ();
15246       else
15247         read_only_private_data_section ();
15248     }
15249   else
15250     {
15251       if (TREE_PUBLIC (decl))
15252         data_section ();
15253       else
15254         private_data_section ();
15255     }
15256 }
15257
15258 static void
15259 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
15260 {
15261   const char *name;
15262
15263   /* Use select_section for private and uninitialized data.  */
15264   if (!TREE_PUBLIC (decl)
15265       || DECL_COMMON (decl)
15266       || DECL_INITIAL (decl) == NULL_TREE
15267       || DECL_INITIAL (decl) == error_mark_node
15268       || (flag_zero_initialized_in_bss
15269           && initializer_zerop (DECL_INITIAL (decl))))
15270     return;
15271
15272   name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
15273   name = (*targetm.strip_name_encoding) (name);
15274   DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
15275 }
15276
15277 /* Select section for constant in constant pool.
15278
15279    On RS/6000, all constants are in the private read-only data area.
15280    However, if this is being placed in the TOC it must be output as a
15281    toc entry.  */
15282
15283 static void
15284 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
15285                                 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15286 {
15287   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15288     toc_section ();
15289   else
15290     read_only_private_data_section ();
15291 }
15292
15293 /* Remove any trailing [DS] or the like from the symbol name.  */
15294
15295 static const char *
15296 rs6000_xcoff_strip_name_encoding (const char *name)
15297 {
15298   size_t len;
15299   if (*name == '*')
15300     name++;
15301   len = strlen (name);
15302   if (name[len - 1] == ']')
15303     return ggc_alloc_string (name, len - 4);
15304   else
15305     return name;
15306 }
15307
15308 /* Section attributes.  AIX is always PIC.  */
15309
15310 static unsigned int
15311 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
15312 {
15313   unsigned int align;
15314   unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
15315
15316   /* Align to at least UNIT size.  */
15317   if (flags & SECTION_CODE)
15318     align = MIN_UNITS_PER_WORD;
15319   else
15320     /* Increase alignment of large objects if not already stricter.  */
15321     align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
15322                  int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
15323                  ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
15324
15325   return flags | (exact_log2 (align) & SECTION_ENTSIZE);
15326 }
15327
15328 /* Output at beginning of assembler file.
15329
15330    Initialize the section names for the RS/6000 at this point.
15331
15332    Specify filename, including full path, to assembler.
15333
15334    We want to go into the TOC section so at least one .toc will be emitted.
15335    Also, in order to output proper .bs/.es pairs, we need at least one static
15336    [RW] section emitted.
15337
15338    Finally, declare mcount when profiling to make the assembler happy.  */
15339
15340 static void
15341 rs6000_xcoff_file_start (void)
15342 {
15343   rs6000_gen_section_name (&xcoff_bss_section_name,
15344                            main_input_filename, ".bss_");
15345   rs6000_gen_section_name (&xcoff_private_data_section_name,
15346                            main_input_filename, ".rw_");
15347   rs6000_gen_section_name (&xcoff_read_only_section_name,
15348                            main_input_filename, ".ro_");
15349
15350   fputs ("\t.file\t", asm_out_file);
15351   output_quoted_string (asm_out_file, main_input_filename);
15352   fputc ('\n', asm_out_file);
15353   toc_section ();
15354   if (write_symbols != NO_DEBUG)
15355     private_data_section ();
15356   text_section ();
15357   if (profile_flag)
15358     fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
15359   rs6000_file_start ();
15360 }
15361
15362 /* Output at end of assembler file.
15363    On the RS/6000, referencing data should automatically pull in text.  */
15364
15365 static void
15366 rs6000_xcoff_file_end (void)
15367 {
15368   text_section ();
15369   fputs ("_section_.text:\n", asm_out_file);
15370   data_section ();
15371   fputs (TARGET_32BIT
15372          ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
15373          asm_out_file);
15374 }
15375 #endif /* TARGET_XCOFF */
15376
15377 #if TARGET_MACHO
15378 /* Cross-module name binding.  Darwin does not support overriding
15379    functions at dynamic-link time.  */
15380
15381 static bool
15382 rs6000_binds_local_p (tree decl)
15383 {
15384   return default_binds_local_p_1 (decl, 0);
15385 }
15386 #endif
15387
15388 /* Compute a (partial) cost for rtx X.  Return true if the complete
15389    cost has been computed, and false if subexpressions should be
15390    scanned.  In either case, *TOTAL contains the cost result.  */
15391
15392 static bool
15393 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
15394                   int *total)
15395 {
15396   switch (code)
15397     {
15398       /* On the RS/6000, if it is valid in the insn, it is free.
15399          So this always returns 0.  */
15400     case CONST_INT:
15401     case CONST:
15402     case LABEL_REF:
15403     case SYMBOL_REF:
15404     case CONST_DOUBLE:
15405     case HIGH:
15406       *total = 0;
15407       return true;
15408
15409     case PLUS:
15410       *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15411                  && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1))
15412                                                + 0x8000) >= 0x10000)
15413                  && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15414                 ? COSTS_N_INSNS (2)
15415                 : COSTS_N_INSNS (1));
15416       return true;
15417
15418     case AND:
15419     case IOR:
15420     case XOR:
15421       *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15422                  && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0
15423                  && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15424                 ? COSTS_N_INSNS (2)
15425                 : COSTS_N_INSNS (1));
15426       return true;
15427
15428     case MULT:
15429       if (optimize_size)
15430         {
15431           *total = COSTS_N_INSNS (2);
15432           return true;
15433         }
15434       switch (rs6000_cpu)
15435         {
15436         case PROCESSOR_RIOS1:
15437         case PROCESSOR_PPC405:
15438           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15439                     ? COSTS_N_INSNS (5)
15440                     : (INTVAL (XEXP (x, 1)) >= -256
15441                        && INTVAL (XEXP (x, 1)) <= 255)
15442                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15443           return true;
15444
15445         case PROCESSOR_PPC440:
15446           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15447                     ? COSTS_N_INSNS (3)
15448                     : COSTS_N_INSNS (2));
15449           return true;
15450
15451         case PROCESSOR_RS64A:
15452           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15453                     ? GET_MODE (XEXP (x, 1)) != DImode
15454                     ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34)
15455                     : (INTVAL (XEXP (x, 1)) >= -256
15456                        && INTVAL (XEXP (x, 1)) <= 255)
15457                     ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12));
15458           return true;
15459
15460         case PROCESSOR_RIOS2:
15461         case PROCESSOR_MPCCORE:
15462         case PROCESSOR_PPC604e:
15463           *total = COSTS_N_INSNS (2);
15464           return true;
15465
15466         case PROCESSOR_PPC601:
15467           *total = COSTS_N_INSNS (5);
15468           return true;
15469
15470         case PROCESSOR_PPC603:
15471         case PROCESSOR_PPC7400:
15472         case PROCESSOR_PPC750:
15473           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15474                     ? COSTS_N_INSNS (5)
15475                     : (INTVAL (XEXP (x, 1)) >= -256
15476                        && INTVAL (XEXP (x, 1)) <= 255)
15477                     ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));
15478           return true;
15479
15480         case PROCESSOR_PPC7450:
15481           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15482                     ? COSTS_N_INSNS (4)
15483                     : COSTS_N_INSNS (3));
15484           return true;
15485
15486         case PROCESSOR_PPC403:
15487         case PROCESSOR_PPC604:
15488         case PROCESSOR_PPC8540:
15489           *total = COSTS_N_INSNS (4);
15490           return true;
15491
15492         case PROCESSOR_PPC620:
15493         case PROCESSOR_PPC630:
15494           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15495                     ? GET_MODE (XEXP (x, 1)) != DImode
15496                     ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
15497                     : (INTVAL (XEXP (x, 1)) >= -256
15498                        && INTVAL (XEXP (x, 1)) <= 255)
15499                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15500           return true;
15501
15502         case PROCESSOR_POWER4:
15503           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15504                     ? GET_MODE (XEXP (x, 1)) != DImode
15505                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
15506                     : COSTS_N_INSNS (2));
15507           return true;
15508
15509         default:
15510           abort ();
15511         }
15512
15513     case DIV:
15514     case MOD:
15515       if (GET_CODE (XEXP (x, 1)) == CONST_INT
15516           && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
15517         {
15518           *total = COSTS_N_INSNS (2);
15519           return true;
15520         }
15521       /* FALLTHRU */
15522
15523     case UDIV:
15524     case UMOD:
15525       switch (rs6000_cpu)
15526         {
15527         case PROCESSOR_RIOS1:
15528           *total = COSTS_N_INSNS (19);
15529           return true;
15530
15531         case PROCESSOR_RIOS2:
15532           *total = COSTS_N_INSNS (13);
15533           return true;
15534
15535         case PROCESSOR_RS64A:
15536           *total = (GET_MODE (XEXP (x, 1)) != DImode
15537                     ? COSTS_N_INSNS (65)
15538                     : COSTS_N_INSNS (67));
15539           return true;
15540
15541         case PROCESSOR_MPCCORE:
15542           *total = COSTS_N_INSNS (6);
15543           return true;
15544
15545         case PROCESSOR_PPC403:
15546           *total = COSTS_N_INSNS (33);
15547           return true;
15548
15549         case PROCESSOR_PPC405:
15550           *total = COSTS_N_INSNS (35);
15551           return true;
15552
15553         case PROCESSOR_PPC440:
15554           *total = COSTS_N_INSNS (34);
15555           return true;
15556
15557         case PROCESSOR_PPC601:
15558           *total = COSTS_N_INSNS (36);
15559           return true;
15560
15561         case PROCESSOR_PPC603:
15562           *total = COSTS_N_INSNS (37);
15563           return true;
15564
15565         case PROCESSOR_PPC604:
15566         case PROCESSOR_PPC604e:
15567           *total = COSTS_N_INSNS (20);
15568           return true;
15569
15570         case PROCESSOR_PPC620:
15571         case PROCESSOR_PPC630:
15572           *total = (GET_MODE (XEXP (x, 1)) != DImode
15573                     ? COSTS_N_INSNS (21)
15574                     : COSTS_N_INSNS (37));
15575           return true;
15576
15577         case PROCESSOR_PPC750:
15578         case PROCESSOR_PPC8540:
15579         case PROCESSOR_PPC7400:
15580           *total = COSTS_N_INSNS (19);
15581           return true;
15582
15583         case PROCESSOR_PPC7450:
15584           *total = COSTS_N_INSNS (23);
15585           return true;
15586
15587         case PROCESSOR_POWER4:
15588           *total = (GET_MODE (XEXP (x, 1)) != DImode
15589                     ? COSTS_N_INSNS (18)
15590                     : COSTS_N_INSNS (34));
15591           return true;
15592
15593         default:
15594           abort ();
15595         }
15596
15597     case FFS:
15598       *total = COSTS_N_INSNS (4);
15599       return true;
15600
15601     case MEM:
15602       /* MEM should be slightly more expensive than (plus (reg) (const)).  */
15603       *total = 5;
15604       return true;
15605
15606     default:
15607       return false;
15608     }
15609 }
15610
15611 /* A C expression returning the cost of moving data from a register of class
15612    CLASS1 to one of CLASS2.  */
15613
15614 int
15615 rs6000_register_move_cost (enum machine_mode mode,
15616                            enum reg_class from, enum reg_class to)
15617 {
15618   /*  Moves from/to GENERAL_REGS.  */
15619   if (reg_classes_intersect_p (to, GENERAL_REGS)
15620       || reg_classes_intersect_p (from, GENERAL_REGS))
15621     {
15622       if (! reg_classes_intersect_p (to, GENERAL_REGS))
15623         from = to;
15624
15625       if (from == FLOAT_REGS || from == ALTIVEC_REGS)
15626         return (rs6000_memory_move_cost (mode, from, 0)
15627                 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
15628
15629 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift....  */
15630       else if (from == CR_REGS)
15631         return 4;
15632
15633       else
15634 /* A move will cost one instruction per GPR moved.  */
15635         return 2 * HARD_REGNO_NREGS (0, mode);
15636     }
15637
15638 /* Moving between two similar registers is just one instruction.  */
15639   else if (reg_classes_intersect_p (to, from))
15640     return mode == TFmode ? 4 : 2;
15641
15642 /* Everything else has to go through GENERAL_REGS.  */
15643   else
15644     return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
15645             + rs6000_register_move_cost (mode, from, GENERAL_REGS));
15646 }
15647
15648 /* A C expressions returning the cost of moving data of MODE from a register to
15649    or from memory.  */
15650
15651 int
15652 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
15653                          int in ATTRIBUTE_UNUSED)
15654 {
15655   if (reg_classes_intersect_p (class, GENERAL_REGS))
15656     return 4 * HARD_REGNO_NREGS (0, mode);
15657   else if (reg_classes_intersect_p (class, FLOAT_REGS))
15658     return 4 * HARD_REGNO_NREGS (32, mode);
15659   else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
15660     return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
15661   else
15662     return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
15663 }
15664
15665 /* Return an RTX representing where to find the function value of a
15666    function returning MODE.  */
15667 static rtx
15668 rs6000_complex_function_value (enum machine_mode mode)
15669 {
15670   unsigned int regno;
15671   rtx r1, r2;
15672   enum machine_mode inner = GET_MODE_INNER (mode);
15673
15674   if (FLOAT_MODE_P (mode))
15675     regno = FP_ARG_RETURN;
15676   else
15677     {
15678       regno = GP_ARG_RETURN;
15679
15680       /* 32-bit is OK since it'll go in r3/r4.  */
15681       if (TARGET_32BIT
15682           && GET_MODE_BITSIZE (inner) >= 32)
15683         return gen_rtx_REG (mode, regno);
15684     }
15685
15686   r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
15687                           const0_rtx);
15688   r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
15689                           GEN_INT (GET_MODE_UNIT_SIZE (inner)));
15690   return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
15691 }
15692
15693 /* Define how to find the value returned by a function.
15694    VALTYPE is the data type of the value (as a tree).
15695    If the precise function being called is known, FUNC is its FUNCTION_DECL;
15696    otherwise, FUNC is 0.
15697
15698    On the SPE, both FPs and vectors are returned in r3.
15699
15700    On RS/6000 an integer value is in r3 and a floating-point value is in
15701    fp1, unless -msoft-float.  */
15702
15703 rtx
15704 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
15705 {
15706   enum machine_mode mode;
15707   unsigned int regno;
15708
15709   if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
15710     {
15711       /* Long long return value need be split in -mpowerpc64, 32bit ABI.  */
15712       return gen_rtx_PARALLEL (DImode,
15713         gen_rtvec (2,
15714                    gen_rtx_EXPR_LIST (VOIDmode,
15715                                       gen_rtx_REG (SImode, GP_ARG_RETURN),
15716                                       const0_rtx),
15717                    gen_rtx_EXPR_LIST (VOIDmode,
15718                                       gen_rtx_REG (SImode,
15719                                                    GP_ARG_RETURN + 1),
15720                                       GEN_INT (4))));
15721     }
15722
15723   if ((INTEGRAL_TYPE_P (valtype)
15724        && TYPE_PRECISION (valtype) < BITS_PER_WORD)
15725       || POINTER_TYPE_P (valtype))
15726     mode = TARGET_32BIT ? SImode : DImode;
15727   else
15728     mode = TYPE_MODE (valtype);
15729
15730   if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS)
15731     regno = FP_ARG_RETURN;
15732   else if (TREE_CODE (valtype) == COMPLEX_TYPE
15733            && TARGET_HARD_FLOAT
15734            && SPLIT_COMPLEX_ARGS)
15735     return rs6000_complex_function_value (mode);
15736   else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC)
15737     regno = ALTIVEC_ARG_RETURN;
15738   else
15739     regno = GP_ARG_RETURN;
15740
15741   return gen_rtx_REG (mode, regno);
15742 }
15743
15744 /* Define how to find the value returned by a library function
15745    assuming the value has mode MODE.  */
15746 rtx
15747 rs6000_libcall_value (enum machine_mode mode)
15748 {
15749   unsigned int regno;
15750
15751   if (GET_MODE_CLASS (mode) == MODE_FLOAT
15752            && TARGET_HARD_FLOAT && TARGET_FPRS)
15753     regno = FP_ARG_RETURN;
15754   else if (ALTIVEC_VECTOR_MODE (mode))
15755     regno = ALTIVEC_ARG_RETURN;
15756   else if (COMPLEX_MODE_P (mode) && SPLIT_COMPLEX_ARGS)
15757     return rs6000_complex_function_value (mode);
15758   else
15759     regno = GP_ARG_RETURN;
15760
15761   return gen_rtx_REG (mode, regno);
15762 }
15763
15764 /* Define the offset between two registers, FROM to be eliminated and its
15765    replacement TO, at the start of a routine.  */
15766 HOST_WIDE_INT
15767 rs6000_initial_elimination_offset (int from, int to)
15768 {
15769   rs6000_stack_t *info = rs6000_stack_info ();
15770   HOST_WIDE_INT offset;
15771
15772   if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15773     offset = info->push_p ? 0 : -info->total_size;
15774   else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
15775     offset = info->total_size;
15776   else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15777     offset = info->push_p ? info->total_size : 0;
15778   else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
15779     offset = 0;
15780   else
15781     abort ();
15782
15783   return offset;
15784 }
15785
15786 /* Return true if TYPE is of type __ev64_opaque__.  */
15787
15788 static bool
15789 is_ev64_opaque_type (tree type)
15790 {
15791   return (TARGET_SPE
15792           && (type == opaque_V2SI_type_node
15793               || type == opaque_V2SF_type_node
15794               || type == opaque_p_V2SI_type_node));
15795 }
15796
15797 static rtx
15798 rs6000_dwarf_register_span (rtx reg)
15799 {
15800   unsigned regno;
15801
15802   if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
15803     return NULL_RTX;
15804
15805   regno = REGNO (reg);
15806
15807   /* The duality of the SPE register size wreaks all kinds of havoc.
15808      This is a way of distinguishing r0 in 32-bits from r0 in
15809      64-bits.  */
15810   return
15811     gen_rtx_PARALLEL (VOIDmode,
15812                       BYTES_BIG_ENDIAN
15813                       ? gen_rtvec (2,
15814                                    gen_rtx_REG (SImode, regno + 1200),
15815                                    gen_rtx_REG (SImode, regno))
15816                       : gen_rtvec (2,
15817                                    gen_rtx_REG (SImode, regno),
15818                                    gen_rtx_REG (SImode, regno + 1200)));
15819 }
15820
15821 /* Map internal gcc register numbers to DWARF2 register numbers.  */
15822
15823 unsigned int
15824 rs6000_dbx_register_number (unsigned int regno)
15825 {
15826   if (regno <= 63 || write_symbols != DWARF2_DEBUG)
15827     return regno;
15828   if (regno == MQ_REGNO)
15829     return 100;
15830   if (regno == LINK_REGISTER_REGNUM)
15831     return 108;
15832   if (regno == COUNT_REGISTER_REGNUM)
15833     return 109;
15834   if (CR_REGNO_P (regno))
15835     return regno - CR0_REGNO + 86;
15836   if (regno == XER_REGNO)
15837     return 101;
15838   if (ALTIVEC_REGNO_P (regno))
15839     return regno - FIRST_ALTIVEC_REGNO + 1124;
15840   if (regno == VRSAVE_REGNO)
15841     return 356;
15842   if (regno == VSCR_REGNO)
15843     return 67;
15844   if (regno == SPE_ACC_REGNO)
15845     return 99;
15846   if (regno == SPEFSCR_REGNO)
15847     return 612;
15848   /* SPE high reg number.  We get these values of regno from
15849      rs6000_dwarf_register_span.  */
15850   if (regno >= 1200 && regno < 1232)
15851     return regno;
15852
15853   abort ();
15854 }
15855
15856 #include "gt-rs6000.h"