1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
53 #include "sched-int.h"
55 #include "tree-flow.h"
58 #include "tm-constrs.h"
60 #include "tree-vectorizer.h"
63 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
66 #include "gstab.h" /* for N_SLINE */
69 #ifndef TARGET_NO_PROTOTYPE
70 #define TARGET_NO_PROTOTYPE 0
73 #define min(A,B) ((A) < (B) ? (A) : (B))
74 #define max(A,B) ((A) > (B) ? (A) : (B))
76 /* Structure used to define the rs6000 stack */
77 typedef struct rs6000_stack
{
78 int reload_completed
; /* stack info won't change from here on */
79 int first_gp_reg_save
; /* first callee saved GP register used */
80 int first_fp_reg_save
; /* first callee saved FP register used */
81 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
82 int lr_save_p
; /* true if the link reg needs to be saved */
83 int cr_save_p
; /* true if the CR reg needs to be saved */
84 unsigned int vrsave_mask
; /* mask of vec registers to save */
85 int push_p
; /* true if we need to allocate stack space */
86 int calls_p
; /* true if the function makes any calls */
87 int world_save_p
; /* true if we're saving *everything*:
88 r13-r31, cr, f14-f31, vrsave, v20-v31 */
89 enum rs6000_abi abi
; /* which ABI to use */
90 int gp_save_offset
; /* offset to save GP regs from initial SP */
91 int fp_save_offset
; /* offset to save FP regs from initial SP */
92 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
93 int lr_save_offset
; /* offset to save LR from initial SP */
94 int cr_save_offset
; /* offset to save CR from initial SP */
95 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
96 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
97 int varargs_save_offset
; /* offset to save the varargs registers */
98 int ehrd_offset
; /* offset to EH return data */
99 int reg_size
; /* register size (4 or 8) */
100 HOST_WIDE_INT vars_size
; /* variable save area size */
101 int parm_size
; /* outgoing parameter size */
102 int save_size
; /* save area size */
103 int fixed_size
; /* fixed size of stack frame */
104 int gp_size
; /* size of saved GP registers */
105 int fp_size
; /* size of saved FP registers */
106 int altivec_size
; /* size of saved AltiVec registers */
107 int cr_size
; /* size to hold CR if not in save_size */
108 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size
; /* size of altivec alignment padding if
111 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size
;
113 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
114 int spe_64bit_regs_used
;
118 /* A C structure for machine-specific, per-function data.
119 This is added to the cfun structure. */
120 typedef struct GTY(()) machine_function
122 /* Some local-dynamic symbol. */
123 const char *some_ld_name
;
124 /* Whether the instruction chain has been scanned already. */
125 int insn_chain_scanned_p
;
126 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
127 int ra_needs_full_frame
;
128 /* Flags if __builtin_return_address (0) was used. */
130 /* Cache lr_save_p after expansion of builtin_eh_return. */
132 /* Whether we need to save the TOC to the reserved stack location in the
133 function prologue. */
134 bool save_toc_in_prologue
;
135 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
136 varargs save area. */
137 HOST_WIDE_INT varargs_save_offset
;
138 /* Temporary stack slot to use for SDmode copies. This slot is
139 64-bits wide and is allocated early enough so that the offset
140 does not overflow the 16-bit load/store offset field. */
141 rtx sdmode_stack_slot
;
144 /* Support targetm.vectorize.builtin_mask_for_load. */
145 static GTY(()) tree altivec_builtin_mask_for_load
;
147 /* Set to nonzero once AIX common-mode calls have been defined. */
148 static GTY(()) int common_mode_defined
;
150 /* Label number of label created for -mrelocatable, to call to so we can
151 get the address of the GOT section */
152 static int rs6000_pic_labelno
;
155 /* Counter for labels which are to be placed in .fixup. */
156 int fixuplabelno
= 0;
159 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
162 /* Specify the machine mode that pointers have. After generation of rtl, the
163 compiler makes no further distinction between pointers and any other objects
164 of this machine mode. The type is unsigned since not all things that
165 include rs6000.h also include machmode.h. */
166 unsigned rs6000_pmode
;
168 /* Width in bits of a pointer. */
169 unsigned rs6000_pointer_size
;
171 #ifdef HAVE_AS_GNU_ATTRIBUTE
172 /* Flag whether floating point values have been passed/returned. */
173 static bool rs6000_passes_float
;
174 /* Flag whether vector values have been passed/returned. */
175 static bool rs6000_passes_vector
;
176 /* Flag whether small (<= 8 byte) structures have been returned. */
177 static bool rs6000_returns_struct
;
180 /* Value is TRUE if register/mode pair is acceptable. */
181 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
183 /* Maximum number of registers needed for a given register class and mode. */
184 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
186 /* How many registers are needed for a given register and mode. */
187 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
189 /* Map register number to register class. */
190 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
192 /* Reload functions based on the type and the vector unit. */
193 static enum insn_code rs6000_vector_reload
[NUM_MACHINE_MODES
][2];
195 static int dbg_cost_ctrl
;
197 /* Built in types. */
198 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
199 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
201 /* Flag to say the TOC is initialized */
203 char toc_label_name
[10];
205 /* Cached value of rs6000_variable_issue. This is cached in
206 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
207 static short cached_can_issue_more
;
209 static GTY(()) section
*read_only_data_section
;
210 static GTY(()) section
*private_data_section
;
211 static GTY(()) section
*tls_data_section
;
212 static GTY(()) section
*tls_private_data_section
;
213 static GTY(()) section
*read_only_private_data_section
;
214 static GTY(()) section
*sdata2_section
;
215 static GTY(()) section
*toc_section
;
217 struct builtin_description
219 const HOST_WIDE_INT mask
;
220 const enum insn_code icode
;
221 const char *const name
;
222 const enum rs6000_builtins code
;
225 /* Describe the vector unit used for modes. */
226 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
227 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
229 /* Register classes for various constraints that are based on the target
231 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
233 /* Describe the alignment of a vector. */
234 int rs6000_vector_align
[NUM_MACHINE_MODES
];
236 /* Map selected modes to types for builtins. */
237 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240 reciprocal sqrt (frsqrte) for. */
241 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
243 /* Masks to determine which reciprocal esitmate instructions to generate
245 enum rs6000_recip_mask
{
246 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
247 RECIP_DF_DIV
= 0x002,
248 RECIP_V4SF_DIV
= 0x004,
249 RECIP_V2DF_DIV
= 0x008,
251 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
252 RECIP_DF_RSQRT
= 0x020,
253 RECIP_V4SF_RSQRT
= 0x040,
254 RECIP_V2DF_RSQRT
= 0x080,
256 /* Various combination of flags for -mrecip=xxx. */
258 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
259 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
260 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
262 RECIP_HIGH_PRECISION
= RECIP_ALL
,
264 /* On low precision machines like the power5, don't enable double precision
265 reciprocal square root estimate, since it isn't accurate enough. */
266 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
269 /* -mrecip options. */
272 const char *string
; /* option name */
273 unsigned int mask
; /* mask bits to set */
274 } recip_options
[] = {
275 { "all", RECIP_ALL
},
276 { "none", RECIP_NONE
},
277 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
279 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
280 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
281 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
282 | RECIP_V2DF_RSQRT
) },
283 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
284 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
287 /* 2 argument gen function typedef. */
288 typedef rtx (*gen_2arg_fn_t
) (rtx
, rtx
, rtx
);
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291 macros that have changed. Languages that don't support the preprocessor
292 don't link in rs6000-c.c, so we can't call it directly. */
293 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
295 /* Simplfy register classes into simpler classifications. We assume
296 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
297 check for standard register classes (gpr/floating/altivec/vsx) and
298 floating/vector classes (float/altivec/vsx). */
300 enum rs6000_reg_type
{
313 /* Map register class to register type. */
314 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
316 /* First/last register type for the 'normal' register types (i.e. general
317 purpose, floating point, altivec, and VSX registers). */
318 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
320 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
322 /* Direct moves to/from vsx/gpr registers that need an additional register to
324 static enum insn_code reload_fpr_gpr
[NUM_MACHINE_MODES
];
325 static enum insn_code reload_gpr_vsx
[NUM_MACHINE_MODES
];
326 static enum insn_code reload_vsx_gpr
[NUM_MACHINE_MODES
];
329 /* Target cpu costs. */
331 struct processor_costs
{
332 const int mulsi
; /* cost of SImode multiplication. */
333 const int mulsi_const
; /* cost of SImode multiplication by constant. */
334 const int mulsi_const9
; /* cost of SImode mult by short constant. */
335 const int muldi
; /* cost of DImode multiplication. */
336 const int divsi
; /* cost of SImode division. */
337 const int divdi
; /* cost of DImode division. */
338 const int fp
; /* cost of simple SFmode and DFmode insns. */
339 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
340 const int sdiv
; /* cost of SFmode division (fdivs). */
341 const int ddiv
; /* cost of DFmode division (fdiv). */
342 const int cache_line_size
; /* cache line size in bytes. */
343 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
344 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
345 const int simultaneous_prefetches
; /* number of parallel prefetch
349 const struct processor_costs
*rs6000_cost
;
351 /* Processor costs (relative to an add) */
353 /* Instruction size costs on 32bit processors. */
355 struct processor_costs size32_cost
= {
356 COSTS_N_INSNS (1), /* mulsi */
357 COSTS_N_INSNS (1), /* mulsi_const */
358 COSTS_N_INSNS (1), /* mulsi_const9 */
359 COSTS_N_INSNS (1), /* muldi */
360 COSTS_N_INSNS (1), /* divsi */
361 COSTS_N_INSNS (1), /* divdi */
362 COSTS_N_INSNS (1), /* fp */
363 COSTS_N_INSNS (1), /* dmul */
364 COSTS_N_INSNS (1), /* sdiv */
365 COSTS_N_INSNS (1), /* ddiv */
372 /* Instruction size costs on 64bit processors. */
374 struct processor_costs size64_cost
= {
375 COSTS_N_INSNS (1), /* mulsi */
376 COSTS_N_INSNS (1), /* mulsi_const */
377 COSTS_N_INSNS (1), /* mulsi_const9 */
378 COSTS_N_INSNS (1), /* muldi */
379 COSTS_N_INSNS (1), /* divsi */
380 COSTS_N_INSNS (1), /* divdi */
381 COSTS_N_INSNS (1), /* fp */
382 COSTS_N_INSNS (1), /* dmul */
383 COSTS_N_INSNS (1), /* sdiv */
384 COSTS_N_INSNS (1), /* ddiv */
391 /* Instruction costs on RS64A processors. */
393 struct processor_costs rs64a_cost
= {
394 COSTS_N_INSNS (20), /* mulsi */
395 COSTS_N_INSNS (12), /* mulsi_const */
396 COSTS_N_INSNS (8), /* mulsi_const9 */
397 COSTS_N_INSNS (34), /* muldi */
398 COSTS_N_INSNS (65), /* divsi */
399 COSTS_N_INSNS (67), /* divdi */
400 COSTS_N_INSNS (4), /* fp */
401 COSTS_N_INSNS (4), /* dmul */
402 COSTS_N_INSNS (31), /* sdiv */
403 COSTS_N_INSNS (31), /* ddiv */
404 128, /* cache line size */
410 /* Instruction costs on MPCCORE processors. */
412 struct processor_costs mpccore_cost
= {
413 COSTS_N_INSNS (2), /* mulsi */
414 COSTS_N_INSNS (2), /* mulsi_const */
415 COSTS_N_INSNS (2), /* mulsi_const9 */
416 COSTS_N_INSNS (2), /* muldi */
417 COSTS_N_INSNS (6), /* divsi */
418 COSTS_N_INSNS (6), /* divdi */
419 COSTS_N_INSNS (4), /* fp */
420 COSTS_N_INSNS (5), /* dmul */
421 COSTS_N_INSNS (10), /* sdiv */
422 COSTS_N_INSNS (17), /* ddiv */
423 32, /* cache line size */
429 /* Instruction costs on PPC403 processors. */
431 struct processor_costs ppc403_cost
= {
432 COSTS_N_INSNS (4), /* mulsi */
433 COSTS_N_INSNS (4), /* mulsi_const */
434 COSTS_N_INSNS (4), /* mulsi_const9 */
435 COSTS_N_INSNS (4), /* muldi */
436 COSTS_N_INSNS (33), /* divsi */
437 COSTS_N_INSNS (33), /* divdi */
438 COSTS_N_INSNS (11), /* fp */
439 COSTS_N_INSNS (11), /* dmul */
440 COSTS_N_INSNS (11), /* sdiv */
441 COSTS_N_INSNS (11), /* ddiv */
442 32, /* cache line size */
448 /* Instruction costs on PPC405 processors. */
450 struct processor_costs ppc405_cost
= {
451 COSTS_N_INSNS (5), /* mulsi */
452 COSTS_N_INSNS (4), /* mulsi_const */
453 COSTS_N_INSNS (3), /* mulsi_const9 */
454 COSTS_N_INSNS (5), /* muldi */
455 COSTS_N_INSNS (35), /* divsi */
456 COSTS_N_INSNS (35), /* divdi */
457 COSTS_N_INSNS (11), /* fp */
458 COSTS_N_INSNS (11), /* dmul */
459 COSTS_N_INSNS (11), /* sdiv */
460 COSTS_N_INSNS (11), /* ddiv */
461 32, /* cache line size */
467 /* Instruction costs on PPC440 processors. */
469 struct processor_costs ppc440_cost
= {
470 COSTS_N_INSNS (3), /* mulsi */
471 COSTS_N_INSNS (2), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (3), /* muldi */
474 COSTS_N_INSNS (34), /* divsi */
475 COSTS_N_INSNS (34), /* divdi */
476 COSTS_N_INSNS (5), /* fp */
477 COSTS_N_INSNS (5), /* dmul */
478 COSTS_N_INSNS (19), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
480 32, /* cache line size */
486 /* Instruction costs on PPC476 processors. */
488 struct processor_costs ppc476_cost
= {
489 COSTS_N_INSNS (4), /* mulsi */
490 COSTS_N_INSNS (4), /* mulsi_const */
491 COSTS_N_INSNS (4), /* mulsi_const9 */
492 COSTS_N_INSNS (4), /* muldi */
493 COSTS_N_INSNS (11), /* divsi */
494 COSTS_N_INSNS (11), /* divdi */
495 COSTS_N_INSNS (6), /* fp */
496 COSTS_N_INSNS (6), /* dmul */
497 COSTS_N_INSNS (19), /* sdiv */
498 COSTS_N_INSNS (33), /* ddiv */
499 32, /* l1 cache line size */
505 /* Instruction costs on PPC601 processors. */
507 struct processor_costs ppc601_cost
= {
508 COSTS_N_INSNS (5), /* mulsi */
509 COSTS_N_INSNS (5), /* mulsi_const */
510 COSTS_N_INSNS (5), /* mulsi_const9 */
511 COSTS_N_INSNS (5), /* muldi */
512 COSTS_N_INSNS (36), /* divsi */
513 COSTS_N_INSNS (36), /* divdi */
514 COSTS_N_INSNS (4), /* fp */
515 COSTS_N_INSNS (5), /* dmul */
516 COSTS_N_INSNS (17), /* sdiv */
517 COSTS_N_INSNS (31), /* ddiv */
518 32, /* cache line size */
524 /* Instruction costs on PPC603 processors. */
526 struct processor_costs ppc603_cost
= {
527 COSTS_N_INSNS (5), /* mulsi */
528 COSTS_N_INSNS (3), /* mulsi_const */
529 COSTS_N_INSNS (2), /* mulsi_const9 */
530 COSTS_N_INSNS (5), /* muldi */
531 COSTS_N_INSNS (37), /* divsi */
532 COSTS_N_INSNS (37), /* divdi */
533 COSTS_N_INSNS (3), /* fp */
534 COSTS_N_INSNS (4), /* dmul */
535 COSTS_N_INSNS (18), /* sdiv */
536 COSTS_N_INSNS (33), /* ddiv */
537 32, /* cache line size */
543 /* Instruction costs on PPC604 processors. */
545 struct processor_costs ppc604_cost
= {
546 COSTS_N_INSNS (4), /* mulsi */
547 COSTS_N_INSNS (4), /* mulsi_const */
548 COSTS_N_INSNS (4), /* mulsi_const9 */
549 COSTS_N_INSNS (4), /* muldi */
550 COSTS_N_INSNS (20), /* divsi */
551 COSTS_N_INSNS (20), /* divdi */
552 COSTS_N_INSNS (3), /* fp */
553 COSTS_N_INSNS (3), /* dmul */
554 COSTS_N_INSNS (18), /* sdiv */
555 COSTS_N_INSNS (32), /* ddiv */
556 32, /* cache line size */
562 /* Instruction costs on PPC604e processors. */
564 struct processor_costs ppc604e_cost
= {
565 COSTS_N_INSNS (2), /* mulsi */
566 COSTS_N_INSNS (2), /* mulsi_const */
567 COSTS_N_INSNS (2), /* mulsi_const9 */
568 COSTS_N_INSNS (2), /* muldi */
569 COSTS_N_INSNS (20), /* divsi */
570 COSTS_N_INSNS (20), /* divdi */
571 COSTS_N_INSNS (3), /* fp */
572 COSTS_N_INSNS (3), /* dmul */
573 COSTS_N_INSNS (18), /* sdiv */
574 COSTS_N_INSNS (32), /* ddiv */
575 32, /* cache line size */
581 /* Instruction costs on PPC620 processors. */
583 struct processor_costs ppc620_cost
= {
584 COSTS_N_INSNS (5), /* mulsi */
585 COSTS_N_INSNS (4), /* mulsi_const */
586 COSTS_N_INSNS (3), /* mulsi_const9 */
587 COSTS_N_INSNS (7), /* muldi */
588 COSTS_N_INSNS (21), /* divsi */
589 COSTS_N_INSNS (37), /* divdi */
590 COSTS_N_INSNS (3), /* fp */
591 COSTS_N_INSNS (3), /* dmul */
592 COSTS_N_INSNS (18), /* sdiv */
593 COSTS_N_INSNS (32), /* ddiv */
594 128, /* cache line size */
600 /* Instruction costs on PPC630 processors. */
602 struct processor_costs ppc630_cost
= {
603 COSTS_N_INSNS (5), /* mulsi */
604 COSTS_N_INSNS (4), /* mulsi_const */
605 COSTS_N_INSNS (3), /* mulsi_const9 */
606 COSTS_N_INSNS (7), /* muldi */
607 COSTS_N_INSNS (21), /* divsi */
608 COSTS_N_INSNS (37), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (17), /* sdiv */
612 COSTS_N_INSNS (21), /* ddiv */
613 128, /* cache line size */
619 /* Instruction costs on Cell processor. */
620 /* COSTS_N_INSNS (1) ~ one add. */
622 struct processor_costs ppccell_cost
= {
623 COSTS_N_INSNS (9/2)+2, /* mulsi */
624 COSTS_N_INSNS (6/2), /* mulsi_const */
625 COSTS_N_INSNS (6/2), /* mulsi_const9 */
626 COSTS_N_INSNS (15/2)+2, /* muldi */
627 COSTS_N_INSNS (38/2), /* divsi */
628 COSTS_N_INSNS (70/2), /* divdi */
629 COSTS_N_INSNS (10/2), /* fp */
630 COSTS_N_INSNS (10/2), /* dmul */
631 COSTS_N_INSNS (74/2), /* sdiv */
632 COSTS_N_INSNS (74/2), /* ddiv */
633 128, /* cache line size */
639 /* Instruction costs on PPC750 and PPC7400 processors. */
641 struct processor_costs ppc750_cost
= {
642 COSTS_N_INSNS (5), /* mulsi */
643 COSTS_N_INSNS (3), /* mulsi_const */
644 COSTS_N_INSNS (2), /* mulsi_const9 */
645 COSTS_N_INSNS (5), /* muldi */
646 COSTS_N_INSNS (17), /* divsi */
647 COSTS_N_INSNS (17), /* divdi */
648 COSTS_N_INSNS (3), /* fp */
649 COSTS_N_INSNS (3), /* dmul */
650 COSTS_N_INSNS (17), /* sdiv */
651 COSTS_N_INSNS (31), /* ddiv */
652 32, /* cache line size */
658 /* Instruction costs on PPC7450 processors. */
660 struct processor_costs ppc7450_cost
= {
661 COSTS_N_INSNS (4), /* mulsi */
662 COSTS_N_INSNS (3), /* mulsi_const */
663 COSTS_N_INSNS (3), /* mulsi_const9 */
664 COSTS_N_INSNS (4), /* muldi */
665 COSTS_N_INSNS (23), /* divsi */
666 COSTS_N_INSNS (23), /* divdi */
667 COSTS_N_INSNS (5), /* fp */
668 COSTS_N_INSNS (5), /* dmul */
669 COSTS_N_INSNS (21), /* sdiv */
670 COSTS_N_INSNS (35), /* ddiv */
671 32, /* cache line size */
677 /* Instruction costs on PPC8540 processors. */
679 struct processor_costs ppc8540_cost
= {
680 COSTS_N_INSNS (4), /* mulsi */
681 COSTS_N_INSNS (4), /* mulsi_const */
682 COSTS_N_INSNS (4), /* mulsi_const9 */
683 COSTS_N_INSNS (4), /* muldi */
684 COSTS_N_INSNS (19), /* divsi */
685 COSTS_N_INSNS (19), /* divdi */
686 COSTS_N_INSNS (4), /* fp */
687 COSTS_N_INSNS (4), /* dmul */
688 COSTS_N_INSNS (29), /* sdiv */
689 COSTS_N_INSNS (29), /* ddiv */
690 32, /* cache line size */
693 1, /* prefetch streams /*/
696 /* Instruction costs on E300C2 and E300C3 cores. */
698 struct processor_costs ppce300c2c3_cost
= {
699 COSTS_N_INSNS (4), /* mulsi */
700 COSTS_N_INSNS (4), /* mulsi_const */
701 COSTS_N_INSNS (4), /* mulsi_const9 */
702 COSTS_N_INSNS (4), /* muldi */
703 COSTS_N_INSNS (19), /* divsi */
704 COSTS_N_INSNS (19), /* divdi */
705 COSTS_N_INSNS (3), /* fp */
706 COSTS_N_INSNS (4), /* dmul */
707 COSTS_N_INSNS (18), /* sdiv */
708 COSTS_N_INSNS (33), /* ddiv */
712 1, /* prefetch streams /*/
715 /* Instruction costs on PPCE500MC processors. */
717 struct processor_costs ppce500mc_cost
= {
718 COSTS_N_INSNS (4), /* mulsi */
719 COSTS_N_INSNS (4), /* mulsi_const */
720 COSTS_N_INSNS (4), /* mulsi_const9 */
721 COSTS_N_INSNS (4), /* muldi */
722 COSTS_N_INSNS (14), /* divsi */
723 COSTS_N_INSNS (14), /* divdi */
724 COSTS_N_INSNS (8), /* fp */
725 COSTS_N_INSNS (10), /* dmul */
726 COSTS_N_INSNS (36), /* sdiv */
727 COSTS_N_INSNS (66), /* ddiv */
728 64, /* cache line size */
731 1, /* prefetch streams /*/
734 /* Instruction costs on PPCE500MC64 processors. */
736 struct processor_costs ppce500mc64_cost
= {
737 COSTS_N_INSNS (4), /* mulsi */
738 COSTS_N_INSNS (4), /* mulsi_const */
739 COSTS_N_INSNS (4), /* mulsi_const9 */
740 COSTS_N_INSNS (4), /* muldi */
741 COSTS_N_INSNS (14), /* divsi */
742 COSTS_N_INSNS (14), /* divdi */
743 COSTS_N_INSNS (4), /* fp */
744 COSTS_N_INSNS (10), /* dmul */
745 COSTS_N_INSNS (36), /* sdiv */
746 COSTS_N_INSNS (66), /* ddiv */
747 64, /* cache line size */
750 1, /* prefetch streams /*/
753 /* Instruction costs on PPCE5500 processors. */
755 struct processor_costs ppce5500_cost
= {
756 COSTS_N_INSNS (5), /* mulsi */
757 COSTS_N_INSNS (5), /* mulsi_const */
758 COSTS_N_INSNS (4), /* mulsi_const9 */
759 COSTS_N_INSNS (5), /* muldi */
760 COSTS_N_INSNS (14), /* divsi */
761 COSTS_N_INSNS (14), /* divdi */
762 COSTS_N_INSNS (7), /* fp */
763 COSTS_N_INSNS (10), /* dmul */
764 COSTS_N_INSNS (36), /* sdiv */
765 COSTS_N_INSNS (66), /* ddiv */
766 64, /* cache line size */
769 1, /* prefetch streams /*/
772 /* Instruction costs on PPCE6500 processors. */
774 struct processor_costs ppce6500_cost
= {
775 COSTS_N_INSNS (5), /* mulsi */
776 COSTS_N_INSNS (5), /* mulsi_const */
777 COSTS_N_INSNS (4), /* mulsi_const9 */
778 COSTS_N_INSNS (5), /* muldi */
779 COSTS_N_INSNS (14), /* divsi */
780 COSTS_N_INSNS (14), /* divdi */
781 COSTS_N_INSNS (7), /* fp */
782 COSTS_N_INSNS (10), /* dmul */
783 COSTS_N_INSNS (36), /* sdiv */
784 COSTS_N_INSNS (66), /* ddiv */
785 64, /* cache line size */
788 1, /* prefetch streams /*/
791 /* Instruction costs on AppliedMicro Titan processors. */
793 struct processor_costs titan_cost
= {
794 COSTS_N_INSNS (5), /* mulsi */
795 COSTS_N_INSNS (5), /* mulsi_const */
796 COSTS_N_INSNS (5), /* mulsi_const9 */
797 COSTS_N_INSNS (5), /* muldi */
798 COSTS_N_INSNS (18), /* divsi */
799 COSTS_N_INSNS (18), /* divdi */
800 COSTS_N_INSNS (10), /* fp */
801 COSTS_N_INSNS (10), /* dmul */
802 COSTS_N_INSNS (46), /* sdiv */
803 COSTS_N_INSNS (72), /* ddiv */
804 32, /* cache line size */
807 1, /* prefetch streams /*/
810 /* Instruction costs on POWER4 and POWER5 processors. */
812 struct processor_costs power4_cost
= {
813 COSTS_N_INSNS (3), /* mulsi */
814 COSTS_N_INSNS (2), /* mulsi_const */
815 COSTS_N_INSNS (2), /* mulsi_const9 */
816 COSTS_N_INSNS (4), /* muldi */
817 COSTS_N_INSNS (18), /* divsi */
818 COSTS_N_INSNS (34), /* divdi */
819 COSTS_N_INSNS (3), /* fp */
820 COSTS_N_INSNS (3), /* dmul */
821 COSTS_N_INSNS (17), /* sdiv */
822 COSTS_N_INSNS (17), /* ddiv */
823 128, /* cache line size */
826 8, /* prefetch streams /*/
829 /* Instruction costs on POWER6 processors. */
831 struct processor_costs power6_cost
= {
832 COSTS_N_INSNS (8), /* mulsi */
833 COSTS_N_INSNS (8), /* mulsi_const */
834 COSTS_N_INSNS (8), /* mulsi_const9 */
835 COSTS_N_INSNS (8), /* muldi */
836 COSTS_N_INSNS (22), /* divsi */
837 COSTS_N_INSNS (28), /* divdi */
838 COSTS_N_INSNS (3), /* fp */
839 COSTS_N_INSNS (3), /* dmul */
840 COSTS_N_INSNS (13), /* sdiv */
841 COSTS_N_INSNS (16), /* ddiv */
842 128, /* cache line size */
845 16, /* prefetch streams */
848 /* Instruction costs on POWER7 processors. */
850 struct processor_costs power7_cost
= {
851 COSTS_N_INSNS (2), /* mulsi */
852 COSTS_N_INSNS (2), /* mulsi_const */
853 COSTS_N_INSNS (2), /* mulsi_const9 */
854 COSTS_N_INSNS (2), /* muldi */
855 COSTS_N_INSNS (18), /* divsi */
856 COSTS_N_INSNS (34), /* divdi */
857 COSTS_N_INSNS (3), /* fp */
858 COSTS_N_INSNS (3), /* dmul */
859 COSTS_N_INSNS (13), /* sdiv */
860 COSTS_N_INSNS (16), /* ddiv */
861 128, /* cache line size */
864 12, /* prefetch streams */
867 /* Instruction costs on POWER8 processors. */
869 struct processor_costs power8_cost
= {
870 COSTS_N_INSNS (3), /* mulsi */
871 COSTS_N_INSNS (3), /* mulsi_const */
872 COSTS_N_INSNS (3), /* mulsi_const9 */
873 COSTS_N_INSNS (3), /* muldi */
874 COSTS_N_INSNS (19), /* divsi */
875 COSTS_N_INSNS (35), /* divdi */
876 COSTS_N_INSNS (3), /* fp */
877 COSTS_N_INSNS (3), /* dmul */
878 COSTS_N_INSNS (14), /* sdiv */
879 COSTS_N_INSNS (17), /* ddiv */
880 128, /* cache line size */
883 12, /* prefetch streams */
886 /* Instruction costs on POWER A2 processors. */
888 struct processor_costs ppca2_cost
= {
889 COSTS_N_INSNS (16), /* mulsi */
890 COSTS_N_INSNS (16), /* mulsi_const */
891 COSTS_N_INSNS (16), /* mulsi_const9 */
892 COSTS_N_INSNS (16), /* muldi */
893 COSTS_N_INSNS (22), /* divsi */
894 COSTS_N_INSNS (28), /* divdi */
895 COSTS_N_INSNS (3), /* fp */
896 COSTS_N_INSNS (3), /* dmul */
897 COSTS_N_INSNS (59), /* sdiv */
898 COSTS_N_INSNS (72), /* ddiv */
902 16, /* prefetch streams */
906 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
907 #undef RS6000_BUILTIN_1
908 #undef RS6000_BUILTIN_2
909 #undef RS6000_BUILTIN_3
910 #undef RS6000_BUILTIN_A
911 #undef RS6000_BUILTIN_D
912 #undef RS6000_BUILTIN_E
913 #undef RS6000_BUILTIN_H
914 #undef RS6000_BUILTIN_P
915 #undef RS6000_BUILTIN_Q
916 #undef RS6000_BUILTIN_S
917 #undef RS6000_BUILTIN_X
919 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
920 { NAME, ICODE, MASK, ATTR },
922 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
923 { NAME, ICODE, MASK, ATTR },
925 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
926 { NAME, ICODE, MASK, ATTR },
928 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
929 { NAME, ICODE, MASK, ATTR },
931 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
932 { NAME, ICODE, MASK, ATTR },
934 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
935 { NAME, ICODE, MASK, ATTR },
937 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
938 { NAME, ICODE, MASK, ATTR },
940 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
941 { NAME, ICODE, MASK, ATTR },
943 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
944 { NAME, ICODE, MASK, ATTR },
946 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
947 { NAME, ICODE, MASK, ATTR },
949 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
950 { NAME, ICODE, MASK, ATTR },
952 struct rs6000_builtin_info_type
{
954 const enum insn_code icode
;
955 const HOST_WIDE_INT mask
;
959 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
961 #include "rs6000-builtin.def"
964 #undef RS6000_BUILTIN_1
965 #undef RS6000_BUILTIN_2
966 #undef RS6000_BUILTIN_3
967 #undef RS6000_BUILTIN_A
968 #undef RS6000_BUILTIN_D
969 #undef RS6000_BUILTIN_E
970 #undef RS6000_BUILTIN_H
971 #undef RS6000_BUILTIN_P
972 #undef RS6000_BUILTIN_Q
973 #undef RS6000_BUILTIN_S
974 #undef RS6000_BUILTIN_X
976 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
977 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
980 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
981 static bool spe_func_has_64bit_regs_p (void);
982 static struct machine_function
* rs6000_init_machine_status (void);
983 static int rs6000_ra_ever_killed (void);
984 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
985 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
986 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
987 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
988 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
989 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
990 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
991 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
993 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
994 static bool is_microcoded_insn (rtx
);
995 static bool is_nonpipeline_insn (rtx
);
996 static bool is_cracked_insn (rtx
);
997 static bool is_load_insn (rtx
, rtx
*);
998 static bool is_store_insn (rtx
, rtx
*);
999 static bool set_to_load_agen (rtx
,rtx
);
1000 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1001 static bool insn_must_be_first_in_group (rtx
);
1002 static bool insn_must_be_last_in_group (rtx
);
1003 static void altivec_init_builtins (void);
1004 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1005 enum machine_mode
, enum machine_mode
,
1006 enum rs6000_builtins
, const char *name
);
1007 static void rs6000_common_init_builtins (void);
1008 static void paired_init_builtins (void);
1009 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1010 static void spe_init_builtins (void);
1011 static void htm_init_builtins (void);
1012 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1013 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1014 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1015 static rs6000_stack_t
*rs6000_stack_info (void);
1016 static void is_altivec_return_reg (rtx
, void *);
1017 int easy_vector_constant (rtx
, enum machine_mode
);
1018 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1019 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1020 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1021 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1022 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1025 static void macho_branch_islands (void);
1027 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1029 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1031 static bool rs6000_mode_dependent_address (const_rtx
);
1032 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1033 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1034 enum machine_mode
, rtx
);
1035 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1038 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1039 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1041 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1043 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1046 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1049 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1052 static bool rs6000_save_toc_in_prologue_p (void);
1054 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1056 = rs6000_legitimize_reload_address
;
1058 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1059 = rs6000_mode_dependent_address
;
1061 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1062 enum machine_mode
, rtx
)
1063 = rs6000_secondary_reload_class
;
1065 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1066 = rs6000_preferred_reload_class
;
1068 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1070 = rs6000_secondary_memory_needed
;
1072 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1075 = rs6000_cannot_change_mode_class
;
1077 const int INSN_NOT_AVAILABLE
= -1;
1079 static void rs6000_print_isa_options (FILE *, int, const char *,
1081 static void rs6000_print_builtin_options (FILE *, int, const char *,
1084 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1085 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1086 enum rs6000_reg_type
,
1088 secondary_reload_info
*,
1091 /* Hash table stuff for keeping track of TOC entries. */
1093 struct GTY(()) toc_hash_struct
1095 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1096 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1098 enum machine_mode key_mode
;
1102 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1104 /* Hash table to keep track of the argument types for builtin functions. */
1106 struct GTY(()) builtin_hash_struct
1109 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1110 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1113 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1116 /* Default register names. */
1117 char rs6000_reg_names
[][8] =
1119 "0", "1", "2", "3", "4", "5", "6", "7",
1120 "8", "9", "10", "11", "12", "13", "14", "15",
1121 "16", "17", "18", "19", "20", "21", "22", "23",
1122 "24", "25", "26", "27", "28", "29", "30", "31",
1123 "0", "1", "2", "3", "4", "5", "6", "7",
1124 "8", "9", "10", "11", "12", "13", "14", "15",
1125 "16", "17", "18", "19", "20", "21", "22", "23",
1126 "24", "25", "26", "27", "28", "29", "30", "31",
1127 "mq", "lr", "ctr","ap",
1128 "0", "1", "2", "3", "4", "5", "6", "7",
1130 /* AltiVec registers. */
1131 "0", "1", "2", "3", "4", "5", "6", "7",
1132 "8", "9", "10", "11", "12", "13", "14", "15",
1133 "16", "17", "18", "19", "20", "21", "22", "23",
1134 "24", "25", "26", "27", "28", "29", "30", "31",
1136 /* SPE registers. */
1137 "spe_acc", "spefscr",
1138 /* Soft frame pointer. */
1140 /* HTM SPR registers. */
1141 "tfhar", "tfiar", "texasr"
1144 #ifdef TARGET_REGNAMES
1145 static const char alt_reg_names
[][8] =
1147 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1148 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1149 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1150 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1151 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1152 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1153 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1154 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1155 "mq", "lr", "ctr", "ap",
1156 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1158 /* AltiVec registers. */
1159 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1160 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1161 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1162 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1164 /* SPE registers. */
1165 "spe_acc", "spefscr",
1166 /* Soft frame pointer. */
1168 /* HTM SPR registers. */
1169 "tfhar", "tfiar", "texasr"
1173 /* Table of valid machine attributes. */
1175 static const struct attribute_spec rs6000_attribute_table
[] =
1177 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1178 affects_type_identity } */
1179 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1181 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1183 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1185 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1187 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1189 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1190 SUBTARGET_ATTRIBUTE_TABLE
,
1192 { NULL
, 0, 0, false, false, false, NULL
, false }
1195 #ifndef TARGET_PROFILE_KERNEL
1196 #define TARGET_PROFILE_KERNEL 0
1199 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1200 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1202 /* Initialize the GCC target structure. */
1203 #undef TARGET_ATTRIBUTE_TABLE
1204 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1205 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1206 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1207 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1208 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1210 #undef TARGET_ASM_ALIGNED_DI_OP
1211 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1213 /* Default unaligned ops are only provided for ELF. Find the ops needed
1214 for non-ELF systems. */
1215 #ifndef OBJECT_FORMAT_ELF
1217 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1219 #undef TARGET_ASM_UNALIGNED_HI_OP
1220 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1221 #undef TARGET_ASM_UNALIGNED_SI_OP
1222 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1223 #undef TARGET_ASM_UNALIGNED_DI_OP
1224 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1227 #undef TARGET_ASM_UNALIGNED_HI_OP
1228 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1229 #undef TARGET_ASM_UNALIGNED_SI_OP
1230 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1231 #undef TARGET_ASM_UNALIGNED_DI_OP
1232 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1233 #undef TARGET_ASM_ALIGNED_DI_OP
1234 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1238 /* This hook deals with fixups for relocatable code and DI-mode objects
1240 #undef TARGET_ASM_INTEGER
1241 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1243 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1244 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1245 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1248 #undef TARGET_SET_UP_BY_PROLOGUE
1249 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1251 #undef TARGET_HAVE_TLS
1252 #define TARGET_HAVE_TLS HAVE_AS_TLS
1254 #undef TARGET_CANNOT_FORCE_CONST_MEM
1255 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1257 #undef TARGET_DELEGITIMIZE_ADDRESS
1258 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1260 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1261 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1263 #undef TARGET_ASM_FUNCTION_PROLOGUE
1264 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1265 #undef TARGET_ASM_FUNCTION_EPILOGUE
1266 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1268 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1269 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1271 #undef TARGET_LEGITIMIZE_ADDRESS
1272 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1274 #undef TARGET_SCHED_VARIABLE_ISSUE
1275 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1277 #undef TARGET_SCHED_ISSUE_RATE
1278 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1279 #undef TARGET_SCHED_ADJUST_COST
1280 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1281 #undef TARGET_SCHED_ADJUST_PRIORITY
1282 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1283 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1284 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1285 #undef TARGET_SCHED_INIT
1286 #define TARGET_SCHED_INIT rs6000_sched_init
1287 #undef TARGET_SCHED_FINISH
1288 #define TARGET_SCHED_FINISH rs6000_sched_finish
1289 #undef TARGET_SCHED_REORDER
1290 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1291 #undef TARGET_SCHED_REORDER2
1292 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1294 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1295 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1297 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1298 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1300 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1301 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1302 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1303 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1304 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1305 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1306 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1307 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1309 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1310 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1311 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1312 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1313 rs6000_builtin_support_vector_misalignment
1314 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1315 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1316 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1317 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1318 rs6000_builtin_vectorization_cost
1319 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1320 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1321 rs6000_preferred_simd_mode
1322 #undef TARGET_VECTORIZE_INIT_COST
1323 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1324 #undef TARGET_VECTORIZE_ADD_STMT_COST
1325 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1326 #undef TARGET_VECTORIZE_FINISH_COST
1327 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1328 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1329 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1331 #undef TARGET_INIT_BUILTINS
1332 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1333 #undef TARGET_BUILTIN_DECL
1334 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1336 #undef TARGET_EXPAND_BUILTIN
1337 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1339 #undef TARGET_MANGLE_TYPE
1340 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1342 #undef TARGET_INIT_LIBFUNCS
1343 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1346 #undef TARGET_BINDS_LOCAL_P
1347 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1350 #undef TARGET_MS_BITFIELD_LAYOUT_P
1351 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1353 #undef TARGET_ASM_OUTPUT_MI_THUNK
1354 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1356 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1357 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1359 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1360 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1362 #undef TARGET_REGISTER_MOVE_COST
1363 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1364 #undef TARGET_MEMORY_MOVE_COST
1365 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1366 #undef TARGET_RTX_COSTS
1367 #define TARGET_RTX_COSTS rs6000_rtx_costs
1368 #undef TARGET_ADDRESS_COST
1369 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1371 #undef TARGET_DWARF_REGISTER_SPAN
1372 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1374 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1375 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1377 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1378 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1380 /* On rs6000, function arguments are promoted, as are function return
1382 #undef TARGET_PROMOTE_FUNCTION_MODE
1383 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1385 #undef TARGET_RETURN_IN_MEMORY
1386 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1388 #undef TARGET_SETUP_INCOMING_VARARGS
1389 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1391 /* Always strict argument naming on rs6000. */
1392 #undef TARGET_STRICT_ARGUMENT_NAMING
1393 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1394 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1395 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1396 #undef TARGET_SPLIT_COMPLEX_ARG
1397 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1398 #undef TARGET_MUST_PASS_IN_STACK
1399 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1400 #undef TARGET_PASS_BY_REFERENCE
1401 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1402 #undef TARGET_ARG_PARTIAL_BYTES
1403 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1404 #undef TARGET_FUNCTION_ARG_ADVANCE
1405 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1406 #undef TARGET_FUNCTION_ARG
1407 #define TARGET_FUNCTION_ARG rs6000_function_arg
1408 #undef TARGET_FUNCTION_ARG_BOUNDARY
1409 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1411 #undef TARGET_BUILD_BUILTIN_VA_LIST
1412 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1414 #undef TARGET_EXPAND_BUILTIN_VA_START
1415 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1417 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1418 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1420 #undef TARGET_EH_RETURN_FILTER_MODE
1421 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1423 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1424 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1426 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1427 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1429 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1430 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1432 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1433 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1435 #undef TARGET_OPTION_OVERRIDE
1436 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1438 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1439 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1440 rs6000_builtin_vectorized_function
1443 #undef TARGET_STACK_PROTECT_FAIL
1444 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1447 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1448 The PowerPC architecture requires only weak consistency among
1449 processors--that is, memory accesses between processors need not be
1450 sequentially consistent and memory accesses among processors can occur
1451 in any order. The ability to order memory accesses weakly provides
1452 opportunities for more efficient use of the system bus. Unless a
1453 dependency exists, the 604e allows read operations to precede store
1455 #undef TARGET_RELAXED_ORDERING
1456 #define TARGET_RELAXED_ORDERING true
1459 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1460 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1463 /* Use a 32-bit anchor range. This leads to sequences like:
1465 addis tmp,anchor,high
1468 where tmp itself acts as an anchor, and can be shared between
1469 accesses to the same 64k page. */
1470 #undef TARGET_MIN_ANCHOR_OFFSET
1471 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1472 #undef TARGET_MAX_ANCHOR_OFFSET
1473 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1474 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1475 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1476 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1477 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1479 #undef TARGET_BUILTIN_RECIPROCAL
1480 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1482 #undef TARGET_EXPAND_TO_RTL_HOOK
1483 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1485 #undef TARGET_INSTANTIATE_DECLS
1486 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1488 #undef TARGET_SECONDARY_RELOAD
1489 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1491 #undef TARGET_LEGITIMATE_ADDRESS_P
1492 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1494 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1495 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1497 #undef TARGET_CAN_ELIMINATE
1498 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1500 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1501 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1503 #undef TARGET_TRAMPOLINE_INIT
1504 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1506 #undef TARGET_FUNCTION_VALUE
1507 #define TARGET_FUNCTION_VALUE rs6000_function_value
1509 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1510 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1512 #undef TARGET_OPTION_SAVE
1513 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1515 #undef TARGET_OPTION_RESTORE
1516 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1518 #undef TARGET_OPTION_PRINT
1519 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1521 #undef TARGET_CAN_INLINE_P
1522 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1524 #undef TARGET_SET_CURRENT_FUNCTION
1525 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1527 #undef TARGET_LEGITIMATE_CONSTANT_P
1528 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1530 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1531 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1534 /* Processor table. */
1537 const char *const name
; /* Canonical processor name. */
1538 const enum processor_type processor
; /* Processor type enum value. */
1539 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1542 static struct rs6000_ptt
const processor_target_table
[] =
1544 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1545 #include "rs6000-cpus.def"
1549 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1553 rs6000_cpu_name_lookup (const char *name
)
1559 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1560 if (! strcmp (name
, processor_target_table
[i
].name
))
1568 /* Return number of consecutive hard regs needed starting at reg REGNO
1569 to hold something of mode MODE.
1570 This is ordinarily the length in words of a value of mode MODE
1571 but can be less for certain modes in special long registers.
1573 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1574 scalar instructions. The upper 32 bits are only available to the
1577 POWER and PowerPC GPRs hold 32 bits worth;
1578 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1581 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1583 unsigned HOST_WIDE_INT reg_size
;
1585 /* TF/TD modes are special in that they always take 2 registers. */
1586 if (FP_REGNO_P (regno
))
1587 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1588 ? UNITS_PER_VSX_WORD
1589 : UNITS_PER_FP_WORD
);
1591 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1592 reg_size
= UNITS_PER_SPE_WORD
;
1594 else if (ALTIVEC_REGNO_P (regno
))
1595 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1597 /* The value returned for SCmode in the E500 double case is 2 for
1598 ABI compatibility; storing an SCmode value in a single register
1599 would require function_arg and rs6000_spe_function_arg to handle
1600 SCmode so as to pass the value correctly in a pair of
1602 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1603 && !DECIMAL_FLOAT_MODE_P (mode
))
1604 reg_size
= UNITS_PER_FP_WORD
;
1607 reg_size
= UNITS_PER_WORD
;
1609 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1612 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1615 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1617 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1619 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1620 register combinations, and use PTImode where we need to deal with quad
1621 word memory operations. Don't allow quad words in the argument or frame
1622 pointer registers, just registers 0..31. */
1623 if (mode
== PTImode
)
1624 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1625 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1626 && ((regno
& 1) == 0));
1628 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1629 implementations. Don't allow an item to be split between a FP register
1630 and an Altivec register. */
1631 if (VECTOR_MEM_VSX_P (mode
))
1633 if (FP_REGNO_P (regno
))
1634 return FP_REGNO_P (last_regno
);
1636 if (ALTIVEC_REGNO_P (regno
))
1637 return ALTIVEC_REGNO_P (last_regno
);
1640 /* Allow TImode in all VSX registers if the user asked for it. */
1641 if (mode
== TImode
&& TARGET_VSX_TIMODE
&& VSX_REGNO_P (regno
))
1644 /* The GPRs can hold any mode, but values bigger than one register
1645 cannot go past R31. */
1646 if (INT_REGNO_P (regno
))
1647 return INT_REGNO_P (last_regno
);
1649 /* The float registers (except for VSX vector modes) can only hold floating
1650 modes and DImode. */
1651 if (FP_REGNO_P (regno
))
1653 if (SCALAR_FLOAT_MODE_P (mode
)
1654 && (mode
!= TDmode
|| (regno
% 2) == 0)
1655 && FP_REGNO_P (last_regno
))
1658 if (GET_MODE_CLASS (mode
) == MODE_INT
1659 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1662 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1663 && PAIRED_VECTOR_MODE (mode
))
1669 /* The CR register can only hold CC modes. */
1670 if (CR_REGNO_P (regno
))
1671 return GET_MODE_CLASS (mode
) == MODE_CC
;
1673 if (CA_REGNO_P (regno
))
1674 return mode
== BImode
;
1676 /* AltiVec only in AldyVec registers. */
1677 if (ALTIVEC_REGNO_P (regno
))
1678 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1680 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1681 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1684 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1685 and it must be able to fit within the register set. */
1687 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1690 /* Print interesting facts about registers. */
1692 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1696 for (r
= first_regno
; r
<= last_regno
; ++r
)
1698 const char *comma
= "";
1701 if (first_regno
== last_regno
)
1702 fprintf (stderr
, "%s:\t", reg_name
);
1704 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1707 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1708 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1712 fprintf (stderr
, ",\n\t");
1717 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1718 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1719 rs6000_hard_regno_nregs
[m
][r
]);
1721 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1726 if (call_used_regs
[r
])
1730 fprintf (stderr
, ",\n\t");
1735 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1743 fprintf (stderr
, ",\n\t");
1748 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1754 fprintf (stderr
, ",\n\t");
1758 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1759 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1764 fprintf (stderr
, ",\n\t");
1768 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1772 #define DEBUG_FMT_ID "%-32s= "
1773 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1774 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1775 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1777 /* Print various interesting information with -mdebug=reg. */
1779 rs6000_debug_reg_global (void)
1781 static const char *const tf
[2] = { "false", "true" };
1782 const char *nl
= (const char *)0;
1785 char costly_num
[20];
1787 char flags_buffer
[40];
1788 const char *costly_str
;
1789 const char *nop_str
;
1790 const char *trace_str
;
1791 const char *abi_str
;
1792 const char *cmodel_str
;
1793 struct cl_target_option cl_opts
;
1795 /* Map enum rs6000_vector to string. */
1796 static const char *rs6000_debug_vector_unit
[] = {
1806 /* Modes we want tieable information on. */
1807 static const enum machine_mode print_tieable_modes
[] = {
1841 /* Virtual regs we are interested in. */
1842 const static struct {
1843 int regno
; /* register number. */
1844 const char *name
; /* register name. */
1845 } virtual_regs
[] = {
1846 { STACK_POINTER_REGNUM
, "stack pointer:" },
1847 { TOC_REGNUM
, "toc: " },
1848 { STATIC_CHAIN_REGNUM
, "static chain: " },
1849 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
1850 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
1851 { ARG_POINTER_REGNUM
, "arg pointer: " },
1852 { FRAME_POINTER_REGNUM
, "frame pointer:" },
1853 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
1854 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
1855 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
1856 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
1857 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
1858 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
1859 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
1860 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
1861 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
1864 fputs ("\nHard register information:\n", stderr
);
1865 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
1866 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
1867 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
1870 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
1871 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
1872 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
1873 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
1874 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
1875 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
1876 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
1877 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
1879 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
1880 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
1881 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
1885 "d reg_class = %s\n"
1886 "f reg_class = %s\n"
1887 "v reg_class = %s\n"
1888 "wa reg_class = %s\n"
1889 "wd reg_class = %s\n"
1890 "wf reg_class = %s\n"
1891 "wg reg_class = %s\n"
1892 "wl reg_class = %s\n"
1893 "wm reg_class = %s\n"
1894 "wr reg_class = %s\n"
1895 "ws reg_class = %s\n"
1896 "wt reg_class = %s\n"
1897 "wv reg_class = %s\n"
1898 "wx reg_class = %s\n"
1899 "wz reg_class = %s\n"
1901 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
1902 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
1903 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
1904 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
1905 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
1906 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
1907 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
1908 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
1909 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
1910 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
1911 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
1912 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
1913 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
1914 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
1915 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
1917 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1918 if (rs6000_vector_unit
[m
] || rs6000_vector_mem
[m
]
1919 || (rs6000_vector_reload
[m
][0] != CODE_FOR_nothing
)
1920 || (rs6000_vector_reload
[m
][1] != CODE_FOR_nothing
))
1924 "Vector mode: %-5s arithmetic: %-10s move: %-10s "
1925 "reload-out: %c reload-in: %c\n",
1927 rs6000_debug_vector_unit
[ rs6000_vector_unit
[m
] ],
1928 rs6000_debug_vector_unit
[ rs6000_vector_mem
[m
] ],
1929 (rs6000_vector_reload
[m
][0] != CODE_FOR_nothing
) ? 'y' : 'n',
1930 (rs6000_vector_reload
[m
][1] != CODE_FOR_nothing
) ? 'y' : 'n');
1936 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
1938 enum machine_mode mode1
= print_tieable_modes
[m1
];
1939 bool first_time
= true;
1941 nl
= (const char *)0;
1942 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
1944 enum machine_mode mode2
= print_tieable_modes
[m2
];
1945 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
1949 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
1954 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
1959 fputs ("\n", stderr
);
1965 if (rs6000_recip_control
)
1967 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
1969 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1970 if (rs6000_recip_bits
[m
])
1973 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1975 (RS6000_RECIP_AUTO_RE_P (m
)
1977 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
1978 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
1980 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
1983 fputs ("\n", stderr
);
1986 if (rs6000_cpu_index
>= 0)
1988 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
1990 = processor_target_table
[rs6000_cpu_index
].target_enable
;
1992 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
1993 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
1996 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
1998 if (rs6000_tune_index
>= 0)
2000 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2002 = processor_target_table
[rs6000_tune_index
].target_enable
;
2004 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2005 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2008 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2010 cl_target_option_save (&cl_opts
, &global_options
);
2011 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2014 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2015 rs6000_isa_flags_explicit
);
2017 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2018 rs6000_builtin_mask
);
2020 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2022 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2023 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2025 switch (rs6000_sched_costly_dep
)
2027 case max_dep_latency
:
2028 costly_str
= "max_dep_latency";
2032 costly_str
= "no_dep_costly";
2035 case all_deps_costly
:
2036 costly_str
= "all_deps_costly";
2039 case true_store_to_load_dep_costly
:
2040 costly_str
= "true_store_to_load_dep_costly";
2043 case store_to_load_dep_costly
:
2044 costly_str
= "store_to_load_dep_costly";
2048 costly_str
= costly_num
;
2049 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2053 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2055 switch (rs6000_sched_insert_nops
)
2057 case sched_finish_regroup_exact
:
2058 nop_str
= "sched_finish_regroup_exact";
2061 case sched_finish_pad_groups
:
2062 nop_str
= "sched_finish_pad_groups";
2065 case sched_finish_none
:
2066 nop_str
= "sched_finish_none";
2071 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2075 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2077 switch (rs6000_sdata
)
2084 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2088 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2092 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2097 switch (rs6000_traceback
)
2099 case traceback_default
: trace_str
= "default"; break;
2100 case traceback_none
: trace_str
= "none"; break;
2101 case traceback_part
: trace_str
= "part"; break;
2102 case traceback_full
: trace_str
= "full"; break;
2103 default: trace_str
= "unknown"; break;
2106 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2108 switch (rs6000_current_cmodel
)
2110 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2111 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2112 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2113 default: cmodel_str
= "unknown"; break;
2116 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2118 switch (rs6000_current_abi
)
2120 case ABI_NONE
: abi_str
= "none"; break;
2121 case ABI_AIX
: abi_str
= "aix"; break;
2122 case ABI_V4
: abi_str
= "V4"; break;
2123 case ABI_DARWIN
: abi_str
= "darwin"; break;
2124 default: abi_str
= "unknown"; break;
2127 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2129 if (rs6000_altivec_abi
)
2130 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2133 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2135 if (rs6000_darwin64_abi
)
2136 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2138 if (rs6000_float_gprs
)
2139 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2141 if (TARGET_LINK_STACK
)
2142 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2144 if (targetm
.lra_p ())
2145 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2147 if (TARGET_P8_FUSION
)
2148 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2149 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2151 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2152 TARGET_SECURE_PLT
? "secure" : "bss");
2153 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2154 aix_struct_return
? "aix" : "sysv");
2155 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2156 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2157 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2158 tf
[!!rs6000_align_branch_targets
]);
2159 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2160 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2161 rs6000_long_double_type_size
);
2162 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2163 (int)rs6000_sched_restricted_insns_priority
);
2164 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2166 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2167 (int)RS6000_BUILTIN_COUNT
);
2170 /* Initialize the various global tables that are based on register size. */
2172 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2178 /* Precalculate REGNO_REG_CLASS. */
2179 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2180 for (r
= 1; r
< 32; ++r
)
2181 rs6000_regno_regclass
[r
] = BASE_REGS
;
2183 for (r
= 32; r
< 64; ++r
)
2184 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2186 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2187 rs6000_regno_regclass
[r
] = NO_REGS
;
2189 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2190 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2192 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2193 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2194 rs6000_regno_regclass
[r
] = CR_REGS
;
2196 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2197 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2198 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2199 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2200 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2201 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2202 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2203 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2204 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2205 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2206 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2207 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2209 /* Precalculate register class to simpler reload register class. We don't
2210 need all of the register classes that are combinations of different
2211 classes, just the simple ones that have constraint letters. */
2212 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2213 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2215 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2216 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2217 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2218 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2219 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2220 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2221 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2222 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2223 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2224 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2225 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2226 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2230 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2231 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2235 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2236 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2239 /* Precalculate vector information, this must be set up before the
2240 rs6000_hard_regno_nregs_internal below. */
2241 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2243 rs6000_vector_unit
[m
] = rs6000_vector_mem
[m
] = VECTOR_NONE
;
2244 rs6000_vector_reload
[m
][0] = CODE_FOR_nothing
;
2245 rs6000_vector_reload
[m
][1] = CODE_FOR_nothing
;
2248 for (c
= 0; c
< (int)(int)RS6000_CONSTRAINT_MAX
; c
++)
2249 rs6000_constraints
[c
] = NO_REGS
;
2251 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2252 believes it can use native alignment or still uses 128-bit alignment. */
2253 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2264 /* V2DF mode, VSX only. */
2267 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2268 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2269 rs6000_vector_align
[V2DFmode
] = align64
;
2272 /* V4SF mode, either VSX or Altivec. */
2275 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2276 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2277 rs6000_vector_align
[V4SFmode
] = align32
;
2279 else if (TARGET_ALTIVEC
)
2281 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2282 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2283 rs6000_vector_align
[V4SFmode
] = align32
;
2286 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2290 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2291 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2292 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2293 rs6000_vector_align
[V4SImode
] = align32
;
2294 rs6000_vector_align
[V8HImode
] = align32
;
2295 rs6000_vector_align
[V16QImode
] = align32
;
2299 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2300 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2301 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2305 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2306 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2307 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2311 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2312 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2315 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2316 rs6000_vector_unit
[V2DImode
]
2317 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2318 rs6000_vector_align
[V2DImode
] = align64
;
2321 /* DFmode, see if we want to use the VSX unit. */
2322 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2324 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2325 rs6000_vector_mem
[DFmode
]
2326 = (TARGET_VSX_SCALAR_MEMORY
? VECTOR_VSX
: VECTOR_NONE
);
2327 rs6000_vector_align
[DFmode
] = align64
;
2330 /* Allow TImode in VSX register and set the VSX memory macros. */
2331 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2333 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2334 rs6000_vector_align
[TImode
] = align64
;
2337 /* TODO add SPE and paired floating point vector support. */
2339 /* Register class constraints for the constraints that depend on compile
2341 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2342 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2344 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2345 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2349 /* At present, we just use VSX_REGS, but we have different constraints
2350 based on the use, in case we want to fine tune the default register
2351 class used. wa = any VSX register, wf = register class to use for
2352 V4SF, wd = register class to use for V2DF, and ws = register classs to
2353 use for DF scalars. */
2354 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2355 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2356 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2357 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = (TARGET_VSX_SCALAR_MEMORY
2360 if (TARGET_VSX_TIMODE
)
2361 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2364 /* Add conditional constraints based on various options, to allow us to
2365 collapse multiple insn patterns. */
2367 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2370 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2373 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2375 if (TARGET_DIRECT_MOVE
)
2376 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2378 if (TARGET_POWERPC64
)
2379 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2381 if (TARGET_P8_VECTOR
)
2382 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2385 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2388 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2390 /* Setup the direct move combinations. */
2391 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2393 reload_fpr_gpr
[m
] = CODE_FOR_nothing
;
2394 reload_gpr_vsx
[m
] = CODE_FOR_nothing
;
2395 reload_vsx_gpr
[m
] = CODE_FOR_nothing
;
2398 /* Set up the reload helper and direct move functions. */
2399 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2403 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_di_store
;
2404 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_di_load
;
2405 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_di_store
;
2406 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_di_load
;
2407 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_di_store
;
2408 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_di_load
;
2409 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_di_store
;
2410 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_di_load
;
2411 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_di_store
;
2412 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_di_load
;
2413 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_di_store
;
2414 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_di_load
;
2415 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2417 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_di_store
;
2418 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_di_load
;
2419 rs6000_vector_reload
[DDmode
][0] = CODE_FOR_reload_dd_di_store
;
2420 rs6000_vector_reload
[DDmode
][1] = CODE_FOR_reload_dd_di_load
;
2422 if (TARGET_P8_VECTOR
)
2424 rs6000_vector_reload
[SFmode
][0] = CODE_FOR_reload_sf_di_store
;
2425 rs6000_vector_reload
[SFmode
][1] = CODE_FOR_reload_sf_di_load
;
2426 rs6000_vector_reload
[SDmode
][0] = CODE_FOR_reload_sd_di_store
;
2427 rs6000_vector_reload
[SDmode
][1] = CODE_FOR_reload_sd_di_load
;
2429 if (TARGET_VSX_TIMODE
)
2431 rs6000_vector_reload
[TImode
][0] = CODE_FOR_reload_ti_di_store
;
2432 rs6000_vector_reload
[TImode
][1] = CODE_FOR_reload_ti_di_load
;
2434 if (TARGET_DIRECT_MOVE
)
2436 if (TARGET_POWERPC64
)
2438 reload_gpr_vsx
[TImode
] = CODE_FOR_reload_gpr_from_vsxti
;
2439 reload_gpr_vsx
[V2DFmode
] = CODE_FOR_reload_gpr_from_vsxv2df
;
2440 reload_gpr_vsx
[V2DImode
] = CODE_FOR_reload_gpr_from_vsxv2di
;
2441 reload_gpr_vsx
[V4SFmode
] = CODE_FOR_reload_gpr_from_vsxv4sf
;
2442 reload_gpr_vsx
[V4SImode
] = CODE_FOR_reload_gpr_from_vsxv4si
;
2443 reload_gpr_vsx
[V8HImode
] = CODE_FOR_reload_gpr_from_vsxv8hi
;
2444 reload_gpr_vsx
[V16QImode
] = CODE_FOR_reload_gpr_from_vsxv16qi
;
2445 reload_gpr_vsx
[SFmode
] = CODE_FOR_reload_gpr_from_vsxsf
;
2447 reload_vsx_gpr
[TImode
] = CODE_FOR_reload_vsx_from_gprti
;
2448 reload_vsx_gpr
[V2DFmode
] = CODE_FOR_reload_vsx_from_gprv2df
;
2449 reload_vsx_gpr
[V2DImode
] = CODE_FOR_reload_vsx_from_gprv2di
;
2450 reload_vsx_gpr
[V4SFmode
] = CODE_FOR_reload_vsx_from_gprv4sf
;
2451 reload_vsx_gpr
[V4SImode
] = CODE_FOR_reload_vsx_from_gprv4si
;
2452 reload_vsx_gpr
[V8HImode
] = CODE_FOR_reload_vsx_from_gprv8hi
;
2453 reload_vsx_gpr
[V16QImode
] = CODE_FOR_reload_vsx_from_gprv16qi
;
2454 reload_vsx_gpr
[SFmode
] = CODE_FOR_reload_vsx_from_gprsf
;
2458 reload_fpr_gpr
[DImode
] = CODE_FOR_reload_fpr_from_gprdi
;
2459 reload_fpr_gpr
[DDmode
] = CODE_FOR_reload_fpr_from_gprdd
;
2460 reload_fpr_gpr
[DFmode
] = CODE_FOR_reload_fpr_from_gprdf
;
2466 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_si_store
;
2467 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_si_load
;
2468 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_si_store
;
2469 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_si_load
;
2470 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_si_store
;
2471 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_si_load
;
2472 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_si_store
;
2473 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_si_load
;
2474 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_si_store
;
2475 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_si_load
;
2476 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_si_store
;
2477 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_si_load
;
2478 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2480 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_si_store
;
2481 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_si_load
;
2482 rs6000_vector_reload
[DDmode
][0] = CODE_FOR_reload_dd_si_store
;
2483 rs6000_vector_reload
[DDmode
][1] = CODE_FOR_reload_dd_si_load
;
2485 if (TARGET_P8_VECTOR
)
2487 rs6000_vector_reload
[SFmode
][0] = CODE_FOR_reload_sf_si_store
;
2488 rs6000_vector_reload
[SFmode
][1] = CODE_FOR_reload_sf_si_load
;
2489 rs6000_vector_reload
[SDmode
][0] = CODE_FOR_reload_sd_si_store
;
2490 rs6000_vector_reload
[SDmode
][1] = CODE_FOR_reload_sd_si_load
;
2492 if (TARGET_VSX_TIMODE
)
2494 rs6000_vector_reload
[TImode
][0] = CODE_FOR_reload_ti_si_store
;
2495 rs6000_vector_reload
[TImode
][1] = CODE_FOR_reload_ti_si_load
;
2500 /* Precalculate HARD_REGNO_NREGS. */
2501 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2502 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2503 rs6000_hard_regno_nregs
[m
][r
]
2504 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2506 /* Precalculate HARD_REGNO_MODE_OK. */
2507 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2508 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2509 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2510 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2512 /* Precalculate CLASS_MAX_NREGS sizes. */
2513 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2517 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2518 reg_size
= UNITS_PER_VSX_WORD
;
2520 else if (c
== ALTIVEC_REGS
)
2521 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2523 else if (c
== FLOAT_REGS
)
2524 reg_size
= UNITS_PER_FP_WORD
;
2527 reg_size
= UNITS_PER_WORD
;
2529 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2531 int reg_size2
= reg_size
;
2533 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2534 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2535 && (m
== TDmode
|| m
== TFmode
))
2536 reg_size2
= UNITS_PER_FP_WORD
;
2538 rs6000_class_max_nregs
[m
][c
]
2539 = (GET_MODE_SIZE (m
) + reg_size2
- 1) / reg_size2
;
2543 if (TARGET_E500_DOUBLE
)
2544 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2546 /* Calculate which modes to automatically generate code to use a the
2547 reciprocal divide and square root instructions. In the future, possibly
2548 automatically generate the instructions even if the user did not specify
2549 -mrecip. The older machines double precision reciprocal sqrt estimate is
2550 not accurate enough. */
2551 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2553 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2555 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2556 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2557 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2558 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2559 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2561 if (TARGET_FRSQRTES
)
2562 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2564 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2565 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2566 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2567 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2568 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2570 if (rs6000_recip_control
)
2572 if (!flag_finite_math_only
)
2573 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2574 if (flag_trapping_math
)
2575 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2576 if (!flag_reciprocal_math
)
2577 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2578 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2580 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2581 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2582 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2584 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2585 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2586 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2588 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2589 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2590 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2592 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2593 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2594 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2596 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2597 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2598 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2600 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2601 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2602 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2604 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2605 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2606 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2608 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2609 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2610 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2614 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2616 if (TARGET_DEBUG_REG
)
2617 rs6000_debug_reg_global ();
2619 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2621 "SImode variable mult cost = %d\n"
2622 "SImode constant mult cost = %d\n"
2623 "SImode short constant mult cost = %d\n"
2624 "DImode multipliciation cost = %d\n"
2625 "SImode division cost = %d\n"
2626 "DImode division cost = %d\n"
2627 "Simple fp operation cost = %d\n"
2628 "DFmode multiplication cost = %d\n"
2629 "SFmode division cost = %d\n"
2630 "DFmode division cost = %d\n"
2631 "cache line size = %d\n"
2632 "l1 cache size = %d\n"
2633 "l2 cache size = %d\n"
2634 "simultaneous prefetches = %d\n"
2637 rs6000_cost
->mulsi_const
,
2638 rs6000_cost
->mulsi_const9
,
2646 rs6000_cost
->cache_line_size
,
2647 rs6000_cost
->l1_cache_size
,
2648 rs6000_cost
->l2_cache_size
,
2649 rs6000_cost
->simultaneous_prefetches
);
2654 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2657 darwin_rs6000_override_options (void)
2659 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2661 rs6000_altivec_abi
= 1;
2662 TARGET_ALTIVEC_VRSAVE
= 1;
2663 rs6000_current_abi
= ABI_DARWIN
;
2665 if (DEFAULT_ABI
== ABI_DARWIN
2667 darwin_one_byte_bool
= 1;
2669 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2671 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2672 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2676 rs6000_default_long_calls
= 1;
2677 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2680 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2682 if (!flag_mkernel
&& !flag_apple_kext
2684 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2685 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2687 /* Unless the user (not the configurer) has explicitly overridden
2688 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2689 G4 unless targeting the kernel. */
2692 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2693 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2694 && ! global_options_set
.x_rs6000_cpu_index
)
2696 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2701 /* If not otherwise specified by a target, make 'long double' equivalent to
2704 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2705 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2708 /* Return the builtin mask of the various options used that could affect which
2709 builtins were used. In the past we used target_flags, but we've run out of
2710 bits, and some options like SPE and PAIRED are no longer in
2714 rs6000_builtin_mask_calculate (void)
2716 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2717 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2718 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2719 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2720 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2721 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2722 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2723 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2724 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2725 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
2726 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
2727 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
2728 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0));
2731 /* Override command line options. Mostly we process the processor type and
2732 sometimes adjust other TARGET_ options. */
2735 rs6000_option_override_internal (bool global_init_p
)
2738 bool have_cpu
= false;
2740 /* The default cpu requested at configure time, if any. */
2741 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
2743 HOST_WIDE_INT set_masks
;
2746 struct cl_target_option
*main_target_opt
2747 = ((global_init_p
|| target_option_default_node
== NULL
)
2748 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
2750 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2751 library functions, so warn about it. The flag may be useful for
2752 performance studies from time to time though, so don't disable it
2754 if (global_options_set
.x_rs6000_alignment_flags
2755 && rs6000_alignment_flags
== MASK_ALIGN_POWER
2756 && DEFAULT_ABI
== ABI_DARWIN
2758 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2759 " it is incompatible with the installed C and C++ libraries");
2761 /* Numerous experiment shows that IRA based loop pressure
2762 calculation works better for RTL loop invariant motion on targets
2763 with enough (>= 32) registers. It is an expensive optimization.
2764 So it is on only for peak performance. */
2765 if (optimize
>= 3 && global_init_p
)
2766 flag_ira_loop_pressure
= 1;
2768 /* Set the pointer size. */
2771 rs6000_pmode
= (int)DImode
;
2772 rs6000_pointer_size
= 64;
2776 rs6000_pmode
= (int)SImode
;
2777 rs6000_pointer_size
= 32;
2780 /* Some OSs don't support saving the high part of 64-bit registers on context
2781 switch. Other OSs don't support saving Altivec registers. On those OSs,
2782 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
2783 if the user wants either, the user must explicitly specify them and we
2784 won't interfere with the user's specification. */
2786 set_masks
= POWERPC_MASKS
;
2787 #ifdef OS_MISSING_POWERPC64
2788 if (OS_MISSING_POWERPC64
)
2789 set_masks
&= ~OPTION_MASK_POWERPC64
;
2791 #ifdef OS_MISSING_ALTIVEC
2792 if (OS_MISSING_ALTIVEC
)
2793 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
2796 /* Don't override by the processor default if given explicitly. */
2797 set_masks
&= ~rs6000_isa_flags_explicit
;
2799 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2800 the cpu in a target attribute or pragma, but did not specify a tuning
2801 option, use the cpu for the tuning option rather than the option specified
2802 with -mtune on the command line. Process a '--with-cpu' configuration
2803 request as an implicit --cpu. */
2804 if (rs6000_cpu_index
>= 0)
2806 cpu_index
= rs6000_cpu_index
;
2809 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
2811 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
2814 else if (implicit_cpu
)
2816 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
2821 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
2822 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
2826 gcc_assert (cpu_index
>= 0);
2828 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
2829 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
2830 with those from the cpu, except for options that were explicitly set. If
2831 we don't have a cpu, do not override the target bits set in
2835 rs6000_isa_flags
&= ~set_masks
;
2836 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2840 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
2841 & ~rs6000_isa_flags_explicit
);
2843 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
2844 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
2845 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
2846 to using rs6000_isa_flags, we need to do the initialization here. */
2848 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
2850 if (rs6000_tune_index
>= 0)
2851 tune_index
= rs6000_tune_index
;
2853 rs6000_tune_index
= tune_index
= cpu_index
;
2857 enum processor_type tune_proc
2858 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
2861 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2862 if (processor_target_table
[i
].processor
== tune_proc
)
2864 rs6000_tune_index
= tune_index
= i
;
2869 gcc_assert (tune_index
>= 0);
2870 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
2872 /* Pick defaults for SPE related control flags. Do this early to make sure
2873 that the TARGET_ macros are representative ASAP. */
2875 int spe_capable_cpu
=
2876 (rs6000_cpu
== PROCESSOR_PPC8540
2877 || rs6000_cpu
== PROCESSOR_PPC8548
);
2879 if (!global_options_set
.x_rs6000_spe_abi
)
2880 rs6000_spe_abi
= spe_capable_cpu
;
2882 if (!global_options_set
.x_rs6000_spe
)
2883 rs6000_spe
= spe_capable_cpu
;
2885 if (!global_options_set
.x_rs6000_float_gprs
)
2887 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
2888 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
2892 if (global_options_set
.x_rs6000_spe_abi
2895 error ("not configured for SPE ABI");
2897 if (global_options_set
.x_rs6000_spe
2900 error ("not configured for SPE instruction set");
2902 if (main_target_opt
!= NULL
2903 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
2904 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
2905 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
2906 error ("target attribute or pragma changes SPE ABI");
2908 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
2909 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
2910 || rs6000_cpu
== PROCESSOR_PPCE5500
)
2913 error ("AltiVec not supported in this target");
2915 error ("SPE not supported in this target");
2917 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
2920 error ("SPE not supported in this target");
2923 /* Disable Cell microcode if we are optimizing for the Cell
2924 and not optimizing for size. */
2925 if (rs6000_gen_cell_microcode
== -1)
2926 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
2929 /* If we are optimizing big endian systems for space and it's OK to
2930 use instructions that would be microcoded on the Cell, use the
2931 load/store multiple and string instructions. */
2932 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
2933 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
2934 | OPTION_MASK_STRING
);
2936 /* Don't allow -mmultiple or -mstring on little endian systems
2937 unless the cpu is a 750, because the hardware doesn't support the
2938 instructions used in little endian mode, and causes an alignment
2939 trap. The 750 does not cause an alignment trap (except when the
2940 target is unaligned). */
2942 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
2944 if (TARGET_MULTIPLE
)
2946 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
2947 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
2948 warning (0, "-mmultiple is not supported on little endian systems");
2953 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
2954 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
2955 warning (0, "-mstring is not supported on little endian systems");
2959 /* Add some warnings for VSX. */
2962 const char *msg
= NULL
;
2963 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
2964 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
2966 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2967 msg
= N_("-mvsx requires hardware floating point");
2970 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2971 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
2974 else if (TARGET_PAIRED_FLOAT
)
2975 msg
= N_("-mvsx and -mpaired are incompatible");
2976 /* The hardware will allow VSX and little endian, but until we make sure
2977 things like vector select, etc. work don't allow VSX on little endian
2978 systems at this point. */
2979 else if (!BYTES_BIG_ENDIAN
)
2980 msg
= N_("-mvsx used with little endian code");
2981 else if (TARGET_AVOID_XFORM
> 0)
2982 msg
= N_("-mvsx needs indexed addressing");
2983 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
2984 & OPTION_MASK_ALTIVEC
))
2986 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
2987 msg
= N_("-mvsx and -mno-altivec are incompatible");
2989 msg
= N_("-mno-altivec disables vsx");
2995 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
2996 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3000 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3001 the -mcpu setting to enable options that conflict. */
3002 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3003 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3004 | OPTION_MASK_ALTIVEC
3005 | OPTION_MASK_VSX
)) != 0)
3006 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3007 | OPTION_MASK_DIRECT_MOVE
)
3008 & ~rs6000_isa_flags_explicit
);
3010 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3011 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3013 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3014 unless the user explicitly used the -mno-<option> to disable the code. */
3015 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3016 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3017 else if (TARGET_VSX
)
3018 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3019 else if (TARGET_POPCNTD
)
3020 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3021 else if (TARGET_DFP
)
3022 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3023 else if (TARGET_CMPB
)
3024 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3025 else if (TARGET_FPRND
)
3026 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3027 else if (TARGET_POPCNTB
)
3028 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3029 else if (TARGET_ALTIVEC
)
3030 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3032 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3034 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3035 error ("-mcrypto requires -maltivec");
3036 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3039 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3041 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3042 error ("-mdirect-move requires -mvsx");
3043 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3046 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3048 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3049 error ("-mpower8-vector requires -maltivec");
3050 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3053 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3055 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3056 error ("-mpower8-vector requires -mvsx");
3057 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3060 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3062 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3063 error ("-mvsx-timode requires -mvsx");
3064 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3067 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3068 silently turn off quad memory mode. */
3069 if (TARGET_QUAD_MEMORY
&& !TARGET_POWERPC64
)
3071 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3072 warning (0, N_("-mquad-memory requires 64-bit mode"));
3074 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3077 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3078 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3080 /* E500mc does "better" if we inline more aggressively. Respect the
3081 user's opinion, though. */
3082 if (rs6000_block_move_inline_limit
== 0
3083 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3084 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3085 || rs6000_cpu
== PROCESSOR_PPCE5500
3086 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3087 rs6000_block_move_inline_limit
= 128;
3089 /* store_one_arg depends on expand_block_move to handle at least the
3090 size of reg_parm_stack_space. */
3091 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3092 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3096 /* If the appropriate debug option is enabled, replace the target hooks
3097 with debug versions that call the real version and then prints
3098 debugging information. */
3099 if (TARGET_DEBUG_COST
)
3101 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3102 targetm
.address_cost
= rs6000_debug_address_cost
;
3103 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3106 if (TARGET_DEBUG_ADDR
)
3108 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3109 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3110 rs6000_secondary_reload_class_ptr
3111 = rs6000_debug_secondary_reload_class
;
3112 rs6000_secondary_memory_needed_ptr
3113 = rs6000_debug_secondary_memory_needed
;
3114 rs6000_cannot_change_mode_class_ptr
3115 = rs6000_debug_cannot_change_mode_class
;
3116 rs6000_preferred_reload_class_ptr
3117 = rs6000_debug_preferred_reload_class
;
3118 rs6000_legitimize_reload_address_ptr
3119 = rs6000_debug_legitimize_reload_address
;
3120 rs6000_mode_dependent_address_ptr
3121 = rs6000_debug_mode_dependent_address
;
3124 if (rs6000_veclibabi_name
)
3126 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3127 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3130 error ("unknown vectorization library ABI type (%s) for "
3131 "-mveclibabi= switch", rs6000_veclibabi_name
);
3137 if (!global_options_set
.x_rs6000_long_double_type_size
)
3139 if (main_target_opt
!= NULL
3140 && (main_target_opt
->x_rs6000_long_double_type_size
3141 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3142 error ("target attribute or pragma changes long double size");
3144 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3147 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3148 if (!global_options_set
.x_rs6000_ieeequad
)
3149 rs6000_ieeequad
= 1;
3152 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3153 target attribute or pragma which automatically enables both options,
3154 unless the altivec ABI was set. This is set by default for 64-bit, but
3156 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3157 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3158 & ~rs6000_isa_flags_explicit
);
3160 /* Enable Altivec ABI for AIX -maltivec. */
3161 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3163 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3164 error ("target attribute or pragma changes AltiVec ABI");
3166 rs6000_altivec_abi
= 1;
3169 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3170 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3171 be explicitly overridden in either case. */
3174 if (!global_options_set
.x_rs6000_altivec_abi
3175 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3177 if (main_target_opt
!= NULL
&&
3178 !main_target_opt
->x_rs6000_altivec_abi
)
3179 error ("target attribute or pragma changes AltiVec ABI");
3181 rs6000_altivec_abi
= 1;
3185 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3186 So far, the only darwin64 targets are also MACH-O. */
3188 && DEFAULT_ABI
== ABI_DARWIN
3191 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3192 error ("target attribute or pragma changes darwin64 ABI");
3195 rs6000_darwin64_abi
= 1;
3196 /* Default to natural alignment, for better performance. */
3197 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3201 /* Place FP constants in the constant pool instead of TOC
3202 if section anchors enabled. */
3203 if (flag_section_anchors
3204 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3205 TARGET_NO_FP_IN_TOC
= 1;
3207 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3208 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3210 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3211 SUBTARGET_OVERRIDE_OPTIONS
;
3213 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3214 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3216 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3217 SUB3TARGET_OVERRIDE_OPTIONS
;
3220 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3221 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3223 /* For the E500 family of cores, reset the single/double FP flags to let us
3224 check that they remain constant across attributes or pragmas. Also,
3225 clear a possible request for string instructions, not supported and which
3226 we might have silently queried above for -Os.
3228 For other families, clear ISEL in case it was set implicitly.
3233 case PROCESSOR_PPC8540
:
3234 case PROCESSOR_PPC8548
:
3235 case PROCESSOR_PPCE500MC
:
3236 case PROCESSOR_PPCE500MC64
:
3237 case PROCESSOR_PPCE5500
:
3238 case PROCESSOR_PPCE6500
:
3240 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3241 rs6000_double_float
= TARGET_E500_DOUBLE
;
3243 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3249 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3250 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3255 if (main_target_opt
)
3257 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3258 error ("target attribute or pragma changes single precision floating "
3260 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3261 error ("target attribute or pragma changes double precision floating "
3265 /* Detect invalid option combinations with E500. */
3268 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3269 && rs6000_cpu
!= PROCESSOR_POWER5
3270 && rs6000_cpu
!= PROCESSOR_POWER6
3271 && rs6000_cpu
!= PROCESSOR_POWER7
3272 && rs6000_cpu
!= PROCESSOR_POWER8
3273 && rs6000_cpu
!= PROCESSOR_PPCA2
3274 && rs6000_cpu
!= PROCESSOR_CELL
3275 && rs6000_cpu
!= PROCESSOR_PPC476
);
3276 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3277 || rs6000_cpu
== PROCESSOR_POWER5
3278 || rs6000_cpu
== PROCESSOR_POWER7
3279 || rs6000_cpu
== PROCESSOR_POWER8
);
3280 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3281 || rs6000_cpu
== PROCESSOR_POWER5
3282 || rs6000_cpu
== PROCESSOR_POWER6
3283 || rs6000_cpu
== PROCESSOR_POWER7
3284 || rs6000_cpu
== PROCESSOR_POWER8
3285 || rs6000_cpu
== PROCESSOR_PPCE500MC
3286 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3287 || rs6000_cpu
== PROCESSOR_PPCE5500
3288 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3290 /* Allow debug switches to override the above settings. These are set to -1
3291 in rs6000.opt to indicate the user hasn't directly set the switch. */
3292 if (TARGET_ALWAYS_HINT
>= 0)
3293 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3295 if (TARGET_SCHED_GROUPS
>= 0)
3296 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3298 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3299 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3301 rs6000_sched_restricted_insns_priority
3302 = (rs6000_sched_groups
? 1 : 0);
3304 /* Handle -msched-costly-dep option. */
3305 rs6000_sched_costly_dep
3306 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3308 if (rs6000_sched_costly_dep_str
)
3310 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3311 rs6000_sched_costly_dep
= no_dep_costly
;
3312 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3313 rs6000_sched_costly_dep
= all_deps_costly
;
3314 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3315 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3316 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3317 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3319 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3320 atoi (rs6000_sched_costly_dep_str
));
3323 /* Handle -minsert-sched-nops option. */
3324 rs6000_sched_insert_nops
3325 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3327 if (rs6000_sched_insert_nops_str
)
3329 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3330 rs6000_sched_insert_nops
= sched_finish_none
;
3331 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3332 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3333 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3334 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3336 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3337 atoi (rs6000_sched_insert_nops_str
));
3342 #ifdef TARGET_REGNAMES
3343 /* If the user desires alternate register names, copy in the
3344 alternate names now. */
3345 if (TARGET_REGNAMES
)
3346 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3349 /* Set aix_struct_return last, after the ABI is determined.
3350 If -maix-struct-return or -msvr4-struct-return was explicitly
3351 used, don't override with the ABI default. */
3352 if (!global_options_set
.x_aix_struct_return
)
3353 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3356 /* IBM XL compiler defaults to unsigned bitfields. */
3357 if (TARGET_XL_COMPAT
)
3358 flag_signed_bitfields
= 0;
3361 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3362 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3365 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3367 /* We can only guarantee the availability of DI pseudo-ops when
3368 assembling for 64-bit targets. */
3371 targetm
.asm_out
.aligned_op
.di
= NULL
;
3372 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3376 /* Set branch target alignment, if not optimizing for size. */
3379 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3380 aligned 8byte to avoid misprediction by the branch predictor. */
3381 if (rs6000_cpu
== PROCESSOR_TITAN
3382 || rs6000_cpu
== PROCESSOR_CELL
)
3384 if (align_functions
<= 0)
3385 align_functions
= 8;
3386 if (align_jumps
<= 0)
3388 if (align_loops
<= 0)
3391 if (rs6000_align_branch_targets
)
3393 if (align_functions
<= 0)
3394 align_functions
= 16;
3395 if (align_jumps
<= 0)
3397 if (align_loops
<= 0)
3399 can_override_loop_align
= 1;
3403 if (align_jumps_max_skip
<= 0)
3404 align_jumps_max_skip
= 15;
3405 if (align_loops_max_skip
<= 0)
3406 align_loops_max_skip
= 15;
3409 /* Arrange to save and restore machine status around nested functions. */
3410 init_machine_status
= rs6000_init_machine_status
;
3412 /* We should always be splitting complex arguments, but we can't break
3413 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3414 if (DEFAULT_ABI
!= ABI_AIX
)
3415 targetm
.calls
.split_complex_arg
= NULL
;
3418 /* Initialize rs6000_cost with the appropriate target costs. */
3420 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3424 case PROCESSOR_RS64A
:
3425 rs6000_cost
= &rs64a_cost
;
3428 case PROCESSOR_MPCCORE
:
3429 rs6000_cost
= &mpccore_cost
;
3432 case PROCESSOR_PPC403
:
3433 rs6000_cost
= &ppc403_cost
;
3436 case PROCESSOR_PPC405
:
3437 rs6000_cost
= &ppc405_cost
;
3440 case PROCESSOR_PPC440
:
3441 rs6000_cost
= &ppc440_cost
;
3444 case PROCESSOR_PPC476
:
3445 rs6000_cost
= &ppc476_cost
;
3448 case PROCESSOR_PPC601
:
3449 rs6000_cost
= &ppc601_cost
;
3452 case PROCESSOR_PPC603
:
3453 rs6000_cost
= &ppc603_cost
;
3456 case PROCESSOR_PPC604
:
3457 rs6000_cost
= &ppc604_cost
;
3460 case PROCESSOR_PPC604e
:
3461 rs6000_cost
= &ppc604e_cost
;
3464 case PROCESSOR_PPC620
:
3465 rs6000_cost
= &ppc620_cost
;
3468 case PROCESSOR_PPC630
:
3469 rs6000_cost
= &ppc630_cost
;
3472 case PROCESSOR_CELL
:
3473 rs6000_cost
= &ppccell_cost
;
3476 case PROCESSOR_PPC750
:
3477 case PROCESSOR_PPC7400
:
3478 rs6000_cost
= &ppc750_cost
;
3481 case PROCESSOR_PPC7450
:
3482 rs6000_cost
= &ppc7450_cost
;
3485 case PROCESSOR_PPC8540
:
3486 case PROCESSOR_PPC8548
:
3487 rs6000_cost
= &ppc8540_cost
;
3490 case PROCESSOR_PPCE300C2
:
3491 case PROCESSOR_PPCE300C3
:
3492 rs6000_cost
= &ppce300c2c3_cost
;
3495 case PROCESSOR_PPCE500MC
:
3496 rs6000_cost
= &ppce500mc_cost
;
3499 case PROCESSOR_PPCE500MC64
:
3500 rs6000_cost
= &ppce500mc64_cost
;
3503 case PROCESSOR_PPCE5500
:
3504 rs6000_cost
= &ppce5500_cost
;
3507 case PROCESSOR_PPCE6500
:
3508 rs6000_cost
= &ppce6500_cost
;
3511 case PROCESSOR_TITAN
:
3512 rs6000_cost
= &titan_cost
;
3515 case PROCESSOR_POWER4
:
3516 case PROCESSOR_POWER5
:
3517 rs6000_cost
= &power4_cost
;
3520 case PROCESSOR_POWER6
:
3521 rs6000_cost
= &power6_cost
;
3524 case PROCESSOR_POWER7
:
3525 rs6000_cost
= &power7_cost
;
3528 case PROCESSOR_POWER8
:
3529 rs6000_cost
= &power8_cost
;
3532 case PROCESSOR_PPCA2
:
3533 rs6000_cost
= &ppca2_cost
;
3542 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3543 rs6000_cost
->simultaneous_prefetches
,
3544 global_options
.x_param_values
,
3545 global_options_set
.x_param_values
);
3546 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3547 global_options
.x_param_values
,
3548 global_options_set
.x_param_values
);
3549 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3550 rs6000_cost
->cache_line_size
,
3551 global_options
.x_param_values
,
3552 global_options_set
.x_param_values
);
3553 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3554 global_options
.x_param_values
,
3555 global_options_set
.x_param_values
);
3557 /* Increase loop peeling limits based on performance analysis. */
3558 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3559 global_options
.x_param_values
,
3560 global_options_set
.x_param_values
);
3561 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3562 global_options
.x_param_values
,
3563 global_options_set
.x_param_values
);
3565 /* If using typedef char *va_list, signal that
3566 __builtin_va_start (&ap, 0) can be optimized to
3567 ap = __builtin_next_arg (0). */
3568 if (DEFAULT_ABI
!= ABI_V4
)
3569 targetm
.expand_builtin_va_start
= NULL
;
3572 /* Set up single/double float flags.
3573 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3574 then set both flags. */
3575 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3576 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3577 rs6000_single_float
= rs6000_double_float
= 1;
3579 /* If not explicitly specified via option, decide whether to generate indexed
3580 load/store instructions. */
3581 if (TARGET_AVOID_XFORM
== -1)
3582 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3583 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3584 need indexed accesses and the type used is the scalar type of the element
3585 being loaded or stored. */
3586 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3587 && !TARGET_ALTIVEC
);
3589 /* Set the -mrecip options. */
3590 if (rs6000_recip_name
)
3592 char *p
= ASTRDUP (rs6000_recip_name
);
3594 unsigned int mask
, i
;
3597 while ((q
= strtok (p
, ",")) != NULL
)
3608 if (!strcmp (q
, "default"))
3609 mask
= ((TARGET_RECIP_PRECISION
)
3610 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3613 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3614 if (!strcmp (q
, recip_options
[i
].string
))
3616 mask
= recip_options
[i
].mask
;
3620 if (i
== ARRAY_SIZE (recip_options
))
3622 error ("unknown option for -mrecip=%s", q
);
3630 rs6000_recip_control
&= ~mask
;
3632 rs6000_recip_control
|= mask
;
3636 /* Set the builtin mask of the various options used that could affect which
3637 builtins were used. In the past we used target_flags, but we've run out
3638 of bits, and some options like SPE and PAIRED are no longer in
3640 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3641 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3644 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3645 rs6000_builtin_mask
);
3646 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3649 /* Initialize all of the registers. */
3650 rs6000_init_hard_regno_mode_ok (global_init_p
);
3652 /* Save the initial options in case the user does function specific options */
3654 target_option_default_node
= target_option_current_node
3655 = build_target_option_node ();
3657 /* If not explicitly specified via option, decide whether to generate the
3658 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3659 if (TARGET_LINK_STACK
== -1)
3660 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3665 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3666 define the target cpu type. */
3669 rs6000_option_override (void)
3671 (void) rs6000_option_override_internal (true);
3675 /* Implement targetm.vectorize.builtin_mask_for_load. */
3677 rs6000_builtin_mask_for_load (void)
3679 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3680 return altivec_builtin_mask_for_load
;
3685 /* Implement LOOP_ALIGN. */
3687 rs6000_loop_align (rtx label
)
3692 /* Don't override loop alignment if -falign-loops was specified. */
3693 if (!can_override_loop_align
)
3694 return align_loops_log
;
3696 bb
= BLOCK_FOR_INSN (label
);
3697 ninsns
= num_loop_insns(bb
->loop_father
);
3699 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3700 if (ninsns
> 4 && ninsns
<= 8
3701 && (rs6000_cpu
== PROCESSOR_POWER4
3702 || rs6000_cpu
== PROCESSOR_POWER5
3703 || rs6000_cpu
== PROCESSOR_POWER6
3704 || rs6000_cpu
== PROCESSOR_POWER7
3705 || rs6000_cpu
== PROCESSOR_POWER8
))
3708 return align_loops_log
;
3711 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3713 rs6000_loop_align_max_skip (rtx label
)
3715 return (1 << rs6000_loop_align (label
)) - 1;
3718 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3719 after applying N number of iterations. This routine does not determine
3720 how may iterations are required to reach desired alignment. */
3723 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
3730 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
3733 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
3743 /* Assuming that all other types are naturally aligned. CHECKME! */
3748 /* Return true if the vector misalignment factor is supported by the
3751 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
3758 /* Return if movmisalign pattern is not supported for this mode. */
3759 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
3762 if (misalignment
== -1)
3764 /* Misalignment factor is unknown at compile time but we know
3765 it's word aligned. */
3766 if (rs6000_vector_alignment_reachable (type
, is_packed
))
3768 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
3770 if (element_size
== 64 || element_size
== 32)
3777 /* VSX supports word-aligned vector. */
3778 if (misalignment
% 4 == 0)
3784 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3786 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
3787 tree vectype
, int misalign
)
3792 switch (type_of_cost
)
3802 case cond_branch_not_taken
:
3811 case vec_promote_demote
:
3817 case cond_branch_taken
:
3820 case unaligned_load
:
3821 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3823 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3825 /* Double word aligned. */
3833 /* Double word aligned. */
3837 /* Unknown misalignment. */
3850 /* Misaligned loads are not supported. */
3855 case unaligned_store
:
3856 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3858 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3860 /* Double word aligned. */
3868 /* Double word aligned. */
3872 /* Unknown misalignment. */
3885 /* Misaligned stores are not supported. */
3891 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3892 elem_type
= TREE_TYPE (vectype
);
3893 /* 32-bit vectors loaded into registers are stored as double
3894 precision, so we need n/2 converts in addition to the usual
3895 n/2 merges to construct a vector of short floats from them. */
3896 if (SCALAR_FLOAT_TYPE_P (elem_type
)
3897 && TYPE_PRECISION (elem_type
) == 32)
3898 return elements
+ 1;
3900 return elements
/ 2 + 1;
3907 /* Implement targetm.vectorize.preferred_simd_mode. */
3909 static enum machine_mode
3910 rs6000_preferred_simd_mode (enum machine_mode mode
)
3919 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3943 if (TARGET_PAIRED_FLOAT
3949 typedef struct _rs6000_cost_data
3951 struct loop
*loop_info
;
3955 /* Test for likely overcommitment of vector hardware resources. If a
3956 loop iteration is relatively large, and too large a percentage of
3957 instructions in the loop are vectorized, the cost model may not
3958 adequately reflect delays from unavailable vector resources.
3959 Penalize the loop body cost for this case. */
3962 rs6000_density_test (rs6000_cost_data
*data
)
3964 const int DENSITY_PCT_THRESHOLD
= 85;
3965 const int DENSITY_SIZE_THRESHOLD
= 70;
3966 const int DENSITY_PENALTY
= 10;
3967 struct loop
*loop
= data
->loop_info
;
3968 basic_block
*bbs
= get_loop_body (loop
);
3969 int nbbs
= loop
->num_nodes
;
3970 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
3973 for (i
= 0; i
< nbbs
; i
++)
3975 basic_block bb
= bbs
[i
];
3976 gimple_stmt_iterator gsi
;
3978 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
3980 gimple stmt
= gsi_stmt (gsi
);
3981 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
3983 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
3984 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
3990 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
3992 if (density_pct
> DENSITY_PCT_THRESHOLD
3993 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
3995 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
3996 if (dump_enabled_p ())
3997 dump_printf_loc (MSG_NOTE
, vect_location
,
3998 "density %d%%, cost %d exceeds threshold, penalizing "
3999 "loop body cost by %d%%", density_pct
,
4000 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4004 /* Implement targetm.vectorize.init_cost. */
4007 rs6000_init_cost (struct loop
*loop_info
)
4009 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4010 data
->loop_info
= loop_info
;
4011 data
->cost
[vect_prologue
] = 0;
4012 data
->cost
[vect_body
] = 0;
4013 data
->cost
[vect_epilogue
] = 0;
4017 /* Implement targetm.vectorize.add_stmt_cost. */
4020 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4021 struct _stmt_vec_info
*stmt_info
, int misalign
,
4022 enum vect_cost_model_location where
)
4024 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4025 unsigned retval
= 0;
4027 if (flag_vect_cost_model
)
4029 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4030 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4032 /* Statements in an inner loop relative to the loop being
4033 vectorized are weighted more heavily. The value here is
4034 arbitrary and could potentially be improved with analysis. */
4035 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4036 count
*= 50; /* FIXME. */
4038 retval
= (unsigned) (count
* stmt_cost
);
4039 cost_data
->cost
[where
] += retval
;
4045 /* Implement targetm.vectorize.finish_cost. */
4048 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4049 unsigned *body_cost
, unsigned *epilogue_cost
)
4051 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4053 if (cost_data
->loop_info
)
4054 rs6000_density_test (cost_data
);
4056 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4057 *body_cost
= cost_data
->cost
[vect_body
];
4058 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4061 /* Implement targetm.vectorize.destroy_cost_data. */
4064 rs6000_destroy_cost_data (void *data
)
4069 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4070 library with vectorized intrinsics. */
4073 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4076 const char *suffix
= NULL
;
4077 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4080 enum machine_mode el_mode
, in_mode
;
4083 /* Libmass is suitable for unsafe math only as it does not correctly support
4084 parts of IEEE with the required precision such as denormals. Only support
4085 it if we have VSX to use the simd d2 or f4 functions.
4086 XXX: Add variable length support. */
4087 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4090 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4091 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4092 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4093 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4094 if (el_mode
!= in_mode
4098 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4100 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4103 case BUILT_IN_ATAN2
:
4104 case BUILT_IN_HYPOT
:
4110 case BUILT_IN_ACOSH
:
4112 case BUILT_IN_ASINH
:
4114 case BUILT_IN_ATANH
:
4122 case BUILT_IN_EXPM1
:
4123 case BUILT_IN_LGAMMA
:
4124 case BUILT_IN_LOG10
:
4125 case BUILT_IN_LOG1P
:
4133 bdecl
= builtin_decl_implicit (fn
);
4134 suffix
= "d2"; /* pow -> powd2 */
4135 if (el_mode
!= DFmode
4141 case BUILT_IN_ATAN2F
:
4142 case BUILT_IN_HYPOTF
:
4147 case BUILT_IN_ACOSF
:
4148 case BUILT_IN_ACOSHF
:
4149 case BUILT_IN_ASINF
:
4150 case BUILT_IN_ASINHF
:
4151 case BUILT_IN_ATANF
:
4152 case BUILT_IN_ATANHF
:
4153 case BUILT_IN_CBRTF
:
4155 case BUILT_IN_COSHF
:
4157 case BUILT_IN_ERFCF
:
4158 case BUILT_IN_EXP2F
:
4160 case BUILT_IN_EXPM1F
:
4161 case BUILT_IN_LGAMMAF
:
4162 case BUILT_IN_LOG10F
:
4163 case BUILT_IN_LOG1PF
:
4164 case BUILT_IN_LOG2F
:
4167 case BUILT_IN_SINHF
:
4168 case BUILT_IN_SQRTF
:
4170 case BUILT_IN_TANHF
:
4171 bdecl
= builtin_decl_implicit (fn
);
4172 suffix
= "4"; /* powf -> powf4 */
4173 if (el_mode
!= SFmode
4186 gcc_assert (suffix
!= NULL
);
4187 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4191 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4192 strcat (name
, suffix
);
4195 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4196 else if (n_args
== 2)
4197 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4201 /* Build a function declaration for the vectorized function. */
4202 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4203 FUNCTION_DECL
, get_identifier (name
), fntype
);
4204 TREE_PUBLIC (new_fndecl
) = 1;
4205 DECL_EXTERNAL (new_fndecl
) = 1;
4206 DECL_IS_NOVOPS (new_fndecl
) = 1;
4207 TREE_READONLY (new_fndecl
) = 1;
4212 /* Returns a function decl for a vectorized version of the builtin function
4213 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4214 if it is not available. */
4217 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4220 enum machine_mode in_mode
, out_mode
;
4223 if (TARGET_DEBUG_BUILTIN
)
4224 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4225 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4226 GET_MODE_NAME (TYPE_MODE (type_out
)),
4227 GET_MODE_NAME (TYPE_MODE (type_in
)));
4229 if (TREE_CODE (type_out
) != VECTOR_TYPE
4230 || TREE_CODE (type_in
) != VECTOR_TYPE
4231 || !TARGET_VECTORIZE_BUILTINS
)
4234 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4235 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4236 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4237 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4239 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4241 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4244 case BUILT_IN_CLZIMAX
:
4245 case BUILT_IN_CLZLL
:
4248 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4250 if (out_mode
== QImode
&& out_n
== 16)
4251 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4252 else if (out_mode
== HImode
&& out_n
== 8)
4253 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4254 else if (out_mode
== SImode
&& out_n
== 4)
4255 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4256 else if (out_mode
== DImode
&& out_n
== 2)
4257 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4260 case BUILT_IN_COPYSIGN
:
4261 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4262 && out_mode
== DFmode
&& out_n
== 2
4263 && in_mode
== DFmode
&& in_n
== 2)
4264 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4266 case BUILT_IN_COPYSIGNF
:
4267 if (out_mode
!= SFmode
|| out_n
!= 4
4268 || in_mode
!= SFmode
|| in_n
!= 4)
4270 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4271 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4272 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4273 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4275 case BUILT_IN_POPCOUNTIMAX
:
4276 case BUILT_IN_POPCOUNTLL
:
4277 case BUILT_IN_POPCOUNTL
:
4278 case BUILT_IN_POPCOUNT
:
4279 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4281 if (out_mode
== QImode
&& out_n
== 16)
4282 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4283 else if (out_mode
== HImode
&& out_n
== 8)
4284 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4285 else if (out_mode
== SImode
&& out_n
== 4)
4286 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4287 else if (out_mode
== DImode
&& out_n
== 2)
4288 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4292 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4293 && out_mode
== DFmode
&& out_n
== 2
4294 && in_mode
== DFmode
&& in_n
== 2)
4295 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4297 case BUILT_IN_SQRTF
:
4298 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4299 && out_mode
== SFmode
&& out_n
== 4
4300 && in_mode
== SFmode
&& in_n
== 4)
4301 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4304 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4305 && out_mode
== DFmode
&& out_n
== 2
4306 && in_mode
== DFmode
&& in_n
== 2)
4307 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4309 case BUILT_IN_CEILF
:
4310 if (out_mode
!= SFmode
|| out_n
!= 4
4311 || in_mode
!= SFmode
|| in_n
!= 4)
4313 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4314 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4315 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4316 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4318 case BUILT_IN_FLOOR
:
4319 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4320 && out_mode
== DFmode
&& out_n
== 2
4321 && in_mode
== DFmode
&& in_n
== 2)
4322 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4324 case BUILT_IN_FLOORF
:
4325 if (out_mode
!= SFmode
|| out_n
!= 4
4326 || in_mode
!= SFmode
|| in_n
!= 4)
4328 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4329 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4330 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4331 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4334 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4335 && out_mode
== DFmode
&& out_n
== 2
4336 && in_mode
== DFmode
&& in_n
== 2)
4337 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4340 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4341 && out_mode
== SFmode
&& out_n
== 4
4342 && in_mode
== SFmode
&& in_n
== 4)
4343 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4344 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4345 && out_mode
== SFmode
&& out_n
== 4
4346 && in_mode
== SFmode
&& in_n
== 4)
4347 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4349 case BUILT_IN_TRUNC
:
4350 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4351 && out_mode
== DFmode
&& out_n
== 2
4352 && in_mode
== DFmode
&& in_n
== 2)
4353 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4355 case BUILT_IN_TRUNCF
:
4356 if (out_mode
!= SFmode
|| out_n
!= 4
4357 || in_mode
!= SFmode
|| in_n
!= 4)
4359 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4360 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4361 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4362 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4364 case BUILT_IN_NEARBYINT
:
4365 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4366 && flag_unsafe_math_optimizations
4367 && out_mode
== DFmode
&& out_n
== 2
4368 && in_mode
== DFmode
&& in_n
== 2)
4369 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4371 case BUILT_IN_NEARBYINTF
:
4372 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4373 && flag_unsafe_math_optimizations
4374 && out_mode
== SFmode
&& out_n
== 4
4375 && in_mode
== SFmode
&& in_n
== 4)
4376 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4379 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4380 && !flag_trapping_math
4381 && out_mode
== DFmode
&& out_n
== 2
4382 && in_mode
== DFmode
&& in_n
== 2)
4383 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4385 case BUILT_IN_RINTF
:
4386 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4387 && !flag_trapping_math
4388 && out_mode
== SFmode
&& out_n
== 4
4389 && in_mode
== SFmode
&& in_n
== 4)
4390 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4397 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4399 enum rs6000_builtins fn
4400 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4403 case RS6000_BUILTIN_RSQRTF
:
4404 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4405 && out_mode
== SFmode
&& out_n
== 4
4406 && in_mode
== SFmode
&& in_n
== 4)
4407 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4409 case RS6000_BUILTIN_RSQRT
:
4410 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4411 && out_mode
== DFmode
&& out_n
== 2
4412 && in_mode
== DFmode
&& in_n
== 2)
4413 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4415 case RS6000_BUILTIN_RECIPF
:
4416 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4417 && out_mode
== SFmode
&& out_n
== 4
4418 && in_mode
== SFmode
&& in_n
== 4)
4419 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4421 case RS6000_BUILTIN_RECIP
:
4422 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4423 && out_mode
== DFmode
&& out_n
== 2
4424 && in_mode
== DFmode
&& in_n
== 2)
4425 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4432 /* Generate calls to libmass if appropriate. */
4433 if (rs6000_veclib_handler
)
4434 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4439 /* Default CPU string for rs6000*_file_start functions. */
4440 static const char *rs6000_default_cpu
;
4442 /* Do anything needed at the start of the asm file. */
4445 rs6000_file_start (void)
4448 const char *start
= buffer
;
4449 FILE *file
= asm_out_file
;
4451 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4453 default_file_start ();
4455 if (flag_verbose_asm
)
4457 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4459 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4461 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4465 if (global_options_set
.x_rs6000_cpu_index
)
4467 fprintf (file
, "%s -mcpu=%s", start
,
4468 processor_target_table
[rs6000_cpu_index
].name
);
4472 if (global_options_set
.x_rs6000_tune_index
)
4474 fprintf (file
, "%s -mtune=%s", start
,
4475 processor_target_table
[rs6000_tune_index
].name
);
4479 if (PPC405_ERRATUM77
)
4481 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4485 #ifdef USING_ELFOS_H
4486 switch (rs6000_sdata
)
4488 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4489 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4490 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4491 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4494 if (rs6000_sdata
&& g_switch_value
)
4496 fprintf (file
, "%s -G %d", start
,
4506 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
4508 switch_to_section (toc_section
);
4509 switch_to_section (text_section
);
4514 /* Return nonzero if this function is known to have a null epilogue. */
4517 direct_return (void)
4519 if (reload_completed
)
4521 rs6000_stack_t
*info
= rs6000_stack_info ();
4523 if (info
->first_gp_reg_save
== 32
4524 && info
->first_fp_reg_save
== 64
4525 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4526 && ! info
->lr_save_p
4527 && ! info
->cr_save_p
4528 && info
->vrsave_mask
== 0
4536 /* Return the number of instructions it takes to form a constant in an
4537 integer register. */
4540 num_insns_constant_wide (HOST_WIDE_INT value
)
4542 /* signed constant loadable with addi */
4543 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4546 /* constant loadable with addis */
4547 else if ((value
& 0xffff) == 0
4548 && (value
>> 31 == -1 || value
>> 31 == 0))
4551 else if (TARGET_POWERPC64
)
4553 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4554 HOST_WIDE_INT high
= value
>> 31;
4556 if (high
== 0 || high
== -1)
4562 return num_insns_constant_wide (high
) + 1;
4564 return num_insns_constant_wide (low
) + 1;
4566 return (num_insns_constant_wide (high
)
4567 + num_insns_constant_wide (low
) + 1);
4575 num_insns_constant (rtx op
, enum machine_mode mode
)
4577 HOST_WIDE_INT low
, high
;
4579 switch (GET_CODE (op
))
4582 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4583 && mask64_operand (op
, mode
))
4586 return num_insns_constant_wide (INTVAL (op
));
4589 if (mode
== SFmode
|| mode
== SDmode
)
4594 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4595 if (DECIMAL_FLOAT_MODE_P (mode
))
4596 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4598 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4599 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4605 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4606 if (DECIMAL_FLOAT_MODE_P (mode
))
4607 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4609 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4610 high
= l
[WORDS_BIG_ENDIAN
== 0];
4611 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4614 return (num_insns_constant_wide (low
)
4615 + num_insns_constant_wide (high
));
4618 if ((high
== 0 && low
>= 0)
4619 || (high
== -1 && low
< 0))
4620 return num_insns_constant_wide (low
);
4622 else if (mask64_operand (op
, mode
))
4626 return num_insns_constant_wide (high
) + 1;
4629 return (num_insns_constant_wide (high
)
4630 + num_insns_constant_wide (low
) + 1);
4638 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4639 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4640 corresponding element of the vector, but for V4SFmode and V2SFmode,
4641 the corresponding "float" is interpreted as an SImode integer. */
4644 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4648 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4649 gcc_assert (GET_MODE (op
) != V2DImode
4650 && GET_MODE (op
) != V2DFmode
);
4652 tmp
= CONST_VECTOR_ELT (op
, elt
);
4653 if (GET_MODE (op
) == V4SFmode
4654 || GET_MODE (op
) == V2SFmode
)
4655 tmp
= gen_lowpart (SImode
, tmp
);
4656 return INTVAL (tmp
);
4659 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4660 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4661 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4662 all items are set to the same value and contain COPIES replicas of the
4663 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4664 operand and the others are set to the value of the operand's msb. */
4667 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4669 enum machine_mode mode
= GET_MODE (op
);
4670 enum machine_mode inner
= GET_MODE_INNER (mode
);
4678 HOST_WIDE_INT splat_val
;
4679 HOST_WIDE_INT msb_val
;
4681 if (mode
== V2DImode
|| mode
== V2DFmode
)
4684 nunits
= GET_MODE_NUNITS (mode
);
4685 bitsize
= GET_MODE_BITSIZE (inner
);
4686 mask
= GET_MODE_MASK (inner
);
4688 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
4690 msb_val
= val
> 0 ? 0 : -1;
4692 /* Construct the value to be splatted, if possible. If not, return 0. */
4693 for (i
= 2; i
<= copies
; i
*= 2)
4695 HOST_WIDE_INT small_val
;
4697 small_val
= splat_val
>> bitsize
;
4699 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4701 splat_val
= small_val
;
4704 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4705 if (EASY_VECTOR_15 (splat_val
))
4708 /* Also check if we can splat, and then add the result to itself. Do so if
4709 the value is positive, of if the splat instruction is using OP's mode;
4710 for splat_val < 0, the splat and the add should use the same mode. */
4711 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
4712 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
4715 /* Also check if are loading up the most significant bit which can be done by
4716 loading up -1 and shifting the value left by -1. */
4717 else if (EASY_VECTOR_MSB (splat_val
, inner
))
4723 /* Check if VAL is present in every STEP-th element, and the
4724 other elements are filled with its most significant bit. */
4725 for (i
= 0; i
< nunits
- 1; ++i
)
4727 HOST_WIDE_INT desired_val
;
4728 if (((BYTES_BIG_ENDIAN
? i
+ 1 : i
) & (step
- 1)) == 0)
4731 desired_val
= msb_val
;
4733 if (desired_val
!= const_vector_elt_as_int (op
, i
))
4741 /* Return true if OP is of the given MODE and can be synthesized
4742 with a vspltisb, vspltish or vspltisw. */
4745 easy_altivec_constant (rtx op
, enum machine_mode mode
)
4747 unsigned step
, copies
;
4749 if (mode
== VOIDmode
)
4750 mode
= GET_MODE (op
);
4751 else if (mode
!= GET_MODE (op
))
4754 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4756 if (mode
== V2DFmode
)
4757 return zero_constant (op
, mode
);
4759 if (mode
== V2DImode
)
4761 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4763 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
4764 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
4767 if (zero_constant (op
, mode
))
4770 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
4771 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
4777 /* Start with a vspltisw. */
4778 step
= GET_MODE_NUNITS (mode
) / 4;
4781 if (vspltis_constant (op
, step
, copies
))
4784 /* Then try with a vspltish. */
4790 if (vspltis_constant (op
, step
, copies
))
4793 /* And finally a vspltisb. */
4799 if (vspltis_constant (op
, step
, copies
))
4805 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4806 result is OP. Abort if it is not possible. */
4809 gen_easy_altivec_constant (rtx op
)
4811 enum machine_mode mode
= GET_MODE (op
);
4812 int nunits
= GET_MODE_NUNITS (mode
);
4813 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
4814 unsigned step
= nunits
/ 4;
4815 unsigned copies
= 1;
4817 /* Start with a vspltisw. */
4818 if (vspltis_constant (op
, step
, copies
))
4819 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
4821 /* Then try with a vspltish. */
4827 if (vspltis_constant (op
, step
, copies
))
4828 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
4830 /* And finally a vspltisb. */
4836 if (vspltis_constant (op
, step
, copies
))
4837 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
4843 output_vec_const_move (rtx
*operands
)
4846 enum machine_mode mode
;
4851 mode
= GET_MODE (dest
);
4855 if (zero_constant (vec
, mode
))
4856 return "xxlxor %x0,%x0,%x0";
4858 if (mode
== V2DImode
4859 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
4860 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
4861 return "vspltisw %0,-1";
4867 if (zero_constant (vec
, mode
))
4868 return "vxor %0,%0,%0";
4870 splat_vec
= gen_easy_altivec_constant (vec
);
4871 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
4872 operands
[1] = XEXP (splat_vec
, 0);
4873 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
4876 switch (GET_MODE (splat_vec
))
4879 return "vspltisw %0,%1";
4882 return "vspltish %0,%1";
4885 return "vspltisb %0,%1";
4892 gcc_assert (TARGET_SPE
);
4894 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4895 pattern of V1DI, V4HI, and V2SF.
4897 FIXME: We should probably return # and add post reload
4898 splitters for these, but this way is so easy ;-). */
4899 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
4900 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
4901 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
4902 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
4904 return "li %0,%1\n\tevmergelo %0,%0,%0";
4906 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4909 /* Initialize TARGET of vector PAIRED to VALS. */
4912 paired_expand_vector_init (rtx target
, rtx vals
)
4914 enum machine_mode mode
= GET_MODE (target
);
4915 int n_elts
= GET_MODE_NUNITS (mode
);
4917 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
4920 for (i
= 0; i
< n_elts
; ++i
)
4922 x
= XVECEXP (vals
, 0, i
);
4923 if (!(CONST_INT_P (x
)
4924 || GET_CODE (x
) == CONST_DOUBLE
4925 || GET_CODE (x
) == CONST_FIXED
))
4930 /* Load from constant pool. */
4931 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
4937 /* The vector is initialized only with non-constants. */
4938 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
4939 XVECEXP (vals
, 0, 1));
4941 emit_move_insn (target
, new_rtx
);
4945 /* One field is non-constant and the other one is a constant. Load the
4946 constant from the constant pool and use ps_merge instruction to
4947 construct the whole vector. */
4948 op1
= XVECEXP (vals
, 0, 0);
4949 op2
= XVECEXP (vals
, 0, 1);
4951 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
4953 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
4954 emit_move_insn (tmp
, constant_op
);
4956 if (CONSTANT_P (op1
))
4957 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
4959 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
4961 emit_move_insn (target
, new_rtx
);
4965 paired_expand_vector_move (rtx operands
[])
4967 rtx op0
= operands
[0], op1
= operands
[1];
4969 emit_move_insn (op0
, op1
);
4972 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4973 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4974 operands for the relation operation COND. This is a recursive
4978 paired_emit_vector_compare (enum rtx_code rcode
,
4979 rtx dest
, rtx op0
, rtx op1
,
4980 rtx cc_op0
, rtx cc_op1
)
4982 rtx tmp
= gen_reg_rtx (V2SFmode
);
4985 gcc_assert (TARGET_PAIRED_FLOAT
);
4986 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
4992 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4996 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4997 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5001 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5004 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5007 tmp1
= gen_reg_rtx (V2SFmode
);
5008 max
= gen_reg_rtx (V2SFmode
);
5009 min
= gen_reg_rtx (V2SFmode
);
5010 gen_reg_rtx (V2SFmode
);
5012 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5013 emit_insn (gen_selv2sf4
5014 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5015 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5016 emit_insn (gen_selv2sf4
5017 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5018 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5019 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5022 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5025 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5028 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5031 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5034 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5043 /* Emit vector conditional expression.
5044 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5045 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5048 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5049 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5051 enum rtx_code rcode
= GET_CODE (cond
);
5053 if (!TARGET_PAIRED_FLOAT
)
5056 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5061 /* Initialize vector TARGET to VALS. */
5064 rs6000_expand_vector_init (rtx target
, rtx vals
)
5066 enum machine_mode mode
= GET_MODE (target
);
5067 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5068 int n_elts
= GET_MODE_NUNITS (mode
);
5069 int n_var
= 0, one_var
= -1;
5070 bool all_same
= true, all_const_zero
= true;
5074 for (i
= 0; i
< n_elts
; ++i
)
5076 x
= XVECEXP (vals
, 0, i
);
5077 if (!(CONST_INT_P (x
)
5078 || GET_CODE (x
) == CONST_DOUBLE
5079 || GET_CODE (x
) == CONST_FIXED
))
5080 ++n_var
, one_var
= i
;
5081 else if (x
!= CONST0_RTX (inner_mode
))
5082 all_const_zero
= false;
5084 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5090 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5091 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5092 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5094 /* Zero register. */
5095 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5096 gen_rtx_XOR (mode
, target
, target
)));
5099 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5101 /* Splat immediate. */
5102 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5107 /* Load from constant pool. */
5108 emit_move_insn (target
, const_vec
);
5113 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5114 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5116 rtx op0
= XVECEXP (vals
, 0, 0);
5117 rtx op1
= XVECEXP (vals
, 0, 1);
5120 if (!MEM_P (op0
) && !REG_P (op0
))
5121 op0
= force_reg (inner_mode
, op0
);
5122 if (mode
== V2DFmode
)
5123 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5125 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5129 op0
= force_reg (inner_mode
, op0
);
5130 op1
= force_reg (inner_mode
, op1
);
5131 if (mode
== V2DFmode
)
5132 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5134 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5139 /* With single precision floating point on VSX, know that internally single
5140 precision is actually represented as a double, and either make 2 V2DF
5141 vectors, and convert these vectors to single precision, or do one
5142 conversion, and splat the result to the other elements. */
5143 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5147 rtx freg
= gen_reg_rtx (V4SFmode
);
5148 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5149 rtx cvt
= ((TARGET_XSCVDPSPN
)
5150 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5151 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5154 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
5158 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5159 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5160 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5161 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5162 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5163 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5164 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5165 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5167 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5168 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5169 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5170 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5171 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5176 /* Store value to stack temp. Load vector element. Splat. However, splat
5177 of 64-bit items is not supported on Altivec. */
5178 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5181 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5182 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5183 XVECEXP (vals
, 0, 0));
5184 x
= gen_rtx_UNSPEC (VOIDmode
,
5185 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5186 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5188 gen_rtx_SET (VOIDmode
,
5191 field
= (BYTES_BIG_ENDIAN
? const0_rtx
5192 : GEN_INT (GET_MODE_NUNITS (mode
) - 1));
5193 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5194 gen_rtx_PARALLEL (VOIDmode
,
5195 gen_rtvec (1, field
)));
5196 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5197 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5201 /* One field is non-constant. Load constant then overwrite
5205 rtx copy
= copy_rtx (vals
);
5207 /* Load constant part of vector, substitute neighboring value for
5209 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5210 rs6000_expand_vector_init (target
, copy
);
5212 /* Insert variable. */
5213 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5217 /* Construct the vector in memory one field at a time
5218 and load the whole vector. */
5219 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5220 for (i
= 0; i
< n_elts
; i
++)
5221 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5222 i
* GET_MODE_SIZE (inner_mode
)),
5223 XVECEXP (vals
, 0, i
));
5224 emit_move_insn (target
, mem
);
5227 /* Set field ELT of TARGET to VAL. */
5230 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5232 enum machine_mode mode
= GET_MODE (target
);
5233 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5234 rtx reg
= gen_reg_rtx (mode
);
5236 int width
= GET_MODE_SIZE (inner_mode
);
5239 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5241 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5242 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5243 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5247 /* Load single variable value. */
5248 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5249 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5250 x
= gen_rtx_UNSPEC (VOIDmode
,
5251 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5252 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5254 gen_rtx_SET (VOIDmode
,
5258 /* Linear sequence. */
5259 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5260 for (i
= 0; i
< 16; ++i
)
5261 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5263 /* Set permute mask to insert element into target. */
5264 for (i
= 0; i
< width
; ++i
)
5265 XVECEXP (mask
, 0, elt
*width
+ i
)
5266 = GEN_INT (i
+ 0x10);
5267 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5268 x
= gen_rtx_UNSPEC (mode
,
5269 gen_rtvec (3, target
, reg
,
5270 force_reg (V16QImode
, x
)),
5272 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5275 /* Extract field ELT from VEC into TARGET. */
5278 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5280 enum machine_mode mode
= GET_MODE (vec
);
5281 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5284 if (VECTOR_MEM_VSX_P (mode
))
5291 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5294 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5297 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5302 /* Allocate mode-sized buffer. */
5303 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5305 emit_move_insn (mem
, vec
);
5307 /* Add offset to field within buffer matching vector element. */
5308 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5310 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5313 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5314 implement ANDing by the mask IN. */
5316 build_mask64_2_operands (rtx in
, rtx
*out
)
5318 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5321 gcc_assert (GET_CODE (in
) == CONST_INT
);
5326 /* Assume c initially something like 0x00fff000000fffff. The idea
5327 is to rotate the word so that the middle ^^^^^^ group of zeros
5328 is at the MS end and can be cleared with an rldicl mask. We then
5329 rotate back and clear off the MS ^^ group of zeros with a
5331 c
= ~c
; /* c == 0xff000ffffff00000 */
5332 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5333 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5334 c
= ~c
; /* c == 0x00fff000000fffff */
5335 c
&= -lsb
; /* c == 0x00fff00000000000 */
5336 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5337 c
= ~c
; /* c == 0xff000fffffffffff */
5338 c
&= -lsb
; /* c == 0xff00000000000000 */
5340 while ((lsb
>>= 1) != 0)
5341 shift
++; /* shift == 44 on exit from loop */
5342 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5343 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5344 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5348 /* Assume c initially something like 0xff000f0000000000. The idea
5349 is to rotate the word so that the ^^^ middle group of zeros
5350 is at the LS end and can be cleared with an rldicr mask. We then
5351 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5353 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5354 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5355 c
= ~c
; /* c == 0x00fff0ffffffffff */
5356 c
&= -lsb
; /* c == 0x00fff00000000000 */
5357 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5358 c
= ~c
; /* c == 0xff000fffffffffff */
5359 c
&= -lsb
; /* c == 0xff00000000000000 */
5361 while ((lsb
>>= 1) != 0)
5362 shift
++; /* shift == 44 on exit from loop */
5363 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5364 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5365 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5368 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5369 masks will be all 1's. We are guaranteed more than one transition. */
5370 out
[0] = GEN_INT (64 - shift
);
5371 out
[1] = GEN_INT (m1
);
5372 out
[2] = GEN_INT (shift
);
5373 out
[3] = GEN_INT (m2
);
5376 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5379 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5381 if (TARGET_E500_DOUBLE
)
5383 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5384 subreg:TI and reg:TF. Decimal float modes are like integer
5385 modes (only low part of each register used) for this
5387 if (GET_CODE (op
) == SUBREG
5388 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5389 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5390 && REG_P (SUBREG_REG (op
))
5391 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5392 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5395 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5397 if (GET_CODE (op
) == SUBREG
5398 && (mode
== DFmode
|| mode
== TFmode
)
5399 && REG_P (SUBREG_REG (op
))
5400 && (GET_MODE (SUBREG_REG (op
)) == DImode
5401 || GET_MODE (SUBREG_REG (op
)) == TImode
5402 || GET_MODE (SUBREG_REG (op
)) == PTImode
5403 || GET_MODE (SUBREG_REG (op
)) == DDmode
5404 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5409 && GET_CODE (op
) == SUBREG
5411 && REG_P (SUBREG_REG (op
))
5412 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5418 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5419 selects whether the alignment is abi mandated, optional, or
5420 both abi and optional alignment. */
5423 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5425 if (how
!= align_opt
)
5427 if (TREE_CODE (type
) == VECTOR_TYPE
)
5429 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5430 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5435 else if (align
< 128)
5438 else if (TARGET_E500_DOUBLE
5439 && TREE_CODE (type
) == REAL_TYPE
5440 && TYPE_MODE (type
) == DFmode
)
5447 if (how
!= align_abi
)
5449 if (TREE_CODE (type
) == ARRAY_TYPE
5450 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5452 if (align
< BITS_PER_WORD
)
5453 align
= BITS_PER_WORD
;
5460 /* AIX increases natural record alignment to doubleword if the first
5461 field is an FP double while the FP fields remain word aligned. */
5464 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5465 unsigned int specified
)
5467 unsigned int align
= MAX (computed
, specified
);
5468 tree field
= TYPE_FIELDS (type
);
5470 /* Skip all non field decls */
5471 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5472 field
= DECL_CHAIN (field
);
5474 if (field
!= NULL
&& field
!= type
)
5476 type
= TREE_TYPE (field
);
5477 while (TREE_CODE (type
) == ARRAY_TYPE
)
5478 type
= TREE_TYPE (type
);
5480 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5481 align
= MAX (align
, 64);
5487 /* Darwin increases record alignment to the natural alignment of
5491 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5492 unsigned int specified
)
5494 unsigned int align
= MAX (computed
, specified
);
5496 if (TYPE_PACKED (type
))
5499 /* Find the first field, looking down into aggregates. */
5501 tree field
= TYPE_FIELDS (type
);
5502 /* Skip all non field decls */
5503 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5504 field
= DECL_CHAIN (field
);
5507 /* A packed field does not contribute any extra alignment. */
5508 if (DECL_PACKED (field
))
5510 type
= TREE_TYPE (field
);
5511 while (TREE_CODE (type
) == ARRAY_TYPE
)
5512 type
= TREE_TYPE (type
);
5513 } while (AGGREGATE_TYPE_P (type
));
5515 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5516 align
= MAX (align
, TYPE_ALIGN (type
));
5521 /* Return 1 for an operand in small memory on V.4/eabi. */
5524 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5525 enum machine_mode mode ATTRIBUTE_UNUSED
)
5530 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5533 if (DEFAULT_ABI
!= ABI_V4
)
5536 /* Vector and float memory instructions have a limited offset on the
5537 SPE, so using a vector or float variable directly as an operand is
5540 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5543 if (GET_CODE (op
) == SYMBOL_REF
)
5546 else if (GET_CODE (op
) != CONST
5547 || GET_CODE (XEXP (op
, 0)) != PLUS
5548 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5549 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5554 rtx sum
= XEXP (op
, 0);
5555 HOST_WIDE_INT summand
;
5557 /* We have to be careful here, because it is the referenced address
5558 that must be 32k from _SDA_BASE_, not just the symbol. */
5559 summand
= INTVAL (XEXP (sum
, 1));
5560 if (summand
< 0 || summand
> g_switch_value
)
5563 sym_ref
= XEXP (sum
, 0);
5566 return SYMBOL_REF_SMALL_P (sym_ref
);
5572 /* Return true if either operand is a general purpose register. */
5575 gpr_or_gpr_p (rtx op0
, rtx op1
)
5577 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5578 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5581 /* Return true if this is a move direct operation between GPR registers and
5582 floating point/VSX registers. */
5585 direct_move_p (rtx op0
, rtx op1
)
5589 if (!REG_P (op0
) || !REG_P (op1
))
5592 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
5595 regno0
= REGNO (op0
);
5596 regno1
= REGNO (op1
);
5597 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
5600 if (INT_REGNO_P (regno0
))
5601 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
5603 else if (INT_REGNO_P (regno1
))
5605 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
5608 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
5615 /* Return true if this is a load or store quad operation. */
5618 quad_load_store_p (rtx op0
, rtx op1
)
5622 if (!TARGET_QUAD_MEMORY
)
5625 else if (REG_P (op0
) && MEM_P (op1
))
5626 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
5627 && quad_memory_operand (op1
, GET_MODE (op1
))
5628 && !reg_overlap_mentioned_p (op0
, op1
));
5630 else if (MEM_P (op0
) && REG_P (op1
))
5631 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
5632 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
5637 if (TARGET_DEBUG_ADDR
)
5639 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
5640 ret
? "true" : "false");
5641 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
5647 /* Given an address, return a constant offset term if one exists. */
5650 address_offset (rtx op
)
5652 if (GET_CODE (op
) == PRE_INC
5653 || GET_CODE (op
) == PRE_DEC
)
5655 else if (GET_CODE (op
) == PRE_MODIFY
5656 || GET_CODE (op
) == LO_SUM
)
5659 if (GET_CODE (op
) == CONST
)
5662 if (GET_CODE (op
) == PLUS
)
5665 if (CONST_INT_P (op
))
5671 /* Return true if the MEM operand is a memory operand suitable for use
5672 with a (full width, possibly multiple) gpr load/store. On
5673 powerpc64 this means the offset must be divisible by 4.
5674 Implements 'Y' constraint.
5676 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5677 a constraint function we know the operand has satisfied a suitable
5678 memory predicate. Also accept some odd rtl generated by reload
5679 (see rs6000_legitimize_reload_address for various forms). It is
5680 important that reload rtl be accepted by appropriate constraints
5681 but not by the operand predicate.
5683 Offsetting a lo_sum should not be allowed, except where we know by
5684 alignment that a 32k boundary is not crossed, but see the ???
5685 comment in rs6000_legitimize_reload_address. Note that by
5686 "offsetting" here we mean a further offset to access parts of the
5687 MEM. It's fine to have a lo_sum where the inner address is offset
5688 from a sym, since the same sym+offset will appear in the high part
5689 of the address calculation. */
5692 mem_operand_gpr (rtx op
, enum machine_mode mode
)
5694 unsigned HOST_WIDE_INT offset
;
5696 rtx addr
= XEXP (op
, 0);
5698 op
= address_offset (addr
);
5702 offset
= INTVAL (op
);
5703 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
5706 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
5707 gcc_assert (extra
>= 0);
5709 if (GET_CODE (addr
) == LO_SUM
)
5710 /* For lo_sum addresses, we must allow any offset except one that
5711 causes a wrap, so test only the low 16 bits. */
5712 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
5714 return offset
+ 0x8000 < 0x10000u
- extra
;
5717 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5720 reg_offset_addressing_ok_p (enum machine_mode mode
)
5731 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
5732 TImode is not a vector mode, if we want to use the VSX registers to
5733 move it around, we need to restrict ourselves to reg+reg
5735 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
5743 /* Paired vector modes. Only reg+reg addressing is valid. */
5744 if (TARGET_PAIRED_FLOAT
)
5749 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
5750 addressing for the LFIWZX and STFIWX instructions. */
5751 if (TARGET_NO_SDMODE_STACK
)
5763 virtual_stack_registers_memory_p (rtx op
)
5767 if (GET_CODE (op
) == REG
)
5768 regnum
= REGNO (op
);
5770 else if (GET_CODE (op
) == PLUS
5771 && GET_CODE (XEXP (op
, 0)) == REG
5772 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
5773 regnum
= REGNO (XEXP (op
, 0));
5778 return (regnum
>= FIRST_VIRTUAL_REGISTER
5779 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
5782 /* Return true if a MODE sized memory accesses to OP plus OFFSET
5783 is known to not straddle a 32k boundary. */
5786 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
5787 enum machine_mode mode
)
5790 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
5792 if (GET_CODE (op
) != SYMBOL_REF
)
5795 dsize
= GET_MODE_SIZE (mode
);
5796 decl
= SYMBOL_REF_DECL (op
);
5802 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5803 replacing memory addresses with an anchor plus offset. We
5804 could find the decl by rummaging around in the block->objects
5805 VEC for the given offset but that seems like too much work. */
5806 dalign
= BITS_PER_UNIT
;
5807 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
5808 && SYMBOL_REF_ANCHOR_P (op
)
5809 && SYMBOL_REF_BLOCK (op
) != NULL
)
5811 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
5813 dalign
= block
->alignment
;
5814 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
5816 else if (CONSTANT_POOL_ADDRESS_P (op
))
5818 /* It would be nice to have get_pool_align().. */
5819 enum machine_mode cmode
= get_pool_mode (op
);
5821 dalign
= GET_MODE_ALIGNMENT (cmode
);
5824 else if (DECL_P (decl
))
5826 dalign
= DECL_ALIGN (decl
);
5830 /* Allow BLKmode when the entire object is known to not
5831 cross a 32k boundary. */
5832 if (!DECL_SIZE_UNIT (decl
))
5835 if (!host_integerp (DECL_SIZE_UNIT (decl
), 1))
5838 dsize
= tree_low_cst (DECL_SIZE_UNIT (decl
), 1);
5842 return dalign
/ BITS_PER_UNIT
>= dsize
;
5847 type
= TREE_TYPE (decl
);
5849 dalign
= TYPE_ALIGN (type
);
5850 if (CONSTANT_CLASS_P (decl
))
5851 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
5853 dalign
= DATA_ALIGNMENT (decl
, dalign
);
5857 /* BLKmode, check the entire object. */
5858 if (TREE_CODE (decl
) == STRING_CST
)
5859 dsize
= TREE_STRING_LENGTH (decl
);
5860 else if (TYPE_SIZE_UNIT (type
)
5861 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5862 dsize
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
5868 return dalign
/ BITS_PER_UNIT
>= dsize
;
5872 /* Find how many bits of the alignment we know for this access. */
5873 mask
= dalign
/ BITS_PER_UNIT
- 1;
5874 lsb
= offset
& -offset
;
5878 return dalign
>= dsize
;
5882 constant_pool_expr_p (rtx op
)
5886 split_const (op
, &base
, &offset
);
5887 return (GET_CODE (base
) == SYMBOL_REF
5888 && CONSTANT_POOL_ADDRESS_P (base
)
5889 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
5892 static const_rtx tocrel_base
, tocrel_offset
;
5894 /* Return true if OP is a toc pointer relative address (the output
5895 of create_TOC_reference). If STRICT, do not match high part or
5896 non-split -mcmodel=large/medium toc pointer relative addresses. */
5899 toc_relative_expr_p (const_rtx op
, bool strict
)
5904 if (TARGET_CMODEL
!= CMODEL_SMALL
)
5906 /* Only match the low part. */
5907 if (GET_CODE (op
) == LO_SUM
5908 && REG_P (XEXP (op
, 0))
5909 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
5916 tocrel_offset
= const0_rtx
;
5917 if (GET_CODE (op
) == PLUS
&& CONST_INT_P (XEXP (op
, 1)))
5919 tocrel_base
= XEXP (op
, 0);
5920 tocrel_offset
= XEXP (op
, 1);
5923 return (GET_CODE (tocrel_base
) == UNSPEC
5924 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
5927 /* Return true if X is a constant pool address, and also for cmodel=medium
5928 if X is a toc-relative address known to be offsettable within MODE. */
5931 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
5934 return (toc_relative_expr_p (x
, strict
)
5935 && (TARGET_CMODEL
!= CMODEL_MEDIUM
5936 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
5938 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
5939 INTVAL (tocrel_offset
), mode
)));
5943 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
5945 return (DEFAULT_ABI
== ABI_V4
5946 && !flag_pic
&& !TARGET_TOC
5947 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
5948 && small_data_operand (x
, mode
));
5951 /* SPE offset addressing is limited to 5-bits worth of double words. */
5952 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5955 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
5956 bool strict
, bool worst_case
)
5958 unsigned HOST_WIDE_INT offset
;
5961 if (GET_CODE (x
) != PLUS
)
5963 if (!REG_P (XEXP (x
, 0)))
5965 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5967 if (!reg_offset_addressing_ok_p (mode
))
5968 return virtual_stack_registers_memory_p (x
);
5969 if (legitimate_constant_pool_address_p (x
, mode
, strict
))
5971 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5974 offset
= INTVAL (XEXP (x
, 1));
5982 /* SPE vector modes. */
5983 return SPE_CONST_OFFSET_OK (offset
);
5988 /* On e500v2, we may have:
5990 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5992 Which gets addressed with evldd instructions. */
5993 if (TARGET_E500_DOUBLE
)
5994 return SPE_CONST_OFFSET_OK (offset
);
5996 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5998 if (VECTOR_MEM_VSX_P (mode
))
6003 if (!TARGET_POWERPC64
)
6005 else if (offset
& 3)
6013 if (TARGET_E500_DOUBLE
)
6014 return (SPE_CONST_OFFSET_OK (offset
)
6015 && SPE_CONST_OFFSET_OK (offset
+ 8));
6020 if (!TARGET_POWERPC64
)
6022 else if (offset
& 3)
6031 return offset
< 0x10000 - extra
;
6035 legitimate_indexed_address_p (rtx x
, int strict
)
6039 if (GET_CODE (x
) != PLUS
)
6045 /* Recognize the rtl generated by reload which we know will later be
6046 replaced with proper base and index regs. */
6048 && reload_in_progress
6049 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6053 return (REG_P (op0
) && REG_P (op1
)
6054 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6055 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6056 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6057 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6061 avoiding_indexed_address_p (enum machine_mode mode
)
6063 /* Avoid indexed addressing for modes that have non-indexed
6064 load/store instruction forms. */
6065 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6069 legitimate_indirect_address_p (rtx x
, int strict
)
6071 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6075 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6077 if (!TARGET_MACHO
|| !flag_pic
6078 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6082 if (GET_CODE (x
) != LO_SUM
)
6084 if (GET_CODE (XEXP (x
, 0)) != REG
)
6086 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6090 return CONSTANT_P (x
);
6094 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6096 if (GET_CODE (x
) != LO_SUM
)
6098 if (GET_CODE (XEXP (x
, 0)) != REG
)
6100 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6102 /* Restrict addressing for DI because of our SUBREG hackery. */
6103 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6107 if (TARGET_ELF
|| TARGET_MACHO
)
6109 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
6113 if (GET_MODE_NUNITS (mode
) != 1)
6115 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6116 && !(/* ??? Assume floating point reg based on mode? */
6117 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6118 && (mode
== DFmode
|| mode
== DDmode
)))
6121 return CONSTANT_P (x
);
6128 /* Try machine-dependent ways of modifying an illegitimate address
6129 to be legitimate. If we find one, return the new, valid address.
6130 This is used from only one place: `memory_address' in explow.c.
6132 OLDX is the address as it was before break_out_memory_refs was
6133 called. In some cases it is useful to look at this to decide what
6136 It is always safe for this function to do nothing. It exists to
6137 recognize opportunities to optimize the output.
6139 On RS/6000, first check for the sum of a register with a constant
6140 integer that is out of range. If so, generate code to add the
6141 constant with the low-order 16 bits masked to the register and force
6142 this result into another register (this can be done with `cau').
6143 Then generate an address of REG+(CONST&0xffff), allowing for the
6144 possibility of bit 16 being a one.
6146 Then check for the sum of a register and something not constant, try to
6147 load the other things into a register and return the sum. */
6150 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6151 enum machine_mode mode
)
6155 if (!reg_offset_addressing_ok_p (mode
))
6157 if (virtual_stack_registers_memory_p (x
))
6160 /* In theory we should not be seeing addresses of the form reg+0,
6161 but just in case it is generated, optimize it away. */
6162 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6163 return force_reg (Pmode
, XEXP (x
, 0));
6165 /* For TImode with load/store quad, restrict addresses to just a single
6166 pointer, so it works with both GPRs and VSX registers. */
6167 /* Make sure both operands are registers. */
6168 else if (GET_CODE (x
) == PLUS
6169 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6170 return gen_rtx_PLUS (Pmode
,
6171 force_reg (Pmode
, XEXP (x
, 0)),
6172 force_reg (Pmode
, XEXP (x
, 1)));
6174 return force_reg (Pmode
, x
);
6176 if (GET_CODE (x
) == SYMBOL_REF
)
6178 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6180 return rs6000_legitimize_tls_address (x
, model
);
6190 /* As in legitimate_offset_address_p we do not assume
6191 worst-case. The mode here is just a hint as to the registers
6192 used. A TImode is usually in gprs, but may actually be in
6193 fprs. Leave worst-case scenario for reload to handle via
6194 insn constraints. PTImode is only GPRs. */
6201 if (GET_CODE (x
) == PLUS
6202 && GET_CODE (XEXP (x
, 0)) == REG
6203 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6204 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6206 && !(SPE_VECTOR_MODE (mode
)
6207 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6209 HOST_WIDE_INT high_int
, low_int
;
6211 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6212 if (low_int
>= 0x8000 - extra
)
6214 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6215 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6216 GEN_INT (high_int
)), 0);
6217 return plus_constant (Pmode
, sum
, low_int
);
6219 else if (GET_CODE (x
) == PLUS
6220 && GET_CODE (XEXP (x
, 0)) == REG
6221 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6222 && GET_MODE_NUNITS (mode
) == 1
6223 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6224 || (/* ??? Assume floating point reg based on mode? */
6225 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6226 && (mode
== DFmode
|| mode
== DDmode
)))
6227 && !avoiding_indexed_address_p (mode
))
6229 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6230 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6232 else if (SPE_VECTOR_MODE (mode
)
6233 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6237 /* We accept [reg + reg] and [reg + OFFSET]. */
6239 if (GET_CODE (x
) == PLUS
)
6241 rtx op1
= XEXP (x
, 0);
6242 rtx op2
= XEXP (x
, 1);
6245 op1
= force_reg (Pmode
, op1
);
6247 if (GET_CODE (op2
) != REG
6248 && (GET_CODE (op2
) != CONST_INT
6249 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6250 || (GET_MODE_SIZE (mode
) > 8
6251 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6252 op2
= force_reg (Pmode
, op2
);
6254 /* We can't always do [reg + reg] for these, because [reg +
6255 reg + offset] is not a legitimate addressing mode. */
6256 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6258 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6259 return force_reg (Pmode
, y
);
6264 return force_reg (Pmode
, x
);
6266 else if ((TARGET_ELF
6268 || !MACHO_DYNAMIC_NO_PIC_P
6274 && GET_CODE (x
) != CONST_INT
6275 && GET_CODE (x
) != CONST_DOUBLE
6277 && GET_MODE_NUNITS (mode
) == 1
6278 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6279 || (/* ??? Assume floating point reg based on mode? */
6280 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6281 && (mode
== DFmode
|| mode
== DDmode
))))
6283 rtx reg
= gen_reg_rtx (Pmode
);
6285 emit_insn (gen_elf_high (reg
, x
));
6287 emit_insn (gen_macho_high (reg
, x
));
6288 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6291 && GET_CODE (x
) == SYMBOL_REF
6292 && constant_pool_expr_p (x
)
6293 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6294 return create_TOC_reference (x
, NULL_RTX
);
6299 /* Debug version of rs6000_legitimize_address. */
6301 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6307 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6308 insns
= get_insns ();
6314 "\nrs6000_legitimize_address: mode %s, old code %s, "
6315 "new code %s, modified\n",
6316 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6317 GET_RTX_NAME (GET_CODE (ret
)));
6319 fprintf (stderr
, "Original address:\n");
6322 fprintf (stderr
, "oldx:\n");
6325 fprintf (stderr
, "New address:\n");
6330 fprintf (stderr
, "Insns added:\n");
6331 debug_rtx_list (insns
, 20);
6337 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6338 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6349 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6350 We need to emit DTP-relative relocations. */
6352 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6354 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6359 fputs ("\t.long\t", file
);
6362 fputs (DOUBLE_INT_ASM_OP
, file
);
6367 output_addr_const (file
, x
);
6368 fputs ("@dtprel+0x8000", file
);
6371 /* In the name of slightly smaller debug output, and to cater to
6372 general assembler lossage, recognize various UNSPEC sequences
6373 and turn them back into a direct symbol reference. */
6376 rs6000_delegitimize_address (rtx orig_x
)
6380 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6386 if (TARGET_CMODEL
!= CMODEL_SMALL
6387 && GET_CODE (y
) == LO_SUM
)
6391 if (GET_CODE (y
) == PLUS
6392 && GET_MODE (y
) == Pmode
6393 && CONST_INT_P (XEXP (y
, 1)))
6395 offset
= XEXP (y
, 1);
6399 if (GET_CODE (y
) == UNSPEC
6400 && XINT (y
, 1) == UNSPEC_TOCREL
)
6402 #ifdef ENABLE_CHECKING
6403 if (REG_P (XVECEXP (y
, 0, 1))
6404 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6408 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6410 /* Weirdness alert. df_note_compute can replace r2 with a
6411 debug_expr when this unspec is in a debug_insn.
6412 Seen in gcc.dg/pr51957-1.c */
6420 y
= XVECEXP (y
, 0, 0);
6423 /* Do not associate thread-local symbols with the original
6424 constant pool symbol. */
6426 && GET_CODE (y
) == SYMBOL_REF
6427 && CONSTANT_POOL_ADDRESS_P (y
)
6428 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
6432 if (offset
!= NULL_RTX
)
6433 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6434 if (!MEM_P (orig_x
))
6437 return replace_equiv_address_nv (orig_x
, y
);
6441 && GET_CODE (orig_x
) == LO_SUM
6442 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6444 y
= XEXP (XEXP (orig_x
, 1), 0);
6445 if (GET_CODE (y
) == UNSPEC
6446 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6447 return XVECEXP (y
, 0, 0);
6453 /* Return true if X shouldn't be emitted into the debug info.
6454 The linker doesn't like .toc section references from
6455 .debug_* sections, so reject .toc section symbols. */
6458 rs6000_const_not_ok_for_debug_p (rtx x
)
6460 if (GET_CODE (x
) == SYMBOL_REF
6461 && CONSTANT_POOL_ADDRESS_P (x
))
6463 rtx c
= get_pool_constant (x
);
6464 enum machine_mode cmode
= get_pool_mode (x
);
6465 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6472 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6474 static GTY(()) rtx rs6000_tls_symbol
;
6476 rs6000_tls_get_addr (void)
6478 if (!rs6000_tls_symbol
)
6479 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6481 return rs6000_tls_symbol
;
6484 /* Construct the SYMBOL_REF for TLS GOT references. */
6486 static GTY(()) rtx rs6000_got_symbol
;
6488 rs6000_got_sym (void)
6490 if (!rs6000_got_symbol
)
6492 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6493 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6494 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6497 return rs6000_got_symbol
;
6500 /* AIX Thread-Local Address support. */
6503 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6505 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6509 name
= XSTR (addr
, 0);
6510 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6511 or the symbol will be in TLS private data section. */
6512 if (name
[strlen (name
) - 1] != ']'
6513 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6514 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6516 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6517 strcpy (tlsname
, name
);
6519 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6520 tlsaddr
= copy_rtx (addr
);
6521 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6526 /* Place addr into TOC constant pool. */
6527 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6529 /* Output the TOC entry and create the MEM referencing the value. */
6530 if (constant_pool_expr_p (XEXP (sym
, 0))
6531 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6533 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6534 mem
= gen_const_mem (Pmode
, tocref
);
6535 set_mem_alias_set (mem
, get_TOC_alias_set ());
6540 /* Use global-dynamic for local-dynamic. */
6541 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6542 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6544 /* Create new TOC reference for @m symbol. */
6545 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6546 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6547 strcpy (tlsname
, "*LCM");
6548 strcat (tlsname
, name
+ 3);
6549 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6550 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6551 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6552 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6553 set_mem_alias_set (modmem
, get_TOC_alias_set ());
6555 rtx modreg
= gen_reg_rtx (Pmode
);
6556 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
6558 tmpreg
= gen_reg_rtx (Pmode
);
6559 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6561 dest
= gen_reg_rtx (Pmode
);
6563 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
6565 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
6568 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
6569 else if (TARGET_32BIT
)
6571 tlsreg
= gen_reg_rtx (SImode
);
6572 emit_insn (gen_tls_get_tpointer (tlsreg
));
6575 tlsreg
= gen_rtx_REG (DImode
, 13);
6577 /* Load the TOC value into temporary register. */
6578 tmpreg
= gen_reg_rtx (Pmode
);
6579 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6580 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
6581 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
6583 /* Add TOC symbol value to TLS pointer. */
6584 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
6589 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
6590 this (thread-local) address. */
6593 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6598 return rs6000_legitimize_tls_address_aix (addr
, model
);
6600 dest
= gen_reg_rtx (Pmode
);
6601 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
6607 tlsreg
= gen_rtx_REG (Pmode
, 13);
6608 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
6612 tlsreg
= gen_rtx_REG (Pmode
, 2);
6613 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
6617 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
6621 tmp
= gen_reg_rtx (Pmode
);
6624 tlsreg
= gen_rtx_REG (Pmode
, 13);
6625 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6629 tlsreg
= gen_rtx_REG (Pmode
, 2);
6630 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6634 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6636 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6641 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6643 /* We currently use relocations like @got@tlsgd for tls, which
6644 means the linker will handle allocation of tls entries, placing
6645 them in the .got section. So use a pointer to the .got section,
6646 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6647 or to secondary GOT sections used by 32-bit -fPIC. */
6649 got
= gen_rtx_REG (Pmode
, 2);
6653 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6656 rtx gsym
= rs6000_got_sym ();
6657 got
= gen_reg_rtx (Pmode
);
6659 rs6000_emit_move (got
, gsym
, Pmode
);
6664 tmp1
= gen_reg_rtx (Pmode
);
6665 tmp2
= gen_reg_rtx (Pmode
);
6666 mem
= gen_const_mem (Pmode
, tmp1
);
6667 lab
= gen_label_rtx ();
6668 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6669 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6670 if (TARGET_LINK_STACK
)
6671 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6672 emit_move_insn (tmp2
, mem
);
6673 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
6674 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
6679 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
6681 tga
= rs6000_tls_get_addr ();
6682 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
6683 1, const0_rtx
, Pmode
);
6685 r3
= gen_rtx_REG (Pmode
, 3);
6686 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6687 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
6688 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6689 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
6690 else if (DEFAULT_ABI
== ABI_V4
)
6691 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
6694 call_insn
= last_call_insn ();
6695 PATTERN (call_insn
) = insn
;
6696 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6697 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6698 pic_offset_table_rtx
);
6700 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
6702 tga
= rs6000_tls_get_addr ();
6703 tmp1
= gen_reg_rtx (Pmode
);
6704 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
6705 1, const0_rtx
, Pmode
);
6707 r3
= gen_rtx_REG (Pmode
, 3);
6708 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6709 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
6710 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6711 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
6712 else if (DEFAULT_ABI
== ABI_V4
)
6713 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
6716 call_insn
= last_call_insn ();
6717 PATTERN (call_insn
) = insn
;
6718 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6719 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6720 pic_offset_table_rtx
);
6722 if (rs6000_tls_size
== 16)
6725 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
6727 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
6729 else if (rs6000_tls_size
== 32)
6731 tmp2
= gen_reg_rtx (Pmode
);
6733 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
6735 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
6738 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
6740 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
6744 tmp2
= gen_reg_rtx (Pmode
);
6746 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
6748 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
6750 insn
= gen_rtx_SET (Pmode
, dest
,
6751 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
6757 /* IE, or 64-bit offset LE. */
6758 tmp2
= gen_reg_rtx (Pmode
);
6760 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
6762 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
6765 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
6767 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
6775 /* Return 1 if X contains a thread-local symbol. */
6778 rs6000_tls_referenced_p (rtx x
)
6780 if (! TARGET_HAVE_TLS
)
6783 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
6786 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6789 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
6791 if (GET_CODE (x
) == HIGH
6792 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6795 /* A TLS symbol in the TOC cannot contain a sum. */
6796 if (GET_CODE (x
) == CONST
6797 && GET_CODE (XEXP (x
, 0)) == PLUS
6798 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
6799 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
6802 /* Do not place an ELF TLS symbol in the constant pool. */
6803 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
6806 /* Return 1 if *X is a thread-local symbol. This is the same as
6807 rs6000_tls_symbol_ref except for the type of the unused argument. */
6810 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6812 return RS6000_SYMBOL_REF_TLS_P (*x
);
6815 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
6816 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
6817 can be addressed relative to the toc pointer. */
6820 use_toc_relative_ref (rtx sym
)
6822 return ((constant_pool_expr_p (sym
)
6823 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
6824 get_pool_mode (sym
)))
6825 || (TARGET_CMODEL
== CMODEL_MEDIUM
6826 && SYMBOL_REF_LOCAL_P (sym
)));
6829 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6830 replace the input X, or the original X if no replacement is called for.
6831 The output parameter *WIN is 1 if the calling macro should goto WIN,
6834 For RS/6000, we wish to handle large displacements off a base
6835 register by splitting the addend across an addiu/addis and the mem insn.
6836 This cuts number of extra insns needed from 3 to 1.
6838 On Darwin, we use this to generate code for floating point constants.
6839 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6840 The Darwin code is inside #if TARGET_MACHO because only then are the
6841 machopic_* functions defined. */
6843 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6844 int opnum
, int type
,
6845 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
6847 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6849 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6850 DFmode/DImode MEM. */
6853 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
6854 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
6855 reg_offset_p
= false;
6857 /* We must recognize output that we have already generated ourselves. */
6858 if (GET_CODE (x
) == PLUS
6859 && GET_CODE (XEXP (x
, 0)) == PLUS
6860 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6861 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6862 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6864 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6865 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6866 opnum
, (enum reload_type
) type
);
6871 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6872 if (GET_CODE (x
) == LO_SUM
6873 && GET_CODE (XEXP (x
, 0)) == HIGH
)
6875 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6876 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6877 opnum
, (enum reload_type
) type
);
6883 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
6884 && GET_CODE (x
) == LO_SUM
6885 && GET_CODE (XEXP (x
, 0)) == PLUS
6886 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
6887 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
6888 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
6889 && machopic_operand_p (XEXP (x
, 1)))
6891 /* Result of previous invocation of this function on Darwin
6892 floating point constant. */
6893 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6894 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6895 opnum
, (enum reload_type
) type
);
6901 if (TARGET_CMODEL
!= CMODEL_SMALL
6903 && small_toc_ref (x
, VOIDmode
))
6905 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
6906 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
6907 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6908 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6909 opnum
, (enum reload_type
) type
);
6914 if (GET_CODE (x
) == PLUS
6915 && GET_CODE (XEXP (x
, 0)) == REG
6916 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
6917 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
6918 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6920 && !SPE_VECTOR_MODE (mode
)
6921 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
6922 || mode
== DDmode
|| mode
== TDmode
6924 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
6926 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
6927 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
6929 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6931 /* Check for 32-bit overflow. */
6932 if (high
+ low
!= val
)
6938 /* Reload the high part into a base reg; leave the low part
6939 in the mem directly. */
6941 x
= gen_rtx_PLUS (GET_MODE (x
),
6942 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
6946 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6947 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6948 opnum
, (enum reload_type
) type
);
6953 if (GET_CODE (x
) == SYMBOL_REF
6955 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
6956 && !SPE_VECTOR_MODE (mode
)
6958 && DEFAULT_ABI
== ABI_DARWIN
6959 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
6960 && machopic_symbol_defined_p (x
)
6962 && DEFAULT_ABI
== ABI_V4
6965 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6966 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6968 ??? Assume floating point reg based on mode? This assumption is
6969 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
6970 where reload ends up doing a DFmode load of a constant from
6971 mem using two gprs. Unfortunately, at this point reload
6972 hasn't yet selected regs so poking around in reload data
6973 won't help and even if we could figure out the regs reliably,
6974 we'd still want to allow this transformation when the mem is
6975 naturally aligned. Since we say the address is good here, we
6976 can't disable offsets from LO_SUMs in mem_operand_gpr.
6977 FIXME: Allow offset from lo_sum for other modes too, when
6978 mem is sufficiently aligned. */
6981 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
6983 && (mode
!= DImode
|| TARGET_POWERPC64
)
6984 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
6985 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
6990 rtx offset
= machopic_gen_offset (x
);
6991 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6992 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
6993 gen_rtx_HIGH (Pmode
, offset
)), offset
);
6997 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6998 gen_rtx_HIGH (Pmode
, x
), x
);
7000 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7001 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7002 opnum
, (enum reload_type
) type
);
7007 /* Reload an offset address wrapped by an AND that represents the
7008 masking of the lower bits. Strip the outer AND and let reload
7009 convert the offset address into an indirect address. For VSX,
7010 force reload to create the address with an AND in a separate
7011 register, because we can't guarantee an altivec register will
7013 if (VECTOR_MEM_ALTIVEC_P (mode
)
7014 && GET_CODE (x
) == AND
7015 && GET_CODE (XEXP (x
, 0)) == PLUS
7016 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7017 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7018 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7019 && INTVAL (XEXP (x
, 1)) == -16)
7028 && GET_CODE (x
) == SYMBOL_REF
7029 && use_toc_relative_ref (x
))
7031 x
= create_TOC_reference (x
, NULL_RTX
);
7032 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7033 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7034 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7035 opnum
, (enum reload_type
) type
);
7043 /* Debug version of rs6000_legitimize_reload_address. */
7045 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7046 int opnum
, int type
,
7047 int ind_levels
, int *win
)
7049 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7052 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7053 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7054 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7058 fprintf (stderr
, "Same address returned\n");
7060 fprintf (stderr
, "NULL returned\n");
7063 fprintf (stderr
, "New address:\n");
7070 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7071 that is a valid memory address for an instruction.
7072 The MODE argument is the machine mode for the MEM expression
7073 that wants to use this address.
7075 On the RS/6000, there are four valid address: a SYMBOL_REF that
7076 refers to a constant pool entry of an address (or the sum of it
7077 plus a constant), a short (16-bit signed) constant plus a register,
7078 the sum of two registers, or a register indirect, possibly with an
7079 auto-increment. For DFmode, DDmode and DImode with a constant plus
7080 register, we must ensure that both words are addressable or PowerPC64
7081 with offset word aligned.
7083 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7084 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7085 because adjacent memory cells are accessed by adding word-sized offsets
7086 during assembly output. */
7088 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7090 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7092 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7093 if (VECTOR_MEM_ALTIVEC_P (mode
)
7094 && GET_CODE (x
) == AND
7095 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7096 && INTVAL (XEXP (x
, 1)) == -16)
7099 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7101 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7103 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7104 && !ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7105 && !SPE_VECTOR_MODE (mode
)
7110 /* Restrict addressing for DI because of our SUBREG hackery. */
7111 && !(TARGET_E500_DOUBLE
7112 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
7114 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7116 if (virtual_stack_registers_memory_p (x
))
7118 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7121 && legitimate_constant_pool_address_p (x
, mode
, reg_ok_strict
))
7123 /* For TImode, if we have load/store quad, only allow register indirect
7124 addresses. This will allow the values to go in either GPRs or VSX
7125 registers without reloading. The vector types would tend to go into VSX
7126 registers, so we allow REG+REG, while TImode seems somewhat split, in that
7127 some uses are GPR based, and some VSX based. */
7128 if (mode
== TImode
&& TARGET_QUAD_MEMORY
)
7130 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7133 && GET_CODE (x
) == PLUS
7134 && GET_CODE (XEXP (x
, 0)) == REG
7135 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7136 || XEXP (x
, 0) == arg_pointer_rtx
)
7137 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7139 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7143 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7145 || (mode
!= DFmode
&& mode
!= DDmode
)
7146 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7147 && (TARGET_POWERPC64
|| mode
!= DImode
)
7148 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7150 && !avoiding_indexed_address_p (mode
)
7151 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7153 if (GET_CODE (x
) == PRE_MODIFY
7158 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7160 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
7161 && (TARGET_POWERPC64
|| mode
!= DImode
)
7162 && !ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7163 && !SPE_VECTOR_MODE (mode
)
7164 /* Restrict addressing for DI because of our SUBREG hackery. */
7165 && !(TARGET_E500_DOUBLE
7166 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
7168 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7169 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7170 reg_ok_strict
, false)
7171 || (!avoiding_indexed_address_p (mode
)
7172 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7173 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7175 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7180 /* Debug version of rs6000_legitimate_address_p. */
7182 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7185 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7187 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7188 "strict = %d, code = %s\n",
7189 ret
? "true" : "false",
7190 GET_MODE_NAME (mode
),
7192 GET_RTX_NAME (GET_CODE (x
)));
7198 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7201 rs6000_mode_dependent_address_p (const_rtx addr
,
7202 addr_space_t as ATTRIBUTE_UNUSED
)
7204 return rs6000_mode_dependent_address_ptr (addr
);
7207 /* Go to LABEL if ADDR (a legitimate address expression)
7208 has an effect that depends on the machine mode it is used for.
7210 On the RS/6000 this is true of all integral offsets (since AltiVec
7211 and VSX modes don't allow them) or is a pre-increment or decrement.
7213 ??? Except that due to conceptual problems in offsettable_address_p
7214 we can't really report the problems of integral offsets. So leave
7215 this assuming that the adjustable offset must be valid for the
7216 sub-words of a TFmode operand, which is what we had before. */
7219 rs6000_mode_dependent_address (const_rtx addr
)
7221 switch (GET_CODE (addr
))
7224 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7225 is considered a legitimate address before reload, so there
7226 are no offset restrictions in that case. Note that this
7227 condition is safe in strict mode because any address involving
7228 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7229 been rejected as illegitimate. */
7230 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7231 && XEXP (addr
, 0) != arg_pointer_rtx
7232 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7234 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7235 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7240 /* Anything in the constant pool is sufficiently aligned that
7241 all bytes have the same high part address. */
7242 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7244 /* Auto-increment cases are now treated generically in recog.c. */
7246 return TARGET_UPDATE
;
7248 /* AND is only allowed in Altivec loads. */
7259 /* Debug version of rs6000_mode_dependent_address. */
7261 rs6000_debug_mode_dependent_address (const_rtx addr
)
7263 bool ret
= rs6000_mode_dependent_address (addr
);
7265 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7266 ret
? "true" : "false");
7272 /* Implement FIND_BASE_TERM. */
7275 rs6000_find_base_term (rtx op
)
7280 if (GET_CODE (base
) == CONST
)
7281 base
= XEXP (base
, 0);
7282 if (GET_CODE (base
) == PLUS
)
7283 base
= XEXP (base
, 0);
7284 if (GET_CODE (base
) == UNSPEC
)
7285 switch (XINT (base
, 1))
7288 case UNSPEC_MACHOPIC_OFFSET
:
7289 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7290 for aliasing purposes. */
7291 return XVECEXP (base
, 0, 0);
7297 /* More elaborate version of recog's offsettable_memref_p predicate
7298 that works around the ??? note of rs6000_mode_dependent_address.
7299 In particular it accepts
7301 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7303 in 32-bit mode, that the recog predicate rejects. */
7306 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7313 /* First mimic offsettable_memref_p. */
7314 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7317 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7318 the latter predicate knows nothing about the mode of the memory
7319 reference and, therefore, assumes that it is the largest supported
7320 mode (TFmode). As a consequence, legitimate offsettable memory
7321 references are rejected. rs6000_legitimate_offset_address_p contains
7322 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7323 at least with a little bit of help here given that we know the
7324 actual registers used. */
7325 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7326 || GET_MODE_SIZE (reg_mode
) == 4);
7327 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7331 /* Change register usage conditional on target flags. */
7333 rs6000_conditional_register_usage (void)
7337 if (TARGET_DEBUG_TARGET
)
7338 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7340 /* Set MQ register fixed (already call_used) so that it will not be
7344 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7346 fixed_regs
[13] = call_used_regs
[13]
7347 = call_really_used_regs
[13] = 1;
7349 /* Conditionally disable FPRs. */
7350 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7351 for (i
= 32; i
< 64; i
++)
7352 fixed_regs
[i
] = call_used_regs
[i
]
7353 = call_really_used_regs
[i
] = 1;
7355 /* The TOC register is not killed across calls in a way that is
7356 visible to the compiler. */
7357 if (DEFAULT_ABI
== ABI_AIX
)
7358 call_really_used_regs
[2] = 0;
7360 if (DEFAULT_ABI
== ABI_V4
7361 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7363 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7365 if (DEFAULT_ABI
== ABI_V4
7366 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7368 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7369 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7370 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7372 if (DEFAULT_ABI
== ABI_DARWIN
7373 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7374 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7375 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7376 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7378 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7379 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7380 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7384 global_regs
[SPEFSCR_REGNO
] = 1;
7385 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7386 registers in prologues and epilogues. We no longer use r14
7387 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7388 pool for link-compatibility with older versions of GCC. Once
7389 "old" code has died out, we can return r14 to the allocation
7392 = call_used_regs
[14]
7393 = call_really_used_regs
[14] = 1;
7396 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7398 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7399 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7400 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7403 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7404 global_regs
[VSCR_REGNO
] = 1;
7406 if (TARGET_ALTIVEC_ABI
)
7408 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7409 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7411 /* AIX reserves VR20:31 in non-extended ABI mode. */
7413 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7414 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7418 /* Try to output insns to set TARGET equal to the constant C if it can
7419 be done in less than N insns. Do all computations in MODE.
7420 Returns the place where the output has been placed if it can be
7421 done and the insns have been emitted. If it would take more than N
7422 insns, zero is returned and no insns and emitted. */
7425 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7426 rtx source
, int n ATTRIBUTE_UNUSED
)
7428 rtx result
, insn
, set
;
7429 HOST_WIDE_INT c0
, c1
;
7436 dest
= gen_reg_rtx (mode
);
7437 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7441 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7443 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7444 GEN_INT (INTVAL (source
)
7445 & (~ (HOST_WIDE_INT
) 0xffff))));
7446 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7447 gen_rtx_IOR (SImode
, copy_rtx (result
),
7448 GEN_INT (INTVAL (source
) & 0xffff))));
7453 switch (GET_CODE (source
))
7456 c0
= INTVAL (source
);
7464 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7471 insn
= get_last_insn ();
7472 set
= single_set (insn
);
7473 if (! CONSTANT_P (SET_SRC (set
)))
7474 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7479 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7480 fall back to a straight forward decomposition. We do this to avoid
7481 exponential run times encountered when looking for longer sequences
7482 with rs6000_emit_set_const. */
7484 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7486 if (!TARGET_POWERPC64
)
7488 rtx operand1
, operand2
;
7490 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7492 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7494 emit_move_insn (operand1
, GEN_INT (c1
));
7495 emit_move_insn (operand2
, GEN_INT (c2
));
7499 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7502 ud2
= (c1
& 0xffff0000) >> 16;
7505 ud4
= (c2
& 0xffff0000) >> 16;
7507 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7508 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7509 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7511 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7512 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7514 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7517 emit_move_insn (copy_rtx (dest
),
7518 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7521 else if (ud3
== 0 && ud4
== 0)
7523 gcc_assert (ud2
& 0x8000);
7524 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7527 emit_move_insn (copy_rtx (dest
),
7528 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7530 emit_move_insn (copy_rtx (dest
),
7531 gen_rtx_ZERO_EXTEND (DImode
,
7532 gen_lowpart (SImode
,
7535 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7536 || (ud4
== 0 && ! (ud3
& 0x8000)))
7538 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7541 emit_move_insn (copy_rtx (dest
),
7542 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7544 emit_move_insn (copy_rtx (dest
),
7545 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7548 emit_move_insn (copy_rtx (dest
),
7549 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7554 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7557 emit_move_insn (copy_rtx (dest
),
7558 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7561 emit_move_insn (copy_rtx (dest
),
7562 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7565 emit_move_insn (copy_rtx (dest
),
7566 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7567 GEN_INT (ud2
<< 16)));
7569 emit_move_insn (copy_rtx (dest
),
7570 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7577 /* Helper for the following. Get rid of [r+r] memory refs
7578 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
7581 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7583 if (reload_in_progress
)
7586 if (GET_CODE (operands
[0]) == MEM
7587 && GET_CODE (XEXP (operands
[0], 0)) != REG
7588 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7589 GET_MODE (operands
[0]), false))
7591 = replace_equiv_address (operands
[0],
7592 copy_addr_to_reg (XEXP (operands
[0], 0)));
7594 if (GET_CODE (operands
[1]) == MEM
7595 && GET_CODE (XEXP (operands
[1], 0)) != REG
7596 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7597 GET_MODE (operands
[1]), false))
7599 = replace_equiv_address (operands
[1],
7600 copy_addr_to_reg (XEXP (operands
[1], 0)));
7603 /* Emit a move from SOURCE to DEST in mode MODE. */
7605 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
7609 operands
[1] = source
;
7611 if (TARGET_DEBUG_ADDR
)
7614 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
7615 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
7616 GET_MODE_NAME (mode
),
7619 can_create_pseudo_p ());
7621 fprintf (stderr
, "source:\n");
7625 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
7626 if (GET_CODE (operands
[1]) == CONST_DOUBLE
7627 && ! FLOAT_MODE_P (mode
)
7628 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
7630 /* FIXME. This should never happen. */
7631 /* Since it seems that it does, do the safe thing and convert
7633 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
7635 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
7636 || FLOAT_MODE_P (mode
)
7637 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
7638 || CONST_DOUBLE_LOW (operands
[1]) < 0)
7639 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
7640 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
7642 /* Check if GCC is setting up a block move that will end up using FP
7643 registers as temporaries. We must make sure this is acceptable. */
7644 if (GET_CODE (operands
[0]) == MEM
7645 && GET_CODE (operands
[1]) == MEM
7647 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
7648 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
7649 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
7650 ? 32 : MEM_ALIGN (operands
[0])))
7651 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
7653 : MEM_ALIGN (operands
[1]))))
7654 && ! MEM_VOLATILE_P (operands
[0])
7655 && ! MEM_VOLATILE_P (operands
[1]))
7657 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
7658 adjust_address (operands
[1], SImode
, 0));
7659 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
7660 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
7664 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
7665 && !gpc_reg_operand (operands
[1], mode
))
7666 operands
[1] = force_reg (mode
, operands
[1]);
7668 /* Recognize the case where operand[1] is a reference to thread-local
7669 data and load its address to a register. */
7670 if (rs6000_tls_referenced_p (operands
[1]))
7672 enum tls_model model
;
7673 rtx tmp
= operands
[1];
7676 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
7678 addend
= XEXP (XEXP (tmp
, 0), 1);
7679 tmp
= XEXP (XEXP (tmp
, 0), 0);
7682 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
7683 model
= SYMBOL_REF_TLS_MODEL (tmp
);
7684 gcc_assert (model
!= 0);
7686 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
7689 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
7690 tmp
= force_operand (tmp
, operands
[0]);
7695 /* Handle the case where reload calls us with an invalid address. */
7696 if (reload_in_progress
&& mode
== Pmode
7697 && (! general_operand (operands
[1], mode
)
7698 || ! nonimmediate_operand (operands
[0], mode
)))
7701 /* 128-bit constant floating-point values on Darwin should really be
7702 loaded as two parts. */
7703 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
7704 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
7706 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
7707 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
7709 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
7710 GET_MODE_SIZE (DFmode
)),
7711 simplify_gen_subreg (DFmode
, operands
[1], mode
,
7712 GET_MODE_SIZE (DFmode
)),
7717 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
7718 cfun
->machine
->sdmode_stack_slot
=
7719 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
7721 if (reload_in_progress
7723 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
7724 && MEM_P (operands
[0])
7725 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
7726 && REG_P (operands
[1]))
7728 if (FP_REGNO_P (REGNO (operands
[1])))
7730 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
7731 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7732 emit_insn (gen_movsd_store (mem
, operands
[1]));
7734 else if (INT_REGNO_P (REGNO (operands
[1])))
7736 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
7737 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7738 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
7744 if (reload_in_progress
7746 && REG_P (operands
[0])
7747 && MEM_P (operands
[1])
7748 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
7749 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
7751 if (FP_REGNO_P (REGNO (operands
[0])))
7753 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
7754 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7755 emit_insn (gen_movsd_load (operands
[0], mem
));
7757 else if (INT_REGNO_P (REGNO (operands
[0])))
7759 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
7760 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7761 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
7768 /* FIXME: In the long term, this switch statement should go away
7769 and be replaced by a sequence of tests based on things like
7775 if (CONSTANT_P (operands
[1])
7776 && GET_CODE (operands
[1]) != CONST_INT
)
7777 operands
[1] = force_const_mem (mode
, operands
[1]);
7782 rs6000_eliminate_indexed_memrefs (operands
);
7789 if (CONSTANT_P (operands
[1])
7790 && ! easy_fp_constant (operands
[1], mode
))
7791 operands
[1] = force_const_mem (mode
, operands
[1]);
7804 if (CONSTANT_P (operands
[1])
7805 && !easy_vector_constant (operands
[1], mode
))
7806 operands
[1] = force_const_mem (mode
, operands
[1]);
7811 /* Use default pattern for address of ELF small data */
7814 && DEFAULT_ABI
== ABI_V4
7815 && (GET_CODE (operands
[1]) == SYMBOL_REF
7816 || GET_CODE (operands
[1]) == CONST
)
7817 && small_data_operand (operands
[1], mode
))
7819 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7823 if (DEFAULT_ABI
== ABI_V4
7824 && mode
== Pmode
&& mode
== SImode
7825 && flag_pic
== 1 && got_operand (operands
[1], mode
))
7827 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
7831 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
7835 && CONSTANT_P (operands
[1])
7836 && GET_CODE (operands
[1]) != HIGH
7837 && GET_CODE (operands
[1]) != CONST_INT
)
7839 rtx target
= (!can_create_pseudo_p ()
7841 : gen_reg_rtx (mode
));
7843 /* If this is a function address on -mcall-aixdesc,
7844 convert it to the address of the descriptor. */
7845 if (DEFAULT_ABI
== ABI_AIX
7846 && GET_CODE (operands
[1]) == SYMBOL_REF
7847 && XSTR (operands
[1], 0)[0] == '.')
7849 const char *name
= XSTR (operands
[1], 0);
7851 while (*name
== '.')
7853 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
7854 CONSTANT_POOL_ADDRESS_P (new_ref
)
7855 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
7856 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
7857 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
7858 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
7859 operands
[1] = new_ref
;
7862 if (DEFAULT_ABI
== ABI_DARWIN
)
7865 if (MACHO_DYNAMIC_NO_PIC_P
)
7867 /* Take care of any required data indirection. */
7868 operands
[1] = rs6000_machopic_legitimize_pic_address (
7869 operands
[1], mode
, operands
[0]);
7870 if (operands
[0] != operands
[1])
7871 emit_insn (gen_rtx_SET (VOIDmode
,
7872 operands
[0], operands
[1]));
7876 emit_insn (gen_macho_high (target
, operands
[1]));
7877 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
7881 emit_insn (gen_elf_high (target
, operands
[1]));
7882 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
7886 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7887 and we have put it in the TOC, we just need to make a TOC-relative
7890 && GET_CODE (operands
[1]) == SYMBOL_REF
7891 && use_toc_relative_ref (operands
[1]))
7892 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
7893 else if (mode
== Pmode
7894 && CONSTANT_P (operands
[1])
7895 && GET_CODE (operands
[1]) != HIGH
7896 && ((GET_CODE (operands
[1]) != CONST_INT
7897 && ! easy_fp_constant (operands
[1], mode
))
7898 || (GET_CODE (operands
[1]) == CONST_INT
7899 && (num_insns_constant (operands
[1], mode
)
7900 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
7901 || (GET_CODE (operands
[0]) == REG
7902 && FP_REGNO_P (REGNO (operands
[0]))))
7903 && !toc_relative_expr_p (operands
[1], false)
7904 && (TARGET_CMODEL
== CMODEL_SMALL
7905 || can_create_pseudo_p ()
7906 || (REG_P (operands
[0])
7907 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
7911 /* Darwin uses a special PIC legitimizer. */
7912 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
7915 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
7917 if (operands
[0] != operands
[1])
7918 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7923 /* If we are to limit the number of things we put in the TOC and
7924 this is a symbol plus a constant we can add in one insn,
7925 just put the symbol in the TOC and add the constant. Don't do
7926 this if reload is in progress. */
7927 if (GET_CODE (operands
[1]) == CONST
7928 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
7929 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
7930 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
7931 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
7932 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
7933 && ! side_effects_p (operands
[0]))
7936 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
7937 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
7939 sym
= force_reg (mode
, sym
);
7940 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
7944 operands
[1] = force_const_mem (mode
, operands
[1]);
7947 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
7948 && constant_pool_expr_p (XEXP (operands
[1], 0))
7949 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7950 get_pool_constant (XEXP (operands
[1], 0)),
7951 get_pool_mode (XEXP (operands
[1], 0))))
7953 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
7955 operands
[1] = gen_const_mem (mode
, tocref
);
7956 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
7962 if (!VECTOR_MEM_VSX_P (TImode
))
7963 rs6000_eliminate_indexed_memrefs (operands
);
7967 rs6000_eliminate_indexed_memrefs (operands
);
7971 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
7974 /* Above, we may have called force_const_mem which may have returned
7975 an invalid address. If we can, fix this up; otherwise, reload will
7976 have to deal with it. */
7977 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
7978 operands
[1] = validize_mem (operands
[1]);
7981 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7984 /* Return true if a structure, union or array containing FIELD should be
7985 accessed using `BLKMODE'.
7987 For the SPE, simd types are V2SI, and gcc can be tempted to put the
7988 entire thing in a DI and use subregs to access the internals.
7989 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
7990 back-end. Because a single GPR can hold a V2SI, but not a DI, the
7991 best thing to do is set structs to BLKmode and avoid Severe Tire
7994 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
7995 fit into 1, whereas DI still needs two. */
7998 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8000 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8001 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8004 /* Nonzero if we can use a floating-point register to pass this arg. */
8005 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
8006 (SCALAR_FLOAT_MODE_P (MODE) \
8007 && (CUM)->fregno <= FP_ARG_MAX_REG \
8008 && TARGET_HARD_FLOAT && TARGET_FPRS)
8010 /* Nonzero if we can use an AltiVec register to pass this arg. */
8011 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
8012 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8013 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8014 && TARGET_ALTIVEC_ABI \
8017 /* Return a nonzero value to say to return the function value in
8018 memory, just as large structures are always returned. TYPE will be
8019 the data type of the value, and FNTYPE will be the type of the
8020 function doing the returning, or @code{NULL} for libcalls.
8022 The AIX ABI for the RS/6000 specifies that all structures are
8023 returned in memory. The Darwin ABI does the same.
8025 For the Darwin 64 Bit ABI, a function result can be returned in
8026 registers or in memory, depending on the size of the return data
8027 type. If it is returned in registers, the value occupies the same
8028 registers as it would if it were the first and only function
8029 argument. Otherwise, the function places its result in memory at
8030 the location pointed to by GPR3.
8032 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8033 but a draft put them in memory, and GCC used to implement the draft
8034 instead of the final standard. Therefore, aix_struct_return
8035 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8036 compatibility can change DRAFT_V4_STRUCT_RET to override the
8037 default, and -m switches get the final word. See
8038 rs6000_option_override_internal for more details.
8040 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8041 long double support is enabled. These values are returned in memory.
8043 int_size_in_bytes returns -1 for variable size objects, which go in
8044 memory always. The cast to unsigned makes -1 > 8. */
8047 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8049 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8051 && rs6000_darwin64_abi
8052 && TREE_CODE (type
) == RECORD_TYPE
8053 && int_size_in_bytes (type
) > 0)
8055 CUMULATIVE_ARGS valcum
;
8059 valcum
.fregno
= FP_ARG_MIN_REG
;
8060 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8061 /* Do a trial code generation as if this were going to be passed
8062 as an argument; if any part goes in memory, we return NULL. */
8063 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8066 /* Otherwise fall through to more conventional ABI rules. */
8069 if (AGGREGATE_TYPE_P (type
)
8070 && (aix_struct_return
8071 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8074 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8075 modes only exist for GCC vector types if -maltivec. */
8076 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8077 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8080 /* Return synthetic vectors in memory. */
8081 if (TREE_CODE (type
) == VECTOR_TYPE
8082 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8084 static bool warned_for_return_big_vectors
= false;
8085 if (!warned_for_return_big_vectors
)
8087 warning (0, "GCC vector returned by reference: "
8088 "non-standard ABI extension with no compatibility guarantee");
8089 warned_for_return_big_vectors
= true;
8094 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8100 #ifdef HAVE_AS_GNU_ATTRIBUTE
8101 /* Return TRUE if a call to function FNDECL may be one that
8102 potentially affects the function calling ABI of the object file. */
8105 call_ABI_of_interest (tree fndecl
)
8107 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8109 struct cgraph_node
*c_node
;
8111 /* Libcalls are always interesting. */
8112 if (fndecl
== NULL_TREE
)
8115 /* Any call to an external function is interesting. */
8116 if (DECL_EXTERNAL (fndecl
))
8119 /* Interesting functions that we are emitting in this object file. */
8120 c_node
= cgraph_get_node (fndecl
);
8121 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8122 return !cgraph_only_called_directly_p (c_node
);
8128 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8129 for a call to a function whose data type is FNTYPE.
8130 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8132 For incoming args we set the number of arguments in the prototype large
8133 so we never return a PARALLEL. */
8136 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8137 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8138 int libcall
, int n_named_args
,
8139 tree fndecl ATTRIBUTE_UNUSED
,
8140 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8142 static CUMULATIVE_ARGS zero_cumulative
;
8144 *cum
= zero_cumulative
;
8146 cum
->fregno
= FP_ARG_MIN_REG
;
8147 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8148 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8149 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8150 ? CALL_LIBCALL
: CALL_NORMAL
);
8151 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8152 cum
->stdarg
= stdarg_p (fntype
);
8154 cum
->nargs_prototype
= 0;
8155 if (incoming
|| cum
->prototype
)
8156 cum
->nargs_prototype
= n_named_args
;
8158 /* Check for a longcall attribute. */
8159 if ((!fntype
&& rs6000_default_long_calls
)
8161 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
8162 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
8163 cum
->call_cookie
|= CALL_LONG
;
8165 if (TARGET_DEBUG_ARG
)
8167 fprintf (stderr
, "\ninit_cumulative_args:");
8170 tree ret_type
= TREE_TYPE (fntype
);
8171 fprintf (stderr
, " ret code = %s,",
8172 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
8175 if (cum
->call_cookie
& CALL_LONG
)
8176 fprintf (stderr
, " longcall,");
8178 fprintf (stderr
, " proto = %d, nargs = %d\n",
8179 cum
->prototype
, cum
->nargs_prototype
);
8182 #ifdef HAVE_AS_GNU_ATTRIBUTE
8183 if (DEFAULT_ABI
== ABI_V4
)
8185 cum
->escapes
= call_ABI_of_interest (fndecl
);
8192 return_type
= TREE_TYPE (fntype
);
8193 return_mode
= TYPE_MODE (return_type
);
8196 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
8198 if (return_type
!= NULL
)
8200 if (TREE_CODE (return_type
) == RECORD_TYPE
8201 && TYPE_TRANSPARENT_AGGR (return_type
))
8203 return_type
= TREE_TYPE (first_field (return_type
));
8204 return_mode
= TYPE_MODE (return_type
);
8206 if (AGGREGATE_TYPE_P (return_type
)
8207 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
8209 rs6000_returns_struct
= true;
8211 if (SCALAR_FLOAT_MODE_P (return_mode
))
8212 rs6000_passes_float
= true;
8213 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
8214 || SPE_VECTOR_MODE (return_mode
))
8215 rs6000_passes_vector
= true;
8222 && TARGET_ALTIVEC_ABI
8223 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
8225 error ("cannot return value in vector register because"
8226 " altivec instructions are disabled, use -maltivec"
8231 /* Return true if TYPE must be passed on the stack and not in registers. */
8234 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
8236 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
8237 return must_pass_in_stack_var_size (mode
, type
);
8239 return must_pass_in_stack_var_size_or_pad (mode
, type
);
8242 /* If defined, a C expression which determines whether, and in which
8243 direction, to pad out an argument with extra space. The value
8244 should be of type `enum direction': either `upward' to pad above
8245 the argument, `downward' to pad below, or `none' to inhibit
8248 For the AIX ABI structs are always stored left shifted in their
8252 function_arg_padding (enum machine_mode mode
, const_tree type
)
8254 #ifndef AGGREGATE_PADDING_FIXED
8255 #define AGGREGATE_PADDING_FIXED 0
8257 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
8258 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
8261 if (!AGGREGATE_PADDING_FIXED
)
8263 /* GCC used to pass structures of the same size as integer types as
8264 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
8265 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
8266 passed padded downward, except that -mstrict-align further
8267 muddied the water in that multi-component structures of 2 and 4
8268 bytes in size were passed padded upward.
8270 The following arranges for best compatibility with previous
8271 versions of gcc, but removes the -mstrict-align dependency. */
8272 if (BYTES_BIG_ENDIAN
)
8274 HOST_WIDE_INT size
= 0;
8276 if (mode
== BLKmode
)
8278 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
8279 size
= int_size_in_bytes (type
);
8282 size
= GET_MODE_SIZE (mode
);
8284 if (size
== 1 || size
== 2 || size
== 4)
8290 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
8292 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
8296 /* Fall back to the default. */
8297 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8300 /* If defined, a C expression that gives the alignment boundary, in bits,
8301 of an argument with the specified mode and type. If it is not defined,
8302 PARM_BOUNDARY is used for all arguments.
8304 V.4 wants long longs and doubles to be double word aligned. Just
8305 testing the mode size is a boneheaded way to do this as it means
8306 that other types such as complex int are also double word aligned.
8307 However, we're stuck with this because changing the ABI might break
8308 existing library interfaces.
8310 Doubleword align SPE vectors.
8311 Quadword align Altivec/VSX vectors.
8312 Quadword align large synthetic vector types. */
8315 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
8317 if (DEFAULT_ABI
== ABI_V4
8318 && (GET_MODE_SIZE (mode
) == 8
8319 || (TARGET_HARD_FLOAT
8321 && (mode
== TFmode
|| mode
== TDmode
))))
8323 else if (SPE_VECTOR_MODE (mode
)
8324 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8325 && int_size_in_bytes (type
) >= 8
8326 && int_size_in_bytes (type
) < 16))
8328 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8329 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8330 && int_size_in_bytes (type
) >= 16))
8332 else if (TARGET_MACHO
8333 && rs6000_darwin64_abi
8335 && type
&& TYPE_ALIGN (type
) > 64)
8338 return PARM_BOUNDARY
;
8341 /* For a function parm of MODE and TYPE, return the starting word in
8342 the parameter area. NWORDS of the parameter area are already used. */
8345 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
8346 unsigned int nwords
)
8349 unsigned int parm_offset
;
8351 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
8352 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
8353 return nwords
+ (-(parm_offset
+ nwords
) & align
);
8356 /* Compute the size (in words) of a function argument. */
8358 static unsigned long
8359 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
8363 if (mode
!= BLKmode
)
8364 size
= GET_MODE_SIZE (mode
);
8366 size
= int_size_in_bytes (type
);
8369 return (size
+ 3) >> 2;
8371 return (size
+ 7) >> 3;
8374 /* Use this to flush pending int fields. */
8377 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
8378 HOST_WIDE_INT bitpos
, int final
)
8380 unsigned int startbit
, endbit
;
8381 int intregs
, intoffset
;
8382 enum machine_mode mode
;
8384 /* Handle the situations where a float is taking up the first half
8385 of the GPR, and the other half is empty (typically due to
8386 alignment restrictions). We can detect this by a 8-byte-aligned
8387 int field, or by seeing that this is the final flush for this
8388 argument. Count the word and continue on. */
8389 if (cum
->floats_in_gpr
== 1
8390 && (cum
->intoffset
% 64 == 0
8391 || (cum
->intoffset
== -1 && final
)))
8394 cum
->floats_in_gpr
= 0;
8397 if (cum
->intoffset
== -1)
8400 intoffset
= cum
->intoffset
;
8401 cum
->intoffset
= -1;
8402 cum
->floats_in_gpr
= 0;
8404 if (intoffset
% BITS_PER_WORD
!= 0)
8406 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8408 if (mode
== BLKmode
)
8410 /* We couldn't find an appropriate mode, which happens,
8411 e.g., in packed structs when there are 3 bytes to load.
8412 Back intoffset back to the beginning of the word in this
8414 intoffset
= intoffset
& -BITS_PER_WORD
;
8418 startbit
= intoffset
& -BITS_PER_WORD
;
8419 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8420 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8421 cum
->words
+= intregs
;
8422 /* words should be unsigned. */
8423 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
8425 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
8430 /* The darwin64 ABI calls for us to recurse down through structs,
8431 looking for elements passed in registers. Unfortunately, we have
8432 to track int register count here also because of misalignments
8433 in powerpc alignment mode. */
8436 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
8438 HOST_WIDE_INT startbitpos
)
8442 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8443 if (TREE_CODE (f
) == FIELD_DECL
)
8445 HOST_WIDE_INT bitpos
= startbitpos
;
8446 tree ftype
= TREE_TYPE (f
);
8447 enum machine_mode mode
;
8448 if (ftype
== error_mark_node
)
8450 mode
= TYPE_MODE (ftype
);
8452 if (DECL_SIZE (f
) != 0
8453 && host_integerp (bit_position (f
), 1))
8454 bitpos
+= int_bit_position (f
);
8456 /* ??? FIXME: else assume zero offset. */
8458 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8459 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
8460 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8462 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8463 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
8464 cum
->fregno
+= n_fpregs
;
8465 /* Single-precision floats present a special problem for
8466 us, because they are smaller than an 8-byte GPR, and so
8467 the structure-packing rules combined with the standard
8468 varargs behavior mean that we want to pack float/float
8469 and float/int combinations into a single register's
8470 space. This is complicated by the arg advance flushing,
8471 which works on arbitrarily large groups of int-type
8475 if (cum
->floats_in_gpr
== 1)
8477 /* Two floats in a word; count the word and reset
8480 cum
->floats_in_gpr
= 0;
8482 else if (bitpos
% 64 == 0)
8484 /* A float at the beginning of an 8-byte word;
8485 count it and put off adjusting cum->words until
8486 we see if a arg advance flush is going to do it
8488 cum
->floats_in_gpr
++;
8492 /* The float is at the end of a word, preceded
8493 by integer fields, so the arg advance flush
8494 just above has already set cum->words and
8495 everything is taken care of. */
8499 cum
->words
+= n_fpregs
;
8501 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
8503 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
8507 else if (cum
->intoffset
== -1)
8508 cum
->intoffset
= bitpos
;
8512 /* Check for an item that needs to be considered specially under the darwin 64
8513 bit ABI. These are record types where the mode is BLK or the structure is
8516 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
8518 return rs6000_darwin64_abi
8519 && ((mode
== BLKmode
8520 && TREE_CODE (type
) == RECORD_TYPE
8521 && int_size_in_bytes (type
) > 0)
8522 || (type
&& TREE_CODE (type
) == RECORD_TYPE
8523 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
8526 /* Update the data in CUM to advance over an argument
8527 of mode MODE and data type TYPE.
8528 (TYPE is null for libcalls where that information may not be available.)
8530 Note that for args passed by reference, function_arg will be called
8531 with MODE and TYPE set to that of the pointer to the arg, not the arg
8535 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8536 const_tree type
, bool named
, int depth
)
8538 /* Only tick off an argument if we're not recursing. */
8540 cum
->nargs_prototype
--;
8542 #ifdef HAVE_AS_GNU_ATTRIBUTE
8543 if (DEFAULT_ABI
== ABI_V4
8546 if (SCALAR_FLOAT_MODE_P (mode
))
8547 rs6000_passes_float
= true;
8548 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
8549 rs6000_passes_vector
= true;
8550 else if (SPE_VECTOR_MODE (mode
)
8552 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
8553 rs6000_passes_vector
= true;
8557 if (TARGET_ALTIVEC_ABI
8558 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8559 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8560 && int_size_in_bytes (type
) == 16)))
8564 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
8567 if (!TARGET_ALTIVEC
)
8568 error ("cannot pass argument in vector register because"
8569 " altivec instructions are disabled, use -maltivec"
8572 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
8573 even if it is going to be passed in a vector register.
8574 Darwin does the same for variable-argument functions. */
8575 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
8576 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
8586 /* Vector parameters must be 16-byte aligned. This places
8587 them at 2 mod 4 in terms of words in 32-bit mode, since
8588 the parameter save area starts at offset 24 from the
8589 stack. In 64-bit mode, they just have to start on an
8590 even word, since the parameter save area is 16-byte
8591 aligned. Space for GPRs is reserved even if the argument
8592 will be passed in memory. */
8594 align
= (2 - cum
->words
) & 3;
8596 align
= cum
->words
& 1;
8597 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
8599 if (TARGET_DEBUG_ARG
)
8601 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
8603 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
8604 cum
->nargs_prototype
, cum
->prototype
,
8605 GET_MODE_NAME (mode
));
8609 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
8611 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
8614 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8616 int size
= int_size_in_bytes (type
);
8617 /* Variable sized types have size == -1 and are
8618 treated as if consisting entirely of ints.
8619 Pad to 16 byte boundary if needed. */
8620 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8621 && (cum
->words
% 2) != 0)
8623 /* For varargs, we can just go up by the size of the struct. */
8625 cum
->words
+= (size
+ 7) / 8;
8628 /* It is tempting to say int register count just goes up by
8629 sizeof(type)/8, but this is wrong in a case such as
8630 { int; double; int; } [powerpc alignment]. We have to
8631 grovel through the fields for these too. */
8633 cum
->floats_in_gpr
= 0;
8634 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
8635 rs6000_darwin64_record_arg_advance_flush (cum
,
8636 size
* BITS_PER_UNIT
, 1);
8638 if (TARGET_DEBUG_ARG
)
8640 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
8641 cum
->words
, TYPE_ALIGN (type
), size
);
8643 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
8644 cum
->nargs_prototype
, cum
->prototype
,
8645 GET_MODE_NAME (mode
));
8648 else if (DEFAULT_ABI
== ABI_V4
)
8650 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8651 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
8652 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
8653 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
8654 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
8656 /* _Decimal128 must use an even/odd register pair. This assumes
8657 that the register number is odd when fregno is odd. */
8658 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8661 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
8662 <= FP_ARG_V4_MAX_REG
)
8663 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8666 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
8667 if (mode
== DFmode
|| mode
== TFmode
8668 || mode
== DDmode
|| mode
== TDmode
)
8669 cum
->words
+= cum
->words
& 1;
8670 cum
->words
+= rs6000_arg_size (mode
, type
);
8675 int n_words
= rs6000_arg_size (mode
, type
);
8676 int gregno
= cum
->sysv_gregno
;
8678 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8679 (r7,r8) or (r9,r10). As does any other 2 word item such
8680 as complex int due to a historical mistake. */
8682 gregno
+= (1 - gregno
) & 1;
8684 /* Multi-reg args are not split between registers and stack. */
8685 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8687 /* Long long and SPE vectors are aligned on the stack.
8688 So are other 2 word items such as complex int due to
8689 a historical mistake. */
8691 cum
->words
+= cum
->words
& 1;
8692 cum
->words
+= n_words
;
8695 /* Note: continuing to accumulate gregno past when we've started
8696 spilling to the stack indicates the fact that we've started
8697 spilling to the stack to expand_builtin_saveregs. */
8698 cum
->sysv_gregno
= gregno
+ n_words
;
8701 if (TARGET_DEBUG_ARG
)
8703 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8704 cum
->words
, cum
->fregno
);
8705 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
8706 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
8707 fprintf (stderr
, "mode = %4s, named = %d\n",
8708 GET_MODE_NAME (mode
), named
);
8713 int n_words
= rs6000_arg_size (mode
, type
);
8714 int start_words
= cum
->words
;
8715 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
8717 cum
->words
= align_words
+ n_words
;
8719 if (SCALAR_FLOAT_MODE_P (mode
)
8720 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8722 /* _Decimal128 must be passed in an even/odd float register pair.
8723 This assumes that the register number is odd when fregno is
8725 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8727 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8730 if (TARGET_DEBUG_ARG
)
8732 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8733 cum
->words
, cum
->fregno
);
8734 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
8735 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
8736 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
8737 named
, align_words
- start_words
, depth
);
8743 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
8744 const_tree type
, bool named
)
8746 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
8751 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
8758 r1
= gen_rtx_REG (DImode
, gregno
);
8759 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8760 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
8764 r1
= gen_rtx_REG (DImode
, gregno
);
8765 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8766 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8767 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8768 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
8771 r1
= gen_rtx_REG (DImode
, gregno
);
8772 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8773 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8774 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8775 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
8776 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
8777 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
8778 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
8779 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
8786 /* Determine where to put a SIMD argument on the SPE. */
8788 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8791 int gregno
= cum
->sysv_gregno
;
8793 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8794 are passed and returned in a pair of GPRs for ABI compatibility. */
8795 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
8796 || mode
== DCmode
|| mode
== TCmode
))
8798 int n_words
= rs6000_arg_size (mode
, type
);
8800 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8802 gregno
+= (1 - gregno
) & 1;
8804 /* Multi-reg args are not split between registers and stack. */
8805 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8808 return spe_build_register_parallel (mode
, gregno
);
8812 int n_words
= rs6000_arg_size (mode
, type
);
8814 /* SPE vectors are put in odd registers. */
8815 if (n_words
== 2 && (gregno
& 1) == 0)
8818 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
8821 enum machine_mode m
= SImode
;
8823 r1
= gen_rtx_REG (m
, gregno
);
8824 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
8825 r2
= gen_rtx_REG (m
, gregno
+ 1);
8826 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
8827 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
8834 if (gregno
<= GP_ARG_MAX_REG
)
8835 return gen_rtx_REG (mode
, gregno
);
8841 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8842 structure between cum->intoffset and bitpos to integer registers. */
8845 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
8846 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
8848 enum machine_mode mode
;
8850 unsigned int startbit
, endbit
;
8851 int this_regno
, intregs
, intoffset
;
8854 if (cum
->intoffset
== -1)
8857 intoffset
= cum
->intoffset
;
8858 cum
->intoffset
= -1;
8860 /* If this is the trailing part of a word, try to only load that
8861 much into the register. Otherwise load the whole register. Note
8862 that in the latter case we may pick up unwanted bits. It's not a
8863 problem at the moment but may wish to revisit. */
8865 if (intoffset
% BITS_PER_WORD
!= 0)
8867 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8869 if (mode
== BLKmode
)
8871 /* We couldn't find an appropriate mode, which happens,
8872 e.g., in packed structs when there are 3 bytes to load.
8873 Back intoffset back to the beginning of the word in this
8875 intoffset
= intoffset
& -BITS_PER_WORD
;
8882 startbit
= intoffset
& -BITS_PER_WORD
;
8883 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8884 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8885 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
8887 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
8890 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
8894 intoffset
/= BITS_PER_UNIT
;
8897 regno
= GP_ARG_MIN_REG
+ this_regno
;
8898 reg
= gen_rtx_REG (mode
, regno
);
8900 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
8903 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
8907 while (intregs
> 0);
8910 /* Recursive workhorse for the following. */
8913 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
8914 HOST_WIDE_INT startbitpos
, rtx rvec
[],
8919 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8920 if (TREE_CODE (f
) == FIELD_DECL
)
8922 HOST_WIDE_INT bitpos
= startbitpos
;
8923 tree ftype
= TREE_TYPE (f
);
8924 enum machine_mode mode
;
8925 if (ftype
== error_mark_node
)
8927 mode
= TYPE_MODE (ftype
);
8929 if (DECL_SIZE (f
) != 0
8930 && host_integerp (bit_position (f
), 1))
8931 bitpos
+= int_bit_position (f
);
8933 /* ??? FIXME: else assume zero offset. */
8935 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8936 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
8937 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8939 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8943 case SCmode
: mode
= SFmode
; break;
8944 case DCmode
: mode
= DFmode
; break;
8945 case TCmode
: mode
= TFmode
; break;
8949 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8950 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8952 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8953 && (mode
== TFmode
|| mode
== TDmode
));
8954 /* Long double or _Decimal128 split over regs and memory. */
8955 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
8959 = gen_rtx_EXPR_LIST (VOIDmode
,
8960 gen_rtx_REG (mode
, cum
->fregno
++),
8961 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8962 if (mode
== TFmode
|| mode
== TDmode
)
8965 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
8967 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8969 = gen_rtx_EXPR_LIST (VOIDmode
,
8970 gen_rtx_REG (mode
, cum
->vregno
++),
8971 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8973 else if (cum
->intoffset
== -1)
8974 cum
->intoffset
= bitpos
;
8978 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8979 the register(s) to be used for each field and subfield of a struct
8980 being passed by value, along with the offset of where the
8981 register's value may be found in the block. FP fields go in FP
8982 register, vector fields go in vector registers, and everything
8983 else goes in int registers, packed as in memory.
8985 This code is also used for function return values. RETVAL indicates
8986 whether this is the case.
8988 Much of this is taken from the SPARC V9 port, which has a similar
8989 calling convention. */
8992 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
8993 bool named
, bool retval
)
8995 rtx rvec
[FIRST_PSEUDO_REGISTER
];
8996 int k
= 1, kbase
= 1;
8997 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
8998 /* This is a copy; modifications are not visible to our caller. */
8999 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9000 CUMULATIVE_ARGS
*cum
= ©_cum
;
9002 /* Pad to 16 byte boundary if needed. */
9003 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9004 && (cum
->words
% 2) != 0)
9011 /* Put entries into rvec[] for individual FP and vector fields, and
9012 for the chunks of memory that go in int regs. Note we start at
9013 element 1; 0 is reserved for an indication of using memory, and
9014 may or may not be filled in below. */
9015 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9016 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9018 /* If any part of the struct went on the stack put all of it there.
9019 This hack is because the generic code for
9020 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9021 parts of the struct are not at the beginning. */
9025 return NULL_RTX
; /* doesn't go in registers at all */
9027 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9029 if (k
> 1 || cum
->use_stack
)
9030 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9035 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9038 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9043 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9045 if (align_words
>= GP_ARG_NUM_REG
)
9048 n_units
= rs6000_arg_size (mode
, type
);
9050 /* Optimize the simple case where the arg fits in one gpr, except in
9051 the case of BLKmode due to assign_parms assuming that registers are
9052 BITS_PER_WORD wide. */
9054 || (n_units
== 1 && mode
!= BLKmode
))
9055 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9058 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9059 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9060 using a magic NULL_RTX component.
9061 This is not strictly correct. Only some of the arg belongs in
9062 memory, not all of it. However, the normal scheme using
9063 function_arg_partial_nregs can result in unusual subregs, eg.
9064 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9065 store the whole arg to memory is often more efficient than code
9066 to store pieces, and we know that space is available in the right
9067 place for the whole arg. */
9068 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9073 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9074 rtx off
= GEN_INT (i
++ * 4);
9075 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9077 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9079 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9082 /* Determine where to put an argument to a function.
9083 Value is zero to push the argument on the stack,
9084 or a hard register in which to store the argument.
9086 MODE is the argument's machine mode.
9087 TYPE is the data type of the argument (as a tree).
9088 This is null for libcalls where that information may
9090 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9091 the preceding args and about the function being called. It is
9092 not modified in this routine.
9093 NAMED is nonzero if this argument is a named parameter
9094 (otherwise it is an extra parameter matching an ellipsis).
9096 On RS/6000 the first eight words of non-FP are normally in registers
9097 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
9098 Under V.4, the first 8 FP args are in registers.
9100 If this is floating-point and no prototype is specified, we use
9101 both an FP and integer register (or possibly FP reg and stack). Library
9102 functions (when CALL_LIBCALL is set) always have the proper types for args,
9103 so we can pass the FP value just in one register. emit_library_function
9104 doesn't support PARALLEL anyway.
9106 Note that for args passed by reference, function_arg will be called
9107 with MODE and TYPE set to that of the pointer to the arg, not the arg
9111 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
9112 const_tree type
, bool named
)
9114 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9115 enum rs6000_abi abi
= DEFAULT_ABI
;
9117 /* Return a marker to indicate whether CR1 needs to set or clear the
9118 bit that V.4 uses to say fp args were passed in registers.
9119 Assume that we don't need the marker for software floating point,
9120 or compiler generated library calls. */
9121 if (mode
== VOIDmode
)
9124 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
9126 || (cum
->nargs_prototype
< 0
9127 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
9129 /* For the SPE, we need to crxor CR6 always. */
9131 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
9132 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9133 return GEN_INT (cum
->call_cookie
9134 | ((cum
->fregno
== FP_ARG_MIN_REG
)
9135 ? CALL_V4_SET_FP_ARGS
9136 : CALL_V4_CLEAR_FP_ARGS
));
9139 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
9142 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9144 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
9145 if (rslt
!= NULL_RTX
)
9147 /* Else fall through to usual handling. */
9150 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
9151 if (TARGET_64BIT
&& ! cum
->prototype
)
9153 /* Vector parameters get passed in vector register
9154 and also in GPRs or memory, in absence of prototype. */
9157 align_words
= (cum
->words
+ 1) & ~1;
9159 if (align_words
>= GP_ARG_NUM_REG
)
9165 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9167 return gen_rtx_PARALLEL (mode
,
9169 gen_rtx_EXPR_LIST (VOIDmode
,
9171 gen_rtx_EXPR_LIST (VOIDmode
,
9172 gen_rtx_REG (mode
, cum
->vregno
),
9176 return gen_rtx_REG (mode
, cum
->vregno
);
9177 else if (TARGET_ALTIVEC_ABI
9178 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
9179 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9180 && int_size_in_bytes (type
) == 16)))
9182 if (named
|| abi
== ABI_V4
)
9186 /* Vector parameters to varargs functions under AIX or Darwin
9187 get passed in memory and possibly also in GPRs. */
9188 int align
, align_words
, n_words
;
9189 enum machine_mode part_mode
;
9191 /* Vector parameters must be 16-byte aligned. This places them at
9192 2 mod 4 in terms of words in 32-bit mode, since the parameter
9193 save area starts at offset 24 from the stack. In 64-bit mode,
9194 they just have to start on an even word, since the parameter
9195 save area is 16-byte aligned. */
9197 align
= (2 - cum
->words
) & 3;
9199 align
= cum
->words
& 1;
9200 align_words
= cum
->words
+ align
;
9202 /* Out of registers? Memory, then. */
9203 if (align_words
>= GP_ARG_NUM_REG
)
9206 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9207 return rs6000_mixed_function_arg (mode
, type
, align_words
);
9209 /* The vector value goes in GPRs. Only the part of the
9210 value in GPRs is reported here. */
9212 n_words
= rs6000_arg_size (mode
, type
);
9213 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9214 /* Fortunately, there are only two possibilities, the value
9215 is either wholly in GPRs or half in GPRs and half not. */
9218 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
9221 else if (TARGET_SPE_ABI
&& TARGET_SPE
9222 && (SPE_VECTOR_MODE (mode
)
9223 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
9226 || mode
== TCmode
))))
9227 return rs6000_spe_function_arg (cum
, mode
, type
);
9229 else if (abi
== ABI_V4
)
9231 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9232 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9233 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9234 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9235 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9237 /* _Decimal128 must use an even/odd register pair. This assumes
9238 that the register number is odd when fregno is odd. */
9239 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9242 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9243 <= FP_ARG_V4_MAX_REG
)
9244 return gen_rtx_REG (mode
, cum
->fregno
);
9250 int n_words
= rs6000_arg_size (mode
, type
);
9251 int gregno
= cum
->sysv_gregno
;
9253 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9254 (r7,r8) or (r9,r10). As does any other 2 word item such
9255 as complex int due to a historical mistake. */
9257 gregno
+= (1 - gregno
) & 1;
9259 /* Multi-reg args are not split between registers and stack. */
9260 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9263 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9264 return rs6000_mixed_function_arg (mode
, type
,
9265 gregno
- GP_ARG_MIN_REG
);
9266 return gen_rtx_REG (mode
, gregno
);
9271 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
9273 /* _Decimal128 must be passed in an even/odd float register pair.
9274 This assumes that the register number is odd when fregno is odd. */
9275 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9278 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
9280 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9284 enum machine_mode fmode
= mode
;
9285 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9287 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9289 /* Currently, we only ever need one reg here because complex
9290 doubles are split. */
9291 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9292 && (fmode
== TFmode
|| fmode
== TDmode
));
9294 /* Long double or _Decimal128 split over regs and memory. */
9295 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
9298 /* Do we also need to pass this arg in the parameter save
9301 && (cum
->nargs_prototype
<= 0
9302 || (DEFAULT_ABI
== ABI_AIX
9304 && align_words
>= GP_ARG_NUM_REG
)));
9306 if (!needs_psave
&& mode
== fmode
)
9307 return gen_rtx_REG (fmode
, cum
->fregno
);
9312 /* Describe the part that goes in gprs or the stack.
9313 This piece must come first, before the fprs. */
9314 if (align_words
< GP_ARG_NUM_REG
)
9316 unsigned long n_words
= rs6000_arg_size (mode
, type
);
9318 if (align_words
+ n_words
> GP_ARG_NUM_REG
9319 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9321 /* If this is partially on the stack, then we only
9322 include the portion actually in registers here. */
9323 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9326 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9327 /* Not all of the arg fits in gprs. Say that it
9328 goes in memory too, using a magic NULL_RTX
9329 component. Also see comment in
9330 rs6000_mixed_function_arg for why the normal
9331 function_arg_partial_nregs scheme doesn't work
9333 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
9337 r
= gen_rtx_REG (rmode
,
9338 GP_ARG_MIN_REG
+ align_words
);
9339 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9340 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9342 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9346 /* The whole arg fits in gprs. */
9347 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9348 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9352 /* It's entirely in memory. */
9353 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9356 /* Describe where this piece goes in the fprs. */
9357 r
= gen_rtx_REG (fmode
, cum
->fregno
);
9358 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9360 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9362 else if (align_words
< GP_ARG_NUM_REG
)
9364 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9365 return rs6000_mixed_function_arg (mode
, type
, align_words
);
9367 if (mode
== BLKmode
)
9370 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9377 /* For an arg passed partly in registers and partly in memory, this is
9378 the number of bytes passed in registers. For args passed entirely in
9379 registers or entirely in memory, zero. When an arg is described by a
9380 PARALLEL, perhaps using more than one register type, this function
9381 returns the number of bytes used by the first element of the PARALLEL. */
9384 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
9385 tree type
, bool named
)
9387 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9391 if (DEFAULT_ABI
== ABI_V4
)
9394 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
9395 && cum
->nargs_prototype
>= 0)
9398 /* In this complicated case we just disable the partial_nregs code. */
9399 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9402 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
9404 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
9406 /* If we are passing this arg in the fixed parameter save area
9407 (gprs or memory) as well as fprs, then this function should
9408 return the number of partial bytes passed in the parameter
9409 save area rather than partial bytes passed in fprs. */
9411 && (cum
->nargs_prototype
<= 0
9412 || (DEFAULT_ABI
== ABI_AIX
9414 && align_words
>= GP_ARG_NUM_REG
)))
9416 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
9417 > FP_ARG_MAX_REG
+ 1)
9418 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
9419 else if (cum
->nargs_prototype
>= 0)
9423 if (align_words
< GP_ARG_NUM_REG
9424 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
9425 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
9427 if (ret
!= 0 && TARGET_DEBUG_ARG
)
9428 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
9433 /* A C expression that indicates when an argument must be passed by
9434 reference. If nonzero for an argument, a copy of that argument is
9435 made in memory and a pointer to the argument is passed instead of
9436 the argument itself. The pointer is passed in whatever way is
9437 appropriate for passing a pointer to that type.
9439 Under V.4, aggregates and long double are passed by reference.
9441 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
9442 reference unless the AltiVec vector extension ABI is in force.
9444 As an extension to all ABIs, variable sized types are passed by
9448 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
9449 enum machine_mode mode
, const_tree type
,
9450 bool named ATTRIBUTE_UNUSED
)
9452 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
9454 if (TARGET_DEBUG_ARG
)
9455 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
9462 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
9464 if (TARGET_DEBUG_ARG
)
9465 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
9469 if (int_size_in_bytes (type
) < 0)
9471 if (TARGET_DEBUG_ARG
)
9472 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
9476 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9477 modes only exist for GCC vector types if -maltivec. */
9478 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
9480 if (TARGET_DEBUG_ARG
)
9481 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
9485 /* Pass synthetic vectors in memory. */
9486 if (TREE_CODE (type
) == VECTOR_TYPE
9487 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
9489 static bool warned_for_pass_big_vectors
= false;
9490 if (TARGET_DEBUG_ARG
)
9491 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
9492 if (!warned_for_pass_big_vectors
)
9494 warning (0, "GCC vector passed by reference: "
9495 "non-standard ABI extension with no compatibility guarantee");
9496 warned_for_pass_big_vectors
= true;
9505 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
9508 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
9513 for (i
= 0; i
< nregs
; i
++)
9515 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
9516 if (reload_completed
)
9518 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
9521 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
9522 i
* GET_MODE_SIZE (reg_mode
));
9525 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
9529 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
9533 /* Perform any needed actions needed for a function that is receiving a
9534 variable number of arguments.
9538 MODE and TYPE are the mode and type of the current parameter.
9540 PRETEND_SIZE is a variable that should be set to the amount of stack
9541 that must be pushed by the prolog to pretend that our caller pushed
9544 Normally, this macro will push all remaining incoming registers on the
9545 stack and set PRETEND_SIZE to the length of the registers pushed. */
9548 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
9549 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
9552 CUMULATIVE_ARGS next_cum
;
9553 int reg_size
= TARGET_32BIT
? 4 : 8;
9554 rtx save_area
= NULL_RTX
, mem
;
9555 int first_reg_offset
;
9558 /* Skip the last named argument. */
9559 next_cum
= *get_cumulative_args (cum
);
9560 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
9562 if (DEFAULT_ABI
== ABI_V4
)
9564 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
9568 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
9569 HOST_WIDE_INT offset
= 0;
9571 /* Try to optimize the size of the varargs save area.
9572 The ABI requires that ap.reg_save_area is doubleword
9573 aligned, but we don't need to allocate space for all
9574 the bytes, only those to which we actually will save
9576 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
9577 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
9578 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9579 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
9580 && cfun
->va_list_fpr_size
)
9583 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
9584 * UNITS_PER_FP_WORD
;
9585 if (cfun
->va_list_fpr_size
9586 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
9587 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
9589 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
9590 * UNITS_PER_FP_WORD
;
9594 offset
= -((first_reg_offset
* reg_size
) & ~7);
9595 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
9597 gpr_reg_num
= cfun
->va_list_gpr_size
;
9598 if (reg_size
== 4 && (first_reg_offset
& 1))
9601 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
9604 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
9606 - (int) (GP_ARG_NUM_REG
* reg_size
);
9608 if (gpr_size
+ fpr_size
)
9611 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
9612 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
9613 reg_save_area
= XEXP (reg_save_area
, 0);
9614 if (GET_CODE (reg_save_area
) == PLUS
)
9616 gcc_assert (XEXP (reg_save_area
, 0)
9617 == virtual_stack_vars_rtx
);
9618 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
9619 offset
+= INTVAL (XEXP (reg_save_area
, 1));
9622 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
9625 cfun
->machine
->varargs_save_offset
= offset
;
9626 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
9631 first_reg_offset
= next_cum
.words
;
9632 save_area
= virtual_incoming_args_rtx
;
9634 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
9635 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
9638 set
= get_varargs_alias_set ();
9639 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
9640 && cfun
->va_list_gpr_size
)
9642 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
9644 if (va_list_gpr_counter_field
)
9645 /* V4 va_list_gpr_size counts number of registers needed. */
9646 n_gpr
= cfun
->va_list_gpr_size
;
9648 /* char * va_list instead counts number of bytes needed. */
9649 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
9654 mem
= gen_rtx_MEM (BLKmode
,
9655 plus_constant (Pmode
, save_area
,
9656 first_reg_offset
* reg_size
));
9657 MEM_NOTRAP_P (mem
) = 1;
9658 set_mem_alias_set (mem
, set
);
9659 set_mem_align (mem
, BITS_PER_WORD
);
9661 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
9665 /* Save FP registers if needed. */
9666 if (DEFAULT_ABI
== ABI_V4
9667 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9669 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
9670 && cfun
->va_list_fpr_size
)
9672 int fregno
= next_cum
.fregno
, nregs
;
9673 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
9674 rtx lab
= gen_label_rtx ();
9675 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
9676 * UNITS_PER_FP_WORD
);
9679 (gen_rtx_SET (VOIDmode
,
9681 gen_rtx_IF_THEN_ELSE (VOIDmode
,
9682 gen_rtx_NE (VOIDmode
, cr1
,
9684 gen_rtx_LABEL_REF (VOIDmode
, lab
),
9688 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
9689 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
9691 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9693 plus_constant (Pmode
, save_area
, off
));
9694 MEM_NOTRAP_P (mem
) = 1;
9695 set_mem_alias_set (mem
, set
);
9696 set_mem_align (mem
, GET_MODE_ALIGNMENT (
9697 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9698 ? DFmode
: SFmode
));
9699 emit_move_insn (mem
, gen_rtx_REG (
9700 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9701 ? DFmode
: SFmode
, fregno
));
9708 /* Create the va_list data type. */
9711 rs6000_build_builtin_va_list (void)
9713 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
9715 /* For AIX, prefer 'char *' because that's what the system
9716 header files like. */
9717 if (DEFAULT_ABI
!= ABI_V4
)
9718 return build_pointer_type (char_type_node
);
9720 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
9721 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
9722 get_identifier ("__va_list_tag"), record
);
9724 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
9725 unsigned_char_type_node
);
9726 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
9727 unsigned_char_type_node
);
9728 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9730 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9731 get_identifier ("reserved"), short_unsigned_type_node
);
9732 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9733 get_identifier ("overflow_arg_area"),
9735 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9736 get_identifier ("reg_save_area"),
9739 va_list_gpr_counter_field
= f_gpr
;
9740 va_list_fpr_counter_field
= f_fpr
;
9742 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9743 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9744 DECL_FIELD_CONTEXT (f_res
) = record
;
9745 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9746 DECL_FIELD_CONTEXT (f_sav
) = record
;
9748 TYPE_STUB_DECL (record
) = type_decl
;
9749 TYPE_NAME (record
) = type_decl
;
9750 TYPE_FIELDS (record
) = f_gpr
;
9751 DECL_CHAIN (f_gpr
) = f_fpr
;
9752 DECL_CHAIN (f_fpr
) = f_res
;
9753 DECL_CHAIN (f_res
) = f_ovf
;
9754 DECL_CHAIN (f_ovf
) = f_sav
;
9756 layout_type (record
);
9758 /* The correct type is an array type of one element. */
9759 return build_array_type (record
, build_index_type (size_zero_node
));
9762 /* Implement va_start. */
9765 rs6000_va_start (tree valist
, rtx nextarg
)
9767 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
9768 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9769 tree gpr
, fpr
, ovf
, sav
, t
;
9771 /* Only SVR4 needs something special. */
9772 if (DEFAULT_ABI
!= ABI_V4
)
9774 std_expand_builtin_va_start (valist
, nextarg
);
9778 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9779 f_fpr
= DECL_CHAIN (f_gpr
);
9780 f_res
= DECL_CHAIN (f_fpr
);
9781 f_ovf
= DECL_CHAIN (f_res
);
9782 f_sav
= DECL_CHAIN (f_ovf
);
9784 valist
= build_simple_mem_ref (valist
);
9785 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9786 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9788 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9790 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9793 /* Count number of gp and fp argument registers used. */
9794 words
= crtl
->args
.info
.words
;
9795 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
9797 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
9800 if (TARGET_DEBUG_ARG
)
9801 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
9802 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
9803 words
, n_gpr
, n_fpr
);
9805 if (cfun
->va_list_gpr_size
)
9807 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9808 build_int_cst (NULL_TREE
, n_gpr
));
9809 TREE_SIDE_EFFECTS (t
) = 1;
9810 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9813 if (cfun
->va_list_fpr_size
)
9815 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9816 build_int_cst (NULL_TREE
, n_fpr
));
9817 TREE_SIDE_EFFECTS (t
) = 1;
9818 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9820 #ifdef HAVE_AS_GNU_ATTRIBUTE
9821 if (call_ABI_of_interest (cfun
->decl
))
9822 rs6000_passes_float
= true;
9826 /* Find the overflow area. */
9827 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9829 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
9830 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9831 TREE_SIDE_EFFECTS (t
) = 1;
9832 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9834 /* If there were no va_arg invocations, don't set up the register
9836 if (!cfun
->va_list_gpr_size
9837 && !cfun
->va_list_fpr_size
9838 && n_gpr
< GP_ARG_NUM_REG
9839 && n_fpr
< FP_ARG_V4_MAX_REG
)
9842 /* Find the register save area. */
9843 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
9844 if (cfun
->machine
->varargs_save_offset
)
9845 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
9846 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9847 TREE_SIDE_EFFECTS (t
) = 1;
9848 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9851 /* Implement va_arg. */
9854 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9857 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9858 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9859 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
9860 tree lab_false
, lab_over
, addr
;
9862 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9866 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9868 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
9869 return build_va_arg_indirect_ref (t
);
9872 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9873 earlier version of gcc, with the property that it always applied alignment
9874 adjustments to the va-args (even for zero-sized types). The cheapest way
9875 to deal with this is to replicate the effect of the part of
9876 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9878 We don't need to check for pass-by-reference because of the test above.
9879 We can return a simplifed answer, since we know there's no offset to add. */
9882 && rs6000_darwin64_abi
9883 && integer_zerop (TYPE_SIZE (type
)))
9885 unsigned HOST_WIDE_INT align
, boundary
;
9886 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
9887 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
9888 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
9889 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
9890 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
9891 boundary
/= BITS_PER_UNIT
;
9892 if (boundary
> align
)
9895 /* This updates arg ptr by the amount that would be necessary
9896 to align the zero-sized (but not zero-alignment) item. */
9897 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9898 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
9899 gimplify_and_add (t
, pre_p
);
9901 t
= fold_convert (sizetype
, valist_tmp
);
9902 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9903 fold_convert (TREE_TYPE (valist
),
9904 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
9905 size_int (-boundary
))));
9906 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
9907 gimplify_and_add (t
, pre_p
);
9909 /* Since it is zero-sized there's no increment for the item itself. */
9910 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
9911 return build_va_arg_indirect_ref (valist_tmp
);
9914 if (DEFAULT_ABI
!= ABI_V4
)
9916 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
9918 tree elem_type
= TREE_TYPE (type
);
9919 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
9920 int elem_size
= GET_MODE_SIZE (elem_mode
);
9922 if (elem_size
< UNITS_PER_WORD
)
9924 tree real_part
, imag_part
;
9925 gimple_seq post
= NULL
;
9927 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9929 /* Copy the value into a temporary, lest the formal temporary
9930 be reused out from under us. */
9931 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
9932 gimple_seq_add_seq (pre_p
, post
);
9934 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9937 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
9941 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
9944 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9945 f_fpr
= DECL_CHAIN (f_gpr
);
9946 f_res
= DECL_CHAIN (f_fpr
);
9947 f_ovf
= DECL_CHAIN (f_res
);
9948 f_sav
= DECL_CHAIN (f_ovf
);
9950 valist
= build_va_arg_indirect_ref (valist
);
9951 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9952 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9954 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9956 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9959 size
= int_size_in_bytes (type
);
9960 rsize
= (size
+ 3) / 4;
9963 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9964 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
9965 || (TARGET_DOUBLE_FLOAT
9966 && (TYPE_MODE (type
) == DFmode
9967 || TYPE_MODE (type
) == TFmode
9968 || TYPE_MODE (type
) == SDmode
9969 || TYPE_MODE (type
) == DDmode
9970 || TYPE_MODE (type
) == TDmode
))))
9972 /* FP args go in FP registers, if present. */
9974 n_reg
= (size
+ 7) / 8;
9975 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
9976 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
9977 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
9982 /* Otherwise into GP registers. */
9991 /* Pull the value out of the saved registers.... */
9994 addr
= create_tmp_var (ptr_type_node
, "addr");
9996 /* AltiVec vectors never go in registers when -mabi=altivec. */
9997 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10001 lab_false
= create_artificial_label (input_location
);
10002 lab_over
= create_artificial_label (input_location
);
10004 /* Long long and SPE vectors are aligned in the registers.
10005 As are any other 2 gpr item such as complex int due to a
10006 historical mistake. */
10008 if (n_reg
== 2 && reg
== gpr
)
10011 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10012 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
10013 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
10014 unshare_expr (reg
), u
);
10016 /* _Decimal128 is passed in even/odd fpr pairs; the stored
10017 reg number is 0 for f1, so we want to make it odd. */
10018 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
10020 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10021 build_int_cst (TREE_TYPE (reg
), 1));
10022 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
10025 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
10026 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
10027 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
10028 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
10029 gimplify_and_add (t
, pre_p
);
10033 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
10035 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10036 build_int_cst (TREE_TYPE (reg
), n_reg
));
10037 u
= fold_convert (sizetype
, u
);
10038 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
10039 t
= fold_build_pointer_plus (t
, u
);
10041 /* _Decimal32 varargs are located in the second word of the 64-bit
10042 FP register for 32-bit binaries. */
10043 if (!TARGET_POWERPC64
10044 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10045 && TYPE_MODE (type
) == SDmode
)
10046 t
= fold_build_pointer_plus_hwi (t
, size
);
10048 gimplify_assign (addr
, t
, pre_p
);
10050 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
10052 stmt
= gimple_build_label (lab_false
);
10053 gimple_seq_add_stmt (pre_p
, stmt
);
10055 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
10057 /* Ensure that we don't find any more args in regs.
10058 Alignment has taken care of for special cases. */
10059 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
10063 /* ... otherwise out of the overflow area. */
10065 /* Care for on-stack alignment if needed. */
10069 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
10070 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
10071 build_int_cst (TREE_TYPE (t
), -align
));
10073 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
10075 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
10077 t
= fold_build_pointer_plus_hwi (t
, size
);
10078 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
10082 stmt
= gimple_build_label (lab_over
);
10083 gimple_seq_add_stmt (pre_p
, stmt
);
10086 if (STRICT_ALIGNMENT
10087 && (TYPE_ALIGN (type
)
10088 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
10090 /* The value (of type complex double, for example) may not be
10091 aligned in memory in the saved registers, so copy via a
10092 temporary. (This is the same code as used for SPARC.) */
10093 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
10094 tree dest_addr
= build_fold_addr_expr (tmp
);
10096 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
10097 3, dest_addr
, addr
, size_int (rsize
* 4));
10099 gimplify_and_add (copy
, pre_p
);
10103 addr
= fold_convert (ptrtype
, addr
);
10104 return build_va_arg_indirect_ref (addr
);
10110 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
10113 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
10114 const char *attr_string
= "";
10116 gcc_assert (name
!= NULL
);
10117 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
10119 if (rs6000_builtin_decls
[(int)code
])
10120 fatal_error ("internal error: builtin function %s already processed", name
);
10122 rs6000_builtin_decls
[(int)code
] = t
=
10123 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10125 /* Set any special attributes. */
10126 if ((classify
& RS6000_BTC_CONST
) != 0)
10128 /* const function, function only depends on the inputs. */
10129 TREE_READONLY (t
) = 1;
10130 TREE_NOTHROW (t
) = 1;
10131 attr_string
= ", pure";
10133 else if ((classify
& RS6000_BTC_PURE
) != 0)
10135 /* pure function, function can read global memory, but does not set any
10137 DECL_PURE_P (t
) = 1;
10138 TREE_NOTHROW (t
) = 1;
10139 attr_string
= ", const";
10141 else if ((classify
& RS6000_BTC_FP
) != 0)
10143 /* Function is a math function. If rounding mode is on, then treat the
10144 function as not reading global memory, but it can have arbitrary side
10145 effects. If it is off, then assume the function is a const function.
10146 This mimics the ATTR_MATHFN_FPROUNDING attribute in
10147 builtin-attribute.def that is used for the math functions. */
10148 TREE_NOTHROW (t
) = 1;
10149 if (flag_rounding_math
)
10151 DECL_PURE_P (t
) = 1;
10152 DECL_IS_NOVOPS (t
) = 1;
10153 attr_string
= ", fp, pure";
10157 TREE_READONLY (t
) = 1;
10158 attr_string
= ", fp, const";
10161 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
10162 gcc_unreachable ();
10164 if (TARGET_DEBUG_BUILTIN
)
10165 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
10166 (int)code
, name
, attr_string
);
10169 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
10171 #undef RS6000_BUILTIN_1
10172 #undef RS6000_BUILTIN_2
10173 #undef RS6000_BUILTIN_3
10174 #undef RS6000_BUILTIN_A
10175 #undef RS6000_BUILTIN_D
10176 #undef RS6000_BUILTIN_E
10177 #undef RS6000_BUILTIN_H
10178 #undef RS6000_BUILTIN_P
10179 #undef RS6000_BUILTIN_Q
10180 #undef RS6000_BUILTIN_S
10181 #undef RS6000_BUILTIN_X
10183 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10184 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10185 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
10186 { MASK, ICODE, NAME, ENUM },
10188 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10189 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10190 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10191 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10192 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10193 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10194 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10195 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10197 static const struct builtin_description bdesc_3arg
[] =
10199 #include "rs6000-builtin.def"
10202 /* DST operations: void foo (void *, const int, const char). */
10204 #undef RS6000_BUILTIN_1
10205 #undef RS6000_BUILTIN_2
10206 #undef RS6000_BUILTIN_3
10207 #undef RS6000_BUILTIN_A
10208 #undef RS6000_BUILTIN_D
10209 #undef RS6000_BUILTIN_E
10210 #undef RS6000_BUILTIN_H
10211 #undef RS6000_BUILTIN_P
10212 #undef RS6000_BUILTIN_Q
10213 #undef RS6000_BUILTIN_S
10214 #undef RS6000_BUILTIN_X
10216 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10217 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10218 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10219 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10220 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
10221 { MASK, ICODE, NAME, ENUM },
10223 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10224 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10225 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10226 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10227 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10228 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10230 static const struct builtin_description bdesc_dst
[] =
10232 #include "rs6000-builtin.def"
10235 /* Simple binary operations: VECc = foo (VECa, VECb). */
10237 #undef RS6000_BUILTIN_1
10238 #undef RS6000_BUILTIN_2
10239 #undef RS6000_BUILTIN_3
10240 #undef RS6000_BUILTIN_A
10241 #undef RS6000_BUILTIN_D
10242 #undef RS6000_BUILTIN_E
10243 #undef RS6000_BUILTIN_H
10244 #undef RS6000_BUILTIN_P
10245 #undef RS6000_BUILTIN_Q
10246 #undef RS6000_BUILTIN_S
10247 #undef RS6000_BUILTIN_X
10249 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10250 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
10251 { MASK, ICODE, NAME, ENUM },
10253 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10254 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10255 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10256 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10257 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10258 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10259 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10260 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10261 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10263 static const struct builtin_description bdesc_2arg
[] =
10265 #include "rs6000-builtin.def"
10268 #undef RS6000_BUILTIN_1
10269 #undef RS6000_BUILTIN_2
10270 #undef RS6000_BUILTIN_3
10271 #undef RS6000_BUILTIN_A
10272 #undef RS6000_BUILTIN_D
10273 #undef RS6000_BUILTIN_E
10274 #undef RS6000_BUILTIN_H
10275 #undef RS6000_BUILTIN_P
10276 #undef RS6000_BUILTIN_Q
10277 #undef RS6000_BUILTIN_S
10278 #undef RS6000_BUILTIN_X
10280 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10281 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10282 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10283 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10284 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10285 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10286 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10287 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
10288 { MASK, ICODE, NAME, ENUM },
10290 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10291 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10292 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10294 /* AltiVec predicates. */
10296 static const struct builtin_description bdesc_altivec_preds
[] =
10298 #include "rs6000-builtin.def"
10301 /* SPE predicates. */
10302 #undef RS6000_BUILTIN_1
10303 #undef RS6000_BUILTIN_2
10304 #undef RS6000_BUILTIN_3
10305 #undef RS6000_BUILTIN_A
10306 #undef RS6000_BUILTIN_D
10307 #undef RS6000_BUILTIN_E
10308 #undef RS6000_BUILTIN_H
10309 #undef RS6000_BUILTIN_P
10310 #undef RS6000_BUILTIN_Q
10311 #undef RS6000_BUILTIN_S
10312 #undef RS6000_BUILTIN_X
10314 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10315 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10316 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10317 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10318 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10319 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10320 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10321 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10322 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10323 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
10324 { MASK, ICODE, NAME, ENUM },
10326 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10328 static const struct builtin_description bdesc_spe_predicates
[] =
10330 #include "rs6000-builtin.def"
10333 /* SPE evsel predicates. */
10334 #undef RS6000_BUILTIN_1
10335 #undef RS6000_BUILTIN_2
10336 #undef RS6000_BUILTIN_3
10337 #undef RS6000_BUILTIN_A
10338 #undef RS6000_BUILTIN_D
10339 #undef RS6000_BUILTIN_E
10340 #undef RS6000_BUILTIN_H
10341 #undef RS6000_BUILTIN_P
10342 #undef RS6000_BUILTIN_Q
10343 #undef RS6000_BUILTIN_S
10344 #undef RS6000_BUILTIN_X
10346 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10347 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10348 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10349 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10350 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10351 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
10352 { MASK, ICODE, NAME, ENUM },
10354 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10355 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10356 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10357 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10358 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10360 static const struct builtin_description bdesc_spe_evsel
[] =
10362 #include "rs6000-builtin.def"
10365 /* PAIRED predicates. */
10366 #undef RS6000_BUILTIN_1
10367 #undef RS6000_BUILTIN_2
10368 #undef RS6000_BUILTIN_3
10369 #undef RS6000_BUILTIN_A
10370 #undef RS6000_BUILTIN_D
10371 #undef RS6000_BUILTIN_E
10372 #undef RS6000_BUILTIN_H
10373 #undef RS6000_BUILTIN_P
10374 #undef RS6000_BUILTIN_Q
10375 #undef RS6000_BUILTIN_S
10376 #undef RS6000_BUILTIN_X
10378 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10379 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10380 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10381 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10382 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10383 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10384 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10385 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10386 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
10387 { MASK, ICODE, NAME, ENUM },
10389 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10390 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10392 static const struct builtin_description bdesc_paired_preds
[] =
10394 #include "rs6000-builtin.def"
10397 /* ABS* operations. */
10399 #undef RS6000_BUILTIN_1
10400 #undef RS6000_BUILTIN_2
10401 #undef RS6000_BUILTIN_3
10402 #undef RS6000_BUILTIN_A
10403 #undef RS6000_BUILTIN_D
10404 #undef RS6000_BUILTIN_E
10405 #undef RS6000_BUILTIN_H
10406 #undef RS6000_BUILTIN_P
10407 #undef RS6000_BUILTIN_Q
10408 #undef RS6000_BUILTIN_S
10409 #undef RS6000_BUILTIN_X
10411 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10412 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10413 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10414 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
10415 { MASK, ICODE, NAME, ENUM },
10417 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10418 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10419 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10420 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10421 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10422 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10423 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10425 static const struct builtin_description bdesc_abs
[] =
10427 #include "rs6000-builtin.def"
10430 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
10433 #undef RS6000_BUILTIN_1
10434 #undef RS6000_BUILTIN_2
10435 #undef RS6000_BUILTIN_3
10436 #undef RS6000_BUILTIN_A
10437 #undef RS6000_BUILTIN_D
10438 #undef RS6000_BUILTIN_E
10439 #undef RS6000_BUILTIN_H
10440 #undef RS6000_BUILTIN_P
10441 #undef RS6000_BUILTIN_Q
10442 #undef RS6000_BUILTIN_S
10443 #undef RS6000_BUILTIN_X
10445 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
10446 { MASK, ICODE, NAME, ENUM },
10448 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10449 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10450 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10451 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10452 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10453 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10454 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10455 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10456 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10457 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10459 static const struct builtin_description bdesc_1arg
[] =
10461 #include "rs6000-builtin.def"
10464 /* HTM builtins. */
10465 #undef RS6000_BUILTIN_1
10466 #undef RS6000_BUILTIN_2
10467 #undef RS6000_BUILTIN_3
10468 #undef RS6000_BUILTIN_A
10469 #undef RS6000_BUILTIN_D
10470 #undef RS6000_BUILTIN_E
10471 #undef RS6000_BUILTIN_H
10472 #undef RS6000_BUILTIN_P
10473 #undef RS6000_BUILTIN_Q
10474 #undef RS6000_BUILTIN_S
10475 #undef RS6000_BUILTIN_X
10477 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10478 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10479 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10480 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10481 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10482 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10483 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
10484 { MASK, ICODE, NAME, ENUM },
10486 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10487 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10488 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10489 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10491 static const struct builtin_description bdesc_htm
[] =
10493 #include "rs6000-builtin.def"
10496 #undef RS6000_BUILTIN_1
10497 #undef RS6000_BUILTIN_2
10498 #undef RS6000_BUILTIN_3
10499 #undef RS6000_BUILTIN_A
10500 #undef RS6000_BUILTIN_D
10501 #undef RS6000_BUILTIN_E
10502 #undef RS6000_BUILTIN_H
10503 #undef RS6000_BUILTIN_P
10504 #undef RS6000_BUILTIN_Q
10505 #undef RS6000_BUILTIN_S
10507 /* Return true if a builtin function is overloaded. */
10509 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
10511 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
10514 /* Expand an expression EXP that calls a builtin without arguments. */
10516 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
10519 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10521 if (icode
== CODE_FOR_nothing
)
10522 /* Builtin not supported on this processor. */
10526 || GET_MODE (target
) != tmode
10527 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10528 target
= gen_reg_rtx (tmode
);
10530 pat
= GEN_FCN (icode
) (target
);
10540 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10543 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10544 rtx op0
= expand_normal (arg0
);
10545 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10546 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10548 if (icode
== CODE_FOR_nothing
)
10549 /* Builtin not supported on this processor. */
10552 /* If we got invalid arguments bail out before generating bad rtl. */
10553 if (arg0
== error_mark_node
)
10556 if (icode
== CODE_FOR_altivec_vspltisb
10557 || icode
== CODE_FOR_altivec_vspltish
10558 || icode
== CODE_FOR_altivec_vspltisw
10559 || icode
== CODE_FOR_spe_evsplatfi
10560 || icode
== CODE_FOR_spe_evsplati
)
10562 /* Only allow 5-bit *signed* literals. */
10563 if (GET_CODE (op0
) != CONST_INT
10564 || INTVAL (op0
) > 15
10565 || INTVAL (op0
) < -16)
10567 error ("argument 1 must be a 5-bit signed literal");
10573 || GET_MODE (target
) != tmode
10574 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10575 target
= gen_reg_rtx (tmode
);
10577 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10578 op0
= copy_to_mode_reg (mode0
, op0
);
10580 pat
= GEN_FCN (icode
) (target
, op0
);
10589 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
10591 rtx pat
, scratch1
, scratch2
;
10592 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10593 rtx op0
= expand_normal (arg0
);
10594 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10595 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10597 /* If we have invalid arguments, bail out before generating bad rtl. */
10598 if (arg0
== error_mark_node
)
10602 || GET_MODE (target
) != tmode
10603 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10604 target
= gen_reg_rtx (tmode
);
10606 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10607 op0
= copy_to_mode_reg (mode0
, op0
);
10609 scratch1
= gen_reg_rtx (mode0
);
10610 scratch2
= gen_reg_rtx (mode0
);
10612 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
10621 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10624 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10625 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10626 rtx op0
= expand_normal (arg0
);
10627 rtx op1
= expand_normal (arg1
);
10628 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10629 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10630 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10632 if (icode
== CODE_FOR_nothing
)
10633 /* Builtin not supported on this processor. */
10636 /* If we got invalid arguments bail out before generating bad rtl. */
10637 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10640 if (icode
== CODE_FOR_altivec_vcfux
10641 || icode
== CODE_FOR_altivec_vcfsx
10642 || icode
== CODE_FOR_altivec_vctsxs
10643 || icode
== CODE_FOR_altivec_vctuxs
10644 || icode
== CODE_FOR_altivec_vspltb
10645 || icode
== CODE_FOR_altivec_vsplth
10646 || icode
== CODE_FOR_altivec_vspltw
10647 || icode
== CODE_FOR_spe_evaddiw
10648 || icode
== CODE_FOR_spe_evldd
10649 || icode
== CODE_FOR_spe_evldh
10650 || icode
== CODE_FOR_spe_evldw
10651 || icode
== CODE_FOR_spe_evlhhesplat
10652 || icode
== CODE_FOR_spe_evlhhossplat
10653 || icode
== CODE_FOR_spe_evlhhousplat
10654 || icode
== CODE_FOR_spe_evlwhe
10655 || icode
== CODE_FOR_spe_evlwhos
10656 || icode
== CODE_FOR_spe_evlwhou
10657 || icode
== CODE_FOR_spe_evlwhsplat
10658 || icode
== CODE_FOR_spe_evlwwsplat
10659 || icode
== CODE_FOR_spe_evrlwi
10660 || icode
== CODE_FOR_spe_evslwi
10661 || icode
== CODE_FOR_spe_evsrwis
10662 || icode
== CODE_FOR_spe_evsubifw
10663 || icode
== CODE_FOR_spe_evsrwiu
)
10665 /* Only allow 5-bit unsigned literals. */
10667 if (TREE_CODE (arg1
) != INTEGER_CST
10668 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
10670 error ("argument 2 must be a 5-bit unsigned literal");
10676 || GET_MODE (target
) != tmode
10677 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10678 target
= gen_reg_rtx (tmode
);
10680 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10681 op0
= copy_to_mode_reg (mode0
, op0
);
10682 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10683 op1
= copy_to_mode_reg (mode1
, op1
);
10685 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
10694 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
10697 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
10698 tree arg0
= CALL_EXPR_ARG (exp
, 1);
10699 tree arg1
= CALL_EXPR_ARG (exp
, 2);
10700 rtx op0
= expand_normal (arg0
);
10701 rtx op1
= expand_normal (arg1
);
10702 enum machine_mode tmode
= SImode
;
10703 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10704 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10707 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
10709 error ("argument 1 of __builtin_altivec_predicate must be a constant");
10713 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
10715 gcc_assert (mode0
== mode1
);
10717 /* If we have invalid arguments, bail out before generating bad rtl. */
10718 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10722 || GET_MODE (target
) != tmode
10723 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10724 target
= gen_reg_rtx (tmode
);
10726 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10727 op0
= copy_to_mode_reg (mode0
, op0
);
10728 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10729 op1
= copy_to_mode_reg (mode1
, op1
);
10731 scratch
= gen_reg_rtx (mode0
);
10733 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
10738 /* The vec_any* and vec_all* predicates use the same opcodes for two
10739 different operations, but the bits in CR6 will be different
10740 depending on what information we want. So we have to play tricks
10741 with CR6 to get the right bits out.
10743 If you think this is disgusting, look at the specs for the
10744 AltiVec predicates. */
10746 switch (cr6_form_int
)
10749 emit_insn (gen_cr6_test_for_zero (target
));
10752 emit_insn (gen_cr6_test_for_zero_reverse (target
));
10755 emit_insn (gen_cr6_test_for_lt (target
));
10758 emit_insn (gen_cr6_test_for_lt_reverse (target
));
10761 error ("argument 1 of __builtin_altivec_predicate is out of range");
10769 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
10772 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10773 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10774 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10775 enum machine_mode mode0
= Pmode
;
10776 enum machine_mode mode1
= Pmode
;
10777 rtx op0
= expand_normal (arg0
);
10778 rtx op1
= expand_normal (arg1
);
10780 if (icode
== CODE_FOR_nothing
)
10781 /* Builtin not supported on this processor. */
10784 /* If we got invalid arguments bail out before generating bad rtl. */
10785 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10789 || GET_MODE (target
) != tmode
10790 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10791 target
= gen_reg_rtx (tmode
);
10793 op1
= copy_to_mode_reg (mode1
, op1
);
10795 if (op0
== const0_rtx
)
10797 addr
= gen_rtx_MEM (tmode
, op1
);
10801 op0
= copy_to_mode_reg (mode0
, op0
);
10802 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10805 pat
= GEN_FCN (icode
) (target
, addr
);
10815 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
10818 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10819 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10820 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10821 enum machine_mode mode0
= Pmode
;
10822 enum machine_mode mode1
= Pmode
;
10823 rtx op0
= expand_normal (arg0
);
10824 rtx op1
= expand_normal (arg1
);
10826 if (icode
== CODE_FOR_nothing
)
10827 /* Builtin not supported on this processor. */
10830 /* If we got invalid arguments bail out before generating bad rtl. */
10831 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10835 || GET_MODE (target
) != tmode
10836 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10837 target
= gen_reg_rtx (tmode
);
10839 op1
= copy_to_mode_reg (mode1
, op1
);
10841 if (op0
== const0_rtx
)
10843 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
10847 op0
= copy_to_mode_reg (mode0
, op0
);
10848 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10851 pat
= GEN_FCN (icode
) (target
, addr
);
10861 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
10863 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10864 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10865 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10866 rtx op0
= expand_normal (arg0
);
10867 rtx op1
= expand_normal (arg1
);
10868 rtx op2
= expand_normal (arg2
);
10870 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
10871 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
10872 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
10874 /* Invalid arguments. Bail before doing anything stoopid! */
10875 if (arg0
== error_mark_node
10876 || arg1
== error_mark_node
10877 || arg2
== error_mark_node
)
10880 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
10881 op0
= copy_to_mode_reg (mode2
, op0
);
10882 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
10883 op1
= copy_to_mode_reg (mode0
, op1
);
10884 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
10885 op2
= copy_to_mode_reg (mode1
, op2
);
10887 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
10894 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
10896 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10897 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10898 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10899 rtx op0
= expand_normal (arg0
);
10900 rtx op1
= expand_normal (arg1
);
10901 rtx op2
= expand_normal (arg2
);
10903 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10904 enum machine_mode mode1
= Pmode
;
10905 enum machine_mode mode2
= Pmode
;
10907 /* Invalid arguments. Bail before doing anything stoopid! */
10908 if (arg0
== error_mark_node
10909 || arg1
== error_mark_node
10910 || arg2
== error_mark_node
)
10913 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
10914 op0
= copy_to_mode_reg (tmode
, op0
);
10916 op2
= copy_to_mode_reg (mode2
, op2
);
10918 if (op1
== const0_rtx
)
10920 addr
= gen_rtx_MEM (tmode
, op2
);
10924 op1
= copy_to_mode_reg (mode1
, op1
);
10925 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10928 pat
= GEN_FCN (icode
) (addr
, op0
);
10935 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
10937 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10938 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10939 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10940 rtx op0
= expand_normal (arg0
);
10941 rtx op1
= expand_normal (arg1
);
10942 rtx op2
= expand_normal (arg2
);
10944 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10945 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
10946 enum machine_mode mode1
= Pmode
;
10947 enum machine_mode mode2
= Pmode
;
10949 /* Invalid arguments. Bail before doing anything stoopid! */
10950 if (arg0
== error_mark_node
10951 || arg1
== error_mark_node
10952 || arg2
== error_mark_node
)
10955 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
10956 op0
= copy_to_mode_reg (smode
, op0
);
10958 op2
= copy_to_mode_reg (mode2
, op2
);
10960 if (op1
== const0_rtx
)
10962 addr
= gen_rtx_MEM (tmode
, op2
);
10966 op1
= copy_to_mode_reg (mode1
, op1
);
10967 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10970 pat
= GEN_FCN (icode
) (addr
, op0
);
10976 /* Return the appropriate SPR number associated with the given builtin. */
10977 static inline HOST_WIDE_INT
10978 htm_spr_num (enum rs6000_builtins code
)
10980 if (code
== HTM_BUILTIN_GET_TFHAR
10981 || code
== HTM_BUILTIN_SET_TFHAR
)
10983 else if (code
== HTM_BUILTIN_GET_TFIAR
10984 || code
== HTM_BUILTIN_SET_TFIAR
)
10986 else if (code
== HTM_BUILTIN_GET_TEXASR
10987 || code
== HTM_BUILTIN_SET_TEXASR
)
10989 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
10990 || code
== HTM_BUILTIN_SET_TEXASRU
);
10991 return TEXASRU_SPR
;
10994 /* Return the appropriate SPR regno associated with the given builtin. */
10995 static inline HOST_WIDE_INT
10996 htm_spr_regno (enum rs6000_builtins code
)
10998 if (code
== HTM_BUILTIN_GET_TFHAR
10999 || code
== HTM_BUILTIN_SET_TFHAR
)
11000 return TFHAR_REGNO
;
11001 else if (code
== HTM_BUILTIN_GET_TFIAR
11002 || code
== HTM_BUILTIN_SET_TFIAR
)
11003 return TFIAR_REGNO
;
11004 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
11005 || code
== HTM_BUILTIN_SET_TEXASR
11006 || code
== HTM_BUILTIN_GET_TEXASRU
11007 || code
== HTM_BUILTIN_SET_TEXASRU
);
11008 return TEXASR_REGNO
;
11011 /* Return the correct ICODE value depending on whether we are
11012 setting or reading the HTM SPRs. */
11013 static inline enum insn_code
11014 rs6000_htm_spr_icode (bool nonvoid
)
11017 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
11019 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
11022 /* Expand the HTM builtin in EXP and store the result in TARGET.
11023 Store true in *EXPANDEDP if we found a builtin to expand. */
11025 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
11027 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11028 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11029 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11030 const struct builtin_description
*d
;
11033 *expandedp
= false;
11035 /* Expand the HTM builtins. */
11037 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
11038 if (d
->code
== fcode
)
11040 rtx op
[MAX_HTM_OPERANDS
], pat
;
11043 call_expr_arg_iterator iter
;
11044 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
11045 enum insn_code icode
= d
->icode
;
11047 if (attr
& RS6000_BTC_SPR
)
11048 icode
= rs6000_htm_spr_icode (nonvoid
);
11052 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11054 || GET_MODE (target
) != tmode
11055 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11056 target
= gen_reg_rtx (tmode
);
11057 op
[nopnds
++] = target
;
11060 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11062 const struct insn_operand_data
*insn_op
;
11064 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
11067 insn_op
= &insn_data
[icode
].operand
[nopnds
];
11069 op
[nopnds
] = expand_normal (arg
);
11071 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
11073 if (!strcmp (insn_op
->constraint
, "n"))
11075 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
11076 if (!CONST_INT_P (op
[nopnds
]))
11077 error ("argument %d must be an unsigned literal", arg_num
);
11079 error ("argument %d is an unsigned literal that is "
11080 "out of range", arg_num
);
11083 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
11089 /* Handle the builtins for extended mnemonics. These accept
11090 no arguments, but map to builtins that take arguments. */
11093 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
11094 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
11095 op
[nopnds
++] = GEN_INT (1);
11096 #ifdef ENABLE_CHECKING
11097 attr
|= RS6000_BTC_UNARY
;
11100 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
11101 op
[nopnds
++] = GEN_INT (0);
11102 #ifdef ENABLE_CHECKING
11103 attr
|= RS6000_BTC_UNARY
;
11110 /* If this builtin accesses SPRs, then pass in the appropriate
11111 SPR number and SPR regno as the last two operands. */
11112 if (attr
& RS6000_BTC_SPR
)
11114 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
11115 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
11118 #ifdef ENABLE_CHECKING
11119 int expected_nopnds
= 0;
11120 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
11121 expected_nopnds
= 1;
11122 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
11123 expected_nopnds
= 2;
11124 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
11125 expected_nopnds
= 3;
11126 if (!(attr
& RS6000_BTC_VOID
))
11127 expected_nopnds
+= 1;
11128 if (attr
& RS6000_BTC_SPR
)
11129 expected_nopnds
+= 2;
11131 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
11137 pat
= GEN_FCN (icode
) (NULL_RTX
);
11140 pat
= GEN_FCN (icode
) (op
[0]);
11143 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11146 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11149 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11152 gcc_unreachable ();
11168 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11171 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11172 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11173 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11174 rtx op0
= expand_normal (arg0
);
11175 rtx op1
= expand_normal (arg1
);
11176 rtx op2
= expand_normal (arg2
);
11177 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11178 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11179 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11180 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
11182 if (icode
== CODE_FOR_nothing
)
11183 /* Builtin not supported on this processor. */
11186 /* If we got invalid arguments bail out before generating bad rtl. */
11187 if (arg0
== error_mark_node
11188 || arg1
== error_mark_node
11189 || arg2
== error_mark_node
)
11192 /* Check and prepare argument depending on the instruction code.
11194 Note that a switch statement instead of the sequence of tests
11195 would be incorrect as many of the CODE_FOR values could be
11196 CODE_FOR_nothing and that would yield multiple alternatives
11197 with identical values. We'd never reach here at runtime in
11199 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
11200 || icode
== CODE_FOR_altivec_vsldoi_v4si
11201 || icode
== CODE_FOR_altivec_vsldoi_v8hi
11202 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
11204 /* Only allow 4-bit unsigned literals. */
11206 if (TREE_CODE (arg2
) != INTEGER_CST
11207 || TREE_INT_CST_LOW (arg2
) & ~0xf)
11209 error ("argument 3 must be a 4-bit unsigned literal");
11213 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
11214 || icode
== CODE_FOR_vsx_xxpermdi_v2di
11215 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
11216 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
11217 || icode
== CODE_FOR_vsx_xxsldwi_v4si
11218 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
11219 || icode
== CODE_FOR_vsx_xxsldwi_v2di
11220 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
11222 /* Only allow 2-bit unsigned literals. */
11224 if (TREE_CODE (arg2
) != INTEGER_CST
11225 || TREE_INT_CST_LOW (arg2
) & ~0x3)
11227 error ("argument 3 must be a 2-bit unsigned literal");
11231 else if (icode
== CODE_FOR_vsx_set_v2df
11232 || icode
== CODE_FOR_vsx_set_v2di
)
11234 /* Only allow 1-bit unsigned literals. */
11236 if (TREE_CODE (arg2
) != INTEGER_CST
11237 || TREE_INT_CST_LOW (arg2
) & ~0x1)
11239 error ("argument 3 must be a 1-bit unsigned literal");
11243 else if (icode
== CODE_FOR_crypto_vshasigmaw
11244 || icode
== CODE_FOR_crypto_vshasigmad
)
11246 /* Check whether the 2nd and 3rd arguments are integer constants and in
11247 range and prepare arguments. */
11249 if (TREE_CODE (arg1
) != INTEGER_CST
11250 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
11252 error ("argument 2 must be 0 or 1");
11257 if (TREE_CODE (arg2
) != INTEGER_CST
11258 || !IN_RANGE (TREE_INT_CST_LOW (arg2
), 0, 15))
11260 error ("argument 3 must be in the range 0..15");
11266 || GET_MODE (target
) != tmode
11267 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11268 target
= gen_reg_rtx (tmode
);
11270 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11271 op0
= copy_to_mode_reg (mode0
, op0
);
11272 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11273 op1
= copy_to_mode_reg (mode1
, op1
);
11274 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11275 op2
= copy_to_mode_reg (mode2
, op2
);
11277 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
11278 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
11280 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11288 /* Expand the lvx builtins. */
11290 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
11292 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11293 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11295 enum machine_mode tmode
, mode0
;
11297 enum insn_code icode
;
11301 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
11302 icode
= CODE_FOR_vector_altivec_load_v16qi
;
11304 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
11305 icode
= CODE_FOR_vector_altivec_load_v8hi
;
11307 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
11308 icode
= CODE_FOR_vector_altivec_load_v4si
;
11310 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
11311 icode
= CODE_FOR_vector_altivec_load_v4sf
;
11313 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
11314 icode
= CODE_FOR_vector_altivec_load_v2df
;
11316 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
11317 icode
= CODE_FOR_vector_altivec_load_v2di
;
11320 *expandedp
= false;
11326 arg0
= CALL_EXPR_ARG (exp
, 0);
11327 op0
= expand_normal (arg0
);
11328 tmode
= insn_data
[icode
].operand
[0].mode
;
11329 mode0
= insn_data
[icode
].operand
[1].mode
;
11332 || GET_MODE (target
) != tmode
11333 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11334 target
= gen_reg_rtx (tmode
);
11336 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11337 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11339 pat
= GEN_FCN (icode
) (target
, op0
);
11346 /* Expand the stvx builtins. */
11348 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
11351 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11352 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11354 enum machine_mode mode0
, mode1
;
11356 enum insn_code icode
;
11360 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
11361 icode
= CODE_FOR_vector_altivec_store_v16qi
;
11363 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
11364 icode
= CODE_FOR_vector_altivec_store_v8hi
;
11366 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
11367 icode
= CODE_FOR_vector_altivec_store_v4si
;
11369 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
11370 icode
= CODE_FOR_vector_altivec_store_v4sf
;
11372 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
11373 icode
= CODE_FOR_vector_altivec_store_v2df
;
11375 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
11376 icode
= CODE_FOR_vector_altivec_store_v2di
;
11379 *expandedp
= false;
11383 arg0
= CALL_EXPR_ARG (exp
, 0);
11384 arg1
= CALL_EXPR_ARG (exp
, 1);
11385 op0
= expand_normal (arg0
);
11386 op1
= expand_normal (arg1
);
11387 mode0
= insn_data
[icode
].operand
[0].mode
;
11388 mode1
= insn_data
[icode
].operand
[1].mode
;
11390 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11391 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11392 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11393 op1
= copy_to_mode_reg (mode1
, op1
);
11395 pat
= GEN_FCN (icode
) (op0
, op1
);
11403 /* Expand the dst builtins. */
11405 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
11408 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11409 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11410 tree arg0
, arg1
, arg2
;
11411 enum machine_mode mode0
, mode1
;
11412 rtx pat
, op0
, op1
, op2
;
11413 const struct builtin_description
*d
;
11416 *expandedp
= false;
11418 /* Handle DST variants. */
11420 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
11421 if (d
->code
== fcode
)
11423 arg0
= CALL_EXPR_ARG (exp
, 0);
11424 arg1
= CALL_EXPR_ARG (exp
, 1);
11425 arg2
= CALL_EXPR_ARG (exp
, 2);
11426 op0
= expand_normal (arg0
);
11427 op1
= expand_normal (arg1
);
11428 op2
= expand_normal (arg2
);
11429 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
11430 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
11432 /* Invalid arguments, bail out before generating bad rtl. */
11433 if (arg0
== error_mark_node
11434 || arg1
== error_mark_node
11435 || arg2
== error_mark_node
)
11440 if (TREE_CODE (arg2
) != INTEGER_CST
11441 || TREE_INT_CST_LOW (arg2
) & ~0x3)
11443 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
11447 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
11448 op0
= copy_to_mode_reg (Pmode
, op0
);
11449 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
11450 op1
= copy_to_mode_reg (mode1
, op1
);
11452 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
11462 /* Expand vec_init builtin. */
11464 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
11466 enum machine_mode tmode
= TYPE_MODE (type
);
11467 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
11468 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
11469 rtvec v
= rtvec_alloc (n_elt
);
11471 gcc_assert (VECTOR_MODE_P (tmode
));
11472 gcc_assert (n_elt
== call_expr_nargs (exp
));
11474 for (i
= 0; i
< n_elt
; ++i
)
11476 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
11477 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
11480 if (!target
|| !register_operand (target
, tmode
))
11481 target
= gen_reg_rtx (tmode
);
11483 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
11487 /* Return the integer constant in ARG. Constrain it to be in the range
11488 of the subparts of VEC_TYPE; issue an error if not. */
11491 get_element_number (tree vec_type
, tree arg
)
11493 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
11495 if (!host_integerp (arg
, 1)
11496 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
11498 error ("selector must be an integer constant in the range 0..%wi", max
);
11505 /* Expand vec_set builtin. */
11507 altivec_expand_vec_set_builtin (tree exp
)
11509 enum machine_mode tmode
, mode1
;
11510 tree arg0
, arg1
, arg2
;
11514 arg0
= CALL_EXPR_ARG (exp
, 0);
11515 arg1
= CALL_EXPR_ARG (exp
, 1);
11516 arg2
= CALL_EXPR_ARG (exp
, 2);
11518 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
11519 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
11520 gcc_assert (VECTOR_MODE_P (tmode
));
11522 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
11523 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
11524 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
11526 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
11527 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
11529 op0
= force_reg (tmode
, op0
);
11530 op1
= force_reg (mode1
, op1
);
11532 rs6000_expand_vector_set (op0
, op1
, elt
);
11537 /* Expand vec_ext builtin. */
11539 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
11541 enum machine_mode tmode
, mode0
;
11546 arg0
= CALL_EXPR_ARG (exp
, 0);
11547 arg1
= CALL_EXPR_ARG (exp
, 1);
11549 op0
= expand_normal (arg0
);
11550 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
11552 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
11553 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
11554 gcc_assert (VECTOR_MODE_P (mode0
));
11556 op0
= force_reg (mode0
, op0
);
11558 if (optimize
|| !target
|| !register_operand (target
, tmode
))
11559 target
= gen_reg_rtx (tmode
);
11561 rs6000_expand_vector_extract (target
, op0
, elt
);
11566 /* Expand the builtin in EXP and store the result in TARGET. Store
11567 true in *EXPANDEDP if we found a builtin to expand. */
11569 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
11571 const struct builtin_description
*d
;
11573 enum insn_code icode
;
11574 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11577 enum machine_mode tmode
, mode0
;
11578 enum rs6000_builtins fcode
11579 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11581 if (rs6000_overloaded_builtin_p (fcode
))
11584 error ("unresolved overload for Altivec builtin %qF", fndecl
);
11586 /* Given it is invalid, just generate a normal call. */
11587 return expand_call (exp
, target
, false);
11590 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
11594 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
11598 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
11606 case ALTIVEC_BUILTIN_STVX
:
11607 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
11608 case ALTIVEC_BUILTIN_STVEBX
:
11609 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
11610 case ALTIVEC_BUILTIN_STVEHX
:
11611 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
11612 case ALTIVEC_BUILTIN_STVEWX
:
11613 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
11614 case ALTIVEC_BUILTIN_STVXL
:
11615 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
11617 case ALTIVEC_BUILTIN_STVLX
:
11618 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
11619 case ALTIVEC_BUILTIN_STVLXL
:
11620 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
11621 case ALTIVEC_BUILTIN_STVRX
:
11622 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
11623 case ALTIVEC_BUILTIN_STVRXL
:
11624 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
11626 case VSX_BUILTIN_STXVD2X_V2DF
:
11627 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
11628 case VSX_BUILTIN_STXVD2X_V2DI
:
11629 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
11630 case VSX_BUILTIN_STXVW4X_V4SF
:
11631 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
11632 case VSX_BUILTIN_STXVW4X_V4SI
:
11633 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
11634 case VSX_BUILTIN_STXVW4X_V8HI
:
11635 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
11636 case VSX_BUILTIN_STXVW4X_V16QI
:
11637 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
11639 case ALTIVEC_BUILTIN_MFVSCR
:
11640 icode
= CODE_FOR_altivec_mfvscr
;
11641 tmode
= insn_data
[icode
].operand
[0].mode
;
11644 || GET_MODE (target
) != tmode
11645 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11646 target
= gen_reg_rtx (tmode
);
11648 pat
= GEN_FCN (icode
) (target
);
11654 case ALTIVEC_BUILTIN_MTVSCR
:
11655 icode
= CODE_FOR_altivec_mtvscr
;
11656 arg0
= CALL_EXPR_ARG (exp
, 0);
11657 op0
= expand_normal (arg0
);
11658 mode0
= insn_data
[icode
].operand
[0].mode
;
11660 /* If we got invalid arguments bail out before generating bad rtl. */
11661 if (arg0
== error_mark_node
)
11664 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11665 op0
= copy_to_mode_reg (mode0
, op0
);
11667 pat
= GEN_FCN (icode
) (op0
);
11672 case ALTIVEC_BUILTIN_DSSALL
:
11673 emit_insn (gen_altivec_dssall ());
11676 case ALTIVEC_BUILTIN_DSS
:
11677 icode
= CODE_FOR_altivec_dss
;
11678 arg0
= CALL_EXPR_ARG (exp
, 0);
11680 op0
= expand_normal (arg0
);
11681 mode0
= insn_data
[icode
].operand
[0].mode
;
11683 /* If we got invalid arguments bail out before generating bad rtl. */
11684 if (arg0
== error_mark_node
)
11687 if (TREE_CODE (arg0
) != INTEGER_CST
11688 || TREE_INT_CST_LOW (arg0
) & ~0x3)
11690 error ("argument to dss must be a 2-bit unsigned literal");
11694 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11695 op0
= copy_to_mode_reg (mode0
, op0
);
11697 emit_insn (gen_altivec_dss (op0
));
11700 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
11701 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
11702 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
11703 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
11704 case VSX_BUILTIN_VEC_INIT_V2DF
:
11705 case VSX_BUILTIN_VEC_INIT_V2DI
:
11706 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
11708 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
11709 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
11710 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
11711 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
11712 case VSX_BUILTIN_VEC_SET_V2DF
:
11713 case VSX_BUILTIN_VEC_SET_V2DI
:
11714 return altivec_expand_vec_set_builtin (exp
);
11716 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
11717 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
11718 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
11719 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
11720 case VSX_BUILTIN_VEC_EXT_V2DF
:
11721 case VSX_BUILTIN_VEC_EXT_V2DI
:
11722 return altivec_expand_vec_ext_builtin (exp
, target
);
11726 /* Fall through. */
11729 /* Expand abs* operations. */
11731 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
11732 if (d
->code
== fcode
)
11733 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
11735 /* Expand the AltiVec predicates. */
11736 d
= bdesc_altivec_preds
;
11737 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
11738 if (d
->code
== fcode
)
11739 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
11741 /* LV* are funky. We initialized them differently. */
11744 case ALTIVEC_BUILTIN_LVSL
:
11745 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
11746 exp
, target
, false);
11747 case ALTIVEC_BUILTIN_LVSR
:
11748 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
11749 exp
, target
, false);
11750 case ALTIVEC_BUILTIN_LVEBX
:
11751 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
11752 exp
, target
, false);
11753 case ALTIVEC_BUILTIN_LVEHX
:
11754 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
11755 exp
, target
, false);
11756 case ALTIVEC_BUILTIN_LVEWX
:
11757 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
11758 exp
, target
, false);
11759 case ALTIVEC_BUILTIN_LVXL
:
11760 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
11761 exp
, target
, false);
11762 case ALTIVEC_BUILTIN_LVX
:
11763 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
11764 exp
, target
, false);
11765 case ALTIVEC_BUILTIN_LVLX
:
11766 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
11767 exp
, target
, true);
11768 case ALTIVEC_BUILTIN_LVLXL
:
11769 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
11770 exp
, target
, true);
11771 case ALTIVEC_BUILTIN_LVRX
:
11772 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
11773 exp
, target
, true);
11774 case ALTIVEC_BUILTIN_LVRXL
:
11775 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
11776 exp
, target
, true);
11777 case VSX_BUILTIN_LXVD2X_V2DF
:
11778 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
11779 exp
, target
, false);
11780 case VSX_BUILTIN_LXVD2X_V2DI
:
11781 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
11782 exp
, target
, false);
11783 case VSX_BUILTIN_LXVW4X_V4SF
:
11784 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
11785 exp
, target
, false);
11786 case VSX_BUILTIN_LXVW4X_V4SI
:
11787 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
11788 exp
, target
, false);
11789 case VSX_BUILTIN_LXVW4X_V8HI
:
11790 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
11791 exp
, target
, false);
11792 case VSX_BUILTIN_LXVW4X_V16QI
:
11793 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
11794 exp
, target
, false);
11798 /* Fall through. */
11801 *expandedp
= false;
11805 /* Expand the builtin in EXP and store the result in TARGET. Store
11806 true in *EXPANDEDP if we found a builtin to expand. */
11808 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
11810 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11811 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11812 const struct builtin_description
*d
;
11819 case PAIRED_BUILTIN_STX
:
11820 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
11821 case PAIRED_BUILTIN_LX
:
11822 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
11825 /* Fall through. */
11828 /* Expand the paired predicates. */
11829 d
= bdesc_paired_preds
;
11830 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
11831 if (d
->code
== fcode
)
11832 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
11834 *expandedp
= false;
11838 /* Binops that need to be initialized manually, but can be expanded
11839 automagically by rs6000_expand_binop_builtin. */
11840 static const struct builtin_description bdesc_2arg_spe
[] =
11842 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
11843 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
11844 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
11845 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
11846 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
11847 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
11848 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
11849 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
11850 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
11851 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
11852 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
11853 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
11854 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
11855 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
11856 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
11857 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
11858 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
11859 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
11860 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
11861 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
11862 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
11863 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
11866 /* Expand the builtin in EXP and store the result in TARGET. Store
11867 true in *EXPANDEDP if we found a builtin to expand.
11869 This expands the SPE builtins that are not simple unary and binary
11872 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
11874 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11876 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11877 enum insn_code icode
;
11878 enum machine_mode tmode
, mode0
;
11880 const struct builtin_description
*d
;
11885 /* Syntax check for a 5-bit unsigned immediate. */
11888 case SPE_BUILTIN_EVSTDD
:
11889 case SPE_BUILTIN_EVSTDH
:
11890 case SPE_BUILTIN_EVSTDW
:
11891 case SPE_BUILTIN_EVSTWHE
:
11892 case SPE_BUILTIN_EVSTWHO
:
11893 case SPE_BUILTIN_EVSTWWE
:
11894 case SPE_BUILTIN_EVSTWWO
:
11895 arg1
= CALL_EXPR_ARG (exp
, 2);
11896 if (TREE_CODE (arg1
) != INTEGER_CST
11897 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11899 error ("argument 2 must be a 5-bit unsigned literal");
11907 /* The evsplat*i instructions are not quite generic. */
11910 case SPE_BUILTIN_EVSPLATFI
:
11911 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
11913 case SPE_BUILTIN_EVSPLATI
:
11914 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
11920 d
= bdesc_2arg_spe
;
11921 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
11922 if (d
->code
== fcode
)
11923 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
11925 d
= bdesc_spe_predicates
;
11926 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
11927 if (d
->code
== fcode
)
11928 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
11930 d
= bdesc_spe_evsel
;
11931 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
11932 if (d
->code
== fcode
)
11933 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
11937 case SPE_BUILTIN_EVSTDDX
:
11938 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
11939 case SPE_BUILTIN_EVSTDHX
:
11940 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
11941 case SPE_BUILTIN_EVSTDWX
:
11942 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
11943 case SPE_BUILTIN_EVSTWHEX
:
11944 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
11945 case SPE_BUILTIN_EVSTWHOX
:
11946 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
11947 case SPE_BUILTIN_EVSTWWEX
:
11948 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
11949 case SPE_BUILTIN_EVSTWWOX
:
11950 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
11951 case SPE_BUILTIN_EVSTDD
:
11952 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
11953 case SPE_BUILTIN_EVSTDH
:
11954 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
11955 case SPE_BUILTIN_EVSTDW
:
11956 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
11957 case SPE_BUILTIN_EVSTWHE
:
11958 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
11959 case SPE_BUILTIN_EVSTWHO
:
11960 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
11961 case SPE_BUILTIN_EVSTWWE
:
11962 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
11963 case SPE_BUILTIN_EVSTWWO
:
11964 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
11965 case SPE_BUILTIN_MFSPEFSCR
:
11966 icode
= CODE_FOR_spe_mfspefscr
;
11967 tmode
= insn_data
[icode
].operand
[0].mode
;
11970 || GET_MODE (target
) != tmode
11971 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11972 target
= gen_reg_rtx (tmode
);
11974 pat
= GEN_FCN (icode
) (target
);
11979 case SPE_BUILTIN_MTSPEFSCR
:
11980 icode
= CODE_FOR_spe_mtspefscr
;
11981 arg0
= CALL_EXPR_ARG (exp
, 0);
11982 op0
= expand_normal (arg0
);
11983 mode0
= insn_data
[icode
].operand
[0].mode
;
11985 if (arg0
== error_mark_node
)
11988 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11989 op0
= copy_to_mode_reg (mode0
, op0
);
11991 pat
= GEN_FCN (icode
) (op0
);
11999 *expandedp
= false;
12004 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12006 rtx pat
, scratch
, tmp
;
12007 tree form
= CALL_EXPR_ARG (exp
, 0);
12008 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12009 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12010 rtx op0
= expand_normal (arg0
);
12011 rtx op1
= expand_normal (arg1
);
12012 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12013 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12015 enum rtx_code code
;
12017 if (TREE_CODE (form
) != INTEGER_CST
)
12019 error ("argument 1 of __builtin_paired_predicate must be a constant");
12023 form_int
= TREE_INT_CST_LOW (form
);
12025 gcc_assert (mode0
== mode1
);
12027 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12031 || GET_MODE (target
) != SImode
12032 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
12033 target
= gen_reg_rtx (SImode
);
12034 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12035 op0
= copy_to_mode_reg (mode0
, op0
);
12036 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12037 op1
= copy_to_mode_reg (mode1
, op1
);
12039 scratch
= gen_reg_rtx (CCFPmode
);
12041 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12063 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
12066 error ("argument 1 of __builtin_paired_predicate is out of range");
12070 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
12071 emit_move_insn (target
, tmp
);
12076 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12078 rtx pat
, scratch
, tmp
;
12079 tree form
= CALL_EXPR_ARG (exp
, 0);
12080 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12081 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12082 rtx op0
= expand_normal (arg0
);
12083 rtx op1
= expand_normal (arg1
);
12084 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12085 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12087 enum rtx_code code
;
12089 if (TREE_CODE (form
) != INTEGER_CST
)
12091 error ("argument 1 of __builtin_spe_predicate must be a constant");
12095 form_int
= TREE_INT_CST_LOW (form
);
12097 gcc_assert (mode0
== mode1
);
12099 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12103 || GET_MODE (target
) != SImode
12104 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
12105 target
= gen_reg_rtx (SImode
);
12107 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12108 op0
= copy_to_mode_reg (mode0
, op0
);
12109 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12110 op1
= copy_to_mode_reg (mode1
, op1
);
12112 scratch
= gen_reg_rtx (CCmode
);
12114 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12119 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
12120 _lower_. We use one compare, but look in different bits of the
12121 CR for each variant.
12123 There are 2 elements in each SPE simd type (upper/lower). The CR
12124 bits are set as follows:
12126 BIT0 | BIT 1 | BIT 2 | BIT 3
12127 U | L | (U | L) | (U & L)
12129 So, for an "all" relationship, BIT 3 would be set.
12130 For an "any" relationship, BIT 2 would be set. Etc.
12132 Following traditional nomenclature, these bits map to:
12134 BIT0 | BIT 1 | BIT 2 | BIT 3
12137 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
12142 /* All variant. OV bit. */
12144 /* We need to get to the OV bit, which is the ORDERED bit. We
12145 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
12146 that's ugly and will make validate_condition_mode die.
12147 So let's just use another pattern. */
12148 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
12150 /* Any variant. EQ bit. */
12154 /* Upper variant. LT bit. */
12158 /* Lower variant. GT bit. */
12163 error ("argument 1 of __builtin_spe_predicate is out of range");
12167 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
12168 emit_move_insn (target
, tmp
);
12173 /* The evsel builtins look like this:
12175 e = __builtin_spe_evsel_OP (a, b, c, d);
12177 and work like this:
12179 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
12180 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
12184 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
12187 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12188 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12189 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12190 tree arg3
= CALL_EXPR_ARG (exp
, 3);
12191 rtx op0
= expand_normal (arg0
);
12192 rtx op1
= expand_normal (arg1
);
12193 rtx op2
= expand_normal (arg2
);
12194 rtx op3
= expand_normal (arg3
);
12195 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12196 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12198 gcc_assert (mode0
== mode1
);
12200 if (arg0
== error_mark_node
|| arg1
== error_mark_node
12201 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
12205 || GET_MODE (target
) != mode0
12206 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
12207 target
= gen_reg_rtx (mode0
);
12209 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12210 op0
= copy_to_mode_reg (mode0
, op0
);
12211 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12212 op1
= copy_to_mode_reg (mode0
, op1
);
12213 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12214 op2
= copy_to_mode_reg (mode0
, op2
);
12215 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
12216 op3
= copy_to_mode_reg (mode0
, op3
);
12218 /* Generate the compare. */
12219 scratch
= gen_reg_rtx (CCmode
);
12220 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12225 if (mode0
== V2SImode
)
12226 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
12228 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
12233 /* Raise an error message for a builtin function that is called without the
12234 appropriate target options being set. */
12237 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
12239 size_t uns_fncode
= (size_t)fncode
;
12240 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
12241 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
12243 gcc_assert (name
!= NULL
);
12244 if ((fnmask
& RS6000_BTM_CELL
) != 0)
12245 error ("Builtin function %s is only valid for the cell processor", name
);
12246 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
12247 error ("Builtin function %s requires the -mvsx option", name
);
12248 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
12249 error ("Builtin function %s requires the -mhtm option", name
);
12250 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
12251 error ("Builtin function %s requires the -maltivec option", name
);
12252 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
12253 error ("Builtin function %s requires the -mpaired option", name
);
12254 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
12255 error ("Builtin function %s requires the -mspe option", name
);
12257 error ("Builtin function %s is not supported with the current options",
12261 /* Expand an expression EXP that calls a built-in function,
12262 with result going to TARGET if that's convenient
12263 (and in mode MODE if that's convenient).
12264 SUBTARGET may be used as the target for computing one of EXP's operands.
12265 IGNORE is nonzero if the value is to be ignored. */
12268 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
12269 enum machine_mode mode ATTRIBUTE_UNUSED
,
12270 int ignore ATTRIBUTE_UNUSED
)
12272 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12273 enum rs6000_builtins fcode
12274 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
12275 size_t uns_fcode
= (size_t)fcode
;
12276 const struct builtin_description
*d
;
12280 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
12281 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
12283 if (TARGET_DEBUG_BUILTIN
)
12285 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
12286 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
12287 const char *name2
= ((icode
!= CODE_FOR_nothing
)
12288 ? get_insn_name ((int)icode
)
12292 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
12294 default: name3
= "unknown"; break;
12295 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
12296 case RS6000_BTC_UNARY
: name3
= "unary"; break;
12297 case RS6000_BTC_BINARY
: name3
= "binary"; break;
12298 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
12299 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
12300 case RS6000_BTC_ABS
: name3
= "abs"; break;
12301 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
12302 case RS6000_BTC_DST
: name3
= "dst"; break;
12307 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
12308 (name1
) ? name1
: "---", fcode
,
12309 (name2
) ? name2
: "---", (int)icode
,
12311 func_valid_p
? "" : ", not valid");
12316 rs6000_invalid_builtin (fcode
);
12318 /* Given it is invalid, just generate a normal call. */
12319 return expand_call (exp
, target
, ignore
);
12324 case RS6000_BUILTIN_RECIP
:
12325 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
12327 case RS6000_BUILTIN_RECIPF
:
12328 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
12330 case RS6000_BUILTIN_RSQRTF
:
12331 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
12333 case RS6000_BUILTIN_RSQRT
:
12334 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
12336 case POWER7_BUILTIN_BPERMD
:
12337 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
12338 ? CODE_FOR_bpermd_di
12339 : CODE_FOR_bpermd_si
), exp
, target
);
12341 case RS6000_BUILTIN_GET_TB
:
12342 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
12345 case RS6000_BUILTIN_MFTB
:
12346 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
12347 ? CODE_FOR_rs6000_mftb_di
12348 : CODE_FOR_rs6000_mftb_si
),
12351 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
12352 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
12354 int icode
= (int) CODE_FOR_altivec_lvsr
;
12355 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12356 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
12360 gcc_assert (TARGET_ALTIVEC
);
12362 arg
= CALL_EXPR_ARG (exp
, 0);
12363 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
12364 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
12365 addr
= memory_address (mode
, op
);
12366 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
12370 /* For the load case need to negate the address. */
12371 op
= gen_reg_rtx (GET_MODE (addr
));
12372 emit_insn (gen_rtx_SET (VOIDmode
, op
,
12373 gen_rtx_NEG (GET_MODE (addr
), addr
)));
12375 op
= gen_rtx_MEM (mode
, op
);
12378 || GET_MODE (target
) != tmode
12379 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12380 target
= gen_reg_rtx (tmode
);
12382 /*pat = gen_altivec_lvsr (target, op);*/
12383 pat
= GEN_FCN (icode
) (target
, op
);
12391 case ALTIVEC_BUILTIN_VCFUX
:
12392 case ALTIVEC_BUILTIN_VCFSX
:
12393 case ALTIVEC_BUILTIN_VCTUXS
:
12394 case ALTIVEC_BUILTIN_VCTSXS
:
12395 /* FIXME: There's got to be a nicer way to handle this case than
12396 constructing a new CALL_EXPR. */
12397 if (call_expr_nargs (exp
) == 1)
12399 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
12400 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
12408 if (TARGET_ALTIVEC
)
12410 ret
= altivec_expand_builtin (exp
, target
, &success
);
12417 ret
= spe_expand_builtin (exp
, target
, &success
);
12422 if (TARGET_PAIRED_FLOAT
)
12424 ret
= paired_expand_builtin (exp
, target
, &success
);
12431 ret
= htm_expand_builtin (exp
, target
, &success
);
12437 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
12439 /* Handle simple unary operations. */
12441 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12442 if (d
->code
== fcode
)
12443 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
12445 /* Handle simple binary operations. */
12447 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12448 if (d
->code
== fcode
)
12449 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
12451 /* Handle simple ternary operations. */
12453 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
12454 if (d
->code
== fcode
)
12455 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
12457 gcc_unreachable ();
12461 rs6000_init_builtins (void)
12465 enum machine_mode mode
;
12467 if (TARGET_DEBUG_BUILTIN
)
12468 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
12469 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
12470 (TARGET_SPE
) ? ", spe" : "",
12471 (TARGET_ALTIVEC
) ? ", altivec" : "",
12472 (TARGET_VSX
) ? ", vsx" : "");
12474 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
12475 V2SF_type_node
= build_vector_type (float_type_node
, 2);
12476 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
12477 V2DF_type_node
= build_vector_type (double_type_node
, 2);
12478 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
12479 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
12480 V4SF_type_node
= build_vector_type (float_type_node
, 4);
12481 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
12482 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
12484 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
12485 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
12486 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
12487 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
12489 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
12490 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
12491 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
12492 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
12494 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
12495 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
12496 'vector unsigned short'. */
12498 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
12499 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
12500 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
12501 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
12502 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
12504 long_integer_type_internal_node
= long_integer_type_node
;
12505 long_unsigned_type_internal_node
= long_unsigned_type_node
;
12506 long_long_integer_type_internal_node
= long_long_integer_type_node
;
12507 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
12508 intQI_type_internal_node
= intQI_type_node
;
12509 uintQI_type_internal_node
= unsigned_intQI_type_node
;
12510 intHI_type_internal_node
= intHI_type_node
;
12511 uintHI_type_internal_node
= unsigned_intHI_type_node
;
12512 intSI_type_internal_node
= intSI_type_node
;
12513 uintSI_type_internal_node
= unsigned_intSI_type_node
;
12514 intDI_type_internal_node
= intDI_type_node
;
12515 uintDI_type_internal_node
= unsigned_intDI_type_node
;
12516 float_type_internal_node
= float_type_node
;
12517 double_type_internal_node
= double_type_node
;
12518 void_type_internal_node
= void_type_node
;
12520 /* Initialize the modes for builtin_function_type, mapping a machine mode to
12522 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
12523 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
12524 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
12525 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
12526 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
12527 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
12528 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
12529 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
12530 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
12531 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
12532 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
12533 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
12534 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
12535 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
12536 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
12537 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
12538 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
12539 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
12540 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
12541 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
12542 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
12544 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
12545 TYPE_NAME (bool_char_type_node
) = tdecl
;
12547 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
12548 TYPE_NAME (bool_short_type_node
) = tdecl
;
12550 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
12551 TYPE_NAME (bool_int_type_node
) = tdecl
;
12553 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
12554 TYPE_NAME (pixel_type_node
) = tdecl
;
12556 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
12557 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
12558 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
12559 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
12560 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
12562 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
12563 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
12565 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
12566 TYPE_NAME (V16QI_type_node
) = tdecl
;
12568 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
12569 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
12571 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
12572 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
12574 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
12575 TYPE_NAME (V8HI_type_node
) = tdecl
;
12577 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
12578 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
12580 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
12581 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
12583 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
12584 TYPE_NAME (V4SI_type_node
) = tdecl
;
12586 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
12587 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
12589 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
12590 TYPE_NAME (V4SF_type_node
) = tdecl
;
12592 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
12593 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
12595 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
12596 TYPE_NAME (V2DF_type_node
) = tdecl
;
12598 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
12599 TYPE_NAME (V2DI_type_node
) = tdecl
;
12601 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
12602 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
12604 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
12605 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
12607 /* Paired and SPE builtins are only available if you build a compiler with
12608 the appropriate options, so only create those builtins with the
12609 appropriate compiler option. Create Altivec and VSX builtins on machines
12610 with at least the general purpose extensions (970 and newer) to allow the
12611 use of the target attribute. */
12612 if (TARGET_PAIRED_FLOAT
)
12613 paired_init_builtins ();
12615 spe_init_builtins ();
12616 if (TARGET_EXTRA_BUILTINS
)
12617 altivec_init_builtins ();
12619 htm_init_builtins ();
12621 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
12622 rs6000_common_init_builtins ();
12624 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
12625 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
12626 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
12628 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
12629 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
12630 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
12632 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
12633 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
12634 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
12636 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
12637 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
12638 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
12640 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
12641 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
12642 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
12643 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
12645 ftype
= build_function_type_list (unsigned_intDI_type_node
,
12647 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
12650 ftype
= build_function_type_list (unsigned_intDI_type_node
,
12653 ftype
= build_function_type_list (unsigned_intSI_type_node
,
12655 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
12658 /* AIX libm provides clog as __clog. */
12659 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
12660 set_user_assembler_name (tdecl
, "__clog");
12663 #ifdef SUBTARGET_INIT_BUILTINS
12664 SUBTARGET_INIT_BUILTINS
;
12668 /* Returns the rs6000 builtin decl for CODE. */
12671 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
12673 HOST_WIDE_INT fnmask
;
12675 if (code
>= RS6000_BUILTIN_COUNT
)
12676 return error_mark_node
;
12678 fnmask
= rs6000_builtin_info
[code
].mask
;
12679 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
12681 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
12682 return error_mark_node
;
12685 return rs6000_builtin_decls
[code
];
12689 spe_init_builtins (void)
12691 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
12692 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
12693 const struct builtin_description
*d
;
12696 tree v2si_ftype_4_v2si
12697 = build_function_type_list (opaque_V2SI_type_node
,
12698 opaque_V2SI_type_node
,
12699 opaque_V2SI_type_node
,
12700 opaque_V2SI_type_node
,
12701 opaque_V2SI_type_node
,
12704 tree v2sf_ftype_4_v2sf
12705 = build_function_type_list (opaque_V2SF_type_node
,
12706 opaque_V2SF_type_node
,
12707 opaque_V2SF_type_node
,
12708 opaque_V2SF_type_node
,
12709 opaque_V2SF_type_node
,
12712 tree int_ftype_int_v2si_v2si
12713 = build_function_type_list (integer_type_node
,
12715 opaque_V2SI_type_node
,
12716 opaque_V2SI_type_node
,
12719 tree int_ftype_int_v2sf_v2sf
12720 = build_function_type_list (integer_type_node
,
12722 opaque_V2SF_type_node
,
12723 opaque_V2SF_type_node
,
12726 tree void_ftype_v2si_puint_int
12727 = build_function_type_list (void_type_node
,
12728 opaque_V2SI_type_node
,
12733 tree void_ftype_v2si_puint_char
12734 = build_function_type_list (void_type_node
,
12735 opaque_V2SI_type_node
,
12740 tree void_ftype_v2si_pv2si_int
12741 = build_function_type_list (void_type_node
,
12742 opaque_V2SI_type_node
,
12743 opaque_p_V2SI_type_node
,
12747 tree void_ftype_v2si_pv2si_char
12748 = build_function_type_list (void_type_node
,
12749 opaque_V2SI_type_node
,
12750 opaque_p_V2SI_type_node
,
12754 tree void_ftype_int
12755 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
12757 tree int_ftype_void
12758 = build_function_type_list (integer_type_node
, NULL_TREE
);
12760 tree v2si_ftype_pv2si_int
12761 = build_function_type_list (opaque_V2SI_type_node
,
12762 opaque_p_V2SI_type_node
,
12766 tree v2si_ftype_puint_int
12767 = build_function_type_list (opaque_V2SI_type_node
,
12772 tree v2si_ftype_pushort_int
12773 = build_function_type_list (opaque_V2SI_type_node
,
12778 tree v2si_ftype_signed_char
12779 = build_function_type_list (opaque_V2SI_type_node
,
12780 signed_char_type_node
,
12783 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
12785 /* Initialize irregular SPE builtins. */
12787 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
12788 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
12789 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
12790 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
12791 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
12792 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
12793 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
12794 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
12795 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
12796 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
12797 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
12798 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
12799 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
12800 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
12801 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
12802 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
12803 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
12804 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
12807 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
12808 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
12809 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
12810 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
12811 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
12812 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
12813 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
12814 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
12815 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
12816 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
12817 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
12818 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
12819 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
12820 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
12821 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
12822 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
12823 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
12824 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
12825 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
12826 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
12827 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
12828 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
12831 d
= bdesc_spe_predicates
;
12832 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
12836 switch (insn_data
[d
->icode
].operand
[1].mode
)
12839 type
= int_ftype_int_v2si_v2si
;
12842 type
= int_ftype_int_v2sf_v2sf
;
12845 gcc_unreachable ();
12848 def_builtin (d
->name
, type
, d
->code
);
12851 /* Evsel predicates. */
12852 d
= bdesc_spe_evsel
;
12853 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
12857 switch (insn_data
[d
->icode
].operand
[1].mode
)
12860 type
= v2si_ftype_4_v2si
;
12863 type
= v2sf_ftype_4_v2sf
;
12866 gcc_unreachable ();
12869 def_builtin (d
->name
, type
, d
->code
);
12874 paired_init_builtins (void)
12876 const struct builtin_description
*d
;
12879 tree int_ftype_int_v2sf_v2sf
12880 = build_function_type_list (integer_type_node
,
12885 tree pcfloat_type_node
=
12886 build_pointer_type (build_qualified_type
12887 (float_type_node
, TYPE_QUAL_CONST
));
12889 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
12890 long_integer_type_node
,
12893 tree void_ftype_v2sf_long_pcfloat
=
12894 build_function_type_list (void_type_node
,
12896 long_integer_type_node
,
12901 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
12902 PAIRED_BUILTIN_LX
);
12905 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
12906 PAIRED_BUILTIN_STX
);
12909 d
= bdesc_paired_preds
;
12910 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
12914 if (TARGET_DEBUG_BUILTIN
)
12915 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
12916 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
12917 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
12919 switch (insn_data
[d
->icode
].operand
[1].mode
)
12922 type
= int_ftype_int_v2sf_v2sf
;
12925 gcc_unreachable ();
12928 def_builtin (d
->name
, type
, d
->code
);
12933 altivec_init_builtins (void)
12935 const struct builtin_description
*d
;
12940 tree pvoid_type_node
= build_pointer_type (void_type_node
);
12942 tree pcvoid_type_node
12943 = build_pointer_type (build_qualified_type (void_type_node
,
12946 tree int_ftype_opaque
12947 = build_function_type_list (integer_type_node
,
12948 opaque_V4SI_type_node
, NULL_TREE
);
12949 tree opaque_ftype_opaque
12950 = build_function_type_list (integer_type_node
, NULL_TREE
);
12951 tree opaque_ftype_opaque_int
12952 = build_function_type_list (opaque_V4SI_type_node
,
12953 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
12954 tree opaque_ftype_opaque_opaque_int
12955 = build_function_type_list (opaque_V4SI_type_node
,
12956 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
12957 integer_type_node
, NULL_TREE
);
12958 tree int_ftype_int_opaque_opaque
12959 = build_function_type_list (integer_type_node
,
12960 integer_type_node
, opaque_V4SI_type_node
,
12961 opaque_V4SI_type_node
, NULL_TREE
);
12962 tree int_ftype_int_v4si_v4si
12963 = build_function_type_list (integer_type_node
,
12964 integer_type_node
, V4SI_type_node
,
12965 V4SI_type_node
, NULL_TREE
);
12966 tree int_ftype_int_v2di_v2di
12967 = build_function_type_list (integer_type_node
,
12968 integer_type_node
, V2DI_type_node
,
12969 V2DI_type_node
, NULL_TREE
);
12970 tree void_ftype_v4si
12971 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
12972 tree v8hi_ftype_void
12973 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
12974 tree void_ftype_void
12975 = build_function_type_list (void_type_node
, NULL_TREE
);
12976 tree void_ftype_int
12977 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
12979 tree opaque_ftype_long_pcvoid
12980 = build_function_type_list (opaque_V4SI_type_node
,
12981 long_integer_type_node
, pcvoid_type_node
,
12983 tree v16qi_ftype_long_pcvoid
12984 = build_function_type_list (V16QI_type_node
,
12985 long_integer_type_node
, pcvoid_type_node
,
12987 tree v8hi_ftype_long_pcvoid
12988 = build_function_type_list (V8HI_type_node
,
12989 long_integer_type_node
, pcvoid_type_node
,
12991 tree v4si_ftype_long_pcvoid
12992 = build_function_type_list (V4SI_type_node
,
12993 long_integer_type_node
, pcvoid_type_node
,
12995 tree v4sf_ftype_long_pcvoid
12996 = build_function_type_list (V4SF_type_node
,
12997 long_integer_type_node
, pcvoid_type_node
,
12999 tree v2df_ftype_long_pcvoid
13000 = build_function_type_list (V2DF_type_node
,
13001 long_integer_type_node
, pcvoid_type_node
,
13003 tree v2di_ftype_long_pcvoid
13004 = build_function_type_list (V2DI_type_node
,
13005 long_integer_type_node
, pcvoid_type_node
,
13008 tree void_ftype_opaque_long_pvoid
13009 = build_function_type_list (void_type_node
,
13010 opaque_V4SI_type_node
, long_integer_type_node
,
13011 pvoid_type_node
, NULL_TREE
);
13012 tree void_ftype_v4si_long_pvoid
13013 = build_function_type_list (void_type_node
,
13014 V4SI_type_node
, long_integer_type_node
,
13015 pvoid_type_node
, NULL_TREE
);
13016 tree void_ftype_v16qi_long_pvoid
13017 = build_function_type_list (void_type_node
,
13018 V16QI_type_node
, long_integer_type_node
,
13019 pvoid_type_node
, NULL_TREE
);
13020 tree void_ftype_v8hi_long_pvoid
13021 = build_function_type_list (void_type_node
,
13022 V8HI_type_node
, long_integer_type_node
,
13023 pvoid_type_node
, NULL_TREE
);
13024 tree void_ftype_v4sf_long_pvoid
13025 = build_function_type_list (void_type_node
,
13026 V4SF_type_node
, long_integer_type_node
,
13027 pvoid_type_node
, NULL_TREE
);
13028 tree void_ftype_v2df_long_pvoid
13029 = build_function_type_list (void_type_node
,
13030 V2DF_type_node
, long_integer_type_node
,
13031 pvoid_type_node
, NULL_TREE
);
13032 tree void_ftype_v2di_long_pvoid
13033 = build_function_type_list (void_type_node
,
13034 V2DI_type_node
, long_integer_type_node
,
13035 pvoid_type_node
, NULL_TREE
);
13036 tree int_ftype_int_v8hi_v8hi
13037 = build_function_type_list (integer_type_node
,
13038 integer_type_node
, V8HI_type_node
,
13039 V8HI_type_node
, NULL_TREE
);
13040 tree int_ftype_int_v16qi_v16qi
13041 = build_function_type_list (integer_type_node
,
13042 integer_type_node
, V16QI_type_node
,
13043 V16QI_type_node
, NULL_TREE
);
13044 tree int_ftype_int_v4sf_v4sf
13045 = build_function_type_list (integer_type_node
,
13046 integer_type_node
, V4SF_type_node
,
13047 V4SF_type_node
, NULL_TREE
);
13048 tree int_ftype_int_v2df_v2df
13049 = build_function_type_list (integer_type_node
,
13050 integer_type_node
, V2DF_type_node
,
13051 V2DF_type_node
, NULL_TREE
);
13052 tree v2di_ftype_v2di
13053 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
13054 tree v4si_ftype_v4si
13055 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
13056 tree v8hi_ftype_v8hi
13057 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
13058 tree v16qi_ftype_v16qi
13059 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
13060 tree v4sf_ftype_v4sf
13061 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
13062 tree v2df_ftype_v2df
13063 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
13064 tree void_ftype_pcvoid_int_int
13065 = build_function_type_list (void_type_node
,
13066 pcvoid_type_node
, integer_type_node
,
13067 integer_type_node
, NULL_TREE
);
13069 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
13070 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
13071 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
13072 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
13073 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
13074 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
13075 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
13076 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
13077 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
13078 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
13079 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
13080 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
13081 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
13082 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
13083 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
13084 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
13085 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
13086 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
13087 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
13088 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
13089 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
13090 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
13091 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
13092 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
13093 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
13094 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
13095 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
13096 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
13097 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
13098 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
13100 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
13101 VSX_BUILTIN_LXVD2X_V2DF
);
13102 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
13103 VSX_BUILTIN_LXVD2X_V2DI
);
13104 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
13105 VSX_BUILTIN_LXVW4X_V4SF
);
13106 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
13107 VSX_BUILTIN_LXVW4X_V4SI
);
13108 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
13109 VSX_BUILTIN_LXVW4X_V8HI
);
13110 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
13111 VSX_BUILTIN_LXVW4X_V16QI
);
13112 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
13113 VSX_BUILTIN_STXVD2X_V2DF
);
13114 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
13115 VSX_BUILTIN_STXVD2X_V2DI
);
13116 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
13117 VSX_BUILTIN_STXVW4X_V4SF
);
13118 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
13119 VSX_BUILTIN_STXVW4X_V4SI
);
13120 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
13121 VSX_BUILTIN_STXVW4X_V8HI
);
13122 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
13123 VSX_BUILTIN_STXVW4X_V16QI
);
13124 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
13125 VSX_BUILTIN_VEC_LD
);
13126 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
13127 VSX_BUILTIN_VEC_ST
);
13129 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
13130 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
13131 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
13133 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
13134 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
13135 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
13136 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
13137 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
13138 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
13139 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
13140 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
13141 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
13142 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
13143 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
13144 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
13146 /* Cell builtins. */
13147 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
13148 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
13149 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
13150 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
13152 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
13153 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
13154 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
13155 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
13157 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
13158 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
13159 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
13160 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
13162 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
13163 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
13164 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
13165 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
13167 /* Add the DST variants. */
13169 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
13170 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
13172 /* Initialize the predicates. */
13173 d
= bdesc_altivec_preds
;
13174 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
13176 enum machine_mode mode1
;
13179 if (rs6000_overloaded_builtin_p (d
->code
))
13182 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
13187 type
= int_ftype_int_opaque_opaque
;
13190 type
= int_ftype_int_v2di_v2di
;
13193 type
= int_ftype_int_v4si_v4si
;
13196 type
= int_ftype_int_v8hi_v8hi
;
13199 type
= int_ftype_int_v16qi_v16qi
;
13202 type
= int_ftype_int_v4sf_v4sf
;
13205 type
= int_ftype_int_v2df_v2df
;
13208 gcc_unreachable ();
13211 def_builtin (d
->name
, type
, d
->code
);
13214 /* Initialize the abs* operators. */
13216 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
13218 enum machine_mode mode0
;
13221 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
13226 type
= v2di_ftype_v2di
;
13229 type
= v4si_ftype_v4si
;
13232 type
= v8hi_ftype_v8hi
;
13235 type
= v16qi_ftype_v16qi
;
13238 type
= v4sf_ftype_v4sf
;
13241 type
= v2df_ftype_v2df
;
13244 gcc_unreachable ();
13247 def_builtin (d
->name
, type
, d
->code
);
13250 /* Initialize target builtin that implements
13251 targetm.vectorize.builtin_mask_for_load. */
13253 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
13254 v16qi_ftype_long_pcvoid
,
13255 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
13256 BUILT_IN_MD
, NULL
, NULL_TREE
);
13257 TREE_READONLY (decl
) = 1;
13258 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
13259 altivec_builtin_mask_for_load
= decl
;
13261 /* Access to the vec_init patterns. */
13262 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
13263 integer_type_node
, integer_type_node
,
13264 integer_type_node
, NULL_TREE
);
13265 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
13267 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
13268 short_integer_type_node
,
13269 short_integer_type_node
,
13270 short_integer_type_node
,
13271 short_integer_type_node
,
13272 short_integer_type_node
,
13273 short_integer_type_node
,
13274 short_integer_type_node
, NULL_TREE
);
13275 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
13277 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
13278 char_type_node
, char_type_node
,
13279 char_type_node
, char_type_node
,
13280 char_type_node
, char_type_node
,
13281 char_type_node
, char_type_node
,
13282 char_type_node
, char_type_node
,
13283 char_type_node
, char_type_node
,
13284 char_type_node
, char_type_node
,
13285 char_type_node
, NULL_TREE
);
13286 def_builtin ("__builtin_vec_init_v16qi", ftype
,
13287 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
13289 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
13290 float_type_node
, float_type_node
,
13291 float_type_node
, NULL_TREE
);
13292 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
13294 /* VSX builtins. */
13295 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
13296 double_type_node
, NULL_TREE
);
13297 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
13299 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
13300 intDI_type_node
, NULL_TREE
);
13301 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
13303 /* Access to the vec_set patterns. */
13304 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
13306 integer_type_node
, NULL_TREE
);
13307 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
13309 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
13311 integer_type_node
, NULL_TREE
);
13312 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
13314 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
13316 integer_type_node
, NULL_TREE
);
13317 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
13319 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
13321 integer_type_node
, NULL_TREE
);
13322 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
13324 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
13326 integer_type_node
, NULL_TREE
);
13327 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
13329 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
13331 integer_type_node
, NULL_TREE
);
13332 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
13334 /* Access to the vec_extract patterns. */
13335 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
13336 integer_type_node
, NULL_TREE
);
13337 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
13339 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
13340 integer_type_node
, NULL_TREE
);
13341 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
13343 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
13344 integer_type_node
, NULL_TREE
);
13345 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
13347 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
13348 integer_type_node
, NULL_TREE
);
13349 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
13351 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
13352 integer_type_node
, NULL_TREE
);
13353 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
13355 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
13356 integer_type_node
, NULL_TREE
);
13357 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
13361 htm_init_builtins (void)
13363 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
13364 const struct builtin_description
*d
;
13368 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
13370 tree op
[MAX_HTM_OPERANDS
], type
;
13371 HOST_WIDE_INT mask
= d
->mask
;
13372 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
13373 bool void_func
= (attr
& RS6000_BTC_VOID
);
13374 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
13376 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
13377 : unsigned_type_node
;
13379 if ((mask
& builtin_mask
) != mask
)
13381 if (TARGET_DEBUG_BUILTIN
)
13382 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
13388 if (TARGET_DEBUG_BUILTIN
)
13389 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
13390 (long unsigned) i
);
13394 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
13396 if (attr_args
== RS6000_BTC_UNARY
)
13397 op
[nopnds
++] = argtype
;
13398 else if (attr_args
== RS6000_BTC_BINARY
)
13400 op
[nopnds
++] = argtype
;
13401 op
[nopnds
++] = argtype
;
13403 else if (attr_args
== RS6000_BTC_TERNARY
)
13405 op
[nopnds
++] = argtype
;
13406 op
[nopnds
++] = argtype
;
13407 op
[nopnds
++] = argtype
;
13413 type
= build_function_type_list (op
[0], NULL_TREE
);
13416 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
13419 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
13422 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
13426 gcc_unreachable ();
13429 def_builtin (d
->name
, type
, d
->code
);
13433 /* Hash function for builtin functions with up to 3 arguments and a return
13436 builtin_hash_function (const void *hash_entry
)
13440 const struct builtin_hash_struct
*bh
=
13441 (const struct builtin_hash_struct
*) hash_entry
;
13443 for (i
= 0; i
< 4; i
++)
13445 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
13446 ret
= (ret
* 2) + bh
->uns_p
[i
];
13452 /* Compare builtin hash entries H1 and H2 for equivalence. */
13454 builtin_hash_eq (const void *h1
, const void *h2
)
13456 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
13457 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
13459 return ((p1
->mode
[0] == p2
->mode
[0])
13460 && (p1
->mode
[1] == p2
->mode
[1])
13461 && (p1
->mode
[2] == p2
->mode
[2])
13462 && (p1
->mode
[3] == p2
->mode
[3])
13463 && (p1
->uns_p
[0] == p2
->uns_p
[0])
13464 && (p1
->uns_p
[1] == p2
->uns_p
[1])
13465 && (p1
->uns_p
[2] == p2
->uns_p
[2])
13466 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
13469 /* Map types for builtin functions with an explicit return type and up to 3
13470 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
13471 of the argument. */
13473 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
13474 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
13475 enum rs6000_builtins builtin
, const char *name
)
13477 struct builtin_hash_struct h
;
13478 struct builtin_hash_struct
*h2
;
13482 tree ret_type
= NULL_TREE
;
13483 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
13485 /* Create builtin_hash_table. */
13486 if (builtin_hash_table
== NULL
)
13487 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
13488 builtin_hash_eq
, NULL
);
13490 h
.type
= NULL_TREE
;
13491 h
.mode
[0] = mode_ret
;
13492 h
.mode
[1] = mode_arg0
;
13493 h
.mode
[2] = mode_arg1
;
13494 h
.mode
[3] = mode_arg2
;
13500 /* If the builtin is a type that produces unsigned results or takes unsigned
13501 arguments, and it is returned as a decl for the vectorizer (such as
13502 widening multiplies, permute), make sure the arguments and return value
13503 are type correct. */
13506 /* unsigned 1 argument functions. */
13507 case CRYPTO_BUILTIN_VSBOX
:
13508 case P8V_BUILTIN_VGBBD
:
13513 /* unsigned 2 argument functions. */
13514 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
13515 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
13516 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
13517 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
13518 case CRYPTO_BUILTIN_VCIPHER
:
13519 case CRYPTO_BUILTIN_VCIPHERLAST
:
13520 case CRYPTO_BUILTIN_VNCIPHER
:
13521 case CRYPTO_BUILTIN_VNCIPHERLAST
:
13522 case CRYPTO_BUILTIN_VPMSUMB
:
13523 case CRYPTO_BUILTIN_VPMSUMH
:
13524 case CRYPTO_BUILTIN_VPMSUMW
:
13525 case CRYPTO_BUILTIN_VPMSUMD
:
13526 case CRYPTO_BUILTIN_VPMSUM
:
13532 /* unsigned 3 argument functions. */
13533 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
13534 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
13535 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
13536 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
13537 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
13538 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
13539 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
13540 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
13541 case VSX_BUILTIN_VPERM_16QI_UNS
:
13542 case VSX_BUILTIN_VPERM_8HI_UNS
:
13543 case VSX_BUILTIN_VPERM_4SI_UNS
:
13544 case VSX_BUILTIN_VPERM_2DI_UNS
:
13545 case VSX_BUILTIN_XXSEL_16QI_UNS
:
13546 case VSX_BUILTIN_XXSEL_8HI_UNS
:
13547 case VSX_BUILTIN_XXSEL_4SI_UNS
:
13548 case VSX_BUILTIN_XXSEL_2DI_UNS
:
13549 case CRYPTO_BUILTIN_VPERMXOR
:
13550 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
13551 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
13552 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
13553 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
13554 case CRYPTO_BUILTIN_VSHASIGMAW
:
13555 case CRYPTO_BUILTIN_VSHASIGMAD
:
13556 case CRYPTO_BUILTIN_VSHASIGMA
:
13563 /* signed permute functions with unsigned char mask. */
13564 case ALTIVEC_BUILTIN_VPERM_16QI
:
13565 case ALTIVEC_BUILTIN_VPERM_8HI
:
13566 case ALTIVEC_BUILTIN_VPERM_4SI
:
13567 case ALTIVEC_BUILTIN_VPERM_4SF
:
13568 case ALTIVEC_BUILTIN_VPERM_2DI
:
13569 case ALTIVEC_BUILTIN_VPERM_2DF
:
13570 case VSX_BUILTIN_VPERM_16QI
:
13571 case VSX_BUILTIN_VPERM_8HI
:
13572 case VSX_BUILTIN_VPERM_4SI
:
13573 case VSX_BUILTIN_VPERM_4SF
:
13574 case VSX_BUILTIN_VPERM_2DI
:
13575 case VSX_BUILTIN_VPERM_2DF
:
13579 /* unsigned args, signed return. */
13580 case VSX_BUILTIN_XVCVUXDDP_UNS
:
13581 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
13585 /* signed args, unsigned return. */
13586 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
13587 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
13595 /* Figure out how many args are present. */
13596 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
13600 fatal_error ("internal error: builtin function %s had no type", name
);
13602 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
13603 if (!ret_type
&& h
.uns_p
[0])
13604 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
13607 fatal_error ("internal error: builtin function %s had an unexpected "
13608 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
13610 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
13611 arg_type
[i
] = NULL_TREE
;
13613 for (i
= 0; i
< num_args
; i
++)
13615 int m
= (int) h
.mode
[i
+1];
13616 int uns_p
= h
.uns_p
[i
+1];
13618 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
13619 if (!arg_type
[i
] && uns_p
)
13620 arg_type
[i
] = builtin_mode_to_type
[m
][0];
13623 fatal_error ("internal error: builtin function %s, argument %d "
13624 "had unexpected argument type %s", name
, i
,
13625 GET_MODE_NAME (m
));
13628 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
13629 if (*found
== NULL
)
13631 h2
= ggc_alloc_builtin_hash_struct ();
13633 *found
= (void *)h2
;
13635 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
13636 arg_type
[2], NULL_TREE
);
13639 return ((struct builtin_hash_struct
*)(*found
))->type
;
13643 rs6000_common_init_builtins (void)
13645 const struct builtin_description
*d
;
13648 tree opaque_ftype_opaque
= NULL_TREE
;
13649 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
13650 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
13651 tree v2si_ftype_qi
= NULL_TREE
;
13652 tree v2si_ftype_v2si_qi
= NULL_TREE
;
13653 tree v2si_ftype_int_qi
= NULL_TREE
;
13654 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
13656 if (!TARGET_PAIRED_FLOAT
)
13658 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
13659 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
13662 /* Paired and SPE builtins are only available if you build a compiler with
13663 the appropriate options, so only create those builtins with the
13664 appropriate compiler option. Create Altivec and VSX builtins on machines
13665 with at least the general purpose extensions (970 and newer) to allow the
13666 use of the target attribute.. */
13668 if (TARGET_EXTRA_BUILTINS
)
13669 builtin_mask
|= RS6000_BTM_COMMON
;
13671 /* Add the ternary operators. */
13673 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13676 HOST_WIDE_INT mask
= d
->mask
;
13678 if ((mask
& builtin_mask
) != mask
)
13680 if (TARGET_DEBUG_BUILTIN
)
13681 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
13685 if (rs6000_overloaded_builtin_p (d
->code
))
13687 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
13688 type
= opaque_ftype_opaque_opaque_opaque
13689 = build_function_type_list (opaque_V4SI_type_node
,
13690 opaque_V4SI_type_node
,
13691 opaque_V4SI_type_node
,
13692 opaque_V4SI_type_node
,
13697 enum insn_code icode
= d
->icode
;
13700 if (TARGET_DEBUG_BUILTIN
)
13701 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
13707 if (icode
== CODE_FOR_nothing
)
13709 if (TARGET_DEBUG_BUILTIN
)
13710 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
13716 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
13717 insn_data
[icode
].operand
[1].mode
,
13718 insn_data
[icode
].operand
[2].mode
,
13719 insn_data
[icode
].operand
[3].mode
,
13723 def_builtin (d
->name
, type
, d
->code
);
13726 /* Add the binary operators. */
13728 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13730 enum machine_mode mode0
, mode1
, mode2
;
13732 HOST_WIDE_INT mask
= d
->mask
;
13734 if ((mask
& builtin_mask
) != mask
)
13736 if (TARGET_DEBUG_BUILTIN
)
13737 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
13741 if (rs6000_overloaded_builtin_p (d
->code
))
13743 if (! (type
= opaque_ftype_opaque_opaque
))
13744 type
= opaque_ftype_opaque_opaque
13745 = build_function_type_list (opaque_V4SI_type_node
,
13746 opaque_V4SI_type_node
,
13747 opaque_V4SI_type_node
,
13752 enum insn_code icode
= d
->icode
;
13755 if (TARGET_DEBUG_BUILTIN
)
13756 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
13762 if (icode
== CODE_FOR_nothing
)
13764 if (TARGET_DEBUG_BUILTIN
)
13765 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
13771 mode0
= insn_data
[icode
].operand
[0].mode
;
13772 mode1
= insn_data
[icode
].operand
[1].mode
;
13773 mode2
= insn_data
[icode
].operand
[2].mode
;
13775 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
13777 if (! (type
= v2si_ftype_v2si_qi
))
13778 type
= v2si_ftype_v2si_qi
13779 = build_function_type_list (opaque_V2SI_type_node
,
13780 opaque_V2SI_type_node
,
13785 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
13786 && mode2
== QImode
)
13788 if (! (type
= v2si_ftype_int_qi
))
13789 type
= v2si_ftype_int_qi
13790 = build_function_type_list (opaque_V2SI_type_node
,
13797 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
13801 def_builtin (d
->name
, type
, d
->code
);
13804 /* Add the simple unary operators. */
13806 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13808 enum machine_mode mode0
, mode1
;
13810 HOST_WIDE_INT mask
= d
->mask
;
13812 if ((mask
& builtin_mask
) != mask
)
13814 if (TARGET_DEBUG_BUILTIN
)
13815 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
13819 if (rs6000_overloaded_builtin_p (d
->code
))
13821 if (! (type
= opaque_ftype_opaque
))
13822 type
= opaque_ftype_opaque
13823 = build_function_type_list (opaque_V4SI_type_node
,
13824 opaque_V4SI_type_node
,
13829 enum insn_code icode
= d
->icode
;
13832 if (TARGET_DEBUG_BUILTIN
)
13833 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
13839 if (icode
== CODE_FOR_nothing
)
13841 if (TARGET_DEBUG_BUILTIN
)
13842 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
13848 mode0
= insn_data
[icode
].operand
[0].mode
;
13849 mode1
= insn_data
[icode
].operand
[1].mode
;
13851 if (mode0
== V2SImode
&& mode1
== QImode
)
13853 if (! (type
= v2si_ftype_qi
))
13854 type
= v2si_ftype_qi
13855 = build_function_type_list (opaque_V2SI_type_node
,
13861 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
13865 def_builtin (d
->name
, type
, d
->code
);
13870 rs6000_init_libfuncs (void)
13872 if (!TARGET_IEEEQUAD
)
13873 /* AIX/Darwin/64-bit Linux quad floating point routines. */
13874 if (!TARGET_XL_COMPAT
)
13876 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
13877 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
13878 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
13879 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
13881 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
13883 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
13884 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
13885 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
13886 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
13887 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
13888 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
13889 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
13891 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
13892 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
13893 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
13894 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
13895 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
13896 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
13897 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
13898 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
13901 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
13902 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
13906 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
13907 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
13908 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
13909 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
13913 /* 32-bit SVR4 quad floating point routines. */
13915 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
13916 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
13917 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
13918 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
13919 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
13920 if (TARGET_PPC_GPOPT
)
13921 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
13923 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
13924 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
13925 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
13926 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
13927 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
13928 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
13930 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
13931 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
13932 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
13933 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
13934 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
13935 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
13936 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
13937 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
13942 /* Expand a block clear operation, and return 1 if successful. Return 0
13943 if we should let the compiler generate normal code.
13945 operands[0] is the destination
13946 operands[1] is the length
13947 operands[3] is the alignment */
13950 expand_block_clear (rtx operands
[])
13952 rtx orig_dest
= operands
[0];
13953 rtx bytes_rtx
= operands
[1];
13954 rtx align_rtx
= operands
[3];
13955 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
13956 HOST_WIDE_INT align
;
13957 HOST_WIDE_INT bytes
;
13962 /* If this is not a fixed size move, just call memcpy */
13966 /* This must be a fixed size alignment */
13967 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
13968 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
13970 /* Anything to clear? */
13971 bytes
= INTVAL (bytes_rtx
);
13975 /* Use the builtin memset after a point, to avoid huge code bloat.
13976 When optimize_size, avoid any significant code bloat; calling
13977 memset is about 4 instructions, so allow for one instruction to
13978 load zero and three to do clearing. */
13979 if (TARGET_ALTIVEC
&& align
>= 128)
13981 else if (TARGET_POWERPC64
&& align
>= 32)
13983 else if (TARGET_SPE
&& align
>= 64)
13988 if (optimize_size
&& bytes
> 3 * clear_step
)
13990 if (! optimize_size
&& bytes
> 8 * clear_step
)
13993 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
13995 enum machine_mode mode
= BLKmode
;
13998 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
14003 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
14008 else if (bytes
>= 8 && TARGET_POWERPC64
14009 /* 64-bit loads and stores require word-aligned
14011 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
14016 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
14017 { /* move 4 bytes */
14021 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
14022 { /* move 2 bytes */
14026 else /* move 1 byte at a time */
14032 dest
= adjust_address (orig_dest
, mode
, offset
);
14034 emit_move_insn (dest
, CONST0_RTX (mode
));
14041 /* Expand a block move operation, and return 1 if successful. Return 0
14042 if we should let the compiler generate normal code.
14044 operands[0] is the destination
14045 operands[1] is the source
14046 operands[2] is the length
14047 operands[3] is the alignment */
14049 #define MAX_MOVE_REG 4
14052 expand_block_move (rtx operands
[])
14054 rtx orig_dest
= operands
[0];
14055 rtx orig_src
= operands
[1];
14056 rtx bytes_rtx
= operands
[2];
14057 rtx align_rtx
= operands
[3];
14058 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14063 rtx stores
[MAX_MOVE_REG
];
14066 /* If this is not a fixed size move, just call memcpy */
14070 /* This must be a fixed size alignment */
14071 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14072 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14074 /* Anything to move? */
14075 bytes
= INTVAL (bytes_rtx
);
14079 if (bytes
> rs6000_block_move_inline_limit
)
14082 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
14085 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
14086 rtx (*mov
) (rtx
, rtx
);
14088 enum machine_mode mode
= BLKmode
;
14091 /* Altivec first, since it will be faster than a string move
14092 when it applies, and usually not significantly larger. */
14093 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
14097 gen_func
.mov
= gen_movv4si
;
14099 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
14103 gen_func
.mov
= gen_movv2si
;
14105 else if (TARGET_STRING
14106 && bytes
> 24 /* move up to 32 bytes at a time */
14112 && ! fixed_regs
[10]
14113 && ! fixed_regs
[11]
14114 && ! fixed_regs
[12])
14116 move_bytes
= (bytes
> 32) ? 32 : bytes
;
14117 gen_func
.movmemsi
= gen_movmemsi_8reg
;
14119 else if (TARGET_STRING
14120 && bytes
> 16 /* move up to 24 bytes at a time */
14126 && ! fixed_regs
[10])
14128 move_bytes
= (bytes
> 24) ? 24 : bytes
;
14129 gen_func
.movmemsi
= gen_movmemsi_6reg
;
14131 else if (TARGET_STRING
14132 && bytes
> 8 /* move up to 16 bytes at a time */
14136 && ! fixed_regs
[8])
14138 move_bytes
= (bytes
> 16) ? 16 : bytes
;
14139 gen_func
.movmemsi
= gen_movmemsi_4reg
;
14141 else if (bytes
>= 8 && TARGET_POWERPC64
14142 /* 64-bit loads and stores require word-aligned
14144 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
14148 gen_func
.mov
= gen_movdi
;
14150 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
14151 { /* move up to 8 bytes at a time */
14152 move_bytes
= (bytes
> 8) ? 8 : bytes
;
14153 gen_func
.movmemsi
= gen_movmemsi_2reg
;
14155 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
14156 { /* move 4 bytes */
14159 gen_func
.mov
= gen_movsi
;
14161 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
14162 { /* move 2 bytes */
14165 gen_func
.mov
= gen_movhi
;
14167 else if (TARGET_STRING
&& bytes
> 1)
14168 { /* move up to 4 bytes at a time */
14169 move_bytes
= (bytes
> 4) ? 4 : bytes
;
14170 gen_func
.movmemsi
= gen_movmemsi_1reg
;
14172 else /* move 1 byte at a time */
14176 gen_func
.mov
= gen_movqi
;
14179 src
= adjust_address (orig_src
, mode
, offset
);
14180 dest
= adjust_address (orig_dest
, mode
, offset
);
14182 if (mode
!= BLKmode
)
14184 rtx tmp_reg
= gen_reg_rtx (mode
);
14186 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
14187 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
14190 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
14193 for (i
= 0; i
< num_reg
; i
++)
14194 emit_insn (stores
[i
]);
14198 if (mode
== BLKmode
)
14200 /* Move the address into scratch registers. The movmemsi
14201 patterns require zero offset. */
14202 if (!REG_P (XEXP (src
, 0)))
14204 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
14205 src
= replace_equiv_address (src
, src_reg
);
14207 set_mem_size (src
, move_bytes
);
14209 if (!REG_P (XEXP (dest
, 0)))
14211 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
14212 dest
= replace_equiv_address (dest
, dest_reg
);
14214 set_mem_size (dest
, move_bytes
);
14216 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
14217 GEN_INT (move_bytes
& 31),
14226 /* Return a string to perform a load_multiple operation.
14227 operands[0] is the vector.
14228 operands[1] is the source address.
14229 operands[2] is the first destination register. */
14232 rs6000_output_load_multiple (rtx operands
[3])
14234 /* We have to handle the case where the pseudo used to contain the address
14235 is assigned to one of the output registers. */
14237 int words
= XVECLEN (operands
[0], 0);
14240 if (XVECLEN (operands
[0], 0) == 1)
14241 return "lwz %2,0(%1)";
14243 for (i
= 0; i
< words
; i
++)
14244 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
14245 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
14249 xop
[0] = GEN_INT (4 * (words
-1));
14250 xop
[1] = operands
[1];
14251 xop
[2] = operands
[2];
14252 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
14257 xop
[0] = GEN_INT (4 * (words
-1));
14258 xop
[1] = operands
[1];
14259 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
14260 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
14265 for (j
= 0; j
< words
; j
++)
14268 xop
[0] = GEN_INT (j
* 4);
14269 xop
[1] = operands
[1];
14270 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
14271 output_asm_insn ("lwz %2,%0(%1)", xop
);
14273 xop
[0] = GEN_INT (i
* 4);
14274 xop
[1] = operands
[1];
14275 output_asm_insn ("lwz %1,%0(%1)", xop
);
14280 return "lswi %2,%1,%N0";
14284 /* A validation routine: say whether CODE, a condition code, and MODE
14285 match. The other alternatives either don't make sense or should
14286 never be generated. */
14289 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
14291 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
14292 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
14293 && GET_MODE_CLASS (mode
) == MODE_CC
);
14295 /* These don't make sense. */
14296 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
14297 || mode
!= CCUNSmode
);
14299 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
14300 || mode
== CCUNSmode
);
14302 gcc_assert (mode
== CCFPmode
14303 || (code
!= ORDERED
&& code
!= UNORDERED
14304 && code
!= UNEQ
&& code
!= LTGT
14305 && code
!= UNGT
&& code
!= UNLT
14306 && code
!= UNGE
&& code
!= UNLE
));
14308 /* These should never be generated except for
14309 flag_finite_math_only. */
14310 gcc_assert (mode
!= CCFPmode
14311 || flag_finite_math_only
14312 || (code
!= LE
&& code
!= GE
14313 && code
!= UNEQ
&& code
!= LTGT
14314 && code
!= UNGT
&& code
!= UNLT
));
14316 /* These are invalid; the information is not there. */
14317 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
14321 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
14322 mask required to convert the result of a rotate insn into a shift
14323 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
14326 includes_lshift_p (rtx shiftop
, rtx andop
)
14328 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
14330 shift_mask
<<= INTVAL (shiftop
);
14332 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
14335 /* Similar, but for right shift. */
14338 includes_rshift_p (rtx shiftop
, rtx andop
)
14340 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
14342 shift_mask
>>= INTVAL (shiftop
);
14344 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
14347 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
14348 to perform a left shift. It must have exactly SHIFTOP least
14349 significant 0's, then one or more 1's, then zero or more 0's. */
14352 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
14354 if (GET_CODE (andop
) == CONST_INT
)
14356 HOST_WIDE_INT c
, lsb
, shift_mask
;
14358 c
= INTVAL (andop
);
14359 if (c
== 0 || c
== ~0)
14363 shift_mask
<<= INTVAL (shiftop
);
14365 /* Find the least significant one bit. */
14368 /* It must coincide with the LSB of the shift mask. */
14369 if (-lsb
!= shift_mask
)
14372 /* Invert to look for the next transition (if any). */
14375 /* Remove the low group of ones (originally low group of zeros). */
14378 /* Again find the lsb, and check we have all 1's above. */
14386 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
14387 to perform a left shift. It must have SHIFTOP or more least
14388 significant 0's, with the remainder of the word 1's. */
14391 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
14393 if (GET_CODE (andop
) == CONST_INT
)
14395 HOST_WIDE_INT c
, lsb
, shift_mask
;
14398 shift_mask
<<= INTVAL (shiftop
);
14399 c
= INTVAL (andop
);
14401 /* Find the least significant one bit. */
14404 /* It must be covered by the shift mask.
14405 This test also rejects c == 0. */
14406 if ((lsb
& shift_mask
) == 0)
14409 /* Check we have all 1's above the transition, and reject all 1's. */
14410 return c
== -lsb
&& lsb
!= 1;
14416 /* Return 1 if operands will generate a valid arguments to rlwimi
14417 instruction for insert with right shift in 64-bit mode. The mask may
14418 not start on the first bit or stop on the last bit because wrap-around
14419 effects of instruction do not correspond to semantics of RTL insn. */
14422 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
14424 if (INTVAL (startop
) > 32
14425 && INTVAL (startop
) < 64
14426 && INTVAL (sizeop
) > 1
14427 && INTVAL (sizeop
) + INTVAL (startop
) < 64
14428 && INTVAL (shiftop
) > 0
14429 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
14430 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
14436 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
14437 for lfq and stfq insns iff the registers are hard registers. */
14440 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
14442 /* We might have been passed a SUBREG. */
14443 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
14446 /* We might have been passed non floating point registers. */
14447 if (!FP_REGNO_P (REGNO (reg1
))
14448 || !FP_REGNO_P (REGNO (reg2
)))
14451 return (REGNO (reg1
) == REGNO (reg2
) - 1);
14454 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
14455 addr1 and addr2 must be in consecutive memory locations
14456 (addr2 == addr1 + 8). */
14459 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
14462 unsigned int reg1
, reg2
;
14463 int offset1
, offset2
;
14465 /* The mems cannot be volatile. */
14466 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
14469 addr1
= XEXP (mem1
, 0);
14470 addr2
= XEXP (mem2
, 0);
14472 /* Extract an offset (if used) from the first addr. */
14473 if (GET_CODE (addr1
) == PLUS
)
14475 /* If not a REG, return zero. */
14476 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
14480 reg1
= REGNO (XEXP (addr1
, 0));
14481 /* The offset must be constant! */
14482 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
14484 offset1
= INTVAL (XEXP (addr1
, 1));
14487 else if (GET_CODE (addr1
) != REG
)
14491 reg1
= REGNO (addr1
);
14492 /* This was a simple (mem (reg)) expression. Offset is 0. */
14496 /* And now for the second addr. */
14497 if (GET_CODE (addr2
) == PLUS
)
14499 /* If not a REG, return zero. */
14500 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
14504 reg2
= REGNO (XEXP (addr2
, 0));
14505 /* The offset must be constant. */
14506 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
14508 offset2
= INTVAL (XEXP (addr2
, 1));
14511 else if (GET_CODE (addr2
) != REG
)
14515 reg2
= REGNO (addr2
);
14516 /* This was a simple (mem (reg)) expression. Offset is 0. */
14520 /* Both of these must have the same base register. */
14524 /* The offset for the second addr must be 8 more than the first addr. */
14525 if (offset2
!= offset1
+ 8)
14528 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
14535 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
14537 static bool eliminated
= false;
14540 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
14541 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
14544 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
14545 gcc_assert (mem
!= NULL_RTX
);
14549 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
14550 cfun
->machine
->sdmode_stack_slot
= mem
;
14556 if (TARGET_DEBUG_ADDR
)
14558 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
14559 GET_MODE_NAME (mode
));
14561 fprintf (stderr
, "\tNULL_RTX\n");
14570 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
14572 /* Don't walk into types. */
14573 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
14575 *walk_subtrees
= 0;
14579 switch (TREE_CODE (*tp
))
14588 case VIEW_CONVERT_EXPR
:
14589 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
14599 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
14600 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
14601 only work on the traditional altivec registers, note if an altivec register
14604 static enum rs6000_reg_type
14605 register_to_reg_type (rtx reg
, bool *is_altivec
)
14607 HOST_WIDE_INT regno
;
14608 enum reg_class rclass
;
14610 if (GET_CODE (reg
) == SUBREG
)
14611 reg
= SUBREG_REG (reg
);
14614 return NO_REG_TYPE
;
14616 regno
= REGNO (reg
);
14617 if (regno
>= FIRST_PSEUDO_REGISTER
)
14619 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
14620 return PSEUDO_REG_TYPE
;
14622 regno
= true_regnum (reg
);
14623 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
14624 return PSEUDO_REG_TYPE
;
14627 gcc_assert (regno
>= 0);
14629 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
14630 *is_altivec
= true;
14632 rclass
= rs6000_regno_regclass
[regno
];
14633 return reg_class_to_reg_type
[(int)rclass
];
14636 /* Helper function for rs6000_secondary_reload to return true if a move to a
14637 different register classe is really a simple move. */
14640 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
14641 enum rs6000_reg_type from_type
,
14642 enum machine_mode mode
)
14646 /* Add support for various direct moves available. In this function, we only
14647 look at cases where we don't need any extra registers, and one or more
14648 simple move insns are issued. At present, 32-bit integers are not allowed
14649 in FPR/VSX registers. Single precision binary floating is not a simple
14650 move because we need to convert to the single precision memory layout.
14651 The 4-byte SDmode can be moved. */
14652 size
= GET_MODE_SIZE (mode
);
14653 if (TARGET_DIRECT_MOVE
14654 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
14655 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14656 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
14659 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
14660 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
14661 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
14664 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
14665 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
14666 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
14672 /* Power8 helper function for rs6000_secondary_reload, handle all of the
14673 special direct moves that involve allocating an extra register, return the
14674 insn code of the helper function if there is such a function or
14675 CODE_FOR_nothing if not. */
14678 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
14679 enum rs6000_reg_type from_type
,
14680 enum machine_mode mode
,
14681 secondary_reload_info
*sri
,
14685 enum insn_code icode
= CODE_FOR_nothing
;
14687 int size
= GET_MODE_SIZE (mode
);
14689 if (TARGET_POWERPC64
)
14693 /* Handle moving 128-bit values from GPRs to VSX point registers on
14694 power8 when running in 64-bit mode using XXPERMDI to glue the two
14695 64-bit values back together. */
14696 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
14698 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
14699 icode
= reload_vsx_gpr
[(int)mode
];
14702 /* Handle moving 128-bit values from VSX point registers to GPRs on
14703 power8 when running in 64-bit mode using XXPERMDI to get access to the
14704 bottom 64-bit value. */
14705 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14707 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
14708 icode
= reload_gpr_vsx
[(int)mode
];
14712 else if (mode
== SFmode
)
14714 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14716 cost
= 3; /* xscvdpspn, mfvsrd, and. */
14717 icode
= reload_gpr_vsx
[(int)mode
];
14720 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
14722 cost
= 2; /* mtvsrz, xscvspdpn. */
14723 icode
= reload_vsx_gpr
[(int)mode
];
14728 if (TARGET_POWERPC64
&& size
== 16)
14730 /* Handle moving 128-bit values from GPRs to VSX point registers on
14731 power8 when running in 64-bit mode using XXPERMDI to glue the two
14732 64-bit values back together. */
14733 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
14735 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
14736 icode
= reload_vsx_gpr
[(int)mode
];
14739 /* Handle moving 128-bit values from VSX point registers to GPRs on
14740 power8 when running in 64-bit mode using XXPERMDI to get access to the
14741 bottom 64-bit value. */
14742 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
14744 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
14745 icode
= reload_gpr_vsx
[(int)mode
];
14749 else if (!TARGET_POWERPC64
&& size
== 8)
14751 /* Handle moving 64-bit values from GPRs to floating point registers on
14752 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
14753 values back together. Altivec register classes must be handled
14754 specially since a different instruction is used, and the secondary
14755 reload support requires a single instruction class in the scratch
14756 register constraint. However, right now TFmode is not allowed in
14757 Altivec registers, so the pattern will never match. */
14758 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
14760 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
14761 icode
= reload_fpr_gpr
[(int)mode
];
14765 if (icode
!= CODE_FOR_nothing
)
14770 sri
->icode
= icode
;
14771 sri
->extra_cost
= cost
;
14778 /* Return whether a move between two register classes can be done either
14779 directly (simple move) or via a pattern that uses a single extra temporary
14780 (using power8's direct move in this case. */
14783 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
14784 enum rs6000_reg_type from_type
,
14785 enum machine_mode mode
,
14786 secondary_reload_info
*sri
,
14789 /* Fall back to load/store reloads if either type is not a register. */
14790 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
14793 /* If we haven't allocated registers yet, assume the move can be done for the
14794 standard register types. */
14795 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
14796 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
14797 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
14800 /* Moves to the same set of registers is a simple move for non-specialized
14802 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
14805 /* Check whether a simple move can be done directly. */
14806 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
14810 sri
->icode
= CODE_FOR_nothing
;
14811 sri
->extra_cost
= 0;
14816 /* Now check if we can do it in a few steps. */
14817 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
14821 /* Inform reload about cases where moving X with a mode MODE to a register in
14822 RCLASS requires an extra scratch or immediate register. Return the class
14823 needed for the immediate register.
14825 For VSX and Altivec, we may need a register to convert sp+offset into
14828 For misaligned 64-bit gpr loads and stores we need a register to
14829 convert an offset address to indirect. */
14832 rs6000_secondary_reload (bool in_p
,
14834 reg_class_t rclass_i
,
14835 enum machine_mode mode
,
14836 secondary_reload_info
*sri
)
14838 enum reg_class rclass
= (enum reg_class
) rclass_i
;
14839 reg_class_t ret
= ALL_REGS
;
14840 enum insn_code icode
;
14841 bool default_p
= false;
14843 sri
->icode
= CODE_FOR_nothing
;
14844 icode
= rs6000_vector_reload
[mode
][in_p
!= false];
14846 if (REG_P (x
) || register_operand (x
, mode
))
14848 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
14849 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
14850 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
14854 enum rs6000_reg_type exchange
= to_type
;
14855 to_type
= from_type
;
14856 from_type
= exchange
;
14859 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
14862 icode
= (enum insn_code
)sri
->icode
;
14868 /* Handle vector moves with reload helper functions. */
14869 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
14872 sri
->icode
= CODE_FOR_nothing
;
14873 sri
->extra_cost
= 0;
14875 if (GET_CODE (x
) == MEM
)
14877 rtx addr
= XEXP (x
, 0);
14879 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
14880 an extra register in that case, but it would need an extra
14881 register if the addressing is reg+reg or (reg+reg)&(-16). Special
14882 case load/store quad. */
14883 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
14885 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
14886 && GET_MODE_SIZE (mode
) == 16
14887 && quad_memory_operand (x
, mode
))
14889 sri
->icode
= icode
;
14890 sri
->extra_cost
= 2;
14893 else if (!legitimate_indirect_address_p (addr
, false)
14894 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
14897 sri
->icode
= icode
;
14898 /* account for splitting the loads, and converting the
14899 address from reg+reg to reg. */
14900 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
14901 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
14904 /* Allow scalar loads to/from the traditional floating point
14905 registers, even if VSX memory is set. */
14906 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
14907 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
14908 && (legitimate_indirect_address_p (addr
, false)
14909 || legitimate_indirect_address_p (addr
, false)
14910 || rs6000_legitimate_offset_address_p (mode
, addr
,
14914 /* Loads to and stores from vector registers can only do reg+reg
14915 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
14916 scalar modes loading up the traditional floating point registers
14917 to use offset addresses. */
14918 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
14919 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
14921 if (!VECTOR_MEM_ALTIVEC_P (mode
)
14922 && GET_CODE (addr
) == AND
14923 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
14924 && INTVAL (XEXP (addr
, 1)) == -16
14925 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
14926 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
14928 sri
->icode
= icode
;
14929 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
14932 else if (!legitimate_indirect_address_p (addr
, false)
14933 && (rclass
== NO_REGS
14934 || !legitimate_indexed_address_p (addr
, false)))
14936 sri
->icode
= icode
;
14937 sri
->extra_cost
= 1;
14940 icode
= CODE_FOR_nothing
;
14942 /* Any other loads, including to pseudo registers which haven't been
14943 assigned to a register yet, default to require a scratch
14947 sri
->icode
= icode
;
14948 sri
->extra_cost
= 2;
14951 else if (REG_P (x
))
14953 int regno
= true_regnum (x
);
14955 icode
= CODE_FOR_nothing
;
14956 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
14960 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
14961 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
14962 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
14964 /* If memory is needed, use default_secondary_reload to create the
14966 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
14975 else if (TARGET_POWERPC64
14976 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
14978 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
14980 rtx addr
= XEXP (x
, 0);
14981 rtx off
= address_offset (addr
);
14983 if (off
!= NULL_RTX
)
14985 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
14986 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
14988 /* We need a secondary reload when our legitimate_address_p
14989 says the address is good (as otherwise the entire address
14990 will be reloaded), and the offset is not a multiple of
14991 four or we have an address wrap. Address wrap will only
14992 occur for LO_SUMs since legitimate_offset_address_p
14993 rejects addresses for 16-byte mems that will wrap. */
14994 if (GET_CODE (addr
) == LO_SUM
14995 ? (1 /* legitimate_address_p allows any offset for lo_sum */
14996 && ((offset
& 3) != 0
14997 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
14998 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
14999 && (offset
& 3) != 0))
15002 sri
->icode
= CODE_FOR_reload_di_load
;
15004 sri
->icode
= CODE_FOR_reload_di_store
;
15005 sri
->extra_cost
= 2;
15014 else if (!TARGET_POWERPC64
15015 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15017 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
15019 rtx addr
= XEXP (x
, 0);
15020 rtx off
= address_offset (addr
);
15022 if (off
!= NULL_RTX
)
15024 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15025 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15027 /* We need a secondary reload when our legitimate_address_p
15028 says the address is good (as otherwise the entire address
15029 will be reloaded), and we have a wrap.
15031 legitimate_lo_sum_address_p allows LO_SUM addresses to
15032 have any offset so test for wrap in the low 16 bits.
15034 legitimate_offset_address_p checks for the range
15035 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
15036 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
15037 [0x7ff4,0x7fff] respectively, so test for the
15038 intersection of these ranges, [0x7ffc,0x7fff] and
15039 [0x7ff4,0x7ff7] respectively.
15041 Note that the address we see here may have been
15042 manipulated by legitimize_reload_address. */
15043 if (GET_CODE (addr
) == LO_SUM
15044 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
15045 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
15048 sri
->icode
= CODE_FOR_reload_si_load
;
15050 sri
->icode
= CODE_FOR_reload_si_store
;
15051 sri
->extra_cost
= 2;
15064 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
15066 gcc_assert (ret
!= ALL_REGS
);
15068 if (TARGET_DEBUG_ADDR
)
15071 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
15073 reg_class_names
[ret
],
15074 in_p
? "true" : "false",
15075 reg_class_names
[rclass
],
15076 GET_MODE_NAME (mode
));
15079 fprintf (stderr
, ", default secondary reload");
15081 if (sri
->icode
!= CODE_FOR_nothing
)
15082 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
15083 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
15085 fprintf (stderr
, "\n");
15093 /* Better tracing for rs6000_secondary_reload_inner. */
15096 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
15101 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
15103 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
15104 store_p
? "store" : "load");
15107 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
15109 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
15111 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
15112 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
15116 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
15119 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
15120 gcc_unreachable ();
15123 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
15124 to SP+reg addressing. */
15127 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
15129 int regno
= true_regnum (reg
);
15130 enum machine_mode mode
= GET_MODE (reg
);
15131 enum reg_class rclass
;
15133 rtx and_op2
= NULL_RTX
;
15136 rtx scratch_or_premodify
= scratch
;
15140 if (TARGET_DEBUG_ADDR
)
15141 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
15143 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15144 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15146 if (GET_CODE (mem
) != MEM
)
15147 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15149 rclass
= REGNO_REG_CLASS (regno
);
15150 addr
= XEXP (mem
, 0);
15154 /* GPRs can handle reg + small constant, all other addresses need to use
15155 the scratch register. */
15158 if (GET_CODE (addr
) == AND
)
15160 and_op2
= XEXP (addr
, 1);
15161 addr
= XEXP (addr
, 0);
15164 if (GET_CODE (addr
) == PRE_MODIFY
)
15166 scratch_or_premodify
= XEXP (addr
, 0);
15167 if (!REG_P (scratch_or_premodify
))
15168 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15170 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
15171 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15173 addr
= XEXP (addr
, 1);
15176 if (GET_CODE (addr
) == PLUS
15177 && (and_op2
!= NULL_RTX
15178 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15181 addr_op1
= XEXP (addr
, 0);
15182 addr_op2
= XEXP (addr
, 1);
15183 if (!legitimate_indirect_address_p (addr_op1
, false))
15184 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15186 if (!REG_P (addr_op2
)
15187 && (GET_CODE (addr_op2
) != CONST_INT
15188 || !satisfies_constraint_I (addr_op2
)))
15190 if (TARGET_DEBUG_ADDR
)
15193 "\nMove plus addr to register %s, mode = %s: ",
15194 rs6000_reg_names
[REGNO (scratch
)],
15195 GET_MODE_NAME (mode
));
15196 debug_rtx (addr_op2
);
15198 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
15199 addr_op2
= scratch
;
15202 emit_insn (gen_rtx_SET (VOIDmode
,
15203 scratch_or_premodify
,
15204 gen_rtx_PLUS (Pmode
,
15208 addr
= scratch_or_premodify
;
15209 scratch_or_premodify
= scratch
;
15211 else if (!legitimate_indirect_address_p (addr
, false)
15212 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15215 if (TARGET_DEBUG_ADDR
)
15217 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
15218 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
15219 GET_MODE_NAME (mode
));
15222 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
15223 addr
= scratch_or_premodify
;
15224 scratch_or_premodify
= scratch
;
15228 /* Float registers can do offset+reg addressing for scalar types. */
15230 if (legitimate_indirect_address_p (addr
, false) /* reg */
15231 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
15232 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
15233 && and_op2
== NULL_RTX
15234 && scratch_or_premodify
== scratch
15235 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
15238 /* If this isn't a legacy floating point load/store, fall through to the
15241 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
15242 addresses into a scratch register. */
15246 /* With float regs, we need to handle the AND ourselves, since we can't
15247 use the Altivec instruction with an implicit AND -16. Allow scalar
15248 loads to float registers to use reg+offset even if VSX. */
15249 if (GET_CODE (addr
) == AND
15250 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
15251 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
15252 || INTVAL (XEXP (addr
, 1)) != -16
15253 || !VECTOR_MEM_ALTIVEC_P (mode
)))
15255 and_op2
= XEXP (addr
, 1);
15256 addr
= XEXP (addr
, 0);
15259 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
15260 as the address later. */
15261 if (GET_CODE (addr
) == PRE_MODIFY
15262 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
15263 && (rclass
!= FLOAT_REGS
15264 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
15265 || and_op2
!= NULL_RTX
15266 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
15268 scratch_or_premodify
= XEXP (addr
, 0);
15269 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
15270 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15272 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
15273 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15275 addr
= XEXP (addr
, 1);
15278 if (legitimate_indirect_address_p (addr
, false) /* reg */
15279 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
15280 || (GET_CODE (addr
) == AND
/* Altivec memory */
15281 && rclass
== ALTIVEC_REGS
15282 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15283 && INTVAL (XEXP (addr
, 1)) == -16
15284 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
15285 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
15288 else if (GET_CODE (addr
) == PLUS
)
15290 addr_op1
= XEXP (addr
, 0);
15291 addr_op2
= XEXP (addr
, 1);
15292 if (!REG_P (addr_op1
))
15293 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15295 if (TARGET_DEBUG_ADDR
)
15297 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
15298 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
15299 debug_rtx (addr_op2
);
15301 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
15302 emit_insn (gen_rtx_SET (VOIDmode
,
15303 scratch_or_premodify
,
15304 gen_rtx_PLUS (Pmode
,
15307 addr
= scratch_or_premodify
;
15308 scratch_or_premodify
= scratch
;
15311 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
15312 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
15315 if (TARGET_DEBUG_ADDR
)
15317 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
15318 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
15319 GET_MODE_NAME (mode
));
15323 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
15324 addr
= scratch_or_premodify
;
15325 scratch_or_premodify
= scratch
;
15329 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15334 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15337 /* If the original address involved a pre-modify that we couldn't use the VSX
15338 memory instruction with update, and we haven't taken care of already,
15339 store the address in the pre-modify register and use that as the
15341 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
15343 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
15344 addr
= scratch_or_premodify
;
15347 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
15348 memory instruction, recreate the AND now, including the clobber which is
15349 generated by the general ANDSI3/ANDDI3 patterns for the
15350 andi. instruction. */
15351 if (and_op2
!= NULL_RTX
)
15353 if (! legitimate_indirect_address_p (addr
, false))
15355 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
15359 if (TARGET_DEBUG_ADDR
)
15361 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
15362 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
15363 debug_rtx (and_op2
);
15366 and_rtx
= gen_rtx_SET (VOIDmode
,
15368 gen_rtx_AND (Pmode
,
15372 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
15373 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
15374 gen_rtvec (2, and_rtx
, cc_clobber
)));
15378 /* Adjust the address if it changed. */
15379 if (addr
!= XEXP (mem
, 0))
15381 mem
= replace_equiv_address_nv (mem
, addr
);
15382 if (TARGET_DEBUG_ADDR
)
15383 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
15386 /* Now create the move. */
15388 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
15390 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
15395 /* Convert reloads involving 64-bit gprs and misaligned offset
15396 addressing, or multiple 32-bit gprs and offsets that are too large,
15397 to use indirect addressing. */
15400 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
15402 int regno
= true_regnum (reg
);
15403 enum reg_class rclass
;
15405 rtx scratch_or_premodify
= scratch
;
15407 if (TARGET_DEBUG_ADDR
)
15409 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
15410 store_p
? "store" : "load");
15411 fprintf (stderr
, "reg:\n");
15413 fprintf (stderr
, "mem:\n");
15415 fprintf (stderr
, "scratch:\n");
15416 debug_rtx (scratch
);
15419 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
15420 gcc_assert (GET_CODE (mem
) == MEM
);
15421 rclass
= REGNO_REG_CLASS (regno
);
15422 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
15423 addr
= XEXP (mem
, 0);
15425 if (GET_CODE (addr
) == PRE_MODIFY
)
15427 scratch_or_premodify
= XEXP (addr
, 0);
15428 gcc_assert (REG_P (scratch_or_premodify
));
15429 addr
= XEXP (addr
, 1);
15431 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
15433 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
15435 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
15437 /* Now create the move. */
15439 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
15441 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
15446 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
15447 this function has any SDmode references. If we are on a power7 or later, we
15448 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
15449 can load/store the value. */
15452 rs6000_alloc_sdmode_stack_slot (void)
15456 gimple_stmt_iterator gsi
;
15458 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
15460 if (TARGET_NO_SDMODE_STACK
)
15464 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
15466 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
15469 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
15470 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
15476 /* Check for any SDmode parameters of the function. */
15477 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
15479 if (TREE_TYPE (t
) == error_mark_node
)
15482 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
15483 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
15485 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
15486 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
15494 rs6000_instantiate_decls (void)
15496 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
15497 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
15500 /* Given an rtx X being reloaded into a reg required to be
15501 in class CLASS, return the class of reg to actually use.
15502 In general this is just CLASS; but on some machines
15503 in some cases it is preferable to use a more restrictive class.
15505 On the RS/6000, we have to return NO_REGS when we want to reload a
15506 floating-point CONST_DOUBLE to force it to be copied to memory.
15508 We also don't want to reload integer values into floating-point
15509 registers if we can at all help it. In fact, this can
15510 cause reload to die, if it tries to generate a reload of CTR
15511 into a FP register and discovers it doesn't have the memory location
15514 ??? Would it be a good idea to have reload do the converse, that is
15515 try to reload floating modes into FP registers if possible?
15518 static enum reg_class
15519 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
15521 enum machine_mode mode
= GET_MODE (x
);
15523 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
15526 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
15527 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
15528 && easy_vector_constant (x
, mode
))
15529 return ALTIVEC_REGS
;
15531 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
15534 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
15535 return GENERAL_REGS
;
15537 /* For VSX, prefer the traditional registers for 64-bit values because we can
15538 use the non-VSX loads. Prefer the Altivec registers if Altivec is
15539 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
15540 prefer Altivec loads.. */
15541 if (rclass
== VSX_REGS
)
15543 if (GET_MODE_SIZE (mode
) <= 8)
15546 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
15547 return ALTIVEC_REGS
;
15555 /* Debug version of rs6000_preferred_reload_class. */
15556 static enum reg_class
15557 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
15559 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
15562 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
15564 reg_class_names
[ret
], reg_class_names
[rclass
],
15565 GET_MODE_NAME (GET_MODE (x
)));
15571 /* If we are copying between FP or AltiVec registers and anything else, we need
15572 a memory location. The exception is when we are targeting ppc64 and the
15573 move to/from fpr to gpr instructions are available. Also, under VSX, you
15574 can copy vector registers from the FP register set to the Altivec register
15575 set and vice versa. */
15578 rs6000_secondary_memory_needed (enum reg_class from_class
,
15579 enum reg_class to_class
,
15580 enum machine_mode mode
)
15582 enum rs6000_reg_type from_type
, to_type
;
15583 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
15584 || (to_class
== ALTIVEC_REGS
));
15586 /* If a simple/direct move is available, we don't need secondary memory */
15587 from_type
= reg_class_to_reg_type
[(int)from_class
];
15588 to_type
= reg_class_to_reg_type
[(int)to_class
];
15590 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
15591 (secondary_reload_info
*)0, altivec_p
))
15594 /* If we have a floating point or vector register class, we need to use
15595 memory to transfer the data. */
15596 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
15602 /* Debug version of rs6000_secondary_memory_needed. */
15604 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
15605 enum reg_class to_class
,
15606 enum machine_mode mode
)
15608 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
15611 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
15612 "to_class = %s, mode = %s\n",
15613 ret
? "true" : "false",
15614 reg_class_names
[from_class
],
15615 reg_class_names
[to_class
],
15616 GET_MODE_NAME (mode
));
15621 /* Return the register class of a scratch register needed to copy IN into
15622 or out of a register in RCLASS in MODE. If it can be done directly,
15623 NO_REGS is returned. */
15625 static enum reg_class
15626 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
15631 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
15633 && MACHOPIC_INDIRECT
15637 /* We cannot copy a symbolic operand directly into anything
15638 other than BASE_REGS for TARGET_ELF. So indicate that a
15639 register from BASE_REGS is needed as an intermediate
15642 On Darwin, pic addresses require a load from memory, which
15643 needs a base register. */
15644 if (rclass
!= BASE_REGS
15645 && (GET_CODE (in
) == SYMBOL_REF
15646 || GET_CODE (in
) == HIGH
15647 || GET_CODE (in
) == LABEL_REF
15648 || GET_CODE (in
) == CONST
))
15652 if (GET_CODE (in
) == REG
)
15654 regno
= REGNO (in
);
15655 if (regno
>= FIRST_PSEUDO_REGISTER
)
15657 regno
= true_regnum (in
);
15658 if (regno
>= FIRST_PSEUDO_REGISTER
)
15662 else if (GET_CODE (in
) == SUBREG
)
15664 regno
= true_regnum (in
);
15665 if (regno
>= FIRST_PSEUDO_REGISTER
)
15671 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
15673 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
15674 || (regno
>= 0 && INT_REGNO_P (regno
)))
15677 /* Constants, memory, and FP registers can go into FP registers. */
15678 if ((regno
== -1 || FP_REGNO_P (regno
))
15679 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
15680 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
15682 /* Memory, and FP/altivec registers can go into fp/altivec registers under
15683 VSX. However, for scalar variables, use the traditional floating point
15684 registers so that we can use offset+register addressing. */
15686 && (regno
== -1 || VSX_REGNO_P (regno
))
15687 && VSX_REG_CLASS_P (rclass
))
15689 if (GET_MODE_SIZE (mode
) < 16)
15695 /* Memory, and AltiVec registers can go into AltiVec registers. */
15696 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
15697 && rclass
== ALTIVEC_REGS
)
15700 /* We can copy among the CR registers. */
15701 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
15702 && regno
>= 0 && CR_REGNO_P (regno
))
15705 /* Otherwise, we need GENERAL_REGS. */
15706 return GENERAL_REGS
;
15709 /* Debug version of rs6000_secondary_reload_class. */
15710 static enum reg_class
15711 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
15712 enum machine_mode mode
, rtx in
)
15714 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
15716 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
15717 "mode = %s, input rtx:\n",
15718 reg_class_names
[ret
], reg_class_names
[rclass
],
15719 GET_MODE_NAME (mode
));
15725 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
15728 rs6000_cannot_change_mode_class (enum machine_mode from
,
15729 enum machine_mode to
,
15730 enum reg_class rclass
)
15732 unsigned from_size
= GET_MODE_SIZE (from
);
15733 unsigned to_size
= GET_MODE_SIZE (to
);
15735 if (from_size
!= to_size
)
15737 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
15739 if (reg_classes_intersect_p (xclass
, rclass
))
15741 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
15742 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
15744 /* Don't allow 64-bit types to overlap with 128-bit types that take a
15745 single register under VSX because the scalar part of the register
15746 is in the upper 64-bits, and not the lower 64-bits. Types like
15747 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
15748 IEEE floating point can't overlap, and neither can small
15751 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
15754 if (from_size
< 8 || to_size
< 8)
15757 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
15760 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
15769 if (TARGET_E500_DOUBLE
15770 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
15771 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
15772 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
15773 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
15774 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
15777 /* Since the VSX register set includes traditional floating point registers
15778 and altivec registers, just check for the size being different instead of
15779 trying to check whether the modes are vector modes. Otherwise it won't
15780 allow say DF and DI to change classes. For types like TFmode and TDmode
15781 that take 2 64-bit registers, rather than a single 128-bit register, don't
15782 allow subregs of those types to other 128 bit types. */
15783 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
15785 unsigned num_regs
= (from_size
+ 15) / 16;
15786 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
15787 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
15790 return (from_size
!= 8 && from_size
!= 16);
15793 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
15794 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
15797 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
15798 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
15804 /* Debug version of rs6000_cannot_change_mode_class. */
15806 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
15807 enum machine_mode to
,
15808 enum reg_class rclass
)
15810 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
15813 "rs6000_cannot_change_mode_class, return %s, from = %s, "
15814 "to = %s, rclass = %s\n",
15815 ret
? "true" : "false",
15816 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
15817 reg_class_names
[rclass
]);
15822 /* Return a string to do a move operation of 128 bits of data. */
15825 rs6000_output_move_128bit (rtx operands
[])
15827 rtx dest
= operands
[0];
15828 rtx src
= operands
[1];
15829 enum machine_mode mode
= GET_MODE (dest
);
15832 bool dest_gpr_p
, dest_fp_p
, dest_av_p
, dest_vsx_p
;
15833 bool src_gpr_p
, src_fp_p
, src_av_p
, src_vsx_p
;
15837 dest_regno
= REGNO (dest
);
15838 dest_gpr_p
= INT_REGNO_P (dest_regno
);
15839 dest_fp_p
= FP_REGNO_P (dest_regno
);
15840 dest_av_p
= ALTIVEC_REGNO_P (dest_regno
);
15841 dest_vsx_p
= dest_fp_p
| dest_av_p
;
15846 dest_gpr_p
= dest_fp_p
= dest_av_p
= dest_vsx_p
= false;
15851 src_regno
= REGNO (src
);
15852 src_gpr_p
= INT_REGNO_P (src_regno
);
15853 src_fp_p
= FP_REGNO_P (src_regno
);
15854 src_av_p
= ALTIVEC_REGNO_P (src_regno
);
15855 src_vsx_p
= src_fp_p
| src_av_p
;
15860 src_gpr_p
= src_fp_p
= src_av_p
= src_vsx_p
= false;
15863 /* Register moves. */
15864 if (dest_regno
>= 0 && src_regno
>= 0)
15871 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
15875 else if (TARGET_VSX
&& dest_vsx_p
)
15878 return "xxlor %x0,%x1,%x1";
15880 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
15884 else if (TARGET_ALTIVEC
&& dest_av_p
&& src_av_p
)
15885 return "vor %0,%1,%1";
15887 else if (dest_fp_p
&& src_fp_p
)
15892 else if (dest_regno
>= 0 && MEM_P (src
))
15896 if (TARGET_QUAD_MEMORY
&& (dest_regno
& 1) == 0
15897 && quad_memory_operand (src
, mode
)
15898 && !reg_overlap_mentioned_p (dest
, src
))
15900 /* lq/stq only has DQ-form, so avoid X-form that %y produces. */
15901 return REG_P (XEXP (src
, 0)) ? "lq %0,%1" : "lq %0,%y1";
15907 else if (TARGET_ALTIVEC
&& dest_av_p
15908 && altivec_indexed_or_indirect_operand (src
, mode
))
15909 return "lvx %0,%y1";
15911 else if (TARGET_VSX
&& dest_vsx_p
)
15913 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
15914 return "lxvw4x %x0,%y1";
15916 return "lxvd2x %x0,%y1";
15919 else if (TARGET_ALTIVEC
&& dest_av_p
)
15920 return "lvx %0,%y1";
15922 else if (dest_fp_p
)
15927 else if (src_regno
>= 0 && MEM_P (dest
))
15931 if (TARGET_QUAD_MEMORY
&& (src_regno
& 1) == 0
15932 && quad_memory_operand (dest
, mode
))
15934 /* lq/stq only has DQ-form, so avoid X-form that %y produces. */
15935 return REG_P (XEXP (dest
, 0)) ? "stq %1,%0" : "stq %1,%y0";
15941 else if (TARGET_ALTIVEC
&& src_av_p
15942 && altivec_indexed_or_indirect_operand (src
, mode
))
15943 return "stvx %1,%y0";
15945 else if (TARGET_VSX
&& src_vsx_p
)
15947 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
15948 return "stxvw4x %x1,%y0";
15950 return "stxvd2x %x1,%y0";
15953 else if (TARGET_ALTIVEC
&& src_av_p
)
15954 return "stvx %1,%y0";
15961 else if (dest_regno
>= 0
15962 && (GET_CODE (src
) == CONST_INT
15963 || GET_CODE (src
) == CONST_DOUBLE
15964 || GET_CODE (src
) == CONST_VECTOR
))
15969 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
15970 return "xxlxor %x0,%x0,%x0";
15972 else if (TARGET_ALTIVEC
&& dest_av_p
)
15973 return output_vec_const_move (operands
);
15976 if (TARGET_DEBUG_ADDR
)
15978 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
15979 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
15982 gcc_unreachable ();
15986 /* Given a comparison operation, return the bit number in CCR to test. We
15987 know this is a valid comparison.
15989 SCC_P is 1 if this is for an scc. That means that %D will have been
15990 used instead of %C, so the bits will be in different places.
15992 Return -1 if OP isn't a valid comparison for some reason. */
15995 ccr_bit (rtx op
, int scc_p
)
15997 enum rtx_code code
= GET_CODE (op
);
15998 enum machine_mode cc_mode
;
16003 if (!COMPARISON_P (op
))
16006 reg
= XEXP (op
, 0);
16008 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
16010 cc_mode
= GET_MODE (reg
);
16011 cc_regnum
= REGNO (reg
);
16012 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
16014 validate_condition_mode (code
, cc_mode
);
16016 /* When generating a sCOND operation, only positive conditions are
16019 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
16020 || code
== GTU
|| code
== LTU
);
16025 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
16027 return base_bit
+ 2;
16028 case GT
: case GTU
: case UNLE
:
16029 return base_bit
+ 1;
16030 case LT
: case LTU
: case UNGE
:
16032 case ORDERED
: case UNORDERED
:
16033 return base_bit
+ 3;
16036 /* If scc, we will have done a cror to put the bit in the
16037 unordered position. So test that bit. For integer, this is ! LT
16038 unless this is an scc insn. */
16039 return scc_p
? base_bit
+ 3 : base_bit
;
16042 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
16045 gcc_unreachable ();
16049 /* Return the GOT register. */
16052 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
16054 /* The second flow pass currently (June 1999) can't update
16055 regs_ever_live without disturbing other parts of the compiler, so
16056 update it here to make the prolog/epilogue code happy. */
16057 if (!can_create_pseudo_p ()
16058 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
16059 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
16061 crtl
->uses_pic_offset_table
= 1;
16063 return pic_offset_table_rtx
;
16066 static rs6000_stack_t stack_info
;
16068 /* Function to init struct machine_function.
16069 This will be called, via a pointer variable,
16070 from push_function_context. */
16072 static struct machine_function
*
16073 rs6000_init_machine_status (void)
16075 stack_info
.reload_completed
= 0;
16076 return ggc_alloc_cleared_machine_function ();
16079 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
16082 extract_MB (rtx op
)
16085 unsigned long val
= INTVAL (op
);
16087 /* If the high bit is zero, the value is the first 1 bit we find
16089 if ((val
& 0x80000000) == 0)
16091 gcc_assert (val
& 0xffffffff);
16094 while (((val
<<= 1) & 0x80000000) == 0)
16099 /* If the high bit is set and the low bit is not, or the mask is all
16100 1's, the value is zero. */
16101 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
16104 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
16107 while (((val
>>= 1) & 1) != 0)
16114 extract_ME (rtx op
)
16117 unsigned long val
= INTVAL (op
);
16119 /* If the low bit is zero, the value is the first 1 bit we find from
16121 if ((val
& 1) == 0)
16123 gcc_assert (val
& 0xffffffff);
16126 while (((val
>>= 1) & 1) == 0)
16132 /* If the low bit is set and the high bit is not, or the mask is all
16133 1's, the value is 31. */
16134 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
16137 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
16140 while (((val
<<= 1) & 0x80000000) != 0)
16146 /* Locate some local-dynamic symbol still in use by this function
16147 so that we can print its name in some tls_ld pattern. */
16149 static const char *
16150 rs6000_get_some_local_dynamic_name (void)
16154 if (cfun
->machine
->some_ld_name
)
16155 return cfun
->machine
->some_ld_name
;
16157 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16159 && for_each_rtx (&PATTERN (insn
),
16160 rs6000_get_some_local_dynamic_name_1
, 0))
16161 return cfun
->machine
->some_ld_name
;
16163 gcc_unreachable ();
16166 /* Helper function for rs6000_get_some_local_dynamic_name. */
16169 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
16173 if (GET_CODE (x
) == SYMBOL_REF
)
16175 const char *str
= XSTR (x
, 0);
16176 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
16178 cfun
->machine
->some_ld_name
= str
;
16186 /* Write out a function code label. */
16189 rs6000_output_function_entry (FILE *file
, const char *fname
)
16191 if (fname
[0] != '.')
16193 switch (DEFAULT_ABI
)
16196 gcc_unreachable ();
16202 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
16211 RS6000_OUTPUT_BASENAME (file
, fname
);
16214 /* Print an operand. Recognize special options, documented below. */
16217 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
16218 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
16220 #define SMALL_DATA_RELOC "sda21"
16221 #define SMALL_DATA_REG 0
16225 print_operand (FILE *file
, rtx x
, int code
)
16228 unsigned HOST_WIDE_INT uval
;
16232 /* %a is output_address. */
16235 /* If constant, low-order 16 bits of constant, unsigned.
16236 Otherwise, write normally. */
16238 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
16240 print_operand (file
, x
, 0);
16244 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
16245 for 64-bit mask direction. */
16246 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
16249 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
16253 /* Like 'J' but get to the GT bit only. */
16254 gcc_assert (REG_P (x
));
16256 /* Bit 1 is GT bit. */
16257 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
16259 /* Add one for shift count in rlinm for scc. */
16260 fprintf (file
, "%d", i
+ 1);
16264 /* X is a CR register. Print the number of the EQ bit of the CR */
16265 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16266 output_operand_lossage ("invalid %%E value");
16268 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
16272 /* X is a CR register. Print the shift count needed to move it
16273 to the high-order four bits. */
16274 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16275 output_operand_lossage ("invalid %%f value");
16277 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
16281 /* Similar, but print the count for the rotate in the opposite
16283 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16284 output_operand_lossage ("invalid %%F value");
16286 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
16290 /* X is a constant integer. If it is negative, print "m",
16291 otherwise print "z". This is to make an aze or ame insn. */
16292 if (GET_CODE (x
) != CONST_INT
)
16293 output_operand_lossage ("invalid %%G value");
16294 else if (INTVAL (x
) >= 0)
16301 /* If constant, output low-order five bits. Otherwise, write
16304 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
16306 print_operand (file
, x
, 0);
16310 /* If constant, output low-order six bits. Otherwise, write
16313 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
16315 print_operand (file
, x
, 0);
16319 /* Print `i' if this is a constant, else nothing. */
16325 /* Write the bit number in CCR for jump. */
16326 i
= ccr_bit (x
, 0);
16328 output_operand_lossage ("invalid %%j code");
16330 fprintf (file
, "%d", i
);
16334 /* Similar, but add one for shift count in rlinm for scc and pass
16335 scc flag to `ccr_bit'. */
16336 i
= ccr_bit (x
, 1);
16338 output_operand_lossage ("invalid %%J code");
16340 /* If we want bit 31, write a shift count of zero, not 32. */
16341 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
16345 /* X must be a constant. Write the 1's complement of the
16348 output_operand_lossage ("invalid %%k value");
16350 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
16354 /* X must be a symbolic constant on ELF. Write an
16355 expression suitable for an 'addi' that adds in the low 16
16356 bits of the MEM. */
16357 if (GET_CODE (x
) == CONST
)
16359 if (GET_CODE (XEXP (x
, 0)) != PLUS
16360 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
16361 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
16362 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
16363 output_operand_lossage ("invalid %%K value");
16365 print_operand_address (file
, x
);
16366 fputs ("@l", file
);
16369 /* %l is output_asm_label. */
16372 /* Write second word of DImode or DFmode reference. Works on register
16373 or non-indexed memory only. */
16375 fputs (reg_names
[REGNO (x
) + 1], file
);
16376 else if (MEM_P (x
))
16378 /* Handle possible auto-increment. Since it is pre-increment and
16379 we have already done it, we can just use an offset of word. */
16380 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
16381 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16382 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
16384 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16385 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
16388 output_address (XEXP (adjust_address_nv (x
, SImode
,
16392 if (small_data_operand (x
, GET_MODE (x
)))
16393 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16394 reg_names
[SMALL_DATA_REG
]);
16399 /* MB value for a mask operand. */
16400 if (! mask_operand (x
, SImode
))
16401 output_operand_lossage ("invalid %%m value");
16403 fprintf (file
, "%d", extract_MB (x
));
16407 /* ME value for a mask operand. */
16408 if (! mask_operand (x
, SImode
))
16409 output_operand_lossage ("invalid %%M value");
16411 fprintf (file
, "%d", extract_ME (x
));
16414 /* %n outputs the negative of its operand. */
16417 /* Write the number of elements in the vector times 4. */
16418 if (GET_CODE (x
) != PARALLEL
)
16419 output_operand_lossage ("invalid %%N value");
16421 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
16425 /* Similar, but subtract 1 first. */
16426 if (GET_CODE (x
) != PARALLEL
)
16427 output_operand_lossage ("invalid %%O value");
16429 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
16433 /* X is a CONST_INT that is a power of two. Output the logarithm. */
16436 || (i
= exact_log2 (INTVAL (x
))) < 0)
16437 output_operand_lossage ("invalid %%p value");
16439 fprintf (file
, "%d", i
);
16443 /* The operand must be an indirect memory reference. The result
16444 is the register name. */
16445 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
16446 || REGNO (XEXP (x
, 0)) >= 32)
16447 output_operand_lossage ("invalid %%P value");
16449 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
16453 /* This outputs the logical code corresponding to a boolean
16454 expression. The expression may have one or both operands
16455 negated (if one, only the first one). For condition register
16456 logical operations, it will also treat the negated
16457 CR codes as NOTs, but not handle NOTs of them. */
16459 const char *const *t
= 0;
16461 enum rtx_code code
= GET_CODE (x
);
16462 static const char * const tbl
[3][3] = {
16463 { "and", "andc", "nor" },
16464 { "or", "orc", "nand" },
16465 { "xor", "eqv", "xor" } };
16469 else if (code
== IOR
)
16471 else if (code
== XOR
)
16474 output_operand_lossage ("invalid %%q value");
16476 if (GET_CODE (XEXP (x
, 0)) != NOT
)
16480 if (GET_CODE (XEXP (x
, 1)) == NOT
)
16491 if (! TARGET_MFCRF
)
16497 /* X is a CR register. Print the mask for `mtcrf'. */
16498 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16499 output_operand_lossage ("invalid %%R value");
16501 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
16505 /* Low 5 bits of 32 - value */
16507 output_operand_lossage ("invalid %%s value");
16509 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
16513 /* PowerPC64 mask position. All 0's is excluded.
16514 CONST_INT 32-bit mask is considered sign-extended so any
16515 transition must occur within the CONST_INT, not on the boundary. */
16516 if (! mask64_operand (x
, DImode
))
16517 output_operand_lossage ("invalid %%S value");
16521 if (uval
& 1) /* Clear Left */
16523 #if HOST_BITS_PER_WIDE_INT > 64
16524 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
16528 else /* Clear Right */
16531 #if HOST_BITS_PER_WIDE_INT > 64
16532 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
16538 gcc_assert (i
>= 0);
16539 fprintf (file
, "%d", i
);
16543 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
16544 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
16546 /* Bit 3 is OV bit. */
16547 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
16549 /* If we want bit 31, write a shift count of zero, not 32. */
16550 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
16554 /* Print the symbolic name of a branch target register. */
16555 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
16556 && REGNO (x
) != CTR_REGNO
))
16557 output_operand_lossage ("invalid %%T value");
16558 else if (REGNO (x
) == LR_REGNO
)
16559 fputs ("lr", file
);
16561 fputs ("ctr", file
);
16565 /* High-order 16 bits of constant for use in unsigned operand. */
16567 output_operand_lossage ("invalid %%u value");
16569 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
16570 (INTVAL (x
) >> 16) & 0xffff);
16574 /* High-order 16 bits of constant for use in signed operand. */
16576 output_operand_lossage ("invalid %%v value");
16578 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
16579 (INTVAL (x
) >> 16) & 0xffff);
16583 /* Print `u' if this has an auto-increment or auto-decrement. */
16585 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
16586 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
16587 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
16592 /* Print the trap code for this operand. */
16593 switch (GET_CODE (x
))
16596 fputs ("eq", file
); /* 4 */
16599 fputs ("ne", file
); /* 24 */
16602 fputs ("lt", file
); /* 16 */
16605 fputs ("le", file
); /* 20 */
16608 fputs ("gt", file
); /* 8 */
16611 fputs ("ge", file
); /* 12 */
16614 fputs ("llt", file
); /* 2 */
16617 fputs ("lle", file
); /* 6 */
16620 fputs ("lgt", file
); /* 1 */
16623 fputs ("lge", file
); /* 5 */
16626 gcc_unreachable ();
16631 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
16634 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
16635 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
16637 print_operand (file
, x
, 0);
16641 /* MB value for a PowerPC64 rldic operand. */
16642 i
= clz_hwi (INTVAL (x
));
16644 fprintf (file
, "%d", i
);
16648 /* X is a FPR or Altivec register used in a VSX context. */
16649 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
16650 output_operand_lossage ("invalid %%x value");
16653 int reg
= REGNO (x
);
16654 int vsx_reg
= (FP_REGNO_P (reg
)
16656 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
16658 #ifdef TARGET_REGNAMES
16659 if (TARGET_REGNAMES
)
16660 fprintf (file
, "%%vs%d", vsx_reg
);
16663 fprintf (file
, "%d", vsx_reg
);
16669 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
16670 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
16671 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
16676 /* Like 'L', for third word of TImode/PTImode */
16678 fputs (reg_names
[REGNO (x
) + 2], file
);
16679 else if (MEM_P (x
))
16681 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
16682 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16683 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
16684 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16685 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
16687 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
16688 if (small_data_operand (x
, GET_MODE (x
)))
16689 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16690 reg_names
[SMALL_DATA_REG
]);
16695 /* X is a SYMBOL_REF. Write out the name preceded by a
16696 period and without any trailing data in brackets. Used for function
16697 names. If we are configured for System V (or the embedded ABI) on
16698 the PowerPC, do not emit the period, since those systems do not use
16699 TOCs and the like. */
16700 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
16702 /* For macho, check to see if we need a stub. */
16705 const char *name
= XSTR (x
, 0);
16707 if (darwin_emit_branch_islands
16708 && MACHOPIC_INDIRECT
16709 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
16710 name
= machopic_indirection_name (x
, /*stub_p=*/true);
16712 assemble_name (file
, name
);
16714 else if (!DOT_SYMBOLS
)
16715 assemble_name (file
, XSTR (x
, 0));
16717 rs6000_output_function_entry (file
, XSTR (x
, 0));
16721 /* Like 'L', for last word of TImode/PTImode. */
16723 fputs (reg_names
[REGNO (x
) + 3], file
);
16724 else if (MEM_P (x
))
16726 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
16727 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16728 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
16729 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16730 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
16732 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
16733 if (small_data_operand (x
, GET_MODE (x
)))
16734 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16735 reg_names
[SMALL_DATA_REG
]);
16739 /* Print AltiVec or SPE memory operand. */
16744 gcc_assert (MEM_P (x
));
16748 /* Ugly hack because %y is overloaded. */
16749 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
16750 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
16751 || GET_MODE (x
) == TFmode
16752 || GET_MODE (x
) == TImode
16753 || GET_MODE (x
) == PTImode
))
16755 /* Handle [reg]. */
16758 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
16761 /* Handle [reg+UIMM]. */
16762 else if (GET_CODE (tmp
) == PLUS
&&
16763 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
16767 gcc_assert (REG_P (XEXP (tmp
, 0)));
16769 x
= INTVAL (XEXP (tmp
, 1));
16770 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
16774 /* Fall through. Must be [reg+reg]. */
16776 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
16777 && GET_CODE (tmp
) == AND
16778 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
16779 && INTVAL (XEXP (tmp
, 1)) == -16)
16780 tmp
= XEXP (tmp
, 0);
16781 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
16782 && GET_CODE (tmp
) == PRE_MODIFY
)
16783 tmp
= XEXP (tmp
, 1);
16785 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
16788 if (!GET_CODE (tmp
) == PLUS
16789 || !REG_P (XEXP (tmp
, 0))
16790 || !REG_P (XEXP (tmp
, 1)))
16792 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
16796 if (REGNO (XEXP (tmp
, 0)) == 0)
16797 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
16798 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
16800 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
16801 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
16808 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
16809 else if (MEM_P (x
))
16811 /* We need to handle PRE_INC and PRE_DEC here, since we need to
16812 know the width from the mode. */
16813 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
16814 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
16815 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
16816 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16817 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
16818 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
16819 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16820 output_address (XEXP (XEXP (x
, 0), 1));
16822 output_address (XEXP (x
, 0));
16826 if (toc_relative_expr_p (x
, false))
16827 /* This hack along with a corresponding hack in
16828 rs6000_output_addr_const_extra arranges to output addends
16829 where the assembler expects to find them. eg.
16830 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
16831 without this hack would be output as "x@toc+4". We
16833 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
16835 output_addr_const (file
, x
);
16840 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
16844 output_operand_lossage ("invalid %%xn code");
16848 /* Print the address of an operand. */
16851 print_operand_address (FILE *file
, rtx x
)
16854 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
16855 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
16856 || GET_CODE (x
) == LABEL_REF
)
16858 output_addr_const (file
, x
);
16859 if (small_data_operand (x
, GET_MODE (x
)))
16860 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16861 reg_names
[SMALL_DATA_REG
]);
16863 gcc_assert (!TARGET_TOC
);
16865 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
16866 && REG_P (XEXP (x
, 1)))
16868 if (REGNO (XEXP (x
, 0)) == 0)
16869 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
16870 reg_names
[ REGNO (XEXP (x
, 0)) ]);
16872 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
16873 reg_names
[ REGNO (XEXP (x
, 1)) ]);
16875 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
16876 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
16877 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
16878 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
16880 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
16881 && CONSTANT_P (XEXP (x
, 1)))
16883 fprintf (file
, "lo16(");
16884 output_addr_const (file
, XEXP (x
, 1));
16885 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
16889 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
16890 && CONSTANT_P (XEXP (x
, 1)))
16892 output_addr_const (file
, XEXP (x
, 1));
16893 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
16896 else if (toc_relative_expr_p (x
, false))
16898 /* This hack along with a corresponding hack in
16899 rs6000_output_addr_const_extra arranges to output addends
16900 where the assembler expects to find them. eg.
16902 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
16903 without this hack would be output as "x@toc+8@l(9)". We
16904 want "x+8@toc@l(9)". */
16905 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
16906 if (GET_CODE (x
) == LO_SUM
)
16907 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
16909 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
16912 gcc_unreachable ();
16915 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
16918 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
16920 if (GET_CODE (x
) == UNSPEC
)
16921 switch (XINT (x
, 1))
16923 case UNSPEC_TOCREL
:
16924 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
16925 && REG_P (XVECEXP (x
, 0, 1))
16926 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
16927 output_addr_const (file
, XVECEXP (x
, 0, 0));
16928 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
16930 if (INTVAL (tocrel_offset
) >= 0)
16931 fprintf (file
, "+");
16932 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
16934 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
16937 assemble_name (file
, toc_label_name
);
16939 else if (TARGET_ELF
)
16940 fputs ("@toc", file
);
16944 case UNSPEC_MACHOPIC_OFFSET
:
16945 output_addr_const (file
, XVECEXP (x
, 0, 0));
16947 machopic_output_function_base_name (file
);
16954 /* Target hook for assembling integer objects. The PowerPC version has
16955 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
16956 is defined. It also needs to handle DI-mode objects on 64-bit
16960 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
16962 #ifdef RELOCATABLE_NEEDS_FIXUP
16963 /* Special handling for SI values. */
16964 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
16966 static int recurse
= 0;
16968 /* For -mrelocatable, we mark all addresses that need to be fixed up in
16969 the .fixup section. Since the TOC section is already relocated, we
16970 don't need to mark it here. We used to skip the text section, but it
16971 should never be valid for relocated addresses to be placed in the text
16973 if (TARGET_RELOCATABLE
16974 && in_section
!= toc_section
16976 && GET_CODE (x
) != CONST_INT
16977 && GET_CODE (x
) != CONST_DOUBLE
16983 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
16985 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
16986 fprintf (asm_out_file
, "\t.long\t(");
16987 output_addr_const (asm_out_file
, x
);
16988 fprintf (asm_out_file
, ")@fixup\n");
16989 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
16990 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
16991 fprintf (asm_out_file
, "\t.long\t");
16992 assemble_name (asm_out_file
, buf
);
16993 fprintf (asm_out_file
, "\n\t.previous\n");
16997 /* Remove initial .'s to turn a -mcall-aixdesc function
16998 address into the address of the descriptor, not the function
17000 else if (GET_CODE (x
) == SYMBOL_REF
17001 && XSTR (x
, 0)[0] == '.'
17002 && DEFAULT_ABI
== ABI_AIX
)
17004 const char *name
= XSTR (x
, 0);
17005 while (*name
== '.')
17008 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
17012 #endif /* RELOCATABLE_NEEDS_FIXUP */
17013 return default_assemble_integer (x
, size
, aligned_p
);
17016 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
17017 /* Emit an assembler directive to set symbol visibility for DECL to
17018 VISIBILITY_TYPE. */
17021 rs6000_assemble_visibility (tree decl
, int vis
)
17026 /* Functions need to have their entry point symbol visibility set as
17027 well as their descriptor symbol visibility. */
17028 if (DEFAULT_ABI
== ABI_AIX
17030 && TREE_CODE (decl
) == FUNCTION_DECL
)
17032 static const char * const visibility_types
[] = {
17033 NULL
, "internal", "hidden", "protected"
17036 const char *name
, *type
;
17038 name
= ((* targetm
.strip_name_encoding
)
17039 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
17040 type
= visibility_types
[vis
];
17042 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
17043 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
17046 default_assemble_visibility (decl
, vis
);
17051 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
17053 /* Reversal of FP compares takes care -- an ordered compare
17054 becomes an unordered compare and vice versa. */
17055 if (mode
== CCFPmode
17056 && (!flag_finite_math_only
17057 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
17058 || code
== UNEQ
|| code
== LTGT
))
17059 return reverse_condition_maybe_unordered (code
);
17061 return reverse_condition (code
);
17064 /* Generate a compare for CODE. Return a brand-new rtx that
17065 represents the result of the compare. */
17068 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
17070 enum machine_mode comp_mode
;
17071 rtx compare_result
;
17072 enum rtx_code code
= GET_CODE (cmp
);
17073 rtx op0
= XEXP (cmp
, 0);
17074 rtx op1
= XEXP (cmp
, 1);
17076 if (FLOAT_MODE_P (mode
))
17077 comp_mode
= CCFPmode
;
17078 else if (code
== GTU
|| code
== LTU
17079 || code
== GEU
|| code
== LEU
)
17080 comp_mode
= CCUNSmode
;
17081 else if ((code
== EQ
|| code
== NE
)
17082 && unsigned_reg_p (op0
)
17083 && (unsigned_reg_p (op1
)
17084 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
17085 /* These are unsigned values, perhaps there will be a later
17086 ordering compare that can be shared with this one. */
17087 comp_mode
= CCUNSmode
;
17089 comp_mode
= CCmode
;
17091 /* If we have an unsigned compare, make sure we don't have a signed value as
17093 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
17094 && INTVAL (op1
) < 0)
17096 op0
= copy_rtx_if_shared (op0
);
17097 op1
= force_reg (GET_MODE (op0
), op1
);
17098 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
17101 /* First, the compare. */
17102 compare_result
= gen_reg_rtx (comp_mode
);
17104 /* E500 FP compare instructions on the GPRs. Yuck! */
17105 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
17106 && FLOAT_MODE_P (mode
))
17108 rtx cmp
, or_result
, compare_result2
;
17109 enum machine_mode op_mode
= GET_MODE (op0
);
17112 if (op_mode
== VOIDmode
)
17113 op_mode
= GET_MODE (op1
);
17115 /* First reverse the condition codes that aren't directly supported. */
17123 code
= reverse_condition_maybe_unordered (code
);
17136 gcc_unreachable ();
17139 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
17140 This explains the following mess. */
17148 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17149 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
17150 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
17154 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17155 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
17156 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
17160 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17161 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
17162 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
17166 gcc_unreachable ();
17175 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17176 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
17177 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
17181 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17182 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
17183 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
17187 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17188 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
17189 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
17193 gcc_unreachable ();
17202 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17203 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
17204 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
17208 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17209 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
17210 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
17214 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17215 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
17216 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
17220 gcc_unreachable ();
17225 gcc_unreachable ();
17228 /* Synthesize LE and GE from LT/GT || EQ. */
17229 if (code
== LE
|| code
== GE
)
17233 compare_result2
= gen_reg_rtx (CCFPmode
);
17239 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17240 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
17241 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
17245 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17246 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
17247 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
17251 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17252 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
17253 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
17257 gcc_unreachable ();
17262 /* OR them together. */
17263 or_result
= gen_reg_rtx (CCFPmode
);
17264 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
17266 compare_result
= or_result
;
17269 code
= reverse_p
? NE
: EQ
;
17275 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
17276 CLOBBERs to match cmptf_internal2 pattern. */
17277 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
17278 && GET_MODE (op0
) == TFmode
17279 && !TARGET_IEEEQUAD
17280 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
17281 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
17283 gen_rtx_SET (VOIDmode
,
17285 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
17286 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17287 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17288 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17289 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17290 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17291 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17292 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17293 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17294 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
17295 else if (GET_CODE (op1
) == UNSPEC
17296 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
17298 rtx op1b
= XVECEXP (op1
, 0, 0);
17299 comp_mode
= CCEQmode
;
17300 compare_result
= gen_reg_rtx (CCEQmode
);
17302 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
17304 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
17307 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
17308 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
17311 /* Some kinds of FP comparisons need an OR operation;
17312 under flag_finite_math_only we don't bother. */
17313 if (FLOAT_MODE_P (mode
)
17314 && !flag_finite_math_only
17315 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
17316 && (code
== LE
|| code
== GE
17317 || code
== UNEQ
|| code
== LTGT
17318 || code
== UNGT
|| code
== UNLT
))
17320 enum rtx_code or1
, or2
;
17321 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
17322 rtx or_result
= gen_reg_rtx (CCEQmode
);
17326 case LE
: or1
= LT
; or2
= EQ
; break;
17327 case GE
: or1
= GT
; or2
= EQ
; break;
17328 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
17329 case LTGT
: or1
= LT
; or2
= GT
; break;
17330 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
17331 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
17332 default: gcc_unreachable ();
17334 validate_condition_mode (or1
, comp_mode
);
17335 validate_condition_mode (or2
, comp_mode
);
17336 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
17337 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
17338 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
17339 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
17341 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
17343 compare_result
= or_result
;
17347 validate_condition_mode (code
, GET_MODE (compare_result
));
17349 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
17353 /* Emit the RTL for an sISEL pattern. */
17356 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
17358 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
17362 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
17365 enum machine_mode op_mode
;
17366 enum rtx_code cond_code
;
17367 rtx result
= operands
[0];
17369 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
17371 rs6000_emit_sISEL (mode
, operands
);
17375 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
17376 cond_code
= GET_CODE (condition_rtx
);
17378 if (FLOAT_MODE_P (mode
)
17379 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
17383 PUT_MODE (condition_rtx
, SImode
);
17384 t
= XEXP (condition_rtx
, 0);
17386 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
17388 if (cond_code
== NE
)
17389 emit_insn (gen_e500_flip_gt_bit (t
, t
));
17391 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
17395 if (cond_code
== NE
17396 || cond_code
== GE
|| cond_code
== LE
17397 || cond_code
== GEU
|| cond_code
== LEU
17398 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
17400 rtx not_result
= gen_reg_rtx (CCEQmode
);
17401 rtx not_op
, rev_cond_rtx
;
17402 enum machine_mode cc_mode
;
17404 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
17406 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
17407 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
17408 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
17409 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
17410 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
17413 op_mode
= GET_MODE (XEXP (operands
[1], 0));
17414 if (op_mode
== VOIDmode
)
17415 op_mode
= GET_MODE (XEXP (operands
[1], 1));
17417 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
17419 PUT_MODE (condition_rtx
, DImode
);
17420 convert_move (result
, condition_rtx
, 0);
17424 PUT_MODE (condition_rtx
, SImode
);
17425 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
17429 /* Emit a branch of kind CODE to location LOC. */
17432 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
17434 rtx condition_rtx
, loc_ref
;
17436 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
17437 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
17438 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
17439 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
17440 loc_ref
, pc_rtx
)));
17443 /* Return the string to output a conditional branch to LABEL, which is
17444 the operand template of the label, or NULL if the branch is really a
17445 conditional return.
17447 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
17448 condition code register and its mode specifies what kind of
17449 comparison we made.
17451 REVERSED is nonzero if we should reverse the sense of the comparison.
17453 INSN is the insn. */
17456 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
17458 static char string
[64];
17459 enum rtx_code code
= GET_CODE (op
);
17460 rtx cc_reg
= XEXP (op
, 0);
17461 enum machine_mode mode
= GET_MODE (cc_reg
);
17462 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
17463 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
17464 int really_reversed
= reversed
^ need_longbranch
;
17470 validate_condition_mode (code
, mode
);
17472 /* Work out which way this really branches. We could use
17473 reverse_condition_maybe_unordered here always but this
17474 makes the resulting assembler clearer. */
17475 if (really_reversed
)
17477 /* Reversal of FP compares takes care -- an ordered compare
17478 becomes an unordered compare and vice versa. */
17479 if (mode
== CCFPmode
)
17480 code
= reverse_condition_maybe_unordered (code
);
17482 code
= reverse_condition (code
);
17485 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
17487 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
17492 /* Opposite of GT. */
17501 gcc_unreachable ();
17507 /* Not all of these are actually distinct opcodes, but
17508 we distinguish them for clarity of the resulting assembler. */
17509 case NE
: case LTGT
:
17510 ccode
= "ne"; break;
17511 case EQ
: case UNEQ
:
17512 ccode
= "eq"; break;
17514 ccode
= "ge"; break;
17515 case GT
: case GTU
: case UNGT
:
17516 ccode
= "gt"; break;
17518 ccode
= "le"; break;
17519 case LT
: case LTU
: case UNLT
:
17520 ccode
= "lt"; break;
17521 case UNORDERED
: ccode
= "un"; break;
17522 case ORDERED
: ccode
= "nu"; break;
17523 case UNGE
: ccode
= "nl"; break;
17524 case UNLE
: ccode
= "ng"; break;
17526 gcc_unreachable ();
17529 /* Maybe we have a guess as to how likely the branch is. */
17531 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
17532 if (note
!= NULL_RTX
)
17534 /* PROB is the difference from 50%. */
17535 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
17537 /* Only hint for highly probable/improbable branches on newer
17538 cpus as static prediction overrides processor dynamic
17539 prediction. For older cpus we may as well always hint, but
17540 assume not taken for branches that are very close to 50% as a
17541 mispredicted taken branch is more expensive than a
17542 mispredicted not-taken branch. */
17543 if (rs6000_always_hint
17544 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
17545 && br_prob_note_reliable_p (note
)))
17547 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
17548 && ((prob
> 0) ^ need_longbranch
))
17556 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
17558 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
17560 /* We need to escape any '%' characters in the reg_names string.
17561 Assume they'd only be the first character.... */
17562 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
17564 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
17568 /* If the branch distance was too far, we may have to use an
17569 unconditional branch to go the distance. */
17570 if (need_longbranch
)
17571 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
17573 s
+= sprintf (s
, ",%s", label
);
17579 /* Return the string to flip the GT bit on a CR. */
17581 output_e500_flip_gt_bit (rtx dst
, rtx src
)
17583 static char string
[64];
17586 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
17587 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
17590 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
17591 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
17593 sprintf (string
, "crnot %d,%d", a
, b
);
17597 /* Return insn for VSX or Altivec comparisons. */
17600 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
17603 enum machine_mode mode
= GET_MODE (op0
);
17611 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
17621 mask
= gen_reg_rtx (mode
);
17622 emit_insn (gen_rtx_SET (VOIDmode
,
17624 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
17631 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
17632 DMODE is expected destination mode. This is a recursive function. */
17635 rs6000_emit_vector_compare (enum rtx_code rcode
,
17637 enum machine_mode dmode
)
17640 bool swap_operands
= false;
17641 bool try_again
= false;
17643 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
17644 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
17646 /* See if the comparison works as is. */
17647 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
17655 swap_operands
= true;
17660 swap_operands
= true;
17668 /* Invert condition and try again.
17669 e.g., A != B becomes ~(A==B). */
17671 enum rtx_code rev_code
;
17672 enum insn_code nor_code
;
17675 rev_code
= reverse_condition_maybe_unordered (rcode
);
17676 if (rev_code
== UNKNOWN
)
17679 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
17680 if (nor_code
== CODE_FOR_nothing
)
17683 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
17687 mask
= gen_reg_rtx (dmode
);
17688 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
17696 /* Try GT/GTU/LT/LTU OR EQ */
17699 enum insn_code ior_code
;
17700 enum rtx_code new_code
;
17721 gcc_unreachable ();
17724 ior_code
= optab_handler (ior_optab
, dmode
);
17725 if (ior_code
== CODE_FOR_nothing
)
17728 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
17732 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
17736 mask
= gen_reg_rtx (dmode
);
17737 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
17755 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
17760 /* You only get two chances. */
17764 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
17765 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
17766 operands for the relation operation COND. */
17769 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
17770 rtx cond
, rtx cc_op0
, rtx cc_op1
)
17772 enum machine_mode dest_mode
= GET_MODE (dest
);
17773 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
17774 enum rtx_code rcode
= GET_CODE (cond
);
17775 enum machine_mode cc_mode
= CCmode
;
17779 bool invert_move
= false;
17781 if (VECTOR_UNIT_NONE_P (dest_mode
))
17784 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
17785 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
17789 /* Swap operands if we can, and fall back to doing the operation as
17790 specified, and doing a NOR to invert the test. */
17796 /* Invert condition and try again.
17797 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
17798 invert_move
= true;
17799 rcode
= reverse_condition_maybe_unordered (rcode
);
17800 if (rcode
== UNKNOWN
)
17804 /* Mark unsigned tests with CCUNSmode. */
17809 cc_mode
= CCUNSmode
;
17816 /* Get the vector mask for the given relational operations. */
17817 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
17825 op_true
= op_false
;
17829 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
17830 CONST0_RTX (dest_mode
));
17831 emit_insn (gen_rtx_SET (VOIDmode
,
17833 gen_rtx_IF_THEN_ELSE (dest_mode
,
17840 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
17841 operands of the last comparison is nonzero/true, FALSE_COND if it
17842 is zero/false. Return 0 if the hardware has no such operation. */
17845 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
17847 enum rtx_code code
= GET_CODE (op
);
17848 rtx op0
= XEXP (op
, 0);
17849 rtx op1
= XEXP (op
, 1);
17850 REAL_VALUE_TYPE c1
;
17851 enum machine_mode compare_mode
= GET_MODE (op0
);
17852 enum machine_mode result_mode
= GET_MODE (dest
);
17854 bool is_against_zero
;
17856 /* These modes should always match. */
17857 if (GET_MODE (op1
) != compare_mode
17858 /* In the isel case however, we can use a compare immediate, so
17859 op1 may be a small constant. */
17860 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
17862 if (GET_MODE (true_cond
) != result_mode
)
17864 if (GET_MODE (false_cond
) != result_mode
)
17867 /* Don't allow using floating point comparisons for integer results for
17869 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
17872 /* First, work out if the hardware can do this at all, or
17873 if it's too slow.... */
17874 if (!FLOAT_MODE_P (compare_mode
))
17877 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
17880 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
17881 && SCALAR_FLOAT_MODE_P (compare_mode
))
17884 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
17886 /* A floating-point subtract might overflow, underflow, or produce
17887 an inexact result, thus changing the floating-point flags, so it
17888 can't be generated if we care about that. It's safe if one side
17889 of the construct is zero, since then no subtract will be
17891 if (SCALAR_FLOAT_MODE_P (compare_mode
)
17892 && flag_trapping_math
&& ! is_against_zero
)
17895 /* Eliminate half of the comparisons by switching operands, this
17896 makes the remaining code simpler. */
17897 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
17898 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
17900 code
= reverse_condition_maybe_unordered (code
);
17902 true_cond
= false_cond
;
17906 /* UNEQ and LTGT take four instructions for a comparison with zero,
17907 it'll probably be faster to use a branch here too. */
17908 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
17911 if (GET_CODE (op1
) == CONST_DOUBLE
)
17912 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
17914 /* We're going to try to implement comparisons by performing
17915 a subtract, then comparing against zero. Unfortunately,
17916 Inf - Inf is NaN which is not zero, and so if we don't
17917 know that the operand is finite and the comparison
17918 would treat EQ different to UNORDERED, we can't do it. */
17919 if (HONOR_INFINITIES (compare_mode
)
17920 && code
!= GT
&& code
!= UNGE
17921 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
17922 /* Constructs of the form (a OP b ? a : b) are safe. */
17923 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
17924 || (! rtx_equal_p (op0
, true_cond
)
17925 && ! rtx_equal_p (op1
, true_cond
))))
17928 /* At this point we know we can use fsel. */
17930 /* Reduce the comparison to a comparison against zero. */
17931 if (! is_against_zero
)
17933 temp
= gen_reg_rtx (compare_mode
);
17934 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
17935 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
17937 op1
= CONST0_RTX (compare_mode
);
17940 /* If we don't care about NaNs we can reduce some of the comparisons
17941 down to faster ones. */
17942 if (! HONOR_NANS (compare_mode
))
17948 true_cond
= false_cond
;
17961 /* Now, reduce everything down to a GE. */
17968 temp
= gen_reg_rtx (compare_mode
);
17969 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
17974 temp
= gen_reg_rtx (compare_mode
);
17975 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
17980 temp
= gen_reg_rtx (compare_mode
);
17981 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
17982 gen_rtx_NEG (compare_mode
,
17983 gen_rtx_ABS (compare_mode
, op0
))));
17988 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
17989 temp
= gen_reg_rtx (result_mode
);
17990 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
17991 gen_rtx_IF_THEN_ELSE (result_mode
,
17992 gen_rtx_GE (VOIDmode
,
17994 true_cond
, false_cond
)));
17995 false_cond
= true_cond
;
17998 temp
= gen_reg_rtx (compare_mode
);
17999 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18004 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
18005 temp
= gen_reg_rtx (result_mode
);
18006 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18007 gen_rtx_IF_THEN_ELSE (result_mode
,
18008 gen_rtx_GE (VOIDmode
,
18010 true_cond
, false_cond
)));
18011 true_cond
= false_cond
;
18014 temp
= gen_reg_rtx (compare_mode
);
18015 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18020 gcc_unreachable ();
18023 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
18024 gen_rtx_IF_THEN_ELSE (result_mode
,
18025 gen_rtx_GE (VOIDmode
,
18027 true_cond
, false_cond
)));
18031 /* Same as above, but for ints (isel). */
18034 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18036 rtx condition_rtx
, cr
;
18037 enum machine_mode mode
= GET_MODE (dest
);
18038 enum rtx_code cond_code
;
18039 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
18042 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
18045 /* We still have to do the compare, because isel doesn't do a
18046 compare, it just looks at the CRx bits set by a previous compare
18048 condition_rtx
= rs6000_generate_compare (op
, mode
);
18049 cond_code
= GET_CODE (condition_rtx
);
18050 cr
= XEXP (condition_rtx
, 0);
18051 signedp
= GET_MODE (cr
) == CCmode
;
18053 isel_func
= (mode
== SImode
18054 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
18055 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
18059 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
18060 /* isel handles these directly. */
18064 /* We need to swap the sense of the comparison. */
18067 true_cond
= false_cond
;
18069 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
18074 false_cond
= force_reg (mode
, false_cond
);
18075 if (true_cond
!= const0_rtx
)
18076 true_cond
= force_reg (mode
, true_cond
);
18078 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
18084 output_isel (rtx
*operands
)
18086 enum rtx_code code
;
18088 code
= GET_CODE (operands
[1]);
18090 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
18092 gcc_assert (GET_CODE (operands
[2]) == REG
18093 && GET_CODE (operands
[3]) == REG
);
18094 PUT_CODE (operands
[1], reverse_condition (code
));
18095 return "isel %0,%3,%2,%j1";
18098 return "isel %0,%2,%3,%j1";
18102 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
18104 enum machine_mode mode
= GET_MODE (op0
);
18108 /* VSX/altivec have direct min/max insns. */
18109 if ((code
== SMAX
|| code
== SMIN
)
18110 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
18111 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
18113 emit_insn (gen_rtx_SET (VOIDmode
,
18115 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
18119 if (code
== SMAX
|| code
== SMIN
)
18124 if (code
== SMAX
|| code
== UMAX
)
18125 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
18126 op0
, op1
, mode
, 0);
18128 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
18129 op1
, op0
, mode
, 0);
18130 gcc_assert (target
);
18131 if (target
!= dest
)
18132 emit_move_insn (dest
, target
);
18135 /* A subroutine of the atomic operation splitters. Jump to LABEL if
18136 COND is true. Mark the jump as unlikely to be taken. */
18139 emit_unlikely_jump (rtx cond
, rtx label
)
18141 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
18144 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
18145 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
18146 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
18149 /* A subroutine of the atomic operation splitters. Emit a load-locked
18150 instruction in MODE. For QI/HImode, possibly use a pattern than includes
18151 the zero_extend operation. */
18154 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
18156 rtx (*fn
) (rtx
, rtx
) = NULL
;
18161 fn
= gen_load_lockedqi
;
18164 fn
= gen_load_lockedhi
;
18167 if (GET_MODE (mem
) == QImode
)
18168 fn
= gen_load_lockedqi_si
;
18169 else if (GET_MODE (mem
) == HImode
)
18170 fn
= gen_load_lockedhi_si
;
18172 fn
= gen_load_lockedsi
;
18175 fn
= gen_load_lockeddi
;
18178 fn
= gen_load_lockedti
;
18181 gcc_unreachable ();
18183 emit_insn (fn (reg
, mem
));
18186 /* A subroutine of the atomic operation splitters. Emit a store-conditional
18187 instruction in MODE. */
18190 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
18192 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
18197 fn
= gen_store_conditionalqi
;
18200 fn
= gen_store_conditionalhi
;
18203 fn
= gen_store_conditionalsi
;
18206 fn
= gen_store_conditionaldi
;
18209 fn
= gen_store_conditionalti
;
18212 gcc_unreachable ();
18215 /* Emit sync before stwcx. to address PPC405 Erratum. */
18216 if (PPC405_ERRATUM77
)
18217 emit_insn (gen_hwsync ());
18219 emit_insn (fn (res
, mem
, val
));
18222 /* Expand barriers before and after a load_locked/store_cond sequence. */
18225 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
18227 rtx addr
= XEXP (mem
, 0);
18228 int strict_p
= (reload_in_progress
|| reload_completed
);
18230 if (!legitimate_indirect_address_p (addr
, strict_p
)
18231 && !legitimate_indexed_address_p (addr
, strict_p
))
18233 addr
= force_reg (Pmode
, addr
);
18234 mem
= replace_equiv_address_nv (mem
, addr
);
18239 case MEMMODEL_RELAXED
:
18240 case MEMMODEL_CONSUME
:
18241 case MEMMODEL_ACQUIRE
:
18243 case MEMMODEL_RELEASE
:
18244 case MEMMODEL_ACQ_REL
:
18245 emit_insn (gen_lwsync ());
18247 case MEMMODEL_SEQ_CST
:
18248 emit_insn (gen_hwsync ());
18251 gcc_unreachable ();
18257 rs6000_post_atomic_barrier (enum memmodel model
)
18261 case MEMMODEL_RELAXED
:
18262 case MEMMODEL_CONSUME
:
18263 case MEMMODEL_RELEASE
:
18265 case MEMMODEL_ACQUIRE
:
18266 case MEMMODEL_ACQ_REL
:
18267 case MEMMODEL_SEQ_CST
:
18268 emit_insn (gen_isync ());
18271 gcc_unreachable ();
18275 /* A subroutine of the various atomic expanders. For sub-word operations,
18276 we must adjust things to operate on SImode. Given the original MEM,
18277 return a new aligned memory. Also build and return the quantities by
18278 which to shift and mask. */
18281 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
18283 rtx addr
, align
, shift
, mask
, mem
;
18284 HOST_WIDE_INT shift_mask
;
18285 enum machine_mode mode
= GET_MODE (orig_mem
);
18287 /* For smaller modes, we have to implement this via SImode. */
18288 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
18290 addr
= XEXP (orig_mem
, 0);
18291 addr
= force_reg (GET_MODE (addr
), addr
);
18293 /* Aligned memory containing subword. Generate a new memory. We
18294 do not want any of the existing MEM_ATTR data, as we're now
18295 accessing memory outside the original object. */
18296 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
18297 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18298 mem
= gen_rtx_MEM (SImode
, align
);
18299 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
18300 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
18301 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
18303 /* Shift amount for subword relative to aligned word. */
18304 shift
= gen_reg_rtx (SImode
);
18305 addr
= gen_lowpart (SImode
, addr
);
18306 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
18307 if (WORDS_BIG_ENDIAN
)
18308 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
18309 shift
, 1, OPTAB_LIB_WIDEN
);
18312 /* Mask for insertion. */
18313 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
18314 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18320 /* A subroutine of the various atomic expanders. For sub-word operands,
18321 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
18324 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
18328 x
= gen_reg_rtx (SImode
);
18329 emit_insn (gen_rtx_SET (VOIDmode
, x
,
18330 gen_rtx_AND (SImode
,
18331 gen_rtx_NOT (SImode
, mask
),
18334 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
18339 /* A subroutine of the various atomic expanders. For sub-word operands,
18340 extract WIDE to NARROW via SHIFT. */
18343 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
18345 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
18346 wide
, 1, OPTAB_LIB_WIDEN
);
18347 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
18350 /* Expand an atomic compare and swap operation. */
18353 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
18355 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
18356 rtx label1
, label2
, x
, mask
, shift
;
18357 enum machine_mode mode
, orig_mode
;
18358 enum memmodel mod_s
, mod_f
;
18361 boolval
= operands
[0];
18362 retval
= operands
[1];
18364 oldval
= operands
[3];
18365 newval
= operands
[4];
18366 is_weak
= (INTVAL (operands
[5]) != 0);
18367 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
18368 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
18369 orig_mode
= mode
= GET_MODE (mem
);
18371 mask
= shift
= NULL_RTX
;
18372 if (mode
== QImode
|| mode
== HImode
)
18374 /* Before power8, we didn't have access to lbarx/lharx, so generate a
18375 lwarx and shift/mask operations. With power8, we need to do the
18376 comparison in SImode, but the store is still done in QI/HImode. */
18377 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
18379 if (!TARGET_SYNC_HI_QI
)
18381 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
18383 /* Shift and mask OLDVAL into position with the word. */
18384 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
18385 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18387 /* Shift and mask NEWVAL into position within the word. */
18388 newval
= convert_modes (SImode
, mode
, newval
, 1);
18389 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
18390 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18393 /* Prepare to adjust the return value. */
18394 retval
= gen_reg_rtx (SImode
);
18397 else if (reg_overlap_mentioned_p (retval
, oldval
))
18398 oldval
= copy_to_reg (oldval
);
18400 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
18405 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
18406 emit_label (XEXP (label1
, 0));
18408 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
18410 emit_load_locked (mode
, retval
, mem
);
18415 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
18416 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18419 cond
= gen_reg_rtx (CCmode
);
18420 /* If we have TImode, synthesize a comparison. */
18421 if (mode
!= TImode
)
18422 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
18425 rtx xor1_result
= gen_reg_rtx (DImode
);
18426 rtx xor2_result
= gen_reg_rtx (DImode
);
18427 rtx or_result
= gen_reg_rtx (DImode
);
18428 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
18429 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
18430 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
18431 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
18433 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
18434 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
18435 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
18436 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
18439 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
18441 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18442 emit_unlikely_jump (x
, label2
);
18446 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
18448 emit_store_conditional (orig_mode
, cond
, mem
, x
);
18452 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18453 emit_unlikely_jump (x
, label1
);
18456 if (mod_f
!= MEMMODEL_RELAXED
)
18457 emit_label (XEXP (label2
, 0));
18459 rs6000_post_atomic_barrier (mod_s
);
18461 if (mod_f
== MEMMODEL_RELAXED
)
18462 emit_label (XEXP (label2
, 0));
18465 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
18466 else if (mode
!= GET_MODE (operands
[1]))
18467 convert_move (operands
[1], retval
, 1);
18469 /* In all cases, CR0 contains EQ on success, and NE on failure. */
18470 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
18471 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
18474 /* Expand an atomic exchange operation. */
18477 rs6000_expand_atomic_exchange (rtx operands
[])
18479 rtx retval
, mem
, val
, cond
;
18480 enum machine_mode mode
;
18481 enum memmodel model
;
18482 rtx label
, x
, mask
, shift
;
18484 retval
= operands
[0];
18487 model
= (enum memmodel
) INTVAL (operands
[3]);
18488 mode
= GET_MODE (mem
);
18490 mask
= shift
= NULL_RTX
;
18491 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
18493 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
18495 /* Shift and mask VAL into position with the word. */
18496 val
= convert_modes (SImode
, mode
, val
, 1);
18497 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
18498 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18500 /* Prepare to adjust the return value. */
18501 retval
= gen_reg_rtx (SImode
);
18505 mem
= rs6000_pre_atomic_barrier (mem
, model
);
18507 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
18508 emit_label (XEXP (label
, 0));
18510 emit_load_locked (mode
, retval
, mem
);
18514 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
18516 cond
= gen_reg_rtx (CCmode
);
18517 emit_store_conditional (mode
, cond
, mem
, x
);
18519 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18520 emit_unlikely_jump (x
, label
);
18522 rs6000_post_atomic_barrier (model
);
18525 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
18528 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
18529 to perform. MEM is the memory on which to operate. VAL is the second
18530 operand of the binary operator. BEFORE and AFTER are optional locations to
18531 return the value of MEM either before of after the operation. MODEL_RTX
18532 is a CONST_INT containing the memory model to use. */
18535 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
18536 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
18538 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
18539 enum machine_mode mode
= GET_MODE (mem
);
18540 enum machine_mode store_mode
= mode
;
18541 rtx label
, x
, cond
, mask
, shift
;
18542 rtx before
= orig_before
, after
= orig_after
;
18544 mask
= shift
= NULL_RTX
;
18545 /* On power8, we want to use SImode for the operation. On previous systems,
18546 use the operation in a subword and shift/mask to get the proper byte or
18548 if (mode
== QImode
|| mode
== HImode
)
18550 if (TARGET_SYNC_HI_QI
)
18552 val
= convert_modes (SImode
, mode
, val
, 1);
18554 /* Prepare to adjust the return value. */
18555 before
= gen_reg_rtx (SImode
);
18557 after
= gen_reg_rtx (SImode
);
18562 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
18564 /* Shift and mask VAL into position with the word. */
18565 val
= convert_modes (SImode
, mode
, val
, 1);
18566 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
18567 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18573 /* We've already zero-extended VAL. That is sufficient to
18574 make certain that it does not affect other bits. */
18579 /* If we make certain that all of the other bits in VAL are
18580 set, that will be sufficient to not affect other bits. */
18581 x
= gen_rtx_NOT (SImode
, mask
);
18582 x
= gen_rtx_IOR (SImode
, x
, val
);
18583 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
18590 /* These will all affect bits outside the field and need
18591 adjustment via MASK within the loop. */
18595 gcc_unreachable ();
18598 /* Prepare to adjust the return value. */
18599 before
= gen_reg_rtx (SImode
);
18601 after
= gen_reg_rtx (SImode
);
18602 store_mode
= mode
= SImode
;
18606 mem
= rs6000_pre_atomic_barrier (mem
, model
);
18608 label
= gen_label_rtx ();
18609 emit_label (label
);
18610 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
18612 if (before
== NULL_RTX
)
18613 before
= gen_reg_rtx (mode
);
18615 emit_load_locked (mode
, before
, mem
);
18619 x
= expand_simple_binop (mode
, AND
, before
, val
,
18620 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18621 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
18625 after
= expand_simple_binop (mode
, code
, before
, val
,
18626 after
, 1, OPTAB_LIB_WIDEN
);
18632 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
18633 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18634 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
18636 else if (store_mode
!= mode
)
18637 x
= convert_modes (store_mode
, mode
, x
, 1);
18639 cond
= gen_reg_rtx (CCmode
);
18640 emit_store_conditional (store_mode
, cond
, mem
, x
);
18642 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18643 emit_unlikely_jump (x
, label
);
18645 rs6000_post_atomic_barrier (model
);
18649 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
18650 then do the calcuations in a SImode register. */
18652 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
18654 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
18656 else if (store_mode
!= mode
)
18658 /* QImode/HImode on machines with lbarx/lharx where we do the native
18659 operation and then do the calcuations in a SImode register. */
18661 convert_move (orig_before
, before
, 1);
18663 convert_move (orig_after
, after
, 1);
18665 else if (orig_after
&& after
!= orig_after
)
18666 emit_move_insn (orig_after
, after
);
18669 /* Emit instructions to move SRC to DST. Called by splitters for
18670 multi-register moves. It will emit at most one instruction for
18671 each register that is accessed; that is, it won't emit li/lis pairs
18672 (or equivalent for 64-bit code). One of SRC or DST must be a hard
18676 rs6000_split_multireg_move (rtx dst
, rtx src
)
18678 /* The register number of the first register being moved. */
18680 /* The mode that is to be moved. */
18681 enum machine_mode mode
;
18682 /* The mode that the move is being done in, and its size. */
18683 enum machine_mode reg_mode
;
18685 /* The number of registers that will be moved. */
18688 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
18689 mode
= GET_MODE (dst
);
18690 nregs
= hard_regno_nregs
[reg
][mode
];
18691 if (FP_REGNO_P (reg
))
18692 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
18693 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
18694 else if (ALTIVEC_REGNO_P (reg
))
18695 reg_mode
= V16QImode
;
18696 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
18699 reg_mode
= word_mode
;
18700 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
18702 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
18704 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
18706 /* Move register range backwards, if we might have destructive
18709 for (i
= nregs
- 1; i
>= 0; i
--)
18710 emit_insn (gen_rtx_SET (VOIDmode
,
18711 simplify_gen_subreg (reg_mode
, dst
, mode
,
18712 i
* reg_mode_size
),
18713 simplify_gen_subreg (reg_mode
, src
, mode
,
18714 i
* reg_mode_size
)));
18720 bool used_update
= false;
18721 rtx restore_basereg
= NULL_RTX
;
18723 if (MEM_P (src
) && INT_REGNO_P (reg
))
18727 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
18728 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
18731 breg
= XEXP (XEXP (src
, 0), 0);
18732 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
18733 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
18734 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
18735 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
18736 src
= replace_equiv_address (src
, breg
);
18738 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
18740 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
18742 rtx basereg
= XEXP (XEXP (src
, 0), 0);
18745 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
18746 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
18747 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
18748 used_update
= true;
18751 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
18752 XEXP (XEXP (src
, 0), 1)));
18753 src
= replace_equiv_address (src
, basereg
);
18757 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
18758 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
18759 src
= replace_equiv_address (src
, basereg
);
18763 breg
= XEXP (src
, 0);
18764 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
18765 breg
= XEXP (breg
, 0);
18767 /* If the base register we are using to address memory is
18768 also a destination reg, then change that register last. */
18770 && REGNO (breg
) >= REGNO (dst
)
18771 && REGNO (breg
) < REGNO (dst
) + nregs
)
18772 j
= REGNO (breg
) - REGNO (dst
);
18774 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
18778 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
18779 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
18782 breg
= XEXP (XEXP (dst
, 0), 0);
18783 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
18784 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
18785 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
18787 /* We have to update the breg before doing the store.
18788 Use store with update, if available. */
18792 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
18793 emit_insn (TARGET_32BIT
18794 ? (TARGET_POWERPC64
18795 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
18796 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
18797 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
18798 used_update
= true;
18801 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
18802 dst
= replace_equiv_address (dst
, breg
);
18804 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
18805 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
18807 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
18809 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
18812 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
18813 emit_insn (gen_rtx_SET (VOIDmode
,
18814 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
18815 used_update
= true;
18818 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
18819 XEXP (XEXP (dst
, 0), 1)));
18820 dst
= replace_equiv_address (dst
, basereg
);
18824 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
18825 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
18826 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
18828 && REG_P (offsetreg
)
18829 && REGNO (basereg
) != REGNO (offsetreg
));
18830 if (REGNO (basereg
) == 0)
18832 rtx tmp
= offsetreg
;
18833 offsetreg
= basereg
;
18836 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
18837 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
18838 dst
= replace_equiv_address (dst
, basereg
);
18841 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
18842 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
18845 for (i
= 0; i
< nregs
; i
++)
18847 /* Calculate index to next subword. */
18852 /* If compiler already emitted move of first word by
18853 store with update, no need to do anything. */
18854 if (j
== 0 && used_update
)
18857 emit_insn (gen_rtx_SET (VOIDmode
,
18858 simplify_gen_subreg (reg_mode
, dst
, mode
,
18859 j
* reg_mode_size
),
18860 simplify_gen_subreg (reg_mode
, src
, mode
,
18861 j
* reg_mode_size
)));
18863 if (restore_basereg
!= NULL_RTX
)
18864 emit_insn (restore_basereg
);
18869 /* This page contains routines that are used to determine what the
18870 function prologue and epilogue code will do and write them out. */
18875 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
18878 /* Return the first fixed-point register that is required to be
18879 saved. 32 if none. */
18882 first_reg_to_save (void)
18886 /* Find lowest numbered live register. */
18887 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
18888 if (save_reg_p (first_reg
))
18891 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
18892 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
18893 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
18894 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
18895 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
18896 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
18900 && crtl
->uses_pic_offset_table
18901 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
18902 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
18908 /* Similar, for FP regs. */
18911 first_fp_reg_to_save (void)
18915 /* Find lowest numbered live register. */
18916 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
18917 if (save_reg_p (first_reg
))
18923 /* Similar, for AltiVec regs. */
18926 first_altivec_reg_to_save (void)
18930 /* Stack frame remains as is unless we are in AltiVec ABI. */
18931 if (! TARGET_ALTIVEC_ABI
)
18932 return LAST_ALTIVEC_REGNO
+ 1;
18934 /* On Darwin, the unwind routines are compiled without
18935 TARGET_ALTIVEC, and use save_world to save/restore the
18936 altivec registers when necessary. */
18937 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
18938 && ! TARGET_ALTIVEC
)
18939 return FIRST_ALTIVEC_REGNO
+ 20;
18941 /* Find lowest numbered live register. */
18942 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
18943 if (save_reg_p (i
))
18949 /* Return a 32-bit mask of the AltiVec registers we need to set in
18950 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
18951 the 32-bit word is 0. */
18953 static unsigned int
18954 compute_vrsave_mask (void)
18956 unsigned int i
, mask
= 0;
18958 /* On Darwin, the unwind routines are compiled without
18959 TARGET_ALTIVEC, and use save_world to save/restore the
18960 call-saved altivec registers when necessary. */
18961 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
18962 && ! TARGET_ALTIVEC
)
18965 /* First, find out if we use _any_ altivec registers. */
18966 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
18967 if (df_regs_ever_live_p (i
))
18968 mask
|= ALTIVEC_REG_BIT (i
);
18973 /* Next, remove the argument registers from the set. These must
18974 be in the VRSAVE mask set by the caller, so we don't need to add
18975 them in again. More importantly, the mask we compute here is
18976 used to generate CLOBBERs in the set_vrsave insn, and we do not
18977 wish the argument registers to die. */
18978 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
18979 mask
&= ~ALTIVEC_REG_BIT (i
);
18981 /* Similarly, remove the return value from the set. */
18984 diddle_return_value (is_altivec_return_reg
, &yes
);
18986 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
18992 /* For a very restricted set of circumstances, we can cut down the
18993 size of prologues/epilogues by calling our own save/restore-the-world
18997 compute_save_world_info (rs6000_stack_t
*info_ptr
)
18999 info_ptr
->world_save_p
= 1;
19000 info_ptr
->world_save_p
19001 = (WORLD_SAVE_P (info_ptr
)
19002 && DEFAULT_ABI
== ABI_DARWIN
19003 && !cfun
->has_nonlocal_label
19004 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
19005 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
19006 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
19007 && info_ptr
->cr_save_p
);
19009 /* This will not work in conjunction with sibcalls. Make sure there
19010 are none. (This check is expensive, but seldom executed.) */
19011 if (WORLD_SAVE_P (info_ptr
))
19014 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
19015 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
19017 info_ptr
->world_save_p
= 0;
19022 if (WORLD_SAVE_P (info_ptr
))
19024 /* Even if we're not touching VRsave, make sure there's room on the
19025 stack for it, if it looks like we're calling SAVE_WORLD, which
19026 will attempt to save it. */
19027 info_ptr
->vrsave_size
= 4;
19029 /* If we are going to save the world, we need to save the link register too. */
19030 info_ptr
->lr_save_p
= 1;
19032 /* "Save" the VRsave register too if we're saving the world. */
19033 if (info_ptr
->vrsave_mask
== 0)
19034 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
19036 /* Because the Darwin register save/restore routines only handle
19037 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
19039 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
19040 && (info_ptr
->first_altivec_reg_save
19041 >= FIRST_SAVED_ALTIVEC_REGNO
));
19048 is_altivec_return_reg (rtx reg
, void *xyes
)
19050 bool *yes
= (bool *) xyes
;
19051 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
19056 /* Look for user-defined global regs in the range FIRST to LAST-1.
19057 We should not restore these, and so cannot use lmw or out-of-line
19058 restore functions if there are any. We also can't save them
19059 (well, emit frame notes for them), because frame unwinding during
19060 exception handling will restore saved registers. */
19063 global_regs_p (unsigned first
, unsigned last
)
19065 while (first
< last
)
19066 if (global_regs
[first
++])
19071 /* Determine the strategy for savings/restoring registers. */
19074 SAVRES_MULTIPLE
= 0x1,
19075 SAVE_INLINE_FPRS
= 0x2,
19076 SAVE_INLINE_GPRS
= 0x4,
19077 REST_INLINE_FPRS
= 0x8,
19078 REST_INLINE_GPRS
= 0x10,
19079 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
19080 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
19081 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
19082 SAVE_INLINE_VRS
= 0x100,
19083 REST_INLINE_VRS
= 0x200
19087 rs6000_savres_strategy (rs6000_stack_t
*info
,
19088 bool using_static_chain_p
)
19093 if (TARGET_MULTIPLE
19094 && !TARGET_POWERPC64
19095 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
19096 && info
->first_gp_reg_save
< 31
19097 && !global_regs_p (info
->first_gp_reg_save
, 32))
19098 strategy
|= SAVRES_MULTIPLE
;
19100 if (crtl
->calls_eh_return
19101 || cfun
->machine
->ra_need_lr
)
19102 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
19103 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
19104 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
19106 if (info
->first_fp_reg_save
== 64
19107 /* The out-of-line FP routines use double-precision stores;
19108 we can't use those routines if we don't have such stores. */
19109 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
19110 || global_regs_p (info
->first_fp_reg_save
, 64))
19111 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19113 if (info
->first_gp_reg_save
== 32
19114 || (!(strategy
& SAVRES_MULTIPLE
)
19115 && global_regs_p (info
->first_gp_reg_save
, 32)))
19116 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19118 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
19119 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
19120 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19122 /* Define cutoff for using out-of-line functions to save registers. */
19123 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
19125 if (!optimize_size
)
19127 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19128 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19129 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19133 /* Prefer out-of-line restore if it will exit. */
19134 if (info
->first_fp_reg_save
> 61)
19135 strategy
|= SAVE_INLINE_FPRS
;
19136 if (info
->first_gp_reg_save
> 29)
19138 if (info
->first_fp_reg_save
== 64)
19139 strategy
|= SAVE_INLINE_GPRS
;
19141 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19143 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
19144 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19147 else if (DEFAULT_ABI
== ABI_DARWIN
)
19149 if (info
->first_fp_reg_save
> 60)
19150 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19151 if (info
->first_gp_reg_save
> 29)
19152 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19153 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19157 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
);
19158 if (info
->first_fp_reg_save
> 61)
19159 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19160 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19161 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19164 /* Don't bother to try to save things out-of-line if r11 is occupied
19165 by the static chain. It would require too much fiddling and the
19166 static chain is rarely used anyway. FPRs are saved w.r.t the stack
19167 pointer on Darwin, and AIX uses r1 or r12. */
19168 if (using_static_chain_p
&& DEFAULT_ABI
!= ABI_AIX
)
19169 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
19171 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
19173 /* We can only use the out-of-line routines to restore if we've
19174 saved all the registers from first_fp_reg_save in the prologue.
19175 Otherwise, we risk loading garbage. */
19176 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
19180 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
19181 if (!save_reg_p (i
))
19183 strategy
|= REST_INLINE_FPRS
;
19188 /* If we are going to use store multiple, then don't even bother
19189 with the out-of-line routines, since the store-multiple
19190 instruction will always be smaller. */
19191 if ((strategy
& SAVRES_MULTIPLE
))
19192 strategy
|= SAVE_INLINE_GPRS
;
19194 /* info->lr_save_p isn't yet set if the only reason lr needs to be
19195 saved is an out-of-line save or restore. Set up the value for
19196 the next test (excluding out-of-line gpr restore). */
19197 lr_save_p
= (info
->lr_save_p
19198 || !(strategy
& SAVE_INLINE_GPRS
)
19199 || !(strategy
& SAVE_INLINE_FPRS
)
19200 || !(strategy
& SAVE_INLINE_VRS
)
19201 || !(strategy
& REST_INLINE_FPRS
)
19202 || !(strategy
& REST_INLINE_VRS
));
19204 /* The situation is more complicated with load multiple. We'd
19205 prefer to use the out-of-line routines for restores, since the
19206 "exit" out-of-line routines can handle the restore of LR and the
19207 frame teardown. However if doesn't make sense to use the
19208 out-of-line routine if that is the only reason we'd need to save
19209 LR, and we can't use the "exit" out-of-line gpr restore if we
19210 have saved some fprs; In those cases it is advantageous to use
19211 load multiple when available. */
19212 if ((strategy
& SAVRES_MULTIPLE
)
19214 || info
->first_fp_reg_save
!= 64))
19215 strategy
|= REST_INLINE_GPRS
;
19217 /* Saving CR interferes with the exit routines used on the SPE, so
19220 && info
->spe_64bit_regs_used
19221 && info
->cr_save_p
)
19222 strategy
|= REST_INLINE_GPRS
;
19224 /* We can only use load multiple or the out-of-line routines to
19225 restore if we've used store multiple or out-of-line routines
19226 in the prologue, i.e. if we've saved all the registers from
19227 first_gp_reg_save. Otherwise, we risk loading garbage. */
19228 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
19229 == SAVE_INLINE_GPRS
)
19233 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
19234 if (!save_reg_p (i
))
19236 strategy
|= REST_INLINE_GPRS
;
19241 if (TARGET_ELF
&& TARGET_64BIT
)
19243 if (!(strategy
& SAVE_INLINE_FPRS
))
19244 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
19245 else if (!(strategy
& SAVE_INLINE_GPRS
)
19246 && info
->first_fp_reg_save
== 64)
19247 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
19249 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
19250 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
19252 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
19253 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
19258 /* Calculate the stack information for the current function. This is
19259 complicated by having two separate calling sequences, the AIX calling
19260 sequence and the V.4 calling sequence.
19262 AIX (and Darwin/Mac OS X) stack frames look like:
19264 SP----> +---------------------------------------+
19265 | back chain to caller | 0 0
19266 +---------------------------------------+
19267 | saved CR | 4 8 (8-11)
19268 +---------------------------------------+
19270 +---------------------------------------+
19271 | reserved for compilers | 12 24
19272 +---------------------------------------+
19273 | reserved for binders | 16 32
19274 +---------------------------------------+
19275 | saved TOC pointer | 20 40
19276 +---------------------------------------+
19277 | Parameter save area (P) | 24 48
19278 +---------------------------------------+
19279 | Alloca space (A) | 24+P etc.
19280 +---------------------------------------+
19281 | Local variable space (L) | 24+P+A
19282 +---------------------------------------+
19283 | Float/int conversion temporary (X) | 24+P+A+L
19284 +---------------------------------------+
19285 | Save area for AltiVec registers (W) | 24+P+A+L+X
19286 +---------------------------------------+
19287 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
19288 +---------------------------------------+
19289 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
19290 +---------------------------------------+
19291 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
19292 +---------------------------------------+
19293 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
19294 +---------------------------------------+
19295 old SP->| back chain to caller's caller |
19296 +---------------------------------------+
19298 The required alignment for AIX configurations is two words (i.e., 8
19302 V.4 stack frames look like:
19304 SP----> +---------------------------------------+
19305 | back chain to caller | 0
19306 +---------------------------------------+
19307 | caller's saved LR | 4
19308 +---------------------------------------+
19309 | Parameter save area (P) | 8
19310 +---------------------------------------+
19311 | Alloca space (A) | 8+P
19312 +---------------------------------------+
19313 | Varargs save area (V) | 8+P+A
19314 +---------------------------------------+
19315 | Local variable space (L) | 8+P+A+V
19316 +---------------------------------------+
19317 | Float/int conversion temporary (X) | 8+P+A+V+L
19318 +---------------------------------------+
19319 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
19320 +---------------------------------------+
19321 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
19322 +---------------------------------------+
19323 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
19324 +---------------------------------------+
19325 | SPE: area for 64-bit GP registers |
19326 +---------------------------------------+
19327 | SPE alignment padding |
19328 +---------------------------------------+
19329 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
19330 +---------------------------------------+
19331 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
19332 +---------------------------------------+
19333 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
19334 +---------------------------------------+
19335 old SP->| back chain to caller's caller |
19336 +---------------------------------------+
19338 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
19339 given. (But note below and in sysv4.h that we require only 8 and
19340 may round up the size of our stack frame anyways. The historical
19341 reason is early versions of powerpc-linux which didn't properly
19342 align the stack at program startup. A happy side-effect is that
19343 -mno-eabi libraries can be used with -meabi programs.)
19345 The EABI configuration defaults to the V.4 layout. However,
19346 the stack alignment requirements may differ. If -mno-eabi is not
19347 given, the required stack alignment is 8 bytes; if -mno-eabi is
19348 given, the required alignment is 16 bytes. (But see V.4 comment
19351 #ifndef ABI_STACK_BOUNDARY
19352 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
19355 static rs6000_stack_t
*
19356 rs6000_stack_info (void)
19358 rs6000_stack_t
*info_ptr
= &stack_info
;
19359 int reg_size
= TARGET_32BIT
? 4 : 8;
19363 HOST_WIDE_INT non_fixed_size
;
19364 bool using_static_chain_p
;
19366 if (reload_completed
&& info_ptr
->reload_completed
)
19369 memset (info_ptr
, 0, sizeof (*info_ptr
));
19370 info_ptr
->reload_completed
= reload_completed
;
19374 /* Cache value so we don't rescan instruction chain over and over. */
19375 if (cfun
->machine
->insn_chain_scanned_p
== 0)
19376 cfun
->machine
->insn_chain_scanned_p
19377 = spe_func_has_64bit_regs_p () + 1;
19378 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
19381 /* Select which calling sequence. */
19382 info_ptr
->abi
= DEFAULT_ABI
;
19384 /* Calculate which registers need to be saved & save area size. */
19385 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
19386 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
19387 even if it currently looks like we won't. Reload may need it to
19388 get at a constant; if so, it will have already created a constant
19389 pool entry for it. */
19390 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
19391 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
19392 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
19393 && crtl
->uses_const_pool
19394 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
19395 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
19397 first_gp
= info_ptr
->first_gp_reg_save
;
19399 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
19401 /* For the SPE, we have an additional upper 32-bits on each GPR.
19402 Ideally we should save the entire 64-bits only when the upper
19403 half is used in SIMD instructions. Since we only record
19404 registers live (not the size they are used in), this proves
19405 difficult because we'd have to traverse the instruction chain at
19406 the right time, taking reload into account. This is a real pain,
19407 so we opt to save the GPRs in 64-bits always if but one register
19408 gets used in 64-bits. Otherwise, all the registers in the frame
19409 get saved in 32-bits.
19411 So... since when we save all GPRs (except the SP) in 64-bits, the
19412 traditional GP save area will be empty. */
19413 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
19414 info_ptr
->gp_size
= 0;
19416 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
19417 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
19419 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
19420 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
19421 - info_ptr
->first_altivec_reg_save
);
19423 /* Does this function call anything? */
19424 info_ptr
->calls_p
= (! crtl
->is_leaf
19425 || cfun
->machine
->ra_needs_full_frame
);
19427 /* Determine if we need to save the condition code registers. */
19428 if (df_regs_ever_live_p (CR2_REGNO
)
19429 || df_regs_ever_live_p (CR3_REGNO
)
19430 || df_regs_ever_live_p (CR4_REGNO
))
19432 info_ptr
->cr_save_p
= 1;
19433 if (DEFAULT_ABI
== ABI_V4
)
19434 info_ptr
->cr_size
= reg_size
;
19437 /* If the current function calls __builtin_eh_return, then we need
19438 to allocate stack space for registers that will hold data for
19439 the exception handler. */
19440 if (crtl
->calls_eh_return
)
19443 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
19446 /* SPE saves EH registers in 64-bits. */
19447 ehrd_size
= i
* (TARGET_SPE_ABI
19448 && info_ptr
->spe_64bit_regs_used
!= 0
19449 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
19454 /* Determine various sizes. */
19455 info_ptr
->reg_size
= reg_size
;
19456 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
19457 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
19458 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
19459 TARGET_ALTIVEC
? 16 : 8);
19460 if (FRAME_GROWS_DOWNWARD
)
19461 info_ptr
->vars_size
19462 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
19463 + info_ptr
->parm_size
,
19464 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
19465 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
19466 + info_ptr
->parm_size
);
19468 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
19469 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
19471 info_ptr
->spe_gp_size
= 0;
19473 if (TARGET_ALTIVEC_ABI
)
19474 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
19476 info_ptr
->vrsave_mask
= 0;
19478 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
19479 info_ptr
->vrsave_size
= 4;
19481 info_ptr
->vrsave_size
= 0;
19483 compute_save_world_info (info_ptr
);
19485 /* Calculate the offsets. */
19486 switch (DEFAULT_ABI
)
19490 gcc_unreachable ();
19494 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
19495 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
19497 if (TARGET_ALTIVEC_ABI
)
19499 info_ptr
->vrsave_save_offset
19500 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
19502 /* Align stack so vector save area is on a quadword boundary.
19503 The padding goes above the vectors. */
19504 if (info_ptr
->altivec_size
!= 0)
19505 info_ptr
->altivec_padding_size
19506 = info_ptr
->vrsave_save_offset
& 0xF;
19508 info_ptr
->altivec_padding_size
= 0;
19510 info_ptr
->altivec_save_offset
19511 = info_ptr
->vrsave_save_offset
19512 - info_ptr
->altivec_padding_size
19513 - info_ptr
->altivec_size
;
19514 gcc_assert (info_ptr
->altivec_size
== 0
19515 || info_ptr
->altivec_save_offset
% 16 == 0);
19517 /* Adjust for AltiVec case. */
19518 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
19521 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
19522 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
19523 info_ptr
->lr_save_offset
= 2*reg_size
;
19527 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
19528 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
19529 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
19531 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
19533 /* Align stack so SPE GPR save area is aligned on a
19534 double-word boundary. */
19535 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
19536 info_ptr
->spe_padding_size
19537 = 8 - (-info_ptr
->cr_save_offset
% 8);
19539 info_ptr
->spe_padding_size
= 0;
19541 info_ptr
->spe_gp_save_offset
19542 = info_ptr
->cr_save_offset
19543 - info_ptr
->spe_padding_size
19544 - info_ptr
->spe_gp_size
;
19546 /* Adjust for SPE case. */
19547 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
19549 else if (TARGET_ALTIVEC_ABI
)
19551 info_ptr
->vrsave_save_offset
19552 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
19554 /* Align stack so vector save area is on a quadword boundary. */
19555 if (info_ptr
->altivec_size
!= 0)
19556 info_ptr
->altivec_padding_size
19557 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
19559 info_ptr
->altivec_padding_size
= 0;
19561 info_ptr
->altivec_save_offset
19562 = info_ptr
->vrsave_save_offset
19563 - info_ptr
->altivec_padding_size
19564 - info_ptr
->altivec_size
;
19566 /* Adjust for AltiVec case. */
19567 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
19570 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
19571 info_ptr
->ehrd_offset
-= ehrd_size
;
19572 info_ptr
->lr_save_offset
= reg_size
;
19576 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
19577 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
19578 + info_ptr
->gp_size
19579 + info_ptr
->altivec_size
19580 + info_ptr
->altivec_padding_size
19581 + info_ptr
->spe_gp_size
19582 + info_ptr
->spe_padding_size
19584 + info_ptr
->cr_size
19585 + info_ptr
->vrsave_size
,
19588 non_fixed_size
= (info_ptr
->vars_size
19589 + info_ptr
->parm_size
19590 + info_ptr
->save_size
);
19592 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
19593 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
19595 /* Determine if we need to save the link register. */
19596 if (info_ptr
->calls_p
19597 || (DEFAULT_ABI
== ABI_AIX
19599 && !TARGET_PROFILE_KERNEL
)
19600 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
19601 #ifdef TARGET_RELOCATABLE
19602 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
19604 || rs6000_ra_ever_killed ())
19605 info_ptr
->lr_save_p
= 1;
19607 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
19608 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
19609 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
19610 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
19611 using_static_chain_p
);
19613 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
19614 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
19615 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
19616 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
19617 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
19618 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
19619 info_ptr
->lr_save_p
= 1;
19621 if (info_ptr
->lr_save_p
)
19622 df_set_regs_ever_live (LR_REGNO
, true);
19624 /* Determine if we need to allocate any stack frame:
19626 For AIX we need to push the stack if a frame pointer is needed
19627 (because the stack might be dynamically adjusted), if we are
19628 debugging, if we make calls, or if the sum of fp_save, gp_save,
19629 and local variables are more than the space needed to save all
19630 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
19631 + 18*8 = 288 (GPR13 reserved).
19633 For V.4 we don't have the stack cushion that AIX uses, but assume
19634 that the debugger can handle stackless frames. */
19636 if (info_ptr
->calls_p
)
19637 info_ptr
->push_p
= 1;
19639 else if (DEFAULT_ABI
== ABI_V4
)
19640 info_ptr
->push_p
= non_fixed_size
!= 0;
19642 else if (frame_pointer_needed
)
19643 info_ptr
->push_p
= 1;
19645 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
19646 info_ptr
->push_p
= 1;
19649 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
19651 /* Zero offsets if we're not saving those registers. */
19652 if (info_ptr
->fp_size
== 0)
19653 info_ptr
->fp_save_offset
= 0;
19655 if (info_ptr
->gp_size
== 0)
19656 info_ptr
->gp_save_offset
= 0;
19658 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
19659 info_ptr
->altivec_save_offset
= 0;
19661 /* Zero VRSAVE offset if not saved and restored. */
19662 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
19663 info_ptr
->vrsave_save_offset
= 0;
19665 if (! TARGET_SPE_ABI
19666 || info_ptr
->spe_64bit_regs_used
== 0
19667 || info_ptr
->spe_gp_size
== 0)
19668 info_ptr
->spe_gp_save_offset
= 0;
19670 if (! info_ptr
->lr_save_p
)
19671 info_ptr
->lr_save_offset
= 0;
19673 if (! info_ptr
->cr_save_p
)
19674 info_ptr
->cr_save_offset
= 0;
19679 /* Return true if the current function uses any GPRs in 64-bit SIMD
19683 spe_func_has_64bit_regs_p (void)
19687 /* Functions that save and restore all the call-saved registers will
19688 need to save/restore the registers in 64-bits. */
19689 if (crtl
->calls_eh_return
19690 || cfun
->calls_setjmp
19691 || crtl
->has_nonlocal_goto
)
19694 insns
= get_insns ();
19696 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
19702 /* FIXME: This should be implemented with attributes...
19704 (set_attr "spe64" "true")....then,
19705 if (get_spe64(insn)) return true;
19707 It's the only reliable way to do the stuff below. */
19709 i
= PATTERN (insn
);
19710 if (GET_CODE (i
) == SET
)
19712 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
19714 if (SPE_VECTOR_MODE (mode
))
19716 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
19726 debug_stack_info (rs6000_stack_t
*info
)
19728 const char *abi_string
;
19731 info
= rs6000_stack_info ();
19733 fprintf (stderr
, "\nStack information for function %s:\n",
19734 ((current_function_decl
&& DECL_NAME (current_function_decl
))
19735 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
19740 default: abi_string
= "Unknown"; break;
19741 case ABI_NONE
: abi_string
= "NONE"; break;
19742 case ABI_AIX
: abi_string
= "AIX"; break;
19743 case ABI_DARWIN
: abi_string
= "Darwin"; break;
19744 case ABI_V4
: abi_string
= "V.4"; break;
19747 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
19749 if (TARGET_ALTIVEC_ABI
)
19750 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
19752 if (TARGET_SPE_ABI
)
19753 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
19755 if (info
->first_gp_reg_save
!= 32)
19756 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
19758 if (info
->first_fp_reg_save
!= 64)
19759 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
19761 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
19762 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
19763 info
->first_altivec_reg_save
);
19765 if (info
->lr_save_p
)
19766 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
19768 if (info
->cr_save_p
)
19769 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
19771 if (info
->vrsave_mask
)
19772 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
19775 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
19778 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
19780 if (info
->gp_save_offset
)
19781 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
19783 if (info
->fp_save_offset
)
19784 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
19786 if (info
->altivec_save_offset
)
19787 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
19788 info
->altivec_save_offset
);
19790 if (info
->spe_gp_save_offset
)
19791 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
19792 info
->spe_gp_save_offset
);
19794 if (info
->vrsave_save_offset
)
19795 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
19796 info
->vrsave_save_offset
);
19798 if (info
->lr_save_offset
)
19799 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
19801 if (info
->cr_save_offset
)
19802 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
19804 if (info
->varargs_save_offset
)
19805 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
19807 if (info
->total_size
)
19808 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
19811 if (info
->vars_size
)
19812 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
19815 if (info
->parm_size
)
19816 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
19818 if (info
->fixed_size
)
19819 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
19822 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
19824 if (info
->spe_gp_size
)
19825 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
19828 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
19830 if (info
->altivec_size
)
19831 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
19833 if (info
->vrsave_size
)
19834 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
19836 if (info
->altivec_padding_size
)
19837 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
19838 info
->altivec_padding_size
);
19840 if (info
->spe_padding_size
)
19841 fprintf (stderr
, "\tspe_padding_size = %5d\n",
19842 info
->spe_padding_size
);
19845 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
19847 if (info
->save_size
)
19848 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
19850 if (info
->reg_size
!= 4)
19851 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
19853 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
19855 fprintf (stderr
, "\n");
19859 rs6000_return_addr (int count
, rtx frame
)
19861 /* Currently we don't optimize very well between prolog and body
19862 code and for PIC code the code can be actually quite bad, so
19863 don't try to be too clever here. */
19864 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
19866 cfun
->machine
->ra_needs_full_frame
= 1;
19873 plus_constant (Pmode
,
19875 (gen_rtx_MEM (Pmode
,
19876 memory_address (Pmode
, frame
))),
19877 RETURN_ADDRESS_OFFSET
)));
19880 cfun
->machine
->ra_need_lr
= 1;
19881 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
19884 /* Say whether a function is a candidate for sibcall handling or not. */
19887 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
19892 fntype
= TREE_TYPE (decl
);
19894 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
19896 /* We can't do it if the called function has more vector parameters
19897 than the current function; there's nowhere to put the VRsave code. */
19898 if (TARGET_ALTIVEC_ABI
19899 && TARGET_ALTIVEC_VRSAVE
19900 && !(decl
&& decl
== current_function_decl
))
19902 function_args_iterator args_iter
;
19906 /* Functions with vector parameters are required to have a
19907 prototype, so the argument type info must be available
19909 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
19910 if (TREE_CODE (type
) == VECTOR_TYPE
19911 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
19914 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
19915 if (TREE_CODE (type
) == VECTOR_TYPE
19916 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
19923 /* Under the AIX ABI we can't allow calls to non-local functions,
19924 because the callee may have a different TOC pointer to the
19925 caller and there's no way to ensure we restore the TOC when we
19926 return. With the secure-plt SYSV ABI we can't make non-local
19927 calls when -fpic/PIC because the plt call stubs use r30. */
19928 if (DEFAULT_ABI
== ABI_DARWIN
19929 || (DEFAULT_ABI
== ABI_AIX
19931 && !DECL_EXTERNAL (decl
)
19932 && (*targetm
.binds_local_p
) (decl
))
19933 || (DEFAULT_ABI
== ABI_V4
19934 && (!TARGET_SECURE_PLT
19937 && (*targetm
.binds_local_p
) (decl
)))))
19939 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
19941 if (!lookup_attribute ("longcall", attr_list
)
19942 || lookup_attribute ("shortcall", attr_list
))
19950 rs6000_ra_ever_killed (void)
19956 if (cfun
->is_thunk
)
19959 if (cfun
->machine
->lr_save_state
)
19960 return cfun
->machine
->lr_save_state
- 1;
19962 /* regs_ever_live has LR marked as used if any sibcalls are present,
19963 but this should not force saving and restoring in the
19964 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
19965 clobbers LR, so that is inappropriate. */
19967 /* Also, the prologue can generate a store into LR that
19968 doesn't really count, like this:
19971 bcl to set PIC register
19975 When we're called from the epilogue, we need to avoid counting
19976 this as a store. */
19978 push_topmost_sequence ();
19979 top
= get_insns ();
19980 pop_topmost_sequence ();
19981 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
19983 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
19989 if (!SIBLING_CALL_P (insn
))
19992 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
19994 else if (set_of (reg
, insn
) != NULL_RTX
19995 && !prologue_epilogue_contains (insn
))
20002 /* Emit instructions needed to load the TOC register.
20003 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
20004 a constant pool; or for SVR4 -fpic. */
20007 rs6000_emit_load_toc_table (int fromprolog
)
20010 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
20012 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
20015 rtx lab
, tmp1
, tmp2
, got
;
20017 lab
= gen_label_rtx ();
20018 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
20019 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20021 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
20023 got
= rs6000_got_sym ();
20024 tmp1
= tmp2
= dest
;
20027 tmp1
= gen_reg_rtx (Pmode
);
20028 tmp2
= gen_reg_rtx (Pmode
);
20030 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
20031 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
20032 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
20033 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
20035 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
20037 emit_insn (gen_load_toc_v4_pic_si ());
20038 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
20040 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
20043 rtx temp0
= (fromprolog
20044 ? gen_rtx_REG (Pmode
, 0)
20045 : gen_reg_rtx (Pmode
));
20051 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
20052 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20054 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
20055 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20057 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
20058 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
20059 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
20065 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
20066 lab
= gen_label_rtx ();
20067 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
20068 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
20069 if (TARGET_LINK_STACK
)
20070 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
20071 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
20073 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
20075 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
20077 /* This is for AIX code running in non-PIC ELF32. */
20080 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
20081 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20083 emit_insn (gen_elf_high (dest
, realsym
));
20084 emit_insn (gen_elf_low (dest
, dest
, realsym
));
20088 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
20091 emit_insn (gen_load_toc_aix_si (dest
));
20093 emit_insn (gen_load_toc_aix_di (dest
));
20097 /* Emit instructions to restore the link register after determining where
20098 its value has been stored. */
20101 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
20103 rs6000_stack_t
*info
= rs6000_stack_info ();
20106 operands
[0] = source
;
20107 operands
[1] = scratch
;
20109 if (info
->lr_save_p
)
20111 rtx frame_rtx
= stack_pointer_rtx
;
20112 HOST_WIDE_INT sp_offset
= 0;
20115 if (frame_pointer_needed
20116 || cfun
->calls_alloca
20117 || info
->total_size
> 32767)
20119 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
20120 emit_move_insn (operands
[1], tmp
);
20121 frame_rtx
= operands
[1];
20123 else if (info
->push_p
)
20124 sp_offset
= info
->total_size
;
20126 tmp
= plus_constant (Pmode
, frame_rtx
,
20127 info
->lr_save_offset
+ sp_offset
);
20128 tmp
= gen_frame_mem (Pmode
, tmp
);
20129 emit_move_insn (tmp
, operands
[0]);
20132 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
20134 /* Freeze lr_save_p. We've just emitted rtl that depends on the
20135 state of lr_save_p so any change from here on would be a bug. In
20136 particular, stop rs6000_ra_ever_killed from considering the SET
20137 of lr we may have added just above. */
20138 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
20141 static GTY(()) alias_set_type set
= -1;
20144 get_TOC_alias_set (void)
20147 set
= new_alias_set ();
20151 /* This returns nonzero if the current function uses the TOC. This is
20152 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
20153 is generated by the ABI_V4 load_toc_* patterns. */
20160 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
20163 rtx pat
= PATTERN (insn
);
20166 if (GET_CODE (pat
) == PARALLEL
)
20167 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
20169 rtx sub
= XVECEXP (pat
, 0, i
);
20170 if (GET_CODE (sub
) == USE
)
20172 sub
= XEXP (sub
, 0);
20173 if (GET_CODE (sub
) == UNSPEC
20174 && XINT (sub
, 1) == UNSPEC_TOC
)
20184 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
20186 rtx tocrel
, tocreg
, hi
;
20188 if (TARGET_DEBUG_ADDR
)
20190 if (GET_CODE (symbol
) == SYMBOL_REF
)
20191 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
20195 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
20196 GET_RTX_NAME (GET_CODE (symbol
)));
20197 debug_rtx (symbol
);
20201 if (!can_create_pseudo_p ())
20202 df_set_regs_ever_live (TOC_REGISTER
, true);
20204 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
20205 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
20206 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
20209 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
20210 if (largetoc_reg
!= NULL
)
20212 emit_move_insn (largetoc_reg
, hi
);
20215 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
20218 /* Issue assembly directives that create a reference to the given DWARF
20219 FRAME_TABLE_LABEL from the current function section. */
20221 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
20223 fprintf (asm_out_file
, "\t.ref %s\n",
20224 (* targetm
.strip_name_encoding
) (frame_table_label
));
20227 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
20228 and the change to the stack pointer. */
20231 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
20238 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
20239 if (hard_frame_needed
)
20240 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
20241 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
20242 || (hard_frame_needed
20243 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
20246 p
= rtvec_alloc (i
);
20249 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
20250 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
20253 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
20256 /* Emit the correct code for allocating stack space, as insns.
20257 If COPY_REG, make sure a copy of the old frame is left there.
20258 The generated code may use hard register 0 as a temporary. */
20261 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
20264 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
20265 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
20266 rtx todec
= gen_int_mode (-size
, Pmode
);
20269 if (INTVAL (todec
) != -size
)
20271 warning (0, "stack frame too large");
20272 emit_insn (gen_trap ());
20276 if (crtl
->limit_stack
)
20278 if (REG_P (stack_limit_rtx
)
20279 && REGNO (stack_limit_rtx
) > 1
20280 && REGNO (stack_limit_rtx
) <= 31)
20282 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
20283 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
20286 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
20288 && DEFAULT_ABI
== ABI_V4
)
20290 rtx toload
= gen_rtx_CONST (VOIDmode
,
20291 gen_rtx_PLUS (Pmode
,
20295 emit_insn (gen_elf_high (tmp_reg
, toload
));
20296 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
20297 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
20301 warning (0, "stack limit expression is not supported");
20307 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
20309 emit_move_insn (copy_reg
, stack_reg
);
20314 /* Need a note here so that try_split doesn't get confused. */
20315 if (get_last_insn () == NULL_RTX
)
20316 emit_note (NOTE_INSN_DELETED
);
20317 insn
= emit_move_insn (tmp_reg
, todec
);
20318 try_split (PATTERN (insn
), insn
, 0);
20322 insn
= emit_insn (TARGET_32BIT
20323 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
20325 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
20326 todec
, stack_reg
));
20327 /* Since we didn't use gen_frame_mem to generate the MEM, grab
20328 it now and set the alias set/attributes. The above gen_*_update
20329 calls will generate a PARALLEL with the MEM set being the first
20331 par
= PATTERN (insn
);
20332 gcc_assert (GET_CODE (par
) == PARALLEL
);
20333 set
= XVECEXP (par
, 0, 0);
20334 gcc_assert (GET_CODE (set
) == SET
);
20335 mem
= SET_DEST (set
);
20336 gcc_assert (MEM_P (mem
));
20337 MEM_NOTRAP_P (mem
) = 1;
20338 set_mem_alias_set (mem
, get_frame_alias_set ());
20340 RTX_FRAME_RELATED_P (insn
) = 1;
20341 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
20342 gen_rtx_SET (VOIDmode
, stack_reg
,
20343 gen_rtx_PLUS (Pmode
, stack_reg
,
20344 GEN_INT (-size
))));
20347 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
20349 #if PROBE_INTERVAL > 32768
20350 #error Cannot use indexed addressing mode for stack probing
20353 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
20354 inclusive. These are offsets from the current stack pointer. */
20357 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
20359 /* See if we have a constant small number of probes to generate. If so,
20360 that's the easy case. */
20361 if (first
+ size
<= 32768)
20365 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
20366 it exceeds SIZE. If only one probe is needed, this will not
20367 generate any code. Then probe at FIRST + SIZE. */
20368 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
20369 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
20372 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
20376 /* Otherwise, do the same as above, but in a loop. Note that we must be
20377 extra careful with variables wrapping around because we might be at
20378 the very top (or the very bottom) of the address space and we have
20379 to be able to handle this case properly; in particular, we use an
20380 equality test for the loop condition. */
20383 HOST_WIDE_INT rounded_size
;
20384 rtx r12
= gen_rtx_REG (Pmode
, 12);
20385 rtx r0
= gen_rtx_REG (Pmode
, 0);
20387 /* Sanity check for the addressing mode we're going to use. */
20388 gcc_assert (first
<= 32768);
20390 /* Step 1: round SIZE to the previous multiple of the interval. */
20392 rounded_size
= size
& -PROBE_INTERVAL
;
20395 /* Step 2: compute initial and final value of the loop counter. */
20397 /* TEST_ADDR = SP + FIRST. */
20398 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
20399 plus_constant (Pmode
, stack_pointer_rtx
,
20402 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
20403 if (rounded_size
> 32768)
20405 emit_move_insn (r0
, GEN_INT (-rounded_size
));
20406 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
20407 gen_rtx_PLUS (Pmode
, r12
, r0
)));
20410 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
20411 plus_constant (Pmode
, r12
, -rounded_size
)));
20414 /* Step 3: the loop
20416 while (TEST_ADDR != LAST_ADDR)
20418 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
20422 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
20423 until it is equal to ROUNDED_SIZE. */
20426 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
20428 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
20431 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
20432 that SIZE is equal to ROUNDED_SIZE. */
20434 if (size
!= rounded_size
)
20435 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
20439 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
20440 absolute addresses. */
20443 output_probe_stack_range (rtx reg1
, rtx reg2
)
20445 static int labelno
= 0;
20446 char loop_lab
[32], end_lab
[32];
20449 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
20450 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
20452 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
20454 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
20458 output_asm_insn ("cmpd 0,%0,%1", xops
);
20460 output_asm_insn ("cmpw 0,%0,%1", xops
);
20462 fputs ("\tbeq 0,", asm_out_file
);
20463 assemble_name_raw (asm_out_file
, end_lab
);
20464 fputc ('\n', asm_out_file
);
20466 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
20467 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
20468 output_asm_insn ("addi %0,%0,%1", xops
);
20470 /* Probe at TEST_ADDR and branch. */
20471 xops
[1] = gen_rtx_REG (Pmode
, 0);
20472 output_asm_insn ("stw %1,0(%0)", xops
);
20473 fprintf (asm_out_file
, "\tb ");
20474 assemble_name_raw (asm_out_file
, loop_lab
);
20475 fputc ('\n', asm_out_file
);
20477 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
20482 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
20483 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
20484 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
20485 deduce these equivalences by itself so it wasn't necessary to hold
20486 its hand so much. Don't be tempted to always supply d2_f_d_e with
20487 the actual cfa register, ie. r31 when we are using a hard frame
20488 pointer. That fails when saving regs off r1, and sched moves the
20489 r31 setup past the reg saves. */
20492 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
20493 rtx reg2
, rtx rreg
)
20497 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
20499 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
20502 gcc_checking_assert (val
== 0);
20503 real
= PATTERN (insn
);
20504 if (GET_CODE (real
) == PARALLEL
)
20505 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
20506 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
20508 rtx set
= XVECEXP (real
, 0, i
);
20510 RTX_FRAME_RELATED_P (set
) = 1;
20512 RTX_FRAME_RELATED_P (insn
) = 1;
20516 /* copy_rtx will not make unique copies of registers, so we need to
20517 ensure we don't have unwanted sharing here. */
20519 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
20522 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
20524 real
= copy_rtx (PATTERN (insn
));
20526 if (reg2
!= NULL_RTX
)
20527 real
= replace_rtx (real
, reg2
, rreg
);
20529 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
20530 gcc_checking_assert (val
== 0);
20532 real
= replace_rtx (real
, reg
,
20533 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
20534 STACK_POINTER_REGNUM
),
20537 /* We expect that 'real' is either a SET or a PARALLEL containing
20538 SETs (and possibly other stuff). In a PARALLEL, all the SETs
20539 are important so they all have to be marked RTX_FRAME_RELATED_P. */
20541 if (GET_CODE (real
) == SET
)
20545 temp
= simplify_rtx (SET_SRC (set
));
20547 SET_SRC (set
) = temp
;
20548 temp
= simplify_rtx (SET_DEST (set
));
20550 SET_DEST (set
) = temp
;
20551 if (GET_CODE (SET_DEST (set
)) == MEM
)
20553 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
20555 XEXP (SET_DEST (set
), 0) = temp
;
20562 gcc_assert (GET_CODE (real
) == PARALLEL
);
20563 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
20564 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
20566 rtx set
= XVECEXP (real
, 0, i
);
20568 temp
= simplify_rtx (SET_SRC (set
));
20570 SET_SRC (set
) = temp
;
20571 temp
= simplify_rtx (SET_DEST (set
));
20573 SET_DEST (set
) = temp
;
20574 if (GET_CODE (SET_DEST (set
)) == MEM
)
20576 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
20578 XEXP (SET_DEST (set
), 0) = temp
;
20580 RTX_FRAME_RELATED_P (set
) = 1;
20584 RTX_FRAME_RELATED_P (insn
) = 1;
20585 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
20590 /* Returns an insn that has a vrsave set operation with the
20591 appropriate CLOBBERs. */
20594 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
20597 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
20598 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
20601 = gen_rtx_SET (VOIDmode
,
20603 gen_rtx_UNSPEC_VOLATILE (SImode
,
20604 gen_rtvec (2, reg
, vrsave
),
20605 UNSPECV_SET_VRSAVE
));
20609 /* We need to clobber the registers in the mask so the scheduler
20610 does not move sets to VRSAVE before sets of AltiVec registers.
20612 However, if the function receives nonlocal gotos, reload will set
20613 all call saved registers live. We will end up with:
20615 (set (reg 999) (mem))
20616 (parallel [ (set (reg vrsave) (unspec blah))
20617 (clobber (reg 999))])
20619 The clobber will cause the store into reg 999 to be dead, and
20620 flow will attempt to delete an epilogue insn. In this case, we
20621 need an unspec use/set of the register. */
20623 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20624 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20626 if (!epiloguep
|| call_used_regs
[i
])
20627 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
20628 gen_rtx_REG (V4SImode
, i
));
20631 rtx reg
= gen_rtx_REG (V4SImode
, i
);
20634 = gen_rtx_SET (VOIDmode
,
20636 gen_rtx_UNSPEC (V4SImode
,
20637 gen_rtvec (1, reg
), 27));
20641 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
20643 for (i
= 0; i
< nclobs
; ++i
)
20644 XVECEXP (insn
, 0, i
) = clobs
[i
];
20650 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
20654 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
20655 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
20656 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
20660 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
20662 return gen_frame_set (reg
, frame_reg
, offset
, false);
20666 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
20668 return gen_frame_set (reg
, frame_reg
, offset
, true);
20671 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
20672 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
20675 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
20676 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
20680 /* Some cases that need register indexed addressing. */
20681 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
20682 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
20683 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
20685 && SPE_VECTOR_MODE (mode
)
20686 && !SPE_CONST_OFFSET_OK (offset
))));
20688 reg
= gen_rtx_REG (mode
, regno
);
20689 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
20690 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
20691 NULL_RTX
, NULL_RTX
);
20694 /* Emit an offset memory reference suitable for a frame store, while
20695 converting to a valid addressing mode. */
20698 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
20700 rtx int_rtx
, offset_rtx
;
20702 int_rtx
= GEN_INT (offset
);
20704 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
20705 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
20707 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
20708 emit_move_insn (offset_rtx
, int_rtx
);
20711 offset_rtx
= int_rtx
;
20713 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
20716 #ifndef TARGET_FIX_AND_CONTINUE
20717 #define TARGET_FIX_AND_CONTINUE 0
20720 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
20721 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
20722 #define LAST_SAVRES_REGISTER 31
20723 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
20734 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
20736 /* Temporary holding space for an out-of-line register save/restore
20738 static char savres_routine_name
[30];
20740 /* Return the name for an out-of-line register save/restore routine.
20741 We are saving/restoring GPRs if GPR is true. */
20744 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
20746 const char *prefix
= "";
20747 const char *suffix
= "";
20749 /* Different targets are supposed to define
20750 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
20751 routine name could be defined with:
20753 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
20755 This is a nice idea in practice, but in reality, things are
20756 complicated in several ways:
20758 - ELF targets have save/restore routines for GPRs.
20760 - SPE targets use different prefixes for 32/64-bit registers, and
20761 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
20763 - PPC64 ELF targets have routines for save/restore of GPRs that
20764 differ in what they do with the link register, so having a set
20765 prefix doesn't work. (We only use one of the save routines at
20766 the moment, though.)
20768 - PPC32 elf targets have "exit" versions of the restore routines
20769 that restore the link register and can save some extra space.
20770 These require an extra suffix. (There are also "tail" versions
20771 of the restore routines and "GOT" versions of the save routines,
20772 but we don't generate those at present. Same problems apply,
20775 We deal with all this by synthesizing our own prefix/suffix and
20776 using that for the simple sprintf call shown above. */
20779 /* No floating point saves on the SPE. */
20780 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
20782 if ((sel
& SAVRES_SAVE
))
20783 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
20785 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
20787 if ((sel
& SAVRES_LR
))
20790 else if (DEFAULT_ABI
== ABI_V4
)
20795 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
20796 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
20797 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
20798 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
20799 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
20800 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
20804 if ((sel
& SAVRES_LR
))
20807 else if (DEFAULT_ABI
== ABI_AIX
)
20809 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
20810 /* No out-of-line save/restore routines for GPRs on AIX. */
20811 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
20815 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
20816 prefix
= ((sel
& SAVRES_SAVE
)
20817 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
20818 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
20819 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
20821 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
20822 if ((sel
& SAVRES_LR
))
20823 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
20827 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
20828 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
20831 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
20832 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
20837 if (DEFAULT_ABI
== ABI_DARWIN
)
20839 /* The Darwin approach is (slightly) different, in order to be
20840 compatible with code generated by the system toolchain. There is a
20841 single symbol for the start of save sequence, and the code here
20842 embeds an offset into that code on the basis of the first register
20844 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
20845 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
20846 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
20847 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
20848 (regno
- 13) * 4, prefix
, regno
);
20849 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
20850 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
20851 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
20852 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
20853 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
20854 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
20859 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
20861 return savres_routine_name
;
20864 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
20865 We are saving/restoring GPRs if GPR is true. */
20868 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
20870 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
20871 ? info
->first_gp_reg_save
20872 : (sel
& SAVRES_REG
) == SAVRES_FPR
20873 ? info
->first_fp_reg_save
- 32
20874 : (sel
& SAVRES_REG
) == SAVRES_VR
20875 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
20880 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
20881 versions of the gpr routines. */
20882 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
20883 && info
->spe_64bit_regs_used
)
20884 select
^= SAVRES_FPR
^ SAVRES_GPR
;
20886 /* Don't generate bogus routine names. */
20887 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
20888 && regno
<= LAST_SAVRES_REGISTER
20889 && select
>= 0 && select
<= 12);
20891 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
20897 name
= rs6000_savres_routine_name (info
, regno
, sel
);
20899 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
20900 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
20901 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
20907 /* Emit a sequence of insns, including a stack tie if needed, for
20908 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
20909 reset the stack pointer, but move the base of the frame into
20910 reg UPDT_REGNO for use by out-of-line register restore routines. */
20913 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
20914 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
20915 unsigned updt_regno
)
20919 /* This blockage is needed so that sched doesn't decide to move
20920 the sp change before the register restores. */
20921 if (DEFAULT_ABI
== ABI_V4
20923 && info
->spe_64bit_regs_used
!= 0
20924 && info
->first_gp_reg_save
!= 32))
20925 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
20927 /* If we are restoring registers out-of-line, we will be using the
20928 "exit" variants of the restore routines, which will reset the
20929 stack for us. But we do need to point updt_reg into the
20930 right place for those routines. */
20931 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
20933 if (frame_off
!= 0)
20934 return emit_insn (gen_add3_insn (updt_reg_rtx
,
20935 frame_reg_rtx
, GEN_INT (frame_off
)));
20936 else if (REGNO (frame_reg_rtx
) != updt_regno
)
20937 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
20942 /* Return the register number used as a pointer by out-of-line
20943 save/restore functions. */
20945 static inline unsigned
20946 ptr_regno_for_savres (int sel
)
20948 if (DEFAULT_ABI
== ABI_AIX
)
20949 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
20950 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
20953 /* Construct a parallel rtx describing the effect of a call to an
20954 out-of-line register save/restore routine, and emit the insn
20955 or jump_insn as appropriate. */
20958 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
20959 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
20960 enum machine_mode reg_mode
, int sel
)
20963 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
20964 int reg_size
= GET_MODE_SIZE (reg_mode
);
20970 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
20971 ? info
->first_gp_reg_save
20972 : (sel
& SAVRES_REG
) == SAVRES_FPR
20973 ? info
->first_fp_reg_save
20974 : (sel
& SAVRES_REG
) == SAVRES_VR
20975 ? info
->first_altivec_reg_save
20977 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
20979 : (sel
& SAVRES_REG
) == SAVRES_FPR
20981 : (sel
& SAVRES_REG
) == SAVRES_VR
20982 ? LAST_ALTIVEC_REGNO
+ 1
20984 n_regs
= end_reg
- start_reg
;
20985 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
20986 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
20989 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
20990 RTVEC_ELT (p
, offset
++) = ret_rtx
;
20992 RTVEC_ELT (p
, offset
++)
20993 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
20995 sym
= rs6000_savres_routine_sym (info
, sel
);
20996 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
20998 use_reg
= ptr_regno_for_savres (sel
);
20999 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21001 /* Vector regs are saved/restored using [reg+reg] addressing. */
21002 RTVEC_ELT (p
, offset
++)
21003 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21004 RTVEC_ELT (p
, offset
++)
21005 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
21008 RTVEC_ELT (p
, offset
++)
21009 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21011 for (i
= 0; i
< end_reg
- start_reg
; i
++)
21012 RTVEC_ELT (p
, i
+ offset
)
21013 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
21014 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
21015 (sel
& SAVRES_SAVE
) != 0);
21017 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21018 RTVEC_ELT (p
, i
+ offset
)
21019 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
21021 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
21023 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21025 insn
= emit_jump_insn (par
);
21026 JUMP_LABEL (insn
) = ret_rtx
;
21029 insn
= emit_insn (par
);
21033 /* Determine whether the gp REG is really used. */
21036 rs6000_reg_live_or_pic_offset_p (int reg
)
21038 /* If the function calls eh_return, claim used all the registers that would
21039 be checked for liveness otherwise. This is required for the PIC offset
21040 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
21041 register allocation purposes in this case. */
21043 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
21044 && (!call_used_regs
[reg
]
21045 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
21046 && !TARGET_SINGLE_PIC_BASE
21047 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
21048 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
21049 && !TARGET_SINGLE_PIC_BASE
21050 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
21051 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
21054 /* Emit function prologue as insns. */
21057 rs6000_emit_prologue (void)
21059 rs6000_stack_t
*info
= rs6000_stack_info ();
21060 enum machine_mode reg_mode
= Pmode
;
21061 int reg_size
= TARGET_32BIT
? 4 : 8;
21062 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21063 rtx frame_reg_rtx
= sp_reg_rtx
;
21064 unsigned int cr_save_regno
;
21065 rtx cr_save_rtx
= NULL_RTX
;
21068 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
21069 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
21070 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
21071 /* Offset to top of frame for frame_reg and sp respectively. */
21072 HOST_WIDE_INT frame_off
= 0;
21073 HOST_WIDE_INT sp_off
= 0;
21075 #ifdef ENABLE_CHECKING
21076 /* Track and check usage of r0, r11, r12. */
21077 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
21078 #define START_USE(R) do \
21080 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
21081 reg_inuse |= 1 << (R); \
21083 #define END_USE(R) do \
21085 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
21086 reg_inuse &= ~(1 << (R)); \
21088 #define NOT_INUSE(R) do \
21090 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
21093 #define START_USE(R) do {} while (0)
21094 #define END_USE(R) do {} while (0)
21095 #define NOT_INUSE(R) do {} while (0)
21098 if (flag_stack_usage_info
)
21099 current_function_static_stack_size
= info
->total_size
;
21101 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& info
->total_size
)
21102 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, info
->total_size
);
21104 if (TARGET_FIX_AND_CONTINUE
)
21106 /* gdb on darwin arranges to forward a function from the old
21107 address by modifying the first 5 instructions of the function
21108 to branch to the overriding function. This is necessary to
21109 permit function pointers that point to the old function to
21110 actually forward to the new function. */
21111 emit_insn (gen_nop ());
21112 emit_insn (gen_nop ());
21113 emit_insn (gen_nop ());
21114 emit_insn (gen_nop ());
21115 emit_insn (gen_nop ());
21118 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
21120 reg_mode
= V2SImode
;
21124 /* Handle world saves specially here. */
21125 if (WORLD_SAVE_P (info
))
21132 /* save_world expects lr in r0. */
21133 reg0
= gen_rtx_REG (Pmode
, 0);
21134 if (info
->lr_save_p
)
21136 insn
= emit_move_insn (reg0
,
21137 gen_rtx_REG (Pmode
, LR_REGNO
));
21138 RTX_FRAME_RELATED_P (insn
) = 1;
21141 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
21142 assumptions about the offsets of various bits of the stack
21144 gcc_assert (info
->gp_save_offset
== -220
21145 && info
->fp_save_offset
== -144
21146 && info
->lr_save_offset
== 8
21147 && info
->cr_save_offset
== 4
21150 && (!crtl
->calls_eh_return
21151 || info
->ehrd_offset
== -432)
21152 && info
->vrsave_save_offset
== -224
21153 && info
->altivec_save_offset
== -416);
21155 treg
= gen_rtx_REG (SImode
, 11);
21156 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
21158 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
21159 in R11. It also clobbers R12, so beware! */
21161 /* Preserve CR2 for save_world prologues */
21163 sz
+= 32 - info
->first_gp_reg_save
;
21164 sz
+= 64 - info
->first_fp_reg_save
;
21165 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
21166 p
= rtvec_alloc (sz
);
21168 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
21169 gen_rtx_REG (SImode
,
21171 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
21172 gen_rtx_SYMBOL_REF (Pmode
,
21174 /* We do floats first so that the instruction pattern matches
21176 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21178 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
21180 info
->first_fp_reg_save
+ i
),
21182 info
->fp_save_offset
+ frame_off
+ 8 * i
);
21183 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
21185 = gen_frame_store (gen_rtx_REG (V4SImode
,
21186 info
->first_altivec_reg_save
+ i
),
21188 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
21189 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21191 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21193 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
21195 /* CR register traditionally saved as CR2. */
21197 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
21198 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
21199 /* Explain about use of R0. */
21200 if (info
->lr_save_p
)
21202 = gen_frame_store (reg0
,
21203 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
21204 /* Explain what happens to the stack pointer. */
21206 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
21207 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
21210 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21211 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21212 treg
, GEN_INT (-info
->total_size
));
21213 sp_off
= frame_off
= info
->total_size
;
21216 strategy
= info
->savres_strategy
;
21218 /* For V.4, update stack before we do any saving and set back pointer. */
21219 if (! WORLD_SAVE_P (info
)
21221 && (DEFAULT_ABI
== ABI_V4
21222 || crtl
->calls_eh_return
))
21224 bool need_r11
= (TARGET_SPE
21225 ? (!(strategy
& SAVE_INLINE_GPRS
)
21226 && info
->spe_64bit_regs_used
== 0)
21227 : (!(strategy
& SAVE_INLINE_FPRS
)
21228 || !(strategy
& SAVE_INLINE_GPRS
)
21229 || !(strategy
& SAVE_INLINE_VRS
)));
21230 int ptr_regno
= -1;
21231 rtx ptr_reg
= NULL_RTX
;
21234 if (info
->total_size
< 32767)
21235 frame_off
= info
->total_size
;
21238 else if (info
->cr_save_p
21240 || info
->first_fp_reg_save
< 64
21241 || info
->first_gp_reg_save
< 32
21242 || info
->altivec_size
!= 0
21243 || info
->vrsave_mask
!= 0
21244 || crtl
->calls_eh_return
)
21248 /* The prologue won't be saving any regs so there is no need
21249 to set up a frame register to access any frame save area.
21250 We also won't be using frame_off anywhere below, but set
21251 the correct value anyway to protect against future
21252 changes to this function. */
21253 frame_off
= info
->total_size
;
21255 if (ptr_regno
!= -1)
21257 /* Set up the frame offset to that needed by the first
21258 out-of-line save function. */
21259 START_USE (ptr_regno
);
21260 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21261 frame_reg_rtx
= ptr_reg
;
21262 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
21263 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
21264 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
21265 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
21266 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
21267 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
21268 frame_off
= -ptr_off
;
21270 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
21271 sp_off
= info
->total_size
;
21272 if (frame_reg_rtx
!= sp_reg_rtx
)
21273 rs6000_emit_stack_tie (frame_reg_rtx
, false);
21276 /* If we use the link register, get it into r0. */
21277 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
21279 rtx addr
, reg
, mem
;
21281 reg
= gen_rtx_REG (Pmode
, 0);
21283 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
21284 RTX_FRAME_RELATED_P (insn
) = 1;
21286 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
21287 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
21289 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
21290 GEN_INT (info
->lr_save_offset
+ frame_off
));
21291 mem
= gen_rtx_MEM (Pmode
, addr
);
21292 /* This should not be of rs6000_sr_alias_set, because of
21293 __builtin_return_address. */
21295 insn
= emit_move_insn (mem
, reg
);
21296 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21297 NULL_RTX
, NULL_RTX
);
21302 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
21303 r12 will be needed by out-of-line gpr restore. */
21304 cr_save_regno
= (DEFAULT_ABI
== ABI_AIX
21305 && !(strategy
& (SAVE_INLINE_GPRS
21306 | SAVE_NOINLINE_GPRS_SAVES_LR
))
21308 if (!WORLD_SAVE_P (info
)
21310 && REGNO (frame_reg_rtx
) != cr_save_regno
21311 && !(using_static_chain_p
&& cr_save_regno
== 11))
21315 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
21316 START_USE (cr_save_regno
);
21317 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
21318 RTX_FRAME_RELATED_P (insn
) = 1;
21319 /* Now, there's no way that dwarf2out_frame_debug_expr is going
21320 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
21321 But that's OK. All we have to do is specify that _one_ condition
21322 code register is saved in this stack slot. The thrower's epilogue
21323 will then restore all the call-saved registers.
21324 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
21325 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
21326 gen_rtx_REG (SImode
, CR2_REGNO
));
21327 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
21330 /* Do any required saving of fpr's. If only one or two to save, do
21331 it ourselves. Otherwise, call function. */
21332 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
21335 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21336 if (save_reg_p (info
->first_fp_reg_save
+ i
))
21337 emit_frame_save (frame_reg_rtx
,
21338 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
21339 ? DFmode
: SFmode
),
21340 info
->first_fp_reg_save
+ i
,
21341 info
->fp_save_offset
+ frame_off
+ 8 * i
,
21342 sp_off
- frame_off
);
21344 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
21346 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
21347 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21348 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
21349 rtx ptr_reg
= frame_reg_rtx
;
21351 if (REGNO (frame_reg_rtx
) == ptr_regno
)
21352 gcc_checking_assert (frame_off
== 0);
21355 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21356 NOT_INUSE (ptr_regno
);
21357 emit_insn (gen_add3_insn (ptr_reg
,
21358 frame_reg_rtx
, GEN_INT (frame_off
)));
21360 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
21361 info
->fp_save_offset
,
21362 info
->lr_save_offset
,
21364 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
21365 NULL_RTX
, NULL_RTX
);
21370 /* Save GPRs. This is done as a PARALLEL if we are using
21371 the store-multiple instructions. */
21372 if (!WORLD_SAVE_P (info
)
21374 && info
->spe_64bit_regs_used
!= 0
21375 && info
->first_gp_reg_save
!= 32)
21378 rtx spe_save_area_ptr
;
21379 HOST_WIDE_INT save_off
;
21380 int ool_adjust
= 0;
21382 /* Determine whether we can address all of the registers that need
21383 to be saved with an offset from frame_reg_rtx that fits in
21384 the small const field for SPE memory instructions. */
21385 int spe_regs_addressable
21386 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
21387 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
21388 && (strategy
& SAVE_INLINE_GPRS
));
21390 if (spe_regs_addressable
)
21392 spe_save_area_ptr
= frame_reg_rtx
;
21393 save_off
= frame_off
;
21397 /* Make r11 point to the start of the SPE save area. We need
21398 to be careful here if r11 is holding the static chain. If
21399 it is, then temporarily save it in r0. */
21400 HOST_WIDE_INT offset
;
21402 if (!(strategy
& SAVE_INLINE_GPRS
))
21403 ool_adjust
= 8 * (info
->first_gp_reg_save
21404 - (FIRST_SAVRES_REGISTER
+ 1));
21405 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
21406 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
21407 save_off
= frame_off
- offset
;
21409 if (using_static_chain_p
)
21411 rtx r0
= gen_rtx_REG (Pmode
, 0);
21414 gcc_assert (info
->first_gp_reg_save
> 11);
21416 emit_move_insn (r0
, spe_save_area_ptr
);
21418 else if (REGNO (frame_reg_rtx
) != 11)
21421 emit_insn (gen_addsi3 (spe_save_area_ptr
,
21422 frame_reg_rtx
, GEN_INT (offset
)));
21423 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
21424 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
21427 if ((strategy
& SAVE_INLINE_GPRS
))
21429 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21430 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21431 emit_frame_save (spe_save_area_ptr
, reg_mode
,
21432 info
->first_gp_reg_save
+ i
,
21433 (info
->spe_gp_save_offset
+ save_off
21435 sp_off
- save_off
);
21439 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
21440 info
->spe_gp_save_offset
+ save_off
,
21442 SAVRES_SAVE
| SAVRES_GPR
);
21444 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
21445 NULL_RTX
, NULL_RTX
);
21448 /* Move the static chain pointer back. */
21449 if (!spe_regs_addressable
)
21451 if (using_static_chain_p
)
21453 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
21456 else if (REGNO (frame_reg_rtx
) != 11)
21460 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
21462 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
21463 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
21464 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
21465 rtx ptr_reg
= frame_reg_rtx
;
21466 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
21467 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
21471 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21473 /* Need to adjust r11 (r12) if we saved any FPRs. */
21474 if (end_save
+ frame_off
!= 0)
21476 rtx offset
= GEN_INT (end_save
+ frame_off
);
21479 frame_off
= -end_save
;
21481 NOT_INUSE (ptr_regno
);
21482 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
21484 else if (!ptr_set_up
)
21486 NOT_INUSE (ptr_regno
);
21487 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21489 ptr_off
= -end_save
;
21490 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
21491 info
->gp_save_offset
+ ptr_off
,
21492 info
->lr_save_offset
+ ptr_off
,
21494 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
21495 NULL_RTX
, NULL_RTX
);
21499 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
21503 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
21504 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21506 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21508 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
21509 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21510 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21511 NULL_RTX
, NULL_RTX
);
21513 else if (!WORLD_SAVE_P (info
))
21516 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21517 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21518 emit_frame_save (frame_reg_rtx
, reg_mode
,
21519 info
->first_gp_reg_save
+ i
,
21520 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
21521 sp_off
- frame_off
);
21524 if (crtl
->calls_eh_return
)
21531 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
21532 if (regno
== INVALID_REGNUM
)
21536 p
= rtvec_alloc (i
);
21540 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
21541 if (regno
== INVALID_REGNUM
)
21545 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
21547 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
21548 RTVEC_ELT (p
, i
) = insn
;
21549 RTX_FRAME_RELATED_P (insn
) = 1;
21552 insn
= emit_insn (gen_blockage ());
21553 RTX_FRAME_RELATED_P (insn
) = 1;
21554 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
21557 /* In AIX ABI we need to make sure r2 is really saved. */
21558 if (TARGET_AIX
&& crtl
->calls_eh_return
)
21560 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
21561 rtx save_insn
, join_insn
, note
;
21562 long toc_restore_insn
;
21564 tmp_reg
= gen_rtx_REG (Pmode
, 11);
21565 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
21566 if (using_static_chain_p
)
21569 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
21573 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
21574 /* Peek at instruction to which this function returns. If it's
21575 restoring r2, then we know we've already saved r2. We can't
21576 unconditionally save r2 because the value we have will already
21577 be updated if we arrived at this function via a plt call or
21578 toc adjusting stub. */
21579 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
21580 toc_restore_insn
= TARGET_32BIT
? 0x80410014 : 0xE8410028;
21581 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
21582 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
21583 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
21584 validate_condition_mode (EQ
, CCUNSmode
);
21585 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
21586 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
21587 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
21588 toc_save_done
= gen_label_rtx ();
21589 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
21590 gen_rtx_EQ (VOIDmode
, compare_result
,
21592 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
21594 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
21595 JUMP_LABEL (jump
) = toc_save_done
;
21596 LABEL_NUSES (toc_save_done
) += 1;
21598 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
21599 TOC_REGNUM
, frame_off
+ 5 * reg_size
,
21600 sp_off
- frame_off
);
21602 emit_label (toc_save_done
);
21604 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
21605 have a CFG that has different saves along different paths.
21606 Move the note to a dummy blockage insn, which describes that
21607 R2 is unconditionally saved after the label. */
21608 /* ??? An alternate representation might be a special insn pattern
21609 containing both the branch and the store. That might let the
21610 code that minimizes the number of DW_CFA_advance opcodes better
21611 freedom in placing the annotations. */
21612 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
21614 remove_note (save_insn
, note
);
21616 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
21617 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
21618 RTX_FRAME_RELATED_P (save_insn
) = 0;
21620 join_insn
= emit_insn (gen_blockage ());
21621 REG_NOTES (join_insn
) = note
;
21622 RTX_FRAME_RELATED_P (join_insn
) = 1;
21624 if (using_static_chain_p
)
21626 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
21633 /* Save CR if we use any that must be preserved. */
21634 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
21636 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
21637 GEN_INT (info
->cr_save_offset
+ frame_off
));
21638 rtx mem
= gen_frame_mem (SImode
, addr
);
21639 /* See the large comment above about why CR2_REGNO is used. */
21640 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
21642 /* If we didn't copy cr before, do so now using r0. */
21643 if (cr_save_rtx
== NULL_RTX
)
21648 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
21649 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
21650 RTX_FRAME_RELATED_P (insn
) = 1;
21651 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
21652 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
21654 insn
= emit_move_insn (mem
, cr_save_rtx
);
21655 END_USE (REGNO (cr_save_rtx
));
21657 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21658 NULL_RTX
, NULL_RTX
);
21661 /* Update stack and set back pointer unless this is V.4,
21662 for which it was done previously. */
21663 if (!WORLD_SAVE_P (info
) && info
->push_p
21664 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
21666 rtx ptr_reg
= NULL
;
21669 /* If saving altivec regs we need to be able to address all save
21670 locations using a 16-bit offset. */
21671 if ((strategy
& SAVE_INLINE_VRS
) == 0
21672 || (info
->altivec_size
!= 0
21673 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
21674 + info
->total_size
- frame_off
) > 32767)
21675 || (info
->vrsave_size
!= 0
21676 && (info
->vrsave_save_offset
21677 + info
->total_size
- frame_off
) > 32767))
21679 int sel
= SAVRES_SAVE
| SAVRES_VR
;
21680 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
21682 if (using_static_chain_p
21683 && ptr_regno
== STATIC_CHAIN_REGNUM
)
21685 if (REGNO (frame_reg_rtx
) != ptr_regno
)
21686 START_USE (ptr_regno
);
21687 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21688 frame_reg_rtx
= ptr_reg
;
21689 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
21690 frame_off
= -ptr_off
;
21692 else if (REGNO (frame_reg_rtx
) == 1)
21693 frame_off
= info
->total_size
;
21694 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
21695 sp_off
= info
->total_size
;
21696 if (frame_reg_rtx
!= sp_reg_rtx
)
21697 rs6000_emit_stack_tie (frame_reg_rtx
, false);
21700 /* Set frame pointer, if needed. */
21701 if (frame_pointer_needed
)
21703 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
21705 RTX_FRAME_RELATED_P (insn
) = 1;
21708 /* Save AltiVec registers if needed. Save here because the red zone does
21709 not always include AltiVec registers. */
21710 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
21711 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
21713 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
21715 /* Oddly, the vector save/restore functions point r0 at the end
21716 of the save area, then use r11 or r12 to load offsets for
21717 [reg+reg] addressing. */
21718 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
21719 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
21720 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
21722 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
21724 if (end_save
+ frame_off
!= 0)
21726 rtx offset
= GEN_INT (end_save
+ frame_off
);
21728 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
21731 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21733 ptr_off
= -end_save
;
21734 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
21735 info
->altivec_save_offset
+ ptr_off
,
21736 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
21737 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
21738 NULL_RTX
, NULL_RTX
);
21739 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
21741 /* The oddity mentioned above clobbered our frame reg. */
21742 emit_move_insn (frame_reg_rtx
, ptr_reg
);
21743 frame_off
= ptr_off
;
21746 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
21747 && info
->altivec_size
!= 0)
21751 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21752 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21754 rtx areg
, savereg
, mem
;
21757 offset
= (info
->altivec_save_offset
+ frame_off
21758 + 16 * (i
- info
->first_altivec_reg_save
));
21760 savereg
= gen_rtx_REG (V4SImode
, i
);
21763 areg
= gen_rtx_REG (Pmode
, 0);
21764 emit_move_insn (areg
, GEN_INT (offset
));
21766 /* AltiVec addressing mode is [reg+reg]. */
21767 mem
= gen_frame_mem (V4SImode
,
21768 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
21770 insn
= emit_move_insn (mem
, savereg
);
21772 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21773 areg
, GEN_INT (offset
));
21777 /* VRSAVE is a bit vector representing which AltiVec registers
21778 are used. The OS uses this to determine which vector
21779 registers to save on a context switch. We need to save
21780 VRSAVE on the stack frame, add whatever AltiVec registers we
21781 used in this function, and do the corresponding magic in the
21784 if (!WORLD_SAVE_P (info
)
21786 && TARGET_ALTIVEC_VRSAVE
21787 && info
->vrsave_mask
!= 0)
21793 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
21794 be using r12 as frame_reg_rtx and r11 as the static chain
21795 pointer for nested functions. */
21797 if (DEFAULT_ABI
== ABI_AIX
&& !using_static_chain_p
)
21799 else if (REGNO (frame_reg_rtx
) == 12)
21802 if (using_static_chain_p
)
21806 NOT_INUSE (save_regno
);
21807 reg
= gen_rtx_REG (SImode
, save_regno
);
21808 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
21810 emit_insn (gen_get_vrsave_internal (reg
));
21812 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
21815 offset
= info
->vrsave_save_offset
+ frame_off
;
21816 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
21818 /* Include the registers in the mask. */
21819 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
21821 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
21824 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
21825 if (!TARGET_SINGLE_PIC_BASE
21826 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
21827 || (DEFAULT_ABI
== ABI_V4
21828 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
21829 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
21831 /* If emit_load_toc_table will use the link register, we need to save
21832 it. We use R12 for this purpose because emit_load_toc_table
21833 can use register 0. This allows us to use a plain 'blr' to return
21834 from the procedure more often. */
21835 int save_LR_around_toc_setup
= (TARGET_ELF
21836 && DEFAULT_ABI
!= ABI_AIX
21838 && ! info
->lr_save_p
21839 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
21840 if (save_LR_around_toc_setup
)
21842 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
21843 rtx tmp
= gen_rtx_REG (Pmode
, 12);
21845 insn
= emit_move_insn (tmp
, lr
);
21846 RTX_FRAME_RELATED_P (insn
) = 1;
21848 rs6000_emit_load_toc_table (TRUE
);
21850 insn
= emit_move_insn (lr
, tmp
);
21851 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
21852 RTX_FRAME_RELATED_P (insn
) = 1;
21855 rs6000_emit_load_toc_table (TRUE
);
21859 if (!TARGET_SINGLE_PIC_BASE
21860 && DEFAULT_ABI
== ABI_DARWIN
21861 && flag_pic
&& crtl
->uses_pic_offset_table
)
21863 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
21864 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
21866 /* Save and restore LR locally around this call (in R0). */
21867 if (!info
->lr_save_p
)
21868 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
21870 emit_insn (gen_load_macho_picbase (src
));
21872 emit_move_insn (gen_rtx_REG (Pmode
,
21873 RS6000_PIC_OFFSET_TABLE_REGNUM
),
21876 if (!info
->lr_save_p
)
21877 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
21881 /* If we need to, save the TOC register after doing the stack setup.
21882 Do not emit eh frame info for this save. The unwinder wants info,
21883 conceptually attached to instructions in this function, about
21884 register values in the caller of this function. This R2 may have
21885 already been changed from the value in the caller.
21886 We don't attempt to write accurate DWARF EH frame info for R2
21887 because code emitted by gcc for a (non-pointer) function call
21888 doesn't save and restore R2. Instead, R2 is managed out-of-line
21889 by a linker generated plt call stub when the function resides in
21890 a shared library. This behaviour is costly to describe in DWARF,
21891 both in terms of the size of DWARF info and the time taken in the
21892 unwinder to interpret it. R2 changes, apart from the
21893 calls_eh_return case earlier in this function, are handled by
21894 linux-unwind.h frob_update_context. */
21895 if (rs6000_save_toc_in_prologue_p ())
21897 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
21898 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, 5 * reg_size
));
21902 /* Write function prologue. */
21905 rs6000_output_function_prologue (FILE *file
,
21906 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
21908 rs6000_stack_t
*info
= rs6000_stack_info ();
21910 if (TARGET_DEBUG_STACK
)
21911 debug_stack_info (info
);
21913 /* Write .extern for any function we will call to save and restore
21915 if (info
->first_fp_reg_save
< 64
21920 int regno
= info
->first_fp_reg_save
- 32;
21922 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
21924 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
21925 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21926 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21927 fprintf (file
, "\t.extern %s\n", name
);
21929 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
21931 bool lr
= (info
->savres_strategy
21932 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
21933 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21934 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21935 fprintf (file
, "\t.extern %s\n", name
);
21939 rs6000_pic_labelno
++;
21942 /* Non-zero if vmx regs are restored before the frame pop, zero if
21943 we restore after the pop when possible. */
21944 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
21946 /* Restoring cr is a two step process: loading a reg from the frame
21947 save, then moving the reg to cr. For ABI_V4 we must let the
21948 unwinder know that the stack location is no longer valid at or
21949 before the stack deallocation, but we can't emit a cfa_restore for
21950 cr at the stack deallocation like we do for other registers.
21951 The trouble is that it is possible for the move to cr to be
21952 scheduled after the stack deallocation. So say exactly where cr
21953 is located on each of the two insns. */
21956 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
21958 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
21959 rtx reg
= gen_rtx_REG (SImode
, regno
);
21960 rtx insn
= emit_move_insn (reg
, mem
);
21962 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
21964 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
21965 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
21967 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
21968 RTX_FRAME_RELATED_P (insn
) = 1;
21973 /* Reload CR from REG. */
21976 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
21981 if (using_mfcr_multiple
)
21983 for (i
= 0; i
< 8; i
++)
21984 if (save_reg_p (CR0_REGNO
+ i
))
21986 gcc_assert (count
);
21989 if (using_mfcr_multiple
&& count
> 1)
21994 p
= rtvec_alloc (count
);
21997 for (i
= 0; i
< 8; i
++)
21998 if (save_reg_p (CR0_REGNO
+ i
))
22000 rtvec r
= rtvec_alloc (2);
22001 RTVEC_ELT (r
, 0) = reg
;
22002 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
22003 RTVEC_ELT (p
, ndx
) =
22004 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
22005 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
22008 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22009 gcc_assert (ndx
== count
);
22012 for (i
= 0; i
< 8; i
++)
22013 if (save_reg_p (CR0_REGNO
+ i
))
22014 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
22017 if (!exit_func
&& (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
22019 rtx insn
= get_last_insn ();
22020 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
22022 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
22023 RTX_FRAME_RELATED_P (insn
) = 1;
22027 /* Like cr, the move to lr instruction can be scheduled after the
22028 stack deallocation, but unlike cr, its stack frame save is still
22029 valid. So we only need to emit the cfa_restore on the correct
22033 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
22035 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
22036 rtx reg
= gen_rtx_REG (Pmode
, regno
);
22038 emit_move_insn (reg
, mem
);
22042 restore_saved_lr (int regno
, bool exit_func
)
22044 rtx reg
= gen_rtx_REG (Pmode
, regno
);
22045 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22046 rtx insn
= emit_move_insn (lr
, reg
);
22048 if (!exit_func
&& flag_shrink_wrap
)
22050 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
22051 RTX_FRAME_RELATED_P (insn
) = 1;
22056 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
22058 if (info
->cr_save_p
)
22059 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
22060 gen_rtx_REG (SImode
, CR2_REGNO
),
22062 if (info
->lr_save_p
)
22063 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
22064 gen_rtx_REG (Pmode
, LR_REGNO
),
22066 return cfa_restores
;
22069 /* Return true if OFFSET from stack pointer can be clobbered by signals.
22070 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
22071 below stack pointer not cloberred by signals. */
22074 offset_below_red_zone_p (HOST_WIDE_INT offset
)
22076 return offset
< (DEFAULT_ABI
== ABI_V4
22078 : TARGET_32BIT
? -220 : -288);
22081 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
22084 emit_cfa_restores (rtx cfa_restores
)
22086 rtx insn
= get_last_insn ();
22087 rtx
*loc
= ®_NOTES (insn
);
22090 loc
= &XEXP (*loc
, 1);
22091 *loc
= cfa_restores
;
22092 RTX_FRAME_RELATED_P (insn
) = 1;
22095 /* Emit function epilogue as insns. */
22098 rs6000_emit_epilogue (int sibcall
)
22100 rs6000_stack_t
*info
;
22101 int restoring_GPRs_inline
;
22102 int restoring_FPRs_inline
;
22103 int using_load_multiple
;
22104 int using_mtcr_multiple
;
22105 int use_backchain_to_restore_sp
;
22108 HOST_WIDE_INT frame_off
= 0;
22109 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
22110 rtx frame_reg_rtx
= sp_reg_rtx
;
22111 rtx cfa_restores
= NULL_RTX
;
22113 rtx cr_save_reg
= NULL_RTX
;
22114 enum machine_mode reg_mode
= Pmode
;
22115 int reg_size
= TARGET_32BIT
? 4 : 8;
22118 unsigned ptr_regno
;
22120 info
= rs6000_stack_info ();
22122 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22124 reg_mode
= V2SImode
;
22128 strategy
= info
->savres_strategy
;
22129 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
22130 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
22131 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
22132 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
22133 || rs6000_cpu
== PROCESSOR_PPC603
22134 || rs6000_cpu
== PROCESSOR_PPC750
22136 /* Restore via the backchain when we have a large frame, since this
22137 is more efficient than an addis, addi pair. The second condition
22138 here will not trigger at the moment; We don't actually need a
22139 frame pointer for alloca, but the generic parts of the compiler
22140 give us one anyway. */
22141 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
22142 || (cfun
->calls_alloca
22143 && !frame_pointer_needed
));
22144 restore_lr
= (info
->lr_save_p
22145 && (restoring_FPRs_inline
22146 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
22147 && (restoring_GPRs_inline
22148 || info
->first_fp_reg_save
< 64));
22150 if (WORLD_SAVE_P (info
))
22154 const char *alloc_rname
;
22157 /* eh_rest_world_r10 will return to the location saved in the LR
22158 stack slot (which is not likely to be our caller.)
22159 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
22160 rest_world is similar, except any R10 parameter is ignored.
22161 The exception-handling stuff that was here in 2.95 is no
22162 longer necessary. */
22166 + 32 - info
->first_gp_reg_save
22167 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
22168 + 63 + 1 - info
->first_fp_reg_save
);
22170 strcpy (rname
, ((crtl
->calls_eh_return
) ?
22171 "*eh_rest_world_r10" : "*rest_world"));
22172 alloc_rname
= ggc_strdup (rname
);
22175 RTVEC_ELT (p
, j
++) = ret_rtx
;
22176 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22177 gen_rtx_REG (Pmode
,
22180 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
22181 /* The instruction pattern requires a clobber here;
22182 it is shared with the restVEC helper. */
22184 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
22187 /* CR register traditionally saved as CR2. */
22188 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
22190 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
22191 if (flag_shrink_wrap
)
22193 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
22194 gen_rtx_REG (Pmode
, LR_REGNO
),
22196 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22200 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22202 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
22204 = gen_frame_load (reg
,
22205 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
22206 if (flag_shrink_wrap
)
22207 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22209 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22211 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
22213 = gen_frame_load (reg
,
22214 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
22215 if (flag_shrink_wrap
)
22216 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22218 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
22220 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22221 ? DFmode
: SFmode
),
22222 info
->first_fp_reg_save
+ i
);
22224 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
22225 if (flag_shrink_wrap
)
22226 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22229 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
22231 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
22233 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
22235 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
22237 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
22238 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22240 if (flag_shrink_wrap
)
22242 REG_NOTES (insn
) = cfa_restores
;
22243 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
22244 RTX_FRAME_RELATED_P (insn
) = 1;
22249 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
22251 frame_off
= info
->total_size
;
22253 /* Restore AltiVec registers if we must do so before adjusting the
22255 if (TARGET_ALTIVEC_ABI
22256 && info
->altivec_size
!= 0
22257 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22258 || (DEFAULT_ABI
!= ABI_V4
22259 && offset_below_red_zone_p (info
->altivec_save_offset
))))
22262 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
22264 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
22265 if (use_backchain_to_restore_sp
)
22267 int frame_regno
= 11;
22269 if ((strategy
& REST_INLINE_VRS
) == 0)
22271 /* Of r11 and r12, select the one not clobbered by an
22272 out-of-line restore function for the frame register. */
22273 frame_regno
= 11 + 12 - scratch_regno
;
22275 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
22276 emit_move_insn (frame_reg_rtx
,
22277 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
22280 else if (frame_pointer_needed
)
22281 frame_reg_rtx
= hard_frame_pointer_rtx
;
22283 if ((strategy
& REST_INLINE_VRS
) == 0)
22285 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22287 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22288 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22290 if (end_save
+ frame_off
!= 0)
22292 rtx offset
= GEN_INT (end_save
+ frame_off
);
22294 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22297 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22299 ptr_off
= -end_save
;
22300 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22301 info
->altivec_save_offset
+ ptr_off
,
22302 0, V4SImode
, SAVRES_VR
);
22306 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22307 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22309 rtx addr
, areg
, mem
, reg
;
22311 areg
= gen_rtx_REG (Pmode
, 0);
22313 (areg
, GEN_INT (info
->altivec_save_offset
22315 + 16 * (i
- info
->first_altivec_reg_save
)));
22317 /* AltiVec addressing mode is [reg+reg]. */
22318 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
22319 mem
= gen_frame_mem (V4SImode
, addr
);
22321 reg
= gen_rtx_REG (V4SImode
, i
);
22322 emit_move_insn (reg
, mem
);
22326 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22327 if (((strategy
& REST_INLINE_VRS
) == 0
22328 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
22329 && (flag_shrink_wrap
22330 || (offset_below_red_zone_p
22331 (info
->altivec_save_offset
22332 + 16 * (i
- info
->first_altivec_reg_save
)))))
22334 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22335 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22339 /* Restore VRSAVE if we must do so before adjusting the stack. */
22341 && TARGET_ALTIVEC_VRSAVE
22342 && info
->vrsave_mask
!= 0
22343 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22344 || (DEFAULT_ABI
!= ABI_V4
22345 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
22349 if (frame_reg_rtx
== sp_reg_rtx
)
22351 if (use_backchain_to_restore_sp
)
22353 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22354 emit_move_insn (frame_reg_rtx
,
22355 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
22358 else if (frame_pointer_needed
)
22359 frame_reg_rtx
= hard_frame_pointer_rtx
;
22362 reg
= gen_rtx_REG (SImode
, 12);
22363 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22364 info
->vrsave_save_offset
+ frame_off
));
22366 emit_insn (generate_set_vrsave (reg
, info
, 1));
22370 /* If we have a large stack frame, restore the old stack pointer
22371 using the backchain. */
22372 if (use_backchain_to_restore_sp
)
22374 if (frame_reg_rtx
== sp_reg_rtx
)
22376 /* Under V.4, don't reset the stack pointer until after we're done
22377 loading the saved registers. */
22378 if (DEFAULT_ABI
== ABI_V4
)
22379 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22381 insn
= emit_move_insn (frame_reg_rtx
,
22382 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
22385 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22386 && DEFAULT_ABI
== ABI_V4
)
22387 /* frame_reg_rtx has been set up by the altivec restore. */
22391 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
22392 frame_reg_rtx
= sp_reg_rtx
;
22395 /* If we have a frame pointer, we can restore the old stack pointer
22397 else if (frame_pointer_needed
)
22399 frame_reg_rtx
= sp_reg_rtx
;
22400 if (DEFAULT_ABI
== ABI_V4
)
22401 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22402 /* Prevent reordering memory accesses against stack pointer restore. */
22403 else if (cfun
->calls_alloca
22404 || offset_below_red_zone_p (-info
->total_size
))
22405 rs6000_emit_stack_tie (frame_reg_rtx
, true);
22407 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
22408 GEN_INT (info
->total_size
)));
22411 else if (info
->push_p
22412 && DEFAULT_ABI
!= ABI_V4
22413 && !crtl
->calls_eh_return
)
22415 /* Prevent reordering memory accesses against stack pointer restore. */
22416 if (cfun
->calls_alloca
22417 || offset_below_red_zone_p (-info
->total_size
))
22418 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22419 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
22420 GEN_INT (info
->total_size
)));
22423 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
22427 REG_NOTES (insn
) = cfa_restores
;
22428 cfa_restores
= NULL_RTX
;
22430 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
22431 RTX_FRAME_RELATED_P (insn
) = 1;
22434 /* Restore AltiVec registers if we have not done so already. */
22435 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22436 && TARGET_ALTIVEC_ABI
22437 && info
->altivec_size
!= 0
22438 && (DEFAULT_ABI
== ABI_V4
22439 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
22443 if ((strategy
& REST_INLINE_VRS
) == 0)
22445 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22447 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22448 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
22449 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22451 if (end_save
+ frame_off
!= 0)
22453 rtx offset
= GEN_INT (end_save
+ frame_off
);
22455 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22458 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22460 ptr_off
= -end_save
;
22461 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22462 info
->altivec_save_offset
+ ptr_off
,
22463 0, V4SImode
, SAVRES_VR
);
22464 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
22466 /* Frame reg was clobbered by out-of-line save. Restore it
22467 from ptr_reg, and if we are calling out-of-line gpr or
22468 fpr restore set up the correct pointer and offset. */
22469 unsigned newptr_regno
= 1;
22470 if (!restoring_GPRs_inline
)
22472 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
22473 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
22474 newptr_regno
= ptr_regno_for_savres (sel
);
22475 end_save
= info
->gp_save_offset
+ info
->gp_size
;
22477 else if (!restoring_FPRs_inline
)
22479 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
22480 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22481 newptr_regno
= ptr_regno_for_savres (sel
);
22482 end_save
= info
->gp_save_offset
+ info
->gp_size
;
22485 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
22486 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
22488 if (end_save
+ ptr_off
!= 0)
22490 rtx offset
= GEN_INT (end_save
+ ptr_off
);
22492 frame_off
= -end_save
;
22493 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
22497 frame_off
= ptr_off
;
22498 emit_move_insn (frame_reg_rtx
, ptr_reg
);
22504 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22505 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22507 rtx addr
, areg
, mem
, reg
;
22509 areg
= gen_rtx_REG (Pmode
, 0);
22511 (areg
, GEN_INT (info
->altivec_save_offset
22513 + 16 * (i
- info
->first_altivec_reg_save
)));
22515 /* AltiVec addressing mode is [reg+reg]. */
22516 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
22517 mem
= gen_frame_mem (V4SImode
, addr
);
22519 reg
= gen_rtx_REG (V4SImode
, i
);
22520 emit_move_insn (reg
, mem
);
22524 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22525 if (((strategy
& REST_INLINE_VRS
) == 0
22526 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
22527 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
22529 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22530 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22534 /* Restore VRSAVE if we have not done so already. */
22535 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22537 && TARGET_ALTIVEC_VRSAVE
22538 && info
->vrsave_mask
!= 0
22539 && (DEFAULT_ABI
== ABI_V4
22540 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
22544 reg
= gen_rtx_REG (SImode
, 12);
22545 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22546 info
->vrsave_save_offset
+ frame_off
));
22548 emit_insn (generate_set_vrsave (reg
, info
, 1));
22551 /* If we exit by an out-of-line restore function on ABI_V4 then that
22552 function will deallocate the stack, so we don't need to worry
22553 about the unwinder restoring cr from an invalid stack frame
22555 exit_func
= (!restoring_FPRs_inline
22556 || (!restoring_GPRs_inline
22557 && info
->first_fp_reg_save
== 64));
22559 /* Get the old lr if we saved it. If we are restoring registers
22560 out-of-line, then the out-of-line routines can do this for us. */
22561 if (restore_lr
&& restoring_GPRs_inline
)
22562 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22564 /* Get the old cr if we saved it. */
22565 if (info
->cr_save_p
)
22567 unsigned cr_save_regno
= 12;
22569 if (!restoring_GPRs_inline
)
22571 /* Ensure we don't use the register used by the out-of-line
22572 gpr register restore below. */
22573 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
22574 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
22575 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
22577 if (gpr_ptr_regno
== 12)
22578 cr_save_regno
= 11;
22579 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
22581 else if (REGNO (frame_reg_rtx
) == 12)
22582 cr_save_regno
= 11;
22584 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
22585 info
->cr_save_offset
+ frame_off
,
22589 /* Set LR here to try to overlap restores below. */
22590 if (restore_lr
&& restoring_GPRs_inline
)
22591 restore_saved_lr (0, exit_func
);
22593 /* Load exception handler data registers, if needed. */
22594 if (crtl
->calls_eh_return
)
22596 unsigned int i
, regno
;
22600 rtx reg
= gen_rtx_REG (reg_mode
, 2);
22601 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22602 frame_off
+ 5 * reg_size
));
22609 regno
= EH_RETURN_DATA_REGNO (i
);
22610 if (regno
== INVALID_REGNUM
)
22613 /* Note: possible use of r0 here to address SPE regs. */
22614 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
22615 info
->ehrd_offset
+ frame_off
22616 + reg_size
* (int) i
);
22618 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
22622 /* Restore GPRs. This is done as a PARALLEL if we are using
22623 the load-multiple instructions. */
22625 && info
->spe_64bit_regs_used
22626 && info
->first_gp_reg_save
!= 32)
22628 /* Determine whether we can address all of the registers that need
22629 to be saved with an offset from frame_reg_rtx that fits in
22630 the small const field for SPE memory instructions. */
22631 int spe_regs_addressable
22632 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
22633 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
22634 && restoring_GPRs_inline
);
22636 if (!spe_regs_addressable
)
22638 int ool_adjust
= 0;
22639 rtx old_frame_reg_rtx
= frame_reg_rtx
;
22640 /* Make r11 point to the start of the SPE save area. We worried about
22641 not clobbering it when we were saving registers in the prologue.
22642 There's no need to worry here because the static chain is passed
22643 anew to every function. */
22645 if (!restoring_GPRs_inline
)
22646 ool_adjust
= 8 * (info
->first_gp_reg_save
22647 - (FIRST_SAVRES_REGISTER
+ 1));
22648 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22649 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
22650 GEN_INT (info
->spe_gp_save_offset
22653 /* Keep the invariant that frame_reg_rtx + frame_off points
22654 at the top of the stack frame. */
22655 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
22658 if (restoring_GPRs_inline
)
22660 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
22662 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22663 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22665 rtx offset
, addr
, mem
, reg
;
22667 /* We're doing all this to ensure that the immediate offset
22668 fits into the immediate field of 'evldd'. */
22669 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
22671 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
22672 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
22673 mem
= gen_rtx_MEM (V2SImode
, addr
);
22674 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
22676 emit_move_insn (reg
, mem
);
22680 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
22681 info
->spe_gp_save_offset
+ frame_off
,
22682 info
->lr_save_offset
+ frame_off
,
22684 SAVRES_GPR
| SAVRES_LR
);
22686 else if (!restoring_GPRs_inline
)
22688 /* We are jumping to an out-of-line function. */
22690 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
22691 bool can_use_exit
= end_save
== 0;
22692 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
22695 /* Emit stack reset code if we need it. */
22696 ptr_regno
= ptr_regno_for_savres (sel
);
22697 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22699 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
22700 else if (end_save
+ frame_off
!= 0)
22701 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
22702 GEN_INT (end_save
+ frame_off
)));
22703 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
22704 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22705 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22706 frame_off
= -end_save
;
22708 if (can_use_exit
&& info
->cr_save_p
)
22709 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
22711 ptr_off
= -end_save
;
22712 rs6000_emit_savres_rtx (info
, ptr_reg
,
22713 info
->gp_save_offset
+ ptr_off
,
22714 info
->lr_save_offset
+ ptr_off
,
22717 else if (using_load_multiple
)
22720 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
22721 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22723 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22725 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22726 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22730 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22731 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22732 emit_insn (gen_frame_load
22733 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22735 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
22738 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
22740 /* If the frame pointer was used then we can't delay emitting
22741 a REG_CFA_DEF_CFA note. This must happen on the insn that
22742 restores the frame pointer, r31. We may have already emitted
22743 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
22744 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
22745 be harmless if emitted. */
22746 if (frame_pointer_needed
)
22748 insn
= get_last_insn ();
22749 add_reg_note (insn
, REG_CFA_DEF_CFA
,
22750 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
22751 RTX_FRAME_RELATED_P (insn
) = 1;
22754 /* Set up cfa_restores. We always need these when
22755 shrink-wrapping. If not shrink-wrapping then we only need
22756 the cfa_restore when the stack location is no longer valid.
22757 The cfa_restores must be emitted on or before the insn that
22758 invalidates the stack, and of course must not be emitted
22759 before the insn that actually does the restore. The latter
22760 is why it is a bad idea to emit the cfa_restores as a group
22761 on the last instruction here that actually does a restore:
22762 That insn may be reordered with respect to others doing
22764 if (flag_shrink_wrap
22765 && !restoring_GPRs_inline
22766 && info
->first_fp_reg_save
== 64)
22767 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
22769 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
22770 if (!restoring_GPRs_inline
22771 || using_load_multiple
22772 || rs6000_reg_live_or_pic_offset_p (i
))
22774 rtx reg
= gen_rtx_REG (reg_mode
, i
);
22776 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22780 if (!restoring_GPRs_inline
22781 && info
->first_fp_reg_save
== 64)
22783 /* We are jumping to an out-of-line function. */
22785 emit_cfa_restores (cfa_restores
);
22789 if (restore_lr
&& !restoring_GPRs_inline
)
22791 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22792 restore_saved_lr (0, exit_func
);
22795 /* Restore fpr's if we need to do it without calling a function. */
22796 if (restoring_FPRs_inline
)
22797 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22798 if (save_reg_p (info
->first_fp_reg_save
+ i
))
22800 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22801 ? DFmode
: SFmode
),
22802 info
->first_fp_reg_save
+ i
);
22803 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22804 info
->fp_save_offset
+ frame_off
+ 8 * i
));
22805 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
22806 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22809 /* If we saved cr, restore it here. Just those that were used. */
22810 if (info
->cr_save_p
)
22811 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
22813 /* If this is V.4, unwind the stack pointer after all of the loads
22814 have been done, or set up r11 if we are restoring fp out of line. */
22816 if (!restoring_FPRs_inline
)
22818 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
22819 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22820 ptr_regno
= ptr_regno_for_savres (sel
);
22823 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
22824 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22827 if (insn
&& restoring_FPRs_inline
)
22831 REG_NOTES (insn
) = cfa_restores
;
22832 cfa_restores
= NULL_RTX
;
22834 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
22835 RTX_FRAME_RELATED_P (insn
) = 1;
22838 if (crtl
->calls_eh_return
)
22840 rtx sa
= EH_RETURN_STACKADJ_RTX
;
22841 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
22847 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
22848 if (! restoring_FPRs_inline
)
22850 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
22851 RTVEC_ELT (p
, 0) = ret_rtx
;
22857 /* We can't hang the cfa_restores off a simple return,
22858 since the shrink-wrap code sometimes uses an existing
22859 return. This means there might be a path from
22860 pre-prologue code to this return, and dwarf2cfi code
22861 wants the eh_frame unwinder state to be the same on
22862 all paths to any point. So we need to emit the
22863 cfa_restores before the return. For -m64 we really
22864 don't need epilogue cfa_restores at all, except for
22865 this irritating dwarf2cfi with shrink-wrap
22866 requirement; The stack red-zone means eh_frame info
22867 from the prologue telling the unwinder to restore
22868 from the stack is perfectly good right to the end of
22870 emit_insn (gen_blockage ());
22871 emit_cfa_restores (cfa_restores
);
22872 cfa_restores
= NULL_RTX
;
22874 p
= rtvec_alloc (2);
22875 RTVEC_ELT (p
, 0) = simple_return_rtx
;
22878 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
22879 ? gen_rtx_USE (VOIDmode
,
22880 gen_rtx_REG (Pmode
, LR_REGNO
))
22881 : gen_rtx_CLOBBER (VOIDmode
,
22882 gen_rtx_REG (Pmode
, LR_REGNO
)));
22884 /* If we have to restore more than two FP registers, branch to the
22885 restore function. It will return to our caller. */
22886 if (! restoring_FPRs_inline
)
22891 if (flag_shrink_wrap
)
22892 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
22894 sym
= rs6000_savres_routine_sym (info
,
22895 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
22896 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
22897 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
22898 gen_rtx_REG (Pmode
,
22899 DEFAULT_ABI
== ABI_AIX
22901 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22903 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
22905 RTVEC_ELT (p
, i
+ 4)
22906 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
22907 if (flag_shrink_wrap
)
22908 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
22913 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22919 /* Ensure the cfa_restores are hung off an insn that won't
22920 be reordered above other restores. */
22921 emit_insn (gen_blockage ());
22923 emit_cfa_restores (cfa_restores
);
22927 /* Write function epilogue. */
22930 rs6000_output_function_epilogue (FILE *file
,
22931 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
22934 macho_branch_islands ();
22935 /* Mach-O doesn't support labels at the end of objects, so if
22936 it looks like we might want one, insert a NOP. */
22938 rtx insn
= get_last_insn ();
22939 rtx deleted_debug_label
= NULL_RTX
;
22942 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
22944 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
22945 notes only, instead set their CODE_LABEL_NUMBER to -1,
22946 otherwise there would be code generation differences
22947 in between -g and -g0. */
22948 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
22949 deleted_debug_label
= insn
;
22950 insn
= PREV_INSN (insn
);
22955 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
22956 fputs ("\tnop\n", file
);
22957 else if (deleted_debug_label
)
22958 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
22959 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
22960 CODE_LABEL_NUMBER (insn
) = -1;
22964 /* Output a traceback table here. See /usr/include/sys/debug.h for info
22967 We don't output a traceback table if -finhibit-size-directive was
22968 used. The documentation for -finhibit-size-directive reads
22969 ``don't output a @code{.size} assembler directive, or anything
22970 else that would cause trouble if the function is split in the
22971 middle, and the two halves are placed at locations far apart in
22972 memory.'' The traceback table has this property, since it
22973 includes the offset from the start of the function to the
22974 traceback table itself.
22976 System V.4 Powerpc's (and the embedded ABI derived from it) use a
22977 different traceback table. */
22978 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
22979 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
22981 const char *fname
= NULL
;
22982 const char *language_string
= lang_hooks
.name
;
22983 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
22985 int optional_tbtab
;
22986 rs6000_stack_t
*info
= rs6000_stack_info ();
22988 if (rs6000_traceback
== traceback_full
)
22989 optional_tbtab
= 1;
22990 else if (rs6000_traceback
== traceback_part
)
22991 optional_tbtab
= 0;
22993 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
22995 if (optional_tbtab
)
22997 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
22998 while (*fname
== '.') /* V.4 encodes . in the name */
23001 /* Need label immediately before tbtab, so we can compute
23002 its offset from the function start. */
23003 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
23004 ASM_OUTPUT_LABEL (file
, fname
);
23007 /* The .tbtab pseudo-op can only be used for the first eight
23008 expressions, since it can't handle the possibly variable
23009 length fields that follow. However, if you omit the optional
23010 fields, the assembler outputs zeros for all optional fields
23011 anyways, giving each variable length field is minimum length
23012 (as defined in sys/debug.h). Thus we can not use the .tbtab
23013 pseudo-op at all. */
23015 /* An all-zero word flags the start of the tbtab, for debuggers
23016 that have to find it by searching forward from the entry
23017 point or from the current pc. */
23018 fputs ("\t.long 0\n", file
);
23020 /* Tbtab format type. Use format type 0. */
23021 fputs ("\t.byte 0,", file
);
23023 /* Language type. Unfortunately, there does not seem to be any
23024 official way to discover the language being compiled, so we
23025 use language_string.
23026 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
23027 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
23028 a number, so for now use 9. LTO and Go aren't assigned numbers
23029 either, so for now use 0. */
23030 if (! strcmp (language_string
, "GNU C")
23031 || ! strcmp (language_string
, "GNU GIMPLE")
23032 || ! strcmp (language_string
, "GNU Go"))
23034 else if (! strcmp (language_string
, "GNU F77")
23035 || ! strcmp (language_string
, "GNU Fortran"))
23037 else if (! strcmp (language_string
, "GNU Pascal"))
23039 else if (! strcmp (language_string
, "GNU Ada"))
23041 else if (! strcmp (language_string
, "GNU C++")
23042 || ! strcmp (language_string
, "GNU Objective-C++"))
23044 else if (! strcmp (language_string
, "GNU Java"))
23046 else if (! strcmp (language_string
, "GNU Objective-C"))
23049 gcc_unreachable ();
23050 fprintf (file
, "%d,", i
);
23052 /* 8 single bit fields: global linkage (not set for C extern linkage,
23053 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
23054 from start of procedure stored in tbtab, internal function, function
23055 has controlled storage, function has no toc, function uses fp,
23056 function logs/aborts fp operations. */
23057 /* Assume that fp operations are used if any fp reg must be saved. */
23058 fprintf (file
, "%d,",
23059 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
23061 /* 6 bitfields: function is interrupt handler, name present in
23062 proc table, function calls alloca, on condition directives
23063 (controls stack walks, 3 bits), saves condition reg, saves
23065 /* The `function calls alloca' bit seems to be set whenever reg 31 is
23066 set up as a frame pointer, even when there is no alloca call. */
23067 fprintf (file
, "%d,",
23068 ((optional_tbtab
<< 6)
23069 | ((optional_tbtab
& frame_pointer_needed
) << 5)
23070 | (info
->cr_save_p
<< 1)
23071 | (info
->lr_save_p
)));
23073 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
23075 fprintf (file
, "%d,",
23076 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
23078 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
23079 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
23081 if (optional_tbtab
)
23083 /* Compute the parameter info from the function decl argument
23086 int next_parm_info_bit
= 31;
23088 for (decl
= DECL_ARGUMENTS (current_function_decl
);
23089 decl
; decl
= DECL_CHAIN (decl
))
23091 rtx parameter
= DECL_INCOMING_RTL (decl
);
23092 enum machine_mode mode
= GET_MODE (parameter
);
23094 if (GET_CODE (parameter
) == REG
)
23096 if (SCALAR_FLOAT_MODE_P (mode
))
23117 gcc_unreachable ();
23120 /* If only one bit will fit, don't or in this entry. */
23121 if (next_parm_info_bit
> 0)
23122 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
23123 next_parm_info_bit
-= 2;
23127 fixed_parms
+= ((GET_MODE_SIZE (mode
)
23128 + (UNITS_PER_WORD
- 1))
23130 next_parm_info_bit
-= 1;
23136 /* Number of fixed point parameters. */
23137 /* This is actually the number of words of fixed point parameters; thus
23138 an 8 byte struct counts as 2; and thus the maximum value is 8. */
23139 fprintf (file
, "%d,", fixed_parms
);
23141 /* 2 bitfields: number of floating point parameters (7 bits), parameters
23143 /* This is actually the number of fp registers that hold parameters;
23144 and thus the maximum value is 13. */
23145 /* Set parameters on stack bit if parameters are not in their original
23146 registers, regardless of whether they are on the stack? Xlc
23147 seems to set the bit when not optimizing. */
23148 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
23150 if (! optional_tbtab
)
23153 /* Optional fields follow. Some are variable length. */
23155 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
23156 11 double float. */
23157 /* There is an entry for each parameter in a register, in the order that
23158 they occur in the parameter list. Any intervening arguments on the
23159 stack are ignored. If the list overflows a long (max possible length
23160 34 bits) then completely leave off all elements that don't fit. */
23161 /* Only emit this long if there was at least one parameter. */
23162 if (fixed_parms
|| float_parms
)
23163 fprintf (file
, "\t.long %d\n", parm_info
);
23165 /* Offset from start of code to tb table. */
23166 fputs ("\t.long ", file
);
23167 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
23168 RS6000_OUTPUT_BASENAME (file
, fname
);
23170 rs6000_output_function_entry (file
, fname
);
23173 /* Interrupt handler mask. */
23174 /* Omit this long, since we never set the interrupt handler bit
23177 /* Number of CTL (controlled storage) anchors. */
23178 /* Omit this long, since the has_ctl bit is never set above. */
23180 /* Displacement into stack of each CTL anchor. */
23181 /* Omit this list of longs, because there are no CTL anchors. */
23183 /* Length of function name. */
23186 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
23188 /* Function name. */
23189 assemble_string (fname
, strlen (fname
));
23191 /* Register for alloca automatic storage; this is always reg 31.
23192 Only emit this if the alloca bit was set above. */
23193 if (frame_pointer_needed
)
23194 fputs ("\t.byte 31\n", file
);
23196 fputs ("\t.align 2\n", file
);
23200 /* A C compound statement that outputs the assembler code for a thunk
23201 function, used to implement C++ virtual function calls with
23202 multiple inheritance. The thunk acts as a wrapper around a virtual
23203 function, adjusting the implicit object parameter before handing
23204 control off to the real function.
23206 First, emit code to add the integer DELTA to the location that
23207 contains the incoming first argument. Assume that this argument
23208 contains a pointer, and is the one used to pass the `this' pointer
23209 in C++. This is the incoming argument *before* the function
23210 prologue, e.g. `%o0' on a sparc. The addition must preserve the
23211 values of all other incoming arguments.
23213 After the addition, emit code to jump to FUNCTION, which is a
23214 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
23215 not touch the return address. Hence returning from FUNCTION will
23216 return to whoever called the current `thunk'.
23218 The effect must be as if FUNCTION had been called directly with the
23219 adjusted first argument. This macro is responsible for emitting
23220 all of the code for a thunk function; output_function_prologue()
23221 and output_function_epilogue() are not invoked.
23223 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
23224 been extracted from it.) It might possibly be useful on some
23225 targets, but probably not.
23227 If you do not define this macro, the target-independent code in the
23228 C++ frontend will generate a less efficient heavyweight thunk that
23229 calls FUNCTION instead of jumping to it. The generic approach does
23230 not support varargs. */
23233 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
23234 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
23237 rtx this_rtx
, insn
, funexp
;
23239 reload_completed
= 1;
23240 epilogue_completed
= 1;
23242 /* Mark the end of the (empty) prologue. */
23243 emit_note (NOTE_INSN_PROLOGUE_END
);
23245 /* Find the "this" pointer. If the function returns a structure,
23246 the structure return pointer is in r3. */
23247 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
23248 this_rtx
= gen_rtx_REG (Pmode
, 4);
23250 this_rtx
= gen_rtx_REG (Pmode
, 3);
23252 /* Apply the constant offset, if required. */
23254 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
23256 /* Apply the offset from the vtable, if required. */
23259 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
23260 rtx tmp
= gen_rtx_REG (Pmode
, 12);
23262 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
23263 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
23265 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
23266 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
23270 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
23272 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
23274 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
23277 /* Generate a tail call to the target function. */
23278 if (!TREE_USED (function
))
23280 assemble_external (function
);
23281 TREE_USED (function
) = 1;
23283 funexp
= XEXP (DECL_RTL (function
), 0);
23284 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
23287 if (MACHOPIC_INDIRECT
)
23288 funexp
= machopic_indirect_call_target (funexp
);
23291 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
23292 generate sibcall RTL explicitly. */
23293 insn
= emit_call_insn (
23294 gen_rtx_PARALLEL (VOIDmode
,
23296 gen_rtx_CALL (VOIDmode
,
23297 funexp
, const0_rtx
),
23298 gen_rtx_USE (VOIDmode
, const0_rtx
),
23299 gen_rtx_USE (VOIDmode
,
23300 gen_rtx_REG (SImode
,
23302 simple_return_rtx
)));
23303 SIBLING_CALL_P (insn
) = 1;
23306 /* Run just enough of rest_of_compilation to get the insns emitted.
23307 There's not really enough bulk here to make other passes such as
23308 instruction scheduling worth while. Note that use_thunk calls
23309 assemble_start_function and assemble_end_function. */
23310 insn
= get_insns ();
23311 shorten_branches (insn
);
23312 final_start_function (insn
, file
, 1);
23313 final (insn
, file
, 1);
23314 final_end_function ();
23316 reload_completed
= 0;
23317 epilogue_completed
= 0;
23320 /* A quick summary of the various types of 'constant-pool tables'
23323 Target Flags Name One table per
23324 AIX (none) AIX TOC object file
23325 AIX -mfull-toc AIX TOC object file
23326 AIX -mminimal-toc AIX minimal TOC translation unit
23327 SVR4/EABI (none) SVR4 SDATA object file
23328 SVR4/EABI -fpic SVR4 pic object file
23329 SVR4/EABI -fPIC SVR4 PIC translation unit
23330 SVR4/EABI -mrelocatable EABI TOC function
23331 SVR4/EABI -maix AIX TOC object file
23332 SVR4/EABI -maix -mminimal-toc
23333 AIX minimal TOC translation unit
23335 Name Reg. Set by entries contains:
23336 made by addrs? fp? sum?
23338 AIX TOC 2 crt0 as Y option option
23339 AIX minimal TOC 30 prolog gcc Y Y option
23340 SVR4 SDATA 13 crt0 gcc N Y N
23341 SVR4 pic 30 prolog ld Y not yet N
23342 SVR4 PIC 30 prolog gcc Y option option
23343 EABI TOC 30 prolog gcc Y option option
23347 /* Hash functions for the hash table. */
23350 rs6000_hash_constant (rtx k
)
23352 enum rtx_code code
= GET_CODE (k
);
23353 enum machine_mode mode
= GET_MODE (k
);
23354 unsigned result
= (code
<< 3) ^ mode
;
23355 const char *format
;
23358 format
= GET_RTX_FORMAT (code
);
23359 flen
= strlen (format
);
23365 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
23368 if (mode
!= VOIDmode
)
23369 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
23381 for (; fidx
< flen
; fidx
++)
23382 switch (format
[fidx
])
23387 const char *str
= XSTR (k
, fidx
);
23388 len
= strlen (str
);
23389 result
= result
* 613 + len
;
23390 for (i
= 0; i
< len
; i
++)
23391 result
= result
* 613 + (unsigned) str
[i
];
23396 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
23400 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
23403 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
23404 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
23408 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
23409 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
23416 gcc_unreachable ();
23423 toc_hash_function (const void *hash_entry
)
23425 const struct toc_hash_struct
*thc
=
23426 (const struct toc_hash_struct
*) hash_entry
;
23427 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
23430 /* Compare H1 and H2 for equivalence. */
23433 toc_hash_eq (const void *h1
, const void *h2
)
23435 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
23436 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
23438 if (((const struct toc_hash_struct
*) h1
)->key_mode
23439 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
23442 return rtx_equal_p (r1
, r2
);
23445 /* These are the names given by the C++ front-end to vtables, and
23446 vtable-like objects. Ideally, this logic should not be here;
23447 instead, there should be some programmatic way of inquiring as
23448 to whether or not an object is a vtable. */
23450 #define VTABLE_NAME_P(NAME) \
23451 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
23452 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
23453 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
23454 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
23455 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
23457 #ifdef NO_DOLLAR_IN_LABEL
23458 /* Return a GGC-allocated character string translating dollar signs in
23459 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
23462 rs6000_xcoff_strip_dollar (const char *name
)
23468 q
= (const char *) strchr (name
, '$');
23470 if (q
== 0 || q
== name
)
23473 len
= strlen (name
);
23474 strip
= XALLOCAVEC (char, len
+ 1);
23475 strcpy (strip
, name
);
23476 p
= strip
+ (q
- name
);
23480 p
= strchr (p
+ 1, '$');
23483 return ggc_alloc_string (strip
, len
);
23488 rs6000_output_symbol_ref (FILE *file
, rtx x
)
23490 /* Currently C++ toc references to vtables can be emitted before it
23491 is decided whether the vtable is public or private. If this is
23492 the case, then the linker will eventually complain that there is
23493 a reference to an unknown section. Thus, for vtables only,
23494 we emit the TOC reference to reference the symbol and not the
23496 const char *name
= XSTR (x
, 0);
23498 if (VTABLE_NAME_P (name
))
23500 RS6000_OUTPUT_BASENAME (file
, name
);
23503 assemble_name (file
, name
);
23506 /* Output a TOC entry. We derive the entry name from what is being
23510 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
23513 const char *name
= buf
;
23515 HOST_WIDE_INT offset
= 0;
23517 gcc_assert (!TARGET_NO_TOC
);
23519 /* When the linker won't eliminate them, don't output duplicate
23520 TOC entries (this happens on AIX if there is any kind of TOC,
23521 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
23523 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
23525 struct toc_hash_struct
*h
;
23528 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
23529 time because GGC is not initialized at that point. */
23530 if (toc_hash_table
== NULL
)
23531 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
23532 toc_hash_eq
, NULL
);
23534 h
= ggc_alloc_toc_hash_struct ();
23536 h
->key_mode
= mode
;
23537 h
->labelno
= labelno
;
23539 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
23540 if (*found
== NULL
)
23542 else /* This is indeed a duplicate.
23543 Set this label equal to that label. */
23545 fputs ("\t.set ", file
);
23546 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
23547 fprintf (file
, "%d,", labelno
);
23548 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
23549 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
23553 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
23554 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
23555 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
23557 fputs ("\t.set ", file
);
23558 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
23559 fprintf (file
, "%d,", labelno
);
23560 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
23561 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
23569 /* If we're going to put a double constant in the TOC, make sure it's
23570 aligned properly when strict alignment is on. */
23571 if (GET_CODE (x
) == CONST_DOUBLE
23572 && STRICT_ALIGNMENT
23573 && GET_MODE_BITSIZE (mode
) >= 64
23574 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
23575 ASM_OUTPUT_ALIGN (file
, 3);
23578 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
23580 /* Handle FP constants specially. Note that if we have a minimal
23581 TOC, things we put here aren't actually in the TOC, so we can allow
23583 if (GET_CODE (x
) == CONST_DOUBLE
&&
23584 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
23586 REAL_VALUE_TYPE rv
;
23589 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
23590 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
23591 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
23593 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
23597 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23598 fputs (DOUBLE_INT_ASM_OP
, file
);
23600 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
23601 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
23602 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
23603 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
23604 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
23605 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
23606 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
23607 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
23612 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23613 fputs ("\t.long ", file
);
23615 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
23616 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
23617 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
23618 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
23619 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
23620 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
23624 else if (GET_CODE (x
) == CONST_DOUBLE
&&
23625 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
23627 REAL_VALUE_TYPE rv
;
23630 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
23632 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
23633 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
23635 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
23639 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23640 fputs (DOUBLE_INT_ASM_OP
, file
);
23642 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
23643 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
23644 fprintf (file
, "0x%lx%08lx\n",
23645 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
23646 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
23651 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23652 fputs ("\t.long ", file
);
23654 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
23655 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
23656 fprintf (file
, "0x%lx,0x%lx\n",
23657 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
23661 else if (GET_CODE (x
) == CONST_DOUBLE
&&
23662 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
23664 REAL_VALUE_TYPE rv
;
23667 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
23668 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
23669 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
23671 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
23675 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23676 fputs (DOUBLE_INT_ASM_OP
, file
);
23678 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
23679 if (WORDS_BIG_ENDIAN
)
23680 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
23682 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
23687 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23688 fputs ("\t.long ", file
);
23690 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
23691 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
23695 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
23697 unsigned HOST_WIDE_INT low
;
23698 HOST_WIDE_INT high
;
23700 low
= INTVAL (x
) & 0xffffffff;
23701 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
23703 /* TOC entries are always Pmode-sized, so when big-endian
23704 smaller integer constants in the TOC need to be padded.
23705 (This is still a win over putting the constants in
23706 a separate constant pool, because then we'd have
23707 to have both a TOC entry _and_ the actual constant.)
23709 For a 32-bit target, CONST_INT values are loaded and shifted
23710 entirely within `low' and can be stored in one TOC entry. */
23712 /* It would be easy to make this work, but it doesn't now. */
23713 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
23715 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
23718 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
23719 high
= (HOST_WIDE_INT
) low
>> 32;
23725 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23726 fputs (DOUBLE_INT_ASM_OP
, file
);
23728 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
23729 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23730 fprintf (file
, "0x%lx%08lx\n",
23731 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23736 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
23738 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23739 fputs ("\t.long ", file
);
23741 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
23742 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23743 fprintf (file
, "0x%lx,0x%lx\n",
23744 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
23748 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23749 fputs ("\t.long ", file
);
23751 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
23752 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
23758 if (GET_CODE (x
) == CONST
)
23760 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
23761 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
23763 base
= XEXP (XEXP (x
, 0), 0);
23764 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
23767 switch (GET_CODE (base
))
23770 name
= XSTR (base
, 0);
23774 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
23775 CODE_LABEL_NUMBER (XEXP (base
, 0)));
23779 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
23783 gcc_unreachable ();
23786 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
23787 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
23790 fputs ("\t.tc ", file
);
23791 RS6000_OUTPUT_BASENAME (file
, name
);
23794 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
23796 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
23798 /* Mark large TOC symbols on AIX with [TE] so they are mapped
23799 after other TOC symbols, reducing overflow of small TOC access
23800 to [TC] symbols. */
23801 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
23802 ? "[TE]," : "[TC],", file
);
23805 /* Currently C++ toc references to vtables can be emitted before it
23806 is decided whether the vtable is public or private. If this is
23807 the case, then the linker will eventually complain that there is
23808 a TOC reference to an unknown section. Thus, for vtables only,
23809 we emit the TOC reference to reference the symbol and not the
23811 if (VTABLE_NAME_P (name
))
23813 RS6000_OUTPUT_BASENAME (file
, name
);
23815 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
23816 else if (offset
> 0)
23817 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
23820 output_addr_const (file
, x
);
23823 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
23824 && SYMBOL_REF_TLS_MODEL (base
) != 0)
23826 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
23827 fputs ("@le", file
);
23828 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
23829 fputs ("@ie", file
);
23830 /* Use global-dynamic for local-dynamic. */
23831 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
23832 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
23835 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
23836 fputs ("\t.tc .", file
);
23837 RS6000_OUTPUT_BASENAME (file
, name
);
23838 fputs ("[TC],", file
);
23839 output_addr_const (file
, x
);
23840 fputs ("@m", file
);
23848 /* Output an assembler pseudo-op to write an ASCII string of N characters
23849 starting at P to FILE.
23851 On the RS/6000, we have to do this using the .byte operation and
23852 write out special characters outside the quoted string.
23853 Also, the assembler is broken; very long strings are truncated,
23854 so we must artificially break them up early. */
23857 output_ascii (FILE *file
, const char *p
, int n
)
23860 int i
, count_string
;
23861 const char *for_string
= "\t.byte \"";
23862 const char *for_decimal
= "\t.byte ";
23863 const char *to_close
= NULL
;
23866 for (i
= 0; i
< n
; i
++)
23869 if (c
>= ' ' && c
< 0177)
23872 fputs (for_string
, file
);
23875 /* Write two quotes to get one. */
23883 for_decimal
= "\"\n\t.byte ";
23887 if (count_string
>= 512)
23889 fputs (to_close
, file
);
23891 for_string
= "\t.byte \"";
23892 for_decimal
= "\t.byte ";
23900 fputs (for_decimal
, file
);
23901 fprintf (file
, "%d", c
);
23903 for_string
= "\n\t.byte \"";
23904 for_decimal
= ", ";
23910 /* Now close the string if we have written one. Then end the line. */
23912 fputs (to_close
, file
);
23915 /* Generate a unique section name for FILENAME for a section type
23916 represented by SECTION_DESC. Output goes into BUF.
23918 SECTION_DESC can be any string, as long as it is different for each
23919 possible section type.
23921 We name the section in the same manner as xlc. The name begins with an
23922 underscore followed by the filename (after stripping any leading directory
23923 names) with the last period replaced by the string SECTION_DESC. If
23924 FILENAME does not contain a period, SECTION_DESC is appended to the end of
23928 rs6000_gen_section_name (char **buf
, const char *filename
,
23929 const char *section_desc
)
23931 const char *q
, *after_last_slash
, *last_period
= 0;
23935 after_last_slash
= filename
;
23936 for (q
= filename
; *q
; q
++)
23939 after_last_slash
= q
+ 1;
23940 else if (*q
== '.')
23944 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
23945 *buf
= (char *) xmalloc (len
);
23950 for (q
= after_last_slash
; *q
; q
++)
23952 if (q
== last_period
)
23954 strcpy (p
, section_desc
);
23955 p
+= strlen (section_desc
);
23959 else if (ISALNUM (*q
))
23963 if (last_period
== 0)
23964 strcpy (p
, section_desc
);
23969 /* Emit profile function. */
23972 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
23974 /* Non-standard profiling for kernels, which just saves LR then calls
23975 _mcount without worrying about arg saves. The idea is to change
23976 the function prologue as little as possible as it isn't easy to
23977 account for arg save/restore code added just for _mcount. */
23978 if (TARGET_PROFILE_KERNEL
)
23981 if (DEFAULT_ABI
== ABI_AIX
)
23983 #ifndef NO_PROFILE_COUNTERS
23984 # define NO_PROFILE_COUNTERS 0
23986 if (NO_PROFILE_COUNTERS
)
23987 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
23988 LCT_NORMAL
, VOIDmode
, 0);
23992 const char *label_name
;
23995 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
23996 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
23997 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
23999 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
24000 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
24003 else if (DEFAULT_ABI
== ABI_DARWIN
)
24005 const char *mcount_name
= RS6000_MCOUNT
;
24006 int caller_addr_regno
= LR_REGNO
;
24008 /* Be conservative and always set this, at least for now. */
24009 crtl
->uses_pic_offset_table
= 1;
24012 /* For PIC code, set up a stub and collect the caller's address
24013 from r0, which is where the prologue puts it. */
24014 if (MACHOPIC_INDIRECT
24015 && crtl
->uses_pic_offset_table
)
24016 caller_addr_regno
= 0;
24018 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
24019 LCT_NORMAL
, VOIDmode
, 1,
24020 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
24024 /* Write function profiler code. */
24027 output_function_profiler (FILE *file
, int labelno
)
24031 switch (DEFAULT_ABI
)
24034 gcc_unreachable ();
24039 warning (0, "no profiling of 64-bit code for this ABI");
24042 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
24043 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
24044 if (NO_PROFILE_COUNTERS
)
24046 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24047 reg_names
[0], reg_names
[1]);
24049 else if (TARGET_SECURE_PLT
&& flag_pic
)
24051 if (TARGET_LINK_STACK
)
24054 get_ppc476_thunk_name (name
);
24055 asm_fprintf (file
, "\tbl %s\n", name
);
24058 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
24059 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24060 reg_names
[0], reg_names
[1]);
24061 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
24062 asm_fprintf (file
, "\taddis %s,%s,",
24063 reg_names
[12], reg_names
[12]);
24064 assemble_name (file
, buf
);
24065 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
24066 assemble_name (file
, buf
);
24067 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
24069 else if (flag_pic
== 1)
24071 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
24072 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24073 reg_names
[0], reg_names
[1]);
24074 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
24075 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
24076 assemble_name (file
, buf
);
24077 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
24079 else if (flag_pic
> 1)
24081 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24082 reg_names
[0], reg_names
[1]);
24083 /* Now, we need to get the address of the label. */
24084 if (TARGET_LINK_STACK
)
24087 get_ppc476_thunk_name (name
);
24088 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
24089 assemble_name (file
, buf
);
24090 fputs ("-.\n1:", file
);
24091 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
24092 asm_fprintf (file
, "\taddi %s,%s,4\n",
24093 reg_names
[11], reg_names
[11]);
24097 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
24098 assemble_name (file
, buf
);
24099 fputs ("-.\n1:", file
);
24100 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
24102 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
24103 reg_names
[0], reg_names
[11]);
24104 asm_fprintf (file
, "\tadd %s,%s,%s\n",
24105 reg_names
[0], reg_names
[0], reg_names
[11]);
24109 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
24110 assemble_name (file
, buf
);
24111 fputs ("@ha\n", file
);
24112 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24113 reg_names
[0], reg_names
[1]);
24114 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
24115 assemble_name (file
, buf
);
24116 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
24119 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
24120 fprintf (file
, "\tbl %s%s\n",
24121 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
24126 if (!TARGET_PROFILE_KERNEL
)
24128 /* Don't do anything, done in output_profile_hook (). */
24132 gcc_assert (!TARGET_32BIT
);
24134 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
24135 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
24137 if (cfun
->static_chain_decl
!= NULL
)
24139 asm_fprintf (file
, "\tstd %s,24(%s)\n",
24140 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
24141 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
24142 asm_fprintf (file
, "\tld %s,24(%s)\n",
24143 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
24146 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
24154 /* The following variable value is the last issued insn. */
24156 static rtx last_scheduled_insn
;
24158 /* The following variable helps to balance issuing of load and
24159 store instructions */
24161 static int load_store_pendulum
;
24163 /* Power4 load update and store update instructions are cracked into a
24164 load or store and an integer insn which are executed in the same cycle.
24165 Branches have their own dispatch slot which does not count against the
24166 GCC issue rate, but it changes the program flow so there are no other
24167 instructions to issue in this cycle. */
24170 rs6000_variable_issue_1 (rtx insn
, int more
)
24172 last_scheduled_insn
= insn
;
24173 if (GET_CODE (PATTERN (insn
)) == USE
24174 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24176 cached_can_issue_more
= more
;
24177 return cached_can_issue_more
;
24180 if (insn_terminates_group_p (insn
, current_group
))
24182 cached_can_issue_more
= 0;
24183 return cached_can_issue_more
;
24186 /* If no reservation, but reach here */
24187 if (recog_memoized (insn
) < 0)
24190 if (rs6000_sched_groups
)
24192 if (is_microcoded_insn (insn
))
24193 cached_can_issue_more
= 0;
24194 else if (is_cracked_insn (insn
))
24195 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
24197 cached_can_issue_more
= more
- 1;
24199 return cached_can_issue_more
;
24202 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
24205 cached_can_issue_more
= more
- 1;
24206 return cached_can_issue_more
;
24210 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
24212 int r
= rs6000_variable_issue_1 (insn
, more
);
24214 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
24218 /* Adjust the cost of a scheduling dependency. Return the new cost of
24219 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
24222 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
24224 enum attr_type attr_type
;
24226 if (! recog_memoized (insn
))
24229 switch (REG_NOTE_KIND (link
))
24233 /* Data dependency; DEP_INSN writes a register that INSN reads
24234 some cycles later. */
24236 /* Separate a load from a narrower, dependent store. */
24237 if (rs6000_sched_groups
24238 && GET_CODE (PATTERN (insn
)) == SET
24239 && GET_CODE (PATTERN (dep_insn
)) == SET
24240 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
24241 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
24242 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
24243 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
24246 attr_type
= get_attr_type (insn
);
24251 /* Tell the first scheduling pass about the latency between
24252 a mtctr and bctr (and mtlr and br/blr). The first
24253 scheduling pass will not know about this latency since
24254 the mtctr instruction, which has the latency associated
24255 to it, will be generated by reload. */
24258 /* Leave some extra cycles between a compare and its
24259 dependent branch, to inhibit expensive mispredicts. */
24260 if ((rs6000_cpu_attr
== CPU_PPC603
24261 || rs6000_cpu_attr
== CPU_PPC604
24262 || rs6000_cpu_attr
== CPU_PPC604E
24263 || rs6000_cpu_attr
== CPU_PPC620
24264 || rs6000_cpu_attr
== CPU_PPC630
24265 || rs6000_cpu_attr
== CPU_PPC750
24266 || rs6000_cpu_attr
== CPU_PPC7400
24267 || rs6000_cpu_attr
== CPU_PPC7450
24268 || rs6000_cpu_attr
== CPU_PPCE5500
24269 || rs6000_cpu_attr
== CPU_PPCE6500
24270 || rs6000_cpu_attr
== CPU_POWER4
24271 || rs6000_cpu_attr
== CPU_POWER5
24272 || rs6000_cpu_attr
== CPU_POWER7
24273 || rs6000_cpu_attr
== CPU_POWER8
24274 || rs6000_cpu_attr
== CPU_CELL
)
24275 && recog_memoized (dep_insn
)
24276 && (INSN_CODE (dep_insn
) >= 0))
24278 switch (get_attr_type (dep_insn
))
24282 case TYPE_DELAYED_COMPARE
:
24283 case TYPE_IMUL_COMPARE
:
24284 case TYPE_LMUL_COMPARE
:
24285 case TYPE_FPCOMPARE
:
24286 case TYPE_CR_LOGICAL
:
24287 case TYPE_DELAYED_CR
:
24296 case TYPE_STORE_UX
:
24298 case TYPE_FPSTORE_U
:
24299 case TYPE_FPSTORE_UX
:
24300 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24301 && recog_memoized (dep_insn
)
24302 && (INSN_CODE (dep_insn
) >= 0))
24305 if (GET_CODE (PATTERN (insn
)) != SET
)
24306 /* If this happens, we have to extend this to schedule
24307 optimally. Return default for now. */
24310 /* Adjust the cost for the case where the value written
24311 by a fixed point operation is used as the address
24312 gen value on a store. */
24313 switch (get_attr_type (dep_insn
))
24320 if (! store_data_bypass_p (dep_insn
, insn
))
24324 case TYPE_LOAD_EXT
:
24325 case TYPE_LOAD_EXT_U
:
24326 case TYPE_LOAD_EXT_UX
:
24327 case TYPE_VAR_SHIFT_ROTATE
:
24328 case TYPE_VAR_DELAYED_COMPARE
:
24330 if (! store_data_bypass_p (dep_insn
, insn
))
24336 case TYPE_FAST_COMPARE
:
24339 case TYPE_INSERT_WORD
:
24340 case TYPE_INSERT_DWORD
:
24341 case TYPE_FPLOAD_U
:
24342 case TYPE_FPLOAD_UX
:
24344 case TYPE_STORE_UX
:
24345 case TYPE_FPSTORE_U
:
24346 case TYPE_FPSTORE_UX
:
24348 if (! store_data_bypass_p (dep_insn
, insn
))
24356 case TYPE_IMUL_COMPARE
:
24357 case TYPE_LMUL_COMPARE
:
24359 if (! store_data_bypass_p (dep_insn
, insn
))
24365 if (! store_data_bypass_p (dep_insn
, insn
))
24371 if (! store_data_bypass_p (dep_insn
, insn
))
24384 case TYPE_LOAD_EXT
:
24385 case TYPE_LOAD_EXT_U
:
24386 case TYPE_LOAD_EXT_UX
:
24387 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24388 && recog_memoized (dep_insn
)
24389 && (INSN_CODE (dep_insn
) >= 0))
24392 /* Adjust the cost for the case where the value written
24393 by a fixed point instruction is used within the address
24394 gen portion of a subsequent load(u)(x) */
24395 switch (get_attr_type (dep_insn
))
24402 if (set_to_load_agen (dep_insn
, insn
))
24406 case TYPE_LOAD_EXT
:
24407 case TYPE_LOAD_EXT_U
:
24408 case TYPE_LOAD_EXT_UX
:
24409 case TYPE_VAR_SHIFT_ROTATE
:
24410 case TYPE_VAR_DELAYED_COMPARE
:
24412 if (set_to_load_agen (dep_insn
, insn
))
24418 case TYPE_FAST_COMPARE
:
24421 case TYPE_INSERT_WORD
:
24422 case TYPE_INSERT_DWORD
:
24423 case TYPE_FPLOAD_U
:
24424 case TYPE_FPLOAD_UX
:
24426 case TYPE_STORE_UX
:
24427 case TYPE_FPSTORE_U
:
24428 case TYPE_FPSTORE_UX
:
24430 if (set_to_load_agen (dep_insn
, insn
))
24438 case TYPE_IMUL_COMPARE
:
24439 case TYPE_LMUL_COMPARE
:
24441 if (set_to_load_agen (dep_insn
, insn
))
24447 if (set_to_load_agen (dep_insn
, insn
))
24453 if (set_to_load_agen (dep_insn
, insn
))
24464 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24465 && recog_memoized (dep_insn
)
24466 && (INSN_CODE (dep_insn
) >= 0)
24467 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
24474 /* Fall out to return default cost. */
24478 case REG_DEP_OUTPUT
:
24479 /* Output dependency; DEP_INSN writes a register that INSN writes some
24481 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24482 && recog_memoized (dep_insn
)
24483 && (INSN_CODE (dep_insn
) >= 0))
24485 attr_type
= get_attr_type (insn
);
24490 if (get_attr_type (dep_insn
) == TYPE_FP
)
24494 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
24502 /* Anti dependency; DEP_INSN reads a register that INSN writes some
24507 gcc_unreachable ();
24513 /* Debug version of rs6000_adjust_cost. */
24516 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
24518 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
24524 switch (REG_NOTE_KIND (link
))
24526 default: dep
= "unknown depencency"; break;
24527 case REG_DEP_TRUE
: dep
= "data dependency"; break;
24528 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
24529 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
24533 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
24534 "%s, insn:\n", ret
, cost
, dep
);
24542 /* The function returns a true if INSN is microcoded.
24543 Return false otherwise. */
24546 is_microcoded_insn (rtx insn
)
24548 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24549 || GET_CODE (PATTERN (insn
)) == USE
24550 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24553 if (rs6000_cpu_attr
== CPU_CELL
)
24554 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
24556 if (rs6000_sched_groups
24557 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
24559 enum attr_type type
= get_attr_type (insn
);
24560 if (type
== TYPE_LOAD_EXT_U
24561 || type
== TYPE_LOAD_EXT_UX
24562 || type
== TYPE_LOAD_UX
24563 || type
== TYPE_STORE_UX
24564 || type
== TYPE_MFCR
)
24571 /* The function returns true if INSN is cracked into 2 instructions
24572 by the processor (and therefore occupies 2 issue slots). */
24575 is_cracked_insn (rtx insn
)
24577 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24578 || GET_CODE (PATTERN (insn
)) == USE
24579 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24582 if (rs6000_sched_groups
24583 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
24585 enum attr_type type
= get_attr_type (insn
);
24586 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
24587 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
24588 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
24589 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
24590 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
24591 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
24592 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
24593 || type
== TYPE_INSERT_WORD
)
24600 /* The function returns true if INSN can be issued only from
24601 the branch slot. */
24604 is_branch_slot_insn (rtx insn
)
24606 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24607 || GET_CODE (PATTERN (insn
)) == USE
24608 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24611 if (rs6000_sched_groups
)
24613 enum attr_type type
= get_attr_type (insn
);
24614 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
24622 /* The function returns true if out_inst sets a value that is
24623 used in the address generation computation of in_insn */
24625 set_to_load_agen (rtx out_insn
, rtx in_insn
)
24627 rtx out_set
, in_set
;
24629 /* For performance reasons, only handle the simple case where
24630 both loads are a single_set. */
24631 out_set
= single_set (out_insn
);
24634 in_set
= single_set (in_insn
);
24636 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
24642 /* Try to determine base/offset/size parts of the given MEM.
24643 Return true if successful, false if all the values couldn't
24646 This function only looks for REG or REG+CONST address forms.
24647 REG+REG address form will return false. */
24650 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
24651 HOST_WIDE_INT
*size
)
24654 if MEM_SIZE_KNOWN_P (mem
)
24655 *size
= MEM_SIZE (mem
);
24659 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
24660 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
24662 addr_rtx
= (XEXP (mem
, 0));
24664 if (GET_CODE (addr_rtx
) == REG
)
24669 else if (GET_CODE (addr_rtx
) == PLUS
24670 && CONST_INT_P (XEXP (addr_rtx
, 1)))
24672 *base
= XEXP (addr_rtx
, 0);
24673 *offset
= INTVAL (XEXP (addr_rtx
, 1));
24681 /* The function returns true if the target storage location of
24682 mem1 is adjacent to the target storage location of mem2 */
24683 /* Return 1 if memory locations are adjacent. */
24686 adjacent_mem_locations (rtx mem1
, rtx mem2
)
24689 HOST_WIDE_INT off1
, size1
, off2
, size2
;
24691 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
24692 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
24693 return ((REGNO (reg1
) == REGNO (reg2
))
24694 && ((off1
+ size1
== off2
)
24695 || (off2
+ size2
== off1
)));
24700 /* This function returns true if it can be determined that the two MEM
24701 locations overlap by at least 1 byte based on base reg/offset/size. */
24704 mem_locations_overlap (rtx mem1
, rtx mem2
)
24707 HOST_WIDE_INT off1
, size1
, off2
, size2
;
24709 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
24710 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
24711 return ((REGNO (reg1
) == REGNO (reg2
))
24712 && (((off1
<= off2
) && (off1
+ size1
> off2
))
24713 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
24718 /* A C statement (sans semicolon) to update the integer scheduling
24719 priority INSN_PRIORITY (INSN). Increase the priority to execute the
24720 INSN earlier, reduce the priority to execute INSN later. Do not
24721 define this macro if you do not need to adjust the scheduling
24722 priorities of insns. */
24725 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
24727 rtx load_mem
, str_mem
;
24728 /* On machines (like the 750) which have asymmetric integer units,
24729 where one integer unit can do multiply and divides and the other
24730 can't, reduce the priority of multiply/divide so it is scheduled
24731 before other integer operations. */
24734 if (! INSN_P (insn
))
24737 if (GET_CODE (PATTERN (insn
)) == USE
)
24740 switch (rs6000_cpu_attr
) {
24742 switch (get_attr_type (insn
))
24749 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
24750 priority
, priority
);
24751 if (priority
>= 0 && priority
< 0x01000000)
24758 if (insn_must_be_first_in_group (insn
)
24759 && reload_completed
24760 && current_sched_info
->sched_max_insns_priority
24761 && rs6000_sched_restricted_insns_priority
)
24764 /* Prioritize insns that can be dispatched only in the first
24766 if (rs6000_sched_restricted_insns_priority
== 1)
24767 /* Attach highest priority to insn. This means that in
24768 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
24769 precede 'priority' (critical path) considerations. */
24770 return current_sched_info
->sched_max_insns_priority
;
24771 else if (rs6000_sched_restricted_insns_priority
== 2)
24772 /* Increase priority of insn by a minimal amount. This means that in
24773 haifa-sched.c:ready_sort(), only 'priority' (critical path)
24774 considerations precede dispatch-slot restriction considerations. */
24775 return (priority
+ 1);
24778 if (rs6000_cpu
== PROCESSOR_POWER6
24779 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
24780 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
24781 /* Attach highest priority to insn if the scheduler has just issued two
24782 stores and this instruction is a load, or two loads and this instruction
24783 is a store. Power6 wants loads and stores scheduled alternately
24785 return current_sched_info
->sched_max_insns_priority
;
24790 /* Return true if the instruction is nonpipelined on the Cell. */
24792 is_nonpipeline_insn (rtx insn
)
24794 enum attr_type type
;
24795 if (!insn
|| !NONDEBUG_INSN_P (insn
)
24796 || GET_CODE (PATTERN (insn
)) == USE
24797 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24800 type
= get_attr_type (insn
);
24801 if (type
== TYPE_IMUL
24802 || type
== TYPE_IMUL2
24803 || type
== TYPE_IMUL3
24804 || type
== TYPE_LMUL
24805 || type
== TYPE_IDIV
24806 || type
== TYPE_LDIV
24807 || type
== TYPE_SDIV
24808 || type
== TYPE_DDIV
24809 || type
== TYPE_SSQRT
24810 || type
== TYPE_DSQRT
24811 || type
== TYPE_MFCR
24812 || type
== TYPE_MFCRF
24813 || type
== TYPE_MFJMPR
)
24821 /* Return how many instructions the machine can issue per cycle. */
24824 rs6000_issue_rate (void)
24826 /* Unless scheduling for register pressure, use issue rate of 1 for
24827 first scheduling pass to decrease degradation. */
24828 if (!reload_completed
&& !flag_sched_pressure
)
24831 switch (rs6000_cpu_attr
) {
24833 case CPU_PPC601
: /* ? */
24843 case CPU_PPCE300C2
:
24844 case CPU_PPCE300C3
:
24845 case CPU_PPCE500MC
:
24846 case CPU_PPCE500MC64
:
24869 /* Return how many instructions to look ahead for better insn
24873 rs6000_use_sched_lookahead (void)
24875 switch (rs6000_cpu_attr
)
24882 return (reload_completed
? 8 : 0);
24889 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
24891 rs6000_use_sched_lookahead_guard (rtx insn
)
24893 if (rs6000_cpu_attr
!= CPU_CELL
)
24896 if (insn
== NULL_RTX
|| !INSN_P (insn
))
24899 if (!reload_completed
24900 || is_nonpipeline_insn (insn
)
24901 || is_microcoded_insn (insn
))
24907 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
24908 and return true. */
24911 find_mem_ref (rtx pat
, rtx
*mem_ref
)
24916 /* stack_tie does not produce any real memory traffic. */
24917 if (tie_operand (pat
, VOIDmode
))
24920 if (GET_CODE (pat
) == MEM
)
24926 /* Recursively process the pattern. */
24927 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
24929 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
24933 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
24936 else if (fmt
[i
] == 'E')
24937 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
24939 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
24947 /* Determine if PAT is a PATTERN of a load insn. */
24950 is_load_insn1 (rtx pat
, rtx
*load_mem
)
24952 if (!pat
|| pat
== NULL_RTX
)
24955 if (GET_CODE (pat
) == SET
)
24956 return find_mem_ref (SET_SRC (pat
), load_mem
);
24958 if (GET_CODE (pat
) == PARALLEL
)
24962 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
24963 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
24970 /* Determine if INSN loads from memory. */
24973 is_load_insn (rtx insn
, rtx
*load_mem
)
24975 if (!insn
|| !INSN_P (insn
))
24981 return is_load_insn1 (PATTERN (insn
), load_mem
);
24984 /* Determine if PAT is a PATTERN of a store insn. */
24987 is_store_insn1 (rtx pat
, rtx
*str_mem
)
24989 if (!pat
|| pat
== NULL_RTX
)
24992 if (GET_CODE (pat
) == SET
)
24993 return find_mem_ref (SET_DEST (pat
), str_mem
);
24995 if (GET_CODE (pat
) == PARALLEL
)
24999 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
25000 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
25007 /* Determine if INSN stores to memory. */
25010 is_store_insn (rtx insn
, rtx
*str_mem
)
25012 if (!insn
|| !INSN_P (insn
))
25015 return is_store_insn1 (PATTERN (insn
), str_mem
);
25018 /* Returns whether the dependence between INSN and NEXT is considered
25019 costly by the given target. */
25022 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
25026 rtx load_mem
, str_mem
;
25028 /* If the flag is not enabled - no dependence is considered costly;
25029 allow all dependent insns in the same group.
25030 This is the most aggressive option. */
25031 if (rs6000_sched_costly_dep
== no_dep_costly
)
25034 /* If the flag is set to 1 - a dependence is always considered costly;
25035 do not allow dependent instructions in the same group.
25036 This is the most conservative option. */
25037 if (rs6000_sched_costly_dep
== all_deps_costly
)
25040 insn
= DEP_PRO (dep
);
25041 next
= DEP_CON (dep
);
25043 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
25044 && is_load_insn (next
, &load_mem
)
25045 && is_store_insn (insn
, &str_mem
))
25046 /* Prevent load after store in the same group. */
25049 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
25050 && is_load_insn (next
, &load_mem
)
25051 && is_store_insn (insn
, &str_mem
)
25052 && DEP_TYPE (dep
) == REG_DEP_TRUE
25053 && mem_locations_overlap(str_mem
, load_mem
))
25054 /* Prevent load after store in the same group if it is a true
25058 /* The flag is set to X; dependences with latency >= X are considered costly,
25059 and will not be scheduled in the same group. */
25060 if (rs6000_sched_costly_dep
<= max_dep_latency
25061 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
25067 /* Return the next insn after INSN that is found before TAIL is reached,
25068 skipping any "non-active" insns - insns that will not actually occupy
25069 an issue slot. Return NULL_RTX if such an insn is not found. */
25072 get_next_active_insn (rtx insn
, rtx tail
)
25074 if (insn
== NULL_RTX
|| insn
== tail
)
25079 insn
= NEXT_INSN (insn
);
25080 if (insn
== NULL_RTX
|| insn
== tail
)
25084 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
25085 || (NONJUMP_INSN_P (insn
)
25086 && GET_CODE (PATTERN (insn
)) != USE
25087 && GET_CODE (PATTERN (insn
)) != CLOBBER
25088 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
25094 /* We are about to begin issuing insns for this clock cycle. */
25097 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
25098 rtx
*ready ATTRIBUTE_UNUSED
,
25099 int *pn_ready ATTRIBUTE_UNUSED
,
25100 int clock_var ATTRIBUTE_UNUSED
)
25102 int n_ready
= *pn_ready
;
25105 fprintf (dump
, "// rs6000_sched_reorder :\n");
25107 /* Reorder the ready list, if the second to last ready insn
25108 is a nonepipeline insn. */
25109 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
25111 if (is_nonpipeline_insn (ready
[n_ready
- 1])
25112 && (recog_memoized (ready
[n_ready
- 2]) > 0))
25113 /* Simply swap first two insns. */
25115 rtx tmp
= ready
[n_ready
- 1];
25116 ready
[n_ready
- 1] = ready
[n_ready
- 2];
25117 ready
[n_ready
- 2] = tmp
;
25121 if (rs6000_cpu
== PROCESSOR_POWER6
)
25122 load_store_pendulum
= 0;
25124 return rs6000_issue_rate ();
25127 /* Like rs6000_sched_reorder, but called after issuing each insn. */
25130 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
25131 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
25134 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
25136 /* For Power6, we need to handle some special cases to try and keep the
25137 store queue from overflowing and triggering expensive flushes.
25139 This code monitors how load and store instructions are being issued
25140 and skews the ready list one way or the other to increase the likelihood
25141 that a desired instruction is issued at the proper time.
25143 A couple of things are done. First, we maintain a "load_store_pendulum"
25144 to track the current state of load/store issue.
25146 - If the pendulum is at zero, then no loads or stores have been
25147 issued in the current cycle so we do nothing.
25149 - If the pendulum is 1, then a single load has been issued in this
25150 cycle and we attempt to locate another load in the ready list to
25153 - If the pendulum is -2, then two stores have already been
25154 issued in this cycle, so we increase the priority of the first load
25155 in the ready list to increase it's likelihood of being chosen first
25158 - If the pendulum is -1, then a single store has been issued in this
25159 cycle and we attempt to locate another store in the ready list to
25160 issue with it, preferring a store to an adjacent memory location to
25161 facilitate store pairing in the store queue.
25163 - If the pendulum is 2, then two loads have already been
25164 issued in this cycle, so we increase the priority of the first store
25165 in the ready list to increase it's likelihood of being chosen first
25168 - If the pendulum < -2 or > 2, then do nothing.
25170 Note: This code covers the most common scenarios. There exist non
25171 load/store instructions which make use of the LSU and which
25172 would need to be accounted for to strictly model the behavior
25173 of the machine. Those instructions are currently unaccounted
25174 for to help minimize compile time overhead of this code.
25176 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
25180 rtx tmp
, load_mem
, str_mem
;
25182 if (is_store_insn (last_scheduled_insn
, &str_mem
))
25183 /* Issuing a store, swing the load_store_pendulum to the left */
25184 load_store_pendulum
--;
25185 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
25186 /* Issuing a load, swing the load_store_pendulum to the right */
25187 load_store_pendulum
++;
25189 return cached_can_issue_more
;
25191 /* If the pendulum is balanced, or there is only one instruction on
25192 the ready list, then all is well, so return. */
25193 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
25194 return cached_can_issue_more
;
25196 if (load_store_pendulum
== 1)
25198 /* A load has been issued in this cycle. Scan the ready list
25199 for another load to issue with it */
25204 if (is_load_insn (ready
[pos
], &load_mem
))
25206 /* Found a load. Move it to the head of the ready list,
25207 and adjust it's priority so that it is more likely to
25210 for (i
=pos
; i
<*pn_ready
-1; i
++)
25211 ready
[i
] = ready
[i
+ 1];
25212 ready
[*pn_ready
-1] = tmp
;
25214 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
25215 INSN_PRIORITY (tmp
)++;
25221 else if (load_store_pendulum
== -2)
25223 /* Two stores have been issued in this cycle. Increase the
25224 priority of the first load in the ready list to favor it for
25225 issuing in the next cycle. */
25230 if (is_load_insn (ready
[pos
], &load_mem
)
25232 && INSN_PRIORITY_KNOWN (ready
[pos
]))
25234 INSN_PRIORITY (ready
[pos
])++;
25236 /* Adjust the pendulum to account for the fact that a load
25237 was found and increased in priority. This is to prevent
25238 increasing the priority of multiple loads */
25239 load_store_pendulum
--;
25246 else if (load_store_pendulum
== -1)
25248 /* A store has been issued in this cycle. Scan the ready list for
25249 another store to issue with it, preferring a store to an adjacent
25251 int first_store_pos
= -1;
25257 if (is_store_insn (ready
[pos
], &str_mem
))
25260 /* Maintain the index of the first store found on the
25262 if (first_store_pos
== -1)
25263 first_store_pos
= pos
;
25265 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
25266 && adjacent_mem_locations (str_mem
, str_mem2
))
25268 /* Found an adjacent store. Move it to the head of the
25269 ready list, and adjust it's priority so that it is
25270 more likely to stay there */
25272 for (i
=pos
; i
<*pn_ready
-1; i
++)
25273 ready
[i
] = ready
[i
+ 1];
25274 ready
[*pn_ready
-1] = tmp
;
25276 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
25277 INSN_PRIORITY (tmp
)++;
25279 first_store_pos
= -1;
25287 if (first_store_pos
>= 0)
25289 /* An adjacent store wasn't found, but a non-adjacent store was,
25290 so move the non-adjacent store to the front of the ready
25291 list, and adjust its priority so that it is more likely to
25293 tmp
= ready
[first_store_pos
];
25294 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
25295 ready
[i
] = ready
[i
+ 1];
25296 ready
[*pn_ready
-1] = tmp
;
25297 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
25298 INSN_PRIORITY (tmp
)++;
25301 else if (load_store_pendulum
== 2)
25303 /* Two loads have been issued in this cycle. Increase the priority
25304 of the first store in the ready list to favor it for issuing in
25310 if (is_store_insn (ready
[pos
], &str_mem
)
25312 && INSN_PRIORITY_KNOWN (ready
[pos
]))
25314 INSN_PRIORITY (ready
[pos
])++;
25316 /* Adjust the pendulum to account for the fact that a store
25317 was found and increased in priority. This is to prevent
25318 increasing the priority of multiple stores */
25319 load_store_pendulum
++;
25328 return cached_can_issue_more
;
25331 /* Return whether the presence of INSN causes a dispatch group termination
25332 of group WHICH_GROUP.
25334 If WHICH_GROUP == current_group, this function will return true if INSN
25335 causes the termination of the current group (i.e, the dispatch group to
25336 which INSN belongs). This means that INSN will be the last insn in the
25337 group it belongs to.
25339 If WHICH_GROUP == previous_group, this function will return true if INSN
25340 causes the termination of the previous group (i.e, the dispatch group that
25341 precedes the group to which INSN belongs). This means that INSN will be
25342 the first insn in the group it belongs to). */
25345 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
25352 first
= insn_must_be_first_in_group (insn
);
25353 last
= insn_must_be_last_in_group (insn
);
25358 if (which_group
== current_group
)
25360 else if (which_group
== previous_group
)
25368 insn_must_be_first_in_group (rtx insn
)
25370 enum attr_type type
;
25374 || DEBUG_INSN_P (insn
)
25375 || GET_CODE (PATTERN (insn
)) == USE
25376 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25379 switch (rs6000_cpu
)
25381 case PROCESSOR_POWER5
:
25382 if (is_cracked_insn (insn
))
25384 case PROCESSOR_POWER4
:
25385 if (is_microcoded_insn (insn
))
25388 if (!rs6000_sched_groups
)
25391 type
= get_attr_type (insn
);
25398 case TYPE_DELAYED_CR
:
25399 case TYPE_CR_LOGICAL
:
25413 case PROCESSOR_POWER6
:
25414 type
= get_attr_type (insn
);
25418 case TYPE_INSERT_DWORD
:
25422 case TYPE_VAR_SHIFT_ROTATE
:
25429 case TYPE_INSERT_WORD
:
25430 case TYPE_DELAYED_COMPARE
:
25431 case TYPE_IMUL_COMPARE
:
25432 case TYPE_LMUL_COMPARE
:
25433 case TYPE_FPCOMPARE
:
25444 case TYPE_LOAD_EXT_UX
:
25446 case TYPE_STORE_UX
:
25447 case TYPE_FPLOAD_U
:
25448 case TYPE_FPLOAD_UX
:
25449 case TYPE_FPSTORE_U
:
25450 case TYPE_FPSTORE_UX
:
25456 case PROCESSOR_POWER7
:
25457 type
= get_attr_type (insn
);
25461 case TYPE_CR_LOGICAL
:
25468 case TYPE_DELAYED_COMPARE
:
25469 case TYPE_VAR_DELAYED_COMPARE
:
25475 case TYPE_LOAD_EXT
:
25476 case TYPE_LOAD_EXT_U
:
25477 case TYPE_LOAD_EXT_UX
:
25479 case TYPE_STORE_UX
:
25480 case TYPE_FPLOAD_U
:
25481 case TYPE_FPLOAD_UX
:
25482 case TYPE_FPSTORE_U
:
25483 case TYPE_FPSTORE_UX
:
25491 case PROCESSOR_POWER8
:
25492 type
= get_attr_type (insn
);
25496 case TYPE_CR_LOGICAL
:
25497 case TYPE_DELAYED_CR
:
25502 case TYPE_DELAYED_COMPARE
:
25503 case TYPE_VAR_DELAYED_COMPARE
:
25504 case TYPE_IMUL_COMPARE
:
25505 case TYPE_LMUL_COMPARE
:
25512 case TYPE_LOAD_EXT
:
25513 case TYPE_LOAD_EXT_U
:
25514 case TYPE_LOAD_EXT_UX
:
25515 case TYPE_STORE_UX
:
25516 case TYPE_VECSTORE
:
25532 insn_must_be_last_in_group (rtx insn
)
25534 enum attr_type type
;
25538 || DEBUG_INSN_P (insn
)
25539 || GET_CODE (PATTERN (insn
)) == USE
25540 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25543 switch (rs6000_cpu
) {
25544 case PROCESSOR_POWER4
:
25545 case PROCESSOR_POWER5
:
25546 if (is_microcoded_insn (insn
))
25549 if (is_branch_slot_insn (insn
))
25553 case PROCESSOR_POWER6
:
25554 type
= get_attr_type (insn
);
25561 case TYPE_VAR_SHIFT_ROTATE
:
25568 case TYPE_DELAYED_COMPARE
:
25569 case TYPE_IMUL_COMPARE
:
25570 case TYPE_LMUL_COMPARE
:
25571 case TYPE_FPCOMPARE
:
25585 case PROCESSOR_POWER7
:
25586 type
= get_attr_type (insn
);
25594 case TYPE_LOAD_EXT_U
:
25595 case TYPE_LOAD_EXT_UX
:
25596 case TYPE_STORE_UX
:
25602 case PROCESSOR_POWER8
:
25603 type
= get_attr_type (insn
);
25613 case TYPE_LOAD_EXT_U
:
25614 case TYPE_LOAD_EXT_UX
:
25615 case TYPE_STORE_UX
:
25628 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
25629 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
25632 is_costly_group (rtx
*group_insns
, rtx next_insn
)
25635 int issue_rate
= rs6000_issue_rate ();
25637 for (i
= 0; i
< issue_rate
; i
++)
25639 sd_iterator_def sd_it
;
25641 rtx insn
= group_insns
[i
];
25646 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
25648 rtx next
= DEP_CON (dep
);
25650 if (next
== next_insn
25651 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
25659 /* Utility of the function redefine_groups.
25660 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
25661 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
25662 to keep it "far" (in a separate group) from GROUP_INSNS, following
25663 one of the following schemes, depending on the value of the flag
25664 -minsert_sched_nops = X:
25665 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
25666 in order to force NEXT_INSN into a separate group.
25667 (2) X < sched_finish_regroup_exact: insert exactly X nops.
25668 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
25669 insertion (has a group just ended, how many vacant issue slots remain in the
25670 last group, and how many dispatch groups were encountered so far). */
25673 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
25674 rtx next_insn
, bool *group_end
, int can_issue_more
,
25679 int issue_rate
= rs6000_issue_rate ();
25680 bool end
= *group_end
;
25683 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
25684 return can_issue_more
;
25686 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
25687 return can_issue_more
;
25689 force
= is_costly_group (group_insns
, next_insn
);
25691 return can_issue_more
;
25693 if (sched_verbose
> 6)
25694 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
25695 *group_count
,can_issue_more
);
25697 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
25700 can_issue_more
= 0;
25702 /* Since only a branch can be issued in the last issue_slot, it is
25703 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
25704 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
25705 in this case the last nop will start a new group and the branch
25706 will be forced to the new group. */
25707 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
25710 /* Do we have a special group ending nop? */
25711 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
25712 || rs6000_cpu_attr
== CPU_POWER8
)
25714 nop
= gen_group_ending_nop ();
25715 emit_insn_before (nop
, next_insn
);
25716 can_issue_more
= 0;
25719 while (can_issue_more
> 0)
25722 emit_insn_before (nop
, next_insn
);
25730 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
25732 int n_nops
= rs6000_sched_insert_nops
;
25734 /* Nops can't be issued from the branch slot, so the effective
25735 issue_rate for nops is 'issue_rate - 1'. */
25736 if (can_issue_more
== 0)
25737 can_issue_more
= issue_rate
;
25739 if (can_issue_more
== 0)
25741 can_issue_more
= issue_rate
- 1;
25744 for (i
= 0; i
< issue_rate
; i
++)
25746 group_insns
[i
] = 0;
25753 emit_insn_before (nop
, next_insn
);
25754 if (can_issue_more
== issue_rate
- 1) /* new group begins */
25757 if (can_issue_more
== 0)
25759 can_issue_more
= issue_rate
- 1;
25762 for (i
= 0; i
< issue_rate
; i
++)
25764 group_insns
[i
] = 0;
25770 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
25773 /* Is next_insn going to start a new group? */
25776 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
25777 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
25778 || (can_issue_more
< issue_rate
&&
25779 insn_terminates_group_p (next_insn
, previous_group
)));
25780 if (*group_end
&& end
)
25783 if (sched_verbose
> 6)
25784 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
25785 *group_count
, can_issue_more
);
25786 return can_issue_more
;
25789 return can_issue_more
;
25792 /* This function tries to synch the dispatch groups that the compiler "sees"
25793 with the dispatch groups that the processor dispatcher is expected to
25794 form in practice. It tries to achieve this synchronization by forcing the
25795 estimated processor grouping on the compiler (as opposed to the function
25796 'pad_goups' which tries to force the scheduler's grouping on the processor).
25798 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
25799 examines the (estimated) dispatch groups that will be formed by the processor
25800 dispatcher. It marks these group boundaries to reflect the estimated
25801 processor grouping, overriding the grouping that the scheduler had marked.
25802 Depending on the value of the flag '-minsert-sched-nops' this function can
25803 force certain insns into separate groups or force a certain distance between
25804 them by inserting nops, for example, if there exists a "costly dependence"
25807 The function estimates the group boundaries that the processor will form as
25808 follows: It keeps track of how many vacant issue slots are available after
25809 each insn. A subsequent insn will start a new group if one of the following
25811 - no more vacant issue slots remain in the current dispatch group.
25812 - only the last issue slot, which is the branch slot, is vacant, but the next
25813 insn is not a branch.
25814 - only the last 2 or less issue slots, including the branch slot, are vacant,
25815 which means that a cracked insn (which occupies two issue slots) can't be
25816 issued in this group.
25817 - less than 'issue_rate' slots are vacant, and the next insn always needs to
25818 start a new group. */
25821 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
25823 rtx insn
, next_insn
;
25825 int can_issue_more
;
25828 int group_count
= 0;
25832 issue_rate
= rs6000_issue_rate ();
25833 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
25834 for (i
= 0; i
< issue_rate
; i
++)
25836 group_insns
[i
] = 0;
25838 can_issue_more
= issue_rate
;
25840 insn
= get_next_active_insn (prev_head_insn
, tail
);
25843 while (insn
!= NULL_RTX
)
25845 slot
= (issue_rate
- can_issue_more
);
25846 group_insns
[slot
] = insn
;
25848 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
25849 if (insn_terminates_group_p (insn
, current_group
))
25850 can_issue_more
= 0;
25852 next_insn
= get_next_active_insn (insn
, tail
);
25853 if (next_insn
== NULL_RTX
)
25854 return group_count
+ 1;
25856 /* Is next_insn going to start a new group? */
25858 = (can_issue_more
== 0
25859 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
25860 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
25861 || (can_issue_more
< issue_rate
&&
25862 insn_terminates_group_p (next_insn
, previous_group
)));
25864 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
25865 next_insn
, &group_end
, can_issue_more
,
25871 can_issue_more
= 0;
25872 for (i
= 0; i
< issue_rate
; i
++)
25874 group_insns
[i
] = 0;
25878 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
25879 PUT_MODE (next_insn
, VOIDmode
);
25880 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
25881 PUT_MODE (next_insn
, TImode
);
25884 if (can_issue_more
== 0)
25885 can_issue_more
= issue_rate
;
25888 return group_count
;
25891 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
25892 dispatch group boundaries that the scheduler had marked. Pad with nops
25893 any dispatch groups which have vacant issue slots, in order to force the
25894 scheduler's grouping on the processor dispatcher. The function
25895 returns the number of dispatch groups found. */
25898 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
25900 rtx insn
, next_insn
;
25903 int can_issue_more
;
25905 int group_count
= 0;
25907 /* Initialize issue_rate. */
25908 issue_rate
= rs6000_issue_rate ();
25909 can_issue_more
= issue_rate
;
25911 insn
= get_next_active_insn (prev_head_insn
, tail
);
25912 next_insn
= get_next_active_insn (insn
, tail
);
25914 while (insn
!= NULL_RTX
)
25917 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
25919 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
25921 if (next_insn
== NULL_RTX
)
25926 /* If the scheduler had marked group termination at this location
25927 (between insn and next_insn), and neither insn nor next_insn will
25928 force group termination, pad the group with nops to force group
25931 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
25932 && !insn_terminates_group_p (insn
, current_group
)
25933 && !insn_terminates_group_p (next_insn
, previous_group
))
25935 if (!is_branch_slot_insn (next_insn
))
25938 while (can_issue_more
)
25941 emit_insn_before (nop
, next_insn
);
25946 can_issue_more
= issue_rate
;
25951 next_insn
= get_next_active_insn (insn
, tail
);
25954 return group_count
;
25957 /* We're beginning a new block. Initialize data structures as necessary. */
25960 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
25961 int sched_verbose ATTRIBUTE_UNUSED
,
25962 int max_ready ATTRIBUTE_UNUSED
)
25964 last_scheduled_insn
= NULL_RTX
;
25965 load_store_pendulum
= 0;
25968 /* The following function is called at the end of scheduling BB.
25969 After reload, it inserts nops at insn group bundling. */
25972 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
25977 fprintf (dump
, "=== Finishing schedule.\n");
25979 if (reload_completed
&& rs6000_sched_groups
)
25981 /* Do not run sched_finish hook when selective scheduling enabled. */
25982 if (sel_sched_p ())
25985 if (rs6000_sched_insert_nops
== sched_finish_none
)
25988 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
25989 n_groups
= pad_groups (dump
, sched_verbose
,
25990 current_sched_info
->prev_head
,
25991 current_sched_info
->next_tail
);
25993 n_groups
= redefine_groups (dump
, sched_verbose
,
25994 current_sched_info
->prev_head
,
25995 current_sched_info
->next_tail
);
25997 if (sched_verbose
>= 6)
25999 fprintf (dump
, "ngroups = %d\n", n_groups
);
26000 print_rtl (dump
, current_sched_info
->prev_head
);
26001 fprintf (dump
, "Done finish_sched\n");
26006 struct _rs6000_sched_context
26008 short cached_can_issue_more
;
26009 rtx last_scheduled_insn
;
26010 int load_store_pendulum
;
26013 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
26014 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
26016 /* Allocate store for new scheduling context. */
26018 rs6000_alloc_sched_context (void)
26020 return xmalloc (sizeof (rs6000_sched_context_def
));
26023 /* If CLEAN_P is true then initializes _SC with clean data,
26024 and from the global context otherwise. */
26026 rs6000_init_sched_context (void *_sc
, bool clean_p
)
26028 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
26032 sc
->cached_can_issue_more
= 0;
26033 sc
->last_scheduled_insn
= NULL_RTX
;
26034 sc
->load_store_pendulum
= 0;
26038 sc
->cached_can_issue_more
= cached_can_issue_more
;
26039 sc
->last_scheduled_insn
= last_scheduled_insn
;
26040 sc
->load_store_pendulum
= load_store_pendulum
;
26044 /* Sets the global scheduling context to the one pointed to by _SC. */
26046 rs6000_set_sched_context (void *_sc
)
26048 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
26050 gcc_assert (sc
!= NULL
);
26052 cached_can_issue_more
= sc
->cached_can_issue_more
;
26053 last_scheduled_insn
= sc
->last_scheduled_insn
;
26054 load_store_pendulum
= sc
->load_store_pendulum
;
26059 rs6000_free_sched_context (void *_sc
)
26061 gcc_assert (_sc
!= NULL
);
26067 /* Length in units of the trampoline for entering a nested function. */
26070 rs6000_trampoline_size (void)
26074 switch (DEFAULT_ABI
)
26077 gcc_unreachable ();
26080 ret
= (TARGET_32BIT
) ? 12 : 24;
26085 ret
= (TARGET_32BIT
) ? 40 : 48;
26092 /* Emit RTL insns to initialize the variable parts of a trampoline.
26093 FNADDR is an RTX for the address of the function's pure code.
26094 CXT is an RTX for the static chain value for the function. */
26097 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
26099 int regsize
= (TARGET_32BIT
) ? 4 : 8;
26100 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
26101 rtx ctx_reg
= force_reg (Pmode
, cxt
);
26102 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
26104 switch (DEFAULT_ABI
)
26107 gcc_unreachable ();
26109 /* Under AIX, just build the 3 word function descriptor */
26112 rtx fnmem
, fn_reg
, toc_reg
;
26114 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
26115 error ("You cannot take the address of a nested function if you use "
26116 "the -mno-pointers-to-nested-functions option.");
26118 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
26119 fn_reg
= gen_reg_rtx (Pmode
);
26120 toc_reg
= gen_reg_rtx (Pmode
);
26122 /* Macro to shorten the code expansions below. */
26123 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
26125 m_tramp
= replace_equiv_address (m_tramp
, addr
);
26127 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
26128 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
26129 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
26130 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
26131 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
26137 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
26140 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
26141 LCT_NORMAL
, VOIDmode
, 4,
26143 GEN_INT (rs6000_trampoline_size ()), SImode
,
26151 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
26152 identifier as an argument, so the front end shouldn't look it up. */
26155 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
26157 return is_attribute_p ("altivec", attr_id
);
26160 /* Handle the "altivec" attribute. The attribute may have
26161 arguments as follows:
26163 __attribute__((altivec(vector__)))
26164 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
26165 __attribute__((altivec(bool__))) (always followed by 'unsigned')
26167 and may appear more than once (e.g., 'vector bool char') in a
26168 given declaration. */
26171 rs6000_handle_altivec_attribute (tree
*node
,
26172 tree name ATTRIBUTE_UNUSED
,
26174 int flags ATTRIBUTE_UNUSED
,
26175 bool *no_add_attrs
)
26177 tree type
= *node
, result
= NULL_TREE
;
26178 enum machine_mode mode
;
26181 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
26182 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
26183 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
26186 while (POINTER_TYPE_P (type
)
26187 || TREE_CODE (type
) == FUNCTION_TYPE
26188 || TREE_CODE (type
) == METHOD_TYPE
26189 || TREE_CODE (type
) == ARRAY_TYPE
)
26190 type
= TREE_TYPE (type
);
26192 mode
= TYPE_MODE (type
);
26194 /* Check for invalid AltiVec type qualifiers. */
26195 if (type
== long_double_type_node
)
26196 error ("use of %<long double%> in AltiVec types is invalid");
26197 else if (type
== boolean_type_node
)
26198 error ("use of boolean types in AltiVec types is invalid");
26199 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
26200 error ("use of %<complex%> in AltiVec types is invalid");
26201 else if (DECIMAL_FLOAT_MODE_P (mode
))
26202 error ("use of decimal floating point types in AltiVec types is invalid");
26203 else if (!TARGET_VSX
)
26205 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
26208 error ("use of %<long%> in AltiVec types is invalid for "
26209 "64-bit code without -mvsx");
26210 else if (rs6000_warn_altivec_long
)
26211 warning (0, "use of %<long%> in AltiVec types is deprecated; "
26214 else if (type
== long_long_unsigned_type_node
26215 || type
== long_long_integer_type_node
)
26216 error ("use of %<long long%> in AltiVec types is invalid without "
26218 else if (type
== double_type_node
)
26219 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
26222 switch (altivec_type
)
26225 unsigned_p
= TYPE_UNSIGNED (type
);
26229 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
26232 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
26235 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
26238 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
26240 case SFmode
: result
= V4SF_type_node
; break;
26241 case DFmode
: result
= V2DF_type_node
; break;
26242 /* If the user says 'vector int bool', we may be handed the 'bool'
26243 attribute _before_ the 'vector' attribute, and so select the
26244 proper type in the 'b' case below. */
26245 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
26246 case V2DImode
: case V2DFmode
:
26254 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
26255 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
26256 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
26257 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
26264 case V8HImode
: result
= pixel_V8HI_type_node
;
26270 /* Propagate qualifiers attached to the element type
26271 onto the vector type. */
26272 if (result
&& result
!= type
&& TYPE_QUALS (type
))
26273 result
= build_qualified_type (result
, TYPE_QUALS (type
));
26275 *no_add_attrs
= true; /* No need to hang on to the attribute. */
26278 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
26283 /* AltiVec defines four built-in scalar types that serve as vector
26284 elements; we must teach the compiler how to mangle them. */
26286 static const char *
26287 rs6000_mangle_type (const_tree type
)
26289 type
= TYPE_MAIN_VARIANT (type
);
26291 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
26292 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
26295 if (type
== bool_char_type_node
) return "U6__boolc";
26296 if (type
== bool_short_type_node
) return "U6__bools";
26297 if (type
== pixel_type_node
) return "u7__pixel";
26298 if (type
== bool_int_type_node
) return "U6__booli";
26299 if (type
== bool_long_type_node
) return "U6__booll";
26301 /* Mangle IBM extended float long double as `g' (__float128) on
26302 powerpc*-linux where long-double-64 previously was the default. */
26303 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
26305 && TARGET_LONG_DOUBLE_128
26306 && !TARGET_IEEEQUAD
)
26309 /* For all other types, use normal C++ mangling. */
26313 /* Handle a "longcall" or "shortcall" attribute; arguments as in
26314 struct attribute_spec.handler. */
26317 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
26318 tree args ATTRIBUTE_UNUSED
,
26319 int flags ATTRIBUTE_UNUSED
,
26320 bool *no_add_attrs
)
26322 if (TREE_CODE (*node
) != FUNCTION_TYPE
26323 && TREE_CODE (*node
) != FIELD_DECL
26324 && TREE_CODE (*node
) != TYPE_DECL
)
26326 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
26328 *no_add_attrs
= true;
26334 /* Set longcall attributes on all functions declared when
26335 rs6000_default_long_calls is true. */
26337 rs6000_set_default_type_attributes (tree type
)
26339 if (rs6000_default_long_calls
26340 && (TREE_CODE (type
) == FUNCTION_TYPE
26341 || TREE_CODE (type
) == METHOD_TYPE
))
26342 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
26344 TYPE_ATTRIBUTES (type
));
26347 darwin_set_default_type_attributes (type
);
26351 /* Return a reference suitable for calling a function with the
26352 longcall attribute. */
26355 rs6000_longcall_ref (rtx call_ref
)
26357 const char *call_name
;
26360 if (GET_CODE (call_ref
) != SYMBOL_REF
)
26363 /* System V adds '.' to the internal name, so skip them. */
26364 call_name
= XSTR (call_ref
, 0);
26365 if (*call_name
== '.')
26367 while (*call_name
== '.')
26370 node
= get_identifier (call_name
);
26371 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
26374 return force_reg (Pmode
, call_ref
);
26377 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
26378 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
26381 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26382 struct attribute_spec.handler. */
26384 rs6000_handle_struct_attribute (tree
*node
, tree name
,
26385 tree args ATTRIBUTE_UNUSED
,
26386 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
26389 if (DECL_P (*node
))
26391 if (TREE_CODE (*node
) == TYPE_DECL
)
26392 type
= &TREE_TYPE (*node
);
26397 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
26398 || TREE_CODE (*type
) == UNION_TYPE
)))
26400 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
26401 *no_add_attrs
= true;
26404 else if ((is_attribute_p ("ms_struct", name
)
26405 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
26406 || ((is_attribute_p ("gcc_struct", name
)
26407 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
26409 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
26411 *no_add_attrs
= true;
26418 rs6000_ms_bitfield_layout_p (const_tree record_type
)
26420 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
26421 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
26422 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
26425 #ifdef USING_ELFOS_H
26427 /* A get_unnamed_section callback, used for switching to toc_section. */
26430 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
26432 if (DEFAULT_ABI
== ABI_AIX
26433 && TARGET_MINIMAL_TOC
26434 && !TARGET_RELOCATABLE
)
26436 if (!toc_initialized
)
26438 toc_initialized
= 1;
26439 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
26440 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
26441 fprintf (asm_out_file
, "\t.tc ");
26442 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
26443 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
26444 fprintf (asm_out_file
, "\n");
26446 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
26447 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
26448 fprintf (asm_out_file
, " = .+32768\n");
26451 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
26453 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
26454 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
26457 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
26458 if (!toc_initialized
)
26460 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
26461 fprintf (asm_out_file
, " = .+32768\n");
26462 toc_initialized
= 1;
26467 /* Implement TARGET_ASM_INIT_SECTIONS. */
26470 rs6000_elf_asm_init_sections (void)
26473 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
26476 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
26477 SDATA2_SECTION_ASM_OP
);
26480 /* Implement TARGET_SELECT_RTX_SECTION. */
26483 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
26484 unsigned HOST_WIDE_INT align
)
26486 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
26487 return toc_section
;
26489 return default_elf_select_rtx_section (mode
, x
, align
);
26492 /* For a SYMBOL_REF, set generic flags and then perform some
26493 target-specific processing.
26495 When the AIX ABI is requested on a non-AIX system, replace the
26496 function name with the real name (with a leading .) rather than the
26497 function descriptor name. This saves a lot of overriding code to
26498 read the prefixes. */
26500 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
26502 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
26504 default_encode_section_info (decl
, rtl
, first
);
26507 && TREE_CODE (decl
) == FUNCTION_DECL
26509 && DEFAULT_ABI
== ABI_AIX
)
26511 rtx sym_ref
= XEXP (rtl
, 0);
26512 size_t len
= strlen (XSTR (sym_ref
, 0));
26513 char *str
= XALLOCAVEC (char, len
+ 2);
26515 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
26516 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
26521 compare_section_name (const char *section
, const char *templ
)
26525 len
= strlen (templ
);
26526 return (strncmp (section
, templ
, len
) == 0
26527 && (section
[len
] == 0 || section
[len
] == '.'));
26531 rs6000_elf_in_small_data_p (const_tree decl
)
26533 if (rs6000_sdata
== SDATA_NONE
)
26536 /* We want to merge strings, so we never consider them small data. */
26537 if (TREE_CODE (decl
) == STRING_CST
)
26540 /* Functions are never in the small data area. */
26541 if (TREE_CODE (decl
) == FUNCTION_DECL
)
26544 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
26546 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
26547 if (compare_section_name (section
, ".sdata")
26548 || compare_section_name (section
, ".sdata2")
26549 || compare_section_name (section
, ".gnu.linkonce.s")
26550 || compare_section_name (section
, ".sbss")
26551 || compare_section_name (section
, ".sbss2")
26552 || compare_section_name (section
, ".gnu.linkonce.sb")
26553 || strcmp (section
, ".PPC.EMB.sdata0") == 0
26554 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
26559 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
26562 && size
<= g_switch_value
26563 /* If it's not public, and we're not going to reference it there,
26564 there's no need to put it in the small data section. */
26565 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
26572 #endif /* USING_ELFOS_H */
26574 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
26577 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
26579 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
26582 /* Do not place thread-local symbols refs in the object blocks. */
26585 rs6000_use_blocks_for_decl_p (const_tree decl
)
26587 return !DECL_THREAD_LOCAL_P (decl
);
26590 /* Return a REG that occurs in ADDR with coefficient 1.
26591 ADDR can be effectively incremented by incrementing REG.
26593 r0 is special and we must not select it as an address
26594 register by this routine since our caller will try to
26595 increment the returned register via an "la" instruction. */
26598 find_addr_reg (rtx addr
)
26600 while (GET_CODE (addr
) == PLUS
)
26602 if (GET_CODE (XEXP (addr
, 0)) == REG
26603 && REGNO (XEXP (addr
, 0)) != 0)
26604 addr
= XEXP (addr
, 0);
26605 else if (GET_CODE (XEXP (addr
, 1)) == REG
26606 && REGNO (XEXP (addr
, 1)) != 0)
26607 addr
= XEXP (addr
, 1);
26608 else if (CONSTANT_P (XEXP (addr
, 0)))
26609 addr
= XEXP (addr
, 1);
26610 else if (CONSTANT_P (XEXP (addr
, 1)))
26611 addr
= XEXP (addr
, 0);
26613 gcc_unreachable ();
26615 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
26620 rs6000_fatal_bad_address (rtx op
)
26622 fatal_insn ("bad address", op
);
26627 typedef struct branch_island_d
{
26628 tree function_name
;
26634 static vec
<branch_island
, va_gc
> *branch_islands
;
26636 /* Remember to generate a branch island for far calls to the given
26640 add_compiler_branch_island (tree label_name
, tree function_name
,
26643 branch_island bi
= {function_name
, label_name
, line_number
};
26644 vec_safe_push (branch_islands
, bi
);
26647 /* Generate far-jump branch islands for everything recorded in
26648 branch_islands. Invoked immediately after the last instruction of
26649 the epilogue has been emitted; the branch islands must be appended
26650 to, and contiguous with, the function body. Mach-O stubs are
26651 generated in machopic_output_stub(). */
26654 macho_branch_islands (void)
26658 while (!vec_safe_is_empty (branch_islands
))
26660 branch_island
*bi
= &branch_islands
->last ();
26661 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
26662 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
26663 char name_buf
[512];
26664 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
26665 if (name
[0] == '*' || name
[0] == '&')
26666 strcpy (name_buf
, name
+1);
26670 strcpy (name_buf
+1, name
);
26672 strcpy (tmp_buf
, "\n");
26673 strcat (tmp_buf
, label
);
26674 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
26675 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
26676 dbxout_stabd (N_SLINE
, bi
->line_number
);
26677 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
26680 if (TARGET_LINK_STACK
)
26683 get_ppc476_thunk_name (name
);
26684 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
26685 strcat (tmp_buf
, name
);
26686 strcat (tmp_buf
, "\n");
26687 strcat (tmp_buf
, label
);
26688 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
26692 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
26693 strcat (tmp_buf
, label
);
26694 strcat (tmp_buf
, "_pic\n");
26695 strcat (tmp_buf
, label
);
26696 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
26699 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
26700 strcat (tmp_buf
, name_buf
);
26701 strcat (tmp_buf
, " - ");
26702 strcat (tmp_buf
, label
);
26703 strcat (tmp_buf
, "_pic)\n");
26705 strcat (tmp_buf
, "\tmtlr r0\n");
26707 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
26708 strcat (tmp_buf
, name_buf
);
26709 strcat (tmp_buf
, " - ");
26710 strcat (tmp_buf
, label
);
26711 strcat (tmp_buf
, "_pic)\n");
26713 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
26717 strcat (tmp_buf
, ":\nlis r12,hi16(");
26718 strcat (tmp_buf
, name_buf
);
26719 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
26720 strcat (tmp_buf
, name_buf
);
26721 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
26723 output_asm_insn (tmp_buf
, 0);
26724 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
26725 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
26726 dbxout_stabd (N_SLINE
, bi
->line_number
);
26727 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
26728 branch_islands
->pop ();
26732 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
26733 already there or not. */
26736 no_previous_def (tree function_name
)
26741 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
26742 if (function_name
== bi
->function_name
)
26747 /* GET_PREV_LABEL gets the label name from the previous definition of
26751 get_prev_label (tree function_name
)
26756 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
26757 if (function_name
== bi
->function_name
)
26758 return bi
->label_name
;
26762 /* INSN is either a function call or a millicode call. It may have an
26763 unconditional jump in its delay slot.
26765 CALL_DEST is the routine we are calling. */
26768 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
26769 int cookie_operand_number
)
26771 static char buf
[256];
26772 if (darwin_emit_branch_islands
26773 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
26774 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
26777 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
26779 if (no_previous_def (funname
))
26781 rtx label_rtx
= gen_label_rtx ();
26782 char *label_buf
, temp_buf
[256];
26783 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
26784 CODE_LABEL_NUMBER (label_rtx
));
26785 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
26786 labelname
= get_identifier (label_buf
);
26787 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
26790 labelname
= get_prev_label (funname
);
26792 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
26793 instruction will reach 'foo', otherwise link as 'bl L42'".
26794 "L42" should be a 'branch island', that will do a far jump to
26795 'foo'. Branch islands are generated in
26796 macho_branch_islands(). */
26797 sprintf (buf
, "jbsr %%z%d,%.246s",
26798 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
26801 sprintf (buf
, "bl %%z%d", dest_operand_number
);
26805 /* Generate PIC and indirect symbol stubs. */
26808 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
26810 unsigned int length
;
26811 char *symbol_name
, *lazy_ptr_name
;
26812 char *local_label_0
;
26813 static int label
= 0;
26815 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26816 symb
= (*targetm
.strip_name_encoding
) (symb
);
26819 length
= strlen (symb
);
26820 symbol_name
= XALLOCAVEC (char, length
+ 32);
26821 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
26823 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
26824 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
26827 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
26829 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
26833 fprintf (file
, "\t.align 5\n");
26835 fprintf (file
, "%s:\n", stub
);
26836 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
26839 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
26840 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
26842 fprintf (file
, "\tmflr r0\n");
26843 if (TARGET_LINK_STACK
)
26846 get_ppc476_thunk_name (name
);
26847 fprintf (file
, "\tbl %s\n", name
);
26848 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
26852 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
26853 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
26855 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
26856 lazy_ptr_name
, local_label_0
);
26857 fprintf (file
, "\tmtlr r0\n");
26858 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
26859 (TARGET_64BIT
? "ldu" : "lwzu"),
26860 lazy_ptr_name
, local_label_0
);
26861 fprintf (file
, "\tmtctr r12\n");
26862 fprintf (file
, "\tbctr\n");
26866 fprintf (file
, "\t.align 4\n");
26868 fprintf (file
, "%s:\n", stub
);
26869 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
26871 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
26872 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
26873 (TARGET_64BIT
? "ldu" : "lwzu"),
26875 fprintf (file
, "\tmtctr r12\n");
26876 fprintf (file
, "\tbctr\n");
26879 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
26880 fprintf (file
, "%s:\n", lazy_ptr_name
);
26881 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
26882 fprintf (file
, "%sdyld_stub_binding_helper\n",
26883 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
26886 /* Legitimize PIC addresses. If the address is already
26887 position-independent, we return ORIG. Newly generated
26888 position-independent addresses go into a reg. This is REG if non
26889 zero, otherwise we allocate register(s) as necessary. */
26891 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
26894 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
26899 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
26900 reg
= gen_reg_rtx (Pmode
);
26902 if (GET_CODE (orig
) == CONST
)
26906 if (GET_CODE (XEXP (orig
, 0)) == PLUS
26907 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
26910 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
26912 /* Use a different reg for the intermediate value, as
26913 it will be marked UNCHANGING. */
26914 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
26915 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
26918 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
26921 if (GET_CODE (offset
) == CONST_INT
)
26923 if (SMALL_INT (offset
))
26924 return plus_constant (Pmode
, base
, INTVAL (offset
));
26925 else if (! reload_in_progress
&& ! reload_completed
)
26926 offset
= force_reg (Pmode
, offset
);
26929 rtx mem
= force_const_mem (Pmode
, orig
);
26930 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
26933 return gen_rtx_PLUS (Pmode
, base
, offset
);
26936 /* Fall back on generic machopic code. */
26937 return machopic_legitimize_pic_address (orig
, mode
, reg
);
26940 /* Output a .machine directive for the Darwin assembler, and call
26941 the generic start_file routine. */
26944 rs6000_darwin_file_start (void)
26946 static const struct
26950 HOST_WIDE_INT if_set
;
26952 { "ppc64", "ppc64", MASK_64BIT
},
26953 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
26954 { "power4", "ppc970", 0 },
26955 { "G5", "ppc970", 0 },
26956 { "7450", "ppc7450", 0 },
26957 { "7400", "ppc7400", MASK_ALTIVEC
},
26958 { "G4", "ppc7400", 0 },
26959 { "750", "ppc750", 0 },
26960 { "740", "ppc750", 0 },
26961 { "G3", "ppc750", 0 },
26962 { "604e", "ppc604e", 0 },
26963 { "604", "ppc604", 0 },
26964 { "603e", "ppc603", 0 },
26965 { "603", "ppc603", 0 },
26966 { "601", "ppc601", 0 },
26967 { NULL
, "ppc", 0 } };
26968 const char *cpu_id
= "";
26971 rs6000_file_start ();
26972 darwin_file_start ();
26974 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
26976 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
26977 cpu_id
= rs6000_default_cpu
;
26979 if (global_options_set
.x_rs6000_cpu_index
)
26980 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
26982 /* Look through the mapping array. Pick the first name that either
26983 matches the argument, has a bit set in IF_SET that is also set
26984 in the target flags, or has a NULL name. */
26987 while (mapping
[i
].arg
!= NULL
26988 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
26989 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
26992 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
26995 #endif /* TARGET_MACHO */
26999 rs6000_elf_reloc_rw_mask (void)
27003 else if (DEFAULT_ABI
== ABI_AIX
)
27009 /* Record an element in the table of global constructors. SYMBOL is
27010 a SYMBOL_REF of the function to be called; PRIORITY is a number
27011 between 0 and MAX_INIT_PRIORITY.
27013 This differs from default_named_section_asm_out_constructor in
27014 that we have special handling for -mrelocatable. */
27016 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
27018 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
27020 const char *section
= ".ctors";
27023 if (priority
!= DEFAULT_INIT_PRIORITY
)
27025 sprintf (buf
, ".ctors.%.5u",
27026 /* Invert the numbering so the linker puts us in the proper
27027 order; constructors are run from right to left, and the
27028 linker sorts in increasing order. */
27029 MAX_INIT_PRIORITY
- priority
);
27033 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
27034 assemble_align (POINTER_SIZE
);
27036 if (TARGET_RELOCATABLE
)
27038 fputs ("\t.long (", asm_out_file
);
27039 output_addr_const (asm_out_file
, symbol
);
27040 fputs (")@fixup\n", asm_out_file
);
27043 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
27046 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
27048 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
27050 const char *section
= ".dtors";
27053 if (priority
!= DEFAULT_INIT_PRIORITY
)
27055 sprintf (buf
, ".dtors.%.5u",
27056 /* Invert the numbering so the linker puts us in the proper
27057 order; constructors are run from right to left, and the
27058 linker sorts in increasing order. */
27059 MAX_INIT_PRIORITY
- priority
);
27063 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
27064 assemble_align (POINTER_SIZE
);
27066 if (TARGET_RELOCATABLE
)
27068 fputs ("\t.long (", asm_out_file
);
27069 output_addr_const (asm_out_file
, symbol
);
27070 fputs (")@fixup\n", asm_out_file
);
27073 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
27077 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
27081 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
27082 ASM_OUTPUT_LABEL (file
, name
);
27083 fputs (DOUBLE_INT_ASM_OP
, file
);
27084 rs6000_output_function_entry (file
, name
);
27085 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
27088 fputs ("\t.size\t", file
);
27089 assemble_name (file
, name
);
27090 fputs (",24\n\t.type\t.", file
);
27091 assemble_name (file
, name
);
27092 fputs (",@function\n", file
);
27093 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
27095 fputs ("\t.globl\t.", file
);
27096 assemble_name (file
, name
);
27101 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
27102 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
27103 rs6000_output_function_entry (file
, name
);
27104 fputs (":\n", file
);
27108 if (TARGET_RELOCATABLE
27109 && !TARGET_SECURE_PLT
27110 && (get_pool_size () != 0 || crtl
->profile
)
27115 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
27117 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
27118 fprintf (file
, "\t.long ");
27119 assemble_name (file
, buf
);
27121 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27122 assemble_name (file
, buf
);
27126 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
27127 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
27129 if (DEFAULT_ABI
== ABI_AIX
)
27131 const char *desc_name
, *orig_name
;
27133 orig_name
= (*targetm
.strip_name_encoding
) (name
);
27134 desc_name
= orig_name
;
27135 while (*desc_name
== '.')
27138 if (TREE_PUBLIC (decl
))
27139 fprintf (file
, "\t.globl %s\n", desc_name
);
27141 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27142 fprintf (file
, "%s:\n", desc_name
);
27143 fprintf (file
, "\t.long %s\n", orig_name
);
27144 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
27145 if (DEFAULT_ABI
== ABI_AIX
)
27146 fputs ("\t.long 0\n", file
);
27147 fprintf (file
, "\t.previous\n");
27149 ASM_OUTPUT_LABEL (file
, name
);
27152 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
27154 rs6000_elf_file_end (void)
27156 #ifdef HAVE_AS_GNU_ATTRIBUTE
27157 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
27159 if (rs6000_passes_float
)
27160 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
27161 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
27162 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
27164 if (rs6000_passes_vector
)
27165 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
27166 (TARGET_ALTIVEC_ABI
? 2
27167 : TARGET_SPE_ABI
? 3
27169 if (rs6000_returns_struct
)
27170 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
27171 aix_struct_return
? 2 : 1);
27174 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
27176 file_end_indicate_exec_stack ();
27183 rs6000_xcoff_asm_output_anchor (rtx symbol
)
27187 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
27188 SYMBOL_REF_BLOCK_OFFSET (symbol
));
27189 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
27193 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
27195 fputs (GLOBAL_ASM_OP
, stream
);
27196 RS6000_OUTPUT_BASENAME (stream
, name
);
27197 putc ('\n', stream
);
27200 /* A get_unnamed_decl callback, used for read-only sections. PTR
27201 points to the section string variable. */
27204 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
27206 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
27207 *(const char *const *) directive
,
27208 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
27211 /* Likewise for read-write sections. */
27214 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
27216 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
27217 *(const char *const *) directive
,
27218 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
27222 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
27224 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
27225 *(const char *const *) directive
,
27226 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
27229 /* A get_unnamed_section callback, used for switching to toc_section. */
27232 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
27234 if (TARGET_MINIMAL_TOC
)
27236 /* toc_section is always selected at least once from
27237 rs6000_xcoff_file_start, so this is guaranteed to
27238 always be defined once and only once in each file. */
27239 if (!toc_initialized
)
27241 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
27242 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
27243 toc_initialized
= 1;
27245 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
27246 (TARGET_32BIT
? "" : ",3"));
27249 fputs ("\t.toc\n", asm_out_file
);
27252 /* Implement TARGET_ASM_INIT_SECTIONS. */
27255 rs6000_xcoff_asm_init_sections (void)
27257 read_only_data_section
27258 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
27259 &xcoff_read_only_section_name
);
27261 private_data_section
27262 = get_unnamed_section (SECTION_WRITE
,
27263 rs6000_xcoff_output_readwrite_section_asm_op
,
27264 &xcoff_private_data_section_name
);
27267 = get_unnamed_section (SECTION_TLS
,
27268 rs6000_xcoff_output_tls_section_asm_op
,
27269 &xcoff_tls_data_section_name
);
27271 tls_private_data_section
27272 = get_unnamed_section (SECTION_TLS
,
27273 rs6000_xcoff_output_tls_section_asm_op
,
27274 &xcoff_private_data_section_name
);
27276 read_only_private_data_section
27277 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
27278 &xcoff_private_data_section_name
);
27281 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
27283 readonly_data_section
= read_only_data_section
;
27284 exception_section
= data_section
;
27288 rs6000_xcoff_reloc_rw_mask (void)
27294 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
27295 tree decl ATTRIBUTE_UNUSED
)
27298 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
27300 if (flags
& SECTION_CODE
)
27302 else if (flags
& SECTION_TLS
)
27304 else if (flags
& SECTION_WRITE
)
27309 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
27310 (flags
& SECTION_CODE
) ? "." : "",
27311 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
27315 rs6000_xcoff_select_section (tree decl
, int reloc
,
27316 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
27318 if (decl_readonly_section (decl
, reloc
))
27320 if (TREE_PUBLIC (decl
))
27321 return read_only_data_section
;
27323 return read_only_private_data_section
;
27328 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
27330 if (TREE_PUBLIC (decl
))
27331 return tls_data_section
;
27332 else if (bss_initializer_p (decl
))
27334 /* Convert to COMMON to emit in BSS. */
27335 DECL_COMMON (decl
) = 1;
27336 return tls_comm_section
;
27339 return tls_private_data_section
;
27343 if (TREE_PUBLIC (decl
))
27344 return data_section
;
27346 return private_data_section
;
27351 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
27355 /* Use select_section for private and uninitialized data. */
27356 if (!TREE_PUBLIC (decl
)
27357 || DECL_COMMON (decl
)
27358 || DECL_INITIAL (decl
) == NULL_TREE
27359 || DECL_INITIAL (decl
) == error_mark_node
27360 || (flag_zero_initialized_in_bss
27361 && initializer_zerop (DECL_INITIAL (decl
))))
27364 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
27365 name
= (*targetm
.strip_name_encoding
) (name
);
27366 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
27369 /* Select section for constant in constant pool.
27371 On RS/6000, all constants are in the private read-only data area.
27372 However, if this is being placed in the TOC it must be output as a
27376 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
27377 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
27379 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
27380 return toc_section
;
27382 return read_only_private_data_section
;
27385 /* Remove any trailing [DS] or the like from the symbol name. */
27387 static const char *
27388 rs6000_xcoff_strip_name_encoding (const char *name
)
27393 len
= strlen (name
);
27394 if (name
[len
- 1] == ']')
27395 return ggc_alloc_string (name
, len
- 4);
27400 /* Section attributes. AIX is always PIC. */
27402 static unsigned int
27403 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
27405 unsigned int align
;
27406 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
27408 /* Align to at least UNIT size. */
27409 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
27410 align
= MIN_UNITS_PER_WORD
;
27412 /* Increase alignment of large objects if not already stricter. */
27413 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
27414 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
27415 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
27417 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
27420 /* Output at beginning of assembler file.
27422 Initialize the section names for the RS/6000 at this point.
27424 Specify filename, including full path, to assembler.
27426 We want to go into the TOC section so at least one .toc will be emitted.
27427 Also, in order to output proper .bs/.es pairs, we need at least one static
27428 [RW] section emitted.
27430 Finally, declare mcount when profiling to make the assembler happy. */
27433 rs6000_xcoff_file_start (void)
27435 rs6000_gen_section_name (&xcoff_bss_section_name
,
27436 main_input_filename
, ".bss_");
27437 rs6000_gen_section_name (&xcoff_private_data_section_name
,
27438 main_input_filename
, ".rw_");
27439 rs6000_gen_section_name (&xcoff_read_only_section_name
,
27440 main_input_filename
, ".ro_");
27441 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
27442 main_input_filename
, ".tls_");
27443 rs6000_gen_section_name (&xcoff_tbss_section_name
,
27444 main_input_filename
, ".tbss_[UL]");
27446 fputs ("\t.file\t", asm_out_file
);
27447 output_quoted_string (asm_out_file
, main_input_filename
);
27448 fputc ('\n', asm_out_file
);
27449 if (write_symbols
!= NO_DEBUG
)
27450 switch_to_section (private_data_section
);
27451 switch_to_section (text_section
);
27453 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
27454 rs6000_file_start ();
27457 /* Output at end of assembler file.
27458 On the RS/6000, referencing data should automatically pull in text. */
27461 rs6000_xcoff_file_end (void)
27463 switch_to_section (text_section
);
27464 fputs ("_section_.text:\n", asm_out_file
);
27465 switch_to_section (data_section
);
27466 fputs (TARGET_32BIT
27467 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
27473 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
27478 default_encode_section_info (decl
, rtl
, first
);
27480 /* Careful not to prod global register variables. */
27483 symbol
= XEXP (rtl
, 0);
27484 if (GET_CODE (symbol
) != SYMBOL_REF
)
27487 flags
= SYMBOL_REF_FLAGS (symbol
);
27489 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
27490 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
27492 SYMBOL_REF_FLAGS (symbol
) = flags
;
27494 #endif /* HAVE_AS_TLS */
27495 #endif /* TARGET_XCOFF */
27497 /* Compute a (partial) cost for rtx X. Return true if the complete
27498 cost has been computed, and false if subexpressions should be
27499 scanned. In either case, *TOTAL contains the cost result. */
27502 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
27503 int *total
, bool speed
)
27505 enum machine_mode mode
= GET_MODE (x
);
27509 /* On the RS/6000, if it is valid in the insn, it is free. */
27511 if (((outer_code
== SET
27512 || outer_code
== PLUS
27513 || outer_code
== MINUS
)
27514 && (satisfies_constraint_I (x
)
27515 || satisfies_constraint_L (x
)))
27516 || (outer_code
== AND
27517 && (satisfies_constraint_K (x
)
27519 ? satisfies_constraint_L (x
)
27520 : satisfies_constraint_J (x
))
27521 || mask_operand (x
, mode
)
27523 && mask64_operand (x
, DImode
))))
27524 || ((outer_code
== IOR
|| outer_code
== XOR
)
27525 && (satisfies_constraint_K (x
)
27527 ? satisfies_constraint_L (x
)
27528 : satisfies_constraint_J (x
))))
27529 || outer_code
== ASHIFT
27530 || outer_code
== ASHIFTRT
27531 || outer_code
== LSHIFTRT
27532 || outer_code
== ROTATE
27533 || outer_code
== ROTATERT
27534 || outer_code
== ZERO_EXTRACT
27535 || (outer_code
== MULT
27536 && satisfies_constraint_I (x
))
27537 || ((outer_code
== DIV
|| outer_code
== UDIV
27538 || outer_code
== MOD
|| outer_code
== UMOD
)
27539 && exact_log2 (INTVAL (x
)) >= 0)
27540 || (outer_code
== COMPARE
27541 && (satisfies_constraint_I (x
)
27542 || satisfies_constraint_K (x
)))
27543 || ((outer_code
== EQ
|| outer_code
== NE
)
27544 && (satisfies_constraint_I (x
)
27545 || satisfies_constraint_K (x
)
27547 ? satisfies_constraint_L (x
)
27548 : satisfies_constraint_J (x
))))
27549 || (outer_code
== GTU
27550 && satisfies_constraint_I (x
))
27551 || (outer_code
== LTU
27552 && satisfies_constraint_P (x
)))
27557 else if ((outer_code
== PLUS
27558 && reg_or_add_cint_operand (x
, VOIDmode
))
27559 || (outer_code
== MINUS
27560 && reg_or_sub_cint_operand (x
, VOIDmode
))
27561 || ((outer_code
== SET
27562 || outer_code
== IOR
27563 || outer_code
== XOR
)
27565 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
27567 *total
= COSTS_N_INSNS (1);
27577 /* When optimizing for size, MEM should be slightly more expensive
27578 than generating address, e.g., (plus (reg) (const)).
27579 L1 cache latency is about two instructions. */
27580 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
27589 if (FLOAT_MODE_P (mode
))
27590 *total
= rs6000_cost
->fp
;
27592 *total
= COSTS_N_INSNS (1);
27596 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
27597 && satisfies_constraint_I (XEXP (x
, 1)))
27599 if (INTVAL (XEXP (x
, 1)) >= -256
27600 && INTVAL (XEXP (x
, 1)) <= 255)
27601 *total
= rs6000_cost
->mulsi_const9
;
27603 *total
= rs6000_cost
->mulsi_const
;
27605 else if (mode
== SFmode
)
27606 *total
= rs6000_cost
->fp
;
27607 else if (FLOAT_MODE_P (mode
))
27608 *total
= rs6000_cost
->dmul
;
27609 else if (mode
== DImode
)
27610 *total
= rs6000_cost
->muldi
;
27612 *total
= rs6000_cost
->mulsi
;
27616 if (mode
== SFmode
)
27617 *total
= rs6000_cost
->fp
;
27619 *total
= rs6000_cost
->dmul
;
27624 if (FLOAT_MODE_P (mode
))
27626 *total
= mode
== DFmode
? rs6000_cost
->ddiv
27627 : rs6000_cost
->sdiv
;
27634 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
27635 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
27637 if (code
== DIV
|| code
== MOD
)
27639 *total
= COSTS_N_INSNS (2);
27642 *total
= COSTS_N_INSNS (1);
27646 if (GET_MODE (XEXP (x
, 1)) == DImode
)
27647 *total
= rs6000_cost
->divdi
;
27649 *total
= rs6000_cost
->divsi
;
27651 /* Add in shift and subtract for MOD. */
27652 if (code
== MOD
|| code
== UMOD
)
27653 *total
+= COSTS_N_INSNS (2);
27658 *total
= COSTS_N_INSNS (4);
27662 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
27666 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
27670 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
27682 *total
= COSTS_N_INSNS (1);
27690 /* Handle mul_highpart. */
27691 if (outer_code
== TRUNCATE
27692 && GET_CODE (XEXP (x
, 0)) == MULT
)
27694 if (mode
== DImode
)
27695 *total
= rs6000_cost
->muldi
;
27697 *total
= rs6000_cost
->mulsi
;
27700 else if (outer_code
== AND
)
27703 *total
= COSTS_N_INSNS (1);
27708 if (GET_CODE (XEXP (x
, 0)) == MEM
)
27711 *total
= COSTS_N_INSNS (1);
27717 if (!FLOAT_MODE_P (mode
))
27719 *total
= COSTS_N_INSNS (1);
27725 case UNSIGNED_FLOAT
:
27728 case FLOAT_TRUNCATE
:
27729 *total
= rs6000_cost
->fp
;
27733 if (mode
== DFmode
)
27736 *total
= rs6000_cost
->fp
;
27740 switch (XINT (x
, 1))
27743 *total
= rs6000_cost
->fp
;
27755 *total
= COSTS_N_INSNS (1);
27758 else if (FLOAT_MODE_P (mode
)
27759 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
27761 *total
= rs6000_cost
->fp
;
27769 /* Carry bit requires mode == Pmode.
27770 NEG or PLUS already counted so only add one. */
27772 && (outer_code
== NEG
|| outer_code
== PLUS
))
27774 *total
= COSTS_N_INSNS (1);
27777 if (outer_code
== SET
)
27779 if (XEXP (x
, 1) == const0_rtx
)
27781 if (TARGET_ISEL
&& !TARGET_MFCRF
)
27782 *total
= COSTS_N_INSNS (8);
27784 *total
= COSTS_N_INSNS (2);
27787 else if (mode
== Pmode
)
27789 *total
= COSTS_N_INSNS (3);
27798 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
27800 if (TARGET_ISEL
&& !TARGET_MFCRF
)
27801 *total
= COSTS_N_INSNS (8);
27803 *total
= COSTS_N_INSNS (2);
27807 if (outer_code
== COMPARE
)
27821 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
27824 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
27827 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
27830 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
27831 "opno = %d, total = %d, speed = %s, x:\n",
27832 ret
? "complete" : "scan inner",
27833 GET_RTX_NAME (code
),
27834 GET_RTX_NAME (outer_code
),
27837 speed
? "true" : "false");
27844 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
27847 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
27848 addr_space_t as
, bool speed
)
27850 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
27852 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
27853 ret
, speed
? "true" : "false");
27860 /* A C expression returning the cost of moving data from a register of class
27861 CLASS1 to one of CLASS2. */
27864 rs6000_register_move_cost (enum machine_mode mode
,
27865 reg_class_t from
, reg_class_t to
)
27869 if (TARGET_DEBUG_COST
)
27872 /* Moves from/to GENERAL_REGS. */
27873 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
27874 || reg_classes_intersect_p (from
, GENERAL_REGS
))
27876 reg_class_t rclass
= from
;
27878 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
27881 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
27882 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
27883 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
27885 /* It's more expensive to move CR_REGS than CR0_REGS because of the
27887 else if (rclass
== CR_REGS
)
27890 /* For those processors that have slow LR/CTR moves, make them more
27891 expensive than memory in order to bias spills to memory .*/
27892 else if ((rs6000_cpu
== PROCESSOR_POWER6
27893 || rs6000_cpu
== PROCESSOR_POWER7
27894 || rs6000_cpu
== PROCESSOR_POWER8
)
27895 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
27896 ret
= 6 * hard_regno_nregs
[0][mode
];
27899 /* A move will cost one instruction per GPR moved. */
27900 ret
= 2 * hard_regno_nregs
[0][mode
];
27903 /* If we have VSX, we can easily move between FPR or Altivec registers. */
27904 else if (VECTOR_MEM_VSX_P (mode
)
27905 && reg_classes_intersect_p (to
, VSX_REGS
)
27906 && reg_classes_intersect_p (from
, VSX_REGS
))
27907 ret
= 2 * hard_regno_nregs
[32][mode
];
27909 /* Moving between two similar registers is just one instruction. */
27910 else if (reg_classes_intersect_p (to
, from
))
27911 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
27913 /* Everything else has to go through GENERAL_REGS. */
27915 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
27916 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
27918 if (TARGET_DEBUG_COST
)
27920 if (dbg_cost_ctrl
== 1)
27922 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
27923 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
27924 reg_class_names
[to
]);
27931 /* A C expressions returning the cost of moving data of MODE from a register to
27935 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
27936 bool in ATTRIBUTE_UNUSED
)
27940 if (TARGET_DEBUG_COST
)
27943 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
27944 ret
= 4 * hard_regno_nregs
[0][mode
];
27945 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
27946 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
27947 ret
= 4 * hard_regno_nregs
[32][mode
];
27948 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
27949 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
27951 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
27953 if (TARGET_DEBUG_COST
)
27955 if (dbg_cost_ctrl
== 1)
27957 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
27958 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
27965 /* Returns a code for a target-specific builtin that implements
27966 reciprocal of the function, or NULL_TREE if not available. */
27969 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
27970 bool sqrt ATTRIBUTE_UNUSED
)
27972 if (optimize_insn_for_size_p ())
27978 case VSX_BUILTIN_XVSQRTDP
:
27979 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
27982 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
27984 case VSX_BUILTIN_XVSQRTSP
:
27985 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
27988 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
27997 case BUILT_IN_SQRT
:
27998 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
28001 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
28003 case BUILT_IN_SQRTF
:
28004 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
28007 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
28014 /* Load up a constant. If the mode is a vector mode, splat the value across
28015 all of the vector elements. */
28018 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
28022 if (mode
== SFmode
|| mode
== DFmode
)
28024 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
28025 reg
= force_reg (mode
, d
);
28027 else if (mode
== V4SFmode
)
28029 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
28030 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
28031 reg
= gen_reg_rtx (mode
);
28032 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
28034 else if (mode
== V2DFmode
)
28036 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
28037 rtvec v
= gen_rtvec (2, d
, d
);
28038 reg
= gen_reg_rtx (mode
);
28039 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
28042 gcc_unreachable ();
28047 /* Generate an FMA instruction. */
28050 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
28052 enum machine_mode mode
= GET_MODE (target
);
28055 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
28056 gcc_assert (dst
!= NULL
);
28059 emit_move_insn (target
, dst
);
28062 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
28065 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
28067 enum machine_mode mode
= GET_MODE (target
);
28070 /* Altivec does not support fms directly;
28071 generate in terms of fma in that case. */
28072 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
28073 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
28076 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
28077 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
28079 gcc_assert (dst
!= NULL
);
28082 emit_move_insn (target
, dst
);
28085 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
28088 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
28090 enum machine_mode mode
= GET_MODE (dst
);
28093 /* This is a tad more complicated, since the fnma_optab is for
28094 a different expression: fma(-m1, m2, a), which is the same
28095 thing except in the case of signed zeros.
28097 Fortunately we know that if FMA is supported that FNMSUB is
28098 also supported in the ISA. Just expand it directly. */
28100 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
28102 r
= gen_rtx_NEG (mode
, a
);
28103 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
28104 r
= gen_rtx_NEG (mode
, r
);
28105 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
28108 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
28109 add a reg_note saying that this was a division. Support both scalar and
28110 vector divide. Assumes no trapping math and finite arguments. */
28113 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
28115 enum machine_mode mode
= GET_MODE (dst
);
28116 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
28119 /* Low precision estimates guarantee 5 bits of accuracy. High
28120 precision estimates guarantee 14 bits of accuracy. SFmode
28121 requires 23 bits of accuracy. DFmode requires 52 bits of
28122 accuracy. Each pass at least doubles the accuracy, leading
28123 to the following. */
28124 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
28125 if (mode
== DFmode
|| mode
== V2DFmode
)
28128 enum insn_code code
= optab_handler (smul_optab
, mode
);
28129 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
28131 gcc_assert (code
!= CODE_FOR_nothing
);
28133 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
28135 /* x0 = 1./d estimate */
28136 x0
= gen_reg_rtx (mode
);
28137 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
28138 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
28141 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
28144 /* e0 = 1. - d * x0 */
28145 e0
= gen_reg_rtx (mode
);
28146 rs6000_emit_nmsub (e0
, d
, x0
, one
);
28148 /* x1 = x0 + e0 * x0 */
28149 x1
= gen_reg_rtx (mode
);
28150 rs6000_emit_madd (x1
, e0
, x0
, x0
);
28152 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
28153 ++i
, xprev
= xnext
, eprev
= enext
) {
28155 /* enext = eprev * eprev */
28156 enext
= gen_reg_rtx (mode
);
28157 emit_insn (gen_mul (enext
, eprev
, eprev
));
28159 /* xnext = xprev + enext * xprev */
28160 xnext
= gen_reg_rtx (mode
);
28161 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
28167 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
28169 /* u = n * xprev */
28170 u
= gen_reg_rtx (mode
);
28171 emit_insn (gen_mul (u
, n
, xprev
));
28173 /* v = n - (d * u) */
28174 v
= gen_reg_rtx (mode
);
28175 rs6000_emit_nmsub (v
, d
, u
, n
);
28177 /* dst = (v * xprev) + u */
28178 rs6000_emit_madd (dst
, v
, xprev
, u
);
28181 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
28184 /* Newton-Raphson approximation of single/double-precision floating point
28185 rsqrt. Assumes no trapping math and finite arguments. */
28188 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
28190 enum machine_mode mode
= GET_MODE (src
);
28191 rtx x0
= gen_reg_rtx (mode
);
28192 rtx y
= gen_reg_rtx (mode
);
28194 /* Low precision estimates guarantee 5 bits of accuracy. High
28195 precision estimates guarantee 14 bits of accuracy. SFmode
28196 requires 23 bits of accuracy. DFmode requires 52 bits of
28197 accuracy. Each pass at least doubles the accuracy, leading
28198 to the following. */
28199 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
28200 if (mode
== DFmode
|| mode
== V2DFmode
)
28203 REAL_VALUE_TYPE dconst3_2
;
28206 enum insn_code code
= optab_handler (smul_optab
, mode
);
28207 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
28209 gcc_assert (code
!= CODE_FOR_nothing
);
28211 /* Load up the constant 1.5 either as a scalar, or as a vector. */
28212 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
28213 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
28215 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
28217 /* x0 = rsqrt estimate */
28218 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
28219 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
28222 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
28223 rs6000_emit_msub (y
, src
, halfthree
, src
);
28225 for (i
= 0; i
< passes
; i
++)
28227 rtx x1
= gen_reg_rtx (mode
);
28228 rtx u
= gen_reg_rtx (mode
);
28229 rtx v
= gen_reg_rtx (mode
);
28231 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
28232 emit_insn (gen_mul (u
, x0
, x0
));
28233 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
28234 emit_insn (gen_mul (x1
, x0
, v
));
28238 emit_move_insn (dst
, x0
);
28242 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
28243 (Power7) targets. DST is the target, and SRC is the argument operand. */
28246 rs6000_emit_popcount (rtx dst
, rtx src
)
28248 enum machine_mode mode
= GET_MODE (dst
);
28251 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
28252 if (TARGET_POPCNTD
)
28254 if (mode
== SImode
)
28255 emit_insn (gen_popcntdsi2 (dst
, src
));
28257 emit_insn (gen_popcntddi2 (dst
, src
));
28261 tmp1
= gen_reg_rtx (mode
);
28263 if (mode
== SImode
)
28265 emit_insn (gen_popcntbsi2 (tmp1
, src
));
28266 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
28268 tmp2
= force_reg (SImode
, tmp2
);
28269 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
28273 emit_insn (gen_popcntbdi2 (tmp1
, src
));
28274 tmp2
= expand_mult (DImode
, tmp1
,
28275 GEN_INT ((HOST_WIDE_INT
)
28276 0x01010101 << 32 | 0x01010101),
28278 tmp2
= force_reg (DImode
, tmp2
);
28279 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
28284 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
28285 target, and SRC is the argument operand. */
28288 rs6000_emit_parity (rtx dst
, rtx src
)
28290 enum machine_mode mode
= GET_MODE (dst
);
28293 tmp
= gen_reg_rtx (mode
);
28295 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
28298 if (mode
== SImode
)
28300 emit_insn (gen_popcntbsi2 (tmp
, src
));
28301 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
28305 emit_insn (gen_popcntbdi2 (tmp
, src
));
28306 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
28311 if (mode
== SImode
)
28313 /* Is mult+shift >= shift+xor+shift+xor? */
28314 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
28316 rtx tmp1
, tmp2
, tmp3
, tmp4
;
28318 tmp1
= gen_reg_rtx (SImode
);
28319 emit_insn (gen_popcntbsi2 (tmp1
, src
));
28321 tmp2
= gen_reg_rtx (SImode
);
28322 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
28323 tmp3
= gen_reg_rtx (SImode
);
28324 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
28326 tmp4
= gen_reg_rtx (SImode
);
28327 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
28328 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
28331 rs6000_emit_popcount (tmp
, src
);
28332 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
28336 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
28337 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
28339 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
28341 tmp1
= gen_reg_rtx (DImode
);
28342 emit_insn (gen_popcntbdi2 (tmp1
, src
));
28344 tmp2
= gen_reg_rtx (DImode
);
28345 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
28346 tmp3
= gen_reg_rtx (DImode
);
28347 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
28349 tmp4
= gen_reg_rtx (DImode
);
28350 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
28351 tmp5
= gen_reg_rtx (DImode
);
28352 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
28354 tmp6
= gen_reg_rtx (DImode
);
28355 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
28356 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
28359 rs6000_emit_popcount (tmp
, src
);
28360 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
28364 /* Expand an Altivec constant permutation. Return true if we match
28365 an efficient implementation; false to fall back to VPERM. */
28368 altivec_expand_vec_perm_const (rtx operands
[4])
28370 struct altivec_perm_insn
{
28371 HOST_WIDE_INT mask
;
28372 enum insn_code impl
;
28373 unsigned char perm
[16];
28375 static const struct altivec_perm_insn patterns
[] = {
28376 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
,
28377 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
28378 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
,
28379 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
28380 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
,
28381 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
28382 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
,
28383 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
28384 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
,
28385 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
28386 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
,
28387 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
28388 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
,
28389 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
28390 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
,
28391 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
28392 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
28393 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
28394 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
28395 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
28398 unsigned int i
, j
, elt
, which
;
28399 unsigned char perm
[16];
28400 rtx target
, op0
, op1
, sel
, x
;
28403 target
= operands
[0];
28408 /* Unpack the constant selector. */
28409 for (i
= which
= 0; i
< 16; ++i
)
28411 rtx e
= XVECEXP (sel
, 0, i
);
28412 elt
= INTVAL (e
) & 31;
28413 which
|= (elt
< 16 ? 1 : 2);
28417 /* Simplify the constant selector based on operands. */
28421 gcc_unreachable ();
28425 if (!rtx_equal_p (op0
, op1
))
28430 for (i
= 0; i
< 16; ++i
)
28442 /* Look for splat patterns. */
28447 for (i
= 0; i
< 16; ++i
)
28448 if (perm
[i
] != elt
)
28452 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
28458 for (i
= 0; i
< 16; i
+= 2)
28459 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
28463 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
28464 x
= gen_reg_rtx (V8HImode
);
28465 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
28467 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
28474 for (i
= 0; i
< 16; i
+= 4)
28476 || perm
[i
+ 1] != elt
+ 1
28477 || perm
[i
+ 2] != elt
+ 2
28478 || perm
[i
+ 3] != elt
+ 3)
28482 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
28483 x
= gen_reg_rtx (V4SImode
);
28484 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
28486 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
28492 /* Look for merge and pack patterns. */
28493 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
28497 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
28500 elt
= patterns
[j
].perm
[0];
28501 if (perm
[0] == elt
)
28503 else if (perm
[0] == elt
+ 16)
28507 for (i
= 1; i
< 16; ++i
)
28509 elt
= patterns
[j
].perm
[i
];
28511 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
28512 else if (one_vec
&& elt
>= 16)
28514 if (perm
[i
] != elt
)
28519 enum insn_code icode
= patterns
[j
].impl
;
28520 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
28521 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
28523 /* For little-endian, the two input operands must be swapped
28524 (or swapped back) to ensure proper right-to-left numbering
28526 if (swapped
^ !BYTES_BIG_ENDIAN
)
28527 x
= op0
, op0
= op1
, op1
= x
;
28528 if (imode
!= V16QImode
)
28530 op0
= gen_lowpart (imode
, op0
);
28531 op1
= gen_lowpart (imode
, op1
);
28533 if (omode
== V16QImode
)
28536 x
= gen_reg_rtx (omode
);
28537 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
28538 if (omode
!= V16QImode
)
28539 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
28547 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
28548 Return true if we match an efficient implementation. */
28551 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
28552 unsigned char perm0
, unsigned char perm1
)
28556 /* If both selectors come from the same operand, fold to single op. */
28557 if ((perm0
& 2) == (perm1
& 2))
28564 /* If both operands are equal, fold to simpler permutation. */
28565 if (rtx_equal_p (op0
, op1
))
28568 perm1
= (perm1
& 1) + 2;
28570 /* If the first selector comes from the second operand, swap. */
28571 else if (perm0
& 2)
28577 x
= op0
, op0
= op1
, op1
= x
;
28579 /* If the second selector does not come from the second operand, fail. */
28580 else if ((perm1
& 2) == 0)
28584 if (target
!= NULL
)
28586 enum machine_mode vmode
, dmode
;
28589 vmode
= GET_MODE (target
);
28590 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
28591 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
28593 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
28594 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
28595 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
28596 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
28602 rs6000_expand_vec_perm_const (rtx operands
[4])
28604 rtx target
, op0
, op1
, sel
;
28605 unsigned char perm0
, perm1
;
28607 target
= operands
[0];
28612 /* Unpack the constant selector. */
28613 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
28614 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
28616 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
28619 /* Test whether a constant permutation is supported. */
28622 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
28623 const unsigned char *sel
)
28625 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
28626 if (TARGET_ALTIVEC
)
28629 /* Check for ps_merge* or evmerge* insns. */
28630 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
28631 || (TARGET_SPE
&& vmode
== V2SImode
))
28633 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
28634 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
28635 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
28641 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
28644 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
28645 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
28647 enum machine_mode imode
;
28651 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
28653 imode
= GET_MODE_INNER (vmode
);
28654 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
28655 imode
= mode_for_vector (imode
, nelt
);
28658 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
28659 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
28661 emit_move_insn (target
, x
);
28664 /* Expand an extract even operation. */
28667 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
28669 enum machine_mode vmode
= GET_MODE (target
);
28670 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
28673 for (i
= 0; i
< nelt
; i
++)
28674 perm
[i
] = GEN_INT (i
* 2);
28676 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
28679 /* Expand a vector interleave operation. */
28682 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
28684 enum machine_mode vmode
= GET_MODE (target
);
28685 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
28688 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
28689 for (i
= 0; i
< nelt
/ 2; i
++)
28691 perm
[i
* 2] = GEN_INT (i
+ high
);
28692 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
28695 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
28698 /* Return an RTX representing where to find the function value of a
28699 function returning MODE. */
28701 rs6000_complex_function_value (enum machine_mode mode
)
28703 unsigned int regno
;
28705 enum machine_mode inner
= GET_MODE_INNER (mode
);
28706 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
28708 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28709 regno
= FP_ARG_RETURN
;
28712 regno
= GP_ARG_RETURN
;
28714 /* 32-bit is OK since it'll go in r3/r4. */
28715 if (TARGET_32BIT
&& inner_bytes
>= 4)
28716 return gen_rtx_REG (mode
, regno
);
28719 if (inner_bytes
>= 8)
28720 return gen_rtx_REG (mode
, regno
);
28722 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
28724 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
28725 GEN_INT (inner_bytes
));
28726 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
28729 /* Target hook for TARGET_FUNCTION_VALUE.
28731 On the SPE, both FPs and vectors are returned in r3.
28733 On RS/6000 an integer value is in r3 and a floating-point value is in
28734 fp1, unless -msoft-float. */
28737 rs6000_function_value (const_tree valtype
,
28738 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
28739 bool outgoing ATTRIBUTE_UNUSED
)
28741 enum machine_mode mode
;
28742 unsigned int regno
;
28744 /* Special handling for structs in darwin64. */
28746 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
28748 CUMULATIVE_ARGS valcum
;
28752 valcum
.fregno
= FP_ARG_MIN_REG
;
28753 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
28754 /* Do a trial code generation as if this were going to be passed as
28755 an argument; if any part goes in memory, we return NULL. */
28756 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
28759 /* Otherwise fall through to standard ABI rules. */
28762 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
28764 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
28765 return gen_rtx_PARALLEL (DImode
,
28767 gen_rtx_EXPR_LIST (VOIDmode
,
28768 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
28770 gen_rtx_EXPR_LIST (VOIDmode
,
28771 gen_rtx_REG (SImode
,
28772 GP_ARG_RETURN
+ 1),
28775 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
28777 return gen_rtx_PARALLEL (DCmode
,
28779 gen_rtx_EXPR_LIST (VOIDmode
,
28780 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
28782 gen_rtx_EXPR_LIST (VOIDmode
,
28783 gen_rtx_REG (SImode
,
28784 GP_ARG_RETURN
+ 1),
28786 gen_rtx_EXPR_LIST (VOIDmode
,
28787 gen_rtx_REG (SImode
,
28788 GP_ARG_RETURN
+ 2),
28790 gen_rtx_EXPR_LIST (VOIDmode
,
28791 gen_rtx_REG (SImode
,
28792 GP_ARG_RETURN
+ 3),
28796 mode
= TYPE_MODE (valtype
);
28797 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
28798 || POINTER_TYPE_P (valtype
))
28799 mode
= TARGET_32BIT
? SImode
: DImode
;
28801 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28802 /* _Decimal128 must use an even/odd register pair. */
28803 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
28804 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
28805 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
28806 regno
= FP_ARG_RETURN
;
28807 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
28808 && targetm
.calls
.split_complex_arg
)
28809 return rs6000_complex_function_value (mode
);
28810 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
28811 return register is used in both cases, and we won't see V2DImode/V2DFmode
28812 for pure altivec, combine the two cases. */
28813 else if (TREE_CODE (valtype
) == VECTOR_TYPE
28814 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
28815 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
28816 regno
= ALTIVEC_ARG_RETURN
;
28817 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
28818 && (mode
== DFmode
|| mode
== DCmode
28819 || mode
== TFmode
|| mode
== TCmode
))
28820 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
28822 regno
= GP_ARG_RETURN
;
28824 return gen_rtx_REG (mode
, regno
);
28827 /* Define how to find the value returned by a library function
28828 assuming the value has mode MODE. */
28830 rs6000_libcall_value (enum machine_mode mode
)
28832 unsigned int regno
;
28834 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
28836 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
28837 return gen_rtx_PARALLEL (DImode
,
28839 gen_rtx_EXPR_LIST (VOIDmode
,
28840 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
28842 gen_rtx_EXPR_LIST (VOIDmode
,
28843 gen_rtx_REG (SImode
,
28844 GP_ARG_RETURN
+ 1),
28848 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28849 /* _Decimal128 must use an even/odd register pair. */
28850 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
28851 else if (SCALAR_FLOAT_MODE_P (mode
)
28852 && TARGET_HARD_FLOAT
&& TARGET_FPRS
28853 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
28854 regno
= FP_ARG_RETURN
;
28855 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
28856 return register is used in both cases, and we won't see V2DImode/V2DFmode
28857 for pure altivec, combine the two cases. */
28858 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
28859 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
28860 regno
= ALTIVEC_ARG_RETURN
;
28861 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
28862 return rs6000_complex_function_value (mode
);
28863 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
28864 && (mode
== DFmode
|| mode
== DCmode
28865 || mode
== TFmode
|| mode
== TCmode
))
28866 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
28868 regno
= GP_ARG_RETURN
;
28870 return gen_rtx_REG (mode
, regno
);
28874 /* Given FROM and TO register numbers, say whether this elimination is allowed.
28875 Frame pointer elimination is automatically handled.
28877 For the RS/6000, if frame pointer elimination is being done, we would like
28878 to convert ap into fp, not sp.
28880 We need r30 if -mminimal-toc was specified, and there are constant pool
28884 rs6000_can_eliminate (const int from
, const int to
)
28886 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
28887 ? ! frame_pointer_needed
28888 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
28889 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
28893 /* Define the offset between two registers, FROM to be eliminated and its
28894 replacement TO, at the start of a routine. */
28896 rs6000_initial_elimination_offset (int from
, int to
)
28898 rs6000_stack_t
*info
= rs6000_stack_info ();
28899 HOST_WIDE_INT offset
;
28901 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
28902 offset
= info
->push_p
? 0 : -info
->total_size
;
28903 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
28905 offset
= info
->push_p
? 0 : -info
->total_size
;
28906 if (FRAME_GROWS_DOWNWARD
)
28907 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
28909 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
28910 offset
= FRAME_GROWS_DOWNWARD
28911 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
28913 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
28914 offset
= info
->total_size
;
28915 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
28916 offset
= info
->push_p
? info
->total_size
: 0;
28917 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
28920 gcc_unreachable ();
28926 rs6000_dwarf_register_span (rtx reg
)
28930 unsigned regno
= REGNO (reg
);
28931 enum machine_mode mode
= GET_MODE (reg
);
28935 && (SPE_VECTOR_MODE (GET_MODE (reg
))
28936 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
28937 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
28942 regno
= REGNO (reg
);
28944 /* The duality of the SPE register size wreaks all kinds of havoc.
28945 This is a way of distinguishing r0 in 32-bits from r0 in
28947 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
28948 gcc_assert (words
<= 4);
28949 for (i
= 0; i
< words
; i
++, regno
++)
28951 if (BYTES_BIG_ENDIAN
)
28953 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
28954 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
28958 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
28959 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
28963 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
28966 /* Fill in sizes for SPE register high parts in table used by unwinder. */
28969 rs6000_init_dwarf_reg_sizes_extra (tree address
)
28974 enum machine_mode mode
= TYPE_MODE (char_type_node
);
28975 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
28976 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
28977 rtx value
= gen_int_mode (4, mode
);
28979 for (i
= 1201; i
< 1232; i
++)
28981 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
28982 HOST_WIDE_INT offset
28983 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
28985 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
28990 /* Map internal gcc register numbers to DWARF2 register numbers. */
28993 rs6000_dbx_register_number (unsigned int regno
)
28995 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
28997 if (regno
== LR_REGNO
)
28999 if (regno
== CTR_REGNO
)
29001 if (CR_REGNO_P (regno
))
29002 return regno
- CR0_REGNO
+ 86;
29003 if (regno
== CA_REGNO
)
29004 return 101; /* XER */
29005 if (ALTIVEC_REGNO_P (regno
))
29006 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
29007 if (regno
== VRSAVE_REGNO
)
29009 if (regno
== VSCR_REGNO
)
29011 if (regno
== SPE_ACC_REGNO
)
29013 if (regno
== SPEFSCR_REGNO
)
29015 /* SPE high reg number. We get these values of regno from
29016 rs6000_dwarf_register_span. */
29017 gcc_assert (regno
>= 1200 && regno
< 1232);
29021 /* target hook eh_return_filter_mode */
29022 static enum machine_mode
29023 rs6000_eh_return_filter_mode (void)
29025 return TARGET_32BIT
? SImode
: word_mode
;
29028 /* Target hook for scalar_mode_supported_p. */
29030 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
29032 if (DECIMAL_FLOAT_MODE_P (mode
))
29033 return default_decimal_float_supported_p ();
29035 return default_scalar_mode_supported_p (mode
);
29038 /* Target hook for vector_mode_supported_p. */
29040 rs6000_vector_mode_supported_p (enum machine_mode mode
)
29043 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
29046 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
29049 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
29056 /* Target hook for invalid_arg_for_unprototyped_fn. */
29057 static const char *
29058 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
29060 return (!rs6000_darwin64_abi
29062 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
29063 && (funcdecl
== NULL_TREE
29064 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
29065 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
29066 ? N_("AltiVec argument passed to unprototyped function")
29070 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
29071 setup by using __stack_chk_fail_local hidden function instead of
29072 calling __stack_chk_fail directly. Otherwise it is better to call
29073 __stack_chk_fail directly. */
29075 static tree ATTRIBUTE_UNUSED
29076 rs6000_stack_protect_fail (void)
29078 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
29079 ? default_hidden_stack_protect_fail ()
29080 : default_external_stack_protect_fail ();
29084 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
29085 int num_operands ATTRIBUTE_UNUSED
)
29087 if (rs6000_warn_cell_microcode
)
29090 int insn_code_number
= recog_memoized (insn
);
29091 location_t location
= INSN_LOCATION (insn
);
29093 /* Punt on insns we cannot recognize. */
29094 if (insn_code_number
< 0)
29097 temp
= get_insn_template (insn_code_number
, insn
);
29099 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
29100 warning_at (location
, OPT_mwarn_cell_microcode
,
29101 "emitting microcode insn %s\t[%s] #%d",
29102 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
29103 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
29104 warning_at (location
, OPT_mwarn_cell_microcode
,
29105 "emitting conditional microcode insn %s\t[%s] #%d",
29106 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
29110 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
29113 static unsigned HOST_WIDE_INT
29114 rs6000_asan_shadow_offset (void)
29116 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
29120 /* Mask options that we want to support inside of attribute((target)) and
29121 #pragma GCC target operations. Note, we do not include things like
29122 64/32-bit, endianess, hard/soft floating point, etc. that would have
29123 different calling sequences. */
29125 struct rs6000_opt_mask
{
29126 const char *name
; /* option name */
29127 HOST_WIDE_INT mask
; /* mask to set */
29128 bool invert
; /* invert sense of mask */
29129 bool valid_target
; /* option is a target option */
29132 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
29134 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
29135 { "cmpb", OPTION_MASK_CMPB
, false, true },
29136 { "crypto", OPTION_MASK_CRYPTO
, false, true },
29137 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
29138 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
29139 { "fprnd", OPTION_MASK_FPRND
, false, true },
29140 { "hard-dfp", OPTION_MASK_DFP
, false, true },
29141 { "htm", OPTION_MASK_HTM
, false, true },
29142 { "isel", OPTION_MASK_ISEL
, false, true },
29143 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
29144 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
29145 { "mulhw", OPTION_MASK_MULHW
, false, true },
29146 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
29147 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
29148 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
29149 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
29150 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
29151 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
29152 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
29153 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
29154 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
29155 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
29156 { "string", OPTION_MASK_STRING
, false, true },
29157 { "update", OPTION_MASK_NO_UPDATE
, true , true },
29158 { "vsx", OPTION_MASK_VSX
, false, true },
29159 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
29160 #ifdef OPTION_MASK_64BIT
29162 { "aix64", OPTION_MASK_64BIT
, false, false },
29163 { "aix32", OPTION_MASK_64BIT
, true, false },
29165 { "64", OPTION_MASK_64BIT
, false, false },
29166 { "32", OPTION_MASK_64BIT
, true, false },
29169 #ifdef OPTION_MASK_EABI
29170 { "eabi", OPTION_MASK_EABI
, false, false },
29172 #ifdef OPTION_MASK_LITTLE_ENDIAN
29173 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
29174 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
29176 #ifdef OPTION_MASK_RELOCATABLE
29177 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
29179 #ifdef OPTION_MASK_STRICT_ALIGN
29180 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
29182 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
29183 { "string", OPTION_MASK_STRING
, false, false },
29186 /* Builtin mask mapping for printing the flags. */
29187 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
29189 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
29190 { "vsx", RS6000_BTM_VSX
, false, false },
29191 { "spe", RS6000_BTM_SPE
, false, false },
29192 { "paired", RS6000_BTM_PAIRED
, false, false },
29193 { "fre", RS6000_BTM_FRE
, false, false },
29194 { "fres", RS6000_BTM_FRES
, false, false },
29195 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
29196 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
29197 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
29198 { "cell", RS6000_BTM_CELL
, false, false },
29199 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
29200 { "crypto", RS6000_BTM_CRYPTO
, false, false },
29201 { "htm", RS6000_BTM_HTM
, false, false },
29204 /* Option variables that we want to support inside attribute((target)) and
29205 #pragma GCC target operations. */
29207 struct rs6000_opt_var
{
29208 const char *name
; /* option name */
29209 size_t global_offset
; /* offset of the option in global_options. */
29210 size_t target_offset
; /* offset of the option in target optiosn. */
29213 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
29216 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
29217 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
29218 { "avoid-indexed-addresses",
29219 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
29220 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
29222 offsetof (struct gcc_options
, x_rs6000_paired_float
),
29223 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
29225 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
29226 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
29229 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
29230 parsing. Return true if there were no errors. */
29233 rs6000_inner_target_options (tree args
, bool attr_p
)
29237 if (args
== NULL_TREE
)
29240 else if (TREE_CODE (args
) == STRING_CST
)
29242 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
29245 while ((q
= strtok (p
, ",")) != NULL
)
29247 bool error_p
= false;
29248 bool not_valid_p
= false;
29249 const char *cpu_opt
= NULL
;
29252 if (strncmp (q
, "cpu=", 4) == 0)
29254 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
29255 if (cpu_index
>= 0)
29256 rs6000_cpu_index
= cpu_index
;
29263 else if (strncmp (q
, "tune=", 5) == 0)
29265 int tune_index
= rs6000_cpu_name_lookup (q
+5);
29266 if (tune_index
>= 0)
29267 rs6000_tune_index
= tune_index
;
29277 bool invert
= false;
29281 if (strncmp (r
, "no-", 3) == 0)
29287 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
29288 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
29290 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
29292 if (!rs6000_opt_masks
[i
].valid_target
)
29293 not_valid_p
= true;
29297 rs6000_isa_flags_explicit
|= mask
;
29299 /* VSX needs altivec, so -mvsx automagically sets
29301 if (mask
== OPTION_MASK_VSX
&& !invert
)
29302 mask
|= OPTION_MASK_ALTIVEC
;
29304 if (rs6000_opt_masks
[i
].invert
)
29308 rs6000_isa_flags
&= ~mask
;
29310 rs6000_isa_flags
|= mask
;
29315 if (error_p
&& !not_valid_p
)
29317 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
29318 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
29320 size_t j
= rs6000_opt_vars
[i
].global_offset
;
29321 *((int *) ((char *)&global_options
+ j
)) = !invert
;
29330 const char *eprefix
, *esuffix
;
29335 eprefix
= "__attribute__((__target__(";
29340 eprefix
= "#pragma GCC target ";
29345 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
29347 else if (not_valid_p
)
29348 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
29350 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
29355 else if (TREE_CODE (args
) == TREE_LIST
)
29359 tree value
= TREE_VALUE (args
);
29362 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
29366 args
= TREE_CHAIN (args
);
29368 while (args
!= NULL_TREE
);
29372 gcc_unreachable ();
29377 /* Print out the target options as a list for -mdebug=target. */
29380 rs6000_debug_target_options (tree args
, const char *prefix
)
29382 if (args
== NULL_TREE
)
29383 fprintf (stderr
, "%s<NULL>", prefix
);
29385 else if (TREE_CODE (args
) == STRING_CST
)
29387 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
29390 while ((q
= strtok (p
, ",")) != NULL
)
29393 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
29398 else if (TREE_CODE (args
) == TREE_LIST
)
29402 tree value
= TREE_VALUE (args
);
29405 rs6000_debug_target_options (value
, prefix
);
29408 args
= TREE_CHAIN (args
);
29410 while (args
!= NULL_TREE
);
29414 gcc_unreachable ();
29420 /* Hook to validate attribute((target("..."))). */
29423 rs6000_valid_attribute_p (tree fndecl
,
29424 tree
ARG_UNUSED (name
),
29428 struct cl_target_option cur_target
;
29430 tree old_optimize
= build_optimization_node ();
29431 tree new_target
, new_optimize
;
29432 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
29434 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
29436 if (TARGET_DEBUG_TARGET
)
29438 tree tname
= DECL_NAME (fndecl
);
29439 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
29441 fprintf (stderr
, "function: %.*s\n",
29442 (int) IDENTIFIER_LENGTH (tname
),
29443 IDENTIFIER_POINTER (tname
));
29445 fprintf (stderr
, "function: unknown\n");
29447 fprintf (stderr
, "args:");
29448 rs6000_debug_target_options (args
, " ");
29449 fprintf (stderr
, "\n");
29452 fprintf (stderr
, "flags: 0x%x\n", flags
);
29454 fprintf (stderr
, "--------------------\n");
29457 old_optimize
= build_optimization_node ();
29458 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
29460 /* If the function changed the optimization levels as well as setting target
29461 options, start with the optimizations specified. */
29462 if (func_optimize
&& func_optimize
!= old_optimize
)
29463 cl_optimization_restore (&global_options
,
29464 TREE_OPTIMIZATION (func_optimize
));
29466 /* The target attributes may also change some optimization flags, so update
29467 the optimization options if necessary. */
29468 cl_target_option_save (&cur_target
, &global_options
);
29469 rs6000_cpu_index
= rs6000_tune_index
= -1;
29470 ret
= rs6000_inner_target_options (args
, true);
29472 /* Set up any additional state. */
29475 ret
= rs6000_option_override_internal (false);
29476 new_target
= build_target_option_node ();
29481 new_optimize
= build_optimization_node ();
29488 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
29490 if (old_optimize
!= new_optimize
)
29491 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
29494 cl_target_option_restore (&global_options
, &cur_target
);
29496 if (old_optimize
!= new_optimize
)
29497 cl_optimization_restore (&global_options
,
29498 TREE_OPTIMIZATION (old_optimize
));
29504 /* Hook to validate the current #pragma GCC target and set the state, and
29505 update the macros based on what was changed. If ARGS is NULL, then
29506 POP_TARGET is used to reset the options. */
29509 rs6000_pragma_target_parse (tree args
, tree pop_target
)
29511 tree prev_tree
= build_target_option_node ();
29513 struct cl_target_option
*prev_opt
, *cur_opt
;
29514 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
29515 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
29517 if (TARGET_DEBUG_TARGET
)
29519 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
29520 fprintf (stderr
, "args:");
29521 rs6000_debug_target_options (args
, " ");
29522 fprintf (stderr
, "\n");
29526 fprintf (stderr
, "pop_target:\n");
29527 debug_tree (pop_target
);
29530 fprintf (stderr
, "pop_target: <NULL>\n");
29532 fprintf (stderr
, "--------------------\n");
29537 cur_tree
= ((pop_target
)
29539 : target_option_default_node
);
29540 cl_target_option_restore (&global_options
,
29541 TREE_TARGET_OPTION (cur_tree
));
29545 rs6000_cpu_index
= rs6000_tune_index
= -1;
29546 if (!rs6000_inner_target_options (args
, false)
29547 || !rs6000_option_override_internal (false)
29548 || (cur_tree
= build_target_option_node ()) == NULL_TREE
)
29550 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
29551 fprintf (stderr
, "invalid pragma\n");
29557 target_option_current_node
= cur_tree
;
29559 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
29560 change the macros that are defined. */
29561 if (rs6000_target_modify_macros_ptr
)
29563 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
29564 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
29565 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
29567 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
29568 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
29569 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
29571 diff_bumask
= (prev_bumask
^ cur_bumask
);
29572 diff_flags
= (prev_flags
^ cur_flags
);
29574 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
29576 /* Delete old macros. */
29577 rs6000_target_modify_macros_ptr (false,
29578 prev_flags
& diff_flags
,
29579 prev_bumask
& diff_bumask
);
29581 /* Define new macros. */
29582 rs6000_target_modify_macros_ptr (true,
29583 cur_flags
& diff_flags
,
29584 cur_bumask
& diff_bumask
);
29592 /* Remember the last target of rs6000_set_current_function. */
29593 static GTY(()) tree rs6000_previous_fndecl
;
29595 /* Establish appropriate back-end context for processing the function
29596 FNDECL. The argument might be NULL to indicate processing at top
29597 level, outside of any function scope. */
29599 rs6000_set_current_function (tree fndecl
)
29601 tree old_tree
= (rs6000_previous_fndecl
29602 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
29605 tree new_tree
= (fndecl
29606 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
29609 if (TARGET_DEBUG_TARGET
)
29611 bool print_final
= false;
29612 fprintf (stderr
, "\n==================== rs6000_set_current_function");
29615 fprintf (stderr
, ", fndecl %s (%p)",
29616 (DECL_NAME (fndecl
)
29617 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
29618 : "<unknown>"), (void *)fndecl
);
29620 if (rs6000_previous_fndecl
)
29621 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
29623 fprintf (stderr
, "\n");
29626 fprintf (stderr
, "\nnew fndecl target specific options:\n");
29627 debug_tree (new_tree
);
29628 print_final
= true;
29633 fprintf (stderr
, "\nold fndecl target specific options:\n");
29634 debug_tree (old_tree
);
29635 print_final
= true;
29639 fprintf (stderr
, "--------------------\n");
29642 /* Only change the context if the function changes. This hook is called
29643 several times in the course of compiling a function, and we don't want to
29644 slow things down too much or call target_reinit when it isn't safe. */
29645 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
29647 rs6000_previous_fndecl
= fndecl
;
29648 if (old_tree
== new_tree
)
29653 cl_target_option_restore (&global_options
,
29654 TREE_TARGET_OPTION (new_tree
));
29660 struct cl_target_option
*def
29661 = TREE_TARGET_OPTION (target_option_current_node
);
29663 cl_target_option_restore (&global_options
, def
);
29670 /* Save the current options */
29673 rs6000_function_specific_save (struct cl_target_option
*ptr
)
29675 ptr
->x_rs6000_isa_flags
= rs6000_isa_flags
;
29676 ptr
->x_rs6000_isa_flags_explicit
= rs6000_isa_flags_explicit
;
29679 /* Restore the current options */
29682 rs6000_function_specific_restore (struct cl_target_option
*ptr
)
29684 rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
29685 rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
29686 (void) rs6000_option_override_internal (false);
29689 /* Print the current options */
29692 rs6000_function_specific_print (FILE *file
, int indent
,
29693 struct cl_target_option
*ptr
)
29695 rs6000_print_isa_options (file
, indent
, "Isa options set",
29696 ptr
->x_rs6000_isa_flags
);
29698 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
29699 ptr
->x_rs6000_isa_flags_explicit
);
29702 /* Helper function to print the current isa or misc options on a line. */
29705 rs6000_print_options_internal (FILE *file
,
29707 const char *string
,
29708 HOST_WIDE_INT flags
,
29709 const char *prefix
,
29710 const struct rs6000_opt_mask
*opts
,
29711 size_t num_elements
)
29714 size_t start_column
= 0;
29716 size_t max_column
= 76;
29717 const char *comma
= "";
29718 const char *nl
= "\n";
29721 start_column
+= fprintf (file
, "%*s", indent
, "");
29725 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
29729 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
29731 /* Print the various mask options. */
29732 cur_column
= start_column
;
29733 for (i
= 0; i
< num_elements
; i
++)
29735 if ((flags
& opts
[i
].mask
) != 0)
29737 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
29738 size_t len
= (strlen (comma
)
29741 + strlen (rs6000_opt_masks
[i
].name
));
29744 if (cur_column
> max_column
)
29746 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
29747 cur_column
= start_column
+ len
;
29752 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
29753 rs6000_opt_masks
[i
].name
);
29754 flags
&= ~ opts
[i
].mask
;
29762 /* Helper function to print the current isa options on a line. */
29765 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
29766 HOST_WIDE_INT flags
)
29768 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
29769 &rs6000_opt_masks
[0],
29770 ARRAY_SIZE (rs6000_opt_masks
));
29774 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
29775 HOST_WIDE_INT flags
)
29777 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
29778 &rs6000_builtin_mask_names
[0],
29779 ARRAY_SIZE (rs6000_builtin_mask_names
));
29783 /* Hook to determine if one function can safely inline another. */
29786 rs6000_can_inline_p (tree caller
, tree callee
)
29789 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
29790 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
29792 /* If callee has no option attributes, then it is ok to inline. */
29796 /* If caller has no option attributes, but callee does then it is not ok to
29798 else if (!caller_tree
)
29803 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
29804 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
29806 /* Callee's options should a subset of the caller's, i.e. a vsx function
29807 can inline an altivec function but a non-vsx function can't inline a
29809 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
29810 == callee_opts
->x_rs6000_isa_flags
)
29814 if (TARGET_DEBUG_TARGET
)
29815 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
29816 (DECL_NAME (caller
)
29817 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
29819 (DECL_NAME (callee
)
29820 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
29822 (ret
? "can" : "cannot"));
29827 /* Allocate a stack temp and fixup the address so it meets the particular
29828 memory requirements (either offetable or REG+REG addressing). */
29831 rs6000_allocate_stack_temp (enum machine_mode mode
,
29832 bool offsettable_p
,
29835 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
29836 rtx addr
= XEXP (stack
, 0);
29837 int strict_p
= (reload_in_progress
|| reload_completed
);
29839 if (!legitimate_indirect_address_p (addr
, strict_p
))
29842 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
29843 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
29845 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
29846 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
29852 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
29853 to such a form to deal with memory reference instructions like STFIWX that
29854 only take reg+reg addressing. */
29857 rs6000_address_for_fpconvert (rtx x
)
29859 int strict_p
= (reload_in_progress
|| reload_completed
);
29862 gcc_assert (MEM_P (x
));
29863 addr
= XEXP (x
, 0);
29864 if (! legitimate_indirect_address_p (addr
, strict_p
)
29865 && ! legitimate_indexed_address_p (addr
, strict_p
))
29867 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
29869 rtx reg
= XEXP (addr
, 0);
29870 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
29871 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
29872 gcc_assert (REG_P (reg
));
29873 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
29876 else if (GET_CODE (addr
) == PRE_MODIFY
)
29878 rtx reg
= XEXP (addr
, 0);
29879 rtx expr
= XEXP (addr
, 1);
29880 gcc_assert (REG_P (reg
));
29881 gcc_assert (GET_CODE (expr
) == PLUS
);
29882 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
29886 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
29892 /* Given a memory reference, if it is not in the form for altivec memory
29893 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
29894 convert to the altivec format. */
29897 rs6000_address_for_altivec (rtx x
)
29899 gcc_assert (MEM_P (x
));
29900 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
29902 rtx addr
= XEXP (x
, 0);
29903 int strict_p
= (reload_in_progress
|| reload_completed
);
29905 if (!legitimate_indexed_address_p (addr
, strict_p
)
29906 && !legitimate_indirect_address_p (addr
, strict_p
))
29907 addr
= copy_to_mode_reg (Pmode
, addr
);
29909 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
29910 x
= change_address (x
, GET_MODE (x
), addr
);
29916 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
29918 On the RS/6000, all integer constants are acceptable, most won't be valid
29919 for particular insns, though. Only easy FP constants are acceptable. */
29922 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
29924 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
29927 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
29928 || GET_MODE (x
) == VOIDmode
29929 || (TARGET_POWERPC64
&& mode
== DImode
)
29930 || easy_fp_constant (x
, mode
)
29931 || easy_vector_constant (x
, mode
));
29935 /* A function pointer under AIX is a pointer to a data area whose first word
29936 contains the actual address of the function, whose second word contains a
29937 pointer to its TOC, and whose third word contains a value to place in the
29938 static chain register (r11). Note that if we load the static chain, our
29939 "trampoline" need not have any executable code. */
29942 rs6000_call_indirect_aix (rtx value
, rtx func_desc
, rtx flag
)
29948 rtx stack_toc_offset
;
29950 rtx func_toc_offset
;
29952 rtx func_sc_offset
;
29955 rtx (*call_func
) (rtx
, rtx
, rtx
, rtx
);
29956 rtx (*call_value_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
29958 stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29959 toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
29961 /* Load up address of the actual function. */
29962 func_desc
= force_reg (Pmode
, func_desc
);
29963 func_addr
= gen_reg_rtx (Pmode
);
29964 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
29969 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_32BIT
);
29970 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_32BIT
);
29971 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_32BIT
);
29972 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
29974 call_func
= gen_call_indirect_aix32bit
;
29975 call_value_func
= gen_call_value_indirect_aix32bit
;
29979 call_func
= gen_call_indirect_aix32bit_nor11
;
29980 call_value_func
= gen_call_value_indirect_aix32bit_nor11
;
29985 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_64BIT
);
29986 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_64BIT
);
29987 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_64BIT
);
29988 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
29990 call_func
= gen_call_indirect_aix64bit
;
29991 call_value_func
= gen_call_value_indirect_aix64bit
;
29995 call_func
= gen_call_indirect_aix64bit_nor11
;
29996 call_value_func
= gen_call_value_indirect_aix64bit_nor11
;
30000 /* Reserved spot to store the TOC. */
30001 stack_toc_mem
= gen_frame_mem (Pmode
,
30002 gen_rtx_PLUS (Pmode
,
30004 stack_toc_offset
));
30007 gcc_assert (cfun
->machine
);
30009 /* Can we optimize saving the TOC in the prologue or do we need to do it at
30011 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
30012 cfun
->machine
->save_toc_in_prologue
= true;
30016 MEM_VOLATILE_P (stack_toc_mem
) = 1;
30017 emit_move_insn (stack_toc_mem
, toc_reg
);
30020 /* Calculate the address to load the TOC of the called function. We don't
30021 actually load this until the split after reload. */
30022 func_toc_mem
= gen_rtx_MEM (Pmode
,
30023 gen_rtx_PLUS (Pmode
,
30027 /* If we have a static chain, load it up. */
30028 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
30030 func_sc_mem
= gen_rtx_MEM (Pmode
,
30031 gen_rtx_PLUS (Pmode
,
30035 sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
30036 emit_move_insn (sc_reg
, func_sc_mem
);
30039 /* Create the call. */
30041 insn
= call_value_func (value
, func_addr
, flag
, func_toc_mem
,
30044 insn
= call_func (func_addr
, flag
, func_toc_mem
, stack_toc_mem
);
30046 emit_call_insn (insn
);
30049 /* Return whether we need to always update the saved TOC pointer when we update
30050 the stack pointer. */
30053 rs6000_save_toc_in_prologue_p (void)
30055 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
30058 #ifdef HAVE_GAS_HIDDEN
30059 # define USE_HIDDEN_LINKONCE 1
30061 # define USE_HIDDEN_LINKONCE 0
30064 /* Fills in the label name that should be used for a 476 link stack thunk. */
30067 get_ppc476_thunk_name (char name
[32])
30069 gcc_assert (TARGET_LINK_STACK
);
30071 if (USE_HIDDEN_LINKONCE
)
30072 sprintf (name
, "__ppc476.get_thunk");
30074 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
30077 /* This function emits the simple thunk routine that is used to preserve
30078 the link stack on the 476 cpu. */
30080 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
30082 rs6000_code_end (void)
30087 if (!TARGET_LINK_STACK
)
30090 get_ppc476_thunk_name (name
);
30092 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
30093 build_function_type_list (void_type_node
, NULL_TREE
));
30094 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
30095 NULL_TREE
, void_type_node
);
30096 TREE_PUBLIC (decl
) = 1;
30097 TREE_STATIC (decl
) = 1;
30100 if (USE_HIDDEN_LINKONCE
)
30102 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
30103 targetm
.asm_out
.unique_section (decl
, 0);
30104 switch_to_section (get_named_section (decl
, NULL
, 0));
30105 DECL_WEAK (decl
) = 1;
30106 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
30107 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
30108 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
30109 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
30114 switch_to_section (text_section
);
30115 ASM_OUTPUT_LABEL (asm_out_file
, name
);
30118 DECL_INITIAL (decl
) = make_node (BLOCK
);
30119 current_function_decl
= decl
;
30120 init_function_start (decl
);
30121 first_function_block_is_cold
= false;
30122 /* Make sure unwind info is emitted for the thunk if needed. */
30123 final_start_function (emit_barrier (), asm_out_file
, 1);
30125 fputs ("\tblr\n", asm_out_file
);
30127 final_end_function ();
30128 init_insn_lengths ();
30129 free_after_compilation (cfun
);
30131 current_function_decl
= NULL
;
30134 /* Add r30 to hard reg set if the prologue sets it up and it is not
30135 pic_offset_table_rtx. */
30138 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
30140 if (!TARGET_SINGLE_PIC_BASE
30142 && TARGET_MINIMAL_TOC
30143 && get_pool_size () != 0)
30144 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
30148 /* Helper function for rs6000_split_logical to emit a logical instruction after
30149 spliting the operation to single GPR registers.
30151 DEST is the destination register.
30152 OP1 and OP2 are the input source registers.
30153 CODE is the base operation (AND, IOR, XOR, NOT).
30154 MODE is the machine mode.
30155 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
30156 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
30157 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
30158 CLOBBER_REG is either NULL or a scratch register of type CC to allow
30159 formation of the AND instructions. */
30162 rs6000_split_logical_inner (rtx dest
,
30165 enum rtx_code code
,
30166 enum machine_mode mode
,
30167 bool complement_final_p
,
30168 bool complement_op1_p
,
30169 bool complement_op2_p
,
30175 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
30176 if (op2
&& GET_CODE (op2
) == CONST_INT
30177 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
30178 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
30180 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
30181 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
30183 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
30188 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
30192 else if (value
== mask
)
30194 if (!rtx_equal_p (dest
, op1
))
30195 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
30200 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
30201 into separate ORI/ORIS or XORI/XORIS instrucitons. */
30202 else if (code
== IOR
|| code
== XOR
)
30206 if (!rtx_equal_p (dest
, op1
))
30207 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
30213 if (complement_op1_p
)
30214 op1
= gen_rtx_NOT (mode
, op1
);
30216 if (complement_op2_p
)
30217 op2
= gen_rtx_NOT (mode
, op2
);
30219 bool_rtx
= ((code
== NOT
)
30220 ? gen_rtx_NOT (mode
, op1
)
30221 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
30223 if (complement_final_p
)
30224 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
30226 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
30228 /* Is this AND with an explicit clobber? */
30231 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
30232 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
30235 emit_insn (set_rtx
);
30239 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
30240 operations are split immediately during RTL generation to allow for more
30241 optimizations of the AND/IOR/XOR.
30243 OPERANDS is an array containing the destination and two input operands.
30244 CODE is the base operation (AND, IOR, XOR, NOT).
30245 MODE is the machine mode.
30246 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
30247 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
30248 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
30249 CLOBBER_REG is either NULL or a scratch register of type CC to allow
30250 formation of the AND instructions. */
30253 rs6000_split_logical_di (rtx operands
[3],
30254 enum rtx_code code
,
30255 bool complement_final_p
,
30256 bool complement_op1_p
,
30257 bool complement_op2_p
,
30260 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
30261 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
30262 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
30263 enum hi_lo
{ hi
= 0, lo
= 1 };
30264 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
30267 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
30268 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
30269 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
30270 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
30273 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
30276 if (GET_CODE (operands
[2]) != CONST_INT
)
30278 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
30279 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
30283 HOST_WIDE_INT value
= INTVAL (operands
[2]);
30284 HOST_WIDE_INT value_hi_lo
[2];
30286 gcc_assert (!complement_final_p
);
30287 gcc_assert (!complement_op1_p
);
30288 gcc_assert (!complement_op2_p
);
30290 value_hi_lo
[hi
] = value
>> 32;
30291 value_hi_lo
[lo
] = value
& lower_32bits
;
30293 for (i
= 0; i
< 2; i
++)
30295 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
30297 if (sub_value
& sign_bit
)
30298 sub_value
|= upper_32bits
;
30300 op2_hi_lo
[i
] = GEN_INT (sub_value
);
30302 /* If this is an AND instruction, check to see if we need to load
30303 the value in a register. */
30304 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
30305 && !and_operand (op2_hi_lo
[i
], SImode
))
30306 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
30311 for (i
= 0; i
< 2; i
++)
30313 /* Split large IOR/XOR operations. */
30314 if ((code
== IOR
|| code
== XOR
)
30315 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
30316 && !complement_final_p
30317 && !complement_op1_p
30318 && !complement_op2_p
30319 && clobber_reg
== NULL_RTX
30320 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
30322 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
30323 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
30324 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
30325 rtx tmp
= gen_reg_rtx (SImode
);
30327 /* Make sure the constant is sign extended. */
30328 if ((hi_16bits
& sign_bit
) != 0)
30329 hi_16bits
|= upper_32bits
;
30331 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
30332 code
, SImode
, false, false, false,
30335 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
30336 code
, SImode
, false, false, false,
30340 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
30341 code
, SImode
, complement_final_p
,
30342 complement_op1_p
, complement_op2_p
,
30349 /* Split the insns that make up boolean operations operating on multiple GPR
30350 registers. The boolean MD patterns ensure that the inputs either are
30351 exactly the same as the output registers, or there is no overlap.
30353 OPERANDS is an array containing the destination and two input operands.
30354 CODE is the base operation (AND, IOR, XOR, NOT).
30355 MODE is the machine mode.
30356 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
30357 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
30358 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
30359 CLOBBER_REG is either NULL or a scratch register of type CC to allow
30360 formation of the AND instructions. */
30363 rs6000_split_logical (rtx operands
[3],
30364 enum rtx_code code
,
30365 bool complement_final_p
,
30366 bool complement_op1_p
,
30367 bool complement_op2_p
,
30370 enum machine_mode mode
= GET_MODE (operands
[0]);
30371 enum machine_mode sub_mode
;
30373 int sub_size
, regno0
, regno1
, nregs
, i
;
30375 /* If this is DImode, use the specialized version that can run before
30376 register allocation. */
30377 if (mode
== DImode
&& !TARGET_POWERPC64
)
30379 rs6000_split_logical_di (operands
, code
, complement_final_p
,
30380 complement_op1_p
, complement_op2_p
,
30387 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
30388 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
30389 sub_size
= GET_MODE_SIZE (sub_mode
);
30390 regno0
= REGNO (op0
);
30391 regno1
= REGNO (op1
);
30393 gcc_assert (reload_completed
);
30394 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
30395 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
30397 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
30398 gcc_assert (nregs
> 1);
30400 if (op2
&& REG_P (op2
))
30401 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
30403 for (i
= 0; i
< nregs
; i
++)
30405 int offset
= i
* sub_size
;
30406 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
30407 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
30408 rtx sub_op2
= ((code
== NOT
)
30410 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
30412 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
30413 complement_final_p
, complement_op1_p
,
30414 complement_op2_p
, clobber_reg
);
30421 struct gcc_target targetm
= TARGET_INITIALIZER
;
30423 #include "gt-rs6000.h"