1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 /* This file should be included last. */
86 #include "target-def.h"
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
93 systems will also set long double to be IEEE 128-bit. AIX and Darwin
94 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
95 those systems will not pick up this default. This needs to be after all
96 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
98 #ifndef TARGET_IEEEQUAD_DEFAULT
99 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
100 #define TARGET_IEEEQUAD_DEFAULT 1
102 #define TARGET_IEEEQUAD_DEFAULT 0
106 static pad_direction
rs6000_function_arg_padding (machine_mode
, const_tree
);
108 /* Structure used to define the rs6000 stack */
109 typedef struct rs6000_stack
{
110 int reload_completed
; /* stack info won't change from here on */
111 int first_gp_reg_save
; /* first callee saved GP register used */
112 int first_fp_reg_save
; /* first callee saved FP register used */
113 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
114 int lr_save_p
; /* true if the link reg needs to be saved */
115 int cr_save_p
; /* true if the CR reg needs to be saved */
116 unsigned int vrsave_mask
; /* mask of vec registers to save */
117 int push_p
; /* true if we need to allocate stack space */
118 int calls_p
; /* true if the function makes any calls */
119 int world_save_p
; /* true if we're saving *everything*:
120 r13-r31, cr, f14-f31, vrsave, v20-v31 */
121 enum rs6000_abi abi
; /* which ABI to use */
122 int gp_save_offset
; /* offset to save GP regs from initial SP */
123 int fp_save_offset
; /* offset to save FP regs from initial SP */
124 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
125 int lr_save_offset
; /* offset to save LR from initial SP */
126 int cr_save_offset
; /* offset to save CR from initial SP */
127 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
128 int varargs_save_offset
; /* offset to save the varargs registers */
129 int ehrd_offset
; /* offset to EH return data */
130 int ehcr_offset
; /* offset to EH CR field data */
131 int reg_size
; /* register size (4 or 8) */
132 HOST_WIDE_INT vars_size
; /* variable save area size */
133 int parm_size
; /* outgoing parameter size */
134 int save_size
; /* save area size */
135 int fixed_size
; /* fixed size of stack frame */
136 int gp_size
; /* size of saved GP registers */
137 int fp_size
; /* size of saved FP registers */
138 int altivec_size
; /* size of saved AltiVec registers */
139 int cr_size
; /* size to hold CR if not in fixed area */
140 int vrsave_size
; /* size to hold VRSAVE */
141 int altivec_padding_size
; /* size of altivec alignment padding */
142 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
146 /* A C structure for machine-specific, per-function data.
147 This is added to the cfun structure. */
148 typedef struct GTY(()) machine_function
150 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
151 int ra_needs_full_frame
;
152 /* Flags if __builtin_return_address (0) was used. */
154 /* Cache lr_save_p after expansion of builtin_eh_return. */
156 /* Whether we need to save the TOC to the reserved stack location in the
157 function prologue. */
158 bool save_toc_in_prologue
;
159 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
160 varargs save area. */
161 HOST_WIDE_INT varargs_save_offset
;
162 /* Alternative internal arg pointer for -fsplit-stack. */
163 rtx split_stack_arg_pointer
;
164 bool split_stack_argp_used
;
165 /* Flag if r2 setup is needed with ELFv2 ABI. */
166 bool r2_setup_needed
;
167 /* The number of components we use for separate shrink-wrapping. */
169 /* The components already handled by separate shrink-wrapping, which should
170 not be considered by the prologue and epilogue. */
171 bool gpr_is_wrapped_separately
[32];
172 bool fpr_is_wrapped_separately
[32];
173 bool lr_is_wrapped_separately
;
174 bool toc_is_wrapped_separately
;
177 /* Support targetm.vectorize.builtin_mask_for_load. */
178 static GTY(()) tree altivec_builtin_mask_for_load
;
180 /* Set to nonzero once AIX common-mode calls have been defined. */
181 static GTY(()) int common_mode_defined
;
183 /* Label number of label created for -mrelocatable, to call to so we can
184 get the address of the GOT section */
185 static int rs6000_pic_labelno
;
188 /* Counter for labels which are to be placed in .fixup. */
189 int fixuplabelno
= 0;
192 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
195 /* Specify the machine mode that pointers have. After generation of rtl, the
196 compiler makes no further distinction between pointers and any other objects
197 of this machine mode. */
198 scalar_int_mode rs6000_pmode
;
201 /* Note whether IEEE 128-bit floating point was passed or returned, either as
202 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
203 floating point. We changed the default C++ mangling for these types and we
204 may want to generate a weak alias of the old mangling (U10__float128) to the
205 new mangling (u9__ieee128). */
206 static bool rs6000_passes_ieee128
;
209 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
210 name used in current releases (i.e. u9__ieee128). */
211 static bool ieee128_mangling_gcc_8_1
;
213 /* Width in bits of a pointer. */
214 unsigned rs6000_pointer_size
;
216 #ifdef HAVE_AS_GNU_ATTRIBUTE
217 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
218 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
220 /* Flag whether floating point values have been passed/returned.
221 Note that this doesn't say whether fprs are used, since the
222 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
223 should be set for soft-float values passed in gprs and ieee128
224 values passed in vsx registers. */
225 static bool rs6000_passes_float
;
226 static bool rs6000_passes_long_double
;
227 /* Flag whether vector values have been passed/returned. */
228 static bool rs6000_passes_vector
;
229 /* Flag whether small (<= 8 byte) structures have been returned. */
230 static bool rs6000_returns_struct
;
233 /* Value is TRUE if register/mode pair is acceptable. */
234 static bool rs6000_hard_regno_mode_ok_p
235 [NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
237 /* Maximum number of registers needed for a given register class and mode. */
238 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
240 /* How many registers are needed for a given register and mode. */
241 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
243 /* Map register number to register class. */
244 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
246 static int dbg_cost_ctrl
;
248 /* Built in types. */
249 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
250 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
252 /* Flag to say the TOC is initialized */
253 int toc_initialized
, need_toc_init
;
254 char toc_label_name
[10];
256 /* Cached value of rs6000_variable_issue. This is cached in
257 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
258 static short cached_can_issue_more
;
260 static GTY(()) section
*read_only_data_section
;
261 static GTY(()) section
*private_data_section
;
262 static GTY(()) section
*tls_data_section
;
263 static GTY(()) section
*tls_private_data_section
;
264 static GTY(()) section
*read_only_private_data_section
;
265 static GTY(()) section
*sdata2_section
;
266 static GTY(()) section
*toc_section
;
268 struct builtin_description
270 const HOST_WIDE_INT mask
;
271 const enum insn_code icode
;
272 const char *const name
;
273 const enum rs6000_builtins code
;
276 /* Describe the vector unit used for modes. */
277 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
278 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
280 /* Register classes for various constraints that are based on the target
282 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
284 /* Describe the alignment of a vector. */
285 int rs6000_vector_align
[NUM_MACHINE_MODES
];
287 /* Map selected modes to types for builtins. */
288 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
290 /* What modes to automatically generate reciprocal divide estimate (fre) and
291 reciprocal sqrt (frsqrte) for. */
292 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
294 /* Masks to determine which reciprocal esitmate instructions to generate
296 enum rs6000_recip_mask
{
297 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
298 RECIP_DF_DIV
= 0x002,
299 RECIP_V4SF_DIV
= 0x004,
300 RECIP_V2DF_DIV
= 0x008,
302 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
303 RECIP_DF_RSQRT
= 0x020,
304 RECIP_V4SF_RSQRT
= 0x040,
305 RECIP_V2DF_RSQRT
= 0x080,
307 /* Various combination of flags for -mrecip=xxx. */
309 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
310 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
311 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
313 RECIP_HIGH_PRECISION
= RECIP_ALL
,
315 /* On low precision machines like the power5, don't enable double precision
316 reciprocal square root estimate, since it isn't accurate enough. */
317 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
320 /* -mrecip options. */
323 const char *string
; /* option name */
324 unsigned int mask
; /* mask bits to set */
325 } recip_options
[] = {
326 { "all", RECIP_ALL
},
327 { "none", RECIP_NONE
},
328 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
330 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
331 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
332 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
333 | RECIP_V2DF_RSQRT
) },
334 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
335 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
338 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
344 { "power9", PPC_PLATFORM_POWER9
},
345 { "power8", PPC_PLATFORM_POWER8
},
346 { "power7", PPC_PLATFORM_POWER7
},
347 { "power6x", PPC_PLATFORM_POWER6X
},
348 { "power6", PPC_PLATFORM_POWER6
},
349 { "power5+", PPC_PLATFORM_POWER5_PLUS
},
350 { "power5", PPC_PLATFORM_POWER5
},
351 { "ppc970", PPC_PLATFORM_PPC970
},
352 { "power4", PPC_PLATFORM_POWER4
},
353 { "ppca2", PPC_PLATFORM_PPCA2
},
354 { "ppc476", PPC_PLATFORM_PPC476
},
355 { "ppc464", PPC_PLATFORM_PPC464
},
356 { "ppc440", PPC_PLATFORM_PPC440
},
357 { "ppc405", PPC_PLATFORM_PPC405
},
358 { "ppc-cell-be", PPC_PLATFORM_CELL_BE
}
361 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
367 } cpu_supports_info
[] = {
368 /* AT_HWCAP masks. */
369 { "4xxmac", PPC_FEATURE_HAS_4xxMAC
, 0 },
370 { "altivec", PPC_FEATURE_HAS_ALTIVEC
, 0 },
371 { "arch_2_05", PPC_FEATURE_ARCH_2_05
, 0 },
372 { "arch_2_06", PPC_FEATURE_ARCH_2_06
, 0 },
373 { "archpmu", PPC_FEATURE_PERFMON_COMPAT
, 0 },
374 { "booke", PPC_FEATURE_BOOKE
, 0 },
375 { "cellbe", PPC_FEATURE_CELL_BE
, 0 },
376 { "dfp", PPC_FEATURE_HAS_DFP
, 0 },
377 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE
, 0 },
378 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE
, 0 },
379 { "fpu", PPC_FEATURE_HAS_FPU
, 0 },
380 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP
, 0 },
381 { "mmu", PPC_FEATURE_HAS_MMU
, 0 },
382 { "notb", PPC_FEATURE_NO_TB
, 0 },
383 { "pa6t", PPC_FEATURE_PA6T
, 0 },
384 { "power4", PPC_FEATURE_POWER4
, 0 },
385 { "power5", PPC_FEATURE_POWER5
, 0 },
386 { "power5+", PPC_FEATURE_POWER5_PLUS
, 0 },
387 { "power6x", PPC_FEATURE_POWER6_EXT
, 0 },
388 { "ppc32", PPC_FEATURE_32
, 0 },
389 { "ppc601", PPC_FEATURE_601_INSTR
, 0 },
390 { "ppc64", PPC_FEATURE_64
, 0 },
391 { "ppcle", PPC_FEATURE_PPC_LE
, 0 },
392 { "smt", PPC_FEATURE_SMT
, 0 },
393 { "spe", PPC_FEATURE_HAS_SPE
, 0 },
394 { "true_le", PPC_FEATURE_TRUE_LE
, 0 },
395 { "ucache", PPC_FEATURE_UNIFIED_CACHE
, 0 },
396 { "vsx", PPC_FEATURE_HAS_VSX
, 0 },
398 /* AT_HWCAP2 masks. */
399 { "arch_2_07", PPC_FEATURE2_ARCH_2_07
, 1 },
400 { "dscr", PPC_FEATURE2_HAS_DSCR
, 1 },
401 { "ebb", PPC_FEATURE2_HAS_EBB
, 1 },
402 { "htm", PPC_FEATURE2_HAS_HTM
, 1 },
403 { "htm-nosc", PPC_FEATURE2_HTM_NOSC
, 1 },
404 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND
, 1 },
405 { "isel", PPC_FEATURE2_HAS_ISEL
, 1 },
406 { "tar", PPC_FEATURE2_HAS_TAR
, 1 },
407 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO
, 1 },
408 { "arch_3_00", PPC_FEATURE2_ARCH_3_00
, 1 },
409 { "ieee128", PPC_FEATURE2_HAS_IEEE128
, 1 },
410 { "darn", PPC_FEATURE2_DARN
, 1 },
411 { "scv", PPC_FEATURE2_SCV
, 1 }
414 /* On PowerPC, we have a limited number of target clones that we care about
415 which means we can use an array to hold the options, rather than having more
416 elaborate data structures to identify each possible variation. Order the
417 clones from the default to the highest ISA. */
419 CLONE_DEFAULT
= 0, /* default clone. */
420 CLONE_ISA_2_05
, /* ISA 2.05 (power6). */
421 CLONE_ISA_2_06
, /* ISA 2.06 (power7). */
422 CLONE_ISA_2_07
, /* ISA 2.07 (power8). */
423 CLONE_ISA_3_00
, /* ISA 3.00 (power9). */
427 /* Map compiler ISA bits into HWCAP names. */
429 HOST_WIDE_INT isa_mask
; /* rs6000_isa mask */
430 const char *name
; /* name to use in __builtin_cpu_supports. */
433 static const struct clone_map rs6000_clone_map
[CLONE_MAX
] = {
434 { 0, "" }, /* Default options. */
435 { OPTION_MASK_CMPB
, "arch_2_05" }, /* ISA 2.05 (power6). */
436 { OPTION_MASK_POPCNTD
, "arch_2_06" }, /* ISA 2.06 (power7). */
437 { OPTION_MASK_P8_VECTOR
, "arch_2_07" }, /* ISA 2.07 (power8). */
438 { OPTION_MASK_P9_VECTOR
, "arch_3_00" }, /* ISA 3.00 (power9). */
442 /* Newer LIBCs explicitly export this symbol to declare that they provide
443 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
444 reference to this symbol whenever we expand a CPU builtin, so that
445 we never link against an old LIBC. */
446 const char *tcb_verification_symbol
= "__parse_hwcap_and_convert_at_platform";
448 /* True if we have expanded a CPU builtin. */
451 /* Pointer to function (in rs6000-c.c) that can define or undefine target
452 macros that have changed. Languages that don't support the preprocessor
453 don't link in rs6000-c.c, so we can't call it directly. */
454 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
456 /* Simplfy register classes into simpler classifications. We assume
457 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
458 check for standard register classes (gpr/floating/altivec/vsx) and
459 floating/vector classes (float/altivec/vsx). */
461 enum rs6000_reg_type
{
472 /* Map register class to register type. */
473 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
475 /* First/last register type for the 'normal' register types (i.e. general
476 purpose, floating point, altivec, and VSX registers). */
477 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
479 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
482 /* Register classes we care about in secondary reload or go if legitimate
483 address. We only need to worry about GPR, FPR, and Altivec registers here,
484 along an ANY field that is the OR of the 3 register classes. */
486 enum rs6000_reload_reg_type
{
487 RELOAD_REG_GPR
, /* General purpose registers. */
488 RELOAD_REG_FPR
, /* Traditional floating point regs. */
489 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
490 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
494 /* For setting up register classes, loop through the 3 register classes mapping
495 into real registers, and skip the ANY class, which is just an OR of the
497 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
498 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
500 /* Map reload register type to a register in the register class. */
501 struct reload_reg_map_type
{
502 const char *name
; /* Register class name. */
503 int reg
; /* Register in the register class. */
506 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
507 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
508 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
509 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
510 { "Any", -1 }, /* RELOAD_REG_ANY. */
513 /* Mask bits for each register class, indexed per mode. Historically the
514 compiler has been more restrictive which types can do PRE_MODIFY instead of
515 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
516 typedef unsigned char addr_mask_type
;
518 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
519 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
520 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
521 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
522 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
523 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
524 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
525 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
527 /* Register type masks based on the type, of valid addressing modes. */
528 struct rs6000_reg_addr
{
529 enum insn_code reload_load
; /* INSN to reload for loading. */
530 enum insn_code reload_store
; /* INSN to reload for storing. */
531 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
532 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
533 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
534 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
535 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
538 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
540 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
542 mode_supports_pre_incdec_p (machine_mode mode
)
544 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
548 /* Helper function to say whether a mode supports PRE_MODIFY. */
550 mode_supports_pre_modify_p (machine_mode mode
)
552 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
556 /* Return true if we have D-form addressing in altivec registers. */
558 mode_supports_vmx_dform (machine_mode mode
)
560 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_OFFSET
) != 0);
563 /* Return true if we have D-form addressing in VSX registers. This addressing
564 is more limited than normal d-form addressing in that the offset must be
565 aligned on a 16-byte boundary. */
567 mode_supports_dq_form (machine_mode mode
)
569 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_QUAD_OFFSET
)
573 /* Given that there exists at least one variable that is set (produced)
574 by OUT_INSN and read (consumed) by IN_INSN, return true iff
575 IN_INSN represents one or more memory store operations and none of
576 the variables set by OUT_INSN is used by IN_INSN as the address of a
577 store operation. If either IN_INSN or OUT_INSN does not represent
578 a "single" RTL SET expression (as loosely defined by the
579 implementation of the single_set function) or a PARALLEL with only
580 SETs, CLOBBERs, and USEs inside, this function returns false.
582 This rs6000-specific version of store_data_bypass_p checks for
583 certain conditions that result in assertion failures (and internal
584 compiler errors) in the generic store_data_bypass_p function and
585 returns false rather than calling store_data_bypass_p if one of the
586 problematic conditions is detected. */
589 rs6000_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
596 in_set
= single_set (in_insn
);
599 if (MEM_P (SET_DEST (in_set
)))
601 out_set
= single_set (out_insn
);
604 out_pat
= PATTERN (out_insn
);
605 if (GET_CODE (out_pat
) == PARALLEL
)
607 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
609 out_exp
= XVECEXP (out_pat
, 0, i
);
610 if ((GET_CODE (out_exp
) == CLOBBER
)
611 || (GET_CODE (out_exp
) == USE
))
613 else if (GET_CODE (out_exp
) != SET
)
622 in_pat
= PATTERN (in_insn
);
623 if (GET_CODE (in_pat
) != PARALLEL
)
626 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
628 in_exp
= XVECEXP (in_pat
, 0, i
);
629 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
631 else if (GET_CODE (in_exp
) != SET
)
634 if (MEM_P (SET_DEST (in_exp
)))
636 out_set
= single_set (out_insn
);
639 out_pat
= PATTERN (out_insn
);
640 if (GET_CODE (out_pat
) != PARALLEL
)
642 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
644 out_exp
= XVECEXP (out_pat
, 0, j
);
645 if ((GET_CODE (out_exp
) == CLOBBER
)
646 || (GET_CODE (out_exp
) == USE
))
648 else if (GET_CODE (out_exp
) != SET
)
655 return store_data_bypass_p (out_insn
, in_insn
);
659 /* Processor costs (relative to an add) */
661 const struct processor_costs
*rs6000_cost
;
663 /* Instruction size costs on 32bit processors. */
665 struct processor_costs size32_cost
= {
666 COSTS_N_INSNS (1), /* mulsi */
667 COSTS_N_INSNS (1), /* mulsi_const */
668 COSTS_N_INSNS (1), /* mulsi_const9 */
669 COSTS_N_INSNS (1), /* muldi */
670 COSTS_N_INSNS (1), /* divsi */
671 COSTS_N_INSNS (1), /* divdi */
672 COSTS_N_INSNS (1), /* fp */
673 COSTS_N_INSNS (1), /* dmul */
674 COSTS_N_INSNS (1), /* sdiv */
675 COSTS_N_INSNS (1), /* ddiv */
676 32, /* cache line size */
680 0, /* SF->DF convert */
683 /* Instruction size costs on 64bit processors. */
685 struct processor_costs size64_cost
= {
686 COSTS_N_INSNS (1), /* mulsi */
687 COSTS_N_INSNS (1), /* mulsi_const */
688 COSTS_N_INSNS (1), /* mulsi_const9 */
689 COSTS_N_INSNS (1), /* muldi */
690 COSTS_N_INSNS (1), /* divsi */
691 COSTS_N_INSNS (1), /* divdi */
692 COSTS_N_INSNS (1), /* fp */
693 COSTS_N_INSNS (1), /* dmul */
694 COSTS_N_INSNS (1), /* sdiv */
695 COSTS_N_INSNS (1), /* ddiv */
696 128, /* cache line size */
700 0, /* SF->DF convert */
703 /* Instruction costs on RS64A processors. */
705 struct processor_costs rs64a_cost
= {
706 COSTS_N_INSNS (20), /* mulsi */
707 COSTS_N_INSNS (12), /* mulsi_const */
708 COSTS_N_INSNS (8), /* mulsi_const9 */
709 COSTS_N_INSNS (34), /* muldi */
710 COSTS_N_INSNS (65), /* divsi */
711 COSTS_N_INSNS (67), /* divdi */
712 COSTS_N_INSNS (4), /* fp */
713 COSTS_N_INSNS (4), /* dmul */
714 COSTS_N_INSNS (31), /* sdiv */
715 COSTS_N_INSNS (31), /* ddiv */
716 128, /* cache line size */
720 0, /* SF->DF convert */
723 /* Instruction costs on MPCCORE processors. */
725 struct processor_costs mpccore_cost
= {
726 COSTS_N_INSNS (2), /* mulsi */
727 COSTS_N_INSNS (2), /* mulsi_const */
728 COSTS_N_INSNS (2), /* mulsi_const9 */
729 COSTS_N_INSNS (2), /* muldi */
730 COSTS_N_INSNS (6), /* divsi */
731 COSTS_N_INSNS (6), /* divdi */
732 COSTS_N_INSNS (4), /* fp */
733 COSTS_N_INSNS (5), /* dmul */
734 COSTS_N_INSNS (10), /* sdiv */
735 COSTS_N_INSNS (17), /* ddiv */
736 32, /* cache line size */
740 0, /* SF->DF convert */
743 /* Instruction costs on PPC403 processors. */
745 struct processor_costs ppc403_cost
= {
746 COSTS_N_INSNS (4), /* mulsi */
747 COSTS_N_INSNS (4), /* mulsi_const */
748 COSTS_N_INSNS (4), /* mulsi_const9 */
749 COSTS_N_INSNS (4), /* muldi */
750 COSTS_N_INSNS (33), /* divsi */
751 COSTS_N_INSNS (33), /* divdi */
752 COSTS_N_INSNS (11), /* fp */
753 COSTS_N_INSNS (11), /* dmul */
754 COSTS_N_INSNS (11), /* sdiv */
755 COSTS_N_INSNS (11), /* ddiv */
756 32, /* cache line size */
760 0, /* SF->DF convert */
763 /* Instruction costs on PPC405 processors. */
765 struct processor_costs ppc405_cost
= {
766 COSTS_N_INSNS (5), /* mulsi */
767 COSTS_N_INSNS (4), /* mulsi_const */
768 COSTS_N_INSNS (3), /* mulsi_const9 */
769 COSTS_N_INSNS (5), /* muldi */
770 COSTS_N_INSNS (35), /* divsi */
771 COSTS_N_INSNS (35), /* divdi */
772 COSTS_N_INSNS (11), /* fp */
773 COSTS_N_INSNS (11), /* dmul */
774 COSTS_N_INSNS (11), /* sdiv */
775 COSTS_N_INSNS (11), /* ddiv */
776 32, /* cache line size */
780 0, /* SF->DF convert */
783 /* Instruction costs on PPC440 processors. */
785 struct processor_costs ppc440_cost
= {
786 COSTS_N_INSNS (3), /* mulsi */
787 COSTS_N_INSNS (2), /* mulsi_const */
788 COSTS_N_INSNS (2), /* mulsi_const9 */
789 COSTS_N_INSNS (3), /* muldi */
790 COSTS_N_INSNS (34), /* divsi */
791 COSTS_N_INSNS (34), /* divdi */
792 COSTS_N_INSNS (5), /* fp */
793 COSTS_N_INSNS (5), /* dmul */
794 COSTS_N_INSNS (19), /* sdiv */
795 COSTS_N_INSNS (33), /* ddiv */
796 32, /* cache line size */
800 0, /* SF->DF convert */
803 /* Instruction costs on PPC476 processors. */
805 struct processor_costs ppc476_cost
= {
806 COSTS_N_INSNS (4), /* mulsi */
807 COSTS_N_INSNS (4), /* mulsi_const */
808 COSTS_N_INSNS (4), /* mulsi_const9 */
809 COSTS_N_INSNS (4), /* muldi */
810 COSTS_N_INSNS (11), /* divsi */
811 COSTS_N_INSNS (11), /* divdi */
812 COSTS_N_INSNS (6), /* fp */
813 COSTS_N_INSNS (6), /* dmul */
814 COSTS_N_INSNS (19), /* sdiv */
815 COSTS_N_INSNS (33), /* ddiv */
816 32, /* l1 cache line size */
820 0, /* SF->DF convert */
823 /* Instruction costs on PPC601 processors. */
825 struct processor_costs ppc601_cost
= {
826 COSTS_N_INSNS (5), /* mulsi */
827 COSTS_N_INSNS (5), /* mulsi_const */
828 COSTS_N_INSNS (5), /* mulsi_const9 */
829 COSTS_N_INSNS (5), /* muldi */
830 COSTS_N_INSNS (36), /* divsi */
831 COSTS_N_INSNS (36), /* divdi */
832 COSTS_N_INSNS (4), /* fp */
833 COSTS_N_INSNS (5), /* dmul */
834 COSTS_N_INSNS (17), /* sdiv */
835 COSTS_N_INSNS (31), /* ddiv */
836 32, /* cache line size */
840 0, /* SF->DF convert */
843 /* Instruction costs on PPC603 processors. */
845 struct processor_costs ppc603_cost
= {
846 COSTS_N_INSNS (5), /* mulsi */
847 COSTS_N_INSNS (3), /* mulsi_const */
848 COSTS_N_INSNS (2), /* mulsi_const9 */
849 COSTS_N_INSNS (5), /* muldi */
850 COSTS_N_INSNS (37), /* divsi */
851 COSTS_N_INSNS (37), /* divdi */
852 COSTS_N_INSNS (3), /* fp */
853 COSTS_N_INSNS (4), /* dmul */
854 COSTS_N_INSNS (18), /* sdiv */
855 COSTS_N_INSNS (33), /* ddiv */
856 32, /* cache line size */
860 0, /* SF->DF convert */
863 /* Instruction costs on PPC604 processors. */
865 struct processor_costs ppc604_cost
= {
866 COSTS_N_INSNS (4), /* mulsi */
867 COSTS_N_INSNS (4), /* mulsi_const */
868 COSTS_N_INSNS (4), /* mulsi_const9 */
869 COSTS_N_INSNS (4), /* muldi */
870 COSTS_N_INSNS (20), /* divsi */
871 COSTS_N_INSNS (20), /* divdi */
872 COSTS_N_INSNS (3), /* fp */
873 COSTS_N_INSNS (3), /* dmul */
874 COSTS_N_INSNS (18), /* sdiv */
875 COSTS_N_INSNS (32), /* ddiv */
876 32, /* cache line size */
880 0, /* SF->DF convert */
883 /* Instruction costs on PPC604e processors. */
885 struct processor_costs ppc604e_cost
= {
886 COSTS_N_INSNS (2), /* mulsi */
887 COSTS_N_INSNS (2), /* mulsi_const */
888 COSTS_N_INSNS (2), /* mulsi_const9 */
889 COSTS_N_INSNS (2), /* muldi */
890 COSTS_N_INSNS (20), /* divsi */
891 COSTS_N_INSNS (20), /* divdi */
892 COSTS_N_INSNS (3), /* fp */
893 COSTS_N_INSNS (3), /* dmul */
894 COSTS_N_INSNS (18), /* sdiv */
895 COSTS_N_INSNS (32), /* ddiv */
896 32, /* cache line size */
900 0, /* SF->DF convert */
903 /* Instruction costs on PPC620 processors. */
905 struct processor_costs ppc620_cost
= {
906 COSTS_N_INSNS (5), /* mulsi */
907 COSTS_N_INSNS (4), /* mulsi_const */
908 COSTS_N_INSNS (3), /* mulsi_const9 */
909 COSTS_N_INSNS (7), /* muldi */
910 COSTS_N_INSNS (21), /* divsi */
911 COSTS_N_INSNS (37), /* divdi */
912 COSTS_N_INSNS (3), /* fp */
913 COSTS_N_INSNS (3), /* dmul */
914 COSTS_N_INSNS (18), /* sdiv */
915 COSTS_N_INSNS (32), /* ddiv */
916 128, /* cache line size */
920 0, /* SF->DF convert */
923 /* Instruction costs on PPC630 processors. */
925 struct processor_costs ppc630_cost
= {
926 COSTS_N_INSNS (5), /* mulsi */
927 COSTS_N_INSNS (4), /* mulsi_const */
928 COSTS_N_INSNS (3), /* mulsi_const9 */
929 COSTS_N_INSNS (7), /* muldi */
930 COSTS_N_INSNS (21), /* divsi */
931 COSTS_N_INSNS (37), /* divdi */
932 COSTS_N_INSNS (3), /* fp */
933 COSTS_N_INSNS (3), /* dmul */
934 COSTS_N_INSNS (17), /* sdiv */
935 COSTS_N_INSNS (21), /* ddiv */
936 128, /* cache line size */
940 0, /* SF->DF convert */
943 /* Instruction costs on Cell processor. */
944 /* COSTS_N_INSNS (1) ~ one add. */
946 struct processor_costs ppccell_cost
= {
947 COSTS_N_INSNS (9/2)+2, /* mulsi */
948 COSTS_N_INSNS (6/2), /* mulsi_const */
949 COSTS_N_INSNS (6/2), /* mulsi_const9 */
950 COSTS_N_INSNS (15/2)+2, /* muldi */
951 COSTS_N_INSNS (38/2), /* divsi */
952 COSTS_N_INSNS (70/2), /* divdi */
953 COSTS_N_INSNS (10/2), /* fp */
954 COSTS_N_INSNS (10/2), /* dmul */
955 COSTS_N_INSNS (74/2), /* sdiv */
956 COSTS_N_INSNS (74/2), /* ddiv */
957 128, /* cache line size */
961 0, /* SF->DF convert */
964 /* Instruction costs on PPC750 and PPC7400 processors. */
966 struct processor_costs ppc750_cost
= {
967 COSTS_N_INSNS (5), /* mulsi */
968 COSTS_N_INSNS (3), /* mulsi_const */
969 COSTS_N_INSNS (2), /* mulsi_const9 */
970 COSTS_N_INSNS (5), /* muldi */
971 COSTS_N_INSNS (17), /* divsi */
972 COSTS_N_INSNS (17), /* divdi */
973 COSTS_N_INSNS (3), /* fp */
974 COSTS_N_INSNS (3), /* dmul */
975 COSTS_N_INSNS (17), /* sdiv */
976 COSTS_N_INSNS (31), /* ddiv */
977 32, /* cache line size */
981 0, /* SF->DF convert */
984 /* Instruction costs on PPC7450 processors. */
986 struct processor_costs ppc7450_cost
= {
987 COSTS_N_INSNS (4), /* mulsi */
988 COSTS_N_INSNS (3), /* mulsi_const */
989 COSTS_N_INSNS (3), /* mulsi_const9 */
990 COSTS_N_INSNS (4), /* muldi */
991 COSTS_N_INSNS (23), /* divsi */
992 COSTS_N_INSNS (23), /* divdi */
993 COSTS_N_INSNS (5), /* fp */
994 COSTS_N_INSNS (5), /* dmul */
995 COSTS_N_INSNS (21), /* sdiv */
996 COSTS_N_INSNS (35), /* ddiv */
997 32, /* cache line size */
1001 0, /* SF->DF convert */
1004 /* Instruction costs on PPC8540 processors. */
1006 struct processor_costs ppc8540_cost
= {
1007 COSTS_N_INSNS (4), /* mulsi */
1008 COSTS_N_INSNS (4), /* mulsi_const */
1009 COSTS_N_INSNS (4), /* mulsi_const9 */
1010 COSTS_N_INSNS (4), /* muldi */
1011 COSTS_N_INSNS (19), /* divsi */
1012 COSTS_N_INSNS (19), /* divdi */
1013 COSTS_N_INSNS (4), /* fp */
1014 COSTS_N_INSNS (4), /* dmul */
1015 COSTS_N_INSNS (29), /* sdiv */
1016 COSTS_N_INSNS (29), /* ddiv */
1017 32, /* cache line size */
1020 1, /* prefetch streams /*/
1021 0, /* SF->DF convert */
1024 /* Instruction costs on E300C2 and E300C3 cores. */
1026 struct processor_costs ppce300c2c3_cost
= {
1027 COSTS_N_INSNS (4), /* mulsi */
1028 COSTS_N_INSNS (4), /* mulsi_const */
1029 COSTS_N_INSNS (4), /* mulsi_const9 */
1030 COSTS_N_INSNS (4), /* muldi */
1031 COSTS_N_INSNS (19), /* divsi */
1032 COSTS_N_INSNS (19), /* divdi */
1033 COSTS_N_INSNS (3), /* fp */
1034 COSTS_N_INSNS (4), /* dmul */
1035 COSTS_N_INSNS (18), /* sdiv */
1036 COSTS_N_INSNS (33), /* ddiv */
1040 1, /* prefetch streams /*/
1041 0, /* SF->DF convert */
1044 /* Instruction costs on PPCE500MC processors. */
1046 struct processor_costs ppce500mc_cost
= {
1047 COSTS_N_INSNS (4), /* mulsi */
1048 COSTS_N_INSNS (4), /* mulsi_const */
1049 COSTS_N_INSNS (4), /* mulsi_const9 */
1050 COSTS_N_INSNS (4), /* muldi */
1051 COSTS_N_INSNS (14), /* divsi */
1052 COSTS_N_INSNS (14), /* divdi */
1053 COSTS_N_INSNS (8), /* fp */
1054 COSTS_N_INSNS (10), /* dmul */
1055 COSTS_N_INSNS (36), /* sdiv */
1056 COSTS_N_INSNS (66), /* ddiv */
1057 64, /* cache line size */
1060 1, /* prefetch streams /*/
1061 0, /* SF->DF convert */
1064 /* Instruction costs on PPCE500MC64 processors. */
1066 struct processor_costs ppce500mc64_cost
= {
1067 COSTS_N_INSNS (4), /* mulsi */
1068 COSTS_N_INSNS (4), /* mulsi_const */
1069 COSTS_N_INSNS (4), /* mulsi_const9 */
1070 COSTS_N_INSNS (4), /* muldi */
1071 COSTS_N_INSNS (14), /* divsi */
1072 COSTS_N_INSNS (14), /* divdi */
1073 COSTS_N_INSNS (4), /* fp */
1074 COSTS_N_INSNS (10), /* dmul */
1075 COSTS_N_INSNS (36), /* sdiv */
1076 COSTS_N_INSNS (66), /* ddiv */
1077 64, /* cache line size */
1080 1, /* prefetch streams /*/
1081 0, /* SF->DF convert */
1084 /* Instruction costs on PPCE5500 processors. */
1086 struct processor_costs ppce5500_cost
= {
1087 COSTS_N_INSNS (5), /* mulsi */
1088 COSTS_N_INSNS (5), /* mulsi_const */
1089 COSTS_N_INSNS (4), /* mulsi_const9 */
1090 COSTS_N_INSNS (5), /* muldi */
1091 COSTS_N_INSNS (14), /* divsi */
1092 COSTS_N_INSNS (14), /* divdi */
1093 COSTS_N_INSNS (7), /* fp */
1094 COSTS_N_INSNS (10), /* dmul */
1095 COSTS_N_INSNS (36), /* sdiv */
1096 COSTS_N_INSNS (66), /* ddiv */
1097 64, /* cache line size */
1100 1, /* prefetch streams /*/
1101 0, /* SF->DF convert */
1104 /* Instruction costs on PPCE6500 processors. */
1106 struct processor_costs ppce6500_cost
= {
1107 COSTS_N_INSNS (5), /* mulsi */
1108 COSTS_N_INSNS (5), /* mulsi_const */
1109 COSTS_N_INSNS (4), /* mulsi_const9 */
1110 COSTS_N_INSNS (5), /* muldi */
1111 COSTS_N_INSNS (14), /* divsi */
1112 COSTS_N_INSNS (14), /* divdi */
1113 COSTS_N_INSNS (7), /* fp */
1114 COSTS_N_INSNS (10), /* dmul */
1115 COSTS_N_INSNS (36), /* sdiv */
1116 COSTS_N_INSNS (66), /* ddiv */
1117 64, /* cache line size */
1120 1, /* prefetch streams /*/
1121 0, /* SF->DF convert */
1124 /* Instruction costs on AppliedMicro Titan processors. */
1126 struct processor_costs titan_cost
= {
1127 COSTS_N_INSNS (5), /* mulsi */
1128 COSTS_N_INSNS (5), /* mulsi_const */
1129 COSTS_N_INSNS (5), /* mulsi_const9 */
1130 COSTS_N_INSNS (5), /* muldi */
1131 COSTS_N_INSNS (18), /* divsi */
1132 COSTS_N_INSNS (18), /* divdi */
1133 COSTS_N_INSNS (10), /* fp */
1134 COSTS_N_INSNS (10), /* dmul */
1135 COSTS_N_INSNS (46), /* sdiv */
1136 COSTS_N_INSNS (72), /* ddiv */
1137 32, /* cache line size */
1140 1, /* prefetch streams /*/
1141 0, /* SF->DF convert */
1144 /* Instruction costs on POWER4 and POWER5 processors. */
1146 struct processor_costs power4_cost
= {
1147 COSTS_N_INSNS (3), /* mulsi */
1148 COSTS_N_INSNS (2), /* mulsi_const */
1149 COSTS_N_INSNS (2), /* mulsi_const9 */
1150 COSTS_N_INSNS (4), /* muldi */
1151 COSTS_N_INSNS (18), /* divsi */
1152 COSTS_N_INSNS (34), /* divdi */
1153 COSTS_N_INSNS (3), /* fp */
1154 COSTS_N_INSNS (3), /* dmul */
1155 COSTS_N_INSNS (17), /* sdiv */
1156 COSTS_N_INSNS (17), /* ddiv */
1157 128, /* cache line size */
1159 1024, /* l2 cache */
1160 8, /* prefetch streams /*/
1161 0, /* SF->DF convert */
1164 /* Instruction costs on POWER6 processors. */
1166 struct processor_costs power6_cost
= {
1167 COSTS_N_INSNS (8), /* mulsi */
1168 COSTS_N_INSNS (8), /* mulsi_const */
1169 COSTS_N_INSNS (8), /* mulsi_const9 */
1170 COSTS_N_INSNS (8), /* muldi */
1171 COSTS_N_INSNS (22), /* divsi */
1172 COSTS_N_INSNS (28), /* divdi */
1173 COSTS_N_INSNS (3), /* fp */
1174 COSTS_N_INSNS (3), /* dmul */
1175 COSTS_N_INSNS (13), /* sdiv */
1176 COSTS_N_INSNS (16), /* ddiv */
1177 128, /* cache line size */
1179 2048, /* l2 cache */
1180 16, /* prefetch streams */
1181 0, /* SF->DF convert */
1184 /* Instruction costs on POWER7 processors. */
1186 struct processor_costs power7_cost
= {
1187 COSTS_N_INSNS (2), /* mulsi */
1188 COSTS_N_INSNS (2), /* mulsi_const */
1189 COSTS_N_INSNS (2), /* mulsi_const9 */
1190 COSTS_N_INSNS (2), /* muldi */
1191 COSTS_N_INSNS (18), /* divsi */
1192 COSTS_N_INSNS (34), /* divdi */
1193 COSTS_N_INSNS (3), /* fp */
1194 COSTS_N_INSNS (3), /* dmul */
1195 COSTS_N_INSNS (13), /* sdiv */
1196 COSTS_N_INSNS (16), /* ddiv */
1197 128, /* cache line size */
1200 12, /* prefetch streams */
1201 COSTS_N_INSNS (3), /* SF->DF convert */
1204 /* Instruction costs on POWER8 processors. */
1206 struct processor_costs power8_cost
= {
1207 COSTS_N_INSNS (3), /* mulsi */
1208 COSTS_N_INSNS (3), /* mulsi_const */
1209 COSTS_N_INSNS (3), /* mulsi_const9 */
1210 COSTS_N_INSNS (3), /* muldi */
1211 COSTS_N_INSNS (19), /* divsi */
1212 COSTS_N_INSNS (35), /* divdi */
1213 COSTS_N_INSNS (3), /* fp */
1214 COSTS_N_INSNS (3), /* dmul */
1215 COSTS_N_INSNS (14), /* sdiv */
1216 COSTS_N_INSNS (17), /* ddiv */
1217 128, /* cache line size */
1220 12, /* prefetch streams */
1221 COSTS_N_INSNS (3), /* SF->DF convert */
1224 /* Instruction costs on POWER9 processors. */
1226 struct processor_costs power9_cost
= {
1227 COSTS_N_INSNS (3), /* mulsi */
1228 COSTS_N_INSNS (3), /* mulsi_const */
1229 COSTS_N_INSNS (3), /* mulsi_const9 */
1230 COSTS_N_INSNS (3), /* muldi */
1231 COSTS_N_INSNS (8), /* divsi */
1232 COSTS_N_INSNS (12), /* divdi */
1233 COSTS_N_INSNS (3), /* fp */
1234 COSTS_N_INSNS (3), /* dmul */
1235 COSTS_N_INSNS (13), /* sdiv */
1236 COSTS_N_INSNS (18), /* ddiv */
1237 128, /* cache line size */
1240 8, /* prefetch streams */
1241 COSTS_N_INSNS (3), /* SF->DF convert */
1244 /* Instruction costs on POWER A2 processors. */
1246 struct processor_costs ppca2_cost
= {
1247 COSTS_N_INSNS (16), /* mulsi */
1248 COSTS_N_INSNS (16), /* mulsi_const */
1249 COSTS_N_INSNS (16), /* mulsi_const9 */
1250 COSTS_N_INSNS (16), /* muldi */
1251 COSTS_N_INSNS (22), /* divsi */
1252 COSTS_N_INSNS (28), /* divdi */
1253 COSTS_N_INSNS (3), /* fp */
1254 COSTS_N_INSNS (3), /* dmul */
1255 COSTS_N_INSNS (59), /* sdiv */
1256 COSTS_N_INSNS (72), /* ddiv */
1259 2048, /* l2 cache */
1260 16, /* prefetch streams */
1261 0, /* SF->DF convert */
1265 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1266 #undef RS6000_BUILTIN_0
1267 #undef RS6000_BUILTIN_1
1268 #undef RS6000_BUILTIN_2
1269 #undef RS6000_BUILTIN_3
1270 #undef RS6000_BUILTIN_A
1271 #undef RS6000_BUILTIN_D
1272 #undef RS6000_BUILTIN_H
1273 #undef RS6000_BUILTIN_P
1274 #undef RS6000_BUILTIN_X
1276 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1277 { NAME, ICODE, MASK, ATTR },
1279 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1280 { NAME, ICODE, MASK, ATTR },
1282 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1283 { NAME, ICODE, MASK, ATTR },
1285 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1286 { NAME, ICODE, MASK, ATTR },
1288 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1289 { NAME, ICODE, MASK, ATTR },
1291 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1292 { NAME, ICODE, MASK, ATTR },
1294 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1295 { NAME, ICODE, MASK, ATTR },
1297 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1298 { NAME, ICODE, MASK, ATTR },
1300 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1301 { NAME, ICODE, MASK, ATTR },
1303 struct rs6000_builtin_info_type
{
1305 const enum insn_code icode
;
1306 const HOST_WIDE_INT mask
;
1307 const unsigned attr
;
1310 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1312 #include "rs6000-builtin.def"
1315 #undef RS6000_BUILTIN_0
1316 #undef RS6000_BUILTIN_1
1317 #undef RS6000_BUILTIN_2
1318 #undef RS6000_BUILTIN_3
1319 #undef RS6000_BUILTIN_A
1320 #undef RS6000_BUILTIN_D
1321 #undef RS6000_BUILTIN_H
1322 #undef RS6000_BUILTIN_P
1323 #undef RS6000_BUILTIN_X
1325 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1326 static tree (*rs6000_veclib_handler
) (combined_fn
, tree
, tree
);
1329 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1330 static struct machine_function
* rs6000_init_machine_status (void);
1331 static int rs6000_ra_ever_killed (void);
1332 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1333 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1334 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1335 static tree
rs6000_builtin_vectorized_libmass (combined_fn
, tree
, tree
);
1336 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1337 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1338 static bool rs6000_debug_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
1339 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1341 static int rs6000_debug_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
1343 static bool is_microcoded_insn (rtx_insn
*);
1344 static bool is_nonpipeline_insn (rtx_insn
*);
1345 static bool is_cracked_insn (rtx_insn
*);
1346 static bool is_load_insn (rtx
, rtx
*);
1347 static bool is_store_insn (rtx
, rtx
*);
1348 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1349 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1350 static bool insn_must_be_first_in_group (rtx_insn
*);
1351 static bool insn_must_be_last_in_group (rtx_insn
*);
1352 static void altivec_init_builtins (void);
1353 static tree
builtin_function_type (machine_mode
, machine_mode
,
1354 machine_mode
, machine_mode
,
1355 enum rs6000_builtins
, const char *name
);
1356 static void rs6000_common_init_builtins (void);
1357 static void htm_init_builtins (void);
1358 static rs6000_stack_t
*rs6000_stack_info (void);
1359 static void is_altivec_return_reg (rtx
, void *);
1360 int easy_vector_constant (rtx
, machine_mode
);
1361 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1362 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1363 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1366 static void macho_branch_islands (void);
1368 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1370 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1372 static bool rs6000_mode_dependent_address (const_rtx
);
1373 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1374 static bool rs6000_offsettable_memref_p (rtx
, machine_mode
, bool);
1375 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1377 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1380 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1381 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1383 static bool rs6000_debug_secondary_memory_needed (machine_mode
,
1386 static bool rs6000_debug_can_change_mode_class (machine_mode
,
1389 static bool rs6000_save_toc_in_prologue_p (void);
1390 static rtx
rs6000_internal_arg_pointer (void);
1392 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1394 = rs6000_legitimize_reload_address
;
1396 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1397 = rs6000_mode_dependent_address
;
1399 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1401 = rs6000_secondary_reload_class
;
1403 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1404 = rs6000_preferred_reload_class
;
1406 const int INSN_NOT_AVAILABLE
= -1;
1408 static void rs6000_print_isa_options (FILE *, int, const char *,
1410 static void rs6000_print_builtin_options (FILE *, int, const char *,
1412 static HOST_WIDE_INT
rs6000_disable_incompatible_switches (void);
1414 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1415 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1416 enum rs6000_reg_type
,
1418 secondary_reload_info
*,
1420 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1421 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused
));
1422 static tree
rs6000_fold_builtin (tree
, int, tree
*, bool);
1424 /* Hash table stuff for keeping track of TOC entries. */
1426 struct GTY((for_user
)) toc_hash_struct
1428 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1429 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1431 machine_mode key_mode
;
1435 struct toc_hasher
: ggc_ptr_hash
<toc_hash_struct
>
1437 static hashval_t
hash (toc_hash_struct
*);
1438 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1441 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1443 /* Hash table to keep track of the argument types for builtin functions. */
1445 struct GTY((for_user
)) builtin_hash_struct
1448 machine_mode mode
[4]; /* return value + 3 arguments. */
1449 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1452 struct builtin_hasher
: ggc_ptr_hash
<builtin_hash_struct
>
1454 static hashval_t
hash (builtin_hash_struct
*);
1455 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1458 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1461 /* Default register names. */
1462 char rs6000_reg_names
[][8] =
1464 "0", "1", "2", "3", "4", "5", "6", "7",
1465 "8", "9", "10", "11", "12", "13", "14", "15",
1466 "16", "17", "18", "19", "20", "21", "22", "23",
1467 "24", "25", "26", "27", "28", "29", "30", "31",
1468 "0", "1", "2", "3", "4", "5", "6", "7",
1469 "8", "9", "10", "11", "12", "13", "14", "15",
1470 "16", "17", "18", "19", "20", "21", "22", "23",
1471 "24", "25", "26", "27", "28", "29", "30", "31",
1472 "mq", "lr", "ctr","ap",
1473 "0", "1", "2", "3", "4", "5", "6", "7",
1475 /* AltiVec registers. */
1476 "0", "1", "2", "3", "4", "5", "6", "7",
1477 "8", "9", "10", "11", "12", "13", "14", "15",
1478 "16", "17", "18", "19", "20", "21", "22", "23",
1479 "24", "25", "26", "27", "28", "29", "30", "31",
1481 /* Soft frame pointer. */
1483 /* HTM SPR registers. */
1484 "tfhar", "tfiar", "texasr"
1487 #ifdef TARGET_REGNAMES
1488 static const char alt_reg_names
[][8] =
1490 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1491 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1492 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1493 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1494 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1495 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1496 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1497 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1498 "mq", "lr", "ctr", "ap",
1499 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1501 /* AltiVec registers. */
1502 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1503 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1504 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1505 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1507 /* Soft frame pointer. */
1509 /* HTM SPR registers. */
1510 "tfhar", "tfiar", "texasr"
1514 /* Table of valid machine attributes. */
1516 static const struct attribute_spec rs6000_attribute_table
[] =
1518 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1519 affects_type_identity, handler, exclude } */
1520 { "altivec", 1, 1, false, true, false, false,
1521 rs6000_handle_altivec_attribute
, NULL
},
1522 { "longcall", 0, 0, false, true, true, false,
1523 rs6000_handle_longcall_attribute
, NULL
},
1524 { "shortcall", 0, 0, false, true, true, false,
1525 rs6000_handle_longcall_attribute
, NULL
},
1526 { "ms_struct", 0, 0, false, false, false, false,
1527 rs6000_handle_struct_attribute
, NULL
},
1528 { "gcc_struct", 0, 0, false, false, false, false,
1529 rs6000_handle_struct_attribute
, NULL
},
1530 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1531 SUBTARGET_ATTRIBUTE_TABLE
,
1533 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
1536 #ifndef TARGET_PROFILE_KERNEL
1537 #define TARGET_PROFILE_KERNEL 0
1540 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1541 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1543 /* Initialize the GCC target structure. */
1544 #undef TARGET_ATTRIBUTE_TABLE
1545 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1546 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1547 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1548 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1549 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1551 #undef TARGET_ASM_ALIGNED_DI_OP
1552 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1554 /* Default unaligned ops are only provided for ELF. Find the ops needed
1555 for non-ELF systems. */
1556 #ifndef OBJECT_FORMAT_ELF
1558 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1560 #undef TARGET_ASM_UNALIGNED_HI_OP
1561 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1562 #undef TARGET_ASM_UNALIGNED_SI_OP
1563 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1564 #undef TARGET_ASM_UNALIGNED_DI_OP
1565 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1568 #undef TARGET_ASM_UNALIGNED_HI_OP
1569 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1570 #undef TARGET_ASM_UNALIGNED_SI_OP
1571 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1572 #undef TARGET_ASM_UNALIGNED_DI_OP
1573 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1574 #undef TARGET_ASM_ALIGNED_DI_OP
1575 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1579 /* This hook deals with fixups for relocatable code and DI-mode objects
1581 #undef TARGET_ASM_INTEGER
1582 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1584 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1585 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1586 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1589 #undef TARGET_SET_UP_BY_PROLOGUE
1590 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1592 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1593 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1594 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1595 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1596 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1597 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1598 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1599 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1600 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1601 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1602 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1603 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1605 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1606 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1608 #undef TARGET_INTERNAL_ARG_POINTER
1609 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1611 #undef TARGET_HAVE_TLS
1612 #define TARGET_HAVE_TLS HAVE_AS_TLS
1614 #undef TARGET_CANNOT_FORCE_CONST_MEM
1615 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1617 #undef TARGET_DELEGITIMIZE_ADDRESS
1618 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1620 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1621 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1623 #undef TARGET_LEGITIMATE_COMBINED_INSN
1624 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1626 #undef TARGET_ASM_FUNCTION_PROLOGUE
1627 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1628 #undef TARGET_ASM_FUNCTION_EPILOGUE
1629 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1631 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1632 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1634 #undef TARGET_LEGITIMIZE_ADDRESS
1635 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1637 #undef TARGET_SCHED_VARIABLE_ISSUE
1638 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1640 #undef TARGET_SCHED_ISSUE_RATE
1641 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1642 #undef TARGET_SCHED_ADJUST_COST
1643 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1644 #undef TARGET_SCHED_ADJUST_PRIORITY
1645 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1646 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1647 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1648 #undef TARGET_SCHED_INIT
1649 #define TARGET_SCHED_INIT rs6000_sched_init
1650 #undef TARGET_SCHED_FINISH
1651 #define TARGET_SCHED_FINISH rs6000_sched_finish
1652 #undef TARGET_SCHED_REORDER
1653 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1654 #undef TARGET_SCHED_REORDER2
1655 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1657 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1658 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1660 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1661 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1663 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1664 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1665 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1666 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1667 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1668 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1669 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1670 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1672 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1673 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1675 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1676 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1677 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1678 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1679 rs6000_builtin_support_vector_misalignment
1680 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1681 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1682 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1683 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1684 rs6000_builtin_vectorization_cost
1685 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1686 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1687 rs6000_preferred_simd_mode
1688 #undef TARGET_VECTORIZE_INIT_COST
1689 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1690 #undef TARGET_VECTORIZE_ADD_STMT_COST
1691 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1692 #undef TARGET_VECTORIZE_FINISH_COST
1693 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1694 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1695 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1697 #undef TARGET_INIT_BUILTINS
1698 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1699 #undef TARGET_BUILTIN_DECL
1700 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1702 #undef TARGET_FOLD_BUILTIN
1703 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1704 #undef TARGET_GIMPLE_FOLD_BUILTIN
1705 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1707 #undef TARGET_EXPAND_BUILTIN
1708 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1710 #undef TARGET_MANGLE_TYPE
1711 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1713 #undef TARGET_INIT_LIBFUNCS
1714 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1717 #undef TARGET_BINDS_LOCAL_P
1718 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1721 #undef TARGET_MS_BITFIELD_LAYOUT_P
1722 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1724 #undef TARGET_ASM_OUTPUT_MI_THUNK
1725 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1727 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1728 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1730 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1731 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1733 #undef TARGET_REGISTER_MOVE_COST
1734 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1735 #undef TARGET_MEMORY_MOVE_COST
1736 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1737 #undef TARGET_CANNOT_COPY_INSN_P
1738 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1739 #undef TARGET_RTX_COSTS
1740 #define TARGET_RTX_COSTS rs6000_rtx_costs
1741 #undef TARGET_ADDRESS_COST
1742 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1743 #undef TARGET_INSN_COST
1744 #define TARGET_INSN_COST rs6000_insn_cost
1746 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1747 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1749 #undef TARGET_PROMOTE_FUNCTION_MODE
1750 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1752 #undef TARGET_RETURN_IN_MEMORY
1753 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1755 #undef TARGET_RETURN_IN_MSB
1756 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1758 #undef TARGET_SETUP_INCOMING_VARARGS
1759 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1761 /* Always strict argument naming on rs6000. */
1762 #undef TARGET_STRICT_ARGUMENT_NAMING
1763 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1765 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1766 #undef TARGET_SPLIT_COMPLEX_ARG
1767 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1768 #undef TARGET_MUST_PASS_IN_STACK
1769 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1770 #undef TARGET_PASS_BY_REFERENCE
1771 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1772 #undef TARGET_ARG_PARTIAL_BYTES
1773 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1774 #undef TARGET_FUNCTION_ARG_ADVANCE
1775 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1776 #undef TARGET_FUNCTION_ARG
1777 #define TARGET_FUNCTION_ARG rs6000_function_arg
1778 #undef TARGET_FUNCTION_ARG_PADDING
1779 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1780 #undef TARGET_FUNCTION_ARG_BOUNDARY
1781 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1783 #undef TARGET_BUILD_BUILTIN_VA_LIST
1784 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1786 #undef TARGET_EXPAND_BUILTIN_VA_START
1787 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1789 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1790 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1792 #undef TARGET_EH_RETURN_FILTER_MODE
1793 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1795 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1796 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1798 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1799 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1801 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1802 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1804 #undef TARGET_FLOATN_MODE
1805 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1807 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1808 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1810 #undef TARGET_MD_ASM_ADJUST
1811 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1813 #undef TARGET_OPTION_OVERRIDE
1814 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1816 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1817 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1818 rs6000_builtin_vectorized_function
1820 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1821 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1822 rs6000_builtin_md_vectorized_function
1824 #undef TARGET_STACK_PROTECT_GUARD
1825 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1828 #undef TARGET_STACK_PROTECT_FAIL
1829 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1833 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1834 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1837 /* Use a 32-bit anchor range. This leads to sequences like:
1839 addis tmp,anchor,high
1842 where tmp itself acts as an anchor, and can be shared between
1843 accesses to the same 64k page. */
1844 #undef TARGET_MIN_ANCHOR_OFFSET
1845 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1846 #undef TARGET_MAX_ANCHOR_OFFSET
1847 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1848 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1849 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1850 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1851 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1853 #undef TARGET_BUILTIN_RECIPROCAL
1854 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1856 #undef TARGET_SECONDARY_RELOAD
1857 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED
1859 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1860 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1861 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1863 #undef TARGET_LEGITIMATE_ADDRESS_P
1864 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1866 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1867 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1869 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1870 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1872 #undef TARGET_CAN_ELIMINATE
1873 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1875 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1876 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1878 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1879 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1881 #undef TARGET_TRAMPOLINE_INIT
1882 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1884 #undef TARGET_FUNCTION_VALUE
1885 #define TARGET_FUNCTION_VALUE rs6000_function_value
1887 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1888 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1890 #undef TARGET_OPTION_SAVE
1891 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1893 #undef TARGET_OPTION_RESTORE
1894 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1896 #undef TARGET_OPTION_PRINT
1897 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1899 #undef TARGET_CAN_INLINE_P
1900 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1902 #undef TARGET_SET_CURRENT_FUNCTION
1903 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1905 #undef TARGET_LEGITIMATE_CONSTANT_P
1906 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1908 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1909 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1911 #undef TARGET_CAN_USE_DOLOOP_P
1912 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1914 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1915 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1917 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1918 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1919 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1920 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1921 #undef TARGET_UNWIND_WORD_MODE
1922 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1924 #undef TARGET_OFFLOAD_OPTIONS
1925 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1927 #undef TARGET_C_MODE_FOR_SUFFIX
1928 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1930 #undef TARGET_INVALID_BINARY_OP
1931 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1933 #undef TARGET_OPTAB_SUPPORTED_P
1934 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1936 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1937 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1939 #undef TARGET_COMPARE_VERSION_PRIORITY
1940 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1942 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1943 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1944 rs6000_generate_version_dispatcher_body
1946 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1947 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1948 rs6000_get_function_versions_dispatcher
1950 #undef TARGET_OPTION_FUNCTION_VERSIONS
1951 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1953 #undef TARGET_HARD_REGNO_NREGS
1954 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1955 #undef TARGET_HARD_REGNO_MODE_OK
1956 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1958 #undef TARGET_MODES_TIEABLE_P
1959 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1961 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1962 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1963 rs6000_hard_regno_call_part_clobbered
1965 #undef TARGET_SLOW_UNALIGNED_ACCESS
1966 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1968 #undef TARGET_CAN_CHANGE_MODE_CLASS
1969 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1971 #undef TARGET_CONSTANT_ALIGNMENT
1972 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1974 #undef TARGET_STARTING_FRAME_OFFSET
1975 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1977 #if TARGET_ELF && RS6000_WEAK
1978 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1979 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1982 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1983 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1985 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1986 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1989 /* Processor table. */
1992 const char *const name
; /* Canonical processor name. */
1993 const enum processor_type processor
; /* Processor type enum value. */
1994 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1997 static struct rs6000_ptt
const processor_target_table
[] =
1999 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
2000 #include "rs6000-cpus.def"
2004 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2008 rs6000_cpu_name_lookup (const char *name
)
2014 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2015 if (! strcmp (name
, processor_target_table
[i
].name
))
2023 /* Return number of consecutive hard regs needed starting at reg REGNO
2024 to hold something of mode MODE.
2025 This is ordinarily the length in words of a value of mode MODE
2026 but can be less for certain modes in special long registers.
2028 POWER and PowerPC GPRs hold 32 bits worth;
2029 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2032 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
2034 unsigned HOST_WIDE_INT reg_size
;
2036 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2037 128-bit floating point that can go in vector registers, which has VSX
2038 memory addressing. */
2039 if (FP_REGNO_P (regno
))
2040 reg_size
= (VECTOR_MEM_VSX_P (mode
) || FLOAT128_VECTOR_P (mode
)
2041 ? UNITS_PER_VSX_WORD
2042 : UNITS_PER_FP_WORD
);
2044 else if (ALTIVEC_REGNO_P (regno
))
2045 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2048 reg_size
= UNITS_PER_WORD
;
2050 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
2053 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2056 rs6000_hard_regno_mode_ok_uncached (int regno
, machine_mode mode
)
2058 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
2060 if (COMPLEX_MODE_P (mode
))
2061 mode
= GET_MODE_INNER (mode
);
2063 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2064 register combinations, and use PTImode where we need to deal with quad
2065 word memory operations. Don't allow quad words in the argument or frame
2066 pointer registers, just registers 0..31. */
2067 if (mode
== PTImode
)
2068 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2069 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2070 && ((regno
& 1) == 0));
2072 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2073 implementations. Don't allow an item to be split between a FP register
2074 and an Altivec register. Allow TImode in all VSX registers if the user
2076 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
2077 && (VECTOR_MEM_VSX_P (mode
)
2078 || FLOAT128_VECTOR_P (mode
)
2079 || reg_addr
[mode
].scalar_in_vmx_p
2081 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
2083 if (FP_REGNO_P (regno
))
2084 return FP_REGNO_P (last_regno
);
2086 if (ALTIVEC_REGNO_P (regno
))
2088 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
2091 return ALTIVEC_REGNO_P (last_regno
);
2095 /* The GPRs can hold any mode, but values bigger than one register
2096 cannot go past R31. */
2097 if (INT_REGNO_P (regno
))
2098 return INT_REGNO_P (last_regno
);
2100 /* The float registers (except for VSX vector modes) can only hold floating
2101 modes and DImode. */
2102 if (FP_REGNO_P (regno
))
2104 if (FLOAT128_VECTOR_P (mode
))
2107 if (SCALAR_FLOAT_MODE_P (mode
)
2108 && (mode
!= TDmode
|| (regno
% 2) == 0)
2109 && FP_REGNO_P (last_regno
))
2112 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2114 if(GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
2117 if (TARGET_P8_VECTOR
&& (mode
== SImode
))
2120 if (TARGET_P9_VECTOR
&& (mode
== QImode
|| mode
== HImode
))
2127 /* The CR register can only hold CC modes. */
2128 if (CR_REGNO_P (regno
))
2129 return GET_MODE_CLASS (mode
) == MODE_CC
;
2131 if (CA_REGNO_P (regno
))
2132 return mode
== Pmode
|| mode
== SImode
;
2134 /* AltiVec only in AldyVec registers. */
2135 if (ALTIVEC_REGNO_P (regno
))
2136 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
2137 || mode
== V1TImode
);
2139 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2140 and it must be able to fit within the register set. */
2142 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
2145 /* Implement TARGET_HARD_REGNO_NREGS. */
2148 rs6000_hard_regno_nregs_hook (unsigned int regno
, machine_mode mode
)
2150 return rs6000_hard_regno_nregs
[mode
][regno
];
2153 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2156 rs6000_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2158 return rs6000_hard_regno_mode_ok_p
[mode
][regno
];
2161 /* Implement TARGET_MODES_TIEABLE_P.
2163 PTImode cannot tie with other modes because PTImode is restricted to even
2164 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2167 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2168 128-bit floating point on VSX systems ties with other vectors. */
2171 rs6000_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2173 if (mode1
== PTImode
)
2174 return mode2
== PTImode
;
2175 if (mode2
== PTImode
)
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1
))
2179 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2
);
2180 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2
))
2183 if (SCALAR_FLOAT_MODE_P (mode1
))
2184 return SCALAR_FLOAT_MODE_P (mode2
);
2185 if (SCALAR_FLOAT_MODE_P (mode2
))
2188 if (GET_MODE_CLASS (mode1
) == MODE_CC
)
2189 return GET_MODE_CLASS (mode2
) == MODE_CC
;
2190 if (GET_MODE_CLASS (mode2
) == MODE_CC
)
2196 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2199 rs6000_hard_regno_call_part_clobbered (unsigned int regno
, machine_mode mode
)
2203 && GET_MODE_SIZE (mode
) > 4
2204 && INT_REGNO_P (regno
))
2208 && FP_REGNO_P (regno
)
2209 && GET_MODE_SIZE (mode
) > 8
2210 && !FLOAT128_2REG_P (mode
))
2216 /* Print interesting facts about registers. */
2218 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
2222 for (r
= first_regno
; r
<= last_regno
; ++r
)
2224 const char *comma
= "";
2227 if (first_regno
== last_regno
)
2228 fprintf (stderr
, "%s:\t", reg_name
);
2230 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
2233 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2234 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
2238 fprintf (stderr
, ",\n\t");
2243 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
2244 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
2245 rs6000_hard_regno_nregs
[m
][r
]);
2247 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
2252 if (call_used_regs
[r
])
2256 fprintf (stderr
, ",\n\t");
2261 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
2269 fprintf (stderr
, ",\n\t");
2274 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
2280 fprintf (stderr
, ",\n\t");
2284 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
2285 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
2290 fprintf (stderr
, ",\n\t");
2294 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
2299 rs6000_debug_vector_unit (enum rs6000_vector v
)
2305 case VECTOR_NONE
: ret
= "none"; break;
2306 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
2307 case VECTOR_VSX
: ret
= "vsx"; break;
2308 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
2309 default: ret
= "unknown"; break;
2315 /* Inner function printing just the address mask for a particular reload
2317 DEBUG_FUNCTION
char *
2318 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
2323 if ((mask
& RELOAD_REG_VALID
) != 0)
2325 else if (keep_spaces
)
2328 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
2330 else if (keep_spaces
)
2333 if ((mask
& RELOAD_REG_INDEXED
) != 0)
2335 else if (keep_spaces
)
2338 if ((mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
2340 else if ((mask
& RELOAD_REG_OFFSET
) != 0)
2342 else if (keep_spaces
)
2345 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2347 else if (keep_spaces
)
2350 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2352 else if (keep_spaces
)
2355 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2357 else if (keep_spaces
)
2365 /* Print the address masks in a human readble fashion. */
2367 rs6000_debug_print_mode (ssize_t m
)
2372 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2373 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2374 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2375 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2377 if ((reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2378 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
2380 fprintf (stderr
, "%*s Reload=%c%c", spaces
, "",
2381 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2382 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
2386 spaces
+= sizeof (" Reload=sl") - 1;
2388 if (reg_addr
[m
].scalar_in_vmx_p
)
2390 fprintf (stderr
, "%*s Upper=y", spaces
, "");
2394 spaces
+= sizeof (" Upper=y") - 1;
2396 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2397 || rs6000_vector_mem
[m
] != VECTOR_NONE
)
2399 fprintf (stderr
, "%*s vector: arith=%-10s mem=%s",
2401 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2402 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]));
2405 fputs ("\n", stderr
);
2408 #define DEBUG_FMT_ID "%-32s= "
2409 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2410 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2411 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2413 /* Print various interesting information with -mdebug=reg. */
2415 rs6000_debug_reg_global (void)
2417 static const char *const tf
[2] = { "false", "true" };
2418 const char *nl
= (const char *)0;
2421 char costly_num
[20];
2423 char flags_buffer
[40];
2424 const char *costly_str
;
2425 const char *nop_str
;
2426 const char *trace_str
;
2427 const char *abi_str
;
2428 const char *cmodel_str
;
2429 struct cl_target_option cl_opts
;
2431 /* Modes we want tieable information on. */
2432 static const machine_mode print_tieable_modes
[] = {
2466 /* Virtual regs we are interested in. */
2467 const static struct {
2468 int regno
; /* register number. */
2469 const char *name
; /* register name. */
2470 } virtual_regs
[] = {
2471 { STACK_POINTER_REGNUM
, "stack pointer:" },
2472 { TOC_REGNUM
, "toc: " },
2473 { STATIC_CHAIN_REGNUM
, "static chain: " },
2474 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2475 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2476 { ARG_POINTER_REGNUM
, "arg pointer: " },
2477 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2478 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2479 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2480 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2481 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2482 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2483 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2484 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2485 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2486 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2489 fputs ("\nHard register information:\n", stderr
);
2490 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2491 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2492 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2495 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2496 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2497 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2498 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2499 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2500 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2502 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2503 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2504 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2508 "d reg_class = %s\n"
2509 "f reg_class = %s\n"
2510 "v reg_class = %s\n"
2511 "wa reg_class = %s\n"
2512 "wb reg_class = %s\n"
2513 "wd reg_class = %s\n"
2514 "we reg_class = %s\n"
2515 "wf reg_class = %s\n"
2516 "wg reg_class = %s\n"
2517 "wh reg_class = %s\n"
2518 "wi reg_class = %s\n"
2519 "wj reg_class = %s\n"
2520 "wk reg_class = %s\n"
2521 "wl reg_class = %s\n"
2522 "wm reg_class = %s\n"
2523 "wo reg_class = %s\n"
2524 "wp reg_class = %s\n"
2525 "wq reg_class = %s\n"
2526 "wr reg_class = %s\n"
2527 "ws reg_class = %s\n"
2528 "wt reg_class = %s\n"
2529 "wu reg_class = %s\n"
2530 "wv reg_class = %s\n"
2531 "ww reg_class = %s\n"
2532 "wx reg_class = %s\n"
2533 "wy reg_class = %s\n"
2534 "wz reg_class = %s\n"
2535 "wA reg_class = %s\n"
2536 "wH reg_class = %s\n"
2537 "wI reg_class = %s\n"
2538 "wJ reg_class = %s\n"
2539 "wK reg_class = %s\n"
2541 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2542 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2543 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2544 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2545 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wb
]],
2546 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2547 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_we
]],
2548 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2549 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2550 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2551 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2552 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2553 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2554 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2555 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2556 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wo
]],
2557 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wp
]],
2558 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wq
]],
2559 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2560 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2561 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2562 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2563 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2564 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2565 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2566 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2567 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]],
2568 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wA
]],
2569 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wH
]],
2570 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wI
]],
2571 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wJ
]],
2572 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wK
]]);
2575 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2576 rs6000_debug_print_mode (m
);
2578 fputs ("\n", stderr
);
2580 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2582 machine_mode mode1
= print_tieable_modes
[m1
];
2583 bool first_time
= true;
2585 nl
= (const char *)0;
2586 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2588 machine_mode mode2
= print_tieable_modes
[m2
];
2589 if (mode1
!= mode2
&& rs6000_modes_tieable_p (mode1
, mode2
))
2593 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2598 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2603 fputs ("\n", stderr
);
2609 if (rs6000_recip_control
)
2611 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2613 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2614 if (rs6000_recip_bits
[m
])
2617 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2619 (RS6000_RECIP_AUTO_RE_P (m
)
2621 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2622 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2624 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2627 fputs ("\n", stderr
);
2630 if (rs6000_cpu_index
>= 0)
2632 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2634 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2636 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2637 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2640 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2642 if (rs6000_tune_index
>= 0)
2644 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2646 = processor_target_table
[rs6000_tune_index
].target_enable
;
2648 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2649 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2652 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2654 cl_target_option_save (&cl_opts
, &global_options
);
2655 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2658 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2659 rs6000_isa_flags_explicit
);
2661 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2662 rs6000_builtin_mask
);
2664 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2666 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2667 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2669 switch (rs6000_sched_costly_dep
)
2671 case max_dep_latency
:
2672 costly_str
= "max_dep_latency";
2676 costly_str
= "no_dep_costly";
2679 case all_deps_costly
:
2680 costly_str
= "all_deps_costly";
2683 case true_store_to_load_dep_costly
:
2684 costly_str
= "true_store_to_load_dep_costly";
2687 case store_to_load_dep_costly
:
2688 costly_str
= "store_to_load_dep_costly";
2692 costly_str
= costly_num
;
2693 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2697 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2699 switch (rs6000_sched_insert_nops
)
2701 case sched_finish_regroup_exact
:
2702 nop_str
= "sched_finish_regroup_exact";
2705 case sched_finish_pad_groups
:
2706 nop_str
= "sched_finish_pad_groups";
2709 case sched_finish_none
:
2710 nop_str
= "sched_finish_none";
2715 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2719 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2721 switch (rs6000_sdata
)
2728 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2732 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2736 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2741 switch (rs6000_traceback
)
2743 case traceback_default
: trace_str
= "default"; break;
2744 case traceback_none
: trace_str
= "none"; break;
2745 case traceback_part
: trace_str
= "part"; break;
2746 case traceback_full
: trace_str
= "full"; break;
2747 default: trace_str
= "unknown"; break;
2750 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2752 switch (rs6000_current_cmodel
)
2754 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2755 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2756 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2757 default: cmodel_str
= "unknown"; break;
2760 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2762 switch (rs6000_current_abi
)
2764 case ABI_NONE
: abi_str
= "none"; break;
2765 case ABI_AIX
: abi_str
= "aix"; break;
2766 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2767 case ABI_V4
: abi_str
= "V4"; break;
2768 case ABI_DARWIN
: abi_str
= "darwin"; break;
2769 default: abi_str
= "unknown"; break;
2772 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2774 if (rs6000_altivec_abi
)
2775 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2777 if (rs6000_darwin64_abi
)
2778 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2780 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2781 (TARGET_SOFT_FLOAT
? "true" : "false"));
2783 if (TARGET_LINK_STACK
)
2784 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2786 if (TARGET_P8_FUSION
)
2790 strcpy (options
, (TARGET_P9_FUSION
) ? "power9" : "power8");
2791 if (TARGET_P8_FUSION_SIGN
)
2792 strcat (options
, ", sign");
2794 fprintf (stderr
, DEBUG_FMT_S
, "fusion", options
);
2797 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2798 TARGET_SECURE_PLT
? "secure" : "bss");
2799 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2800 aix_struct_return
? "aix" : "sysv");
2801 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2802 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2803 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2804 tf
[!!rs6000_align_branch_targets
]);
2805 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2806 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2807 rs6000_long_double_type_size
);
2808 if (rs6000_long_double_type_size
> 64)
2810 fprintf (stderr
, DEBUG_FMT_S
, "long double type",
2811 TARGET_IEEEQUAD
? "IEEE" : "IBM");
2812 fprintf (stderr
, DEBUG_FMT_S
, "default long double type",
2813 TARGET_IEEEQUAD_DEFAULT
? "IEEE" : "IBM");
2815 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2816 (int)rs6000_sched_restricted_insns_priority
);
2817 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2819 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2820 (int)RS6000_BUILTIN_COUNT
);
2822 fprintf (stderr
, DEBUG_FMT_D
, "Enable float128 on VSX",
2823 (int)TARGET_FLOAT128_ENABLE_TYPE
);
2826 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2827 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2829 if (TARGET_DIRECT_MOVE_128
)
2830 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit mfvsrld element",
2831 (int)VECTOR_ELEMENT_MFVSRLD_64BIT
);
2835 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2836 legitimate address support to figure out the appropriate addressing to
2840 rs6000_setup_reg_addr_masks (void)
2842 ssize_t rc
, reg
, m
, nregs
;
2843 addr_mask_type any_addr_mask
, addr_mask
;
2845 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2847 machine_mode m2
= (machine_mode
) m
;
2848 bool complex_p
= false;
2849 bool small_int_p
= (m2
== QImode
|| m2
== HImode
|| m2
== SImode
);
2852 if (COMPLEX_MODE_P (m2
))
2855 m2
= GET_MODE_INNER (m2
);
2858 msize
= GET_MODE_SIZE (m2
);
2860 /* SDmode is special in that we want to access it only via REG+REG
2861 addressing on power7 and above, since we want to use the LFIWZX and
2862 STFIWZX instructions to load it. */
2863 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2866 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2869 reg
= reload_reg_map
[rc
].reg
;
2871 /* Can mode values go in the GPR/FPR/Altivec registers? */
2872 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2874 bool small_int_vsx_p
= (small_int_p
2875 && (rc
== RELOAD_REG_FPR
2876 || rc
== RELOAD_REG_VMX
));
2878 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2879 addr_mask
|= RELOAD_REG_VALID
;
2881 /* Indicate if the mode takes more than 1 physical register. If
2882 it takes a single register, indicate it can do REG+REG
2883 addressing. Small integers in VSX registers can only do
2884 REG+REG addressing. */
2885 if (small_int_vsx_p
)
2886 addr_mask
|= RELOAD_REG_INDEXED
;
2887 else if (nregs
> 1 || m
== BLKmode
|| complex_p
)
2888 addr_mask
|= RELOAD_REG_MULTIPLE
;
2890 addr_mask
|= RELOAD_REG_INDEXED
;
2892 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2893 addressing. If we allow scalars into Altivec registers,
2894 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2896 For VSX systems, we don't allow update addressing for
2897 DFmode/SFmode if those registers can go in both the
2898 traditional floating point registers and Altivec registers.
2899 The load/store instructions for the Altivec registers do not
2900 have update forms. If we allowed update addressing, it seems
2901 to break IV-OPT code using floating point if the index type is
2902 int instead of long (PR target/81550 and target/84042). */
2905 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2907 && !VECTOR_MODE_P (m2
)
2908 && !FLOAT128_VECTOR_P (m2
)
2910 && (m
!= E_DFmode
|| !TARGET_VSX
)
2911 && (m
!= E_SFmode
|| !TARGET_P8_VECTOR
)
2912 && !small_int_vsx_p
)
2914 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2916 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2917 we don't allow PRE_MODIFY for some multi-register
2922 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2926 if (TARGET_POWERPC64
)
2927 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2932 if (TARGET_HARD_FLOAT
)
2933 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2939 /* GPR and FPR registers can do REG+OFFSET addressing, except
2940 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2941 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2942 if ((addr_mask
!= 0) && !indexed_only_p
2944 && (rc
== RELOAD_REG_GPR
2945 || ((msize
== 8 || m2
== SFmode
)
2946 && (rc
== RELOAD_REG_FPR
2947 || (rc
== RELOAD_REG_VMX
&& TARGET_P9_VECTOR
)))))
2948 addr_mask
|= RELOAD_REG_OFFSET
;
2950 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2951 instructions are enabled. The offset for 128-bit VSX registers is
2952 only 12-bits. While GPRs can handle the full offset range, VSX
2953 registers can only handle the restricted range. */
2954 else if ((addr_mask
!= 0) && !indexed_only_p
2955 && msize
== 16 && TARGET_P9_VECTOR
2956 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2
)
2957 || (m2
== TImode
&& TARGET_VSX
)))
2959 addr_mask
|= RELOAD_REG_OFFSET
;
2960 if (rc
== RELOAD_REG_FPR
|| rc
== RELOAD_REG_VMX
)
2961 addr_mask
|= RELOAD_REG_QUAD_OFFSET
;
2964 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2965 addressing on 128-bit types. */
2966 if (rc
== RELOAD_REG_VMX
&& msize
== 16
2967 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2968 addr_mask
|= RELOAD_REG_AND_M16
;
2970 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2971 any_addr_mask
|= addr_mask
;
2974 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2979 /* Initialize the various global tables that are based on register size. */
2981 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2987 /* Precalculate REGNO_REG_CLASS. */
2988 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2989 for (r
= 1; r
< 32; ++r
)
2990 rs6000_regno_regclass
[r
] = BASE_REGS
;
2992 for (r
= 32; r
< 64; ++r
)
2993 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2995 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2996 rs6000_regno_regclass
[r
] = NO_REGS
;
2998 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2999 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
3001 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
3002 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
3003 rs6000_regno_regclass
[r
] = CR_REGS
;
3005 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
3006 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
3007 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
3008 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
3009 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
3010 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
3011 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
3012 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
3013 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
3014 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
3016 /* Precalculate register class to simpler reload register class. We don't
3017 need all of the register classes that are combinations of different
3018 classes, just the simple ones that have constraint letters. */
3019 for (c
= 0; c
< N_REG_CLASSES
; c
++)
3020 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
3022 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
3023 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
3024 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
3025 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
3026 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
3027 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
3028 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
3029 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
3030 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
3031 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
3035 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
3036 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
3040 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
3041 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
3044 /* Precalculate the valid memory formats as well as the vector information,
3045 this must be set up before the rs6000_hard_regno_nregs_internal calls
3047 gcc_assert ((int)VECTOR_NONE
== 0);
3048 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
3049 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
3051 gcc_assert ((int)CODE_FOR_nothing
== 0);
3052 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
3054 gcc_assert ((int)NO_REGS
== 0);
3055 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
3057 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3058 believes it can use native alignment or still uses 128-bit alignment. */
3059 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
3070 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3071 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3072 if (TARGET_FLOAT128_TYPE
)
3074 rs6000_vector_mem
[KFmode
] = VECTOR_VSX
;
3075 rs6000_vector_align
[KFmode
] = 128;
3077 if (FLOAT128_IEEE_P (TFmode
))
3079 rs6000_vector_mem
[TFmode
] = VECTOR_VSX
;
3080 rs6000_vector_align
[TFmode
] = 128;
3084 /* V2DF mode, VSX only. */
3087 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
3088 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
3089 rs6000_vector_align
[V2DFmode
] = align64
;
3092 /* V4SF mode, either VSX or Altivec. */
3095 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
3096 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
3097 rs6000_vector_align
[V4SFmode
] = align32
;
3099 else if (TARGET_ALTIVEC
)
3101 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
3102 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
3103 rs6000_vector_align
[V4SFmode
] = align32
;
3106 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3110 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
3111 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
3112 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
3113 rs6000_vector_align
[V4SImode
] = align32
;
3114 rs6000_vector_align
[V8HImode
] = align32
;
3115 rs6000_vector_align
[V16QImode
] = align32
;
3119 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
3120 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
3121 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
3125 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
3126 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
3127 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
3131 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3132 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3135 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
3136 rs6000_vector_unit
[V2DImode
]
3137 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3138 rs6000_vector_align
[V2DImode
] = align64
;
3140 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
3141 rs6000_vector_unit
[V1TImode
]
3142 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3143 rs6000_vector_align
[V1TImode
] = 128;
3146 /* DFmode, see if we want to use the VSX unit. Memory is handled
3147 differently, so don't set rs6000_vector_mem. */
3150 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
3151 rs6000_vector_align
[DFmode
] = 64;
3154 /* SFmode, see if we want to use the VSX unit. */
3155 if (TARGET_P8_VECTOR
)
3157 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
3158 rs6000_vector_align
[SFmode
] = 32;
3161 /* Allow TImode in VSX register and set the VSX memory macros. */
3164 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
3165 rs6000_vector_align
[TImode
] = align64
;
3168 /* Register class constraints for the constraints that depend on compile
3169 switches. When the VSX code was added, different constraints were added
3170 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3171 of the VSX registers are used. The register classes for scalar floating
3172 point types is set, based on whether we allow that type into the upper
3173 (Altivec) registers. GCC has register classes to target the Altivec
3174 registers for load/store operations, to select using a VSX memory
3175 operation instead of the traditional floating point operation. The
3178 d - Register class to use with traditional DFmode instructions.
3179 f - Register class to use with traditional SFmode instructions.
3180 v - Altivec register.
3181 wa - Any VSX register.
3182 wc - Reserved to represent individual CR bits (used in LLVM).
3183 wd - Preferred register class for V2DFmode.
3184 wf - Preferred register class for V4SFmode.
3185 wg - Float register for power6x move insns.
3186 wh - FP register for direct move instructions.
3187 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3188 wj - FP or VSX register to hold 64-bit integers for direct moves.
3189 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3190 wl - Float register if we can do 32-bit signed int loads.
3191 wm - VSX register for ISA 2.07 direct move operations.
3192 wn - always NO_REGS.
3193 wr - GPR if 64-bit mode is permitted.
3194 ws - Register class to do ISA 2.06 DF operations.
3195 wt - VSX register for TImode in VSX registers.
3196 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3197 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3198 ww - Register class to do SF conversions in with VSX operations.
3199 wx - Float register if we can do 32-bit int stores.
3200 wy - Register class to do ISA 2.07 SF operations.
3201 wz - Float register if we can do 32-bit unsigned int loads.
3202 wH - Altivec register if SImode is allowed in VSX registers.
3203 wI - VSX register if SImode is allowed in VSX registers.
3204 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3205 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3207 if (TARGET_HARD_FLOAT
)
3209 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
3210 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
3215 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
3216 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
3217 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
3218 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
; /* DFmode */
3219 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
; /* DFmode */
3220 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = VSX_REGS
; /* DImode */
3221 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
3224 /* Add conditional constraints based on various options, to allow us to
3225 collapse multiple insn patterns. */
3227 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
3229 if (TARGET_MFPGPR
) /* DFmode */
3230 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
3233 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
3235 if (TARGET_DIRECT_MOVE
)
3237 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
3238 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
3239 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
3240 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
3241 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
3242 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
3245 if (TARGET_POWERPC64
)
3247 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
3248 rs6000_constraints
[RS6000_CONSTRAINT_wA
] = BASE_REGS
;
3251 if (TARGET_P8_VECTOR
) /* SFmode */
3253 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
3254 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
3255 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
3257 else if (TARGET_VSX
)
3258 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3261 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
3264 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
3266 if (TARGET_FLOAT128_TYPE
)
3268 rs6000_constraints
[RS6000_CONSTRAINT_wq
] = VSX_REGS
; /* KFmode */
3269 if (FLOAT128_IEEE_P (TFmode
))
3270 rs6000_constraints
[RS6000_CONSTRAINT_wp
] = VSX_REGS
; /* TFmode */
3273 if (TARGET_P9_VECTOR
)
3275 /* Support for new D-form instructions. */
3276 rs6000_constraints
[RS6000_CONSTRAINT_wb
] = ALTIVEC_REGS
;
3278 /* Support for ISA 3.0 (power9) vectors. */
3279 rs6000_constraints
[RS6000_CONSTRAINT_wo
] = VSX_REGS
;
3282 /* Support for new direct moves (ISA 3.0 + 64bit). */
3283 if (TARGET_DIRECT_MOVE_128
)
3284 rs6000_constraints
[RS6000_CONSTRAINT_we
] = VSX_REGS
;
3286 /* Support small integers in VSX registers. */
3287 if (TARGET_P8_VECTOR
)
3289 rs6000_constraints
[RS6000_CONSTRAINT_wH
] = ALTIVEC_REGS
;
3290 rs6000_constraints
[RS6000_CONSTRAINT_wI
] = FLOAT_REGS
;
3291 if (TARGET_P9_VECTOR
)
3293 rs6000_constraints
[RS6000_CONSTRAINT_wJ
] = FLOAT_REGS
;
3294 rs6000_constraints
[RS6000_CONSTRAINT_wK
] = ALTIVEC_REGS
;
3298 /* Set up the reload helper and direct move functions. */
3299 if (TARGET_VSX
|| TARGET_ALTIVEC
)
3303 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
3304 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
3305 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
3306 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
3307 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
3308 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
3309 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
3310 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
3311 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
3312 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
3313 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
3314 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
3315 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
3316 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
3317 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
3318 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
3319 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
3320 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
3321 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
3322 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
3324 if (FLOAT128_VECTOR_P (KFmode
))
3326 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_di_store
;
3327 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_di_load
;
3330 if (FLOAT128_VECTOR_P (TFmode
))
3332 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_di_store
;
3333 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_di_load
;
3336 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3338 if (TARGET_NO_SDMODE_STACK
)
3340 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
3341 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
3346 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
3347 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
3350 if (TARGET_DIRECT_MOVE
&& !TARGET_DIRECT_MOVE_128
)
3352 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
3353 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
3354 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
3355 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
3356 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
3357 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
3358 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
3359 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
3360 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
3362 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
3363 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
3364 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
3365 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
3366 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
3367 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
3368 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
3369 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
3370 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
3372 if (FLOAT128_VECTOR_P (KFmode
))
3374 reg_addr
[KFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxkf
;
3375 reg_addr
[KFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprkf
;
3378 if (FLOAT128_VECTOR_P (TFmode
))
3380 reg_addr
[TFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxtf
;
3381 reg_addr
[TFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprtf
;
3387 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
3388 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
3389 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
3390 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
3391 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
3392 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
3393 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
3394 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
3395 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
3396 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
3397 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
3398 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
3399 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
3400 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
3401 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
3402 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
3403 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
3404 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
3405 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
3406 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
3408 if (FLOAT128_VECTOR_P (KFmode
))
3410 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_si_store
;
3411 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_si_load
;
3414 if (FLOAT128_IEEE_P (TFmode
))
3416 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_si_store
;
3417 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_si_load
;
3420 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3422 if (TARGET_NO_SDMODE_STACK
)
3424 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
3425 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
3430 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
3431 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
3434 if (TARGET_DIRECT_MOVE
)
3436 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
3437 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
3438 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
3442 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
3443 reg_addr
[DImode
].scalar_in_vmx_p
= true;
3445 if (TARGET_P8_VECTOR
)
3447 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
3448 reg_addr
[SImode
].scalar_in_vmx_p
= true;
3450 if (TARGET_P9_VECTOR
)
3452 reg_addr
[HImode
].scalar_in_vmx_p
= true;
3453 reg_addr
[QImode
].scalar_in_vmx_p
= true;
3458 /* Precalculate HARD_REGNO_NREGS. */
3459 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3460 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3461 rs6000_hard_regno_nregs
[m
][r
]
3462 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
)m
);
3464 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3465 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3466 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3467 if (rs6000_hard_regno_mode_ok_uncached (r
, (machine_mode
)m
))
3468 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
3470 /* Precalculate CLASS_MAX_NREGS sizes. */
3471 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
3475 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
3476 reg_size
= UNITS_PER_VSX_WORD
;
3478 else if (c
== ALTIVEC_REGS
)
3479 reg_size
= UNITS_PER_ALTIVEC_WORD
;
3481 else if (c
== FLOAT_REGS
)
3482 reg_size
= UNITS_PER_FP_WORD
;
3485 reg_size
= UNITS_PER_WORD
;
3487 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3489 machine_mode m2
= (machine_mode
)m
;
3490 int reg_size2
= reg_size
;
3492 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3494 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
) && FLOAT128_2REG_P (m
))
3495 reg_size2
= UNITS_PER_FP_WORD
;
3497 rs6000_class_max_nregs
[m
][c
]
3498 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3502 /* Calculate which modes to automatically generate code to use a the
3503 reciprocal divide and square root instructions. In the future, possibly
3504 automatically generate the instructions even if the user did not specify
3505 -mrecip. The older machines double precision reciprocal sqrt estimate is
3506 not accurate enough. */
3507 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3509 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3511 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3512 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3513 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3514 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3515 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3517 if (TARGET_FRSQRTES
)
3518 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3520 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3521 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3522 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3523 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3524 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3526 if (rs6000_recip_control
)
3528 if (!flag_finite_math_only
)
3529 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3531 if (flag_trapping_math
)
3532 warning (0, "%qs requires %qs or %qs", "-mrecip",
3533 "-fno-trapping-math", "-ffast-math");
3534 if (!flag_reciprocal_math
)
3535 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3537 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3539 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3540 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3541 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3543 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3544 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3545 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3547 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3548 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3549 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3551 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3552 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3553 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3555 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3556 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3557 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3559 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3560 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3561 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3563 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3564 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3565 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3567 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3568 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3569 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3573 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3574 legitimate address support to figure out the appropriate addressing to
3576 rs6000_setup_reg_addr_masks ();
3578 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3580 if (TARGET_DEBUG_REG
)
3581 rs6000_debug_reg_global ();
3583 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3585 "SImode variable mult cost = %d\n"
3586 "SImode constant mult cost = %d\n"
3587 "SImode short constant mult cost = %d\n"
3588 "DImode multipliciation cost = %d\n"
3589 "SImode division cost = %d\n"
3590 "DImode division cost = %d\n"
3591 "Simple fp operation cost = %d\n"
3592 "DFmode multiplication cost = %d\n"
3593 "SFmode division cost = %d\n"
3594 "DFmode division cost = %d\n"
3595 "cache line size = %d\n"
3596 "l1 cache size = %d\n"
3597 "l2 cache size = %d\n"
3598 "simultaneous prefetches = %d\n"
3601 rs6000_cost
->mulsi_const
,
3602 rs6000_cost
->mulsi_const9
,
3610 rs6000_cost
->cache_line_size
,
3611 rs6000_cost
->l1_cache_size
,
3612 rs6000_cost
->l2_cache_size
,
3613 rs6000_cost
->simultaneous_prefetches
);
3618 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3621 darwin_rs6000_override_options (void)
3623 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3625 rs6000_altivec_abi
= 1;
3626 TARGET_ALTIVEC_VRSAVE
= 1;
3627 rs6000_current_abi
= ABI_DARWIN
;
3629 if (DEFAULT_ABI
== ABI_DARWIN
3631 darwin_one_byte_bool
= 1;
3633 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3635 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3636 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3640 rs6000_default_long_calls
= 1;
3641 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3644 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3646 if (!flag_mkernel
&& !flag_apple_kext
3648 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3649 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3651 /* Unless the user (not the configurer) has explicitly overridden
3652 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3653 G4 unless targeting the kernel. */
3656 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3657 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3658 && ! global_options_set
.x_rs6000_cpu_index
)
3660 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3665 /* If not otherwise specified by a target, make 'long double' equivalent to
3668 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3669 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3672 /* Return the builtin mask of the various options used that could affect which
3673 builtins were used. In the past we used target_flags, but we've run out of
3674 bits, and some options are no longer in target_flags. */
3677 rs6000_builtin_mask_calculate (void)
3679 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3680 | ((TARGET_CMPB
) ? RS6000_BTM_CMPB
: 0)
3681 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3682 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3683 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3684 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3685 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3686 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3687 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3688 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3689 | ((TARGET_P9_VECTOR
) ? RS6000_BTM_P9_VECTOR
: 0)
3690 | ((TARGET_P9_MISC
) ? RS6000_BTM_P9_MISC
: 0)
3691 | ((TARGET_MODULO
) ? RS6000_BTM_MODULO
: 0)
3692 | ((TARGET_64BIT
) ? RS6000_BTM_64BIT
: 0)
3693 | ((TARGET_POWERPC64
) ? RS6000_BTM_POWERPC64
: 0)
3694 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3695 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3696 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3697 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3698 | ((TARGET_LONG_DOUBLE_128
3699 && TARGET_HARD_FLOAT
3700 && !TARGET_IEEEQUAD
) ? RS6000_BTM_LDBL128
: 0)
3701 | ((TARGET_FLOAT128_TYPE
) ? RS6000_BTM_FLOAT128
: 0)
3702 | ((TARGET_FLOAT128_HW
) ? RS6000_BTM_FLOAT128_HW
: 0));
3705 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3706 to clobber the XER[CA] bit because clobbering that bit without telling
3707 the compiler worked just fine with versions of GCC before GCC 5, and
3708 breaking a lot of older code in ways that are hard to track down is
3709 not such a great idea. */
3712 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3713 vec
<const char *> &/*constraints*/,
3714 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3716 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3717 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3721 /* Override command line options.
3723 Combine build-specific configuration information with options
3724 specified on the command line to set various state variables which
3725 influence code generation, optimization, and expansion of built-in
3726 functions. Assure that command-line configuration preferences are
3727 compatible with each other and with the build configuration; issue
3728 warnings while adjusting configuration or error messages while
3729 rejecting configuration.
3731 Upon entry to this function:
3733 This function is called once at the beginning of
3734 compilation, and then again at the start and end of compiling
3735 each section of code that has a different configuration, as
3736 indicated, for example, by adding the
3738 __attribute__((__target__("cpu=power9")))
3740 qualifier to a function definition or, for example, by bracketing
3743 #pragma GCC target("altivec")
3747 #pragma GCC reset_options
3749 directives. Parameter global_init_p is true for the initial
3750 invocation, which initializes global variables, and false for all
3751 subsequent invocations.
3754 Various global state information is assumed to be valid. This
3755 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3756 default CPU specified at build configure time, TARGET_DEFAULT,
3757 representing the default set of option flags for the default
3758 target, and global_options_set.x_rs6000_isa_flags, representing
3759 which options were requested on the command line.
3761 Upon return from this function:
3763 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3764 was set by name on the command line. Additionally, if certain
3765 attributes are automatically enabled or disabled by this function
3766 in order to assure compatibility between options and
3767 configuration, the flags associated with those attributes are
3768 also set. By setting these "explicit bits", we avoid the risk
3769 that other code might accidentally overwrite these particular
3770 attributes with "default values".
3772 The various bits of rs6000_isa_flags are set to indicate the
3773 target options that have been selected for the most current
3774 compilation efforts. This has the effect of also turning on the
3775 associated TARGET_XXX values since these are macros which are
3776 generally defined to test the corresponding bit of the
3777 rs6000_isa_flags variable.
3779 The variable rs6000_builtin_mask is set to represent the target
3780 options for the most current compilation efforts, consistent with
3781 the current contents of rs6000_isa_flags. This variable controls
3782 expansion of built-in functions.
3784 Various other global variables and fields of global structures
3785 (over 50 in all) are initialized to reflect the desired options
3786 for the most current compilation efforts. */
3789 rs6000_option_override_internal (bool global_init_p
)
3793 HOST_WIDE_INT set_masks
;
3794 HOST_WIDE_INT ignore_masks
;
3797 struct cl_target_option
*main_target_opt
3798 = ((global_init_p
|| target_option_default_node
== NULL
)
3799 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3801 /* Print defaults. */
3802 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3803 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3805 /* Remember the explicit arguments. */
3807 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3809 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3810 library functions, so warn about it. The flag may be useful for
3811 performance studies from time to time though, so don't disable it
3813 if (global_options_set
.x_rs6000_alignment_flags
3814 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3815 && DEFAULT_ABI
== ABI_DARWIN
3817 warning (0, "%qs is not supported for 64-bit Darwin;"
3818 " it is incompatible with the installed C and C++ libraries",
3821 /* Numerous experiment shows that IRA based loop pressure
3822 calculation works better for RTL loop invariant motion on targets
3823 with enough (>= 32) registers. It is an expensive optimization.
3824 So it is on only for peak performance. */
3825 if (optimize
>= 3 && global_init_p
3826 && !global_options_set
.x_flag_ira_loop_pressure
)
3827 flag_ira_loop_pressure
= 1;
3829 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3830 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3831 options were already specified. */
3832 if (flag_sanitize
& SANITIZE_USER_ADDRESS
3833 && !global_options_set
.x_flag_asynchronous_unwind_tables
)
3834 flag_asynchronous_unwind_tables
= 1;
3836 /* Set the pointer size. */
3839 rs6000_pmode
= DImode
;
3840 rs6000_pointer_size
= 64;
3844 rs6000_pmode
= SImode
;
3845 rs6000_pointer_size
= 32;
3848 /* Some OSs don't support saving the high part of 64-bit registers on context
3849 switch. Other OSs don't support saving Altivec registers. On those OSs,
3850 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3851 if the user wants either, the user must explicitly specify them and we
3852 won't interfere with the user's specification. */
3854 set_masks
= POWERPC_MASKS
;
3855 #ifdef OS_MISSING_POWERPC64
3856 if (OS_MISSING_POWERPC64
)
3857 set_masks
&= ~OPTION_MASK_POWERPC64
;
3859 #ifdef OS_MISSING_ALTIVEC
3860 if (OS_MISSING_ALTIVEC
)
3861 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
3862 | OTHER_VSX_VECTOR_MASKS
);
3865 /* Don't override by the processor default if given explicitly. */
3866 set_masks
&= ~rs6000_isa_flags_explicit
;
3868 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3869 the cpu in a target attribute or pragma, but did not specify a tuning
3870 option, use the cpu for the tuning option rather than the option specified
3871 with -mtune on the command line. Process a '--with-cpu' configuration
3872 request as an implicit --cpu. */
3873 if (rs6000_cpu_index
>= 0)
3874 cpu_index
= rs6000_cpu_index
;
3875 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3876 cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3877 else if (OPTION_TARGET_CPU_DEFAULT
)
3878 cpu_index
= rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT
);
3880 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3881 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3882 with those from the cpu, except for options that were explicitly set. If
3883 we don't have a cpu, do not override the target bits set in
3887 rs6000_cpu_index
= cpu_index
;
3888 rs6000_isa_flags
&= ~set_masks
;
3889 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3894 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3895 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3896 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3897 to using rs6000_isa_flags, we need to do the initialization here.
3899 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3900 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3901 HOST_WIDE_INT flags
;
3903 flags
= TARGET_DEFAULT
;
3906 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3907 const char *default_cpu
= (!TARGET_POWERPC64
3912 int default_cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3913 flags
= processor_target_table
[default_cpu_index
].target_enable
;
3915 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
3918 if (rs6000_tune_index
>= 0)
3919 tune_index
= rs6000_tune_index
;
3920 else if (cpu_index
>= 0)
3921 rs6000_tune_index
= tune_index
= cpu_index
;
3925 enum processor_type tune_proc
3926 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3929 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3930 if (processor_target_table
[i
].processor
== tune_proc
)
3938 rs6000_cpu
= processor_target_table
[cpu_index
].processor
;
3940 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
3942 gcc_assert (tune_index
>= 0);
3943 rs6000_tune
= processor_target_table
[tune_index
].processor
;
3945 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3946 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3947 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3950 error ("AltiVec not supported in this target");
3953 /* If we are optimizing big endian systems for space, use the load/store
3954 multiple instructions. */
3955 if (BYTES_BIG_ENDIAN
&& optimize_size
)
3956 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
;
3958 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3959 because the hardware doesn't support the instructions used in little
3960 endian mode, and causes an alignment trap. The 750 does not cause an
3961 alignment trap (except when the target is unaligned). */
3963 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
&& TARGET_MULTIPLE
)
3965 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3966 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3967 warning (0, "%qs is not supported on little endian systems",
3971 /* If little-endian, default to -mstrict-align on older processors.
3972 Testing for htm matches power8 and later. */
3973 if (!BYTES_BIG_ENDIAN
3974 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3975 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3977 if (!rs6000_fold_gimple
)
3979 "gimple folding of rs6000 builtins has been disabled.\n");
3981 /* Add some warnings for VSX. */
3984 const char *msg
= NULL
;
3985 if (!TARGET_HARD_FLOAT
)
3987 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3988 msg
= N_("-mvsx requires hardware floating point");
3991 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3992 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3995 else if (TARGET_AVOID_XFORM
> 0)
3996 msg
= N_("-mvsx needs indexed addressing");
3997 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3998 & OPTION_MASK_ALTIVEC
))
4000 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4001 msg
= N_("-mvsx and -mno-altivec are incompatible");
4003 msg
= N_("-mno-altivec disables vsx");
4009 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
4010 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4014 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4015 the -mcpu setting to enable options that conflict. */
4016 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
4017 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
4018 | OPTION_MASK_ALTIVEC
4019 | OPTION_MASK_VSX
)) != 0)
4020 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
4021 | OPTION_MASK_DIRECT_MOVE
)
4022 & ~rs6000_isa_flags_explicit
);
4024 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4025 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
4027 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4028 off all of the options that depend on those flags. */
4029 ignore_masks
= rs6000_disable_incompatible_switches ();
4031 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4032 unless the user explicitly used the -mno-<option> to disable the code. */
4033 if (TARGET_P9_VECTOR
|| TARGET_MODULO
|| TARGET_P9_MISC
)
4034 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4035 else if (TARGET_P9_MINMAX
)
4039 if (cpu_index
== PROCESSOR_POWER9
)
4041 /* legacy behavior: allow -mcpu=power9 with certain
4042 capabilities explicitly disabled. */
4043 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4046 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4047 "for <xxx> less than power9", "-mcpu");
4049 else if ((ISA_3_0_MASKS_SERVER
& rs6000_isa_flags_explicit
)
4050 != (ISA_3_0_MASKS_SERVER
& rs6000_isa_flags
4051 & rs6000_isa_flags_explicit
))
4052 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4053 were explicitly cleared. */
4054 error ("%qs incompatible with explicitly disabled options",
4057 rs6000_isa_flags
|= ISA_3_0_MASKS_SERVER
;
4059 else if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
4060 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~ignore_masks
);
4061 else if (TARGET_VSX
)
4062 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~ignore_masks
);
4063 else if (TARGET_POPCNTD
)
4064 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~ignore_masks
);
4065 else if (TARGET_DFP
)
4066 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~ignore_masks
);
4067 else if (TARGET_CMPB
)
4068 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~ignore_masks
);
4069 else if (TARGET_FPRND
)
4070 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~ignore_masks
);
4071 else if (TARGET_POPCNTB
)
4072 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~ignore_masks
);
4073 else if (TARGET_ALTIVEC
)
4074 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~ignore_masks
);
4076 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
4078 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
4079 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4080 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
4083 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
4085 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
4086 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4087 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
4090 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
4092 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4093 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4094 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4097 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
4099 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4100 && (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
))
4101 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4102 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
) == 0)
4104 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4105 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4106 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4110 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4112 rs6000_isa_flags
|= OPTION_MASK_VSX
;
4113 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4117 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
4119 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
4120 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4121 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
4124 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4125 silently turn off quad memory mode. */
4126 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
4128 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4129 warning (0, N_("-mquad-memory requires 64-bit mode"));
4131 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
4132 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4134 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
4135 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
4138 /* Non-atomic quad memory load/store are disabled for little endian, since
4139 the words are reversed, but atomic operations can still be done by
4140 swapping the words. */
4141 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
4143 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4144 warning (0, N_("-mquad-memory is not available in little endian "
4147 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
4150 /* Assume if the user asked for normal quad memory instructions, they want
4151 the atomic versions as well, unless they explicity told us not to use quad
4152 word atomic instructions. */
4153 if (TARGET_QUAD_MEMORY
4154 && !TARGET_QUAD_MEMORY_ATOMIC
4155 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
4156 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
4158 /* If we can shrink-wrap the TOC register save separately, then use
4159 -msave-toc-indirect unless explicitly disabled. */
4160 if ((rs6000_isa_flags_explicit
& OPTION_MASK_SAVE_TOC_INDIRECT
) == 0
4161 && flag_shrink_wrap_separate
4162 && optimize_function_for_speed_p (cfun
))
4163 rs6000_isa_flags
|= OPTION_MASK_SAVE_TOC_INDIRECT
;
4165 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4166 generating power8 instructions. */
4167 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
4168 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4169 & OPTION_MASK_P8_FUSION
);
4171 /* Setting additional fusion flags turns on base fusion. */
4172 if (!TARGET_P8_FUSION
&& TARGET_P8_FUSION_SIGN
)
4174 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4176 if (TARGET_P8_FUSION_SIGN
)
4177 error ("%qs requires %qs", "-mpower8-fusion-sign",
4180 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4183 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4186 /* Power9 fusion is a superset over power8 fusion. */
4187 if (TARGET_P9_FUSION
&& !TARGET_P8_FUSION
)
4189 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4191 /* We prefer to not mention undocumented options in
4192 error messages. However, if users have managed to select
4193 power9-fusion without selecting power8-fusion, they
4194 already know about undocumented flags. */
4195 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4196 rs6000_isa_flags
&= ~OPTION_MASK_P9_FUSION
;
4199 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4202 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4203 generating power9 instructions. */
4204 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_FUSION
))
4205 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4206 & OPTION_MASK_P9_FUSION
);
4208 /* Power8 does not fuse sign extended loads with the addis. If we are
4209 optimizing at high levels for speed, convert a sign extended load into a
4210 zero extending load, and an explicit sign extension. */
4211 if (TARGET_P8_FUSION
4212 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
4213 && optimize_function_for_speed_p (cfun
)
4215 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
4217 /* ISA 3.0 vector instructions include ISA 2.07. */
4218 if (TARGET_P9_VECTOR
&& !TARGET_P8_VECTOR
)
4220 /* We prefer to not mention undocumented options in
4221 error messages. However, if users have managed to select
4222 power9-vector without selecting power8-vector, they
4223 already know about undocumented flags. */
4224 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) &&
4225 (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
))
4226 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4227 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) == 0)
4229 rs6000_isa_flags
&= ~OPTION_MASK_P9_VECTOR
;
4230 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4231 rs6000_isa_flags_explicit
|= OPTION_MASK_P9_VECTOR
;
4235 /* OPTION_MASK_P9_VECTOR is explicit and
4236 OPTION_MASK_P8_VECTOR is not explicit. */
4237 rs6000_isa_flags
|= OPTION_MASK_P8_VECTOR
;
4238 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4242 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4243 support. If we only have ISA 2.06 support, and the user did not specify
4244 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4245 but we don't enable the full vectorization support */
4246 if (TARGET_ALLOW_MOVMISALIGN
== -1 && TARGET_P8_VECTOR
&& TARGET_DIRECT_MOVE
)
4247 TARGET_ALLOW_MOVMISALIGN
= 1;
4249 else if (TARGET_ALLOW_MOVMISALIGN
&& !TARGET_VSX
)
4251 if (TARGET_ALLOW_MOVMISALIGN
> 0
4252 && global_options_set
.x_TARGET_ALLOW_MOVMISALIGN
)
4253 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4255 TARGET_ALLOW_MOVMISALIGN
= 0;
4258 /* Determine when unaligned vector accesses are permitted, and when
4259 they are preferred over masked Altivec loads. Note that if
4260 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4261 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4263 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4267 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4268 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4270 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4273 else if (!TARGET_ALLOW_MOVMISALIGN
)
4275 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4276 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4277 "-mallow-movmisalign");
4279 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4283 /* Use long double size to select the appropriate long double. We use
4284 TYPE_PRECISION to differentiate the 3 different long double types. We map
4285 128 into the precision used for TFmode. */
4286 int default_long_double_size
= (RS6000_DEFAULT_LONG_DOUBLE_SIZE
== 64
4288 : FLOAT_PRECISION_TFmode
);
4290 /* Set long double size before the IEEE 128-bit tests. */
4291 if (!global_options_set
.x_rs6000_long_double_type_size
)
4293 if (main_target_opt
!= NULL
4294 && (main_target_opt
->x_rs6000_long_double_type_size
4295 != default_long_double_size
))
4296 error ("target attribute or pragma changes long double size");
4298 rs6000_long_double_type_size
= default_long_double_size
;
4300 else if (rs6000_long_double_type_size
== 128)
4301 rs6000_long_double_type_size
= FLOAT_PRECISION_TFmode
;
4303 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4304 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4305 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4306 those systems will not pick up this default. Warn if the user changes the
4307 default unless -Wno-psabi. */
4308 if (!global_options_set
.x_rs6000_ieeequad
)
4309 rs6000_ieeequad
= TARGET_IEEEQUAD_DEFAULT
;
4311 else if (rs6000_ieeequad
!= TARGET_IEEEQUAD_DEFAULT
&& TARGET_LONG_DOUBLE_128
)
4313 static bool warned_change_long_double
;
4314 if (!warned_change_long_double
)
4316 warned_change_long_double
= true;
4317 if (TARGET_IEEEQUAD
)
4318 warning (OPT_Wpsabi
, "Using IEEE extended precision long double");
4320 warning (OPT_Wpsabi
, "Using IBM extended precision long double");
4324 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4325 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4326 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4327 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4328 the keyword as well as the type. */
4329 TARGET_FLOAT128_TYPE
= TARGET_FLOAT128_ENABLE_TYPE
&& TARGET_VSX
;
4331 /* IEEE 128-bit floating point requires VSX support. */
4332 if (TARGET_FLOAT128_KEYWORD
)
4336 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) != 0)
4337 error ("%qs requires VSX support", "-mfloat128");
4339 TARGET_FLOAT128_TYPE
= 0;
4340 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_KEYWORD
4341 | OPTION_MASK_FLOAT128_HW
);
4343 else if (!TARGET_FLOAT128_TYPE
)
4345 TARGET_FLOAT128_TYPE
= 1;
4346 warning (0, "The -mfloat128 option may not be fully supported");
4350 /* Enable the __float128 keyword under Linux by default. */
4351 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_KEYWORD
4352 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) == 0)
4353 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_KEYWORD
;
4355 /* If we have are supporting the float128 type and full ISA 3.0 support,
4356 enable -mfloat128-hardware by default. However, don't enable the
4357 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4358 because sometimes the compiler wants to put things in an integer
4359 container, and if we don't have __int128 support, it is impossible. */
4360 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_HW
&& TARGET_64BIT
4361 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) == ISA_3_0_MASKS_IEEE
4362 && !(rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
))
4363 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_HW
;
4365 if (TARGET_FLOAT128_HW
4366 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) != ISA_3_0_MASKS_IEEE
)
4368 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4369 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4371 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4374 if (TARGET_FLOAT128_HW
&& !TARGET_64BIT
)
4376 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4377 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4379 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4382 /* Print the options after updating the defaults. */
4383 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4384 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
4386 /* E500mc does "better" if we inline more aggressively. Respect the
4387 user's opinion, though. */
4388 if (rs6000_block_move_inline_limit
== 0
4389 && (rs6000_tune
== PROCESSOR_PPCE500MC
4390 || rs6000_tune
== PROCESSOR_PPCE500MC64
4391 || rs6000_tune
== PROCESSOR_PPCE5500
4392 || rs6000_tune
== PROCESSOR_PPCE6500
))
4393 rs6000_block_move_inline_limit
= 128;
4395 /* store_one_arg depends on expand_block_move to handle at least the
4396 size of reg_parm_stack_space. */
4397 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
4398 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
4402 /* If the appropriate debug option is enabled, replace the target hooks
4403 with debug versions that call the real version and then prints
4404 debugging information. */
4405 if (TARGET_DEBUG_COST
)
4407 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
4408 targetm
.address_cost
= rs6000_debug_address_cost
;
4409 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
4412 if (TARGET_DEBUG_ADDR
)
4414 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
4415 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
4416 rs6000_secondary_reload_class_ptr
4417 = rs6000_debug_secondary_reload_class
;
4418 targetm
.secondary_memory_needed
4419 = rs6000_debug_secondary_memory_needed
;
4420 targetm
.can_change_mode_class
4421 = rs6000_debug_can_change_mode_class
;
4422 rs6000_preferred_reload_class_ptr
4423 = rs6000_debug_preferred_reload_class
;
4424 rs6000_legitimize_reload_address_ptr
4425 = rs6000_debug_legitimize_reload_address
;
4426 rs6000_mode_dependent_address_ptr
4427 = rs6000_debug_mode_dependent_address
;
4430 if (rs6000_veclibabi_name
)
4432 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
4433 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
4436 error ("unknown vectorization library ABI type (%qs) for "
4437 "%qs switch", rs6000_veclibabi_name
, "-mveclibabi=");
4443 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4444 target attribute or pragma which automatically enables both options,
4445 unless the altivec ABI was set. This is set by default for 64-bit, but
4447 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4449 TARGET_FLOAT128_TYPE
= 0;
4450 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
4451 | OPTION_MASK_FLOAT128_KEYWORD
)
4452 & ~rs6000_isa_flags_explicit
);
4455 /* Enable Altivec ABI for AIX -maltivec. */
4456 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
4458 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4459 error ("target attribute or pragma changes AltiVec ABI");
4461 rs6000_altivec_abi
= 1;
4464 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4465 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4466 be explicitly overridden in either case. */
4469 if (!global_options_set
.x_rs6000_altivec_abi
4470 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
4472 if (main_target_opt
!= NULL
&&
4473 !main_target_opt
->x_rs6000_altivec_abi
)
4474 error ("target attribute or pragma changes AltiVec ABI");
4476 rs6000_altivec_abi
= 1;
4480 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4481 So far, the only darwin64 targets are also MACH-O. */
4483 && DEFAULT_ABI
== ABI_DARWIN
4486 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
4487 error ("target attribute or pragma changes darwin64 ABI");
4490 rs6000_darwin64_abi
= 1;
4491 /* Default to natural alignment, for better performance. */
4492 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
4496 /* Place FP constants in the constant pool instead of TOC
4497 if section anchors enabled. */
4498 if (flag_section_anchors
4499 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
4500 TARGET_NO_FP_IN_TOC
= 1;
4502 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4503 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
4505 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4506 SUBTARGET_OVERRIDE_OPTIONS
;
4508 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4509 SUBSUBTARGET_OVERRIDE_OPTIONS
;
4511 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4512 SUB3TARGET_OVERRIDE_OPTIONS
;
4515 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4516 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
4518 rs6000_always_hint
= (rs6000_tune
!= PROCESSOR_POWER4
4519 && rs6000_tune
!= PROCESSOR_POWER5
4520 && rs6000_tune
!= PROCESSOR_POWER6
4521 && rs6000_tune
!= PROCESSOR_POWER7
4522 && rs6000_tune
!= PROCESSOR_POWER8
4523 && rs6000_tune
!= PROCESSOR_POWER9
4524 && rs6000_tune
!= PROCESSOR_PPCA2
4525 && rs6000_tune
!= PROCESSOR_CELL
4526 && rs6000_tune
!= PROCESSOR_PPC476
);
4527 rs6000_sched_groups
= (rs6000_tune
== PROCESSOR_POWER4
4528 || rs6000_tune
== PROCESSOR_POWER5
4529 || rs6000_tune
== PROCESSOR_POWER7
4530 || rs6000_tune
== PROCESSOR_POWER8
);
4531 rs6000_align_branch_targets
= (rs6000_tune
== PROCESSOR_POWER4
4532 || rs6000_tune
== PROCESSOR_POWER5
4533 || rs6000_tune
== PROCESSOR_POWER6
4534 || rs6000_tune
== PROCESSOR_POWER7
4535 || rs6000_tune
== PROCESSOR_POWER8
4536 || rs6000_tune
== PROCESSOR_POWER9
4537 || rs6000_tune
== PROCESSOR_PPCE500MC
4538 || rs6000_tune
== PROCESSOR_PPCE500MC64
4539 || rs6000_tune
== PROCESSOR_PPCE5500
4540 || rs6000_tune
== PROCESSOR_PPCE6500
);
4542 /* Allow debug switches to override the above settings. These are set to -1
4543 in rs6000.opt to indicate the user hasn't directly set the switch. */
4544 if (TARGET_ALWAYS_HINT
>= 0)
4545 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
4547 if (TARGET_SCHED_GROUPS
>= 0)
4548 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
4550 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
4551 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
4553 rs6000_sched_restricted_insns_priority
4554 = (rs6000_sched_groups
? 1 : 0);
4556 /* Handle -msched-costly-dep option. */
4557 rs6000_sched_costly_dep
4558 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
4560 if (rs6000_sched_costly_dep_str
)
4562 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
4563 rs6000_sched_costly_dep
= no_dep_costly
;
4564 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
4565 rs6000_sched_costly_dep
= all_deps_costly
;
4566 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
4567 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
4568 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
4569 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
4571 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
4572 atoi (rs6000_sched_costly_dep_str
));
4575 /* Handle -minsert-sched-nops option. */
4576 rs6000_sched_insert_nops
4577 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
4579 if (rs6000_sched_insert_nops_str
)
4581 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
4582 rs6000_sched_insert_nops
= sched_finish_none
;
4583 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
4584 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
4585 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
4586 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
4588 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
4589 atoi (rs6000_sched_insert_nops_str
));
4592 /* Handle stack protector */
4593 if (!global_options_set
.x_rs6000_stack_protector_guard
)
4594 #ifdef TARGET_THREAD_SSP_OFFSET
4595 rs6000_stack_protector_guard
= SSP_TLS
;
4597 rs6000_stack_protector_guard
= SSP_GLOBAL
;
4600 #ifdef TARGET_THREAD_SSP_OFFSET
4601 rs6000_stack_protector_guard_offset
= TARGET_THREAD_SSP_OFFSET
;
4602 rs6000_stack_protector_guard_reg
= TARGET_64BIT
? 13 : 2;
4605 if (global_options_set
.x_rs6000_stack_protector_guard_offset_str
)
4608 const char *str
= rs6000_stack_protector_guard_offset_str
;
4611 long offset
= strtol (str
, &endp
, 0);
4612 if (!*str
|| *endp
|| errno
)
4613 error ("%qs is not a valid number in %qs", str
,
4614 "-mstack-protector-guard-offset=");
4616 if (!IN_RANGE (offset
, -0x8000, 0x7fff)
4617 || (TARGET_64BIT
&& (offset
& 3)))
4618 error ("%qs is not a valid offset in %qs", str
,
4619 "-mstack-protector-guard-offset=");
4621 rs6000_stack_protector_guard_offset
= offset
;
4624 if (global_options_set
.x_rs6000_stack_protector_guard_reg_str
)
4626 const char *str
= rs6000_stack_protector_guard_reg_str
;
4627 int reg
= decode_reg_name (str
);
4629 if (!IN_RANGE (reg
, 1, 31))
4630 error ("%qs is not a valid base register in %qs", str
,
4631 "-mstack-protector-guard-reg=");
4633 rs6000_stack_protector_guard_reg
= reg
;
4636 if (rs6000_stack_protector_guard
== SSP_TLS
4637 && !IN_RANGE (rs6000_stack_protector_guard_reg
, 1, 31))
4638 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4642 #ifdef TARGET_REGNAMES
4643 /* If the user desires alternate register names, copy in the
4644 alternate names now. */
4645 if (TARGET_REGNAMES
)
4646 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
4649 /* Set aix_struct_return last, after the ABI is determined.
4650 If -maix-struct-return or -msvr4-struct-return was explicitly
4651 used, don't override with the ABI default. */
4652 if (!global_options_set
.x_aix_struct_return
)
4653 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
4656 /* IBM XL compiler defaults to unsigned bitfields. */
4657 if (TARGET_XL_COMPAT
)
4658 flag_signed_bitfields
= 0;
4661 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
4662 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
4664 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
4666 /* We can only guarantee the availability of DI pseudo-ops when
4667 assembling for 64-bit targets. */
4670 targetm
.asm_out
.aligned_op
.di
= NULL
;
4671 targetm
.asm_out
.unaligned_op
.di
= NULL
;
4675 /* Set branch target alignment, if not optimizing for size. */
4678 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4679 aligned 8byte to avoid misprediction by the branch predictor. */
4680 if (rs6000_tune
== PROCESSOR_TITAN
4681 || rs6000_tune
== PROCESSOR_CELL
)
4683 if (flag_align_functions
&& !str_align_functions
)
4684 str_align_functions
= "8";
4685 if (flag_align_jumps
&& !str_align_jumps
)
4686 str_align_jumps
= "8";
4687 if (flag_align_loops
&& !str_align_loops
)
4688 str_align_loops
= "8";
4690 if (rs6000_align_branch_targets
)
4692 if (flag_align_functions
&& !str_align_functions
)
4693 str_align_functions
= "16";
4694 if (flag_align_jumps
&& !str_align_jumps
)
4695 str_align_jumps
= "16";
4696 if (flag_align_loops
&& !str_align_loops
)
4698 can_override_loop_align
= 1;
4699 str_align_loops
= "16";
4703 if (flag_align_jumps
&& !str_align_jumps
)
4704 str_align_jumps
= "16";
4705 if (flag_align_loops
&& !str_align_loops
)
4706 str_align_loops
= "16";
4709 /* Arrange to save and restore machine status around nested functions. */
4710 init_machine_status
= rs6000_init_machine_status
;
4712 /* We should always be splitting complex arguments, but we can't break
4713 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4714 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
4715 targetm
.calls
.split_complex_arg
= NULL
;
4717 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4718 if (DEFAULT_ABI
== ABI_AIX
)
4719 targetm
.calls
.custom_function_descriptors
= 0;
4722 /* Initialize rs6000_cost with the appropriate target costs. */
4724 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
4726 switch (rs6000_tune
)
4728 case PROCESSOR_RS64A
:
4729 rs6000_cost
= &rs64a_cost
;
4732 case PROCESSOR_MPCCORE
:
4733 rs6000_cost
= &mpccore_cost
;
4736 case PROCESSOR_PPC403
:
4737 rs6000_cost
= &ppc403_cost
;
4740 case PROCESSOR_PPC405
:
4741 rs6000_cost
= &ppc405_cost
;
4744 case PROCESSOR_PPC440
:
4745 rs6000_cost
= &ppc440_cost
;
4748 case PROCESSOR_PPC476
:
4749 rs6000_cost
= &ppc476_cost
;
4752 case PROCESSOR_PPC601
:
4753 rs6000_cost
= &ppc601_cost
;
4756 case PROCESSOR_PPC603
:
4757 rs6000_cost
= &ppc603_cost
;
4760 case PROCESSOR_PPC604
:
4761 rs6000_cost
= &ppc604_cost
;
4764 case PROCESSOR_PPC604e
:
4765 rs6000_cost
= &ppc604e_cost
;
4768 case PROCESSOR_PPC620
:
4769 rs6000_cost
= &ppc620_cost
;
4772 case PROCESSOR_PPC630
:
4773 rs6000_cost
= &ppc630_cost
;
4776 case PROCESSOR_CELL
:
4777 rs6000_cost
= &ppccell_cost
;
4780 case PROCESSOR_PPC750
:
4781 case PROCESSOR_PPC7400
:
4782 rs6000_cost
= &ppc750_cost
;
4785 case PROCESSOR_PPC7450
:
4786 rs6000_cost
= &ppc7450_cost
;
4789 case PROCESSOR_PPC8540
:
4790 case PROCESSOR_PPC8548
:
4791 rs6000_cost
= &ppc8540_cost
;
4794 case PROCESSOR_PPCE300C2
:
4795 case PROCESSOR_PPCE300C3
:
4796 rs6000_cost
= &ppce300c2c3_cost
;
4799 case PROCESSOR_PPCE500MC
:
4800 rs6000_cost
= &ppce500mc_cost
;
4803 case PROCESSOR_PPCE500MC64
:
4804 rs6000_cost
= &ppce500mc64_cost
;
4807 case PROCESSOR_PPCE5500
:
4808 rs6000_cost
= &ppce5500_cost
;
4811 case PROCESSOR_PPCE6500
:
4812 rs6000_cost
= &ppce6500_cost
;
4815 case PROCESSOR_TITAN
:
4816 rs6000_cost
= &titan_cost
;
4819 case PROCESSOR_POWER4
:
4820 case PROCESSOR_POWER5
:
4821 rs6000_cost
= &power4_cost
;
4824 case PROCESSOR_POWER6
:
4825 rs6000_cost
= &power6_cost
;
4828 case PROCESSOR_POWER7
:
4829 rs6000_cost
= &power7_cost
;
4832 case PROCESSOR_POWER8
:
4833 rs6000_cost
= &power8_cost
;
4836 case PROCESSOR_POWER9
:
4837 rs6000_cost
= &power9_cost
;
4840 case PROCESSOR_PPCA2
:
4841 rs6000_cost
= &ppca2_cost
;
4850 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
4851 rs6000_cost
->simultaneous_prefetches
,
4852 global_options
.x_param_values
,
4853 global_options_set
.x_param_values
);
4854 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
4855 global_options
.x_param_values
,
4856 global_options_set
.x_param_values
);
4857 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
4858 rs6000_cost
->cache_line_size
,
4859 global_options
.x_param_values
,
4860 global_options_set
.x_param_values
);
4861 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
4862 global_options
.x_param_values
,
4863 global_options_set
.x_param_values
);
4865 /* Increase loop peeling limits based on performance analysis. */
4866 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
4867 global_options
.x_param_values
,
4868 global_options_set
.x_param_values
);
4869 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
4870 global_options
.x_param_values
,
4871 global_options_set
.x_param_values
);
4873 /* Use the 'model' -fsched-pressure algorithm by default. */
4874 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
,
4875 SCHED_PRESSURE_MODEL
,
4876 global_options
.x_param_values
,
4877 global_options_set
.x_param_values
);
4879 /* If using typedef char *va_list, signal that
4880 __builtin_va_start (&ap, 0) can be optimized to
4881 ap = __builtin_next_arg (0). */
4882 if (DEFAULT_ABI
!= ABI_V4
)
4883 targetm
.expand_builtin_va_start
= NULL
;
4886 /* If not explicitly specified via option, decide whether to generate indexed
4887 load/store instructions. A value of -1 indicates that the
4888 initial value of this variable has not been overwritten. During
4889 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4890 if (TARGET_AVOID_XFORM
== -1)
4891 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4892 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4893 need indexed accesses and the type used is the scalar type of the element
4894 being loaded or stored. */
4895 TARGET_AVOID_XFORM
= (rs6000_tune
== PROCESSOR_POWER6
&& TARGET_CMPB
4896 && !TARGET_ALTIVEC
);
4898 /* Set the -mrecip options. */
4899 if (rs6000_recip_name
)
4901 char *p
= ASTRDUP (rs6000_recip_name
);
4903 unsigned int mask
, i
;
4906 while ((q
= strtok (p
, ",")) != NULL
)
4917 if (!strcmp (q
, "default"))
4918 mask
= ((TARGET_RECIP_PRECISION
)
4919 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
4922 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
4923 if (!strcmp (q
, recip_options
[i
].string
))
4925 mask
= recip_options
[i
].mask
;
4929 if (i
== ARRAY_SIZE (recip_options
))
4931 error ("unknown option for %<%s=%s%>", "-mrecip", q
);
4939 rs6000_recip_control
&= ~mask
;
4941 rs6000_recip_control
|= mask
;
4945 /* Set the builtin mask of the various options used that could affect which
4946 builtins were used. In the past we used target_flags, but we've run out
4947 of bits, and some options are no longer in target_flags. */
4948 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4949 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4950 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
4951 rs6000_builtin_mask
);
4953 /* Initialize all of the registers. */
4954 rs6000_init_hard_regno_mode_ok (global_init_p
);
4956 /* Save the initial options in case the user does function specific options */
4958 target_option_default_node
= target_option_current_node
4959 = build_target_option_node (&global_options
);
4961 /* If not explicitly specified via option, decide whether to generate the
4962 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4963 if (TARGET_LINK_STACK
== -1)
4964 SET_TARGET_LINK_STACK (rs6000_tune
== PROCESSOR_PPC476
&& flag_pic
);
4966 /* Deprecate use of -mno-speculate-indirect-jumps. */
4967 if (!rs6000_speculate_indirect_jumps
)
4968 warning (0, "%qs is deprecated and not recommended in any circumstances",
4969 "-mno-speculate-indirect-jumps");
4974 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4975 define the target cpu type. */
4978 rs6000_option_override (void)
4980 (void) rs6000_option_override_internal (true);
4984 /* Implement targetm.vectorize.builtin_mask_for_load. */
4986 rs6000_builtin_mask_for_load (void)
4988 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4989 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
4990 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
4991 return altivec_builtin_mask_for_load
;
4996 /* Implement LOOP_ALIGN. */
4998 rs6000_loop_align (rtx label
)
5003 /* Don't override loop alignment if -falign-loops was specified. */
5004 if (!can_override_loop_align
)
5007 bb
= BLOCK_FOR_INSN (label
);
5008 ninsns
= num_loop_insns(bb
->loop_father
);
5010 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5011 if (ninsns
> 4 && ninsns
<= 8
5012 && (rs6000_tune
== PROCESSOR_POWER4
5013 || rs6000_tune
== PROCESSOR_POWER5
5014 || rs6000_tune
== PROCESSOR_POWER6
5015 || rs6000_tune
== PROCESSOR_POWER7
5016 || rs6000_tune
== PROCESSOR_POWER8
))
5017 return align_flags (5);
5022 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5023 after applying N number of iterations. This routine does not determine
5024 how may iterations are required to reach desired alignment. */
5027 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
5034 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
5037 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
5047 /* Assuming that all other types are naturally aligned. CHECKME! */
5052 /* Return true if the vector misalignment factor is supported by the
5055 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
5062 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5065 /* Return if movmisalign pattern is not supported for this mode. */
5066 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
5069 if (misalignment
== -1)
5071 /* Misalignment factor is unknown at compile time but we know
5072 it's word aligned. */
5073 if (rs6000_vector_alignment_reachable (type
, is_packed
))
5075 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
5077 if (element_size
== 64 || element_size
== 32)
5084 /* VSX supports word-aligned vector. */
5085 if (misalignment
% 4 == 0)
5091 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5093 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
5094 tree vectype
, int misalign
)
5099 switch (type_of_cost
)
5109 case cond_branch_not_taken
:
5118 case vec_promote_demote
:
5124 case cond_branch_taken
:
5127 case unaligned_load
:
5128 case vector_gather_load
:
5129 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5132 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5134 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5136 /* Double word aligned. */
5144 /* Double word aligned. */
5148 /* Unknown misalignment. */
5161 /* Misaligned loads are not supported. */
5166 case unaligned_store
:
5167 case vector_scatter_store
:
5168 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5171 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5173 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5175 /* Double word aligned. */
5183 /* Double word aligned. */
5187 /* Unknown misalignment. */
5200 /* Misaligned stores are not supported. */
5206 /* This is a rough approximation assuming non-constant elements
5207 constructed into a vector via element insertion. FIXME:
5208 vec_construct is not granular enough for uniformly good
5209 decisions. If the initialization is a splat, this is
5210 cheaper than we estimate. Improve this someday. */
5211 elem_type
= TREE_TYPE (vectype
);
5212 /* 32-bit vectors loaded into registers are stored as double
5213 precision, so we need 2 permutes, 2 converts, and 1 merge
5214 to construct a vector of short floats from them. */
5215 if (SCALAR_FLOAT_TYPE_P (elem_type
)
5216 && TYPE_PRECISION (elem_type
) == 32)
5218 /* On POWER9, integer vector types are built up in GPRs and then
5219 use a direct move (2 cycles). For POWER8 this is even worse,
5220 as we need two direct moves and a merge, and the direct moves
5222 else if (INTEGRAL_TYPE_P (elem_type
))
5224 if (TARGET_P9_VECTOR
)
5225 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 2;
5227 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 5;
5230 /* V2DFmode doesn't need a direct move. */
5238 /* Implement targetm.vectorize.preferred_simd_mode. */
5241 rs6000_preferred_simd_mode (scalar_mode mode
)
5250 if (TARGET_ALTIVEC
|| TARGET_VSX
)
5270 typedef struct _rs6000_cost_data
5272 struct loop
*loop_info
;
5276 /* Test for likely overcommitment of vector hardware resources. If a
5277 loop iteration is relatively large, and too large a percentage of
5278 instructions in the loop are vectorized, the cost model may not
5279 adequately reflect delays from unavailable vector resources.
5280 Penalize the loop body cost for this case. */
5283 rs6000_density_test (rs6000_cost_data
*data
)
5285 const int DENSITY_PCT_THRESHOLD
= 85;
5286 const int DENSITY_SIZE_THRESHOLD
= 70;
5287 const int DENSITY_PENALTY
= 10;
5288 struct loop
*loop
= data
->loop_info
;
5289 basic_block
*bbs
= get_loop_body (loop
);
5290 int nbbs
= loop
->num_nodes
;
5291 loop_vec_info loop_vinfo
= loop_vec_info_for_loop (data
->loop_info
);
5292 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
5295 for (i
= 0; i
< nbbs
; i
++)
5297 basic_block bb
= bbs
[i
];
5298 gimple_stmt_iterator gsi
;
5300 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
5302 gimple
*stmt
= gsi_stmt (gsi
);
5303 stmt_vec_info stmt_info
= loop_vinfo
->lookup_stmt (stmt
);
5305 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
5306 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
5312 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
5314 if (density_pct
> DENSITY_PCT_THRESHOLD
5315 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
5317 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
5318 if (dump_enabled_p ())
5319 dump_printf_loc (MSG_NOTE
, vect_location
,
5320 "density %d%%, cost %d exceeds threshold, penalizing "
5321 "loop body cost by %d%%", density_pct
,
5322 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
5326 /* Implement targetm.vectorize.init_cost. */
5328 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5329 instruction is needed by the vectorization. */
5330 static bool rs6000_vect_nonmem
;
5333 rs6000_init_cost (struct loop
*loop_info
)
5335 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
5336 data
->loop_info
= loop_info
;
5337 data
->cost
[vect_prologue
] = 0;
5338 data
->cost
[vect_body
] = 0;
5339 data
->cost
[vect_epilogue
] = 0;
5340 rs6000_vect_nonmem
= false;
5344 /* Implement targetm.vectorize.add_stmt_cost. */
5347 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
5348 struct _stmt_vec_info
*stmt_info
, int misalign
,
5349 enum vect_cost_model_location where
)
5351 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5352 unsigned retval
= 0;
5354 if (flag_vect_cost_model
)
5356 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
5357 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
5359 /* Statements in an inner loop relative to the loop being
5360 vectorized are weighted more heavily. The value here is
5361 arbitrary and could potentially be improved with analysis. */
5362 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
5363 count
*= 50; /* FIXME. */
5365 retval
= (unsigned) (count
* stmt_cost
);
5366 cost_data
->cost
[where
] += retval
;
5368 /* Check whether we're doing something other than just a copy loop.
5369 Not all such loops may be profitably vectorized; see
5370 rs6000_finish_cost. */
5371 if ((kind
== vec_to_scalar
|| kind
== vec_perm
5372 || kind
== vec_promote_demote
|| kind
== vec_construct
5373 || kind
== scalar_to_vec
)
5374 || (where
== vect_body
&& kind
== vector_stmt
))
5375 rs6000_vect_nonmem
= true;
5381 /* Implement targetm.vectorize.finish_cost. */
5384 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
5385 unsigned *body_cost
, unsigned *epilogue_cost
)
5387 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5389 if (cost_data
->loop_info
)
5390 rs6000_density_test (cost_data
);
5392 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5393 that require versioning for any reason. The vectorization is at
5394 best a wash inside the loop, and the versioning checks make
5395 profitability highly unlikely and potentially quite harmful. */
5396 if (cost_data
->loop_info
)
5398 loop_vec_info vec_info
= loop_vec_info_for_loop (cost_data
->loop_info
);
5399 if (!rs6000_vect_nonmem
5400 && LOOP_VINFO_VECT_FACTOR (vec_info
) == 2
5401 && LOOP_REQUIRES_VERSIONING (vec_info
))
5402 cost_data
->cost
[vect_body
] += 10000;
5405 *prologue_cost
= cost_data
->cost
[vect_prologue
];
5406 *body_cost
= cost_data
->cost
[vect_body
];
5407 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
5410 /* Implement targetm.vectorize.destroy_cost_data. */
5413 rs6000_destroy_cost_data (void *data
)
5418 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5419 library with vectorized intrinsics. */
5422 rs6000_builtin_vectorized_libmass (combined_fn fn
, tree type_out
,
5426 const char *suffix
= NULL
;
5427 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
5430 machine_mode el_mode
, in_mode
;
5433 /* Libmass is suitable for unsafe math only as it does not correctly support
5434 parts of IEEE with the required precision such as denormals. Only support
5435 it if we have VSX to use the simd d2 or f4 functions.
5436 XXX: Add variable length support. */
5437 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
5440 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5441 n
= TYPE_VECTOR_SUBPARTS (type_out
);
5442 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5443 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5444 if (el_mode
!= in_mode
5480 if (el_mode
== DFmode
&& n
== 2)
5482 bdecl
= mathfn_built_in (double_type_node
, fn
);
5483 suffix
= "d2"; /* pow -> powd2 */
5485 else if (el_mode
== SFmode
&& n
== 4)
5487 bdecl
= mathfn_built_in (float_type_node
, fn
);
5488 suffix
= "4"; /* powf -> powf4 */
5500 gcc_assert (suffix
!= NULL
);
5501 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
5505 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
5506 strcat (name
, suffix
);
5509 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
5510 else if (n_args
== 2)
5511 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
5515 /* Build a function declaration for the vectorized function. */
5516 new_fndecl
= build_decl (BUILTINS_LOCATION
,
5517 FUNCTION_DECL
, get_identifier (name
), fntype
);
5518 TREE_PUBLIC (new_fndecl
) = 1;
5519 DECL_EXTERNAL (new_fndecl
) = 1;
5520 DECL_IS_NOVOPS (new_fndecl
) = 1;
5521 TREE_READONLY (new_fndecl
) = 1;
5526 /* Returns a function decl for a vectorized version of the builtin function
5527 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5528 if it is not available. */
5531 rs6000_builtin_vectorized_function (unsigned int fn
, tree type_out
,
5534 machine_mode in_mode
, out_mode
;
5537 if (TARGET_DEBUG_BUILTIN
)
5538 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5539 combined_fn_name (combined_fn (fn
)),
5540 GET_MODE_NAME (TYPE_MODE (type_out
)),
5541 GET_MODE_NAME (TYPE_MODE (type_in
)));
5543 if (TREE_CODE (type_out
) != VECTOR_TYPE
5544 || TREE_CODE (type_in
) != VECTOR_TYPE
)
5547 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5548 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5549 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5550 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5555 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5556 && out_mode
== DFmode
&& out_n
== 2
5557 && in_mode
== DFmode
&& in_n
== 2)
5558 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
5559 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5560 && out_mode
== SFmode
&& out_n
== 4
5561 && in_mode
== SFmode
&& in_n
== 4)
5562 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
5563 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5564 && out_mode
== SFmode
&& out_n
== 4
5565 && in_mode
== SFmode
&& in_n
== 4)
5566 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
5569 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5570 && out_mode
== DFmode
&& out_n
== 2
5571 && in_mode
== DFmode
&& in_n
== 2)
5572 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
5573 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5574 && out_mode
== SFmode
&& out_n
== 4
5575 && in_mode
== SFmode
&& in_n
== 4)
5576 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
5577 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5578 && out_mode
== SFmode
&& out_n
== 4
5579 && in_mode
== SFmode
&& in_n
== 4)
5580 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
5583 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5584 && out_mode
== DFmode
&& out_n
== 2
5585 && in_mode
== DFmode
&& in_n
== 2)
5586 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
5587 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5588 && out_mode
== SFmode
&& out_n
== 4
5589 && in_mode
== SFmode
&& in_n
== 4)
5590 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
5591 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5592 && out_mode
== SFmode
&& out_n
== 4
5593 && in_mode
== SFmode
&& in_n
== 4)
5594 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
5597 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5598 && out_mode
== DFmode
&& out_n
== 2
5599 && in_mode
== DFmode
&& in_n
== 2)
5600 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
5601 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5602 && out_mode
== SFmode
&& out_n
== 4
5603 && in_mode
== SFmode
&& in_n
== 4)
5604 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
5605 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5606 && out_mode
== SFmode
&& out_n
== 4
5607 && in_mode
== SFmode
&& in_n
== 4)
5608 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5611 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5612 && out_mode
== DFmode
&& out_n
== 2
5613 && in_mode
== DFmode
&& in_n
== 2)
5614 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5615 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5616 && out_mode
== SFmode
&& out_n
== 4
5617 && in_mode
== SFmode
&& in_n
== 4)
5618 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5619 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5620 && out_mode
== SFmode
&& out_n
== 4
5621 && in_mode
== SFmode
&& in_n
== 4)
5622 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5625 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5626 && flag_unsafe_math_optimizations
5627 && out_mode
== DFmode
&& out_n
== 2
5628 && in_mode
== DFmode
&& in_n
== 2)
5629 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5630 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5631 && flag_unsafe_math_optimizations
5632 && out_mode
== SFmode
&& out_n
== 4
5633 && in_mode
== SFmode
&& in_n
== 4)
5634 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
5637 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5638 && !flag_trapping_math
5639 && out_mode
== DFmode
&& out_n
== 2
5640 && in_mode
== DFmode
&& in_n
== 2)
5641 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
5642 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5643 && !flag_trapping_math
5644 && out_mode
== SFmode
&& out_n
== 4
5645 && in_mode
== SFmode
&& in_n
== 4)
5646 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
5652 /* Generate calls to libmass if appropriate. */
5653 if (rs6000_veclib_handler
)
5654 return rs6000_veclib_handler (combined_fn (fn
), type_out
, type_in
);
5659 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5662 rs6000_builtin_md_vectorized_function (tree fndecl
, tree type_out
,
5665 machine_mode in_mode
, out_mode
;
5668 if (TARGET_DEBUG_BUILTIN
)
5669 fprintf (stderr
, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5670 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
5671 GET_MODE_NAME (TYPE_MODE (type_out
)),
5672 GET_MODE_NAME (TYPE_MODE (type_in
)));
5674 if (TREE_CODE (type_out
) != VECTOR_TYPE
5675 || TREE_CODE (type_in
) != VECTOR_TYPE
)
5678 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5679 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5680 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5681 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5683 enum rs6000_builtins fn
5684 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
5687 case RS6000_BUILTIN_RSQRTF
:
5688 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5689 && out_mode
== SFmode
&& out_n
== 4
5690 && in_mode
== SFmode
&& in_n
== 4)
5691 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
5693 case RS6000_BUILTIN_RSQRT
:
5694 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5695 && out_mode
== DFmode
&& out_n
== 2
5696 && in_mode
== DFmode
&& in_n
== 2)
5697 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
5699 case RS6000_BUILTIN_RECIPF
:
5700 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5701 && out_mode
== SFmode
&& out_n
== 4
5702 && in_mode
== SFmode
&& in_n
== 4)
5703 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
5705 case RS6000_BUILTIN_RECIP
:
5706 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5707 && out_mode
== DFmode
&& out_n
== 2
5708 && in_mode
== DFmode
&& in_n
== 2)
5709 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
5717 /* Default CPU string for rs6000*_file_start functions. */
5718 static const char *rs6000_default_cpu
;
5720 /* Do anything needed at the start of the asm file. */
5723 rs6000_file_start (void)
5726 const char *start
= buffer
;
5727 FILE *file
= asm_out_file
;
5729 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
5731 default_file_start ();
5733 if (flag_verbose_asm
)
5735 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
5737 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
5739 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
5743 if (global_options_set
.x_rs6000_cpu_index
)
5745 fprintf (file
, "%s -mcpu=%s", start
,
5746 processor_target_table
[rs6000_cpu_index
].name
);
5750 if (global_options_set
.x_rs6000_tune_index
)
5752 fprintf (file
, "%s -mtune=%s", start
,
5753 processor_target_table
[rs6000_tune_index
].name
);
5757 if (PPC405_ERRATUM77
)
5759 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
5763 #ifdef USING_ELFOS_H
5764 switch (rs6000_sdata
)
5766 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
5767 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
5768 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
5769 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
5772 if (rs6000_sdata
&& g_switch_value
)
5774 fprintf (file
, "%s -G %d", start
,
5784 #ifdef USING_ELFOS_H
5785 if (!(rs6000_default_cpu
&& rs6000_default_cpu
[0])
5786 && !global_options_set
.x_rs6000_cpu_index
)
5788 fputs ("\t.machine ", asm_out_file
);
5789 if ((rs6000_isa_flags
& OPTION_MASK_MODULO
) != 0)
5790 fputs ("power9\n", asm_out_file
);
5791 else if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
5792 fputs ("power8\n", asm_out_file
);
5793 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
5794 fputs ("power7\n", asm_out_file
);
5795 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
5796 fputs ("power6\n", asm_out_file
);
5797 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
5798 fputs ("power5\n", asm_out_file
);
5799 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
5800 fputs ("power4\n", asm_out_file
);
5801 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
5802 fputs ("ppc64\n", asm_out_file
);
5804 fputs ("ppc\n", asm_out_file
);
5808 if (DEFAULT_ABI
== ABI_ELFv2
)
5809 fprintf (file
, "\t.abiversion 2\n");
5813 /* Return nonzero if this function is known to have a null epilogue. */
5816 direct_return (void)
5818 if (reload_completed
)
5820 rs6000_stack_t
*info
= rs6000_stack_info ();
5822 if (info
->first_gp_reg_save
== 32
5823 && info
->first_fp_reg_save
== 64
5824 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
5825 && ! info
->lr_save_p
5826 && ! info
->cr_save_p
5827 && info
->vrsave_size
== 0
5835 /* Return the number of instructions it takes to form a constant in an
5836 integer register. */
5839 num_insns_constant_wide (HOST_WIDE_INT value
)
5841 /* signed constant loadable with addi */
5842 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
5845 /* constant loadable with addis */
5846 else if ((value
& 0xffff) == 0
5847 && (value
>> 31 == -1 || value
>> 31 == 0))
5850 else if (TARGET_POWERPC64
)
5852 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
5853 HOST_WIDE_INT high
= value
>> 31;
5855 if (high
== 0 || high
== -1)
5861 return num_insns_constant_wide (high
) + 1;
5863 return num_insns_constant_wide (low
) + 1;
5865 return (num_insns_constant_wide (high
)
5866 + num_insns_constant_wide (low
) + 1);
5874 num_insns_constant (rtx op
, machine_mode mode
)
5876 HOST_WIDE_INT low
, high
;
5878 switch (GET_CODE (op
))
5881 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
5882 && rs6000_is_valid_and_mask (op
, mode
))
5885 return num_insns_constant_wide (INTVAL (op
));
5887 case CONST_WIDE_INT
:
5890 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
5891 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
5892 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
5897 if (mode
== SFmode
|| mode
== SDmode
)
5901 if (DECIMAL_FLOAT_MODE_P (mode
))
5902 REAL_VALUE_TO_TARGET_DECIMAL32
5903 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5905 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5906 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
5910 if (DECIMAL_FLOAT_MODE_P (mode
))
5911 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5913 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5914 high
= l
[WORDS_BIG_ENDIAN
== 0];
5915 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5918 return (num_insns_constant_wide (low
)
5919 + num_insns_constant_wide (high
));
5922 if ((high
== 0 && low
>= 0)
5923 || (high
== -1 && low
< 0))
5924 return num_insns_constant_wide (low
);
5926 else if (rs6000_is_valid_and_mask (op
, mode
))
5930 return num_insns_constant_wide (high
) + 1;
5933 return (num_insns_constant_wide (high
)
5934 + num_insns_constant_wide (low
) + 1);
5942 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5943 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5944 corresponding element of the vector, but for V4SFmode, the
5945 corresponding "float" is interpreted as an SImode integer. */
5948 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5952 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5953 gcc_assert (GET_MODE (op
) != V2DImode
5954 && GET_MODE (op
) != V2DFmode
);
5956 tmp
= CONST_VECTOR_ELT (op
, elt
);
5957 if (GET_MODE (op
) == V4SFmode
)
5958 tmp
= gen_lowpart (SImode
, tmp
);
5959 return INTVAL (tmp
);
5962 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5963 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5964 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5965 all items are set to the same value and contain COPIES replicas of the
5966 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5967 operand and the others are set to the value of the operand's msb. */
5970 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5972 machine_mode mode
= GET_MODE (op
);
5973 machine_mode inner
= GET_MODE_INNER (mode
);
5981 HOST_WIDE_INT splat_val
;
5982 HOST_WIDE_INT msb_val
;
5984 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5987 nunits
= GET_MODE_NUNITS (mode
);
5988 bitsize
= GET_MODE_BITSIZE (inner
);
5989 mask
= GET_MODE_MASK (inner
);
5991 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5993 msb_val
= val
>= 0 ? 0 : -1;
5995 /* Construct the value to be splatted, if possible. If not, return 0. */
5996 for (i
= 2; i
<= copies
; i
*= 2)
5998 HOST_WIDE_INT small_val
;
6000 small_val
= splat_val
>> bitsize
;
6002 if (splat_val
!= ((HOST_WIDE_INT
)
6003 ((unsigned HOST_WIDE_INT
) small_val
<< bitsize
)
6004 | (small_val
& mask
)))
6006 splat_val
= small_val
;
6009 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6010 if (EASY_VECTOR_15 (splat_val
))
6013 /* Also check if we can splat, and then add the result to itself. Do so if
6014 the value is positive, of if the splat instruction is using OP's mode;
6015 for splat_val < 0, the splat and the add should use the same mode. */
6016 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
6017 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
6020 /* Also check if are loading up the most significant bit which can be done by
6021 loading up -1 and shifting the value left by -1. */
6022 else if (EASY_VECTOR_MSB (splat_val
, inner
))
6028 /* Check if VAL is present in every STEP-th element, and the
6029 other elements are filled with its most significant bit. */
6030 for (i
= 1; i
< nunits
; ++i
)
6032 HOST_WIDE_INT desired_val
;
6033 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
6034 if ((i
& (step
- 1)) == 0)
6037 desired_val
= msb_val
;
6039 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
6046 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6047 instruction, filling in the bottom elements with 0 or -1.
6049 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6050 for the number of zeroes to shift in, or negative for the number of 0xff
6053 OP is a CONST_VECTOR. */
6056 vspltis_shifted (rtx op
)
6058 machine_mode mode
= GET_MODE (op
);
6059 machine_mode inner
= GET_MODE_INNER (mode
);
6067 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
)
6070 /* We need to create pseudo registers to do the shift, so don't recognize
6071 shift vector constants after reload. */
6072 if (!can_create_pseudo_p ())
6075 nunits
= GET_MODE_NUNITS (mode
);
6076 mask
= GET_MODE_MASK (inner
);
6078 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? 0 : nunits
- 1);
6080 /* Check if the value can really be the operand of a vspltis[bhw]. */
6081 if (EASY_VECTOR_15 (val
))
6084 /* Also check if we are loading up the most significant bit which can be done
6085 by loading up -1 and shifting the value left by -1. */
6086 else if (EASY_VECTOR_MSB (val
, inner
))
6092 /* Check if VAL is present in every STEP-th element until we find elements
6093 that are 0 or all 1 bits. */
6094 for (i
= 1; i
< nunits
; ++i
)
6096 unsigned elt
= BYTES_BIG_ENDIAN
? i
: nunits
- 1 - i
;
6097 HOST_WIDE_INT elt_val
= const_vector_elt_as_int (op
, elt
);
6099 /* If the value isn't the splat value, check for the remaining elements
6105 for (j
= i
+1; j
< nunits
; ++j
)
6107 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6108 if (const_vector_elt_as_int (op
, elt2
) != 0)
6112 return (nunits
- i
) * GET_MODE_SIZE (inner
);
6115 else if ((elt_val
& mask
) == mask
)
6117 for (j
= i
+1; j
< nunits
; ++j
)
6119 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6120 if ((const_vector_elt_as_int (op
, elt2
) & mask
) != mask
)
6124 return -((nunits
- i
) * GET_MODE_SIZE (inner
));
6132 /* If all elements are equal, we don't need to do VLSDOI. */
6137 /* Return true if OP is of the given MODE and can be synthesized
6138 with a vspltisb, vspltish or vspltisw. */
6141 easy_altivec_constant (rtx op
, machine_mode mode
)
6143 unsigned step
, copies
;
6145 if (mode
== VOIDmode
)
6146 mode
= GET_MODE (op
);
6147 else if (mode
!= GET_MODE (op
))
6150 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6152 if (mode
== V2DFmode
)
6153 return zero_constant (op
, mode
);
6155 else if (mode
== V2DImode
)
6157 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
6158 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
6161 if (zero_constant (op
, mode
))
6164 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
6165 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
6171 /* V1TImode is a special container for TImode. Ignore for now. */
6172 else if (mode
== V1TImode
)
6175 /* Start with a vspltisw. */
6176 step
= GET_MODE_NUNITS (mode
) / 4;
6179 if (vspltis_constant (op
, step
, copies
))
6182 /* Then try with a vspltish. */
6188 if (vspltis_constant (op
, step
, copies
))
6191 /* And finally a vspltisb. */
6197 if (vspltis_constant (op
, step
, copies
))
6200 if (vspltis_shifted (op
) != 0)
6206 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6207 result is OP. Abort if it is not possible. */
6210 gen_easy_altivec_constant (rtx op
)
6212 machine_mode mode
= GET_MODE (op
);
6213 int nunits
= GET_MODE_NUNITS (mode
);
6214 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6215 unsigned step
= nunits
/ 4;
6216 unsigned copies
= 1;
6218 /* Start with a vspltisw. */
6219 if (vspltis_constant (op
, step
, copies
))
6220 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
6222 /* Then try with a vspltish. */
6228 if (vspltis_constant (op
, step
, copies
))
6229 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
6231 /* And finally a vspltisb. */
6237 if (vspltis_constant (op
, step
, copies
))
6238 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
6243 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6244 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6246 Return the number of instructions needed (1 or 2) into the address pointed
6249 Return the constant that is being split via CONSTANT_PTR. */
6252 xxspltib_constant_p (rtx op
,
6257 size_t nunits
= GET_MODE_NUNITS (mode
);
6259 HOST_WIDE_INT value
;
6262 /* Set the returned values to out of bound values. */
6263 *num_insns_ptr
= -1;
6264 *constant_ptr
= 256;
6266 if (!TARGET_P9_VECTOR
)
6269 if (mode
== VOIDmode
)
6270 mode
= GET_MODE (op
);
6272 else if (mode
!= GET_MODE (op
) && GET_MODE (op
) != VOIDmode
)
6275 /* Handle (vec_duplicate <constant>). */
6276 if (GET_CODE (op
) == VEC_DUPLICATE
)
6278 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6279 && mode
!= V2DImode
)
6282 element
= XEXP (op
, 0);
6283 if (!CONST_INT_P (element
))
6286 value
= INTVAL (element
);
6287 if (!IN_RANGE (value
, -128, 127))
6291 /* Handle (const_vector [...]). */
6292 else if (GET_CODE (op
) == CONST_VECTOR
)
6294 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6295 && mode
!= V2DImode
)
6298 element
= CONST_VECTOR_ELT (op
, 0);
6299 if (!CONST_INT_P (element
))
6302 value
= INTVAL (element
);
6303 if (!IN_RANGE (value
, -128, 127))
6306 for (i
= 1; i
< nunits
; i
++)
6308 element
= CONST_VECTOR_ELT (op
, i
);
6309 if (!CONST_INT_P (element
))
6312 if (value
!= INTVAL (element
))
6317 /* Handle integer constants being loaded into the upper part of the VSX
6318 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6319 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6320 else if (CONST_INT_P (op
))
6322 if (!SCALAR_INT_MODE_P (mode
))
6325 value
= INTVAL (op
);
6326 if (!IN_RANGE (value
, -128, 127))
6329 if (!IN_RANGE (value
, -1, 0))
6331 if (!(reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
))
6334 if (EASY_VECTOR_15 (value
))
6342 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6343 sign extend. Special case 0/-1 to allow getting any VSX register instead
6344 of an Altivec register. */
6345 if ((mode
== V4SImode
|| mode
== V8HImode
) && !IN_RANGE (value
, -1, 0)
6346 && EASY_VECTOR_15 (value
))
6349 /* Return # of instructions and the constant byte for XXSPLTIB. */
6350 if (mode
== V16QImode
)
6353 else if (IN_RANGE (value
, -1, 0))
6359 *constant_ptr
= (int) value
;
6364 output_vec_const_move (rtx
*operands
)
6372 mode
= GET_MODE (dest
);
6376 bool dest_vmx_p
= ALTIVEC_REGNO_P (REGNO (dest
));
6377 int xxspltib_value
= 256;
6380 if (zero_constant (vec
, mode
))
6382 if (TARGET_P9_VECTOR
)
6383 return "xxspltib %x0,0";
6385 else if (dest_vmx_p
)
6386 return "vspltisw %0,0";
6389 return "xxlxor %x0,%x0,%x0";
6392 if (all_ones_constant (vec
, mode
))
6394 if (TARGET_P9_VECTOR
)
6395 return "xxspltib %x0,255";
6397 else if (dest_vmx_p
)
6398 return "vspltisw %0,-1";
6400 else if (TARGET_P8_VECTOR
)
6401 return "xxlorc %x0,%x0,%x0";
6407 if (TARGET_P9_VECTOR
6408 && xxspltib_constant_p (vec
, mode
, &num_insns
, &xxspltib_value
))
6412 operands
[2] = GEN_INT (xxspltib_value
& 0xff);
6413 return "xxspltib %x0,%2";
6424 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest
)));
6425 if (zero_constant (vec
, mode
))
6426 return "vspltisw %0,0";
6428 if (all_ones_constant (vec
, mode
))
6429 return "vspltisw %0,-1";
6431 /* Do we need to construct a value using VSLDOI? */
6432 shift
= vspltis_shifted (vec
);
6436 splat_vec
= gen_easy_altivec_constant (vec
);
6437 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
6438 operands
[1] = XEXP (splat_vec
, 0);
6439 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
6442 switch (GET_MODE (splat_vec
))
6445 return "vspltisw %0,%1";
6448 return "vspltish %0,%1";
6451 return "vspltisb %0,%1";
6461 /* Initialize vector TARGET to VALS. */
6464 rs6000_expand_vector_init (rtx target
, rtx vals
)
6466 machine_mode mode
= GET_MODE (target
);
6467 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6468 int n_elts
= GET_MODE_NUNITS (mode
);
6469 int n_var
= 0, one_var
= -1;
6470 bool all_same
= true, all_const_zero
= true;
6474 for (i
= 0; i
< n_elts
; ++i
)
6476 x
= XVECEXP (vals
, 0, i
);
6477 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6478 ++n_var
, one_var
= i
;
6479 else if (x
!= CONST0_RTX (inner_mode
))
6480 all_const_zero
= false;
6482 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6488 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
6489 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
6490 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
6492 /* Zero register. */
6493 emit_move_insn (target
, CONST0_RTX (mode
));
6496 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
6498 /* Splat immediate. */
6499 emit_insn (gen_rtx_SET (target
, const_vec
));
6504 /* Load from constant pool. */
6505 emit_move_insn (target
, const_vec
);
6510 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6511 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
6515 size_t num_elements
= all_same
? 1 : 2;
6516 for (i
= 0; i
< num_elements
; i
++)
6518 op
[i
] = XVECEXP (vals
, 0, i
);
6519 /* Just in case there is a SUBREG with a smaller mode, do a
6521 if (GET_MODE (op
[i
]) != inner_mode
)
6523 rtx tmp
= gen_reg_rtx (inner_mode
);
6524 convert_move (tmp
, op
[i
], 0);
6527 /* Allow load with splat double word. */
6528 else if (MEM_P (op
[i
]))
6531 op
[i
] = force_reg (inner_mode
, op
[i
]);
6533 else if (!REG_P (op
[i
]))
6534 op
[i
] = force_reg (inner_mode
, op
[i
]);
6539 if (mode
== V2DFmode
)
6540 emit_insn (gen_vsx_splat_v2df (target
, op
[0]));
6542 emit_insn (gen_vsx_splat_v2di (target
, op
[0]));
6546 if (mode
== V2DFmode
)
6547 emit_insn (gen_vsx_concat_v2df (target
, op
[0], op
[1]));
6549 emit_insn (gen_vsx_concat_v2di (target
, op
[0], op
[1]));
6554 /* Special case initializing vector int if we are on 64-bit systems with
6555 direct move or we have the ISA 3.0 instructions. */
6556 if (mode
== V4SImode
&& VECTOR_MEM_VSX_P (V4SImode
)
6557 && TARGET_DIRECT_MOVE_64BIT
)
6561 rtx element0
= XVECEXP (vals
, 0, 0);
6562 if (MEM_P (element0
))
6563 element0
= rs6000_force_indexed_or_indirect_mem (element0
);
6565 element0
= force_reg (SImode
, element0
);
6567 if (TARGET_P9_VECTOR
)
6568 emit_insn (gen_vsx_splat_v4si (target
, element0
));
6571 rtx tmp
= gen_reg_rtx (DImode
);
6572 emit_insn (gen_zero_extendsidi2 (tmp
, element0
));
6573 emit_insn (gen_vsx_splat_v4si_di (target
, tmp
));
6582 for (i
= 0; i
< 4; i
++)
6583 elements
[i
] = force_reg (SImode
, XVECEXP (vals
, 0, i
));
6585 emit_insn (gen_vsx_init_v4si (target
, elements
[0], elements
[1],
6586 elements
[2], elements
[3]));
6591 /* With single precision floating point on VSX, know that internally single
6592 precision is actually represented as a double, and either make 2 V2DF
6593 vectors, and convert these vectors to single precision, or do one
6594 conversion, and splat the result to the other elements. */
6595 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (V4SFmode
))
6599 rtx element0
= XVECEXP (vals
, 0, 0);
6601 if (TARGET_P9_VECTOR
)
6603 if (MEM_P (element0
))
6604 element0
= rs6000_force_indexed_or_indirect_mem (element0
);
6606 emit_insn (gen_vsx_splat_v4sf (target
, element0
));
6611 rtx freg
= gen_reg_rtx (V4SFmode
);
6612 rtx sreg
= force_reg (SFmode
, element0
);
6613 rtx cvt
= (TARGET_XSCVDPSPN
6614 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
6615 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
6618 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
,
6624 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
6625 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
6626 rtx flt_even
= gen_reg_rtx (V4SFmode
);
6627 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
6628 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
6629 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
6630 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
6631 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
6633 /* Use VMRGEW if we can instead of doing a permute. */
6634 if (TARGET_P8_VECTOR
)
6636 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op2
));
6637 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op1
, op3
));
6638 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6639 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6640 if (BYTES_BIG_ENDIAN
)
6641 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_even
, flt_odd
));
6643 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_odd
, flt_even
));
6647 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
6648 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
6649 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6650 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6651 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
6657 /* Special case initializing vector short/char that are splats if we are on
6658 64-bit systems with direct move. */
6659 if (all_same
&& TARGET_DIRECT_MOVE_64BIT
6660 && (mode
== V16QImode
|| mode
== V8HImode
))
6662 rtx op0
= XVECEXP (vals
, 0, 0);
6663 rtx di_tmp
= gen_reg_rtx (DImode
);
6666 op0
= force_reg (GET_MODE_INNER (mode
), op0
);
6668 if (mode
== V16QImode
)
6670 emit_insn (gen_zero_extendqidi2 (di_tmp
, op0
));
6671 emit_insn (gen_vsx_vspltb_di (target
, di_tmp
));
6675 if (mode
== V8HImode
)
6677 emit_insn (gen_zero_extendhidi2 (di_tmp
, op0
));
6678 emit_insn (gen_vsx_vsplth_di (target
, di_tmp
));
6683 /* Store value to stack temp. Load vector element. Splat. However, splat
6684 of 64-bit items is not supported on Altivec. */
6685 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
6687 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6688 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
6689 XVECEXP (vals
, 0, 0));
6690 x
= gen_rtx_UNSPEC (VOIDmode
,
6691 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6692 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6694 gen_rtx_SET (target
, mem
),
6696 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
6697 gen_rtx_PARALLEL (VOIDmode
,
6698 gen_rtvec (1, const0_rtx
)));
6699 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
6703 /* One field is non-constant. Load constant then overwrite
6707 rtx copy
= copy_rtx (vals
);
6709 /* Load constant part of vector, substitute neighboring value for
6711 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
6712 rs6000_expand_vector_init (target
, copy
);
6714 /* Insert variable. */
6715 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
6719 /* Construct the vector in memory one field at a time
6720 and load the whole vector. */
6721 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6722 for (i
= 0; i
< n_elts
; i
++)
6723 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
6724 i
* GET_MODE_SIZE (inner_mode
)),
6725 XVECEXP (vals
, 0, i
));
6726 emit_move_insn (target
, mem
);
6729 /* Set field ELT of TARGET to VAL. */
6732 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
6734 machine_mode mode
= GET_MODE (target
);
6735 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6736 rtx reg
= gen_reg_rtx (mode
);
6738 int width
= GET_MODE_SIZE (inner_mode
);
6741 val
= force_reg (GET_MODE (val
), val
);
6743 if (VECTOR_MEM_VSX_P (mode
))
6745 rtx insn
= NULL_RTX
;
6746 rtx elt_rtx
= GEN_INT (elt
);
6748 if (mode
== V2DFmode
)
6749 insn
= gen_vsx_set_v2df (target
, target
, val
, elt_rtx
);
6751 else if (mode
== V2DImode
)
6752 insn
= gen_vsx_set_v2di (target
, target
, val
, elt_rtx
);
6754 else if (TARGET_P9_VECTOR
&& TARGET_POWERPC64
)
6756 if (mode
== V4SImode
)
6757 insn
= gen_vsx_set_v4si_p9 (target
, target
, val
, elt_rtx
);
6758 else if (mode
== V8HImode
)
6759 insn
= gen_vsx_set_v8hi_p9 (target
, target
, val
, elt_rtx
);
6760 else if (mode
== V16QImode
)
6761 insn
= gen_vsx_set_v16qi_p9 (target
, target
, val
, elt_rtx
);
6762 else if (mode
== V4SFmode
)
6763 insn
= gen_vsx_set_v4sf_p9 (target
, target
, val
, elt_rtx
);
6773 /* Simplify setting single element vectors like V1TImode. */
6774 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
6776 emit_move_insn (target
, gen_lowpart (mode
, val
));
6780 /* Load single variable value. */
6781 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6782 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
6783 x
= gen_rtx_UNSPEC (VOIDmode
,
6784 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6785 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6787 gen_rtx_SET (reg
, mem
),
6790 /* Linear sequence. */
6791 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
6792 for (i
= 0; i
< 16; ++i
)
6793 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
6795 /* Set permute mask to insert element into target. */
6796 for (i
= 0; i
< width
; ++i
)
6797 XVECEXP (mask
, 0, elt
*width
+ i
)
6798 = GEN_INT (i
+ 0x10);
6799 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
6801 if (BYTES_BIG_ENDIAN
)
6802 x
= gen_rtx_UNSPEC (mode
,
6803 gen_rtvec (3, target
, reg
,
6804 force_reg (V16QImode
, x
)),
6808 if (TARGET_P9_VECTOR
)
6809 x
= gen_rtx_UNSPEC (mode
,
6810 gen_rtvec (3, reg
, target
,
6811 force_reg (V16QImode
, x
)),
6815 /* Invert selector. We prefer to generate VNAND on P8 so
6816 that future fusion opportunities can kick in, but must
6817 generate VNOR elsewhere. */
6818 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
6819 rtx iorx
= (TARGET_P8_VECTOR
6820 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
6821 : gen_rtx_AND (V16QImode
, notx
, notx
));
6822 rtx tmp
= gen_reg_rtx (V16QImode
);
6823 emit_insn (gen_rtx_SET (tmp
, iorx
));
6825 /* Permute with operands reversed and adjusted selector. */
6826 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
6831 emit_insn (gen_rtx_SET (target
, x
));
6834 /* Extract field ELT from VEC into TARGET. */
6837 rs6000_expand_vector_extract (rtx target
, rtx vec
, rtx elt
)
6839 machine_mode mode
= GET_MODE (vec
);
6840 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6843 if (VECTOR_MEM_VSX_P (mode
) && CONST_INT_P (elt
))
6850 gcc_assert (INTVAL (elt
) == 0 && inner_mode
== TImode
);
6851 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
6854 emit_insn (gen_vsx_extract_v2df (target
, vec
, elt
));
6857 emit_insn (gen_vsx_extract_v2di (target
, vec
, elt
));
6860 emit_insn (gen_vsx_extract_v4sf (target
, vec
, elt
));
6863 if (TARGET_DIRECT_MOVE_64BIT
)
6865 emit_insn (gen_vsx_extract_v16qi (target
, vec
, elt
));
6871 if (TARGET_DIRECT_MOVE_64BIT
)
6873 emit_insn (gen_vsx_extract_v8hi (target
, vec
, elt
));
6879 if (TARGET_DIRECT_MOVE_64BIT
)
6881 emit_insn (gen_vsx_extract_v4si (target
, vec
, elt
));
6887 else if (VECTOR_MEM_VSX_P (mode
) && !CONST_INT_P (elt
)
6888 && TARGET_DIRECT_MOVE_64BIT
)
6890 if (GET_MODE (elt
) != DImode
)
6892 rtx tmp
= gen_reg_rtx (DImode
);
6893 convert_move (tmp
, elt
, 0);
6896 else if (!REG_P (elt
))
6897 elt
= force_reg (DImode
, elt
);
6902 emit_insn (gen_vsx_extract_v2df_var (target
, vec
, elt
));
6906 emit_insn (gen_vsx_extract_v2di_var (target
, vec
, elt
));
6910 emit_insn (gen_vsx_extract_v4sf_var (target
, vec
, elt
));
6914 emit_insn (gen_vsx_extract_v4si_var (target
, vec
, elt
));
6918 emit_insn (gen_vsx_extract_v8hi_var (target
, vec
, elt
));
6922 emit_insn (gen_vsx_extract_v16qi_var (target
, vec
, elt
));
6930 gcc_assert (CONST_INT_P (elt
));
6932 /* Allocate mode-sized buffer. */
6933 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6935 emit_move_insn (mem
, vec
);
6937 /* Add offset to field within buffer matching vector element. */
6938 mem
= adjust_address_nv (mem
, inner_mode
,
6939 INTVAL (elt
) * GET_MODE_SIZE (inner_mode
));
6941 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
6944 /* Helper function to return the register number of a RTX. */
6946 regno_or_subregno (rtx op
)
6950 else if (SUBREG_P (op
))
6951 return subreg_regno (op
);
6956 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6957 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6958 temporary (BASE_TMP) to fixup the address. Return the new memory address
6959 that is valid for reads or writes to a given register (SCALAR_REG). */
6962 rs6000_adjust_vec_address (rtx scalar_reg
,
6966 machine_mode scalar_mode
)
6968 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
6969 rtx addr
= XEXP (mem
, 0);
6974 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6975 gcc_assert (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
);
6977 /* Calculate what we need to add to the address to get the element
6979 if (CONST_INT_P (element
))
6980 element_offset
= GEN_INT (INTVAL (element
) * scalar_size
);
6983 int byte_shift
= exact_log2 (scalar_size
);
6984 gcc_assert (byte_shift
>= 0);
6986 if (byte_shift
== 0)
6987 element_offset
= element
;
6991 if (TARGET_POWERPC64
)
6992 emit_insn (gen_ashldi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
6994 emit_insn (gen_ashlsi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
6996 element_offset
= base_tmp
;
7000 /* Create the new address pointing to the element within the vector. If we
7001 are adding 0, we don't have to change the address. */
7002 if (element_offset
== const0_rtx
)
7005 /* A simple indirect address can be converted into a reg + offset
7007 else if (REG_P (addr
) || SUBREG_P (addr
))
7008 new_addr
= gen_rtx_PLUS (Pmode
, addr
, element_offset
);
7010 /* Optimize D-FORM addresses with constant offset with a constant element, to
7011 include the element offset in the address directly. */
7012 else if (GET_CODE (addr
) == PLUS
)
7014 rtx op0
= XEXP (addr
, 0);
7015 rtx op1
= XEXP (addr
, 1);
7018 gcc_assert (REG_P (op0
) || SUBREG_P (op0
));
7019 if (CONST_INT_P (op1
) && CONST_INT_P (element_offset
))
7021 HOST_WIDE_INT offset
= INTVAL (op1
) + INTVAL (element_offset
);
7022 rtx offset_rtx
= GEN_INT (offset
);
7024 if (IN_RANGE (offset
, -32768, 32767)
7025 && (scalar_size
< 8 || (offset
& 0x3) == 0))
7026 new_addr
= gen_rtx_PLUS (Pmode
, op0
, offset_rtx
);
7029 emit_move_insn (base_tmp
, offset_rtx
);
7030 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7035 bool op1_reg_p
= (REG_P (op1
) || SUBREG_P (op1
));
7036 bool ele_reg_p
= (REG_P (element_offset
) || SUBREG_P (element_offset
));
7038 /* Note, ADDI requires the register being added to be a base
7039 register. If the register was R0, load it up into the temporary
7042 && (ele_reg_p
|| reg_or_subregno (op1
) != FIRST_GPR_REGNO
))
7044 insn
= gen_add3_insn (base_tmp
, op1
, element_offset
);
7045 gcc_assert (insn
!= NULL_RTX
);
7050 && reg_or_subregno (element_offset
) != FIRST_GPR_REGNO
)
7052 insn
= gen_add3_insn (base_tmp
, element_offset
, op1
);
7053 gcc_assert (insn
!= NULL_RTX
);
7059 emit_move_insn (base_tmp
, op1
);
7060 emit_insn (gen_add2_insn (base_tmp
, element_offset
));
7063 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7069 emit_move_insn (base_tmp
, addr
);
7070 new_addr
= gen_rtx_PLUS (Pmode
, base_tmp
, element_offset
);
7073 /* If we have a PLUS, we need to see whether the particular register class
7074 allows for D-FORM or X-FORM addressing. */
7075 if (GET_CODE (new_addr
) == PLUS
)
7077 rtx op1
= XEXP (new_addr
, 1);
7078 addr_mask_type addr_mask
;
7079 int scalar_regno
= regno_or_subregno (scalar_reg
);
7081 gcc_assert (scalar_regno
< FIRST_PSEUDO_REGISTER
);
7082 if (INT_REGNO_P (scalar_regno
))
7083 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_GPR
];
7085 else if (FP_REGNO_P (scalar_regno
))
7086 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_FPR
];
7088 else if (ALTIVEC_REGNO_P (scalar_regno
))
7089 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_VMX
];
7094 if (REG_P (op1
) || SUBREG_P (op1
))
7095 valid_addr_p
= (addr_mask
& RELOAD_REG_INDEXED
) != 0;
7097 valid_addr_p
= (addr_mask
& RELOAD_REG_OFFSET
) != 0;
7100 else if (REG_P (new_addr
) || SUBREG_P (new_addr
))
7101 valid_addr_p
= true;
7104 valid_addr_p
= false;
7108 emit_move_insn (base_tmp
, new_addr
);
7109 new_addr
= base_tmp
;
7112 return change_address (mem
, scalar_mode
, new_addr
);
7115 /* Split a variable vec_extract operation into the component instructions. */
7118 rs6000_split_vec_extract_var (rtx dest
, rtx src
, rtx element
, rtx tmp_gpr
,
7121 machine_mode mode
= GET_MODE (src
);
7122 machine_mode scalar_mode
= GET_MODE (dest
);
7123 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7124 int byte_shift
= exact_log2 (scalar_size
);
7126 gcc_assert (byte_shift
>= 0);
7128 /* If we are given a memory address, optimize to load just the element. We
7129 don't have to adjust the vector element number on little endian
7133 gcc_assert (REG_P (tmp_gpr
));
7134 emit_move_insn (dest
, rs6000_adjust_vec_address (dest
, src
, element
,
7135 tmp_gpr
, scalar_mode
));
7139 else if (REG_P (src
) || SUBREG_P (src
))
7141 int bit_shift
= byte_shift
+ 3;
7143 int dest_regno
= regno_or_subregno (dest
);
7144 int src_regno
= regno_or_subregno (src
);
7145 int element_regno
= regno_or_subregno (element
);
7147 gcc_assert (REG_P (tmp_gpr
));
7149 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7150 a general purpose register. */
7151 if (TARGET_P9_VECTOR
7152 && (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
7153 && INT_REGNO_P (dest_regno
)
7154 && ALTIVEC_REGNO_P (src_regno
)
7155 && INT_REGNO_P (element_regno
))
7157 rtx dest_si
= gen_rtx_REG (SImode
, dest_regno
);
7158 rtx element_si
= gen_rtx_REG (SImode
, element_regno
);
7160 if (mode
== V16QImode
)
7161 emit_insn (BYTES_BIG_ENDIAN
7162 ? gen_vextublx (dest_si
, element_si
, src
)
7163 : gen_vextubrx (dest_si
, element_si
, src
));
7165 else if (mode
== V8HImode
)
7167 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7168 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const1_rtx
));
7169 emit_insn (BYTES_BIG_ENDIAN
7170 ? gen_vextuhlx (dest_si
, tmp_gpr_si
, src
)
7171 : gen_vextuhrx (dest_si
, tmp_gpr_si
, src
));
7177 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7178 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const2_rtx
));
7179 emit_insn (BYTES_BIG_ENDIAN
7180 ? gen_vextuwlx (dest_si
, tmp_gpr_si
, src
)
7181 : gen_vextuwrx (dest_si
, tmp_gpr_si
, src
));
7188 gcc_assert (REG_P (tmp_altivec
));
7190 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7191 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7192 will shift the element into the upper position (adding 3 to convert a
7193 byte shift into a bit shift). */
7194 if (scalar_size
== 8)
7196 if (!BYTES_BIG_ENDIAN
)
7198 emit_insn (gen_xordi3 (tmp_gpr
, element
, const1_rtx
));
7204 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7206 emit_insn (gen_rtx_SET (tmp_gpr
,
7207 gen_rtx_AND (DImode
,
7208 gen_rtx_ASHIFT (DImode
,
7215 if (!BYTES_BIG_ENDIAN
)
7217 rtx num_ele_m1
= GEN_INT (GET_MODE_NUNITS (mode
) - 1);
7219 emit_insn (gen_anddi3 (tmp_gpr
, element
, num_ele_m1
));
7220 emit_insn (gen_subdi3 (tmp_gpr
, num_ele_m1
, tmp_gpr
));
7226 emit_insn (gen_ashldi3 (tmp_gpr
, element2
, GEN_INT (bit_shift
)));
7229 /* Get the value into the lower byte of the Altivec register where VSLO
7231 if (TARGET_P9_VECTOR
)
7232 emit_insn (gen_vsx_splat_v2di (tmp_altivec
, tmp_gpr
));
7233 else if (can_create_pseudo_p ())
7234 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_gpr
, tmp_gpr
));
7237 rtx tmp_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7238 emit_move_insn (tmp_di
, tmp_gpr
);
7239 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_di
, tmp_di
));
7242 /* Do the VSLO to get the value into the final location. */
7246 emit_insn (gen_vsx_vslo_v2df (dest
, src
, tmp_altivec
));
7250 emit_insn (gen_vsx_vslo_v2di (dest
, src
, tmp_altivec
));
7255 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7256 rtx tmp_altivec_v4sf
= gen_rtx_REG (V4SFmode
, REGNO (tmp_altivec
));
7257 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7258 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7261 emit_insn (gen_vsx_xscvspdp_scalar2 (dest
, tmp_altivec_v4sf
));
7269 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7270 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7271 rtx tmp_gpr_di
= gen_rtx_REG (DImode
, REGNO (dest
));
7272 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7274 emit_move_insn (tmp_gpr_di
, tmp_altivec_di
);
7275 emit_insn (gen_ashrdi3 (tmp_gpr_di
, tmp_gpr_di
,
7276 GEN_INT (64 - (8 * scalar_size
))));
7290 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7291 selects whether the alignment is abi mandated, optional, or
7292 both abi and optional alignment. */
7295 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
7297 if (how
!= align_opt
)
7299 if (TREE_CODE (type
) == VECTOR_TYPE
&& align
< 128)
7303 if (how
!= align_abi
)
7305 if (TREE_CODE (type
) == ARRAY_TYPE
7306 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
7308 if (align
< BITS_PER_WORD
)
7309 align
= BITS_PER_WORD
;
7316 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7317 instructions simply ignore the low bits; VSX memory instructions
7318 are aligned to 4 or 8 bytes. */
7321 rs6000_slow_unaligned_access (machine_mode mode
, unsigned int align
)
7323 return (STRICT_ALIGNMENT
7324 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7325 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && align
< 32)
7326 || ((VECTOR_MODE_P (mode
) || FLOAT128_VECTOR_P (mode
))
7327 && (int) align
< VECTOR_ALIGN (mode
)))));
7330 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7333 rs6000_special_adjust_field_align_p (tree type
, unsigned int computed
)
7335 if (TARGET_ALTIVEC
&& TREE_CODE (type
) == VECTOR_TYPE
)
7337 if (computed
!= 128)
7340 if (!warned
&& warn_psabi
)
7343 inform (input_location
,
7344 "the layout of aggregates containing vectors with"
7345 " %d-byte alignment has changed in GCC 5",
7346 computed
/ BITS_PER_UNIT
);
7349 /* In current GCC there is no special case. */
7356 /* AIX increases natural record alignment to doubleword if the first
7357 field is an FP double while the FP fields remain word aligned. */
7360 rs6000_special_round_type_align (tree type
, unsigned int computed
,
7361 unsigned int specified
)
7363 unsigned int align
= MAX (computed
, specified
);
7364 tree field
= TYPE_FIELDS (type
);
7366 /* Skip all non field decls */
7367 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7368 field
= DECL_CHAIN (field
);
7370 if (field
!= NULL
&& field
!= type
)
7372 type
= TREE_TYPE (field
);
7373 while (TREE_CODE (type
) == ARRAY_TYPE
)
7374 type
= TREE_TYPE (type
);
7376 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
7377 align
= MAX (align
, 64);
7383 /* Darwin increases record alignment to the natural alignment of
7387 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
7388 unsigned int specified
)
7390 unsigned int align
= MAX (computed
, specified
);
7392 if (TYPE_PACKED (type
))
7395 /* Find the first field, looking down into aggregates. */
7397 tree field
= TYPE_FIELDS (type
);
7398 /* Skip all non field decls */
7399 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7400 field
= DECL_CHAIN (field
);
7403 /* A packed field does not contribute any extra alignment. */
7404 if (DECL_PACKED (field
))
7406 type
= TREE_TYPE (field
);
7407 while (TREE_CODE (type
) == ARRAY_TYPE
)
7408 type
= TREE_TYPE (type
);
7409 } while (AGGREGATE_TYPE_P (type
));
7411 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
7412 align
= MAX (align
, TYPE_ALIGN (type
));
7417 /* Return 1 for an operand in small memory on V.4/eabi. */
7420 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
7421 machine_mode mode ATTRIBUTE_UNUSED
)
7426 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
7429 if (DEFAULT_ABI
!= ABI_V4
)
7432 if (GET_CODE (op
) == SYMBOL_REF
)
7435 else if (GET_CODE (op
) != CONST
7436 || GET_CODE (XEXP (op
, 0)) != PLUS
7437 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
7438 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
7443 rtx sum
= XEXP (op
, 0);
7444 HOST_WIDE_INT summand
;
7446 /* We have to be careful here, because it is the referenced address
7447 that must be 32k from _SDA_BASE_, not just the symbol. */
7448 summand
= INTVAL (XEXP (sum
, 1));
7449 if (summand
< 0 || summand
> g_switch_value
)
7452 sym_ref
= XEXP (sum
, 0);
7455 return SYMBOL_REF_SMALL_P (sym_ref
);
7461 /* Return true if either operand is a general purpose register. */
7464 gpr_or_gpr_p (rtx op0
, rtx op1
)
7466 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
7467 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
7470 /* Return true if this is a move direct operation between GPR registers and
7471 floating point/VSX registers. */
7474 direct_move_p (rtx op0
, rtx op1
)
7478 if (!REG_P (op0
) || !REG_P (op1
))
7481 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
7484 regno0
= REGNO (op0
);
7485 regno1
= REGNO (op1
);
7486 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
7489 if (INT_REGNO_P (regno0
))
7490 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
7492 else if (INT_REGNO_P (regno1
))
7494 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
7497 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
7504 /* Return true if the OFFSET is valid for the quad address instructions that
7505 use d-form (register + offset) addressing. */
7508 quad_address_offset_p (HOST_WIDE_INT offset
)
7510 return (IN_RANGE (offset
, -32768, 32767) && ((offset
) & 0xf) == 0);
7513 /* Return true if the ADDR is an acceptable address for a quad memory
7514 operation of mode MODE (either LQ/STQ for general purpose registers, or
7515 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7516 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7517 3.0 LXV/STXV instruction. */
7520 quad_address_p (rtx addr
, machine_mode mode
, bool strict
)
7524 if (GET_MODE_SIZE (mode
) != 16)
7527 if (legitimate_indirect_address_p (addr
, strict
))
7530 if (VECTOR_MODE_P (mode
) && !mode_supports_dq_form (mode
))
7533 if (GET_CODE (addr
) != PLUS
)
7536 op0
= XEXP (addr
, 0);
7537 if (!REG_P (op0
) || !INT_REG_OK_FOR_BASE_P (op0
, strict
))
7540 op1
= XEXP (addr
, 1);
7541 if (!CONST_INT_P (op1
))
7544 return quad_address_offset_p (INTVAL (op1
));
7547 /* Return true if this is a load or store quad operation. This function does
7548 not handle the atomic quad memory instructions. */
7551 quad_load_store_p (rtx op0
, rtx op1
)
7555 if (!TARGET_QUAD_MEMORY
)
7558 else if (REG_P (op0
) && MEM_P (op1
))
7559 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
7560 && quad_memory_operand (op1
, GET_MODE (op1
))
7561 && !reg_overlap_mentioned_p (op0
, op1
));
7563 else if (MEM_P (op0
) && REG_P (op1
))
7564 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
7565 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
7570 if (TARGET_DEBUG_ADDR
)
7572 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
7573 ret
? "true" : "false");
7574 debug_rtx (gen_rtx_SET (op0
, op1
));
7580 /* Given an address, return a constant offset term if one exists. */
7583 address_offset (rtx op
)
7585 if (GET_CODE (op
) == PRE_INC
7586 || GET_CODE (op
) == PRE_DEC
)
7588 else if (GET_CODE (op
) == PRE_MODIFY
7589 || GET_CODE (op
) == LO_SUM
)
7592 if (GET_CODE (op
) == CONST
)
7595 if (GET_CODE (op
) == PLUS
)
7598 if (CONST_INT_P (op
))
7604 /* Return true if the MEM operand is a memory operand suitable for use
7605 with a (full width, possibly multiple) gpr load/store. On
7606 powerpc64 this means the offset must be divisible by 4.
7607 Implements 'Y' constraint.
7609 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7610 a constraint function we know the operand has satisfied a suitable
7611 memory predicate. Also accept some odd rtl generated by reload
7612 (see rs6000_legitimize_reload_address for various forms). It is
7613 important that reload rtl be accepted by appropriate constraints
7614 but not by the operand predicate.
7616 Offsetting a lo_sum should not be allowed, except where we know by
7617 alignment that a 32k boundary is not crossed, but see the ???
7618 comment in rs6000_legitimize_reload_address. Note that by
7619 "offsetting" here we mean a further offset to access parts of the
7620 MEM. It's fine to have a lo_sum where the inner address is offset
7621 from a sym, since the same sym+offset will appear in the high part
7622 of the address calculation. */
7625 mem_operand_gpr (rtx op
, machine_mode mode
)
7627 unsigned HOST_WIDE_INT offset
;
7629 rtx addr
= XEXP (op
, 0);
7631 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7633 && (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
7634 && mode_supports_pre_incdec_p (mode
)
7635 && legitimate_indirect_address_p (XEXP (addr
, 0), false))
7638 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7639 if (!rs6000_offsettable_memref_p (op
, mode
, false))
7642 op
= address_offset (addr
);
7646 offset
= INTVAL (op
);
7647 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
7650 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
7654 if (GET_CODE (addr
) == LO_SUM
)
7655 /* For lo_sum addresses, we must allow any offset except one that
7656 causes a wrap, so test only the low 16 bits. */
7657 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
7659 return offset
+ 0x8000 < 0x10000u
- extra
;
7662 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7663 enforce an offset divisible by 4 even for 32-bit. */
7666 mem_operand_ds_form (rtx op
, machine_mode mode
)
7668 unsigned HOST_WIDE_INT offset
;
7670 rtx addr
= XEXP (op
, 0);
7672 if (!offsettable_address_p (false, mode
, addr
))
7675 op
= address_offset (addr
);
7679 offset
= INTVAL (op
);
7680 if ((offset
& 3) != 0)
7683 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
7687 if (GET_CODE (addr
) == LO_SUM
)
7688 /* For lo_sum addresses, we must allow any offset except one that
7689 causes a wrap, so test only the low 16 bits. */
7690 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
7692 return offset
+ 0x8000 < 0x10000u
- extra
;
7695 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7698 reg_offset_addressing_ok_p (machine_mode mode
)
7712 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7713 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7714 a vector mode, if we want to use the VSX registers to move it around,
7715 we need to restrict ourselves to reg+reg addressing. Similarly for
7716 IEEE 128-bit floating point that is passed in a single vector
7718 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
7719 return mode_supports_dq_form (mode
);
7723 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7724 addressing for the LFIWZX and STFIWX instructions. */
7725 if (TARGET_NO_SDMODE_STACK
)
7737 virtual_stack_registers_memory_p (rtx op
)
7741 if (GET_CODE (op
) == REG
)
7742 regnum
= REGNO (op
);
7744 else if (GET_CODE (op
) == PLUS
7745 && GET_CODE (XEXP (op
, 0)) == REG
7746 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
7747 regnum
= REGNO (XEXP (op
, 0));
7752 return (regnum
>= FIRST_VIRTUAL_REGISTER
7753 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
7756 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7757 is known to not straddle a 32k boundary. This function is used
7758 to determine whether -mcmodel=medium code can use TOC pointer
7759 relative addressing for OP. This means the alignment of the TOC
7760 pointer must also be taken into account, and unfortunately that is
7763 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7764 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7768 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
7772 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
7774 if (GET_CODE (op
) != SYMBOL_REF
)
7777 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7779 if (mode_supports_dq_form (mode
))
7782 dsize
= GET_MODE_SIZE (mode
);
7783 decl
= SYMBOL_REF_DECL (op
);
7789 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7790 replacing memory addresses with an anchor plus offset. We
7791 could find the decl by rummaging around in the block->objects
7792 VEC for the given offset but that seems like too much work. */
7793 dalign
= BITS_PER_UNIT
;
7794 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
7795 && SYMBOL_REF_ANCHOR_P (op
)
7796 && SYMBOL_REF_BLOCK (op
) != NULL
)
7798 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
7800 dalign
= block
->alignment
;
7801 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
7803 else if (CONSTANT_POOL_ADDRESS_P (op
))
7805 /* It would be nice to have get_pool_align().. */
7806 machine_mode cmode
= get_pool_mode (op
);
7808 dalign
= GET_MODE_ALIGNMENT (cmode
);
7811 else if (DECL_P (decl
))
7813 dalign
= DECL_ALIGN (decl
);
7817 /* Allow BLKmode when the entire object is known to not
7818 cross a 32k boundary. */
7819 if (!DECL_SIZE_UNIT (decl
))
7822 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
7825 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
7829 dalign
/= BITS_PER_UNIT
;
7830 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7831 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7832 return dalign
>= dsize
;
7838 /* Find how many bits of the alignment we know for this access. */
7839 dalign
/= BITS_PER_UNIT
;
7840 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7841 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7843 lsb
= offset
& -offset
;
7847 return dalign
>= dsize
;
7851 constant_pool_expr_p (rtx op
)
7855 split_const (op
, &base
, &offset
);
7856 return (GET_CODE (base
) == SYMBOL_REF
7857 && CONSTANT_POOL_ADDRESS_P (base
)
7858 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
7861 /* These are only used to pass through from print_operand/print_operand_address
7862 to rs6000_output_addr_const_extra over the intervening function
7863 output_addr_const which is not target code. */
7864 static const_rtx tocrel_base_oac
, tocrel_offset_oac
;
7866 /* Return true if OP is a toc pointer relative address (the output
7867 of create_TOC_reference). If STRICT, do not match non-split
7868 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7869 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7870 TOCREL_OFFSET_RET respectively. */
7873 toc_relative_expr_p (const_rtx op
, bool strict
, const_rtx
*tocrel_base_ret
,
7874 const_rtx
*tocrel_offset_ret
)
7879 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7881 /* When strict ensure we have everything tidy. */
7883 && !(GET_CODE (op
) == LO_SUM
7884 && REG_P (XEXP (op
, 0))
7885 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
)))
7888 /* When not strict, allow non-split TOC addresses and also allow
7889 (lo_sum (high ..)) TOC addresses created during reload. */
7890 if (GET_CODE (op
) == LO_SUM
)
7894 const_rtx tocrel_base
= op
;
7895 const_rtx tocrel_offset
= const0_rtx
;
7897 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
7899 tocrel_base
= XEXP (op
, 0);
7900 tocrel_offset
= XEXP (op
, 1);
7903 if (tocrel_base_ret
)
7904 *tocrel_base_ret
= tocrel_base
;
7905 if (tocrel_offset_ret
)
7906 *tocrel_offset_ret
= tocrel_offset
;
7908 return (GET_CODE (tocrel_base
) == UNSPEC
7909 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
7910 && REG_P (XVECEXP (tocrel_base
, 0, 1))
7911 && REGNO (XVECEXP (tocrel_base
, 0, 1)) == TOC_REGISTER
);
7914 /* Return true if X is a constant pool address, and also for cmodel=medium
7915 if X is a toc-relative address known to be offsettable within MODE. */
7918 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
7921 const_rtx tocrel_base
, tocrel_offset
;
7922 return (toc_relative_expr_p (x
, strict
, &tocrel_base
, &tocrel_offset
)
7923 && (TARGET_CMODEL
!= CMODEL_MEDIUM
7924 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
7926 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
7927 INTVAL (tocrel_offset
), mode
)));
7931 legitimate_small_data_p (machine_mode mode
, rtx x
)
7933 return (DEFAULT_ABI
== ABI_V4
7934 && !flag_pic
&& !TARGET_TOC
7935 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
7936 && small_data_operand (x
, mode
));
7940 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
7941 bool strict
, bool worst_case
)
7943 unsigned HOST_WIDE_INT offset
;
7946 if (GET_CODE (x
) != PLUS
)
7948 if (!REG_P (XEXP (x
, 0)))
7950 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
7952 if (mode_supports_dq_form (mode
))
7953 return quad_address_p (x
, mode
, strict
);
7954 if (!reg_offset_addressing_ok_p (mode
))
7955 return virtual_stack_registers_memory_p (x
);
7956 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
7958 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
7961 offset
= INTVAL (XEXP (x
, 1));
7968 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7970 if (VECTOR_MEM_VSX_P (mode
))
7975 if (!TARGET_POWERPC64
)
7977 else if (offset
& 3)
7990 if (!TARGET_POWERPC64
)
7992 else if (offset
& 3)
8001 return offset
< 0x10000 - extra
;
8005 legitimate_indexed_address_p (rtx x
, int strict
)
8009 if (GET_CODE (x
) != PLUS
)
8015 return (REG_P (op0
) && REG_P (op1
)
8016 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
8017 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
8018 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
8019 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
8023 avoiding_indexed_address_p (machine_mode mode
)
8025 /* Avoid indexed addressing for modes that have non-indexed
8026 load/store instruction forms. */
8027 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
8031 legitimate_indirect_address_p (rtx x
, int strict
)
8033 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
8037 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
8039 if (!TARGET_MACHO
|| !flag_pic
8040 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
8044 if (GET_CODE (x
) != LO_SUM
)
8046 if (GET_CODE (XEXP (x
, 0)) != REG
)
8048 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
8052 return CONSTANT_P (x
);
8056 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
8058 if (GET_CODE (x
) != LO_SUM
)
8060 if (GET_CODE (XEXP (x
, 0)) != REG
)
8062 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8064 /* quad word addresses are restricted, and we can't use LO_SUM. */
8065 if (mode_supports_dq_form (mode
))
8069 if (TARGET_ELF
|| TARGET_MACHO
)
8073 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
8075 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8076 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8077 recognizes some LO_SUM addresses as valid although this
8078 function says opposite. In most cases, LRA through different
8079 transformations can generate correct code for address reloads.
8080 It can not manage only some LO_SUM cases. So we need to add
8081 code analogous to one in rs6000_legitimize_reload_address for
8082 LOW_SUM here saying that some addresses are still valid. */
8083 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
8084 && small_toc_ref (x
, VOIDmode
));
8085 if (TARGET_TOC
&& ! large_toc_ok
)
8087 if (GET_MODE_NUNITS (mode
) != 1)
8089 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
8090 && !(/* ??? Assume floating point reg based on mode? */
8091 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
)))
8094 return CONSTANT_P (x
) || large_toc_ok
;
8101 /* Try machine-dependent ways of modifying an illegitimate address
8102 to be legitimate. If we find one, return the new, valid address.
8103 This is used from only one place: `memory_address' in explow.c.
8105 OLDX is the address as it was before break_out_memory_refs was
8106 called. In some cases it is useful to look at this to decide what
8109 It is always safe for this function to do nothing. It exists to
8110 recognize opportunities to optimize the output.
8112 On RS/6000, first check for the sum of a register with a constant
8113 integer that is out of range. If so, generate code to add the
8114 constant with the low-order 16 bits masked to the register and force
8115 this result into another register (this can be done with `cau').
8116 Then generate an address of REG+(CONST&0xffff), allowing for the
8117 possibility of bit 16 being a one.
8119 Then check for the sum of a register and something not constant, try to
8120 load the other things into a register and return the sum. */
8123 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
8128 if (!reg_offset_addressing_ok_p (mode
)
8129 || mode_supports_dq_form (mode
))
8131 if (virtual_stack_registers_memory_p (x
))
8134 /* In theory we should not be seeing addresses of the form reg+0,
8135 but just in case it is generated, optimize it away. */
8136 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
8137 return force_reg (Pmode
, XEXP (x
, 0));
8139 /* For TImode with load/store quad, restrict addresses to just a single
8140 pointer, so it works with both GPRs and VSX registers. */
8141 /* Make sure both operands are registers. */
8142 else if (GET_CODE (x
) == PLUS
8143 && (mode
!= TImode
|| !TARGET_VSX
))
8144 return gen_rtx_PLUS (Pmode
,
8145 force_reg (Pmode
, XEXP (x
, 0)),
8146 force_reg (Pmode
, XEXP (x
, 1)));
8148 return force_reg (Pmode
, x
);
8150 if (GET_CODE (x
) == SYMBOL_REF
)
8152 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
8154 return rs6000_legitimize_tls_address (x
, model
);
8166 /* As in legitimate_offset_address_p we do not assume
8167 worst-case. The mode here is just a hint as to the registers
8168 used. A TImode is usually in gprs, but may actually be in
8169 fprs. Leave worst-case scenario for reload to handle via
8170 insn constraints. PTImode is only GPRs. */
8177 if (GET_CODE (x
) == PLUS
8178 && GET_CODE (XEXP (x
, 0)) == REG
8179 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8180 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
8181 >= 0x10000 - extra
))
8183 HOST_WIDE_INT high_int
, low_int
;
8185 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8186 if (low_int
>= 0x8000 - extra
)
8188 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
8189 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8190 GEN_INT (high_int
)), 0);
8191 return plus_constant (Pmode
, sum
, low_int
);
8193 else if (GET_CODE (x
) == PLUS
8194 && GET_CODE (XEXP (x
, 0)) == REG
8195 && GET_CODE (XEXP (x
, 1)) != CONST_INT
8196 && GET_MODE_NUNITS (mode
) == 1
8197 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8198 || (/* ??? Assume floating point reg based on mode? */
8199 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
)))
8200 && !avoiding_indexed_address_p (mode
))
8202 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8203 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
8205 else if ((TARGET_ELF
8207 || !MACHO_DYNAMIC_NO_PIC_P
8213 && GET_CODE (x
) != CONST_INT
8214 && GET_CODE (x
) != CONST_WIDE_INT
8215 && GET_CODE (x
) != CONST_DOUBLE
8217 && GET_MODE_NUNITS (mode
) == 1
8218 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8219 || (/* ??? Assume floating point reg based on mode? */
8220 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
))))
8222 rtx reg
= gen_reg_rtx (Pmode
);
8224 emit_insn (gen_elf_high (reg
, x
));
8226 emit_insn (gen_macho_high (reg
, x
));
8227 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
8230 && GET_CODE (x
) == SYMBOL_REF
8231 && constant_pool_expr_p (x
)
8232 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
8233 return create_TOC_reference (x
, NULL_RTX
);
8238 /* Debug version of rs6000_legitimize_address. */
8240 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
8246 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
8247 insns
= get_insns ();
8253 "\nrs6000_legitimize_address: mode %s, old code %s, "
8254 "new code %s, modified\n",
8255 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
8256 GET_RTX_NAME (GET_CODE (ret
)));
8258 fprintf (stderr
, "Original address:\n");
8261 fprintf (stderr
, "oldx:\n");
8264 fprintf (stderr
, "New address:\n");
8269 fprintf (stderr
, "Insns added:\n");
8270 debug_rtx_list (insns
, 20);
8276 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8277 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
8288 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8289 We need to emit DTP-relative relocations. */
8291 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
8293 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8298 fputs ("\t.long\t", file
);
8301 fputs (DOUBLE_INT_ASM_OP
, file
);
8306 output_addr_const (file
, x
);
8308 fputs ("@dtprel+0x8000", file
);
8309 else if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
)
8311 switch (SYMBOL_REF_TLS_MODEL (x
))
8315 case TLS_MODEL_LOCAL_EXEC
:
8316 fputs ("@le", file
);
8318 case TLS_MODEL_INITIAL_EXEC
:
8319 fputs ("@ie", file
);
8321 case TLS_MODEL_GLOBAL_DYNAMIC
:
8322 case TLS_MODEL_LOCAL_DYNAMIC
:
8331 /* Return true if X is a symbol that refers to real (rather than emulated)
8335 rs6000_real_tls_symbol_ref_p (rtx x
)
8337 return (GET_CODE (x
) == SYMBOL_REF
8338 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
8341 /* In the name of slightly smaller debug output, and to cater to
8342 general assembler lossage, recognize various UNSPEC sequences
8343 and turn them back into a direct symbol reference. */
8346 rs6000_delegitimize_address (rtx orig_x
)
8350 orig_x
= delegitimize_mem_from_attrs (orig_x
);
8356 if (TARGET_CMODEL
!= CMODEL_SMALL
8357 && GET_CODE (y
) == LO_SUM
)
8361 if (GET_CODE (y
) == PLUS
8362 && GET_MODE (y
) == Pmode
8363 && CONST_INT_P (XEXP (y
, 1)))
8365 offset
= XEXP (y
, 1);
8369 if (GET_CODE (y
) == UNSPEC
8370 && XINT (y
, 1) == UNSPEC_TOCREL
)
8372 y
= XVECEXP (y
, 0, 0);
8375 /* Do not associate thread-local symbols with the original
8376 constant pool symbol. */
8378 && GET_CODE (y
) == SYMBOL_REF
8379 && CONSTANT_POOL_ADDRESS_P (y
)
8380 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
8384 if (offset
!= NULL_RTX
)
8385 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
8386 if (!MEM_P (orig_x
))
8389 return replace_equiv_address_nv (orig_x
, y
);
8393 && GET_CODE (orig_x
) == LO_SUM
8394 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
8396 y
= XEXP (XEXP (orig_x
, 1), 0);
8397 if (GET_CODE (y
) == UNSPEC
8398 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
8399 return XVECEXP (y
, 0, 0);
8405 /* Return true if X shouldn't be emitted into the debug info.
8406 The linker doesn't like .toc section references from
8407 .debug_* sections, so reject .toc section symbols. */
8410 rs6000_const_not_ok_for_debug_p (rtx x
)
8412 if (GET_CODE (x
) == UNSPEC
)
8414 if (GET_CODE (x
) == SYMBOL_REF
8415 && CONSTANT_POOL_ADDRESS_P (x
))
8417 rtx c
= get_pool_constant (x
);
8418 machine_mode cmode
= get_pool_mode (x
);
8419 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
8426 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8429 rs6000_legitimate_combined_insn (rtx_insn
*insn
)
8431 int icode
= INSN_CODE (insn
);
8433 /* Reject creating doloop insns. Combine should not be allowed
8434 to create these for a number of reasons:
8435 1) In a nested loop, if combine creates one of these in an
8436 outer loop and the register allocator happens to allocate ctr
8437 to the outer loop insn, then the inner loop can't use ctr.
8438 Inner loops ought to be more highly optimized.
8439 2) Combine often wants to create one of these from what was
8440 originally a three insn sequence, first combining the three
8441 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8442 allocated ctr, the splitter takes use back to the three insn
8443 sequence. It's better to stop combine at the two insn
8445 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8446 insns, the register allocator sometimes uses floating point
8447 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8448 jump insn and output reloads are not implemented for jumps,
8449 the ctrsi/ctrdi splitters need to handle all possible cases.
8450 That's a pain, and it gets to be seriously difficult when a
8451 splitter that runs after reload needs memory to transfer from
8452 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8453 for the difficult case. It's better to not create problems
8454 in the first place. */
8455 if (icode
!= CODE_FOR_nothing
8456 && (icode
== CODE_FOR_bdz_si
8457 || icode
== CODE_FOR_bdz_di
8458 || icode
== CODE_FOR_bdnz_si
8459 || icode
== CODE_FOR_bdnz_di
8460 || icode
== CODE_FOR_bdztf_si
8461 || icode
== CODE_FOR_bdztf_di
8462 || icode
== CODE_FOR_bdnztf_si
8463 || icode
== CODE_FOR_bdnztf_di
))
8469 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8471 static GTY(()) rtx rs6000_tls_symbol
;
8473 rs6000_tls_get_addr (void)
8475 if (!rs6000_tls_symbol
)
8476 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
8478 return rs6000_tls_symbol
;
8481 /* Construct the SYMBOL_REF for TLS GOT references. */
8483 static GTY(()) rtx rs6000_got_symbol
;
8485 rs6000_got_sym (void)
8487 if (!rs6000_got_symbol
)
8489 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8490 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
8491 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
8494 return rs6000_got_symbol
;
8497 /* AIX Thread-Local Address support. */
8500 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
8502 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
8506 name
= XSTR (addr
, 0);
8507 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8508 or the symbol will be in TLS private data section. */
8509 if (name
[strlen (name
) - 1] != ']'
8510 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
8511 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
8513 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
8514 strcpy (tlsname
, name
);
8516 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
8517 tlsaddr
= copy_rtx (addr
);
8518 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
8523 /* Place addr into TOC constant pool. */
8524 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
8526 /* Output the TOC entry and create the MEM referencing the value. */
8527 if (constant_pool_expr_p (XEXP (sym
, 0))
8528 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
8530 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
8531 mem
= gen_const_mem (Pmode
, tocref
);
8532 set_mem_alias_set (mem
, get_TOC_alias_set ());
8537 /* Use global-dynamic for local-dynamic. */
8538 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
8539 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
8541 /* Create new TOC reference for @m symbol. */
8542 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
8543 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
8544 strcpy (tlsname
, "*LCM");
8545 strcat (tlsname
, name
+ 3);
8546 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
8547 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
8548 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
8549 rtx modmem
= gen_const_mem (Pmode
, tocref
);
8550 set_mem_alias_set (modmem
, get_TOC_alias_set ());
8552 rtx modreg
= gen_reg_rtx (Pmode
);
8553 emit_insn (gen_rtx_SET (modreg
, modmem
));
8555 tmpreg
= gen_reg_rtx (Pmode
);
8556 emit_insn (gen_rtx_SET (tmpreg
, mem
));
8558 dest
= gen_reg_rtx (Pmode
);
8560 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
8562 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
8565 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8566 else if (TARGET_32BIT
)
8568 tlsreg
= gen_reg_rtx (SImode
);
8569 emit_insn (gen_tls_get_tpointer (tlsreg
));
8572 tlsreg
= gen_rtx_REG (DImode
, 13);
8574 /* Load the TOC value into temporary register. */
8575 tmpreg
= gen_reg_rtx (Pmode
);
8576 emit_insn (gen_rtx_SET (tmpreg
, mem
));
8577 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
8578 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
8580 /* Add TOC symbol value to TLS pointer. */
8581 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
8586 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8587 this (thread-local) address. */
8590 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
8595 return rs6000_legitimize_tls_address_aix (addr
, model
);
8597 dest
= gen_reg_rtx (Pmode
);
8598 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
8604 tlsreg
= gen_rtx_REG (Pmode
, 13);
8605 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
8609 tlsreg
= gen_rtx_REG (Pmode
, 2);
8610 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
8614 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
8618 tmp
= gen_reg_rtx (Pmode
);
8621 tlsreg
= gen_rtx_REG (Pmode
, 13);
8622 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
8626 tlsreg
= gen_rtx_REG (Pmode
, 2);
8627 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
8631 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
8633 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
8638 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
8640 /* We currently use relocations like @got@tlsgd for tls, which
8641 means the linker will handle allocation of tls entries, placing
8642 them in the .got section. So use a pointer to the .got section,
8643 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8644 or to secondary GOT sections used by 32-bit -fPIC. */
8646 got
= gen_rtx_REG (Pmode
, 2);
8650 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
8653 rtx gsym
= rs6000_got_sym ();
8654 got
= gen_reg_rtx (Pmode
);
8656 rs6000_emit_move (got
, gsym
, Pmode
);
8661 tmp1
= gen_reg_rtx (Pmode
);
8662 tmp2
= gen_reg_rtx (Pmode
);
8663 mem
= gen_const_mem (Pmode
, tmp1
);
8664 lab
= gen_label_rtx ();
8665 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
8666 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
8667 if (TARGET_LINK_STACK
)
8668 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
8669 emit_move_insn (tmp2
, mem
);
8670 rtx_insn
*last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
8671 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
8676 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
8678 tga
= rs6000_tls_get_addr ();
8679 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
8682 r3
= gen_rtx_REG (Pmode
, 3);
8683 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
8686 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
8688 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
8690 else if (DEFAULT_ABI
== ABI_V4
)
8691 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
8694 call_insn
= last_call_insn ();
8695 PATTERN (call_insn
) = insn
;
8696 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
8697 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
8698 pic_offset_table_rtx
);
8700 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
8702 tga
= rs6000_tls_get_addr ();
8703 tmp1
= gen_reg_rtx (Pmode
);
8704 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
8707 r3
= gen_rtx_REG (Pmode
, 3);
8708 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
8711 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
8713 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
8715 else if (DEFAULT_ABI
== ABI_V4
)
8716 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
8719 call_insn
= last_call_insn ();
8720 PATTERN (call_insn
) = insn
;
8721 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
8722 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
8723 pic_offset_table_rtx
);
8725 if (rs6000_tls_size
== 16)
8728 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
8730 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
8732 else if (rs6000_tls_size
== 32)
8734 tmp2
= gen_reg_rtx (Pmode
);
8736 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
8738 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
8741 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
8743 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
8747 tmp2
= gen_reg_rtx (Pmode
);
8749 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
8751 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
8753 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
8759 /* IE, or 64-bit offset LE. */
8760 tmp2
= gen_reg_rtx (Pmode
);
8762 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
8764 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
8767 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
8769 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
8777 /* Only create the global variable for the stack protect guard if we are using
8778 the global flavor of that guard. */
8780 rs6000_init_stack_protect_guard (void)
8782 if (rs6000_stack_protector_guard
== SSP_GLOBAL
)
8783 return default_stack_protect_guard ();
8788 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8791 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
8793 if (GET_CODE (x
) == HIGH
8794 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
8797 /* A TLS symbol in the TOC cannot contain a sum. */
8798 if (GET_CODE (x
) == CONST
8799 && GET_CODE (XEXP (x
, 0)) == PLUS
8800 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
8801 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
8804 /* Do not place an ELF TLS symbol in the constant pool. */
8805 return TARGET_ELF
&& tls_referenced_p (x
);
8808 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8809 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8810 can be addressed relative to the toc pointer. */
8813 use_toc_relative_ref (rtx sym
, machine_mode mode
)
8815 return ((constant_pool_expr_p (sym
)
8816 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
8817 get_pool_mode (sym
)))
8818 || (TARGET_CMODEL
== CMODEL_MEDIUM
8819 && SYMBOL_REF_LOCAL_P (sym
)
8820 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
8823 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
8824 replace the input X, or the original X if no replacement is called for.
8825 The output parameter *WIN is 1 if the calling macro should goto WIN,
8828 For RS/6000, we wish to handle large displacements off a base
8829 register by splitting the addend across an addiu/addis and the mem insn.
8830 This cuts number of extra insns needed from 3 to 1.
8832 On Darwin, we use this to generate code for floating point constants.
8833 A movsf_low is generated so we wind up with 2 instructions rather than 3.
8834 The Darwin code is inside #if TARGET_MACHO because only then are the
8835 machopic_* functions defined. */
8837 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
8838 int opnum
, int type
,
8839 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
8841 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
8842 bool quad_offset_p
= mode_supports_dq_form (mode
);
8844 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
8845 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
8848 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
8849 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)
8850 || (mode
== SFmode
&& recog_data
.operand_mode
[0] == V4SFmode
8851 && TARGET_P9_VECTOR
)
8852 || (mode
== SImode
&& recog_data
.operand_mode
[0] == V4SImode
8853 && TARGET_P9_VECTOR
)))
8854 reg_offset_p
= false;
8856 /* We must recognize output that we have already generated ourselves. */
8857 if (GET_CODE (x
) == PLUS
8858 && GET_CODE (XEXP (x
, 0)) == PLUS
8859 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
8860 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
8861 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8863 if (TARGET_DEBUG_ADDR
)
8865 fprintf (stderr
, "\nlegitimize_reload_address push_reload #1:\n");
8868 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8869 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
8870 opnum
, (enum reload_type
) type
);
8875 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
8876 if (GET_CODE (x
) == LO_SUM
8877 && GET_CODE (XEXP (x
, 0)) == HIGH
)
8879 if (TARGET_DEBUG_ADDR
)
8881 fprintf (stderr
, "\nlegitimize_reload_address push_reload #2:\n");
8884 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8885 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8886 opnum
, (enum reload_type
) type
);
8892 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
8893 && GET_CODE (x
) == LO_SUM
8894 && GET_CODE (XEXP (x
, 0)) == PLUS
8895 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
8896 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
8897 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
8898 && machopic_operand_p (XEXP (x
, 1)))
8900 /* Result of previous invocation of this function on Darwin
8901 floating point constant. */
8902 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8903 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8904 opnum
, (enum reload_type
) type
);
8910 if (TARGET_CMODEL
!= CMODEL_SMALL
8913 && small_toc_ref (x
, VOIDmode
))
8915 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
8916 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
8917 if (TARGET_DEBUG_ADDR
)
8919 fprintf (stderr
, "\nlegitimize_reload_address push_reload #3:\n");
8922 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8923 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8924 opnum
, (enum reload_type
) type
);
8929 if (GET_CODE (x
) == PLUS
8930 && REG_P (XEXP (x
, 0))
8931 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
8932 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
8933 && CONST_INT_P (XEXP (x
, 1))
8935 && (quad_offset_p
|| !VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
8937 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
8938 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
8940 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8942 /* Check for 32-bit overflow or quad addresses with one of the
8943 four least significant bits set. */
8944 if (high
+ low
!= val
8945 || (quad_offset_p
&& (low
& 0xf)))
8951 /* Reload the high part into a base reg; leave the low part
8952 in the mem directly. */
8954 x
= gen_rtx_PLUS (GET_MODE (x
),
8955 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
8959 if (TARGET_DEBUG_ADDR
)
8961 fprintf (stderr
, "\nlegitimize_reload_address push_reload #4:\n");
8964 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8965 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
8966 opnum
, (enum reload_type
) type
);
8971 if (GET_CODE (x
) == SYMBOL_REF
8974 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
8976 && DEFAULT_ABI
== ABI_DARWIN
8977 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
8978 && machopic_symbol_defined_p (x
)
8980 && DEFAULT_ABI
== ABI_V4
8983 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
8984 The same goes for DImode without 64-bit gprs and DFmode and DDmode
8986 ??? Assume floating point reg based on mode? This assumption is
8987 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
8988 where reload ends up doing a DFmode load of a constant from
8989 mem using two gprs. Unfortunately, at this point reload
8990 hasn't yet selected regs so poking around in reload data
8991 won't help and even if we could figure out the regs reliably,
8992 we'd still want to allow this transformation when the mem is
8993 naturally aligned. Since we say the address is good here, we
8994 can't disable offsets from LO_SUMs in mem_operand_gpr.
8995 FIXME: Allow offset from lo_sum for other modes too, when
8996 mem is sufficiently aligned.
8998 Also disallow this if the type can go in VMX/Altivec registers, since
8999 those registers do not have d-form (reg+offset) address modes. */
9000 && !reg_addr
[mode
].scalar_in_vmx_p
9005 && (mode
!= TImode
|| !TARGET_VSX
)
9007 && (mode
!= DImode
|| TARGET_POWERPC64
)
9008 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
9009 || TARGET_HARD_FLOAT
))
9014 rtx offset
= machopic_gen_offset (x
);
9015 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9016 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
9017 gen_rtx_HIGH (Pmode
, offset
)), offset
);
9021 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9022 gen_rtx_HIGH (Pmode
, x
), x
);
9024 if (TARGET_DEBUG_ADDR
)
9026 fprintf (stderr
, "\nlegitimize_reload_address push_reload #5:\n");
9029 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9030 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9031 opnum
, (enum reload_type
) type
);
9036 /* Reload an offset address wrapped by an AND that represents the
9037 masking of the lower bits. Strip the outer AND and let reload
9038 convert the offset address into an indirect address. For VSX,
9039 force reload to create the address with an AND in a separate
9040 register, because we can't guarantee an altivec register will
9042 if (VECTOR_MEM_ALTIVEC_P (mode
)
9043 && GET_CODE (x
) == AND
9044 && GET_CODE (XEXP (x
, 0)) == PLUS
9045 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
9046 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
9047 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9048 && INTVAL (XEXP (x
, 1)) == -16)
9058 && GET_CODE (x
) == SYMBOL_REF
9059 && use_toc_relative_ref (x
, mode
))
9061 x
= create_TOC_reference (x
, NULL_RTX
);
9062 if (TARGET_CMODEL
!= CMODEL_SMALL
)
9064 if (TARGET_DEBUG_ADDR
)
9066 fprintf (stderr
, "\nlegitimize_reload_address push_reload #6:\n");
9069 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9070 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9071 opnum
, (enum reload_type
) type
);
9080 /* Debug version of rs6000_legitimize_reload_address. */
9082 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
9083 int opnum
, int type
,
9084 int ind_levels
, int *win
)
9086 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
9089 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9090 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9091 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
9095 fprintf (stderr
, "Same address returned\n");
9097 fprintf (stderr
, "NULL returned\n");
9100 fprintf (stderr
, "New address:\n");
9107 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9108 that is a valid memory address for an instruction.
9109 The MODE argument is the machine mode for the MEM expression
9110 that wants to use this address.
9112 On the RS/6000, there are four valid address: a SYMBOL_REF that
9113 refers to a constant pool entry of an address (or the sum of it
9114 plus a constant), a short (16-bit signed) constant plus a register,
9115 the sum of two registers, or a register indirect, possibly with an
9116 auto-increment. For DFmode, DDmode and DImode with a constant plus
9117 register, we must ensure that both words are addressable or PowerPC64
9118 with offset word aligned.
9120 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9121 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9122 because adjacent memory cells are accessed by adding word-sized offsets
9123 during assembly output. */
9125 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
9127 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
9128 bool quad_offset_p
= mode_supports_dq_form (mode
);
9130 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9131 if (VECTOR_MEM_ALTIVEC_P (mode
)
9132 && GET_CODE (x
) == AND
9133 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9134 && INTVAL (XEXP (x
, 1)) == -16)
9137 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
9139 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
9142 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
9143 && mode_supports_pre_incdec_p (mode
)
9144 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
9146 /* Handle restricted vector d-form offsets in ISA 3.0. */
9149 if (quad_address_p (x
, mode
, reg_ok_strict
))
9152 else if (virtual_stack_registers_memory_p (x
))
9155 else if (reg_offset_p
)
9157 if (legitimate_small_data_p (mode
, x
))
9159 if (legitimate_constant_pool_address_p (x
, mode
,
9160 reg_ok_strict
|| lra_in_progress
))
9164 /* For TImode, if we have TImode in VSX registers, only allow register
9165 indirect addresses. This will allow the values to go in either GPRs
9166 or VSX registers without reloading. The vector types would tend to
9167 go into VSX registers, so we allow REG+REG, while TImode seems
9168 somewhat split, in that some uses are GPR based, and some VSX based. */
9169 /* FIXME: We could loosen this by changing the following to
9170 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9171 but currently we cannot allow REG+REG addressing for TImode. See
9172 PR72827 for complete details on how this ends up hoodwinking DSE. */
9173 if (mode
== TImode
&& TARGET_VSX
)
9175 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9178 && GET_CODE (x
) == PLUS
9179 && GET_CODE (XEXP (x
, 0)) == REG
9180 && (XEXP (x
, 0) == virtual_stack_vars_rtx
9181 || XEXP (x
, 0) == arg_pointer_rtx
)
9182 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9184 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
9186 if (!FLOAT128_2REG_P (mode
)
9187 && (TARGET_HARD_FLOAT
9189 || (mode
!= DFmode
&& mode
!= DDmode
))
9190 && (TARGET_POWERPC64
|| mode
!= DImode
)
9191 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
9193 && !avoiding_indexed_address_p (mode
)
9194 && legitimate_indexed_address_p (x
, reg_ok_strict
))
9196 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
9197 && mode_supports_pre_modify_p (mode
)
9198 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
9199 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
9200 reg_ok_strict
, false)
9201 || (!avoiding_indexed_address_p (mode
)
9202 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
9203 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
9205 if (reg_offset_p
&& !quad_offset_p
9206 && legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
9211 /* Debug version of rs6000_legitimate_address_p. */
9213 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
9216 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
9218 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9219 "strict = %d, reload = %s, code = %s\n",
9220 ret
? "true" : "false",
9221 GET_MODE_NAME (mode
),
9223 (reload_completed
? "after" : "before"),
9224 GET_RTX_NAME (GET_CODE (x
)));
9230 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9233 rs6000_mode_dependent_address_p (const_rtx addr
,
9234 addr_space_t as ATTRIBUTE_UNUSED
)
9236 return rs6000_mode_dependent_address_ptr (addr
);
9239 /* Go to LABEL if ADDR (a legitimate address expression)
9240 has an effect that depends on the machine mode it is used for.
9242 On the RS/6000 this is true of all integral offsets (since AltiVec
9243 and VSX modes don't allow them) or is a pre-increment or decrement.
9245 ??? Except that due to conceptual problems in offsettable_address_p
9246 we can't really report the problems of integral offsets. So leave
9247 this assuming that the adjustable offset must be valid for the
9248 sub-words of a TFmode operand, which is what we had before. */
9251 rs6000_mode_dependent_address (const_rtx addr
)
9253 switch (GET_CODE (addr
))
9256 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9257 is considered a legitimate address before reload, so there
9258 are no offset restrictions in that case. Note that this
9259 condition is safe in strict mode because any address involving
9260 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9261 been rejected as illegitimate. */
9262 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
9263 && XEXP (addr
, 0) != arg_pointer_rtx
9264 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
9266 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
9267 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
9272 /* Anything in the constant pool is sufficiently aligned that
9273 all bytes have the same high part address. */
9274 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
9276 /* Auto-increment cases are now treated generically in recog.c. */
9278 return TARGET_UPDATE
;
9280 /* AND is only allowed in Altivec loads. */
9291 /* Debug version of rs6000_mode_dependent_address. */
9293 rs6000_debug_mode_dependent_address (const_rtx addr
)
9295 bool ret
= rs6000_mode_dependent_address (addr
);
9297 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
9298 ret
? "true" : "false");
9304 /* Implement FIND_BASE_TERM. */
9307 rs6000_find_base_term (rtx op
)
9312 if (GET_CODE (base
) == CONST
)
9313 base
= XEXP (base
, 0);
9314 if (GET_CODE (base
) == PLUS
)
9315 base
= XEXP (base
, 0);
9316 if (GET_CODE (base
) == UNSPEC
)
9317 switch (XINT (base
, 1))
9320 case UNSPEC_MACHOPIC_OFFSET
:
9321 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9322 for aliasing purposes. */
9323 return XVECEXP (base
, 0, 0);
9329 /* More elaborate version of recog's offsettable_memref_p predicate
9330 that works around the ??? note of rs6000_mode_dependent_address.
9331 In particular it accepts
9333 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9335 in 32-bit mode, that the recog predicate rejects. */
9338 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
, bool strict
)
9345 /* First mimic offsettable_memref_p. */
9346 if (offsettable_address_p (strict
, GET_MODE (op
), XEXP (op
, 0)))
9349 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9350 the latter predicate knows nothing about the mode of the memory
9351 reference and, therefore, assumes that it is the largest supported
9352 mode (TFmode). As a consequence, legitimate offsettable memory
9353 references are rejected. rs6000_legitimate_offset_address_p contains
9354 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9355 at least with a little bit of help here given that we know the
9356 actual registers used. */
9357 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
9358 || GET_MODE_SIZE (reg_mode
) == 4);
9359 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
9360 strict
, worst_case
);
9363 /* Determine the reassociation width to be used in reassociate_bb.
9364 This takes into account how many parallel operations we
9365 can actually do of a given type, and also the latency.
9369 vect add/sub/mul 2/cycle
9370 fp add/sub/mul 2/cycle
9375 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
9378 switch (rs6000_tune
)
9380 case PROCESSOR_POWER8
:
9381 case PROCESSOR_POWER9
:
9382 if (DECIMAL_FLOAT_MODE_P (mode
))
9384 if (VECTOR_MODE_P (mode
))
9386 if (INTEGRAL_MODE_P (mode
))
9388 if (FLOAT_MODE_P (mode
))
9397 /* Change register usage conditional on target flags. */
9399 rs6000_conditional_register_usage (void)
9403 if (TARGET_DEBUG_TARGET
)
9404 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
9406 /* Set MQ register fixed (already call_used) so that it will not be
9410 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9412 fixed_regs
[13] = call_used_regs
[13]
9413 = call_really_used_regs
[13] = 1;
9415 /* Conditionally disable FPRs. */
9416 if (TARGET_SOFT_FLOAT
)
9417 for (i
= 32; i
< 64; i
++)
9418 fixed_regs
[i
] = call_used_regs
[i
]
9419 = call_really_used_regs
[i
] = 1;
9421 /* The TOC register is not killed across calls in a way that is
9422 visible to the compiler. */
9423 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9424 call_really_used_regs
[2] = 0;
9426 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
9427 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9429 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
9430 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9431 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9432 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9434 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
9435 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9436 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9437 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9439 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
9440 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9441 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9443 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
9445 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
9446 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9447 call_really_used_regs
[VRSAVE_REGNO
] = 1;
9450 if (TARGET_ALTIVEC
|| TARGET_VSX
)
9451 global_regs
[VSCR_REGNO
] = 1;
9453 if (TARGET_ALTIVEC_ABI
)
9455 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
9456 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9458 /* AIX reserves VR20:31 in non-extended ABI mode. */
9460 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
9461 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9466 /* Output insns to set DEST equal to the constant SOURCE as a series of
9467 lis, ori and shl instructions and return TRUE. */
9470 rs6000_emit_set_const (rtx dest
, rtx source
)
9472 machine_mode mode
= GET_MODE (dest
);
9477 gcc_checking_assert (CONST_INT_P (source
));
9478 c
= INTVAL (source
);
9483 emit_insn (gen_rtx_SET (dest
, source
));
9487 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
9489 emit_insn (gen_rtx_SET (copy_rtx (temp
),
9490 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
9491 emit_insn (gen_rtx_SET (dest
,
9492 gen_rtx_IOR (SImode
, copy_rtx (temp
),
9493 GEN_INT (c
& 0xffff))));
9497 if (!TARGET_POWERPC64
)
9501 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
9503 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
9505 emit_move_insn (hi
, GEN_INT (c
>> 32));
9506 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
9507 emit_move_insn (lo
, GEN_INT (c
));
9510 rs6000_emit_set_long_const (dest
, c
);
9517 insn
= get_last_insn ();
9518 set
= single_set (insn
);
9519 if (! CONSTANT_P (SET_SRC (set
)))
9520 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
9525 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9526 Output insns to set DEST equal to the constant C as a series of
9527 lis, ori and shl instructions. */
9530 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
9533 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
9543 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
9544 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
9545 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
9547 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
9548 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
9550 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9552 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9553 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
9555 emit_move_insn (dest
,
9556 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9559 else if (ud3
== 0 && ud4
== 0)
9561 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9563 gcc_assert (ud2
& 0x8000);
9564 emit_move_insn (copy_rtx (temp
),
9565 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
9567 emit_move_insn (copy_rtx (temp
),
9568 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9570 emit_move_insn (dest
,
9571 gen_rtx_ZERO_EXTEND (DImode
,
9572 gen_lowpart (SImode
,
9575 else if ((ud4
== 0xffff && (ud3
& 0x8000))
9576 || (ud4
== 0 && ! (ud3
& 0x8000)))
9578 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9580 emit_move_insn (copy_rtx (temp
),
9581 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
9583 emit_move_insn (copy_rtx (temp
),
9584 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9586 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9587 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
9590 emit_move_insn (dest
,
9591 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9596 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9598 emit_move_insn (copy_rtx (temp
),
9599 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
9601 emit_move_insn (copy_rtx (temp
),
9602 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9605 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
9606 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
9609 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9610 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9611 GEN_INT (ud2
<< 16)));
9613 emit_move_insn (dest
,
9614 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9619 /* Helper for the following. Get rid of [r+r] memory refs
9620 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9623 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
9625 if (GET_CODE (operands
[0]) == MEM
9626 && GET_CODE (XEXP (operands
[0], 0)) != REG
9627 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
9628 GET_MODE (operands
[0]), false))
9630 = replace_equiv_address (operands
[0],
9631 copy_addr_to_reg (XEXP (operands
[0], 0)));
9633 if (GET_CODE (operands
[1]) == MEM
9634 && GET_CODE (XEXP (operands
[1], 0)) != REG
9635 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
9636 GET_MODE (operands
[1]), false))
9638 = replace_equiv_address (operands
[1],
9639 copy_addr_to_reg (XEXP (operands
[1], 0)));
9642 /* Generate a vector of constants to permute MODE for a little-endian
9643 storage operation by swapping the two halves of a vector. */
9645 rs6000_const_vec (machine_mode mode
)
9673 v
= rtvec_alloc (subparts
);
9675 for (i
= 0; i
< subparts
/ 2; ++i
)
9676 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
9677 for (i
= subparts
/ 2; i
< subparts
; ++i
)
9678 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
9683 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9686 rs6000_emit_le_vsx_permute (rtx dest
, rtx source
, machine_mode mode
)
9688 /* Scalar permutations are easier to express in integer modes rather than
9689 floating-point modes, so cast them here. We use V1TImode instead
9690 of TImode to ensure that the values don't go through GPRs. */
9691 if (FLOAT128_VECTOR_P (mode
))
9693 dest
= gen_lowpart (V1TImode
, dest
);
9694 source
= gen_lowpart (V1TImode
, source
);
9698 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9700 if (mode
== TImode
|| mode
== V1TImode
)
9701 emit_insn (gen_rtx_SET (dest
, gen_rtx_ROTATE (mode
, source
,
9705 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
9706 emit_insn (gen_rtx_SET (dest
, gen_rtx_VEC_SELECT (mode
, source
, par
)));
9710 /* Emit a little-endian load from vector memory location SOURCE to VSX
9711 register DEST in mode MODE. The load is done with two permuting
9712 insn's that represent an lxvd2x and xxpermdi. */
9714 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
9716 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9718 if (mode
== TImode
|| mode
== V1TImode
)
9721 dest
= gen_lowpart (V2DImode
, dest
);
9722 source
= adjust_address (source
, V2DImode
, 0);
9725 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
9726 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
9727 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
9730 /* Emit a little-endian store to vector memory location DEST from VSX
9731 register SOURCE in mode MODE. The store is done with two permuting
9732 insn's that represent an xxpermdi and an stxvd2x. */
9734 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
9736 /* This should never be called during or after LRA, because it does
9737 not re-permute the source register. It is intended only for use
9739 gcc_assert (!lra_in_progress
&& !reload_completed
);
9741 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9743 if (mode
== TImode
|| mode
== V1TImode
)
9746 dest
= adjust_address (dest
, V2DImode
, 0);
9747 source
= gen_lowpart (V2DImode
, source
);
9750 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
9751 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
9752 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
9755 /* Emit a sequence representing a little-endian VSX load or store,
9756 moving data from SOURCE to DEST in mode MODE. This is done
9757 separately from rs6000_emit_move to ensure it is called only
9758 during expand. LE VSX loads and stores introduced later are
9759 handled with a split. The expand-time RTL generation allows
9760 us to optimize away redundant pairs of register-permutes. */
9762 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
9764 gcc_assert (!BYTES_BIG_ENDIAN
9765 && VECTOR_MEM_VSX_P (mode
)
9766 && !TARGET_P9_VECTOR
9767 && !gpr_or_gpr_p (dest
, source
)
9768 && (MEM_P (source
) ^ MEM_P (dest
)));
9772 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
9773 rs6000_emit_le_vsx_load (dest
, source
, mode
);
9777 if (!REG_P (source
))
9778 source
= force_reg (mode
, source
);
9779 rs6000_emit_le_vsx_store (dest
, source
, mode
);
9783 /* Return whether a SFmode or SImode move can be done without converting one
9784 mode to another. This arrises when we have:
9786 (SUBREG:SF (REG:SI ...))
9787 (SUBREG:SI (REG:SF ...))
9789 and one of the values is in a floating point/vector register, where SFmode
9790 scalars are stored in DFmode format. */
9793 valid_sf_si_move (rtx dest
, rtx src
, machine_mode mode
)
9795 if (TARGET_ALLOW_SF_SUBREG
)
9798 if (mode
!= SFmode
&& GET_MODE_CLASS (mode
) != MODE_INT
)
9801 if (!SUBREG_P (src
) || !sf_subreg_operand (src
, mode
))
9804 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9805 if (SUBREG_P (dest
))
9807 rtx dest_subreg
= SUBREG_REG (dest
);
9808 rtx src_subreg
= SUBREG_REG (src
);
9809 return GET_MODE (dest_subreg
) == GET_MODE (src_subreg
);
9816 /* Helper function to change moves with:
9818 (SUBREG:SF (REG:SI)) and
9819 (SUBREG:SI (REG:SF))
9821 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9822 values are stored as DFmode values in the VSX registers. We need to convert
9823 the bits before we can use a direct move or operate on the bits in the
9824 vector register as an integer type.
9826 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9829 rs6000_emit_move_si_sf_subreg (rtx dest
, rtx source
, machine_mode mode
)
9831 if (TARGET_DIRECT_MOVE_64BIT
&& !lra_in_progress
&& !reload_completed
9832 && (!SUBREG_P (dest
) || !sf_subreg_operand (dest
, mode
))
9833 && SUBREG_P (source
) && sf_subreg_operand (source
, mode
))
9835 rtx inner_source
= SUBREG_REG (source
);
9836 machine_mode inner_mode
= GET_MODE (inner_source
);
9838 if (mode
== SImode
&& inner_mode
== SFmode
)
9840 emit_insn (gen_movsi_from_sf (dest
, inner_source
));
9844 if (mode
== SFmode
&& inner_mode
== SImode
)
9846 emit_insn (gen_movsf_from_si (dest
, inner_source
));
9854 /* Emit a move from SOURCE to DEST in mode MODE. */
9856 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
9860 operands
[1] = source
;
9862 if (TARGET_DEBUG_ADDR
)
9865 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9866 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9867 GET_MODE_NAME (mode
),
9870 can_create_pseudo_p ());
9872 fprintf (stderr
, "source:\n");
9876 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
9877 if (CONST_WIDE_INT_P (operands
[1])
9878 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9880 /* This should be fixed with the introduction of CONST_WIDE_INT. */
9884 #ifdef HAVE_AS_GNU_ATTRIBUTE
9885 /* If we use a long double type, set the flags in .gnu_attribute that say
9886 what the long double type is. This is to allow the linker's warning
9887 message for the wrong long double to be useful, even if the function does
9888 not do a call (for example, doing a 128-bit add on power9 if the long
9889 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9890 used if they aren't the default long dobule type. */
9891 if (rs6000_gnu_attr
&& (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
))
9893 if (TARGET_LONG_DOUBLE_128
&& (mode
== TFmode
|| mode
== TCmode
))
9894 rs6000_passes_float
= rs6000_passes_long_double
= true;
9896 else if (!TARGET_LONG_DOUBLE_128
&& (mode
== DFmode
|| mode
== DCmode
))
9897 rs6000_passes_float
= rs6000_passes_long_double
= true;
9901 /* See if we need to special case SImode/SFmode SUBREG moves. */
9902 if ((mode
== SImode
|| mode
== SFmode
) && SUBREG_P (source
)
9903 && rs6000_emit_move_si_sf_subreg (dest
, source
, mode
))
9906 /* Check if GCC is setting up a block move that will end up using FP
9907 registers as temporaries. We must make sure this is acceptable. */
9908 if (GET_CODE (operands
[0]) == MEM
9909 && GET_CODE (operands
[1]) == MEM
9911 && (rs6000_slow_unaligned_access (DImode
, MEM_ALIGN (operands
[0]))
9912 || rs6000_slow_unaligned_access (DImode
, MEM_ALIGN (operands
[1])))
9913 && ! (rs6000_slow_unaligned_access (SImode
,
9914 (MEM_ALIGN (operands
[0]) > 32
9915 ? 32 : MEM_ALIGN (operands
[0])))
9916 || rs6000_slow_unaligned_access (SImode
,
9917 (MEM_ALIGN (operands
[1]) > 32
9918 ? 32 : MEM_ALIGN (operands
[1]))))
9919 && ! MEM_VOLATILE_P (operands
[0])
9920 && ! MEM_VOLATILE_P (operands
[1]))
9922 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
9923 adjust_address (operands
[1], SImode
, 0));
9924 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
9925 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
9929 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
9930 && !gpc_reg_operand (operands
[1], mode
))
9931 operands
[1] = force_reg (mode
, operands
[1]);
9933 /* Recognize the case where operand[1] is a reference to thread-local
9934 data and load its address to a register. */
9935 if (tls_referenced_p (operands
[1]))
9937 enum tls_model model
;
9938 rtx tmp
= operands
[1];
9941 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
9943 addend
= XEXP (XEXP (tmp
, 0), 1);
9944 tmp
= XEXP (XEXP (tmp
, 0), 0);
9947 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
9948 model
= SYMBOL_REF_TLS_MODEL (tmp
);
9949 gcc_assert (model
!= 0);
9951 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
9954 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
9955 tmp
= force_operand (tmp
, operands
[0]);
9960 /* 128-bit constant floating-point values on Darwin should really be loaded
9961 as two parts. However, this premature splitting is a problem when DFmode
9962 values can go into Altivec registers. */
9963 if (FLOAT128_IBM_P (mode
) && !reg_addr
[DFmode
].scalar_in_vmx_p
9964 && GET_CODE (operands
[1]) == CONST_DOUBLE
)
9966 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
9967 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
9969 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
9970 GET_MODE_SIZE (DFmode
)),
9971 simplify_gen_subreg (DFmode
, operands
[1], mode
,
9972 GET_MODE_SIZE (DFmode
)),
9977 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9978 p1:SD) if p1 is not of floating point class and p0 is spilled as
9979 we can have no analogous movsd_store for this. */
9980 if (lra_in_progress
&& mode
== DDmode
9981 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
9982 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
9983 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
9984 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
9987 int regno
= REGNO (SUBREG_REG (operands
[1]));
9989 if (regno
>= FIRST_PSEUDO_REGISTER
)
9991 cl
= reg_preferred_class (regno
);
9992 regno
= reg_renumber
[regno
];
9994 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
9996 if (regno
>= 0 && ! FP_REGNO_P (regno
))
9999 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
10000 operands
[1] = SUBREG_REG (operands
[1]);
10003 if (lra_in_progress
10005 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
10006 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10007 && (REG_P (operands
[1])
10008 || (GET_CODE (operands
[1]) == SUBREG
10009 && REG_P (SUBREG_REG (operands
[1])))))
10011 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
10012 ? SUBREG_REG (operands
[1]) : operands
[1]);
10015 if (regno
>= FIRST_PSEUDO_REGISTER
)
10017 cl
= reg_preferred_class (regno
);
10018 gcc_assert (cl
!= NO_REGS
);
10019 regno
= reg_renumber
[regno
];
10021 regno
= ira_class_hard_regs
[cl
][0];
10023 if (FP_REGNO_P (regno
))
10025 if (GET_MODE (operands
[0]) != DDmode
)
10026 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
10027 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
10029 else if (INT_REGNO_P (regno
))
10030 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10035 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10036 p:DD)) if p0 is not of floating point class and p1 is spilled as
10037 we can have no analogous movsd_load for this. */
10038 if (lra_in_progress
&& mode
== DDmode
10039 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
10040 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
10041 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10042 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10045 int regno
= REGNO (SUBREG_REG (operands
[0]));
10047 if (regno
>= FIRST_PSEUDO_REGISTER
)
10049 cl
= reg_preferred_class (regno
);
10050 regno
= reg_renumber
[regno
];
10052 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
10054 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10057 operands
[0] = SUBREG_REG (operands
[0]);
10058 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
10061 if (lra_in_progress
10063 && (REG_P (operands
[0])
10064 || (GET_CODE (operands
[0]) == SUBREG
10065 && REG_P (SUBREG_REG (operands
[0]))))
10066 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10067 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10069 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
10070 ? SUBREG_REG (operands
[0]) : operands
[0]);
10073 if (regno
>= FIRST_PSEUDO_REGISTER
)
10075 cl
= reg_preferred_class (regno
);
10076 gcc_assert (cl
!= NO_REGS
);
10077 regno
= reg_renumber
[regno
];
10079 regno
= ira_class_hard_regs
[cl
][0];
10081 if (FP_REGNO_P (regno
))
10083 if (GET_MODE (operands
[1]) != DDmode
)
10084 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
10085 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
10087 else if (INT_REGNO_P (regno
))
10088 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10094 /* FIXME: In the long term, this switch statement should go away
10095 and be replaced by a sequence of tests based on things like
10101 if (CONSTANT_P (operands
[1])
10102 && GET_CODE (operands
[1]) != CONST_INT
)
10103 operands
[1] = force_const_mem (mode
, operands
[1]);
10110 if (FLOAT128_2REG_P (mode
))
10111 rs6000_eliminate_indexed_memrefs (operands
);
10118 if (CONSTANT_P (operands
[1])
10119 && ! easy_fp_constant (operands
[1], mode
))
10120 operands
[1] = force_const_mem (mode
, operands
[1]);
10130 if (CONSTANT_P (operands
[1])
10131 && !easy_vector_constant (operands
[1], mode
))
10132 operands
[1] = force_const_mem (mode
, operands
[1]);
10137 /* Use default pattern for address of ELF small data */
10140 && DEFAULT_ABI
== ABI_V4
10141 && (GET_CODE (operands
[1]) == SYMBOL_REF
10142 || GET_CODE (operands
[1]) == CONST
)
10143 && small_data_operand (operands
[1], mode
))
10145 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10149 if (DEFAULT_ABI
== ABI_V4
10150 && mode
== Pmode
&& mode
== SImode
10151 && flag_pic
== 1 && got_operand (operands
[1], mode
))
10153 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
10157 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
10161 && CONSTANT_P (operands
[1])
10162 && GET_CODE (operands
[1]) != HIGH
10163 && GET_CODE (operands
[1]) != CONST_INT
)
10165 rtx target
= (!can_create_pseudo_p ()
10167 : gen_reg_rtx (mode
));
10169 /* If this is a function address on -mcall-aixdesc,
10170 convert it to the address of the descriptor. */
10171 if (DEFAULT_ABI
== ABI_AIX
10172 && GET_CODE (operands
[1]) == SYMBOL_REF
10173 && XSTR (operands
[1], 0)[0] == '.')
10175 const char *name
= XSTR (operands
[1], 0);
10177 while (*name
== '.')
10179 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
10180 CONSTANT_POOL_ADDRESS_P (new_ref
)
10181 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
10182 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
10183 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
10184 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
10185 operands
[1] = new_ref
;
10188 if (DEFAULT_ABI
== ABI_DARWIN
)
10191 if (MACHO_DYNAMIC_NO_PIC_P
)
10193 /* Take care of any required data indirection. */
10194 operands
[1] = rs6000_machopic_legitimize_pic_address (
10195 operands
[1], mode
, operands
[0]);
10196 if (operands
[0] != operands
[1])
10197 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10201 emit_insn (gen_macho_high (target
, operands
[1]));
10202 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
10206 emit_insn (gen_elf_high (target
, operands
[1]));
10207 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
10211 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10212 and we have put it in the TOC, we just need to make a TOC-relative
10213 reference to it. */
10215 && GET_CODE (operands
[1]) == SYMBOL_REF
10216 && use_toc_relative_ref (operands
[1], mode
))
10217 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
10218 else if (mode
== Pmode
10219 && CONSTANT_P (operands
[1])
10220 && GET_CODE (operands
[1]) != HIGH
10221 && ((GET_CODE (operands
[1]) != CONST_INT
10222 && ! easy_fp_constant (operands
[1], mode
))
10223 || (GET_CODE (operands
[1]) == CONST_INT
10224 && (num_insns_constant (operands
[1], mode
)
10225 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
10226 || (GET_CODE (operands
[0]) == REG
10227 && FP_REGNO_P (REGNO (operands
[0]))))
10228 && !toc_relative_expr_p (operands
[1], false, NULL
, NULL
)
10229 && (TARGET_CMODEL
== CMODEL_SMALL
10230 || can_create_pseudo_p ()
10231 || (REG_P (operands
[0])
10232 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
10236 /* Darwin uses a special PIC legitimizer. */
10237 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
10240 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
10242 if (operands
[0] != operands
[1])
10243 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10248 /* If we are to limit the number of things we put in the TOC and
10249 this is a symbol plus a constant we can add in one insn,
10250 just put the symbol in the TOC and add the constant. */
10251 if (GET_CODE (operands
[1]) == CONST
10252 && TARGET_NO_SUM_IN_TOC
10253 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
10254 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
10255 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
10256 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
10257 && ! side_effects_p (operands
[0]))
10260 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
10261 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
10263 sym
= force_reg (mode
, sym
);
10264 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
10268 operands
[1] = force_const_mem (mode
, operands
[1]);
10271 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
10272 && use_toc_relative_ref (XEXP (operands
[1], 0), mode
))
10274 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
10276 operands
[1] = gen_const_mem (mode
, tocref
);
10277 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
10283 if (!VECTOR_MEM_VSX_P (TImode
))
10284 rs6000_eliminate_indexed_memrefs (operands
);
10288 rs6000_eliminate_indexed_memrefs (operands
);
10292 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
10295 /* Above, we may have called force_const_mem which may have returned
10296 an invalid address. If we can, fix this up; otherwise, reload will
10297 have to deal with it. */
10298 if (GET_CODE (operands
[1]) == MEM
)
10299 operands
[1] = validize_mem (operands
[1]);
10301 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10304 /* Nonzero if we can use a floating-point register to pass this arg. */
10305 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10306 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10307 && (CUM)->fregno <= FP_ARG_MAX_REG \
10308 && TARGET_HARD_FLOAT)
10310 /* Nonzero if we can use an AltiVec register to pass this arg. */
10311 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10312 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10313 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10314 && TARGET_ALTIVEC_ABI \
10317 /* Walk down the type tree of TYPE counting consecutive base elements.
10318 If *MODEP is VOIDmode, then set it to the first valid floating point
10319 or vector type. If a non-floating point or vector type is found, or
10320 if a floating point or vector type that doesn't match a non-VOIDmode
10321 *MODEP is found, then return -1, otherwise return the count in the
10325 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
10328 HOST_WIDE_INT size
;
10330 switch (TREE_CODE (type
))
10333 mode
= TYPE_MODE (type
);
10334 if (!SCALAR_FLOAT_MODE_P (mode
))
10337 if (*modep
== VOIDmode
)
10340 if (*modep
== mode
)
10346 mode
= TYPE_MODE (TREE_TYPE (type
));
10347 if (!SCALAR_FLOAT_MODE_P (mode
))
10350 if (*modep
== VOIDmode
)
10353 if (*modep
== mode
)
10359 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
10362 /* Use V4SImode as representative of all 128-bit vector types. */
10363 size
= int_size_in_bytes (type
);
10373 if (*modep
== VOIDmode
)
10376 /* Vector modes are considered to be opaque: two vectors are
10377 equivalent for the purposes of being homogeneous aggregates
10378 if they are the same size. */
10379 if (*modep
== mode
)
10387 tree index
= TYPE_DOMAIN (type
);
10389 /* Can't handle incomplete types nor sizes that are not
10391 if (!COMPLETE_TYPE_P (type
)
10392 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10395 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
10398 || !TYPE_MAX_VALUE (index
)
10399 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
10400 || !TYPE_MIN_VALUE (index
)
10401 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
10405 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
10406 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
10408 /* There must be no padding. */
10409 if (wi::to_wide (TYPE_SIZE (type
))
10410 != count
* GET_MODE_BITSIZE (*modep
))
10422 /* Can't handle incomplete types nor sizes that are not
10424 if (!COMPLETE_TYPE_P (type
)
10425 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10428 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10430 if (TREE_CODE (field
) != FIELD_DECL
)
10433 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10436 count
+= sub_count
;
10439 /* There must be no padding. */
10440 if (wi::to_wide (TYPE_SIZE (type
))
10441 != count
* GET_MODE_BITSIZE (*modep
))
10448 case QUAL_UNION_TYPE
:
10450 /* These aren't very interesting except in a degenerate case. */
10455 /* Can't handle incomplete types nor sizes that are not
10457 if (!COMPLETE_TYPE_P (type
)
10458 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10461 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10463 if (TREE_CODE (field
) != FIELD_DECL
)
10466 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10469 count
= count
> sub_count
? count
: sub_count
;
10472 /* There must be no padding. */
10473 if (wi::to_wide (TYPE_SIZE (type
))
10474 != count
* GET_MODE_BITSIZE (*modep
))
10487 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10488 float or vector aggregate that shall be passed in FP/vector registers
10489 according to the ELFv2 ABI, return the homogeneous element mode in
10490 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10492 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10495 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
10496 machine_mode
*elt_mode
,
10499 /* Note that we do not accept complex types at the top level as
10500 homogeneous aggregates; these types are handled via the
10501 targetm.calls.split_complex_arg mechanism. Complex types
10502 can be elements of homogeneous aggregates, however. */
10503 if (TARGET_HARD_FLOAT
&& DEFAULT_ABI
== ABI_ELFv2
&& type
10504 && AGGREGATE_TYPE_P (type
))
10506 machine_mode field_mode
= VOIDmode
;
10507 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
10509 if (field_count
> 0)
10511 int reg_size
= ALTIVEC_OR_VSX_VECTOR_MODE (field_mode
) ? 16 : 8;
10512 int field_size
= ROUND_UP (GET_MODE_SIZE (field_mode
), reg_size
);
10514 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10515 up to AGGR_ARG_NUM_REG registers. */
10516 if (field_count
* field_size
<= AGGR_ARG_NUM_REG
* reg_size
)
10519 *elt_mode
= field_mode
;
10521 *n_elts
= field_count
;
10534 /* Return a nonzero value to say to return the function value in
10535 memory, just as large structures are always returned. TYPE will be
10536 the data type of the value, and FNTYPE will be the type of the
10537 function doing the returning, or @code{NULL} for libcalls.
10539 The AIX ABI for the RS/6000 specifies that all structures are
10540 returned in memory. The Darwin ABI does the same.
10542 For the Darwin 64 Bit ABI, a function result can be returned in
10543 registers or in memory, depending on the size of the return data
10544 type. If it is returned in registers, the value occupies the same
10545 registers as it would if it were the first and only function
10546 argument. Otherwise, the function places its result in memory at
10547 the location pointed to by GPR3.
10549 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10550 but a draft put them in memory, and GCC used to implement the draft
10551 instead of the final standard. Therefore, aix_struct_return
10552 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10553 compatibility can change DRAFT_V4_STRUCT_RET to override the
10554 default, and -m switches get the final word. See
10555 rs6000_option_override_internal for more details.
10557 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10558 long double support is enabled. These values are returned in memory.
10560 int_size_in_bytes returns -1 for variable size objects, which go in
10561 memory always. The cast to unsigned makes -1 > 8. */
10564 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
10566 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10568 && rs6000_darwin64_abi
10569 && TREE_CODE (type
) == RECORD_TYPE
10570 && int_size_in_bytes (type
) > 0)
10572 CUMULATIVE_ARGS valcum
;
10576 valcum
.fregno
= FP_ARG_MIN_REG
;
10577 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
10578 /* Do a trial code generation as if this were going to be passed
10579 as an argument; if any part goes in memory, we return NULL. */
10580 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
10583 /* Otherwise fall through to more conventional ABI rules. */
10586 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10587 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
10591 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10592 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
10593 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
10596 if (AGGREGATE_TYPE_P (type
)
10597 && (aix_struct_return
10598 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
10601 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10602 modes only exist for GCC vector types if -maltivec. */
10603 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
10604 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10607 /* Return synthetic vectors in memory. */
10608 if (TREE_CODE (type
) == VECTOR_TYPE
10609 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10611 static bool warned_for_return_big_vectors
= false;
10612 if (!warned_for_return_big_vectors
)
10614 warning (OPT_Wpsabi
, "GCC vector returned by reference: "
10615 "non-standard ABI extension with no compatibility "
10617 warned_for_return_big_vectors
= true;
10622 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
10623 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
10629 /* Specify whether values returned in registers should be at the most
10630 significant end of a register. We want aggregates returned by
10631 value to match the way aggregates are passed to functions. */
10634 rs6000_return_in_msb (const_tree valtype
)
10636 return (DEFAULT_ABI
== ABI_ELFv2
10637 && BYTES_BIG_ENDIAN
10638 && AGGREGATE_TYPE_P (valtype
)
10639 && (rs6000_function_arg_padding (TYPE_MODE (valtype
), valtype
)
10643 #ifdef HAVE_AS_GNU_ATTRIBUTE
10644 /* Return TRUE if a call to function FNDECL may be one that
10645 potentially affects the function calling ABI of the object file. */
10648 call_ABI_of_interest (tree fndecl
)
10650 if (rs6000_gnu_attr
&& symtab
->state
== EXPANSION
)
10652 struct cgraph_node
*c_node
;
10654 /* Libcalls are always interesting. */
10655 if (fndecl
== NULL_TREE
)
10658 /* Any call to an external function is interesting. */
10659 if (DECL_EXTERNAL (fndecl
))
10662 /* Interesting functions that we are emitting in this object file. */
10663 c_node
= cgraph_node::get (fndecl
);
10664 c_node
= c_node
->ultimate_alias_target ();
10665 return !c_node
->only_called_directly_p ();
10671 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10672 for a call to a function whose data type is FNTYPE.
10673 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10675 For incoming args we set the number of arguments in the prototype large
10676 so we never return a PARALLEL. */
10679 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
10680 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
10681 int libcall
, int n_named_args
,
10682 tree fndecl ATTRIBUTE_UNUSED
,
10683 machine_mode return_mode ATTRIBUTE_UNUSED
)
10685 static CUMULATIVE_ARGS zero_cumulative
;
10687 *cum
= zero_cumulative
;
10689 cum
->fregno
= FP_ARG_MIN_REG
;
10690 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
10691 cum
->prototype
= (fntype
&& prototype_p (fntype
));
10692 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
10693 ? CALL_LIBCALL
: CALL_NORMAL
);
10694 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
10695 cum
->stdarg
= stdarg_p (fntype
);
10696 cum
->libcall
= libcall
;
10698 cum
->nargs_prototype
= 0;
10699 if (incoming
|| cum
->prototype
)
10700 cum
->nargs_prototype
= n_named_args
;
10702 /* Check for a longcall attribute. */
10703 if ((!fntype
&& rs6000_default_long_calls
)
10705 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
10706 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
10707 cum
->call_cookie
|= CALL_LONG
;
10709 if (TARGET_DEBUG_ARG
)
10711 fprintf (stderr
, "\ninit_cumulative_args:");
10714 tree ret_type
= TREE_TYPE (fntype
);
10715 fprintf (stderr
, " ret code = %s,",
10716 get_tree_code_name (TREE_CODE (ret_type
)));
10719 if (cum
->call_cookie
& CALL_LONG
)
10720 fprintf (stderr
, " longcall,");
10722 fprintf (stderr
, " proto = %d, nargs = %d\n",
10723 cum
->prototype
, cum
->nargs_prototype
);
10726 #ifdef HAVE_AS_GNU_ATTRIBUTE
10727 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
))
10729 cum
->escapes
= call_ABI_of_interest (fndecl
);
10736 return_type
= TREE_TYPE (fntype
);
10737 return_mode
= TYPE_MODE (return_type
);
10740 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
10742 if (return_type
!= NULL
)
10744 if (TREE_CODE (return_type
) == RECORD_TYPE
10745 && TYPE_TRANSPARENT_AGGR (return_type
))
10747 return_type
= TREE_TYPE (first_field (return_type
));
10748 return_mode
= TYPE_MODE (return_type
);
10750 if (AGGREGATE_TYPE_P (return_type
)
10751 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
10753 rs6000_returns_struct
= true;
10755 if (SCALAR_FLOAT_MODE_P (return_mode
))
10757 rs6000_passes_float
= true;
10758 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
10759 && (FLOAT128_IBM_P (return_mode
)
10760 || FLOAT128_IEEE_P (return_mode
)
10761 || (return_type
!= NULL
10762 && (TYPE_MAIN_VARIANT (return_type
)
10763 == long_double_type_node
))))
10764 rs6000_passes_long_double
= true;
10766 /* Note if we passed or return a IEEE 128-bit type. We changed
10767 the mangling for these types, and we may need to make an alias
10768 with the old mangling. */
10769 if (FLOAT128_IEEE_P (return_mode
))
10770 rs6000_passes_ieee128
= true;
10772 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
))
10773 rs6000_passes_vector
= true;
10780 && TARGET_ALTIVEC_ABI
10781 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
10783 error ("cannot return value in vector register because"
10784 " altivec instructions are disabled, use %qs"
10785 " to enable them", "-maltivec");
10789 /* The mode the ABI uses for a word. This is not the same as word_mode
10790 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10792 static scalar_int_mode
10793 rs6000_abi_word_mode (void)
10795 return TARGET_32BIT
? SImode
: DImode
;
10798 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10800 rs6000_offload_options (void)
10803 return xstrdup ("-foffload-abi=lp64");
10805 return xstrdup ("-foffload-abi=ilp32");
10808 /* On rs6000, function arguments are promoted, as are function return
10811 static machine_mode
10812 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
10814 int *punsignedp ATTRIBUTE_UNUSED
,
10817 PROMOTE_MODE (mode
, *punsignedp
, type
);
10822 /* Return true if TYPE must be passed on the stack and not in registers. */
10825 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
10827 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
10828 return must_pass_in_stack_var_size (mode
, type
);
10830 return must_pass_in_stack_var_size_or_pad (mode
, type
);
10834 is_complex_IBM_long_double (machine_mode mode
)
10836 return mode
== ICmode
|| (mode
== TCmode
&& FLOAT128_IBM_P (TCmode
));
10839 /* Whether ABI_V4 passes MODE args to a function in floating point
10843 abi_v4_pass_in_fpr (machine_mode mode
, bool named
)
10845 if (!TARGET_HARD_FLOAT
)
10847 if (mode
== DFmode
)
10849 if (mode
== SFmode
&& named
)
10851 /* ABI_V4 passes complex IBM long double in 8 gprs.
10852 Stupid, but we can't change the ABI now. */
10853 if (is_complex_IBM_long_double (mode
))
10855 if (FLOAT128_2REG_P (mode
))
10857 if (DECIMAL_FLOAT_MODE_P (mode
))
10862 /* Implement TARGET_FUNCTION_ARG_PADDING.
10864 For the AIX ABI structs are always stored left shifted in their
10867 static pad_direction
10868 rs6000_function_arg_padding (machine_mode mode
, const_tree type
)
10870 #ifndef AGGREGATE_PADDING_FIXED
10871 #define AGGREGATE_PADDING_FIXED 0
10873 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10874 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10877 if (!AGGREGATE_PADDING_FIXED
)
10879 /* GCC used to pass structures of the same size as integer types as
10880 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10881 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10882 passed padded downward, except that -mstrict-align further
10883 muddied the water in that multi-component structures of 2 and 4
10884 bytes in size were passed padded upward.
10886 The following arranges for best compatibility with previous
10887 versions of gcc, but removes the -mstrict-align dependency. */
10888 if (BYTES_BIG_ENDIAN
)
10890 HOST_WIDE_INT size
= 0;
10892 if (mode
== BLKmode
)
10894 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
10895 size
= int_size_in_bytes (type
);
10898 size
= GET_MODE_SIZE (mode
);
10900 if (size
== 1 || size
== 2 || size
== 4)
10901 return PAD_DOWNWARD
;
10906 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
10908 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
10912 /* Fall back to the default. */
10913 return default_function_arg_padding (mode
, type
);
10916 /* If defined, a C expression that gives the alignment boundary, in bits,
10917 of an argument with the specified mode and type. If it is not defined,
10918 PARM_BOUNDARY is used for all arguments.
10920 V.4 wants long longs and doubles to be double word aligned. Just
10921 testing the mode size is a boneheaded way to do this as it means
10922 that other types such as complex int are also double word aligned.
10923 However, we're stuck with this because changing the ABI might break
10924 existing library interfaces.
10926 Quadword align Altivec/VSX vectors.
10927 Quadword align large synthetic vector types. */
10929 static unsigned int
10930 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
10932 machine_mode elt_mode
;
10935 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10937 if (DEFAULT_ABI
== ABI_V4
10938 && (GET_MODE_SIZE (mode
) == 8
10939 || (TARGET_HARD_FLOAT
10940 && !is_complex_IBM_long_double (mode
)
10941 && FLOAT128_2REG_P (mode
))))
10943 else if (FLOAT128_VECTOR_P (mode
))
10945 else if (type
&& TREE_CODE (type
) == VECTOR_TYPE
10946 && int_size_in_bytes (type
) >= 8
10947 && int_size_in_bytes (type
) < 16)
10949 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
10950 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10951 && int_size_in_bytes (type
) >= 16))
10954 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10955 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10956 -mcompat-align-parm is used. */
10957 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
10958 || DEFAULT_ABI
== ABI_ELFv2
)
10959 && type
&& TYPE_ALIGN (type
) > 64)
10961 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10962 or homogeneous float/vector aggregates here. We already handled
10963 vector aggregates above, but still need to check for float here. */
10964 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
10965 && !SCALAR_FLOAT_MODE_P (elt_mode
));
10967 /* We used to check for BLKmode instead of the above aggregate type
10968 check. Warn when this results in any difference to the ABI. */
10969 if (aggregate_p
!= (mode
== BLKmode
))
10971 static bool warned
;
10972 if (!warned
&& warn_psabi
)
10975 inform (input_location
,
10976 "the ABI of passing aggregates with %d-byte alignment"
10977 " has changed in GCC 5",
10978 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
10986 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10987 implement the "aggregate type" check as a BLKmode check here; this
10988 means certain aggregate types are in fact not aligned. */
10989 if (TARGET_MACHO
&& rs6000_darwin64_abi
10991 && type
&& TYPE_ALIGN (type
) > 64)
10994 return PARM_BOUNDARY
;
10997 /* The offset in words to the start of the parameter save area. */
10999 static unsigned int
11000 rs6000_parm_offset (void)
11002 return (DEFAULT_ABI
== ABI_V4
? 2
11003 : DEFAULT_ABI
== ABI_ELFv2
? 4
11007 /* For a function parm of MODE and TYPE, return the starting word in
11008 the parameter area. NWORDS of the parameter area are already used. */
11010 static unsigned int
11011 rs6000_parm_start (machine_mode mode
, const_tree type
,
11012 unsigned int nwords
)
11014 unsigned int align
;
11016 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
11017 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
11020 /* Compute the size (in words) of a function argument. */
11022 static unsigned long
11023 rs6000_arg_size (machine_mode mode
, const_tree type
)
11025 unsigned long size
;
11027 if (mode
!= BLKmode
)
11028 size
= GET_MODE_SIZE (mode
);
11030 size
= int_size_in_bytes (type
);
11033 return (size
+ 3) >> 2;
11035 return (size
+ 7) >> 3;
11038 /* Use this to flush pending int fields. */
11041 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
11042 HOST_WIDE_INT bitpos
, int final
)
11044 unsigned int startbit
, endbit
;
11045 int intregs
, intoffset
;
11047 /* Handle the situations where a float is taking up the first half
11048 of the GPR, and the other half is empty (typically due to
11049 alignment restrictions). We can detect this by a 8-byte-aligned
11050 int field, or by seeing that this is the final flush for this
11051 argument. Count the word and continue on. */
11052 if (cum
->floats_in_gpr
== 1
11053 && (cum
->intoffset
% 64 == 0
11054 || (cum
->intoffset
== -1 && final
)))
11057 cum
->floats_in_gpr
= 0;
11060 if (cum
->intoffset
== -1)
11063 intoffset
= cum
->intoffset
;
11064 cum
->intoffset
= -1;
11065 cum
->floats_in_gpr
= 0;
11067 if (intoffset
% BITS_PER_WORD
!= 0)
11069 unsigned int bits
= BITS_PER_WORD
- intoffset
% BITS_PER_WORD
;
11070 if (!int_mode_for_size (bits
, 0).exists ())
11072 /* We couldn't find an appropriate mode, which happens,
11073 e.g., in packed structs when there are 3 bytes to load.
11074 Back intoffset back to the beginning of the word in this
11076 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11080 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11081 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11082 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11083 cum
->words
+= intregs
;
11084 /* words should be unsigned. */
11085 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
11087 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
11092 /* The darwin64 ABI calls for us to recurse down through structs,
11093 looking for elements passed in registers. Unfortunately, we have
11094 to track int register count here also because of misalignments
11095 in powerpc alignment mode. */
11098 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
11100 HOST_WIDE_INT startbitpos
)
11104 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11105 if (TREE_CODE (f
) == FIELD_DECL
)
11107 HOST_WIDE_INT bitpos
= startbitpos
;
11108 tree ftype
= TREE_TYPE (f
);
11110 if (ftype
== error_mark_node
)
11112 mode
= TYPE_MODE (ftype
);
11114 if (DECL_SIZE (f
) != 0
11115 && tree_fits_uhwi_p (bit_position (f
)))
11116 bitpos
+= int_bit_position (f
);
11118 /* ??? FIXME: else assume zero offset. */
11120 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11121 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
11122 else if (USE_FP_FOR_ARG_P (cum
, mode
))
11124 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11125 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11126 cum
->fregno
+= n_fpregs
;
11127 /* Single-precision floats present a special problem for
11128 us, because they are smaller than an 8-byte GPR, and so
11129 the structure-packing rules combined with the standard
11130 varargs behavior mean that we want to pack float/float
11131 and float/int combinations into a single register's
11132 space. This is complicated by the arg advance flushing,
11133 which works on arbitrarily large groups of int-type
11135 if (mode
== SFmode
)
11137 if (cum
->floats_in_gpr
== 1)
11139 /* Two floats in a word; count the word and reset
11140 the float count. */
11142 cum
->floats_in_gpr
= 0;
11144 else if (bitpos
% 64 == 0)
11146 /* A float at the beginning of an 8-byte word;
11147 count it and put off adjusting cum->words until
11148 we see if a arg advance flush is going to do it
11150 cum
->floats_in_gpr
++;
11154 /* The float is at the end of a word, preceded
11155 by integer fields, so the arg advance flush
11156 just above has already set cum->words and
11157 everything is taken care of. */
11161 cum
->words
+= n_fpregs
;
11163 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11165 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11169 else if (cum
->intoffset
== -1)
11170 cum
->intoffset
= bitpos
;
11174 /* Check for an item that needs to be considered specially under the darwin 64
11175 bit ABI. These are record types where the mode is BLK or the structure is
11176 8 bytes in size. */
11178 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
11180 return rs6000_darwin64_abi
11181 && ((mode
== BLKmode
11182 && TREE_CODE (type
) == RECORD_TYPE
11183 && int_size_in_bytes (type
) > 0)
11184 || (type
&& TREE_CODE (type
) == RECORD_TYPE
11185 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
11188 /* Update the data in CUM to advance over an argument
11189 of mode MODE and data type TYPE.
11190 (TYPE is null for libcalls where that information may not be available.)
11192 Note that for args passed by reference, function_arg will be called
11193 with MODE and TYPE set to that of the pointer to the arg, not the arg
11197 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
11198 const_tree type
, bool named
, int depth
)
11200 machine_mode elt_mode
;
11203 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11205 /* Only tick off an argument if we're not recursing. */
11207 cum
->nargs_prototype
--;
11209 #ifdef HAVE_AS_GNU_ATTRIBUTE
11210 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
11213 if (SCALAR_FLOAT_MODE_P (mode
))
11215 rs6000_passes_float
= true;
11216 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
11217 && (FLOAT128_IBM_P (mode
)
11218 || FLOAT128_IEEE_P (mode
)
11220 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
)))
11221 rs6000_passes_long_double
= true;
11223 /* Note if we passed or return a IEEE 128-bit type. We changed the
11224 mangling for these types, and we may need to make an alias with
11225 the old mangling. */
11226 if (FLOAT128_IEEE_P (mode
))
11227 rs6000_passes_ieee128
= true;
11229 if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
11230 rs6000_passes_vector
= true;
11234 if (TARGET_ALTIVEC_ABI
11235 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11236 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11237 && int_size_in_bytes (type
) == 16)))
11239 bool stack
= false;
11241 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11243 cum
->vregno
+= n_elts
;
11245 if (!TARGET_ALTIVEC
)
11246 error ("cannot pass argument in vector register because"
11247 " altivec instructions are disabled, use %qs"
11248 " to enable them", "-maltivec");
11250 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11251 even if it is going to be passed in a vector register.
11252 Darwin does the same for variable-argument functions. */
11253 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11255 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
11265 /* Vector parameters must be 16-byte aligned. In 32-bit
11266 mode this means we need to take into account the offset
11267 to the parameter save area. In 64-bit mode, they just
11268 have to start on an even word, since the parameter save
11269 area is 16-byte aligned. */
11271 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11273 align
= cum
->words
& 1;
11274 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
11276 if (TARGET_DEBUG_ARG
)
11278 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
11279 cum
->words
, align
);
11280 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
11281 cum
->nargs_prototype
, cum
->prototype
,
11282 GET_MODE_NAME (mode
));
11286 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11288 int size
= int_size_in_bytes (type
);
11289 /* Variable sized types have size == -1 and are
11290 treated as if consisting entirely of ints.
11291 Pad to 16 byte boundary if needed. */
11292 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11293 && (cum
->words
% 2) != 0)
11295 /* For varargs, we can just go up by the size of the struct. */
11297 cum
->words
+= (size
+ 7) / 8;
11300 /* It is tempting to say int register count just goes up by
11301 sizeof(type)/8, but this is wrong in a case such as
11302 { int; double; int; } [powerpc alignment]. We have to
11303 grovel through the fields for these too. */
11304 cum
->intoffset
= 0;
11305 cum
->floats_in_gpr
= 0;
11306 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
11307 rs6000_darwin64_record_arg_advance_flush (cum
,
11308 size
* BITS_PER_UNIT
, 1);
11310 if (TARGET_DEBUG_ARG
)
11312 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
11313 cum
->words
, TYPE_ALIGN (type
), size
);
11315 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11316 cum
->nargs_prototype
, cum
->prototype
,
11317 GET_MODE_NAME (mode
));
11320 else if (DEFAULT_ABI
== ABI_V4
)
11322 if (abi_v4_pass_in_fpr (mode
, named
))
11324 /* _Decimal128 must use an even/odd register pair. This assumes
11325 that the register number is odd when fregno is odd. */
11326 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11329 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11330 <= FP_ARG_V4_MAX_REG
)
11331 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
11334 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
11335 if (mode
== DFmode
|| FLOAT128_IBM_P (mode
)
11336 || mode
== DDmode
|| mode
== TDmode
)
11337 cum
->words
+= cum
->words
& 1;
11338 cum
->words
+= rs6000_arg_size (mode
, type
);
11343 int n_words
= rs6000_arg_size (mode
, type
);
11344 int gregno
= cum
->sysv_gregno
;
11346 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11347 As does any other 2 word item such as complex int due to a
11348 historical mistake. */
11350 gregno
+= (1 - gregno
) & 1;
11352 /* Multi-reg args are not split between registers and stack. */
11353 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11355 /* Long long is aligned on the stack. So are other 2 word
11356 items such as complex int due to a historical mistake. */
11358 cum
->words
+= cum
->words
& 1;
11359 cum
->words
+= n_words
;
11362 /* Note: continuing to accumulate gregno past when we've started
11363 spilling to the stack indicates the fact that we've started
11364 spilling to the stack to expand_builtin_saveregs. */
11365 cum
->sysv_gregno
= gregno
+ n_words
;
11368 if (TARGET_DEBUG_ARG
)
11370 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11371 cum
->words
, cum
->fregno
);
11372 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
11373 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
11374 fprintf (stderr
, "mode = %4s, named = %d\n",
11375 GET_MODE_NAME (mode
), named
);
11380 int n_words
= rs6000_arg_size (mode
, type
);
11381 int start_words
= cum
->words
;
11382 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
11384 cum
->words
= align_words
+ n_words
;
11386 if (SCALAR_FLOAT_MODE_P (elt_mode
) && TARGET_HARD_FLOAT
)
11388 /* _Decimal128 must be passed in an even/odd float register pair.
11389 This assumes that the register number is odd when fregno is
11391 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11393 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
11396 if (TARGET_DEBUG_ARG
)
11398 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11399 cum
->words
, cum
->fregno
);
11400 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
11401 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
11402 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
11403 named
, align_words
- start_words
, depth
);
11409 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
11410 const_tree type
, bool named
)
11412 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
11416 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11417 structure between cum->intoffset and bitpos to integer registers. */
11420 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
11421 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
11424 unsigned int regno
;
11425 unsigned int startbit
, endbit
;
11426 int this_regno
, intregs
, intoffset
;
11429 if (cum
->intoffset
== -1)
11432 intoffset
= cum
->intoffset
;
11433 cum
->intoffset
= -1;
11435 /* If this is the trailing part of a word, try to only load that
11436 much into the register. Otherwise load the whole register. Note
11437 that in the latter case we may pick up unwanted bits. It's not a
11438 problem at the moment but may wish to revisit. */
11440 if (intoffset
% BITS_PER_WORD
!= 0)
11442 unsigned int bits
= BITS_PER_WORD
- intoffset
% BITS_PER_WORD
;
11443 if (!int_mode_for_size (bits
, 0).exists (&mode
))
11445 /* We couldn't find an appropriate mode, which happens,
11446 e.g., in packed structs when there are 3 bytes to load.
11447 Back intoffset back to the beginning of the word in this
11449 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11456 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11457 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11458 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11459 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
11461 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
11462 cum
->use_stack
= 1;
11464 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
11468 intoffset
/= BITS_PER_UNIT
;
11471 regno
= GP_ARG_MIN_REG
+ this_regno
;
11472 reg
= gen_rtx_REG (mode
, regno
);
11474 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
11477 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
11481 while (intregs
> 0);
11484 /* Recursive workhorse for the following. */
11487 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
11488 HOST_WIDE_INT startbitpos
, rtx rvec
[],
11493 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11494 if (TREE_CODE (f
) == FIELD_DECL
)
11496 HOST_WIDE_INT bitpos
= startbitpos
;
11497 tree ftype
= TREE_TYPE (f
);
11499 if (ftype
== error_mark_node
)
11501 mode
= TYPE_MODE (ftype
);
11503 if (DECL_SIZE (f
) != 0
11504 && tree_fits_uhwi_p (bit_position (f
)))
11505 bitpos
+= int_bit_position (f
);
11507 /* ??? FIXME: else assume zero offset. */
11509 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11510 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
11511 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
11513 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11517 case E_SCmode
: mode
= SFmode
; break;
11518 case E_DCmode
: mode
= DFmode
; break;
11519 case E_TCmode
: mode
= TFmode
; break;
11523 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
11524 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
11526 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
11527 && (mode
== TFmode
|| mode
== TDmode
));
11528 /* Long double or _Decimal128 split over regs and memory. */
11529 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
11533 = gen_rtx_EXPR_LIST (VOIDmode
,
11534 gen_rtx_REG (mode
, cum
->fregno
++),
11535 GEN_INT (bitpos
/ BITS_PER_UNIT
));
11536 if (FLOAT128_2REG_P (mode
))
11539 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11541 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
11543 = gen_rtx_EXPR_LIST (VOIDmode
,
11544 gen_rtx_REG (mode
, cum
->vregno
++),
11545 GEN_INT (bitpos
/ BITS_PER_UNIT
));
11547 else if (cum
->intoffset
== -1)
11548 cum
->intoffset
= bitpos
;
11552 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11553 the register(s) to be used for each field and subfield of a struct
11554 being passed by value, along with the offset of where the
11555 register's value may be found in the block. FP fields go in FP
11556 register, vector fields go in vector registers, and everything
11557 else goes in int registers, packed as in memory.
11559 This code is also used for function return values. RETVAL indicates
11560 whether this is the case.
11562 Much of this is taken from the SPARC V9 port, which has a similar
11563 calling convention. */
11566 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
11567 bool named
, bool retval
)
11569 rtx rvec
[FIRST_PSEUDO_REGISTER
];
11570 int k
= 1, kbase
= 1;
11571 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
11572 /* This is a copy; modifications are not visible to our caller. */
11573 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
11574 CUMULATIVE_ARGS
*cum
= ©_cum
;
11576 /* Pad to 16 byte boundary if needed. */
11577 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11578 && (cum
->words
% 2) != 0)
11581 cum
->intoffset
= 0;
11582 cum
->use_stack
= 0;
11583 cum
->named
= named
;
11585 /* Put entries into rvec[] for individual FP and vector fields, and
11586 for the chunks of memory that go in int regs. Note we start at
11587 element 1; 0 is reserved for an indication of using memory, and
11588 may or may not be filled in below. */
11589 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
11590 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
11592 /* If any part of the struct went on the stack put all of it there.
11593 This hack is because the generic code for
11594 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11595 parts of the struct are not at the beginning. */
11596 if (cum
->use_stack
)
11599 return NULL_RTX
; /* doesn't go in registers at all */
11601 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11603 if (k
> 1 || cum
->use_stack
)
11604 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
11609 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11612 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
11617 rtx rvec
[GP_ARG_NUM_REG
+ 1];
11619 if (align_words
>= GP_ARG_NUM_REG
)
11622 n_units
= rs6000_arg_size (mode
, type
);
11624 /* Optimize the simple case where the arg fits in one gpr, except in
11625 the case of BLKmode due to assign_parms assuming that registers are
11626 BITS_PER_WORD wide. */
11628 || (n_units
== 1 && mode
!= BLKmode
))
11629 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
11632 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
11633 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11634 using a magic NULL_RTX component.
11635 This is not strictly correct. Only some of the arg belongs in
11636 memory, not all of it. However, the normal scheme using
11637 function_arg_partial_nregs can result in unusual subregs, eg.
11638 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11639 store the whole arg to memory is often more efficient than code
11640 to store pieces, and we know that space is available in the right
11641 place for the whole arg. */
11642 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11647 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
11648 rtx off
= GEN_INT (i
++ * 4);
11649 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11651 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
11653 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
11656 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11657 but must also be copied into the parameter save area starting at
11658 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11659 to the GPRs and/or memory. Return the number of elements used. */
11662 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
11663 int align_words
, rtx
*rvec
)
11667 if (align_words
< GP_ARG_NUM_REG
)
11669 int n_words
= rs6000_arg_size (mode
, type
);
11671 if (align_words
+ n_words
> GP_ARG_NUM_REG
11673 || (TARGET_32BIT
&& TARGET_POWERPC64
))
11675 /* If this is partially on the stack, then we only
11676 include the portion actually in registers here. */
11677 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
11680 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
11682 /* Not all of the arg fits in gprs. Say that it goes in memory
11683 too, using a magic NULL_RTX component. Also see comment in
11684 rs6000_mixed_function_arg for why the normal
11685 function_arg_partial_nregs scheme doesn't work in this case. */
11686 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11691 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
11692 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
11693 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11695 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
11699 /* The whole arg fits in gprs. */
11700 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
11701 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
11706 /* It's entirely in memory. */
11707 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11713 /* RVEC is a vector of K components of an argument of mode MODE.
11714 Construct the final function_arg return value from it. */
11717 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
11719 gcc_assert (k
>= 1);
11721 /* Avoid returning a PARALLEL in the trivial cases. */
11724 if (XEXP (rvec
[0], 0) == NULL_RTX
)
11727 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
11728 return XEXP (rvec
[0], 0);
11731 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
11734 /* Determine where to put an argument to a function.
11735 Value is zero to push the argument on the stack,
11736 or a hard register in which to store the argument.
11738 MODE is the argument's machine mode.
11739 TYPE is the data type of the argument (as a tree).
11740 This is null for libcalls where that information may
11742 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11743 the preceding args and about the function being called. It is
11744 not modified in this routine.
11745 NAMED is nonzero if this argument is a named parameter
11746 (otherwise it is an extra parameter matching an ellipsis).
11748 On RS/6000 the first eight words of non-FP are normally in registers
11749 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11750 Under V.4, the first 8 FP args are in registers.
11752 If this is floating-point and no prototype is specified, we use
11753 both an FP and integer register (or possibly FP reg and stack). Library
11754 functions (when CALL_LIBCALL is set) always have the proper types for args,
11755 so we can pass the FP value just in one register. emit_library_function
11756 doesn't support PARALLEL anyway.
11758 Note that for args passed by reference, function_arg will be called
11759 with MODE and TYPE set to that of the pointer to the arg, not the arg
11763 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
11764 const_tree type
, bool named
)
11766 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11767 enum rs6000_abi abi
= DEFAULT_ABI
;
11768 machine_mode elt_mode
;
11771 /* Return a marker to indicate whether CR1 needs to set or clear the
11772 bit that V.4 uses to say fp args were passed in registers.
11773 Assume that we don't need the marker for software floating point,
11774 or compiler generated library calls. */
11775 if (mode
== VOIDmode
)
11778 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
11780 || (cum
->nargs_prototype
< 0
11781 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
)))
11782 && TARGET_HARD_FLOAT
)
11783 return GEN_INT (cum
->call_cookie
11784 | ((cum
->fregno
== FP_ARG_MIN_REG
)
11785 ? CALL_V4_SET_FP_ARGS
11786 : CALL_V4_CLEAR_FP_ARGS
));
11788 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
11791 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11793 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11795 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
11796 if (rslt
!= NULL_RTX
)
11798 /* Else fall through to usual handling. */
11801 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11803 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
11807 /* Do we also need to pass this argument in the parameter save area?
11808 Library support functions for IEEE 128-bit are assumed to not need the
11809 value passed both in GPRs and in vector registers. */
11810 if (TARGET_64BIT
&& !cum
->prototype
11811 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
11813 int align_words
= ROUND_UP (cum
->words
, 2);
11814 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
11817 /* Describe where this argument goes in the vector registers. */
11818 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
11820 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
11821 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
11822 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11825 return rs6000_finish_function_arg (mode
, rvec
, k
);
11827 else if (TARGET_ALTIVEC_ABI
11828 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
11829 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11830 && int_size_in_bytes (type
) == 16)))
11832 if (named
|| abi
== ABI_V4
)
11836 /* Vector parameters to varargs functions under AIX or Darwin
11837 get passed in memory and possibly also in GPRs. */
11838 int align
, align_words
, n_words
;
11839 machine_mode part_mode
;
11841 /* Vector parameters must be 16-byte aligned. In 32-bit
11842 mode this means we need to take into account the offset
11843 to the parameter save area. In 64-bit mode, they just
11844 have to start on an even word, since the parameter save
11845 area is 16-byte aligned. */
11847 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11849 align
= cum
->words
& 1;
11850 align_words
= cum
->words
+ align
;
11852 /* Out of registers? Memory, then. */
11853 if (align_words
>= GP_ARG_NUM_REG
)
11856 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11857 return rs6000_mixed_function_arg (mode
, type
, align_words
);
11859 /* The vector value goes in GPRs. Only the part of the
11860 value in GPRs is reported here. */
11862 n_words
= rs6000_arg_size (mode
, type
);
11863 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
11864 /* Fortunately, there are only two possibilities, the value
11865 is either wholly in GPRs or half in GPRs and half not. */
11866 part_mode
= DImode
;
11868 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
11872 else if (abi
== ABI_V4
)
11874 if (abi_v4_pass_in_fpr (mode
, named
))
11876 /* _Decimal128 must use an even/odd register pair. This assumes
11877 that the register number is odd when fregno is odd. */
11878 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11881 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11882 <= FP_ARG_V4_MAX_REG
)
11883 return gen_rtx_REG (mode
, cum
->fregno
);
11889 int n_words
= rs6000_arg_size (mode
, type
);
11890 int gregno
= cum
->sysv_gregno
;
11892 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11893 As does any other 2 word item such as complex int due to a
11894 historical mistake. */
11896 gregno
+= (1 - gregno
) & 1;
11898 /* Multi-reg args are not split between registers and stack. */
11899 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11902 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11903 return rs6000_mixed_function_arg (mode
, type
,
11904 gregno
- GP_ARG_MIN_REG
);
11905 return gen_rtx_REG (mode
, gregno
);
11910 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
11912 /* _Decimal128 must be passed in an even/odd float register pair.
11913 This assumes that the register number is odd when fregno is odd. */
11914 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11917 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
11919 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
11922 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
11925 /* Do we also need to pass this argument in the parameter
11927 if (type
&& (cum
->nargs_prototype
<= 0
11928 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11929 && TARGET_XL_COMPAT
11930 && align_words
>= GP_ARG_NUM_REG
)))
11931 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
11933 /* Describe where this argument goes in the fprs. */
11934 for (i
= 0; i
< n_elts
11935 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
11937 /* Check if the argument is split over registers and memory.
11938 This can only ever happen for long double or _Decimal128;
11939 complex types are handled via split_complex_arg. */
11940 machine_mode fmode
= elt_mode
;
11941 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
11943 gcc_assert (FLOAT128_2REG_P (fmode
));
11944 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
11947 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
11948 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
11949 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11952 /* If there were not enough FPRs to hold the argument, the rest
11953 usually goes into memory. However, if the current position
11954 is still within the register parameter area, a portion may
11955 actually have to go into GPRs.
11957 Note that it may happen that the portion of the argument
11958 passed in the first "half" of the first GPR was already
11959 passed in the last FPR as well.
11961 For unnamed arguments, we already set up GPRs to cover the
11962 whole argument in rs6000_psave_function_arg, so there is
11963 nothing further to do at this point. */
11964 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
11965 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
11966 && cum
->nargs_prototype
> 0)
11968 static bool warned
;
11970 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
11971 int n_words
= rs6000_arg_size (mode
, type
);
11973 align_words
+= fpr_words
;
11974 n_words
-= fpr_words
;
11978 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
11979 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
11980 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11982 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
11984 if (!warned
&& warn_psabi
)
11987 inform (input_location
,
11988 "the ABI of passing homogeneous float aggregates"
11989 " has changed in GCC 5");
11993 return rs6000_finish_function_arg (mode
, rvec
, k
);
11995 else if (align_words
< GP_ARG_NUM_REG
)
11997 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11998 return rs6000_mixed_function_arg (mode
, type
, align_words
);
12000 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12007 /* For an arg passed partly in registers and partly in memory, this is
12008 the number of bytes passed in registers. For args passed entirely in
12009 registers or entirely in memory, zero. When an arg is described by a
12010 PARALLEL, perhaps using more than one register type, this function
12011 returns the number of bytes used by the first element of the PARALLEL. */
12014 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
12015 tree type
, bool named
)
12017 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12018 bool passed_in_gprs
= true;
12021 machine_mode elt_mode
;
12024 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
12026 if (DEFAULT_ABI
== ABI_V4
)
12029 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
12031 /* If we are passing this arg in the fixed parameter save area (gprs or
12032 memory) as well as VRs, we do not use the partial bytes mechanism;
12033 instead, rs6000_function_arg will return a PARALLEL including a memory
12034 element as necessary. Library support functions for IEEE 128-bit are
12035 assumed to not need the value passed both in GPRs and in vector
12037 if (TARGET_64BIT
&& !cum
->prototype
12038 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
12041 /* Otherwise, we pass in VRs only. Check for partial copies. */
12042 passed_in_gprs
= false;
12043 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
12044 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
12047 /* In this complicated case we just disable the partial_nregs code. */
12048 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
12051 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12053 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
12055 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12057 /* If we are passing this arg in the fixed parameter save area
12058 (gprs or memory) as well as FPRs, we do not use the partial
12059 bytes mechanism; instead, rs6000_function_arg will return a
12060 PARALLEL including a memory element as necessary. */
12062 && (cum
->nargs_prototype
<= 0
12063 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12064 && TARGET_XL_COMPAT
12065 && align_words
>= GP_ARG_NUM_REG
)))
12068 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12069 passed_in_gprs
= false;
12070 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
12072 /* Compute number of bytes / words passed in FPRs. If there
12073 is still space available in the register parameter area
12074 *after* that amount, a part of the argument will be passed
12075 in GPRs. In that case, the total amount passed in any
12076 registers is equal to the amount that would have been passed
12077 in GPRs if everything were passed there, so we fall back to
12078 the GPR code below to compute the appropriate value. */
12079 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
12080 * MIN (8, GET_MODE_SIZE (elt_mode
)));
12081 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
12083 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
12084 passed_in_gprs
= true;
12091 && align_words
< GP_ARG_NUM_REG
12092 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
12093 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
12095 if (ret
!= 0 && TARGET_DEBUG_ARG
)
12096 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
12101 /* A C expression that indicates when an argument must be passed by
12102 reference. If nonzero for an argument, a copy of that argument is
12103 made in memory and a pointer to the argument is passed instead of
12104 the argument itself. The pointer is passed in whatever way is
12105 appropriate for passing a pointer to that type.
12107 Under V.4, aggregates and long double are passed by reference.
12109 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12110 reference unless the AltiVec vector extension ABI is in force.
12112 As an extension to all ABIs, variable sized types are passed by
12116 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
12117 machine_mode mode
, const_tree type
,
12118 bool named ATTRIBUTE_UNUSED
)
12123 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
12124 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
12126 if (TARGET_DEBUG_ARG
)
12127 fprintf (stderr
, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12131 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
12133 if (TARGET_DEBUG_ARG
)
12134 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
12138 if (int_size_in_bytes (type
) < 0)
12140 if (TARGET_DEBUG_ARG
)
12141 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
12145 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12146 modes only exist for GCC vector types if -maltivec. */
12147 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12149 if (TARGET_DEBUG_ARG
)
12150 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
12154 /* Pass synthetic vectors in memory. */
12155 if (TREE_CODE (type
) == VECTOR_TYPE
12156 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
12158 static bool warned_for_pass_big_vectors
= false;
12159 if (TARGET_DEBUG_ARG
)
12160 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
12161 if (!warned_for_pass_big_vectors
)
12163 warning (OPT_Wpsabi
, "GCC vector passed by reference: "
12164 "non-standard ABI extension with no compatibility "
12166 warned_for_pass_big_vectors
= true;
12174 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12175 already processes. Return true if the parameter must be passed
12176 (fully or partially) on the stack. */
12179 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
12185 /* Catch errors. */
12186 if (type
== NULL
|| type
== error_mark_node
)
12189 /* Handle types with no storage requirement. */
12190 if (TYPE_MODE (type
) == VOIDmode
)
12193 /* Handle complex types. */
12194 if (TREE_CODE (type
) == COMPLEX_TYPE
)
12195 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
12196 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
12198 /* Handle transparent aggregates. */
12199 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
12200 && TYPE_TRANSPARENT_AGGR (type
))
12201 type
= TREE_TYPE (first_field (type
));
12203 /* See if this arg was passed by invisible reference. */
12204 if (pass_by_reference (get_cumulative_args (args_so_far
),
12205 TYPE_MODE (type
), type
, true))
12206 type
= build_pointer_type (type
);
12208 /* Find mode as it is passed by the ABI. */
12209 unsignedp
= TYPE_UNSIGNED (type
);
12210 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
12212 /* If we must pass in stack, we need a stack. */
12213 if (rs6000_must_pass_in_stack (mode
, type
))
12216 /* If there is no incoming register, we need a stack. */
12217 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
12218 if (entry_parm
== NULL
)
12221 /* Likewise if we need to pass both in registers and on the stack. */
12222 if (GET_CODE (entry_parm
) == PARALLEL
12223 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
12226 /* Also true if we're partially in registers and partially not. */
12227 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
12230 /* Update info on where next arg arrives in registers. */
12231 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
12235 /* Return true if FUN has no prototype, has a variable argument
12236 list, or passes any parameter in memory. */
12239 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
12241 tree fntype
, result
;
12242 CUMULATIVE_ARGS args_so_far_v
;
12243 cumulative_args_t args_so_far
;
12246 /* Must be a libcall, all of which only use reg parms. */
12251 fntype
= TREE_TYPE (fun
);
12253 /* Varargs functions need the parameter save area. */
12254 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
12257 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
12258 args_so_far
= pack_cumulative_args (&args_so_far_v
);
12260 /* When incoming, we will have been passed the function decl.
12261 It is necessary to use the decl to handle K&R style functions,
12262 where TYPE_ARG_TYPES may not be available. */
12265 gcc_assert (DECL_P (fun
));
12266 result
= DECL_RESULT (fun
);
12269 result
= TREE_TYPE (fntype
);
12271 if (result
&& aggregate_value_p (result
, fntype
))
12273 if (!TYPE_P (result
))
12274 result
= TREE_TYPE (result
);
12275 result
= build_pointer_type (result
);
12276 rs6000_parm_needs_stack (args_so_far
, result
);
12283 for (parm
= DECL_ARGUMENTS (fun
);
12284 parm
&& parm
!= void_list_node
;
12285 parm
= TREE_CHAIN (parm
))
12286 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
12291 function_args_iterator args_iter
;
12294 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
12295 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
12302 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12303 usually a constant depending on the ABI. However, in the ELFv2 ABI
12304 the register parameter area is optional when calling a function that
12305 has a prototype is scope, has no variable argument list, and passes
12306 all parameters in registers. */
12309 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
12311 int reg_parm_stack_space
;
12313 switch (DEFAULT_ABI
)
12316 reg_parm_stack_space
= 0;
12321 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12325 /* ??? Recomputing this every time is a bit expensive. Is there
12326 a place to cache this information? */
12327 if (rs6000_function_parms_need_stack (fun
, incoming
))
12328 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12330 reg_parm_stack_space
= 0;
12334 return reg_parm_stack_space
;
12338 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
12341 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
12346 for (i
= 0; i
< nregs
; i
++)
12348 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
12349 if (reload_completed
)
12351 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
12354 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
12355 i
* GET_MODE_SIZE (reg_mode
));
12358 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
12362 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
12366 /* Perform any needed actions needed for a function that is receiving a
12367 variable number of arguments.
12371 MODE and TYPE are the mode and type of the current parameter.
12373 PRETEND_SIZE is a variable that should be set to the amount of stack
12374 that must be pushed by the prolog to pretend that our caller pushed
12377 Normally, this macro will push all remaining incoming registers on the
12378 stack and set PRETEND_SIZE to the length of the registers pushed. */
12381 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
12382 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
12385 CUMULATIVE_ARGS next_cum
;
12386 int reg_size
= TARGET_32BIT
? 4 : 8;
12387 rtx save_area
= NULL_RTX
, mem
;
12388 int first_reg_offset
;
12389 alias_set_type set
;
12391 /* Skip the last named argument. */
12392 next_cum
= *get_cumulative_args (cum
);
12393 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
12395 if (DEFAULT_ABI
== ABI_V4
)
12397 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
12401 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
12402 HOST_WIDE_INT offset
= 0;
12404 /* Try to optimize the size of the varargs save area.
12405 The ABI requires that ap.reg_save_area is doubleword
12406 aligned, but we don't need to allocate space for all
12407 the bytes, only those to which we actually will save
12409 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
12410 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
12411 if (TARGET_HARD_FLOAT
12412 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
12413 && cfun
->va_list_fpr_size
)
12416 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
12417 * UNITS_PER_FP_WORD
;
12418 if (cfun
->va_list_fpr_size
12419 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12420 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
12422 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12423 * UNITS_PER_FP_WORD
;
12427 offset
= -((first_reg_offset
* reg_size
) & ~7);
12428 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
12430 gpr_reg_num
= cfun
->va_list_gpr_size
;
12431 if (reg_size
== 4 && (first_reg_offset
& 1))
12434 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
12437 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
12438 * UNITS_PER_FP_WORD
12439 - (int) (GP_ARG_NUM_REG
* reg_size
);
12441 if (gpr_size
+ fpr_size
)
12444 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
12445 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
12446 reg_save_area
= XEXP (reg_save_area
, 0);
12447 if (GET_CODE (reg_save_area
) == PLUS
)
12449 gcc_assert (XEXP (reg_save_area
, 0)
12450 == virtual_stack_vars_rtx
);
12451 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
12452 offset
+= INTVAL (XEXP (reg_save_area
, 1));
12455 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
12458 cfun
->machine
->varargs_save_offset
= offset
;
12459 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
12464 first_reg_offset
= next_cum
.words
;
12465 save_area
= crtl
->args
.internal_arg_pointer
;
12467 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
12468 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
12471 set
= get_varargs_alias_set ();
12472 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
12473 && cfun
->va_list_gpr_size
)
12475 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
12477 if (va_list_gpr_counter_field
)
12478 /* V4 va_list_gpr_size counts number of registers needed. */
12479 n_gpr
= cfun
->va_list_gpr_size
;
12481 /* char * va_list instead counts number of bytes needed. */
12482 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
12487 mem
= gen_rtx_MEM (BLKmode
,
12488 plus_constant (Pmode
, save_area
,
12489 first_reg_offset
* reg_size
));
12490 MEM_NOTRAP_P (mem
) = 1;
12491 set_mem_alias_set (mem
, set
);
12492 set_mem_align (mem
, BITS_PER_WORD
);
12494 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
12498 /* Save FP registers if needed. */
12499 if (DEFAULT_ABI
== ABI_V4
12500 && TARGET_HARD_FLOAT
12502 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
12503 && cfun
->va_list_fpr_size
)
12505 int fregno
= next_cum
.fregno
, nregs
;
12506 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
12507 rtx lab
= gen_label_rtx ();
12508 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
12509 * UNITS_PER_FP_WORD
);
12512 (gen_rtx_SET (pc_rtx
,
12513 gen_rtx_IF_THEN_ELSE (VOIDmode
,
12514 gen_rtx_NE (VOIDmode
, cr1
,
12516 gen_rtx_LABEL_REF (VOIDmode
, lab
),
12520 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
12521 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
12523 mem
= gen_rtx_MEM (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
12524 plus_constant (Pmode
, save_area
, off
));
12525 MEM_NOTRAP_P (mem
) = 1;
12526 set_mem_alias_set (mem
, set
);
12527 set_mem_align (mem
, GET_MODE_ALIGNMENT (
12528 TARGET_HARD_FLOAT
? DFmode
: SFmode
));
12529 emit_move_insn (mem
, gen_rtx_REG (
12530 TARGET_HARD_FLOAT
? DFmode
: SFmode
, fregno
));
12537 /* Create the va_list data type. */
12540 rs6000_build_builtin_va_list (void)
12542 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
12544 /* For AIX, prefer 'char *' because that's what the system
12545 header files like. */
12546 if (DEFAULT_ABI
!= ABI_V4
)
12547 return build_pointer_type (char_type_node
);
12549 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
12550 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
12551 get_identifier ("__va_list_tag"), record
);
12553 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
12554 unsigned_char_type_node
);
12555 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
12556 unsigned_char_type_node
);
12557 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12558 every user file. */
12559 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12560 get_identifier ("reserved"), short_unsigned_type_node
);
12561 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12562 get_identifier ("overflow_arg_area"),
12564 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12565 get_identifier ("reg_save_area"),
12568 va_list_gpr_counter_field
= f_gpr
;
12569 va_list_fpr_counter_field
= f_fpr
;
12571 DECL_FIELD_CONTEXT (f_gpr
) = record
;
12572 DECL_FIELD_CONTEXT (f_fpr
) = record
;
12573 DECL_FIELD_CONTEXT (f_res
) = record
;
12574 DECL_FIELD_CONTEXT (f_ovf
) = record
;
12575 DECL_FIELD_CONTEXT (f_sav
) = record
;
12577 TYPE_STUB_DECL (record
) = type_decl
;
12578 TYPE_NAME (record
) = type_decl
;
12579 TYPE_FIELDS (record
) = f_gpr
;
12580 DECL_CHAIN (f_gpr
) = f_fpr
;
12581 DECL_CHAIN (f_fpr
) = f_res
;
12582 DECL_CHAIN (f_res
) = f_ovf
;
12583 DECL_CHAIN (f_ovf
) = f_sav
;
12585 layout_type (record
);
12587 /* The correct type is an array type of one element. */
12588 return build_array_type (record
, build_index_type (size_zero_node
));
12591 /* Implement va_start. */
12594 rs6000_va_start (tree valist
, rtx nextarg
)
12596 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
12597 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
12598 tree gpr
, fpr
, ovf
, sav
, t
;
12600 /* Only SVR4 needs something special. */
12601 if (DEFAULT_ABI
!= ABI_V4
)
12603 std_expand_builtin_va_start (valist
, nextarg
);
12607 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12608 f_fpr
= DECL_CHAIN (f_gpr
);
12609 f_res
= DECL_CHAIN (f_fpr
);
12610 f_ovf
= DECL_CHAIN (f_res
);
12611 f_sav
= DECL_CHAIN (f_ovf
);
12613 valist
= build_simple_mem_ref (valist
);
12614 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12615 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
12617 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
12619 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
12622 /* Count number of gp and fp argument registers used. */
12623 words
= crtl
->args
.info
.words
;
12624 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
12626 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
12629 if (TARGET_DEBUG_ARG
)
12630 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
12631 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
12632 words
, n_gpr
, n_fpr
);
12634 if (cfun
->va_list_gpr_size
)
12636 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
12637 build_int_cst (NULL_TREE
, n_gpr
));
12638 TREE_SIDE_EFFECTS (t
) = 1;
12639 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12642 if (cfun
->va_list_fpr_size
)
12644 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
12645 build_int_cst (NULL_TREE
, n_fpr
));
12646 TREE_SIDE_EFFECTS (t
) = 1;
12647 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12649 #ifdef HAVE_AS_GNU_ATTRIBUTE
12650 if (call_ABI_of_interest (cfun
->decl
))
12651 rs6000_passes_float
= true;
12655 /* Find the overflow area. */
12656 t
= make_tree (TREE_TYPE (ovf
), crtl
->args
.internal_arg_pointer
);
12658 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
12659 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
12660 TREE_SIDE_EFFECTS (t
) = 1;
12661 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12663 /* If there were no va_arg invocations, don't set up the register
12665 if (!cfun
->va_list_gpr_size
12666 && !cfun
->va_list_fpr_size
12667 && n_gpr
< GP_ARG_NUM_REG
12668 && n_fpr
< FP_ARG_V4_MAX_REG
)
12671 /* Find the register save area. */
12672 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
12673 if (cfun
->machine
->varargs_save_offset
)
12674 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
12675 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
12676 TREE_SIDE_EFFECTS (t
) = 1;
12677 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12680 /* Implement va_arg. */
12683 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
12684 gimple_seq
*post_p
)
12686 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
12687 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
12688 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
12689 tree lab_false
, lab_over
, addr
;
12691 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
12695 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
12697 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
12698 return build_va_arg_indirect_ref (t
);
12701 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12702 earlier version of gcc, with the property that it always applied alignment
12703 adjustments to the va-args (even for zero-sized types). The cheapest way
12704 to deal with this is to replicate the effect of the part of
12705 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12707 We don't need to check for pass-by-reference because of the test above.
12708 We can return a simplifed answer, since we know there's no offset to add. */
12711 && rs6000_darwin64_abi
)
12712 || DEFAULT_ABI
== ABI_ELFv2
12713 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
12714 && integer_zerop (TYPE_SIZE (type
)))
12716 unsigned HOST_WIDE_INT align
, boundary
;
12717 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
12718 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
12719 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
12720 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
12721 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
12722 boundary
/= BITS_PER_UNIT
;
12723 if (boundary
> align
)
12726 /* This updates arg ptr by the amount that would be necessary
12727 to align the zero-sized (but not zero-alignment) item. */
12728 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
12729 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
12730 gimplify_and_add (t
, pre_p
);
12732 t
= fold_convert (sizetype
, valist_tmp
);
12733 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
12734 fold_convert (TREE_TYPE (valist
),
12735 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
12736 size_int (-boundary
))));
12737 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
12738 gimplify_and_add (t
, pre_p
);
12740 /* Since it is zero-sized there's no increment for the item itself. */
12741 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
12742 return build_va_arg_indirect_ref (valist_tmp
);
12745 if (DEFAULT_ABI
!= ABI_V4
)
12747 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
12749 tree elem_type
= TREE_TYPE (type
);
12750 machine_mode elem_mode
= TYPE_MODE (elem_type
);
12751 int elem_size
= GET_MODE_SIZE (elem_mode
);
12753 if (elem_size
< UNITS_PER_WORD
)
12755 tree real_part
, imag_part
;
12756 gimple_seq post
= NULL
;
12758 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
12760 /* Copy the value into a temporary, lest the formal temporary
12761 be reused out from under us. */
12762 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
12763 gimple_seq_add_seq (pre_p
, post
);
12765 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
12768 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
12772 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
12775 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12776 f_fpr
= DECL_CHAIN (f_gpr
);
12777 f_res
= DECL_CHAIN (f_fpr
);
12778 f_ovf
= DECL_CHAIN (f_res
);
12779 f_sav
= DECL_CHAIN (f_ovf
);
12781 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12782 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
12784 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
12786 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
12789 size
= int_size_in_bytes (type
);
12790 rsize
= (size
+ 3) / 4;
12791 int pad
= 4 * rsize
- size
;
12794 machine_mode mode
= TYPE_MODE (type
);
12795 if (abi_v4_pass_in_fpr (mode
, false))
12797 /* FP args go in FP registers, if present. */
12799 n_reg
= (size
+ 7) / 8;
12800 sav_ofs
= (TARGET_HARD_FLOAT
? 8 : 4) * 4;
12801 sav_scale
= (TARGET_HARD_FLOAT
? 8 : 4);
12802 if (mode
!= SFmode
&& mode
!= SDmode
)
12807 /* Otherwise into GP registers. */
12816 /* Pull the value out of the saved registers.... */
12819 addr
= create_tmp_var (ptr_type_node
, "addr");
12821 /* AltiVec vectors never go in registers when -mabi=altivec. */
12822 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12826 lab_false
= create_artificial_label (input_location
);
12827 lab_over
= create_artificial_label (input_location
);
12829 /* Long long is aligned in the registers. As are any other 2 gpr
12830 item such as complex int due to a historical mistake. */
12832 if (n_reg
== 2 && reg
== gpr
)
12835 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12836 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
12837 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
12838 unshare_expr (reg
), u
);
12840 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12841 reg number is 0 for f1, so we want to make it odd. */
12842 else if (reg
== fpr
&& mode
== TDmode
)
12844 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12845 build_int_cst (TREE_TYPE (reg
), 1));
12846 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
12849 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
12850 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
12851 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
12852 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
12853 gimplify_and_add (t
, pre_p
);
12857 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
12859 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12860 build_int_cst (TREE_TYPE (reg
), n_reg
));
12861 u
= fold_convert (sizetype
, u
);
12862 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
12863 t
= fold_build_pointer_plus (t
, u
);
12865 /* _Decimal32 varargs are located in the second word of the 64-bit
12866 FP register for 32-bit binaries. */
12867 if (TARGET_32BIT
&& TARGET_HARD_FLOAT
&& mode
== SDmode
)
12868 t
= fold_build_pointer_plus_hwi (t
, size
);
12870 /* Args are passed right-aligned. */
12871 if (BYTES_BIG_ENDIAN
)
12872 t
= fold_build_pointer_plus_hwi (t
, pad
);
12874 gimplify_assign (addr
, t
, pre_p
);
12876 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
12878 stmt
= gimple_build_label (lab_false
);
12879 gimple_seq_add_stmt (pre_p
, stmt
);
12881 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
12883 /* Ensure that we don't find any more args in regs.
12884 Alignment has taken care of for special cases. */
12885 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
12889 /* ... otherwise out of the overflow area. */
12891 /* Care for on-stack alignment if needed. */
12895 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
12896 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
12897 build_int_cst (TREE_TYPE (t
), -align
));
12900 /* Args are passed right-aligned. */
12901 if (BYTES_BIG_ENDIAN
)
12902 t
= fold_build_pointer_plus_hwi (t
, pad
);
12904 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
12906 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
12908 t
= fold_build_pointer_plus_hwi (t
, size
);
12909 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
12913 stmt
= gimple_build_label (lab_over
);
12914 gimple_seq_add_stmt (pre_p
, stmt
);
12917 if (STRICT_ALIGNMENT
12918 && (TYPE_ALIGN (type
)
12919 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
12921 /* The value (of type complex double, for example) may not be
12922 aligned in memory in the saved registers, so copy via a
12923 temporary. (This is the same code as used for SPARC.) */
12924 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
12925 tree dest_addr
= build_fold_addr_expr (tmp
);
12927 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
12928 3, dest_addr
, addr
, size_int (rsize
* 4));
12929 TREE_ADDRESSABLE (tmp
) = 1;
12931 gimplify_and_add (copy
, pre_p
);
12935 addr
= fold_convert (ptrtype
, addr
);
12936 return build_va_arg_indirect_ref (addr
);
12942 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
12945 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
12946 const char *attr_string
= "";
12948 gcc_assert (name
!= NULL
);
12949 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
12951 if (rs6000_builtin_decls
[(int)code
])
12952 fatal_error (input_location
,
12953 "internal error: builtin function %qs already processed",
12956 rs6000_builtin_decls
[(int)code
] = t
=
12957 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
12959 /* Set any special attributes. */
12960 if ((classify
& RS6000_BTC_CONST
) != 0)
12962 /* const function, function only depends on the inputs. */
12963 TREE_READONLY (t
) = 1;
12964 TREE_NOTHROW (t
) = 1;
12965 attr_string
= ", const";
12967 else if ((classify
& RS6000_BTC_PURE
) != 0)
12969 /* pure function, function can read global memory, but does not set any
12971 DECL_PURE_P (t
) = 1;
12972 TREE_NOTHROW (t
) = 1;
12973 attr_string
= ", pure";
12975 else if ((classify
& RS6000_BTC_FP
) != 0)
12977 /* Function is a math function. If rounding mode is on, then treat the
12978 function as not reading global memory, but it can have arbitrary side
12979 effects. If it is off, then assume the function is a const function.
12980 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12981 builtin-attribute.def that is used for the math functions. */
12982 TREE_NOTHROW (t
) = 1;
12983 if (flag_rounding_math
)
12985 DECL_PURE_P (t
) = 1;
12986 DECL_IS_NOVOPS (t
) = 1;
12987 attr_string
= ", fp, pure";
12991 TREE_READONLY (t
) = 1;
12992 attr_string
= ", fp, const";
12995 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
12996 gcc_unreachable ();
12998 if (TARGET_DEBUG_BUILTIN
)
12999 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
13000 (int)code
, name
, attr_string
);
13003 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13005 #undef RS6000_BUILTIN_0
13006 #undef RS6000_BUILTIN_1
13007 #undef RS6000_BUILTIN_2
13008 #undef RS6000_BUILTIN_3
13009 #undef RS6000_BUILTIN_A
13010 #undef RS6000_BUILTIN_D
13011 #undef RS6000_BUILTIN_H
13012 #undef RS6000_BUILTIN_P
13013 #undef RS6000_BUILTIN_X
13015 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13016 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13017 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13018 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13019 { MASK, ICODE, NAME, ENUM },
13021 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13022 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13023 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13024 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13025 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13027 static const struct builtin_description bdesc_3arg
[] =
13029 #include "rs6000-builtin.def"
13032 /* DST operations: void foo (void *, const int, const char). */
13034 #undef RS6000_BUILTIN_0
13035 #undef RS6000_BUILTIN_1
13036 #undef RS6000_BUILTIN_2
13037 #undef RS6000_BUILTIN_3
13038 #undef RS6000_BUILTIN_A
13039 #undef RS6000_BUILTIN_D
13040 #undef RS6000_BUILTIN_H
13041 #undef RS6000_BUILTIN_P
13042 #undef RS6000_BUILTIN_X
13044 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13045 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13046 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13047 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13048 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13049 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13050 { MASK, ICODE, NAME, ENUM },
13052 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13053 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13054 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13056 static const struct builtin_description bdesc_dst
[] =
13058 #include "rs6000-builtin.def"
13061 /* Simple binary operations: VECc = foo (VECa, VECb). */
13063 #undef RS6000_BUILTIN_0
13064 #undef RS6000_BUILTIN_1
13065 #undef RS6000_BUILTIN_2
13066 #undef RS6000_BUILTIN_3
13067 #undef RS6000_BUILTIN_A
13068 #undef RS6000_BUILTIN_D
13069 #undef RS6000_BUILTIN_H
13070 #undef RS6000_BUILTIN_P
13071 #undef RS6000_BUILTIN_X
13073 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13074 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13075 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13076 { MASK, ICODE, NAME, ENUM },
13078 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13079 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13080 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13081 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13082 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13083 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13085 static const struct builtin_description bdesc_2arg
[] =
13087 #include "rs6000-builtin.def"
13090 #undef RS6000_BUILTIN_0
13091 #undef RS6000_BUILTIN_1
13092 #undef RS6000_BUILTIN_2
13093 #undef RS6000_BUILTIN_3
13094 #undef RS6000_BUILTIN_A
13095 #undef RS6000_BUILTIN_D
13096 #undef RS6000_BUILTIN_H
13097 #undef RS6000_BUILTIN_P
13098 #undef RS6000_BUILTIN_X
13100 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13101 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13102 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13103 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13104 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13105 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13106 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13107 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13108 { MASK, ICODE, NAME, ENUM },
13110 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13112 /* AltiVec predicates. */
13114 static const struct builtin_description bdesc_altivec_preds
[] =
13116 #include "rs6000-builtin.def"
13119 /* ABS* operations. */
13121 #undef RS6000_BUILTIN_0
13122 #undef RS6000_BUILTIN_1
13123 #undef RS6000_BUILTIN_2
13124 #undef RS6000_BUILTIN_3
13125 #undef RS6000_BUILTIN_A
13126 #undef RS6000_BUILTIN_D
13127 #undef RS6000_BUILTIN_H
13128 #undef RS6000_BUILTIN_P
13129 #undef RS6000_BUILTIN_X
13131 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13132 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13133 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13134 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13135 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13136 { MASK, ICODE, NAME, ENUM },
13138 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13139 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13140 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13141 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13143 static const struct builtin_description bdesc_abs
[] =
13145 #include "rs6000-builtin.def"
13148 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13151 #undef RS6000_BUILTIN_0
13152 #undef RS6000_BUILTIN_1
13153 #undef RS6000_BUILTIN_2
13154 #undef RS6000_BUILTIN_3
13155 #undef RS6000_BUILTIN_A
13156 #undef RS6000_BUILTIN_D
13157 #undef RS6000_BUILTIN_H
13158 #undef RS6000_BUILTIN_P
13159 #undef RS6000_BUILTIN_X
13161 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13162 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13163 { MASK, ICODE, NAME, ENUM },
13165 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13166 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13167 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13168 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13169 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13170 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13171 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13173 static const struct builtin_description bdesc_1arg
[] =
13175 #include "rs6000-builtin.def"
13178 /* Simple no-argument operations: result = __builtin_darn_32 () */
13180 #undef RS6000_BUILTIN_0
13181 #undef RS6000_BUILTIN_1
13182 #undef RS6000_BUILTIN_2
13183 #undef RS6000_BUILTIN_3
13184 #undef RS6000_BUILTIN_A
13185 #undef RS6000_BUILTIN_D
13186 #undef RS6000_BUILTIN_H
13187 #undef RS6000_BUILTIN_P
13188 #undef RS6000_BUILTIN_X
13190 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13191 { MASK, ICODE, NAME, ENUM },
13193 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13194 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13195 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13196 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13197 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13198 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13199 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13200 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13202 static const struct builtin_description bdesc_0arg
[] =
13204 #include "rs6000-builtin.def"
13207 /* HTM builtins. */
13208 #undef RS6000_BUILTIN_0
13209 #undef RS6000_BUILTIN_1
13210 #undef RS6000_BUILTIN_2
13211 #undef RS6000_BUILTIN_3
13212 #undef RS6000_BUILTIN_A
13213 #undef RS6000_BUILTIN_D
13214 #undef RS6000_BUILTIN_H
13215 #undef RS6000_BUILTIN_P
13216 #undef RS6000_BUILTIN_X
13218 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13219 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13220 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13221 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13222 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13223 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13224 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13225 { MASK, ICODE, NAME, ENUM },
13227 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13228 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13230 static const struct builtin_description bdesc_htm
[] =
13232 #include "rs6000-builtin.def"
13235 #undef RS6000_BUILTIN_0
13236 #undef RS6000_BUILTIN_1
13237 #undef RS6000_BUILTIN_2
13238 #undef RS6000_BUILTIN_3
13239 #undef RS6000_BUILTIN_A
13240 #undef RS6000_BUILTIN_D
13241 #undef RS6000_BUILTIN_H
13242 #undef RS6000_BUILTIN_P
13244 /* Return true if a builtin function is overloaded. */
13246 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
13248 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
13252 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode
)
13254 return rs6000_builtin_info
[(int)fncode
].name
;
13257 /* Expand an expression EXP that calls a builtin without arguments. */
13259 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
13262 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13264 if (icode
== CODE_FOR_nothing
)
13265 /* Builtin not supported on this processor. */
13268 if (icode
== CODE_FOR_rs6000_mffsl
13269 && rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13271 error ("__builtin_mffsl() not supported with -msoft-float");
13276 || GET_MODE (target
) != tmode
13277 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13278 target
= gen_reg_rtx (tmode
);
13280 pat
= GEN_FCN (icode
) (target
);
13290 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
13293 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13294 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13295 rtx op0
= expand_normal (arg0
);
13296 rtx op1
= expand_normal (arg1
);
13297 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13298 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13300 if (icode
== CODE_FOR_nothing
)
13301 /* Builtin not supported on this processor. */
13304 /* If we got invalid arguments bail out before generating bad rtl. */
13305 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13308 if (GET_CODE (op0
) != CONST_INT
13309 || INTVAL (op0
) > 255
13310 || INTVAL (op0
) < 0)
13312 error ("argument 1 must be an 8-bit field value");
13316 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13317 op0
= copy_to_mode_reg (mode0
, op0
);
13319 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13320 op1
= copy_to_mode_reg (mode1
, op1
);
13322 pat
= GEN_FCN (icode
) (op0
, op1
);
13331 rs6000_expand_mtfsb_builtin (enum insn_code icode
, tree exp
)
13334 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13335 rtx op0
= expand_normal (arg0
);
13337 if (icode
== CODE_FOR_nothing
)
13338 /* Builtin not supported on this processor. */
13341 if (rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13343 error ("__builtin_mtfsb0 and __builtin_mtfsb1 not supported with -msoft-float");
13347 /* If we got invalid arguments bail out before generating bad rtl. */
13348 if (arg0
== error_mark_node
)
13351 /* Only allow bit numbers 0 to 31. */
13352 if (!u5bit_cint_operand (op0
, VOIDmode
))
13354 error ("Argument must be a constant between 0 and 31.");
13358 pat
= GEN_FCN (icode
) (op0
);
13367 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode
, tree exp
)
13370 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13371 rtx op0
= expand_normal (arg0
);
13372 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13374 if (icode
== CODE_FOR_nothing
)
13375 /* Builtin not supported on this processor. */
13378 if (rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13380 error ("__builtin_set_fpscr_rn not supported with -msoft-float");
13384 /* If we got invalid arguments bail out before generating bad rtl. */
13385 if (arg0
== error_mark_node
)
13388 /* If the argument is a constant, check the range. Argument can only be a
13389 2-bit value. Unfortunately, can't check the range of the value at
13390 compile time if the argument is a variable. The least significant two
13391 bits of the argument, regardless of type, are used to set the rounding
13392 mode. All other bits are ignored. */
13393 if (GET_CODE (op0
) == CONST_INT
&& !const_0_to_3_operand(op0
, VOIDmode
))
13395 error ("Argument must be a value between 0 and 3.");
13399 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13400 op0
= copy_to_mode_reg (mode0
, op0
);
13402 pat
= GEN_FCN (icode
) (op0
);
13410 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode
, tree exp
)
13413 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13414 rtx op0
= expand_normal (arg0
);
13415 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13418 /* Builtin not supported in 32-bit mode. */
13419 fatal_error (input_location
,
13420 "__builtin_set_fpscr_drn is not supported in 32-bit mode.");
13422 if (rs6000_isa_flags_explicit
& OPTION_MASK_SOFT_FLOAT
)
13424 error ("__builtin_set_fpscr_drn not supported with -msoft-float");
13428 if (icode
== CODE_FOR_nothing
)
13429 /* Builtin not supported on this processor. */
13432 /* If we got invalid arguments bail out before generating bad rtl. */
13433 if (arg0
== error_mark_node
)
13436 /* If the argument is a constant, check the range. Agrument can only be a
13437 3-bit value. Unfortunately, can't check the range of the value at
13438 compile time if the argument is a variable. The least significant two
13439 bits of the argument, regardless of type, are used to set the rounding
13440 mode. All other bits are ignored. */
13441 if (GET_CODE (op0
) == CONST_INT
&& !const_0_to_7_operand(op0
, VOIDmode
))
13443 error ("Argument must be a value between 0 and 7.");
13447 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13448 op0
= copy_to_mode_reg (mode0
, op0
);
13450 pat
= GEN_FCN (icode
) (op0
);
13459 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13462 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13463 rtx op0
= expand_normal (arg0
);
13464 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13465 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13467 if (icode
== CODE_FOR_nothing
)
13468 /* Builtin not supported on this processor. */
13471 /* If we got invalid arguments bail out before generating bad rtl. */
13472 if (arg0
== error_mark_node
)
13475 if (icode
== CODE_FOR_altivec_vspltisb
13476 || icode
== CODE_FOR_altivec_vspltish
13477 || icode
== CODE_FOR_altivec_vspltisw
)
13479 /* Only allow 5-bit *signed* literals. */
13480 if (GET_CODE (op0
) != CONST_INT
13481 || INTVAL (op0
) > 15
13482 || INTVAL (op0
) < -16)
13484 error ("argument 1 must be a 5-bit signed literal");
13485 return CONST0_RTX (tmode
);
13490 || GET_MODE (target
) != tmode
13491 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13492 target
= gen_reg_rtx (tmode
);
13494 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13495 op0
= copy_to_mode_reg (mode0
, op0
);
13497 pat
= GEN_FCN (icode
) (target
, op0
);
13506 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
13508 rtx pat
, scratch1
, scratch2
;
13509 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13510 rtx op0
= expand_normal (arg0
);
13511 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13512 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13514 /* If we have invalid arguments, bail out before generating bad rtl. */
13515 if (arg0
== error_mark_node
)
13519 || GET_MODE (target
) != tmode
13520 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13521 target
= gen_reg_rtx (tmode
);
13523 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13524 op0
= copy_to_mode_reg (mode0
, op0
);
13526 scratch1
= gen_reg_rtx (mode0
);
13527 scratch2
= gen_reg_rtx (mode0
);
13529 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
13538 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13541 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13542 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13543 rtx op0
= expand_normal (arg0
);
13544 rtx op1
= expand_normal (arg1
);
13545 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13546 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13547 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13549 if (icode
== CODE_FOR_nothing
)
13550 /* Builtin not supported on this processor. */
13553 /* If we got invalid arguments bail out before generating bad rtl. */
13554 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13557 if (icode
== CODE_FOR_unpackv1ti
13558 || icode
== CODE_FOR_unpackkf
13559 || icode
== CODE_FOR_unpacktf
13560 || icode
== CODE_FOR_unpackif
13561 || icode
== CODE_FOR_unpacktd
)
13563 /* Only allow 1-bit unsigned literals. */
13565 if (TREE_CODE (arg1
) != INTEGER_CST
13566 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
13568 error ("argument 2 must be a 1-bit unsigned literal");
13569 return CONST0_RTX (tmode
);
13572 else if (icode
== CODE_FOR_altivec_vspltw
)
13574 /* Only allow 2-bit unsigned literals. */
13576 if (TREE_CODE (arg1
) != INTEGER_CST
13577 || TREE_INT_CST_LOW (arg1
) & ~3)
13579 error ("argument 2 must be a 2-bit unsigned literal");
13580 return CONST0_RTX (tmode
);
13583 else if (icode
== CODE_FOR_altivec_vsplth
)
13585 /* Only allow 3-bit unsigned literals. */
13587 if (TREE_CODE (arg1
) != INTEGER_CST
13588 || TREE_INT_CST_LOW (arg1
) & ~7)
13590 error ("argument 2 must be a 3-bit unsigned literal");
13591 return CONST0_RTX (tmode
);
13594 else if (icode
== CODE_FOR_altivec_vspltb
)
13596 /* Only allow 4-bit unsigned literals. */
13598 if (TREE_CODE (arg1
) != INTEGER_CST
13599 || TREE_INT_CST_LOW (arg1
) & ~15)
13601 error ("argument 2 must be a 4-bit unsigned literal");
13602 return CONST0_RTX (tmode
);
13605 else if (icode
== CODE_FOR_altivec_vcfux
13606 || icode
== CODE_FOR_altivec_vcfsx
13607 || icode
== CODE_FOR_altivec_vctsxs
13608 || icode
== CODE_FOR_altivec_vctuxs
)
13610 /* Only allow 5-bit unsigned literals. */
13612 if (TREE_CODE (arg1
) != INTEGER_CST
13613 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13615 error ("argument 2 must be a 5-bit unsigned literal");
13616 return CONST0_RTX (tmode
);
13619 else if (icode
== CODE_FOR_dfptstsfi_eq_dd
13620 || icode
== CODE_FOR_dfptstsfi_lt_dd
13621 || icode
== CODE_FOR_dfptstsfi_gt_dd
13622 || icode
== CODE_FOR_dfptstsfi_unordered_dd
13623 || icode
== CODE_FOR_dfptstsfi_eq_td
13624 || icode
== CODE_FOR_dfptstsfi_lt_td
13625 || icode
== CODE_FOR_dfptstsfi_gt_td
13626 || icode
== CODE_FOR_dfptstsfi_unordered_td
)
13628 /* Only allow 6-bit unsigned literals. */
13630 if (TREE_CODE (arg0
) != INTEGER_CST
13631 || !IN_RANGE (TREE_INT_CST_LOW (arg0
), 0, 63))
13633 error ("argument 1 must be a 6-bit unsigned literal");
13634 return CONST0_RTX (tmode
);
13637 else if (icode
== CODE_FOR_xststdcqp_kf
13638 || icode
== CODE_FOR_xststdcqp_tf
13639 || icode
== CODE_FOR_xststdcdp
13640 || icode
== CODE_FOR_xststdcsp
13641 || icode
== CODE_FOR_xvtstdcdp
13642 || icode
== CODE_FOR_xvtstdcsp
)
13644 /* Only allow 7-bit unsigned literals. */
13646 if (TREE_CODE (arg1
) != INTEGER_CST
13647 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 127))
13649 error ("argument 2 must be a 7-bit unsigned literal");
13650 return CONST0_RTX (tmode
);
13655 || GET_MODE (target
) != tmode
13656 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13657 target
= gen_reg_rtx (tmode
);
13659 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13660 op0
= copy_to_mode_reg (mode0
, op0
);
13661 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13662 op1
= copy_to_mode_reg (mode1
, op1
);
13664 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13673 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13676 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
13677 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13678 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13679 rtx op0
= expand_normal (arg0
);
13680 rtx op1
= expand_normal (arg1
);
13681 machine_mode tmode
= SImode
;
13682 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13683 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13686 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
13688 error ("argument 1 of %qs must be a constant",
13689 "__builtin_altivec_predicate");
13693 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
13695 gcc_assert (mode0
== mode1
);
13697 /* If we have invalid arguments, bail out before generating bad rtl. */
13698 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13702 || GET_MODE (target
) != tmode
13703 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13704 target
= gen_reg_rtx (tmode
);
13706 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13707 op0
= copy_to_mode_reg (mode0
, op0
);
13708 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13709 op1
= copy_to_mode_reg (mode1
, op1
);
13711 /* Note that for many of the relevant operations (e.g. cmpne or
13712 cmpeq) with float or double operands, it makes more sense for the
13713 mode of the allocated scratch register to select a vector of
13714 integer. But the choice to copy the mode of operand 0 was made
13715 long ago and there are no plans to change it. */
13716 scratch
= gen_reg_rtx (mode0
);
13718 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13723 /* The vec_any* and vec_all* predicates use the same opcodes for two
13724 different operations, but the bits in CR6 will be different
13725 depending on what information we want. So we have to play tricks
13726 with CR6 to get the right bits out.
13728 If you think this is disgusting, look at the specs for the
13729 AltiVec predicates. */
13731 switch (cr6_form_int
)
13734 emit_insn (gen_cr6_test_for_zero (target
));
13737 emit_insn (gen_cr6_test_for_zero_reverse (target
));
13740 emit_insn (gen_cr6_test_for_lt (target
));
13743 emit_insn (gen_cr6_test_for_lt_reverse (target
));
13746 error ("argument 1 of %qs is out of range",
13747 "__builtin_altivec_predicate");
13755 swap_endian_selector_for_mode (machine_mode mode
)
13757 unsigned int swap1
[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13758 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13759 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13760 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13762 unsigned int *swaparray
, i
;
13782 gcc_unreachable ();
13785 for (i
= 0; i
< 16; ++i
)
13786 perm
[i
] = GEN_INT (swaparray
[i
]);
13788 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
,
13789 gen_rtvec_v (16, perm
)));
13793 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
13796 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13797 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13798 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13799 machine_mode mode0
= Pmode
;
13800 machine_mode mode1
= Pmode
;
13801 rtx op0
= expand_normal (arg0
);
13802 rtx op1
= expand_normal (arg1
);
13804 if (icode
== CODE_FOR_nothing
)
13805 /* Builtin not supported on this processor. */
13808 /* If we got invalid arguments bail out before generating bad rtl. */
13809 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13813 || GET_MODE (target
) != tmode
13814 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13815 target
= gen_reg_rtx (tmode
);
13817 op1
= copy_to_mode_reg (mode1
, op1
);
13819 /* For LVX, express the RTL accurately by ANDing the address with -16.
13820 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13821 so the raw address is fine. */
13822 if (icode
== CODE_FOR_altivec_lvx_v1ti
13823 || icode
== CODE_FOR_altivec_lvx_v2df
13824 || icode
== CODE_FOR_altivec_lvx_v2di
13825 || icode
== CODE_FOR_altivec_lvx_v4sf
13826 || icode
== CODE_FOR_altivec_lvx_v4si
13827 || icode
== CODE_FOR_altivec_lvx_v8hi
13828 || icode
== CODE_FOR_altivec_lvx_v16qi
)
13831 if (op0
== const0_rtx
)
13835 op0
= copy_to_mode_reg (mode0
, op0
);
13836 rawaddr
= gen_rtx_PLUS (Pmode
, op1
, op0
);
13838 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
13839 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, addr
);
13841 emit_insn (gen_rtx_SET (target
, addr
));
13845 if (op0
== const0_rtx
)
13846 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
13849 op0
= copy_to_mode_reg (mode0
, op0
);
13850 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
,
13851 gen_rtx_PLUS (Pmode
, op1
, op0
));
13854 pat
= GEN_FCN (icode
) (target
, addr
);
13864 altivec_expand_stxvl_builtin (enum insn_code icode
, tree exp
)
13867 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13868 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13869 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13870 rtx op0
= expand_normal (arg0
);
13871 rtx op1
= expand_normal (arg1
);
13872 rtx op2
= expand_normal (arg2
);
13873 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13874 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13875 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
13877 if (icode
== CODE_FOR_nothing
)
13878 /* Builtin not supported on this processor. */
13881 /* If we got invalid arguments bail out before generating bad rtl. */
13882 if (arg0
== error_mark_node
13883 || arg1
== error_mark_node
13884 || arg2
== error_mark_node
)
13887 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13888 op0
= copy_to_mode_reg (mode0
, op0
);
13889 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13890 op1
= copy_to_mode_reg (mode1
, op1
);
13891 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13892 op2
= copy_to_mode_reg (mode2
, op2
);
13894 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
13902 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
13904 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13905 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13906 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13907 rtx op0
= expand_normal (arg0
);
13908 rtx op1
= expand_normal (arg1
);
13909 rtx op2
= expand_normal (arg2
);
13910 rtx pat
, addr
, rawaddr
;
13911 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13912 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
13913 machine_mode mode1
= Pmode
;
13914 machine_mode mode2
= Pmode
;
13916 /* Invalid arguments. Bail before doing anything stoopid! */
13917 if (arg0
== error_mark_node
13918 || arg1
== error_mark_node
13919 || arg2
== error_mark_node
)
13922 op2
= copy_to_mode_reg (mode2
, op2
);
13924 /* For STVX, express the RTL accurately by ANDing the address with -16.
13925 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13926 so the raw address is fine. */
13927 if (icode
== CODE_FOR_altivec_stvx_v2df
13928 || icode
== CODE_FOR_altivec_stvx_v2di
13929 || icode
== CODE_FOR_altivec_stvx_v4sf
13930 || icode
== CODE_FOR_altivec_stvx_v4si
13931 || icode
== CODE_FOR_altivec_stvx_v8hi
13932 || icode
== CODE_FOR_altivec_stvx_v16qi
)
13934 if (op1
== const0_rtx
)
13938 op1
= copy_to_mode_reg (mode1
, op1
);
13939 rawaddr
= gen_rtx_PLUS (Pmode
, op2
, op1
);
13942 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
13943 addr
= gen_rtx_MEM (tmode
, addr
);
13945 op0
= copy_to_mode_reg (tmode
, op0
);
13947 emit_insn (gen_rtx_SET (addr
, op0
));
13951 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
13952 op0
= copy_to_mode_reg (smode
, op0
);
13954 if (op1
== const0_rtx
)
13955 addr
= gen_rtx_MEM (tmode
, op2
);
13958 op1
= copy_to_mode_reg (mode1
, op1
);
13959 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op2
, op1
));
13962 pat
= GEN_FCN (icode
) (addr
, op0
);
13970 /* Return the appropriate SPR number associated with the given builtin. */
13971 static inline HOST_WIDE_INT
13972 htm_spr_num (enum rs6000_builtins code
)
13974 if (code
== HTM_BUILTIN_GET_TFHAR
13975 || code
== HTM_BUILTIN_SET_TFHAR
)
13977 else if (code
== HTM_BUILTIN_GET_TFIAR
13978 || code
== HTM_BUILTIN_SET_TFIAR
)
13980 else if (code
== HTM_BUILTIN_GET_TEXASR
13981 || code
== HTM_BUILTIN_SET_TEXASR
)
13983 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
13984 || code
== HTM_BUILTIN_SET_TEXASRU
);
13985 return TEXASRU_SPR
;
13988 /* Return the appropriate SPR regno associated with the given builtin. */
13989 static inline HOST_WIDE_INT
13990 htm_spr_regno (enum rs6000_builtins code
)
13992 if (code
== HTM_BUILTIN_GET_TFHAR
13993 || code
== HTM_BUILTIN_SET_TFHAR
)
13994 return TFHAR_REGNO
;
13995 else if (code
== HTM_BUILTIN_GET_TFIAR
13996 || code
== HTM_BUILTIN_SET_TFIAR
)
13997 return TFIAR_REGNO
;
13998 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
13999 || code
== HTM_BUILTIN_SET_TEXASR
14000 || code
== HTM_BUILTIN_GET_TEXASRU
14001 || code
== HTM_BUILTIN_SET_TEXASRU
);
14002 return TEXASR_REGNO
;
14005 /* Return the correct ICODE value depending on whether we are
14006 setting or reading the HTM SPRs. */
14007 static inline enum insn_code
14008 rs6000_htm_spr_icode (bool nonvoid
)
14011 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
14013 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
14016 /* Expand the HTM builtin in EXP and store the result in TARGET.
14017 Store true in *EXPANDEDP if we found a builtin to expand. */
14019 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
14021 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14022 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
14023 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14024 const struct builtin_description
*d
;
14029 if (!TARGET_POWERPC64
14030 && (fcode
== HTM_BUILTIN_TABORTDC
14031 || fcode
== HTM_BUILTIN_TABORTDCI
))
14033 size_t uns_fcode
= (size_t)fcode
;
14034 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
14035 error ("builtin %qs is only valid in 64-bit mode", name
);
14039 /* Expand the HTM builtins. */
14041 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14042 if (d
->code
== fcode
)
14044 rtx op
[MAX_HTM_OPERANDS
], pat
;
14047 call_expr_arg_iterator iter
;
14048 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
14049 enum insn_code icode
= d
->icode
;
14050 const struct insn_operand_data
*insn_op
;
14051 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
14055 icode
= rs6000_htm_spr_icode (nonvoid
);
14056 insn_op
= &insn_data
[icode
].operand
[0];
14060 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: E_SImode
;
14062 || GET_MODE (target
) != tmode
14063 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
14064 target
= gen_reg_rtx (tmode
);
14066 op
[nopnds
++] = target
;
14069 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
14071 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
14074 insn_op
= &insn_data
[icode
].operand
[nopnds
];
14076 op
[nopnds
] = expand_normal (arg
);
14078 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
14080 if (!strcmp (insn_op
->constraint
, "n"))
14082 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
14083 if (!CONST_INT_P (op
[nopnds
]))
14084 error ("argument %d must be an unsigned literal", arg_num
);
14086 error ("argument %d is an unsigned literal that is "
14087 "out of range", arg_num
);
14090 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
14096 /* Handle the builtins for extended mnemonics. These accept
14097 no arguments, but map to builtins that take arguments. */
14100 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
14101 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
14102 op
[nopnds
++] = GEN_INT (1);
14104 attr
|= RS6000_BTC_UNARY
;
14106 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
14107 op
[nopnds
++] = GEN_INT (0);
14109 attr
|= RS6000_BTC_UNARY
;
14115 /* If this builtin accesses SPRs, then pass in the appropriate
14116 SPR number and SPR regno as the last two operands. */
14119 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
14120 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
14121 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
14123 /* If this builtin accesses a CR, then pass in a scratch
14124 CR as the last operand. */
14125 else if (attr
& RS6000_BTC_CR
)
14126 { cr
= gen_reg_rtx (CCmode
);
14132 int expected_nopnds
= 0;
14133 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
14134 expected_nopnds
= 1;
14135 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
14136 expected_nopnds
= 2;
14137 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
14138 expected_nopnds
= 3;
14139 if (!(attr
& RS6000_BTC_VOID
))
14140 expected_nopnds
+= 1;
14142 expected_nopnds
+= 2;
14144 gcc_assert (nopnds
== expected_nopnds
14145 && nopnds
<= MAX_HTM_OPERANDS
);
14151 pat
= GEN_FCN (icode
) (op
[0]);
14154 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
14157 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
14160 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
14163 gcc_unreachable ();
14169 if (attr
& RS6000_BTC_CR
)
14171 if (fcode
== HTM_BUILTIN_TBEGIN
)
14173 /* Emit code to set TARGET to true or false depending on
14174 whether the tbegin. instruction successfully or failed
14175 to start a transaction. We do this by placing the 1's
14176 complement of CR's EQ bit into TARGET. */
14177 rtx scratch
= gen_reg_rtx (SImode
);
14178 emit_insn (gen_rtx_SET (scratch
,
14179 gen_rtx_EQ (SImode
, cr
,
14181 emit_insn (gen_rtx_SET (target
,
14182 gen_rtx_XOR (SImode
, scratch
,
14187 /* Emit code to copy the 4-bit condition register field
14188 CR into the least significant end of register TARGET. */
14189 rtx scratch1
= gen_reg_rtx (SImode
);
14190 rtx scratch2
= gen_reg_rtx (SImode
);
14191 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
14192 emit_insn (gen_movcc (subreg
, cr
));
14193 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
14194 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
14203 *expandedp
= false;
14207 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14210 cpu_expand_builtin (enum rs6000_builtins fcode
, tree exp ATTRIBUTE_UNUSED
,
14213 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14214 if (fcode
== RS6000_BUILTIN_CPU_INIT
)
14217 if (target
== 0 || GET_MODE (target
) != SImode
)
14218 target
= gen_reg_rtx (SImode
);
14220 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14221 tree arg
= TREE_OPERAND (CALL_EXPR_ARG (exp
, 0), 0);
14222 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14223 to a STRING_CST. */
14224 if (TREE_CODE (arg
) == ARRAY_REF
14225 && TREE_CODE (TREE_OPERAND (arg
, 0)) == STRING_CST
14226 && TREE_CODE (TREE_OPERAND (arg
, 1)) == INTEGER_CST
14227 && compare_tree_int (TREE_OPERAND (arg
, 1), 0) == 0)
14228 arg
= TREE_OPERAND (arg
, 0);
14230 if (TREE_CODE (arg
) != STRING_CST
)
14232 error ("builtin %qs only accepts a string argument",
14233 rs6000_builtin_info
[(size_t) fcode
].name
);
14237 if (fcode
== RS6000_BUILTIN_CPU_IS
)
14239 const char *cpu
= TREE_STRING_POINTER (arg
);
14240 rtx cpuid
= NULL_RTX
;
14241 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_is_info
); i
++)
14242 if (strcmp (cpu
, cpu_is_info
[i
].cpu
) == 0)
14244 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14245 cpuid
= GEN_INT (cpu_is_info
[i
].cpuid
+ _DL_FIRST_PLATFORM
);
14248 if (cpuid
== NULL_RTX
)
14250 /* Invalid CPU argument. */
14251 error ("cpu %qs is an invalid argument to builtin %qs",
14252 cpu
, rs6000_builtin_info
[(size_t) fcode
].name
);
14256 rtx platform
= gen_reg_rtx (SImode
);
14257 rtx tcbmem
= gen_const_mem (SImode
,
14258 gen_rtx_PLUS (Pmode
,
14259 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14260 GEN_INT (TCB_PLATFORM_OFFSET
)));
14261 emit_move_insn (platform
, tcbmem
);
14262 emit_insn (gen_eqsi3 (target
, platform
, cpuid
));
14264 else if (fcode
== RS6000_BUILTIN_CPU_SUPPORTS
)
14266 const char *hwcap
= TREE_STRING_POINTER (arg
);
14267 rtx mask
= NULL_RTX
;
14269 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_supports_info
); i
++)
14270 if (strcmp (hwcap
, cpu_supports_info
[i
].hwcap
) == 0)
14272 mask
= GEN_INT (cpu_supports_info
[i
].mask
);
14273 hwcap_offset
= TCB_HWCAP_OFFSET (cpu_supports_info
[i
].id
);
14276 if (mask
== NULL_RTX
)
14278 /* Invalid HWCAP argument. */
14279 error ("%s %qs is an invalid argument to builtin %qs",
14280 "hwcap", hwcap
, rs6000_builtin_info
[(size_t) fcode
].name
);
14284 rtx tcb_hwcap
= gen_reg_rtx (SImode
);
14285 rtx tcbmem
= gen_const_mem (SImode
,
14286 gen_rtx_PLUS (Pmode
,
14287 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14288 GEN_INT (hwcap_offset
)));
14289 emit_move_insn (tcb_hwcap
, tcbmem
);
14290 rtx scratch1
= gen_reg_rtx (SImode
);
14291 emit_insn (gen_rtx_SET (scratch1
, gen_rtx_AND (SImode
, tcb_hwcap
, mask
)));
14292 rtx scratch2
= gen_reg_rtx (SImode
);
14293 emit_insn (gen_eqsi3 (scratch2
, scratch1
, const0_rtx
));
14294 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (SImode
, scratch2
, const1_rtx
)));
14297 gcc_unreachable ();
14299 /* Record that we have expanded a CPU builtin, so that we can later
14300 emit a reference to the special symbol exported by LIBC to ensure we
14301 do not link against an old LIBC that doesn't support this feature. */
14302 cpu_builtin_p
= true;
14305 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14306 "capability bits", rs6000_builtin_info
[(size_t) fcode
].name
);
14308 /* For old LIBCs, always return FALSE. */
14309 emit_move_insn (target
, GEN_INT (0));
14310 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14316 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
14319 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14320 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14321 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14322 rtx op0
= expand_normal (arg0
);
14323 rtx op1
= expand_normal (arg1
);
14324 rtx op2
= expand_normal (arg2
);
14325 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14326 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14327 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14328 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
14330 if (icode
== CODE_FOR_nothing
)
14331 /* Builtin not supported on this processor. */
14334 /* If we got invalid arguments bail out before generating bad rtl. */
14335 if (arg0
== error_mark_node
14336 || arg1
== error_mark_node
14337 || arg2
== error_mark_node
)
14340 /* Check and prepare argument depending on the instruction code.
14342 Note that a switch statement instead of the sequence of tests
14343 would be incorrect as many of the CODE_FOR values could be
14344 CODE_FOR_nothing and that would yield multiple alternatives
14345 with identical values. We'd never reach here at runtime in
14347 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
14348 || icode
== CODE_FOR_altivec_vsldoi_v2df
14349 || icode
== CODE_FOR_altivec_vsldoi_v4si
14350 || icode
== CODE_FOR_altivec_vsldoi_v8hi
14351 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
14353 /* Only allow 4-bit unsigned literals. */
14355 if (TREE_CODE (arg2
) != INTEGER_CST
14356 || TREE_INT_CST_LOW (arg2
) & ~0xf)
14358 error ("argument 3 must be a 4-bit unsigned literal");
14359 return CONST0_RTX (tmode
);
14362 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
14363 || icode
== CODE_FOR_vsx_xxpermdi_v2di
14364 || icode
== CODE_FOR_vsx_xxpermdi_v2df_be
14365 || icode
== CODE_FOR_vsx_xxpermdi_v2di_be
14366 || icode
== CODE_FOR_vsx_xxpermdi_v1ti
14367 || icode
== CODE_FOR_vsx_xxpermdi_v4sf
14368 || icode
== CODE_FOR_vsx_xxpermdi_v4si
14369 || icode
== CODE_FOR_vsx_xxpermdi_v8hi
14370 || icode
== CODE_FOR_vsx_xxpermdi_v16qi
14371 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
14372 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
14373 || icode
== CODE_FOR_vsx_xxsldwi_v4si
14374 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
14375 || icode
== CODE_FOR_vsx_xxsldwi_v2di
14376 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
14378 /* Only allow 2-bit unsigned literals. */
14380 if (TREE_CODE (arg2
) != INTEGER_CST
14381 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14383 error ("argument 3 must be a 2-bit unsigned literal");
14384 return CONST0_RTX (tmode
);
14387 else if (icode
== CODE_FOR_vsx_set_v2df
14388 || icode
== CODE_FOR_vsx_set_v2di
14389 || icode
== CODE_FOR_bcdadd
14390 || icode
== CODE_FOR_bcdadd_lt
14391 || icode
== CODE_FOR_bcdadd_eq
14392 || icode
== CODE_FOR_bcdadd_gt
14393 || icode
== CODE_FOR_bcdsub
14394 || icode
== CODE_FOR_bcdsub_lt
14395 || icode
== CODE_FOR_bcdsub_eq
14396 || icode
== CODE_FOR_bcdsub_gt
)
14398 /* Only allow 1-bit unsigned literals. */
14400 if (TREE_CODE (arg2
) != INTEGER_CST
14401 || TREE_INT_CST_LOW (arg2
) & ~0x1)
14403 error ("argument 3 must be a 1-bit unsigned literal");
14404 return CONST0_RTX (tmode
);
14407 else if (icode
== CODE_FOR_dfp_ddedpd_dd
14408 || icode
== CODE_FOR_dfp_ddedpd_td
)
14410 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14412 if (TREE_CODE (arg0
) != INTEGER_CST
14413 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14415 error ("argument 1 must be 0 or 2");
14416 return CONST0_RTX (tmode
);
14419 else if (icode
== CODE_FOR_dfp_denbcd_dd
14420 || icode
== CODE_FOR_dfp_denbcd_td
)
14422 /* Only allow 1-bit unsigned literals. */
14424 if (TREE_CODE (arg0
) != INTEGER_CST
14425 || TREE_INT_CST_LOW (arg0
) & ~0x1)
14427 error ("argument 1 must be a 1-bit unsigned literal");
14428 return CONST0_RTX (tmode
);
14431 else if (icode
== CODE_FOR_dfp_dscli_dd
14432 || icode
== CODE_FOR_dfp_dscli_td
14433 || icode
== CODE_FOR_dfp_dscri_dd
14434 || icode
== CODE_FOR_dfp_dscri_td
)
14436 /* Only allow 6-bit unsigned literals. */
14438 if (TREE_CODE (arg1
) != INTEGER_CST
14439 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
14441 error ("argument 2 must be a 6-bit unsigned literal");
14442 return CONST0_RTX (tmode
);
14445 else if (icode
== CODE_FOR_crypto_vshasigmaw
14446 || icode
== CODE_FOR_crypto_vshasigmad
)
14448 /* Check whether the 2nd and 3rd arguments are integer constants and in
14449 range and prepare arguments. */
14451 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (wi::to_wide (arg1
), 2))
14453 error ("argument 2 must be 0 or 1");
14454 return CONST0_RTX (tmode
);
14458 if (TREE_CODE (arg2
) != INTEGER_CST
14459 || wi::geu_p (wi::to_wide (arg2
), 16))
14461 error ("argument 3 must be in the range 0..15");
14462 return CONST0_RTX (tmode
);
14467 || GET_MODE (target
) != tmode
14468 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14469 target
= gen_reg_rtx (tmode
);
14471 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14472 op0
= copy_to_mode_reg (mode0
, op0
);
14473 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14474 op1
= copy_to_mode_reg (mode1
, op1
);
14475 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
14476 op2
= copy_to_mode_reg (mode2
, op2
);
14478 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
14487 /* Expand the dst builtins. */
14489 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
14492 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14493 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14494 tree arg0
, arg1
, arg2
;
14495 machine_mode mode0
, mode1
;
14496 rtx pat
, op0
, op1
, op2
;
14497 const struct builtin_description
*d
;
14500 *expandedp
= false;
14502 /* Handle DST variants. */
14504 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14505 if (d
->code
== fcode
)
14507 arg0
= CALL_EXPR_ARG (exp
, 0);
14508 arg1
= CALL_EXPR_ARG (exp
, 1);
14509 arg2
= CALL_EXPR_ARG (exp
, 2);
14510 op0
= expand_normal (arg0
);
14511 op1
= expand_normal (arg1
);
14512 op2
= expand_normal (arg2
);
14513 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14514 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14516 /* Invalid arguments, bail out before generating bad rtl. */
14517 if (arg0
== error_mark_node
14518 || arg1
== error_mark_node
14519 || arg2
== error_mark_node
)
14524 if (TREE_CODE (arg2
) != INTEGER_CST
14525 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14527 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
14531 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
14532 op0
= copy_to_mode_reg (Pmode
, op0
);
14533 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
14534 op1
= copy_to_mode_reg (mode1
, op1
);
14536 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
14546 /* Expand vec_init builtin. */
14548 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
14550 machine_mode tmode
= TYPE_MODE (type
);
14551 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
14552 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
14554 gcc_assert (VECTOR_MODE_P (tmode
));
14555 gcc_assert (n_elt
== call_expr_nargs (exp
));
14557 if (!target
|| !register_operand (target
, tmode
))
14558 target
= gen_reg_rtx (tmode
);
14560 /* If we have a vector compromised of a single element, such as V1TImode, do
14561 the initialization directly. */
14562 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
14564 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
14565 emit_move_insn (target
, gen_lowpart (tmode
, x
));
14569 rtvec v
= rtvec_alloc (n_elt
);
14571 for (i
= 0; i
< n_elt
; ++i
)
14573 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
14574 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
14577 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
14583 /* Return the integer constant in ARG. Constrain it to be in the range
14584 of the subparts of VEC_TYPE; issue an error if not. */
14587 get_element_number (tree vec_type
, tree arg
)
14589 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
14591 if (!tree_fits_uhwi_p (arg
)
14592 || (elt
= tree_to_uhwi (arg
), elt
> max
))
14594 error ("selector must be an integer constant in the range 0..%wi", max
);
14601 /* Expand vec_set builtin. */
14603 altivec_expand_vec_set_builtin (tree exp
)
14605 machine_mode tmode
, mode1
;
14606 tree arg0
, arg1
, arg2
;
14610 arg0
= CALL_EXPR_ARG (exp
, 0);
14611 arg1
= CALL_EXPR_ARG (exp
, 1);
14612 arg2
= CALL_EXPR_ARG (exp
, 2);
14614 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
14615 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
14616 gcc_assert (VECTOR_MODE_P (tmode
));
14618 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
14619 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
14620 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
14622 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
14623 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
14625 op0
= force_reg (tmode
, op0
);
14626 op1
= force_reg (mode1
, op1
);
14628 rs6000_expand_vector_set (op0
, op1
, elt
);
14633 /* Expand vec_ext builtin. */
14635 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
14637 machine_mode tmode
, mode0
;
14642 arg0
= CALL_EXPR_ARG (exp
, 0);
14643 arg1
= CALL_EXPR_ARG (exp
, 1);
14645 op0
= expand_normal (arg0
);
14646 op1
= expand_normal (arg1
);
14648 /* Call get_element_number to validate arg1 if it is a constant. */
14649 if (TREE_CODE (arg1
) == INTEGER_CST
)
14650 (void) get_element_number (TREE_TYPE (arg0
), arg1
);
14652 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
14653 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
14654 gcc_assert (VECTOR_MODE_P (mode0
));
14656 op0
= force_reg (mode0
, op0
);
14658 if (optimize
|| !target
|| !register_operand (target
, tmode
))
14659 target
= gen_reg_rtx (tmode
);
14661 rs6000_expand_vector_extract (target
, op0
, op1
);
14666 /* Expand the builtin in EXP and store the result in TARGET. Store
14667 true in *EXPANDEDP if we found a builtin to expand. */
14669 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
14671 const struct builtin_description
*d
;
14673 enum insn_code icode
;
14674 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14675 tree arg0
, arg1
, arg2
;
14677 machine_mode tmode
, mode0
;
14678 enum rs6000_builtins fcode
14679 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14681 if (rs6000_overloaded_builtin_p (fcode
))
14684 error ("unresolved overload for Altivec builtin %qF", fndecl
);
14686 /* Given it is invalid, just generate a normal call. */
14687 return expand_call (exp
, target
, false);
14690 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
14698 case ALTIVEC_BUILTIN_STVX_V2DF
:
14699 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
14700 case ALTIVEC_BUILTIN_STVX_V2DI
:
14701 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
14702 case ALTIVEC_BUILTIN_STVX_V4SF
:
14703 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
14704 case ALTIVEC_BUILTIN_STVX
:
14705 case ALTIVEC_BUILTIN_STVX_V4SI
:
14706 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
14707 case ALTIVEC_BUILTIN_STVX_V8HI
:
14708 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
14709 case ALTIVEC_BUILTIN_STVX_V16QI
:
14710 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
14711 case ALTIVEC_BUILTIN_STVEBX
:
14712 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
14713 case ALTIVEC_BUILTIN_STVEHX
:
14714 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
14715 case ALTIVEC_BUILTIN_STVEWX
:
14716 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
14717 case ALTIVEC_BUILTIN_STVXL_V2DF
:
14718 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
14719 case ALTIVEC_BUILTIN_STVXL_V2DI
:
14720 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
14721 case ALTIVEC_BUILTIN_STVXL_V4SF
:
14722 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
14723 case ALTIVEC_BUILTIN_STVXL
:
14724 case ALTIVEC_BUILTIN_STVXL_V4SI
:
14725 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
14726 case ALTIVEC_BUILTIN_STVXL_V8HI
:
14727 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
14728 case ALTIVEC_BUILTIN_STVXL_V16QI
:
14729 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
14731 case ALTIVEC_BUILTIN_STVLX
:
14732 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
14733 case ALTIVEC_BUILTIN_STVLXL
:
14734 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
14735 case ALTIVEC_BUILTIN_STVRX
:
14736 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
14737 case ALTIVEC_BUILTIN_STVRXL
:
14738 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
14740 case P9V_BUILTIN_STXVL
:
14741 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl
, exp
);
14743 case P9V_BUILTIN_XST_LEN_R
:
14744 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r
, exp
);
14746 case VSX_BUILTIN_STXVD2X_V1TI
:
14747 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
14748 case VSX_BUILTIN_STXVD2X_V2DF
:
14749 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
14750 case VSX_BUILTIN_STXVD2X_V2DI
:
14751 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
14752 case VSX_BUILTIN_STXVW4X_V4SF
:
14753 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
14754 case VSX_BUILTIN_STXVW4X_V4SI
:
14755 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
14756 case VSX_BUILTIN_STXVW4X_V8HI
:
14757 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
14758 case VSX_BUILTIN_STXVW4X_V16QI
:
14759 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
14761 /* For the following on big endian, it's ok to use any appropriate
14762 unaligned-supporting store, so use a generic expander. For
14763 little-endian, the exact element-reversing instruction must
14765 case VSX_BUILTIN_ST_ELEMREV_V1TI
:
14767 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v1ti
14768 : CODE_FOR_vsx_st_elemrev_v1ti
);
14769 return altivec_expand_stv_builtin (code
, exp
);
14771 case VSX_BUILTIN_ST_ELEMREV_V2DF
:
14773 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2df
14774 : CODE_FOR_vsx_st_elemrev_v2df
);
14775 return altivec_expand_stv_builtin (code
, exp
);
14777 case VSX_BUILTIN_ST_ELEMREV_V2DI
:
14779 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2di
14780 : CODE_FOR_vsx_st_elemrev_v2di
);
14781 return altivec_expand_stv_builtin (code
, exp
);
14783 case VSX_BUILTIN_ST_ELEMREV_V4SF
:
14785 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4sf
14786 : CODE_FOR_vsx_st_elemrev_v4sf
);
14787 return altivec_expand_stv_builtin (code
, exp
);
14789 case VSX_BUILTIN_ST_ELEMREV_V4SI
:
14791 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4si
14792 : CODE_FOR_vsx_st_elemrev_v4si
);
14793 return altivec_expand_stv_builtin (code
, exp
);
14795 case VSX_BUILTIN_ST_ELEMREV_V8HI
:
14797 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v8hi
14798 : CODE_FOR_vsx_st_elemrev_v8hi
);
14799 return altivec_expand_stv_builtin (code
, exp
);
14801 case VSX_BUILTIN_ST_ELEMREV_V16QI
:
14803 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v16qi
14804 : CODE_FOR_vsx_st_elemrev_v16qi
);
14805 return altivec_expand_stv_builtin (code
, exp
);
14808 case ALTIVEC_BUILTIN_MFVSCR
:
14809 icode
= CODE_FOR_altivec_mfvscr
;
14810 tmode
= insn_data
[icode
].operand
[0].mode
;
14813 || GET_MODE (target
) != tmode
14814 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14815 target
= gen_reg_rtx (tmode
);
14817 pat
= GEN_FCN (icode
) (target
);
14823 case ALTIVEC_BUILTIN_MTVSCR
:
14824 icode
= CODE_FOR_altivec_mtvscr
;
14825 arg0
= CALL_EXPR_ARG (exp
, 0);
14826 op0
= expand_normal (arg0
);
14827 mode0
= insn_data
[icode
].operand
[0].mode
;
14829 /* If we got invalid arguments bail out before generating bad rtl. */
14830 if (arg0
== error_mark_node
)
14833 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
14834 op0
= copy_to_mode_reg (mode0
, op0
);
14836 pat
= GEN_FCN (icode
) (op0
);
14841 case ALTIVEC_BUILTIN_DSSALL
:
14842 emit_insn (gen_altivec_dssall ());
14845 case ALTIVEC_BUILTIN_DSS
:
14846 icode
= CODE_FOR_altivec_dss
;
14847 arg0
= CALL_EXPR_ARG (exp
, 0);
14849 op0
= expand_normal (arg0
);
14850 mode0
= insn_data
[icode
].operand
[0].mode
;
14852 /* If we got invalid arguments bail out before generating bad rtl. */
14853 if (arg0
== error_mark_node
)
14856 if (TREE_CODE (arg0
) != INTEGER_CST
14857 || TREE_INT_CST_LOW (arg0
) & ~0x3)
14859 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14863 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
14864 op0
= copy_to_mode_reg (mode0
, op0
);
14866 emit_insn (gen_altivec_dss (op0
));
14869 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
14870 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
14871 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
14872 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
14873 case VSX_BUILTIN_VEC_INIT_V2DF
:
14874 case VSX_BUILTIN_VEC_INIT_V2DI
:
14875 case VSX_BUILTIN_VEC_INIT_V1TI
:
14876 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
14878 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
14879 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
14880 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
14881 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
14882 case VSX_BUILTIN_VEC_SET_V2DF
:
14883 case VSX_BUILTIN_VEC_SET_V2DI
:
14884 case VSX_BUILTIN_VEC_SET_V1TI
:
14885 return altivec_expand_vec_set_builtin (exp
);
14887 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
14888 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
14889 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
14890 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
14891 case VSX_BUILTIN_VEC_EXT_V2DF
:
14892 case VSX_BUILTIN_VEC_EXT_V2DI
:
14893 case VSX_BUILTIN_VEC_EXT_V1TI
:
14894 return altivec_expand_vec_ext_builtin (exp
, target
);
14896 case P9V_BUILTIN_VEC_EXTRACT4B
:
14897 arg1
= CALL_EXPR_ARG (exp
, 1);
14900 /* Generate a normal call if it is invalid. */
14901 if (arg1
== error_mark_node
)
14902 return expand_call (exp
, target
, false);
14904 if (TREE_CODE (arg1
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg1
) > 12)
14906 error ("second argument to %qs must be 0..12", "vec_vextract4b");
14907 return expand_call (exp
, target
, false);
14911 case P9V_BUILTIN_VEC_INSERT4B
:
14912 arg2
= CALL_EXPR_ARG (exp
, 2);
14915 /* Generate a normal call if it is invalid. */
14916 if (arg2
== error_mark_node
)
14917 return expand_call (exp
, target
, false);
14919 if (TREE_CODE (arg2
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg2
) > 12)
14921 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
14922 return expand_call (exp
, target
, false);
14928 /* Fall through. */
14931 /* Expand abs* operations. */
14933 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14934 if (d
->code
== fcode
)
14935 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
14937 /* Expand the AltiVec predicates. */
14938 d
= bdesc_altivec_preds
;
14939 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14940 if (d
->code
== fcode
)
14941 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
14943 /* LV* are funky. We initialized them differently. */
14946 case ALTIVEC_BUILTIN_LVSL
:
14947 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
14948 exp
, target
, false);
14949 case ALTIVEC_BUILTIN_LVSR
:
14950 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
14951 exp
, target
, false);
14952 case ALTIVEC_BUILTIN_LVEBX
:
14953 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
14954 exp
, target
, false);
14955 case ALTIVEC_BUILTIN_LVEHX
:
14956 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
14957 exp
, target
, false);
14958 case ALTIVEC_BUILTIN_LVEWX
:
14959 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
14960 exp
, target
, false);
14961 case ALTIVEC_BUILTIN_LVXL_V2DF
:
14962 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
14963 exp
, target
, false);
14964 case ALTIVEC_BUILTIN_LVXL_V2DI
:
14965 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
14966 exp
, target
, false);
14967 case ALTIVEC_BUILTIN_LVXL_V4SF
:
14968 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
14969 exp
, target
, false);
14970 case ALTIVEC_BUILTIN_LVXL
:
14971 case ALTIVEC_BUILTIN_LVXL_V4SI
:
14972 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
14973 exp
, target
, false);
14974 case ALTIVEC_BUILTIN_LVXL_V8HI
:
14975 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
14976 exp
, target
, false);
14977 case ALTIVEC_BUILTIN_LVXL_V16QI
:
14978 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
14979 exp
, target
, false);
14980 case ALTIVEC_BUILTIN_LVX_V1TI
:
14981 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti
,
14982 exp
, target
, false);
14983 case ALTIVEC_BUILTIN_LVX_V2DF
:
14984 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
14985 exp
, target
, false);
14986 case ALTIVEC_BUILTIN_LVX_V2DI
:
14987 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
14988 exp
, target
, false);
14989 case ALTIVEC_BUILTIN_LVX_V4SF
:
14990 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
14991 exp
, target
, false);
14992 case ALTIVEC_BUILTIN_LVX
:
14993 case ALTIVEC_BUILTIN_LVX_V4SI
:
14994 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
14995 exp
, target
, false);
14996 case ALTIVEC_BUILTIN_LVX_V8HI
:
14997 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
14998 exp
, target
, false);
14999 case ALTIVEC_BUILTIN_LVX_V16QI
:
15000 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
15001 exp
, target
, false);
15002 case ALTIVEC_BUILTIN_LVLX
:
15003 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
15004 exp
, target
, true);
15005 case ALTIVEC_BUILTIN_LVLXL
:
15006 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
15007 exp
, target
, true);
15008 case ALTIVEC_BUILTIN_LVRX
:
15009 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
15010 exp
, target
, true);
15011 case ALTIVEC_BUILTIN_LVRXL
:
15012 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
15013 exp
, target
, true);
15014 case VSX_BUILTIN_LXVD2X_V1TI
:
15015 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
15016 exp
, target
, false);
15017 case VSX_BUILTIN_LXVD2X_V2DF
:
15018 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
15019 exp
, target
, false);
15020 case VSX_BUILTIN_LXVD2X_V2DI
:
15021 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
15022 exp
, target
, false);
15023 case VSX_BUILTIN_LXVW4X_V4SF
:
15024 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
15025 exp
, target
, false);
15026 case VSX_BUILTIN_LXVW4X_V4SI
:
15027 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
15028 exp
, target
, false);
15029 case VSX_BUILTIN_LXVW4X_V8HI
:
15030 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
15031 exp
, target
, false);
15032 case VSX_BUILTIN_LXVW4X_V16QI
:
15033 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
15034 exp
, target
, false);
15035 /* For the following on big endian, it's ok to use any appropriate
15036 unaligned-supporting load, so use a generic expander. For
15037 little-endian, the exact element-reversing instruction must
15039 case VSX_BUILTIN_LD_ELEMREV_V2DF
:
15041 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2df
15042 : CODE_FOR_vsx_ld_elemrev_v2df
);
15043 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15045 case VSX_BUILTIN_LD_ELEMREV_V1TI
:
15047 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v1ti
15048 : CODE_FOR_vsx_ld_elemrev_v1ti
);
15049 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15051 case VSX_BUILTIN_LD_ELEMREV_V2DI
:
15053 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2di
15054 : CODE_FOR_vsx_ld_elemrev_v2di
);
15055 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15057 case VSX_BUILTIN_LD_ELEMREV_V4SF
:
15059 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4sf
15060 : CODE_FOR_vsx_ld_elemrev_v4sf
);
15061 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15063 case VSX_BUILTIN_LD_ELEMREV_V4SI
:
15065 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4si
15066 : CODE_FOR_vsx_ld_elemrev_v4si
);
15067 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15069 case VSX_BUILTIN_LD_ELEMREV_V8HI
:
15071 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v8hi
15072 : CODE_FOR_vsx_ld_elemrev_v8hi
);
15073 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15075 case VSX_BUILTIN_LD_ELEMREV_V16QI
:
15077 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v16qi
15078 : CODE_FOR_vsx_ld_elemrev_v16qi
);
15079 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15084 /* Fall through. */
15087 *expandedp
= false;
15091 /* Check whether a builtin function is supported in this target
15094 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode
)
15096 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[fncode
].mask
;
15097 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
15103 /* Raise an error message for a builtin function that is called without the
15104 appropriate target options being set. */
15107 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
15109 size_t uns_fncode
= (size_t) fncode
;
15110 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
15111 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
15113 gcc_assert (name
!= NULL
);
15114 if ((fnmask
& RS6000_BTM_CELL
) != 0)
15115 error ("builtin function %qs is only valid for the cell processor", name
);
15116 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
15117 error ("builtin function %qs requires the %qs option", name
, "-mvsx");
15118 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
15119 error ("builtin function %qs requires the %qs option", name
, "-mhtm");
15120 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
15121 error ("builtin function %qs requires the %qs option", name
, "-maltivec");
15122 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
15123 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
15124 error ("builtin function %qs requires the %qs and %qs options",
15125 name
, "-mhard-dfp", "-mpower8-vector");
15126 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
15127 error ("builtin function %qs requires the %qs option", name
, "-mhard-dfp");
15128 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
15129 error ("builtin function %qs requires the %qs option", name
,
15130 "-mpower8-vector");
15131 else if ((fnmask
& (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
15132 == (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
15133 error ("builtin function %qs requires the %qs and %qs options",
15134 name
, "-mcpu=power9", "-m64");
15135 else if ((fnmask
& RS6000_BTM_P9_VECTOR
) != 0)
15136 error ("builtin function %qs requires the %qs option", name
,
15138 else if ((fnmask
& (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
15139 == (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
15140 error ("builtin function %qs requires the %qs and %qs options",
15141 name
, "-mcpu=power9", "-m64");
15142 else if ((fnmask
& RS6000_BTM_P9_MISC
) == RS6000_BTM_P9_MISC
)
15143 error ("builtin function %qs requires the %qs option", name
,
15145 else if ((fnmask
& RS6000_BTM_LDBL128
) == RS6000_BTM_LDBL128
)
15147 if (!TARGET_HARD_FLOAT
)
15148 error ("builtin function %qs requires the %qs option", name
,
15151 error ("builtin function %qs requires the %qs option", name
,
15152 TARGET_IEEEQUAD
? "-mabi=ibmlongdouble" : "-mlong-double-128");
15154 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
15155 error ("builtin function %qs requires the %qs option", name
,
15157 else if ((fnmask
& RS6000_BTM_FLOAT128_HW
) != 0)
15158 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
15160 else if ((fnmask
& RS6000_BTM_FLOAT128
) != 0)
15161 error ("builtin function %qs requires the %qs option", name
, "-mfloat128");
15162 else if ((fnmask
& (RS6000_BTM_POPCNTD
| RS6000_BTM_POWERPC64
))
15163 == (RS6000_BTM_POPCNTD
| RS6000_BTM_POWERPC64
))
15164 error ("builtin function %qs requires the %qs (or newer), and "
15165 "%qs or %qs options",
15166 name
, "-mcpu=power7", "-m64", "-mpowerpc64");
15168 error ("builtin function %qs is not supported with the current options",
15172 /* Target hook for early folding of built-ins, shamelessly stolen
15176 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED
,
15177 int n_args ATTRIBUTE_UNUSED
,
15178 tree
*args ATTRIBUTE_UNUSED
,
15179 bool ignore ATTRIBUTE_UNUSED
)
15181 #ifdef SUBTARGET_FOLD_BUILTIN
15182 return SUBTARGET_FOLD_BUILTIN (fndecl
, n_args
, args
, ignore
);
15188 /* Helper function to sort out which built-ins may be valid without having
15191 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code
)
15195 case ALTIVEC_BUILTIN_STVX_V16QI
:
15196 case ALTIVEC_BUILTIN_STVX_V8HI
:
15197 case ALTIVEC_BUILTIN_STVX_V4SI
:
15198 case ALTIVEC_BUILTIN_STVX_V4SF
:
15199 case ALTIVEC_BUILTIN_STVX_V2DI
:
15200 case ALTIVEC_BUILTIN_STVX_V2DF
:
15201 case VSX_BUILTIN_STXVW4X_V16QI
:
15202 case VSX_BUILTIN_STXVW4X_V8HI
:
15203 case VSX_BUILTIN_STXVW4X_V4SF
:
15204 case VSX_BUILTIN_STXVW4X_V4SI
:
15205 case VSX_BUILTIN_STXVD2X_V2DF
:
15206 case VSX_BUILTIN_STXVD2X_V2DI
:
15213 /* Helper function to handle the gimple folding of a vector compare
15214 operation. This sets up true/false vectors, and uses the
15215 VEC_COND_EXPR operation.
15216 CODE indicates which comparison is to be made. (EQ, GT, ...).
15217 TYPE indicates the type of the result. */
15219 fold_build_vec_cmp (tree_code code
, tree type
,
15220 tree arg0
, tree arg1
)
15222 tree cmp_type
= build_same_sized_truth_vector_type (type
);
15223 tree zero_vec
= build_zero_cst (type
);
15224 tree minus_one_vec
= build_minus_one_cst (type
);
15225 tree cmp
= fold_build2 (code
, cmp_type
, arg0
, arg1
);
15226 return fold_build3 (VEC_COND_EXPR
, type
, cmp
, minus_one_vec
, zero_vec
);
15229 /* Helper function to handle the in-between steps for the
15230 vector compare built-ins. */
15232 fold_compare_helper (gimple_stmt_iterator
*gsi
, tree_code code
, gimple
*stmt
)
15234 tree arg0
= gimple_call_arg (stmt
, 0);
15235 tree arg1
= gimple_call_arg (stmt
, 1);
15236 tree lhs
= gimple_call_lhs (stmt
);
15237 tree cmp
= fold_build_vec_cmp (code
, TREE_TYPE (lhs
), arg0
, arg1
);
15238 gimple
*g
= gimple_build_assign (lhs
, cmp
);
15239 gimple_set_location (g
, gimple_location (stmt
));
15240 gsi_replace (gsi
, g
, true);
15243 /* Helper function to map V2DF and V4SF types to their
15244 integral equivalents (V2DI and V4SI). */
15245 tree
map_to_integral_tree_type (tree input_tree_type
)
15247 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type
)))
15248 return input_tree_type
;
15251 if (types_compatible_p (TREE_TYPE (input_tree_type
),
15252 TREE_TYPE (V2DF_type_node
)))
15253 return V2DI_type_node
;
15254 else if (types_compatible_p (TREE_TYPE (input_tree_type
),
15255 TREE_TYPE (V4SF_type_node
)))
15256 return V4SI_type_node
;
15258 gcc_unreachable ();
15262 /* Helper function to handle the vector merge[hl] built-ins. The
15263 implementation difference between h and l versions for this code are in
15264 the values used when building of the permute vector for high word versus
15265 low word merge. The variance is keyed off the use_high parameter. */
15267 fold_mergehl_helper (gimple_stmt_iterator
*gsi
, gimple
*stmt
, int use_high
)
15269 tree arg0
= gimple_call_arg (stmt
, 0);
15270 tree arg1
= gimple_call_arg (stmt
, 1);
15271 tree lhs
= gimple_call_lhs (stmt
);
15272 tree lhs_type
= TREE_TYPE (lhs
);
15273 int n_elts
= TYPE_VECTOR_SUBPARTS (lhs_type
);
15274 int midpoint
= n_elts
/ 2;
15280 /* The permute_type will match the lhs for integral types. For double and
15281 float types, the permute type needs to map to the V2 or V4 type that
15284 permute_type
= map_to_integral_tree_type (lhs_type
);
15285 tree_vector_builder
elts (permute_type
, VECTOR_CST_NELTS (arg0
), 1);
15287 for (int i
= 0; i
< midpoint
; i
++)
15289 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15291 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15292 offset
+ n_elts
+ i
));
15295 tree permute
= elts
.build ();
15297 gimple
*g
= gimple_build_assign (lhs
, VEC_PERM_EXPR
, arg0
, arg1
, permute
);
15298 gimple_set_location (g
, gimple_location (stmt
));
15299 gsi_replace (gsi
, g
, true);
15302 /* Helper function to handle the vector merge[eo] built-ins. */
15304 fold_mergeeo_helper (gimple_stmt_iterator
*gsi
, gimple
*stmt
, int use_odd
)
15306 tree arg0
= gimple_call_arg (stmt
, 0);
15307 tree arg1
= gimple_call_arg (stmt
, 1);
15308 tree lhs
= gimple_call_lhs (stmt
);
15309 tree lhs_type
= TREE_TYPE (lhs
);
15310 int n_elts
= TYPE_VECTOR_SUBPARTS (lhs_type
);
15312 /* The permute_type will match the lhs for integral types. For double and
15313 float types, the permute type needs to map to the V2 or V4 type that
15316 permute_type
= map_to_integral_tree_type (lhs_type
);
15318 tree_vector_builder
elts (permute_type
, VECTOR_CST_NELTS (arg0
), 1);
15320 /* Build the permute vector. */
15321 for (int i
= 0; i
< n_elts
/ 2; i
++)
15323 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15325 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15326 2*i
+ use_odd
+ n_elts
));
15329 tree permute
= elts
.build ();
15331 gimple
*g
= gimple_build_assign (lhs
, VEC_PERM_EXPR
, arg0
, arg1
, permute
);
15332 gimple_set_location (g
, gimple_location (stmt
));
15333 gsi_replace (gsi
, g
, true);
15336 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15337 a constant, use rs6000_fold_builtin.) */
15340 rs6000_gimple_fold_builtin (gimple_stmt_iterator
*gsi
)
15342 gimple
*stmt
= gsi_stmt (*gsi
);
15343 tree fndecl
= gimple_call_fndecl (stmt
);
15344 gcc_checking_assert (fndecl
&& DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
);
15345 enum rs6000_builtins fn_code
15346 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15347 tree arg0
, arg1
, lhs
, temp
;
15350 size_t uns_fncode
= (size_t) fn_code
;
15351 enum insn_code icode
= rs6000_builtin_info
[uns_fncode
].icode
;
15352 const char *fn_name1
= rs6000_builtin_info
[uns_fncode
].name
;
15353 const char *fn_name2
= (icode
!= CODE_FOR_nothing
)
15354 ? get_insn_name ((int) icode
)
15357 if (TARGET_DEBUG_BUILTIN
)
15358 fprintf (stderr
, "rs6000_gimple_fold_builtin %d %s %s\n",
15359 fn_code
, fn_name1
, fn_name2
);
15361 if (!rs6000_fold_gimple
)
15364 /* Prevent gimple folding for code that does not have a LHS, unless it is
15365 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15366 if (!gimple_call_lhs (stmt
) && !rs6000_builtin_valid_without_lhs (fn_code
))
15369 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15370 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fncode
].mask
;
15371 bool func_valid_p
= (rs6000_builtin_mask
& mask
) == mask
;
15377 /* Flavors of vec_add. We deliberately don't expand
15378 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15379 TImode, resulting in much poorer code generation. */
15380 case ALTIVEC_BUILTIN_VADDUBM
:
15381 case ALTIVEC_BUILTIN_VADDUHM
:
15382 case ALTIVEC_BUILTIN_VADDUWM
:
15383 case P8V_BUILTIN_VADDUDM
:
15384 case ALTIVEC_BUILTIN_VADDFP
:
15385 case VSX_BUILTIN_XVADDDP
:
15386 arg0
= gimple_call_arg (stmt
, 0);
15387 arg1
= gimple_call_arg (stmt
, 1);
15388 lhs
= gimple_call_lhs (stmt
);
15389 g
= gimple_build_assign (lhs
, PLUS_EXPR
, arg0
, arg1
);
15390 gimple_set_location (g
, gimple_location (stmt
));
15391 gsi_replace (gsi
, g
, true);
15393 /* Flavors of vec_sub. We deliberately don't expand
15394 P8V_BUILTIN_VSUBUQM. */
15395 case ALTIVEC_BUILTIN_VSUBUBM
:
15396 case ALTIVEC_BUILTIN_VSUBUHM
:
15397 case ALTIVEC_BUILTIN_VSUBUWM
:
15398 case P8V_BUILTIN_VSUBUDM
:
15399 case ALTIVEC_BUILTIN_VSUBFP
:
15400 case VSX_BUILTIN_XVSUBDP
:
15401 arg0
= gimple_call_arg (stmt
, 0);
15402 arg1
= gimple_call_arg (stmt
, 1);
15403 lhs
= gimple_call_lhs (stmt
);
15404 g
= gimple_build_assign (lhs
, MINUS_EXPR
, arg0
, arg1
);
15405 gimple_set_location (g
, gimple_location (stmt
));
15406 gsi_replace (gsi
, g
, true);
15408 case VSX_BUILTIN_XVMULSP
:
15409 case VSX_BUILTIN_XVMULDP
:
15410 arg0
= gimple_call_arg (stmt
, 0);
15411 arg1
= gimple_call_arg (stmt
, 1);
15412 lhs
= gimple_call_lhs (stmt
);
15413 g
= gimple_build_assign (lhs
, MULT_EXPR
, arg0
, arg1
);
15414 gimple_set_location (g
, gimple_location (stmt
));
15415 gsi_replace (gsi
, g
, true);
15417 /* Even element flavors of vec_mul (signed). */
15418 case ALTIVEC_BUILTIN_VMULESB
:
15419 case ALTIVEC_BUILTIN_VMULESH
:
15420 case P8V_BUILTIN_VMULESW
:
15421 /* Even element flavors of vec_mul (unsigned). */
15422 case ALTIVEC_BUILTIN_VMULEUB
:
15423 case ALTIVEC_BUILTIN_VMULEUH
:
15424 case P8V_BUILTIN_VMULEUW
:
15425 arg0
= gimple_call_arg (stmt
, 0);
15426 arg1
= gimple_call_arg (stmt
, 1);
15427 lhs
= gimple_call_lhs (stmt
);
15428 g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_EVEN_EXPR
, arg0
, arg1
);
15429 gimple_set_location (g
, gimple_location (stmt
));
15430 gsi_replace (gsi
, g
, true);
15432 /* Odd element flavors of vec_mul (signed). */
15433 case ALTIVEC_BUILTIN_VMULOSB
:
15434 case ALTIVEC_BUILTIN_VMULOSH
:
15435 case P8V_BUILTIN_VMULOSW
:
15436 /* Odd element flavors of vec_mul (unsigned). */
15437 case ALTIVEC_BUILTIN_VMULOUB
:
15438 case ALTIVEC_BUILTIN_VMULOUH
:
15439 case P8V_BUILTIN_VMULOUW
:
15440 arg0
= gimple_call_arg (stmt
, 0);
15441 arg1
= gimple_call_arg (stmt
, 1);
15442 lhs
= gimple_call_lhs (stmt
);
15443 g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_ODD_EXPR
, arg0
, arg1
);
15444 gimple_set_location (g
, gimple_location (stmt
));
15445 gsi_replace (gsi
, g
, true);
15447 /* Flavors of vec_div (Integer). */
15448 case VSX_BUILTIN_DIV_V2DI
:
15449 case VSX_BUILTIN_UDIV_V2DI
:
15450 arg0
= gimple_call_arg (stmt
, 0);
15451 arg1
= gimple_call_arg (stmt
, 1);
15452 lhs
= gimple_call_lhs (stmt
);
15453 g
= gimple_build_assign (lhs
, TRUNC_DIV_EXPR
, arg0
, arg1
);
15454 gimple_set_location (g
, gimple_location (stmt
));
15455 gsi_replace (gsi
, g
, true);
15457 /* Flavors of vec_div (Float). */
15458 case VSX_BUILTIN_XVDIVSP
:
15459 case VSX_BUILTIN_XVDIVDP
:
15460 arg0
= gimple_call_arg (stmt
, 0);
15461 arg1
= gimple_call_arg (stmt
, 1);
15462 lhs
= gimple_call_lhs (stmt
);
15463 g
= gimple_build_assign (lhs
, RDIV_EXPR
, arg0
, arg1
);
15464 gimple_set_location (g
, gimple_location (stmt
));
15465 gsi_replace (gsi
, g
, true);
15467 /* Flavors of vec_and. */
15468 case ALTIVEC_BUILTIN_VAND
:
15469 arg0
= gimple_call_arg (stmt
, 0);
15470 arg1
= gimple_call_arg (stmt
, 1);
15471 lhs
= gimple_call_lhs (stmt
);
15472 g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, arg1
);
15473 gimple_set_location (g
, gimple_location (stmt
));
15474 gsi_replace (gsi
, g
, true);
15476 /* Flavors of vec_andc. */
15477 case ALTIVEC_BUILTIN_VANDC
:
15478 arg0
= gimple_call_arg (stmt
, 0);
15479 arg1
= gimple_call_arg (stmt
, 1);
15480 lhs
= gimple_call_lhs (stmt
);
15481 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15482 g
= gimple_build_assign (temp
, BIT_NOT_EXPR
, arg1
);
15483 gimple_set_location (g
, gimple_location (stmt
));
15484 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15485 g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, temp
);
15486 gimple_set_location (g
, gimple_location (stmt
));
15487 gsi_replace (gsi
, g
, true);
15489 /* Flavors of vec_nand. */
15490 case P8V_BUILTIN_VEC_NAND
:
15491 case P8V_BUILTIN_NAND_V16QI
:
15492 case P8V_BUILTIN_NAND_V8HI
:
15493 case P8V_BUILTIN_NAND_V4SI
:
15494 case P8V_BUILTIN_NAND_V4SF
:
15495 case P8V_BUILTIN_NAND_V2DF
:
15496 case P8V_BUILTIN_NAND_V2DI
:
15497 arg0
= gimple_call_arg (stmt
, 0);
15498 arg1
= gimple_call_arg (stmt
, 1);
15499 lhs
= gimple_call_lhs (stmt
);
15500 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15501 g
= gimple_build_assign (temp
, BIT_AND_EXPR
, arg0
, arg1
);
15502 gimple_set_location (g
, gimple_location (stmt
));
15503 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15504 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15505 gimple_set_location (g
, gimple_location (stmt
));
15506 gsi_replace (gsi
, g
, true);
15508 /* Flavors of vec_or. */
15509 case ALTIVEC_BUILTIN_VOR
:
15510 arg0
= gimple_call_arg (stmt
, 0);
15511 arg1
= gimple_call_arg (stmt
, 1);
15512 lhs
= gimple_call_lhs (stmt
);
15513 g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, arg1
);
15514 gimple_set_location (g
, gimple_location (stmt
));
15515 gsi_replace (gsi
, g
, true);
15517 /* flavors of vec_orc. */
15518 case P8V_BUILTIN_ORC_V16QI
:
15519 case P8V_BUILTIN_ORC_V8HI
:
15520 case P8V_BUILTIN_ORC_V4SI
:
15521 case P8V_BUILTIN_ORC_V4SF
:
15522 case P8V_BUILTIN_ORC_V2DF
:
15523 case P8V_BUILTIN_ORC_V2DI
:
15524 arg0
= gimple_call_arg (stmt
, 0);
15525 arg1
= gimple_call_arg (stmt
, 1);
15526 lhs
= gimple_call_lhs (stmt
);
15527 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15528 g
= gimple_build_assign (temp
, BIT_NOT_EXPR
, arg1
);
15529 gimple_set_location (g
, gimple_location (stmt
));
15530 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15531 g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, temp
);
15532 gimple_set_location (g
, gimple_location (stmt
));
15533 gsi_replace (gsi
, g
, true);
15535 /* Flavors of vec_xor. */
15536 case ALTIVEC_BUILTIN_VXOR
:
15537 arg0
= gimple_call_arg (stmt
, 0);
15538 arg1
= gimple_call_arg (stmt
, 1);
15539 lhs
= gimple_call_lhs (stmt
);
15540 g
= gimple_build_assign (lhs
, BIT_XOR_EXPR
, arg0
, arg1
);
15541 gimple_set_location (g
, gimple_location (stmt
));
15542 gsi_replace (gsi
, g
, true);
15544 /* Flavors of vec_nor. */
15545 case ALTIVEC_BUILTIN_VNOR
:
15546 arg0
= gimple_call_arg (stmt
, 0);
15547 arg1
= gimple_call_arg (stmt
, 1);
15548 lhs
= gimple_call_lhs (stmt
);
15549 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15550 g
= gimple_build_assign (temp
, BIT_IOR_EXPR
, arg0
, arg1
);
15551 gimple_set_location (g
, gimple_location (stmt
));
15552 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15553 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15554 gimple_set_location (g
, gimple_location (stmt
));
15555 gsi_replace (gsi
, g
, true);
15557 /* flavors of vec_abs. */
15558 case ALTIVEC_BUILTIN_ABS_V16QI
:
15559 case ALTIVEC_BUILTIN_ABS_V8HI
:
15560 case ALTIVEC_BUILTIN_ABS_V4SI
:
15561 case ALTIVEC_BUILTIN_ABS_V4SF
:
15562 case P8V_BUILTIN_ABS_V2DI
:
15563 case VSX_BUILTIN_XVABSDP
:
15564 arg0
= gimple_call_arg (stmt
, 0);
15565 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0
)))
15566 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0
))))
15568 lhs
= gimple_call_lhs (stmt
);
15569 g
= gimple_build_assign (lhs
, ABS_EXPR
, arg0
);
15570 gimple_set_location (g
, gimple_location (stmt
));
15571 gsi_replace (gsi
, g
, true);
15573 /* flavors of vec_min. */
15574 case VSX_BUILTIN_XVMINDP
:
15575 case P8V_BUILTIN_VMINSD
:
15576 case P8V_BUILTIN_VMINUD
:
15577 case ALTIVEC_BUILTIN_VMINSB
:
15578 case ALTIVEC_BUILTIN_VMINSH
:
15579 case ALTIVEC_BUILTIN_VMINSW
:
15580 case ALTIVEC_BUILTIN_VMINUB
:
15581 case ALTIVEC_BUILTIN_VMINUH
:
15582 case ALTIVEC_BUILTIN_VMINUW
:
15583 case ALTIVEC_BUILTIN_VMINFP
:
15584 arg0
= gimple_call_arg (stmt
, 0);
15585 arg1
= gimple_call_arg (stmt
, 1);
15586 lhs
= gimple_call_lhs (stmt
);
15587 g
= gimple_build_assign (lhs
, MIN_EXPR
, arg0
, arg1
);
15588 gimple_set_location (g
, gimple_location (stmt
));
15589 gsi_replace (gsi
, g
, true);
15591 /* flavors of vec_max. */
15592 case VSX_BUILTIN_XVMAXDP
:
15593 case P8V_BUILTIN_VMAXSD
:
15594 case P8V_BUILTIN_VMAXUD
:
15595 case ALTIVEC_BUILTIN_VMAXSB
:
15596 case ALTIVEC_BUILTIN_VMAXSH
:
15597 case ALTIVEC_BUILTIN_VMAXSW
:
15598 case ALTIVEC_BUILTIN_VMAXUB
:
15599 case ALTIVEC_BUILTIN_VMAXUH
:
15600 case ALTIVEC_BUILTIN_VMAXUW
:
15601 case ALTIVEC_BUILTIN_VMAXFP
:
15602 arg0
= gimple_call_arg (stmt
, 0);
15603 arg1
= gimple_call_arg (stmt
, 1);
15604 lhs
= gimple_call_lhs (stmt
);
15605 g
= gimple_build_assign (lhs
, MAX_EXPR
, arg0
, arg1
);
15606 gimple_set_location (g
, gimple_location (stmt
));
15607 gsi_replace (gsi
, g
, true);
15609 /* Flavors of vec_eqv. */
15610 case P8V_BUILTIN_EQV_V16QI
:
15611 case P8V_BUILTIN_EQV_V8HI
:
15612 case P8V_BUILTIN_EQV_V4SI
:
15613 case P8V_BUILTIN_EQV_V4SF
:
15614 case P8V_BUILTIN_EQV_V2DF
:
15615 case P8V_BUILTIN_EQV_V2DI
:
15616 arg0
= gimple_call_arg (stmt
, 0);
15617 arg1
= gimple_call_arg (stmt
, 1);
15618 lhs
= gimple_call_lhs (stmt
);
15619 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15620 g
= gimple_build_assign (temp
, BIT_XOR_EXPR
, arg0
, arg1
);
15621 gimple_set_location (g
, gimple_location (stmt
));
15622 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15623 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15624 gimple_set_location (g
, gimple_location (stmt
));
15625 gsi_replace (gsi
, g
, true);
15627 /* Flavors of vec_rotate_left. */
15628 case ALTIVEC_BUILTIN_VRLB
:
15629 case ALTIVEC_BUILTIN_VRLH
:
15630 case ALTIVEC_BUILTIN_VRLW
:
15631 case P8V_BUILTIN_VRLD
:
15632 arg0
= gimple_call_arg (stmt
, 0);
15633 arg1
= gimple_call_arg (stmt
, 1);
15634 lhs
= gimple_call_lhs (stmt
);
15635 g
= gimple_build_assign (lhs
, LROTATE_EXPR
, arg0
, arg1
);
15636 gimple_set_location (g
, gimple_location (stmt
));
15637 gsi_replace (gsi
, g
, true);
15639 /* Flavors of vector shift right algebraic.
15640 vec_sra{b,h,w} -> vsra{b,h,w}. */
15641 case ALTIVEC_BUILTIN_VSRAB
:
15642 case ALTIVEC_BUILTIN_VSRAH
:
15643 case ALTIVEC_BUILTIN_VSRAW
:
15644 case P8V_BUILTIN_VSRAD
:
15645 arg0
= gimple_call_arg (stmt
, 0);
15646 arg1
= gimple_call_arg (stmt
, 1);
15647 lhs
= gimple_call_lhs (stmt
);
15648 g
= gimple_build_assign (lhs
, RSHIFT_EXPR
, arg0
, arg1
);
15649 gimple_set_location (g
, gimple_location (stmt
));
15650 gsi_replace (gsi
, g
, true);
15652 /* Flavors of vector shift left.
15653 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15654 case ALTIVEC_BUILTIN_VSLB
:
15655 case ALTIVEC_BUILTIN_VSLH
:
15656 case ALTIVEC_BUILTIN_VSLW
:
15657 case P8V_BUILTIN_VSLD
:
15660 gimple_seq stmts
= NULL
;
15661 arg0
= gimple_call_arg (stmt
, 0);
15662 tree arg0_type
= TREE_TYPE (arg0
);
15663 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type
))
15664 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type
)))
15666 arg1
= gimple_call_arg (stmt
, 1);
15667 tree arg1_type
= TREE_TYPE (arg1
);
15668 tree unsigned_arg1_type
= unsigned_type_for (TREE_TYPE (arg1
));
15669 tree unsigned_element_type
= unsigned_type_for (TREE_TYPE (arg1_type
));
15670 loc
= gimple_location (stmt
);
15671 lhs
= gimple_call_lhs (stmt
);
15672 /* Force arg1 into the range valid matching the arg0 type. */
15673 /* Build a vector consisting of the max valid bit-size values. */
15674 int n_elts
= VECTOR_CST_NELTS (arg1
);
15675 int tree_size_in_bits
= TREE_INT_CST_LOW (size_in_bytes (arg1_type
))
15677 tree element_size
= build_int_cst (unsigned_element_type
,
15678 tree_size_in_bits
/ n_elts
);
15679 tree_vector_builder
elts (unsigned_type_for (arg1_type
), n_elts
, 1);
15680 for (int i
= 0; i
< n_elts
; i
++)
15681 elts
.safe_push (element_size
);
15682 tree modulo_tree
= elts
.build ();
15683 /* Modulo the provided shift value against that vector. */
15684 tree unsigned_arg1
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15685 unsigned_arg1_type
, arg1
);
15686 tree new_arg1
= gimple_build (&stmts
, loc
, TRUNC_MOD_EXPR
,
15687 unsigned_arg1_type
, unsigned_arg1
,
15689 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15690 /* And finally, do the shift. */
15691 g
= gimple_build_assign (lhs
, LSHIFT_EXPR
, arg0
, new_arg1
);
15692 gimple_set_location (g
, gimple_location (stmt
));
15693 gsi_replace (gsi
, g
, true);
15696 /* Flavors of vector shift right. */
15697 case ALTIVEC_BUILTIN_VSRB
:
15698 case ALTIVEC_BUILTIN_VSRH
:
15699 case ALTIVEC_BUILTIN_VSRW
:
15700 case P8V_BUILTIN_VSRD
:
15702 arg0
= gimple_call_arg (stmt
, 0);
15703 arg1
= gimple_call_arg (stmt
, 1);
15704 lhs
= gimple_call_lhs (stmt
);
15705 gimple_seq stmts
= NULL
;
15706 /* Convert arg0 to unsigned. */
15708 = gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15709 unsigned_type_for (TREE_TYPE (arg0
)), arg0
);
15711 = gimple_build (&stmts
, RSHIFT_EXPR
,
15712 TREE_TYPE (arg0_unsigned
), arg0_unsigned
, arg1
);
15713 /* Convert result back to the lhs type. */
15714 res
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
, TREE_TYPE (lhs
), res
);
15715 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15716 update_call_from_tree (gsi
, res
);
15719 /* Vector loads. */
15720 case ALTIVEC_BUILTIN_LVX_V16QI
:
15721 case ALTIVEC_BUILTIN_LVX_V8HI
:
15722 case ALTIVEC_BUILTIN_LVX_V4SI
:
15723 case ALTIVEC_BUILTIN_LVX_V4SF
:
15724 case ALTIVEC_BUILTIN_LVX_V2DI
:
15725 case ALTIVEC_BUILTIN_LVX_V2DF
:
15726 case ALTIVEC_BUILTIN_LVX_V1TI
:
15728 arg0
= gimple_call_arg (stmt
, 0); // offset
15729 arg1
= gimple_call_arg (stmt
, 1); // address
15730 lhs
= gimple_call_lhs (stmt
);
15731 location_t loc
= gimple_location (stmt
);
15732 /* Since arg1 may be cast to a different type, just use ptr_type_node
15733 here instead of trying to enforce TBAA on pointer types. */
15734 tree arg1_type
= ptr_type_node
;
15735 tree lhs_type
= TREE_TYPE (lhs
);
15736 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15737 the tree using the value from arg0. The resulting type will match
15738 the type of arg1. */
15739 gimple_seq stmts
= NULL
;
15740 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg0
);
15741 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15742 arg1_type
, arg1
, temp_offset
);
15743 /* Mask off any lower bits from the address. */
15744 tree aligned_addr
= gimple_build (&stmts
, loc
, BIT_AND_EXPR
,
15745 arg1_type
, temp_addr
,
15746 build_int_cst (arg1_type
, -16));
15747 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15748 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15749 take an offset, but since we've already incorporated the offset
15750 above, here we just pass in a zero. */
15752 = gimple_build_assign (lhs
, build2 (MEM_REF
, lhs_type
, aligned_addr
,
15753 build_int_cst (arg1_type
, 0)));
15754 gimple_set_location (g
, loc
);
15755 gsi_replace (gsi
, g
, true);
15758 /* Vector stores. */
15759 case ALTIVEC_BUILTIN_STVX_V16QI
:
15760 case ALTIVEC_BUILTIN_STVX_V8HI
:
15761 case ALTIVEC_BUILTIN_STVX_V4SI
:
15762 case ALTIVEC_BUILTIN_STVX_V4SF
:
15763 case ALTIVEC_BUILTIN_STVX_V2DI
:
15764 case ALTIVEC_BUILTIN_STVX_V2DF
:
15766 arg0
= gimple_call_arg (stmt
, 0); /* Value to be stored. */
15767 arg1
= gimple_call_arg (stmt
, 1); /* Offset. */
15768 tree arg2
= gimple_call_arg (stmt
, 2); /* Store-to address. */
15769 location_t loc
= gimple_location (stmt
);
15770 tree arg0_type
= TREE_TYPE (arg0
);
15771 /* Use ptr_type_node (no TBAA) for the arg2_type.
15772 FIXME: (Richard) "A proper fix would be to transition this type as
15773 seen from the frontend to GIMPLE, for example in a similar way we
15774 do for MEM_REFs by piggy-backing that on an extra argument, a
15775 constant zero pointer of the alias pointer type to use (which would
15776 also serve as a type indicator of the store itself). I'd use a
15777 target specific internal function for this (not sure if we can have
15778 those target specific, but I guess if it's folded away then that's
15779 fine) and get away with the overload set." */
15780 tree arg2_type
= ptr_type_node
;
15781 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15782 the tree using the value from arg0. The resulting type will match
15783 the type of arg2. */
15784 gimple_seq stmts
= NULL
;
15785 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg1
);
15786 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15787 arg2_type
, arg2
, temp_offset
);
15788 /* Mask off any lower bits from the address. */
15789 tree aligned_addr
= gimple_build (&stmts
, loc
, BIT_AND_EXPR
,
15790 arg2_type
, temp_addr
,
15791 build_int_cst (arg2_type
, -16));
15792 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15793 /* The desired gimple result should be similar to:
15794 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15796 = gimple_build_assign (build2 (MEM_REF
, arg0_type
, aligned_addr
,
15797 build_int_cst (arg2_type
, 0)), arg0
);
15798 gimple_set_location (g
, loc
);
15799 gsi_replace (gsi
, g
, true);
15803 /* unaligned Vector loads. */
15804 case VSX_BUILTIN_LXVW4X_V16QI
:
15805 case VSX_BUILTIN_LXVW4X_V8HI
:
15806 case VSX_BUILTIN_LXVW4X_V4SF
:
15807 case VSX_BUILTIN_LXVW4X_V4SI
:
15808 case VSX_BUILTIN_LXVD2X_V2DF
:
15809 case VSX_BUILTIN_LXVD2X_V2DI
:
15811 arg0
= gimple_call_arg (stmt
, 0); // offset
15812 arg1
= gimple_call_arg (stmt
, 1); // address
15813 lhs
= gimple_call_lhs (stmt
);
15814 location_t loc
= gimple_location (stmt
);
15815 /* Since arg1 may be cast to a different type, just use ptr_type_node
15816 here instead of trying to enforce TBAA on pointer types. */
15817 tree arg1_type
= ptr_type_node
;
15818 tree lhs_type
= TREE_TYPE (lhs
);
15819 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15820 required alignment (power) is 4 bytes regardless of data type. */
15821 tree align_ltype
= build_aligned_type (lhs_type
, 4);
15822 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15823 the tree using the value from arg0. The resulting type will match
15824 the type of arg1. */
15825 gimple_seq stmts
= NULL
;
15826 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg0
);
15827 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15828 arg1_type
, arg1
, temp_offset
);
15829 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15830 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15831 take an offset, but since we've already incorporated the offset
15832 above, here we just pass in a zero. */
15834 g
= gimple_build_assign (lhs
, build2 (MEM_REF
, align_ltype
, temp_addr
,
15835 build_int_cst (arg1_type
, 0)));
15836 gimple_set_location (g
, loc
);
15837 gsi_replace (gsi
, g
, true);
15841 /* unaligned Vector stores. */
15842 case VSX_BUILTIN_STXVW4X_V16QI
:
15843 case VSX_BUILTIN_STXVW4X_V8HI
:
15844 case VSX_BUILTIN_STXVW4X_V4SF
:
15845 case VSX_BUILTIN_STXVW4X_V4SI
:
15846 case VSX_BUILTIN_STXVD2X_V2DF
:
15847 case VSX_BUILTIN_STXVD2X_V2DI
:
15849 arg0
= gimple_call_arg (stmt
, 0); /* Value to be stored. */
15850 arg1
= gimple_call_arg (stmt
, 1); /* Offset. */
15851 tree arg2
= gimple_call_arg (stmt
, 2); /* Store-to address. */
15852 location_t loc
= gimple_location (stmt
);
15853 tree arg0_type
= TREE_TYPE (arg0
);
15854 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15855 tree arg2_type
= ptr_type_node
;
15856 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15857 required alignment (power) is 4 bytes regardless of data type. */
15858 tree align_stype
= build_aligned_type (arg0_type
, 4);
15859 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15860 the tree using the value from arg1. */
15861 gimple_seq stmts
= NULL
;
15862 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg1
);
15863 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15864 arg2_type
, arg2
, temp_offset
);
15865 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15867 g
= gimple_build_assign (build2 (MEM_REF
, align_stype
, temp_addr
,
15868 build_int_cst (arg2_type
, 0)), arg0
);
15869 gimple_set_location (g
, loc
);
15870 gsi_replace (gsi
, g
, true);
15874 /* Vector Fused multiply-add (fma). */
15875 case ALTIVEC_BUILTIN_VMADDFP
:
15876 case VSX_BUILTIN_XVMADDDP
:
15877 case ALTIVEC_BUILTIN_VMLADDUHM
:
15879 arg0
= gimple_call_arg (stmt
, 0);
15880 arg1
= gimple_call_arg (stmt
, 1);
15881 tree arg2
= gimple_call_arg (stmt
, 2);
15882 lhs
= gimple_call_lhs (stmt
);
15883 gcall
*g
= gimple_build_call_internal (IFN_FMA
, 3, arg0
, arg1
, arg2
);
15884 gimple_call_set_lhs (g
, lhs
);
15885 gimple_call_set_nothrow (g
, true);
15886 gimple_set_location (g
, gimple_location (stmt
));
15887 gsi_replace (gsi
, g
, true);
15891 /* Vector compares; EQ, NE, GE, GT, LE. */
15892 case ALTIVEC_BUILTIN_VCMPEQUB
:
15893 case ALTIVEC_BUILTIN_VCMPEQUH
:
15894 case ALTIVEC_BUILTIN_VCMPEQUW
:
15895 case P8V_BUILTIN_VCMPEQUD
:
15896 fold_compare_helper (gsi
, EQ_EXPR
, stmt
);
15899 case P9V_BUILTIN_CMPNEB
:
15900 case P9V_BUILTIN_CMPNEH
:
15901 case P9V_BUILTIN_CMPNEW
:
15902 fold_compare_helper (gsi
, NE_EXPR
, stmt
);
15905 case VSX_BUILTIN_CMPGE_16QI
:
15906 case VSX_BUILTIN_CMPGE_U16QI
:
15907 case VSX_BUILTIN_CMPGE_8HI
:
15908 case VSX_BUILTIN_CMPGE_U8HI
:
15909 case VSX_BUILTIN_CMPGE_4SI
:
15910 case VSX_BUILTIN_CMPGE_U4SI
:
15911 case VSX_BUILTIN_CMPGE_2DI
:
15912 case VSX_BUILTIN_CMPGE_U2DI
:
15913 fold_compare_helper (gsi
, GE_EXPR
, stmt
);
15916 case ALTIVEC_BUILTIN_VCMPGTSB
:
15917 case ALTIVEC_BUILTIN_VCMPGTUB
:
15918 case ALTIVEC_BUILTIN_VCMPGTSH
:
15919 case ALTIVEC_BUILTIN_VCMPGTUH
:
15920 case ALTIVEC_BUILTIN_VCMPGTSW
:
15921 case ALTIVEC_BUILTIN_VCMPGTUW
:
15922 case P8V_BUILTIN_VCMPGTUD
:
15923 case P8V_BUILTIN_VCMPGTSD
:
15924 fold_compare_helper (gsi
, GT_EXPR
, stmt
);
15927 case VSX_BUILTIN_CMPLE_16QI
:
15928 case VSX_BUILTIN_CMPLE_U16QI
:
15929 case VSX_BUILTIN_CMPLE_8HI
:
15930 case VSX_BUILTIN_CMPLE_U8HI
:
15931 case VSX_BUILTIN_CMPLE_4SI
:
15932 case VSX_BUILTIN_CMPLE_U4SI
:
15933 case VSX_BUILTIN_CMPLE_2DI
:
15934 case VSX_BUILTIN_CMPLE_U2DI
:
15935 fold_compare_helper (gsi
, LE_EXPR
, stmt
);
15938 /* flavors of vec_splat_[us]{8,16,32}. */
15939 case ALTIVEC_BUILTIN_VSPLTISB
:
15940 case ALTIVEC_BUILTIN_VSPLTISH
:
15941 case ALTIVEC_BUILTIN_VSPLTISW
:
15944 if (fn_code
== ALTIVEC_BUILTIN_VSPLTISB
)
15946 else if (fn_code
== ALTIVEC_BUILTIN_VSPLTISH
)
15951 arg0
= gimple_call_arg (stmt
, 0);
15952 lhs
= gimple_call_lhs (stmt
);
15954 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15955 5-bit signed constant in range -16 to +15. */
15956 if (TREE_CODE (arg0
) != INTEGER_CST
15957 || !IN_RANGE (sext_hwi (TREE_INT_CST_LOW (arg0
), size
),
15960 gimple_seq stmts
= NULL
;
15961 location_t loc
= gimple_location (stmt
);
15962 tree splat_value
= gimple_convert (&stmts
, loc
,
15963 TREE_TYPE (TREE_TYPE (lhs
)), arg0
);
15964 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15965 tree splat_tree
= build_vector_from_val (TREE_TYPE (lhs
), splat_value
);
15966 g
= gimple_build_assign (lhs
, splat_tree
);
15967 gimple_set_location (g
, gimple_location (stmt
));
15968 gsi_replace (gsi
, g
, true);
15972 /* Flavors of vec_splat. */
15973 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
15974 case ALTIVEC_BUILTIN_VSPLTB
:
15975 case ALTIVEC_BUILTIN_VSPLTH
:
15976 case ALTIVEC_BUILTIN_VSPLTW
:
15977 case VSX_BUILTIN_XXSPLTD_V2DI
:
15978 case VSX_BUILTIN_XXSPLTD_V2DF
:
15980 arg0
= gimple_call_arg (stmt
, 0); /* input vector. */
15981 arg1
= gimple_call_arg (stmt
, 1); /* index into arg0. */
15982 /* Only fold the vec_splat_*() if arg1 is both a constant value and
15983 is a valid index into the arg0 vector. */
15984 unsigned int n_elts
= VECTOR_CST_NELTS (arg0
);
15985 if (TREE_CODE (arg1
) != INTEGER_CST
15986 || TREE_INT_CST_LOW (arg1
) > (n_elts
-1))
15988 lhs
= gimple_call_lhs (stmt
);
15989 tree lhs_type
= TREE_TYPE (lhs
);
15990 tree arg0_type
= TREE_TYPE (arg0
);
15992 if (TREE_CODE (arg0
) == VECTOR_CST
)
15993 splat
= VECTOR_CST_ELT (arg0
, TREE_INT_CST_LOW (arg1
));
15996 /* Determine (in bits) the length and start location of the
15997 splat value for a call to the tree_vec_extract helper. */
15998 int splat_elem_size
= TREE_INT_CST_LOW (size_in_bytes (arg0_type
))
15999 * BITS_PER_UNIT
/ n_elts
;
16000 int splat_start_bit
= TREE_INT_CST_LOW (arg1
) * splat_elem_size
;
16001 tree len
= build_int_cst (bitsizetype
, splat_elem_size
);
16002 tree start
= build_int_cst (bitsizetype
, splat_start_bit
);
16003 splat
= tree_vec_extract (gsi
, TREE_TYPE (lhs_type
), arg0
,
16006 /* And finally, build the new vector. */
16007 tree splat_tree
= build_vector_from_val (lhs_type
, splat
);
16008 g
= gimple_build_assign (lhs
, splat_tree
);
16009 gimple_set_location (g
, gimple_location (stmt
));
16010 gsi_replace (gsi
, g
, true);
16014 /* vec_mergel (integrals). */
16015 case ALTIVEC_BUILTIN_VMRGLH
:
16016 case ALTIVEC_BUILTIN_VMRGLW
:
16017 case VSX_BUILTIN_XXMRGLW_4SI
:
16018 case ALTIVEC_BUILTIN_VMRGLB
:
16019 case VSX_BUILTIN_VEC_MERGEL_V2DI
:
16020 case VSX_BUILTIN_XXMRGLW_4SF
:
16021 case VSX_BUILTIN_VEC_MERGEL_V2DF
:
16022 fold_mergehl_helper (gsi
, stmt
, 1);
16024 /* vec_mergeh (integrals). */
16025 case ALTIVEC_BUILTIN_VMRGHH
:
16026 case ALTIVEC_BUILTIN_VMRGHW
:
16027 case VSX_BUILTIN_XXMRGHW_4SI
:
16028 case ALTIVEC_BUILTIN_VMRGHB
:
16029 case VSX_BUILTIN_VEC_MERGEH_V2DI
:
16030 case VSX_BUILTIN_XXMRGHW_4SF
:
16031 case VSX_BUILTIN_VEC_MERGEH_V2DF
:
16032 fold_mergehl_helper (gsi
, stmt
, 0);
16035 /* Flavors of vec_mergee. */
16036 case P8V_BUILTIN_VMRGEW_V4SI
:
16037 case P8V_BUILTIN_VMRGEW_V2DI
:
16038 case P8V_BUILTIN_VMRGEW_V4SF
:
16039 case P8V_BUILTIN_VMRGEW_V2DF
:
16040 fold_mergeeo_helper (gsi
, stmt
, 0);
16042 /* Flavors of vec_mergeo. */
16043 case P8V_BUILTIN_VMRGOW_V4SI
:
16044 case P8V_BUILTIN_VMRGOW_V2DI
:
16045 case P8V_BUILTIN_VMRGOW_V4SF
:
16046 case P8V_BUILTIN_VMRGOW_V2DF
:
16047 fold_mergeeo_helper (gsi
, stmt
, 1);
16050 /* d = vec_pack (a, b) */
16051 case P8V_BUILTIN_VPKUDUM
:
16052 case ALTIVEC_BUILTIN_VPKUHUM
:
16053 case ALTIVEC_BUILTIN_VPKUWUM
:
16055 arg0
= gimple_call_arg (stmt
, 0);
16056 arg1
= gimple_call_arg (stmt
, 1);
16057 lhs
= gimple_call_lhs (stmt
);
16058 gimple
*g
= gimple_build_assign (lhs
, VEC_PACK_TRUNC_EXPR
, arg0
, arg1
);
16059 gimple_set_location (g
, gimple_location (stmt
));
16060 gsi_replace (gsi
, g
, true);
16064 /* d = vec_unpackh (a) */
16065 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
16066 in this code is sensitive to endian-ness, and needs to be inverted to
16067 handle both LE and BE targets. */
16068 case ALTIVEC_BUILTIN_VUPKHSB
:
16069 case ALTIVEC_BUILTIN_VUPKHSH
:
16070 case P8V_BUILTIN_VUPKHSW
:
16072 arg0
= gimple_call_arg (stmt
, 0);
16073 lhs
= gimple_call_lhs (stmt
);
16074 if (BYTES_BIG_ENDIAN
)
16075 g
= gimple_build_assign (lhs
, VEC_UNPACK_HI_EXPR
, arg0
);
16077 g
= gimple_build_assign (lhs
, VEC_UNPACK_LO_EXPR
, arg0
);
16078 gimple_set_location (g
, gimple_location (stmt
));
16079 gsi_replace (gsi
, g
, true);
16082 /* d = vec_unpackl (a) */
16083 case ALTIVEC_BUILTIN_VUPKLSB
:
16084 case ALTIVEC_BUILTIN_VUPKLSH
:
16085 case P8V_BUILTIN_VUPKLSW
:
16087 arg0
= gimple_call_arg (stmt
, 0);
16088 lhs
= gimple_call_lhs (stmt
);
16089 if (BYTES_BIG_ENDIAN
)
16090 g
= gimple_build_assign (lhs
, VEC_UNPACK_LO_EXPR
, arg0
);
16092 g
= gimple_build_assign (lhs
, VEC_UNPACK_HI_EXPR
, arg0
);
16093 gimple_set_location (g
, gimple_location (stmt
));
16094 gsi_replace (gsi
, g
, true);
16097 /* There is no gimple type corresponding with pixel, so just return. */
16098 case ALTIVEC_BUILTIN_VUPKHPX
:
16099 case ALTIVEC_BUILTIN_VUPKLPX
:
16103 case ALTIVEC_BUILTIN_VPERM_16QI
:
16104 case ALTIVEC_BUILTIN_VPERM_8HI
:
16105 case ALTIVEC_BUILTIN_VPERM_4SI
:
16106 case ALTIVEC_BUILTIN_VPERM_2DI
:
16107 case ALTIVEC_BUILTIN_VPERM_4SF
:
16108 case ALTIVEC_BUILTIN_VPERM_2DF
:
16110 arg0
= gimple_call_arg (stmt
, 0);
16111 arg1
= gimple_call_arg (stmt
, 1);
16112 tree permute
= gimple_call_arg (stmt
, 2);
16113 lhs
= gimple_call_lhs (stmt
);
16114 location_t loc
= gimple_location (stmt
);
16115 gimple_seq stmts
= NULL
;
16116 // convert arg0 and arg1 to match the type of the permute
16117 // for the VEC_PERM_EXPR operation.
16118 tree permute_type
= (TREE_TYPE (permute
));
16119 tree arg0_ptype
= gimple_convert (&stmts
, loc
, permute_type
, arg0
);
16120 tree arg1_ptype
= gimple_convert (&stmts
, loc
, permute_type
, arg1
);
16121 tree lhs_ptype
= gimple_build (&stmts
, loc
, VEC_PERM_EXPR
,
16122 permute_type
, arg0_ptype
, arg1_ptype
,
16124 // Convert the result back to the desired lhs type upon completion.
16125 tree temp
= gimple_convert (&stmts
, loc
, TREE_TYPE (lhs
), lhs_ptype
);
16126 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
16127 g
= gimple_build_assign (lhs
, temp
);
16128 gimple_set_location (g
, loc
);
16129 gsi_replace (gsi
, g
, true);
16134 if (TARGET_DEBUG_BUILTIN
)
16135 fprintf (stderr
, "gimple builtin intrinsic not matched:%d %s %s\n",
16136 fn_code
, fn_name1
, fn_name2
);
16143 /* Expand an expression EXP that calls a built-in function,
16144 with result going to TARGET if that's convenient
16145 (and in mode MODE if that's convenient).
16146 SUBTARGET may be used as the target for computing one of EXP's operands.
16147 IGNORE is nonzero if the value is to be ignored. */
16150 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
16151 machine_mode mode ATTRIBUTE_UNUSED
,
16152 int ignore ATTRIBUTE_UNUSED
)
16154 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
16155 enum rs6000_builtins fcode
16156 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
16157 size_t uns_fcode
= (size_t)fcode
;
16158 const struct builtin_description
*d
;
16162 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
16163 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
16164 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
16166 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16167 floating point type, depending on whether long double is the IBM extended
16168 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16169 we only define one variant of the built-in function, and switch the code
16170 when defining it, rather than defining two built-ins and using the
16171 overload table in rs6000-c.c to switch between the two. If we don't have
16172 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16173 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16174 if (FLOAT128_IEEE_P (TFmode
))
16180 case CODE_FOR_sqrtkf2_odd
: icode
= CODE_FOR_sqrttf2_odd
; break;
16181 case CODE_FOR_trunckfdf2_odd
: icode
= CODE_FOR_trunctfdf2_odd
; break;
16182 case CODE_FOR_addkf3_odd
: icode
= CODE_FOR_addtf3_odd
; break;
16183 case CODE_FOR_subkf3_odd
: icode
= CODE_FOR_subtf3_odd
; break;
16184 case CODE_FOR_mulkf3_odd
: icode
= CODE_FOR_multf3_odd
; break;
16185 case CODE_FOR_divkf3_odd
: icode
= CODE_FOR_divtf3_odd
; break;
16186 case CODE_FOR_fmakf4_odd
: icode
= CODE_FOR_fmatf4_odd
; break;
16187 case CODE_FOR_xsxexpqp_kf
: icode
= CODE_FOR_xsxexpqp_tf
; break;
16188 case CODE_FOR_xsxsigqp_kf
: icode
= CODE_FOR_xsxsigqp_tf
; break;
16189 case CODE_FOR_xststdcnegqp_kf
: icode
= CODE_FOR_xststdcnegqp_tf
; break;
16190 case CODE_FOR_xsiexpqp_kf
: icode
= CODE_FOR_xsiexpqp_tf
; break;
16191 case CODE_FOR_xsiexpqpf_kf
: icode
= CODE_FOR_xsiexpqpf_tf
; break;
16192 case CODE_FOR_xststdcqp_kf
: icode
= CODE_FOR_xststdcqp_tf
; break;
16195 if (TARGET_DEBUG_BUILTIN
)
16197 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
16198 const char *name2
= (icode
!= CODE_FOR_nothing
)
16199 ? get_insn_name ((int) icode
)
16203 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
16205 default: name3
= "unknown"; break;
16206 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
16207 case RS6000_BTC_UNARY
: name3
= "unary"; break;
16208 case RS6000_BTC_BINARY
: name3
= "binary"; break;
16209 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
16210 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
16211 case RS6000_BTC_ABS
: name3
= "abs"; break;
16212 case RS6000_BTC_DST
: name3
= "dst"; break;
16217 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16218 (name1
) ? name1
: "---", fcode
,
16219 (name2
) ? name2
: "---", (int) icode
,
16221 func_valid_p
? "" : ", not valid");
16226 rs6000_invalid_builtin (fcode
);
16228 /* Given it is invalid, just generate a normal call. */
16229 return expand_call (exp
, target
, ignore
);
16234 case RS6000_BUILTIN_RECIP
:
16235 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
16237 case RS6000_BUILTIN_RECIPF
:
16238 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
16240 case RS6000_BUILTIN_RSQRTF
:
16241 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
16243 case RS6000_BUILTIN_RSQRT
:
16244 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
16246 case POWER7_BUILTIN_BPERMD
:
16247 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
16248 ? CODE_FOR_bpermd_di
16249 : CODE_FOR_bpermd_si
), exp
, target
);
16251 case RS6000_BUILTIN_GET_TB
:
16252 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
16255 case RS6000_BUILTIN_MFTB
:
16256 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
16257 ? CODE_FOR_rs6000_mftb_di
16258 : CODE_FOR_rs6000_mftb_si
),
16261 case RS6000_BUILTIN_MFFS
:
16262 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
16264 case RS6000_BUILTIN_MTFSB0
:
16265 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0
, exp
);
16267 case RS6000_BUILTIN_MTFSB1
:
16268 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1
, exp
);
16270 case RS6000_BUILTIN_SET_FPSCR_RN
:
16271 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn
,
16274 case RS6000_BUILTIN_SET_FPSCR_DRN
:
16276 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn
,
16279 case RS6000_BUILTIN_MFFSL
:
16280 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl
, target
);
16282 case RS6000_BUILTIN_MTFSF
:
16283 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
16285 case RS6000_BUILTIN_CPU_INIT
:
16286 case RS6000_BUILTIN_CPU_IS
:
16287 case RS6000_BUILTIN_CPU_SUPPORTS
:
16288 return cpu_expand_builtin (fcode
, exp
, target
);
16290 case MISC_BUILTIN_SPEC_BARRIER
:
16292 emit_insn (gen_speculation_barrier ());
16296 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
16297 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
16299 int icode2
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
16300 : (int) CODE_FOR_altivec_lvsl_direct
);
16301 machine_mode tmode
= insn_data
[icode2
].operand
[0].mode
;
16302 machine_mode mode
= insn_data
[icode2
].operand
[1].mode
;
16306 gcc_assert (TARGET_ALTIVEC
);
16308 arg
= CALL_EXPR_ARG (exp
, 0);
16309 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
16310 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
16311 addr
= memory_address (mode
, op
);
16312 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
16316 /* For the load case need to negate the address. */
16317 op
= gen_reg_rtx (GET_MODE (addr
));
16318 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
16320 op
= gen_rtx_MEM (mode
, op
);
16323 || GET_MODE (target
) != tmode
16324 || ! (*insn_data
[icode2
].operand
[0].predicate
) (target
, tmode
))
16325 target
= gen_reg_rtx (tmode
);
16327 pat
= GEN_FCN (icode2
) (target
, op
);
16335 case ALTIVEC_BUILTIN_VCFUX
:
16336 case ALTIVEC_BUILTIN_VCFSX
:
16337 case ALTIVEC_BUILTIN_VCTUXS
:
16338 case ALTIVEC_BUILTIN_VCTSXS
:
16339 /* FIXME: There's got to be a nicer way to handle this case than
16340 constructing a new CALL_EXPR. */
16341 if (call_expr_nargs (exp
) == 1)
16343 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
16344 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
16348 /* For the pack and unpack int128 routines, fix up the builtin so it
16349 uses the correct IBM128 type. */
16350 case MISC_BUILTIN_PACK_IF
:
16351 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
16353 icode
= CODE_FOR_packtf
;
16354 fcode
= MISC_BUILTIN_PACK_TF
;
16355 uns_fcode
= (size_t)fcode
;
16359 case MISC_BUILTIN_UNPACK_IF
:
16360 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
16362 icode
= CODE_FOR_unpacktf
;
16363 fcode
= MISC_BUILTIN_UNPACK_TF
;
16364 uns_fcode
= (size_t)fcode
;
16372 if (TARGET_ALTIVEC
)
16374 ret
= altivec_expand_builtin (exp
, target
, &success
);
16381 ret
= htm_expand_builtin (exp
, target
, &success
);
16387 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
16388 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16389 gcc_assert (attr
== RS6000_BTC_UNARY
16390 || attr
== RS6000_BTC_BINARY
16391 || attr
== RS6000_BTC_TERNARY
16392 || attr
== RS6000_BTC_SPECIAL
);
16394 /* Handle simple unary operations. */
16396 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
16397 if (d
->code
== fcode
)
16398 return rs6000_expand_unop_builtin (icode
, exp
, target
);
16400 /* Handle simple binary operations. */
16402 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
16403 if (d
->code
== fcode
)
16404 return rs6000_expand_binop_builtin (icode
, exp
, target
);
16406 /* Handle simple ternary operations. */
16408 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
16409 if (d
->code
== fcode
)
16410 return rs6000_expand_ternop_builtin (icode
, exp
, target
);
16412 /* Handle simple no-argument operations. */
16414 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
16415 if (d
->code
== fcode
)
16416 return rs6000_expand_zeroop_builtin (icode
, target
);
16418 gcc_unreachable ();
16421 /* Create a builtin vector type with a name. Taking care not to give
16422 the canonical type a name. */
16425 rs6000_vector_type (const char *name
, tree elt_type
, unsigned num_elts
)
16427 tree result
= build_vector_type (elt_type
, num_elts
);
16429 /* Copy so we don't give the canonical type a name. */
16430 result
= build_variant_type_copy (result
);
16432 add_builtin_type (name
, result
);
16438 rs6000_init_builtins (void)
16444 if (TARGET_DEBUG_BUILTIN
)
16445 fprintf (stderr
, "rs6000_init_builtins%s%s\n",
16446 (TARGET_ALTIVEC
) ? ", altivec" : "",
16447 (TARGET_VSX
) ? ", vsx" : "");
16449 V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
? "__vector long"
16450 : "__vector long long",
16451 intDI_type_node
, 2);
16452 V2DF_type_node
= rs6000_vector_type ("__vector double", double_type_node
, 2);
16453 V4SI_type_node
= rs6000_vector_type ("__vector signed int",
16454 intSI_type_node
, 4);
16455 V4SF_type_node
= rs6000_vector_type ("__vector float", float_type_node
, 4);
16456 V8HI_type_node
= rs6000_vector_type ("__vector signed short",
16457 intHI_type_node
, 8);
16458 V16QI_type_node
= rs6000_vector_type ("__vector signed char",
16459 intQI_type_node
, 16);
16461 unsigned_V16QI_type_node
= rs6000_vector_type ("__vector unsigned char",
16462 unsigned_intQI_type_node
, 16);
16463 unsigned_V8HI_type_node
= rs6000_vector_type ("__vector unsigned short",
16464 unsigned_intHI_type_node
, 8);
16465 unsigned_V4SI_type_node
= rs6000_vector_type ("__vector unsigned int",
16466 unsigned_intSI_type_node
, 4);
16467 unsigned_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16468 ? "__vector unsigned long"
16469 : "__vector unsigned long long",
16470 unsigned_intDI_type_node
, 2);
16472 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
16474 const_str_type_node
16475 = build_pointer_type (build_qualified_type (char_type_node
,
16478 /* We use V1TI mode as a special container to hold __int128_t items that
16479 must live in VSX registers. */
16480 if (intTI_type_node
)
16482 V1TI_type_node
= rs6000_vector_type ("__vector __int128",
16483 intTI_type_node
, 1);
16484 unsigned_V1TI_type_node
16485 = rs6000_vector_type ("__vector unsigned __int128",
16486 unsigned_intTI_type_node
, 1);
16489 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16490 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16491 'vector unsigned short'. */
16493 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
16494 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16495 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
16496 bool_long_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
16497 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16499 long_integer_type_internal_node
= long_integer_type_node
;
16500 long_unsigned_type_internal_node
= long_unsigned_type_node
;
16501 long_long_integer_type_internal_node
= long_long_integer_type_node
;
16502 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
16503 intQI_type_internal_node
= intQI_type_node
;
16504 uintQI_type_internal_node
= unsigned_intQI_type_node
;
16505 intHI_type_internal_node
= intHI_type_node
;
16506 uintHI_type_internal_node
= unsigned_intHI_type_node
;
16507 intSI_type_internal_node
= intSI_type_node
;
16508 uintSI_type_internal_node
= unsigned_intSI_type_node
;
16509 intDI_type_internal_node
= intDI_type_node
;
16510 uintDI_type_internal_node
= unsigned_intDI_type_node
;
16511 intTI_type_internal_node
= intTI_type_node
;
16512 uintTI_type_internal_node
= unsigned_intTI_type_node
;
16513 float_type_internal_node
= float_type_node
;
16514 double_type_internal_node
= double_type_node
;
16515 long_double_type_internal_node
= long_double_type_node
;
16516 dfloat64_type_internal_node
= dfloat64_type_node
;
16517 dfloat128_type_internal_node
= dfloat128_type_node
;
16518 void_type_internal_node
= void_type_node
;
16520 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16521 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16522 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16523 format that uses a pair of doubles, depending on the switches and
16526 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16527 floating point, we need make sure the type is non-zero or else self-test
16528 fails during bootstrap.
16530 Always create __ibm128 as a separate type, even if the current long double
16531 format is IBM extended double.
16533 For IEEE 128-bit floating point, always create the type __ieee128. If the
16534 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16536 if (TARGET_FLOAT128_TYPE
)
16538 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
)
16539 ibm128_float_type_node
= long_double_type_node
;
16542 ibm128_float_type_node
= make_node (REAL_TYPE
);
16543 TYPE_PRECISION (ibm128_float_type_node
) = 128;
16544 SET_TYPE_MODE (ibm128_float_type_node
, IFmode
);
16545 layout_type (ibm128_float_type_node
);
16548 lang_hooks
.types
.register_builtin_type (ibm128_float_type_node
,
16551 if (TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
)
16552 ieee128_float_type_node
= long_double_type_node
;
16554 ieee128_float_type_node
= float128_type_node
;
16556 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
16561 ieee128_float_type_node
= ibm128_float_type_node
= long_double_type_node
;
16563 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16565 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
16566 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
16567 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
16568 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
16569 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
16570 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
16571 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
16572 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
16573 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
16574 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
16575 builtin_mode_to_type
[IFmode
][0] = ibm128_float_type_node
;
16576 builtin_mode_to_type
[KFmode
][0] = ieee128_float_type_node
;
16577 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
16578 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
16579 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
16580 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
16581 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
16582 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
16583 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
16584 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
16585 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
16586 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
16587 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
16588 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
16589 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
16590 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
16591 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
16593 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
16594 TYPE_NAME (bool_char_type_node
) = tdecl
;
16596 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
16597 TYPE_NAME (bool_short_type_node
) = tdecl
;
16599 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
16600 TYPE_NAME (bool_int_type_node
) = tdecl
;
16602 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
16603 TYPE_NAME (pixel_type_node
) = tdecl
;
16605 bool_V16QI_type_node
= rs6000_vector_type ("__vector __bool char",
16606 bool_char_type_node
, 16);
16607 bool_V8HI_type_node
= rs6000_vector_type ("__vector __bool short",
16608 bool_short_type_node
, 8);
16609 bool_V4SI_type_node
= rs6000_vector_type ("__vector __bool int",
16610 bool_int_type_node
, 4);
16611 bool_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16612 ? "__vector __bool long"
16613 : "__vector __bool long long",
16614 bool_long_long_type_node
, 2);
16615 pixel_V8HI_type_node
= rs6000_vector_type ("__vector __pixel",
16616 pixel_type_node
, 8);
16618 /* Create Altivec and VSX builtins on machines with at least the
16619 general purpose extensions (970 and newer) to allow the use of
16620 the target attribute. */
16621 if (TARGET_EXTRA_BUILTINS
)
16622 altivec_init_builtins ();
16624 htm_init_builtins ();
16626 if (TARGET_EXTRA_BUILTINS
)
16627 rs6000_common_init_builtins ();
16629 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
16630 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
16631 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
16633 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
16634 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
16635 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
16637 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
16638 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
16639 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
16641 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
16642 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
16643 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
16645 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
16646 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
16647 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
16648 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
16650 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16652 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
16655 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16658 ftype
= build_function_type_list (unsigned_intSI_type_node
,
16660 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
16662 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
16663 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
16665 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
16666 def_builtin ("__builtin_mffsl", ftype
, RS6000_BUILTIN_MFFSL
);
16668 ftype
= build_function_type_list (void_type_node
,
16671 def_builtin ("__builtin_mtfsb0", ftype
, RS6000_BUILTIN_MTFSB0
);
16673 ftype
= build_function_type_list (void_type_node
,
16676 def_builtin ("__builtin_mtfsb1", ftype
, RS6000_BUILTIN_MTFSB1
);
16678 ftype
= build_function_type_list (void_type_node
,
16681 def_builtin ("__builtin_set_fpscr_rn", ftype
, RS6000_BUILTIN_SET_FPSCR_RN
);
16683 ftype
= build_function_type_list (void_type_node
,
16686 def_builtin ("__builtin_set_fpscr_drn", ftype
, RS6000_BUILTIN_SET_FPSCR_DRN
);
16688 ftype
= build_function_type_list (void_type_node
,
16689 intSI_type_node
, double_type_node
,
16691 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
16693 ftype
= build_function_type_list (void_type_node
, NULL_TREE
);
16694 def_builtin ("__builtin_cpu_init", ftype
, RS6000_BUILTIN_CPU_INIT
);
16695 def_builtin ("__builtin_ppc_speculation_barrier", ftype
,
16696 MISC_BUILTIN_SPEC_BARRIER
);
16698 ftype
= build_function_type_list (bool_int_type_node
, const_ptr_type_node
,
16700 def_builtin ("__builtin_cpu_is", ftype
, RS6000_BUILTIN_CPU_IS
);
16701 def_builtin ("__builtin_cpu_supports", ftype
, RS6000_BUILTIN_CPU_SUPPORTS
);
16703 /* AIX libm provides clog as __clog. */
16704 if (TARGET_XCOFF
&&
16705 (tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
16706 set_user_assembler_name (tdecl
, "__clog");
16708 #ifdef SUBTARGET_INIT_BUILTINS
16709 SUBTARGET_INIT_BUILTINS
;
16713 /* Returns the rs6000 builtin decl for CODE. */
16716 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
16718 HOST_WIDE_INT fnmask
;
16720 if (code
>= RS6000_BUILTIN_COUNT
)
16721 return error_mark_node
;
16723 fnmask
= rs6000_builtin_info
[code
].mask
;
16724 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
16726 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
16727 return error_mark_node
;
16730 return rs6000_builtin_decls
[code
];
16734 altivec_init_builtins (void)
16736 const struct builtin_description
*d
;
16740 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
16742 tree pvoid_type_node
= build_pointer_type (void_type_node
);
16744 tree pcvoid_type_node
16745 = build_pointer_type (build_qualified_type (void_type_node
,
16748 tree int_ftype_opaque
16749 = build_function_type_list (integer_type_node
,
16750 opaque_V4SI_type_node
, NULL_TREE
);
16751 tree opaque_ftype_opaque
16752 = build_function_type_list (integer_type_node
, NULL_TREE
);
16753 tree opaque_ftype_opaque_int
16754 = build_function_type_list (opaque_V4SI_type_node
,
16755 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
16756 tree opaque_ftype_opaque_opaque_int
16757 = build_function_type_list (opaque_V4SI_type_node
,
16758 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16759 integer_type_node
, NULL_TREE
);
16760 tree opaque_ftype_opaque_opaque_opaque
16761 = build_function_type_list (opaque_V4SI_type_node
,
16762 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16763 opaque_V4SI_type_node
, NULL_TREE
);
16764 tree opaque_ftype_opaque_opaque
16765 = build_function_type_list (opaque_V4SI_type_node
,
16766 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16768 tree int_ftype_int_opaque_opaque
16769 = build_function_type_list (integer_type_node
,
16770 integer_type_node
, opaque_V4SI_type_node
,
16771 opaque_V4SI_type_node
, NULL_TREE
);
16772 tree int_ftype_int_v4si_v4si
16773 = build_function_type_list (integer_type_node
,
16774 integer_type_node
, V4SI_type_node
,
16775 V4SI_type_node
, NULL_TREE
);
16776 tree int_ftype_int_v2di_v2di
16777 = build_function_type_list (integer_type_node
,
16778 integer_type_node
, V2DI_type_node
,
16779 V2DI_type_node
, NULL_TREE
);
16780 tree void_ftype_v4si
16781 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
16782 tree v8hi_ftype_void
16783 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
16784 tree void_ftype_void
16785 = build_function_type_list (void_type_node
, NULL_TREE
);
16786 tree void_ftype_int
16787 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
16789 tree opaque_ftype_long_pcvoid
16790 = build_function_type_list (opaque_V4SI_type_node
,
16791 long_integer_type_node
, pcvoid_type_node
,
16793 tree v16qi_ftype_long_pcvoid
16794 = build_function_type_list (V16QI_type_node
,
16795 long_integer_type_node
, pcvoid_type_node
,
16797 tree v8hi_ftype_long_pcvoid
16798 = build_function_type_list (V8HI_type_node
,
16799 long_integer_type_node
, pcvoid_type_node
,
16801 tree v4si_ftype_long_pcvoid
16802 = build_function_type_list (V4SI_type_node
,
16803 long_integer_type_node
, pcvoid_type_node
,
16805 tree v4sf_ftype_long_pcvoid
16806 = build_function_type_list (V4SF_type_node
,
16807 long_integer_type_node
, pcvoid_type_node
,
16809 tree v2df_ftype_long_pcvoid
16810 = build_function_type_list (V2DF_type_node
,
16811 long_integer_type_node
, pcvoid_type_node
,
16813 tree v2di_ftype_long_pcvoid
16814 = build_function_type_list (V2DI_type_node
,
16815 long_integer_type_node
, pcvoid_type_node
,
16817 tree v1ti_ftype_long_pcvoid
16818 = build_function_type_list (V1TI_type_node
,
16819 long_integer_type_node
, pcvoid_type_node
,
16822 tree void_ftype_opaque_long_pvoid
16823 = build_function_type_list (void_type_node
,
16824 opaque_V4SI_type_node
, long_integer_type_node
,
16825 pvoid_type_node
, NULL_TREE
);
16826 tree void_ftype_v4si_long_pvoid
16827 = build_function_type_list (void_type_node
,
16828 V4SI_type_node
, long_integer_type_node
,
16829 pvoid_type_node
, NULL_TREE
);
16830 tree void_ftype_v16qi_long_pvoid
16831 = build_function_type_list (void_type_node
,
16832 V16QI_type_node
, long_integer_type_node
,
16833 pvoid_type_node
, NULL_TREE
);
16835 tree void_ftype_v16qi_pvoid_long
16836 = build_function_type_list (void_type_node
,
16837 V16QI_type_node
, pvoid_type_node
,
16838 long_integer_type_node
, NULL_TREE
);
16840 tree void_ftype_v8hi_long_pvoid
16841 = build_function_type_list (void_type_node
,
16842 V8HI_type_node
, long_integer_type_node
,
16843 pvoid_type_node
, NULL_TREE
);
16844 tree void_ftype_v4sf_long_pvoid
16845 = build_function_type_list (void_type_node
,
16846 V4SF_type_node
, long_integer_type_node
,
16847 pvoid_type_node
, NULL_TREE
);
16848 tree void_ftype_v2df_long_pvoid
16849 = build_function_type_list (void_type_node
,
16850 V2DF_type_node
, long_integer_type_node
,
16851 pvoid_type_node
, NULL_TREE
);
16852 tree void_ftype_v1ti_long_pvoid
16853 = build_function_type_list (void_type_node
,
16854 V1TI_type_node
, long_integer_type_node
,
16855 pvoid_type_node
, NULL_TREE
);
16856 tree void_ftype_v2di_long_pvoid
16857 = build_function_type_list (void_type_node
,
16858 V2DI_type_node
, long_integer_type_node
,
16859 pvoid_type_node
, NULL_TREE
);
16860 tree int_ftype_int_v8hi_v8hi
16861 = build_function_type_list (integer_type_node
,
16862 integer_type_node
, V8HI_type_node
,
16863 V8HI_type_node
, NULL_TREE
);
16864 tree int_ftype_int_v16qi_v16qi
16865 = build_function_type_list (integer_type_node
,
16866 integer_type_node
, V16QI_type_node
,
16867 V16QI_type_node
, NULL_TREE
);
16868 tree int_ftype_int_v4sf_v4sf
16869 = build_function_type_list (integer_type_node
,
16870 integer_type_node
, V4SF_type_node
,
16871 V4SF_type_node
, NULL_TREE
);
16872 tree int_ftype_int_v2df_v2df
16873 = build_function_type_list (integer_type_node
,
16874 integer_type_node
, V2DF_type_node
,
16875 V2DF_type_node
, NULL_TREE
);
16876 tree v2di_ftype_v2di
16877 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
16878 tree v4si_ftype_v4si
16879 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
16880 tree v8hi_ftype_v8hi
16881 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
16882 tree v16qi_ftype_v16qi
16883 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
16884 tree v4sf_ftype_v4sf
16885 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
16886 tree v2df_ftype_v2df
16887 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
16888 tree void_ftype_pcvoid_int_int
16889 = build_function_type_list (void_type_node
,
16890 pcvoid_type_node
, integer_type_node
,
16891 integer_type_node
, NULL_TREE
);
16893 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
16894 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
16895 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
16896 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
16897 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
16898 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
16899 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
16900 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
16901 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
16902 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
16903 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
16904 ALTIVEC_BUILTIN_LVXL_V2DF
);
16905 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
16906 ALTIVEC_BUILTIN_LVXL_V2DI
);
16907 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
16908 ALTIVEC_BUILTIN_LVXL_V4SF
);
16909 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
16910 ALTIVEC_BUILTIN_LVXL_V4SI
);
16911 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
16912 ALTIVEC_BUILTIN_LVXL_V8HI
);
16913 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
16914 ALTIVEC_BUILTIN_LVXL_V16QI
);
16915 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
16916 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid
,
16917 ALTIVEC_BUILTIN_LVX_V1TI
);
16918 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
16919 ALTIVEC_BUILTIN_LVX_V2DF
);
16920 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
16921 ALTIVEC_BUILTIN_LVX_V2DI
);
16922 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
16923 ALTIVEC_BUILTIN_LVX_V4SF
);
16924 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
16925 ALTIVEC_BUILTIN_LVX_V4SI
);
16926 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
16927 ALTIVEC_BUILTIN_LVX_V8HI
);
16928 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
16929 ALTIVEC_BUILTIN_LVX_V16QI
);
16930 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
16931 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
16932 ALTIVEC_BUILTIN_STVX_V2DF
);
16933 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
16934 ALTIVEC_BUILTIN_STVX_V2DI
);
16935 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
16936 ALTIVEC_BUILTIN_STVX_V4SF
);
16937 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
16938 ALTIVEC_BUILTIN_STVX_V4SI
);
16939 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
16940 ALTIVEC_BUILTIN_STVX_V8HI
);
16941 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
16942 ALTIVEC_BUILTIN_STVX_V16QI
);
16943 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
16944 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
16945 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
16946 ALTIVEC_BUILTIN_STVXL_V2DF
);
16947 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
16948 ALTIVEC_BUILTIN_STVXL_V2DI
);
16949 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
16950 ALTIVEC_BUILTIN_STVXL_V4SF
);
16951 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
16952 ALTIVEC_BUILTIN_STVXL_V4SI
);
16953 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
16954 ALTIVEC_BUILTIN_STVXL_V8HI
);
16955 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
16956 ALTIVEC_BUILTIN_STVXL_V16QI
);
16957 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
16958 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
16959 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
16960 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
16961 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
16962 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
16963 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
16964 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
16965 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
16966 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
16967 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
16968 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
16969 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
16970 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
16971 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
16972 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
16974 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
16975 VSX_BUILTIN_LXVD2X_V2DF
);
16976 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
16977 VSX_BUILTIN_LXVD2X_V2DI
);
16978 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
16979 VSX_BUILTIN_LXVW4X_V4SF
);
16980 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
16981 VSX_BUILTIN_LXVW4X_V4SI
);
16982 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
16983 VSX_BUILTIN_LXVW4X_V8HI
);
16984 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
16985 VSX_BUILTIN_LXVW4X_V16QI
);
16986 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
16987 VSX_BUILTIN_STXVD2X_V2DF
);
16988 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
16989 VSX_BUILTIN_STXVD2X_V2DI
);
16990 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
16991 VSX_BUILTIN_STXVW4X_V4SF
);
16992 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
16993 VSX_BUILTIN_STXVW4X_V4SI
);
16994 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
16995 VSX_BUILTIN_STXVW4X_V8HI
);
16996 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
16997 VSX_BUILTIN_STXVW4X_V16QI
);
16999 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid
,
17000 VSX_BUILTIN_LD_ELEMREV_V2DF
);
17001 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid
,
17002 VSX_BUILTIN_LD_ELEMREV_V2DI
);
17003 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid
,
17004 VSX_BUILTIN_LD_ELEMREV_V4SF
);
17005 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid
,
17006 VSX_BUILTIN_LD_ELEMREV_V4SI
);
17007 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid
,
17008 VSX_BUILTIN_LD_ELEMREV_V8HI
);
17009 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid
,
17010 VSX_BUILTIN_LD_ELEMREV_V16QI
);
17011 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid
,
17012 VSX_BUILTIN_ST_ELEMREV_V2DF
);
17013 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid
,
17014 VSX_BUILTIN_ST_ELEMREV_V1TI
);
17015 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid
,
17016 VSX_BUILTIN_ST_ELEMREV_V2DI
);
17017 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid
,
17018 VSX_BUILTIN_ST_ELEMREV_V4SF
);
17019 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid
,
17020 VSX_BUILTIN_ST_ELEMREV_V4SI
);
17021 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid
,
17022 VSX_BUILTIN_ST_ELEMREV_V8HI
);
17023 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid
,
17024 VSX_BUILTIN_ST_ELEMREV_V16QI
);
17026 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
17027 VSX_BUILTIN_VEC_LD
);
17028 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
17029 VSX_BUILTIN_VEC_ST
);
17030 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid
,
17031 VSX_BUILTIN_VEC_XL
);
17032 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid
,
17033 VSX_BUILTIN_VEC_XL_BE
);
17034 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid
,
17035 VSX_BUILTIN_VEC_XST
);
17036 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid
,
17037 VSX_BUILTIN_VEC_XST_BE
);
17039 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
17040 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
17041 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
17043 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
17044 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
17045 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
17046 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
17047 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
17048 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
17049 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
17050 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
17051 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
17052 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
17053 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
17054 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
17056 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque
,
17057 ALTIVEC_BUILTIN_VEC_ADDE
);
17058 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque
,
17059 ALTIVEC_BUILTIN_VEC_ADDEC
);
17060 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque
,
17061 ALTIVEC_BUILTIN_VEC_CMPNE
);
17062 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque
,
17063 ALTIVEC_BUILTIN_VEC_MUL
);
17064 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque
,
17065 ALTIVEC_BUILTIN_VEC_SUBE
);
17066 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque
,
17067 ALTIVEC_BUILTIN_VEC_SUBEC
);
17069 /* Cell builtins. */
17070 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
17071 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
17072 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
17073 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
17075 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
17076 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
17077 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
17078 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
17080 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
17081 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
17082 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
17083 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
17085 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
17086 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
17087 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
17088 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
17090 if (TARGET_P9_VECTOR
)
17092 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long
,
17093 P9V_BUILTIN_STXVL
);
17094 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long
,
17095 P9V_BUILTIN_XST_LEN_R
);
17098 /* Add the DST variants. */
17100 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
17102 HOST_WIDE_INT mask
= d
->mask
;
17104 /* It is expected that these dst built-in functions may have
17105 d->icode equal to CODE_FOR_nothing. */
17106 if ((mask
& builtin_mask
) != mask
)
17108 if (TARGET_DEBUG_BUILTIN
)
17109 fprintf (stderr
, "altivec_init_builtins, skip dst %s\n",
17113 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
17116 /* Initialize the predicates. */
17117 d
= bdesc_altivec_preds
;
17118 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
17120 machine_mode mode1
;
17122 HOST_WIDE_INT mask
= d
->mask
;
17124 if ((mask
& builtin_mask
) != mask
)
17126 if (TARGET_DEBUG_BUILTIN
)
17127 fprintf (stderr
, "altivec_init_builtins, skip predicate %s\n",
17132 if (rs6000_overloaded_builtin_p (d
->code
))
17136 /* Cannot define builtin if the instruction is disabled. */
17137 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17138 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
17144 type
= int_ftype_int_opaque_opaque
;
17147 type
= int_ftype_int_v2di_v2di
;
17150 type
= int_ftype_int_v4si_v4si
;
17153 type
= int_ftype_int_v8hi_v8hi
;
17156 type
= int_ftype_int_v16qi_v16qi
;
17159 type
= int_ftype_int_v4sf_v4sf
;
17162 type
= int_ftype_int_v2df_v2df
;
17165 gcc_unreachable ();
17168 def_builtin (d
->name
, type
, d
->code
);
17171 /* Initialize the abs* operators. */
17173 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
17175 machine_mode mode0
;
17177 HOST_WIDE_INT mask
= d
->mask
;
17179 if ((mask
& builtin_mask
) != mask
)
17181 if (TARGET_DEBUG_BUILTIN
)
17182 fprintf (stderr
, "altivec_init_builtins, skip abs %s\n",
17187 /* Cannot define builtin if the instruction is disabled. */
17188 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17189 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
17194 type
= v2di_ftype_v2di
;
17197 type
= v4si_ftype_v4si
;
17200 type
= v8hi_ftype_v8hi
;
17203 type
= v16qi_ftype_v16qi
;
17206 type
= v4sf_ftype_v4sf
;
17209 type
= v2df_ftype_v2df
;
17212 gcc_unreachable ();
17215 def_builtin (d
->name
, type
, d
->code
);
17218 /* Initialize target builtin that implements
17219 targetm.vectorize.builtin_mask_for_load. */
17221 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
17222 v16qi_ftype_long_pcvoid
,
17223 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
17224 BUILT_IN_MD
, NULL
, NULL_TREE
);
17225 TREE_READONLY (decl
) = 1;
17226 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17227 altivec_builtin_mask_for_load
= decl
;
17229 /* Access to the vec_init patterns. */
17230 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
17231 integer_type_node
, integer_type_node
,
17232 integer_type_node
, NULL_TREE
);
17233 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
17235 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
17236 short_integer_type_node
,
17237 short_integer_type_node
,
17238 short_integer_type_node
,
17239 short_integer_type_node
,
17240 short_integer_type_node
,
17241 short_integer_type_node
,
17242 short_integer_type_node
, NULL_TREE
);
17243 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
17245 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
17246 char_type_node
, char_type_node
,
17247 char_type_node
, char_type_node
,
17248 char_type_node
, char_type_node
,
17249 char_type_node
, char_type_node
,
17250 char_type_node
, char_type_node
,
17251 char_type_node
, char_type_node
,
17252 char_type_node
, char_type_node
,
17253 char_type_node
, NULL_TREE
);
17254 def_builtin ("__builtin_vec_init_v16qi", ftype
,
17255 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
17257 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
17258 float_type_node
, float_type_node
,
17259 float_type_node
, NULL_TREE
);
17260 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
17262 /* VSX builtins. */
17263 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
17264 double_type_node
, NULL_TREE
);
17265 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
17267 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
17268 intDI_type_node
, NULL_TREE
);
17269 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
17271 /* Access to the vec_set patterns. */
17272 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
17274 integer_type_node
, NULL_TREE
);
17275 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
17277 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
17279 integer_type_node
, NULL_TREE
);
17280 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
17282 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
17284 integer_type_node
, NULL_TREE
);
17285 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
17287 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
17289 integer_type_node
, NULL_TREE
);
17290 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
17292 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
17294 integer_type_node
, NULL_TREE
);
17295 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
17297 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
17299 integer_type_node
, NULL_TREE
);
17300 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
17302 /* Access to the vec_extract patterns. */
17303 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
17304 integer_type_node
, NULL_TREE
);
17305 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
17307 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
17308 integer_type_node
, NULL_TREE
);
17309 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
17311 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
17312 integer_type_node
, NULL_TREE
);
17313 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
17315 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
17316 integer_type_node
, NULL_TREE
);
17317 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
17319 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
17320 integer_type_node
, NULL_TREE
);
17321 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
17323 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
17324 integer_type_node
, NULL_TREE
);
17325 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
17328 if (V1TI_type_node
)
17330 tree v1ti_ftype_long_pcvoid
17331 = build_function_type_list (V1TI_type_node
,
17332 long_integer_type_node
, pcvoid_type_node
,
17334 tree void_ftype_v1ti_long_pvoid
17335 = build_function_type_list (void_type_node
,
17336 V1TI_type_node
, long_integer_type_node
,
17337 pvoid_type_node
, NULL_TREE
);
17338 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid
,
17339 VSX_BUILTIN_LD_ELEMREV_V1TI
);
17340 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
17341 VSX_BUILTIN_LXVD2X_V1TI
);
17342 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
17343 VSX_BUILTIN_STXVD2X_V1TI
);
17344 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
17345 NULL_TREE
, NULL_TREE
);
17346 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
17347 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
17349 integer_type_node
, NULL_TREE
);
17350 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
17351 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
17352 integer_type_node
, NULL_TREE
);
17353 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
17359 htm_init_builtins (void)
17361 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17362 const struct builtin_description
*d
;
17366 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
17368 tree op
[MAX_HTM_OPERANDS
], type
;
17369 HOST_WIDE_INT mask
= d
->mask
;
17370 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
17371 bool void_func
= (attr
& RS6000_BTC_VOID
);
17372 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
17374 tree gpr_type_node
;
17378 /* It is expected that these htm built-in functions may have
17379 d->icode equal to CODE_FOR_nothing. */
17381 if (TARGET_32BIT
&& TARGET_POWERPC64
)
17382 gpr_type_node
= long_long_unsigned_type_node
;
17384 gpr_type_node
= long_unsigned_type_node
;
17386 if (attr
& RS6000_BTC_SPR
)
17388 rettype
= gpr_type_node
;
17389 argtype
= gpr_type_node
;
17391 else if (d
->code
== HTM_BUILTIN_TABORTDC
17392 || d
->code
== HTM_BUILTIN_TABORTDCI
)
17394 rettype
= unsigned_type_node
;
17395 argtype
= gpr_type_node
;
17399 rettype
= unsigned_type_node
;
17400 argtype
= unsigned_type_node
;
17403 if ((mask
& builtin_mask
) != mask
)
17405 if (TARGET_DEBUG_BUILTIN
)
17406 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
17412 if (TARGET_DEBUG_BUILTIN
)
17413 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
17414 (long unsigned) i
);
17418 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
17420 if (attr_args
== RS6000_BTC_UNARY
)
17421 op
[nopnds
++] = argtype
;
17422 else if (attr_args
== RS6000_BTC_BINARY
)
17424 op
[nopnds
++] = argtype
;
17425 op
[nopnds
++] = argtype
;
17427 else if (attr_args
== RS6000_BTC_TERNARY
)
17429 op
[nopnds
++] = argtype
;
17430 op
[nopnds
++] = argtype
;
17431 op
[nopnds
++] = argtype
;
17437 type
= build_function_type_list (op
[0], NULL_TREE
);
17440 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
17443 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
17446 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
17450 gcc_unreachable ();
17453 def_builtin (d
->name
, type
, d
->code
);
17457 /* Hash function for builtin functions with up to 3 arguments and a return
17460 builtin_hasher::hash (builtin_hash_struct
*bh
)
17465 for (i
= 0; i
< 4; i
++)
17467 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
17468 ret
= (ret
* 2) + bh
->uns_p
[i
];
17474 /* Compare builtin hash entries H1 and H2 for equivalence. */
17476 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
17478 return ((p1
->mode
[0] == p2
->mode
[0])
17479 && (p1
->mode
[1] == p2
->mode
[1])
17480 && (p1
->mode
[2] == p2
->mode
[2])
17481 && (p1
->mode
[3] == p2
->mode
[3])
17482 && (p1
->uns_p
[0] == p2
->uns_p
[0])
17483 && (p1
->uns_p
[1] == p2
->uns_p
[1])
17484 && (p1
->uns_p
[2] == p2
->uns_p
[2])
17485 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
17488 /* Map types for builtin functions with an explicit return type and up to 3
17489 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17490 of the argument. */
17492 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
17493 machine_mode mode_arg1
, machine_mode mode_arg2
,
17494 enum rs6000_builtins builtin
, const char *name
)
17496 struct builtin_hash_struct h
;
17497 struct builtin_hash_struct
*h2
;
17500 tree ret_type
= NULL_TREE
;
17501 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
17503 /* Create builtin_hash_table. */
17504 if (builtin_hash_table
== NULL
)
17505 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
17507 h
.type
= NULL_TREE
;
17508 h
.mode
[0] = mode_ret
;
17509 h
.mode
[1] = mode_arg0
;
17510 h
.mode
[2] = mode_arg1
;
17511 h
.mode
[3] = mode_arg2
;
17517 /* If the builtin is a type that produces unsigned results or takes unsigned
17518 arguments, and it is returned as a decl for the vectorizer (such as
17519 widening multiplies, permute), make sure the arguments and return value
17520 are type correct. */
17523 /* unsigned 1 argument functions. */
17524 case CRYPTO_BUILTIN_VSBOX
:
17525 case P8V_BUILTIN_VGBBD
:
17526 case MISC_BUILTIN_CDTBCD
:
17527 case MISC_BUILTIN_CBCDTD
:
17532 /* unsigned 2 argument functions. */
17533 case ALTIVEC_BUILTIN_VMULEUB
:
17534 case ALTIVEC_BUILTIN_VMULEUH
:
17535 case P8V_BUILTIN_VMULEUW
:
17536 case ALTIVEC_BUILTIN_VMULOUB
:
17537 case ALTIVEC_BUILTIN_VMULOUH
:
17538 case P8V_BUILTIN_VMULOUW
:
17539 case CRYPTO_BUILTIN_VCIPHER
:
17540 case CRYPTO_BUILTIN_VCIPHERLAST
:
17541 case CRYPTO_BUILTIN_VNCIPHER
:
17542 case CRYPTO_BUILTIN_VNCIPHERLAST
:
17543 case CRYPTO_BUILTIN_VPMSUMB
:
17544 case CRYPTO_BUILTIN_VPMSUMH
:
17545 case CRYPTO_BUILTIN_VPMSUMW
:
17546 case CRYPTO_BUILTIN_VPMSUMD
:
17547 case CRYPTO_BUILTIN_VPMSUM
:
17548 case MISC_BUILTIN_ADDG6S
:
17549 case MISC_BUILTIN_DIVWEU
:
17550 case MISC_BUILTIN_DIVDEU
:
17551 case VSX_BUILTIN_UDIV_V2DI
:
17552 case ALTIVEC_BUILTIN_VMAXUB
:
17553 case ALTIVEC_BUILTIN_VMINUB
:
17554 case ALTIVEC_BUILTIN_VMAXUH
:
17555 case ALTIVEC_BUILTIN_VMINUH
:
17556 case ALTIVEC_BUILTIN_VMAXUW
:
17557 case ALTIVEC_BUILTIN_VMINUW
:
17558 case P8V_BUILTIN_VMAXUD
:
17559 case P8V_BUILTIN_VMINUD
:
17565 /* unsigned 3 argument functions. */
17566 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
17567 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
17568 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
17569 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
17570 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
17571 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
17572 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
17573 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
17574 case VSX_BUILTIN_VPERM_16QI_UNS
:
17575 case VSX_BUILTIN_VPERM_8HI_UNS
:
17576 case VSX_BUILTIN_VPERM_4SI_UNS
:
17577 case VSX_BUILTIN_VPERM_2DI_UNS
:
17578 case VSX_BUILTIN_XXSEL_16QI_UNS
:
17579 case VSX_BUILTIN_XXSEL_8HI_UNS
:
17580 case VSX_BUILTIN_XXSEL_4SI_UNS
:
17581 case VSX_BUILTIN_XXSEL_2DI_UNS
:
17582 case CRYPTO_BUILTIN_VPERMXOR
:
17583 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
17584 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
17585 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
17586 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
17587 case CRYPTO_BUILTIN_VSHASIGMAW
:
17588 case CRYPTO_BUILTIN_VSHASIGMAD
:
17589 case CRYPTO_BUILTIN_VSHASIGMA
:
17596 /* signed permute functions with unsigned char mask. */
17597 case ALTIVEC_BUILTIN_VPERM_16QI
:
17598 case ALTIVEC_BUILTIN_VPERM_8HI
:
17599 case ALTIVEC_BUILTIN_VPERM_4SI
:
17600 case ALTIVEC_BUILTIN_VPERM_4SF
:
17601 case ALTIVEC_BUILTIN_VPERM_2DI
:
17602 case ALTIVEC_BUILTIN_VPERM_2DF
:
17603 case VSX_BUILTIN_VPERM_16QI
:
17604 case VSX_BUILTIN_VPERM_8HI
:
17605 case VSX_BUILTIN_VPERM_4SI
:
17606 case VSX_BUILTIN_VPERM_4SF
:
17607 case VSX_BUILTIN_VPERM_2DI
:
17608 case VSX_BUILTIN_VPERM_2DF
:
17612 /* unsigned args, signed return. */
17613 case VSX_BUILTIN_XVCVUXDSP
:
17614 case VSX_BUILTIN_XVCVUXDDP_UNS
:
17615 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
17619 /* signed args, unsigned return. */
17620 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
17621 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
17622 case MISC_BUILTIN_UNPACK_TD
:
17623 case MISC_BUILTIN_UNPACK_V1TI
:
17627 /* unsigned arguments, bool return (compares). */
17628 case ALTIVEC_BUILTIN_VCMPEQUB
:
17629 case ALTIVEC_BUILTIN_VCMPEQUH
:
17630 case ALTIVEC_BUILTIN_VCMPEQUW
:
17631 case P8V_BUILTIN_VCMPEQUD
:
17632 case VSX_BUILTIN_CMPGE_U16QI
:
17633 case VSX_BUILTIN_CMPGE_U8HI
:
17634 case VSX_BUILTIN_CMPGE_U4SI
:
17635 case VSX_BUILTIN_CMPGE_U2DI
:
17636 case ALTIVEC_BUILTIN_VCMPGTUB
:
17637 case ALTIVEC_BUILTIN_VCMPGTUH
:
17638 case ALTIVEC_BUILTIN_VCMPGTUW
:
17639 case P8V_BUILTIN_VCMPGTUD
:
17644 /* unsigned arguments for 128-bit pack instructions. */
17645 case MISC_BUILTIN_PACK_TD
:
17646 case MISC_BUILTIN_PACK_V1TI
:
17651 /* unsigned second arguments (vector shift right). */
17652 case ALTIVEC_BUILTIN_VSRB
:
17653 case ALTIVEC_BUILTIN_VSRH
:
17654 case ALTIVEC_BUILTIN_VSRW
:
17655 case P8V_BUILTIN_VSRD
:
17663 /* Figure out how many args are present. */
17664 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
17667 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
17668 if (!ret_type
&& h
.uns_p
[0])
17669 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
17672 fatal_error (input_location
,
17673 "internal error: builtin function %qs had an unexpected "
17674 "return type %qs", name
, GET_MODE_NAME (h
.mode
[0]));
17676 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
17677 arg_type
[i
] = NULL_TREE
;
17679 for (i
= 0; i
< num_args
; i
++)
17681 int m
= (int) h
.mode
[i
+1];
17682 int uns_p
= h
.uns_p
[i
+1];
17684 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
17685 if (!arg_type
[i
] && uns_p
)
17686 arg_type
[i
] = builtin_mode_to_type
[m
][0];
17689 fatal_error (input_location
,
17690 "internal error: builtin function %qs, argument %d "
17691 "had unexpected argument type %qs", name
, i
,
17692 GET_MODE_NAME (m
));
17695 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
17696 if (*found
== NULL
)
17698 h2
= ggc_alloc
<builtin_hash_struct
> ();
17702 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
17703 arg_type
[2], NULL_TREE
);
17706 return (*found
)->type
;
17710 rs6000_common_init_builtins (void)
17712 const struct builtin_description
*d
;
17715 tree opaque_ftype_opaque
= NULL_TREE
;
17716 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
17717 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
17718 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17720 /* Create Altivec and VSX builtins on machines with at least the
17721 general purpose extensions (970 and newer) to allow the use of
17722 the target attribute. */
17724 if (TARGET_EXTRA_BUILTINS
)
17725 builtin_mask
|= RS6000_BTM_COMMON
;
17727 /* Add the ternary operators. */
17729 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
17732 HOST_WIDE_INT mask
= d
->mask
;
17734 if ((mask
& builtin_mask
) != mask
)
17736 if (TARGET_DEBUG_BUILTIN
)
17737 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
17741 if (rs6000_overloaded_builtin_p (d
->code
))
17743 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
17744 type
= opaque_ftype_opaque_opaque_opaque
17745 = build_function_type_list (opaque_V4SI_type_node
,
17746 opaque_V4SI_type_node
,
17747 opaque_V4SI_type_node
,
17748 opaque_V4SI_type_node
,
17753 enum insn_code icode
= d
->icode
;
17756 if (TARGET_DEBUG_BUILTIN
)
17757 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17763 if (icode
== CODE_FOR_nothing
)
17765 if (TARGET_DEBUG_BUILTIN
)
17766 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
17772 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
17773 insn_data
[icode
].operand
[1].mode
,
17774 insn_data
[icode
].operand
[2].mode
,
17775 insn_data
[icode
].operand
[3].mode
,
17779 def_builtin (d
->name
, type
, d
->code
);
17782 /* Add the binary operators. */
17784 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
17786 machine_mode mode0
, mode1
, mode2
;
17788 HOST_WIDE_INT mask
= d
->mask
;
17790 if ((mask
& builtin_mask
) != mask
)
17792 if (TARGET_DEBUG_BUILTIN
)
17793 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
17797 if (rs6000_overloaded_builtin_p (d
->code
))
17799 if (! (type
= opaque_ftype_opaque_opaque
))
17800 type
= opaque_ftype_opaque_opaque
17801 = build_function_type_list (opaque_V4SI_type_node
,
17802 opaque_V4SI_type_node
,
17803 opaque_V4SI_type_node
,
17808 enum insn_code icode
= d
->icode
;
17811 if (TARGET_DEBUG_BUILTIN
)
17812 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17818 if (icode
== CODE_FOR_nothing
)
17820 if (TARGET_DEBUG_BUILTIN
)
17821 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
17827 mode0
= insn_data
[icode
].operand
[0].mode
;
17828 mode1
= insn_data
[icode
].operand
[1].mode
;
17829 mode2
= insn_data
[icode
].operand
[2].mode
;
17831 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
17835 def_builtin (d
->name
, type
, d
->code
);
17838 /* Add the simple unary operators. */
17840 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
17842 machine_mode mode0
, mode1
;
17844 HOST_WIDE_INT mask
= d
->mask
;
17846 if ((mask
& builtin_mask
) != mask
)
17848 if (TARGET_DEBUG_BUILTIN
)
17849 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
17853 if (rs6000_overloaded_builtin_p (d
->code
))
17855 if (! (type
= opaque_ftype_opaque
))
17856 type
= opaque_ftype_opaque
17857 = build_function_type_list (opaque_V4SI_type_node
,
17858 opaque_V4SI_type_node
,
17863 enum insn_code icode
= d
->icode
;
17866 if (TARGET_DEBUG_BUILTIN
)
17867 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17873 if (icode
== CODE_FOR_nothing
)
17875 if (TARGET_DEBUG_BUILTIN
)
17876 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
17882 mode0
= insn_data
[icode
].operand
[0].mode
;
17883 mode1
= insn_data
[icode
].operand
[1].mode
;
17885 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
17889 def_builtin (d
->name
, type
, d
->code
);
17892 /* Add the simple no-argument operators. */
17894 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
17896 machine_mode mode0
;
17898 HOST_WIDE_INT mask
= d
->mask
;
17900 if ((mask
& builtin_mask
) != mask
)
17902 if (TARGET_DEBUG_BUILTIN
)
17903 fprintf (stderr
, "rs6000_builtin, skip no-argument %s\n", d
->name
);
17906 if (rs6000_overloaded_builtin_p (d
->code
))
17908 if (!opaque_ftype_opaque
)
17909 opaque_ftype_opaque
17910 = build_function_type_list (opaque_V4SI_type_node
, NULL_TREE
);
17911 type
= opaque_ftype_opaque
;
17915 enum insn_code icode
= d
->icode
;
17918 if (TARGET_DEBUG_BUILTIN
)
17919 fprintf (stderr
, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17920 (long unsigned) i
);
17923 if (icode
== CODE_FOR_nothing
)
17925 if (TARGET_DEBUG_BUILTIN
)
17927 "rs6000_builtin, skip no-argument %s (no code)\n",
17931 mode0
= insn_data
[icode
].operand
[0].mode
;
17932 type
= builtin_function_type (mode0
, VOIDmode
, VOIDmode
, VOIDmode
,
17935 def_builtin (d
->name
, type
, d
->code
);
17939 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17941 init_float128_ibm (machine_mode mode
)
17943 if (!TARGET_XL_COMPAT
)
17945 set_optab_libfunc (add_optab
, mode
, "__gcc_qadd");
17946 set_optab_libfunc (sub_optab
, mode
, "__gcc_qsub");
17947 set_optab_libfunc (smul_optab
, mode
, "__gcc_qmul");
17948 set_optab_libfunc (sdiv_optab
, mode
, "__gcc_qdiv");
17950 if (!TARGET_HARD_FLOAT
)
17952 set_optab_libfunc (neg_optab
, mode
, "__gcc_qneg");
17953 set_optab_libfunc (eq_optab
, mode
, "__gcc_qeq");
17954 set_optab_libfunc (ne_optab
, mode
, "__gcc_qne");
17955 set_optab_libfunc (gt_optab
, mode
, "__gcc_qgt");
17956 set_optab_libfunc (ge_optab
, mode
, "__gcc_qge");
17957 set_optab_libfunc (lt_optab
, mode
, "__gcc_qlt");
17958 set_optab_libfunc (le_optab
, mode
, "__gcc_qle");
17959 set_optab_libfunc (unord_optab
, mode
, "__gcc_qunord");
17961 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__gcc_stoq");
17962 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__gcc_dtoq");
17963 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__gcc_qtos");
17964 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__gcc_qtod");
17965 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__gcc_qtoi");
17966 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__gcc_qtou");
17967 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__gcc_itoq");
17968 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__gcc_utoq");
17973 set_optab_libfunc (add_optab
, mode
, "_xlqadd");
17974 set_optab_libfunc (sub_optab
, mode
, "_xlqsub");
17975 set_optab_libfunc (smul_optab
, mode
, "_xlqmul");
17976 set_optab_libfunc (sdiv_optab
, mode
, "_xlqdiv");
17979 /* Add various conversions for IFmode to use the traditional TFmode
17981 if (mode
== IFmode
)
17983 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdtf");
17984 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddtf");
17985 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctdtf");
17986 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunctfsd");
17987 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunctfdd");
17988 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtftd");
17990 if (TARGET_POWERPC64
)
17992 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixtfti");
17993 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunstfti");
17994 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattitf");
17995 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntitf");
18000 /* Create a decl for either complex long double multiply or complex long double
18001 divide when long double is IEEE 128-bit floating point. We can't use
18002 __multc3 and __divtc3 because the original long double using IBM extended
18003 double used those names. The complex multiply/divide functions are encoded
18004 as builtin functions with a complex result and 4 scalar inputs. */
18007 create_complex_muldiv (const char *name
, built_in_function fncode
, tree fntype
)
18009 tree fndecl
= add_builtin_function (name
, fntype
, fncode
, BUILT_IN_NORMAL
,
18012 set_builtin_decl (fncode
, fndecl
, true);
18014 if (TARGET_DEBUG_BUILTIN
)
18015 fprintf (stderr
, "create complex %s, fncode: %d\n", name
, (int) fncode
);
18020 /* Set up IEEE 128-bit floating point routines. Use different names if the
18021 arguments can be passed in a vector register. The historical PowerPC
18022 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18023 continue to use that if we aren't using vector registers to pass IEEE
18024 128-bit floating point. */
18027 init_float128_ieee (machine_mode mode
)
18029 if (FLOAT128_VECTOR_P (mode
))
18031 static bool complex_muldiv_init_p
= false;
18033 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
18034 we have clone or target attributes, this will be called a second
18035 time. We want to create the built-in function only once. */
18036 if (mode
== TFmode
&& TARGET_IEEEQUAD
&& !complex_muldiv_init_p
)
18038 complex_muldiv_init_p
= true;
18039 built_in_function fncode_mul
=
18040 (built_in_function
) (BUILT_IN_COMPLEX_MUL_MIN
+ TCmode
18041 - MIN_MODE_COMPLEX_FLOAT
);
18042 built_in_function fncode_div
=
18043 (built_in_function
) (BUILT_IN_COMPLEX_DIV_MIN
+ TCmode
18044 - MIN_MODE_COMPLEX_FLOAT
);
18046 tree fntype
= build_function_type_list (complex_long_double_type_node
,
18047 long_double_type_node
,
18048 long_double_type_node
,
18049 long_double_type_node
,
18050 long_double_type_node
,
18053 create_complex_muldiv ("__mulkc3", fncode_mul
, fntype
);
18054 create_complex_muldiv ("__divkc3", fncode_div
, fntype
);
18057 set_optab_libfunc (add_optab
, mode
, "__addkf3");
18058 set_optab_libfunc (sub_optab
, mode
, "__subkf3");
18059 set_optab_libfunc (neg_optab
, mode
, "__negkf2");
18060 set_optab_libfunc (smul_optab
, mode
, "__mulkf3");
18061 set_optab_libfunc (sdiv_optab
, mode
, "__divkf3");
18062 set_optab_libfunc (sqrt_optab
, mode
, "__sqrtkf2");
18063 set_optab_libfunc (abs_optab
, mode
, "__abskf2");
18064 set_optab_libfunc (powi_optab
, mode
, "__powikf2");
18066 set_optab_libfunc (eq_optab
, mode
, "__eqkf2");
18067 set_optab_libfunc (ne_optab
, mode
, "__nekf2");
18068 set_optab_libfunc (gt_optab
, mode
, "__gtkf2");
18069 set_optab_libfunc (ge_optab
, mode
, "__gekf2");
18070 set_optab_libfunc (lt_optab
, mode
, "__ltkf2");
18071 set_optab_libfunc (le_optab
, mode
, "__lekf2");
18072 set_optab_libfunc (unord_optab
, mode
, "__unordkf2");
18074 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__extendsfkf2");
18075 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__extenddfkf2");
18076 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__trunckfsf2");
18077 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__trunckfdf2");
18079 set_conv_libfunc (sext_optab
, mode
, IFmode
, "__trunctfkf2");
18080 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18081 set_conv_libfunc (sext_optab
, mode
, TFmode
, "__trunctfkf2");
18083 set_conv_libfunc (trunc_optab
, IFmode
, mode
, "__extendkftf2");
18084 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18085 set_conv_libfunc (trunc_optab
, TFmode
, mode
, "__extendkftf2");
18087 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdkf");
18088 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddkf");
18089 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctdkf");
18090 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunckfsd");
18091 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunckfdd");
18092 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendkftd");
18094 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__fixkfsi");
18095 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__fixunskfsi");
18096 set_conv_libfunc (sfix_optab
, DImode
, mode
, "__fixkfdi");
18097 set_conv_libfunc (ufix_optab
, DImode
, mode
, "__fixunskfdi");
18099 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__floatsikf");
18100 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__floatunsikf");
18101 set_conv_libfunc (sfloat_optab
, mode
, DImode
, "__floatdikf");
18102 set_conv_libfunc (ufloat_optab
, mode
, DImode
, "__floatundikf");
18104 if (TARGET_POWERPC64
)
18106 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixkfti");
18107 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunskfti");
18108 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattikf");
18109 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntikf");
18115 set_optab_libfunc (add_optab
, mode
, "_q_add");
18116 set_optab_libfunc (sub_optab
, mode
, "_q_sub");
18117 set_optab_libfunc (neg_optab
, mode
, "_q_neg");
18118 set_optab_libfunc (smul_optab
, mode
, "_q_mul");
18119 set_optab_libfunc (sdiv_optab
, mode
, "_q_div");
18120 if (TARGET_PPC_GPOPT
)
18121 set_optab_libfunc (sqrt_optab
, mode
, "_q_sqrt");
18123 set_optab_libfunc (eq_optab
, mode
, "_q_feq");
18124 set_optab_libfunc (ne_optab
, mode
, "_q_fne");
18125 set_optab_libfunc (gt_optab
, mode
, "_q_fgt");
18126 set_optab_libfunc (ge_optab
, mode
, "_q_fge");
18127 set_optab_libfunc (lt_optab
, mode
, "_q_flt");
18128 set_optab_libfunc (le_optab
, mode
, "_q_fle");
18130 set_conv_libfunc (sext_optab
, mode
, SFmode
, "_q_stoq");
18131 set_conv_libfunc (sext_optab
, mode
, DFmode
, "_q_dtoq");
18132 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "_q_qtos");
18133 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "_q_qtod");
18134 set_conv_libfunc (sfix_optab
, SImode
, mode
, "_q_qtoi");
18135 set_conv_libfunc (ufix_optab
, SImode
, mode
, "_q_qtou");
18136 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "_q_itoq");
18137 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "_q_utoq");
18142 rs6000_init_libfuncs (void)
18144 /* __float128 support. */
18145 if (TARGET_FLOAT128_TYPE
)
18147 init_float128_ibm (IFmode
);
18148 init_float128_ieee (KFmode
);
18151 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18152 if (TARGET_LONG_DOUBLE_128
)
18154 if (!TARGET_IEEEQUAD
)
18155 init_float128_ibm (TFmode
);
18157 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18159 init_float128_ieee (TFmode
);
18163 /* Emit a potentially record-form instruction, setting DST from SRC.
18164 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18165 signed comparison of DST with zero. If DOT is 1, the generated RTL
18166 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18167 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18168 a separate COMPARE. */
18171 rs6000_emit_dot_insn (rtx dst
, rtx src
, int dot
, rtx ccreg
)
18175 emit_move_insn (dst
, src
);
18179 if (cc_reg_not_cr0_operand (ccreg
, CCmode
))
18181 emit_move_insn (dst
, src
);
18182 emit_move_insn (ccreg
, gen_rtx_COMPARE (CCmode
, dst
, const0_rtx
));
18186 rtx ccset
= gen_rtx_SET (ccreg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
));
18189 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, dst
);
18190 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, clobber
)));
18194 rtx set
= gen_rtx_SET (dst
, src
);
18195 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, set
)));
18200 /* A validation routine: say whether CODE, a condition code, and MODE
18201 match. The other alternatives either don't make sense or should
18202 never be generated. */
18205 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
18207 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
18208 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
18209 && GET_MODE_CLASS (mode
) == MODE_CC
);
18211 /* These don't make sense. */
18212 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
18213 || mode
!= CCUNSmode
);
18215 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
18216 || mode
== CCUNSmode
);
18218 gcc_assert (mode
== CCFPmode
18219 || (code
!= ORDERED
&& code
!= UNORDERED
18220 && code
!= UNEQ
&& code
!= LTGT
18221 && code
!= UNGT
&& code
!= UNLT
18222 && code
!= UNGE
&& code
!= UNLE
));
18224 /* These should never be generated except for
18225 flag_finite_math_only. */
18226 gcc_assert (mode
!= CCFPmode
18227 || flag_finite_math_only
18228 || (code
!= LE
&& code
!= GE
18229 && code
!= UNEQ
&& code
!= LTGT
18230 && code
!= UNGT
&& code
!= UNLT
));
18232 /* These are invalid; the information is not there. */
18233 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
18237 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18238 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18239 not zero, store there the bit offset (counted from the right) where
18240 the single stretch of 1 bits begins; and similarly for B, the bit
18241 offset where it ends. */
18244 rs6000_is_valid_mask (rtx mask
, int *b
, int *e
, machine_mode mode
)
18246 unsigned HOST_WIDE_INT val
= INTVAL (mask
);
18247 unsigned HOST_WIDE_INT bit
;
18249 int n
= GET_MODE_PRECISION (mode
);
18251 if (mode
!= DImode
&& mode
!= SImode
)
18254 if (INTVAL (mask
) >= 0)
18257 ne
= exact_log2 (bit
);
18258 nb
= exact_log2 (val
+ bit
);
18260 else if (val
+ 1 == 0)
18269 nb
= exact_log2 (bit
);
18270 ne
= exact_log2 (val
+ bit
);
18275 ne
= exact_log2 (bit
);
18276 if (val
+ bit
== 0)
18284 if (nb
< 0 || ne
< 0 || nb
>= n
|| ne
>= n
)
18295 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18296 or rldicr instruction, to implement an AND with it in mode MODE. */
18299 rs6000_is_valid_and_mask (rtx mask
, machine_mode mode
)
18303 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18306 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18308 if (mode
== DImode
)
18309 return (ne
== 0 || nb
== 63 || (nb
< 32 && ne
<= nb
));
18311 /* For SImode, rlwinm can do everything. */
18312 if (mode
== SImode
)
18313 return (nb
< 32 && ne
< 32);
18318 /* Return the instruction template for an AND with mask in mode MODE, with
18319 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18322 rs6000_insn_for_and_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18326 if (!rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
))
18327 gcc_unreachable ();
18329 if (mode
== DImode
&& ne
== 0)
18331 operands
[3] = GEN_INT (63 - nb
);
18333 return "rldicl. %0,%1,0,%3";
18334 return "rldicl %0,%1,0,%3";
18337 if (mode
== DImode
&& nb
== 63)
18339 operands
[3] = GEN_INT (63 - ne
);
18341 return "rldicr. %0,%1,0,%3";
18342 return "rldicr %0,%1,0,%3";
18345 if (nb
< 32 && ne
< 32)
18347 operands
[3] = GEN_INT (31 - nb
);
18348 operands
[4] = GEN_INT (31 - ne
);
18350 return "rlwinm. %0,%1,0,%3,%4";
18351 return "rlwinm %0,%1,0,%3,%4";
18354 gcc_unreachable ();
18357 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18358 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18359 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18362 rs6000_is_valid_shift_mask (rtx mask
, rtx shift
, machine_mode mode
)
18366 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18369 int n
= GET_MODE_PRECISION (mode
);
18372 if (CONST_INT_P (XEXP (shift
, 1)))
18374 sh
= INTVAL (XEXP (shift
, 1));
18375 if (sh
< 0 || sh
>= n
)
18379 rtx_code code
= GET_CODE (shift
);
18381 /* Convert any shift by 0 to a rotate, to simplify below code. */
18385 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18386 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18388 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18394 /* DImode rotates need rld*. */
18395 if (mode
== DImode
&& code
== ROTATE
)
18396 return (nb
== 63 || ne
== 0 || ne
== sh
);
18398 /* SImode rotates need rlw*. */
18399 if (mode
== SImode
&& code
== ROTATE
)
18400 return (nb
< 32 && ne
< 32 && sh
< 32);
18402 /* Wrap-around masks are only okay for rotates. */
18406 /* Variable shifts are only okay for rotates. */
18410 /* Don't allow ASHIFT if the mask is wrong for that. */
18411 if (code
== ASHIFT
&& ne
< sh
)
18414 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18415 if the mask is wrong for that. */
18416 if (nb
< 32 && ne
< 32 && sh
< 32
18417 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18420 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18421 if the mask is wrong for that. */
18422 if (code
== LSHIFTRT
)
18424 if (nb
== 63 || ne
== 0 || ne
== sh
)
18425 return !(code
== LSHIFTRT
&& nb
>= sh
);
18430 /* Return the instruction template for a shift with mask in mode MODE, with
18431 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18434 rs6000_insn_for_shift_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18438 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18439 gcc_unreachable ();
18441 if (mode
== DImode
&& ne
== 0)
18443 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18444 operands
[2] = GEN_INT (64 - INTVAL (operands
[2]));
18445 operands
[3] = GEN_INT (63 - nb
);
18447 return "rld%I2cl. %0,%1,%2,%3";
18448 return "rld%I2cl %0,%1,%2,%3";
18451 if (mode
== DImode
&& nb
== 63)
18453 operands
[3] = GEN_INT (63 - ne
);
18455 return "rld%I2cr. %0,%1,%2,%3";
18456 return "rld%I2cr %0,%1,%2,%3";
18460 && GET_CODE (operands
[4]) != LSHIFTRT
18461 && CONST_INT_P (operands
[2])
18462 && ne
== INTVAL (operands
[2]))
18464 operands
[3] = GEN_INT (63 - nb
);
18466 return "rld%I2c. %0,%1,%2,%3";
18467 return "rld%I2c %0,%1,%2,%3";
18470 if (nb
< 32 && ne
< 32)
18472 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18473 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
18474 operands
[3] = GEN_INT (31 - nb
);
18475 operands
[4] = GEN_INT (31 - ne
);
18476 /* This insn can also be a 64-bit rotate with mask that really makes
18477 it just a shift right (with mask); the %h below are to adjust for
18478 that situation (shift count is >= 32 in that case). */
18480 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18481 return "rlw%I2nm %0,%1,%h2,%3,%4";
18484 gcc_unreachable ();
18487 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18488 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18489 ASHIFT, or LSHIFTRT) in mode MODE. */
18492 rs6000_is_valid_insert_mask (rtx mask
, rtx shift
, machine_mode mode
)
18496 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18499 int n
= GET_MODE_PRECISION (mode
);
18501 int sh
= INTVAL (XEXP (shift
, 1));
18502 if (sh
< 0 || sh
>= n
)
18505 rtx_code code
= GET_CODE (shift
);
18507 /* Convert any shift by 0 to a rotate, to simplify below code. */
18511 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18512 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18514 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18520 /* DImode rotates need rldimi. */
18521 if (mode
== DImode
&& code
== ROTATE
)
18524 /* SImode rotates need rlwimi. */
18525 if (mode
== SImode
&& code
== ROTATE
)
18526 return (nb
< 32 && ne
< 32 && sh
< 32);
18528 /* Wrap-around masks are only okay for rotates. */
18532 /* Don't allow ASHIFT if the mask is wrong for that. */
18533 if (code
== ASHIFT
&& ne
< sh
)
18536 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18537 if the mask is wrong for that. */
18538 if (nb
< 32 && ne
< 32 && sh
< 32
18539 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18542 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18543 if the mask is wrong for that. */
18544 if (code
== LSHIFTRT
)
18547 return !(code
== LSHIFTRT
&& nb
>= sh
);
18552 /* Return the instruction template for an insert with mask in mode MODE, with
18553 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18556 rs6000_insn_for_insert_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18560 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18561 gcc_unreachable ();
18563 /* Prefer rldimi because rlwimi is cracked. */
18564 if (TARGET_POWERPC64
18565 && (!dot
|| mode
== DImode
)
18566 && GET_CODE (operands
[4]) != LSHIFTRT
18567 && ne
== INTVAL (operands
[2]))
18569 operands
[3] = GEN_INT (63 - nb
);
18571 return "rldimi. %0,%1,%2,%3";
18572 return "rldimi %0,%1,%2,%3";
18575 if (nb
< 32 && ne
< 32)
18577 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18578 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
18579 operands
[3] = GEN_INT (31 - nb
);
18580 operands
[4] = GEN_INT (31 - ne
);
18582 return "rlwimi. %0,%1,%2,%3,%4";
18583 return "rlwimi %0,%1,%2,%3,%4";
18586 gcc_unreachable ();
18589 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18590 using two machine instructions. */
18593 rs6000_is_valid_2insn_and (rtx c
, machine_mode mode
)
18595 /* There are two kinds of AND we can handle with two insns:
18596 1) those we can do with two rl* insn;
18599 We do not handle that last case yet. */
18601 /* If there is just one stretch of ones, we can do it. */
18602 if (rs6000_is_valid_mask (c
, NULL
, NULL
, mode
))
18605 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18606 one insn, we can do the whole thing with two. */
18607 unsigned HOST_WIDE_INT val
= INTVAL (c
);
18608 unsigned HOST_WIDE_INT bit1
= val
& -val
;
18609 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
18610 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
18611 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
18612 return rs6000_is_valid_and_mask (GEN_INT (val
+ bit3
- bit2
), mode
);
18615 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18616 If EXPAND is true, split rotate-and-mask instructions we generate to
18617 their constituent parts as well (this is used during expand); if DOT
18618 is 1, make the last insn a record-form instruction clobbering the
18619 destination GPR and setting the CC reg (from operands[3]); if 2, set
18620 that GPR as well as the CC reg. */
18623 rs6000_emit_2insn_and (machine_mode mode
, rtx
*operands
, bool expand
, int dot
)
18625 gcc_assert (!(expand
&& dot
));
18627 unsigned HOST_WIDE_INT val
= INTVAL (operands
[2]);
18629 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18630 shift right. This generates better code than doing the masks without
18631 shifts, or shifting first right and then left. */
18633 if (rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
) && nb
>= ne
)
18635 gcc_assert (mode
== DImode
);
18637 int shift
= 63 - nb
;
18640 rtx tmp1
= gen_reg_rtx (DImode
);
18641 rtx tmp2
= gen_reg_rtx (DImode
);
18642 emit_insn (gen_ashldi3 (tmp1
, operands
[1], GEN_INT (shift
)));
18643 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (val
<< shift
)));
18644 emit_insn (gen_lshrdi3 (operands
[0], tmp2
, GEN_INT (shift
)));
18648 rtx tmp
= gen_rtx_ASHIFT (mode
, operands
[1], GEN_INT (shift
));
18649 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (val
<< shift
));
18650 emit_move_insn (operands
[0], tmp
);
18651 tmp
= gen_rtx_LSHIFTRT (mode
, operands
[0], GEN_INT (shift
));
18652 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18657 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18658 that does the rest. */
18659 unsigned HOST_WIDE_INT bit1
= val
& -val
;
18660 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
18661 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
18662 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
18664 unsigned HOST_WIDE_INT mask1
= -bit3
+ bit2
- 1;
18665 unsigned HOST_WIDE_INT mask2
= val
+ bit3
- bit2
;
18667 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2
), mode
));
18669 /* Two "no-rotate"-and-mask instructions, for SImode. */
18670 if (rs6000_is_valid_and_mask (GEN_INT (mask1
), mode
))
18672 gcc_assert (mode
== SImode
);
18674 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
18675 rtx tmp
= gen_rtx_AND (mode
, operands
[1], GEN_INT (mask1
));
18676 emit_move_insn (reg
, tmp
);
18677 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
18678 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18682 gcc_assert (mode
== DImode
);
18684 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18685 insns; we have to do the first in SImode, because it wraps. */
18686 if (mask2
<= 0xffffffff
18687 && rs6000_is_valid_and_mask (GEN_INT (mask1
), SImode
))
18689 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
18690 rtx tmp
= gen_rtx_AND (SImode
, gen_lowpart (SImode
, operands
[1]),
18692 rtx reg_low
= gen_lowpart (SImode
, reg
);
18693 emit_move_insn (reg_low
, tmp
);
18694 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
18695 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18699 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18700 at the top end), rotate back and clear the other hole. */
18701 int right
= exact_log2 (bit3
);
18702 int left
= 64 - right
;
18704 /* Rotate the mask too. */
18705 mask1
= (mask1
>> right
) | ((bit2
- 1) << left
);
18709 rtx tmp1
= gen_reg_rtx (DImode
);
18710 rtx tmp2
= gen_reg_rtx (DImode
);
18711 rtx tmp3
= gen_reg_rtx (DImode
);
18712 emit_insn (gen_rotldi3 (tmp1
, operands
[1], GEN_INT (left
)));
18713 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (mask1
)));
18714 emit_insn (gen_rotldi3 (tmp3
, tmp2
, GEN_INT (right
)));
18715 emit_insn (gen_anddi3 (operands
[0], tmp3
, GEN_INT (mask2
)));
18719 rtx tmp
= gen_rtx_ROTATE (mode
, operands
[1], GEN_INT (left
));
18720 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask1
));
18721 emit_move_insn (operands
[0], tmp
);
18722 tmp
= gen_rtx_ROTATE (mode
, operands
[0], GEN_INT (right
));
18723 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask2
));
18724 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18728 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18729 for lfq and stfq insns iff the registers are hard registers. */
18732 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
18734 /* We might have been passed a SUBREG. */
18735 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
18738 /* We might have been passed non floating point registers. */
18739 if (!FP_REGNO_P (REGNO (reg1
))
18740 || !FP_REGNO_P (REGNO (reg2
)))
18743 return (REGNO (reg1
) == REGNO (reg2
) - 1);
18746 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18747 addr1 and addr2 must be in consecutive memory locations
18748 (addr2 == addr1 + 8). */
18751 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
18754 unsigned int reg1
, reg2
;
18755 int offset1
, offset2
;
18757 /* The mems cannot be volatile. */
18758 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
18761 addr1
= XEXP (mem1
, 0);
18762 addr2
= XEXP (mem2
, 0);
18764 /* Extract an offset (if used) from the first addr. */
18765 if (GET_CODE (addr1
) == PLUS
)
18767 /* If not a REG, return zero. */
18768 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
18772 reg1
= REGNO (XEXP (addr1
, 0));
18773 /* The offset must be constant! */
18774 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
18776 offset1
= INTVAL (XEXP (addr1
, 1));
18779 else if (GET_CODE (addr1
) != REG
)
18783 reg1
= REGNO (addr1
);
18784 /* This was a simple (mem (reg)) expression. Offset is 0. */
18788 /* And now for the second addr. */
18789 if (GET_CODE (addr2
) == PLUS
)
18791 /* If not a REG, return zero. */
18792 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
18796 reg2
= REGNO (XEXP (addr2
, 0));
18797 /* The offset must be constant. */
18798 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
18800 offset2
= INTVAL (XEXP (addr2
, 1));
18803 else if (GET_CODE (addr2
) != REG
)
18807 reg2
= REGNO (addr2
);
18808 /* This was a simple (mem (reg)) expression. Offset is 0. */
18812 /* Both of these must have the same base register. */
18816 /* The offset for the second addr must be 8 more than the first addr. */
18817 if (offset2
!= offset1
+ 8)
18820 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18825 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18826 need to use DDmode, in all other cases we can use the same mode. */
18827 static machine_mode
18828 rs6000_secondary_memory_needed_mode (machine_mode mode
)
18830 if (lra_in_progress
&& mode
== SDmode
)
18835 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18836 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18837 only work on the traditional altivec registers, note if an altivec register
18840 static enum rs6000_reg_type
18841 register_to_reg_type (rtx reg
, bool *is_altivec
)
18843 HOST_WIDE_INT regno
;
18844 enum reg_class rclass
;
18846 if (GET_CODE (reg
) == SUBREG
)
18847 reg
= SUBREG_REG (reg
);
18850 return NO_REG_TYPE
;
18852 regno
= REGNO (reg
);
18853 if (regno
>= FIRST_PSEUDO_REGISTER
)
18855 if (!lra_in_progress
&& !reload_completed
)
18856 return PSEUDO_REG_TYPE
;
18858 regno
= true_regnum (reg
);
18859 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
18860 return PSEUDO_REG_TYPE
;
18863 gcc_assert (regno
>= 0);
18865 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
18866 *is_altivec
= true;
18868 rclass
= rs6000_regno_regclass
[regno
];
18869 return reg_class_to_reg_type
[(int)rclass
];
18872 /* Helper function to return the cost of adding a TOC entry address. */
18875 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
18879 if (TARGET_CMODEL
!= CMODEL_SMALL
)
18880 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
18883 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
18888 /* Helper function for rs6000_secondary_reload to determine whether the memory
18889 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18890 needs reloading. Return negative if the memory is not handled by the memory
18891 helper functions and to try a different reload method, 0 if no additional
18892 instructions are need, and positive to give the extra cost for the
18896 rs6000_secondary_reload_memory (rtx addr
,
18897 enum reg_class rclass
,
18900 int extra_cost
= 0;
18901 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
18902 addr_mask_type addr_mask
;
18903 const char *type
= NULL
;
18904 const char *fail_msg
= NULL
;
18906 if (GPR_REG_CLASS_P (rclass
))
18907 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
18909 else if (rclass
== FLOAT_REGS
)
18910 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
18912 else if (rclass
== ALTIVEC_REGS
)
18913 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
18915 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18916 else if (rclass
== VSX_REGS
)
18917 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
18918 & ~RELOAD_REG_AND_M16
);
18920 /* If the register allocator hasn't made up its mind yet on the register
18921 class to use, settle on defaults to use. */
18922 else if (rclass
== NO_REGS
)
18924 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
]
18925 & ~RELOAD_REG_AND_M16
);
18927 if ((addr_mask
& RELOAD_REG_MULTIPLE
) != 0)
18928 addr_mask
&= ~(RELOAD_REG_INDEXED
18929 | RELOAD_REG_PRE_INCDEC
18930 | RELOAD_REG_PRE_MODIFY
);
18936 /* If the register isn't valid in this register class, just return now. */
18937 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
18939 if (TARGET_DEBUG_ADDR
)
18942 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18943 "not valid in class\n",
18944 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
18951 switch (GET_CODE (addr
))
18953 /* Does the register class supports auto update forms for this mode? We
18954 don't need a scratch register, since the powerpc only supports
18955 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18958 reg
= XEXP (addr
, 0);
18959 if (!base_reg_operand (addr
, GET_MODE (reg
)))
18961 fail_msg
= "no base register #1";
18965 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
18973 reg
= XEXP (addr
, 0);
18974 plus_arg1
= XEXP (addr
, 1);
18975 if (!base_reg_operand (reg
, GET_MODE (reg
))
18976 || GET_CODE (plus_arg1
) != PLUS
18977 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
18979 fail_msg
= "bad PRE_MODIFY";
18983 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
18990 /* Do we need to simulate AND -16 to clear the bottom address bits used
18991 in VMX load/stores? Only allow the AND for vector sizes. */
18993 and_arg
= XEXP (addr
, 0);
18994 if (GET_MODE_SIZE (mode
) != 16
18995 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
18996 || INTVAL (XEXP (addr
, 1)) != -16)
18998 fail_msg
= "bad Altivec AND #1";
19002 if (rclass
!= ALTIVEC_REGS
)
19004 if (legitimate_indirect_address_p (and_arg
, false))
19007 else if (legitimate_indexed_address_p (and_arg
, false))
19012 fail_msg
= "bad Altivec AND #2";
19020 /* If this is an indirect address, make sure it is a base register. */
19023 if (!legitimate_indirect_address_p (addr
, false))
19030 /* If this is an indexed address, make sure the register class can handle
19031 indexed addresses for this mode. */
19033 plus_arg0
= XEXP (addr
, 0);
19034 plus_arg1
= XEXP (addr
, 1);
19036 /* (plus (plus (reg) (constant)) (constant)) is generated during
19037 push_reload processing, so handle it now. */
19038 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
19040 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19047 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19048 push_reload processing, so handle it now. */
19049 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
19051 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19054 type
= "indexed #2";
19058 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
19060 fail_msg
= "no base register #2";
19064 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
19066 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
19067 || !legitimate_indexed_address_p (addr
, false))
19074 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0
19075 && CONST_INT_P (plus_arg1
))
19077 if (!quad_address_offset_p (INTVAL (plus_arg1
)))
19080 type
= "vector d-form offset";
19084 /* Make sure the register class can handle offset addresses. */
19085 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
19087 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19090 type
= "offset #2";
19096 fail_msg
= "bad PLUS";
19103 /* Quad offsets are restricted and can't handle normal addresses. */
19104 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19107 type
= "vector d-form lo_sum";
19110 else if (!legitimate_lo_sum_address_p (mode
, addr
, false))
19112 fail_msg
= "bad LO_SUM";
19116 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19123 /* Static addresses need to create a TOC entry. */
19127 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19130 type
= "vector d-form lo_sum #2";
19136 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
19140 /* TOC references look like offsetable memory. */
19142 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
19144 fail_msg
= "bad UNSPEC";
19148 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19151 type
= "vector d-form lo_sum #3";
19154 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19157 type
= "toc reference";
19163 fail_msg
= "bad address";
19168 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
19170 if (extra_cost
< 0)
19172 "rs6000_secondary_reload_memory error: mode = %s, "
19173 "class = %s, addr_mask = '%s', %s\n",
19174 GET_MODE_NAME (mode
),
19175 reg_class_names
[rclass
],
19176 rs6000_debug_addr_mask (addr_mask
, false),
19177 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
19181 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19182 "addr_mask = '%s', extra cost = %d, %s\n",
19183 GET_MODE_NAME (mode
),
19184 reg_class_names
[rclass
],
19185 rs6000_debug_addr_mask (addr_mask
, false),
19187 (type
) ? type
: "<none>");
19195 /* Helper function for rs6000_secondary_reload to return true if a move to a
19196 different register classe is really a simple move. */
19199 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
19200 enum rs6000_reg_type from_type
,
19203 int size
= GET_MODE_SIZE (mode
);
19205 /* Add support for various direct moves available. In this function, we only
19206 look at cases where we don't need any extra registers, and one or more
19207 simple move insns are issued. Originally small integers are not allowed
19208 in FPR/VSX registers. Single precision binary floating is not a simple
19209 move because we need to convert to the single precision memory layout.
19210 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19211 need special direct move handling, which we do not support yet. */
19212 if (TARGET_DIRECT_MOVE
19213 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19214 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19216 if (TARGET_POWERPC64
)
19218 /* ISA 2.07: MTVSRD or MVFVSRD. */
19222 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19223 if (size
== 16 && TARGET_P9_VECTOR
&& mode
!= TDmode
)
19227 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19228 if (TARGET_P8_VECTOR
)
19230 if (mode
== SImode
)
19233 if (TARGET_P9_VECTOR
&& (mode
== HImode
|| mode
== QImode
))
19237 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19238 if (mode
== SDmode
)
19242 /* Power6+: MFTGPR or MFFGPR. */
19243 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
19244 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
19245 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19248 /* Move to/from SPR. */
19249 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
19250 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
19251 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19257 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19258 special direct moves that involve allocating an extra register, return the
19259 insn code of the helper function if there is such a function or
19260 CODE_FOR_nothing if not. */
19263 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
19264 enum rs6000_reg_type from_type
,
19266 secondary_reload_info
*sri
,
19270 enum insn_code icode
= CODE_FOR_nothing
;
19272 int size
= GET_MODE_SIZE (mode
);
19274 if (TARGET_POWERPC64
&& size
== 16)
19276 /* Handle moving 128-bit values from GPRs to VSX point registers on
19277 ISA 2.07 (power8, power9) when running in 64-bit mode using
19278 XXPERMDI to glue the two 64-bit values back together. */
19279 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19281 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
19282 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19285 /* Handle moving 128-bit values from VSX point registers to GPRs on
19286 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19287 bottom 64-bit value. */
19288 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19290 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
19291 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19295 else if (TARGET_POWERPC64
&& mode
== SFmode
)
19297 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19299 cost
= 3; /* xscvdpspn, mfvsrd, and. */
19300 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19303 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19305 cost
= 2; /* mtvsrz, xscvspdpn. */
19306 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19310 else if (!TARGET_POWERPC64
&& size
== 8)
19312 /* Handle moving 64-bit values from GPRs to floating point registers on
19313 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19314 32-bit values back together. Altivec register classes must be handled
19315 specially since a different instruction is used, and the secondary
19316 reload support requires a single instruction class in the scratch
19317 register constraint. However, right now TFmode is not allowed in
19318 Altivec registers, so the pattern will never match. */
19319 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
19321 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
19322 icode
= reg_addr
[mode
].reload_fpr_gpr
;
19326 if (icode
!= CODE_FOR_nothing
)
19331 sri
->icode
= icode
;
19332 sri
->extra_cost
= cost
;
19339 /* Return whether a move between two register classes can be done either
19340 directly (simple move) or via a pattern that uses a single extra temporary
19341 (using ISA 2.07's direct move in this case. */
19344 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
19345 enum rs6000_reg_type from_type
,
19347 secondary_reload_info
*sri
,
19350 /* Fall back to load/store reloads if either type is not a register. */
19351 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
19354 /* If we haven't allocated registers yet, assume the move can be done for the
19355 standard register types. */
19356 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
19357 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
19358 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
19361 /* Moves to the same set of registers is a simple move for non-specialized
19363 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
19366 /* Check whether a simple move can be done directly. */
19367 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
19371 sri
->icode
= CODE_FOR_nothing
;
19372 sri
->extra_cost
= 0;
19377 /* Now check if we can do it in a few steps. */
19378 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
19382 /* Inform reload about cases where moving X with a mode MODE to a register in
19383 RCLASS requires an extra scratch or immediate register. Return the class
19384 needed for the immediate register.
19386 For VSX and Altivec, we may need a register to convert sp+offset into
19389 For misaligned 64-bit gpr loads and stores we need a register to
19390 convert an offset address to indirect. */
19393 rs6000_secondary_reload (bool in_p
,
19395 reg_class_t rclass_i
,
19397 secondary_reload_info
*sri
)
19399 enum reg_class rclass
= (enum reg_class
) rclass_i
;
19400 reg_class_t ret
= ALL_REGS
;
19401 enum insn_code icode
;
19402 bool default_p
= false;
19403 bool done_p
= false;
19405 /* Allow subreg of memory before/during reload. */
19406 bool memory_p
= (MEM_P (x
)
19407 || (!reload_completed
&& GET_CODE (x
) == SUBREG
19408 && MEM_P (SUBREG_REG (x
))));
19410 sri
->icode
= CODE_FOR_nothing
;
19411 sri
->t_icode
= CODE_FOR_nothing
;
19412 sri
->extra_cost
= 0;
19414 ? reg_addr
[mode
].reload_load
19415 : reg_addr
[mode
].reload_store
);
19417 if (REG_P (x
) || register_operand (x
, mode
))
19419 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
19420 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
19421 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
19424 std::swap (to_type
, from_type
);
19426 /* Can we do a direct move of some sort? */
19427 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
19430 icode
= (enum insn_code
)sri
->icode
;
19437 /* Make sure 0.0 is not reloaded or forced into memory. */
19438 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
19445 /* If this is a scalar floating point value and we want to load it into the
19446 traditional Altivec registers, do it via a move via a traditional floating
19447 point register, unless we have D-form addressing. Also make sure that
19448 non-zero constants use a FPR. */
19449 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
19450 && !mode_supports_vmx_dform (mode
)
19451 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
19452 && (memory_p
|| (GET_CODE (x
) == CONST_DOUBLE
)))
19459 /* Handle reload of load/stores if we have reload helper functions. */
19460 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
19462 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
19465 if (extra_cost
>= 0)
19469 if (extra_cost
> 0)
19471 sri
->extra_cost
= extra_cost
;
19472 sri
->icode
= icode
;
19477 /* Handle unaligned loads and stores of integer registers. */
19478 if (!done_p
&& TARGET_POWERPC64
19479 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19481 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
19483 rtx addr
= XEXP (x
, 0);
19484 rtx off
= address_offset (addr
);
19486 if (off
!= NULL_RTX
)
19488 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19489 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19491 /* We need a secondary reload when our legitimate_address_p
19492 says the address is good (as otherwise the entire address
19493 will be reloaded), and the offset is not a multiple of
19494 four or we have an address wrap. Address wrap will only
19495 occur for LO_SUMs since legitimate_offset_address_p
19496 rejects addresses for 16-byte mems that will wrap. */
19497 if (GET_CODE (addr
) == LO_SUM
19498 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19499 && ((offset
& 3) != 0
19500 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
19501 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
19502 && (offset
& 3) != 0))
19504 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19506 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
19507 : CODE_FOR_reload_di_load
);
19509 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
19510 : CODE_FOR_reload_di_store
);
19511 sri
->extra_cost
= 2;
19522 if (!done_p
&& !TARGET_POWERPC64
19523 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19525 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
19527 rtx addr
= XEXP (x
, 0);
19528 rtx off
= address_offset (addr
);
19530 if (off
!= NULL_RTX
)
19532 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19533 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19535 /* We need a secondary reload when our legitimate_address_p
19536 says the address is good (as otherwise the entire address
19537 will be reloaded), and we have a wrap.
19539 legitimate_lo_sum_address_p allows LO_SUM addresses to
19540 have any offset so test for wrap in the low 16 bits.
19542 legitimate_offset_address_p checks for the range
19543 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19544 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19545 [0x7ff4,0x7fff] respectively, so test for the
19546 intersection of these ranges, [0x7ffc,0x7fff] and
19547 [0x7ff4,0x7ff7] respectively.
19549 Note that the address we see here may have been
19550 manipulated by legitimize_reload_address. */
19551 if (GET_CODE (addr
) == LO_SUM
19552 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
19553 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
19556 sri
->icode
= CODE_FOR_reload_si_load
;
19558 sri
->icode
= CODE_FOR_reload_si_store
;
19559 sri
->extra_cost
= 2;
19574 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
19576 gcc_assert (ret
!= ALL_REGS
);
19578 if (TARGET_DEBUG_ADDR
)
19581 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19583 reg_class_names
[ret
],
19584 in_p
? "true" : "false",
19585 reg_class_names
[rclass
],
19586 GET_MODE_NAME (mode
));
19588 if (reload_completed
)
19589 fputs (", after reload", stderr
);
19592 fputs (", done_p not set", stderr
);
19595 fputs (", default secondary reload", stderr
);
19597 if (sri
->icode
!= CODE_FOR_nothing
)
19598 fprintf (stderr
, ", reload func = %s, extra cost = %d",
19599 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
19601 else if (sri
->extra_cost
> 0)
19602 fprintf (stderr
, ", extra cost = %d", sri
->extra_cost
);
19604 fputs ("\n", stderr
);
19611 /* Better tracing for rs6000_secondary_reload_inner. */
19614 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
19619 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
19621 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
19622 store_p
? "store" : "load");
19625 set
= gen_rtx_SET (mem
, reg
);
19627 set
= gen_rtx_SET (reg
, mem
);
19629 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
19630 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
19633 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
19634 ATTRIBUTE_NORETURN
;
19637 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
19640 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
19641 gcc_unreachable ();
19644 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19645 reload helper functions. These were identified in
19646 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19647 reload, it calls the insns:
19648 reload_<RELOAD:mode>_<P:mptrsize>_store
19649 reload_<RELOAD:mode>_<P:mptrsize>_load
19651 which in turn calls this function, to do whatever is necessary to create
19652 valid addresses. */
19655 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
19657 int regno
= true_regnum (reg
);
19658 machine_mode mode
= GET_MODE (reg
);
19659 addr_mask_type addr_mask
;
19662 rtx op_reg
, op0
, op1
;
19667 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
|| !MEM_P (mem
)
19668 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
19669 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19671 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
19672 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
19674 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
19675 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
19677 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
19678 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
19681 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19683 /* Make sure the mode is valid in this register class. */
19684 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
19685 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19687 if (TARGET_DEBUG_ADDR
)
19688 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
19690 new_addr
= addr
= XEXP (mem
, 0);
19691 switch (GET_CODE (addr
))
19693 /* Does the register class support auto update forms for this mode? If
19694 not, do the update now. We don't need a scratch register, since the
19695 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19698 op_reg
= XEXP (addr
, 0);
19699 if (!base_reg_operand (op_reg
, Pmode
))
19700 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19702 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
19704 int delta
= GET_MODE_SIZE (mode
);
19705 if (GET_CODE (addr
) == PRE_DEC
)
19707 emit_insn (gen_add2_insn (op_reg
, GEN_INT (delta
)));
19713 op0
= XEXP (addr
, 0);
19714 op1
= XEXP (addr
, 1);
19715 if (!base_reg_operand (op0
, Pmode
)
19716 || GET_CODE (op1
) != PLUS
19717 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
19718 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19720 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
19722 emit_insn (gen_rtx_SET (op0
, op1
));
19727 /* Do we need to simulate AND -16 to clear the bottom address bits used
19728 in VMX load/stores? */
19730 op0
= XEXP (addr
, 0);
19731 op1
= XEXP (addr
, 1);
19732 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
19734 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
19737 else if (GET_CODE (op1
) == PLUS
)
19739 emit_insn (gen_rtx_SET (scratch
, op1
));
19744 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19746 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
19747 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
19748 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
19749 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
19750 new_addr
= scratch
;
19754 /* If this is an indirect address, make sure it is a base register. */
19757 if (!base_reg_operand (addr
, GET_MODE (addr
)))
19759 emit_insn (gen_rtx_SET (scratch
, addr
));
19760 new_addr
= scratch
;
19764 /* If this is an indexed address, make sure the register class can handle
19765 indexed addresses for this mode. */
19767 op0
= XEXP (addr
, 0);
19768 op1
= XEXP (addr
, 1);
19769 if (!base_reg_operand (op0
, Pmode
))
19770 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19772 else if (int_reg_operand (op1
, Pmode
))
19774 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19776 emit_insn (gen_rtx_SET (scratch
, addr
));
19777 new_addr
= scratch
;
19781 else if (mode_supports_dq_form (mode
) && CONST_INT_P (op1
))
19783 if (((addr_mask
& RELOAD_REG_QUAD_OFFSET
) == 0)
19784 || !quad_address_p (addr
, mode
, false))
19786 emit_insn (gen_rtx_SET (scratch
, addr
));
19787 new_addr
= scratch
;
19791 /* Make sure the register class can handle offset addresses. */
19792 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
19794 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19796 emit_insn (gen_rtx_SET (scratch
, addr
));
19797 new_addr
= scratch
;
19802 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19807 op0
= XEXP (addr
, 0);
19808 op1
= XEXP (addr
, 1);
19809 if (!base_reg_operand (op0
, Pmode
))
19810 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19812 else if (int_reg_operand (op1
, Pmode
))
19814 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19816 emit_insn (gen_rtx_SET (scratch
, addr
));
19817 new_addr
= scratch
;
19821 /* Quad offsets are restricted and can't handle normal addresses. */
19822 else if (mode_supports_dq_form (mode
))
19824 emit_insn (gen_rtx_SET (scratch
, addr
));
19825 new_addr
= scratch
;
19828 /* Make sure the register class can handle offset addresses. */
19829 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
19831 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19833 emit_insn (gen_rtx_SET (scratch
, addr
));
19834 new_addr
= scratch
;
19839 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19846 rs6000_emit_move (scratch
, addr
, Pmode
);
19847 new_addr
= scratch
;
19851 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19854 /* Adjust the address if it changed. */
19855 if (addr
!= new_addr
)
19857 mem
= replace_equiv_address_nv (mem
, new_addr
);
19858 if (TARGET_DEBUG_ADDR
)
19859 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19862 /* Now create the move. */
19864 emit_insn (gen_rtx_SET (mem
, reg
));
19866 emit_insn (gen_rtx_SET (reg
, mem
));
19871 /* Convert reloads involving 64-bit gprs and misaligned offset
19872 addressing, or multiple 32-bit gprs and offsets that are too large,
19873 to use indirect addressing. */
19876 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
19878 int regno
= true_regnum (reg
);
19879 enum reg_class rclass
;
19881 rtx scratch_or_premodify
= scratch
;
19883 if (TARGET_DEBUG_ADDR
)
19885 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
19886 store_p
? "store" : "load");
19887 fprintf (stderr
, "reg:\n");
19889 fprintf (stderr
, "mem:\n");
19891 fprintf (stderr
, "scratch:\n");
19892 debug_rtx (scratch
);
19895 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
19896 gcc_assert (GET_CODE (mem
) == MEM
);
19897 rclass
= REGNO_REG_CLASS (regno
);
19898 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
19899 addr
= XEXP (mem
, 0);
19901 if (GET_CODE (addr
) == PRE_MODIFY
)
19903 gcc_assert (REG_P (XEXP (addr
, 0))
19904 && GET_CODE (XEXP (addr
, 1)) == PLUS
19905 && XEXP (XEXP (addr
, 1), 0) == XEXP (addr
, 0));
19906 scratch_or_premodify
= XEXP (addr
, 0);
19907 addr
= XEXP (addr
, 1);
19909 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
19911 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
19913 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
19915 /* Now create the move. */
19917 emit_insn (gen_rtx_SET (mem
, reg
));
19919 emit_insn (gen_rtx_SET (reg
, mem
));
19924 /* Given an rtx X being reloaded into a reg required to be
19925 in class CLASS, return the class of reg to actually use.
19926 In general this is just CLASS; but on some machines
19927 in some cases it is preferable to use a more restrictive class.
19929 On the RS/6000, we have to return NO_REGS when we want to reload a
19930 floating-point CONST_DOUBLE to force it to be copied to memory.
19932 We also don't want to reload integer values into floating-point
19933 registers if we can at all help it. In fact, this can
19934 cause reload to die, if it tries to generate a reload of CTR
19935 into a FP register and discovers it doesn't have the memory location
19938 ??? Would it be a good idea to have reload do the converse, that is
19939 try to reload floating modes into FP registers if possible?
19942 static enum reg_class
19943 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
19945 machine_mode mode
= GET_MODE (x
);
19946 bool is_constant
= CONSTANT_P (x
);
19948 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19949 reload class for it. */
19950 if ((rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
19951 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
) == 0)
19954 if ((rclass
== FLOAT_REGS
|| rclass
== VSX_REGS
)
19955 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
] & RELOAD_REG_VALID
) == 0)
19958 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19959 the reloading of address expressions using PLUS into floating point
19961 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
19965 /* Zero is always allowed in all VSX registers. */
19966 if (x
== CONST0_RTX (mode
))
19969 /* If this is a vector constant that can be formed with a few Altivec
19970 instructions, we want altivec registers. */
19971 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
19972 return ALTIVEC_REGS
;
19974 /* If this is an integer constant that can easily be loaded into
19975 vector registers, allow it. */
19976 if (CONST_INT_P (x
))
19978 HOST_WIDE_INT value
= INTVAL (x
);
19980 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19981 2.06 can generate it in the Altivec registers with
19985 if (TARGET_P8_VECTOR
)
19987 else if (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
19988 return ALTIVEC_REGS
;
19993 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19994 a sign extend in the Altivec registers. */
19995 if (IN_RANGE (value
, -128, 127) && TARGET_P9_VECTOR
19996 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
))
19997 return ALTIVEC_REGS
;
20000 /* Force constant to memory. */
20004 /* D-form addressing can easily reload the value. */
20005 if (mode_supports_vmx_dform (mode
)
20006 || mode_supports_dq_form (mode
))
20009 /* If this is a scalar floating point value and we don't have D-form
20010 addressing, prefer the traditional floating point registers so that we
20011 can use D-form (register+offset) addressing. */
20012 if (rclass
== VSX_REGS
20013 && (mode
== SFmode
|| GET_MODE_SIZE (mode
) == 8))
20016 /* Prefer the Altivec registers if Altivec is handling the vector
20017 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20019 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
20020 || mode
== V1TImode
)
20021 return ALTIVEC_REGS
;
20026 if (is_constant
|| GET_CODE (x
) == PLUS
)
20028 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
20029 return GENERAL_REGS
;
20030 if (reg_class_subset_p (BASE_REGS
, rclass
))
20035 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
20036 return GENERAL_REGS
;
20041 /* Debug version of rs6000_preferred_reload_class. */
20042 static enum reg_class
20043 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
20045 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
20048 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20050 reg_class_names
[ret
], reg_class_names
[rclass
],
20051 GET_MODE_NAME (GET_MODE (x
)));
20057 /* If we are copying between FP or AltiVec registers and anything else, we need
20058 a memory location. The exception is when we are targeting ppc64 and the
20059 move to/from fpr to gpr instructions are available. Also, under VSX, you
20060 can copy vector registers from the FP register set to the Altivec register
20061 set and vice versa. */
20064 rs6000_secondary_memory_needed (machine_mode mode
,
20065 reg_class_t from_class
,
20066 reg_class_t to_class
)
20068 enum rs6000_reg_type from_type
, to_type
;
20069 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
20070 || (to_class
== ALTIVEC_REGS
));
20072 /* If a simple/direct move is available, we don't need secondary memory */
20073 from_type
= reg_class_to_reg_type
[(int)from_class
];
20074 to_type
= reg_class_to_reg_type
[(int)to_class
];
20076 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
20077 (secondary_reload_info
*)0, altivec_p
))
20080 /* If we have a floating point or vector register class, we need to use
20081 memory to transfer the data. */
20082 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
20088 /* Debug version of rs6000_secondary_memory_needed. */
20090 rs6000_debug_secondary_memory_needed (machine_mode mode
,
20091 reg_class_t from_class
,
20092 reg_class_t to_class
)
20094 bool ret
= rs6000_secondary_memory_needed (mode
, from_class
, to_class
);
20097 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20098 "to_class = %s, mode = %s\n",
20099 ret
? "true" : "false",
20100 reg_class_names
[from_class
],
20101 reg_class_names
[to_class
],
20102 GET_MODE_NAME (mode
));
20107 /* Return the register class of a scratch register needed to copy IN into
20108 or out of a register in RCLASS in MODE. If it can be done directly,
20109 NO_REGS is returned. */
20111 static enum reg_class
20112 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
20117 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
20119 && MACHOPIC_INDIRECT
20123 /* We cannot copy a symbolic operand directly into anything
20124 other than BASE_REGS for TARGET_ELF. So indicate that a
20125 register from BASE_REGS is needed as an intermediate
20128 On Darwin, pic addresses require a load from memory, which
20129 needs a base register. */
20130 if (rclass
!= BASE_REGS
20131 && (GET_CODE (in
) == SYMBOL_REF
20132 || GET_CODE (in
) == HIGH
20133 || GET_CODE (in
) == LABEL_REF
20134 || GET_CODE (in
) == CONST
))
20138 if (GET_CODE (in
) == REG
)
20140 regno
= REGNO (in
);
20141 if (regno
>= FIRST_PSEUDO_REGISTER
)
20143 regno
= true_regnum (in
);
20144 if (regno
>= FIRST_PSEUDO_REGISTER
)
20148 else if (GET_CODE (in
) == SUBREG
)
20150 regno
= true_regnum (in
);
20151 if (regno
>= FIRST_PSEUDO_REGISTER
)
20157 /* If we have VSX register moves, prefer moving scalar values between
20158 Altivec registers and GPR by going via an FPR (and then via memory)
20159 instead of reloading the secondary memory address for Altivec moves. */
20161 && GET_MODE_SIZE (mode
) < 16
20162 && !mode_supports_vmx_dform (mode
)
20163 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
20164 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
20165 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
20166 && (regno
>= 0 && INT_REGNO_P (regno
)))))
20169 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20171 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
20172 || (regno
>= 0 && INT_REGNO_P (regno
)))
20175 /* Constants, memory, and VSX registers can go into VSX registers (both the
20176 traditional floating point and the altivec registers). */
20177 if (rclass
== VSX_REGS
20178 && (regno
== -1 || VSX_REGNO_P (regno
)))
20181 /* Constants, memory, and FP registers can go into FP registers. */
20182 if ((regno
== -1 || FP_REGNO_P (regno
))
20183 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
20184 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
20186 /* Memory, and AltiVec registers can go into AltiVec registers. */
20187 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
20188 && rclass
== ALTIVEC_REGS
)
20191 /* We can copy among the CR registers. */
20192 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
20193 && regno
>= 0 && CR_REGNO_P (regno
))
20196 /* Otherwise, we need GENERAL_REGS. */
20197 return GENERAL_REGS
;
20200 /* Debug version of rs6000_secondary_reload_class. */
20201 static enum reg_class
20202 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
20203 machine_mode mode
, rtx in
)
20205 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
20207 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20208 "mode = %s, input rtx:\n",
20209 reg_class_names
[ret
], reg_class_names
[rclass
],
20210 GET_MODE_NAME (mode
));
20216 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20219 rs6000_can_change_mode_class (machine_mode from
,
20221 reg_class_t rclass
)
20223 unsigned from_size
= GET_MODE_SIZE (from
);
20224 unsigned to_size
= GET_MODE_SIZE (to
);
20226 if (from_size
!= to_size
)
20228 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
20230 if (reg_classes_intersect_p (xclass
, rclass
))
20232 unsigned to_nregs
= hard_regno_nregs (FIRST_FPR_REGNO
, to
);
20233 unsigned from_nregs
= hard_regno_nregs (FIRST_FPR_REGNO
, from
);
20234 bool to_float128_vector_p
= FLOAT128_VECTOR_P (to
);
20235 bool from_float128_vector_p
= FLOAT128_VECTOR_P (from
);
20237 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20238 single register under VSX because the scalar part of the register
20239 is in the upper 64-bits, and not the lower 64-bits. Types like
20240 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20241 IEEE floating point can't overlap, and neither can small
20244 if (to_float128_vector_p
&& from_float128_vector_p
)
20247 else if (to_float128_vector_p
|| from_float128_vector_p
)
20250 /* TDmode in floating-mode registers must always go into a register
20251 pair with the most significant word in the even-numbered register
20252 to match ISA requirements. In little-endian mode, this does not
20253 match subreg numbering, so we cannot allow subregs. */
20254 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
20257 if (from_size
< 8 || to_size
< 8)
20260 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
20263 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
20272 /* Since the VSX register set includes traditional floating point registers
20273 and altivec registers, just check for the size being different instead of
20274 trying to check whether the modes are vector modes. Otherwise it won't
20275 allow say DF and DI to change classes. For types like TFmode and TDmode
20276 that take 2 64-bit registers, rather than a single 128-bit register, don't
20277 allow subregs of those types to other 128 bit types. */
20278 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
20280 unsigned num_regs
= (from_size
+ 15) / 16;
20281 if (hard_regno_nregs (FIRST_FPR_REGNO
, to
) > num_regs
20282 || hard_regno_nregs (FIRST_FPR_REGNO
, from
) > num_regs
)
20285 return (from_size
== 8 || from_size
== 16);
20288 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
20289 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
20295 /* Debug version of rs6000_can_change_mode_class. */
20297 rs6000_debug_can_change_mode_class (machine_mode from
,
20299 reg_class_t rclass
)
20301 bool ret
= rs6000_can_change_mode_class (from
, to
, rclass
);
20304 "rs6000_can_change_mode_class, return %s, from = %s, "
20305 "to = %s, rclass = %s\n",
20306 ret
? "true" : "false",
20307 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
20308 reg_class_names
[rclass
]);
20313 /* Return a string to do a move operation of 128 bits of data. */
20316 rs6000_output_move_128bit (rtx operands
[])
20318 rtx dest
= operands
[0];
20319 rtx src
= operands
[1];
20320 machine_mode mode
= GET_MODE (dest
);
20323 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
20324 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
20328 dest_regno
= REGNO (dest
);
20329 dest_gpr_p
= INT_REGNO_P (dest_regno
);
20330 dest_fp_p
= FP_REGNO_P (dest_regno
);
20331 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
20332 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
20337 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
20342 src_regno
= REGNO (src
);
20343 src_gpr_p
= INT_REGNO_P (src_regno
);
20344 src_fp_p
= FP_REGNO_P (src_regno
);
20345 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
20346 src_vsx_p
= src_fp_p
| src_vmx_p
;
20351 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
20354 /* Register moves. */
20355 if (dest_regno
>= 0 && src_regno
>= 0)
20362 if (TARGET_DIRECT_MOVE_128
&& src_vsx_p
)
20363 return (WORDS_BIG_ENDIAN
20364 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20365 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20367 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
20371 else if (TARGET_VSX
&& dest_vsx_p
)
20374 return "xxlor %x0,%x1,%x1";
20376 else if (TARGET_DIRECT_MOVE_128
&& src_gpr_p
)
20377 return (WORDS_BIG_ENDIAN
20378 ? "mtvsrdd %x0,%1,%L1"
20379 : "mtvsrdd %x0,%L1,%1");
20381 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
20385 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
20386 return "vor %0,%1,%1";
20388 else if (dest_fp_p
&& src_fp_p
)
20393 else if (dest_regno
>= 0 && MEM_P (src
))
20397 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20403 else if (TARGET_ALTIVEC
&& dest_vmx_p
20404 && altivec_indexed_or_indirect_operand (src
, mode
))
20405 return "lvx %0,%y1";
20407 else if (TARGET_VSX
&& dest_vsx_p
)
20409 if (mode_supports_dq_form (mode
)
20410 && quad_address_p (XEXP (src
, 0), mode
, true))
20411 return "lxv %x0,%1";
20413 else if (TARGET_P9_VECTOR
)
20414 return "lxvx %x0,%y1";
20416 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20417 return "lxvw4x %x0,%y1";
20420 return "lxvd2x %x0,%y1";
20423 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
20424 return "lvx %0,%y1";
20426 else if (dest_fp_p
)
20431 else if (src_regno
>= 0 && MEM_P (dest
))
20435 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20436 return "stq %1,%0";
20441 else if (TARGET_ALTIVEC
&& src_vmx_p
20442 && altivec_indexed_or_indirect_operand (dest
, mode
))
20443 return "stvx %1,%y0";
20445 else if (TARGET_VSX
&& src_vsx_p
)
20447 if (mode_supports_dq_form (mode
)
20448 && quad_address_p (XEXP (dest
, 0), mode
, true))
20449 return "stxv %x1,%0";
20451 else if (TARGET_P9_VECTOR
)
20452 return "stxvx %x1,%y0";
20454 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20455 return "stxvw4x %x1,%y0";
20458 return "stxvd2x %x1,%y0";
20461 else if (TARGET_ALTIVEC
&& src_vmx_p
)
20462 return "stvx %1,%y0";
20469 else if (dest_regno
>= 0
20470 && (GET_CODE (src
) == CONST_INT
20471 || GET_CODE (src
) == CONST_WIDE_INT
20472 || GET_CODE (src
) == CONST_DOUBLE
20473 || GET_CODE (src
) == CONST_VECTOR
))
20478 else if ((dest_vmx_p
&& TARGET_ALTIVEC
)
20479 || (dest_vsx_p
&& TARGET_VSX
))
20480 return output_vec_const_move (operands
);
20483 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest
, src
));
20486 /* Validate a 128-bit move. */
20488 rs6000_move_128bit_ok_p (rtx operands
[])
20490 machine_mode mode
= GET_MODE (operands
[0]);
20491 return (gpc_reg_operand (operands
[0], mode
)
20492 || gpc_reg_operand (operands
[1], mode
));
20495 /* Return true if a 128-bit move needs to be split. */
20497 rs6000_split_128bit_ok_p (rtx operands
[])
20499 if (!reload_completed
)
20502 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
20505 if (quad_load_store_p (operands
[0], operands
[1]))
20512 /* Given a comparison operation, return the bit number in CCR to test. We
20513 know this is a valid comparison.
20515 SCC_P is 1 if this is for an scc. That means that %D will have been
20516 used instead of %C, so the bits will be in different places.
20518 Return -1 if OP isn't a valid comparison for some reason. */
20521 ccr_bit (rtx op
, int scc_p
)
20523 enum rtx_code code
= GET_CODE (op
);
20524 machine_mode cc_mode
;
20529 if (!COMPARISON_P (op
))
20532 reg
= XEXP (op
, 0);
20534 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
20536 cc_mode
= GET_MODE (reg
);
20537 cc_regnum
= REGNO (reg
);
20538 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
20540 validate_condition_mode (code
, cc_mode
);
20542 /* When generating a sCOND operation, only positive conditions are
20545 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
20546 || code
== GTU
|| code
== LTU
);
20551 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
20553 return base_bit
+ 2;
20554 case GT
: case GTU
: case UNLE
:
20555 return base_bit
+ 1;
20556 case LT
: case LTU
: case UNGE
:
20558 case ORDERED
: case UNORDERED
:
20559 return base_bit
+ 3;
20562 /* If scc, we will have done a cror to put the bit in the
20563 unordered position. So test that bit. For integer, this is ! LT
20564 unless this is an scc insn. */
20565 return scc_p
? base_bit
+ 3 : base_bit
;
20568 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
20571 gcc_unreachable ();
20575 /* Return the GOT register. */
20578 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
20580 /* The second flow pass currently (June 1999) can't update
20581 regs_ever_live without disturbing other parts of the compiler, so
20582 update it here to make the prolog/epilogue code happy. */
20583 if (!can_create_pseudo_p ()
20584 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
20585 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
20587 crtl
->uses_pic_offset_table
= 1;
20589 return pic_offset_table_rtx
;
20592 static rs6000_stack_t stack_info
;
20594 /* Function to init struct machine_function.
20595 This will be called, via a pointer variable,
20596 from push_function_context. */
20598 static struct machine_function
*
20599 rs6000_init_machine_status (void)
20601 stack_info
.reload_completed
= 0;
20602 return ggc_cleared_alloc
<machine_function
> ();
20605 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
20607 /* Write out a function code label. */
20610 rs6000_output_function_entry (FILE *file
, const char *fname
)
20612 if (fname
[0] != '.')
20614 switch (DEFAULT_ABI
)
20617 gcc_unreachable ();
20623 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
20633 RS6000_OUTPUT_BASENAME (file
, fname
);
20636 /* Print an operand. Recognize special options, documented below. */
20639 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20640 only introduced by the linker, when applying the sda21
20642 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20643 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20645 #define SMALL_DATA_RELOC "sda21"
20646 #define SMALL_DATA_REG 0
20650 print_operand (FILE *file
, rtx x
, int code
)
20653 unsigned HOST_WIDE_INT uval
;
20657 /* %a is output_address. */
20659 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20663 /* Like 'J' but get to the GT bit only. */
20664 gcc_assert (REG_P (x
));
20666 /* Bit 1 is GT bit. */
20667 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
20669 /* Add one for shift count in rlinm for scc. */
20670 fprintf (file
, "%d", i
+ 1);
20674 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20677 output_operand_lossage ("invalid %%e value");
20682 if ((uval
& 0xffff) == 0 && uval
!= 0)
20687 /* X is a CR register. Print the number of the EQ bit of the CR */
20688 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20689 output_operand_lossage ("invalid %%E value");
20691 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
20695 /* X is a CR register. Print the shift count needed to move it
20696 to the high-order four bits. */
20697 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20698 output_operand_lossage ("invalid %%f value");
20700 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
20704 /* Similar, but print the count for the rotate in the opposite
20706 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20707 output_operand_lossage ("invalid %%F value");
20709 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
20713 /* X is a constant integer. If it is negative, print "m",
20714 otherwise print "z". This is to make an aze or ame insn. */
20715 if (GET_CODE (x
) != CONST_INT
)
20716 output_operand_lossage ("invalid %%G value");
20717 else if (INTVAL (x
) >= 0)
20724 /* If constant, output low-order five bits. Otherwise, write
20727 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
20729 print_operand (file
, x
, 0);
20733 /* If constant, output low-order six bits. Otherwise, write
20736 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
20738 print_operand (file
, x
, 0);
20742 /* Print `i' if this is a constant, else nothing. */
20748 /* Write the bit number in CCR for jump. */
20749 i
= ccr_bit (x
, 0);
20751 output_operand_lossage ("invalid %%j code");
20753 fprintf (file
, "%d", i
);
20757 /* Similar, but add one for shift count in rlinm for scc and pass
20758 scc flag to `ccr_bit'. */
20759 i
= ccr_bit (x
, 1);
20761 output_operand_lossage ("invalid %%J code");
20763 /* If we want bit 31, write a shift count of zero, not 32. */
20764 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
20768 /* X must be a constant. Write the 1's complement of the
20771 output_operand_lossage ("invalid %%k value");
20773 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
20777 /* X must be a symbolic constant on ELF. Write an
20778 expression suitable for an 'addi' that adds in the low 16
20779 bits of the MEM. */
20780 if (GET_CODE (x
) == CONST
)
20782 if (GET_CODE (XEXP (x
, 0)) != PLUS
20783 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
20784 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
20785 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
20786 output_operand_lossage ("invalid %%K value");
20788 print_operand_address (file
, x
);
20789 fputs ("@l", file
);
20792 /* %l is output_asm_label. */
20795 /* Write second word of DImode or DFmode reference. Works on register
20796 or non-indexed memory only. */
20798 fputs (reg_names
[REGNO (x
) + 1], file
);
20799 else if (MEM_P (x
))
20801 machine_mode mode
= GET_MODE (x
);
20802 /* Handle possible auto-increment. Since it is pre-increment and
20803 we have already done it, we can just use an offset of word. */
20804 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
20805 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
20806 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
20808 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
20809 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
20812 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
,
20816 if (small_data_operand (x
, GET_MODE (x
)))
20817 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
20818 reg_names
[SMALL_DATA_REG
]);
20822 case 'N': /* Unused */
20823 /* Write the number of elements in the vector times 4. */
20824 if (GET_CODE (x
) != PARALLEL
)
20825 output_operand_lossage ("invalid %%N value");
20827 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
20830 case 'O': /* Unused */
20831 /* Similar, but subtract 1 first. */
20832 if (GET_CODE (x
) != PARALLEL
)
20833 output_operand_lossage ("invalid %%O value");
20835 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
20839 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20842 || (i
= exact_log2 (INTVAL (x
))) < 0)
20843 output_operand_lossage ("invalid %%p value");
20845 fprintf (file
, "%d", i
);
20849 /* The operand must be an indirect memory reference. The result
20850 is the register name. */
20851 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
20852 || REGNO (XEXP (x
, 0)) >= 32)
20853 output_operand_lossage ("invalid %%P value");
20855 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
20859 /* This outputs the logical code corresponding to a boolean
20860 expression. The expression may have one or both operands
20861 negated (if one, only the first one). For condition register
20862 logical operations, it will also treat the negated
20863 CR codes as NOTs, but not handle NOTs of them. */
20865 const char *const *t
= 0;
20867 enum rtx_code code
= GET_CODE (x
);
20868 static const char * const tbl
[3][3] = {
20869 { "and", "andc", "nor" },
20870 { "or", "orc", "nand" },
20871 { "xor", "eqv", "xor" } };
20875 else if (code
== IOR
)
20877 else if (code
== XOR
)
20880 output_operand_lossage ("invalid %%q value");
20882 if (GET_CODE (XEXP (x
, 0)) != NOT
)
20886 if (GET_CODE (XEXP (x
, 1)) == NOT
)
20897 if (! TARGET_MFCRF
)
20903 /* X is a CR register. Print the mask for `mtcrf'. */
20904 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
20905 output_operand_lossage ("invalid %%R value");
20907 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
20911 /* Low 5 bits of 32 - value */
20913 output_operand_lossage ("invalid %%s value");
20915 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
20919 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20920 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
20922 /* Bit 3 is OV bit. */
20923 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
20925 /* If we want bit 31, write a shift count of zero, not 32. */
20926 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
20930 /* Print the symbolic name of a branch target register. */
20931 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
20932 && REGNO (x
) != CTR_REGNO
))
20933 output_operand_lossage ("invalid %%T value");
20934 else if (REGNO (x
) == LR_REGNO
)
20935 fputs ("lr", file
);
20937 fputs ("ctr", file
);
20941 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20942 for use in unsigned operand. */
20945 output_operand_lossage ("invalid %%u value");
20950 if ((uval
& 0xffff) == 0)
20953 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
20957 /* High-order 16 bits of constant for use in signed operand. */
20959 output_operand_lossage ("invalid %%v value");
20961 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
20962 (INTVAL (x
) >> 16) & 0xffff);
20966 /* Print `u' if this has an auto-increment or auto-decrement. */
20968 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
20969 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
20970 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
20975 /* Print the trap code for this operand. */
20976 switch (GET_CODE (x
))
20979 fputs ("eq", file
); /* 4 */
20982 fputs ("ne", file
); /* 24 */
20985 fputs ("lt", file
); /* 16 */
20988 fputs ("le", file
); /* 20 */
20991 fputs ("gt", file
); /* 8 */
20994 fputs ("ge", file
); /* 12 */
20997 fputs ("llt", file
); /* 2 */
21000 fputs ("lle", file
); /* 6 */
21003 fputs ("lgt", file
); /* 1 */
21006 fputs ("lge", file
); /* 5 */
21009 gcc_unreachable ();
21014 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21017 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
21018 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
21020 print_operand (file
, x
, 0);
21024 /* X is a FPR or Altivec register used in a VSX context. */
21025 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
21026 output_operand_lossage ("invalid %%x value");
21029 int reg
= REGNO (x
);
21030 int vsx_reg
= (FP_REGNO_P (reg
)
21032 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
21034 #ifdef TARGET_REGNAMES
21035 if (TARGET_REGNAMES
)
21036 fprintf (file
, "%%vs%d", vsx_reg
);
21039 fprintf (file
, "%d", vsx_reg
);
21045 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
21046 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
21047 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
21052 /* Like 'L', for third word of TImode/PTImode */
21054 fputs (reg_names
[REGNO (x
) + 2], file
);
21055 else if (MEM_P (x
))
21057 machine_mode mode
= GET_MODE (x
);
21058 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21059 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21060 output_address (mode
, plus_constant (Pmode
,
21061 XEXP (XEXP (x
, 0), 0), 8));
21062 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21063 output_address (mode
, plus_constant (Pmode
,
21064 XEXP (XEXP (x
, 0), 0), 8));
21066 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 8), 0));
21067 if (small_data_operand (x
, GET_MODE (x
)))
21068 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21069 reg_names
[SMALL_DATA_REG
]);
21074 /* X is a SYMBOL_REF. Write out the name preceded by a
21075 period and without any trailing data in brackets. Used for function
21076 names. If we are configured for System V (or the embedded ABI) on
21077 the PowerPC, do not emit the period, since those systems do not use
21078 TOCs and the like. */
21079 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
21081 /* For macho, check to see if we need a stub. */
21084 const char *name
= XSTR (x
, 0);
21086 if (darwin_emit_branch_islands
21087 && MACHOPIC_INDIRECT
21088 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
21089 name
= machopic_indirection_name (x
, /*stub_p=*/true);
21091 assemble_name (file
, name
);
21093 else if (!DOT_SYMBOLS
)
21094 assemble_name (file
, XSTR (x
, 0));
21096 rs6000_output_function_entry (file
, XSTR (x
, 0));
21100 /* Like 'L', for last word of TImode/PTImode. */
21102 fputs (reg_names
[REGNO (x
) + 3], file
);
21103 else if (MEM_P (x
))
21105 machine_mode mode
= GET_MODE (x
);
21106 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21107 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21108 output_address (mode
, plus_constant (Pmode
,
21109 XEXP (XEXP (x
, 0), 0), 12));
21110 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21111 output_address (mode
, plus_constant (Pmode
,
21112 XEXP (XEXP (x
, 0), 0), 12));
21114 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 12), 0));
21115 if (small_data_operand (x
, GET_MODE (x
)))
21116 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21117 reg_names
[SMALL_DATA_REG
]);
21121 /* Print AltiVec memory operand. */
21126 gcc_assert (MEM_P (x
));
21130 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x
))
21131 && GET_CODE (tmp
) == AND
21132 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
21133 && INTVAL (XEXP (tmp
, 1)) == -16)
21134 tmp
= XEXP (tmp
, 0);
21135 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
21136 && GET_CODE (tmp
) == PRE_MODIFY
)
21137 tmp
= XEXP (tmp
, 1);
21139 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
21142 if (GET_CODE (tmp
) != PLUS
21143 || !REG_P (XEXP (tmp
, 0))
21144 || !REG_P (XEXP (tmp
, 1)))
21146 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21150 if (REGNO (XEXP (tmp
, 0)) == 0)
21151 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
21152 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
21154 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
21155 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
21162 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
21163 else if (MEM_P (x
))
21165 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21166 know the width from the mode. */
21167 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
21168 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
21169 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21170 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21171 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
21172 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21173 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21174 output_address (GET_MODE (x
), XEXP (XEXP (x
, 0), 1));
21176 output_address (GET_MODE (x
), XEXP (x
, 0));
21180 if (toc_relative_expr_p (x
, false, &tocrel_base_oac
, &tocrel_offset_oac
))
21181 /* This hack along with a corresponding hack in
21182 rs6000_output_addr_const_extra arranges to output addends
21183 where the assembler expects to find them. eg.
21184 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21185 without this hack would be output as "x@toc+4". We
21187 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21189 output_addr_const (file
, x
);
21194 if (const char *name
= get_some_local_dynamic_name ())
21195 assemble_name (file
, name
);
21197 output_operand_lossage ("'%%&' used without any "
21198 "local dynamic TLS references");
21202 output_operand_lossage ("invalid %%xn code");
21206 /* Print the address of an operand. */
21209 print_operand_address (FILE *file
, rtx x
)
21212 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
21213 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
21214 || GET_CODE (x
) == LABEL_REF
)
21216 output_addr_const (file
, x
);
21217 if (small_data_operand (x
, GET_MODE (x
)))
21218 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21219 reg_names
[SMALL_DATA_REG
]);
21221 gcc_assert (!TARGET_TOC
);
21223 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21224 && REG_P (XEXP (x
, 1)))
21226 if (REGNO (XEXP (x
, 0)) == 0)
21227 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
21228 reg_names
[ REGNO (XEXP (x
, 0)) ]);
21230 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
21231 reg_names
[ REGNO (XEXP (x
, 1)) ]);
21233 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21234 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
21235 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
21236 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
21238 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21239 && CONSTANT_P (XEXP (x
, 1)))
21241 fprintf (file
, "lo16(");
21242 output_addr_const (file
, XEXP (x
, 1));
21243 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21247 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21248 && CONSTANT_P (XEXP (x
, 1)))
21250 output_addr_const (file
, XEXP (x
, 1));
21251 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21254 else if (toc_relative_expr_p (x
, false, &tocrel_base_oac
, &tocrel_offset_oac
))
21256 /* This hack along with a corresponding hack in
21257 rs6000_output_addr_const_extra arranges to output addends
21258 where the assembler expects to find them. eg.
21260 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21261 without this hack would be output as "x@toc+8@l(9)". We
21262 want "x+8@toc@l(9)". */
21263 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21264 if (GET_CODE (x
) == LO_SUM
)
21265 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
21267 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base_oac
, 0, 1))]);
21270 output_addr_const (file
, x
);
21273 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21276 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
21278 if (GET_CODE (x
) == UNSPEC
)
21279 switch (XINT (x
, 1))
21281 case UNSPEC_TOCREL
:
21282 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
21283 && REG_P (XVECEXP (x
, 0, 1))
21284 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
21285 output_addr_const (file
, XVECEXP (x
, 0, 0));
21286 if (x
== tocrel_base_oac
&& tocrel_offset_oac
!= const0_rtx
)
21288 if (INTVAL (tocrel_offset_oac
) >= 0)
21289 fprintf (file
, "+");
21290 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset_oac
));
21292 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
21295 assemble_name (file
, toc_label_name
);
21298 else if (TARGET_ELF
)
21299 fputs ("@toc", file
);
21303 case UNSPEC_MACHOPIC_OFFSET
:
21304 output_addr_const (file
, XVECEXP (x
, 0, 0));
21306 machopic_output_function_base_name (file
);
21313 /* Target hook for assembling integer objects. The PowerPC version has
21314 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21315 is defined. It also needs to handle DI-mode objects on 64-bit
21319 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
21321 #ifdef RELOCATABLE_NEEDS_FIXUP
21322 /* Special handling for SI values. */
21323 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
21325 static int recurse
= 0;
21327 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21328 the .fixup section. Since the TOC section is already relocated, we
21329 don't need to mark it here. We used to skip the text section, but it
21330 should never be valid for relocated addresses to be placed in the text
21332 if (DEFAULT_ABI
== ABI_V4
21333 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
21334 && in_section
!= toc_section
21336 && !CONST_SCALAR_INT_P (x
)
21342 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
21344 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
21345 fprintf (asm_out_file
, "\t.long\t(");
21346 output_addr_const (asm_out_file
, x
);
21347 fprintf (asm_out_file
, ")@fixup\n");
21348 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
21349 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
21350 fprintf (asm_out_file
, "\t.long\t");
21351 assemble_name (asm_out_file
, buf
);
21352 fprintf (asm_out_file
, "\n\t.previous\n");
21356 /* Remove initial .'s to turn a -mcall-aixdesc function
21357 address into the address of the descriptor, not the function
21359 else if (GET_CODE (x
) == SYMBOL_REF
21360 && XSTR (x
, 0)[0] == '.'
21361 && DEFAULT_ABI
== ABI_AIX
)
21363 const char *name
= XSTR (x
, 0);
21364 while (*name
== '.')
21367 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
21371 #endif /* RELOCATABLE_NEEDS_FIXUP */
21372 return default_assemble_integer (x
, size
, aligned_p
);
21375 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21376 /* Emit an assembler directive to set symbol visibility for DECL to
21377 VISIBILITY_TYPE. */
21380 rs6000_assemble_visibility (tree decl
, int vis
)
21385 /* Functions need to have their entry point symbol visibility set as
21386 well as their descriptor symbol visibility. */
21387 if (DEFAULT_ABI
== ABI_AIX
21389 && TREE_CODE (decl
) == FUNCTION_DECL
)
21391 static const char * const visibility_types
[] = {
21392 NULL
, "protected", "hidden", "internal"
21395 const char *name
, *type
;
21397 name
= ((* targetm
.strip_name_encoding
)
21398 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
21399 type
= visibility_types
[vis
];
21401 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
21402 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
21405 default_assemble_visibility (decl
, vis
);
21410 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
21412 /* Reversal of FP compares takes care -- an ordered compare
21413 becomes an unordered compare and vice versa. */
21414 if (mode
== CCFPmode
21415 && (!flag_finite_math_only
21416 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
21417 || code
== UNEQ
|| code
== LTGT
))
21418 return reverse_condition_maybe_unordered (code
);
21420 return reverse_condition (code
);
21423 /* Generate a compare for CODE. Return a brand-new rtx that
21424 represents the result of the compare. */
21427 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
21429 machine_mode comp_mode
;
21430 rtx compare_result
;
21431 enum rtx_code code
= GET_CODE (cmp
);
21432 rtx op0
= XEXP (cmp
, 0);
21433 rtx op1
= XEXP (cmp
, 1);
21435 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
21436 comp_mode
= CCmode
;
21437 else if (FLOAT_MODE_P (mode
))
21438 comp_mode
= CCFPmode
;
21439 else if (code
== GTU
|| code
== LTU
21440 || code
== GEU
|| code
== LEU
)
21441 comp_mode
= CCUNSmode
;
21442 else if ((code
== EQ
|| code
== NE
)
21443 && unsigned_reg_p (op0
)
21444 && (unsigned_reg_p (op1
)
21445 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
21446 /* These are unsigned values, perhaps there will be a later
21447 ordering compare that can be shared with this one. */
21448 comp_mode
= CCUNSmode
;
21450 comp_mode
= CCmode
;
21452 /* If we have an unsigned compare, make sure we don't have a signed value as
21454 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
21455 && INTVAL (op1
) < 0)
21457 op0
= copy_rtx_if_shared (op0
);
21458 op1
= force_reg (GET_MODE (op0
), op1
);
21459 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
21462 /* First, the compare. */
21463 compare_result
= gen_reg_rtx (comp_mode
);
21465 /* IEEE 128-bit support in VSX registers when we do not have hardware
21467 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
21469 rtx libfunc
= NULL_RTX
;
21470 bool check_nan
= false;
21477 libfunc
= optab_libfunc (eq_optab
, mode
);
21482 libfunc
= optab_libfunc (ge_optab
, mode
);
21487 libfunc
= optab_libfunc (le_optab
, mode
);
21492 libfunc
= optab_libfunc (unord_optab
, mode
);
21493 code
= (code
== UNORDERED
) ? NE
: EQ
;
21499 libfunc
= optab_libfunc (ge_optab
, mode
);
21500 code
= (code
== UNGE
) ? GE
: GT
;
21506 libfunc
= optab_libfunc (le_optab
, mode
);
21507 code
= (code
== UNLE
) ? LE
: LT
;
21513 libfunc
= optab_libfunc (eq_optab
, mode
);
21514 code
= (code
= UNEQ
) ? EQ
: NE
;
21518 gcc_unreachable ();
21521 gcc_assert (libfunc
);
21524 dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
21525 SImode
, op0
, mode
, op1
, mode
);
21527 /* The library signals an exception for signalling NaNs, so we need to
21528 handle isgreater, etc. by first checking isordered. */
21531 rtx ne_rtx
, normal_dest
, unord_dest
;
21532 rtx unord_func
= optab_libfunc (unord_optab
, mode
);
21533 rtx join_label
= gen_label_rtx ();
21534 rtx join_ref
= gen_rtx_LABEL_REF (VOIDmode
, join_label
);
21535 rtx unord_cmp
= gen_reg_rtx (comp_mode
);
21538 /* Test for either value being a NaN. */
21539 gcc_assert (unord_func
);
21540 unord_dest
= emit_library_call_value (unord_func
, NULL_RTX
, LCT_CONST
,
21541 SImode
, op0
, mode
, op1
, mode
);
21543 /* Set value (0) if either value is a NaN, and jump to the join
21545 dest
= gen_reg_rtx (SImode
);
21546 emit_move_insn (dest
, const1_rtx
);
21547 emit_insn (gen_rtx_SET (unord_cmp
,
21548 gen_rtx_COMPARE (comp_mode
, unord_dest
,
21551 ne_rtx
= gen_rtx_NE (comp_mode
, unord_cmp
, const0_rtx
);
21552 emit_jump_insn (gen_rtx_SET (pc_rtx
,
21553 gen_rtx_IF_THEN_ELSE (VOIDmode
, ne_rtx
,
21557 /* Do the normal comparison, knowing that the values are not
21559 normal_dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
21560 SImode
, op0
, mode
, op1
, mode
);
21562 emit_insn (gen_cstoresi4 (dest
,
21563 gen_rtx_fmt_ee (code
, SImode
, normal_dest
,
21565 normal_dest
, const0_rtx
));
21567 /* Join NaN and non-Nan paths. Compare dest against 0. */
21568 emit_label (join_label
);
21572 emit_insn (gen_rtx_SET (compare_result
,
21573 gen_rtx_COMPARE (comp_mode
, dest
, const0_rtx
)));
21578 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21579 CLOBBERs to match cmptf_internal2 pattern. */
21580 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
21581 && FLOAT128_IBM_P (GET_MODE (op0
))
21582 && TARGET_HARD_FLOAT
)
21583 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
21585 gen_rtx_SET (compare_result
,
21586 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
21587 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21588 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21589 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21590 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21591 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21592 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21593 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21594 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
21595 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
21596 else if (GET_CODE (op1
) == UNSPEC
21597 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
21599 rtx op1b
= XVECEXP (op1
, 0, 0);
21600 comp_mode
= CCEQmode
;
21601 compare_result
= gen_reg_rtx (CCEQmode
);
21603 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
21605 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
21608 emit_insn (gen_rtx_SET (compare_result
,
21609 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
21612 /* Some kinds of FP comparisons need an OR operation;
21613 under flag_finite_math_only we don't bother. */
21614 if (FLOAT_MODE_P (mode
)
21615 && (!FLOAT128_IEEE_P (mode
) || TARGET_FLOAT128_HW
)
21616 && !flag_finite_math_only
21617 && (code
== LE
|| code
== GE
21618 || code
== UNEQ
|| code
== LTGT
21619 || code
== UNGT
|| code
== UNLT
))
21621 enum rtx_code or1
, or2
;
21622 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
21623 rtx or_result
= gen_reg_rtx (CCEQmode
);
21627 case LE
: or1
= LT
; or2
= EQ
; break;
21628 case GE
: or1
= GT
; or2
= EQ
; break;
21629 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
21630 case LTGT
: or1
= LT
; or2
= GT
; break;
21631 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
21632 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
21633 default: gcc_unreachable ();
21635 validate_condition_mode (or1
, comp_mode
);
21636 validate_condition_mode (or2
, comp_mode
);
21637 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
21638 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
21639 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
21640 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
21642 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
21644 compare_result
= or_result
;
21648 validate_condition_mode (code
, GET_MODE (compare_result
));
21650 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
21654 /* Return the diagnostic message string if the binary operation OP is
21655 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21658 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED
,
21662 machine_mode mode1
= TYPE_MODE (type1
);
21663 machine_mode mode2
= TYPE_MODE (type2
);
21665 /* For complex modes, use the inner type. */
21666 if (COMPLEX_MODE_P (mode1
))
21667 mode1
= GET_MODE_INNER (mode1
);
21669 if (COMPLEX_MODE_P (mode2
))
21670 mode2
= GET_MODE_INNER (mode2
);
21672 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21673 double to intermix unless -mfloat128-convert. */
21674 if (mode1
== mode2
)
21677 if (!TARGET_FLOAT128_CVT
)
21679 if ((mode1
== KFmode
&& mode2
== IFmode
)
21680 || (mode1
== IFmode
&& mode2
== KFmode
))
21681 return N_("__float128 and __ibm128 cannot be used in the same "
21684 if (TARGET_IEEEQUAD
21685 && ((mode1
== IFmode
&& mode2
== TFmode
)
21686 || (mode1
== TFmode
&& mode2
== IFmode
)))
21687 return N_("__ibm128 and long double cannot be used in the same "
21690 if (!TARGET_IEEEQUAD
21691 && ((mode1
== KFmode
&& mode2
== TFmode
)
21692 || (mode1
== TFmode
&& mode2
== KFmode
)))
21693 return N_("__float128 and long double cannot be used in the same "
21701 /* Expand floating point conversion to/from __float128 and __ibm128. */
21704 rs6000_expand_float128_convert (rtx dest
, rtx src
, bool unsigned_p
)
21706 machine_mode dest_mode
= GET_MODE (dest
);
21707 machine_mode src_mode
= GET_MODE (src
);
21708 convert_optab cvt
= unknown_optab
;
21709 bool do_move
= false;
21710 rtx libfunc
= NULL_RTX
;
21712 typedef rtx (*rtx_2func_t
) (rtx
, rtx
);
21713 rtx_2func_t hw_convert
= (rtx_2func_t
)0;
21717 rtx_2func_t from_df
;
21718 rtx_2func_t from_sf
;
21719 rtx_2func_t from_si_sign
;
21720 rtx_2func_t from_si_uns
;
21721 rtx_2func_t from_di_sign
;
21722 rtx_2func_t from_di_uns
;
21725 rtx_2func_t to_si_sign
;
21726 rtx_2func_t to_si_uns
;
21727 rtx_2func_t to_di_sign
;
21728 rtx_2func_t to_di_uns
;
21729 } hw_conversions
[2] = {
21730 /* convertions to/from KFmode */
21732 gen_extenddfkf2_hw
, /* KFmode <- DFmode. */
21733 gen_extendsfkf2_hw
, /* KFmode <- SFmode. */
21734 gen_float_kfsi2_hw
, /* KFmode <- SImode (signed). */
21735 gen_floatuns_kfsi2_hw
, /* KFmode <- SImode (unsigned). */
21736 gen_float_kfdi2_hw
, /* KFmode <- DImode (signed). */
21737 gen_floatuns_kfdi2_hw
, /* KFmode <- DImode (unsigned). */
21738 gen_trunckfdf2_hw
, /* DFmode <- KFmode. */
21739 gen_trunckfsf2_hw
, /* SFmode <- KFmode. */
21740 gen_fix_kfsi2_hw
, /* SImode <- KFmode (signed). */
21741 gen_fixuns_kfsi2_hw
, /* SImode <- KFmode (unsigned). */
21742 gen_fix_kfdi2_hw
, /* DImode <- KFmode (signed). */
21743 gen_fixuns_kfdi2_hw
, /* DImode <- KFmode (unsigned). */
21746 /* convertions to/from TFmode */
21748 gen_extenddftf2_hw
, /* TFmode <- DFmode. */
21749 gen_extendsftf2_hw
, /* TFmode <- SFmode. */
21750 gen_float_tfsi2_hw
, /* TFmode <- SImode (signed). */
21751 gen_floatuns_tfsi2_hw
, /* TFmode <- SImode (unsigned). */
21752 gen_float_tfdi2_hw
, /* TFmode <- DImode (signed). */
21753 gen_floatuns_tfdi2_hw
, /* TFmode <- DImode (unsigned). */
21754 gen_trunctfdf2_hw
, /* DFmode <- TFmode. */
21755 gen_trunctfsf2_hw
, /* SFmode <- TFmode. */
21756 gen_fix_tfsi2_hw
, /* SImode <- TFmode (signed). */
21757 gen_fixuns_tfsi2_hw
, /* SImode <- TFmode (unsigned). */
21758 gen_fix_tfdi2_hw
, /* DImode <- TFmode (signed). */
21759 gen_fixuns_tfdi2_hw
, /* DImode <- TFmode (unsigned). */
21763 if (dest_mode
== src_mode
)
21764 gcc_unreachable ();
21766 /* Eliminate memory operations. */
21768 src
= force_reg (src_mode
, src
);
21772 rtx tmp
= gen_reg_rtx (dest_mode
);
21773 rs6000_expand_float128_convert (tmp
, src
, unsigned_p
);
21774 rs6000_emit_move (dest
, tmp
, dest_mode
);
21778 /* Convert to IEEE 128-bit floating point. */
21779 if (FLOAT128_IEEE_P (dest_mode
))
21781 if (dest_mode
== KFmode
)
21783 else if (dest_mode
== TFmode
)
21786 gcc_unreachable ();
21792 hw_convert
= hw_conversions
[kf_or_tf
].from_df
;
21797 hw_convert
= hw_conversions
[kf_or_tf
].from_sf
;
21803 if (FLOAT128_IBM_P (src_mode
))
21812 cvt
= ufloat_optab
;
21813 hw_convert
= hw_conversions
[kf_or_tf
].from_si_uns
;
21817 cvt
= sfloat_optab
;
21818 hw_convert
= hw_conversions
[kf_or_tf
].from_si_sign
;
21825 cvt
= ufloat_optab
;
21826 hw_convert
= hw_conversions
[kf_or_tf
].from_di_uns
;
21830 cvt
= sfloat_optab
;
21831 hw_convert
= hw_conversions
[kf_or_tf
].from_di_sign
;
21836 gcc_unreachable ();
21840 /* Convert from IEEE 128-bit floating point. */
21841 else if (FLOAT128_IEEE_P (src_mode
))
21843 if (src_mode
== KFmode
)
21845 else if (src_mode
== TFmode
)
21848 gcc_unreachable ();
21854 hw_convert
= hw_conversions
[kf_or_tf
].to_df
;
21859 hw_convert
= hw_conversions
[kf_or_tf
].to_sf
;
21865 if (FLOAT128_IBM_P (dest_mode
))
21875 hw_convert
= hw_conversions
[kf_or_tf
].to_si_uns
;
21880 hw_convert
= hw_conversions
[kf_or_tf
].to_si_sign
;
21888 hw_convert
= hw_conversions
[kf_or_tf
].to_di_uns
;
21893 hw_convert
= hw_conversions
[kf_or_tf
].to_di_sign
;
21898 gcc_unreachable ();
21902 /* Both IBM format. */
21903 else if (FLOAT128_IBM_P (dest_mode
) && FLOAT128_IBM_P (src_mode
))
21907 gcc_unreachable ();
21909 /* Handle conversion between TFmode/KFmode/IFmode. */
21911 emit_insn (gen_rtx_SET (dest
, gen_rtx_FLOAT_EXTEND (dest_mode
, src
)));
21913 /* Handle conversion if we have hardware support. */
21914 else if (TARGET_FLOAT128_HW
&& hw_convert
)
21915 emit_insn ((hw_convert
) (dest
, src
));
21917 /* Call an external function to do the conversion. */
21918 else if (cvt
!= unknown_optab
)
21920 libfunc
= convert_optab_libfunc (cvt
, dest_mode
, src_mode
);
21921 gcc_assert (libfunc
!= NULL_RTX
);
21923 dest2
= emit_library_call_value (libfunc
, dest
, LCT_CONST
, dest_mode
,
21926 gcc_assert (dest2
!= NULL_RTX
);
21927 if (!rtx_equal_p (dest
, dest2
))
21928 emit_move_insn (dest
, dest2
);
21932 gcc_unreachable ();
21938 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
21939 can be used as that dest register. Return the dest register. */
21942 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
21944 if (op2
== const0_rtx
)
21947 if (GET_CODE (scratch
) == SCRATCH
)
21948 scratch
= gen_reg_rtx (mode
);
21950 if (logical_operand (op2
, mode
))
21951 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
21953 emit_insn (gen_rtx_SET (scratch
,
21954 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
21960 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
21963 machine_mode op_mode
;
21964 enum rtx_code cond_code
;
21965 rtx result
= operands
[0];
21967 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
21968 cond_code
= GET_CODE (condition_rtx
);
21970 if (cond_code
== NE
21971 || cond_code
== GE
|| cond_code
== LE
21972 || cond_code
== GEU
|| cond_code
== LEU
21973 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
21975 rtx not_result
= gen_reg_rtx (CCEQmode
);
21976 rtx not_op
, rev_cond_rtx
;
21977 machine_mode cc_mode
;
21979 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
21981 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
21982 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
21983 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
21984 emit_insn (gen_rtx_SET (not_result
, not_op
));
21985 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
21988 op_mode
= GET_MODE (XEXP (operands
[1], 0));
21989 if (op_mode
== VOIDmode
)
21990 op_mode
= GET_MODE (XEXP (operands
[1], 1));
21992 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
21994 PUT_MODE (condition_rtx
, DImode
);
21995 convert_move (result
, condition_rtx
, 0);
21999 PUT_MODE (condition_rtx
, SImode
);
22000 emit_insn (gen_rtx_SET (result
, condition_rtx
));
22004 /* Emit a branch of kind CODE to location LOC. */
22007 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
22009 rtx condition_rtx
, loc_ref
;
22011 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
22012 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
22013 emit_jump_insn (gen_rtx_SET (pc_rtx
,
22014 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
22015 loc_ref
, pc_rtx
)));
22018 /* Return the string to output a conditional branch to LABEL, which is
22019 the operand template of the label, or NULL if the branch is really a
22020 conditional return.
22022 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22023 condition code register and its mode specifies what kind of
22024 comparison we made.
22026 REVERSED is nonzero if we should reverse the sense of the comparison.
22028 INSN is the insn. */
22031 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
22033 static char string
[64];
22034 enum rtx_code code
= GET_CODE (op
);
22035 rtx cc_reg
= XEXP (op
, 0);
22036 machine_mode mode
= GET_MODE (cc_reg
);
22037 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
22038 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
22039 int really_reversed
= reversed
^ need_longbranch
;
22045 validate_condition_mode (code
, mode
);
22047 /* Work out which way this really branches. We could use
22048 reverse_condition_maybe_unordered here always but this
22049 makes the resulting assembler clearer. */
22050 if (really_reversed
)
22052 /* Reversal of FP compares takes care -- an ordered compare
22053 becomes an unordered compare and vice versa. */
22054 if (mode
== CCFPmode
)
22055 code
= reverse_condition_maybe_unordered (code
);
22057 code
= reverse_condition (code
);
22062 /* Not all of these are actually distinct opcodes, but
22063 we distinguish them for clarity of the resulting assembler. */
22064 case NE
: case LTGT
:
22065 ccode
= "ne"; break;
22066 case EQ
: case UNEQ
:
22067 ccode
= "eq"; break;
22069 ccode
= "ge"; break;
22070 case GT
: case GTU
: case UNGT
:
22071 ccode
= "gt"; break;
22073 ccode
= "le"; break;
22074 case LT
: case LTU
: case UNLT
:
22075 ccode
= "lt"; break;
22076 case UNORDERED
: ccode
= "un"; break;
22077 case ORDERED
: ccode
= "nu"; break;
22078 case UNGE
: ccode
= "nl"; break;
22079 case UNLE
: ccode
= "ng"; break;
22081 gcc_unreachable ();
22084 /* Maybe we have a guess as to how likely the branch is. */
22086 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
22087 if (note
!= NULL_RTX
)
22089 /* PROB is the difference from 50%. */
22090 int prob
= profile_probability::from_reg_br_prob_note (XINT (note
, 0))
22091 .to_reg_br_prob_base () - REG_BR_PROB_BASE
/ 2;
22093 /* Only hint for highly probable/improbable branches on newer cpus when
22094 we have real profile data, as static prediction overrides processor
22095 dynamic prediction. For older cpus we may as well always hint, but
22096 assume not taken for branches that are very close to 50% as a
22097 mispredicted taken branch is more expensive than a
22098 mispredicted not-taken branch. */
22099 if (rs6000_always_hint
22100 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
22101 && (profile_status_for_fn (cfun
) != PROFILE_GUESSED
)
22102 && br_prob_note_reliable_p (note
)))
22104 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
22105 && ((prob
> 0) ^ need_longbranch
))
22113 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
22115 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
22117 /* We need to escape any '%' characters in the reg_names string.
22118 Assume they'd only be the first character.... */
22119 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
22121 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
22125 /* If the branch distance was too far, we may have to use an
22126 unconditional branch to go the distance. */
22127 if (need_longbranch
)
22128 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
22130 s
+= sprintf (s
, ",%s", label
);
22136 /* Return insn for VSX or Altivec comparisons. */
22139 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
22142 machine_mode mode
= GET_MODE (op0
);
22150 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
22161 mask
= gen_reg_rtx (mode
);
22162 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
22169 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22170 DMODE is expected destination mode. This is a recursive function. */
22173 rs6000_emit_vector_compare (enum rtx_code rcode
,
22175 machine_mode dmode
)
22178 bool swap_operands
= false;
22179 bool try_again
= false;
22181 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
22182 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
22184 /* See if the comparison works as is. */
22185 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22193 swap_operands
= true;
22198 swap_operands
= true;
22206 /* Invert condition and try again.
22207 e.g., A != B becomes ~(A==B). */
22209 enum rtx_code rev_code
;
22210 enum insn_code nor_code
;
22213 rev_code
= reverse_condition_maybe_unordered (rcode
);
22214 if (rev_code
== UNKNOWN
)
22217 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
22218 if (nor_code
== CODE_FOR_nothing
)
22221 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
22225 mask
= gen_reg_rtx (dmode
);
22226 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
22234 /* Try GT/GTU/LT/LTU OR EQ */
22237 enum insn_code ior_code
;
22238 enum rtx_code new_code
;
22259 gcc_unreachable ();
22262 ior_code
= optab_handler (ior_optab
, dmode
);
22263 if (ior_code
== CODE_FOR_nothing
)
22266 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
22270 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
22274 mask
= gen_reg_rtx (dmode
);
22275 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
22286 std::swap (op0
, op1
);
22288 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22293 /* You only get two chances. */
22297 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22298 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22299 operands for the relation operation COND. */
22302 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
22303 rtx cond
, rtx cc_op0
, rtx cc_op1
)
22305 machine_mode dest_mode
= GET_MODE (dest
);
22306 machine_mode mask_mode
= GET_MODE (cc_op0
);
22307 enum rtx_code rcode
= GET_CODE (cond
);
22308 machine_mode cc_mode
= CCmode
;
22311 bool invert_move
= false;
22313 if (VECTOR_UNIT_NONE_P (dest_mode
))
22316 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
22317 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
22321 /* Swap operands if we can, and fall back to doing the operation as
22322 specified, and doing a NOR to invert the test. */
22328 /* Invert condition and try again.
22329 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22330 invert_move
= true;
22331 rcode
= reverse_condition_maybe_unordered (rcode
);
22332 if (rcode
== UNKNOWN
)
22338 if (GET_MODE_CLASS (mask_mode
) == MODE_VECTOR_INT
)
22340 /* Invert condition to avoid compound test. */
22341 invert_move
= true;
22342 rcode
= reverse_condition (rcode
);
22350 /* Mark unsigned tests with CCUNSmode. */
22351 cc_mode
= CCUNSmode
;
22353 /* Invert condition to avoid compound test if necessary. */
22354 if (rcode
== GEU
|| rcode
== LEU
)
22356 invert_move
= true;
22357 rcode
= reverse_condition (rcode
);
22365 /* Get the vector mask for the given relational operations. */
22366 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
22372 std::swap (op_true
, op_false
);
22374 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22375 if (GET_MODE_CLASS (dest_mode
) == MODE_VECTOR_INT
22376 && (GET_CODE (op_true
) == CONST_VECTOR
22377 || GET_CODE (op_false
) == CONST_VECTOR
))
22379 rtx constant_0
= CONST0_RTX (dest_mode
);
22380 rtx constant_m1
= CONSTM1_RTX (dest_mode
);
22382 if (op_true
== constant_m1
&& op_false
== constant_0
)
22384 emit_move_insn (dest
, mask
);
22388 else if (op_true
== constant_0
&& op_false
== constant_m1
)
22390 emit_insn (gen_rtx_SET (dest
, gen_rtx_NOT (dest_mode
, mask
)));
22394 /* If we can't use the vector comparison directly, perhaps we can use
22395 the mask for the true or false fields, instead of loading up a
22397 if (op_true
== constant_m1
)
22400 if (op_false
== constant_0
)
22404 if (!REG_P (op_true
) && !SUBREG_P (op_true
))
22405 op_true
= force_reg (dest_mode
, op_true
);
22407 if (!REG_P (op_false
) && !SUBREG_P (op_false
))
22408 op_false
= force_reg (dest_mode
, op_false
);
22410 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
22411 CONST0_RTX (dest_mode
));
22412 emit_insn (gen_rtx_SET (dest
,
22413 gen_rtx_IF_THEN_ELSE (dest_mode
,
22420 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22421 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22422 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22423 hardware has no such operation. */
22426 rs6000_emit_p9_fp_minmax (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22428 enum rtx_code code
= GET_CODE (op
);
22429 rtx op0
= XEXP (op
, 0);
22430 rtx op1
= XEXP (op
, 1);
22431 machine_mode compare_mode
= GET_MODE (op0
);
22432 machine_mode result_mode
= GET_MODE (dest
);
22433 bool max_p
= false;
22435 if (result_mode
!= compare_mode
)
22438 if (code
== GE
|| code
== GT
)
22440 else if (code
== LE
|| code
== LT
)
22445 if (rtx_equal_p (op0
, true_cond
) && rtx_equal_p (op1
, false_cond
))
22448 else if (rtx_equal_p (op1
, true_cond
) && rtx_equal_p (op0
, false_cond
))
22454 rs6000_emit_minmax (dest
, max_p
? SMAX
: SMIN
, op0
, op1
);
22458 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22459 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22460 operands of the last comparison is nonzero/true, FALSE_COND if it is
22461 zero/false. Return 0 if the hardware has no such operation. */
22464 rs6000_emit_p9_fp_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22466 enum rtx_code code
= GET_CODE (op
);
22467 rtx op0
= XEXP (op
, 0);
22468 rtx op1
= XEXP (op
, 1);
22469 machine_mode result_mode
= GET_MODE (dest
);
22474 if (!can_create_pseudo_p ())
22487 code
= swap_condition (code
);
22488 std::swap (op0
, op1
);
22495 /* Generate: [(parallel [(set (dest)
22496 (if_then_else (op (cmp1) (cmp2))
22499 (clobber (scratch))])]. */
22501 compare_rtx
= gen_rtx_fmt_ee (code
, CCFPmode
, op0
, op1
);
22502 cmove_rtx
= gen_rtx_SET (dest
,
22503 gen_rtx_IF_THEN_ELSE (result_mode
,
22508 clobber_rtx
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (V2DImode
));
22509 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22510 gen_rtvec (2, cmove_rtx
, clobber_rtx
)));
22515 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22516 operands of the last comparison is nonzero/true, FALSE_COND if it
22517 is zero/false. Return 0 if the hardware has no such operation. */
22520 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22522 enum rtx_code code
= GET_CODE (op
);
22523 rtx op0
= XEXP (op
, 0);
22524 rtx op1
= XEXP (op
, 1);
22525 machine_mode compare_mode
= GET_MODE (op0
);
22526 machine_mode result_mode
= GET_MODE (dest
);
22528 bool is_against_zero
;
22530 /* These modes should always match. */
22531 if (GET_MODE (op1
) != compare_mode
22532 /* In the isel case however, we can use a compare immediate, so
22533 op1 may be a small constant. */
22534 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
22536 if (GET_MODE (true_cond
) != result_mode
)
22538 if (GET_MODE (false_cond
) != result_mode
)
22541 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22542 if (TARGET_P9_MINMAX
22543 && (compare_mode
== SFmode
|| compare_mode
== DFmode
)
22544 && (result_mode
== SFmode
|| result_mode
== DFmode
))
22546 if (rs6000_emit_p9_fp_minmax (dest
, op
, true_cond
, false_cond
))
22549 if (rs6000_emit_p9_fp_cmove (dest
, op
, true_cond
, false_cond
))
22553 /* Don't allow using floating point comparisons for integer results for
22555 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
22558 /* First, work out if the hardware can do this at all, or
22559 if it's too slow.... */
22560 if (!FLOAT_MODE_P (compare_mode
))
22563 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
22567 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
22569 /* A floating-point subtract might overflow, underflow, or produce
22570 an inexact result, thus changing the floating-point flags, so it
22571 can't be generated if we care about that. It's safe if one side
22572 of the construct is zero, since then no subtract will be
22574 if (SCALAR_FLOAT_MODE_P (compare_mode
)
22575 && flag_trapping_math
&& ! is_against_zero
)
22578 /* Eliminate half of the comparisons by switching operands, this
22579 makes the remaining code simpler. */
22580 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
22581 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
22583 code
= reverse_condition_maybe_unordered (code
);
22585 true_cond
= false_cond
;
22589 /* UNEQ and LTGT take four instructions for a comparison with zero,
22590 it'll probably be faster to use a branch here too. */
22591 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
22594 /* We're going to try to implement comparisons by performing
22595 a subtract, then comparing against zero. Unfortunately,
22596 Inf - Inf is NaN which is not zero, and so if we don't
22597 know that the operand is finite and the comparison
22598 would treat EQ different to UNORDERED, we can't do it. */
22599 if (HONOR_INFINITIES (compare_mode
)
22600 && code
!= GT
&& code
!= UNGE
22601 && (GET_CODE (op1
) != CONST_DOUBLE
22602 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1
)))
22603 /* Constructs of the form (a OP b ? a : b) are safe. */
22604 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
22605 || (! rtx_equal_p (op0
, true_cond
)
22606 && ! rtx_equal_p (op1
, true_cond
))))
22609 /* At this point we know we can use fsel. */
22611 /* Reduce the comparison to a comparison against zero. */
22612 if (! is_against_zero
)
22614 temp
= gen_reg_rtx (compare_mode
);
22615 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
22617 op1
= CONST0_RTX (compare_mode
);
22620 /* If we don't care about NaNs we can reduce some of the comparisons
22621 down to faster ones. */
22622 if (! HONOR_NANS (compare_mode
))
22628 true_cond
= false_cond
;
22641 /* Now, reduce everything down to a GE. */
22648 temp
= gen_reg_rtx (compare_mode
);
22649 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
22654 temp
= gen_reg_rtx (compare_mode
);
22655 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
22660 temp
= gen_reg_rtx (compare_mode
);
22661 emit_insn (gen_rtx_SET (temp
,
22662 gen_rtx_NEG (compare_mode
,
22663 gen_rtx_ABS (compare_mode
, op0
))));
22668 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22669 temp
= gen_reg_rtx (result_mode
);
22670 emit_insn (gen_rtx_SET (temp
,
22671 gen_rtx_IF_THEN_ELSE (result_mode
,
22672 gen_rtx_GE (VOIDmode
,
22674 true_cond
, false_cond
)));
22675 false_cond
= true_cond
;
22678 temp
= gen_reg_rtx (compare_mode
);
22679 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
22684 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22685 temp
= gen_reg_rtx (result_mode
);
22686 emit_insn (gen_rtx_SET (temp
,
22687 gen_rtx_IF_THEN_ELSE (result_mode
,
22688 gen_rtx_GE (VOIDmode
,
22690 true_cond
, false_cond
)));
22691 true_cond
= false_cond
;
22694 temp
= gen_reg_rtx (compare_mode
);
22695 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
22700 gcc_unreachable ();
22703 emit_insn (gen_rtx_SET (dest
,
22704 gen_rtx_IF_THEN_ELSE (result_mode
,
22705 gen_rtx_GE (VOIDmode
,
22707 true_cond
, false_cond
)));
22711 /* Same as above, but for ints (isel). */
22714 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22716 rtx condition_rtx
, cr
;
22717 machine_mode mode
= GET_MODE (dest
);
22718 enum rtx_code cond_code
;
22719 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
22722 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
22725 /* We still have to do the compare, because isel doesn't do a
22726 compare, it just looks at the CRx bits set by a previous compare
22728 condition_rtx
= rs6000_generate_compare (op
, mode
);
22729 cond_code
= GET_CODE (condition_rtx
);
22730 cr
= XEXP (condition_rtx
, 0);
22731 signedp
= GET_MODE (cr
) == CCmode
;
22733 isel_func
= (mode
== SImode
22734 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
22735 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
22739 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
22740 /* isel handles these directly. */
22744 /* We need to swap the sense of the comparison. */
22746 std::swap (false_cond
, true_cond
);
22747 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
22752 false_cond
= force_reg (mode
, false_cond
);
22753 if (true_cond
!= const0_rtx
)
22754 true_cond
= force_reg (mode
, true_cond
);
22756 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
22762 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
22764 machine_mode mode
= GET_MODE (op0
);
22768 /* VSX/altivec have direct min/max insns. */
22769 if ((code
== SMAX
|| code
== SMIN
)
22770 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
22771 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
22773 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
22777 if (code
== SMAX
|| code
== SMIN
)
22782 if (code
== SMAX
|| code
== UMAX
)
22783 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
22784 op0
, op1
, mode
, 0);
22786 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
22787 op1
, op0
, mode
, 0);
22788 gcc_assert (target
);
22789 if (target
!= dest
)
22790 emit_move_insn (dest
, target
);
22793 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22794 COND is true. Mark the jump as unlikely to be taken. */
22797 emit_unlikely_jump (rtx cond
, rtx label
)
22799 rtx x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
22800 rtx_insn
*insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
22801 add_reg_br_prob_note (insn
, profile_probability::very_unlikely ());
22804 /* A subroutine of the atomic operation splitters. Emit a load-locked
22805 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22806 the zero_extend operation. */
22809 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
22811 rtx (*fn
) (rtx
, rtx
) = NULL
;
22816 fn
= gen_load_lockedqi
;
22819 fn
= gen_load_lockedhi
;
22822 if (GET_MODE (mem
) == QImode
)
22823 fn
= gen_load_lockedqi_si
;
22824 else if (GET_MODE (mem
) == HImode
)
22825 fn
= gen_load_lockedhi_si
;
22827 fn
= gen_load_lockedsi
;
22830 fn
= gen_load_lockeddi
;
22833 fn
= gen_load_lockedti
;
22836 gcc_unreachable ();
22838 emit_insn (fn (reg
, mem
));
22841 /* A subroutine of the atomic operation splitters. Emit a store-conditional
22842 instruction in MODE. */
22845 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
22847 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
22852 fn
= gen_store_conditionalqi
;
22855 fn
= gen_store_conditionalhi
;
22858 fn
= gen_store_conditionalsi
;
22861 fn
= gen_store_conditionaldi
;
22864 fn
= gen_store_conditionalti
;
22867 gcc_unreachable ();
22870 /* Emit sync before stwcx. to address PPC405 Erratum. */
22871 if (PPC405_ERRATUM77
)
22872 emit_insn (gen_hwsync ());
22874 emit_insn (fn (res
, mem
, val
));
22877 /* Expand barriers before and after a load_locked/store_cond sequence. */
22880 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
22882 rtx addr
= XEXP (mem
, 0);
22884 if (!legitimate_indirect_address_p (addr
, reload_completed
)
22885 && !legitimate_indexed_address_p (addr
, reload_completed
))
22887 addr
= force_reg (Pmode
, addr
);
22888 mem
= replace_equiv_address_nv (mem
, addr
);
22893 case MEMMODEL_RELAXED
:
22894 case MEMMODEL_CONSUME
:
22895 case MEMMODEL_ACQUIRE
:
22897 case MEMMODEL_RELEASE
:
22898 case MEMMODEL_ACQ_REL
:
22899 emit_insn (gen_lwsync ());
22901 case MEMMODEL_SEQ_CST
:
22902 emit_insn (gen_hwsync ());
22905 gcc_unreachable ();
22911 rs6000_post_atomic_barrier (enum memmodel model
)
22915 case MEMMODEL_RELAXED
:
22916 case MEMMODEL_CONSUME
:
22917 case MEMMODEL_RELEASE
:
22919 case MEMMODEL_ACQUIRE
:
22920 case MEMMODEL_ACQ_REL
:
22921 case MEMMODEL_SEQ_CST
:
22922 emit_insn (gen_isync ());
22925 gcc_unreachable ();
22929 /* A subroutine of the various atomic expanders. For sub-word operations,
22930 we must adjust things to operate on SImode. Given the original MEM,
22931 return a new aligned memory. Also build and return the quantities by
22932 which to shift and mask. */
22935 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
22937 rtx addr
, align
, shift
, mask
, mem
;
22938 HOST_WIDE_INT shift_mask
;
22939 machine_mode mode
= GET_MODE (orig_mem
);
22941 /* For smaller modes, we have to implement this via SImode. */
22942 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
22944 addr
= XEXP (orig_mem
, 0);
22945 addr
= force_reg (GET_MODE (addr
), addr
);
22947 /* Aligned memory containing subword. Generate a new memory. We
22948 do not want any of the existing MEM_ATTR data, as we're now
22949 accessing memory outside the original object. */
22950 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
22951 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22952 mem
= gen_rtx_MEM (SImode
, align
);
22953 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
22954 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
22955 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
22957 /* Shift amount for subword relative to aligned word. */
22958 shift
= gen_reg_rtx (SImode
);
22959 addr
= gen_lowpart (SImode
, addr
);
22960 rtx tmp
= gen_reg_rtx (SImode
);
22961 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
22962 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
22963 if (BYTES_BIG_ENDIAN
)
22964 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
22965 shift
, 1, OPTAB_LIB_WIDEN
);
22968 /* Mask for insertion. */
22969 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
22970 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22976 /* A subroutine of the various atomic expanders. For sub-word operands,
22977 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
22980 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
22984 x
= gen_reg_rtx (SImode
);
22985 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
22986 gen_rtx_NOT (SImode
, mask
),
22989 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
22994 /* A subroutine of the various atomic expanders. For sub-word operands,
22995 extract WIDE to NARROW via SHIFT. */
22998 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
23000 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
23001 wide
, 1, OPTAB_LIB_WIDEN
);
23002 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
23005 /* Expand an atomic compare and swap operation. */
23008 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
23010 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
23011 rtx label1
, label2
, x
, mask
, shift
;
23012 machine_mode mode
, orig_mode
;
23013 enum memmodel mod_s
, mod_f
;
23016 boolval
= operands
[0];
23017 retval
= operands
[1];
23019 oldval
= operands
[3];
23020 newval
= operands
[4];
23021 is_weak
= (INTVAL (operands
[5]) != 0);
23022 mod_s
= memmodel_base (INTVAL (operands
[6]));
23023 mod_f
= memmodel_base (INTVAL (operands
[7]));
23024 orig_mode
= mode
= GET_MODE (mem
);
23026 mask
= shift
= NULL_RTX
;
23027 if (mode
== QImode
|| mode
== HImode
)
23029 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23030 lwarx and shift/mask operations. With power8, we need to do the
23031 comparison in SImode, but the store is still done in QI/HImode. */
23032 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
23034 if (!TARGET_SYNC_HI_QI
)
23036 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23038 /* Shift and mask OLDVAL into position with the word. */
23039 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
23040 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23042 /* Shift and mask NEWVAL into position within the word. */
23043 newval
= convert_modes (SImode
, mode
, newval
, 1);
23044 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
23045 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23048 /* Prepare to adjust the return value. */
23049 retval
= gen_reg_rtx (SImode
);
23052 else if (reg_overlap_mentioned_p (retval
, oldval
))
23053 oldval
= copy_to_reg (oldval
);
23055 if (mode
!= TImode
&& !reg_or_short_operand (oldval
, mode
))
23056 oldval
= copy_to_mode_reg (mode
, oldval
);
23058 if (reg_overlap_mentioned_p (retval
, newval
))
23059 newval
= copy_to_reg (newval
);
23061 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
23066 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23067 emit_label (XEXP (label1
, 0));
23069 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23071 emit_load_locked (mode
, retval
, mem
);
23075 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
23076 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23078 cond
= gen_reg_rtx (CCmode
);
23079 /* If we have TImode, synthesize a comparison. */
23080 if (mode
!= TImode
)
23081 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
23084 rtx xor1_result
= gen_reg_rtx (DImode
);
23085 rtx xor2_result
= gen_reg_rtx (DImode
);
23086 rtx or_result
= gen_reg_rtx (DImode
);
23087 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
23088 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
23089 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
23090 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
23092 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
23093 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
23094 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
23095 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
23098 emit_insn (gen_rtx_SET (cond
, x
));
23100 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23101 emit_unlikely_jump (x
, label2
);
23105 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
23107 emit_store_conditional (orig_mode
, cond
, mem
, x
);
23111 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23112 emit_unlikely_jump (x
, label1
);
23115 if (!is_mm_relaxed (mod_f
))
23116 emit_label (XEXP (label2
, 0));
23118 rs6000_post_atomic_barrier (mod_s
);
23120 if (is_mm_relaxed (mod_f
))
23121 emit_label (XEXP (label2
, 0));
23124 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
23125 else if (mode
!= GET_MODE (operands
[1]))
23126 convert_move (operands
[1], retval
, 1);
23128 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23129 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
23130 emit_insn (gen_rtx_SET (boolval
, x
));
23133 /* Expand an atomic exchange operation. */
23136 rs6000_expand_atomic_exchange (rtx operands
[])
23138 rtx retval
, mem
, val
, cond
;
23140 enum memmodel model
;
23141 rtx label
, x
, mask
, shift
;
23143 retval
= operands
[0];
23146 model
= memmodel_base (INTVAL (operands
[3]));
23147 mode
= GET_MODE (mem
);
23149 mask
= shift
= NULL_RTX
;
23150 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
23152 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23154 /* Shift and mask VAL into position with the word. */
23155 val
= convert_modes (SImode
, mode
, val
, 1);
23156 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23157 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23159 /* Prepare to adjust the return value. */
23160 retval
= gen_reg_rtx (SImode
);
23164 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23166 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23167 emit_label (XEXP (label
, 0));
23169 emit_load_locked (mode
, retval
, mem
);
23173 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
23175 cond
= gen_reg_rtx (CCmode
);
23176 emit_store_conditional (mode
, cond
, mem
, x
);
23178 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23179 emit_unlikely_jump (x
, label
);
23181 rs6000_post_atomic_barrier (model
);
23184 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
23187 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23188 to perform. MEM is the memory on which to operate. VAL is the second
23189 operand of the binary operator. BEFORE and AFTER are optional locations to
23190 return the value of MEM either before of after the operation. MODEL_RTX
23191 is a CONST_INT containing the memory model to use. */
23194 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
23195 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
23197 enum memmodel model
= memmodel_base (INTVAL (model_rtx
));
23198 machine_mode mode
= GET_MODE (mem
);
23199 machine_mode store_mode
= mode
;
23200 rtx label
, x
, cond
, mask
, shift
;
23201 rtx before
= orig_before
, after
= orig_after
;
23203 mask
= shift
= NULL_RTX
;
23204 /* On power8, we want to use SImode for the operation. On previous systems,
23205 use the operation in a subword and shift/mask to get the proper byte or
23207 if (mode
== QImode
|| mode
== HImode
)
23209 if (TARGET_SYNC_HI_QI
)
23211 val
= convert_modes (SImode
, mode
, val
, 1);
23213 /* Prepare to adjust the return value. */
23214 before
= gen_reg_rtx (SImode
);
23216 after
= gen_reg_rtx (SImode
);
23221 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23223 /* Shift and mask VAL into position with the word. */
23224 val
= convert_modes (SImode
, mode
, val
, 1);
23225 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23226 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23232 /* We've already zero-extended VAL. That is sufficient to
23233 make certain that it does not affect other bits. */
23238 /* If we make certain that all of the other bits in VAL are
23239 set, that will be sufficient to not affect other bits. */
23240 x
= gen_rtx_NOT (SImode
, mask
);
23241 x
= gen_rtx_IOR (SImode
, x
, val
);
23242 emit_insn (gen_rtx_SET (val
, x
));
23249 /* These will all affect bits outside the field and need
23250 adjustment via MASK within the loop. */
23254 gcc_unreachable ();
23257 /* Prepare to adjust the return value. */
23258 before
= gen_reg_rtx (SImode
);
23260 after
= gen_reg_rtx (SImode
);
23261 store_mode
= mode
= SImode
;
23265 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23267 label
= gen_label_rtx ();
23268 emit_label (label
);
23269 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
23271 if (before
== NULL_RTX
)
23272 before
= gen_reg_rtx (mode
);
23274 emit_load_locked (mode
, before
, mem
);
23278 x
= expand_simple_binop (mode
, AND
, before
, val
,
23279 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23280 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
23284 after
= expand_simple_binop (mode
, code
, before
, val
,
23285 after
, 1, OPTAB_LIB_WIDEN
);
23291 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
23292 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23293 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
23295 else if (store_mode
!= mode
)
23296 x
= convert_modes (store_mode
, mode
, x
, 1);
23298 cond
= gen_reg_rtx (CCmode
);
23299 emit_store_conditional (store_mode
, cond
, mem
, x
);
23301 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23302 emit_unlikely_jump (x
, label
);
23304 rs6000_post_atomic_barrier (model
);
23308 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23309 then do the calcuations in a SImode register. */
23311 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
23313 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
23315 else if (store_mode
!= mode
)
23317 /* QImode/HImode on machines with lbarx/lharx where we do the native
23318 operation and then do the calcuations in a SImode register. */
23320 convert_move (orig_before
, before
, 1);
23322 convert_move (orig_after
, after
, 1);
23324 else if (orig_after
&& after
!= orig_after
)
23325 emit_move_insn (orig_after
, after
);
23328 /* Emit instructions to move SRC to DST. Called by splitters for
23329 multi-register moves. It will emit at most one instruction for
23330 each register that is accessed; that is, it won't emit li/lis pairs
23331 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23335 rs6000_split_multireg_move (rtx dst
, rtx src
)
23337 /* The register number of the first register being moved. */
23339 /* The mode that is to be moved. */
23341 /* The mode that the move is being done in, and its size. */
23342 machine_mode reg_mode
;
23344 /* The number of registers that will be moved. */
23347 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
23348 mode
= GET_MODE (dst
);
23349 nregs
= hard_regno_nregs (reg
, mode
);
23350 if (FP_REGNO_P (reg
))
23351 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
23352 (TARGET_HARD_FLOAT
? DFmode
: SFmode
);
23353 else if (ALTIVEC_REGNO_P (reg
))
23354 reg_mode
= V16QImode
;
23356 reg_mode
= word_mode
;
23357 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
23359 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
23361 /* TDmode residing in FP registers is special, since the ISA requires that
23362 the lower-numbered word of a register pair is always the most significant
23363 word, even in little-endian mode. This does not match the usual subreg
23364 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23365 the appropriate constituent registers "by hand" in little-endian mode.
23367 Note we do not need to check for destructive overlap here since TDmode
23368 can only reside in even/odd register pairs. */
23369 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
23374 for (i
= 0; i
< nregs
; i
++)
23376 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
23377 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
23379 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
23380 i
* reg_mode_size
);
23382 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
23383 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
23385 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
23386 i
* reg_mode_size
);
23388 emit_insn (gen_rtx_SET (p_dst
, p_src
));
23394 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
23396 /* Move register range backwards, if we might have destructive
23399 for (i
= nregs
- 1; i
>= 0; i
--)
23400 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
23401 i
* reg_mode_size
),
23402 simplify_gen_subreg (reg_mode
, src
, mode
,
23403 i
* reg_mode_size
)));
23409 bool used_update
= false;
23410 rtx restore_basereg
= NULL_RTX
;
23412 if (MEM_P (src
) && INT_REGNO_P (reg
))
23416 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
23417 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
23420 breg
= XEXP (XEXP (src
, 0), 0);
23421 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
23422 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
23423 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
23424 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
23425 src
= replace_equiv_address (src
, breg
);
23427 else if (! rs6000_offsettable_memref_p (src
, reg_mode
, true))
23429 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
23431 rtx basereg
= XEXP (XEXP (src
, 0), 0);
23434 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
23435 emit_insn (gen_rtx_SET (ndst
,
23436 gen_rtx_MEM (reg_mode
,
23438 used_update
= true;
23441 emit_insn (gen_rtx_SET (basereg
,
23442 XEXP (XEXP (src
, 0), 1)));
23443 src
= replace_equiv_address (src
, basereg
);
23447 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
23448 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
23449 src
= replace_equiv_address (src
, basereg
);
23453 breg
= XEXP (src
, 0);
23454 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
23455 breg
= XEXP (breg
, 0);
23457 /* If the base register we are using to address memory is
23458 also a destination reg, then change that register last. */
23460 && REGNO (breg
) >= REGNO (dst
)
23461 && REGNO (breg
) < REGNO (dst
) + nregs
)
23462 j
= REGNO (breg
) - REGNO (dst
);
23464 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
23468 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
23469 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
23472 breg
= XEXP (XEXP (dst
, 0), 0);
23473 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
23474 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
23475 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
23477 /* We have to update the breg before doing the store.
23478 Use store with update, if available. */
23482 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
23483 emit_insn (TARGET_32BIT
23484 ? (TARGET_POWERPC64
23485 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
23486 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
23487 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
23488 used_update
= true;
23491 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
23492 dst
= replace_equiv_address (dst
, breg
);
23494 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
, true)
23495 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
23497 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
23499 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
23502 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
23503 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
23506 used_update
= true;
23509 emit_insn (gen_rtx_SET (basereg
,
23510 XEXP (XEXP (dst
, 0), 1)));
23511 dst
= replace_equiv_address (dst
, basereg
);
23515 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
23516 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
23517 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
23519 && REG_P (offsetreg
)
23520 && REGNO (basereg
) != REGNO (offsetreg
));
23521 if (REGNO (basereg
) == 0)
23523 rtx tmp
= offsetreg
;
23524 offsetreg
= basereg
;
23527 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
23528 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
23529 dst
= replace_equiv_address (dst
, basereg
);
23532 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
23533 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
, true));
23536 for (i
= 0; i
< nregs
; i
++)
23538 /* Calculate index to next subword. */
23543 /* If compiler already emitted move of first word by
23544 store with update, no need to do anything. */
23545 if (j
== 0 && used_update
)
23548 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
23549 j
* reg_mode_size
),
23550 simplify_gen_subreg (reg_mode
, src
, mode
,
23551 j
* reg_mode_size
)));
23553 if (restore_basereg
!= NULL_RTX
)
23554 emit_insn (restore_basereg
);
23559 /* This page contains routines that are used to determine what the
23560 function prologue and epilogue code will do and write them out. */
23562 /* Determine whether the REG is really used. */
23565 save_reg_p (int reg
)
23567 /* We need to mark the PIC offset register live for the same conditions
23568 as it is set up, or otherwise it won't be saved before we clobber it. */
23570 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
&& !TARGET_SINGLE_PIC_BASE
)
23572 /* When calling eh_return, we must return true for all the cases
23573 where conditional_register_usage marks the PIC offset reg
23575 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
23576 && (crtl
->calls_eh_return
23577 || df_regs_ever_live_p (reg
)
23578 || !constant_pool_empty_p ()))
23581 if ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
23586 return !call_used_regs
[reg
] && df_regs_ever_live_p (reg
);
23589 /* Return the first fixed-point register that is required to be
23590 saved. 32 if none. */
23593 first_reg_to_save (void)
23597 /* Find lowest numbered live register. */
23598 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
23599 if (save_reg_p (first_reg
))
23604 && crtl
->uses_pic_offset_table
23605 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
23606 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
23612 /* Similar, for FP regs. */
23615 first_fp_reg_to_save (void)
23619 /* Find lowest numbered live register. */
23620 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
23621 if (save_reg_p (first_reg
))
23627 /* Similar, for AltiVec regs. */
23630 first_altivec_reg_to_save (void)
23634 /* Stack frame remains as is unless we are in AltiVec ABI. */
23635 if (! TARGET_ALTIVEC_ABI
)
23636 return LAST_ALTIVEC_REGNO
+ 1;
23638 /* On Darwin, the unwind routines are compiled without
23639 TARGET_ALTIVEC, and use save_world to save/restore the
23640 altivec registers when necessary. */
23641 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
23642 && ! TARGET_ALTIVEC
)
23643 return FIRST_ALTIVEC_REGNO
+ 20;
23645 /* Find lowest numbered live register. */
23646 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23647 if (save_reg_p (i
))
23653 /* Return a 32-bit mask of the AltiVec registers we need to set in
23654 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23655 the 32-bit word is 0. */
23657 static unsigned int
23658 compute_vrsave_mask (void)
23660 unsigned int i
, mask
= 0;
23662 /* On Darwin, the unwind routines are compiled without
23663 TARGET_ALTIVEC, and use save_world to save/restore the
23664 call-saved altivec registers when necessary. */
23665 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
23666 && ! TARGET_ALTIVEC
)
23669 /* First, find out if we use _any_ altivec registers. */
23670 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23671 if (df_regs_ever_live_p (i
))
23672 mask
|= ALTIVEC_REG_BIT (i
);
23677 /* Next, remove the argument registers from the set. These must
23678 be in the VRSAVE mask set by the caller, so we don't need to add
23679 them in again. More importantly, the mask we compute here is
23680 used to generate CLOBBERs in the set_vrsave insn, and we do not
23681 wish the argument registers to die. */
23682 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
23683 mask
&= ~ALTIVEC_REG_BIT (i
);
23685 /* Similarly, remove the return value from the set. */
23688 diddle_return_value (is_altivec_return_reg
, &yes
);
23690 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
23696 /* For a very restricted set of circumstances, we can cut down the
23697 size of prologues/epilogues by calling our own save/restore-the-world
23701 compute_save_world_info (rs6000_stack_t
*info
)
23703 info
->world_save_p
= 1;
23705 = (WORLD_SAVE_P (info
)
23706 && DEFAULT_ABI
== ABI_DARWIN
23707 && !cfun
->has_nonlocal_label
23708 && info
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
23709 && info
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
23710 && info
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
23711 && info
->cr_save_p
);
23713 /* This will not work in conjunction with sibcalls. Make sure there
23714 are none. (This check is expensive, but seldom executed.) */
23715 if (WORLD_SAVE_P (info
))
23718 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
23719 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
23721 info
->world_save_p
= 0;
23726 if (WORLD_SAVE_P (info
))
23728 /* Even if we're not touching VRsave, make sure there's room on the
23729 stack for it, if it looks like we're calling SAVE_WORLD, which
23730 will attempt to save it. */
23731 info
->vrsave_size
= 4;
23733 /* If we are going to save the world, we need to save the link register too. */
23734 info
->lr_save_p
= 1;
23736 /* "Save" the VRsave register too if we're saving the world. */
23737 if (info
->vrsave_mask
== 0)
23738 info
->vrsave_mask
= compute_vrsave_mask ();
23740 /* Because the Darwin register save/restore routines only handle
23741 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23743 gcc_assert (info
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
23744 && (info
->first_altivec_reg_save
23745 >= FIRST_SAVED_ALTIVEC_REGNO
));
23753 is_altivec_return_reg (rtx reg
, void *xyes
)
23755 bool *yes
= (bool *) xyes
;
23756 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
23761 /* Return whether REG is a global user reg or has been specifed by
23762 -ffixed-REG. We should not restore these, and so cannot use
23763 lmw or out-of-line restore functions if there are any. We also
23764 can't save them (well, emit frame notes for them), because frame
23765 unwinding during exception handling will restore saved registers. */
23768 fixed_reg_p (int reg
)
23770 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23771 backend sets it, overriding anything the user might have given. */
23772 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
23773 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
)
23774 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
23775 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
23778 return fixed_regs
[reg
];
23781 /* Determine the strategy for savings/restoring registers. */
23784 SAVE_MULTIPLE
= 0x1,
23785 SAVE_INLINE_GPRS
= 0x2,
23786 SAVE_INLINE_FPRS
= 0x4,
23787 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x8,
23788 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x10,
23789 SAVE_INLINE_VRS
= 0x20,
23790 REST_MULTIPLE
= 0x100,
23791 REST_INLINE_GPRS
= 0x200,
23792 REST_INLINE_FPRS
= 0x400,
23793 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x800,
23794 REST_INLINE_VRS
= 0x1000
23798 rs6000_savres_strategy (rs6000_stack_t
*info
,
23799 bool using_static_chain_p
)
23803 /* Select between in-line and out-of-line save and restore of regs.
23804 First, all the obvious cases where we don't use out-of-line. */
23805 if (crtl
->calls_eh_return
23806 || cfun
->machine
->ra_need_lr
)
23807 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
23808 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
23809 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
23811 if (info
->first_gp_reg_save
== 32)
23812 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
23814 if (info
->first_fp_reg_save
== 64)
23815 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
23817 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1)
23818 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
23820 /* Define cutoff for using out-of-line functions to save registers. */
23821 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
23823 if (!optimize_size
)
23825 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
23826 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
23827 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
23831 /* Prefer out-of-line restore if it will exit. */
23832 if (info
->first_fp_reg_save
> 61)
23833 strategy
|= SAVE_INLINE_FPRS
;
23834 if (info
->first_gp_reg_save
> 29)
23836 if (info
->first_fp_reg_save
== 64)
23837 strategy
|= SAVE_INLINE_GPRS
;
23839 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
23841 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
23842 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
23845 else if (DEFAULT_ABI
== ABI_DARWIN
)
23847 if (info
->first_fp_reg_save
> 60)
23848 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
23849 if (info
->first_gp_reg_save
> 29)
23850 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
23851 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
23855 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23856 if ((flag_shrink_wrap_separate
&& optimize_function_for_speed_p (cfun
))
23857 || info
->first_fp_reg_save
> 61)
23858 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
23859 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
23860 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
23863 /* Don't bother to try to save things out-of-line if r11 is occupied
23864 by the static chain. It would require too much fiddling and the
23865 static chain is rarely used anyway. FPRs are saved w.r.t the stack
23866 pointer on Darwin, and AIX uses r1 or r12. */
23867 if (using_static_chain_p
23868 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
23869 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
23871 | SAVE_INLINE_VRS
);
23873 /* Don't ever restore fixed regs. That means we can't use the
23874 out-of-line register restore functions if a fixed reg is in the
23875 range of regs restored. */
23876 if (!(strategy
& REST_INLINE_FPRS
))
23877 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
23880 strategy
|= REST_INLINE_FPRS
;
23884 /* We can only use the out-of-line routines to restore fprs if we've
23885 saved all the registers from first_fp_reg_save in the prologue.
23886 Otherwise, we risk loading garbage. Of course, if we have saved
23887 out-of-line then we know we haven't skipped any fprs. */
23888 if ((strategy
& SAVE_INLINE_FPRS
)
23889 && !(strategy
& REST_INLINE_FPRS
))
23890 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
23891 if (!save_reg_p (i
))
23893 strategy
|= REST_INLINE_FPRS
;
23897 /* Similarly, for altivec regs. */
23898 if (!(strategy
& REST_INLINE_VRS
))
23899 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
23902 strategy
|= REST_INLINE_VRS
;
23906 if ((strategy
& SAVE_INLINE_VRS
)
23907 && !(strategy
& REST_INLINE_VRS
))
23908 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
23909 if (!save_reg_p (i
))
23911 strategy
|= REST_INLINE_VRS
;
23915 /* info->lr_save_p isn't yet set if the only reason lr needs to be
23916 saved is an out-of-line save or restore. Set up the value for
23917 the next test (excluding out-of-line gprs). */
23918 bool lr_save_p
= (info
->lr_save_p
23919 || !(strategy
& SAVE_INLINE_FPRS
)
23920 || !(strategy
& SAVE_INLINE_VRS
)
23921 || !(strategy
& REST_INLINE_FPRS
)
23922 || !(strategy
& REST_INLINE_VRS
));
23924 if (TARGET_MULTIPLE
23925 && !TARGET_POWERPC64
23926 && info
->first_gp_reg_save
< 31
23927 && !(flag_shrink_wrap
23928 && flag_shrink_wrap_separate
23929 && optimize_function_for_speed_p (cfun
)))
23932 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
23933 if (save_reg_p (i
))
23937 /* Don't use store multiple if only one reg needs to be
23938 saved. This can occur for example when the ABI_V4 pic reg
23939 (r30) needs to be saved to make calls, but r31 is not
23941 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
23944 /* Prefer store multiple for saves over out-of-line
23945 routines, since the store-multiple instruction will
23946 always be smaller. */
23947 strategy
|= SAVE_INLINE_GPRS
| SAVE_MULTIPLE
;
23949 /* The situation is more complicated with load multiple.
23950 We'd prefer to use the out-of-line routines for restores,
23951 since the "exit" out-of-line routines can handle the
23952 restore of LR and the frame teardown. However if doesn't
23953 make sense to use the out-of-line routine if that is the
23954 only reason we'd need to save LR, and we can't use the
23955 "exit" out-of-line gpr restore if we have saved some
23956 fprs; In those cases it is advantageous to use load
23957 multiple when available. */
23958 if (info
->first_fp_reg_save
!= 64 || !lr_save_p
)
23959 strategy
|= REST_INLINE_GPRS
| REST_MULTIPLE
;
23963 /* Using the "exit" out-of-line routine does not improve code size
23964 if using it would require lr to be saved and if only saving one
23966 else if (!lr_save_p
&& info
->first_gp_reg_save
> 29)
23967 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
23969 /* Don't ever restore fixed regs. */
23970 if ((strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
23971 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
23972 if (fixed_reg_p (i
))
23974 strategy
|= REST_INLINE_GPRS
;
23975 strategy
&= ~REST_MULTIPLE
;
23979 /* We can only use load multiple or the out-of-line routines to
23980 restore gprs if we've saved all the registers from
23981 first_gp_reg_save. Otherwise, we risk loading garbage.
23982 Of course, if we have saved out-of-line or used stmw then we know
23983 we haven't skipped any gprs. */
23984 if ((strategy
& (SAVE_INLINE_GPRS
| SAVE_MULTIPLE
)) == SAVE_INLINE_GPRS
23985 && (strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
23986 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
23987 if (!save_reg_p (i
))
23989 strategy
|= REST_INLINE_GPRS
;
23990 strategy
&= ~REST_MULTIPLE
;
23994 if (TARGET_ELF
&& TARGET_64BIT
)
23996 if (!(strategy
& SAVE_INLINE_FPRS
))
23997 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
23998 else if (!(strategy
& SAVE_INLINE_GPRS
)
23999 && info
->first_fp_reg_save
== 64)
24000 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
24002 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
24003 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
24005 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
24006 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
24011 /* Calculate the stack information for the current function. This is
24012 complicated by having two separate calling sequences, the AIX calling
24013 sequence and the V.4 calling sequence.
24015 AIX (and Darwin/Mac OS X) stack frames look like:
24017 SP----> +---------------------------------------+
24018 | back chain to caller | 0 0
24019 +---------------------------------------+
24020 | saved CR | 4 8 (8-11)
24021 +---------------------------------------+
24023 +---------------------------------------+
24024 | reserved for compilers | 12 24
24025 +---------------------------------------+
24026 | reserved for binders | 16 32
24027 +---------------------------------------+
24028 | saved TOC pointer | 20 40
24029 +---------------------------------------+
24030 | Parameter save area (+padding*) (P) | 24 48
24031 +---------------------------------------+
24032 | Alloca space (A) | 24+P etc.
24033 +---------------------------------------+
24034 | Local variable space (L) | 24+P+A
24035 +---------------------------------------+
24036 | Float/int conversion temporary (X) | 24+P+A+L
24037 +---------------------------------------+
24038 | Save area for AltiVec registers (W) | 24+P+A+L+X
24039 +---------------------------------------+
24040 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24041 +---------------------------------------+
24042 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24043 +---------------------------------------+
24044 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24045 +---------------------------------------+
24046 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24047 +---------------------------------------+
24048 old SP->| back chain to caller's caller |
24049 +---------------------------------------+
24051 * If the alloca area is present, the parameter save area is
24052 padded so that the former starts 16-byte aligned.
24054 The required alignment for AIX configurations is two words (i.e., 8
24057 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24059 SP----> +---------------------------------------+
24060 | Back chain to caller | 0
24061 +---------------------------------------+
24062 | Save area for CR | 8
24063 +---------------------------------------+
24065 +---------------------------------------+
24066 | Saved TOC pointer | 24
24067 +---------------------------------------+
24068 | Parameter save area (+padding*) (P) | 32
24069 +---------------------------------------+
24070 | Alloca space (A) | 32+P
24071 +---------------------------------------+
24072 | Local variable space (L) | 32+P+A
24073 +---------------------------------------+
24074 | Save area for AltiVec registers (W) | 32+P+A+L
24075 +---------------------------------------+
24076 | AltiVec alignment padding (Y) | 32+P+A+L+W
24077 +---------------------------------------+
24078 | Save area for GP registers (G) | 32+P+A+L+W+Y
24079 +---------------------------------------+
24080 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24081 +---------------------------------------+
24082 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24083 +---------------------------------------+
24085 * If the alloca area is present, the parameter save area is
24086 padded so that the former starts 16-byte aligned.
24088 V.4 stack frames look like:
24090 SP----> +---------------------------------------+
24091 | back chain to caller | 0
24092 +---------------------------------------+
24093 | caller's saved LR | 4
24094 +---------------------------------------+
24095 | Parameter save area (+padding*) (P) | 8
24096 +---------------------------------------+
24097 | Alloca space (A) | 8+P
24098 +---------------------------------------+
24099 | Varargs save area (V) | 8+P+A
24100 +---------------------------------------+
24101 | Local variable space (L) | 8+P+A+V
24102 +---------------------------------------+
24103 | Float/int conversion temporary (X) | 8+P+A+V+L
24104 +---------------------------------------+
24105 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24106 +---------------------------------------+
24107 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24108 +---------------------------------------+
24109 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24110 +---------------------------------------+
24111 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24112 +---------------------------------------+
24113 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24114 +---------------------------------------+
24115 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24116 +---------------------------------------+
24117 old SP->| back chain to caller's caller |
24118 +---------------------------------------+
24120 * If the alloca area is present and the required alignment is
24121 16 bytes, the parameter save area is padded so that the
24122 alloca area starts 16-byte aligned.
24124 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24125 given. (But note below and in sysv4.h that we require only 8 and
24126 may round up the size of our stack frame anyways. The historical
24127 reason is early versions of powerpc-linux which didn't properly
24128 align the stack at program startup. A happy side-effect is that
24129 -mno-eabi libraries can be used with -meabi programs.)
24131 The EABI configuration defaults to the V.4 layout. However,
24132 the stack alignment requirements may differ. If -mno-eabi is not
24133 given, the required stack alignment is 8 bytes; if -mno-eabi is
24134 given, the required alignment is 16 bytes. (But see V.4 comment
24137 #ifndef ABI_STACK_BOUNDARY
24138 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24141 static rs6000_stack_t
*
24142 rs6000_stack_info (void)
24144 /* We should never be called for thunks, we are not set up for that. */
24145 gcc_assert (!cfun
->is_thunk
);
24147 rs6000_stack_t
*info
= &stack_info
;
24148 int reg_size
= TARGET_32BIT
? 4 : 8;
24153 HOST_WIDE_INT non_fixed_size
;
24154 bool using_static_chain_p
;
24156 if (reload_completed
&& info
->reload_completed
)
24159 memset (info
, 0, sizeof (*info
));
24160 info
->reload_completed
= reload_completed
;
24162 /* Select which calling sequence. */
24163 info
->abi
= DEFAULT_ABI
;
24165 /* Calculate which registers need to be saved & save area size. */
24166 info
->first_gp_reg_save
= first_reg_to_save ();
24167 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24168 even if it currently looks like we won't. Reload may need it to
24169 get at a constant; if so, it will have already created a constant
24170 pool entry for it. */
24171 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
24172 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
24173 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
24174 && crtl
->uses_const_pool
24175 && info
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
24176 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
24178 first_gp
= info
->first_gp_reg_save
;
24180 info
->gp_size
= reg_size
* (32 - first_gp
);
24182 info
->first_fp_reg_save
= first_fp_reg_to_save ();
24183 info
->fp_size
= 8 * (64 - info
->first_fp_reg_save
);
24185 info
->first_altivec_reg_save
= first_altivec_reg_to_save ();
24186 info
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
24187 - info
->first_altivec_reg_save
);
24189 /* Does this function call anything? */
24190 info
->calls_p
= (!crtl
->is_leaf
|| cfun
->machine
->ra_needs_full_frame
);
24192 /* Determine if we need to save the condition code registers. */
24193 if (save_reg_p (CR2_REGNO
)
24194 || save_reg_p (CR3_REGNO
)
24195 || save_reg_p (CR4_REGNO
))
24197 info
->cr_save_p
= 1;
24198 if (DEFAULT_ABI
== ABI_V4
)
24199 info
->cr_size
= reg_size
;
24202 /* If the current function calls __builtin_eh_return, then we need
24203 to allocate stack space for registers that will hold data for
24204 the exception handler. */
24205 if (crtl
->calls_eh_return
)
24208 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
24211 ehrd_size
= i
* UNITS_PER_WORD
;
24216 /* In the ELFv2 ABI, we also need to allocate space for separate
24217 CR field save areas if the function calls __builtin_eh_return. */
24218 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24220 /* This hard-codes that we have three call-saved CR fields. */
24221 ehcr_size
= 3 * reg_size
;
24222 /* We do *not* use the regular CR save mechanism. */
24223 info
->cr_save_p
= 0;
24228 /* Determine various sizes. */
24229 info
->reg_size
= reg_size
;
24230 info
->fixed_size
= RS6000_SAVE_AREA
;
24231 info
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
24232 if (cfun
->calls_alloca
)
24234 RS6000_ALIGN (crtl
->outgoing_args_size
+ info
->fixed_size
,
24235 STACK_BOUNDARY
/ BITS_PER_UNIT
) - info
->fixed_size
;
24237 info
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
24238 TARGET_ALTIVEC
? 16 : 8);
24239 if (FRAME_GROWS_DOWNWARD
)
24241 += RS6000_ALIGN (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
,
24242 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
24243 - (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
);
24245 if (TARGET_ALTIVEC_ABI
)
24246 info
->vrsave_mask
= compute_vrsave_mask ();
24248 if (TARGET_ALTIVEC_VRSAVE
&& info
->vrsave_mask
)
24249 info
->vrsave_size
= 4;
24251 compute_save_world_info (info
);
24253 /* Calculate the offsets. */
24254 switch (DEFAULT_ABI
)
24258 gcc_unreachable ();
24263 info
->fp_save_offset
= -info
->fp_size
;
24264 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24266 if (TARGET_ALTIVEC_ABI
)
24268 info
->vrsave_save_offset
= info
->gp_save_offset
- info
->vrsave_size
;
24270 /* Align stack so vector save area is on a quadword boundary.
24271 The padding goes above the vectors. */
24272 if (info
->altivec_size
!= 0)
24273 info
->altivec_padding_size
= info
->vrsave_save_offset
& 0xF;
24275 info
->altivec_save_offset
= info
->vrsave_save_offset
24276 - info
->altivec_padding_size
24277 - info
->altivec_size
;
24278 gcc_assert (info
->altivec_size
== 0
24279 || info
->altivec_save_offset
% 16 == 0);
24281 /* Adjust for AltiVec case. */
24282 info
->ehrd_offset
= info
->altivec_save_offset
- ehrd_size
;
24285 info
->ehrd_offset
= info
->gp_save_offset
- ehrd_size
;
24287 info
->ehcr_offset
= info
->ehrd_offset
- ehcr_size
;
24288 info
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
24289 info
->lr_save_offset
= 2*reg_size
;
24293 info
->fp_save_offset
= -info
->fp_size
;
24294 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24295 info
->cr_save_offset
= info
->gp_save_offset
- info
->cr_size
;
24297 if (TARGET_ALTIVEC_ABI
)
24299 info
->vrsave_save_offset
= info
->cr_save_offset
- info
->vrsave_size
;
24301 /* Align stack so vector save area is on a quadword boundary. */
24302 if (info
->altivec_size
!= 0)
24303 info
->altivec_padding_size
= 16 - (-info
->vrsave_save_offset
% 16);
24305 info
->altivec_save_offset
= info
->vrsave_save_offset
24306 - info
->altivec_padding_size
24307 - info
->altivec_size
;
24309 /* Adjust for AltiVec case. */
24310 info
->ehrd_offset
= info
->altivec_save_offset
;
24313 info
->ehrd_offset
= info
->cr_save_offset
;
24315 info
->ehrd_offset
-= ehrd_size
;
24316 info
->lr_save_offset
= reg_size
;
24319 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
24320 info
->save_size
= RS6000_ALIGN (info
->fp_size
24322 + info
->altivec_size
24323 + info
->altivec_padding_size
24327 + info
->vrsave_size
,
24330 non_fixed_size
= info
->vars_size
+ info
->parm_size
+ info
->save_size
;
24332 info
->total_size
= RS6000_ALIGN (non_fixed_size
+ info
->fixed_size
,
24333 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
24335 /* Determine if we need to save the link register. */
24337 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24339 && !TARGET_PROFILE_KERNEL
)
24340 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
24341 #ifdef TARGET_RELOCATABLE
24342 || (DEFAULT_ABI
== ABI_V4
24343 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
24344 && !constant_pool_empty_p ())
24346 || rs6000_ra_ever_killed ())
24347 info
->lr_save_p
= 1;
24349 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
24350 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
24351 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
24352 info
->savres_strategy
= rs6000_savres_strategy (info
, using_static_chain_p
);
24354 if (!(info
->savres_strategy
& SAVE_INLINE_GPRS
)
24355 || !(info
->savres_strategy
& SAVE_INLINE_FPRS
)
24356 || !(info
->savres_strategy
& SAVE_INLINE_VRS
)
24357 || !(info
->savres_strategy
& REST_INLINE_GPRS
)
24358 || !(info
->savres_strategy
& REST_INLINE_FPRS
)
24359 || !(info
->savres_strategy
& REST_INLINE_VRS
))
24360 info
->lr_save_p
= 1;
24362 if (info
->lr_save_p
)
24363 df_set_regs_ever_live (LR_REGNO
, true);
24365 /* Determine if we need to allocate any stack frame:
24367 For AIX we need to push the stack if a frame pointer is needed
24368 (because the stack might be dynamically adjusted), if we are
24369 debugging, if we make calls, or if the sum of fp_save, gp_save,
24370 and local variables are more than the space needed to save all
24371 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24372 + 18*8 = 288 (GPR13 reserved).
24374 For V.4 we don't have the stack cushion that AIX uses, but assume
24375 that the debugger can handle stackless frames. */
24380 else if (DEFAULT_ABI
== ABI_V4
)
24381 info
->push_p
= non_fixed_size
!= 0;
24383 else if (frame_pointer_needed
)
24386 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
24390 info
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
24396 debug_stack_info (rs6000_stack_t
*info
)
24398 const char *abi_string
;
24401 info
= rs6000_stack_info ();
24403 fprintf (stderr
, "\nStack information for function %s:\n",
24404 ((current_function_decl
&& DECL_NAME (current_function_decl
))
24405 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
24410 default: abi_string
= "Unknown"; break;
24411 case ABI_NONE
: abi_string
= "NONE"; break;
24412 case ABI_AIX
: abi_string
= "AIX"; break;
24413 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
24414 case ABI_DARWIN
: abi_string
= "Darwin"; break;
24415 case ABI_V4
: abi_string
= "V.4"; break;
24418 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
24420 if (TARGET_ALTIVEC_ABI
)
24421 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
24423 if (info
->first_gp_reg_save
!= 32)
24424 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
24426 if (info
->first_fp_reg_save
!= 64)
24427 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
24429 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
24430 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
24431 info
->first_altivec_reg_save
);
24433 if (info
->lr_save_p
)
24434 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
24436 if (info
->cr_save_p
)
24437 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
24439 if (info
->vrsave_mask
)
24440 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
24443 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
24446 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
24449 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
24452 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
24454 if (info
->altivec_size
)
24455 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
24456 info
->altivec_save_offset
);
24458 if (info
->vrsave_size
)
24459 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
24460 info
->vrsave_save_offset
);
24462 if (info
->lr_save_p
)
24463 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
24465 if (info
->cr_save_p
)
24466 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
24468 if (info
->varargs_save_offset
)
24469 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
24471 if (info
->total_size
)
24472 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
24475 if (info
->vars_size
)
24476 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
24479 if (info
->parm_size
)
24480 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
24482 if (info
->fixed_size
)
24483 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
24486 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
24489 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
24491 if (info
->altivec_size
)
24492 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
24494 if (info
->vrsave_size
)
24495 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
24497 if (info
->altivec_padding_size
)
24498 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
24499 info
->altivec_padding_size
);
24502 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
24504 if (info
->save_size
)
24505 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
24507 if (info
->reg_size
!= 4)
24508 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
24510 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
24512 fprintf (stderr
, "\n");
24516 rs6000_return_addr (int count
, rtx frame
)
24518 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24519 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24521 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
24523 cfun
->machine
->ra_needs_full_frame
= 1;
24526 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24527 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24528 frame
= stack_pointer_rtx
;
24529 rtx prev_frame_addr
= memory_address (Pmode
, frame
);
24530 rtx prev_frame
= copy_to_reg (gen_rtx_MEM (Pmode
, prev_frame_addr
));
24531 rtx lr_save_off
= plus_constant (Pmode
,
24532 prev_frame
, RETURN_ADDRESS_OFFSET
);
24533 rtx lr_save_addr
= memory_address (Pmode
, lr_save_off
);
24534 return gen_rtx_MEM (Pmode
, lr_save_addr
);
24537 cfun
->machine
->ra_need_lr
= 1;
24538 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
24541 /* Say whether a function is a candidate for sibcall handling or not. */
24544 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
24548 /* The sibcall epilogue may clobber the static chain register.
24549 ??? We could work harder and avoid that, but it's probably
24550 not worth the hassle in practice. */
24551 if (CALL_EXPR_STATIC_CHAIN (exp
))
24555 fntype
= TREE_TYPE (decl
);
24557 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
24559 /* We can't do it if the called function has more vector parameters
24560 than the current function; there's nowhere to put the VRsave code. */
24561 if (TARGET_ALTIVEC_ABI
24562 && TARGET_ALTIVEC_VRSAVE
24563 && !(decl
&& decl
== current_function_decl
))
24565 function_args_iterator args_iter
;
24569 /* Functions with vector parameters are required to have a
24570 prototype, so the argument type info must be available
24572 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
24573 if (TREE_CODE (type
) == VECTOR_TYPE
24574 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
24577 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
24578 if (TREE_CODE (type
) == VECTOR_TYPE
24579 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
24586 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24587 functions, because the callee may have a different TOC pointer to
24588 the caller and there's no way to ensure we restore the TOC when
24589 we return. With the secure-plt SYSV ABI we can't make non-local
24590 calls when -fpic/PIC because the plt call stubs use r30. */
24591 if (DEFAULT_ABI
== ABI_DARWIN
24592 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24594 && !DECL_EXTERNAL (decl
)
24595 && !DECL_WEAK (decl
)
24596 && (*targetm
.binds_local_p
) (decl
))
24597 || (DEFAULT_ABI
== ABI_V4
24598 && (!TARGET_SECURE_PLT
24601 && (*targetm
.binds_local_p
) (decl
)))))
24603 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
24605 if (!lookup_attribute ("longcall", attr_list
)
24606 || lookup_attribute ("shortcall", attr_list
))
24614 rs6000_ra_ever_killed (void)
24620 if (cfun
->is_thunk
)
24623 if (cfun
->machine
->lr_save_state
)
24624 return cfun
->machine
->lr_save_state
- 1;
24626 /* regs_ever_live has LR marked as used if any sibcalls are present,
24627 but this should not force saving and restoring in the
24628 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24629 clobbers LR, so that is inappropriate. */
24631 /* Also, the prologue can generate a store into LR that
24632 doesn't really count, like this:
24635 bcl to set PIC register
24639 When we're called from the epilogue, we need to avoid counting
24640 this as a store. */
24642 push_topmost_sequence ();
24643 top
= get_insns ();
24644 pop_topmost_sequence ();
24645 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
24647 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
24653 if (!SIBLING_CALL_P (insn
))
24656 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
24658 else if (set_of (reg
, insn
) != NULL_RTX
24659 && !prologue_epilogue_contains (insn
))
24666 /* Emit instructions needed to load the TOC register.
24667 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24668 a constant pool; or for SVR4 -fpic. */
24671 rs6000_emit_load_toc_table (int fromprolog
)
24674 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
24676 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
24679 rtx lab
, tmp1
, tmp2
, got
;
24681 lab
= gen_label_rtx ();
24682 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
24683 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
24686 got
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
24690 got
= rs6000_got_sym ();
24691 tmp1
= tmp2
= dest
;
24694 tmp1
= gen_reg_rtx (Pmode
);
24695 tmp2
= gen_reg_rtx (Pmode
);
24697 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
24698 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
24699 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
24700 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
24702 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
24704 emit_insn (gen_load_toc_v4_pic_si ());
24705 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
24707 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
24710 rtx temp0
= (fromprolog
24711 ? gen_rtx_REG (Pmode
, 0)
24712 : gen_reg_rtx (Pmode
));
24718 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
24719 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
24721 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
24722 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
24724 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
24725 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
24726 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
24732 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
24734 lab
= gen_label_rtx ();
24735 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
24736 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
24737 if (TARGET_LINK_STACK
)
24738 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
24739 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
24741 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
24743 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
24745 /* This is for AIX code running in non-PIC ELF32. */
24746 rtx realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
24749 emit_insn (gen_elf_high (dest
, realsym
));
24750 emit_insn (gen_elf_low (dest
, dest
, realsym
));
24754 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
24757 emit_insn (gen_load_toc_aix_si (dest
));
24759 emit_insn (gen_load_toc_aix_di (dest
));
24763 /* Emit instructions to restore the link register after determining where
24764 its value has been stored. */
24767 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
24769 rs6000_stack_t
*info
= rs6000_stack_info ();
24772 operands
[0] = source
;
24773 operands
[1] = scratch
;
24775 if (info
->lr_save_p
)
24777 rtx frame_rtx
= stack_pointer_rtx
;
24778 HOST_WIDE_INT sp_offset
= 0;
24781 if (frame_pointer_needed
24782 || cfun
->calls_alloca
24783 || info
->total_size
> 32767)
24785 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
24786 emit_move_insn (operands
[1], tmp
);
24787 frame_rtx
= operands
[1];
24789 else if (info
->push_p
)
24790 sp_offset
= info
->total_size
;
24792 tmp
= plus_constant (Pmode
, frame_rtx
,
24793 info
->lr_save_offset
+ sp_offset
);
24794 tmp
= gen_frame_mem (Pmode
, tmp
);
24795 emit_move_insn (tmp
, operands
[0]);
24798 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
24800 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24801 state of lr_save_p so any change from here on would be a bug. In
24802 particular, stop rs6000_ra_ever_killed from considering the SET
24803 of lr we may have added just above. */
24804 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
24807 static GTY(()) alias_set_type set
= -1;
24810 get_TOC_alias_set (void)
24813 set
= new_alias_set ();
24817 /* This returns nonzero if the current function uses the TOC. This is
24818 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24819 is generated by the ABI_V4 load_toc_* patterns.
24820 Return 2 instead of 1 if the load_toc_* pattern is in the function
24821 partition that doesn't start the function. */
24829 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
24833 rtx pat
= PATTERN (insn
);
24836 if (GET_CODE (pat
) == PARALLEL
)
24837 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
24839 rtx sub
= XVECEXP (pat
, 0, i
);
24840 if (GET_CODE (sub
) == USE
)
24842 sub
= XEXP (sub
, 0);
24843 if (GET_CODE (sub
) == UNSPEC
24844 && XINT (sub
, 1) == UNSPEC_TOC
)
24849 else if (crtl
->has_bb_partition
24851 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
24859 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
24861 rtx tocrel
, tocreg
, hi
;
24863 if (TARGET_DEBUG_ADDR
)
24865 if (GET_CODE (symbol
) == SYMBOL_REF
)
24866 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
24870 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
24871 GET_RTX_NAME (GET_CODE (symbol
)));
24872 debug_rtx (symbol
);
24876 if (!can_create_pseudo_p ())
24877 df_set_regs_ever_live (TOC_REGISTER
, true);
24879 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
24880 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
24881 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
24884 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
24885 if (largetoc_reg
!= NULL
)
24887 emit_move_insn (largetoc_reg
, hi
);
24890 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
24893 /* Issue assembly directives that create a reference to the given DWARF
24894 FRAME_TABLE_LABEL from the current function section. */
24896 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
24898 fprintf (asm_out_file
, "\t.ref %s\n",
24899 (* targetm
.strip_name_encoding
) (frame_table_label
));
24902 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
24903 and the change to the stack pointer. */
24906 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
24913 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
24914 if (hard_frame_needed
)
24915 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
24916 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
24917 || (hard_frame_needed
24918 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
24921 p
= rtvec_alloc (i
);
24924 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
24925 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
24928 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
24931 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
24932 and set the appropriate attributes for the generated insn. Return the
24933 first insn which adjusts the stack pointer or the last insn before
24934 the stack adjustment loop.
24936 SIZE_INT is used to create the CFI note for the allocation.
24938 SIZE_RTX is an rtx containing the size of the adjustment. Note that
24939 since stacks grow to lower addresses its runtime value is -SIZE_INT.
24941 ORIG_SP contains the backchain value that must be stored at *sp. */
24944 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int
, rtx orig_sp
)
24948 rtx size_rtx
= GEN_INT (-size_int
);
24949 if (size_int
> 32767)
24951 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
24952 /* Need a note here so that try_split doesn't get confused. */
24953 if (get_last_insn () == NULL_RTX
)
24954 emit_note (NOTE_INSN_DELETED
);
24955 insn
= emit_move_insn (tmp_reg
, size_rtx
);
24956 try_split (PATTERN (insn
), insn
, 0);
24957 size_rtx
= tmp_reg
;
24960 if (Pmode
== SImode
)
24961 insn
= emit_insn (gen_movsi_update_stack (stack_pointer_rtx
,
24966 insn
= emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx
,
24970 rtx par
= PATTERN (insn
);
24971 gcc_assert (GET_CODE (par
) == PARALLEL
);
24972 rtx set
= XVECEXP (par
, 0, 0);
24973 gcc_assert (GET_CODE (set
) == SET
);
24974 rtx mem
= SET_DEST (set
);
24975 gcc_assert (MEM_P (mem
));
24976 MEM_NOTRAP_P (mem
) = 1;
24977 set_mem_alias_set (mem
, get_frame_alias_set ());
24979 RTX_FRAME_RELATED_P (insn
) = 1;
24980 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
24981 gen_rtx_SET (stack_pointer_rtx
,
24982 gen_rtx_PLUS (Pmode
,
24984 GEN_INT (-size_int
))));
24986 /* Emit a blockage to ensure the allocation/probing insns are
24987 not optimized, combined, removed, etc. Add REG_STACK_CHECK
24988 note for similar reasons. */
24989 if (flag_stack_clash_protection
)
24991 add_reg_note (insn
, REG_STACK_CHECK
, const0_rtx
);
24992 emit_insn (gen_blockage ());
24998 static HOST_WIDE_INT
24999 get_stack_clash_protection_probe_interval (void)
25001 return (HOST_WIDE_INT_1U
25002 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
));
25005 static HOST_WIDE_INT
25006 get_stack_clash_protection_guard_size (void)
25008 return (HOST_WIDE_INT_1U
25009 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE
));
25012 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25013 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25015 COPY_REG, if non-null, should contain a copy of the original
25016 stack pointer at exit from this function.
25018 This is subtly different than the Ada probing in that it tries hard to
25019 prevent attacks that jump the stack guard. Thus it is never allowed to
25020 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25021 space without a suitable probe. */
25023 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size
,
25026 rtx orig_sp
= copy_reg
;
25028 HOST_WIDE_INT probe_interval
= get_stack_clash_protection_probe_interval ();
25030 /* Round the size down to a multiple of PROBE_INTERVAL. */
25031 HOST_WIDE_INT rounded_size
= ROUND_DOWN (orig_size
, probe_interval
);
25033 /* If explicitly requested,
25034 or the rounded size is not the same as the original size
25035 or the the rounded size is greater than a page,
25036 then we will need a copy of the original stack pointer. */
25037 if (rounded_size
!= orig_size
25038 || rounded_size
> probe_interval
25041 /* If the caller did not request a copy of the incoming stack
25042 pointer, then we use r0 to hold the copy. */
25044 orig_sp
= gen_rtx_REG (Pmode
, 0);
25045 emit_move_insn (orig_sp
, stack_pointer_rtx
);
25048 /* There's three cases here.
25050 One is a single probe which is the most common and most efficiently
25051 implemented as it does not have to have a copy of the original
25052 stack pointer if there are no residuals.
25054 Second is unrolled allocation/probes which we use if there's just
25055 a few of them. It needs to save the original stack pointer into a
25056 temporary for use as a source register in the allocation/probe.
25058 Last is a loop. This is the most uncommon case and least efficient. */
25059 rtx_insn
*retval
= NULL
;
25060 if (rounded_size
== probe_interval
)
25062 retval
= rs6000_emit_allocate_stack_1 (probe_interval
, stack_pointer_rtx
);
25064 dump_stack_clash_frame_info (PROBE_INLINE
, rounded_size
!= orig_size
);
25066 else if (rounded_size
<= 8 * probe_interval
)
25068 /* The ABI requires using the store with update insns to allocate
25069 space and store the backchain into the stack
25071 So we save the current stack pointer into a temporary, then
25072 emit the store-with-update insns to store the saved stack pointer
25073 into the right location in each new page. */
25074 for (int i
= 0; i
< rounded_size
; i
+= probe_interval
)
25077 = rs6000_emit_allocate_stack_1 (probe_interval
, orig_sp
);
25079 /* Save the first stack adjustment in RETVAL. */
25084 dump_stack_clash_frame_info (PROBE_INLINE
, rounded_size
!= orig_size
);
25088 /* Compute the ending address. */
25090 = copy_reg
? gen_rtx_REG (Pmode
, 0) : gen_rtx_REG (Pmode
, 12);
25091 rtx rs
= GEN_INT (-rounded_size
);
25093 if (add_operand (rs
, Pmode
))
25094 insn
= emit_insn (gen_add3_insn (end_addr
, stack_pointer_rtx
, rs
));
25097 emit_move_insn (end_addr
, GEN_INT (-rounded_size
));
25098 insn
= emit_insn (gen_add3_insn (end_addr
, end_addr
,
25099 stack_pointer_rtx
));
25100 /* Describe the effect of INSN to the CFI engine. */
25101 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25102 gen_rtx_SET (end_addr
,
25103 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
25106 RTX_FRAME_RELATED_P (insn
) = 1;
25108 /* Emit the loop. */
25110 retval
= emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx
,
25111 stack_pointer_rtx
, orig_sp
,
25114 retval
= emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx
,
25115 stack_pointer_rtx
, orig_sp
,
25117 RTX_FRAME_RELATED_P (retval
) = 1;
25118 /* Describe the effect of INSN to the CFI engine. */
25119 add_reg_note (retval
, REG_FRAME_RELATED_EXPR
,
25120 gen_rtx_SET (stack_pointer_rtx
, end_addr
));
25122 /* Emit a blockage to ensure the allocation/probing insns are
25123 not optimized, combined, removed, etc. Other cases handle this
25124 within their call to rs6000_emit_allocate_stack_1. */
25125 emit_insn (gen_blockage ());
25127 dump_stack_clash_frame_info (PROBE_LOOP
, rounded_size
!= orig_size
);
25130 if (orig_size
!= rounded_size
)
25132 /* Allocate (and implicitly probe) any residual space. */
25133 HOST_WIDE_INT residual
= orig_size
- rounded_size
;
25135 rtx_insn
*insn
= rs6000_emit_allocate_stack_1 (residual
, orig_sp
);
25137 /* If the residual was the only allocation, then we can return the
25138 allocating insn. */
25146 /* Emit the correct code for allocating stack space, as insns.
25147 If COPY_REG, make sure a copy of the old frame is left there.
25148 The generated code may use hard register 0 as a temporary. */
25151 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
25154 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
25155 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
25156 rtx todec
= gen_int_mode (-size
, Pmode
);
25158 if (INTVAL (todec
) != -size
)
25160 warning (0, "stack frame too large");
25161 emit_insn (gen_trap ());
25165 if (crtl
->limit_stack
)
25167 if (REG_P (stack_limit_rtx
)
25168 && REGNO (stack_limit_rtx
) > 1
25169 && REGNO (stack_limit_rtx
) <= 31)
25172 = gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
));
25175 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
, const0_rtx
));
25177 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
25179 && DEFAULT_ABI
== ABI_V4
25182 rtx toload
= gen_rtx_CONST (VOIDmode
,
25183 gen_rtx_PLUS (Pmode
,
25187 emit_insn (gen_elf_high (tmp_reg
, toload
));
25188 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
25189 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
25193 warning (0, "stack limit expression is not supported");
25196 if (flag_stack_clash_protection
)
25198 if (size
< get_stack_clash_protection_guard_size ())
25199 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME
, true);
25202 rtx_insn
*insn
= rs6000_emit_probe_stack_range_stack_clash (size
,
25205 /* If we asked for a copy with an offset, then we still need add in
25207 if (copy_reg
&& copy_off
)
25208 emit_insn (gen_add3_insn (copy_reg
, copy_reg
, GEN_INT (copy_off
)));
25216 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
25218 emit_move_insn (copy_reg
, stack_reg
);
25221 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25222 it now and set the alias set/attributes. The above gen_*_update
25223 calls will generate a PARALLEL with the MEM set being the first
25225 insn
= rs6000_emit_allocate_stack_1 (size
, stack_reg
);
25229 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25231 #if PROBE_INTERVAL > 32768
25232 #error Cannot use indexed addressing mode for stack probing
25235 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25236 inclusive. These are offsets from the current stack pointer. */
25239 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
25241 /* See if we have a constant small number of probes to generate. If so,
25242 that's the easy case. */
25243 if (first
+ size
<= 32768)
25247 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25248 it exceeds SIZE. If only one probe is needed, this will not
25249 generate any code. Then probe at FIRST + SIZE. */
25250 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
25251 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25254 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25258 /* Otherwise, do the same as above, but in a loop. Note that we must be
25259 extra careful with variables wrapping around because we might be at
25260 the very top (or the very bottom) of the address space and we have
25261 to be able to handle this case properly; in particular, we use an
25262 equality test for the loop condition. */
25265 HOST_WIDE_INT rounded_size
;
25266 rtx r12
= gen_rtx_REG (Pmode
, 12);
25267 rtx r0
= gen_rtx_REG (Pmode
, 0);
25269 /* Sanity check for the addressing mode we're going to use. */
25270 gcc_assert (first
<= 32768);
25272 /* Step 1: round SIZE to the previous multiple of the interval. */
25274 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
25277 /* Step 2: compute initial and final value of the loop counter. */
25279 /* TEST_ADDR = SP + FIRST. */
25280 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
25283 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25284 if (rounded_size
> 32768)
25286 emit_move_insn (r0
, GEN_INT (-rounded_size
));
25287 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
25290 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
25294 /* Step 3: the loop
25298 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25301 while (TEST_ADDR != LAST_ADDR)
25303 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25304 until it is equal to ROUNDED_SIZE. */
25307 emit_insn (gen_probe_stack_rangedi (r12
, r12
, stack_pointer_rtx
, r0
));
25309 emit_insn (gen_probe_stack_rangesi (r12
, r12
, stack_pointer_rtx
, r0
));
25312 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25313 that SIZE is equal to ROUNDED_SIZE. */
25315 if (size
!= rounded_size
)
25316 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
25320 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25321 addresses, not offsets. */
25323 static const char *
25324 output_probe_stack_range_1 (rtx reg1
, rtx reg2
)
25326 static int labelno
= 0;
25330 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
25333 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
25335 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25337 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
25338 output_asm_insn ("addi %0,%0,%1", xops
);
25340 /* Probe at TEST_ADDR. */
25341 xops
[1] = gen_rtx_REG (Pmode
, 0);
25342 output_asm_insn ("stw %1,0(%0)", xops
);
25344 /* Test if TEST_ADDR == LAST_ADDR. */
25347 output_asm_insn ("cmpd 0,%0,%1", xops
);
25349 output_asm_insn ("cmpw 0,%0,%1", xops
);
25352 fputs ("\tbne 0,", asm_out_file
);
25353 assemble_name_raw (asm_out_file
, loop_lab
);
25354 fputc ('\n', asm_out_file
);
25359 /* This function is called when rs6000_frame_related is processing
25360 SETs within a PARALLEL, and returns whether the REGNO save ought to
25361 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25362 for out-of-line register save functions, store multiple, and the
25363 Darwin world_save. They may contain registers that don't really
25367 interesting_frame_related_regno (unsigned int regno
)
25369 /* Saves apparently of r0 are actually saving LR. It doesn't make
25370 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25371 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25372 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25373 as frame related. */
25376 /* If we see CR2 then we are here on a Darwin world save. Saves of
25377 CR2 signify the whole CR is being saved. This is a long-standing
25378 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25379 that CR needs to be saved. */
25380 if (regno
== CR2_REGNO
)
25382 /* Omit frame info for any user-defined global regs. If frame info
25383 is supplied for them, frame unwinding will restore a user reg.
25384 Also omit frame info for any reg we don't need to save, as that
25385 bloats frame info and can cause problems with shrink wrapping.
25386 Since global regs won't be seen as needing to be saved, both of
25387 these conditions are covered by save_reg_p. */
25388 return save_reg_p (regno
);
25391 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25392 addresses, not offsets.
25394 REG2 contains the backchain that must be stored into *sp at each allocation.
25396 This is subtly different than the Ada probing above in that it tries hard
25397 to prevent attacks that jump the stack guard. Thus, it is never allowed
25398 to allocate more than PROBE_INTERVAL bytes of stack space without a
25401 static const char *
25402 output_probe_stack_range_stack_clash (rtx reg1
, rtx reg2
, rtx reg3
)
25404 static int labelno
= 0;
25408 HOST_WIDE_INT probe_interval
= get_stack_clash_protection_probe_interval ();
25410 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
25412 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
25414 /* This allocates and probes. */
25417 xops
[2] = GEN_INT (-probe_interval
);
25419 output_asm_insn ("stdu %1,%2(%0)", xops
);
25421 output_asm_insn ("stwu %1,%2(%0)", xops
);
25423 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25427 output_asm_insn ("cmpd 0,%0,%1", xops
);
25429 output_asm_insn ("cmpw 0,%0,%1", xops
);
25431 fputs ("\tbne 0,", asm_out_file
);
25432 assemble_name_raw (asm_out_file
, loop_lab
);
25433 fputc ('\n', asm_out_file
);
25438 /* Wrapper around the output_probe_stack_range routines. */
25440 output_probe_stack_range (rtx reg1
, rtx reg2
, rtx reg3
)
25442 if (flag_stack_clash_protection
)
25443 return output_probe_stack_range_stack_clash (reg1
, reg2
, reg3
);
25445 return output_probe_stack_range_1 (reg1
, reg3
);
25448 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25449 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25450 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25451 deduce these equivalences by itself so it wasn't necessary to hold
25452 its hand so much. Don't be tempted to always supply d2_f_d_e with
25453 the actual cfa register, ie. r31 when we are using a hard frame
25454 pointer. That fails when saving regs off r1, and sched moves the
25455 r31 setup past the reg saves. */
25458 rs6000_frame_related (rtx_insn
*insn
, rtx reg
, HOST_WIDE_INT val
,
25459 rtx reg2
, rtx repl2
)
25463 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
25465 gcc_checking_assert (val
== 0);
25469 repl
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
25472 rtx pat
= PATTERN (insn
);
25473 if (!repl
&& !reg2
)
25475 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25476 if (GET_CODE (pat
) == PARALLEL
)
25477 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
25478 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
25480 rtx set
= XVECEXP (pat
, 0, i
);
25482 if (!REG_P (SET_SRC (set
))
25483 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
25484 RTX_FRAME_RELATED_P (set
) = 1;
25486 RTX_FRAME_RELATED_P (insn
) = 1;
25490 /* We expect that 'pat' is either a SET or a PARALLEL containing
25491 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25492 are important so they all have to be marked RTX_FRAME_RELATED_P.
25493 Call simplify_replace_rtx on the SETs rather than the whole insn
25494 so as to leave the other stuff alone (for example USE of r12). */
25496 set_used_flags (pat
);
25497 if (GET_CODE (pat
) == SET
)
25500 pat
= simplify_replace_rtx (pat
, reg
, repl
);
25502 pat
= simplify_replace_rtx (pat
, reg2
, repl2
);
25504 else if (GET_CODE (pat
) == PARALLEL
)
25506 pat
= shallow_copy_rtx (pat
);
25507 XVEC (pat
, 0) = shallow_copy_rtvec (XVEC (pat
, 0));
25509 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
25510 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
25512 rtx set
= XVECEXP (pat
, 0, i
);
25515 set
= simplify_replace_rtx (set
, reg
, repl
);
25517 set
= simplify_replace_rtx (set
, reg2
, repl2
);
25518 XVECEXP (pat
, 0, i
) = set
;
25520 if (!REG_P (SET_SRC (set
))
25521 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
25522 RTX_FRAME_RELATED_P (set
) = 1;
25526 gcc_unreachable ();
25528 RTX_FRAME_RELATED_P (insn
) = 1;
25529 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, copy_rtx_if_shared (pat
));
25534 /* Returns an insn that has a vrsave set operation with the
25535 appropriate CLOBBERs. */
25538 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
25541 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
25542 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
25545 = gen_rtx_SET (vrsave
,
25546 gen_rtx_UNSPEC_VOLATILE (SImode
,
25547 gen_rtvec (2, reg
, vrsave
),
25548 UNSPECV_SET_VRSAVE
));
25552 /* We need to clobber the registers in the mask so the scheduler
25553 does not move sets to VRSAVE before sets of AltiVec registers.
25555 However, if the function receives nonlocal gotos, reload will set
25556 all call saved registers live. We will end up with:
25558 (set (reg 999) (mem))
25559 (parallel [ (set (reg vrsave) (unspec blah))
25560 (clobber (reg 999))])
25562 The clobber will cause the store into reg 999 to be dead, and
25563 flow will attempt to delete an epilogue insn. In this case, we
25564 need an unspec use/set of the register. */
25566 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25567 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
25569 if (!epiloguep
|| call_used_regs
[i
])
25570 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
25571 gen_rtx_REG (V4SImode
, i
));
25574 rtx reg
= gen_rtx_REG (V4SImode
, i
);
25577 = gen_rtx_SET (reg
,
25578 gen_rtx_UNSPEC (V4SImode
,
25579 gen_rtvec (1, reg
), 27));
25583 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
25585 for (i
= 0; i
< nclobs
; ++i
)
25586 XVECEXP (insn
, 0, i
) = clobs
[i
];
25592 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
25596 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
25597 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
25598 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
25602 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
25604 return gen_frame_set (reg
, frame_reg
, offset
, false);
25608 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
25610 return gen_frame_set (reg
, frame_reg
, offset
, true);
25613 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25614 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25617 emit_frame_save (rtx frame_reg
, machine_mode mode
,
25618 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
25622 /* Some cases that need register indexed addressing. */
25623 gcc_checking_assert (!(TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
25624 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
)));
25626 reg
= gen_rtx_REG (mode
, regno
);
25627 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
25628 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
25629 NULL_RTX
, NULL_RTX
);
25632 /* Emit an offset memory reference suitable for a frame store, while
25633 converting to a valid addressing mode. */
25636 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
25638 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, GEN_INT (offset
)));
25641 #ifndef TARGET_FIX_AND_CONTINUE
25642 #define TARGET_FIX_AND_CONTINUE 0
25645 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25646 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25647 #define LAST_SAVRES_REGISTER 31
25648 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25659 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
25661 /* Temporary holding space for an out-of-line register save/restore
25663 static char savres_routine_name
[30];
25665 /* Return the name for an out-of-line register save/restore routine.
25666 We are saving/restoring GPRs if GPR is true. */
25669 rs6000_savres_routine_name (int regno
, int sel
)
25671 const char *prefix
= "";
25672 const char *suffix
= "";
25674 /* Different targets are supposed to define
25675 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25676 routine name could be defined with:
25678 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25680 This is a nice idea in practice, but in reality, things are
25681 complicated in several ways:
25683 - ELF targets have save/restore routines for GPRs.
25685 - PPC64 ELF targets have routines for save/restore of GPRs that
25686 differ in what they do with the link register, so having a set
25687 prefix doesn't work. (We only use one of the save routines at
25688 the moment, though.)
25690 - PPC32 elf targets have "exit" versions of the restore routines
25691 that restore the link register and can save some extra space.
25692 These require an extra suffix. (There are also "tail" versions
25693 of the restore routines and "GOT" versions of the save routines,
25694 but we don't generate those at present. Same problems apply,
25697 We deal with all this by synthesizing our own prefix/suffix and
25698 using that for the simple sprintf call shown above. */
25699 if (DEFAULT_ABI
== ABI_V4
)
25704 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
25705 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
25706 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
25707 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
25708 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25709 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
25713 if ((sel
& SAVRES_LR
))
25716 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25718 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25719 /* No out-of-line save/restore routines for GPRs on AIX. */
25720 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
25724 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
25725 prefix
= ((sel
& SAVRES_SAVE
)
25726 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
25727 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
25728 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
25730 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25731 if ((sel
& SAVRES_LR
))
25732 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
25736 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
25737 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
25740 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25741 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
25746 if (DEFAULT_ABI
== ABI_DARWIN
)
25748 /* The Darwin approach is (slightly) different, in order to be
25749 compatible with code generated by the system toolchain. There is a
25750 single symbol for the start of save sequence, and the code here
25751 embeds an offset into that code on the basis of the first register
25753 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
25754 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
25755 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
25756 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
25757 (regno
- 13) * 4, prefix
, regno
);
25758 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
25759 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
25760 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
25761 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25762 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
25763 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
25768 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
25770 return savres_routine_name
;
25773 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25774 We are saving/restoring GPRs if GPR is true. */
25777 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
25779 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
25780 ? info
->first_gp_reg_save
25781 : (sel
& SAVRES_REG
) == SAVRES_FPR
25782 ? info
->first_fp_reg_save
- 32
25783 : (sel
& SAVRES_REG
) == SAVRES_VR
25784 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
25789 /* Don't generate bogus routine names. */
25790 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
25791 && regno
<= LAST_SAVRES_REGISTER
25792 && select
>= 0 && select
<= 12);
25794 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
25800 name
= rs6000_savres_routine_name (regno
, sel
);
25802 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
25803 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
25804 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
25810 /* Emit a sequence of insns, including a stack tie if needed, for
25811 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25812 reset the stack pointer, but move the base of the frame into
25813 reg UPDT_REGNO for use by out-of-line register restore routines. */
25816 rs6000_emit_stack_reset (rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
25817 unsigned updt_regno
)
25819 /* If there is nothing to do, don't do anything. */
25820 if (frame_off
== 0 && REGNO (frame_reg_rtx
) == updt_regno
)
25823 rtx updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
25825 /* This blockage is needed so that sched doesn't decide to move
25826 the sp change before the register restores. */
25827 if (DEFAULT_ABI
== ABI_V4
)
25828 return emit_insn (gen_stack_restore_tie (updt_reg_rtx
, frame_reg_rtx
,
25829 GEN_INT (frame_off
)));
25831 /* If we are restoring registers out-of-line, we will be using the
25832 "exit" variants of the restore routines, which will reset the
25833 stack for us. But we do need to point updt_reg into the
25834 right place for those routines. */
25835 if (frame_off
!= 0)
25836 return emit_insn (gen_add3_insn (updt_reg_rtx
,
25837 frame_reg_rtx
, GEN_INT (frame_off
)));
25839 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
25844 /* Return the register number used as a pointer by out-of-line
25845 save/restore functions. */
25847 static inline unsigned
25848 ptr_regno_for_savres (int sel
)
25850 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25851 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
25852 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
25855 /* Construct a parallel rtx describing the effect of a call to an
25856 out-of-line register save/restore routine, and emit the insn
25857 or jump_insn as appropriate. */
25860 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
25861 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
25862 machine_mode reg_mode
, int sel
)
25865 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
25866 int reg_size
= GET_MODE_SIZE (reg_mode
);
25873 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
25874 ? info
->first_gp_reg_save
25875 : (sel
& SAVRES_REG
) == SAVRES_FPR
25876 ? info
->first_fp_reg_save
25877 : (sel
& SAVRES_REG
) == SAVRES_VR
25878 ? info
->first_altivec_reg_save
25880 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
25882 : (sel
& SAVRES_REG
) == SAVRES_FPR
25884 : (sel
& SAVRES_REG
) == SAVRES_VR
25885 ? LAST_ALTIVEC_REGNO
+ 1
25887 n_regs
= end_reg
- start_reg
;
25888 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
25889 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
25892 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
25893 RTVEC_ELT (p
, offset
++) = ret_rtx
;
25895 RTVEC_ELT (p
, offset
++)
25896 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
25898 sym
= rs6000_savres_routine_sym (info
, sel
);
25899 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
25901 use_reg
= ptr_regno_for_savres (sel
);
25902 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
25904 /* Vector regs are saved/restored using [reg+reg] addressing. */
25905 RTVEC_ELT (p
, offset
++)
25906 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
25907 RTVEC_ELT (p
, offset
++)
25908 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
25911 RTVEC_ELT (p
, offset
++)
25912 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
25914 for (i
= 0; i
< end_reg
- start_reg
; i
++)
25915 RTVEC_ELT (p
, i
+ offset
)
25916 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
25917 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
25918 (sel
& SAVRES_SAVE
) != 0);
25920 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
25921 RTVEC_ELT (p
, i
+ offset
)
25922 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
25924 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
25926 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
25928 insn
= emit_jump_insn (par
);
25929 JUMP_LABEL (insn
) = ret_rtx
;
25932 insn
= emit_insn (par
);
25936 /* Emit prologue code to store CR fields that need to be saved into REG. This
25937 function should only be called when moving the non-volatile CRs to REG, it
25938 is not a general purpose routine to move the entire set of CRs to REG.
25939 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
25943 rs6000_emit_prologue_move_from_cr (rtx reg
)
25945 /* Only the ELFv2 ABI allows storing only selected fields. */
25946 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
25948 int i
, cr_reg
[8], count
= 0;
25950 /* Collect CR fields that must be saved. */
25951 for (i
= 0; i
< 8; i
++)
25952 if (save_reg_p (CR0_REGNO
+ i
))
25953 cr_reg
[count
++] = i
;
25955 /* If it's just a single one, use mfcrf. */
25958 rtvec p
= rtvec_alloc (1);
25959 rtvec r
= rtvec_alloc (2);
25960 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
25961 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
25963 = gen_rtx_SET (reg
,
25964 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
25966 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25970 /* ??? It might be better to handle count == 2 / 3 cases here
25971 as well, using logical operations to combine the values. */
25974 emit_insn (gen_prologue_movesi_from_cr (reg
));
25977 /* Return whether the split-stack arg pointer (r12) is used. */
25980 split_stack_arg_pointer_used_p (void)
25982 /* If the pseudo holding the arg pointer is no longer a pseudo,
25983 then the arg pointer is used. */
25984 if (cfun
->machine
->split_stack_arg_pointer
!= NULL_RTX
25985 && (!REG_P (cfun
->machine
->split_stack_arg_pointer
)
25986 || (REGNO (cfun
->machine
->split_stack_arg_pointer
)
25987 < FIRST_PSEUDO_REGISTER
)))
25990 /* Unfortunately we also need to do some code scanning, since
25991 r12 may have been substituted for the pseudo. */
25993 basic_block bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
;
25994 FOR_BB_INSNS (bb
, insn
)
25995 if (NONDEBUG_INSN_P (insn
))
25997 /* A call destroys r12. */
26002 FOR_EACH_INSN_USE (use
, insn
)
26004 rtx x
= DF_REF_REG (use
);
26005 if (REG_P (x
) && REGNO (x
) == 12)
26009 FOR_EACH_INSN_DEF (def
, insn
)
26011 rtx x
= DF_REF_REG (def
);
26012 if (REG_P (x
) && REGNO (x
) == 12)
26016 return bitmap_bit_p (DF_LR_OUT (bb
), 12);
26019 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26022 rs6000_global_entry_point_needed_p (void)
26024 /* Only needed for the ELFv2 ABI. */
26025 if (DEFAULT_ABI
!= ABI_ELFv2
)
26028 /* With -msingle-pic-base, we assume the whole program shares the same
26029 TOC, so no global entry point prologues are needed anywhere. */
26030 if (TARGET_SINGLE_PIC_BASE
)
26033 /* Ensure we have a global entry point for thunks. ??? We could
26034 avoid that if the target routine doesn't need a global entry point,
26035 but we do not know whether this is the case at this point. */
26036 if (cfun
->is_thunk
)
26039 /* For regular functions, rs6000_emit_prologue sets this flag if the
26040 routine ever uses the TOC pointer. */
26041 return cfun
->machine
->r2_setup_needed
;
26044 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26046 rs6000_get_separate_components (void)
26048 rs6000_stack_t
*info
= rs6000_stack_info ();
26050 if (WORLD_SAVE_P (info
))
26053 gcc_assert (!(info
->savres_strategy
& SAVE_MULTIPLE
)
26054 && !(info
->savres_strategy
& REST_MULTIPLE
));
26056 /* Component 0 is the save/restore of LR (done via GPR0).
26057 Component 2 is the save of the TOC (GPR2).
26058 Components 13..31 are the save/restore of GPR13..GPR31.
26059 Components 46..63 are the save/restore of FPR14..FPR31. */
26061 cfun
->machine
->n_components
= 64;
26063 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26064 bitmap_clear (components
);
26066 int reg_size
= TARGET_32BIT
? 4 : 8;
26067 int fp_reg_size
= 8;
26069 /* The GPRs we need saved to the frame. */
26070 if ((info
->savres_strategy
& SAVE_INLINE_GPRS
)
26071 && (info
->savres_strategy
& REST_INLINE_GPRS
))
26073 int offset
= info
->gp_save_offset
;
26075 offset
+= info
->total_size
;
26077 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26079 if (IN_RANGE (offset
, -0x8000, 0x7fff)
26080 && save_reg_p (regno
))
26081 bitmap_set_bit (components
, regno
);
26083 offset
+= reg_size
;
26087 /* Don't mess with the hard frame pointer. */
26088 if (frame_pointer_needed
)
26089 bitmap_clear_bit (components
, HARD_FRAME_POINTER_REGNUM
);
26091 /* Don't mess with the fixed TOC register. */
26092 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
26093 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
26094 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
26095 bitmap_clear_bit (components
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
26097 /* The FPRs we need saved to the frame. */
26098 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
)
26099 && (info
->savres_strategy
& REST_INLINE_FPRS
))
26101 int offset
= info
->fp_save_offset
;
26103 offset
+= info
->total_size
;
26105 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26107 if (IN_RANGE (offset
, -0x8000, 0x7fff) && save_reg_p (regno
))
26108 bitmap_set_bit (components
, regno
);
26110 offset
+= fp_reg_size
;
26114 /* Optimize LR save and restore if we can. This is component 0. Any
26115 out-of-line register save/restore routines need LR. */
26116 if (info
->lr_save_p
26117 && !(flag_pic
&& (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
26118 && (info
->savres_strategy
& SAVE_INLINE_GPRS
)
26119 && (info
->savres_strategy
& REST_INLINE_GPRS
)
26120 && (info
->savres_strategy
& SAVE_INLINE_FPRS
)
26121 && (info
->savres_strategy
& REST_INLINE_FPRS
)
26122 && (info
->savres_strategy
& SAVE_INLINE_VRS
)
26123 && (info
->savres_strategy
& REST_INLINE_VRS
))
26125 int offset
= info
->lr_save_offset
;
26127 offset
+= info
->total_size
;
26128 if (IN_RANGE (offset
, -0x8000, 0x7fff))
26129 bitmap_set_bit (components
, 0);
26132 /* Optimize saving the TOC. This is component 2. */
26133 if (cfun
->machine
->save_toc_in_prologue
)
26134 bitmap_set_bit (components
, 2);
26139 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26141 rs6000_components_for_bb (basic_block bb
)
26143 rs6000_stack_t
*info
= rs6000_stack_info ();
26145 bitmap in
= DF_LIVE_IN (bb
);
26146 bitmap gen
= &DF_LIVE_BB_INFO (bb
)->gen
;
26147 bitmap kill
= &DF_LIVE_BB_INFO (bb
)->kill
;
26149 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26150 bitmap_clear (components
);
26152 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26155 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26156 if (bitmap_bit_p (in
, regno
)
26157 || bitmap_bit_p (gen
, regno
)
26158 || bitmap_bit_p (kill
, regno
))
26159 bitmap_set_bit (components
, regno
);
26162 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26163 if (bitmap_bit_p (in
, regno
)
26164 || bitmap_bit_p (gen
, regno
)
26165 || bitmap_bit_p (kill
, regno
))
26166 bitmap_set_bit (components
, regno
);
26168 /* The link register. */
26169 if (bitmap_bit_p (in
, LR_REGNO
)
26170 || bitmap_bit_p (gen
, LR_REGNO
)
26171 || bitmap_bit_p (kill
, LR_REGNO
))
26172 bitmap_set_bit (components
, 0);
26174 /* The TOC save. */
26175 if (bitmap_bit_p (in
, TOC_REGNUM
)
26176 || bitmap_bit_p (gen
, TOC_REGNUM
)
26177 || bitmap_bit_p (kill
, TOC_REGNUM
))
26178 bitmap_set_bit (components
, 2);
26183 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26185 rs6000_disqualify_components (sbitmap components
, edge e
,
26186 sbitmap edge_components
, bool /*is_prologue*/)
26188 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26189 live where we want to place that code. */
26190 if (bitmap_bit_p (edge_components
, 0)
26191 && bitmap_bit_p (DF_LIVE_IN (e
->dest
), 0))
26194 fprintf (dump_file
, "Disqualifying LR because GPR0 is live "
26195 "on entry to bb %d\n", e
->dest
->index
);
26196 bitmap_clear_bit (components
, 0);
26200 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26202 rs6000_emit_prologue_components (sbitmap components
)
26204 rs6000_stack_t
*info
= rs6000_stack_info ();
26205 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26206 ? HARD_FRAME_POINTER_REGNUM
26207 : STACK_POINTER_REGNUM
);
26209 machine_mode reg_mode
= Pmode
;
26210 int reg_size
= TARGET_32BIT
? 4 : 8;
26211 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26212 int fp_reg_size
= 8;
26214 /* Prologue for LR. */
26215 if (bitmap_bit_p (components
, 0))
26217 rtx lr
= gen_rtx_REG (reg_mode
, LR_REGNO
);
26218 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26219 rtx_insn
*insn
= emit_move_insn (reg
, lr
);
26220 RTX_FRAME_RELATED_P (insn
) = 1;
26221 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (reg
, lr
));
26223 int offset
= info
->lr_save_offset
;
26225 offset
+= info
->total_size
;
26227 insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26228 RTX_FRAME_RELATED_P (insn
) = 1;
26229 rtx mem
= copy_rtx (SET_DEST (single_set (insn
)));
26230 add_reg_note (insn
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, lr
));
26233 /* Prologue for TOC. */
26234 if (bitmap_bit_p (components
, 2))
26236 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
26237 rtx sp_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26238 emit_insn (gen_frame_store (reg
, sp_reg
, RS6000_TOC_SAVE_SLOT
));
26241 /* Prologue for the GPRs. */
26242 int offset
= info
->gp_save_offset
;
26244 offset
+= info
->total_size
;
26246 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26248 if (bitmap_bit_p (components
, i
))
26250 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26251 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26252 RTX_FRAME_RELATED_P (insn
) = 1;
26253 rtx set
= copy_rtx (single_set (insn
));
26254 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26257 offset
+= reg_size
;
26260 /* Prologue for the FPRs. */
26261 offset
= info
->fp_save_offset
;
26263 offset
+= info
->total_size
;
26265 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26267 if (bitmap_bit_p (components
, i
))
26269 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26270 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26271 RTX_FRAME_RELATED_P (insn
) = 1;
26272 rtx set
= copy_rtx (single_set (insn
));
26273 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26276 offset
+= fp_reg_size
;
26280 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26282 rs6000_emit_epilogue_components (sbitmap components
)
26284 rs6000_stack_t
*info
= rs6000_stack_info ();
26285 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26286 ? HARD_FRAME_POINTER_REGNUM
26287 : STACK_POINTER_REGNUM
);
26289 machine_mode reg_mode
= Pmode
;
26290 int reg_size
= TARGET_32BIT
? 4 : 8;
26292 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26293 int fp_reg_size
= 8;
26295 /* Epilogue for the FPRs. */
26296 int offset
= info
->fp_save_offset
;
26298 offset
+= info
->total_size
;
26300 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26302 if (bitmap_bit_p (components
, i
))
26304 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26305 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26306 RTX_FRAME_RELATED_P (insn
) = 1;
26307 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26310 offset
+= fp_reg_size
;
26313 /* Epilogue for the GPRs. */
26314 offset
= info
->gp_save_offset
;
26316 offset
+= info
->total_size
;
26318 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26320 if (bitmap_bit_p (components
, i
))
26322 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26323 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26324 RTX_FRAME_RELATED_P (insn
) = 1;
26325 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26328 offset
+= reg_size
;
26331 /* Epilogue for LR. */
26332 if (bitmap_bit_p (components
, 0))
26334 int offset
= info
->lr_save_offset
;
26336 offset
+= info
->total_size
;
26338 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26339 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26341 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
26342 insn
= emit_move_insn (lr
, reg
);
26343 RTX_FRAME_RELATED_P (insn
) = 1;
26344 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
26348 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26350 rs6000_set_handled_components (sbitmap components
)
26352 rs6000_stack_t
*info
= rs6000_stack_info ();
26354 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26355 if (bitmap_bit_p (components
, i
))
26356 cfun
->machine
->gpr_is_wrapped_separately
[i
] = true;
26358 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26359 if (bitmap_bit_p (components
, i
))
26360 cfun
->machine
->fpr_is_wrapped_separately
[i
- 32] = true;
26362 if (bitmap_bit_p (components
, 0))
26363 cfun
->machine
->lr_is_wrapped_separately
= true;
26365 if (bitmap_bit_p (components
, 2))
26366 cfun
->machine
->toc_is_wrapped_separately
= true;
26369 /* VRSAVE is a bit vector representing which AltiVec registers
26370 are used. The OS uses this to determine which vector
26371 registers to save on a context switch. We need to save
26372 VRSAVE on the stack frame, add whatever AltiVec registers we
26373 used in this function, and do the corresponding magic in the
26376 emit_vrsave_prologue (rs6000_stack_t
*info
, int save_regno
,
26377 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26379 /* Get VRSAVE into a GPR. */
26380 rtx reg
= gen_rtx_REG (SImode
, save_regno
);
26381 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
26383 emit_insn (gen_get_vrsave_internal (reg
));
26385 emit_insn (gen_rtx_SET (reg
, vrsave
));
26388 int offset
= info
->vrsave_save_offset
+ frame_off
;
26389 emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
26391 /* Include the registers in the mask. */
26392 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT (info
->vrsave_mask
)));
26394 emit_insn (generate_set_vrsave (reg
, info
, 0));
26397 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26398 called, it left the arg pointer to the old stack in r29. Otherwise, the
26399 arg pointer is the top of the current frame. */
26401 emit_split_stack_prologue (rs6000_stack_t
*info
, rtx_insn
*sp_adjust
,
26402 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26404 cfun
->machine
->split_stack_argp_used
= true;
26408 rtx r12
= gen_rtx_REG (Pmode
, 12);
26409 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26410 rtx set_r12
= gen_rtx_SET (r12
, sp_reg_rtx
);
26411 emit_insn_before (set_r12
, sp_adjust
);
26413 else if (frame_off
!= 0 || REGNO (frame_reg_rtx
) != 12)
26415 rtx r12
= gen_rtx_REG (Pmode
, 12);
26416 if (frame_off
== 0)
26417 emit_move_insn (r12
, frame_reg_rtx
);
26419 emit_insn (gen_add3_insn (r12
, frame_reg_rtx
, GEN_INT (frame_off
)));
26424 rtx r12
= gen_rtx_REG (Pmode
, 12);
26425 rtx r29
= gen_rtx_REG (Pmode
, 29);
26426 rtx cr7
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
26427 rtx not_more
= gen_label_rtx ();
26430 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
26431 gen_rtx_GEU (VOIDmode
, cr7
, const0_rtx
),
26432 gen_rtx_LABEL_REF (VOIDmode
, not_more
),
26434 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
26435 JUMP_LABEL (jump
) = not_more
;
26436 LABEL_NUSES (not_more
) += 1;
26437 emit_move_insn (r12
, r29
);
26438 emit_label (not_more
);
26442 /* Emit function prologue as insns. */
26445 rs6000_emit_prologue (void)
26447 rs6000_stack_t
*info
= rs6000_stack_info ();
26448 machine_mode reg_mode
= Pmode
;
26449 int reg_size
= TARGET_32BIT
? 4 : 8;
26450 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26451 int fp_reg_size
= 8;
26452 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26453 rtx frame_reg_rtx
= sp_reg_rtx
;
26454 unsigned int cr_save_regno
;
26455 rtx cr_save_rtx
= NULL_RTX
;
26458 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
26459 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
26460 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
26461 int using_split_stack
= (flag_split_stack
26462 && (lookup_attribute ("no_split_stack",
26463 DECL_ATTRIBUTES (cfun
->decl
))
26466 /* Offset to top of frame for frame_reg and sp respectively. */
26467 HOST_WIDE_INT frame_off
= 0;
26468 HOST_WIDE_INT sp_off
= 0;
26469 /* sp_adjust is the stack adjusting instruction, tracked so that the
26470 insn setting up the split-stack arg pointer can be emitted just
26471 prior to it, when r12 is not used here for other purposes. */
26472 rtx_insn
*sp_adjust
= 0;
26475 /* Track and check usage of r0, r11, r12. */
26476 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
26477 #define START_USE(R) do \
26479 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26480 reg_inuse |= 1 << (R); \
26482 #define END_USE(R) do \
26484 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26485 reg_inuse &= ~(1 << (R)); \
26487 #define NOT_INUSE(R) do \
26489 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26492 #define START_USE(R) do {} while (0)
26493 #define END_USE(R) do {} while (0)
26494 #define NOT_INUSE(R) do {} while (0)
26497 if (DEFAULT_ABI
== ABI_ELFv2
26498 && !TARGET_SINGLE_PIC_BASE
)
26500 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
26502 /* With -mminimal-toc we may generate an extra use of r2 below. */
26503 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
26504 && !constant_pool_empty_p ())
26505 cfun
->machine
->r2_setup_needed
= true;
26509 if (flag_stack_usage_info
)
26510 current_function_static_stack_size
= info
->total_size
;
26512 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
26514 HOST_WIDE_INT size
= info
->total_size
;
26516 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
26518 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
26519 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26520 size
- get_stack_check_protect ());
26523 rs6000_emit_probe_stack_range (get_stack_check_protect (), size
);
26526 if (TARGET_FIX_AND_CONTINUE
)
26528 /* gdb on darwin arranges to forward a function from the old
26529 address by modifying the first 5 instructions of the function
26530 to branch to the overriding function. This is necessary to
26531 permit function pointers that point to the old function to
26532 actually forward to the new function. */
26533 emit_insn (gen_nop ());
26534 emit_insn (gen_nop ());
26535 emit_insn (gen_nop ());
26536 emit_insn (gen_nop ());
26537 emit_insn (gen_nop ());
26540 /* Handle world saves specially here. */
26541 if (WORLD_SAVE_P (info
))
26548 /* save_world expects lr in r0. */
26549 reg0
= gen_rtx_REG (Pmode
, 0);
26550 if (info
->lr_save_p
)
26552 insn
= emit_move_insn (reg0
,
26553 gen_rtx_REG (Pmode
, LR_REGNO
));
26554 RTX_FRAME_RELATED_P (insn
) = 1;
26557 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26558 assumptions about the offsets of various bits of the stack
26560 gcc_assert (info
->gp_save_offset
== -220
26561 && info
->fp_save_offset
== -144
26562 && info
->lr_save_offset
== 8
26563 && info
->cr_save_offset
== 4
26566 && (!crtl
->calls_eh_return
26567 || info
->ehrd_offset
== -432)
26568 && info
->vrsave_save_offset
== -224
26569 && info
->altivec_save_offset
== -416);
26571 treg
= gen_rtx_REG (SImode
, 11);
26572 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
26574 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26575 in R11. It also clobbers R12, so beware! */
26577 /* Preserve CR2 for save_world prologues */
26579 sz
+= 32 - info
->first_gp_reg_save
;
26580 sz
+= 64 - info
->first_fp_reg_save
;
26581 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
26582 p
= rtvec_alloc (sz
);
26584 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
26585 gen_rtx_REG (SImode
,
26587 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
26588 gen_rtx_SYMBOL_REF (Pmode
,
26590 /* We do floats first so that the instruction pattern matches
26592 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
26594 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
26595 info
->first_fp_reg_save
+ i
),
26597 info
->fp_save_offset
+ frame_off
+ 8 * i
);
26598 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
26600 = gen_frame_store (gen_rtx_REG (V4SImode
,
26601 info
->first_altivec_reg_save
+ i
),
26603 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
26604 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26606 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26608 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
26610 /* CR register traditionally saved as CR2. */
26612 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
26613 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
26614 /* Explain about use of R0. */
26615 if (info
->lr_save_p
)
26617 = gen_frame_store (reg0
,
26618 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
26619 /* Explain what happens to the stack pointer. */
26621 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
26622 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
26625 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26626 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
26627 treg
, GEN_INT (-info
->total_size
));
26628 sp_off
= frame_off
= info
->total_size
;
26631 strategy
= info
->savres_strategy
;
26633 /* For V.4, update stack before we do any saving and set back pointer. */
26634 if (! WORLD_SAVE_P (info
)
26636 && (DEFAULT_ABI
== ABI_V4
26637 || crtl
->calls_eh_return
))
26639 bool need_r11
= (!(strategy
& SAVE_INLINE_FPRS
)
26640 || !(strategy
& SAVE_INLINE_GPRS
)
26641 || !(strategy
& SAVE_INLINE_VRS
));
26642 int ptr_regno
= -1;
26643 rtx ptr_reg
= NULL_RTX
;
26646 if (info
->total_size
< 32767)
26647 frame_off
= info
->total_size
;
26650 else if (info
->cr_save_p
26652 || info
->first_fp_reg_save
< 64
26653 || info
->first_gp_reg_save
< 32
26654 || info
->altivec_size
!= 0
26655 || info
->vrsave_size
!= 0
26656 || crtl
->calls_eh_return
)
26660 /* The prologue won't be saving any regs so there is no need
26661 to set up a frame register to access any frame save area.
26662 We also won't be using frame_off anywhere below, but set
26663 the correct value anyway to protect against future
26664 changes to this function. */
26665 frame_off
= info
->total_size
;
26667 if (ptr_regno
!= -1)
26669 /* Set up the frame offset to that needed by the first
26670 out-of-line save function. */
26671 START_USE (ptr_regno
);
26672 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26673 frame_reg_rtx
= ptr_reg
;
26674 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
26675 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
26676 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
26677 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
26678 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
26679 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
26680 frame_off
= -ptr_off
;
26682 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
26684 if (REGNO (frame_reg_rtx
) == 12)
26686 sp_off
= info
->total_size
;
26687 if (frame_reg_rtx
!= sp_reg_rtx
)
26688 rs6000_emit_stack_tie (frame_reg_rtx
, false);
26691 /* If we use the link register, get it into r0. */
26692 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
26693 && !cfun
->machine
->lr_is_wrapped_separately
)
26695 rtx addr
, reg
, mem
;
26697 reg
= gen_rtx_REG (Pmode
, 0);
26699 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
26700 RTX_FRAME_RELATED_P (insn
) = 1;
26702 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
26703 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
26705 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
26706 GEN_INT (info
->lr_save_offset
+ frame_off
));
26707 mem
= gen_rtx_MEM (Pmode
, addr
);
26708 /* This should not be of rs6000_sr_alias_set, because of
26709 __builtin_return_address. */
26711 insn
= emit_move_insn (mem
, reg
);
26712 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
26713 NULL_RTX
, NULL_RTX
);
26718 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26719 r12 will be needed by out-of-line gpr save. */
26720 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26721 && !(strategy
& (SAVE_INLINE_GPRS
26722 | SAVE_NOINLINE_GPRS_SAVES_LR
))
26724 if (!WORLD_SAVE_P (info
)
26726 && REGNO (frame_reg_rtx
) != cr_save_regno
26727 && !(using_static_chain_p
&& cr_save_regno
== 11)
26728 && !(using_split_stack
&& cr_save_regno
== 12 && sp_adjust
))
26730 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
26731 START_USE (cr_save_regno
);
26732 rs6000_emit_prologue_move_from_cr (cr_save_rtx
);
26735 /* Do any required saving of fpr's. If only one or two to save, do
26736 it ourselves. Otherwise, call function. */
26737 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
26739 int offset
= info
->fp_save_offset
+ frame_off
;
26740 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26743 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
26744 emit_frame_save (frame_reg_rtx
, fp_reg_mode
, i
, offset
,
26745 sp_off
- frame_off
);
26747 offset
+= fp_reg_size
;
26750 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
26752 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
26753 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
26754 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
26755 rtx ptr_reg
= frame_reg_rtx
;
26757 if (REGNO (frame_reg_rtx
) == ptr_regno
)
26758 gcc_checking_assert (frame_off
== 0);
26761 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26762 NOT_INUSE (ptr_regno
);
26763 emit_insn (gen_add3_insn (ptr_reg
,
26764 frame_reg_rtx
, GEN_INT (frame_off
)));
26766 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
26767 info
->fp_save_offset
,
26768 info
->lr_save_offset
,
26770 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
26771 NULL_RTX
, NULL_RTX
);
26776 /* Save GPRs. This is done as a PARALLEL if we are using
26777 the store-multiple instructions. */
26778 if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
26780 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
26781 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
26782 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
26783 rtx ptr_reg
= frame_reg_rtx
;
26784 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
26785 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
26788 if (ptr_regno
== 12)
26791 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26793 /* Need to adjust r11 (r12) if we saved any FPRs. */
26794 if (end_save
+ frame_off
!= 0)
26796 rtx offset
= GEN_INT (end_save
+ frame_off
);
26799 frame_off
= -end_save
;
26801 NOT_INUSE (ptr_regno
);
26802 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
26804 else if (!ptr_set_up
)
26806 NOT_INUSE (ptr_regno
);
26807 emit_move_insn (ptr_reg
, frame_reg_rtx
);
26809 ptr_off
= -end_save
;
26810 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
26811 info
->gp_save_offset
+ ptr_off
,
26812 info
->lr_save_offset
+ ptr_off
,
26814 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
26815 NULL_RTX
, NULL_RTX
);
26819 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_MULTIPLE
))
26823 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
26824 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26826 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26828 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
26829 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26830 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
26831 NULL_RTX
, NULL_RTX
);
26833 else if (!WORLD_SAVE_P (info
))
26835 int offset
= info
->gp_save_offset
+ frame_off
;
26836 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26839 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
26840 emit_frame_save (frame_reg_rtx
, reg_mode
, i
, offset
,
26841 sp_off
- frame_off
);
26843 offset
+= reg_size
;
26847 if (crtl
->calls_eh_return
)
26854 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
26855 if (regno
== INVALID_REGNUM
)
26859 p
= rtvec_alloc (i
);
26863 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
26864 if (regno
== INVALID_REGNUM
)
26868 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
26870 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
26871 RTVEC_ELT (p
, i
) = set
;
26872 RTX_FRAME_RELATED_P (set
) = 1;
26875 insn
= emit_insn (gen_blockage ());
26876 RTX_FRAME_RELATED_P (insn
) = 1;
26877 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
26880 /* In AIX ABI we need to make sure r2 is really saved. */
26881 if (TARGET_AIX
&& crtl
->calls_eh_return
)
26883 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
26884 rtx join_insn
, note
;
26885 rtx_insn
*save_insn
;
26886 long toc_restore_insn
;
26888 tmp_reg
= gen_rtx_REG (Pmode
, 11);
26889 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
26890 if (using_static_chain_p
)
26893 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
26897 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
26898 /* Peek at instruction to which this function returns. If it's
26899 restoring r2, then we know we've already saved r2. We can't
26900 unconditionally save r2 because the value we have will already
26901 be updated if we arrived at this function via a plt call or
26902 toc adjusting stub. */
26903 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
26904 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
26905 + RS6000_TOC_SAVE_SLOT
);
26906 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
26907 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
26908 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
26909 validate_condition_mode (EQ
, CCUNSmode
);
26910 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
26911 emit_insn (gen_rtx_SET (compare_result
,
26912 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
26913 toc_save_done
= gen_label_rtx ();
26914 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
26915 gen_rtx_EQ (VOIDmode
, compare_result
,
26917 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
26919 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
26920 JUMP_LABEL (jump
) = toc_save_done
;
26921 LABEL_NUSES (toc_save_done
) += 1;
26923 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
26924 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
26925 sp_off
- frame_off
);
26927 emit_label (toc_save_done
);
26929 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
26930 have a CFG that has different saves along different paths.
26931 Move the note to a dummy blockage insn, which describes that
26932 R2 is unconditionally saved after the label. */
26933 /* ??? An alternate representation might be a special insn pattern
26934 containing both the branch and the store. That might let the
26935 code that minimizes the number of DW_CFA_advance opcodes better
26936 freedom in placing the annotations. */
26937 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
26939 remove_note (save_insn
, note
);
26941 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
26942 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
26943 RTX_FRAME_RELATED_P (save_insn
) = 0;
26945 join_insn
= emit_insn (gen_blockage ());
26946 REG_NOTES (join_insn
) = note
;
26947 RTX_FRAME_RELATED_P (join_insn
) = 1;
26949 if (using_static_chain_p
)
26951 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
26958 /* Save CR if we use any that must be preserved. */
26959 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
26961 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
26962 GEN_INT (info
->cr_save_offset
+ frame_off
));
26963 rtx mem
= gen_frame_mem (SImode
, addr
);
26965 /* If we didn't copy cr before, do so now using r0. */
26966 if (cr_save_rtx
== NULL_RTX
)
26969 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
26970 rs6000_emit_prologue_move_from_cr (cr_save_rtx
);
26973 /* Saving CR requires a two-instruction sequence: one instruction
26974 to move the CR to a general-purpose register, and a second
26975 instruction that stores the GPR to memory.
26977 We do not emit any DWARF CFI records for the first of these,
26978 because we cannot properly represent the fact that CR is saved in
26979 a register. One reason is that we cannot express that multiple
26980 CR fields are saved; another reason is that on 64-bit, the size
26981 of the CR register in DWARF (4 bytes) differs from the size of
26982 a general-purpose register.
26984 This means if any intervening instruction were to clobber one of
26985 the call-saved CR fields, we'd have incorrect CFI. To prevent
26986 this from happening, we mark the store to memory as a use of
26987 those CR fields, which prevents any such instruction from being
26988 scheduled in between the two instructions. */
26993 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
26994 for (i
= 0; i
< 8; i
++)
26995 if (save_reg_p (CR0_REGNO
+ i
))
26996 crsave_v
[n_crsave
++]
26997 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
26999 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
27000 gen_rtvec_v (n_crsave
, crsave_v
)));
27001 END_USE (REGNO (cr_save_rtx
));
27003 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27004 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27005 so we need to construct a frame expression manually. */
27006 RTX_FRAME_RELATED_P (insn
) = 1;
27008 /* Update address to be stack-pointer relative, like
27009 rs6000_frame_related would do. */
27010 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
27011 GEN_INT (info
->cr_save_offset
+ sp_off
));
27012 mem
= gen_frame_mem (SImode
, addr
);
27014 if (DEFAULT_ABI
== ABI_ELFv2
)
27016 /* In the ELFv2 ABI we generate separate CFI records for each
27017 CR field that was actually saved. They all point to the
27018 same 32-bit stack slot. */
27022 for (i
= 0; i
< 8; i
++)
27023 if (save_reg_p (CR0_REGNO
+ i
))
27026 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27028 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
27032 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27033 gen_rtx_PARALLEL (VOIDmode
,
27034 gen_rtvec_v (n_crframe
, crframe
)));
27038 /* In other ABIs, by convention, we use a single CR regnum to
27039 represent the fact that all call-saved CR fields are saved.
27040 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27041 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
27042 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
27046 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27047 *separate* slots if the routine calls __builtin_eh_return, so
27048 that they can be independently restored by the unwinder. */
27049 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
27051 int i
, cr_off
= info
->ehcr_offset
;
27054 /* ??? We might get better performance by using multiple mfocrf
27056 crsave
= gen_rtx_REG (SImode
, 0);
27057 emit_insn (gen_prologue_movesi_from_cr (crsave
));
27059 for (i
= 0; i
< 8; i
++)
27060 if (!call_used_regs
[CR0_REGNO
+ i
])
27062 rtvec p
= rtvec_alloc (2);
27064 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
27066 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
27068 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27070 RTX_FRAME_RELATED_P (insn
) = 1;
27071 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27072 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
27073 sp_reg_rtx
, cr_off
+ sp_off
));
27075 cr_off
+= reg_size
;
27079 /* If we are emitting stack probes, but allocate no stack, then
27080 just note that in the dump file. */
27081 if (flag_stack_clash_protection
27084 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME
, false);
27086 /* Update stack and set back pointer unless this is V.4,
27087 for which it was done previously. */
27088 if (!WORLD_SAVE_P (info
) && info
->push_p
27089 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
27091 rtx ptr_reg
= NULL
;
27094 /* If saving altivec regs we need to be able to address all save
27095 locations using a 16-bit offset. */
27096 if ((strategy
& SAVE_INLINE_VRS
) == 0
27097 || (info
->altivec_size
!= 0
27098 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
27099 + info
->total_size
- frame_off
) > 32767)
27100 || (info
->vrsave_size
!= 0
27101 && (info
->vrsave_save_offset
27102 + info
->total_size
- frame_off
) > 32767))
27104 int sel
= SAVRES_SAVE
| SAVRES_VR
;
27105 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27107 if (using_static_chain_p
27108 && ptr_regno
== STATIC_CHAIN_REGNUM
)
27110 if (REGNO (frame_reg_rtx
) != ptr_regno
)
27111 START_USE (ptr_regno
);
27112 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27113 frame_reg_rtx
= ptr_reg
;
27114 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
27115 frame_off
= -ptr_off
;
27117 else if (REGNO (frame_reg_rtx
) == 1)
27118 frame_off
= info
->total_size
;
27119 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
27121 if (REGNO (frame_reg_rtx
) == 12)
27123 sp_off
= info
->total_size
;
27124 if (frame_reg_rtx
!= sp_reg_rtx
)
27125 rs6000_emit_stack_tie (frame_reg_rtx
, false);
27128 /* Set frame pointer, if needed. */
27129 if (frame_pointer_needed
)
27131 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
27133 RTX_FRAME_RELATED_P (insn
) = 1;
27136 /* Save AltiVec registers if needed. Save here because the red zone does
27137 not always include AltiVec registers. */
27138 if (!WORLD_SAVE_P (info
)
27139 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
27141 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
27143 /* Oddly, the vector save/restore functions point r0 at the end
27144 of the save area, then use r11 or r12 to load offsets for
27145 [reg+reg] addressing. */
27146 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
27147 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
27148 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
27150 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
27152 if (scratch_regno
== 12)
27154 if (end_save
+ frame_off
!= 0)
27156 rtx offset
= GEN_INT (end_save
+ frame_off
);
27158 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27161 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27163 ptr_off
= -end_save
;
27164 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
27165 info
->altivec_save_offset
+ ptr_off
,
27166 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
27167 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
27168 NULL_RTX
, NULL_RTX
);
27169 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
27171 /* The oddity mentioned above clobbered our frame reg. */
27172 emit_move_insn (frame_reg_rtx
, ptr_reg
);
27173 frame_off
= ptr_off
;
27176 else if (!WORLD_SAVE_P (info
)
27177 && info
->altivec_size
!= 0)
27181 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
27182 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
27184 rtx areg
, savereg
, mem
;
27185 HOST_WIDE_INT offset
;
27187 offset
= (info
->altivec_save_offset
+ frame_off
27188 + 16 * (i
- info
->first_altivec_reg_save
));
27190 savereg
= gen_rtx_REG (V4SImode
, i
);
27192 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
27194 mem
= gen_frame_mem (V4SImode
,
27195 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27196 GEN_INT (offset
)));
27197 insn
= emit_insn (gen_rtx_SET (mem
, savereg
));
27203 areg
= gen_rtx_REG (Pmode
, 0);
27204 emit_move_insn (areg
, GEN_INT (offset
));
27206 /* AltiVec addressing mode is [reg+reg]. */
27207 mem
= gen_frame_mem (V4SImode
,
27208 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
27210 /* Rather than emitting a generic move, force use of the stvx
27211 instruction, which we always want on ISA 2.07 (power8) systems.
27212 In particular we don't want xxpermdi/stxvd2x for little
27214 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
27217 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27218 areg
, GEN_INT (offset
));
27222 /* VRSAVE is a bit vector representing which AltiVec registers
27223 are used. The OS uses this to determine which vector
27224 registers to save on a context switch. We need to save
27225 VRSAVE on the stack frame, add whatever AltiVec registers we
27226 used in this function, and do the corresponding magic in the
27229 if (!WORLD_SAVE_P (info
) && info
->vrsave_size
!= 0)
27231 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27232 be using r12 as frame_reg_rtx and r11 as the static chain
27233 pointer for nested functions. */
27234 int save_regno
= 12;
27235 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27236 && !using_static_chain_p
)
27238 else if (using_split_stack
|| REGNO (frame_reg_rtx
) == 12)
27241 if (using_static_chain_p
)
27244 NOT_INUSE (save_regno
);
27246 emit_vrsave_prologue (info
, save_regno
, frame_off
, frame_reg_rtx
);
27249 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27250 if (!TARGET_SINGLE_PIC_BASE
27251 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
27252 && !constant_pool_empty_p ())
27253 || (DEFAULT_ABI
== ABI_V4
27254 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
27255 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
27257 /* If emit_load_toc_table will use the link register, we need to save
27258 it. We use R12 for this purpose because emit_load_toc_table
27259 can use register 0. This allows us to use a plain 'blr' to return
27260 from the procedure more often. */
27261 int save_LR_around_toc_setup
= (TARGET_ELF
27262 && DEFAULT_ABI
== ABI_V4
27264 && ! info
->lr_save_p
27265 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
27266 if (save_LR_around_toc_setup
)
27268 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27269 rtx tmp
= gen_rtx_REG (Pmode
, 12);
27272 insn
= emit_move_insn (tmp
, lr
);
27273 RTX_FRAME_RELATED_P (insn
) = 1;
27275 rs6000_emit_load_toc_table (TRUE
);
27277 insn
= emit_move_insn (lr
, tmp
);
27278 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27279 RTX_FRAME_RELATED_P (insn
) = 1;
27282 rs6000_emit_load_toc_table (TRUE
);
27286 if (!TARGET_SINGLE_PIC_BASE
27287 && DEFAULT_ABI
== ABI_DARWIN
27288 && flag_pic
&& crtl
->uses_pic_offset_table
)
27290 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27291 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
27293 /* Save and restore LR locally around this call (in R0). */
27294 if (!info
->lr_save_p
)
27295 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
27297 emit_insn (gen_load_macho_picbase (src
));
27299 emit_move_insn (gen_rtx_REG (Pmode
,
27300 RS6000_PIC_OFFSET_TABLE_REGNUM
),
27303 if (!info
->lr_save_p
)
27304 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
27308 /* If we need to, save the TOC register after doing the stack setup.
27309 Do not emit eh frame info for this save. The unwinder wants info,
27310 conceptually attached to instructions in this function, about
27311 register values in the caller of this function. This R2 may have
27312 already been changed from the value in the caller.
27313 We don't attempt to write accurate DWARF EH frame info for R2
27314 because code emitted by gcc for a (non-pointer) function call
27315 doesn't save and restore R2. Instead, R2 is managed out-of-line
27316 by a linker generated plt call stub when the function resides in
27317 a shared library. This behavior is costly to describe in DWARF,
27318 both in terms of the size of DWARF info and the time taken in the
27319 unwinder to interpret it. R2 changes, apart from the
27320 calls_eh_return case earlier in this function, are handled by
27321 linux-unwind.h frob_update_context. */
27322 if (rs6000_save_toc_in_prologue_p ()
27323 && !cfun
->machine
->toc_is_wrapped_separately
)
27325 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
27326 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
27329 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27330 if (using_split_stack
&& split_stack_arg_pointer_used_p ())
27331 emit_split_stack_prologue (info
, sp_adjust
, frame_off
, frame_reg_rtx
);
27334 /* Output .extern statements for the save/restore routines we use. */
27337 rs6000_output_savres_externs (FILE *file
)
27339 rs6000_stack_t
*info
= rs6000_stack_info ();
27341 if (TARGET_DEBUG_STACK
)
27342 debug_stack_info (info
);
27344 /* Write .extern for any function we will call to save and restore
27346 if (info
->first_fp_reg_save
< 64
27351 int regno
= info
->first_fp_reg_save
- 32;
27353 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
27355 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
27356 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27357 name
= rs6000_savres_routine_name (regno
, sel
);
27358 fprintf (file
, "\t.extern %s\n", name
);
27360 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
27362 bool lr
= (info
->savres_strategy
27363 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
27364 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27365 name
= rs6000_savres_routine_name (regno
, sel
);
27366 fprintf (file
, "\t.extern %s\n", name
);
27371 /* Write function prologue. */
27374 rs6000_output_function_prologue (FILE *file
)
27376 if (!cfun
->is_thunk
)
27377 rs6000_output_savres_externs (file
);
27379 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27380 immediately after the global entry point label. */
27381 if (rs6000_global_entry_point_needed_p ())
27383 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
27385 (*targetm
.asm_out
.internal_label
) (file
, "LCF", rs6000_pic_labelno
);
27387 if (TARGET_CMODEL
!= CMODEL_LARGE
)
27389 /* In the small and medium code models, we assume the TOC is less
27390 2 GB away from the text section, so it can be computed via the
27391 following two-instruction sequence. */
27394 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27395 fprintf (file
, "0:\taddis 2,12,.TOC.-");
27396 assemble_name (file
, buf
);
27397 fprintf (file
, "@ha\n");
27398 fprintf (file
, "\taddi 2,2,.TOC.-");
27399 assemble_name (file
, buf
);
27400 fprintf (file
, "@l\n");
27404 /* In the large code model, we allow arbitrary offsets between the
27405 TOC and the text section, so we have to load the offset from
27406 memory. The data field is emitted directly before the global
27407 entry point in rs6000_elf_declare_function_name. */
27410 #ifdef HAVE_AS_ENTRY_MARKERS
27411 /* If supported by the linker, emit a marker relocation. If the
27412 total code size of the final executable or shared library
27413 happens to fit into 2 GB after all, the linker will replace
27414 this code sequence with the sequence for the small or medium
27416 fprintf (file
, "\t.reloc .,R_PPC64_ENTRY\n");
27418 fprintf (file
, "\tld 2,");
27419 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
27420 assemble_name (file
, buf
);
27421 fprintf (file
, "-");
27422 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27423 assemble_name (file
, buf
);
27424 fprintf (file
, "(12)\n");
27425 fprintf (file
, "\tadd 2,2,12\n");
27428 fputs ("\t.localentry\t", file
);
27429 assemble_name (file
, name
);
27430 fputs (",.-", file
);
27431 assemble_name (file
, name
);
27432 fputs ("\n", file
);
27435 /* Output -mprofile-kernel code. This needs to be done here instead of
27436 in output_function_profile since it must go after the ELFv2 ABI
27437 local entry point. */
27438 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
27440 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
27441 gcc_assert (!TARGET_32BIT
);
27443 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
27445 /* In the ELFv2 ABI we have no compiler stack word. It must be
27446 the resposibility of _mcount to preserve the static chain
27447 register if required. */
27448 if (DEFAULT_ABI
!= ABI_ELFv2
27449 && cfun
->static_chain_decl
!= NULL
)
27451 asm_fprintf (file
, "\tstd %s,24(%s)\n",
27452 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27453 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27454 asm_fprintf (file
, "\tld %s,24(%s)\n",
27455 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27458 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27461 rs6000_pic_labelno
++;
27464 /* -mprofile-kernel code calls mcount before the function prolog,
27465 so a profiled leaf function should stay a leaf function. */
27467 rs6000_keep_leaf_when_profiled ()
27469 return TARGET_PROFILE_KERNEL
;
27472 /* Non-zero if vmx regs are restored before the frame pop, zero if
27473 we restore after the pop when possible. */
27474 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27476 /* Restoring cr is a two step process: loading a reg from the frame
27477 save, then moving the reg to cr. For ABI_V4 we must let the
27478 unwinder know that the stack location is no longer valid at or
27479 before the stack deallocation, but we can't emit a cfa_restore for
27480 cr at the stack deallocation like we do for other registers.
27481 The trouble is that it is possible for the move to cr to be
27482 scheduled after the stack deallocation. So say exactly where cr
27483 is located on each of the two insns. */
27486 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
27488 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
27489 rtx reg
= gen_rtx_REG (SImode
, regno
);
27490 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
27492 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
27494 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
27495 rtx set
= gen_rtx_SET (reg
, cr
);
27497 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
27498 RTX_FRAME_RELATED_P (insn
) = 1;
27503 /* Reload CR from REG. */
27506 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
27511 if (using_mfcr_multiple
)
27513 for (i
= 0; i
< 8; i
++)
27514 if (save_reg_p (CR0_REGNO
+ i
))
27516 gcc_assert (count
);
27519 if (using_mfcr_multiple
&& count
> 1)
27525 p
= rtvec_alloc (count
);
27528 for (i
= 0; i
< 8; i
++)
27529 if (save_reg_p (CR0_REGNO
+ i
))
27531 rtvec r
= rtvec_alloc (2);
27532 RTVEC_ELT (r
, 0) = reg
;
27533 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
27534 RTVEC_ELT (p
, ndx
) =
27535 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
27536 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
27539 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27540 gcc_assert (ndx
== count
);
27542 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27543 CR field separately. */
27544 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
27546 for (i
= 0; i
< 8; i
++)
27547 if (save_reg_p (CR0_REGNO
+ i
))
27548 add_reg_note (insn
, REG_CFA_RESTORE
,
27549 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27551 RTX_FRAME_RELATED_P (insn
) = 1;
27555 for (i
= 0; i
< 8; i
++)
27556 if (save_reg_p (CR0_REGNO
+ i
))
27558 rtx insn
= emit_insn (gen_movsi_to_cr_one
27559 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
27561 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27562 CR field separately, attached to the insn that in fact
27563 restores this particular CR field. */
27564 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
27566 add_reg_note (insn
, REG_CFA_RESTORE
,
27567 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27569 RTX_FRAME_RELATED_P (insn
) = 1;
27573 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27574 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
27575 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
27577 rtx_insn
*insn
= get_last_insn ();
27578 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
27580 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
27581 RTX_FRAME_RELATED_P (insn
) = 1;
27585 /* Like cr, the move to lr instruction can be scheduled after the
27586 stack deallocation, but unlike cr, its stack frame save is still
27587 valid. So we only need to emit the cfa_restore on the correct
27591 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
27593 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
27594 rtx reg
= gen_rtx_REG (Pmode
, regno
);
27596 emit_move_insn (reg
, mem
);
27600 restore_saved_lr (int regno
, bool exit_func
)
27602 rtx reg
= gen_rtx_REG (Pmode
, regno
);
27603 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27604 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
27606 if (!exit_func
&& flag_shrink_wrap
)
27608 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27609 RTX_FRAME_RELATED_P (insn
) = 1;
27614 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
27616 if (DEFAULT_ABI
== ABI_ELFv2
)
27619 for (i
= 0; i
< 8; i
++)
27620 if (save_reg_p (CR0_REGNO
+ i
))
27622 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
27623 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
27627 else if (info
->cr_save_p
)
27628 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27629 gen_rtx_REG (SImode
, CR2_REGNO
),
27632 if (info
->lr_save_p
)
27633 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27634 gen_rtx_REG (Pmode
, LR_REGNO
),
27636 return cfa_restores
;
27639 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27640 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27641 below stack pointer not cloberred by signals. */
27644 offset_below_red_zone_p (HOST_WIDE_INT offset
)
27646 return offset
< (DEFAULT_ABI
== ABI_V4
27648 : TARGET_32BIT
? -220 : -288);
27651 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27654 emit_cfa_restores (rtx cfa_restores
)
27656 rtx_insn
*insn
= get_last_insn ();
27657 rtx
*loc
= ®_NOTES (insn
);
27660 loc
= &XEXP (*loc
, 1);
27661 *loc
= cfa_restores
;
27662 RTX_FRAME_RELATED_P (insn
) = 1;
27665 /* Emit function epilogue as insns. */
27668 rs6000_emit_epilogue (int sibcall
)
27670 rs6000_stack_t
*info
;
27671 int restoring_GPRs_inline
;
27672 int restoring_FPRs_inline
;
27673 int using_load_multiple
;
27674 int using_mtcr_multiple
;
27675 int use_backchain_to_restore_sp
;
27678 HOST_WIDE_INT frame_off
= 0;
27679 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
27680 rtx frame_reg_rtx
= sp_reg_rtx
;
27681 rtx cfa_restores
= NULL_RTX
;
27683 rtx cr_save_reg
= NULL_RTX
;
27684 machine_mode reg_mode
= Pmode
;
27685 int reg_size
= TARGET_32BIT
? 4 : 8;
27686 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
27687 int fp_reg_size
= 8;
27690 unsigned ptr_regno
;
27692 info
= rs6000_stack_info ();
27694 strategy
= info
->savres_strategy
;
27695 using_load_multiple
= strategy
& REST_MULTIPLE
;
27696 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
27697 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
27698 using_mtcr_multiple
= (rs6000_tune
== PROCESSOR_PPC601
27699 || rs6000_tune
== PROCESSOR_PPC603
27700 || rs6000_tune
== PROCESSOR_PPC750
27702 /* Restore via the backchain when we have a large frame, since this
27703 is more efficient than an addis, addi pair. The second condition
27704 here will not trigger at the moment; We don't actually need a
27705 frame pointer for alloca, but the generic parts of the compiler
27706 give us one anyway. */
27707 use_backchain_to_restore_sp
= (info
->total_size
+ (info
->lr_save_p
27708 ? info
->lr_save_offset
27710 || (cfun
->calls_alloca
27711 && !frame_pointer_needed
));
27712 restore_lr
= (info
->lr_save_p
27713 && (restoring_FPRs_inline
27714 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
27715 && (restoring_GPRs_inline
27716 || info
->first_fp_reg_save
< 64)
27717 && !cfun
->machine
->lr_is_wrapped_separately
);
27720 if (WORLD_SAVE_P (info
))
27724 const char *alloc_rname
;
27727 /* eh_rest_world_r10 will return to the location saved in the LR
27728 stack slot (which is not likely to be our caller.)
27729 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27730 rest_world is similar, except any R10 parameter is ignored.
27731 The exception-handling stuff that was here in 2.95 is no
27732 longer necessary. */
27735 + 32 - info
->first_gp_reg_save
27736 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
27737 + 63 + 1 - info
->first_fp_reg_save
);
27739 strcpy (rname
, ((crtl
->calls_eh_return
) ?
27740 "*eh_rest_world_r10" : "*rest_world"));
27741 alloc_rname
= ggc_strdup (rname
);
27744 RTVEC_ELT (p
, j
++) = ret_rtx
;
27746 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
27747 /* The instruction pattern requires a clobber here;
27748 it is shared with the restVEC helper. */
27750 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
27753 /* CR register traditionally saved as CR2. */
27754 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
27756 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
27757 if (flag_shrink_wrap
)
27759 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
27760 gen_rtx_REG (Pmode
, LR_REGNO
),
27762 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27766 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
27768 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
27770 = gen_frame_load (reg
,
27771 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
27772 if (flag_shrink_wrap
27773 && save_reg_p (info
->first_gp_reg_save
+ i
))
27774 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27776 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
27778 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
27780 = gen_frame_load (reg
,
27781 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
27782 if (flag_shrink_wrap
27783 && save_reg_p (info
->first_altivec_reg_save
+ i
))
27784 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27786 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
27788 rtx reg
= gen_rtx_REG (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
27789 info
->first_fp_reg_save
+ i
);
27791 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
27792 if (flag_shrink_wrap
27793 && save_reg_p (info
->first_fp_reg_save
+ i
))
27794 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27797 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
27799 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
27801 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
27803 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
27805 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
27806 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27808 if (flag_shrink_wrap
)
27810 REG_NOTES (insn
) = cfa_restores
;
27811 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
27812 RTX_FRAME_RELATED_P (insn
) = 1;
27817 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
27819 frame_off
= info
->total_size
;
27821 /* Restore AltiVec registers if we must do so before adjusting the
27823 if (info
->altivec_size
!= 0
27824 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27825 || (DEFAULT_ABI
!= ABI_V4
27826 && offset_below_red_zone_p (info
->altivec_save_offset
))))
27829 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
27831 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
27832 if (use_backchain_to_restore_sp
)
27834 int frame_regno
= 11;
27836 if ((strategy
& REST_INLINE_VRS
) == 0)
27838 /* Of r11 and r12, select the one not clobbered by an
27839 out-of-line restore function for the frame register. */
27840 frame_regno
= 11 + 12 - scratch_regno
;
27842 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
27843 emit_move_insn (frame_reg_rtx
,
27844 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
27847 else if (frame_pointer_needed
)
27848 frame_reg_rtx
= hard_frame_pointer_rtx
;
27850 if ((strategy
& REST_INLINE_VRS
) == 0)
27852 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
27854 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
27855 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
27857 if (end_save
+ frame_off
!= 0)
27859 rtx offset
= GEN_INT (end_save
+ frame_off
);
27861 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27864 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27866 ptr_off
= -end_save
;
27867 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
27868 info
->altivec_save_offset
+ ptr_off
,
27869 0, V4SImode
, SAVRES_VR
);
27873 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
27874 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
27876 rtx addr
, areg
, mem
, insn
;
27877 rtx reg
= gen_rtx_REG (V4SImode
, i
);
27878 HOST_WIDE_INT offset
27879 = (info
->altivec_save_offset
+ frame_off
27880 + 16 * (i
- info
->first_altivec_reg_save
));
27882 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
27884 mem
= gen_frame_mem (V4SImode
,
27885 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27886 GEN_INT (offset
)));
27887 insn
= gen_rtx_SET (reg
, mem
);
27891 areg
= gen_rtx_REG (Pmode
, 0);
27892 emit_move_insn (areg
, GEN_INT (offset
));
27894 /* AltiVec addressing mode is [reg+reg]. */
27895 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
27896 mem
= gen_frame_mem (V4SImode
, addr
);
27898 /* Rather than emitting a generic move, force use of the
27899 lvx instruction, which we always want. In particular we
27900 don't want lxvd2x/xxpermdi for little endian. */
27901 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
27904 (void) emit_insn (insn
);
27908 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
27909 if (((strategy
& REST_INLINE_VRS
) == 0
27910 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
27911 && (flag_shrink_wrap
27912 || (offset_below_red_zone_p
27913 (info
->altivec_save_offset
27914 + 16 * (i
- info
->first_altivec_reg_save
))))
27917 rtx reg
= gen_rtx_REG (V4SImode
, i
);
27918 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
27922 /* Restore VRSAVE if we must do so before adjusting the stack. */
27923 if (info
->vrsave_size
!= 0
27924 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27925 || (DEFAULT_ABI
!= ABI_V4
27926 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
27930 if (frame_reg_rtx
== sp_reg_rtx
)
27932 if (use_backchain_to_restore_sp
)
27934 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
27935 emit_move_insn (frame_reg_rtx
,
27936 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
27939 else if (frame_pointer_needed
)
27940 frame_reg_rtx
= hard_frame_pointer_rtx
;
27943 reg
= gen_rtx_REG (SImode
, 12);
27944 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
27945 info
->vrsave_save_offset
+ frame_off
));
27947 emit_insn (generate_set_vrsave (reg
, info
, 1));
27951 /* If we have a large stack frame, restore the old stack pointer
27952 using the backchain. */
27953 if (use_backchain_to_restore_sp
)
27955 if (frame_reg_rtx
== sp_reg_rtx
)
27957 /* Under V.4, don't reset the stack pointer until after we're done
27958 loading the saved registers. */
27959 if (DEFAULT_ABI
== ABI_V4
)
27960 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
27962 insn
= emit_move_insn (frame_reg_rtx
,
27963 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
27966 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27967 && DEFAULT_ABI
== ABI_V4
)
27968 /* frame_reg_rtx has been set up by the altivec restore. */
27972 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
27973 frame_reg_rtx
= sp_reg_rtx
;
27976 /* If we have a frame pointer, we can restore the old stack pointer
27978 else if (frame_pointer_needed
)
27980 frame_reg_rtx
= sp_reg_rtx
;
27981 if (DEFAULT_ABI
== ABI_V4
)
27982 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
27983 /* Prevent reordering memory accesses against stack pointer restore. */
27984 else if (cfun
->calls_alloca
27985 || offset_below_red_zone_p (-info
->total_size
))
27986 rs6000_emit_stack_tie (frame_reg_rtx
, true);
27988 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
27989 GEN_INT (info
->total_size
)));
27992 else if (info
->push_p
27993 && DEFAULT_ABI
!= ABI_V4
27994 && !crtl
->calls_eh_return
)
27996 /* Prevent reordering memory accesses against stack pointer restore. */
27997 if (cfun
->calls_alloca
27998 || offset_below_red_zone_p (-info
->total_size
))
27999 rs6000_emit_stack_tie (frame_reg_rtx
, false);
28000 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
28001 GEN_INT (info
->total_size
)));
28004 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
28008 REG_NOTES (insn
) = cfa_restores
;
28009 cfa_restores
= NULL_RTX
;
28011 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28012 RTX_FRAME_RELATED_P (insn
) = 1;
28015 /* Restore AltiVec registers if we have not done so already. */
28016 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28017 && info
->altivec_size
!= 0
28018 && (DEFAULT_ABI
== ABI_V4
28019 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
28023 if ((strategy
& REST_INLINE_VRS
) == 0)
28025 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28027 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28028 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
28029 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28031 if (end_save
+ frame_off
!= 0)
28033 rtx offset
= GEN_INT (end_save
+ frame_off
);
28035 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28038 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28040 ptr_off
= -end_save
;
28041 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28042 info
->altivec_save_offset
+ ptr_off
,
28043 0, V4SImode
, SAVRES_VR
);
28044 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
28046 /* Frame reg was clobbered by out-of-line save. Restore it
28047 from ptr_reg, and if we are calling out-of-line gpr or
28048 fpr restore set up the correct pointer and offset. */
28049 unsigned newptr_regno
= 1;
28050 if (!restoring_GPRs_inline
)
28052 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28053 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28054 newptr_regno
= ptr_regno_for_savres (sel
);
28055 end_save
= info
->gp_save_offset
+ info
->gp_size
;
28057 else if (!restoring_FPRs_inline
)
28059 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
28060 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28061 newptr_regno
= ptr_regno_for_savres (sel
);
28062 end_save
= info
->fp_save_offset
+ info
->fp_size
;
28065 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
28066 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
28068 if (end_save
+ ptr_off
!= 0)
28070 rtx offset
= GEN_INT (end_save
+ ptr_off
);
28072 frame_off
= -end_save
;
28074 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
28077 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
28082 frame_off
= ptr_off
;
28083 emit_move_insn (frame_reg_rtx
, ptr_reg
);
28089 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28090 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28092 rtx addr
, areg
, mem
, insn
;
28093 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28094 HOST_WIDE_INT offset
28095 = (info
->altivec_save_offset
+ frame_off
28096 + 16 * (i
- info
->first_altivec_reg_save
));
28098 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
28100 mem
= gen_frame_mem (V4SImode
,
28101 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28102 GEN_INT (offset
)));
28103 insn
= gen_rtx_SET (reg
, mem
);
28107 areg
= gen_rtx_REG (Pmode
, 0);
28108 emit_move_insn (areg
, GEN_INT (offset
));
28110 /* AltiVec addressing mode is [reg+reg]. */
28111 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
28112 mem
= gen_frame_mem (V4SImode
, addr
);
28114 /* Rather than emitting a generic move, force use of the
28115 lvx instruction, which we always want. In particular we
28116 don't want lxvd2x/xxpermdi for little endian. */
28117 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
28120 (void) emit_insn (insn
);
28124 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28125 if (((strategy
& REST_INLINE_VRS
) == 0
28126 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
28127 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28130 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28131 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28135 /* Restore VRSAVE if we have not done so already. */
28136 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28137 && info
->vrsave_size
!= 0
28138 && (DEFAULT_ABI
== ABI_V4
28139 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
28143 reg
= gen_rtx_REG (SImode
, 12);
28144 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28145 info
->vrsave_save_offset
+ frame_off
));
28147 emit_insn (generate_set_vrsave (reg
, info
, 1));
28150 /* If we exit by an out-of-line restore function on ABI_V4 then that
28151 function will deallocate the stack, so we don't need to worry
28152 about the unwinder restoring cr from an invalid stack frame
28154 exit_func
= (!restoring_FPRs_inline
28155 || (!restoring_GPRs_inline
28156 && info
->first_fp_reg_save
== 64));
28158 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28159 *separate* slots if the routine calls __builtin_eh_return, so
28160 that they can be independently restored by the unwinder. */
28161 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
28163 int i
, cr_off
= info
->ehcr_offset
;
28165 for (i
= 0; i
< 8; i
++)
28166 if (!call_used_regs
[CR0_REGNO
+ i
])
28168 rtx reg
= gen_rtx_REG (SImode
, 0);
28169 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28170 cr_off
+ frame_off
));
28172 insn
= emit_insn (gen_movsi_to_cr_one
28173 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
28175 if (!exit_func
&& flag_shrink_wrap
)
28177 add_reg_note (insn
, REG_CFA_RESTORE
,
28178 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
28180 RTX_FRAME_RELATED_P (insn
) = 1;
28183 cr_off
+= reg_size
;
28187 /* Get the old lr if we saved it. If we are restoring registers
28188 out-of-line, then the out-of-line routines can do this for us. */
28189 if (restore_lr
&& restoring_GPRs_inline
)
28190 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28192 /* Get the old cr if we saved it. */
28193 if (info
->cr_save_p
)
28195 unsigned cr_save_regno
= 12;
28197 if (!restoring_GPRs_inline
)
28199 /* Ensure we don't use the register used by the out-of-line
28200 gpr register restore below. */
28201 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28202 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28203 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
28205 if (gpr_ptr_regno
== 12)
28206 cr_save_regno
= 11;
28207 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
28209 else if (REGNO (frame_reg_rtx
) == 12)
28210 cr_save_regno
= 11;
28212 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
28213 info
->cr_save_offset
+ frame_off
,
28217 /* Set LR here to try to overlap restores below. */
28218 if (restore_lr
&& restoring_GPRs_inline
)
28219 restore_saved_lr (0, exit_func
);
28221 /* Load exception handler data registers, if needed. */
28222 if (crtl
->calls_eh_return
)
28224 unsigned int i
, regno
;
28228 rtx reg
= gen_rtx_REG (reg_mode
, 2);
28229 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28230 frame_off
+ RS6000_TOC_SAVE_SLOT
));
28237 regno
= EH_RETURN_DATA_REGNO (i
);
28238 if (regno
== INVALID_REGNUM
)
28241 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
28242 info
->ehrd_offset
+ frame_off
28243 + reg_size
* (int) i
);
28245 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
28249 /* Restore GPRs. This is done as a PARALLEL if we are using
28250 the load-multiple instructions. */
28251 if (!restoring_GPRs_inline
)
28253 /* We are jumping to an out-of-line function. */
28255 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
28256 bool can_use_exit
= end_save
== 0;
28257 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
28260 /* Emit stack reset code if we need it. */
28261 ptr_regno
= ptr_regno_for_savres (sel
);
28262 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28264 rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28265 else if (end_save
+ frame_off
!= 0)
28266 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
28267 GEN_INT (end_save
+ frame_off
)));
28268 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
28269 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28270 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28271 frame_off
= -end_save
;
28273 if (can_use_exit
&& info
->cr_save_p
)
28274 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
28276 ptr_off
= -end_save
;
28277 rs6000_emit_savres_rtx (info
, ptr_reg
,
28278 info
->gp_save_offset
+ ptr_off
,
28279 info
->lr_save_offset
+ ptr_off
,
28282 else if (using_load_multiple
)
28285 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
28286 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28288 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
28290 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
28291 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28295 int offset
= info
->gp_save_offset
+ frame_off
;
28296 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28299 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28301 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28302 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28305 offset
+= reg_size
;
28309 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28311 /* If the frame pointer was used then we can't delay emitting
28312 a REG_CFA_DEF_CFA note. This must happen on the insn that
28313 restores the frame pointer, r31. We may have already emitted
28314 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28315 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28316 be harmless if emitted. */
28317 if (frame_pointer_needed
)
28319 insn
= get_last_insn ();
28320 add_reg_note (insn
, REG_CFA_DEF_CFA
,
28321 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
28322 RTX_FRAME_RELATED_P (insn
) = 1;
28325 /* Set up cfa_restores. We always need these when
28326 shrink-wrapping. If not shrink-wrapping then we only need
28327 the cfa_restore when the stack location is no longer valid.
28328 The cfa_restores must be emitted on or before the insn that
28329 invalidates the stack, and of course must not be emitted
28330 before the insn that actually does the restore. The latter
28331 is why it is a bad idea to emit the cfa_restores as a group
28332 on the last instruction here that actually does a restore:
28333 That insn may be reordered with respect to others doing
28335 if (flag_shrink_wrap
28336 && !restoring_GPRs_inline
28337 && info
->first_fp_reg_save
== 64)
28338 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28340 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28342 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28344 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28345 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28349 if (!restoring_GPRs_inline
28350 && info
->first_fp_reg_save
== 64)
28352 /* We are jumping to an out-of-line function. */
28354 emit_cfa_restores (cfa_restores
);
28358 if (restore_lr
&& !restoring_GPRs_inline
)
28360 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28361 restore_saved_lr (0, exit_func
);
28364 /* Restore fpr's if we need to do it without calling a function. */
28365 if (restoring_FPRs_inline
)
28367 int offset
= info
->fp_save_offset
+ frame_off
;
28368 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
28371 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
28373 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
28374 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28375 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28376 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
28380 offset
+= fp_reg_size
;
28384 /* If we saved cr, restore it here. Just those that were used. */
28385 if (info
->cr_save_p
)
28386 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
28388 /* If this is V.4, unwind the stack pointer after all of the loads
28389 have been done, or set up r11 if we are restoring fp out of line. */
28391 if (!restoring_FPRs_inline
)
28393 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28394 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28395 ptr_regno
= ptr_regno_for_savres (sel
);
28398 insn
= rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28399 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28402 if (insn
&& restoring_FPRs_inline
)
28406 REG_NOTES (insn
) = cfa_restores
;
28407 cfa_restores
= NULL_RTX
;
28409 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28410 RTX_FRAME_RELATED_P (insn
) = 1;
28413 if (crtl
->calls_eh_return
)
28415 rtx sa
= EH_RETURN_STACKADJ_RTX
;
28416 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
28419 if (!sibcall
&& restoring_FPRs_inline
)
28423 /* We can't hang the cfa_restores off a simple return,
28424 since the shrink-wrap code sometimes uses an existing
28425 return. This means there might be a path from
28426 pre-prologue code to this return, and dwarf2cfi code
28427 wants the eh_frame unwinder state to be the same on
28428 all paths to any point. So we need to emit the
28429 cfa_restores before the return. For -m64 we really
28430 don't need epilogue cfa_restores at all, except for
28431 this irritating dwarf2cfi with shrink-wrap
28432 requirement; The stack red-zone means eh_frame info
28433 from the prologue telling the unwinder to restore
28434 from the stack is perfectly good right to the end of
28436 emit_insn (gen_blockage ());
28437 emit_cfa_restores (cfa_restores
);
28438 cfa_restores
= NULL_RTX
;
28441 emit_jump_insn (targetm
.gen_simple_return ());
28444 if (!sibcall
&& !restoring_FPRs_inline
)
28446 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28447 rtvec p
= rtvec_alloc (3 + !!lr
+ 64 - info
->first_fp_reg_save
);
28449 RTVEC_ELT (p
, elt
++) = ret_rtx
;
28451 RTVEC_ELT (p
, elt
++)
28452 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
28454 /* We have to restore more than two FP registers, so branch to the
28455 restore function. It will return to our caller. */
28460 if (flag_shrink_wrap
)
28461 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28463 sym
= rs6000_savres_routine_sym (info
, SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
28464 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, sym
);
28465 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
28466 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
28468 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
28470 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
28472 RTVEC_ELT (p
, elt
++)
28473 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
28474 if (flag_shrink_wrap
28475 && save_reg_p (info
->first_fp_reg_save
+ i
))
28476 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28479 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28485 /* Ensure the cfa_restores are hung off an insn that won't
28486 be reordered above other restores. */
28487 emit_insn (gen_blockage ());
28489 emit_cfa_restores (cfa_restores
);
28493 /* Write function epilogue. */
28496 rs6000_output_function_epilogue (FILE *file
)
28499 macho_branch_islands ();
28502 rtx_insn
*insn
= get_last_insn ();
28503 rtx_insn
*deleted_debug_label
= NULL
;
28505 /* Mach-O doesn't support labels at the end of objects, so if
28506 it looks like we might want one, take special action.
28508 First, collect any sequence of deleted debug labels. */
28511 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
28513 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28514 notes only, instead set their CODE_LABEL_NUMBER to -1,
28515 otherwise there would be code generation differences
28516 in between -g and -g0. */
28517 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
28518 deleted_debug_label
= insn
;
28519 insn
= PREV_INSN (insn
);
28522 /* Second, if we have:
28525 then this needs to be detected, so skip past the barrier. */
28527 if (insn
&& BARRIER_P (insn
))
28528 insn
= PREV_INSN (insn
);
28530 /* Up to now we've only seen notes or barriers. */
28535 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
))
28536 /* Trailing label: <barrier>. */
28537 fputs ("\tnop\n", file
);
28540 /* Lastly, see if we have a completely empty function body. */
28541 while (insn
&& ! INSN_P (insn
))
28542 insn
= PREV_INSN (insn
);
28543 /* If we don't find any insns, we've got an empty function body;
28544 I.e. completely empty - without a return or branch. This is
28545 taken as the case where a function body has been removed
28546 because it contains an inline __builtin_unreachable(). GCC
28547 states that reaching __builtin_unreachable() means UB so we're
28548 not obliged to do anything special; however, we want
28549 non-zero-sized function bodies. To meet this, and help the
28550 user out, let's trap the case. */
28552 fputs ("\ttrap\n", file
);
28555 else if (deleted_debug_label
)
28556 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
28557 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
28558 CODE_LABEL_NUMBER (insn
) = -1;
28562 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28565 We don't output a traceback table if -finhibit-size-directive was
28566 used. The documentation for -finhibit-size-directive reads
28567 ``don't output a @code{.size} assembler directive, or anything
28568 else that would cause trouble if the function is split in the
28569 middle, and the two halves are placed at locations far apart in
28570 memory.'' The traceback table has this property, since it
28571 includes the offset from the start of the function to the
28572 traceback table itself.
28574 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28575 different traceback table. */
28576 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28577 && ! flag_inhibit_size_directive
28578 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
28580 const char *fname
= NULL
;
28581 const char *language_string
= lang_hooks
.name
;
28582 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
28584 int optional_tbtab
;
28585 rs6000_stack_t
*info
= rs6000_stack_info ();
28587 if (rs6000_traceback
== traceback_full
)
28588 optional_tbtab
= 1;
28589 else if (rs6000_traceback
== traceback_part
)
28590 optional_tbtab
= 0;
28592 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
28594 if (optional_tbtab
)
28596 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
28597 while (*fname
== '.') /* V.4 encodes . in the name */
28600 /* Need label immediately before tbtab, so we can compute
28601 its offset from the function start. */
28602 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
28603 ASM_OUTPUT_LABEL (file
, fname
);
28606 /* The .tbtab pseudo-op can only be used for the first eight
28607 expressions, since it can't handle the possibly variable
28608 length fields that follow. However, if you omit the optional
28609 fields, the assembler outputs zeros for all optional fields
28610 anyways, giving each variable length field is minimum length
28611 (as defined in sys/debug.h). Thus we can not use the .tbtab
28612 pseudo-op at all. */
28614 /* An all-zero word flags the start of the tbtab, for debuggers
28615 that have to find it by searching forward from the entry
28616 point or from the current pc. */
28617 fputs ("\t.long 0\n", file
);
28619 /* Tbtab format type. Use format type 0. */
28620 fputs ("\t.byte 0,", file
);
28622 /* Language type. Unfortunately, there does not seem to be any
28623 official way to discover the language being compiled, so we
28624 use language_string.
28625 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28626 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28627 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28628 numbers either, so for now use 0. */
28630 || ! strcmp (language_string
, "GNU GIMPLE")
28631 || ! strcmp (language_string
, "GNU Go")
28632 || ! strcmp (language_string
, "GNU D")
28633 || ! strcmp (language_string
, "libgccjit"))
28635 else if (! strcmp (language_string
, "GNU F77")
28636 || lang_GNU_Fortran ())
28638 else if (! strcmp (language_string
, "GNU Ada"))
28640 else if (lang_GNU_CXX ()
28641 || ! strcmp (language_string
, "GNU Objective-C++"))
28643 else if (! strcmp (language_string
, "GNU Java"))
28645 else if (! strcmp (language_string
, "GNU Objective-C"))
28648 gcc_unreachable ();
28649 fprintf (file
, "%d,", i
);
28651 /* 8 single bit fields: global linkage (not set for C extern linkage,
28652 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28653 from start of procedure stored in tbtab, internal function, function
28654 has controlled storage, function has no toc, function uses fp,
28655 function logs/aborts fp operations. */
28656 /* Assume that fp operations are used if any fp reg must be saved. */
28657 fprintf (file
, "%d,",
28658 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
28660 /* 6 bitfields: function is interrupt handler, name present in
28661 proc table, function calls alloca, on condition directives
28662 (controls stack walks, 3 bits), saves condition reg, saves
28664 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28665 set up as a frame pointer, even when there is no alloca call. */
28666 fprintf (file
, "%d,",
28667 ((optional_tbtab
<< 6)
28668 | ((optional_tbtab
& frame_pointer_needed
) << 5)
28669 | (info
->cr_save_p
<< 1)
28670 | (info
->lr_save_p
)));
28672 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28674 fprintf (file
, "%d,",
28675 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
28677 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28678 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
28680 if (optional_tbtab
)
28682 /* Compute the parameter info from the function decl argument
28685 int next_parm_info_bit
= 31;
28687 for (decl
= DECL_ARGUMENTS (current_function_decl
);
28688 decl
; decl
= DECL_CHAIN (decl
))
28690 rtx parameter
= DECL_INCOMING_RTL (decl
);
28691 machine_mode mode
= GET_MODE (parameter
);
28693 if (GET_CODE (parameter
) == REG
)
28695 if (SCALAR_FLOAT_MODE_P (mode
))
28718 gcc_unreachable ();
28721 /* If only one bit will fit, don't or in this entry. */
28722 if (next_parm_info_bit
> 0)
28723 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
28724 next_parm_info_bit
-= 2;
28728 fixed_parms
+= ((GET_MODE_SIZE (mode
)
28729 + (UNITS_PER_WORD
- 1))
28731 next_parm_info_bit
-= 1;
28737 /* Number of fixed point parameters. */
28738 /* This is actually the number of words of fixed point parameters; thus
28739 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28740 fprintf (file
, "%d,", fixed_parms
);
28742 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28744 /* This is actually the number of fp registers that hold parameters;
28745 and thus the maximum value is 13. */
28746 /* Set parameters on stack bit if parameters are not in their original
28747 registers, regardless of whether they are on the stack? Xlc
28748 seems to set the bit when not optimizing. */
28749 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
28751 if (optional_tbtab
)
28753 /* Optional fields follow. Some are variable length. */
28755 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28756 float, 11 double float. */
28757 /* There is an entry for each parameter in a register, in the order
28758 that they occur in the parameter list. Any intervening arguments
28759 on the stack are ignored. If the list overflows a long (max
28760 possible length 34 bits) then completely leave off all elements
28762 /* Only emit this long if there was at least one parameter. */
28763 if (fixed_parms
|| float_parms
)
28764 fprintf (file
, "\t.long %d\n", parm_info
);
28766 /* Offset from start of code to tb table. */
28767 fputs ("\t.long ", file
);
28768 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
28769 RS6000_OUTPUT_BASENAME (file
, fname
);
28771 rs6000_output_function_entry (file
, fname
);
28774 /* Interrupt handler mask. */
28775 /* Omit this long, since we never set the interrupt handler bit
28778 /* Number of CTL (controlled storage) anchors. */
28779 /* Omit this long, since the has_ctl bit is never set above. */
28781 /* Displacement into stack of each CTL anchor. */
28782 /* Omit this list of longs, because there are no CTL anchors. */
28784 /* Length of function name. */
28787 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
28789 /* Function name. */
28790 assemble_string (fname
, strlen (fname
));
28792 /* Register for alloca automatic storage; this is always reg 31.
28793 Only emit this if the alloca bit was set above. */
28794 if (frame_pointer_needed
)
28795 fputs ("\t.byte 31\n", file
);
28797 fputs ("\t.align 2\n", file
);
28801 /* Arrange to define .LCTOC1 label, if not already done. */
28805 if (!toc_initialized
)
28807 switch_to_section (toc_section
);
28808 switch_to_section (current_function_section ());
28813 /* -fsplit-stack support. */
28815 /* A SYMBOL_REF for __morestack. */
28816 static GTY(()) rtx morestack_ref
;
28819 gen_add3_const (rtx rt
, rtx ra
, long c
)
28822 return gen_adddi3 (rt
, ra
, GEN_INT (c
));
28824 return gen_addsi3 (rt
, ra
, GEN_INT (c
));
28827 /* Emit -fsplit-stack prologue, which goes before the regular function
28828 prologue (at local entry point in the case of ELFv2). */
28831 rs6000_expand_split_stack_prologue (void)
28833 rs6000_stack_t
*info
= rs6000_stack_info ();
28834 unsigned HOST_WIDE_INT allocate
;
28835 long alloc_hi
, alloc_lo
;
28836 rtx r0
, r1
, r12
, lr
, ok_label
, compare
, jump
, call_fusage
;
28839 gcc_assert (flag_split_stack
&& reload_completed
);
28844 if (global_regs
[29])
28846 error ("%qs uses register r29", "-fsplit-stack");
28847 inform (DECL_SOURCE_LOCATION (global_regs_decl
[29]),
28848 "conflicts with %qD", global_regs_decl
[29]);
28851 allocate
= info
->total_size
;
28852 if (allocate
> (unsigned HOST_WIDE_INT
) 1 << 31)
28854 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
28857 if (morestack_ref
== NULL_RTX
)
28859 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
28860 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
28861 | SYMBOL_FLAG_FUNCTION
);
28864 r0
= gen_rtx_REG (Pmode
, 0);
28865 r1
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
28866 r12
= gen_rtx_REG (Pmode
, 12);
28867 emit_insn (gen_load_split_stack_limit (r0
));
28868 /* Always emit two insns here to calculate the requested stack,
28869 so that the linker can edit them when adjusting size for calling
28870 non-split-stack code. */
28871 alloc_hi
= (-allocate
+ 0x8000) & ~0xffffL
;
28872 alloc_lo
= -allocate
- alloc_hi
;
28875 emit_insn (gen_add3_const (r12
, r1
, alloc_hi
));
28877 emit_insn (gen_add3_const (r12
, r12
, alloc_lo
));
28879 emit_insn (gen_nop ());
28883 emit_insn (gen_add3_const (r12
, r1
, alloc_lo
));
28884 emit_insn (gen_nop ());
28887 compare
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
28888 emit_insn (gen_rtx_SET (compare
, gen_rtx_COMPARE (CCUNSmode
, r12
, r0
)));
28889 ok_label
= gen_label_rtx ();
28890 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
28891 gen_rtx_GEU (VOIDmode
, compare
, const0_rtx
),
28892 gen_rtx_LABEL_REF (VOIDmode
, ok_label
),
28894 insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
28895 JUMP_LABEL (insn
) = ok_label
;
28896 /* Mark the jump as very likely to be taken. */
28897 add_reg_br_prob_note (insn
, profile_probability::very_likely ());
28899 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
28900 insn
= emit_move_insn (r0
, lr
);
28901 RTX_FRAME_RELATED_P (insn
) = 1;
28902 insn
= emit_insn (gen_frame_store (r0
, r1
, info
->lr_save_offset
));
28903 RTX_FRAME_RELATED_P (insn
) = 1;
28905 insn
= emit_call_insn (gen_call (gen_rtx_MEM (SImode
, morestack_ref
),
28906 const0_rtx
, const0_rtx
));
28907 call_fusage
= NULL_RTX
;
28908 use_reg (&call_fusage
, r12
);
28909 /* Say the call uses r0, even though it doesn't, to stop regrename
28910 from twiddling with the insns saving lr, trashing args for cfun.
28911 The insns restoring lr are similarly protected by making
28912 split_stack_return use r0. */
28913 use_reg (&call_fusage
, r0
);
28914 add_function_usage_to (insn
, call_fusage
);
28915 /* Indicate that this function can't jump to non-local gotos. */
28916 make_reg_eh_region_note_nothrow_nononlocal (insn
);
28917 emit_insn (gen_frame_load (r0
, r1
, info
->lr_save_offset
));
28918 insn
= emit_move_insn (lr
, r0
);
28919 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
28920 RTX_FRAME_RELATED_P (insn
) = 1;
28921 emit_insn (gen_split_stack_return ());
28923 emit_label (ok_label
);
28924 LABEL_NUSES (ok_label
) = 1;
28927 /* Return the internal arg pointer used for function incoming
28928 arguments. When -fsplit-stack, the arg pointer is r12 so we need
28929 to copy it to a pseudo in order for it to be preserved over calls
28930 and suchlike. We'd really like to use a pseudo here for the
28931 internal arg pointer but data-flow analysis is not prepared to
28932 accept pseudos as live at the beginning of a function. */
28935 rs6000_internal_arg_pointer (void)
28937 if (flag_split_stack
28938 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
28942 if (cfun
->machine
->split_stack_arg_pointer
== NULL_RTX
)
28946 cfun
->machine
->split_stack_arg_pointer
= gen_reg_rtx (Pmode
);
28947 REG_POINTER (cfun
->machine
->split_stack_arg_pointer
) = 1;
28949 /* Put the pseudo initialization right after the note at the
28950 beginning of the function. */
28951 pat
= gen_rtx_SET (cfun
->machine
->split_stack_arg_pointer
,
28952 gen_rtx_REG (Pmode
, 12));
28953 push_topmost_sequence ();
28954 emit_insn_after (pat
, get_insns ());
28955 pop_topmost_sequence ();
28957 rtx ret
= plus_constant (Pmode
, cfun
->machine
->split_stack_arg_pointer
,
28958 FIRST_PARM_OFFSET (current_function_decl
));
28959 return copy_to_reg (ret
);
28961 return virtual_incoming_args_rtx
;
28964 /* We may have to tell the dataflow pass that the split stack prologue
28965 is initializing a register. */
28968 rs6000_live_on_entry (bitmap regs
)
28970 if (flag_split_stack
)
28971 bitmap_set_bit (regs
, 12);
28974 /* Emit -fsplit-stack dynamic stack allocation space check. */
28977 rs6000_split_stack_space_check (rtx size
, rtx label
)
28979 rtx sp
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
28980 rtx limit
= gen_reg_rtx (Pmode
);
28981 rtx requested
= gen_reg_rtx (Pmode
);
28982 rtx cmp
= gen_reg_rtx (CCUNSmode
);
28985 emit_insn (gen_load_split_stack_limit (limit
));
28986 if (CONST_INT_P (size
))
28987 emit_insn (gen_add3_insn (requested
, sp
, GEN_INT (-INTVAL (size
))));
28990 size
= force_reg (Pmode
, size
);
28991 emit_move_insn (requested
, gen_rtx_MINUS (Pmode
, sp
, size
));
28993 emit_insn (gen_rtx_SET (cmp
, gen_rtx_COMPARE (CCUNSmode
, requested
, limit
)));
28994 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
28995 gen_rtx_GEU (VOIDmode
, cmp
, const0_rtx
),
28996 gen_rtx_LABEL_REF (VOIDmode
, label
),
28998 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
28999 JUMP_LABEL (jump
) = label
;
29002 /* A C compound statement that outputs the assembler code for a thunk
29003 function, used to implement C++ virtual function calls with
29004 multiple inheritance. The thunk acts as a wrapper around a virtual
29005 function, adjusting the implicit object parameter before handing
29006 control off to the real function.
29008 First, emit code to add the integer DELTA to the location that
29009 contains the incoming first argument. Assume that this argument
29010 contains a pointer, and is the one used to pass the `this' pointer
29011 in C++. This is the incoming argument *before* the function
29012 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29013 values of all other incoming arguments.
29015 After the addition, emit code to jump to FUNCTION, which is a
29016 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29017 not touch the return address. Hence returning from FUNCTION will
29018 return to whoever called the current `thunk'.
29020 The effect must be as if FUNCTION had been called directly with the
29021 adjusted first argument. This macro is responsible for emitting
29022 all of the code for a thunk function; output_function_prologue()
29023 and output_function_epilogue() are not invoked.
29025 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29026 been extracted from it.) It might possibly be useful on some
29027 targets, but probably not.
29029 If you do not define this macro, the target-independent code in the
29030 C++ frontend will generate a less efficient heavyweight thunk that
29031 calls FUNCTION instead of jumping to it. The generic approach does
29032 not support varargs. */
29035 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
29036 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
29039 rtx this_rtx
, funexp
;
29042 reload_completed
= 1;
29043 epilogue_completed
= 1;
29045 /* Mark the end of the (empty) prologue. */
29046 emit_note (NOTE_INSN_PROLOGUE_END
);
29048 /* Find the "this" pointer. If the function returns a structure,
29049 the structure return pointer is in r3. */
29050 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
29051 this_rtx
= gen_rtx_REG (Pmode
, 4);
29053 this_rtx
= gen_rtx_REG (Pmode
, 3);
29055 /* Apply the constant offset, if required. */
29057 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
29059 /* Apply the offset from the vtable, if required. */
29062 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
29063 rtx tmp
= gen_rtx_REG (Pmode
, 12);
29065 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
29066 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
29068 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
29069 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
29073 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
29075 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
29077 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
29080 /* Generate a tail call to the target function. */
29081 if (!TREE_USED (function
))
29083 assemble_external (function
);
29084 TREE_USED (function
) = 1;
29086 funexp
= XEXP (DECL_RTL (function
), 0);
29087 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
29090 if (MACHOPIC_INDIRECT
)
29091 funexp
= machopic_indirect_call_target (funexp
);
29094 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29095 generate sibcall RTL explicitly. */
29096 insn
= emit_call_insn (
29097 gen_rtx_PARALLEL (VOIDmode
,
29099 gen_rtx_CALL (VOIDmode
,
29100 funexp
, const0_rtx
),
29101 gen_rtx_USE (VOIDmode
, const0_rtx
),
29102 simple_return_rtx
)));
29103 SIBLING_CALL_P (insn
) = 1;
29106 /* Run just enough of rest_of_compilation to get the insns emitted.
29107 There's not really enough bulk here to make other passes such as
29108 instruction scheduling worth while. Note that use_thunk calls
29109 assemble_start_function and assemble_end_function. */
29110 insn
= get_insns ();
29111 shorten_branches (insn
);
29112 final_start_function (insn
, file
, 1);
29113 final (insn
, file
, 1);
29114 final_end_function ();
29116 reload_completed
= 0;
29117 epilogue_completed
= 0;
29120 /* A quick summary of the various types of 'constant-pool tables'
29123 Target Flags Name One table per
29124 AIX (none) AIX TOC object file
29125 AIX -mfull-toc AIX TOC object file
29126 AIX -mminimal-toc AIX minimal TOC translation unit
29127 SVR4/EABI (none) SVR4 SDATA object file
29128 SVR4/EABI -fpic SVR4 pic object file
29129 SVR4/EABI -fPIC SVR4 PIC translation unit
29130 SVR4/EABI -mrelocatable EABI TOC function
29131 SVR4/EABI -maix AIX TOC object file
29132 SVR4/EABI -maix -mminimal-toc
29133 AIX minimal TOC translation unit
29135 Name Reg. Set by entries contains:
29136 made by addrs? fp? sum?
29138 AIX TOC 2 crt0 as Y option option
29139 AIX minimal TOC 30 prolog gcc Y Y option
29140 SVR4 SDATA 13 crt0 gcc N Y N
29141 SVR4 pic 30 prolog ld Y not yet N
29142 SVR4 PIC 30 prolog gcc Y option option
29143 EABI TOC 30 prolog gcc Y option option
29147 /* Hash functions for the hash table. */
29150 rs6000_hash_constant (rtx k
)
29152 enum rtx_code code
= GET_CODE (k
);
29153 machine_mode mode
= GET_MODE (k
);
29154 unsigned result
= (code
<< 3) ^ mode
;
29155 const char *format
;
29158 format
= GET_RTX_FORMAT (code
);
29159 flen
= strlen (format
);
29165 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
29167 case CONST_WIDE_INT
:
29170 flen
= CONST_WIDE_INT_NUNITS (k
);
29171 for (i
= 0; i
< flen
; i
++)
29172 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
29177 if (mode
!= VOIDmode
)
29178 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
29190 for (; fidx
< flen
; fidx
++)
29191 switch (format
[fidx
])
29196 const char *str
= XSTR (k
, fidx
);
29197 len
= strlen (str
);
29198 result
= result
* 613 + len
;
29199 for (i
= 0; i
< len
; i
++)
29200 result
= result
* 613 + (unsigned) str
[i
];
29205 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
29209 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
29212 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
29213 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
29217 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
29218 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
29225 gcc_unreachable ();
29232 toc_hasher::hash (toc_hash_struct
*thc
)
29234 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
29237 /* Compare H1 and H2 for equivalence. */
29240 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
29245 if (h1
->key_mode
!= h2
->key_mode
)
29248 return rtx_equal_p (r1
, r2
);
29251 /* These are the names given by the C++ front-end to vtables, and
29252 vtable-like objects. Ideally, this logic should not be here;
29253 instead, there should be some programmatic way of inquiring as
29254 to whether or not an object is a vtable. */
29256 #define VTABLE_NAME_P(NAME) \
29257 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29258 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29259 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29260 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29261 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29263 #ifdef NO_DOLLAR_IN_LABEL
29264 /* Return a GGC-allocated character string translating dollar signs in
29265 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29268 rs6000_xcoff_strip_dollar (const char *name
)
29274 q
= (const char *) strchr (name
, '$');
29276 if (q
== 0 || q
== name
)
29279 len
= strlen (name
);
29280 strip
= XALLOCAVEC (char, len
+ 1);
29281 strcpy (strip
, name
);
29282 p
= strip
+ (q
- name
);
29286 p
= strchr (p
+ 1, '$');
29289 return ggc_alloc_string (strip
, len
);
29294 rs6000_output_symbol_ref (FILE *file
, rtx x
)
29296 const char *name
= XSTR (x
, 0);
29298 /* Currently C++ toc references to vtables can be emitted before it
29299 is decided whether the vtable is public or private. If this is
29300 the case, then the linker will eventually complain that there is
29301 a reference to an unknown section. Thus, for vtables only,
29302 we emit the TOC reference to reference the identifier and not the
29304 if (VTABLE_NAME_P (name
))
29306 RS6000_OUTPUT_BASENAME (file
, name
);
29309 assemble_name (file
, name
);
29312 /* Output a TOC entry. We derive the entry name from what is being
29316 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
29319 const char *name
= buf
;
29321 HOST_WIDE_INT offset
= 0;
29323 gcc_assert (!TARGET_NO_TOC
);
29325 /* When the linker won't eliminate them, don't output duplicate
29326 TOC entries (this happens on AIX if there is any kind of TOC,
29327 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29329 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
29331 struct toc_hash_struct
*h
;
29333 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29334 time because GGC is not initialized at that point. */
29335 if (toc_hash_table
== NULL
)
29336 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
29338 h
= ggc_alloc
<toc_hash_struct
> ();
29340 h
->key_mode
= mode
;
29341 h
->labelno
= labelno
;
29343 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
29344 if (*found
== NULL
)
29346 else /* This is indeed a duplicate.
29347 Set this label equal to that label. */
29349 fputs ("\t.set ", file
);
29350 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29351 fprintf (file
, "%d,", labelno
);
29352 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29353 fprintf (file
, "%d\n", ((*found
)->labelno
));
29356 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
29357 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
29358 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
29360 fputs ("\t.set ", file
);
29361 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29362 fprintf (file
, "%d,", labelno
);
29363 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29364 fprintf (file
, "%d\n", ((*found
)->labelno
));
29371 /* If we're going to put a double constant in the TOC, make sure it's
29372 aligned properly when strict alignment is on. */
29373 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
29374 && STRICT_ALIGNMENT
29375 && GET_MODE_BITSIZE (mode
) >= 64
29376 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
29377 ASM_OUTPUT_ALIGN (file
, 3);
29380 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
29382 /* Handle FP constants specially. Note that if we have a minimal
29383 TOC, things we put here aren't actually in the TOC, so we can allow
29385 if (GET_CODE (x
) == CONST_DOUBLE
&&
29386 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
29387 || GET_MODE (x
) == IFmode
|| GET_MODE (x
) == KFmode
))
29391 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29392 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29394 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29398 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29399 fputs (DOUBLE_INT_ASM_OP
, file
);
29401 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29402 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29403 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29404 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
29405 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29406 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
29407 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
29408 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
29413 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29414 fputs ("\t.long ", file
);
29416 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29417 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29418 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29419 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29420 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29421 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29425 else if (GET_CODE (x
) == CONST_DOUBLE
&&
29426 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
29430 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29431 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29433 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29437 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29438 fputs (DOUBLE_INT_ASM_OP
, file
);
29440 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29441 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29442 fprintf (file
, "0x%lx%08lx\n",
29443 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29444 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
29449 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29450 fputs ("\t.long ", file
);
29452 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29453 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29454 fprintf (file
, "0x%lx,0x%lx\n",
29455 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29459 else if (GET_CODE (x
) == CONST_DOUBLE
&&
29460 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
29464 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29465 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29467 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29471 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29472 fputs (DOUBLE_INT_ASM_OP
, file
);
29474 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
29475 if (WORDS_BIG_ENDIAN
)
29476 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
29478 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
29483 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29484 fputs ("\t.long ", file
);
29486 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
29487 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
29491 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
29493 unsigned HOST_WIDE_INT low
;
29494 HOST_WIDE_INT high
;
29496 low
= INTVAL (x
) & 0xffffffff;
29497 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
29499 /* TOC entries are always Pmode-sized, so when big-endian
29500 smaller integer constants in the TOC need to be padded.
29501 (This is still a win over putting the constants in
29502 a separate constant pool, because then we'd have
29503 to have both a TOC entry _and_ the actual constant.)
29505 For a 32-bit target, CONST_INT values are loaded and shifted
29506 entirely within `low' and can be stored in one TOC entry. */
29508 /* It would be easy to make this work, but it doesn't now. */
29509 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
29511 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
29514 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
29515 high
= (HOST_WIDE_INT
) low
>> 32;
29521 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29522 fputs (DOUBLE_INT_ASM_OP
, file
);
29524 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
29525 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29526 fprintf (file
, "0x%lx%08lx\n",
29527 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29532 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
29534 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29535 fputs ("\t.long ", file
);
29537 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
29538 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29539 fprintf (file
, "0x%lx,0x%lx\n",
29540 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
29544 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29545 fputs ("\t.long ", file
);
29547 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
29548 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
29554 if (GET_CODE (x
) == CONST
)
29556 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
29557 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
29559 base
= XEXP (XEXP (x
, 0), 0);
29560 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
29563 switch (GET_CODE (base
))
29566 name
= XSTR (base
, 0);
29570 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
29571 CODE_LABEL_NUMBER (XEXP (base
, 0)));
29575 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
29579 gcc_unreachable ();
29582 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29583 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
29586 fputs ("\t.tc ", file
);
29587 RS6000_OUTPUT_BASENAME (file
, name
);
29590 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
29592 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
29594 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29595 after other TOC symbols, reducing overflow of small TOC access
29596 to [TC] symbols. */
29597 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
29598 ? "[TE]," : "[TC],", file
);
29601 /* Currently C++ toc references to vtables can be emitted before it
29602 is decided whether the vtable is public or private. If this is
29603 the case, then the linker will eventually complain that there is
29604 a TOC reference to an unknown section. Thus, for vtables only,
29605 we emit the TOC reference to reference the symbol and not the
29607 if (VTABLE_NAME_P (name
))
29609 RS6000_OUTPUT_BASENAME (file
, name
);
29611 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
29612 else if (offset
> 0)
29613 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
29616 output_addr_const (file
, x
);
29619 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
)
29621 switch (SYMBOL_REF_TLS_MODEL (base
))
29625 case TLS_MODEL_LOCAL_EXEC
:
29626 fputs ("@le", file
);
29628 case TLS_MODEL_INITIAL_EXEC
:
29629 fputs ("@ie", file
);
29631 /* Use global-dynamic for local-dynamic. */
29632 case TLS_MODEL_GLOBAL_DYNAMIC
:
29633 case TLS_MODEL_LOCAL_DYNAMIC
:
29635 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
29636 fputs ("\t.tc .", file
);
29637 RS6000_OUTPUT_BASENAME (file
, name
);
29638 fputs ("[TC],", file
);
29639 output_addr_const (file
, x
);
29640 fputs ("@m", file
);
29643 gcc_unreachable ();
29651 /* Output an assembler pseudo-op to write an ASCII string of N characters
29652 starting at P to FILE.
29654 On the RS/6000, we have to do this using the .byte operation and
29655 write out special characters outside the quoted string.
29656 Also, the assembler is broken; very long strings are truncated,
29657 so we must artificially break them up early. */
29660 output_ascii (FILE *file
, const char *p
, int n
)
29663 int i
, count_string
;
29664 const char *for_string
= "\t.byte \"";
29665 const char *for_decimal
= "\t.byte ";
29666 const char *to_close
= NULL
;
29669 for (i
= 0; i
< n
; i
++)
29672 if (c
>= ' ' && c
< 0177)
29675 fputs (for_string
, file
);
29678 /* Write two quotes to get one. */
29686 for_decimal
= "\"\n\t.byte ";
29690 if (count_string
>= 512)
29692 fputs (to_close
, file
);
29694 for_string
= "\t.byte \"";
29695 for_decimal
= "\t.byte ";
29703 fputs (for_decimal
, file
);
29704 fprintf (file
, "%d", c
);
29706 for_string
= "\n\t.byte \"";
29707 for_decimal
= ", ";
29713 /* Now close the string if we have written one. Then end the line. */
29715 fputs (to_close
, file
);
29718 /* Generate a unique section name for FILENAME for a section type
29719 represented by SECTION_DESC. Output goes into BUF.
29721 SECTION_DESC can be any string, as long as it is different for each
29722 possible section type.
29724 We name the section in the same manner as xlc. The name begins with an
29725 underscore followed by the filename (after stripping any leading directory
29726 names) with the last period replaced by the string SECTION_DESC. If
29727 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29731 rs6000_gen_section_name (char **buf
, const char *filename
,
29732 const char *section_desc
)
29734 const char *q
, *after_last_slash
, *last_period
= 0;
29738 after_last_slash
= filename
;
29739 for (q
= filename
; *q
; q
++)
29742 after_last_slash
= q
+ 1;
29743 else if (*q
== '.')
29747 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
29748 *buf
= (char *) xmalloc (len
);
29753 for (q
= after_last_slash
; *q
; q
++)
29755 if (q
== last_period
)
29757 strcpy (p
, section_desc
);
29758 p
+= strlen (section_desc
);
29762 else if (ISALNUM (*q
))
29766 if (last_period
== 0)
29767 strcpy (p
, section_desc
);
29772 /* Emit profile function. */
29775 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
29777 /* Non-standard profiling for kernels, which just saves LR then calls
29778 _mcount without worrying about arg saves. The idea is to change
29779 the function prologue as little as possible as it isn't easy to
29780 account for arg save/restore code added just for _mcount. */
29781 if (TARGET_PROFILE_KERNEL
)
29784 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29786 #ifndef NO_PROFILE_COUNTERS
29787 # define NO_PROFILE_COUNTERS 0
29789 if (NO_PROFILE_COUNTERS
)
29790 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
29791 LCT_NORMAL
, VOIDmode
);
29795 const char *label_name
;
29798 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
29799 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
29800 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
29802 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
29803 LCT_NORMAL
, VOIDmode
, fun
, Pmode
);
29806 else if (DEFAULT_ABI
== ABI_DARWIN
)
29808 const char *mcount_name
= RS6000_MCOUNT
;
29809 int caller_addr_regno
= LR_REGNO
;
29811 /* Be conservative and always set this, at least for now. */
29812 crtl
->uses_pic_offset_table
= 1;
29815 /* For PIC code, set up a stub and collect the caller's address
29816 from r0, which is where the prologue puts it. */
29817 if (MACHOPIC_INDIRECT
29818 && crtl
->uses_pic_offset_table
)
29819 caller_addr_regno
= 0;
29821 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
29822 LCT_NORMAL
, VOIDmode
,
29823 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
29827 /* Write function profiler code. */
29830 output_function_profiler (FILE *file
, int labelno
)
29834 switch (DEFAULT_ABI
)
29837 gcc_unreachable ();
29842 warning (0, "no profiling of 64-bit code for this ABI");
29845 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
29846 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
29847 if (NO_PROFILE_COUNTERS
)
29849 asm_fprintf (file
, "\tstw %s,4(%s)\n",
29850 reg_names
[0], reg_names
[1]);
29852 else if (TARGET_SECURE_PLT
&& flag_pic
)
29854 if (TARGET_LINK_STACK
)
29857 get_ppc476_thunk_name (name
);
29858 asm_fprintf (file
, "\tbl %s\n", name
);
29861 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
29862 asm_fprintf (file
, "\tstw %s,4(%s)\n",
29863 reg_names
[0], reg_names
[1]);
29864 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
29865 asm_fprintf (file
, "\taddis %s,%s,",
29866 reg_names
[12], reg_names
[12]);
29867 assemble_name (file
, buf
);
29868 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
29869 assemble_name (file
, buf
);
29870 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
29872 else if (flag_pic
== 1)
29874 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
29875 asm_fprintf (file
, "\tstw %s,4(%s)\n",
29876 reg_names
[0], reg_names
[1]);
29877 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
29878 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
29879 assemble_name (file
, buf
);
29880 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
29882 else if (flag_pic
> 1)
29884 asm_fprintf (file
, "\tstw %s,4(%s)\n",
29885 reg_names
[0], reg_names
[1]);
29886 /* Now, we need to get the address of the label. */
29887 if (TARGET_LINK_STACK
)
29890 get_ppc476_thunk_name (name
);
29891 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
29892 assemble_name (file
, buf
);
29893 fputs ("-.\n1:", file
);
29894 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
29895 asm_fprintf (file
, "\taddi %s,%s,4\n",
29896 reg_names
[11], reg_names
[11]);
29900 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
29901 assemble_name (file
, buf
);
29902 fputs ("-.\n1:", file
);
29903 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
29905 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
29906 reg_names
[0], reg_names
[11]);
29907 asm_fprintf (file
, "\tadd %s,%s,%s\n",
29908 reg_names
[0], reg_names
[0], reg_names
[11]);
29912 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
29913 assemble_name (file
, buf
);
29914 fputs ("@ha\n", file
);
29915 asm_fprintf (file
, "\tstw %s,4(%s)\n",
29916 reg_names
[0], reg_names
[1]);
29917 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
29918 assemble_name (file
, buf
);
29919 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
29922 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
29923 fprintf (file
, "\tbl %s%s\n",
29924 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
29930 /* Don't do anything, done in output_profile_hook (). */
29937 /* The following variable value is the last issued insn. */
29939 static rtx_insn
*last_scheduled_insn
;
29941 /* The following variable helps to balance issuing of load and
29942 store instructions */
29944 static int load_store_pendulum
;
29946 /* The following variable helps pair divide insns during scheduling. */
29947 static int divide_cnt
;
29948 /* The following variable helps pair and alternate vector and vector load
29949 insns during scheduling. */
29950 static int vec_pairing
;
29953 /* Power4 load update and store update instructions are cracked into a
29954 load or store and an integer insn which are executed in the same cycle.
29955 Branches have their own dispatch slot which does not count against the
29956 GCC issue rate, but it changes the program flow so there are no other
29957 instructions to issue in this cycle. */
29960 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
29962 last_scheduled_insn
= insn
;
29963 if (GET_CODE (PATTERN (insn
)) == USE
29964 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
29966 cached_can_issue_more
= more
;
29967 return cached_can_issue_more
;
29970 if (insn_terminates_group_p (insn
, current_group
))
29972 cached_can_issue_more
= 0;
29973 return cached_can_issue_more
;
29976 /* If no reservation, but reach here */
29977 if (recog_memoized (insn
) < 0)
29980 if (rs6000_sched_groups
)
29982 if (is_microcoded_insn (insn
))
29983 cached_can_issue_more
= 0;
29984 else if (is_cracked_insn (insn
))
29985 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
29987 cached_can_issue_more
= more
- 1;
29989 return cached_can_issue_more
;
29992 if (rs6000_tune
== PROCESSOR_CELL
&& is_nonpipeline_insn (insn
))
29995 cached_can_issue_more
= more
- 1;
29996 return cached_can_issue_more
;
30000 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
30002 int r
= rs6000_variable_issue_1 (insn
, more
);
30004 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
30008 /* Adjust the cost of a scheduling dependency. Return the new cost of
30009 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30012 rs6000_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
30015 enum attr_type attr_type
;
30017 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
30024 /* Data dependency; DEP_INSN writes a register that INSN reads
30025 some cycles later. */
30027 /* Separate a load from a narrower, dependent store. */
30028 if ((rs6000_sched_groups
|| rs6000_tune
== PROCESSOR_POWER9
)
30029 && GET_CODE (PATTERN (insn
)) == SET
30030 && GET_CODE (PATTERN (dep_insn
)) == SET
30031 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
30032 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
30033 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
30034 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
30037 attr_type
= get_attr_type (insn
);
30042 /* Tell the first scheduling pass about the latency between
30043 a mtctr and bctr (and mtlr and br/blr). The first
30044 scheduling pass will not know about this latency since
30045 the mtctr instruction, which has the latency associated
30046 to it, will be generated by reload. */
30049 /* Leave some extra cycles between a compare and its
30050 dependent branch, to inhibit expensive mispredicts. */
30051 if ((rs6000_tune
== PROCESSOR_PPC603
30052 || rs6000_tune
== PROCESSOR_PPC604
30053 || rs6000_tune
== PROCESSOR_PPC604e
30054 || rs6000_tune
== PROCESSOR_PPC620
30055 || rs6000_tune
== PROCESSOR_PPC630
30056 || rs6000_tune
== PROCESSOR_PPC750
30057 || rs6000_tune
== PROCESSOR_PPC7400
30058 || rs6000_tune
== PROCESSOR_PPC7450
30059 || rs6000_tune
== PROCESSOR_PPCE5500
30060 || rs6000_tune
== PROCESSOR_PPCE6500
30061 || rs6000_tune
== PROCESSOR_POWER4
30062 || rs6000_tune
== PROCESSOR_POWER5
30063 || rs6000_tune
== PROCESSOR_POWER7
30064 || rs6000_tune
== PROCESSOR_POWER8
30065 || rs6000_tune
== PROCESSOR_POWER9
30066 || rs6000_tune
== PROCESSOR_CELL
)
30067 && recog_memoized (dep_insn
)
30068 && (INSN_CODE (dep_insn
) >= 0))
30070 switch (get_attr_type (dep_insn
))
30073 case TYPE_FPCOMPARE
:
30074 case TYPE_CR_LOGICAL
:
30078 if (get_attr_dot (dep_insn
) == DOT_YES
)
30083 if (get_attr_dot (dep_insn
) == DOT_YES
30084 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
30095 if ((rs6000_tune
== PROCESSOR_POWER6
)
30096 && recog_memoized (dep_insn
)
30097 && (INSN_CODE (dep_insn
) >= 0))
30100 if (GET_CODE (PATTERN (insn
)) != SET
)
30101 /* If this happens, we have to extend this to schedule
30102 optimally. Return default for now. */
30105 /* Adjust the cost for the case where the value written
30106 by a fixed point operation is used as the address
30107 gen value on a store. */
30108 switch (get_attr_type (dep_insn
))
30113 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30114 return get_attr_sign_extend (dep_insn
)
30115 == SIGN_EXTEND_YES
? 6 : 4;
30120 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30121 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30131 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30139 if (get_attr_update (dep_insn
) == UPDATE_YES
30140 && ! rs6000_store_data_bypass_p (dep_insn
, insn
))
30146 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30152 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30153 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30163 if ((rs6000_tune
== PROCESSOR_POWER6
)
30164 && recog_memoized (dep_insn
)
30165 && (INSN_CODE (dep_insn
) >= 0))
30168 /* Adjust the cost for the case where the value written
30169 by a fixed point instruction is used within the address
30170 gen portion of a subsequent load(u)(x) */
30171 switch (get_attr_type (dep_insn
))
30176 if (set_to_load_agen (dep_insn
, insn
))
30177 return get_attr_sign_extend (dep_insn
)
30178 == SIGN_EXTEND_YES
? 6 : 4;
30183 if (set_to_load_agen (dep_insn
, insn
))
30184 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30194 if (set_to_load_agen (dep_insn
, insn
))
30202 if (get_attr_update (dep_insn
) == UPDATE_YES
30203 && set_to_load_agen (dep_insn
, insn
))
30209 if (set_to_load_agen (dep_insn
, insn
))
30215 if (set_to_load_agen (dep_insn
, insn
))
30216 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30226 if ((rs6000_tune
== PROCESSOR_POWER6
)
30227 && get_attr_update (insn
) == UPDATE_NO
30228 && recog_memoized (dep_insn
)
30229 && (INSN_CODE (dep_insn
) >= 0)
30230 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
30237 /* Fall out to return default cost. */
30241 case REG_DEP_OUTPUT
:
30242 /* Output dependency; DEP_INSN writes a register that INSN writes some
30244 if ((rs6000_tune
== PROCESSOR_POWER6
)
30245 && recog_memoized (dep_insn
)
30246 && (INSN_CODE (dep_insn
) >= 0))
30248 attr_type
= get_attr_type (insn
);
30253 case TYPE_FPSIMPLE
:
30254 if (get_attr_type (dep_insn
) == TYPE_FP
30255 || get_attr_type (dep_insn
) == TYPE_FPSIMPLE
)
30259 if (get_attr_update (insn
) == UPDATE_NO
30260 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
30267 /* Fall through, no cost for output dependency. */
30271 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30276 gcc_unreachable ();
30282 /* Debug version of rs6000_adjust_cost. */
30285 rs6000_debug_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
30286 int cost
, unsigned int dw
)
30288 int ret
= rs6000_adjust_cost (insn
, dep_type
, dep_insn
, cost
, dw
);
30296 default: dep
= "unknown depencency"; break;
30297 case REG_DEP_TRUE
: dep
= "data dependency"; break;
30298 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
30299 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
30303 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30304 "%s, insn:\n", ret
, cost
, dep
);
30312 /* The function returns a true if INSN is microcoded.
30313 Return false otherwise. */
30316 is_microcoded_insn (rtx_insn
*insn
)
30318 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30319 || GET_CODE (PATTERN (insn
)) == USE
30320 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30323 if (rs6000_tune
== PROCESSOR_CELL
)
30324 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
30326 if (rs6000_sched_groups
30327 && (rs6000_tune
== PROCESSOR_POWER4
|| rs6000_tune
== PROCESSOR_POWER5
))
30329 enum attr_type type
= get_attr_type (insn
);
30330 if ((type
== TYPE_LOAD
30331 && get_attr_update (insn
) == UPDATE_YES
30332 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
30333 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
30334 && get_attr_update (insn
) == UPDATE_YES
30335 && get_attr_indexed (insn
) == INDEXED_YES
)
30336 || type
== TYPE_MFCR
)
30343 /* The function returns true if INSN is cracked into 2 instructions
30344 by the processor (and therefore occupies 2 issue slots). */
30347 is_cracked_insn (rtx_insn
*insn
)
30349 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30350 || GET_CODE (PATTERN (insn
)) == USE
30351 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30354 if (rs6000_sched_groups
30355 && (rs6000_tune
== PROCESSOR_POWER4
|| rs6000_tune
== PROCESSOR_POWER5
))
30357 enum attr_type type
= get_attr_type (insn
);
30358 if ((type
== TYPE_LOAD
30359 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
30360 && get_attr_update (insn
) == UPDATE_NO
)
30361 || (type
== TYPE_LOAD
30362 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
30363 && get_attr_update (insn
) == UPDATE_YES
30364 && get_attr_indexed (insn
) == INDEXED_NO
)
30365 || (type
== TYPE_STORE
30366 && get_attr_update (insn
) == UPDATE_YES
30367 && get_attr_indexed (insn
) == INDEXED_NO
)
30368 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
30369 && get_attr_update (insn
) == UPDATE_YES
)
30370 || (type
== TYPE_CR_LOGICAL
30371 && get_attr_cr_logical_3op (insn
) == CR_LOGICAL_3OP_YES
)
30372 || (type
== TYPE_EXTS
30373 && get_attr_dot (insn
) == DOT_YES
)
30374 || (type
== TYPE_SHIFT
30375 && get_attr_dot (insn
) == DOT_YES
30376 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
30377 || (type
== TYPE_MUL
30378 && get_attr_dot (insn
) == DOT_YES
)
30379 || type
== TYPE_DIV
30380 || (type
== TYPE_INSERT
30381 && get_attr_size (insn
) == SIZE_32
))
30388 /* The function returns true if INSN can be issued only from
30389 the branch slot. */
30392 is_branch_slot_insn (rtx_insn
*insn
)
30394 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30395 || GET_CODE (PATTERN (insn
)) == USE
30396 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30399 if (rs6000_sched_groups
)
30401 enum attr_type type
= get_attr_type (insn
);
30402 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
30410 /* The function returns true if out_inst sets a value that is
30411 used in the address generation computation of in_insn */
30413 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
30415 rtx out_set
, in_set
;
30417 /* For performance reasons, only handle the simple case where
30418 both loads are a single_set. */
30419 out_set
= single_set (out_insn
);
30422 in_set
= single_set (in_insn
);
30424 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
30430 /* Try to determine base/offset/size parts of the given MEM.
30431 Return true if successful, false if all the values couldn't
30434 This function only looks for REG or REG+CONST address forms.
30435 REG+REG address form will return false. */
30438 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
30439 HOST_WIDE_INT
*size
)
30442 if MEM_SIZE_KNOWN_P (mem
)
30443 *size
= MEM_SIZE (mem
);
30447 addr_rtx
= (XEXP (mem
, 0));
30448 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
30449 addr_rtx
= XEXP (addr_rtx
, 1);
30452 while (GET_CODE (addr_rtx
) == PLUS
30453 && CONST_INT_P (XEXP (addr_rtx
, 1)))
30455 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
30456 addr_rtx
= XEXP (addr_rtx
, 0);
30458 if (!REG_P (addr_rtx
))
30465 /* The function returns true if the target storage location of
30466 mem1 is adjacent to the target storage location of mem2 */
30467 /* Return 1 if memory locations are adjacent. */
30470 adjacent_mem_locations (rtx mem1
, rtx mem2
)
30473 HOST_WIDE_INT off1
, size1
, off2
, size2
;
30475 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
30476 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
30477 return ((REGNO (reg1
) == REGNO (reg2
))
30478 && ((off1
+ size1
== off2
)
30479 || (off2
+ size2
== off1
)));
30484 /* This function returns true if it can be determined that the two MEM
30485 locations overlap by at least 1 byte based on base reg/offset/size. */
30488 mem_locations_overlap (rtx mem1
, rtx mem2
)
30491 HOST_WIDE_INT off1
, size1
, off2
, size2
;
30493 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
30494 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
30495 return ((REGNO (reg1
) == REGNO (reg2
))
30496 && (((off1
<= off2
) && (off1
+ size1
> off2
))
30497 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
30502 /* A C statement (sans semicolon) to update the integer scheduling
30503 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30504 INSN earlier, reduce the priority to execute INSN later. Do not
30505 define this macro if you do not need to adjust the scheduling
30506 priorities of insns. */
30509 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
30511 rtx load_mem
, str_mem
;
30512 /* On machines (like the 750) which have asymmetric integer units,
30513 where one integer unit can do multiply and divides and the other
30514 can't, reduce the priority of multiply/divide so it is scheduled
30515 before other integer operations. */
30518 if (! INSN_P (insn
))
30521 if (GET_CODE (PATTERN (insn
)) == USE
)
30524 switch (rs6000_tune
) {
30525 case PROCESSOR_PPC750
:
30526 switch (get_attr_type (insn
))
30533 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
30534 priority
, priority
);
30535 if (priority
>= 0 && priority
< 0x01000000)
30542 if (insn_must_be_first_in_group (insn
)
30543 && reload_completed
30544 && current_sched_info
->sched_max_insns_priority
30545 && rs6000_sched_restricted_insns_priority
)
30548 /* Prioritize insns that can be dispatched only in the first
30550 if (rs6000_sched_restricted_insns_priority
== 1)
30551 /* Attach highest priority to insn. This means that in
30552 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30553 precede 'priority' (critical path) considerations. */
30554 return current_sched_info
->sched_max_insns_priority
;
30555 else if (rs6000_sched_restricted_insns_priority
== 2)
30556 /* Increase priority of insn by a minimal amount. This means that in
30557 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30558 considerations precede dispatch-slot restriction considerations. */
30559 return (priority
+ 1);
30562 if (rs6000_tune
== PROCESSOR_POWER6
30563 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
30564 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
30565 /* Attach highest priority to insn if the scheduler has just issued two
30566 stores and this instruction is a load, or two loads and this instruction
30567 is a store. Power6 wants loads and stores scheduled alternately
30569 return current_sched_info
->sched_max_insns_priority
;
30574 /* Return true if the instruction is nonpipelined on the Cell. */
30576 is_nonpipeline_insn (rtx_insn
*insn
)
30578 enum attr_type type
;
30579 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30580 || GET_CODE (PATTERN (insn
)) == USE
30581 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30584 type
= get_attr_type (insn
);
30585 if (type
== TYPE_MUL
30586 || type
== TYPE_DIV
30587 || type
== TYPE_SDIV
30588 || type
== TYPE_DDIV
30589 || type
== TYPE_SSQRT
30590 || type
== TYPE_DSQRT
30591 || type
== TYPE_MFCR
30592 || type
== TYPE_MFCRF
30593 || type
== TYPE_MFJMPR
)
30601 /* Return how many instructions the machine can issue per cycle. */
30604 rs6000_issue_rate (void)
30606 /* Unless scheduling for register pressure, use issue rate of 1 for
30607 first scheduling pass to decrease degradation. */
30608 if (!reload_completed
&& !flag_sched_pressure
)
30611 switch (rs6000_tune
) {
30612 case PROCESSOR_RS64A
:
30613 case PROCESSOR_PPC601
: /* ? */
30614 case PROCESSOR_PPC7450
:
30616 case PROCESSOR_PPC440
:
30617 case PROCESSOR_PPC603
:
30618 case PROCESSOR_PPC750
:
30619 case PROCESSOR_PPC7400
:
30620 case PROCESSOR_PPC8540
:
30621 case PROCESSOR_PPC8548
:
30622 case PROCESSOR_CELL
:
30623 case PROCESSOR_PPCE300C2
:
30624 case PROCESSOR_PPCE300C3
:
30625 case PROCESSOR_PPCE500MC
:
30626 case PROCESSOR_PPCE500MC64
:
30627 case PROCESSOR_PPCE5500
:
30628 case PROCESSOR_PPCE6500
:
30629 case PROCESSOR_TITAN
:
30631 case PROCESSOR_PPC476
:
30632 case PROCESSOR_PPC604
:
30633 case PROCESSOR_PPC604e
:
30634 case PROCESSOR_PPC620
:
30635 case PROCESSOR_PPC630
:
30637 case PROCESSOR_POWER4
:
30638 case PROCESSOR_POWER5
:
30639 case PROCESSOR_POWER6
:
30640 case PROCESSOR_POWER7
:
30642 case PROCESSOR_POWER8
:
30644 case PROCESSOR_POWER9
:
30651 /* Return how many instructions to look ahead for better insn
30655 rs6000_use_sched_lookahead (void)
30657 switch (rs6000_tune
)
30659 case PROCESSOR_PPC8540
:
30660 case PROCESSOR_PPC8548
:
30663 case PROCESSOR_CELL
:
30664 return (reload_completed
? 8 : 0);
30671 /* We are choosing insn from the ready queue. Return zero if INSN can be
30674 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
30676 if (ready_index
== 0)
30679 if (rs6000_tune
!= PROCESSOR_CELL
)
30682 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
30684 if (!reload_completed
30685 || is_nonpipeline_insn (insn
)
30686 || is_microcoded_insn (insn
))
30692 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30693 and return true. */
30696 find_mem_ref (rtx pat
, rtx
*mem_ref
)
30701 /* stack_tie does not produce any real memory traffic. */
30702 if (tie_operand (pat
, VOIDmode
))
30705 if (GET_CODE (pat
) == MEM
)
30711 /* Recursively process the pattern. */
30712 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
30714 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
30718 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
30721 else if (fmt
[i
] == 'E')
30722 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
30724 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
30732 /* Determine if PAT is a PATTERN of a load insn. */
30735 is_load_insn1 (rtx pat
, rtx
*load_mem
)
30737 if (!pat
|| pat
== NULL_RTX
)
30740 if (GET_CODE (pat
) == SET
)
30741 return find_mem_ref (SET_SRC (pat
), load_mem
);
30743 if (GET_CODE (pat
) == PARALLEL
)
30747 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
30748 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
30755 /* Determine if INSN loads from memory. */
30758 is_load_insn (rtx insn
, rtx
*load_mem
)
30760 if (!insn
|| !INSN_P (insn
))
30766 return is_load_insn1 (PATTERN (insn
), load_mem
);
30769 /* Determine if PAT is a PATTERN of a store insn. */
30772 is_store_insn1 (rtx pat
, rtx
*str_mem
)
30774 if (!pat
|| pat
== NULL_RTX
)
30777 if (GET_CODE (pat
) == SET
)
30778 return find_mem_ref (SET_DEST (pat
), str_mem
);
30780 if (GET_CODE (pat
) == PARALLEL
)
30784 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
30785 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
30792 /* Determine if INSN stores to memory. */
30795 is_store_insn (rtx insn
, rtx
*str_mem
)
30797 if (!insn
|| !INSN_P (insn
))
30800 return is_store_insn1 (PATTERN (insn
), str_mem
);
30803 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30806 is_power9_pairable_vec_type (enum attr_type type
)
30810 case TYPE_VECSIMPLE
:
30811 case TYPE_VECCOMPLEX
:
30815 case TYPE_VECFLOAT
:
30817 case TYPE_VECDOUBLE
:
30825 /* Returns whether the dependence between INSN and NEXT is considered
30826 costly by the given target. */
30829 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
30833 rtx load_mem
, str_mem
;
30835 /* If the flag is not enabled - no dependence is considered costly;
30836 allow all dependent insns in the same group.
30837 This is the most aggressive option. */
30838 if (rs6000_sched_costly_dep
== no_dep_costly
)
30841 /* If the flag is set to 1 - a dependence is always considered costly;
30842 do not allow dependent instructions in the same group.
30843 This is the most conservative option. */
30844 if (rs6000_sched_costly_dep
== all_deps_costly
)
30847 insn
= DEP_PRO (dep
);
30848 next
= DEP_CON (dep
);
30850 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
30851 && is_load_insn (next
, &load_mem
)
30852 && is_store_insn (insn
, &str_mem
))
30853 /* Prevent load after store in the same group. */
30856 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
30857 && is_load_insn (next
, &load_mem
)
30858 && is_store_insn (insn
, &str_mem
)
30859 && DEP_TYPE (dep
) == REG_DEP_TRUE
30860 && mem_locations_overlap(str_mem
, load_mem
))
30861 /* Prevent load after store in the same group if it is a true
30865 /* The flag is set to X; dependences with latency >= X are considered costly,
30866 and will not be scheduled in the same group. */
30867 if (rs6000_sched_costly_dep
<= max_dep_latency
30868 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
30874 /* Return the next insn after INSN that is found before TAIL is reached,
30875 skipping any "non-active" insns - insns that will not actually occupy
30876 an issue slot. Return NULL_RTX if such an insn is not found. */
30879 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
30881 if (insn
== NULL_RTX
|| insn
== tail
)
30886 insn
= NEXT_INSN (insn
);
30887 if (insn
== NULL_RTX
|| insn
== tail
)
30891 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
30892 || (NONJUMP_INSN_P (insn
)
30893 && GET_CODE (PATTERN (insn
)) != USE
30894 && GET_CODE (PATTERN (insn
)) != CLOBBER
30895 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
30901 /* Do Power9 specific sched_reorder2 reordering of ready list. */
30904 power9_sched_reorder2 (rtx_insn
**ready
, int lastpos
)
30909 enum attr_type type
, type2
;
30911 type
= get_attr_type (last_scheduled_insn
);
30913 /* Try to issue fixed point divides back-to-back in pairs so they will be
30914 routed to separate execution units and execute in parallel. */
30915 if (type
== TYPE_DIV
&& divide_cnt
== 0)
30917 /* First divide has been scheduled. */
30920 /* Scan the ready list looking for another divide, if found move it
30921 to the end of the list so it is chosen next. */
30925 if (recog_memoized (ready
[pos
]) >= 0
30926 && get_attr_type (ready
[pos
]) == TYPE_DIV
)
30929 for (i
= pos
; i
< lastpos
; i
++)
30930 ready
[i
] = ready
[i
+ 1];
30931 ready
[lastpos
] = tmp
;
30939 /* Last insn was the 2nd divide or not a divide, reset the counter. */
30942 /* The best dispatch throughput for vector and vector load insns can be
30943 achieved by interleaving a vector and vector load such that they'll
30944 dispatch to the same superslice. If this pairing cannot be achieved
30945 then it is best to pair vector insns together and vector load insns
30948 To aid in this pairing, vec_pairing maintains the current state with
30949 the following values:
30951 0 : Initial state, no vecload/vector pairing has been started.
30953 1 : A vecload or vector insn has been issued and a candidate for
30954 pairing has been found and moved to the end of the ready
30956 if (type
== TYPE_VECLOAD
)
30958 /* Issued a vecload. */
30959 if (vec_pairing
== 0)
30961 int vecload_pos
= -1;
30962 /* We issued a single vecload, look for a vector insn to pair it
30963 with. If one isn't found, try to pair another vecload. */
30967 if (recog_memoized (ready
[pos
]) >= 0)
30969 type2
= get_attr_type (ready
[pos
]);
30970 if (is_power9_pairable_vec_type (type2
))
30972 /* Found a vector insn to pair with, move it to the
30973 end of the ready list so it is scheduled next. */
30975 for (i
= pos
; i
< lastpos
; i
++)
30976 ready
[i
] = ready
[i
+ 1];
30977 ready
[lastpos
] = tmp
;
30979 return cached_can_issue_more
;
30981 else if (type2
== TYPE_VECLOAD
&& vecload_pos
== -1)
30982 /* Remember position of first vecload seen. */
30987 if (vecload_pos
>= 0)
30989 /* Didn't find a vector to pair with but did find a vecload,
30990 move it to the end of the ready list. */
30991 tmp
= ready
[vecload_pos
];
30992 for (i
= vecload_pos
; i
< lastpos
; i
++)
30993 ready
[i
] = ready
[i
+ 1];
30994 ready
[lastpos
] = tmp
;
30996 return cached_can_issue_more
;
31000 else if (is_power9_pairable_vec_type (type
))
31002 /* Issued a vector operation. */
31003 if (vec_pairing
== 0)
31006 /* We issued a single vector insn, look for a vecload to pair it
31007 with. If one isn't found, try to pair another vector. */
31011 if (recog_memoized (ready
[pos
]) >= 0)
31013 type2
= get_attr_type (ready
[pos
]);
31014 if (type2
== TYPE_VECLOAD
)
31016 /* Found a vecload insn to pair with, move it to the
31017 end of the ready list so it is scheduled next. */
31019 for (i
= pos
; i
< lastpos
; i
++)
31020 ready
[i
] = ready
[i
+ 1];
31021 ready
[lastpos
] = tmp
;
31023 return cached_can_issue_more
;
31025 else if (is_power9_pairable_vec_type (type2
)
31027 /* Remember position of first vector insn seen. */
31034 /* Didn't find a vecload to pair with but did find a vector
31035 insn, move it to the end of the ready list. */
31036 tmp
= ready
[vec_pos
];
31037 for (i
= vec_pos
; i
< lastpos
; i
++)
31038 ready
[i
] = ready
[i
+ 1];
31039 ready
[lastpos
] = tmp
;
31041 return cached_can_issue_more
;
31046 /* We've either finished a vec/vecload pair, couldn't find an insn to
31047 continue the current pair, or the last insn had nothing to do with
31048 with pairing. In any case, reset the state. */
31052 return cached_can_issue_more
;
31055 /* We are about to begin issuing insns for this clock cycle. */
31058 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
31059 rtx_insn
**ready ATTRIBUTE_UNUSED
,
31060 int *pn_ready ATTRIBUTE_UNUSED
,
31061 int clock_var ATTRIBUTE_UNUSED
)
31063 int n_ready
= *pn_ready
;
31066 fprintf (dump
, "// rs6000_sched_reorder :\n");
31068 /* Reorder the ready list, if the second to last ready insn
31069 is a nonepipeline insn. */
31070 if (rs6000_tune
== PROCESSOR_CELL
&& n_ready
> 1)
31072 if (is_nonpipeline_insn (ready
[n_ready
- 1])
31073 && (recog_memoized (ready
[n_ready
- 2]) > 0))
31074 /* Simply swap first two insns. */
31075 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
31078 if (rs6000_tune
== PROCESSOR_POWER6
)
31079 load_store_pendulum
= 0;
31081 return rs6000_issue_rate ();
31084 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31087 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
31088 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
31091 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
31093 /* For Power6, we need to handle some special cases to try and keep the
31094 store queue from overflowing and triggering expensive flushes.
31096 This code monitors how load and store instructions are being issued
31097 and skews the ready list one way or the other to increase the likelihood
31098 that a desired instruction is issued at the proper time.
31100 A couple of things are done. First, we maintain a "load_store_pendulum"
31101 to track the current state of load/store issue.
31103 - If the pendulum is at zero, then no loads or stores have been
31104 issued in the current cycle so we do nothing.
31106 - If the pendulum is 1, then a single load has been issued in this
31107 cycle and we attempt to locate another load in the ready list to
31110 - If the pendulum is -2, then two stores have already been
31111 issued in this cycle, so we increase the priority of the first load
31112 in the ready list to increase it's likelihood of being chosen first
31115 - If the pendulum is -1, then a single store has been issued in this
31116 cycle and we attempt to locate another store in the ready list to
31117 issue with it, preferring a store to an adjacent memory location to
31118 facilitate store pairing in the store queue.
31120 - If the pendulum is 2, then two loads have already been
31121 issued in this cycle, so we increase the priority of the first store
31122 in the ready list to increase it's likelihood of being chosen first
31125 - If the pendulum < -2 or > 2, then do nothing.
31127 Note: This code covers the most common scenarios. There exist non
31128 load/store instructions which make use of the LSU and which
31129 would need to be accounted for to strictly model the behavior
31130 of the machine. Those instructions are currently unaccounted
31131 for to help minimize compile time overhead of this code.
31133 if (rs6000_tune
== PROCESSOR_POWER6
&& last_scheduled_insn
)
31138 rtx load_mem
, str_mem
;
31140 if (is_store_insn (last_scheduled_insn
, &str_mem
))
31141 /* Issuing a store, swing the load_store_pendulum to the left */
31142 load_store_pendulum
--;
31143 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
31144 /* Issuing a load, swing the load_store_pendulum to the right */
31145 load_store_pendulum
++;
31147 return cached_can_issue_more
;
31149 /* If the pendulum is balanced, or there is only one instruction on
31150 the ready list, then all is well, so return. */
31151 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
31152 return cached_can_issue_more
;
31154 if (load_store_pendulum
== 1)
31156 /* A load has been issued in this cycle. Scan the ready list
31157 for another load to issue with it */
31162 if (is_load_insn (ready
[pos
], &load_mem
))
31164 /* Found a load. Move it to the head of the ready list,
31165 and adjust it's priority so that it is more likely to
31168 for (i
=pos
; i
<*pn_ready
-1; i
++)
31169 ready
[i
] = ready
[i
+ 1];
31170 ready
[*pn_ready
-1] = tmp
;
31172 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31173 INSN_PRIORITY (tmp
)++;
31179 else if (load_store_pendulum
== -2)
31181 /* Two stores have been issued in this cycle. Increase the
31182 priority of the first load in the ready list to favor it for
31183 issuing in the next cycle. */
31188 if (is_load_insn (ready
[pos
], &load_mem
)
31190 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31192 INSN_PRIORITY (ready
[pos
])++;
31194 /* Adjust the pendulum to account for the fact that a load
31195 was found and increased in priority. This is to prevent
31196 increasing the priority of multiple loads */
31197 load_store_pendulum
--;
31204 else if (load_store_pendulum
== -1)
31206 /* A store has been issued in this cycle. Scan the ready list for
31207 another store to issue with it, preferring a store to an adjacent
31209 int first_store_pos
= -1;
31215 if (is_store_insn (ready
[pos
], &str_mem
))
31218 /* Maintain the index of the first store found on the
31220 if (first_store_pos
== -1)
31221 first_store_pos
= pos
;
31223 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
31224 && adjacent_mem_locations (str_mem
, str_mem2
))
31226 /* Found an adjacent store. Move it to the head of the
31227 ready list, and adjust it's priority so that it is
31228 more likely to stay there */
31230 for (i
=pos
; i
<*pn_ready
-1; i
++)
31231 ready
[i
] = ready
[i
+ 1];
31232 ready
[*pn_ready
-1] = tmp
;
31234 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31235 INSN_PRIORITY (tmp
)++;
31237 first_store_pos
= -1;
31245 if (first_store_pos
>= 0)
31247 /* An adjacent store wasn't found, but a non-adjacent store was,
31248 so move the non-adjacent store to the front of the ready
31249 list, and adjust its priority so that it is more likely to
31251 tmp
= ready
[first_store_pos
];
31252 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
31253 ready
[i
] = ready
[i
+ 1];
31254 ready
[*pn_ready
-1] = tmp
;
31255 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31256 INSN_PRIORITY (tmp
)++;
31259 else if (load_store_pendulum
== 2)
31261 /* Two loads have been issued in this cycle. Increase the priority
31262 of the first store in the ready list to favor it for issuing in
31268 if (is_store_insn (ready
[pos
], &str_mem
)
31270 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31272 INSN_PRIORITY (ready
[pos
])++;
31274 /* Adjust the pendulum to account for the fact that a store
31275 was found and increased in priority. This is to prevent
31276 increasing the priority of multiple stores */
31277 load_store_pendulum
++;
31286 /* Do Power9 dependent reordering if necessary. */
31287 if (rs6000_tune
== PROCESSOR_POWER9
&& last_scheduled_insn
31288 && recog_memoized (last_scheduled_insn
) >= 0)
31289 return power9_sched_reorder2 (ready
, *pn_ready
- 1);
31291 return cached_can_issue_more
;
31294 /* Return whether the presence of INSN causes a dispatch group termination
31295 of group WHICH_GROUP.
31297 If WHICH_GROUP == current_group, this function will return true if INSN
31298 causes the termination of the current group (i.e, the dispatch group to
31299 which INSN belongs). This means that INSN will be the last insn in the
31300 group it belongs to.
31302 If WHICH_GROUP == previous_group, this function will return true if INSN
31303 causes the termination of the previous group (i.e, the dispatch group that
31304 precedes the group to which INSN belongs). This means that INSN will be
31305 the first insn in the group it belongs to). */
31308 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
31315 first
= insn_must_be_first_in_group (insn
);
31316 last
= insn_must_be_last_in_group (insn
);
31321 if (which_group
== current_group
)
31323 else if (which_group
== previous_group
)
31331 insn_must_be_first_in_group (rtx_insn
*insn
)
31333 enum attr_type type
;
31337 || DEBUG_INSN_P (insn
)
31338 || GET_CODE (PATTERN (insn
)) == USE
31339 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31342 switch (rs6000_tune
)
31344 case PROCESSOR_POWER5
:
31345 if (is_cracked_insn (insn
))
31348 case PROCESSOR_POWER4
:
31349 if (is_microcoded_insn (insn
))
31352 if (!rs6000_sched_groups
)
31355 type
= get_attr_type (insn
);
31362 case TYPE_CR_LOGICAL
:
31375 case PROCESSOR_POWER6
:
31376 type
= get_attr_type (insn
);
31385 case TYPE_FPCOMPARE
:
31396 if (get_attr_dot (insn
) == DOT_NO
31397 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31402 if (get_attr_size (insn
) == SIZE_32
)
31410 if (get_attr_update (insn
) == UPDATE_YES
)
31418 case PROCESSOR_POWER7
:
31419 type
= get_attr_type (insn
);
31423 case TYPE_CR_LOGICAL
:
31437 if (get_attr_dot (insn
) == DOT_YES
)
31442 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31443 || get_attr_update (insn
) == UPDATE_YES
)
31450 if (get_attr_update (insn
) == UPDATE_YES
)
31458 case PROCESSOR_POWER8
:
31459 type
= get_attr_type (insn
);
31463 case TYPE_CR_LOGICAL
:
31471 case TYPE_VECSTORE
:
31478 if (get_attr_dot (insn
) == DOT_YES
)
31483 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31484 || get_attr_update (insn
) == UPDATE_YES
)
31489 if (get_attr_update (insn
) == UPDATE_YES
31490 && get_attr_indexed (insn
) == INDEXED_YES
)
31506 insn_must_be_last_in_group (rtx_insn
*insn
)
31508 enum attr_type type
;
31512 || DEBUG_INSN_P (insn
)
31513 || GET_CODE (PATTERN (insn
)) == USE
31514 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31517 switch (rs6000_tune
) {
31518 case PROCESSOR_POWER4
:
31519 case PROCESSOR_POWER5
:
31520 if (is_microcoded_insn (insn
))
31523 if (is_branch_slot_insn (insn
))
31527 case PROCESSOR_POWER6
:
31528 type
= get_attr_type (insn
);
31536 case TYPE_FPCOMPARE
:
31547 if (get_attr_dot (insn
) == DOT_NO
31548 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31553 if (get_attr_size (insn
) == SIZE_32
)
31561 case PROCESSOR_POWER7
:
31562 type
= get_attr_type (insn
);
31572 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31573 && get_attr_update (insn
) == UPDATE_YES
)
31578 if (get_attr_update (insn
) == UPDATE_YES
31579 && get_attr_indexed (insn
) == INDEXED_YES
)
31587 case PROCESSOR_POWER8
:
31588 type
= get_attr_type (insn
);
31600 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31601 && get_attr_update (insn
) == UPDATE_YES
)
31606 if (get_attr_update (insn
) == UPDATE_YES
31607 && get_attr_indexed (insn
) == INDEXED_YES
)
31622 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31623 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31626 is_costly_group (rtx
*group_insns
, rtx next_insn
)
31629 int issue_rate
= rs6000_issue_rate ();
31631 for (i
= 0; i
< issue_rate
; i
++)
31633 sd_iterator_def sd_it
;
31635 rtx insn
= group_insns
[i
];
31640 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
31642 rtx next
= DEP_CON (dep
);
31644 if (next
== next_insn
31645 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
31653 /* Utility of the function redefine_groups.
31654 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31655 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31656 to keep it "far" (in a separate group) from GROUP_INSNS, following
31657 one of the following schemes, depending on the value of the flag
31658 -minsert_sched_nops = X:
31659 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31660 in order to force NEXT_INSN into a separate group.
31661 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31662 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31663 insertion (has a group just ended, how many vacant issue slots remain in the
31664 last group, and how many dispatch groups were encountered so far). */
31667 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
31668 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
31673 int issue_rate
= rs6000_issue_rate ();
31674 bool end
= *group_end
;
31677 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
31678 return can_issue_more
;
31680 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
31681 return can_issue_more
;
31683 force
= is_costly_group (group_insns
, next_insn
);
31685 return can_issue_more
;
31687 if (sched_verbose
> 6)
31688 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
31689 *group_count
,can_issue_more
);
31691 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
31694 can_issue_more
= 0;
31696 /* Since only a branch can be issued in the last issue_slot, it is
31697 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31698 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31699 in this case the last nop will start a new group and the branch
31700 will be forced to the new group. */
31701 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
31704 /* Do we have a special group ending nop? */
31705 if (rs6000_tune
== PROCESSOR_POWER6
|| rs6000_tune
== PROCESSOR_POWER7
31706 || rs6000_tune
== PROCESSOR_POWER8
)
31708 nop
= gen_group_ending_nop ();
31709 emit_insn_before (nop
, next_insn
);
31710 can_issue_more
= 0;
31713 while (can_issue_more
> 0)
31716 emit_insn_before (nop
, next_insn
);
31724 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
31726 int n_nops
= rs6000_sched_insert_nops
;
31728 /* Nops can't be issued from the branch slot, so the effective
31729 issue_rate for nops is 'issue_rate - 1'. */
31730 if (can_issue_more
== 0)
31731 can_issue_more
= issue_rate
;
31733 if (can_issue_more
== 0)
31735 can_issue_more
= issue_rate
- 1;
31738 for (i
= 0; i
< issue_rate
; i
++)
31740 group_insns
[i
] = 0;
31747 emit_insn_before (nop
, next_insn
);
31748 if (can_issue_more
== issue_rate
- 1) /* new group begins */
31751 if (can_issue_more
== 0)
31753 can_issue_more
= issue_rate
- 1;
31756 for (i
= 0; i
< issue_rate
; i
++)
31758 group_insns
[i
] = 0;
31764 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31767 /* Is next_insn going to start a new group? */
31770 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
31771 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
31772 || (can_issue_more
< issue_rate
&&
31773 insn_terminates_group_p (next_insn
, previous_group
)));
31774 if (*group_end
&& end
)
31777 if (sched_verbose
> 6)
31778 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
31779 *group_count
, can_issue_more
);
31780 return can_issue_more
;
31783 return can_issue_more
;
31786 /* This function tries to synch the dispatch groups that the compiler "sees"
31787 with the dispatch groups that the processor dispatcher is expected to
31788 form in practice. It tries to achieve this synchronization by forcing the
31789 estimated processor grouping on the compiler (as opposed to the function
31790 'pad_goups' which tries to force the scheduler's grouping on the processor).
31792 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31793 examines the (estimated) dispatch groups that will be formed by the processor
31794 dispatcher. It marks these group boundaries to reflect the estimated
31795 processor grouping, overriding the grouping that the scheduler had marked.
31796 Depending on the value of the flag '-minsert-sched-nops' this function can
31797 force certain insns into separate groups or force a certain distance between
31798 them by inserting nops, for example, if there exists a "costly dependence"
31801 The function estimates the group boundaries that the processor will form as
31802 follows: It keeps track of how many vacant issue slots are available after
31803 each insn. A subsequent insn will start a new group if one of the following
31805 - no more vacant issue slots remain in the current dispatch group.
31806 - only the last issue slot, which is the branch slot, is vacant, but the next
31807 insn is not a branch.
31808 - only the last 2 or less issue slots, including the branch slot, are vacant,
31809 which means that a cracked insn (which occupies two issue slots) can't be
31810 issued in this group.
31811 - less than 'issue_rate' slots are vacant, and the next insn always needs to
31812 start a new group. */
31815 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
31818 rtx_insn
*insn
, *next_insn
;
31820 int can_issue_more
;
31823 int group_count
= 0;
31827 issue_rate
= rs6000_issue_rate ();
31828 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
31829 for (i
= 0; i
< issue_rate
; i
++)
31831 group_insns
[i
] = 0;
31833 can_issue_more
= issue_rate
;
31835 insn
= get_next_active_insn (prev_head_insn
, tail
);
31838 while (insn
!= NULL_RTX
)
31840 slot
= (issue_rate
- can_issue_more
);
31841 group_insns
[slot
] = insn
;
31843 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
31844 if (insn_terminates_group_p (insn
, current_group
))
31845 can_issue_more
= 0;
31847 next_insn
= get_next_active_insn (insn
, tail
);
31848 if (next_insn
== NULL_RTX
)
31849 return group_count
+ 1;
31851 /* Is next_insn going to start a new group? */
31853 = (can_issue_more
== 0
31854 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
31855 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
31856 || (can_issue_more
< issue_rate
&&
31857 insn_terminates_group_p (next_insn
, previous_group
)));
31859 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
31860 next_insn
, &group_end
, can_issue_more
,
31866 can_issue_more
= 0;
31867 for (i
= 0; i
< issue_rate
; i
++)
31869 group_insns
[i
] = 0;
31873 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
31874 PUT_MODE (next_insn
, VOIDmode
);
31875 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
31876 PUT_MODE (next_insn
, TImode
);
31879 if (can_issue_more
== 0)
31880 can_issue_more
= issue_rate
;
31883 return group_count
;
31886 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
31887 dispatch group boundaries that the scheduler had marked. Pad with nops
31888 any dispatch groups which have vacant issue slots, in order to force the
31889 scheduler's grouping on the processor dispatcher. The function
31890 returns the number of dispatch groups found. */
31893 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
31896 rtx_insn
*insn
, *next_insn
;
31899 int can_issue_more
;
31901 int group_count
= 0;
31903 /* Initialize issue_rate. */
31904 issue_rate
= rs6000_issue_rate ();
31905 can_issue_more
= issue_rate
;
31907 insn
= get_next_active_insn (prev_head_insn
, tail
);
31908 next_insn
= get_next_active_insn (insn
, tail
);
31910 while (insn
!= NULL_RTX
)
31913 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
31915 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
31917 if (next_insn
== NULL_RTX
)
31922 /* If the scheduler had marked group termination at this location
31923 (between insn and next_insn), and neither insn nor next_insn will
31924 force group termination, pad the group with nops to force group
31927 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
31928 && !insn_terminates_group_p (insn
, current_group
)
31929 && !insn_terminates_group_p (next_insn
, previous_group
))
31931 if (!is_branch_slot_insn (next_insn
))
31934 while (can_issue_more
)
31937 emit_insn_before (nop
, next_insn
);
31942 can_issue_more
= issue_rate
;
31947 next_insn
= get_next_active_insn (insn
, tail
);
31950 return group_count
;
31953 /* We're beginning a new block. Initialize data structures as necessary. */
31956 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
31957 int sched_verbose ATTRIBUTE_UNUSED
,
31958 int max_ready ATTRIBUTE_UNUSED
)
31960 last_scheduled_insn
= NULL
;
31961 load_store_pendulum
= 0;
31966 /* The following function is called at the end of scheduling BB.
31967 After reload, it inserts nops at insn group bundling. */
31970 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
31975 fprintf (dump
, "=== Finishing schedule.\n");
31977 if (reload_completed
&& rs6000_sched_groups
)
31979 /* Do not run sched_finish hook when selective scheduling enabled. */
31980 if (sel_sched_p ())
31983 if (rs6000_sched_insert_nops
== sched_finish_none
)
31986 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
31987 n_groups
= pad_groups (dump
, sched_verbose
,
31988 current_sched_info
->prev_head
,
31989 current_sched_info
->next_tail
);
31991 n_groups
= redefine_groups (dump
, sched_verbose
,
31992 current_sched_info
->prev_head
,
31993 current_sched_info
->next_tail
);
31995 if (sched_verbose
>= 6)
31997 fprintf (dump
, "ngroups = %d\n", n_groups
);
31998 print_rtl (dump
, current_sched_info
->prev_head
);
31999 fprintf (dump
, "Done finish_sched\n");
32004 struct rs6000_sched_context
32006 short cached_can_issue_more
;
32007 rtx_insn
*last_scheduled_insn
;
32008 int load_store_pendulum
;
32013 typedef struct rs6000_sched_context rs6000_sched_context_def
;
32014 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
32016 /* Allocate store for new scheduling context. */
32018 rs6000_alloc_sched_context (void)
32020 return xmalloc (sizeof (rs6000_sched_context_def
));
32023 /* If CLEAN_P is true then initializes _SC with clean data,
32024 and from the global context otherwise. */
32026 rs6000_init_sched_context (void *_sc
, bool clean_p
)
32028 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32032 sc
->cached_can_issue_more
= 0;
32033 sc
->last_scheduled_insn
= NULL
;
32034 sc
->load_store_pendulum
= 0;
32035 sc
->divide_cnt
= 0;
32036 sc
->vec_pairing
= 0;
32040 sc
->cached_can_issue_more
= cached_can_issue_more
;
32041 sc
->last_scheduled_insn
= last_scheduled_insn
;
32042 sc
->load_store_pendulum
= load_store_pendulum
;
32043 sc
->divide_cnt
= divide_cnt
;
32044 sc
->vec_pairing
= vec_pairing
;
32048 /* Sets the global scheduling context to the one pointed to by _SC. */
32050 rs6000_set_sched_context (void *_sc
)
32052 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32054 gcc_assert (sc
!= NULL
);
32056 cached_can_issue_more
= sc
->cached_can_issue_more
;
32057 last_scheduled_insn
= sc
->last_scheduled_insn
;
32058 load_store_pendulum
= sc
->load_store_pendulum
;
32059 divide_cnt
= sc
->divide_cnt
;
32060 vec_pairing
= sc
->vec_pairing
;
32065 rs6000_free_sched_context (void *_sc
)
32067 gcc_assert (_sc
!= NULL
);
32073 rs6000_sched_can_speculate_insn (rtx_insn
*insn
)
32075 switch (get_attr_type (insn
))
32090 /* Length in units of the trampoline for entering a nested function. */
32093 rs6000_trampoline_size (void)
32097 switch (DEFAULT_ABI
)
32100 gcc_unreachable ();
32103 ret
= (TARGET_32BIT
) ? 12 : 24;
32107 gcc_assert (!TARGET_32BIT
);
32113 ret
= (TARGET_32BIT
) ? 40 : 48;
32120 /* Emit RTL insns to initialize the variable parts of a trampoline.
32121 FNADDR is an RTX for the address of the function's pure code.
32122 CXT is an RTX for the static chain value for the function. */
32125 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
32127 int regsize
= (TARGET_32BIT
) ? 4 : 8;
32128 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
32129 rtx ctx_reg
= force_reg (Pmode
, cxt
);
32130 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
32132 switch (DEFAULT_ABI
)
32135 gcc_unreachable ();
32137 /* Under AIX, just build the 3 word function descriptor */
32140 rtx fnmem
, fn_reg
, toc_reg
;
32142 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32143 error ("you cannot take the address of a nested function if you use "
32144 "the %qs option", "-mno-pointers-to-nested-functions");
32146 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
32147 fn_reg
= gen_reg_rtx (Pmode
);
32148 toc_reg
= gen_reg_rtx (Pmode
);
32150 /* Macro to shorten the code expansions below. */
32151 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32153 m_tramp
= replace_equiv_address (m_tramp
, addr
);
32155 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
32156 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
32157 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
32158 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
32159 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
32165 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32169 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
32170 LCT_NORMAL
, VOIDmode
,
32172 GEN_INT (rs6000_trampoline_size ()), SImode
,
32180 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32181 identifier as an argument, so the front end shouldn't look it up. */
32184 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
32186 return is_attribute_p ("altivec", attr_id
);
32189 /* Handle the "altivec" attribute. The attribute may have
32190 arguments as follows:
32192 __attribute__((altivec(vector__)))
32193 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32194 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32196 and may appear more than once (e.g., 'vector bool char') in a
32197 given declaration. */
32200 rs6000_handle_altivec_attribute (tree
*node
,
32201 tree name ATTRIBUTE_UNUSED
,
32203 int flags ATTRIBUTE_UNUSED
,
32204 bool *no_add_attrs
)
32206 tree type
= *node
, result
= NULL_TREE
;
32210 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
32211 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
32212 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
32215 while (POINTER_TYPE_P (type
)
32216 || TREE_CODE (type
) == FUNCTION_TYPE
32217 || TREE_CODE (type
) == METHOD_TYPE
32218 || TREE_CODE (type
) == ARRAY_TYPE
)
32219 type
= TREE_TYPE (type
);
32221 mode
= TYPE_MODE (type
);
32223 /* Check for invalid AltiVec type qualifiers. */
32224 if (type
== long_double_type_node
)
32225 error ("use of %<long double%> in AltiVec types is invalid");
32226 else if (type
== boolean_type_node
)
32227 error ("use of boolean types in AltiVec types is invalid");
32228 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
32229 error ("use of %<complex%> in AltiVec types is invalid");
32230 else if (DECIMAL_FLOAT_MODE_P (mode
))
32231 error ("use of decimal floating point types in AltiVec types is invalid");
32232 else if (!TARGET_VSX
)
32234 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
32237 error ("use of %<long%> in AltiVec types is invalid for "
32238 "64-bit code without %qs", "-mvsx");
32239 else if (rs6000_warn_altivec_long
)
32240 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32243 else if (type
== long_long_unsigned_type_node
32244 || type
== long_long_integer_type_node
)
32245 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32247 else if (type
== double_type_node
)
32248 error ("use of %<double%> in AltiVec types is invalid without %qs",
32252 switch (altivec_type
)
32255 unsigned_p
= TYPE_UNSIGNED (type
);
32259 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
32262 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
32265 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
32268 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
32271 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
32273 case E_SFmode
: result
= V4SF_type_node
; break;
32274 case E_DFmode
: result
= V2DF_type_node
; break;
32275 /* If the user says 'vector int bool', we may be handed the 'bool'
32276 attribute _before_ the 'vector' attribute, and so select the
32277 proper type in the 'b' case below. */
32278 case E_V4SImode
: case E_V8HImode
: case E_V16QImode
: case E_V4SFmode
:
32279 case E_V2DImode
: case E_V2DFmode
:
32287 case E_DImode
: case E_V2DImode
: result
= bool_V2DI_type_node
; break;
32288 case E_SImode
: case E_V4SImode
: result
= bool_V4SI_type_node
; break;
32289 case E_HImode
: case E_V8HImode
: result
= bool_V8HI_type_node
; break;
32290 case E_QImode
: case E_V16QImode
: result
= bool_V16QI_type_node
;
32297 case E_V8HImode
: result
= pixel_V8HI_type_node
;
32303 /* Propagate qualifiers attached to the element type
32304 onto the vector type. */
32305 if (result
&& result
!= type
&& TYPE_QUALS (type
))
32306 result
= build_qualified_type (result
, TYPE_QUALS (type
));
32308 *no_add_attrs
= true; /* No need to hang on to the attribute. */
32311 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
32316 /* AltiVec defines five built-in scalar types that serve as vector
32317 elements; we must teach the compiler how to mangle them. The 128-bit
32318 floating point mangling is target-specific as well. */
32320 static const char *
32321 rs6000_mangle_type (const_tree type
)
32323 type
= TYPE_MAIN_VARIANT (type
);
32325 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
32326 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
32329 if (type
== bool_char_type_node
) return "U6__boolc";
32330 if (type
== bool_short_type_node
) return "U6__bools";
32331 if (type
== pixel_type_node
) return "u7__pixel";
32332 if (type
== bool_int_type_node
) return "U6__booli";
32333 if (type
== bool_long_long_type_node
) return "U6__boolx";
32335 if (SCALAR_FLOAT_TYPE_P (type
) && FLOAT128_IBM_P (TYPE_MODE (type
)))
32337 if (SCALAR_FLOAT_TYPE_P (type
) && FLOAT128_IEEE_P (TYPE_MODE (type
)))
32338 return ieee128_mangling_gcc_8_1
? "U10__float128" : "u9__ieee128";
32340 /* For all other types, use the default mangling. */
32344 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32345 struct attribute_spec.handler. */
32348 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
32349 tree args ATTRIBUTE_UNUSED
,
32350 int flags ATTRIBUTE_UNUSED
,
32351 bool *no_add_attrs
)
32353 if (TREE_CODE (*node
) != FUNCTION_TYPE
32354 && TREE_CODE (*node
) != FIELD_DECL
32355 && TREE_CODE (*node
) != TYPE_DECL
)
32357 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
32359 *no_add_attrs
= true;
32365 /* Set longcall attributes on all functions declared when
32366 rs6000_default_long_calls is true. */
32368 rs6000_set_default_type_attributes (tree type
)
32370 if (rs6000_default_long_calls
32371 && (TREE_CODE (type
) == FUNCTION_TYPE
32372 || TREE_CODE (type
) == METHOD_TYPE
))
32373 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
32375 TYPE_ATTRIBUTES (type
));
32378 darwin_set_default_type_attributes (type
);
32382 /* Return a reference suitable for calling a function with the
32383 longcall attribute. */
32386 rs6000_longcall_ref (rtx call_ref
)
32388 const char *call_name
;
32391 if (GET_CODE (call_ref
) != SYMBOL_REF
)
32394 /* System V adds '.' to the internal name, so skip them. */
32395 call_name
= XSTR (call_ref
, 0);
32396 if (*call_name
== '.')
32398 while (*call_name
== '.')
32401 node
= get_identifier (call_name
);
32402 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
32405 return force_reg (Pmode
, call_ref
);
32408 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32409 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32412 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32413 struct attribute_spec.handler. */
32415 rs6000_handle_struct_attribute (tree
*node
, tree name
,
32416 tree args ATTRIBUTE_UNUSED
,
32417 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
32420 if (DECL_P (*node
))
32422 if (TREE_CODE (*node
) == TYPE_DECL
)
32423 type
= &TREE_TYPE (*node
);
32428 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
32429 || TREE_CODE (*type
) == UNION_TYPE
)))
32431 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
32432 *no_add_attrs
= true;
32435 else if ((is_attribute_p ("ms_struct", name
)
32436 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
32437 || ((is_attribute_p ("gcc_struct", name
)
32438 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
32440 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
32442 *no_add_attrs
= true;
32449 rs6000_ms_bitfield_layout_p (const_tree record_type
)
32451 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
32452 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
32453 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
32456 #ifdef USING_ELFOS_H
32458 /* A get_unnamed_section callback, used for switching to toc_section. */
32461 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
32463 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
32464 && TARGET_MINIMAL_TOC
)
32466 if (!toc_initialized
)
32468 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
32469 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32470 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
32471 fprintf (asm_out_file
, "\t.tc ");
32472 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
32473 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32474 fprintf (asm_out_file
, "\n");
32476 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32477 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32478 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32479 fprintf (asm_out_file
, " = .+32768\n");
32480 toc_initialized
= 1;
32483 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32485 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
32487 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
32488 if (!toc_initialized
)
32490 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32491 toc_initialized
= 1;
32496 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
32497 if (!toc_initialized
)
32499 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
32500 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
32501 fprintf (asm_out_file
, " = .+32768\n");
32502 toc_initialized
= 1;
32507 /* Implement TARGET_ASM_INIT_SECTIONS. */
32510 rs6000_elf_asm_init_sections (void)
32513 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
32516 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
32517 SDATA2_SECTION_ASM_OP
);
32520 /* Implement TARGET_SELECT_RTX_SECTION. */
32523 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
32524 unsigned HOST_WIDE_INT align
)
32526 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
32527 return toc_section
;
32529 return default_elf_select_rtx_section (mode
, x
, align
);
32532 /* For a SYMBOL_REF, set generic flags and then perform some
32533 target-specific processing.
32535 When the AIX ABI is requested on a non-AIX system, replace the
32536 function name with the real name (with a leading .) rather than the
32537 function descriptor name. This saves a lot of overriding code to
32538 read the prefixes. */
32540 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
32542 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
32544 default_encode_section_info (decl
, rtl
, first
);
32547 && TREE_CODE (decl
) == FUNCTION_DECL
32549 && DEFAULT_ABI
== ABI_AIX
)
32551 rtx sym_ref
= XEXP (rtl
, 0);
32552 size_t len
= strlen (XSTR (sym_ref
, 0));
32553 char *str
= XALLOCAVEC (char, len
+ 2);
32555 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
32556 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
32561 compare_section_name (const char *section
, const char *templ
)
32565 len
= strlen (templ
);
32566 return (strncmp (section
, templ
, len
) == 0
32567 && (section
[len
] == 0 || section
[len
] == '.'));
32571 rs6000_elf_in_small_data_p (const_tree decl
)
32573 if (rs6000_sdata
== SDATA_NONE
)
32576 /* We want to merge strings, so we never consider them small data. */
32577 if (TREE_CODE (decl
) == STRING_CST
)
32580 /* Functions are never in the small data area. */
32581 if (TREE_CODE (decl
) == FUNCTION_DECL
)
32584 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
32586 const char *section
= DECL_SECTION_NAME (decl
);
32587 if (compare_section_name (section
, ".sdata")
32588 || compare_section_name (section
, ".sdata2")
32589 || compare_section_name (section
, ".gnu.linkonce.s")
32590 || compare_section_name (section
, ".sbss")
32591 || compare_section_name (section
, ".sbss2")
32592 || compare_section_name (section
, ".gnu.linkonce.sb")
32593 || strcmp (section
, ".PPC.EMB.sdata0") == 0
32594 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
32599 /* If we are told not to put readonly data in sdata, then don't. */
32600 if (TREE_READONLY (decl
) && rs6000_sdata
!= SDATA_EABI
32601 && !rs6000_readonly_in_sdata
)
32604 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
32607 && size
<= g_switch_value
32608 /* If it's not public, and we're not going to reference it there,
32609 there's no need to put it in the small data section. */
32610 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
32617 #endif /* USING_ELFOS_H */
32619 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32622 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
32624 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
32627 /* Do not place thread-local symbols refs in the object blocks. */
32630 rs6000_use_blocks_for_decl_p (const_tree decl
)
32632 return !DECL_THREAD_LOCAL_P (decl
);
32635 /* Return a REG that occurs in ADDR with coefficient 1.
32636 ADDR can be effectively incremented by incrementing REG.
32638 r0 is special and we must not select it as an address
32639 register by this routine since our caller will try to
32640 increment the returned register via an "la" instruction. */
32643 find_addr_reg (rtx addr
)
32645 while (GET_CODE (addr
) == PLUS
)
32647 if (GET_CODE (XEXP (addr
, 0)) == REG
32648 && REGNO (XEXP (addr
, 0)) != 0)
32649 addr
= XEXP (addr
, 0);
32650 else if (GET_CODE (XEXP (addr
, 1)) == REG
32651 && REGNO (XEXP (addr
, 1)) != 0)
32652 addr
= XEXP (addr
, 1);
32653 else if (CONSTANT_P (XEXP (addr
, 0)))
32654 addr
= XEXP (addr
, 1);
32655 else if (CONSTANT_P (XEXP (addr
, 1)))
32656 addr
= XEXP (addr
, 0);
32658 gcc_unreachable ();
32660 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
32665 rs6000_fatal_bad_address (rtx op
)
32667 fatal_insn ("bad address", op
);
32672 typedef struct branch_island_d
{
32673 tree function_name
;
32679 static vec
<branch_island
, va_gc
> *branch_islands
;
32681 /* Remember to generate a branch island for far calls to the given
32685 add_compiler_branch_island (tree label_name
, tree function_name
,
32688 branch_island bi
= {function_name
, label_name
, line_number
};
32689 vec_safe_push (branch_islands
, bi
);
32692 /* Generate far-jump branch islands for everything recorded in
32693 branch_islands. Invoked immediately after the last instruction of
32694 the epilogue has been emitted; the branch islands must be appended
32695 to, and contiguous with, the function body. Mach-O stubs are
32696 generated in machopic_output_stub(). */
32699 macho_branch_islands (void)
32703 while (!vec_safe_is_empty (branch_islands
))
32705 branch_island
*bi
= &branch_islands
->last ();
32706 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
32707 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
32708 char name_buf
[512];
32709 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32710 if (name
[0] == '*' || name
[0] == '&')
32711 strcpy (name_buf
, name
+1);
32715 strcpy (name_buf
+1, name
);
32717 strcpy (tmp_buf
, "\n");
32718 strcat (tmp_buf
, label
);
32719 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32720 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
32721 dbxout_stabd (N_SLINE
, bi
->line_number
);
32722 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32725 if (TARGET_LINK_STACK
)
32728 get_ppc476_thunk_name (name
);
32729 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
32730 strcat (tmp_buf
, name
);
32731 strcat (tmp_buf
, "\n");
32732 strcat (tmp_buf
, label
);
32733 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
32737 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
32738 strcat (tmp_buf
, label
);
32739 strcat (tmp_buf
, "_pic\n");
32740 strcat (tmp_buf
, label
);
32741 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
32744 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
32745 strcat (tmp_buf
, name_buf
);
32746 strcat (tmp_buf
, " - ");
32747 strcat (tmp_buf
, label
);
32748 strcat (tmp_buf
, "_pic)\n");
32750 strcat (tmp_buf
, "\tmtlr r0\n");
32752 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
32753 strcat (tmp_buf
, name_buf
);
32754 strcat (tmp_buf
, " - ");
32755 strcat (tmp_buf
, label
);
32756 strcat (tmp_buf
, "_pic)\n");
32758 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
32762 strcat (tmp_buf
, ":\nlis r12,hi16(");
32763 strcat (tmp_buf
, name_buf
);
32764 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
32765 strcat (tmp_buf
, name_buf
);
32766 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
32768 output_asm_insn (tmp_buf
, 0);
32769 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32770 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
32771 dbxout_stabd (N_SLINE
, bi
->line_number
);
32772 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32773 branch_islands
->pop ();
32777 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32778 already there or not. */
32781 no_previous_def (tree function_name
)
32786 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
32787 if (function_name
== bi
->function_name
)
32792 /* GET_PREV_LABEL gets the label name from the previous definition of
32796 get_prev_label (tree function_name
)
32801 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
32802 if (function_name
== bi
->function_name
)
32803 return bi
->label_name
;
32807 /* INSN is either a function call or a millicode call. It may have an
32808 unconditional jump in its delay slot.
32810 CALL_DEST is the routine we are calling. */
32813 output_call (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
32814 int cookie_operand_number
)
32816 static char buf
[256];
32817 if (darwin_emit_branch_islands
32818 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
32819 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
32822 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
32824 if (no_previous_def (funname
))
32826 rtx label_rtx
= gen_label_rtx ();
32827 char *label_buf
, temp_buf
[256];
32828 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
32829 CODE_LABEL_NUMBER (label_rtx
));
32830 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
32831 labelname
= get_identifier (label_buf
);
32832 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
32835 labelname
= get_prev_label (funname
);
32837 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
32838 instruction will reach 'foo', otherwise link as 'bl L42'".
32839 "L42" should be a 'branch island', that will do a far jump to
32840 'foo'. Branch islands are generated in
32841 macho_branch_islands(). */
32842 sprintf (buf
, "jbsr %%z%d,%.246s",
32843 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
32846 sprintf (buf
, "bl %%z%d", dest_operand_number
);
32850 /* Generate PIC and indirect symbol stubs. */
32853 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
32855 unsigned int length
;
32856 char *symbol_name
, *lazy_ptr_name
;
32857 char *local_label_0
;
32858 static int label
= 0;
32860 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
32861 symb
= (*targetm
.strip_name_encoding
) (symb
);
32864 length
= strlen (symb
);
32865 symbol_name
= XALLOCAVEC (char, length
+ 32);
32866 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
32868 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
32869 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
32872 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
32874 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
32878 fprintf (file
, "\t.align 5\n");
32880 fprintf (file
, "%s:\n", stub
);
32881 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
32884 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
32885 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
32887 fprintf (file
, "\tmflr r0\n");
32888 if (TARGET_LINK_STACK
)
32891 get_ppc476_thunk_name (name
);
32892 fprintf (file
, "\tbl %s\n", name
);
32893 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
32897 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
32898 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
32900 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
32901 lazy_ptr_name
, local_label_0
);
32902 fprintf (file
, "\tmtlr r0\n");
32903 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
32904 (TARGET_64BIT
? "ldu" : "lwzu"),
32905 lazy_ptr_name
, local_label_0
);
32906 fprintf (file
, "\tmtctr r12\n");
32907 fprintf (file
, "\tbctr\n");
32911 fprintf (file
, "\t.align 4\n");
32913 fprintf (file
, "%s:\n", stub
);
32914 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
32916 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
32917 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
32918 (TARGET_64BIT
? "ldu" : "lwzu"),
32920 fprintf (file
, "\tmtctr r12\n");
32921 fprintf (file
, "\tbctr\n");
32924 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
32925 fprintf (file
, "%s:\n", lazy_ptr_name
);
32926 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
32927 fprintf (file
, "%sdyld_stub_binding_helper\n",
32928 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
32931 /* Legitimize PIC addresses. If the address is already
32932 position-independent, we return ORIG. Newly generated
32933 position-independent addresses go into a reg. This is REG if non
32934 zero, otherwise we allocate register(s) as necessary. */
32936 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
32939 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
32944 if (reg
== NULL
&& !reload_completed
)
32945 reg
= gen_reg_rtx (Pmode
);
32947 if (GET_CODE (orig
) == CONST
)
32951 if (GET_CODE (XEXP (orig
, 0)) == PLUS
32952 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
32955 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
32957 /* Use a different reg for the intermediate value, as
32958 it will be marked UNCHANGING. */
32959 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
32960 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
32963 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
32966 if (GET_CODE (offset
) == CONST_INT
)
32968 if (SMALL_INT (offset
))
32969 return plus_constant (Pmode
, base
, INTVAL (offset
));
32970 else if (!reload_completed
)
32971 offset
= force_reg (Pmode
, offset
);
32974 rtx mem
= force_const_mem (Pmode
, orig
);
32975 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
32978 return gen_rtx_PLUS (Pmode
, base
, offset
);
32981 /* Fall back on generic machopic code. */
32982 return machopic_legitimize_pic_address (orig
, mode
, reg
);
32985 /* Output a .machine directive for the Darwin assembler, and call
32986 the generic start_file routine. */
32989 rs6000_darwin_file_start (void)
32991 static const struct
32995 HOST_WIDE_INT if_set
;
32997 { "ppc64", "ppc64", MASK_64BIT
},
32998 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
32999 { "power4", "ppc970", 0 },
33000 { "G5", "ppc970", 0 },
33001 { "7450", "ppc7450", 0 },
33002 { "7400", "ppc7400", MASK_ALTIVEC
},
33003 { "G4", "ppc7400", 0 },
33004 { "750", "ppc750", 0 },
33005 { "740", "ppc750", 0 },
33006 { "G3", "ppc750", 0 },
33007 { "604e", "ppc604e", 0 },
33008 { "604", "ppc604", 0 },
33009 { "603e", "ppc603", 0 },
33010 { "603", "ppc603", 0 },
33011 { "601", "ppc601", 0 },
33012 { NULL
, "ppc", 0 } };
33013 const char *cpu_id
= "";
33016 rs6000_file_start ();
33017 darwin_file_start ();
33019 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33021 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
33022 cpu_id
= rs6000_default_cpu
;
33024 if (global_options_set
.x_rs6000_cpu_index
)
33025 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
33027 /* Look through the mapping array. Pick the first name that either
33028 matches the argument, has a bit set in IF_SET that is also set
33029 in the target flags, or has a NULL name. */
33032 while (mapping
[i
].arg
!= NULL
33033 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
33034 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
33037 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
33040 #endif /* TARGET_MACHO */
33044 rs6000_elf_reloc_rw_mask (void)
33048 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
33054 /* Record an element in the table of global constructors. SYMBOL is
33055 a SYMBOL_REF of the function to be called; PRIORITY is a number
33056 between 0 and MAX_INIT_PRIORITY.
33058 This differs from default_named_section_asm_out_constructor in
33059 that we have special handling for -mrelocatable. */
33061 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
33063 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
33065 const char *section
= ".ctors";
33068 if (priority
!= DEFAULT_INIT_PRIORITY
)
33070 sprintf (buf
, ".ctors.%.5u",
33071 /* Invert the numbering so the linker puts us in the proper
33072 order; constructors are run from right to left, and the
33073 linker sorts in increasing order. */
33074 MAX_INIT_PRIORITY
- priority
);
33078 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33079 assemble_align (POINTER_SIZE
);
33081 if (DEFAULT_ABI
== ABI_V4
33082 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33084 fputs ("\t.long (", asm_out_file
);
33085 output_addr_const (asm_out_file
, symbol
);
33086 fputs (")@fixup\n", asm_out_file
);
33089 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33092 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
33094 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
33096 const char *section
= ".dtors";
33099 if (priority
!= DEFAULT_INIT_PRIORITY
)
33101 sprintf (buf
, ".dtors.%.5u",
33102 /* Invert the numbering so the linker puts us in the proper
33103 order; constructors are run from right to left, and the
33104 linker sorts in increasing order. */
33105 MAX_INIT_PRIORITY
- priority
);
33109 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33110 assemble_align (POINTER_SIZE
);
33112 if (DEFAULT_ABI
== ABI_V4
33113 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33115 fputs ("\t.long (", asm_out_file
);
33116 output_addr_const (asm_out_file
, symbol
);
33117 fputs (")@fixup\n", asm_out_file
);
33120 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33124 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
33126 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
33128 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
33129 ASM_OUTPUT_LABEL (file
, name
);
33130 fputs (DOUBLE_INT_ASM_OP
, file
);
33131 rs6000_output_function_entry (file
, name
);
33132 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
33135 fputs ("\t.size\t", file
);
33136 assemble_name (file
, name
);
33137 fputs (",24\n\t.type\t.", file
);
33138 assemble_name (file
, name
);
33139 fputs (",@function\n", file
);
33140 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
33142 fputs ("\t.globl\t.", file
);
33143 assemble_name (file
, name
);
33148 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33149 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33150 rs6000_output_function_entry (file
, name
);
33151 fputs (":\n", file
);
33156 if (DEFAULT_ABI
== ABI_V4
33157 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
33158 && !TARGET_SECURE_PLT
33159 && (!constant_pool_empty_p () || crtl
->profile
)
33160 && (uses_toc
= uses_TOC ()))
33165 switch_to_other_text_partition ();
33166 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33168 fprintf (file
, "\t.long ");
33169 assemble_name (file
, toc_label_name
);
33172 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33173 assemble_name (file
, buf
);
33176 switch_to_other_text_partition ();
33179 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33180 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33182 if (TARGET_CMODEL
== CMODEL_LARGE
&& rs6000_global_entry_point_needed_p ())
33186 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33188 fprintf (file
, "\t.quad .TOC.-");
33189 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33190 assemble_name (file
, buf
);
33194 if (DEFAULT_ABI
== ABI_AIX
)
33196 const char *desc_name
, *orig_name
;
33198 orig_name
= (*targetm
.strip_name_encoding
) (name
);
33199 desc_name
= orig_name
;
33200 while (*desc_name
== '.')
33203 if (TREE_PUBLIC (decl
))
33204 fprintf (file
, "\t.globl %s\n", desc_name
);
33206 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
33207 fprintf (file
, "%s:\n", desc_name
);
33208 fprintf (file
, "\t.long %s\n", orig_name
);
33209 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
33210 fputs ("\t.long 0\n", file
);
33211 fprintf (file
, "\t.previous\n");
33213 ASM_OUTPUT_LABEL (file
, name
);
33216 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
33218 rs6000_elf_file_end (void)
33220 #ifdef HAVE_AS_GNU_ATTRIBUTE
33221 /* ??? The value emitted depends on options active at file end.
33222 Assume anyone using #pragma or attributes that might change
33223 options knows what they are doing. */
33224 if ((TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
33225 && rs6000_passes_float
)
33229 if (TARGET_HARD_FLOAT
)
33233 if (rs6000_passes_long_double
)
33235 if (!TARGET_LONG_DOUBLE_128
)
33237 else if (TARGET_IEEEQUAD
)
33242 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", fp
);
33244 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
33246 if (rs6000_passes_vector
)
33247 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
33248 (TARGET_ALTIVEC_ABI
? 2 : 1));
33249 if (rs6000_returns_struct
)
33250 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
33251 aix_struct_return
? 2 : 1);
33254 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33255 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
33256 file_end_indicate_exec_stack ();
33259 if (flag_split_stack
)
33260 file_end_indicate_split_stack ();
33264 /* We have expanded a CPU builtin, so we need to emit a reference to
33265 the special symbol that LIBC uses to declare it supports the
33266 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33267 switch_to_section (data_section
);
33268 fprintf (asm_out_file
, "\t.align %u\n", TARGET_32BIT
? 2 : 3);
33269 fprintf (asm_out_file
, "\t%s %s\n",
33270 TARGET_32BIT
? ".long" : ".quad", tcb_verification_symbol
);
33277 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33278 #define HAVE_XCOFF_DWARF_EXTRAS 0
33281 static enum unwind_info_type
33282 rs6000_xcoff_debug_unwind_info (void)
33288 rs6000_xcoff_asm_output_anchor (rtx symbol
)
33292 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
33293 SYMBOL_REF_BLOCK_OFFSET (symbol
));
33294 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
33295 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
33296 fprintf (asm_out_file
, ",");
33297 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
33298 fprintf (asm_out_file
, "\n");
33302 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
33304 fputs (GLOBAL_ASM_OP
, stream
);
33305 RS6000_OUTPUT_BASENAME (stream
, name
);
33306 putc ('\n', stream
);
33309 /* A get_unnamed_decl callback, used for read-only sections. PTR
33310 points to the section string variable. */
33313 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
33315 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
33316 *(const char *const *) directive
,
33317 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33320 /* Likewise for read-write sections. */
33323 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
33325 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
33326 *(const char *const *) directive
,
33327 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33331 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
33333 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
33334 *(const char *const *) directive
,
33335 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33338 /* A get_unnamed_section callback, used for switching to toc_section. */
33341 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
33343 if (TARGET_MINIMAL_TOC
)
33345 /* toc_section is always selected at least once from
33346 rs6000_xcoff_file_start, so this is guaranteed to
33347 always be defined once and only once in each file. */
33348 if (!toc_initialized
)
33350 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
33351 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
33352 toc_initialized
= 1;
33354 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
33355 (TARGET_32BIT
? "" : ",3"));
33358 fputs ("\t.toc\n", asm_out_file
);
33361 /* Implement TARGET_ASM_INIT_SECTIONS. */
33364 rs6000_xcoff_asm_init_sections (void)
33366 read_only_data_section
33367 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33368 &xcoff_read_only_section_name
);
33370 private_data_section
33371 = get_unnamed_section (SECTION_WRITE
,
33372 rs6000_xcoff_output_readwrite_section_asm_op
,
33373 &xcoff_private_data_section_name
);
33376 = get_unnamed_section (SECTION_TLS
,
33377 rs6000_xcoff_output_tls_section_asm_op
,
33378 &xcoff_tls_data_section_name
);
33380 tls_private_data_section
33381 = get_unnamed_section (SECTION_TLS
,
33382 rs6000_xcoff_output_tls_section_asm_op
,
33383 &xcoff_private_data_section_name
);
33385 read_only_private_data_section
33386 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33387 &xcoff_private_data_section_name
);
33390 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
33392 readonly_data_section
= read_only_data_section
;
33396 rs6000_xcoff_reloc_rw_mask (void)
33402 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
33403 tree decl ATTRIBUTE_UNUSED
)
33406 static const char * const suffix
[5] = { "PR", "RO", "RW", "TL", "XO" };
33408 if (flags
& SECTION_EXCLUDE
)
33410 else if (flags
& SECTION_DEBUG
)
33412 fprintf (asm_out_file
, "\t.dwsect %s\n", name
);
33415 else if (flags
& SECTION_CODE
)
33417 else if (flags
& SECTION_TLS
)
33419 else if (flags
& SECTION_WRITE
)
33424 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
33425 (flags
& SECTION_CODE
) ? "." : "",
33426 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
33429 #define IN_NAMED_SECTION(DECL) \
33430 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33431 && DECL_SECTION_NAME (DECL) != NULL)
33434 rs6000_xcoff_select_section (tree decl
, int reloc
,
33435 unsigned HOST_WIDE_INT align
)
33437 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33439 if (align
> BIGGEST_ALIGNMENT
)
33441 resolve_unique_section (decl
, reloc
, true);
33442 if (IN_NAMED_SECTION (decl
))
33443 return get_named_section (decl
, NULL
, reloc
);
33446 if (decl_readonly_section (decl
, reloc
))
33448 if (TREE_PUBLIC (decl
))
33449 return read_only_data_section
;
33451 return read_only_private_data_section
;
33456 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
33458 if (TREE_PUBLIC (decl
))
33459 return tls_data_section
;
33460 else if (bss_initializer_p (decl
))
33462 /* Convert to COMMON to emit in BSS. */
33463 DECL_COMMON (decl
) = 1;
33464 return tls_comm_section
;
33467 return tls_private_data_section
;
33471 if (TREE_PUBLIC (decl
))
33472 return data_section
;
33474 return private_data_section
;
33479 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
33483 /* Use select_section for private data and uninitialized data with
33484 alignment <= BIGGEST_ALIGNMENT. */
33485 if (!TREE_PUBLIC (decl
)
33486 || DECL_COMMON (decl
)
33487 || (DECL_INITIAL (decl
) == NULL_TREE
33488 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
33489 || DECL_INITIAL (decl
) == error_mark_node
33490 || (flag_zero_initialized_in_bss
33491 && initializer_zerop (DECL_INITIAL (decl
))))
33494 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
33495 name
= (*targetm
.strip_name_encoding
) (name
);
33496 set_decl_section_name (decl
, name
);
33499 /* Select section for constant in constant pool.
33501 On RS/6000, all constants are in the private read-only data area.
33502 However, if this is being placed in the TOC it must be output as a
33506 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
33507 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
33509 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
33510 return toc_section
;
33512 return read_only_private_data_section
;
33515 /* Remove any trailing [DS] or the like from the symbol name. */
33517 static const char *
33518 rs6000_xcoff_strip_name_encoding (const char *name
)
33523 len
= strlen (name
);
33524 if (name
[len
- 1] == ']')
33525 return ggc_alloc_string (name
, len
- 4);
33530 /* Section attributes. AIX is always PIC. */
33532 static unsigned int
33533 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
33535 unsigned int align
;
33536 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
33538 /* Align to at least UNIT size. */
33539 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
33540 align
= MIN_UNITS_PER_WORD
;
33542 /* Increase alignment of large objects if not already stricter. */
33543 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
33544 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
33545 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
33547 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
33550 /* Output at beginning of assembler file.
33552 Initialize the section names for the RS/6000 at this point.
33554 Specify filename, including full path, to assembler.
33556 We want to go into the TOC section so at least one .toc will be emitted.
33557 Also, in order to output proper .bs/.es pairs, we need at least one static
33558 [RW] section emitted.
33560 Finally, declare mcount when profiling to make the assembler happy. */
33563 rs6000_xcoff_file_start (void)
33565 rs6000_gen_section_name (&xcoff_bss_section_name
,
33566 main_input_filename
, ".bss_");
33567 rs6000_gen_section_name (&xcoff_private_data_section_name
,
33568 main_input_filename
, ".rw_");
33569 rs6000_gen_section_name (&xcoff_read_only_section_name
,
33570 main_input_filename
, ".ro_");
33571 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
33572 main_input_filename
, ".tls_");
33573 rs6000_gen_section_name (&xcoff_tbss_section_name
,
33574 main_input_filename
, ".tbss_[UL]");
33576 fputs ("\t.file\t", asm_out_file
);
33577 output_quoted_string (asm_out_file
, main_input_filename
);
33578 fputc ('\n', asm_out_file
);
33579 if (write_symbols
!= NO_DEBUG
)
33580 switch_to_section (private_data_section
);
33581 switch_to_section (toc_section
);
33582 switch_to_section (text_section
);
33584 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
33585 rs6000_file_start ();
33588 /* Output at end of assembler file.
33589 On the RS/6000, referencing data should automatically pull in text. */
33592 rs6000_xcoff_file_end (void)
33594 switch_to_section (text_section
);
33595 fputs ("_section_.text:\n", asm_out_file
);
33596 switch_to_section (data_section
);
33597 fputs (TARGET_32BIT
33598 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33602 struct declare_alias_data
33605 bool function_descriptor
;
33608 /* Declare alias N. A helper function for for_node_and_aliases. */
33611 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
33613 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
33614 /* Main symbol is output specially, because varasm machinery does part of
33615 the job for us - we do not need to declare .globl/lglobs and such. */
33616 if (!n
->alias
|| n
->weakref
)
33619 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
33622 /* Prevent assemble_alias from trying to use .set pseudo operation
33623 that does not behave as expected by the middle-end. */
33624 TREE_ASM_WRITTEN (n
->decl
) = true;
33626 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
33627 char *buffer
= (char *) alloca (strlen (name
) + 2);
33629 int dollar_inside
= 0;
33631 strcpy (buffer
, name
);
33632 p
= strchr (buffer
, '$');
33636 p
= strchr (p
+ 1, '$');
33638 if (TREE_PUBLIC (n
->decl
))
33640 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
33642 if (dollar_inside
) {
33643 if (data
->function_descriptor
)
33644 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33645 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33647 if (data
->function_descriptor
)
33649 fputs ("\t.globl .", data
->file
);
33650 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33651 putc ('\n', data
->file
);
33653 fputs ("\t.globl ", data
->file
);
33654 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33655 putc ('\n', data
->file
);
33657 #ifdef ASM_WEAKEN_DECL
33658 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
33659 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
33666 if (data
->function_descriptor
)
33667 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33668 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33670 if (data
->function_descriptor
)
33672 fputs ("\t.lglobl .", data
->file
);
33673 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33674 putc ('\n', data
->file
);
33676 fputs ("\t.lglobl ", data
->file
);
33677 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33678 putc ('\n', data
->file
);
33680 if (data
->function_descriptor
)
33681 fputs (".", data
->file
);
33682 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
33683 fputs (":\n", data
->file
);
33688 #ifdef HAVE_GAS_HIDDEN
33689 /* Helper function to calculate visibility of a DECL
33690 and return the value as a const string. */
33692 static const char *
33693 rs6000_xcoff_visibility (tree decl
)
33695 static const char * const visibility_types
[] = {
33696 "", ",protected", ",hidden", ",internal"
33699 enum symbol_visibility vis
= DECL_VISIBILITY (decl
);
33700 return visibility_types
[vis
];
33705 /* This macro produces the initial definition of a function name.
33706 On the RS/6000, we need to place an extra '.' in the function name and
33707 output the function descriptor.
33708 Dollar signs are converted to underscores.
33710 The csect for the function will have already been created when
33711 text_section was selected. We do have to go back to that csect, however.
33713 The third and fourth parameters to the .function pseudo-op (16 and 044)
33714 are placeholders which no longer have any use.
33716 Because AIX assembler's .set command has unexpected semantics, we output
33717 all aliases as alternative labels in front of the definition. */
33720 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
33722 char *buffer
= (char *) alloca (strlen (name
) + 1);
33724 int dollar_inside
= 0;
33725 struct declare_alias_data data
= {file
, false};
33727 strcpy (buffer
, name
);
33728 p
= strchr (buffer
, '$');
33732 p
= strchr (p
+ 1, '$');
33734 if (TREE_PUBLIC (decl
))
33736 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
33738 if (dollar_inside
) {
33739 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33740 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33742 fputs ("\t.globl .", file
);
33743 RS6000_OUTPUT_BASENAME (file
, buffer
);
33744 #ifdef HAVE_GAS_HIDDEN
33745 fputs (rs6000_xcoff_visibility (decl
), file
);
33752 if (dollar_inside
) {
33753 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
33754 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
33756 fputs ("\t.lglobl .", file
);
33757 RS6000_OUTPUT_BASENAME (file
, buffer
);
33760 fputs ("\t.csect ", file
);
33761 RS6000_OUTPUT_BASENAME (file
, buffer
);
33762 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
33763 RS6000_OUTPUT_BASENAME (file
, buffer
);
33764 fputs (":\n", file
);
33765 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
33767 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
33768 RS6000_OUTPUT_BASENAME (file
, buffer
);
33769 fputs (", TOC[tc0], 0\n", file
);
33771 switch_to_section (function_section (decl
));
33773 RS6000_OUTPUT_BASENAME (file
, buffer
);
33774 fputs (":\n", file
);
33775 data
.function_descriptor
= true;
33776 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
33778 if (!DECL_IGNORED_P (decl
))
33780 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
33781 xcoffout_declare_function (file
, decl
, buffer
);
33782 else if (write_symbols
== DWARF2_DEBUG
)
33784 name
= (*targetm
.strip_name_encoding
) (name
);
33785 fprintf (file
, "\t.function .%s,.%s,2,0\n", name
, name
);
33792 /* Output assembly language to globalize a symbol from a DECL,
33793 possibly with visibility. */
33796 rs6000_xcoff_asm_globalize_decl_name (FILE *stream
, tree decl
)
33798 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
33799 fputs (GLOBAL_ASM_OP
, stream
);
33800 RS6000_OUTPUT_BASENAME (stream
, name
);
33801 #ifdef HAVE_GAS_HIDDEN
33802 fputs (rs6000_xcoff_visibility (decl
), stream
);
33804 putc ('\n', stream
);
33807 /* Output assembly language to define a symbol as COMMON from a DECL,
33808 possibly with visibility. */
33811 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream
,
33812 tree decl ATTRIBUTE_UNUSED
,
33814 unsigned HOST_WIDE_INT size
,
33815 unsigned HOST_WIDE_INT align
)
33817 unsigned HOST_WIDE_INT align2
= 2;
33820 align2
= floor_log2 (align
/ BITS_PER_UNIT
);
33824 fputs (COMMON_ASM_OP
, stream
);
33825 RS6000_OUTPUT_BASENAME (stream
, name
);
33828 "," HOST_WIDE_INT_PRINT_UNSIGNED
"," HOST_WIDE_INT_PRINT_UNSIGNED
,
33831 #ifdef HAVE_GAS_HIDDEN
33833 fputs (rs6000_xcoff_visibility (decl
), stream
);
33835 putc ('\n', stream
);
33838 /* This macro produces the initial definition of a object (variable) name.
33839 Because AIX assembler's .set command has unexpected semantics, we output
33840 all aliases as alternative labels in front of the definition. */
33843 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
33845 struct declare_alias_data data
= {file
, false};
33846 RS6000_OUTPUT_BASENAME (file
, name
);
33847 fputs (":\n", file
);
33848 symtab_node::get_create (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
33852 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
33855 rs6000_asm_output_dwarf_pcrel (FILE *file
, int size
, const char *label
)
33857 fputs (integer_asm_op (size
, FALSE
), file
);
33858 assemble_name (file
, label
);
33859 fputs ("-$", file
);
33862 /* Output a symbol offset relative to the dbase for the current object.
33863 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
33866 __gcc_unwind_dbase is embedded in all executables/libraries through
33867 libgcc/config/rs6000/crtdbase.S. */
33870 rs6000_asm_output_dwarf_datarel (FILE *file
, int size
, const char *label
)
33872 fputs (integer_asm_op (size
, FALSE
), file
);
33873 assemble_name (file
, label
);
33874 fputs("-__gcc_unwind_dbase", file
);
33879 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
33883 const char *symname
;
33885 default_encode_section_info (decl
, rtl
, first
);
33887 /* Careful not to prod global register variables. */
33890 symbol
= XEXP (rtl
, 0);
33891 if (GET_CODE (symbol
) != SYMBOL_REF
)
33894 flags
= SYMBOL_REF_FLAGS (symbol
);
33896 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
33897 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
33899 SYMBOL_REF_FLAGS (symbol
) = flags
;
33901 /* Append mapping class to extern decls. */
33902 symname
= XSTR (symbol
, 0);
33903 if (decl
/* sync condition with assemble_external () */
33904 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
33905 && ((TREE_CODE (decl
) == VAR_DECL
&& !DECL_THREAD_LOCAL_P (decl
))
33906 || TREE_CODE (decl
) == FUNCTION_DECL
)
33907 && symname
[strlen (symname
) - 1] != ']')
33909 char *newname
= (char *) alloca (strlen (symname
) + 5);
33910 strcpy (newname
, symname
);
33911 strcat (newname
, (TREE_CODE (decl
) == FUNCTION_DECL
33912 ? "[DS]" : "[UA]"));
33913 XSTR (symbol
, 0) = ggc_strdup (newname
);
33916 #endif /* HAVE_AS_TLS */
33917 #endif /* TARGET_XCOFF */
33920 rs6000_asm_weaken_decl (FILE *stream
, tree decl
,
33921 const char *name
, const char *val
)
33923 fputs ("\t.weak\t", stream
);
33924 RS6000_OUTPUT_BASENAME (stream
, name
);
33925 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
33926 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
33929 fputs ("[DS]", stream
);
33930 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33932 fputs (rs6000_xcoff_visibility (decl
), stream
);
33934 fputs ("\n\t.weak\t.", stream
);
33935 RS6000_OUTPUT_BASENAME (stream
, name
);
33937 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
33939 fputs (rs6000_xcoff_visibility (decl
), stream
);
33941 fputc ('\n', stream
);
33944 #ifdef ASM_OUTPUT_DEF
33945 ASM_OUTPUT_DEF (stream
, name
, val
);
33947 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
33948 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
33950 fputs ("\t.set\t.", stream
);
33951 RS6000_OUTPUT_BASENAME (stream
, name
);
33952 fputs (",.", stream
);
33953 RS6000_OUTPUT_BASENAME (stream
, val
);
33954 fputc ('\n', stream
);
33960 /* Return true if INSN should not be copied. */
33963 rs6000_cannot_copy_insn_p (rtx_insn
*insn
)
33965 return recog_memoized (insn
) >= 0
33966 && get_attr_cannot_copy (insn
);
33969 /* Compute a (partial) cost for rtx X. Return true if the complete
33970 cost has been computed, and false if subexpressions should be
33971 scanned. In either case, *TOTAL contains the cost result. */
33974 rs6000_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
33975 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
33977 int code
= GET_CODE (x
);
33981 /* On the RS/6000, if it is valid in the insn, it is free. */
33983 if (((outer_code
== SET
33984 || outer_code
== PLUS
33985 || outer_code
== MINUS
)
33986 && (satisfies_constraint_I (x
)
33987 || satisfies_constraint_L (x
)))
33988 || (outer_code
== AND
33989 && (satisfies_constraint_K (x
)
33991 ? satisfies_constraint_L (x
)
33992 : satisfies_constraint_J (x
))))
33993 || ((outer_code
== IOR
|| outer_code
== XOR
)
33994 && (satisfies_constraint_K (x
)
33996 ? satisfies_constraint_L (x
)
33997 : satisfies_constraint_J (x
))))
33998 || outer_code
== ASHIFT
33999 || outer_code
== ASHIFTRT
34000 || outer_code
== LSHIFTRT
34001 || outer_code
== ROTATE
34002 || outer_code
== ROTATERT
34003 || outer_code
== ZERO_EXTRACT
34004 || (outer_code
== MULT
34005 && satisfies_constraint_I (x
))
34006 || ((outer_code
== DIV
|| outer_code
== UDIV
34007 || outer_code
== MOD
|| outer_code
== UMOD
)
34008 && exact_log2 (INTVAL (x
)) >= 0)
34009 || (outer_code
== COMPARE
34010 && (satisfies_constraint_I (x
)
34011 || satisfies_constraint_K (x
)))
34012 || ((outer_code
== EQ
|| outer_code
== NE
)
34013 && (satisfies_constraint_I (x
)
34014 || satisfies_constraint_K (x
)
34016 ? satisfies_constraint_L (x
)
34017 : satisfies_constraint_J (x
))))
34018 || (outer_code
== GTU
34019 && satisfies_constraint_I (x
))
34020 || (outer_code
== LTU
34021 && satisfies_constraint_P (x
)))
34026 else if ((outer_code
== PLUS
34027 && reg_or_add_cint_operand (x
, VOIDmode
))
34028 || (outer_code
== MINUS
34029 && reg_or_sub_cint_operand (x
, VOIDmode
))
34030 || ((outer_code
== SET
34031 || outer_code
== IOR
34032 || outer_code
== XOR
)
34034 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
34036 *total
= COSTS_N_INSNS (1);
34042 case CONST_WIDE_INT
:
34046 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34050 /* When optimizing for size, MEM should be slightly more expensive
34051 than generating address, e.g., (plus (reg) (const)).
34052 L1 cache latency is about two instructions. */
34053 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34054 if (rs6000_slow_unaligned_access (mode
, MEM_ALIGN (x
)))
34055 *total
+= COSTS_N_INSNS (100);
34064 if (FLOAT_MODE_P (mode
))
34065 *total
= rs6000_cost
->fp
;
34067 *total
= COSTS_N_INSNS (1);
34071 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
34072 && satisfies_constraint_I (XEXP (x
, 1)))
34074 if (INTVAL (XEXP (x
, 1)) >= -256
34075 && INTVAL (XEXP (x
, 1)) <= 255)
34076 *total
= rs6000_cost
->mulsi_const9
;
34078 *total
= rs6000_cost
->mulsi_const
;
34080 else if (mode
== SFmode
)
34081 *total
= rs6000_cost
->fp
;
34082 else if (FLOAT_MODE_P (mode
))
34083 *total
= rs6000_cost
->dmul
;
34084 else if (mode
== DImode
)
34085 *total
= rs6000_cost
->muldi
;
34087 *total
= rs6000_cost
->mulsi
;
34091 if (mode
== SFmode
)
34092 *total
= rs6000_cost
->fp
;
34094 *total
= rs6000_cost
->dmul
;
34099 if (FLOAT_MODE_P (mode
))
34101 *total
= mode
== DFmode
? rs6000_cost
->ddiv
34102 : rs6000_cost
->sdiv
;
34109 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
34110 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
34112 if (code
== DIV
|| code
== MOD
)
34114 *total
= COSTS_N_INSNS (2);
34117 *total
= COSTS_N_INSNS (1);
34121 if (GET_MODE (XEXP (x
, 1)) == DImode
)
34122 *total
= rs6000_cost
->divdi
;
34124 *total
= rs6000_cost
->divsi
;
34126 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34127 if (!TARGET_MODULO
&& (code
== MOD
|| code
== UMOD
))
34128 *total
+= COSTS_N_INSNS (2);
34132 *total
= COSTS_N_INSNS (TARGET_CTZ
? 1 : 4);
34136 *total
= COSTS_N_INSNS (4);
34140 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
34144 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
34148 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
34151 *total
= COSTS_N_INSNS (1);
34155 if (CONST_INT_P (XEXP (x
, 1)))
34157 rtx left
= XEXP (x
, 0);
34158 rtx_code left_code
= GET_CODE (left
);
34160 /* rotate-and-mask: 1 insn. */
34161 if ((left_code
== ROTATE
34162 || left_code
== ASHIFT
34163 || left_code
== LSHIFTRT
)
34164 && rs6000_is_valid_shift_mask (XEXP (x
, 1), left
, mode
))
34166 *total
= rtx_cost (XEXP (left
, 0), mode
, left_code
, 0, speed
);
34167 if (!CONST_INT_P (XEXP (left
, 1)))
34168 *total
+= rtx_cost (XEXP (left
, 1), SImode
, left_code
, 1, speed
);
34169 *total
+= COSTS_N_INSNS (1);
34173 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34174 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
34175 if (rs6000_is_valid_and_mask (XEXP (x
, 1), mode
)
34176 || (val
& 0xffff) == val
34177 || (val
& 0xffff0000) == val
34178 || ((val
& 0xffff) == 0 && mode
== SImode
))
34180 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34181 *total
+= COSTS_N_INSNS (1);
34186 if (rs6000_is_valid_2insn_and (XEXP (x
, 1), mode
))
34188 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34189 *total
+= COSTS_N_INSNS (2);
34194 *total
= COSTS_N_INSNS (1);
34199 *total
= COSTS_N_INSNS (1);
34205 *total
= COSTS_N_INSNS (1);
34209 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34210 the sign extend and shift separately within the insn. */
34211 if (TARGET_EXTSWSLI
&& mode
== DImode
34212 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
34213 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == SImode
)
34224 /* Handle mul_highpart. */
34225 if (outer_code
== TRUNCATE
34226 && GET_CODE (XEXP (x
, 0)) == MULT
)
34228 if (mode
== DImode
)
34229 *total
= rs6000_cost
->muldi
;
34231 *total
= rs6000_cost
->mulsi
;
34234 else if (outer_code
== AND
)
34237 *total
= COSTS_N_INSNS (1);
34242 if (GET_CODE (XEXP (x
, 0)) == MEM
)
34245 *total
= COSTS_N_INSNS (1);
34251 if (!FLOAT_MODE_P (mode
))
34253 *total
= COSTS_N_INSNS (1);
34259 case UNSIGNED_FLOAT
:
34262 case FLOAT_TRUNCATE
:
34263 *total
= rs6000_cost
->fp
;
34267 if (mode
== DFmode
)
34268 *total
= rs6000_cost
->sfdf_convert
;
34270 *total
= rs6000_cost
->fp
;
34274 switch (XINT (x
, 1))
34277 *total
= rs6000_cost
->fp
;
34289 *total
= COSTS_N_INSNS (1);
34292 else if (FLOAT_MODE_P (mode
) && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
)
34294 *total
= rs6000_cost
->fp
;
34303 /* Carry bit requires mode == Pmode.
34304 NEG or PLUS already counted so only add one. */
34306 && (outer_code
== NEG
|| outer_code
== PLUS
))
34308 *total
= COSTS_N_INSNS (1);
34316 if (outer_code
== SET
)
34318 if (XEXP (x
, 1) == const0_rtx
)
34320 *total
= COSTS_N_INSNS (2);
34325 *total
= COSTS_N_INSNS (3);
34330 if (outer_code
== COMPARE
)
34344 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34347 rs6000_debug_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
34348 int opno
, int *total
, bool speed
)
34350 bool ret
= rs6000_rtx_costs (x
, mode
, outer_code
, opno
, total
, speed
);
34353 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34354 "opno = %d, total = %d, speed = %s, x:\n",
34355 ret
? "complete" : "scan inner",
34356 GET_MODE_NAME (mode
),
34357 GET_RTX_NAME (outer_code
),
34360 speed
? "true" : "false");
34368 rs6000_insn_cost (rtx_insn
*insn
, bool speed
)
34370 if (recog_memoized (insn
) < 0)
34374 return get_attr_length (insn
);
34376 int cost
= get_attr_cost (insn
);
34380 int n
= get_attr_length (insn
) / 4;
34381 enum attr_type type
= get_attr_type (insn
);
34388 cost
= COSTS_N_INSNS (n
+ 1);
34392 switch (get_attr_size (insn
))
34395 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi_const9
;
34398 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi_const
;
34401 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi
;
34404 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->muldi
;
34407 gcc_unreachable ();
34411 switch (get_attr_size (insn
))
34414 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->divsi
;
34417 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->divdi
;
34420 gcc_unreachable ();
34425 cost
= n
* rs6000_cost
->fp
;
34428 cost
= n
* rs6000_cost
->dmul
;
34431 cost
= n
* rs6000_cost
->sdiv
;
34434 cost
= n
* rs6000_cost
->ddiv
;
34441 cost
= COSTS_N_INSNS (n
+ 2);
34445 cost
= COSTS_N_INSNS (n
);
34451 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34454 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
34455 addr_space_t as
, bool speed
)
34457 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
34459 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34460 ret
, speed
? "true" : "false");
34467 /* A C expression returning the cost of moving data from a register of class
34468 CLASS1 to one of CLASS2. */
34471 rs6000_register_move_cost (machine_mode mode
,
34472 reg_class_t from
, reg_class_t to
)
34476 if (TARGET_DEBUG_COST
)
34479 /* Moves from/to GENERAL_REGS. */
34480 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
34481 || reg_classes_intersect_p (from
, GENERAL_REGS
))
34483 reg_class_t rclass
= from
;
34485 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
34488 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
34489 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
34490 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
34492 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34494 else if (rclass
== CR_REGS
)
34497 /* For those processors that have slow LR/CTR moves, make them more
34498 expensive than memory in order to bias spills to memory .*/
34499 else if ((rs6000_tune
== PROCESSOR_POWER6
34500 || rs6000_tune
== PROCESSOR_POWER7
34501 || rs6000_tune
== PROCESSOR_POWER8
34502 || rs6000_tune
== PROCESSOR_POWER9
)
34503 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
34504 ret
= 6 * hard_regno_nregs (0, mode
);
34507 /* A move will cost one instruction per GPR moved. */
34508 ret
= 2 * hard_regno_nregs (0, mode
);
34511 /* If we have VSX, we can easily move between FPR or Altivec registers. */
34512 else if (VECTOR_MEM_VSX_P (mode
)
34513 && reg_classes_intersect_p (to
, VSX_REGS
)
34514 && reg_classes_intersect_p (from
, VSX_REGS
))
34515 ret
= 2 * hard_regno_nregs (FIRST_FPR_REGNO
, mode
);
34517 /* Moving between two similar registers is just one instruction. */
34518 else if (reg_classes_intersect_p (to
, from
))
34519 ret
= (FLOAT128_2REG_P (mode
)) ? 4 : 2;
34521 /* Everything else has to go through GENERAL_REGS. */
34523 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
34524 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
34526 if (TARGET_DEBUG_COST
)
34528 if (dbg_cost_ctrl
== 1)
34530 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
34531 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
34532 reg_class_names
[to
]);
34539 /* A C expressions returning the cost of moving data of MODE from a register to
34543 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
34544 bool in ATTRIBUTE_UNUSED
)
34548 if (TARGET_DEBUG_COST
)
34551 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
34552 ret
= 4 * hard_regno_nregs (0, mode
);
34553 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
34554 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
34555 ret
= 4 * hard_regno_nregs (32, mode
);
34556 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
34557 ret
= 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO
, mode
);
34559 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
34561 if (TARGET_DEBUG_COST
)
34563 if (dbg_cost_ctrl
== 1)
34565 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34566 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
34573 /* Returns a code for a target-specific builtin that implements
34574 reciprocal of the function, or NULL_TREE if not available. */
34577 rs6000_builtin_reciprocal (tree fndecl
)
34579 switch (DECL_FUNCTION_CODE (fndecl
))
34581 case VSX_BUILTIN_XVSQRTDP
:
34582 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
34585 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
34587 case VSX_BUILTIN_XVSQRTSP
:
34588 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
34591 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
34598 /* Load up a constant. If the mode is a vector mode, splat the value across
34599 all of the vector elements. */
34602 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
34606 if (mode
== SFmode
|| mode
== DFmode
)
34608 rtx d
= const_double_from_real_value (dconst
, mode
);
34609 reg
= force_reg (mode
, d
);
34611 else if (mode
== V4SFmode
)
34613 rtx d
= const_double_from_real_value (dconst
, SFmode
);
34614 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
34615 reg
= gen_reg_rtx (mode
);
34616 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
34618 else if (mode
== V2DFmode
)
34620 rtx d
= const_double_from_real_value (dconst
, DFmode
);
34621 rtvec v
= gen_rtvec (2, d
, d
);
34622 reg
= gen_reg_rtx (mode
);
34623 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
34626 gcc_unreachable ();
34631 /* Generate an FMA instruction. */
34634 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
34636 machine_mode mode
= GET_MODE (target
);
34639 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
34640 gcc_assert (dst
!= NULL
);
34643 emit_move_insn (target
, dst
);
34646 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34649 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
34651 machine_mode mode
= GET_MODE (dst
);
34654 /* This is a tad more complicated, since the fnma_optab is for
34655 a different expression: fma(-m1, m2, a), which is the same
34656 thing except in the case of signed zeros.
34658 Fortunately we know that if FMA is supported that FNMSUB is
34659 also supported in the ISA. Just expand it directly. */
34661 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
34663 r
= gen_rtx_NEG (mode
, a
);
34664 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
34665 r
= gen_rtx_NEG (mode
, r
);
34666 emit_insn (gen_rtx_SET (dst
, r
));
34669 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34670 add a reg_note saying that this was a division. Support both scalar and
34671 vector divide. Assumes no trapping math and finite arguments. */
34674 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
34676 machine_mode mode
= GET_MODE (dst
);
34677 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
34680 /* Low precision estimates guarantee 5 bits of accuracy. High
34681 precision estimates guarantee 14 bits of accuracy. SFmode
34682 requires 23 bits of accuracy. DFmode requires 52 bits of
34683 accuracy. Each pass at least doubles the accuracy, leading
34684 to the following. */
34685 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
34686 if (mode
== DFmode
|| mode
== V2DFmode
)
34689 enum insn_code code
= optab_handler (smul_optab
, mode
);
34690 insn_gen_fn gen_mul
= GEN_FCN (code
);
34692 gcc_assert (code
!= CODE_FOR_nothing
);
34694 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
34696 /* x0 = 1./d estimate */
34697 x0
= gen_reg_rtx (mode
);
34698 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
34701 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34704 /* e0 = 1. - d * x0 */
34705 e0
= gen_reg_rtx (mode
);
34706 rs6000_emit_nmsub (e0
, d
, x0
, one
);
34708 /* x1 = x0 + e0 * x0 */
34709 x1
= gen_reg_rtx (mode
);
34710 rs6000_emit_madd (x1
, e0
, x0
, x0
);
34712 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
34713 ++i
, xprev
= xnext
, eprev
= enext
) {
34715 /* enext = eprev * eprev */
34716 enext
= gen_reg_rtx (mode
);
34717 emit_insn (gen_mul (enext
, eprev
, eprev
));
34719 /* xnext = xprev + enext * xprev */
34720 xnext
= gen_reg_rtx (mode
);
34721 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
34727 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34729 /* u = n * xprev */
34730 u
= gen_reg_rtx (mode
);
34731 emit_insn (gen_mul (u
, n
, xprev
));
34733 /* v = n - (d * u) */
34734 v
= gen_reg_rtx (mode
);
34735 rs6000_emit_nmsub (v
, d
, u
, n
);
34737 /* dst = (v * xprev) + u */
34738 rs6000_emit_madd (dst
, v
, xprev
, u
);
34741 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
34744 /* Goldschmidt's Algorithm for single/double-precision floating point
34745 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34748 rs6000_emit_swsqrt (rtx dst
, rtx src
, bool recip
)
34750 machine_mode mode
= GET_MODE (src
);
34751 rtx e
= gen_reg_rtx (mode
);
34752 rtx g
= gen_reg_rtx (mode
);
34753 rtx h
= gen_reg_rtx (mode
);
34755 /* Low precision estimates guarantee 5 bits of accuracy. High
34756 precision estimates guarantee 14 bits of accuracy. SFmode
34757 requires 23 bits of accuracy. DFmode requires 52 bits of
34758 accuracy. Each pass at least doubles the accuracy, leading
34759 to the following. */
34760 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
34761 if (mode
== DFmode
|| mode
== V2DFmode
)
34766 enum insn_code code
= optab_handler (smul_optab
, mode
);
34767 insn_gen_fn gen_mul
= GEN_FCN (code
);
34769 gcc_assert (code
!= CODE_FOR_nothing
);
34771 mhalf
= rs6000_load_constant_and_splat (mode
, dconsthalf
);
34773 /* e = rsqrt estimate */
34774 emit_insn (gen_rtx_SET (e
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
34777 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
34780 rtx zero
= force_reg (mode
, CONST0_RTX (mode
));
34782 if (mode
== SFmode
)
34784 rtx target
= emit_conditional_move (e
, GT
, src
, zero
, mode
,
34787 emit_move_insn (e
, target
);
34791 rtx cond
= gen_rtx_GT (VOIDmode
, e
, zero
);
34792 rs6000_emit_vector_cond_expr (e
, e
, zero
, cond
, src
, zero
);
34796 /* g = sqrt estimate. */
34797 emit_insn (gen_mul (g
, e
, src
));
34798 /* h = 1/(2*sqrt) estimate. */
34799 emit_insn (gen_mul (h
, e
, mhalf
));
34805 rtx t
= gen_reg_rtx (mode
);
34806 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
34807 /* Apply correction directly to 1/rsqrt estimate. */
34808 rs6000_emit_madd (dst
, e
, t
, e
);
34812 for (i
= 0; i
< passes
; i
++)
34814 rtx t1
= gen_reg_rtx (mode
);
34815 rtx g1
= gen_reg_rtx (mode
);
34816 rtx h1
= gen_reg_rtx (mode
);
34818 rs6000_emit_nmsub (t1
, g
, h
, mhalf
);
34819 rs6000_emit_madd (g1
, g
, t1
, g
);
34820 rs6000_emit_madd (h1
, h
, t1
, h
);
34825 /* Multiply by 2 for 1/rsqrt. */
34826 emit_insn (gen_add3_insn (dst
, h
, h
));
34831 rtx t
= gen_reg_rtx (mode
);
34832 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
34833 rs6000_emit_madd (dst
, g
, t
, g
);
34839 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
34840 (Power7) targets. DST is the target, and SRC is the argument operand. */
34843 rs6000_emit_popcount (rtx dst
, rtx src
)
34845 machine_mode mode
= GET_MODE (dst
);
34848 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
34849 if (TARGET_POPCNTD
)
34851 if (mode
== SImode
)
34852 emit_insn (gen_popcntdsi2 (dst
, src
));
34854 emit_insn (gen_popcntddi2 (dst
, src
));
34858 tmp1
= gen_reg_rtx (mode
);
34860 if (mode
== SImode
)
34862 emit_insn (gen_popcntbsi2 (tmp1
, src
));
34863 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
34865 tmp2
= force_reg (SImode
, tmp2
);
34866 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
34870 emit_insn (gen_popcntbdi2 (tmp1
, src
));
34871 tmp2
= expand_mult (DImode
, tmp1
,
34872 GEN_INT ((HOST_WIDE_INT
)
34873 0x01010101 << 32 | 0x01010101),
34875 tmp2
= force_reg (DImode
, tmp2
);
34876 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
34881 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
34882 target, and SRC is the argument operand. */
34885 rs6000_emit_parity (rtx dst
, rtx src
)
34887 machine_mode mode
= GET_MODE (dst
);
34890 tmp
= gen_reg_rtx (mode
);
34892 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
34895 if (mode
== SImode
)
34897 emit_insn (gen_popcntbsi2 (tmp
, src
));
34898 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
34902 emit_insn (gen_popcntbdi2 (tmp
, src
));
34903 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
34908 if (mode
== SImode
)
34910 /* Is mult+shift >= shift+xor+shift+xor? */
34911 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
34913 rtx tmp1
, tmp2
, tmp3
, tmp4
;
34915 tmp1
= gen_reg_rtx (SImode
);
34916 emit_insn (gen_popcntbsi2 (tmp1
, src
));
34918 tmp2
= gen_reg_rtx (SImode
);
34919 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
34920 tmp3
= gen_reg_rtx (SImode
);
34921 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
34923 tmp4
= gen_reg_rtx (SImode
);
34924 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
34925 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
34928 rs6000_emit_popcount (tmp
, src
);
34929 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
34933 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
34934 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
34936 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
34938 tmp1
= gen_reg_rtx (DImode
);
34939 emit_insn (gen_popcntbdi2 (tmp1
, src
));
34941 tmp2
= gen_reg_rtx (DImode
);
34942 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
34943 tmp3
= gen_reg_rtx (DImode
);
34944 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
34946 tmp4
= gen_reg_rtx (DImode
);
34947 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
34948 tmp5
= gen_reg_rtx (DImode
);
34949 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
34951 tmp6
= gen_reg_rtx (DImode
);
34952 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
34953 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
34956 rs6000_emit_popcount (tmp
, src
);
34957 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
34961 /* Expand an Altivec constant permutation for little endian mode.
34962 OP0 and OP1 are the input vectors and TARGET is the output vector.
34963 SEL specifies the constant permutation vector.
34965 There are two issues: First, the two input operands must be
34966 swapped so that together they form a double-wide array in LE
34967 order. Second, the vperm instruction has surprising behavior
34968 in LE mode: it interprets the elements of the source vectors
34969 in BE mode ("left to right") and interprets the elements of
34970 the destination vector in LE mode ("right to left"). To
34971 correct for this, we must subtract each element of the permute
34972 control vector from 31.
34974 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
34975 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
34976 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
34977 serve as the permute control vector. Then, in BE mode,
34981 places the desired result in vr9. However, in LE mode the
34982 vector contents will be
34984 vr10 = 00000003 00000002 00000001 00000000
34985 vr11 = 00000007 00000006 00000005 00000004
34987 The result of the vperm using the same permute control vector is
34989 vr9 = 05000000 07000000 01000000 03000000
34991 That is, the leftmost 4 bytes of vr10 are interpreted as the
34992 source for the rightmost 4 bytes of vr9, and so on.
34994 If we change the permute control vector to
34996 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35004 vr9 = 00000006 00000004 00000002 00000000. */
35007 altivec_expand_vec_perm_const_le (rtx target
, rtx op0
, rtx op1
,
35008 const vec_perm_indices
&sel
)
35012 rtx constv
, unspec
;
35014 /* Unpack and adjust the constant selector. */
35015 for (i
= 0; i
< 16; ++i
)
35017 unsigned int elt
= 31 - (sel
[i
] & 31);
35018 perm
[i
] = GEN_INT (elt
);
35021 /* Expand to a permute, swapping the inputs and using the
35022 adjusted selector. */
35024 op0
= force_reg (V16QImode
, op0
);
35026 op1
= force_reg (V16QImode
, op1
);
35028 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
35029 constv
= force_reg (V16QImode
, constv
);
35030 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
35032 if (!REG_P (target
))
35034 rtx tmp
= gen_reg_rtx (V16QImode
);
35035 emit_move_insn (tmp
, unspec
);
35039 emit_move_insn (target
, unspec
);
35042 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35043 permute control vector. But here it's not a constant, so we must
35044 generate a vector NAND or NOR to do the adjustment. */
35047 altivec_expand_vec_perm_le (rtx operands
[4])
35049 rtx notx
, iorx
, unspec
;
35050 rtx target
= operands
[0];
35051 rtx op0
= operands
[1];
35052 rtx op1
= operands
[2];
35053 rtx sel
= operands
[3];
35055 rtx norreg
= gen_reg_rtx (V16QImode
);
35056 machine_mode mode
= GET_MODE (target
);
35058 /* Get everything in regs so the pattern matches. */
35060 op0
= force_reg (mode
, op0
);
35062 op1
= force_reg (mode
, op1
);
35064 sel
= force_reg (V16QImode
, sel
);
35065 if (!REG_P (target
))
35066 tmp
= gen_reg_rtx (mode
);
35068 if (TARGET_P9_VECTOR
)
35070 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, sel
),
35075 /* Invert the selector with a VNAND if available, else a VNOR.
35076 The VNAND is preferred for future fusion opportunities. */
35077 notx
= gen_rtx_NOT (V16QImode
, sel
);
35078 iorx
= (TARGET_P8_VECTOR
35079 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
35080 : gen_rtx_AND (V16QImode
, notx
, notx
));
35081 emit_insn (gen_rtx_SET (norreg
, iorx
));
35083 /* Permute with operands reversed and adjusted selector. */
35084 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
35088 /* Copy into target, possibly by way of a register. */
35089 if (!REG_P (target
))
35091 emit_move_insn (tmp
, unspec
);
35095 emit_move_insn (target
, unspec
);
35098 /* Expand an Altivec constant permutation. Return true if we match
35099 an efficient implementation; false to fall back to VPERM.
35101 OP0 and OP1 are the input vectors and TARGET is the output vector.
35102 SEL specifies the constant permutation vector. */
35105 altivec_expand_vec_perm_const (rtx target
, rtx op0
, rtx op1
,
35106 const vec_perm_indices
&sel
)
35108 struct altivec_perm_insn
{
35109 HOST_WIDE_INT mask
;
35110 enum insn_code impl
;
35111 unsigned char perm
[16];
35113 static const struct altivec_perm_insn patterns
[] = {
35114 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
35115 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35116 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
35117 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35118 { OPTION_MASK_ALTIVEC
,
35119 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
35120 : CODE_FOR_altivec_vmrglb_direct
),
35121 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35122 { OPTION_MASK_ALTIVEC
,
35123 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
35124 : CODE_FOR_altivec_vmrglh_direct
),
35125 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35126 { OPTION_MASK_ALTIVEC
,
35127 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
35128 : CODE_FOR_altivec_vmrglw_direct
),
35129 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35130 { OPTION_MASK_ALTIVEC
,
35131 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
35132 : CODE_FOR_altivec_vmrghb_direct
),
35133 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35134 { OPTION_MASK_ALTIVEC
,
35135 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
35136 : CODE_FOR_altivec_vmrghh_direct
),
35137 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35138 { OPTION_MASK_ALTIVEC
,
35139 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
35140 : CODE_FOR_altivec_vmrghw_direct
),
35141 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35142 { OPTION_MASK_P8_VECTOR
,
35143 (BYTES_BIG_ENDIAN
? CODE_FOR_p8_vmrgew_v4sf_direct
35144 : CODE_FOR_p8_vmrgow_v4sf_direct
),
35145 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35146 { OPTION_MASK_P8_VECTOR
,
35147 (BYTES_BIG_ENDIAN
? CODE_FOR_p8_vmrgow_v4sf_direct
35148 : CODE_FOR_p8_vmrgew_v4sf_direct
),
35149 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35152 unsigned int i
, j
, elt
, which
;
35153 unsigned char perm
[16];
35157 /* Unpack the constant selector. */
35158 for (i
= which
= 0; i
< 16; ++i
)
35161 which
|= (elt
< 16 ? 1 : 2);
35165 /* Simplify the constant selector based on operands. */
35169 gcc_unreachable ();
35173 if (!rtx_equal_p (op0
, op1
))
35178 for (i
= 0; i
< 16; ++i
)
35190 /* Look for splat patterns. */
35195 for (i
= 0; i
< 16; ++i
)
35196 if (perm
[i
] != elt
)
35200 if (!BYTES_BIG_ENDIAN
)
35202 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
35208 for (i
= 0; i
< 16; i
+= 2)
35209 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
35213 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
35214 x
= gen_reg_rtx (V8HImode
);
35215 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
35217 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35224 for (i
= 0; i
< 16; i
+= 4)
35226 || perm
[i
+ 1] != elt
+ 1
35227 || perm
[i
+ 2] != elt
+ 2
35228 || perm
[i
+ 3] != elt
+ 3)
35232 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
35233 x
= gen_reg_rtx (V4SImode
);
35234 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
35236 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35242 /* Look for merge and pack patterns. */
35243 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
35247 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
35250 elt
= patterns
[j
].perm
[0];
35251 if (perm
[0] == elt
)
35253 else if (perm
[0] == elt
+ 16)
35257 for (i
= 1; i
< 16; ++i
)
35259 elt
= patterns
[j
].perm
[i
];
35261 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
35262 else if (one_vec
&& elt
>= 16)
35264 if (perm
[i
] != elt
)
35269 enum insn_code icode
= patterns
[j
].impl
;
35270 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
35271 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
35273 /* For little-endian, don't use vpkuwum and vpkuhum if the
35274 underlying vector type is not V4SI and V8HI, respectively.
35275 For example, using vpkuwum with a V8HI picks up the even
35276 halfwords (BE numbering) when the even halfwords (LE
35277 numbering) are what we need. */
35278 if (!BYTES_BIG_ENDIAN
35279 && icode
== CODE_FOR_altivec_vpkuwum_direct
35280 && ((GET_CODE (op0
) == REG
35281 && GET_MODE (op0
) != V4SImode
)
35282 || (GET_CODE (op0
) == SUBREG
35283 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
35285 if (!BYTES_BIG_ENDIAN
35286 && icode
== CODE_FOR_altivec_vpkuhum_direct
35287 && ((GET_CODE (op0
) == REG
35288 && GET_MODE (op0
) != V8HImode
)
35289 || (GET_CODE (op0
) == SUBREG
35290 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
35293 /* For little-endian, the two input operands must be swapped
35294 (or swapped back) to ensure proper right-to-left numbering
35296 if (swapped
^ !BYTES_BIG_ENDIAN
)
35297 std::swap (op0
, op1
);
35298 if (imode
!= V16QImode
)
35300 op0
= gen_lowpart (imode
, op0
);
35301 op1
= gen_lowpart (imode
, op1
);
35303 if (omode
== V16QImode
)
35306 x
= gen_reg_rtx (omode
);
35307 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
35308 if (omode
!= V16QImode
)
35309 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35314 if (!BYTES_BIG_ENDIAN
)
35316 altivec_expand_vec_perm_const_le (target
, op0
, op1
, sel
);
35323 /* Expand a VSX Permute Doubleword constant permutation.
35324 Return true if we match an efficient implementation. */
35327 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
35328 unsigned char perm0
, unsigned char perm1
)
35332 /* If both selectors come from the same operand, fold to single op. */
35333 if ((perm0
& 2) == (perm1
& 2))
35340 /* If both operands are equal, fold to simpler permutation. */
35341 if (rtx_equal_p (op0
, op1
))
35344 perm1
= (perm1
& 1) + 2;
35346 /* If the first selector comes from the second operand, swap. */
35347 else if (perm0
& 2)
35353 std::swap (op0
, op1
);
35355 /* If the second selector does not come from the second operand, fail. */
35356 else if ((perm1
& 2) == 0)
35360 if (target
!= NULL
)
35362 machine_mode vmode
, dmode
;
35365 vmode
= GET_MODE (target
);
35366 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
35367 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4).require ();
35368 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
35369 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
35370 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
35371 emit_insn (gen_rtx_SET (target
, x
));
35376 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35379 rs6000_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
,
35380 rtx op1
, const vec_perm_indices
&sel
)
35382 bool testing_p
= !target
;
35384 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35385 if (TARGET_ALTIVEC
&& testing_p
)
35388 /* Check for ps_merge* or xxpermdi insns. */
35389 if ((vmode
== V2DFmode
|| vmode
== V2DImode
) && VECTOR_MEM_VSX_P (vmode
))
35393 op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
35394 op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
35396 if (rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, sel
[0], sel
[1]))
35400 if (TARGET_ALTIVEC
)
35402 /* Force the target-independent code to lower to V16QImode. */
35403 if (vmode
!= V16QImode
)
35405 if (altivec_expand_vec_perm_const (target
, op0
, op1
, sel
))
35412 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35413 OP0 and OP1 are the input vectors and TARGET is the output vector.
35414 PERM specifies the constant permutation vector. */
35417 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
35418 machine_mode vmode
, const vec_perm_builder
&perm
)
35420 rtx x
= expand_vec_perm_const (vmode
, op0
, op1
, perm
, BLKmode
, target
);
35422 emit_move_insn (target
, x
);
35425 /* Expand an extract even operation. */
35428 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
35430 machine_mode vmode
= GET_MODE (target
);
35431 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
35432 vec_perm_builder
perm (nelt
, nelt
, 1);
35434 for (i
= 0; i
< nelt
; i
++)
35435 perm
.quick_push (i
* 2);
35437 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, perm
);
35440 /* Expand a vector interleave operation. */
35443 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
35445 machine_mode vmode
= GET_MODE (target
);
35446 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
35447 vec_perm_builder
perm (nelt
, nelt
, 1);
35449 high
= (highp
? 0 : nelt
/ 2);
35450 for (i
= 0; i
< nelt
/ 2; i
++)
35452 perm
.quick_push (i
+ high
);
35453 perm
.quick_push (i
+ nelt
+ high
);
35456 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, perm
);
35459 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35461 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
35463 HOST_WIDE_INT
hwi_scale (scale
);
35464 REAL_VALUE_TYPE r_pow
;
35465 rtvec v
= rtvec_alloc (2);
35467 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
35468 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
35469 elt
= const_double_from_real_value (r_pow
, DFmode
);
35470 RTVEC_ELT (v
, 0) = elt
;
35471 RTVEC_ELT (v
, 1) = elt
;
35472 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
35473 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
35476 /* Return an RTX representing where to find the function value of a
35477 function returning MODE. */
35479 rs6000_complex_function_value (machine_mode mode
)
35481 unsigned int regno
;
35483 machine_mode inner
= GET_MODE_INNER (mode
);
35484 unsigned int inner_bytes
= GET_MODE_UNIT_SIZE (mode
);
35486 if (TARGET_FLOAT128_TYPE
35488 || (mode
== TCmode
&& TARGET_IEEEQUAD
)))
35489 regno
= ALTIVEC_ARG_RETURN
;
35491 else if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35492 regno
= FP_ARG_RETURN
;
35496 regno
= GP_ARG_RETURN
;
35498 /* 32-bit is OK since it'll go in r3/r4. */
35499 if (TARGET_32BIT
&& inner_bytes
>= 4)
35500 return gen_rtx_REG (mode
, regno
);
35503 if (inner_bytes
>= 8)
35504 return gen_rtx_REG (mode
, regno
);
35506 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
35508 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
35509 GEN_INT (inner_bytes
));
35510 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
35513 /* Return an rtx describing a return value of MODE as a PARALLEL
35514 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35515 stride REG_STRIDE. */
35518 rs6000_parallel_return (machine_mode mode
,
35519 int n_elts
, machine_mode elt_mode
,
35520 unsigned int regno
, unsigned int reg_stride
)
35522 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
35525 for (i
= 0; i
< n_elts
; i
++)
35527 rtx r
= gen_rtx_REG (elt_mode
, regno
);
35528 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
35529 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
35530 regno
+= reg_stride
;
35536 /* Target hook for TARGET_FUNCTION_VALUE.
35538 An integer value is in r3 and a floating-point value is in fp1,
35539 unless -msoft-float. */
35542 rs6000_function_value (const_tree valtype
,
35543 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
35544 bool outgoing ATTRIBUTE_UNUSED
)
35547 unsigned int regno
;
35548 machine_mode elt_mode
;
35551 /* Special handling for structs in darwin64. */
35553 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
35555 CUMULATIVE_ARGS valcum
;
35559 valcum
.fregno
= FP_ARG_MIN_REG
;
35560 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
35561 /* Do a trial code generation as if this were going to be passed as
35562 an argument; if any part goes in memory, we return NULL. */
35563 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
35566 /* Otherwise fall through to standard ABI rules. */
35569 mode
= TYPE_MODE (valtype
);
35571 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35572 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
35574 int first_reg
, n_regs
;
35576 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode
))
35578 /* _Decimal128 must use even/odd register pairs. */
35579 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35580 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
35584 first_reg
= ALTIVEC_ARG_RETURN
;
35588 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
35591 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35592 if (TARGET_32BIT
&& TARGET_POWERPC64
)
35601 int count
= GET_MODE_SIZE (mode
) / 4;
35602 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
35605 if ((INTEGRAL_TYPE_P (valtype
)
35606 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
35607 || POINTER_TYPE_P (valtype
))
35608 mode
= TARGET_32BIT
? SImode
: DImode
;
35610 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35611 /* _Decimal128 must use an even/odd register pair. */
35612 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35613 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
35614 && !FLOAT128_VECTOR_P (mode
))
35615 regno
= FP_ARG_RETURN
;
35616 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
35617 && targetm
.calls
.split_complex_arg
)
35618 return rs6000_complex_function_value (mode
);
35619 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35620 return register is used in both cases, and we won't see V2DImode/V2DFmode
35621 for pure altivec, combine the two cases. */
35622 else if ((TREE_CODE (valtype
) == VECTOR_TYPE
|| FLOAT128_VECTOR_P (mode
))
35623 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
35624 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
35625 regno
= ALTIVEC_ARG_RETURN
;
35627 regno
= GP_ARG_RETURN
;
35629 return gen_rtx_REG (mode
, regno
);
35632 /* Define how to find the value returned by a library function
35633 assuming the value has mode MODE. */
35635 rs6000_libcall_value (machine_mode mode
)
35637 unsigned int regno
;
35639 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35640 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
35641 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
35643 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35644 /* _Decimal128 must use an even/odd register pair. */
35645 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
35646 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && TARGET_HARD_FLOAT
)
35647 regno
= FP_ARG_RETURN
;
35648 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35649 return register is used in both cases, and we won't see V2DImode/V2DFmode
35650 for pure altivec, combine the two cases. */
35651 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
35652 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
35653 regno
= ALTIVEC_ARG_RETURN
;
35654 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
35655 return rs6000_complex_function_value (mode
);
35657 regno
= GP_ARG_RETURN
;
35659 return gen_rtx_REG (mode
, regno
);
35662 /* Compute register pressure classes. We implement the target hook to avoid
35663 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
35664 lead to incorrect estimates of number of available registers and therefor
35665 increased register pressure/spill. */
35667 rs6000_compute_pressure_classes (enum reg_class
*pressure_classes
)
35672 pressure_classes
[n
++] = GENERAL_REGS
;
35674 pressure_classes
[n
++] = VSX_REGS
;
35677 if (TARGET_ALTIVEC
)
35678 pressure_classes
[n
++] = ALTIVEC_REGS
;
35679 if (TARGET_HARD_FLOAT
)
35680 pressure_classes
[n
++] = FLOAT_REGS
;
35682 pressure_classes
[n
++] = CR_REGS
;
35683 pressure_classes
[n
++] = SPECIAL_REGS
;
35688 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35689 Frame pointer elimination is automatically handled.
35691 For the RS/6000, if frame pointer elimination is being done, we would like
35692 to convert ap into fp, not sp.
35694 We need r30 if -mminimal-toc was specified, and there are constant pool
35698 rs6000_can_eliminate (const int from
, const int to
)
35700 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
35701 ? ! frame_pointer_needed
35702 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
35703 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
35704 || constant_pool_empty_p ()
35708 /* Define the offset between two registers, FROM to be eliminated and its
35709 replacement TO, at the start of a routine. */
35711 rs6000_initial_elimination_offset (int from
, int to
)
35713 rs6000_stack_t
*info
= rs6000_stack_info ();
35714 HOST_WIDE_INT offset
;
35716 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
35717 offset
= info
->push_p
? 0 : -info
->total_size
;
35718 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
35720 offset
= info
->push_p
? 0 : -info
->total_size
;
35721 if (FRAME_GROWS_DOWNWARD
)
35722 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
35724 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
35725 offset
= FRAME_GROWS_DOWNWARD
35726 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
35728 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
35729 offset
= info
->total_size
;
35730 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
35731 offset
= info
->push_p
? info
->total_size
: 0;
35732 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
35735 gcc_unreachable ();
35740 /* Fill in sizes of registers used by unwinder. */
35743 rs6000_init_dwarf_reg_sizes_extra (tree address
)
35745 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
35748 machine_mode mode
= TYPE_MODE (char_type_node
);
35749 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
35750 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
35751 rtx value
= gen_int_mode (16, mode
);
35753 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35754 The unwinder still needs to know the size of Altivec registers. */
35756 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
35758 int column
= DWARF_REG_TO_UNWIND_COLUMN
35759 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
35760 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
35762 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
35767 /* Map internal gcc register numbers to debug format register numbers.
35768 FORMAT specifies the type of debug register number to use:
35769 0 -- debug information, except for frame-related sections
35770 1 -- DWARF .debug_frame section
35771 2 -- DWARF .eh_frame section */
35774 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
35776 /* Except for the above, we use the internal number for non-DWARF
35777 debug information, and also for .eh_frame. */
35778 if ((format
== 0 && write_symbols
!= DWARF2_DEBUG
) || format
== 2)
35781 /* On some platforms, we use the standard DWARF register
35782 numbering for .debug_info and .debug_frame. */
35783 #ifdef RS6000_USE_DWARF_NUMBERING
35786 if (regno
== LR_REGNO
)
35788 if (regno
== CTR_REGNO
)
35790 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
35791 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
35792 The actual code emitted saves the whole of CR, so we map CR2_REGNO
35793 to the DWARF reg for CR. */
35794 if (format
== 1 && regno
== CR2_REGNO
)
35796 if (CR_REGNO_P (regno
))
35797 return regno
- CR0_REGNO
+ 86;
35798 if (regno
== CA_REGNO
)
35799 return 101; /* XER */
35800 if (ALTIVEC_REGNO_P (regno
))
35801 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
35802 if (regno
== VRSAVE_REGNO
)
35804 if (regno
== VSCR_REGNO
)
35810 /* target hook eh_return_filter_mode */
35811 static scalar_int_mode
35812 rs6000_eh_return_filter_mode (void)
35814 return TARGET_32BIT
? SImode
: word_mode
;
35817 /* Target hook for translate_mode_attribute. */
35818 static machine_mode
35819 rs6000_translate_mode_attribute (machine_mode mode
)
35821 if ((FLOAT128_IEEE_P (mode
)
35822 && ieee128_float_type_node
== long_double_type_node
)
35823 || (FLOAT128_IBM_P (mode
)
35824 && ibm128_float_type_node
== long_double_type_node
))
35825 return COMPLEX_MODE_P (mode
) ? E_TCmode
: E_TFmode
;
35829 /* Target hook for scalar_mode_supported_p. */
35831 rs6000_scalar_mode_supported_p (scalar_mode mode
)
35833 /* -m32 does not support TImode. This is the default, from
35834 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
35835 same ABI as for -m32. But default_scalar_mode_supported_p allows
35836 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
35837 for -mpowerpc64. */
35838 if (TARGET_32BIT
&& mode
== TImode
)
35841 if (DECIMAL_FLOAT_MODE_P (mode
))
35842 return default_decimal_float_supported_p ();
35843 else if (TARGET_FLOAT128_TYPE
&& (mode
== KFmode
|| mode
== IFmode
))
35846 return default_scalar_mode_supported_p (mode
);
35849 /* Target hook for vector_mode_supported_p. */
35851 rs6000_vector_mode_supported_p (machine_mode mode
)
35853 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
35854 128-bit, the compiler might try to widen IEEE 128-bit to IBM
35856 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
) && !FLOAT128_IEEE_P (mode
))
35863 /* Target hook for floatn_mode. */
35864 static opt_scalar_float_mode
35865 rs6000_floatn_mode (int n
, bool extended
)
35875 if (TARGET_FLOAT128_TYPE
)
35876 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
35878 return opt_scalar_float_mode ();
35881 return opt_scalar_float_mode ();
35884 /* Those are the only valid _FloatNx types. */
35885 gcc_unreachable ();
35899 if (TARGET_FLOAT128_TYPE
)
35900 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
35902 return opt_scalar_float_mode ();
35905 return opt_scalar_float_mode ();
35911 /* Target hook for c_mode_for_suffix. */
35912 static machine_mode
35913 rs6000_c_mode_for_suffix (char suffix
)
35915 if (TARGET_FLOAT128_TYPE
)
35917 if (suffix
== 'q' || suffix
== 'Q')
35918 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
35920 /* At the moment, we are not defining a suffix for IBM extended double.
35921 If/when the default for -mabi=ieeelongdouble is changed, and we want
35922 to support __ibm128 constants in legacy library code, we may need to
35923 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
35924 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
35925 __float80 constants. */
35931 /* Target hook for invalid_arg_for_unprototyped_fn. */
35932 static const char *
35933 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
35935 return (!rs6000_darwin64_abi
35937 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
35938 && (funcdecl
== NULL_TREE
35939 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
35940 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
35941 ? N_("AltiVec argument passed to unprototyped function")
35945 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
35946 setup by using __stack_chk_fail_local hidden function instead of
35947 calling __stack_chk_fail directly. Otherwise it is better to call
35948 __stack_chk_fail directly. */
35950 static tree ATTRIBUTE_UNUSED
35951 rs6000_stack_protect_fail (void)
35953 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
35954 ? default_hidden_stack_protect_fail ()
35955 : default_external_stack_protect_fail ();
35958 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
35961 static unsigned HOST_WIDE_INT
35962 rs6000_asan_shadow_offset (void)
35964 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
35968 /* Mask options that we want to support inside of attribute((target)) and
35969 #pragma GCC target operations. Note, we do not include things like
35970 64/32-bit, endianness, hard/soft floating point, etc. that would have
35971 different calling sequences. */
35973 struct rs6000_opt_mask
{
35974 const char *name
; /* option name */
35975 HOST_WIDE_INT mask
; /* mask to set */
35976 bool invert
; /* invert sense of mask */
35977 bool valid_target
; /* option is a target option */
35980 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
35982 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
35983 { "cmpb", OPTION_MASK_CMPB
, false, true },
35984 { "crypto", OPTION_MASK_CRYPTO
, false, true },
35985 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
35986 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
35987 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX
,
35989 { "float128", OPTION_MASK_FLOAT128_KEYWORD
, false, true },
35990 { "float128-hardware", OPTION_MASK_FLOAT128_HW
, false, true },
35991 { "fprnd", OPTION_MASK_FPRND
, false, true },
35992 { "hard-dfp", OPTION_MASK_DFP
, false, true },
35993 { "htm", OPTION_MASK_HTM
, false, true },
35994 { "isel", OPTION_MASK_ISEL
, false, true },
35995 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
35996 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
35997 { "modulo", OPTION_MASK_MODULO
, false, true },
35998 { "mulhw", OPTION_MASK_MULHW
, false, true },
35999 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
36000 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
36001 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
36002 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
36003 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
36004 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
36005 { "power9-fusion", OPTION_MASK_P9_FUSION
, false, true },
36006 { "power9-minmax", OPTION_MASK_P9_MINMAX
, false, true },
36007 { "power9-misc", OPTION_MASK_P9_MISC
, false, true },
36008 { "power9-vector", OPTION_MASK_P9_VECTOR
, false, true },
36009 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
36010 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
36011 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
36012 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
36013 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
36014 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
36015 { "string", 0, false, true },
36016 { "update", OPTION_MASK_NO_UPDATE
, true , true },
36017 { "vsx", OPTION_MASK_VSX
, false, true },
36018 #ifdef OPTION_MASK_64BIT
36020 { "aix64", OPTION_MASK_64BIT
, false, false },
36021 { "aix32", OPTION_MASK_64BIT
, true, false },
36023 { "64", OPTION_MASK_64BIT
, false, false },
36024 { "32", OPTION_MASK_64BIT
, true, false },
36027 #ifdef OPTION_MASK_EABI
36028 { "eabi", OPTION_MASK_EABI
, false, false },
36030 #ifdef OPTION_MASK_LITTLE_ENDIAN
36031 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
36032 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
36034 #ifdef OPTION_MASK_RELOCATABLE
36035 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
36037 #ifdef OPTION_MASK_STRICT_ALIGN
36038 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
36040 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
36041 { "string", 0, false, false },
36044 /* Builtin mask mapping for printing the flags. */
36045 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
36047 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
36048 { "vsx", RS6000_BTM_VSX
, false, false },
36049 { "fre", RS6000_BTM_FRE
, false, false },
36050 { "fres", RS6000_BTM_FRES
, false, false },
36051 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
36052 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
36053 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
36054 { "cell", RS6000_BTM_CELL
, false, false },
36055 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
36056 { "power9-vector", RS6000_BTM_P9_VECTOR
, false, false },
36057 { "power9-misc", RS6000_BTM_P9_MISC
, false, false },
36058 { "crypto", RS6000_BTM_CRYPTO
, false, false },
36059 { "htm", RS6000_BTM_HTM
, false, false },
36060 { "hard-dfp", RS6000_BTM_DFP
, false, false },
36061 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
36062 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
36063 { "powerpc64", RS6000_BTM_POWERPC64
, false, false },
36064 { "float128", RS6000_BTM_FLOAT128
, false, false },
36065 { "float128-hw", RS6000_BTM_FLOAT128_HW
,false, false },
36068 /* Option variables that we want to support inside attribute((target)) and
36069 #pragma GCC target operations. */
36071 struct rs6000_opt_var
{
36072 const char *name
; /* option name */
36073 size_t global_offset
; /* offset of the option in global_options. */
36074 size_t target_offset
; /* offset of the option in target options. */
36077 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
36080 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
36081 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
36082 { "avoid-indexed-addresses",
36083 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
36084 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
36086 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
36087 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
36088 { "optimize-swaps",
36089 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
36090 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
36091 { "allow-movmisalign",
36092 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
36093 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
36095 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
36096 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
36098 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
36099 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
36100 { "align-branch-targets",
36101 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
36102 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
36104 offsetof (struct gcc_options
, x_tls_markers
),
36105 offsetof (struct cl_target_option
, x_tls_markers
), },
36107 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36108 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36110 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36111 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36112 { "speculate-indirect-jumps",
36113 offsetof (struct gcc_options
, x_rs6000_speculate_indirect_jumps
),
36114 offsetof (struct cl_target_option
, x_rs6000_speculate_indirect_jumps
), },
36117 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36118 parsing. Return true if there were no errors. */
36121 rs6000_inner_target_options (tree args
, bool attr_p
)
36125 if (args
== NULL_TREE
)
36128 else if (TREE_CODE (args
) == STRING_CST
)
36130 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36133 while ((q
= strtok (p
, ",")) != NULL
)
36135 bool error_p
= false;
36136 bool not_valid_p
= false;
36137 const char *cpu_opt
= NULL
;
36140 if (strncmp (q
, "cpu=", 4) == 0)
36142 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
36143 if (cpu_index
>= 0)
36144 rs6000_cpu_index
= cpu_index
;
36151 else if (strncmp (q
, "tune=", 5) == 0)
36153 int tune_index
= rs6000_cpu_name_lookup (q
+5);
36154 if (tune_index
>= 0)
36155 rs6000_tune_index
= tune_index
;
36165 bool invert
= false;
36169 if (strncmp (r
, "no-", 3) == 0)
36175 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
36176 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
36178 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
36180 if (!rs6000_opt_masks
[i
].valid_target
)
36181 not_valid_p
= true;
36185 rs6000_isa_flags_explicit
|= mask
;
36187 /* VSX needs altivec, so -mvsx automagically sets
36188 altivec and disables -mavoid-indexed-addresses. */
36191 if (mask
== OPTION_MASK_VSX
)
36193 mask
|= OPTION_MASK_ALTIVEC
;
36194 TARGET_AVOID_XFORM
= 0;
36198 if (rs6000_opt_masks
[i
].invert
)
36202 rs6000_isa_flags
&= ~mask
;
36204 rs6000_isa_flags
|= mask
;
36209 if (error_p
&& !not_valid_p
)
36211 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
36212 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
36214 size_t j
= rs6000_opt_vars
[i
].global_offset
;
36215 *((int *) ((char *)&global_options
+ j
)) = !invert
;
36217 not_valid_p
= false;
36225 const char *eprefix
, *esuffix
;
36230 eprefix
= "__attribute__((__target__(";
36235 eprefix
= "#pragma GCC target ";
36240 error ("invalid cpu %qs for %s%qs%s", cpu_opt
, eprefix
,
36242 else if (not_valid_p
)
36243 error ("%s%qs%s is not allowed", eprefix
, q
, esuffix
);
36245 error ("%s%qs%s is invalid", eprefix
, q
, esuffix
);
36250 else if (TREE_CODE (args
) == TREE_LIST
)
36254 tree value
= TREE_VALUE (args
);
36257 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
36261 args
= TREE_CHAIN (args
);
36263 while (args
!= NULL_TREE
);
36268 error ("attribute %<target%> argument not a string");
36275 /* Print out the target options as a list for -mdebug=target. */
36278 rs6000_debug_target_options (tree args
, const char *prefix
)
36280 if (args
== NULL_TREE
)
36281 fprintf (stderr
, "%s<NULL>", prefix
);
36283 else if (TREE_CODE (args
) == STRING_CST
)
36285 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36288 while ((q
= strtok (p
, ",")) != NULL
)
36291 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
36296 else if (TREE_CODE (args
) == TREE_LIST
)
36300 tree value
= TREE_VALUE (args
);
36303 rs6000_debug_target_options (value
, prefix
);
36306 args
= TREE_CHAIN (args
);
36308 while (args
!= NULL_TREE
);
36312 gcc_unreachable ();
36318 /* Hook to validate attribute((target("..."))). */
36321 rs6000_valid_attribute_p (tree fndecl
,
36322 tree
ARG_UNUSED (name
),
36326 struct cl_target_option cur_target
;
36329 tree new_target
, new_optimize
;
36330 tree func_optimize
;
36332 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
36334 if (TARGET_DEBUG_TARGET
)
36336 tree tname
= DECL_NAME (fndecl
);
36337 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
36339 fprintf (stderr
, "function: %.*s\n",
36340 (int) IDENTIFIER_LENGTH (tname
),
36341 IDENTIFIER_POINTER (tname
));
36343 fprintf (stderr
, "function: unknown\n");
36345 fprintf (stderr
, "args:");
36346 rs6000_debug_target_options (args
, " ");
36347 fprintf (stderr
, "\n");
36350 fprintf (stderr
, "flags: 0x%x\n", flags
);
36352 fprintf (stderr
, "--------------------\n");
36355 /* attribute((target("default"))) does nothing, beyond
36356 affecting multi-versioning. */
36357 if (TREE_VALUE (args
)
36358 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
36359 && TREE_CHAIN (args
) == NULL_TREE
36360 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args
)), "default") == 0)
36363 old_optimize
= build_optimization_node (&global_options
);
36364 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
36366 /* If the function changed the optimization levels as well as setting target
36367 options, start with the optimizations specified. */
36368 if (func_optimize
&& func_optimize
!= old_optimize
)
36369 cl_optimization_restore (&global_options
,
36370 TREE_OPTIMIZATION (func_optimize
));
36372 /* The target attributes may also change some optimization flags, so update
36373 the optimization options if necessary. */
36374 cl_target_option_save (&cur_target
, &global_options
);
36375 rs6000_cpu_index
= rs6000_tune_index
= -1;
36376 ret
= rs6000_inner_target_options (args
, true);
36378 /* Set up any additional state. */
36381 ret
= rs6000_option_override_internal (false);
36382 new_target
= build_target_option_node (&global_options
);
36387 new_optimize
= build_optimization_node (&global_options
);
36394 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
36396 if (old_optimize
!= new_optimize
)
36397 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
36400 cl_target_option_restore (&global_options
, &cur_target
);
36402 if (old_optimize
!= new_optimize
)
36403 cl_optimization_restore (&global_options
,
36404 TREE_OPTIMIZATION (old_optimize
));
36410 /* Hook to validate the current #pragma GCC target and set the state, and
36411 update the macros based on what was changed. If ARGS is NULL, then
36412 POP_TARGET is used to reset the options. */
36415 rs6000_pragma_target_parse (tree args
, tree pop_target
)
36417 tree prev_tree
= build_target_option_node (&global_options
);
36419 struct cl_target_option
*prev_opt
, *cur_opt
;
36420 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
36421 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
36423 if (TARGET_DEBUG_TARGET
)
36425 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
36426 fprintf (stderr
, "args:");
36427 rs6000_debug_target_options (args
, " ");
36428 fprintf (stderr
, "\n");
36432 fprintf (stderr
, "pop_target:\n");
36433 debug_tree (pop_target
);
36436 fprintf (stderr
, "pop_target: <NULL>\n");
36438 fprintf (stderr
, "--------------------\n");
36443 cur_tree
= ((pop_target
)
36445 : target_option_default_node
);
36446 cl_target_option_restore (&global_options
,
36447 TREE_TARGET_OPTION (cur_tree
));
36451 rs6000_cpu_index
= rs6000_tune_index
= -1;
36452 if (!rs6000_inner_target_options (args
, false)
36453 || !rs6000_option_override_internal (false)
36454 || (cur_tree
= build_target_option_node (&global_options
))
36457 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
36458 fprintf (stderr
, "invalid pragma\n");
36464 target_option_current_node
= cur_tree
;
36465 rs6000_activate_target_options (target_option_current_node
);
36467 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36468 change the macros that are defined. */
36469 if (rs6000_target_modify_macros_ptr
)
36471 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
36472 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
36473 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
36475 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
36476 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
36477 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
36479 diff_bumask
= (prev_bumask
^ cur_bumask
);
36480 diff_flags
= (prev_flags
^ cur_flags
);
36482 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
36484 /* Delete old macros. */
36485 rs6000_target_modify_macros_ptr (false,
36486 prev_flags
& diff_flags
,
36487 prev_bumask
& diff_bumask
);
36489 /* Define new macros. */
36490 rs6000_target_modify_macros_ptr (true,
36491 cur_flags
& diff_flags
,
36492 cur_bumask
& diff_bumask
);
36500 /* Remember the last target of rs6000_set_current_function. */
36501 static GTY(()) tree rs6000_previous_fndecl
;
36503 /* Restore target's globals from NEW_TREE and invalidate the
36504 rs6000_previous_fndecl cache. */
36507 rs6000_activate_target_options (tree new_tree
)
36509 cl_target_option_restore (&global_options
, TREE_TARGET_OPTION (new_tree
));
36510 if (TREE_TARGET_GLOBALS (new_tree
))
36511 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
36512 else if (new_tree
== target_option_default_node
)
36513 restore_target_globals (&default_target_globals
);
36515 TREE_TARGET_GLOBALS (new_tree
) = save_target_globals_default_opts ();
36516 rs6000_previous_fndecl
= NULL_TREE
;
36519 /* Establish appropriate back-end context for processing the function
36520 FNDECL. The argument might be NULL to indicate processing at top
36521 level, outside of any function scope. */
36523 rs6000_set_current_function (tree fndecl
)
36525 if (TARGET_DEBUG_TARGET
)
36527 fprintf (stderr
, "\n==================== rs6000_set_current_function");
36530 fprintf (stderr
, ", fndecl %s (%p)",
36531 (DECL_NAME (fndecl
)
36532 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
36533 : "<unknown>"), (void *)fndecl
);
36535 if (rs6000_previous_fndecl
)
36536 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
36538 fprintf (stderr
, "\n");
36541 /* Only change the context if the function changes. This hook is called
36542 several times in the course of compiling a function, and we don't want to
36543 slow things down too much or call target_reinit when it isn't safe. */
36544 if (fndecl
== rs6000_previous_fndecl
)
36548 if (rs6000_previous_fndecl
== NULL_TREE
)
36549 old_tree
= target_option_current_node
;
36550 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
))
36551 old_tree
= DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
);
36553 old_tree
= target_option_default_node
;
36556 if (fndecl
== NULL_TREE
)
36558 if (old_tree
!= target_option_current_node
)
36559 new_tree
= target_option_current_node
;
36561 new_tree
= NULL_TREE
;
36565 new_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
36566 if (new_tree
== NULL_TREE
)
36567 new_tree
= target_option_default_node
;
36570 if (TARGET_DEBUG_TARGET
)
36574 fprintf (stderr
, "\nnew fndecl target specific options:\n");
36575 debug_tree (new_tree
);
36580 fprintf (stderr
, "\nold fndecl target specific options:\n");
36581 debug_tree (old_tree
);
36584 if (old_tree
!= NULL_TREE
|| new_tree
!= NULL_TREE
)
36585 fprintf (stderr
, "--------------------\n");
36588 if (new_tree
&& old_tree
!= new_tree
)
36589 rs6000_activate_target_options (new_tree
);
36592 rs6000_previous_fndecl
= fndecl
;
36596 /* Save the current options */
36599 rs6000_function_specific_save (struct cl_target_option
*ptr
,
36600 struct gcc_options
*opts
)
36602 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
36603 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
36606 /* Restore the current options */
36609 rs6000_function_specific_restore (struct gcc_options
*opts
,
36610 struct cl_target_option
*ptr
)
36613 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
36614 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
36615 (void) rs6000_option_override_internal (false);
36618 /* Print the current options */
36621 rs6000_function_specific_print (FILE *file
, int indent
,
36622 struct cl_target_option
*ptr
)
36624 rs6000_print_isa_options (file
, indent
, "Isa options set",
36625 ptr
->x_rs6000_isa_flags
);
36627 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
36628 ptr
->x_rs6000_isa_flags_explicit
);
36631 /* Helper function to print the current isa or misc options on a line. */
36634 rs6000_print_options_internal (FILE *file
,
36636 const char *string
,
36637 HOST_WIDE_INT flags
,
36638 const char *prefix
,
36639 const struct rs6000_opt_mask
*opts
,
36640 size_t num_elements
)
36643 size_t start_column
= 0;
36645 size_t max_column
= 120;
36646 size_t prefix_len
= strlen (prefix
);
36647 size_t comma_len
= 0;
36648 const char *comma
= "";
36651 start_column
+= fprintf (file
, "%*s", indent
, "");
36655 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
36659 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
36661 /* Print the various mask options. */
36662 cur_column
= start_column
;
36663 for (i
= 0; i
< num_elements
; i
++)
36665 bool invert
= opts
[i
].invert
;
36666 const char *name
= opts
[i
].name
;
36667 const char *no_str
= "";
36668 HOST_WIDE_INT mask
= opts
[i
].mask
;
36669 size_t len
= comma_len
+ prefix_len
+ strlen (name
);
36673 if ((flags
& mask
) == 0)
36676 len
+= sizeof ("no-") - 1;
36684 if ((flags
& mask
) != 0)
36687 len
+= sizeof ("no-") - 1;
36694 if (cur_column
> max_column
)
36696 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
36697 cur_column
= start_column
+ len
;
36701 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
, name
);
36703 comma_len
= sizeof (", ") - 1;
36706 fputs ("\n", file
);
36709 /* Helper function to print the current isa options on a line. */
36712 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
36713 HOST_WIDE_INT flags
)
36715 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
36716 &rs6000_opt_masks
[0],
36717 ARRAY_SIZE (rs6000_opt_masks
));
36721 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
36722 HOST_WIDE_INT flags
)
36724 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
36725 &rs6000_builtin_mask_names
[0],
36726 ARRAY_SIZE (rs6000_builtin_mask_names
));
36729 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36730 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36731 -mupper-regs-df, etc.).
36733 If the user used -mno-power8-vector, we need to turn off all of the implicit
36734 ISA 2.07 and 3.0 options that relate to the vector unit.
36736 If the user used -mno-power9-vector, we need to turn off all of the implicit
36737 ISA 3.0 options that relate to the vector unit.
36739 This function does not handle explicit options such as the user specifying
36740 -mdirect-move. These are handled in rs6000_option_override_internal, and
36741 the appropriate error is given if needed.
36743 We return a mask of all of the implicit options that should not be enabled
36746 static HOST_WIDE_INT
36747 rs6000_disable_incompatible_switches (void)
36749 HOST_WIDE_INT ignore_masks
= rs6000_isa_flags_explicit
;
36752 static const struct {
36753 const HOST_WIDE_INT no_flag
; /* flag explicitly turned off. */
36754 const HOST_WIDE_INT dep_flags
; /* flags that depend on this option. */
36755 const char *const name
; /* name of the switch. */
36757 { OPTION_MASK_P9_VECTOR
, OTHER_P9_VECTOR_MASKS
, "power9-vector" },
36758 { OPTION_MASK_P8_VECTOR
, OTHER_P8_VECTOR_MASKS
, "power8-vector" },
36759 { OPTION_MASK_VSX
, OTHER_VSX_VECTOR_MASKS
, "vsx" },
36762 for (i
= 0; i
< ARRAY_SIZE (flags
); i
++)
36764 HOST_WIDE_INT no_flag
= flags
[i
].no_flag
;
36766 if ((rs6000_isa_flags
& no_flag
) == 0
36767 && (rs6000_isa_flags_explicit
& no_flag
) != 0)
36769 HOST_WIDE_INT dep_flags
= flags
[i
].dep_flags
;
36770 HOST_WIDE_INT set_flags
= (rs6000_isa_flags_explicit
36776 for (j
= 0; j
< ARRAY_SIZE (rs6000_opt_masks
); j
++)
36777 if ((set_flags
& rs6000_opt_masks
[j
].mask
) != 0)
36779 set_flags
&= ~rs6000_opt_masks
[j
].mask
;
36780 error ("%<-mno-%s%> turns off %<-m%s%>",
36782 rs6000_opt_masks
[j
].name
);
36785 gcc_assert (!set_flags
);
36788 rs6000_isa_flags
&= ~dep_flags
;
36789 ignore_masks
|= no_flag
| dep_flags
;
36793 return ignore_masks
;
36797 /* Helper function for printing the function name when debugging. */
36799 static const char *
36800 get_decl_name (tree fn
)
36807 name
= DECL_NAME (fn
);
36809 return "<no-name>";
36811 return IDENTIFIER_POINTER (name
);
36814 /* Return the clone id of the target we are compiling code for in a target
36815 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
36816 the priority list for the target clones (ordered from lowest to
36820 rs6000_clone_priority (tree fndecl
)
36822 tree fn_opts
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
36823 HOST_WIDE_INT isa_masks
;
36824 int ret
= CLONE_DEFAULT
;
36825 tree attrs
= lookup_attribute ("target", DECL_ATTRIBUTES (fndecl
));
36826 const char *attrs_str
= NULL
;
36828 attrs
= TREE_VALUE (TREE_VALUE (attrs
));
36829 attrs_str
= TREE_STRING_POINTER (attrs
);
36831 /* Return priority zero for default function. Return the ISA needed for the
36832 function if it is not the default. */
36833 if (strcmp (attrs_str
, "default") != 0)
36835 if (fn_opts
== NULL_TREE
)
36836 fn_opts
= target_option_default_node
;
36838 if (!fn_opts
|| !TREE_TARGET_OPTION (fn_opts
))
36839 isa_masks
= rs6000_isa_flags
;
36841 isa_masks
= TREE_TARGET_OPTION (fn_opts
)->x_rs6000_isa_flags
;
36843 for (ret
= CLONE_MAX
- 1; ret
!= 0; ret
--)
36844 if ((rs6000_clone_map
[ret
].isa_mask
& isa_masks
) != 0)
36848 if (TARGET_DEBUG_TARGET
)
36849 fprintf (stderr
, "rs6000_get_function_version_priority (%s) => %d\n",
36850 get_decl_name (fndecl
), ret
);
36855 /* This compares the priority of target features in function DECL1 and DECL2.
36856 It returns positive value if DECL1 is higher priority, negative value if
36857 DECL2 is higher priority and 0 if they are the same. Note, priorities are
36858 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
36861 rs6000_compare_version_priority (tree decl1
, tree decl2
)
36863 int priority1
= rs6000_clone_priority (decl1
);
36864 int priority2
= rs6000_clone_priority (decl2
);
36865 int ret
= priority1
- priority2
;
36867 if (TARGET_DEBUG_TARGET
)
36868 fprintf (stderr
, "rs6000_compare_version_priority (%s, %s) => %d\n",
36869 get_decl_name (decl1
), get_decl_name (decl2
), ret
);
36874 /* Make a dispatcher declaration for the multi-versioned function DECL.
36875 Calls to DECL function will be replaced with calls to the dispatcher
36876 by the front-end. Returns the decl of the dispatcher function. */
36879 rs6000_get_function_versions_dispatcher (void *decl
)
36881 tree fn
= (tree
) decl
;
36882 struct cgraph_node
*node
= NULL
;
36883 struct cgraph_node
*default_node
= NULL
;
36884 struct cgraph_function_version_info
*node_v
= NULL
;
36885 struct cgraph_function_version_info
*first_v
= NULL
;
36887 tree dispatch_decl
= NULL
;
36889 struct cgraph_function_version_info
*default_version_info
= NULL
;
36890 gcc_assert (fn
!= NULL
&& DECL_FUNCTION_VERSIONED (fn
));
36892 if (TARGET_DEBUG_TARGET
)
36893 fprintf (stderr
, "rs6000_get_function_versions_dispatcher (%s)\n",
36894 get_decl_name (fn
));
36896 node
= cgraph_node::get (fn
);
36897 gcc_assert (node
!= NULL
);
36899 node_v
= node
->function_version ();
36900 gcc_assert (node_v
!= NULL
);
36902 if (node_v
->dispatcher_resolver
!= NULL
)
36903 return node_v
->dispatcher_resolver
;
36905 /* Find the default version and make it the first node. */
36907 /* Go to the beginning of the chain. */
36908 while (first_v
->prev
!= NULL
)
36909 first_v
= first_v
->prev
;
36911 default_version_info
= first_v
;
36912 while (default_version_info
!= NULL
)
36914 const tree decl2
= default_version_info
->this_node
->decl
;
36915 if (is_function_default_version (decl2
))
36917 default_version_info
= default_version_info
->next
;
36920 /* If there is no default node, just return NULL. */
36921 if (default_version_info
== NULL
)
36924 /* Make default info the first node. */
36925 if (first_v
!= default_version_info
)
36927 default_version_info
->prev
->next
= default_version_info
->next
;
36928 if (default_version_info
->next
)
36929 default_version_info
->next
->prev
= default_version_info
->prev
;
36930 first_v
->prev
= default_version_info
;
36931 default_version_info
->next
= first_v
;
36932 default_version_info
->prev
= NULL
;
36935 default_node
= default_version_info
->this_node
;
36937 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
36938 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
36939 "target_clones attribute needs GLIBC (2.23 and newer) that "
36940 "exports hardware capability bits");
36943 if (targetm
.has_ifunc_p ())
36945 struct cgraph_function_version_info
*it_v
= NULL
;
36946 struct cgraph_node
*dispatcher_node
= NULL
;
36947 struct cgraph_function_version_info
*dispatcher_version_info
= NULL
;
36949 /* Right now, the dispatching is done via ifunc. */
36950 dispatch_decl
= make_dispatcher_decl (default_node
->decl
);
36952 dispatcher_node
= cgraph_node::get_create (dispatch_decl
);
36953 gcc_assert (dispatcher_node
!= NULL
);
36954 dispatcher_node
->dispatcher_function
= 1;
36955 dispatcher_version_info
36956 = dispatcher_node
->insert_new_function_version ();
36957 dispatcher_version_info
->next
= default_version_info
;
36958 dispatcher_node
->definition
= 1;
36960 /* Set the dispatcher for all the versions. */
36961 it_v
= default_version_info
;
36962 while (it_v
!= NULL
)
36964 it_v
->dispatcher_resolver
= dispatch_decl
;
36970 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
36971 "multiversioning needs ifunc which is not supported "
36976 return dispatch_decl
;
36979 /* Make the resolver function decl to dispatch the versions of a multi-
36980 versioned function, DEFAULT_DECL. Create an empty basic block in the
36981 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
36985 make_resolver_func (const tree default_decl
,
36986 const tree dispatch_decl
,
36987 basic_block
*empty_bb
)
36989 /* Make the resolver function static. The resolver function returns
36991 tree decl_name
= clone_function_name_numbered (default_decl
, "resolver");
36992 const char *resolver_name
= IDENTIFIER_POINTER (decl_name
);
36993 tree type
= build_function_type_list (ptr_type_node
, NULL_TREE
);
36994 tree decl
= build_fn_decl (resolver_name
, type
);
36995 SET_DECL_ASSEMBLER_NAME (decl
, decl_name
);
36997 DECL_NAME (decl
) = decl_name
;
36998 TREE_USED (decl
) = 1;
36999 DECL_ARTIFICIAL (decl
) = 1;
37000 DECL_IGNORED_P (decl
) = 0;
37001 TREE_PUBLIC (decl
) = 0;
37002 DECL_UNINLINABLE (decl
) = 1;
37004 /* Resolver is not external, body is generated. */
37005 DECL_EXTERNAL (decl
) = 0;
37006 DECL_EXTERNAL (dispatch_decl
) = 0;
37008 DECL_CONTEXT (decl
) = NULL_TREE
;
37009 DECL_INITIAL (decl
) = make_node (BLOCK
);
37010 DECL_STATIC_CONSTRUCTOR (decl
) = 0;
37012 /* Build result decl and add to function_decl. */
37013 tree t
= build_decl (UNKNOWN_LOCATION
, RESULT_DECL
, NULL_TREE
, ptr_type_node
);
37014 DECL_ARTIFICIAL (t
) = 1;
37015 DECL_IGNORED_P (t
) = 1;
37016 DECL_RESULT (decl
) = t
;
37018 gimplify_function_tree (decl
);
37019 push_cfun (DECL_STRUCT_FUNCTION (decl
));
37020 *empty_bb
= init_lowered_empty_function (decl
, false,
37021 profile_count::uninitialized ());
37023 cgraph_node::add_new_function (decl
, true);
37024 symtab
->call_cgraph_insertion_hooks (cgraph_node::get_create (decl
));
37028 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37029 DECL_ATTRIBUTES (dispatch_decl
)
37030 = make_attribute ("ifunc", resolver_name
, DECL_ATTRIBUTES (dispatch_decl
));
37032 cgraph_node::create_same_body_alias (dispatch_decl
, decl
);
37037 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37038 return a pointer to VERSION_DECL if we are running on a machine that
37039 supports the index CLONE_ISA hardware architecture bits. This function will
37040 be called during version dispatch to decide which function version to
37041 execute. It returns the basic block at the end, to which more conditions
37045 add_condition_to_bb (tree function_decl
, tree version_decl
,
37046 int clone_isa
, basic_block new_bb
)
37048 push_cfun (DECL_STRUCT_FUNCTION (function_decl
));
37050 gcc_assert (new_bb
!= NULL
);
37051 gimple_seq gseq
= bb_seq (new_bb
);
37054 tree convert_expr
= build1 (CONVERT_EXPR
, ptr_type_node
,
37055 build_fold_addr_expr (version_decl
));
37056 tree result_var
= create_tmp_var (ptr_type_node
);
37057 gimple
*convert_stmt
= gimple_build_assign (result_var
, convert_expr
);
37058 gimple
*return_stmt
= gimple_build_return (result_var
);
37060 if (clone_isa
== CLONE_DEFAULT
)
37062 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37063 gimple_seq_add_stmt (&gseq
, return_stmt
);
37064 set_bb_seq (new_bb
, gseq
);
37065 gimple_set_bb (convert_stmt
, new_bb
);
37066 gimple_set_bb (return_stmt
, new_bb
);
37071 tree bool_zero
= build_int_cst (bool_int_type_node
, 0);
37072 tree cond_var
= create_tmp_var (bool_int_type_node
);
37073 tree predicate_decl
= rs6000_builtin_decls
[(int) RS6000_BUILTIN_CPU_SUPPORTS
];
37074 const char *arg_str
= rs6000_clone_map
[clone_isa
].name
;
37075 tree predicate_arg
= build_string_literal (strlen (arg_str
) + 1, arg_str
);
37076 gimple
*call_cond_stmt
= gimple_build_call (predicate_decl
, 1, predicate_arg
);
37077 gimple_call_set_lhs (call_cond_stmt
, cond_var
);
37079 gimple_set_block (call_cond_stmt
, DECL_INITIAL (function_decl
));
37080 gimple_set_bb (call_cond_stmt
, new_bb
);
37081 gimple_seq_add_stmt (&gseq
, call_cond_stmt
);
37083 gimple
*if_else_stmt
= gimple_build_cond (NE_EXPR
, cond_var
, bool_zero
,
37084 NULL_TREE
, NULL_TREE
);
37085 gimple_set_block (if_else_stmt
, DECL_INITIAL (function_decl
));
37086 gimple_set_bb (if_else_stmt
, new_bb
);
37087 gimple_seq_add_stmt (&gseq
, if_else_stmt
);
37089 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37090 gimple_seq_add_stmt (&gseq
, return_stmt
);
37091 set_bb_seq (new_bb
, gseq
);
37093 basic_block bb1
= new_bb
;
37094 edge e12
= split_block (bb1
, if_else_stmt
);
37095 basic_block bb2
= e12
->dest
;
37096 e12
->flags
&= ~EDGE_FALLTHRU
;
37097 e12
->flags
|= EDGE_TRUE_VALUE
;
37099 edge e23
= split_block (bb2
, return_stmt
);
37100 gimple_set_bb (convert_stmt
, bb2
);
37101 gimple_set_bb (return_stmt
, bb2
);
37103 basic_block bb3
= e23
->dest
;
37104 make_edge (bb1
, bb3
, EDGE_FALSE_VALUE
);
37107 make_edge (bb2
, EXIT_BLOCK_PTR_FOR_FN (cfun
), 0);
37113 /* This function generates the dispatch function for multi-versioned functions.
37114 DISPATCH_DECL is the function which will contain the dispatch logic.
37115 FNDECLS are the function choices for dispatch, and is a tree chain.
37116 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37117 code is generated. */
37120 dispatch_function_versions (tree dispatch_decl
,
37122 basic_block
*empty_bb
)
37126 vec
<tree
> *fndecls
;
37127 tree clones
[CLONE_MAX
];
37129 if (TARGET_DEBUG_TARGET
)
37130 fputs ("dispatch_function_versions, top\n", stderr
);
37132 gcc_assert (dispatch_decl
!= NULL
37133 && fndecls_p
!= NULL
37134 && empty_bb
!= NULL
);
37136 /* fndecls_p is actually a vector. */
37137 fndecls
= static_cast<vec
<tree
> *> (fndecls_p
);
37139 /* At least one more version other than the default. */
37140 gcc_assert (fndecls
->length () >= 2);
37142 /* The first version in the vector is the default decl. */
37143 memset ((void *) clones
, '\0', sizeof (clones
));
37144 clones
[CLONE_DEFAULT
] = (*fndecls
)[0];
37146 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37147 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37148 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37149 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37150 to insert the code here to do the call. */
37152 for (ix
= 1; fndecls
->iterate (ix
, &ele
); ++ix
)
37154 int priority
= rs6000_clone_priority (ele
);
37155 if (!clones
[priority
])
37156 clones
[priority
] = ele
;
37159 for (ix
= CLONE_MAX
- 1; ix
>= 0; ix
--)
37162 if (TARGET_DEBUG_TARGET
)
37163 fprintf (stderr
, "dispatch_function_versions, clone %d, %s\n",
37164 ix
, get_decl_name (clones
[ix
]));
37166 *empty_bb
= add_condition_to_bb (dispatch_decl
, clones
[ix
], ix
,
37173 /* Generate the dispatching code body to dispatch multi-versioned function
37174 DECL. The target hook is called to process the "target" attributes and
37175 provide the code to dispatch the right function at run-time. NODE points
37176 to the dispatcher decl whose body will be created. */
37179 rs6000_generate_version_dispatcher_body (void *node_p
)
37182 basic_block empty_bb
;
37183 struct cgraph_node
*node
= (cgraph_node
*) node_p
;
37184 struct cgraph_function_version_info
*ninfo
= node
->function_version ();
37186 if (ninfo
->dispatcher_resolver
)
37187 return ninfo
->dispatcher_resolver
;
37189 /* node is going to be an alias, so remove the finalized bit. */
37190 node
->definition
= false;
37192 /* The first version in the chain corresponds to the default version. */
37193 ninfo
->dispatcher_resolver
= resolver
37194 = make_resolver_func (ninfo
->next
->this_node
->decl
, node
->decl
, &empty_bb
);
37196 if (TARGET_DEBUG_TARGET
)
37197 fprintf (stderr
, "rs6000_get_function_versions_dispatcher, %s\n",
37198 get_decl_name (resolver
));
37200 push_cfun (DECL_STRUCT_FUNCTION (resolver
));
37201 auto_vec
<tree
, 2> fn_ver_vec
;
37203 for (struct cgraph_function_version_info
*vinfo
= ninfo
->next
;
37205 vinfo
= vinfo
->next
)
37207 struct cgraph_node
*version
= vinfo
->this_node
;
37208 /* Check for virtual functions here again, as by this time it should
37209 have been determined if this function needs a vtable index or
37210 not. This happens for methods in derived classes that override
37211 virtual methods in base classes but are not explicitly marked as
37213 if (DECL_VINDEX (version
->decl
))
37214 sorry ("Virtual function multiversioning not supported");
37216 fn_ver_vec
.safe_push (version
->decl
);
37219 dispatch_function_versions (resolver
, &fn_ver_vec
, &empty_bb
);
37220 cgraph_edge::rebuild_edges ();
37226 /* Hook to determine if one function can safely inline another. */
37229 rs6000_can_inline_p (tree caller
, tree callee
)
37232 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
37233 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
37235 /* If callee has no option attributes, then it is ok to inline. */
37239 /* If caller has no option attributes, but callee does then it is not ok to
37241 else if (!caller_tree
)
37246 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
37247 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
37249 /* Callee's options should a subset of the caller's, i.e. a vsx function
37250 can inline an altivec function but a non-vsx function can't inline a
37252 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
37253 == callee_opts
->x_rs6000_isa_flags
)
37257 if (TARGET_DEBUG_TARGET
)
37258 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37259 get_decl_name (caller
), get_decl_name (callee
),
37260 (ret
? "can" : "cannot"));
37265 /* Allocate a stack temp and fixup the address so it meets the particular
37266 memory requirements (either offetable or REG+REG addressing). */
37269 rs6000_allocate_stack_temp (machine_mode mode
,
37270 bool offsettable_p
,
37273 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
37274 rtx addr
= XEXP (stack
, 0);
37275 int strict_p
= reload_completed
;
37277 if (!legitimate_indirect_address_p (addr
, strict_p
))
37280 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
37281 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37283 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
37284 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37290 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37291 convert to such a form to deal with memory reference instructions
37292 like STFIWX and LDBRX that only take reg+reg addressing. */
37295 rs6000_force_indexed_or_indirect_mem (rtx x
)
37297 machine_mode mode
= GET_MODE (x
);
37299 gcc_assert (MEM_P (x
));
37300 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x
, mode
))
37302 rtx addr
= XEXP (x
, 0);
37303 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
37305 rtx reg
= XEXP (addr
, 0);
37306 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
37307 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
37308 gcc_assert (REG_P (reg
));
37309 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
37312 else if (GET_CODE (addr
) == PRE_MODIFY
)
37314 rtx reg
= XEXP (addr
, 0);
37315 rtx expr
= XEXP (addr
, 1);
37316 gcc_assert (REG_P (reg
));
37317 gcc_assert (GET_CODE (expr
) == PLUS
);
37318 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
37322 x
= replace_equiv_address (x
, force_reg (Pmode
, addr
));
37328 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37330 On the RS/6000, all integer constants are acceptable, most won't be valid
37331 for particular insns, though. Only easy FP constants are acceptable. */
37334 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
37336 if (TARGET_ELF
&& tls_referenced_p (x
))
37339 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
37340 || GET_MODE (x
) == VOIDmode
37341 || (TARGET_POWERPC64
&& mode
== DImode
)
37342 || easy_fp_constant (x
, mode
)
37343 || easy_vector_constant (x
, mode
));
37347 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37350 chain_already_loaded (rtx_insn
*last
)
37352 for (; last
!= NULL
; last
= PREV_INSN (last
))
37354 if (NONJUMP_INSN_P (last
))
37356 rtx patt
= PATTERN (last
);
37358 if (GET_CODE (patt
) == SET
)
37360 rtx lhs
= XEXP (patt
, 0);
37362 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
37370 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37373 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
37375 const bool direct_call_p
37376 = GET_CODE (func_desc
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (func_desc
);
37377 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
37378 rtx toc_load
= NULL_RTX
;
37379 rtx toc_restore
= NULL_RTX
;
37381 rtx abi_reg
= NULL_RTX
;
37386 /* Handle longcall attributes. */
37387 if (INTVAL (cookie
) & CALL_LONG
)
37388 func_desc
= rs6000_longcall_ref (func_desc
);
37390 /* Handle indirect calls. */
37391 if (GET_CODE (func_desc
) != SYMBOL_REF
37392 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
37394 /* Save the TOC into its reserved slot before the call,
37395 and prepare to restore it after the call. */
37396 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
37397 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
37398 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
37399 gen_rtx_PLUS (Pmode
, stack_ptr
,
37400 stack_toc_offset
));
37401 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
37402 gen_rtvec (1, stack_toc_offset
),
37404 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
37406 /* Can we optimize saving the TOC in the prologue or
37407 do we need to do it at every call? */
37408 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
37409 cfun
->machine
->save_toc_in_prologue
= true;
37412 MEM_VOLATILE_P (stack_toc_mem
) = 1;
37413 emit_move_insn (stack_toc_mem
, toc_reg
);
37416 if (DEFAULT_ABI
== ABI_ELFv2
)
37418 /* A function pointer in the ELFv2 ABI is just a plain address, but
37419 the ABI requires it to be loaded into r12 before the call. */
37420 func_addr
= gen_rtx_REG (Pmode
, 12);
37421 emit_move_insn (func_addr
, func_desc
);
37422 abi_reg
= func_addr
;
37426 /* A function pointer under AIX is a pointer to a data area whose
37427 first word contains the actual address of the function, whose
37428 second word contains a pointer to its TOC, and whose third word
37429 contains a value to place in the static chain register (r11).
37430 Note that if we load the static chain, our "trampoline" need
37431 not have any executable code. */
37433 /* Load up address of the actual function. */
37434 func_desc
= force_reg (Pmode
, func_desc
);
37435 func_addr
= gen_reg_rtx (Pmode
);
37436 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
37438 /* Prepare to load the TOC of the called function. Note that the
37439 TOC load must happen immediately before the actual call so
37440 that unwinding the TOC registers works correctly. See the
37441 comment in frob_update_context. */
37442 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
37443 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
37444 gen_rtx_PLUS (Pmode
, func_desc
,
37446 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
37448 /* If we have a static chain, load it up. But, if the call was
37449 originally direct, the 3rd word has not been written since no
37450 trampoline has been built, so we ought not to load it, lest we
37451 override a static chain value. */
37453 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37454 && !chain_already_loaded (get_current_sequence ()->next
->last
))
37456 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
37457 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
37458 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
37459 gen_rtx_PLUS (Pmode
, func_desc
,
37461 emit_move_insn (sc_reg
, func_sc_mem
);
37468 /* Direct calls use the TOC: for local calls, the callee will
37469 assume the TOC register is set; for non-local calls, the
37470 PLT stub needs the TOC register. */
37472 func_addr
= func_desc
;
37475 /* Create the call. */
37476 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
37477 if (value
!= NULL_RTX
)
37478 call
[0] = gen_rtx_SET (value
, call
[0]);
37482 call
[n_call
++] = toc_load
;
37484 call
[n_call
++] = toc_restore
;
37486 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
37488 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
37489 insn
= emit_call_insn (insn
);
37491 /* Mention all registers defined by the ABI to hold information
37492 as uses in CALL_INSN_FUNCTION_USAGE. */
37494 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
37497 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37500 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
37505 gcc_assert (INTVAL (cookie
) == 0);
37507 /* Create the call. */
37508 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
37509 if (value
!= NULL_RTX
)
37510 call
[0] = gen_rtx_SET (value
, call
[0]);
37512 call
[1] = simple_return_rtx
;
37514 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
37515 insn
= emit_call_insn (insn
);
37517 /* Note use of the TOC register. */
37518 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
37521 /* Return whether we need to always update the saved TOC pointer when we update
37522 the stack pointer. */
37525 rs6000_save_toc_in_prologue_p (void)
37527 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
37530 #ifdef HAVE_GAS_HIDDEN
37531 # define USE_HIDDEN_LINKONCE 1
37533 # define USE_HIDDEN_LINKONCE 0
37536 /* Fills in the label name that should be used for a 476 link stack thunk. */
37539 get_ppc476_thunk_name (char name
[32])
37541 gcc_assert (TARGET_LINK_STACK
);
37543 if (USE_HIDDEN_LINKONCE
)
37544 sprintf (name
, "__ppc476.get_thunk");
37546 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
37549 /* This function emits the simple thunk routine that is used to preserve
37550 the link stack on the 476 cpu. */
37552 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
37554 rs6000_code_end (void)
37559 if (!TARGET_LINK_STACK
)
37562 get_ppc476_thunk_name (name
);
37564 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
37565 build_function_type_list (void_type_node
, NULL_TREE
));
37566 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
37567 NULL_TREE
, void_type_node
);
37568 TREE_PUBLIC (decl
) = 1;
37569 TREE_STATIC (decl
) = 1;
37572 if (USE_HIDDEN_LINKONCE
&& !TARGET_XCOFF
)
37574 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
37575 targetm
.asm_out
.unique_section (decl
, 0);
37576 switch_to_section (get_named_section (decl
, NULL
, 0));
37577 DECL_WEAK (decl
) = 1;
37578 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
37579 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
37580 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
37581 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
37586 switch_to_section (text_section
);
37587 ASM_OUTPUT_LABEL (asm_out_file
, name
);
37590 DECL_INITIAL (decl
) = make_node (BLOCK
);
37591 current_function_decl
= decl
;
37592 allocate_struct_function (decl
, false);
37593 init_function_start (decl
);
37594 first_function_block_is_cold
= false;
37595 /* Make sure unwind info is emitted for the thunk if needed. */
37596 final_start_function (emit_barrier (), asm_out_file
, 1);
37598 fputs ("\tblr\n", asm_out_file
);
37600 final_end_function ();
37601 init_insn_lengths ();
37602 free_after_compilation (cfun
);
37604 current_function_decl
= NULL
;
37607 /* Add r30 to hard reg set if the prologue sets it up and it is not
37608 pic_offset_table_rtx. */
37611 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
37613 if (!TARGET_SINGLE_PIC_BASE
37615 && TARGET_MINIMAL_TOC
37616 && !constant_pool_empty_p ())
37617 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
37618 if (cfun
->machine
->split_stack_argp_used
)
37619 add_to_hard_reg_set (&set
->set
, Pmode
, 12);
37621 /* Make sure the hard reg set doesn't include r2, which was possibly added
37622 via PIC_OFFSET_TABLE_REGNUM. */
37624 remove_from_hard_reg_set (&set
->set
, Pmode
, TOC_REGNUM
);
37628 /* Helper function for rs6000_split_logical to emit a logical instruction after
37629 spliting the operation to single GPR registers.
37631 DEST is the destination register.
37632 OP1 and OP2 are the input source registers.
37633 CODE is the base operation (AND, IOR, XOR, NOT).
37634 MODE is the machine mode.
37635 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37636 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37637 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37640 rs6000_split_logical_inner (rtx dest
,
37643 enum rtx_code code
,
37645 bool complement_final_p
,
37646 bool complement_op1_p
,
37647 bool complement_op2_p
)
37651 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
37652 if (op2
&& GET_CODE (op2
) == CONST_INT
37653 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
37654 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
37656 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
37657 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
37659 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
37664 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
37668 else if (value
== mask
)
37670 if (!rtx_equal_p (dest
, op1
))
37671 emit_insn (gen_rtx_SET (dest
, op1
));
37676 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
37677 into separate ORI/ORIS or XORI/XORIS instrucitons. */
37678 else if (code
== IOR
|| code
== XOR
)
37682 if (!rtx_equal_p (dest
, op1
))
37683 emit_insn (gen_rtx_SET (dest
, op1
));
37689 if (code
== AND
&& mode
== SImode
37690 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
37692 emit_insn (gen_andsi3 (dest
, op1
, op2
));
37696 if (complement_op1_p
)
37697 op1
= gen_rtx_NOT (mode
, op1
);
37699 if (complement_op2_p
)
37700 op2
= gen_rtx_NOT (mode
, op2
);
37702 /* For canonical RTL, if only one arm is inverted it is the first. */
37703 if (!complement_op1_p
&& complement_op2_p
)
37704 std::swap (op1
, op2
);
37706 bool_rtx
= ((code
== NOT
)
37707 ? gen_rtx_NOT (mode
, op1
)
37708 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
37710 if (complement_final_p
)
37711 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
37713 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
37716 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
37717 operations are split immediately during RTL generation to allow for more
37718 optimizations of the AND/IOR/XOR.
37720 OPERANDS is an array containing the destination and two input operands.
37721 CODE is the base operation (AND, IOR, XOR, NOT).
37722 MODE is the machine mode.
37723 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37724 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37725 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
37726 CLOBBER_REG is either NULL or a scratch register of type CC to allow
37727 formation of the AND instructions. */
37730 rs6000_split_logical_di (rtx operands
[3],
37731 enum rtx_code code
,
37732 bool complement_final_p
,
37733 bool complement_op1_p
,
37734 bool complement_op2_p
)
37736 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
37737 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
37738 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
37739 enum hi_lo
{ hi
= 0, lo
= 1 };
37740 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
37743 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
37744 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
37745 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
37746 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
37749 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
37752 if (GET_CODE (operands
[2]) != CONST_INT
)
37754 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
37755 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
37759 HOST_WIDE_INT value
= INTVAL (operands
[2]);
37760 HOST_WIDE_INT value_hi_lo
[2];
37762 gcc_assert (!complement_final_p
);
37763 gcc_assert (!complement_op1_p
);
37764 gcc_assert (!complement_op2_p
);
37766 value_hi_lo
[hi
] = value
>> 32;
37767 value_hi_lo
[lo
] = value
& lower_32bits
;
37769 for (i
= 0; i
< 2; i
++)
37771 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
37773 if (sub_value
& sign_bit
)
37774 sub_value
|= upper_32bits
;
37776 op2_hi_lo
[i
] = GEN_INT (sub_value
);
37778 /* If this is an AND instruction, check to see if we need to load
37779 the value in a register. */
37780 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
37781 && !and_operand (op2_hi_lo
[i
], SImode
))
37782 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
37787 for (i
= 0; i
< 2; i
++)
37789 /* Split large IOR/XOR operations. */
37790 if ((code
== IOR
|| code
== XOR
)
37791 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
37792 && !complement_final_p
37793 && !complement_op1_p
37794 && !complement_op2_p
37795 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
37797 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
37798 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
37799 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
37800 rtx tmp
= gen_reg_rtx (SImode
);
37802 /* Make sure the constant is sign extended. */
37803 if ((hi_16bits
& sign_bit
) != 0)
37804 hi_16bits
|= upper_32bits
;
37806 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
37807 code
, SImode
, false, false, false);
37809 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
37810 code
, SImode
, false, false, false);
37813 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
37814 code
, SImode
, complement_final_p
,
37815 complement_op1_p
, complement_op2_p
);
37821 /* Split the insns that make up boolean operations operating on multiple GPR
37822 registers. The boolean MD patterns ensure that the inputs either are
37823 exactly the same as the output registers, or there is no overlap.
37825 OPERANDS is an array containing the destination and two input operands.
37826 CODE is the base operation (AND, IOR, XOR, NOT).
37827 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
37828 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
37829 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
37832 rs6000_split_logical (rtx operands
[3],
37833 enum rtx_code code
,
37834 bool complement_final_p
,
37835 bool complement_op1_p
,
37836 bool complement_op2_p
)
37838 machine_mode mode
= GET_MODE (operands
[0]);
37839 machine_mode sub_mode
;
37841 int sub_size
, regno0
, regno1
, nregs
, i
;
37843 /* If this is DImode, use the specialized version that can run before
37844 register allocation. */
37845 if (mode
== DImode
&& !TARGET_POWERPC64
)
37847 rs6000_split_logical_di (operands
, code
, complement_final_p
,
37848 complement_op1_p
, complement_op2_p
);
37854 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
37855 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
37856 sub_size
= GET_MODE_SIZE (sub_mode
);
37857 regno0
= REGNO (op0
);
37858 regno1
= REGNO (op1
);
37860 gcc_assert (reload_completed
);
37861 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
37862 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
37864 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
37865 gcc_assert (nregs
> 1);
37867 if (op2
&& REG_P (op2
))
37868 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
37870 for (i
= 0; i
< nregs
; i
++)
37872 int offset
= i
* sub_size
;
37873 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
37874 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
37875 rtx sub_op2
= ((code
== NOT
)
37877 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
37879 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
37880 complement_final_p
, complement_op1_p
,
37888 /* Return true if the peephole2 can combine a load involving a combination of
37889 an addis instruction and a load with an offset that can be fused together on
37893 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
37894 rtx addis_value
, /* addis value. */
37895 rtx target
, /* target register that is loaded. */
37896 rtx mem
) /* bottom part of the memory addr. */
37901 /* Validate arguments. */
37902 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
37905 if (!base_reg_operand (target
, GET_MODE (target
)))
37908 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
37911 /* Allow sign/zero extension. */
37912 if (GET_CODE (mem
) == ZERO_EXTEND
37913 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
37914 mem
= XEXP (mem
, 0);
37919 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
37922 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
37923 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
37926 /* Validate that the register used to load the high value is either the
37927 register being loaded, or we can safely replace its use.
37929 This function is only called from the peephole2 pass and we assume that
37930 there are 2 instructions in the peephole (addis and load), so we want to
37931 check if the target register was not used in the memory address and the
37932 register to hold the addis result is dead after the peephole. */
37933 if (REGNO (addis_reg
) != REGNO (target
))
37935 if (reg_mentioned_p (target
, mem
))
37938 if (!peep2_reg_dead_p (2, addis_reg
))
37941 /* If the target register being loaded is the stack pointer, we must
37942 avoid loading any other value into it, even temporarily. */
37943 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
37947 base_reg
= XEXP (addr
, 0);
37948 return REGNO (addis_reg
) == REGNO (base_reg
);
37951 /* During the peephole2 pass, adjust and expand the insns for a load fusion
37952 sequence. We adjust the addis register to use the target register. If the
37953 load sign extends, we adjust the code to do the zero extending load, and an
37954 explicit sign extension later since the fusion only covers zero extending
37958 operands[0] register set with addis (to be replaced with target)
37959 operands[1] value set via addis
37960 operands[2] target register being loaded
37961 operands[3] D-form memory reference using operands[0]. */
37964 expand_fusion_gpr_load (rtx
*operands
)
37966 rtx addis_value
= operands
[1];
37967 rtx target
= operands
[2];
37968 rtx orig_mem
= operands
[3];
37969 rtx new_addr
, new_mem
, orig_addr
, offset
;
37970 enum rtx_code plus_or_lo_sum
;
37971 machine_mode target_mode
= GET_MODE (target
);
37972 machine_mode extend_mode
= target_mode
;
37973 machine_mode ptr_mode
= Pmode
;
37974 enum rtx_code extend
= UNKNOWN
;
37976 if (GET_CODE (orig_mem
) == ZERO_EXTEND
37977 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
37979 extend
= GET_CODE (orig_mem
);
37980 orig_mem
= XEXP (orig_mem
, 0);
37981 target_mode
= GET_MODE (orig_mem
);
37984 gcc_assert (MEM_P (orig_mem
));
37986 orig_addr
= XEXP (orig_mem
, 0);
37987 plus_or_lo_sum
= GET_CODE (orig_addr
);
37988 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
37990 offset
= XEXP (orig_addr
, 1);
37991 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
37992 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
37994 if (extend
!= UNKNOWN
)
37995 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
37997 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
37998 UNSPEC_FUSION_GPR
);
37999 emit_insn (gen_rtx_SET (target
, new_mem
));
38001 if (extend
== SIGN_EXTEND
)
38003 int sub_off
= ((BYTES_BIG_ENDIAN
)
38004 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
38007 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
38009 emit_insn (gen_rtx_SET (target
,
38010 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
38016 /* Emit the addis instruction that will be part of a fused instruction
38020 emit_fusion_addis (rtx target
, rtx addis_value
)
38023 const char *addis_str
= NULL
;
38025 /* Emit the addis instruction. */
38026 fuse_ops
[0] = target
;
38027 if (satisfies_constraint_L (addis_value
))
38029 fuse_ops
[1] = addis_value
;
38030 addis_str
= "lis %0,%v1";
38033 else if (GET_CODE (addis_value
) == PLUS
)
38035 rtx op0
= XEXP (addis_value
, 0);
38036 rtx op1
= XEXP (addis_value
, 1);
38038 if (REG_P (op0
) && CONST_INT_P (op1
)
38039 && satisfies_constraint_L (op1
))
38043 addis_str
= "addis %0,%1,%v2";
38047 else if (GET_CODE (addis_value
) == HIGH
)
38049 rtx value
= XEXP (addis_value
, 0);
38050 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
38052 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
38053 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
38055 addis_str
= "addis %0,%2,%1@toc@ha";
38057 else if (TARGET_XCOFF
)
38058 addis_str
= "addis %0,%1@u(%2)";
38061 gcc_unreachable ();
38064 else if (GET_CODE (value
) == PLUS
)
38066 rtx op0
= XEXP (value
, 0);
38067 rtx op1
= XEXP (value
, 1);
38069 if (GET_CODE (op0
) == UNSPEC
38070 && XINT (op0
, 1) == UNSPEC_TOCREL
38071 && CONST_INT_P (op1
))
38073 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
38074 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
38077 addis_str
= "addis %0,%2,%1+%3@toc@ha";
38079 else if (TARGET_XCOFF
)
38080 addis_str
= "addis %0,%1+%3@u(%2)";
38083 gcc_unreachable ();
38087 else if (satisfies_constraint_L (value
))
38089 fuse_ops
[1] = value
;
38090 addis_str
= "lis %0,%v1";
38093 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
38095 fuse_ops
[1] = value
;
38096 addis_str
= "lis %0,%1@ha";
38101 fatal_insn ("Could not generate addis value for fusion", addis_value
);
38103 output_asm_insn (addis_str
, fuse_ops
);
38106 /* Emit a D-form load or store instruction that is the second instruction
38107 of a fusion sequence. */
38110 emit_fusion_load_store (rtx load_store_reg
, rtx addis_reg
, rtx offset
,
38111 const char *insn_str
)
38114 char insn_template
[80];
38116 fuse_ops
[0] = load_store_reg
;
38117 fuse_ops
[1] = addis_reg
;
38119 if (CONST_INT_P (offset
) && satisfies_constraint_I (offset
))
38121 sprintf (insn_template
, "%s %%0,%%2(%%1)", insn_str
);
38122 fuse_ops
[2] = offset
;
38123 output_asm_insn (insn_template
, fuse_ops
);
38126 else if (GET_CODE (offset
) == UNSPEC
38127 && XINT (offset
, 1) == UNSPEC_TOCREL
)
38130 sprintf (insn_template
, "%s %%0,%%2@toc@l(%%1)", insn_str
);
38132 else if (TARGET_XCOFF
)
38133 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
38136 gcc_unreachable ();
38138 fuse_ops
[2] = XVECEXP (offset
, 0, 0);
38139 output_asm_insn (insn_template
, fuse_ops
);
38142 else if (GET_CODE (offset
) == PLUS
38143 && GET_CODE (XEXP (offset
, 0)) == UNSPEC
38144 && XINT (XEXP (offset
, 0), 1) == UNSPEC_TOCREL
38145 && CONST_INT_P (XEXP (offset
, 1)))
38147 rtx tocrel_unspec
= XEXP (offset
, 0);
38149 sprintf (insn_template
, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str
);
38151 else if (TARGET_XCOFF
)
38152 sprintf (insn_template
, "%s %%0,%%2+%%3@l(%%1)", insn_str
);
38155 gcc_unreachable ();
38157 fuse_ops
[2] = XVECEXP (tocrel_unspec
, 0, 0);
38158 fuse_ops
[3] = XEXP (offset
, 1);
38159 output_asm_insn (insn_template
, fuse_ops
);
38162 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (offset
))
38164 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
38166 fuse_ops
[2] = offset
;
38167 output_asm_insn (insn_template
, fuse_ops
);
38171 fatal_insn ("Unable to generate load/store offset for fusion", offset
);
38176 /* Given an address, convert it into the addis and load offset parts. Addresses
38177 created during the peephole2 process look like:
38178 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38179 (unspec [(...)] UNSPEC_TOCREL)) */
38182 fusion_split_address (rtx addr
, rtx
*p_hi
, rtx
*p_lo
)
38186 if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
38188 hi
= XEXP (addr
, 0);
38189 lo
= XEXP (addr
, 1);
38192 gcc_unreachable ();
38198 /* Return a string to fuse an addis instruction with a gpr load to the same
38199 register that we loaded up the addis instruction. The address that is used
38200 is the logical address that was formed during peephole2:
38201 (lo_sum (high) (low-part))
38203 The code is complicated, so we call output_asm_insn directly, and just
38207 emit_fusion_gpr_load (rtx target
, rtx mem
)
38212 const char *load_str
= NULL
;
38215 if (GET_CODE (mem
) == ZERO_EXTEND
)
38216 mem
= XEXP (mem
, 0);
38218 gcc_assert (REG_P (target
) && MEM_P (mem
));
38220 addr
= XEXP (mem
, 0);
38221 fusion_split_address (addr
, &addis_value
, &load_offset
);
38223 /* Now emit the load instruction to the same register. */
38224 mode
= GET_MODE (mem
);
38242 gcc_assert (TARGET_POWERPC64
);
38247 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target
, mem
));
38250 /* Emit the addis instruction. */
38251 emit_fusion_addis (target
, addis_value
);
38253 /* Emit the D-form load instruction. */
38254 emit_fusion_load_store (target
, target
, load_offset
, load_str
);
38260 /* Return true if the peephole2 can combine a load/store involving a
38261 combination of an addis instruction and the memory operation. This was
38262 added to the ISA 3.0 (power9) hardware. */
38265 fusion_p9_p (rtx addis_reg
, /* register set via addis. */
38266 rtx addis_value
, /* addis value. */
38267 rtx dest
, /* destination (memory or register). */
38268 rtx src
) /* source (register or memory). */
38270 rtx addr
, mem
, offset
;
38271 machine_mode mode
= GET_MODE (src
);
38273 /* Validate arguments. */
38274 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
38277 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
38280 /* Ignore extend operations that are part of the load. */
38281 if (GET_CODE (src
) == FLOAT_EXTEND
|| GET_CODE (src
) == ZERO_EXTEND
)
38282 src
= XEXP (src
, 0);
38284 /* Test for memory<-register or register<-memory. */
38285 if (fpr_reg_operand (src
, mode
) || int_reg_operand (src
, mode
))
38293 else if (MEM_P (src
))
38295 if (!fpr_reg_operand (dest
, mode
) && !int_reg_operand (dest
, mode
))
38304 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
38305 if (GET_CODE (addr
) == PLUS
)
38307 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
38310 return satisfies_constraint_I (XEXP (addr
, 1));
38313 else if (GET_CODE (addr
) == LO_SUM
)
38315 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
38318 offset
= XEXP (addr
, 1);
38319 if (TARGET_XCOFF
|| (TARGET_ELF
&& TARGET_POWERPC64
))
38320 return small_toc_ref (offset
, GET_MODE (offset
));
38322 else if (TARGET_ELF
&& !TARGET_POWERPC64
)
38323 return CONSTANT_P (offset
);
38329 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38333 operands[0] register set with addis
38334 operands[1] value set via addis
38335 operands[2] target register being loaded
38336 operands[3] D-form memory reference using operands[0].
38338 This is similar to the fusion introduced with power8, except it scales to
38339 both loads/stores and does not require the result register to be the same as
38340 the base register. At the moment, we only do this if register set with addis
38344 expand_fusion_p9_load (rtx
*operands
)
38346 rtx tmp_reg
= operands
[0];
38347 rtx addis_value
= operands
[1];
38348 rtx target
= operands
[2];
38349 rtx orig_mem
= operands
[3];
38350 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
;
38351 enum rtx_code plus_or_lo_sum
;
38352 machine_mode target_mode
= GET_MODE (target
);
38353 machine_mode extend_mode
= target_mode
;
38354 machine_mode ptr_mode
= Pmode
;
38355 enum rtx_code extend
= UNKNOWN
;
38357 if (GET_CODE (orig_mem
) == FLOAT_EXTEND
|| GET_CODE (orig_mem
) == ZERO_EXTEND
)
38359 extend
= GET_CODE (orig_mem
);
38360 orig_mem
= XEXP (orig_mem
, 0);
38361 target_mode
= GET_MODE (orig_mem
);
38364 gcc_assert (MEM_P (orig_mem
));
38366 orig_addr
= XEXP (orig_mem
, 0);
38367 plus_or_lo_sum
= GET_CODE (orig_addr
);
38368 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
38370 offset
= XEXP (orig_addr
, 1);
38371 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
38372 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
38374 if (extend
!= UNKNOWN
)
38375 new_mem
= gen_rtx_fmt_e (extend
, extend_mode
, new_mem
);
38377 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
38380 set
= gen_rtx_SET (target
, new_mem
);
38381 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
38382 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
38388 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
38392 operands[0] register set with addis
38393 operands[1] value set via addis
38394 operands[2] target D-form memory being stored to
38395 operands[3] register being stored
38397 This is similar to the fusion introduced with power8, except it scales to
38398 both loads/stores and does not require the result register to be the same as
38399 the base register. At the moment, we only do this if register set with addis
38403 expand_fusion_p9_store (rtx
*operands
)
38405 rtx tmp_reg
= operands
[0];
38406 rtx addis_value
= operands
[1];
38407 rtx orig_mem
= operands
[2];
38408 rtx src
= operands
[3];
38409 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
, new_src
;
38410 enum rtx_code plus_or_lo_sum
;
38411 machine_mode target_mode
= GET_MODE (orig_mem
);
38412 machine_mode ptr_mode
= Pmode
;
38414 gcc_assert (MEM_P (orig_mem
));
38416 orig_addr
= XEXP (orig_mem
, 0);
38417 plus_or_lo_sum
= GET_CODE (orig_addr
);
38418 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
38420 offset
= XEXP (orig_addr
, 1);
38421 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
38422 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
38424 new_src
= gen_rtx_UNSPEC (target_mode
, gen_rtvec (1, src
),
38427 set
= gen_rtx_SET (new_mem
, new_src
);
38428 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
38429 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
38435 /* Return a string to fuse an addis instruction with a load using extended
38436 fusion. The address that is used is the logical address that was formed
38437 during peephole2: (lo_sum (high) (low-part))
38439 The code is complicated, so we call output_asm_insn directly, and just
38443 emit_fusion_p9_load (rtx reg
, rtx mem
, rtx tmp_reg
)
38445 machine_mode mode
= GET_MODE (reg
);
38449 const char *load_string
;
38452 if (GET_CODE (mem
) == FLOAT_EXTEND
|| GET_CODE (mem
) == ZERO_EXTEND
)
38454 mem
= XEXP (mem
, 0);
38455 mode
= GET_MODE (mem
);
38458 if (GET_CODE (reg
) == SUBREG
)
38460 gcc_assert (SUBREG_BYTE (reg
) == 0);
38461 reg
= SUBREG_REG (reg
);
38465 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg
);
38468 if (FP_REGNO_P (r
))
38470 if (mode
== SFmode
)
38471 load_string
= "lfs";
38472 else if (mode
== DFmode
|| mode
== DImode
)
38473 load_string
= "lfd";
38475 gcc_unreachable ();
38477 else if (ALTIVEC_REGNO_P (r
) && TARGET_P9_VECTOR
)
38479 if (mode
== SFmode
)
38480 load_string
= "lxssp";
38481 else if (mode
== DFmode
|| mode
== DImode
)
38482 load_string
= "lxsd";
38484 gcc_unreachable ();
38486 else if (INT_REGNO_P (r
))
38491 load_string
= "lbz";
38494 load_string
= "lhz";
38498 load_string
= "lwz";
38502 if (!TARGET_POWERPC64
)
38503 gcc_unreachable ();
38504 load_string
= "ld";
38507 gcc_unreachable ();
38511 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg
);
38514 fatal_insn ("emit_fusion_p9_load not MEM", mem
);
38516 addr
= XEXP (mem
, 0);
38517 fusion_split_address (addr
, &hi
, &lo
);
38519 /* Emit the addis instruction. */
38520 emit_fusion_addis (tmp_reg
, hi
);
38522 /* Emit the D-form load instruction. */
38523 emit_fusion_load_store (reg
, tmp_reg
, lo
, load_string
);
38528 /* Return a string to fuse an addis instruction with a store using extended
38529 fusion. The address that is used is the logical address that was formed
38530 during peephole2: (lo_sum (high) (low-part))
38532 The code is complicated, so we call output_asm_insn directly, and just
38536 emit_fusion_p9_store (rtx mem
, rtx reg
, rtx tmp_reg
)
38538 machine_mode mode
= GET_MODE (reg
);
38542 const char *store_string
;
38545 if (GET_CODE (reg
) == SUBREG
)
38547 gcc_assert (SUBREG_BYTE (reg
) == 0);
38548 reg
= SUBREG_REG (reg
);
38552 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg
);
38555 if (FP_REGNO_P (r
))
38557 if (mode
== SFmode
)
38558 store_string
= "stfs";
38559 else if (mode
== DFmode
)
38560 store_string
= "stfd";
38562 gcc_unreachable ();
38564 else if (ALTIVEC_REGNO_P (r
) && TARGET_P9_VECTOR
)
38566 if (mode
== SFmode
)
38567 store_string
= "stxssp";
38568 else if (mode
== DFmode
|| mode
== DImode
)
38569 store_string
= "stxsd";
38571 gcc_unreachable ();
38573 else if (INT_REGNO_P (r
))
38578 store_string
= "stb";
38581 store_string
= "sth";
38585 store_string
= "stw";
38589 if (!TARGET_POWERPC64
)
38590 gcc_unreachable ();
38591 store_string
= "std";
38594 gcc_unreachable ();
38598 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg
);
38601 fatal_insn ("emit_fusion_p9_store not MEM", mem
);
38603 addr
= XEXP (mem
, 0);
38604 fusion_split_address (addr
, &hi
, &lo
);
38606 /* Emit the addis instruction. */
38607 emit_fusion_addis (tmp_reg
, hi
);
38609 /* Emit the D-form load instruction. */
38610 emit_fusion_load_store (reg
, tmp_reg
, lo
, store_string
);
38615 #ifdef RS6000_GLIBC_ATOMIC_FENV
38616 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38617 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
38620 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38623 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
38625 if (!TARGET_HARD_FLOAT
)
38627 #ifdef RS6000_GLIBC_ATOMIC_FENV
38628 if (atomic_hold_decl
== NULL_TREE
)
38631 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38632 get_identifier ("__atomic_feholdexcept"),
38633 build_function_type_list (void_type_node
,
38634 double_ptr_type_node
,
38636 TREE_PUBLIC (atomic_hold_decl
) = 1;
38637 DECL_EXTERNAL (atomic_hold_decl
) = 1;
38640 if (atomic_clear_decl
== NULL_TREE
)
38643 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38644 get_identifier ("__atomic_feclearexcept"),
38645 build_function_type_list (void_type_node
,
38647 TREE_PUBLIC (atomic_clear_decl
) = 1;
38648 DECL_EXTERNAL (atomic_clear_decl
) = 1;
38651 tree const_double
= build_qualified_type (double_type_node
,
38653 tree const_double_ptr
= build_pointer_type (const_double
);
38654 if (atomic_update_decl
== NULL_TREE
)
38657 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
38658 get_identifier ("__atomic_feupdateenv"),
38659 build_function_type_list (void_type_node
,
38662 TREE_PUBLIC (atomic_update_decl
) = 1;
38663 DECL_EXTERNAL (atomic_update_decl
) = 1;
38666 tree fenv_var
= create_tmp_var_raw (double_type_node
);
38667 TREE_ADDRESSABLE (fenv_var
) = 1;
38668 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
38670 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
38671 *clear
= build_call_expr (atomic_clear_decl
, 0);
38672 *update
= build_call_expr (atomic_update_decl
, 1,
38673 fold_convert (const_double_ptr
, fenv_addr
));
38678 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
38679 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
38680 tree call_mffs
= build_call_expr (mffs
, 0);
38682 /* Generates the equivalent of feholdexcept (&fenv_var)
38684 *fenv_var = __builtin_mffs ();
38686 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38687 __builtin_mtfsf (0xff, fenv_hold); */
38689 /* Mask to clear everything except for the rounding modes and non-IEEE
38690 arithmetic flag. */
38691 const unsigned HOST_WIDE_INT hold_exception_mask
=
38692 HOST_WIDE_INT_C (0xffffffff00000007);
38694 tree fenv_var
= create_tmp_var_raw (double_type_node
);
38696 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
38698 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
38699 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
38700 build_int_cst (uint64_type_node
,
38701 hold_exception_mask
));
38703 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38706 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
38707 build_int_cst (unsigned_type_node
, 0xff),
38710 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
38712 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38714 double fenv_clear = __builtin_mffs ();
38715 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38716 __builtin_mtfsf (0xff, fenv_clear); */
38718 /* Mask to clear everything except for the rounding modes and non-IEEE
38719 arithmetic flag. */
38720 const unsigned HOST_WIDE_INT clear_exception_mask
=
38721 HOST_WIDE_INT_C (0xffffffff00000000);
38723 tree fenv_clear
= create_tmp_var_raw (double_type_node
);
38725 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
38727 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
38728 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
38730 build_int_cst (uint64_type_node
,
38731 clear_exception_mask
));
38733 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38734 fenv_clear_llu_and
);
38736 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
38737 build_int_cst (unsigned_type_node
, 0xff),
38740 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
38742 /* Generates the equivalent of feupdateenv (&fenv_var)
38744 double old_fenv = __builtin_mffs ();
38745 double fenv_update;
38746 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38747 (*(uint64_t*)fenv_var 0x1ff80fff);
38748 __builtin_mtfsf (0xff, fenv_update); */
38750 const unsigned HOST_WIDE_INT update_exception_mask
=
38751 HOST_WIDE_INT_C (0xffffffff1fffff00);
38752 const unsigned HOST_WIDE_INT new_exception_mask
=
38753 HOST_WIDE_INT_C (0x1ff80fff);
38755 tree old_fenv
= create_tmp_var_raw (double_type_node
);
38756 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
38758 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
38759 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
38760 build_int_cst (uint64_type_node
,
38761 update_exception_mask
));
38763 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
38764 build_int_cst (uint64_type_node
,
38765 new_exception_mask
));
38767 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
38768 old_llu_and
, new_llu_and
);
38770 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38773 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
38774 build_int_cst (unsigned_type_node
, 0xff),
38775 fenv_update_mtfsf
);
38777 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
38781 rs6000_generate_float2_double_code (rtx dst
, rtx src1
, rtx src2
)
38783 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
38785 rtx_tmp0
= gen_reg_rtx (V2DFmode
);
38786 rtx_tmp1
= gen_reg_rtx (V2DFmode
);
38788 /* The destination of the vmrgew instruction layout is:
38789 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38790 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38791 vmrgew instruction will be correct. */
38792 if (BYTES_BIG_ENDIAN
)
38794 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0
, src1
, src2
,
38796 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1
, src1
, src2
,
38801 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0
, src1
, src2
, GEN_INT (3)));
38802 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1
, src1
, src2
, GEN_INT (0)));
38805 rtx_tmp2
= gen_reg_rtx (V4SFmode
);
38806 rtx_tmp3
= gen_reg_rtx (V4SFmode
);
38808 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2
, rtx_tmp0
));
38809 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3
, rtx_tmp1
));
38811 if (BYTES_BIG_ENDIAN
)
38812 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp2
, rtx_tmp3
));
38814 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp3
, rtx_tmp2
));
38818 rs6000_generate_float2_code (bool signed_convert
, rtx dst
, rtx src1
, rtx src2
)
38820 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
38822 rtx_tmp0
= gen_reg_rtx (V2DImode
);
38823 rtx_tmp1
= gen_reg_rtx (V2DImode
);
38825 /* The destination of the vmrgew instruction layout is:
38826 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
38827 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
38828 vmrgew instruction will be correct. */
38829 if (BYTES_BIG_ENDIAN
)
38831 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
38832 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
38836 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0
, src1
, src2
, GEN_INT (3)));
38837 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1
, src1
, src2
, GEN_INT (0)));
38840 rtx_tmp2
= gen_reg_rtx (V4SFmode
);
38841 rtx_tmp3
= gen_reg_rtx (V4SFmode
);
38843 if (signed_convert
)
38845 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2
, rtx_tmp0
));
38846 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3
, rtx_tmp1
));
38850 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2
, rtx_tmp0
));
38851 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3
, rtx_tmp1
));
38854 if (BYTES_BIG_ENDIAN
)
38855 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp2
, rtx_tmp3
));
38857 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp3
, rtx_tmp2
));
38861 rs6000_generate_vsigned2_code (bool signed_convert
, rtx dst
, rtx src1
,
38864 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
38866 rtx_tmp0
= gen_reg_rtx (V2DFmode
);
38867 rtx_tmp1
= gen_reg_rtx (V2DFmode
);
38869 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
38870 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
38872 rtx_tmp2
= gen_reg_rtx (V4SImode
);
38873 rtx_tmp3
= gen_reg_rtx (V4SImode
);
38875 if (signed_convert
)
38877 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2
, rtx_tmp0
));
38878 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3
, rtx_tmp1
));
38882 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2
, rtx_tmp0
));
38883 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3
, rtx_tmp1
));
38886 emit_insn (gen_p8_vmrgew_v4si (dst
, rtx_tmp2
, rtx_tmp3
));
38889 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
38892 rs6000_optab_supported_p (int op
, machine_mode mode1
, machine_mode
,
38893 optimization_type opt_type
)
38898 return (opt_type
== OPTIMIZE_FOR_SPEED
38899 && RS6000_RECIP_AUTO_RSQRTE_P (mode1
));
38906 /* Implement TARGET_CONSTANT_ALIGNMENT. */
38908 static HOST_WIDE_INT
38909 rs6000_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
38911 if (TREE_CODE (exp
) == STRING_CST
38912 && (STRICT_ALIGNMENT
|| !optimize_size
))
38913 return MAX (align
, BITS_PER_WORD
);
38917 /* Implement TARGET_STARTING_FRAME_OFFSET. */
38919 static HOST_WIDE_INT
38920 rs6000_starting_frame_offset (void)
38922 if (FRAME_GROWS_DOWNWARD
)
38924 return RS6000_STARTING_FRAME_OFFSET
;
38928 /* Create an alias for a mangled name where we have changed the mangling (in
38929 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
38930 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
38932 #if TARGET_ELF && RS6000_WEAK
38934 rs6000_globalize_decl_name (FILE * stream
, tree decl
)
38936 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
38938 targetm
.asm_out
.globalize_label (stream
, name
);
38940 if (rs6000_passes_ieee128
&& name
[0] == '_' && name
[1] == 'Z')
38942 tree save_asm_name
= DECL_ASSEMBLER_NAME (decl
);
38943 const char *old_name
;
38945 ieee128_mangling_gcc_8_1
= true;
38946 lang_hooks
.set_decl_assembler_name (decl
);
38947 old_name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
38948 SET_DECL_ASSEMBLER_NAME (decl
, save_asm_name
);
38949 ieee128_mangling_gcc_8_1
= false;
38951 if (strcmp (name
, old_name
) != 0)
38953 fprintf (stream
, "\t.weak %s\n", old_name
);
38954 fprintf (stream
, "\t.set %s,%s\n", old_name
, name
);
38961 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
38962 function names from <foo>l to <foo>f128 if the default long double type is
38963 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
38964 include file switches the names on systems that support long double as IEEE
38965 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
38966 In the future, glibc will export names like __ieee128_sinf128 and we can
38967 switch to using those instead of using sinf128, which pollutes the user's
38970 This will switch the names for Fortran math functions as well (which doesn't
38971 use math.h). However, Fortran needs other changes to the compiler and
38972 library before you can switch the real*16 type at compile time.
38974 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
38975 only do this if the default is that long double is IBM extended double, and
38976 the user asked for IEEE 128-bit. */
38979 rs6000_mangle_decl_assembler_name (tree decl
, tree id
)
38981 if (!TARGET_IEEEQUAD_DEFAULT
&& TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
38982 && TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_IS_BUILTIN (decl
) )
38984 size_t len
= IDENTIFIER_LENGTH (id
);
38985 const char *name
= IDENTIFIER_POINTER (id
);
38987 if (name
[len
- 1] == 'l')
38989 bool uses_ieee128_p
= false;
38990 tree type
= TREE_TYPE (decl
);
38991 machine_mode ret_mode
= TYPE_MODE (type
);
38993 /* See if the function returns a IEEE 128-bit floating point type or
38995 if (ret_mode
== TFmode
|| ret_mode
== TCmode
)
38996 uses_ieee128_p
= true;
38999 function_args_iterator args_iter
;
39002 /* See if the function passes a IEEE 128-bit floating point type
39003 or complex type. */
39004 FOREACH_FUNCTION_ARGS (type
, arg
, args_iter
)
39006 machine_mode arg_mode
= TYPE_MODE (arg
);
39007 if (arg_mode
== TFmode
|| arg_mode
== TCmode
)
39009 uses_ieee128_p
= true;
39015 /* If we passed or returned an IEEE 128-bit floating point type,
39016 change the name. */
39017 if (uses_ieee128_p
)
39019 char *name2
= (char *) alloca (len
+ 4);
39020 memcpy (name2
, name
, len
- 1);
39021 strcpy (name2
+ len
- 1, "f128");
39022 id
= get_identifier (name2
);
39031 struct gcc_target targetm
= TARGET_INITIALIZER
;
39033 #include "gt-rs6000.h"