1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 #include "tree-ssanames.h"
87 /* This file should be included last. */
88 #include "target-def.h"
90 #ifndef TARGET_NO_PROTOTYPE
91 #define TARGET_NO_PROTOTYPE 0
94 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
95 systems will also set long double to be IEEE 128-bit. AIX and Darwin
96 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
97 those systems will not pick up this default. This needs to be after all
98 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
100 #ifndef TARGET_IEEEQUAD_DEFAULT
101 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
102 #define TARGET_IEEEQUAD_DEFAULT 1
104 #define TARGET_IEEEQUAD_DEFAULT 0
108 static pad_direction
rs6000_function_arg_padding (machine_mode
, const_tree
);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack
{
112 int reload_completed
; /* stack info won't change from here on */
113 int first_gp_reg_save
; /* first callee saved GP register used */
114 int first_fp_reg_save
; /* first callee saved FP register used */
115 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
116 int lr_save_p
; /* true if the link reg needs to be saved */
117 int cr_save_p
; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask
; /* mask of vec registers to save */
119 int push_p
; /* true if we need to allocate stack space */
120 int calls_p
; /* true if the function makes any calls */
121 int world_save_p
; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi
; /* which ABI to use */
124 int gp_save_offset
; /* offset to save GP regs from initial SP */
125 int fp_save_offset
; /* offset to save FP regs from initial SP */
126 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset
; /* offset to save LR from initial SP */
128 int cr_save_offset
; /* offset to save CR from initial SP */
129 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset
; /* offset to save the varargs registers */
131 int ehrd_offset
; /* offset to EH return data */
132 int ehcr_offset
; /* offset to EH CR field data */
133 int reg_size
; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size
; /* variable save area size */
135 int parm_size
; /* outgoing parameter size */
136 int save_size
; /* save area size */
137 int fixed_size
; /* fixed size of stack frame */
138 int gp_size
; /* size of saved GP registers */
139 int fp_size
; /* size of saved FP registers */
140 int altivec_size
; /* size of saved AltiVec registers */
141 int cr_size
; /* size to hold CR if not in fixed area */
142 int vrsave_size
; /* size to hold VRSAVE */
143 int altivec_padding_size
; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame
;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue
;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset
;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer
;
166 bool split_stack_argp_used
;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed
;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately
[32];
174 bool fpr_is_wrapped_separately
[32];
175 bool lr_is_wrapped_separately
;
176 bool toc_is_wrapped_separately
;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load
;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined
;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno
;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno
= 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode
;
203 /* Note whether IEEE 128-bit floating point was passed or returned, either as
204 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
205 floating point. We changed the default C++ mangling for these types and we
206 may want to generate a weak alias of the old mangling (U10__float128) to the
207 new mangling (u9__ieee128). */
208 static bool rs6000_passes_ieee128
;
211 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
212 name used in current releases (i.e. u9__ieee128). */
213 static bool ieee128_mangling_gcc_8_1
;
215 /* Width in bits of a pointer. */
216 unsigned rs6000_pointer_size
;
218 #ifdef HAVE_AS_GNU_ATTRIBUTE
219 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
220 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
222 /* Flag whether floating point values have been passed/returned.
223 Note that this doesn't say whether fprs are used, since the
224 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
225 should be set for soft-float values passed in gprs and ieee128
226 values passed in vsx registers. */
227 static bool rs6000_passes_float
;
228 static bool rs6000_passes_long_double
;
229 /* Flag whether vector values have been passed/returned. */
230 static bool rs6000_passes_vector
;
231 /* Flag whether small (<= 8 byte) structures have been returned. */
232 static bool rs6000_returns_struct
;
235 /* Value is TRUE if register/mode pair is acceptable. */
236 static bool rs6000_hard_regno_mode_ok_p
237 [NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
239 /* Maximum number of registers needed for a given register class and mode. */
240 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
242 /* How many registers are needed for a given register and mode. */
243 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
245 /* Map register number to register class. */
246 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
248 static int dbg_cost_ctrl
;
250 /* Built in types. */
251 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
252 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
254 /* Flag to say the TOC is initialized */
255 int toc_initialized
, need_toc_init
;
256 char toc_label_name
[10];
258 /* Cached value of rs6000_variable_issue. This is cached in
259 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
260 static short cached_can_issue_more
;
262 static GTY(()) section
*read_only_data_section
;
263 static GTY(()) section
*private_data_section
;
264 static GTY(()) section
*tls_data_section
;
265 static GTY(()) section
*tls_private_data_section
;
266 static GTY(()) section
*read_only_private_data_section
;
267 static GTY(()) section
*sdata2_section
;
268 static GTY(()) section
*toc_section
;
270 struct builtin_description
272 const HOST_WIDE_INT mask
;
273 const enum insn_code icode
;
274 const char *const name
;
275 const enum rs6000_builtins code
;
278 /* Describe the vector unit used for modes. */
279 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
280 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
282 /* Register classes for various constraints that are based on the target
284 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
286 /* Describe the alignment of a vector. */
287 int rs6000_vector_align
[NUM_MACHINE_MODES
];
289 /* Map selected modes to types for builtins. */
290 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
292 /* What modes to automatically generate reciprocal divide estimate (fre) and
293 reciprocal sqrt (frsqrte) for. */
294 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
296 /* Masks to determine which reciprocal esitmate instructions to generate
298 enum rs6000_recip_mask
{
299 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
300 RECIP_DF_DIV
= 0x002,
301 RECIP_V4SF_DIV
= 0x004,
302 RECIP_V2DF_DIV
= 0x008,
304 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
305 RECIP_DF_RSQRT
= 0x020,
306 RECIP_V4SF_RSQRT
= 0x040,
307 RECIP_V2DF_RSQRT
= 0x080,
309 /* Various combination of flags for -mrecip=xxx. */
311 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
312 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
313 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
315 RECIP_HIGH_PRECISION
= RECIP_ALL
,
317 /* On low precision machines like the power5, don't enable double precision
318 reciprocal square root estimate, since it isn't accurate enough. */
319 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
322 /* -mrecip options. */
325 const char *string
; /* option name */
326 unsigned int mask
; /* mask bits to set */
327 } recip_options
[] = {
328 { "all", RECIP_ALL
},
329 { "none", RECIP_NONE
},
330 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
332 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
333 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
334 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
335 | RECIP_V2DF_RSQRT
) },
336 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
337 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
340 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
346 { "power9", PPC_PLATFORM_POWER9
},
347 { "power8", PPC_PLATFORM_POWER8
},
348 { "power7", PPC_PLATFORM_POWER7
},
349 { "power6x", PPC_PLATFORM_POWER6X
},
350 { "power6", PPC_PLATFORM_POWER6
},
351 { "power5+", PPC_PLATFORM_POWER5_PLUS
},
352 { "power5", PPC_PLATFORM_POWER5
},
353 { "ppc970", PPC_PLATFORM_PPC970
},
354 { "power4", PPC_PLATFORM_POWER4
},
355 { "ppca2", PPC_PLATFORM_PPCA2
},
356 { "ppc476", PPC_PLATFORM_PPC476
},
357 { "ppc464", PPC_PLATFORM_PPC464
},
358 { "ppc440", PPC_PLATFORM_PPC440
},
359 { "ppc405", PPC_PLATFORM_PPC405
},
360 { "ppc-cell-be", PPC_PLATFORM_CELL_BE
}
363 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
369 } cpu_supports_info
[] = {
370 /* AT_HWCAP masks. */
371 { "4xxmac", PPC_FEATURE_HAS_4xxMAC
, 0 },
372 { "altivec", PPC_FEATURE_HAS_ALTIVEC
, 0 },
373 { "arch_2_05", PPC_FEATURE_ARCH_2_05
, 0 },
374 { "arch_2_06", PPC_FEATURE_ARCH_2_06
, 0 },
375 { "archpmu", PPC_FEATURE_PERFMON_COMPAT
, 0 },
376 { "booke", PPC_FEATURE_BOOKE
, 0 },
377 { "cellbe", PPC_FEATURE_CELL_BE
, 0 },
378 { "dfp", PPC_FEATURE_HAS_DFP
, 0 },
379 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE
, 0 },
380 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE
, 0 },
381 { "fpu", PPC_FEATURE_HAS_FPU
, 0 },
382 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP
, 0 },
383 { "mmu", PPC_FEATURE_HAS_MMU
, 0 },
384 { "notb", PPC_FEATURE_NO_TB
, 0 },
385 { "pa6t", PPC_FEATURE_PA6T
, 0 },
386 { "power4", PPC_FEATURE_POWER4
, 0 },
387 { "power5", PPC_FEATURE_POWER5
, 0 },
388 { "power5+", PPC_FEATURE_POWER5_PLUS
, 0 },
389 { "power6x", PPC_FEATURE_POWER6_EXT
, 0 },
390 { "ppc32", PPC_FEATURE_32
, 0 },
391 { "ppc601", PPC_FEATURE_601_INSTR
, 0 },
392 { "ppc64", PPC_FEATURE_64
, 0 },
393 { "ppcle", PPC_FEATURE_PPC_LE
, 0 },
394 { "smt", PPC_FEATURE_SMT
, 0 },
395 { "spe", PPC_FEATURE_HAS_SPE
, 0 },
396 { "true_le", PPC_FEATURE_TRUE_LE
, 0 },
397 { "ucache", PPC_FEATURE_UNIFIED_CACHE
, 0 },
398 { "vsx", PPC_FEATURE_HAS_VSX
, 0 },
400 /* AT_HWCAP2 masks. */
401 { "arch_2_07", PPC_FEATURE2_ARCH_2_07
, 1 },
402 { "dscr", PPC_FEATURE2_HAS_DSCR
, 1 },
403 { "ebb", PPC_FEATURE2_HAS_EBB
, 1 },
404 { "htm", PPC_FEATURE2_HAS_HTM
, 1 },
405 { "htm-nosc", PPC_FEATURE2_HTM_NOSC
, 1 },
406 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND
, 1 },
407 { "isel", PPC_FEATURE2_HAS_ISEL
, 1 },
408 { "tar", PPC_FEATURE2_HAS_TAR
, 1 },
409 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO
, 1 },
410 { "arch_3_00", PPC_FEATURE2_ARCH_3_00
, 1 },
411 { "ieee128", PPC_FEATURE2_HAS_IEEE128
, 1 },
412 { "darn", PPC_FEATURE2_DARN
, 1 },
413 { "scv", PPC_FEATURE2_SCV
, 1 }
416 /* On PowerPC, we have a limited number of target clones that we care about
417 which means we can use an array to hold the options, rather than having more
418 elaborate data structures to identify each possible variation. Order the
419 clones from the default to the highest ISA. */
421 CLONE_DEFAULT
= 0, /* default clone. */
422 CLONE_ISA_2_05
, /* ISA 2.05 (power6). */
423 CLONE_ISA_2_06
, /* ISA 2.06 (power7). */
424 CLONE_ISA_2_07
, /* ISA 2.07 (power8). */
425 CLONE_ISA_3_00
, /* ISA 3.00 (power9). */
429 /* Map compiler ISA bits into HWCAP names. */
431 HOST_WIDE_INT isa_mask
; /* rs6000_isa mask */
432 const char *name
; /* name to use in __builtin_cpu_supports. */
435 static const struct clone_map rs6000_clone_map
[CLONE_MAX
] = {
436 { 0, "" }, /* Default options. */
437 { OPTION_MASK_CMPB
, "arch_2_05" }, /* ISA 2.05 (power6). */
438 { OPTION_MASK_POPCNTD
, "arch_2_06" }, /* ISA 2.06 (power7). */
439 { OPTION_MASK_P8_VECTOR
, "arch_2_07" }, /* ISA 2.07 (power8). */
440 { OPTION_MASK_P9_VECTOR
, "arch_3_00" }, /* ISA 3.00 (power9). */
444 /* Newer LIBCs explicitly export this symbol to declare that they provide
445 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
446 reference to this symbol whenever we expand a CPU builtin, so that
447 we never link against an old LIBC. */
448 const char *tcb_verification_symbol
= "__parse_hwcap_and_convert_at_platform";
450 /* True if we have expanded a CPU builtin. */
453 /* Pointer to function (in rs6000-c.c) that can define or undefine target
454 macros that have changed. Languages that don't support the preprocessor
455 don't link in rs6000-c.c, so we can't call it directly. */
456 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
458 /* Simplfy register classes into simpler classifications. We assume
459 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
460 check for standard register classes (gpr/floating/altivec/vsx) and
461 floating/vector classes (float/altivec/vsx). */
463 enum rs6000_reg_type
{
474 /* Map register class to register type. */
475 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
477 /* First/last register type for the 'normal' register types (i.e. general
478 purpose, floating point, altivec, and VSX registers). */
479 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
481 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
484 /* Register classes we care about in secondary reload or go if legitimate
485 address. We only need to worry about GPR, FPR, and Altivec registers here,
486 along an ANY field that is the OR of the 3 register classes. */
488 enum rs6000_reload_reg_type
{
489 RELOAD_REG_GPR
, /* General purpose registers. */
490 RELOAD_REG_FPR
, /* Traditional floating point regs. */
491 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
492 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
496 /* For setting up register classes, loop through the 3 register classes mapping
497 into real registers, and skip the ANY class, which is just an OR of the
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
502 /* Map reload register type to a register in the register class. */
503 struct reload_reg_map_type
{
504 const char *name
; /* Register class name. */
505 int reg
; /* Register in the register class. */
508 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
509 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
510 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
511 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
512 { "Any", -1 }, /* RELOAD_REG_ANY. */
515 /* Mask bits for each register class, indexed per mode. Historically the
516 compiler has been more restrictive which types can do PRE_MODIFY instead of
517 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
518 typedef unsigned char addr_mask_type
;
520 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
521 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
522 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
523 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
526 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
527 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
529 /* Register type masks based on the type, of valid addressing modes. */
530 struct rs6000_reg_addr
{
531 enum insn_code reload_load
; /* INSN to reload for loading. */
532 enum insn_code reload_store
; /* INSN to reload for storing. */
533 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
534 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
535 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
536 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
537 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
540 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
542 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
544 mode_supports_pre_incdec_p (machine_mode mode
)
546 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
550 /* Helper function to say whether a mode supports PRE_MODIFY. */
552 mode_supports_pre_modify_p (machine_mode mode
)
554 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
558 /* Return true if we have D-form addressing in altivec registers. */
560 mode_supports_vmx_dform (machine_mode mode
)
562 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_OFFSET
) != 0);
565 /* Return true if we have D-form addressing in VSX registers. This addressing
566 is more limited than normal d-form addressing in that the offset must be
567 aligned on a 16-byte boundary. */
569 mode_supports_dq_form (machine_mode mode
)
571 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_QUAD_OFFSET
)
575 /* Given that there exists at least one variable that is set (produced)
576 by OUT_INSN and read (consumed) by IN_INSN, return true iff
577 IN_INSN represents one or more memory store operations and none of
578 the variables set by OUT_INSN is used by IN_INSN as the address of a
579 store operation. If either IN_INSN or OUT_INSN does not represent
580 a "single" RTL SET expression (as loosely defined by the
581 implementation of the single_set function) or a PARALLEL with only
582 SETs, CLOBBERs, and USEs inside, this function returns false.
584 This rs6000-specific version of store_data_bypass_p checks for
585 certain conditions that result in assertion failures (and internal
586 compiler errors) in the generic store_data_bypass_p function and
587 returns false rather than calling store_data_bypass_p if one of the
588 problematic conditions is detected. */
591 rs6000_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
598 in_set
= single_set (in_insn
);
601 if (MEM_P (SET_DEST (in_set
)))
603 out_set
= single_set (out_insn
);
606 out_pat
= PATTERN (out_insn
);
607 if (GET_CODE (out_pat
) == PARALLEL
)
609 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
611 out_exp
= XVECEXP (out_pat
, 0, i
);
612 if ((GET_CODE (out_exp
) == CLOBBER
)
613 || (GET_CODE (out_exp
) == USE
))
615 else if (GET_CODE (out_exp
) != SET
)
624 in_pat
= PATTERN (in_insn
);
625 if (GET_CODE (in_pat
) != PARALLEL
)
628 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
630 in_exp
= XVECEXP (in_pat
, 0, i
);
631 if ((GET_CODE (in_exp
) == CLOBBER
) || (GET_CODE (in_exp
) == USE
))
633 else if (GET_CODE (in_exp
) != SET
)
636 if (MEM_P (SET_DEST (in_exp
)))
638 out_set
= single_set (out_insn
);
641 out_pat
= PATTERN (out_insn
);
642 if (GET_CODE (out_pat
) != PARALLEL
)
644 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
646 out_exp
= XVECEXP (out_pat
, 0, j
);
647 if ((GET_CODE (out_exp
) == CLOBBER
)
648 || (GET_CODE (out_exp
) == USE
))
650 else if (GET_CODE (out_exp
) != SET
)
657 return store_data_bypass_p (out_insn
, in_insn
);
661 /* Processor costs (relative to an add) */
663 const struct processor_costs
*rs6000_cost
;
665 /* Instruction size costs on 32bit processors. */
667 struct processor_costs size32_cost
= {
668 COSTS_N_INSNS (1), /* mulsi */
669 COSTS_N_INSNS (1), /* mulsi_const */
670 COSTS_N_INSNS (1), /* mulsi_const9 */
671 COSTS_N_INSNS (1), /* muldi */
672 COSTS_N_INSNS (1), /* divsi */
673 COSTS_N_INSNS (1), /* divdi */
674 COSTS_N_INSNS (1), /* fp */
675 COSTS_N_INSNS (1), /* dmul */
676 COSTS_N_INSNS (1), /* sdiv */
677 COSTS_N_INSNS (1), /* ddiv */
678 32, /* cache line size */
682 0, /* SF->DF convert */
685 /* Instruction size costs on 64bit processors. */
687 struct processor_costs size64_cost
= {
688 COSTS_N_INSNS (1), /* mulsi */
689 COSTS_N_INSNS (1), /* mulsi_const */
690 COSTS_N_INSNS (1), /* mulsi_const9 */
691 COSTS_N_INSNS (1), /* muldi */
692 COSTS_N_INSNS (1), /* divsi */
693 COSTS_N_INSNS (1), /* divdi */
694 COSTS_N_INSNS (1), /* fp */
695 COSTS_N_INSNS (1), /* dmul */
696 COSTS_N_INSNS (1), /* sdiv */
697 COSTS_N_INSNS (1), /* ddiv */
698 128, /* cache line size */
702 0, /* SF->DF convert */
705 /* Instruction costs on RS64A processors. */
707 struct processor_costs rs64a_cost
= {
708 COSTS_N_INSNS (20), /* mulsi */
709 COSTS_N_INSNS (12), /* mulsi_const */
710 COSTS_N_INSNS (8), /* mulsi_const9 */
711 COSTS_N_INSNS (34), /* muldi */
712 COSTS_N_INSNS (65), /* divsi */
713 COSTS_N_INSNS (67), /* divdi */
714 COSTS_N_INSNS (4), /* fp */
715 COSTS_N_INSNS (4), /* dmul */
716 COSTS_N_INSNS (31), /* sdiv */
717 COSTS_N_INSNS (31), /* ddiv */
718 128, /* cache line size */
722 0, /* SF->DF convert */
725 /* Instruction costs on MPCCORE processors. */
727 struct processor_costs mpccore_cost
= {
728 COSTS_N_INSNS (2), /* mulsi */
729 COSTS_N_INSNS (2), /* mulsi_const */
730 COSTS_N_INSNS (2), /* mulsi_const9 */
731 COSTS_N_INSNS (2), /* muldi */
732 COSTS_N_INSNS (6), /* divsi */
733 COSTS_N_INSNS (6), /* divdi */
734 COSTS_N_INSNS (4), /* fp */
735 COSTS_N_INSNS (5), /* dmul */
736 COSTS_N_INSNS (10), /* sdiv */
737 COSTS_N_INSNS (17), /* ddiv */
738 32, /* cache line size */
742 0, /* SF->DF convert */
745 /* Instruction costs on PPC403 processors. */
747 struct processor_costs ppc403_cost
= {
748 COSTS_N_INSNS (4), /* mulsi */
749 COSTS_N_INSNS (4), /* mulsi_const */
750 COSTS_N_INSNS (4), /* mulsi_const9 */
751 COSTS_N_INSNS (4), /* muldi */
752 COSTS_N_INSNS (33), /* divsi */
753 COSTS_N_INSNS (33), /* divdi */
754 COSTS_N_INSNS (11), /* fp */
755 COSTS_N_INSNS (11), /* dmul */
756 COSTS_N_INSNS (11), /* sdiv */
757 COSTS_N_INSNS (11), /* ddiv */
758 32, /* cache line size */
762 0, /* SF->DF convert */
765 /* Instruction costs on PPC405 processors. */
767 struct processor_costs ppc405_cost
= {
768 COSTS_N_INSNS (5), /* mulsi */
769 COSTS_N_INSNS (4), /* mulsi_const */
770 COSTS_N_INSNS (3), /* mulsi_const9 */
771 COSTS_N_INSNS (5), /* muldi */
772 COSTS_N_INSNS (35), /* divsi */
773 COSTS_N_INSNS (35), /* divdi */
774 COSTS_N_INSNS (11), /* fp */
775 COSTS_N_INSNS (11), /* dmul */
776 COSTS_N_INSNS (11), /* sdiv */
777 COSTS_N_INSNS (11), /* ddiv */
778 32, /* cache line size */
782 0, /* SF->DF convert */
785 /* Instruction costs on PPC440 processors. */
787 struct processor_costs ppc440_cost
= {
788 COSTS_N_INSNS (3), /* mulsi */
789 COSTS_N_INSNS (2), /* mulsi_const */
790 COSTS_N_INSNS (2), /* mulsi_const9 */
791 COSTS_N_INSNS (3), /* muldi */
792 COSTS_N_INSNS (34), /* divsi */
793 COSTS_N_INSNS (34), /* divdi */
794 COSTS_N_INSNS (5), /* fp */
795 COSTS_N_INSNS (5), /* dmul */
796 COSTS_N_INSNS (19), /* sdiv */
797 COSTS_N_INSNS (33), /* ddiv */
798 32, /* cache line size */
802 0, /* SF->DF convert */
805 /* Instruction costs on PPC476 processors. */
807 struct processor_costs ppc476_cost
= {
808 COSTS_N_INSNS (4), /* mulsi */
809 COSTS_N_INSNS (4), /* mulsi_const */
810 COSTS_N_INSNS (4), /* mulsi_const9 */
811 COSTS_N_INSNS (4), /* muldi */
812 COSTS_N_INSNS (11), /* divsi */
813 COSTS_N_INSNS (11), /* divdi */
814 COSTS_N_INSNS (6), /* fp */
815 COSTS_N_INSNS (6), /* dmul */
816 COSTS_N_INSNS (19), /* sdiv */
817 COSTS_N_INSNS (33), /* ddiv */
818 32, /* l1 cache line size */
822 0, /* SF->DF convert */
825 /* Instruction costs on PPC601 processors. */
827 struct processor_costs ppc601_cost
= {
828 COSTS_N_INSNS (5), /* mulsi */
829 COSTS_N_INSNS (5), /* mulsi_const */
830 COSTS_N_INSNS (5), /* mulsi_const9 */
831 COSTS_N_INSNS (5), /* muldi */
832 COSTS_N_INSNS (36), /* divsi */
833 COSTS_N_INSNS (36), /* divdi */
834 COSTS_N_INSNS (4), /* fp */
835 COSTS_N_INSNS (5), /* dmul */
836 COSTS_N_INSNS (17), /* sdiv */
837 COSTS_N_INSNS (31), /* ddiv */
838 32, /* cache line size */
842 0, /* SF->DF convert */
845 /* Instruction costs on PPC603 processors. */
847 struct processor_costs ppc603_cost
= {
848 COSTS_N_INSNS (5), /* mulsi */
849 COSTS_N_INSNS (3), /* mulsi_const */
850 COSTS_N_INSNS (2), /* mulsi_const9 */
851 COSTS_N_INSNS (5), /* muldi */
852 COSTS_N_INSNS (37), /* divsi */
853 COSTS_N_INSNS (37), /* divdi */
854 COSTS_N_INSNS (3), /* fp */
855 COSTS_N_INSNS (4), /* dmul */
856 COSTS_N_INSNS (18), /* sdiv */
857 COSTS_N_INSNS (33), /* ddiv */
858 32, /* cache line size */
862 0, /* SF->DF convert */
865 /* Instruction costs on PPC604 processors. */
867 struct processor_costs ppc604_cost
= {
868 COSTS_N_INSNS (4), /* mulsi */
869 COSTS_N_INSNS (4), /* mulsi_const */
870 COSTS_N_INSNS (4), /* mulsi_const9 */
871 COSTS_N_INSNS (4), /* muldi */
872 COSTS_N_INSNS (20), /* divsi */
873 COSTS_N_INSNS (20), /* divdi */
874 COSTS_N_INSNS (3), /* fp */
875 COSTS_N_INSNS (3), /* dmul */
876 COSTS_N_INSNS (18), /* sdiv */
877 COSTS_N_INSNS (32), /* ddiv */
878 32, /* cache line size */
882 0, /* SF->DF convert */
885 /* Instruction costs on PPC604e processors. */
887 struct processor_costs ppc604e_cost
= {
888 COSTS_N_INSNS (2), /* mulsi */
889 COSTS_N_INSNS (2), /* mulsi_const */
890 COSTS_N_INSNS (2), /* mulsi_const9 */
891 COSTS_N_INSNS (2), /* muldi */
892 COSTS_N_INSNS (20), /* divsi */
893 COSTS_N_INSNS (20), /* divdi */
894 COSTS_N_INSNS (3), /* fp */
895 COSTS_N_INSNS (3), /* dmul */
896 COSTS_N_INSNS (18), /* sdiv */
897 COSTS_N_INSNS (32), /* ddiv */
898 32, /* cache line size */
902 0, /* SF->DF convert */
905 /* Instruction costs on PPC620 processors. */
907 struct processor_costs ppc620_cost
= {
908 COSTS_N_INSNS (5), /* mulsi */
909 COSTS_N_INSNS (4), /* mulsi_const */
910 COSTS_N_INSNS (3), /* mulsi_const9 */
911 COSTS_N_INSNS (7), /* muldi */
912 COSTS_N_INSNS (21), /* divsi */
913 COSTS_N_INSNS (37), /* divdi */
914 COSTS_N_INSNS (3), /* fp */
915 COSTS_N_INSNS (3), /* dmul */
916 COSTS_N_INSNS (18), /* sdiv */
917 COSTS_N_INSNS (32), /* ddiv */
918 128, /* cache line size */
922 0, /* SF->DF convert */
925 /* Instruction costs on PPC630 processors. */
927 struct processor_costs ppc630_cost
= {
928 COSTS_N_INSNS (5), /* mulsi */
929 COSTS_N_INSNS (4), /* mulsi_const */
930 COSTS_N_INSNS (3), /* mulsi_const9 */
931 COSTS_N_INSNS (7), /* muldi */
932 COSTS_N_INSNS (21), /* divsi */
933 COSTS_N_INSNS (37), /* divdi */
934 COSTS_N_INSNS (3), /* fp */
935 COSTS_N_INSNS (3), /* dmul */
936 COSTS_N_INSNS (17), /* sdiv */
937 COSTS_N_INSNS (21), /* ddiv */
938 128, /* cache line size */
942 0, /* SF->DF convert */
945 /* Instruction costs on Cell processor. */
946 /* COSTS_N_INSNS (1) ~ one add. */
948 struct processor_costs ppccell_cost
= {
949 COSTS_N_INSNS (9/2)+2, /* mulsi */
950 COSTS_N_INSNS (6/2), /* mulsi_const */
951 COSTS_N_INSNS (6/2), /* mulsi_const9 */
952 COSTS_N_INSNS (15/2)+2, /* muldi */
953 COSTS_N_INSNS (38/2), /* divsi */
954 COSTS_N_INSNS (70/2), /* divdi */
955 COSTS_N_INSNS (10/2), /* fp */
956 COSTS_N_INSNS (10/2), /* dmul */
957 COSTS_N_INSNS (74/2), /* sdiv */
958 COSTS_N_INSNS (74/2), /* ddiv */
959 128, /* cache line size */
963 0, /* SF->DF convert */
966 /* Instruction costs on PPC750 and PPC7400 processors. */
968 struct processor_costs ppc750_cost
= {
969 COSTS_N_INSNS (5), /* mulsi */
970 COSTS_N_INSNS (3), /* mulsi_const */
971 COSTS_N_INSNS (2), /* mulsi_const9 */
972 COSTS_N_INSNS (5), /* muldi */
973 COSTS_N_INSNS (17), /* divsi */
974 COSTS_N_INSNS (17), /* divdi */
975 COSTS_N_INSNS (3), /* fp */
976 COSTS_N_INSNS (3), /* dmul */
977 COSTS_N_INSNS (17), /* sdiv */
978 COSTS_N_INSNS (31), /* ddiv */
979 32, /* cache line size */
983 0, /* SF->DF convert */
986 /* Instruction costs on PPC7450 processors. */
988 struct processor_costs ppc7450_cost
= {
989 COSTS_N_INSNS (4), /* mulsi */
990 COSTS_N_INSNS (3), /* mulsi_const */
991 COSTS_N_INSNS (3), /* mulsi_const9 */
992 COSTS_N_INSNS (4), /* muldi */
993 COSTS_N_INSNS (23), /* divsi */
994 COSTS_N_INSNS (23), /* divdi */
995 COSTS_N_INSNS (5), /* fp */
996 COSTS_N_INSNS (5), /* dmul */
997 COSTS_N_INSNS (21), /* sdiv */
998 COSTS_N_INSNS (35), /* ddiv */
999 32, /* cache line size */
1001 1024, /* l2 cache */
1003 0, /* SF->DF convert */
1006 /* Instruction costs on PPC8540 processors. */
1008 struct processor_costs ppc8540_cost
= {
1009 COSTS_N_INSNS (4), /* mulsi */
1010 COSTS_N_INSNS (4), /* mulsi_const */
1011 COSTS_N_INSNS (4), /* mulsi_const9 */
1012 COSTS_N_INSNS (4), /* muldi */
1013 COSTS_N_INSNS (19), /* divsi */
1014 COSTS_N_INSNS (19), /* divdi */
1015 COSTS_N_INSNS (4), /* fp */
1016 COSTS_N_INSNS (4), /* dmul */
1017 COSTS_N_INSNS (29), /* sdiv */
1018 COSTS_N_INSNS (29), /* ddiv */
1019 32, /* cache line size */
1022 1, /* prefetch streams /*/
1023 0, /* SF->DF convert */
1026 /* Instruction costs on E300C2 and E300C3 cores. */
1028 struct processor_costs ppce300c2c3_cost
= {
1029 COSTS_N_INSNS (4), /* mulsi */
1030 COSTS_N_INSNS (4), /* mulsi_const */
1031 COSTS_N_INSNS (4), /* mulsi_const9 */
1032 COSTS_N_INSNS (4), /* muldi */
1033 COSTS_N_INSNS (19), /* divsi */
1034 COSTS_N_INSNS (19), /* divdi */
1035 COSTS_N_INSNS (3), /* fp */
1036 COSTS_N_INSNS (4), /* dmul */
1037 COSTS_N_INSNS (18), /* sdiv */
1038 COSTS_N_INSNS (33), /* ddiv */
1042 1, /* prefetch streams /*/
1043 0, /* SF->DF convert */
1046 /* Instruction costs on PPCE500MC processors. */
1048 struct processor_costs ppce500mc_cost
= {
1049 COSTS_N_INSNS (4), /* mulsi */
1050 COSTS_N_INSNS (4), /* mulsi_const */
1051 COSTS_N_INSNS (4), /* mulsi_const9 */
1052 COSTS_N_INSNS (4), /* muldi */
1053 COSTS_N_INSNS (14), /* divsi */
1054 COSTS_N_INSNS (14), /* divdi */
1055 COSTS_N_INSNS (8), /* fp */
1056 COSTS_N_INSNS (10), /* dmul */
1057 COSTS_N_INSNS (36), /* sdiv */
1058 COSTS_N_INSNS (66), /* ddiv */
1059 64, /* cache line size */
1062 1, /* prefetch streams /*/
1063 0, /* SF->DF convert */
1066 /* Instruction costs on PPCE500MC64 processors. */
1068 struct processor_costs ppce500mc64_cost
= {
1069 COSTS_N_INSNS (4), /* mulsi */
1070 COSTS_N_INSNS (4), /* mulsi_const */
1071 COSTS_N_INSNS (4), /* mulsi_const9 */
1072 COSTS_N_INSNS (4), /* muldi */
1073 COSTS_N_INSNS (14), /* divsi */
1074 COSTS_N_INSNS (14), /* divdi */
1075 COSTS_N_INSNS (4), /* fp */
1076 COSTS_N_INSNS (10), /* dmul */
1077 COSTS_N_INSNS (36), /* sdiv */
1078 COSTS_N_INSNS (66), /* ddiv */
1079 64, /* cache line size */
1082 1, /* prefetch streams /*/
1083 0, /* SF->DF convert */
1086 /* Instruction costs on PPCE5500 processors. */
1088 struct processor_costs ppce5500_cost
= {
1089 COSTS_N_INSNS (5), /* mulsi */
1090 COSTS_N_INSNS (5), /* mulsi_const */
1091 COSTS_N_INSNS (4), /* mulsi_const9 */
1092 COSTS_N_INSNS (5), /* muldi */
1093 COSTS_N_INSNS (14), /* divsi */
1094 COSTS_N_INSNS (14), /* divdi */
1095 COSTS_N_INSNS (7), /* fp */
1096 COSTS_N_INSNS (10), /* dmul */
1097 COSTS_N_INSNS (36), /* sdiv */
1098 COSTS_N_INSNS (66), /* ddiv */
1099 64, /* cache line size */
1102 1, /* prefetch streams /*/
1103 0, /* SF->DF convert */
1106 /* Instruction costs on PPCE6500 processors. */
1108 struct processor_costs ppce6500_cost
= {
1109 COSTS_N_INSNS (5), /* mulsi */
1110 COSTS_N_INSNS (5), /* mulsi_const */
1111 COSTS_N_INSNS (4), /* mulsi_const9 */
1112 COSTS_N_INSNS (5), /* muldi */
1113 COSTS_N_INSNS (14), /* divsi */
1114 COSTS_N_INSNS (14), /* divdi */
1115 COSTS_N_INSNS (7), /* fp */
1116 COSTS_N_INSNS (10), /* dmul */
1117 COSTS_N_INSNS (36), /* sdiv */
1118 COSTS_N_INSNS (66), /* ddiv */
1119 64, /* cache line size */
1122 1, /* prefetch streams /*/
1123 0, /* SF->DF convert */
1126 /* Instruction costs on AppliedMicro Titan processors. */
1128 struct processor_costs titan_cost
= {
1129 COSTS_N_INSNS (5), /* mulsi */
1130 COSTS_N_INSNS (5), /* mulsi_const */
1131 COSTS_N_INSNS (5), /* mulsi_const9 */
1132 COSTS_N_INSNS (5), /* muldi */
1133 COSTS_N_INSNS (18), /* divsi */
1134 COSTS_N_INSNS (18), /* divdi */
1135 COSTS_N_INSNS (10), /* fp */
1136 COSTS_N_INSNS (10), /* dmul */
1137 COSTS_N_INSNS (46), /* sdiv */
1138 COSTS_N_INSNS (72), /* ddiv */
1139 32, /* cache line size */
1142 1, /* prefetch streams /*/
1143 0, /* SF->DF convert */
1146 /* Instruction costs on POWER4 and POWER5 processors. */
1148 struct processor_costs power4_cost
= {
1149 COSTS_N_INSNS (3), /* mulsi */
1150 COSTS_N_INSNS (2), /* mulsi_const */
1151 COSTS_N_INSNS (2), /* mulsi_const9 */
1152 COSTS_N_INSNS (4), /* muldi */
1153 COSTS_N_INSNS (18), /* divsi */
1154 COSTS_N_INSNS (34), /* divdi */
1155 COSTS_N_INSNS (3), /* fp */
1156 COSTS_N_INSNS (3), /* dmul */
1157 COSTS_N_INSNS (17), /* sdiv */
1158 COSTS_N_INSNS (17), /* ddiv */
1159 128, /* cache line size */
1161 1024, /* l2 cache */
1162 8, /* prefetch streams /*/
1163 0, /* SF->DF convert */
1166 /* Instruction costs on POWER6 processors. */
1168 struct processor_costs power6_cost
= {
1169 COSTS_N_INSNS (8), /* mulsi */
1170 COSTS_N_INSNS (8), /* mulsi_const */
1171 COSTS_N_INSNS (8), /* mulsi_const9 */
1172 COSTS_N_INSNS (8), /* muldi */
1173 COSTS_N_INSNS (22), /* divsi */
1174 COSTS_N_INSNS (28), /* divdi */
1175 COSTS_N_INSNS (3), /* fp */
1176 COSTS_N_INSNS (3), /* dmul */
1177 COSTS_N_INSNS (13), /* sdiv */
1178 COSTS_N_INSNS (16), /* ddiv */
1179 128, /* cache line size */
1181 2048, /* l2 cache */
1182 16, /* prefetch streams */
1183 0, /* SF->DF convert */
1186 /* Instruction costs on POWER7 processors. */
1188 struct processor_costs power7_cost
= {
1189 COSTS_N_INSNS (2), /* mulsi */
1190 COSTS_N_INSNS (2), /* mulsi_const */
1191 COSTS_N_INSNS (2), /* mulsi_const9 */
1192 COSTS_N_INSNS (2), /* muldi */
1193 COSTS_N_INSNS (18), /* divsi */
1194 COSTS_N_INSNS (34), /* divdi */
1195 COSTS_N_INSNS (3), /* fp */
1196 COSTS_N_INSNS (3), /* dmul */
1197 COSTS_N_INSNS (13), /* sdiv */
1198 COSTS_N_INSNS (16), /* ddiv */
1199 128, /* cache line size */
1202 12, /* prefetch streams */
1203 COSTS_N_INSNS (3), /* SF->DF convert */
1206 /* Instruction costs on POWER8 processors. */
1208 struct processor_costs power8_cost
= {
1209 COSTS_N_INSNS (3), /* mulsi */
1210 COSTS_N_INSNS (3), /* mulsi_const */
1211 COSTS_N_INSNS (3), /* mulsi_const9 */
1212 COSTS_N_INSNS (3), /* muldi */
1213 COSTS_N_INSNS (19), /* divsi */
1214 COSTS_N_INSNS (35), /* divdi */
1215 COSTS_N_INSNS (3), /* fp */
1216 COSTS_N_INSNS (3), /* dmul */
1217 COSTS_N_INSNS (14), /* sdiv */
1218 COSTS_N_INSNS (17), /* ddiv */
1219 128, /* cache line size */
1222 12, /* prefetch streams */
1223 COSTS_N_INSNS (3), /* SF->DF convert */
1226 /* Instruction costs on POWER9 processors. */
1228 struct processor_costs power9_cost
= {
1229 COSTS_N_INSNS (3), /* mulsi */
1230 COSTS_N_INSNS (3), /* mulsi_const */
1231 COSTS_N_INSNS (3), /* mulsi_const9 */
1232 COSTS_N_INSNS (3), /* muldi */
1233 COSTS_N_INSNS (8), /* divsi */
1234 COSTS_N_INSNS (12), /* divdi */
1235 COSTS_N_INSNS (3), /* fp */
1236 COSTS_N_INSNS (3), /* dmul */
1237 COSTS_N_INSNS (13), /* sdiv */
1238 COSTS_N_INSNS (18), /* ddiv */
1239 128, /* cache line size */
1242 8, /* prefetch streams */
1243 COSTS_N_INSNS (3), /* SF->DF convert */
1246 /* Instruction costs on POWER A2 processors. */
1248 struct processor_costs ppca2_cost
= {
1249 COSTS_N_INSNS (16), /* mulsi */
1250 COSTS_N_INSNS (16), /* mulsi_const */
1251 COSTS_N_INSNS (16), /* mulsi_const9 */
1252 COSTS_N_INSNS (16), /* muldi */
1253 COSTS_N_INSNS (22), /* divsi */
1254 COSTS_N_INSNS (28), /* divdi */
1255 COSTS_N_INSNS (3), /* fp */
1256 COSTS_N_INSNS (3), /* dmul */
1257 COSTS_N_INSNS (59), /* sdiv */
1258 COSTS_N_INSNS (72), /* ddiv */
1261 2048, /* l2 cache */
1262 16, /* prefetch streams */
1263 0, /* SF->DF convert */
1267 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1268 #undef RS6000_BUILTIN_0
1269 #undef RS6000_BUILTIN_1
1270 #undef RS6000_BUILTIN_2
1271 #undef RS6000_BUILTIN_3
1272 #undef RS6000_BUILTIN_A
1273 #undef RS6000_BUILTIN_D
1274 #undef RS6000_BUILTIN_H
1275 #undef RS6000_BUILTIN_P
1276 #undef RS6000_BUILTIN_X
1278 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1279 { NAME, ICODE, MASK, ATTR },
1281 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1282 { NAME, ICODE, MASK, ATTR },
1284 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1285 { NAME, ICODE, MASK, ATTR },
1287 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 struct rs6000_builtin_info_type
{
1307 const enum insn_code icode
;
1308 const HOST_WIDE_INT mask
;
1309 const unsigned attr
;
1312 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1314 #include "rs6000-builtin.def"
1317 #undef RS6000_BUILTIN_0
1318 #undef RS6000_BUILTIN_1
1319 #undef RS6000_BUILTIN_2
1320 #undef RS6000_BUILTIN_3
1321 #undef RS6000_BUILTIN_A
1322 #undef RS6000_BUILTIN_D
1323 #undef RS6000_BUILTIN_H
1324 #undef RS6000_BUILTIN_P
1325 #undef RS6000_BUILTIN_X
1327 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1328 static tree (*rs6000_veclib_handler
) (combined_fn
, tree
, tree
);
1331 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1332 static struct machine_function
* rs6000_init_machine_status (void);
1333 static int rs6000_ra_ever_killed (void);
1334 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1335 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1336 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1337 static tree
rs6000_builtin_vectorized_libmass (combined_fn
, tree
, tree
);
1338 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1339 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1340 static bool rs6000_debug_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
1341 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1343 static int rs6000_debug_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
1345 static bool is_microcoded_insn (rtx_insn
*);
1346 static bool is_nonpipeline_insn (rtx_insn
*);
1347 static bool is_cracked_insn (rtx_insn
*);
1348 static bool is_load_insn (rtx
, rtx
*);
1349 static bool is_store_insn (rtx
, rtx
*);
1350 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1351 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1352 static bool insn_must_be_first_in_group (rtx_insn
*);
1353 static bool insn_must_be_last_in_group (rtx_insn
*);
1354 static void altivec_init_builtins (void);
1355 static tree
builtin_function_type (machine_mode
, machine_mode
,
1356 machine_mode
, machine_mode
,
1357 enum rs6000_builtins
, const char *name
);
1358 static void rs6000_common_init_builtins (void);
1359 static void htm_init_builtins (void);
1360 static rs6000_stack_t
*rs6000_stack_info (void);
1361 static void is_altivec_return_reg (rtx
, void *);
1362 int easy_vector_constant (rtx
, machine_mode
);
1363 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1364 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1365 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1368 static void macho_branch_islands (void);
1369 static tree
get_prev_label (tree
);
1371 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1373 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1375 static bool rs6000_mode_dependent_address (const_rtx
);
1376 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1377 static bool rs6000_offsettable_memref_p (rtx
, machine_mode
, bool);
1378 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1380 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1383 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1384 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1386 static bool rs6000_debug_secondary_memory_needed (machine_mode
,
1389 static bool rs6000_debug_can_change_mode_class (machine_mode
,
1392 static bool rs6000_save_toc_in_prologue_p (void);
1393 static rtx
rs6000_internal_arg_pointer (void);
1395 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1397 = rs6000_legitimize_reload_address
;
1399 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1400 = rs6000_mode_dependent_address
;
1402 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1404 = rs6000_secondary_reload_class
;
1406 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1407 = rs6000_preferred_reload_class
;
1409 const int INSN_NOT_AVAILABLE
= -1;
1411 static void rs6000_print_isa_options (FILE *, int, const char *,
1413 static void rs6000_print_builtin_options (FILE *, int, const char *,
1415 static HOST_WIDE_INT
rs6000_disable_incompatible_switches (void);
1417 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1418 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1419 enum rs6000_reg_type
,
1421 secondary_reload_info
*,
1423 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1424 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused
));
1425 static tree
rs6000_fold_builtin (tree
, int, tree
*, bool);
1427 /* Hash table stuff for keeping track of TOC entries. */
1429 struct GTY((for_user
)) toc_hash_struct
1431 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1432 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1434 machine_mode key_mode
;
1438 struct toc_hasher
: ggc_ptr_hash
<toc_hash_struct
>
1440 static hashval_t
hash (toc_hash_struct
*);
1441 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1444 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1446 /* Hash table to keep track of the argument types for builtin functions. */
1448 struct GTY((for_user
)) builtin_hash_struct
1451 machine_mode mode
[4]; /* return value + 3 arguments. */
1452 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1455 struct builtin_hasher
: ggc_ptr_hash
<builtin_hash_struct
>
1457 static hashval_t
hash (builtin_hash_struct
*);
1458 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1461 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1464 /* Default register names. */
1465 char rs6000_reg_names
[][8] =
1467 "0", "1", "2", "3", "4", "5", "6", "7",
1468 "8", "9", "10", "11", "12", "13", "14", "15",
1469 "16", "17", "18", "19", "20", "21", "22", "23",
1470 "24", "25", "26", "27", "28", "29", "30", "31",
1471 "0", "1", "2", "3", "4", "5", "6", "7",
1472 "8", "9", "10", "11", "12", "13", "14", "15",
1473 "16", "17", "18", "19", "20", "21", "22", "23",
1474 "24", "25", "26", "27", "28", "29", "30", "31",
1475 "mq", "lr", "ctr","ap",
1476 "0", "1", "2", "3", "4", "5", "6", "7",
1478 /* AltiVec registers. */
1479 "0", "1", "2", "3", "4", "5", "6", "7",
1480 "8", "9", "10", "11", "12", "13", "14", "15",
1481 "16", "17", "18", "19", "20", "21", "22", "23",
1482 "24", "25", "26", "27", "28", "29", "30", "31",
1484 /* Soft frame pointer. */
1486 /* HTM SPR registers. */
1487 "tfhar", "tfiar", "texasr"
1490 #ifdef TARGET_REGNAMES
1491 static const char alt_reg_names
[][8] =
1493 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1494 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1495 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1496 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1497 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1498 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1499 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1500 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1501 "mq", "lr", "ctr", "ap",
1502 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1504 /* AltiVec registers. */
1505 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1506 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1507 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1508 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1510 /* Soft frame pointer. */
1512 /* HTM SPR registers. */
1513 "tfhar", "tfiar", "texasr"
1517 /* Table of valid machine attributes. */
1519 static const struct attribute_spec rs6000_attribute_table
[] =
1521 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1522 affects_type_identity, handler, exclude } */
1523 { "altivec", 1, 1, false, true, false, false,
1524 rs6000_handle_altivec_attribute
, NULL
},
1525 { "longcall", 0, 0, false, true, true, false,
1526 rs6000_handle_longcall_attribute
, NULL
},
1527 { "shortcall", 0, 0, false, true, true, false,
1528 rs6000_handle_longcall_attribute
, NULL
},
1529 { "ms_struct", 0, 0, false, false, false, false,
1530 rs6000_handle_struct_attribute
, NULL
},
1531 { "gcc_struct", 0, 0, false, false, false, false,
1532 rs6000_handle_struct_attribute
, NULL
},
1533 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1534 SUBTARGET_ATTRIBUTE_TABLE
,
1536 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
1539 #ifndef TARGET_PROFILE_KERNEL
1540 #define TARGET_PROFILE_KERNEL 0
1543 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1544 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1546 /* Initialize the GCC target structure. */
1547 #undef TARGET_ATTRIBUTE_TABLE
1548 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1549 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1550 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1551 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1552 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1554 #undef TARGET_ASM_ALIGNED_DI_OP
1555 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1557 /* Default unaligned ops are only provided for ELF. Find the ops needed
1558 for non-ELF systems. */
1559 #ifndef OBJECT_FORMAT_ELF
1561 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1563 #undef TARGET_ASM_UNALIGNED_HI_OP
1564 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1565 #undef TARGET_ASM_UNALIGNED_SI_OP
1566 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1567 #undef TARGET_ASM_UNALIGNED_DI_OP
1568 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1571 #undef TARGET_ASM_UNALIGNED_HI_OP
1572 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1573 #undef TARGET_ASM_UNALIGNED_SI_OP
1574 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1575 #undef TARGET_ASM_UNALIGNED_DI_OP
1576 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1577 #undef TARGET_ASM_ALIGNED_DI_OP
1578 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1582 /* This hook deals with fixups for relocatable code and DI-mode objects
1584 #undef TARGET_ASM_INTEGER
1585 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1587 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1588 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1589 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1592 #undef TARGET_SET_UP_BY_PROLOGUE
1593 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1595 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1596 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1597 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1598 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1599 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1600 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1601 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1602 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1603 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1604 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1605 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1606 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1608 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1609 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1611 #undef TARGET_INTERNAL_ARG_POINTER
1612 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1614 #undef TARGET_HAVE_TLS
1615 #define TARGET_HAVE_TLS HAVE_AS_TLS
1617 #undef TARGET_CANNOT_FORCE_CONST_MEM
1618 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1620 #undef TARGET_DELEGITIMIZE_ADDRESS
1621 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1623 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1624 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1626 #undef TARGET_LEGITIMATE_COMBINED_INSN
1627 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1629 #undef TARGET_ASM_FUNCTION_PROLOGUE
1630 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1631 #undef TARGET_ASM_FUNCTION_EPILOGUE
1632 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1634 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1635 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1637 #undef TARGET_LEGITIMIZE_ADDRESS
1638 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1640 #undef TARGET_SCHED_VARIABLE_ISSUE
1641 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1643 #undef TARGET_SCHED_ISSUE_RATE
1644 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1645 #undef TARGET_SCHED_ADJUST_COST
1646 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1647 #undef TARGET_SCHED_ADJUST_PRIORITY
1648 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1649 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1650 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1651 #undef TARGET_SCHED_INIT
1652 #define TARGET_SCHED_INIT rs6000_sched_init
1653 #undef TARGET_SCHED_FINISH
1654 #define TARGET_SCHED_FINISH rs6000_sched_finish
1655 #undef TARGET_SCHED_REORDER
1656 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1657 #undef TARGET_SCHED_REORDER2
1658 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1660 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1661 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1663 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1664 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1666 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1667 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1668 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1669 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1670 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1671 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1672 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1673 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1675 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1676 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1678 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1679 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1680 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1681 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1682 rs6000_builtin_support_vector_misalignment
1683 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1684 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1685 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1686 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1687 rs6000_builtin_vectorization_cost
1688 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1689 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1690 rs6000_preferred_simd_mode
1691 #undef TARGET_VECTORIZE_INIT_COST
1692 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1693 #undef TARGET_VECTORIZE_ADD_STMT_COST
1694 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1695 #undef TARGET_VECTORIZE_FINISH_COST
1696 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1697 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1698 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1700 #undef TARGET_INIT_BUILTINS
1701 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1702 #undef TARGET_BUILTIN_DECL
1703 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1705 #undef TARGET_FOLD_BUILTIN
1706 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1707 #undef TARGET_GIMPLE_FOLD_BUILTIN
1708 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1710 #undef TARGET_EXPAND_BUILTIN
1711 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1713 #undef TARGET_MANGLE_TYPE
1714 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1716 #undef TARGET_INIT_LIBFUNCS
1717 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1720 #undef TARGET_BINDS_LOCAL_P
1721 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1724 #undef TARGET_MS_BITFIELD_LAYOUT_P
1725 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1727 #undef TARGET_ASM_OUTPUT_MI_THUNK
1728 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1730 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1731 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1733 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1734 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1736 #undef TARGET_REGISTER_MOVE_COST
1737 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1738 #undef TARGET_MEMORY_MOVE_COST
1739 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1740 #undef TARGET_CANNOT_COPY_INSN_P
1741 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1742 #undef TARGET_RTX_COSTS
1743 #define TARGET_RTX_COSTS rs6000_rtx_costs
1744 #undef TARGET_ADDRESS_COST
1745 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1746 #undef TARGET_INSN_COST
1747 #define TARGET_INSN_COST rs6000_insn_cost
1749 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1750 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1752 #undef TARGET_PROMOTE_FUNCTION_MODE
1753 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1755 #undef TARGET_RETURN_IN_MEMORY
1756 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1758 #undef TARGET_RETURN_IN_MSB
1759 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1761 #undef TARGET_SETUP_INCOMING_VARARGS
1762 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1764 /* Always strict argument naming on rs6000. */
1765 #undef TARGET_STRICT_ARGUMENT_NAMING
1766 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1767 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1768 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1769 #undef TARGET_SPLIT_COMPLEX_ARG
1770 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1771 #undef TARGET_MUST_PASS_IN_STACK
1772 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1773 #undef TARGET_PASS_BY_REFERENCE
1774 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1775 #undef TARGET_ARG_PARTIAL_BYTES
1776 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1777 #undef TARGET_FUNCTION_ARG_ADVANCE
1778 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1779 #undef TARGET_FUNCTION_ARG
1780 #define TARGET_FUNCTION_ARG rs6000_function_arg
1781 #undef TARGET_FUNCTION_ARG_PADDING
1782 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1783 #undef TARGET_FUNCTION_ARG_BOUNDARY
1784 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1786 #undef TARGET_BUILD_BUILTIN_VA_LIST
1787 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1789 #undef TARGET_EXPAND_BUILTIN_VA_START
1790 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1792 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1793 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1795 #undef TARGET_EH_RETURN_FILTER_MODE
1796 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1798 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1799 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1801 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1802 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1804 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1805 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1807 #undef TARGET_FLOATN_MODE
1808 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1810 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1811 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1813 #undef TARGET_MD_ASM_ADJUST
1814 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1816 #undef TARGET_OPTION_OVERRIDE
1817 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1819 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1820 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1821 rs6000_builtin_vectorized_function
1823 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1824 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1825 rs6000_builtin_md_vectorized_function
1827 #undef TARGET_STACK_PROTECT_GUARD
1828 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1831 #undef TARGET_STACK_PROTECT_FAIL
1832 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1836 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1837 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1840 /* Use a 32-bit anchor range. This leads to sequences like:
1842 addis tmp,anchor,high
1845 where tmp itself acts as an anchor, and can be shared between
1846 accesses to the same 64k page. */
1847 #undef TARGET_MIN_ANCHOR_OFFSET
1848 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1849 #undef TARGET_MAX_ANCHOR_OFFSET
1850 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1851 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1852 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1853 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1854 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1856 #undef TARGET_BUILTIN_RECIPROCAL
1857 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1859 #undef TARGET_SECONDARY_RELOAD
1860 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1861 #undef TARGET_SECONDARY_MEMORY_NEEDED
1862 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1863 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1864 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1866 #undef TARGET_LEGITIMATE_ADDRESS_P
1867 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1869 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1870 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1872 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1873 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1875 #undef TARGET_CAN_ELIMINATE
1876 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1878 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1879 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1881 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1882 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1884 #undef TARGET_TRAMPOLINE_INIT
1885 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1887 #undef TARGET_FUNCTION_VALUE
1888 #define TARGET_FUNCTION_VALUE rs6000_function_value
1890 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1891 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1893 #undef TARGET_OPTION_SAVE
1894 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1896 #undef TARGET_OPTION_RESTORE
1897 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1899 #undef TARGET_OPTION_PRINT
1900 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1902 #undef TARGET_CAN_INLINE_P
1903 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1905 #undef TARGET_SET_CURRENT_FUNCTION
1906 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1908 #undef TARGET_LEGITIMATE_CONSTANT_P
1909 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1911 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1912 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1914 #undef TARGET_CAN_USE_DOLOOP_P
1915 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1917 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1918 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1920 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1921 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1922 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1923 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1924 #undef TARGET_UNWIND_WORD_MODE
1925 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1927 #undef TARGET_OFFLOAD_OPTIONS
1928 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1930 #undef TARGET_C_MODE_FOR_SUFFIX
1931 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1933 #undef TARGET_INVALID_BINARY_OP
1934 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1936 #undef TARGET_OPTAB_SUPPORTED_P
1937 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1939 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1940 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1942 #undef TARGET_COMPARE_VERSION_PRIORITY
1943 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1945 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1946 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1947 rs6000_generate_version_dispatcher_body
1949 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1950 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1951 rs6000_get_function_versions_dispatcher
1953 #undef TARGET_OPTION_FUNCTION_VERSIONS
1954 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1956 #undef TARGET_HARD_REGNO_NREGS
1957 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1958 #undef TARGET_HARD_REGNO_MODE_OK
1959 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1961 #undef TARGET_MODES_TIEABLE_P
1962 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1964 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1965 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1966 rs6000_hard_regno_call_part_clobbered
1968 #undef TARGET_SLOW_UNALIGNED_ACCESS
1969 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1971 #undef TARGET_CAN_CHANGE_MODE_CLASS
1972 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1974 #undef TARGET_CONSTANT_ALIGNMENT
1975 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1977 #undef TARGET_STARTING_FRAME_OFFSET
1978 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1980 #if TARGET_ELF && RS6000_WEAK
1981 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1982 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1985 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1986 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1988 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1989 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1992 /* Processor table. */
1995 const char *const name
; /* Canonical processor name. */
1996 const enum processor_type processor
; /* Processor type enum value. */
1997 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
2000 static struct rs6000_ptt
const processor_target_table
[] =
2002 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
2003 #include "rs6000-cpus.def"
2007 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2011 rs6000_cpu_name_lookup (const char *name
)
2017 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2018 if (! strcmp (name
, processor_target_table
[i
].name
))
2026 /* Return number of consecutive hard regs needed starting at reg REGNO
2027 to hold something of mode MODE.
2028 This is ordinarily the length in words of a value of mode MODE
2029 but can be less for certain modes in special long registers.
2031 POWER and PowerPC GPRs hold 32 bits worth;
2032 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2035 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
2037 unsigned HOST_WIDE_INT reg_size
;
2039 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2040 128-bit floating point that can go in vector registers, which has VSX
2041 memory addressing. */
2042 if (FP_REGNO_P (regno
))
2043 reg_size
= (VECTOR_MEM_VSX_P (mode
) || FLOAT128_VECTOR_P (mode
)
2044 ? UNITS_PER_VSX_WORD
2045 : UNITS_PER_FP_WORD
);
2047 else if (ALTIVEC_REGNO_P (regno
))
2048 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2051 reg_size
= UNITS_PER_WORD
;
2053 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
2056 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2059 rs6000_hard_regno_mode_ok_uncached (int regno
, machine_mode mode
)
2061 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
2063 if (COMPLEX_MODE_P (mode
))
2064 mode
= GET_MODE_INNER (mode
);
2066 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2067 register combinations, and use PTImode where we need to deal with quad
2068 word memory operations. Don't allow quad words in the argument or frame
2069 pointer registers, just registers 0..31. */
2070 if (mode
== PTImode
)
2071 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2072 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
2073 && ((regno
& 1) == 0));
2075 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2076 implementations. Don't allow an item to be split between a FP register
2077 and an Altivec register. Allow TImode in all VSX registers if the user
2079 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
2080 && (VECTOR_MEM_VSX_P (mode
)
2081 || FLOAT128_VECTOR_P (mode
)
2082 || reg_addr
[mode
].scalar_in_vmx_p
2084 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
2086 if (FP_REGNO_P (regno
))
2087 return FP_REGNO_P (last_regno
);
2089 if (ALTIVEC_REGNO_P (regno
))
2091 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
2094 return ALTIVEC_REGNO_P (last_regno
);
2098 /* The GPRs can hold any mode, but values bigger than one register
2099 cannot go past R31. */
2100 if (INT_REGNO_P (regno
))
2101 return INT_REGNO_P (last_regno
);
2103 /* The float registers (except for VSX vector modes) can only hold floating
2104 modes and DImode. */
2105 if (FP_REGNO_P (regno
))
2107 if (FLOAT128_VECTOR_P (mode
))
2110 if (SCALAR_FLOAT_MODE_P (mode
)
2111 && (mode
!= TDmode
|| (regno
% 2) == 0)
2112 && FP_REGNO_P (last_regno
))
2115 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2117 if(GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
2120 if (TARGET_P8_VECTOR
&& (mode
== SImode
))
2123 if (TARGET_P9_VECTOR
&& (mode
== QImode
|| mode
== HImode
))
2130 /* The CR register can only hold CC modes. */
2131 if (CR_REGNO_P (regno
))
2132 return GET_MODE_CLASS (mode
) == MODE_CC
;
2134 if (CA_REGNO_P (regno
))
2135 return mode
== Pmode
|| mode
== SImode
;
2137 /* AltiVec only in AldyVec registers. */
2138 if (ALTIVEC_REGNO_P (regno
))
2139 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
2140 || mode
== V1TImode
);
2142 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2143 and it must be able to fit within the register set. */
2145 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
2148 /* Implement TARGET_HARD_REGNO_NREGS. */
2151 rs6000_hard_regno_nregs_hook (unsigned int regno
, machine_mode mode
)
2153 return rs6000_hard_regno_nregs
[mode
][regno
];
2156 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2159 rs6000_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2161 return rs6000_hard_regno_mode_ok_p
[mode
][regno
];
2164 /* Implement TARGET_MODES_TIEABLE_P.
2166 PTImode cannot tie with other modes because PTImode is restricted to even
2167 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2170 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2171 128-bit floating point on VSX systems ties with other vectors. */
2174 rs6000_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2176 if (mode1
== PTImode
)
2177 return mode2
== PTImode
;
2178 if (mode2
== PTImode
)
2181 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1
))
2182 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2
);
2183 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2
))
2186 if (SCALAR_FLOAT_MODE_P (mode1
))
2187 return SCALAR_FLOAT_MODE_P (mode2
);
2188 if (SCALAR_FLOAT_MODE_P (mode2
))
2191 if (GET_MODE_CLASS (mode1
) == MODE_CC
)
2192 return GET_MODE_CLASS (mode2
) == MODE_CC
;
2193 if (GET_MODE_CLASS (mode2
) == MODE_CC
)
2199 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2202 rs6000_hard_regno_call_part_clobbered (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2203 unsigned int regno
, machine_mode mode
)
2207 && GET_MODE_SIZE (mode
) > 4
2208 && INT_REGNO_P (regno
))
2212 && FP_REGNO_P (regno
)
2213 && GET_MODE_SIZE (mode
) > 8
2214 && !FLOAT128_2REG_P (mode
))
2220 /* Print interesting facts about registers. */
2222 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
2226 for (r
= first_regno
; r
<= last_regno
; ++r
)
2228 const char *comma
= "";
2231 if (first_regno
== last_regno
)
2232 fprintf (stderr
, "%s:\t", reg_name
);
2234 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
2237 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2238 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
2242 fprintf (stderr
, ",\n\t");
2247 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
2248 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
2249 rs6000_hard_regno_nregs
[m
][r
]);
2251 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
2256 if (call_used_regs
[r
])
2260 fprintf (stderr
, ",\n\t");
2265 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
2273 fprintf (stderr
, ",\n\t");
2278 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
2284 fprintf (stderr
, ",\n\t");
2288 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
2289 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
2294 fprintf (stderr
, ",\n\t");
2298 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
2303 rs6000_debug_vector_unit (enum rs6000_vector v
)
2309 case VECTOR_NONE
: ret
= "none"; break;
2310 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
2311 case VECTOR_VSX
: ret
= "vsx"; break;
2312 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
2313 default: ret
= "unknown"; break;
2319 /* Inner function printing just the address mask for a particular reload
2321 DEBUG_FUNCTION
char *
2322 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
2327 if ((mask
& RELOAD_REG_VALID
) != 0)
2329 else if (keep_spaces
)
2332 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
2334 else if (keep_spaces
)
2337 if ((mask
& RELOAD_REG_INDEXED
) != 0)
2339 else if (keep_spaces
)
2342 if ((mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
2344 else if ((mask
& RELOAD_REG_OFFSET
) != 0)
2346 else if (keep_spaces
)
2349 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2351 else if (keep_spaces
)
2354 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2356 else if (keep_spaces
)
2359 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2361 else if (keep_spaces
)
2369 /* Print the address masks in a human readble fashion. */
2371 rs6000_debug_print_mode (ssize_t m
)
2376 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2377 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2378 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2379 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2381 if ((reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2382 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
2384 fprintf (stderr
, "%*s Reload=%c%c", spaces
, "",
2385 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2386 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
2390 spaces
+= sizeof (" Reload=sl") - 1;
2392 if (reg_addr
[m
].scalar_in_vmx_p
)
2394 fprintf (stderr
, "%*s Upper=y", spaces
, "");
2398 spaces
+= sizeof (" Upper=y") - 1;
2400 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2401 || rs6000_vector_mem
[m
] != VECTOR_NONE
)
2403 fprintf (stderr
, "%*s vector: arith=%-10s mem=%s",
2405 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2406 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]));
2409 fputs ("\n", stderr
);
2412 #define DEBUG_FMT_ID "%-32s= "
2413 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2414 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2415 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2417 /* Print various interesting information with -mdebug=reg. */
2419 rs6000_debug_reg_global (void)
2421 static const char *const tf
[2] = { "false", "true" };
2422 const char *nl
= (const char *)0;
2425 char costly_num
[20];
2427 char flags_buffer
[40];
2428 const char *costly_str
;
2429 const char *nop_str
;
2430 const char *trace_str
;
2431 const char *abi_str
;
2432 const char *cmodel_str
;
2433 struct cl_target_option cl_opts
;
2435 /* Modes we want tieable information on. */
2436 static const machine_mode print_tieable_modes
[] = {
2470 /* Virtual regs we are interested in. */
2471 const static struct {
2472 int regno
; /* register number. */
2473 const char *name
; /* register name. */
2474 } virtual_regs
[] = {
2475 { STACK_POINTER_REGNUM
, "stack pointer:" },
2476 { TOC_REGNUM
, "toc: " },
2477 { STATIC_CHAIN_REGNUM
, "static chain: " },
2478 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2479 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2480 { ARG_POINTER_REGNUM
, "arg pointer: " },
2481 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2482 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2483 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2484 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2485 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2486 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2487 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2488 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2489 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2490 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2493 fputs ("\nHard register information:\n", stderr
);
2494 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2495 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2496 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2499 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2500 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2501 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2502 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2503 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2504 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2506 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2507 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2508 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2512 "d reg_class = %s\n"
2513 "f reg_class = %s\n"
2514 "v reg_class = %s\n"
2515 "wa reg_class = %s\n"
2516 "wb reg_class = %s\n"
2517 "wd reg_class = %s\n"
2518 "we reg_class = %s\n"
2519 "wf reg_class = %s\n"
2520 "wg reg_class = %s\n"
2521 "wh reg_class = %s\n"
2522 "wi reg_class = %s\n"
2523 "wj reg_class = %s\n"
2524 "wk reg_class = %s\n"
2525 "wl reg_class = %s\n"
2526 "wm reg_class = %s\n"
2527 "wo reg_class = %s\n"
2528 "wp reg_class = %s\n"
2529 "wq reg_class = %s\n"
2530 "wr reg_class = %s\n"
2531 "ws reg_class = %s\n"
2532 "wt reg_class = %s\n"
2533 "wu reg_class = %s\n"
2534 "wv reg_class = %s\n"
2535 "ww reg_class = %s\n"
2536 "wx reg_class = %s\n"
2537 "wy reg_class = %s\n"
2538 "wz reg_class = %s\n"
2539 "wA reg_class = %s\n"
2540 "wH reg_class = %s\n"
2541 "wI reg_class = %s\n"
2542 "wJ reg_class = %s\n"
2543 "wK reg_class = %s\n"
2545 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2546 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2547 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2548 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2549 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wb
]],
2550 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2551 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_we
]],
2552 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2553 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2554 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2555 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2556 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2557 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2558 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2559 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2560 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wo
]],
2561 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wp
]],
2562 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wq
]],
2563 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2564 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2565 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2566 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2567 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2568 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2569 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2570 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2571 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]],
2572 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wA
]],
2573 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wH
]],
2574 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wI
]],
2575 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wJ
]],
2576 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wK
]]);
2579 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2580 rs6000_debug_print_mode (m
);
2582 fputs ("\n", stderr
);
2584 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2586 machine_mode mode1
= print_tieable_modes
[m1
];
2587 bool first_time
= true;
2589 nl
= (const char *)0;
2590 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2592 machine_mode mode2
= print_tieable_modes
[m2
];
2593 if (mode1
!= mode2
&& rs6000_modes_tieable_p (mode1
, mode2
))
2597 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2602 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2607 fputs ("\n", stderr
);
2613 if (rs6000_recip_control
)
2615 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2617 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2618 if (rs6000_recip_bits
[m
])
2621 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2623 (RS6000_RECIP_AUTO_RE_P (m
)
2625 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2626 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2628 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2631 fputs ("\n", stderr
);
2634 if (rs6000_cpu_index
>= 0)
2636 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2638 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2640 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2641 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2644 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2646 if (rs6000_tune_index
>= 0)
2648 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2650 = processor_target_table
[rs6000_tune_index
].target_enable
;
2652 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2653 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2656 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2658 cl_target_option_save (&cl_opts
, &global_options
);
2659 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2662 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2663 rs6000_isa_flags_explicit
);
2665 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2666 rs6000_builtin_mask
);
2668 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2670 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2671 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2673 switch (rs6000_sched_costly_dep
)
2675 case max_dep_latency
:
2676 costly_str
= "max_dep_latency";
2680 costly_str
= "no_dep_costly";
2683 case all_deps_costly
:
2684 costly_str
= "all_deps_costly";
2687 case true_store_to_load_dep_costly
:
2688 costly_str
= "true_store_to_load_dep_costly";
2691 case store_to_load_dep_costly
:
2692 costly_str
= "store_to_load_dep_costly";
2696 costly_str
= costly_num
;
2697 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2701 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2703 switch (rs6000_sched_insert_nops
)
2705 case sched_finish_regroup_exact
:
2706 nop_str
= "sched_finish_regroup_exact";
2709 case sched_finish_pad_groups
:
2710 nop_str
= "sched_finish_pad_groups";
2713 case sched_finish_none
:
2714 nop_str
= "sched_finish_none";
2719 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2723 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2725 switch (rs6000_sdata
)
2732 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2736 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2740 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2745 switch (rs6000_traceback
)
2747 case traceback_default
: trace_str
= "default"; break;
2748 case traceback_none
: trace_str
= "none"; break;
2749 case traceback_part
: trace_str
= "part"; break;
2750 case traceback_full
: trace_str
= "full"; break;
2751 default: trace_str
= "unknown"; break;
2754 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2756 switch (rs6000_current_cmodel
)
2758 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2759 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2760 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2761 default: cmodel_str
= "unknown"; break;
2764 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2766 switch (rs6000_current_abi
)
2768 case ABI_NONE
: abi_str
= "none"; break;
2769 case ABI_AIX
: abi_str
= "aix"; break;
2770 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2771 case ABI_V4
: abi_str
= "V4"; break;
2772 case ABI_DARWIN
: abi_str
= "darwin"; break;
2773 default: abi_str
= "unknown"; break;
2776 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2778 if (rs6000_altivec_abi
)
2779 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2781 if (rs6000_darwin64_abi
)
2782 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2784 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2785 (TARGET_SOFT_FLOAT
? "true" : "false"));
2787 if (TARGET_LINK_STACK
)
2788 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2790 if (TARGET_P8_FUSION
)
2794 strcpy (options
, "power8");
2795 if (TARGET_P8_FUSION_SIGN
)
2796 strcat (options
, ", sign");
2798 fprintf (stderr
, DEBUG_FMT_S
, "fusion", options
);
2801 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2802 TARGET_SECURE_PLT
? "secure" : "bss");
2803 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2804 aix_struct_return
? "aix" : "sysv");
2805 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2806 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2807 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2808 tf
[!!rs6000_align_branch_targets
]);
2809 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2810 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2811 rs6000_long_double_type_size
);
2812 if (rs6000_long_double_type_size
> 64)
2814 fprintf (stderr
, DEBUG_FMT_S
, "long double type",
2815 TARGET_IEEEQUAD
? "IEEE" : "IBM");
2816 fprintf (stderr
, DEBUG_FMT_S
, "default long double type",
2817 TARGET_IEEEQUAD_DEFAULT
? "IEEE" : "IBM");
2819 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2820 (int)rs6000_sched_restricted_insns_priority
);
2821 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2823 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2824 (int)RS6000_BUILTIN_COUNT
);
2826 fprintf (stderr
, DEBUG_FMT_D
, "Enable float128 on VSX",
2827 (int)TARGET_FLOAT128_ENABLE_TYPE
);
2830 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2831 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2833 if (TARGET_DIRECT_MOVE_128
)
2834 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit mfvsrld element",
2835 (int)VECTOR_ELEMENT_MFVSRLD_64BIT
);
2839 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2840 legitimate address support to figure out the appropriate addressing to
2844 rs6000_setup_reg_addr_masks (void)
2846 ssize_t rc
, reg
, m
, nregs
;
2847 addr_mask_type any_addr_mask
, addr_mask
;
2849 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2851 machine_mode m2
= (machine_mode
) m
;
2852 bool complex_p
= false;
2853 bool small_int_p
= (m2
== QImode
|| m2
== HImode
|| m2
== SImode
);
2856 if (COMPLEX_MODE_P (m2
))
2859 m2
= GET_MODE_INNER (m2
);
2862 msize
= GET_MODE_SIZE (m2
);
2864 /* SDmode is special in that we want to access it only via REG+REG
2865 addressing on power7 and above, since we want to use the LFIWZX and
2866 STFIWZX instructions to load it. */
2867 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2870 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2873 reg
= reload_reg_map
[rc
].reg
;
2875 /* Can mode values go in the GPR/FPR/Altivec registers? */
2876 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2878 bool small_int_vsx_p
= (small_int_p
2879 && (rc
== RELOAD_REG_FPR
2880 || rc
== RELOAD_REG_VMX
));
2882 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2883 addr_mask
|= RELOAD_REG_VALID
;
2885 /* Indicate if the mode takes more than 1 physical register. If
2886 it takes a single register, indicate it can do REG+REG
2887 addressing. Small integers in VSX registers can only do
2888 REG+REG addressing. */
2889 if (small_int_vsx_p
)
2890 addr_mask
|= RELOAD_REG_INDEXED
;
2891 else if (nregs
> 1 || m
== BLKmode
|| complex_p
)
2892 addr_mask
|= RELOAD_REG_MULTIPLE
;
2894 addr_mask
|= RELOAD_REG_INDEXED
;
2896 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2897 addressing. If we allow scalars into Altivec registers,
2898 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2900 For VSX systems, we don't allow update addressing for
2901 DFmode/SFmode if those registers can go in both the
2902 traditional floating point registers and Altivec registers.
2903 The load/store instructions for the Altivec registers do not
2904 have update forms. If we allowed update addressing, it seems
2905 to break IV-OPT code using floating point if the index type is
2906 int instead of long (PR target/81550 and target/84042). */
2909 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2911 && !VECTOR_MODE_P (m2
)
2912 && !FLOAT128_VECTOR_P (m2
)
2914 && (m
!= E_DFmode
|| !TARGET_VSX
)
2915 && (m
!= E_SFmode
|| !TARGET_P8_VECTOR
)
2916 && !small_int_vsx_p
)
2918 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2920 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2921 we don't allow PRE_MODIFY for some multi-register
2926 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2930 if (TARGET_POWERPC64
)
2931 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2936 if (TARGET_HARD_FLOAT
)
2937 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2943 /* GPR and FPR registers can do REG+OFFSET addressing, except
2944 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2945 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2946 if ((addr_mask
!= 0) && !indexed_only_p
2948 && (rc
== RELOAD_REG_GPR
2949 || ((msize
== 8 || m2
== SFmode
)
2950 && (rc
== RELOAD_REG_FPR
2951 || (rc
== RELOAD_REG_VMX
&& TARGET_P9_VECTOR
)))))
2952 addr_mask
|= RELOAD_REG_OFFSET
;
2954 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2955 instructions are enabled. The offset for 128-bit VSX registers is
2956 only 12-bits. While GPRs can handle the full offset range, VSX
2957 registers can only handle the restricted range. */
2958 else if ((addr_mask
!= 0) && !indexed_only_p
2959 && msize
== 16 && TARGET_P9_VECTOR
2960 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2
)
2961 || (m2
== TImode
&& TARGET_VSX
)))
2963 addr_mask
|= RELOAD_REG_OFFSET
;
2964 if (rc
== RELOAD_REG_FPR
|| rc
== RELOAD_REG_VMX
)
2965 addr_mask
|= RELOAD_REG_QUAD_OFFSET
;
2968 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2969 addressing on 128-bit types. */
2970 if (rc
== RELOAD_REG_VMX
&& msize
== 16
2971 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2972 addr_mask
|= RELOAD_REG_AND_M16
;
2974 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2975 any_addr_mask
|= addr_mask
;
2978 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2983 /* Initialize the various global tables that are based on register size. */
2985 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2991 /* Precalculate REGNO_REG_CLASS. */
2992 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2993 for (r
= 1; r
< 32; ++r
)
2994 rs6000_regno_regclass
[r
] = BASE_REGS
;
2996 for (r
= 32; r
< 64; ++r
)
2997 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2999 for (r
= 64; HARD_REGISTER_NUM_P (r
); ++r
)
3000 rs6000_regno_regclass
[r
] = NO_REGS
;
3002 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
3003 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
3005 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
3006 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
3007 rs6000_regno_regclass
[r
] = CR_REGS
;
3009 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
3010 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
3011 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
3012 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
3013 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
3014 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
3015 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
3016 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
3017 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
3018 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
3020 /* Precalculate register class to simpler reload register class. We don't
3021 need all of the register classes that are combinations of different
3022 classes, just the simple ones that have constraint letters. */
3023 for (c
= 0; c
< N_REG_CLASSES
; c
++)
3024 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
3026 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
3027 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
3028 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
3029 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
3030 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
3031 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
3032 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
3033 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
3034 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
3035 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
3039 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
3040 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
3044 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
3045 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
3048 /* Precalculate the valid memory formats as well as the vector information,
3049 this must be set up before the rs6000_hard_regno_nregs_internal calls
3051 gcc_assert ((int)VECTOR_NONE
== 0);
3052 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
3053 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_mem
));
3055 gcc_assert ((int)CODE_FOR_nothing
== 0);
3056 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
3058 gcc_assert ((int)NO_REGS
== 0);
3059 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
3061 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3062 believes it can use native alignment or still uses 128-bit alignment. */
3063 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
3074 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3075 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3076 if (TARGET_FLOAT128_TYPE
)
3078 rs6000_vector_mem
[KFmode
] = VECTOR_VSX
;
3079 rs6000_vector_align
[KFmode
] = 128;
3081 if (FLOAT128_IEEE_P (TFmode
))
3083 rs6000_vector_mem
[TFmode
] = VECTOR_VSX
;
3084 rs6000_vector_align
[TFmode
] = 128;
3088 /* V2DF mode, VSX only. */
3091 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
3092 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
3093 rs6000_vector_align
[V2DFmode
] = align64
;
3096 /* V4SF mode, either VSX or Altivec. */
3099 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
3100 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
3101 rs6000_vector_align
[V4SFmode
] = align32
;
3103 else if (TARGET_ALTIVEC
)
3105 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
3106 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
3107 rs6000_vector_align
[V4SFmode
] = align32
;
3110 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3114 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
3115 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
3116 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
3117 rs6000_vector_align
[V4SImode
] = align32
;
3118 rs6000_vector_align
[V8HImode
] = align32
;
3119 rs6000_vector_align
[V16QImode
] = align32
;
3123 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
3124 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
3125 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
3129 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
3130 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
3131 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
3135 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3136 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3139 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
3140 rs6000_vector_unit
[V2DImode
]
3141 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3142 rs6000_vector_align
[V2DImode
] = align64
;
3144 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
3145 rs6000_vector_unit
[V1TImode
]
3146 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3147 rs6000_vector_align
[V1TImode
] = 128;
3150 /* DFmode, see if we want to use the VSX unit. Memory is handled
3151 differently, so don't set rs6000_vector_mem. */
3154 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
3155 rs6000_vector_align
[DFmode
] = 64;
3158 /* SFmode, see if we want to use the VSX unit. */
3159 if (TARGET_P8_VECTOR
)
3161 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
3162 rs6000_vector_align
[SFmode
] = 32;
3165 /* Allow TImode in VSX register and set the VSX memory macros. */
3168 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
3169 rs6000_vector_align
[TImode
] = align64
;
3172 /* Register class constraints for the constraints that depend on compile
3173 switches. When the VSX code was added, different constraints were added
3174 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3175 of the VSX registers are used. The register classes for scalar floating
3176 point types is set, based on whether we allow that type into the upper
3177 (Altivec) registers. GCC has register classes to target the Altivec
3178 registers for load/store operations, to select using a VSX memory
3179 operation instead of the traditional floating point operation. The
3182 d - Register class to use with traditional DFmode instructions.
3183 f - Register class to use with traditional SFmode instructions.
3184 v - Altivec register.
3185 wa - Any VSX register.
3186 wc - Reserved to represent individual CR bits (used in LLVM).
3187 wd - Preferred register class for V2DFmode.
3188 wf - Preferred register class for V4SFmode.
3189 wg - Float register for power6x move insns.
3190 wh - FP register for direct move instructions.
3191 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3192 wj - FP or VSX register to hold 64-bit integers for direct moves.
3193 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3194 wl - Float register if we can do 32-bit signed int loads.
3195 wm - VSX register for ISA 2.07 direct move operations.
3196 wn - always NO_REGS.
3197 wr - GPR if 64-bit mode is permitted.
3198 ws - Register class to do ISA 2.06 DF operations.
3199 wt - VSX register for TImode in VSX registers.
3200 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3201 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3202 ww - Register class to do SF conversions in with VSX operations.
3203 wx - Float register if we can do 32-bit int stores.
3204 wy - Register class to do ISA 2.07 SF operations.
3205 wz - Float register if we can do 32-bit unsigned int loads.
3206 wH - Altivec register if SImode is allowed in VSX registers.
3207 wI - Float register if SImode is allowed in VSX registers.
3208 wJ - Float register if QImode/HImode are allowed in VSX registers.
3209 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3211 if (TARGET_HARD_FLOAT
)
3213 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
3214 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
3219 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
3220 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
3221 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
3222 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
; /* DFmode */
3223 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
; /* DFmode */
3224 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = VSX_REGS
; /* DImode */
3225 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
3228 /* Add conditional constraints based on various options, to allow us to
3229 collapse multiple insn patterns. */
3231 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
3233 if (TARGET_MFPGPR
) /* DFmode */
3234 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
3237 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
3239 if (TARGET_DIRECT_MOVE
)
3241 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
3242 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
3243 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
3244 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
3245 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
3246 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
3249 if (TARGET_POWERPC64
)
3251 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
3252 rs6000_constraints
[RS6000_CONSTRAINT_wA
] = BASE_REGS
;
3255 if (TARGET_P8_VECTOR
) /* SFmode */
3257 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
3258 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
3259 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
3261 else if (TARGET_VSX
)
3262 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3265 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
3268 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
3270 if (TARGET_FLOAT128_TYPE
)
3272 rs6000_constraints
[RS6000_CONSTRAINT_wq
] = VSX_REGS
; /* KFmode */
3273 if (FLOAT128_IEEE_P (TFmode
))
3274 rs6000_constraints
[RS6000_CONSTRAINT_wp
] = VSX_REGS
; /* TFmode */
3277 if (TARGET_P9_VECTOR
)
3279 /* Support for new D-form instructions. */
3280 rs6000_constraints
[RS6000_CONSTRAINT_wb
] = ALTIVEC_REGS
;
3282 /* Support for ISA 3.0 (power9) vectors. */
3283 rs6000_constraints
[RS6000_CONSTRAINT_wo
] = VSX_REGS
;
3286 /* Support for new direct moves (ISA 3.0 + 64bit). */
3287 if (TARGET_DIRECT_MOVE_128
)
3288 rs6000_constraints
[RS6000_CONSTRAINT_we
] = VSX_REGS
;
3290 /* Support small integers in VSX registers. */
3291 if (TARGET_P8_VECTOR
)
3293 rs6000_constraints
[RS6000_CONSTRAINT_wH
] = ALTIVEC_REGS
;
3294 rs6000_constraints
[RS6000_CONSTRAINT_wI
] = FLOAT_REGS
;
3295 if (TARGET_P9_VECTOR
)
3297 rs6000_constraints
[RS6000_CONSTRAINT_wJ
] = FLOAT_REGS
;
3298 rs6000_constraints
[RS6000_CONSTRAINT_wK
] = ALTIVEC_REGS
;
3302 /* Set up the reload helper and direct move functions. */
3303 if (TARGET_VSX
|| TARGET_ALTIVEC
)
3307 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
3308 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
3309 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
3310 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
3311 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
3312 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
3313 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
3314 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
3315 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
3316 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
3317 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
3318 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
3319 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
3320 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
3321 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
3322 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
3323 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
3324 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
3325 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
3326 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
3328 if (FLOAT128_VECTOR_P (KFmode
))
3330 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_di_store
;
3331 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_di_load
;
3334 if (FLOAT128_VECTOR_P (TFmode
))
3336 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_di_store
;
3337 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_di_load
;
3340 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3342 if (TARGET_NO_SDMODE_STACK
)
3344 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
3345 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
3350 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
3351 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
3354 if (TARGET_DIRECT_MOVE
&& !TARGET_DIRECT_MOVE_128
)
3356 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
3357 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
3358 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
3359 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
3360 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
3361 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
3362 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
3363 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
3364 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
3366 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
3367 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
3368 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
3369 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
3370 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
3371 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
3372 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
3373 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
3374 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
3376 if (FLOAT128_VECTOR_P (KFmode
))
3378 reg_addr
[KFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxkf
;
3379 reg_addr
[KFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprkf
;
3382 if (FLOAT128_VECTOR_P (TFmode
))
3384 reg_addr
[TFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxtf
;
3385 reg_addr
[TFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprtf
;
3391 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
3392 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
3393 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
3394 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
3395 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
3396 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
3397 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
3398 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
3399 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
3400 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
3401 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
3402 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
3403 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
3404 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
3405 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
3406 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
3407 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
3408 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
3409 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
3410 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
3412 if (FLOAT128_VECTOR_P (KFmode
))
3414 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_si_store
;
3415 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_si_load
;
3418 if (FLOAT128_IEEE_P (TFmode
))
3420 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_si_store
;
3421 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_si_load
;
3424 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3426 if (TARGET_NO_SDMODE_STACK
)
3428 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
3429 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
3434 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
3435 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
3438 if (TARGET_DIRECT_MOVE
)
3440 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
3441 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
3442 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
3446 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
3447 reg_addr
[DImode
].scalar_in_vmx_p
= true;
3449 if (TARGET_P8_VECTOR
)
3451 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
3452 reg_addr
[SImode
].scalar_in_vmx_p
= true;
3454 if (TARGET_P9_VECTOR
)
3456 reg_addr
[HImode
].scalar_in_vmx_p
= true;
3457 reg_addr
[QImode
].scalar_in_vmx_p
= true;
3462 /* Precalculate HARD_REGNO_NREGS. */
3463 for (r
= 0; HARD_REGISTER_NUM_P (r
); ++r
)
3464 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3465 rs6000_hard_regno_nregs
[m
][r
]
3466 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
) m
);
3468 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3469 for (r
= 0; HARD_REGISTER_NUM_P (r
); ++r
)
3470 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3471 rs6000_hard_regno_mode_ok_p
[m
][r
]
3472 = rs6000_hard_regno_mode_ok_uncached (r
, (machine_mode
) m
);
3474 /* Precalculate CLASS_MAX_NREGS sizes. */
3475 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
3479 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
3480 reg_size
= UNITS_PER_VSX_WORD
;
3482 else if (c
== ALTIVEC_REGS
)
3483 reg_size
= UNITS_PER_ALTIVEC_WORD
;
3485 else if (c
== FLOAT_REGS
)
3486 reg_size
= UNITS_PER_FP_WORD
;
3489 reg_size
= UNITS_PER_WORD
;
3491 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3493 machine_mode m2
= (machine_mode
)m
;
3494 int reg_size2
= reg_size
;
3496 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3498 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
) && FLOAT128_2REG_P (m
))
3499 reg_size2
= UNITS_PER_FP_WORD
;
3501 rs6000_class_max_nregs
[m
][c
]
3502 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3506 /* Calculate which modes to automatically generate code to use a the
3507 reciprocal divide and square root instructions. In the future, possibly
3508 automatically generate the instructions even if the user did not specify
3509 -mrecip. The older machines double precision reciprocal sqrt estimate is
3510 not accurate enough. */
3511 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3513 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3515 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3516 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3517 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3518 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3519 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3521 if (TARGET_FRSQRTES
)
3522 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3524 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3525 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3526 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3527 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3528 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3530 if (rs6000_recip_control
)
3532 if (!flag_finite_math_only
)
3533 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3535 if (flag_trapping_math
)
3536 warning (0, "%qs requires %qs or %qs", "-mrecip",
3537 "-fno-trapping-math", "-ffast-math");
3538 if (!flag_reciprocal_math
)
3539 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3541 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3543 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3544 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3545 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3547 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3548 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3549 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3551 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3552 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3553 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3555 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3556 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3557 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3559 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3560 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3561 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3563 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3564 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3565 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3567 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3568 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3569 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3571 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3572 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3573 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3577 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3578 legitimate address support to figure out the appropriate addressing to
3580 rs6000_setup_reg_addr_masks ();
3582 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3584 if (TARGET_DEBUG_REG
)
3585 rs6000_debug_reg_global ();
3587 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3589 "SImode variable mult cost = %d\n"
3590 "SImode constant mult cost = %d\n"
3591 "SImode short constant mult cost = %d\n"
3592 "DImode multipliciation cost = %d\n"
3593 "SImode division cost = %d\n"
3594 "DImode division cost = %d\n"
3595 "Simple fp operation cost = %d\n"
3596 "DFmode multiplication cost = %d\n"
3597 "SFmode division cost = %d\n"
3598 "DFmode division cost = %d\n"
3599 "cache line size = %d\n"
3600 "l1 cache size = %d\n"
3601 "l2 cache size = %d\n"
3602 "simultaneous prefetches = %d\n"
3605 rs6000_cost
->mulsi_const
,
3606 rs6000_cost
->mulsi_const9
,
3614 rs6000_cost
->cache_line_size
,
3615 rs6000_cost
->l1_cache_size
,
3616 rs6000_cost
->l2_cache_size
,
3617 rs6000_cost
->simultaneous_prefetches
);
3622 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3625 darwin_rs6000_override_options (void)
3627 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3629 rs6000_altivec_abi
= 1;
3630 TARGET_ALTIVEC_VRSAVE
= 1;
3631 rs6000_current_abi
= ABI_DARWIN
;
3633 if (DEFAULT_ABI
== ABI_DARWIN
3635 darwin_one_byte_bool
= 1;
3637 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3639 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3640 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3644 rs6000_default_long_calls
= 1;
3645 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3648 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3650 if (!flag_mkernel
&& !flag_apple_kext
3652 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3653 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3655 /* Unless the user (not the configurer) has explicitly overridden
3656 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3657 G4 unless targeting the kernel. */
3660 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3661 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3662 && ! global_options_set
.x_rs6000_cpu_index
)
3664 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3669 /* If not otherwise specified by a target, make 'long double' equivalent to
3672 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3673 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3676 /* Return the builtin mask of the various options used that could affect which
3677 builtins were used. In the past we used target_flags, but we've run out of
3678 bits, and some options are no longer in target_flags. */
3681 rs6000_builtin_mask_calculate (void)
3683 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3684 | ((TARGET_CMPB
) ? RS6000_BTM_CMPB
: 0)
3685 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3686 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3687 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3688 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3689 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3690 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3691 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3692 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3693 | ((TARGET_P9_VECTOR
) ? RS6000_BTM_P9_VECTOR
: 0)
3694 | ((TARGET_P9_MISC
) ? RS6000_BTM_P9_MISC
: 0)
3695 | ((TARGET_MODULO
) ? RS6000_BTM_MODULO
: 0)
3696 | ((TARGET_64BIT
) ? RS6000_BTM_64BIT
: 0)
3697 | ((TARGET_POWERPC64
) ? RS6000_BTM_POWERPC64
: 0)
3698 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3699 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3700 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3701 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3702 | ((TARGET_LONG_DOUBLE_128
3703 && TARGET_HARD_FLOAT
3704 && !TARGET_IEEEQUAD
) ? RS6000_BTM_LDBL128
: 0)
3705 | ((TARGET_FLOAT128_TYPE
) ? RS6000_BTM_FLOAT128
: 0)
3706 | ((TARGET_FLOAT128_HW
) ? RS6000_BTM_FLOAT128_HW
: 0));
3709 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3710 to clobber the XER[CA] bit because clobbering that bit without telling
3711 the compiler worked just fine with versions of GCC before GCC 5, and
3712 breaking a lot of older code in ways that are hard to track down is
3713 not such a great idea. */
3716 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3717 vec
<const char *> &/*constraints*/,
3718 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3720 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3721 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3725 /* Override command line options.
3727 Combine build-specific configuration information with options
3728 specified on the command line to set various state variables which
3729 influence code generation, optimization, and expansion of built-in
3730 functions. Assure that command-line configuration preferences are
3731 compatible with each other and with the build configuration; issue
3732 warnings while adjusting configuration or error messages while
3733 rejecting configuration.
3735 Upon entry to this function:
3737 This function is called once at the beginning of
3738 compilation, and then again at the start and end of compiling
3739 each section of code that has a different configuration, as
3740 indicated, for example, by adding the
3742 __attribute__((__target__("cpu=power9")))
3744 qualifier to a function definition or, for example, by bracketing
3747 #pragma GCC target("altivec")
3751 #pragma GCC reset_options
3753 directives. Parameter global_init_p is true for the initial
3754 invocation, which initializes global variables, and false for all
3755 subsequent invocations.
3758 Various global state information is assumed to be valid. This
3759 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3760 default CPU specified at build configure time, TARGET_DEFAULT,
3761 representing the default set of option flags for the default
3762 target, and global_options_set.x_rs6000_isa_flags, representing
3763 which options were requested on the command line.
3765 Upon return from this function:
3767 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3768 was set by name on the command line. Additionally, if certain
3769 attributes are automatically enabled or disabled by this function
3770 in order to assure compatibility between options and
3771 configuration, the flags associated with those attributes are
3772 also set. By setting these "explicit bits", we avoid the risk
3773 that other code might accidentally overwrite these particular
3774 attributes with "default values".
3776 The various bits of rs6000_isa_flags are set to indicate the
3777 target options that have been selected for the most current
3778 compilation efforts. This has the effect of also turning on the
3779 associated TARGET_XXX values since these are macros which are
3780 generally defined to test the corresponding bit of the
3781 rs6000_isa_flags variable.
3783 The variable rs6000_builtin_mask is set to represent the target
3784 options for the most current compilation efforts, consistent with
3785 the current contents of rs6000_isa_flags. This variable controls
3786 expansion of built-in functions.
3788 Various other global variables and fields of global structures
3789 (over 50 in all) are initialized to reflect the desired options
3790 for the most current compilation efforts. */
3793 rs6000_option_override_internal (bool global_init_p
)
3797 HOST_WIDE_INT set_masks
;
3798 HOST_WIDE_INT ignore_masks
;
3801 struct cl_target_option
*main_target_opt
3802 = ((global_init_p
|| target_option_default_node
== NULL
)
3803 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3805 /* Print defaults. */
3806 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3807 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3809 /* Remember the explicit arguments. */
3811 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3813 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3814 library functions, so warn about it. The flag may be useful for
3815 performance studies from time to time though, so don't disable it
3817 if (global_options_set
.x_rs6000_alignment_flags
3818 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3819 && DEFAULT_ABI
== ABI_DARWIN
3821 warning (0, "%qs is not supported for 64-bit Darwin;"
3822 " it is incompatible with the installed C and C++ libraries",
3825 /* Numerous experiment shows that IRA based loop pressure
3826 calculation works better for RTL loop invariant motion on targets
3827 with enough (>= 32) registers. It is an expensive optimization.
3828 So it is on only for peak performance. */
3829 if (optimize
>= 3 && global_init_p
3830 && !global_options_set
.x_flag_ira_loop_pressure
)
3831 flag_ira_loop_pressure
= 1;
3833 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3834 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3835 options were already specified. */
3836 if (flag_sanitize
& SANITIZE_USER_ADDRESS
3837 && !global_options_set
.x_flag_asynchronous_unwind_tables
)
3838 flag_asynchronous_unwind_tables
= 1;
3840 /* Set the pointer size. */
3843 rs6000_pmode
= DImode
;
3844 rs6000_pointer_size
= 64;
3848 rs6000_pmode
= SImode
;
3849 rs6000_pointer_size
= 32;
3852 /* Some OSs don't support saving the high part of 64-bit registers on context
3853 switch. Other OSs don't support saving Altivec registers. On those OSs,
3854 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3855 if the user wants either, the user must explicitly specify them and we
3856 won't interfere with the user's specification. */
3858 set_masks
= POWERPC_MASKS
;
3859 #ifdef OS_MISSING_POWERPC64
3860 if (OS_MISSING_POWERPC64
)
3861 set_masks
&= ~OPTION_MASK_POWERPC64
;
3863 #ifdef OS_MISSING_ALTIVEC
3864 if (OS_MISSING_ALTIVEC
)
3865 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
3866 | OTHER_VSX_VECTOR_MASKS
);
3869 /* Don't override by the processor default if given explicitly. */
3870 set_masks
&= ~rs6000_isa_flags_explicit
;
3872 if (global_init_p
&& rs6000_dejagnu_cpu_index
>= 0)
3873 rs6000_cpu_index
= rs6000_dejagnu_cpu_index
;
3875 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3876 the cpu in a target attribute or pragma, but did not specify a tuning
3877 option, use the cpu for the tuning option rather than the option specified
3878 with -mtune on the command line. Process a '--with-cpu' configuration
3879 request as an implicit --cpu. */
3880 if (rs6000_cpu_index
>= 0)
3881 cpu_index
= rs6000_cpu_index
;
3882 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3883 cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3884 else if (OPTION_TARGET_CPU_DEFAULT
)
3885 cpu_index
= rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT
);
3887 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3888 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3889 with those from the cpu, except for options that were explicitly set. If
3890 we don't have a cpu, do not override the target bits set in
3894 rs6000_cpu_index
= cpu_index
;
3895 rs6000_isa_flags
&= ~set_masks
;
3896 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3901 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3902 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3903 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3904 to using rs6000_isa_flags, we need to do the initialization here.
3906 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3907 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3908 HOST_WIDE_INT flags
;
3910 flags
= TARGET_DEFAULT
;
3913 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3914 const char *default_cpu
= (!TARGET_POWERPC64
3919 int default_cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3920 flags
= processor_target_table
[default_cpu_index
].target_enable
;
3922 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
3925 if (rs6000_tune_index
>= 0)
3926 tune_index
= rs6000_tune_index
;
3927 else if (cpu_index
>= 0)
3928 rs6000_tune_index
= tune_index
= cpu_index
;
3932 enum processor_type tune_proc
3933 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3936 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3937 if (processor_target_table
[i
].processor
== tune_proc
)
3945 rs6000_cpu
= processor_target_table
[cpu_index
].processor
;
3947 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
3949 gcc_assert (tune_index
>= 0);
3950 rs6000_tune
= processor_target_table
[tune_index
].processor
;
3952 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3953 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3954 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3957 error ("AltiVec not supported in this target");
3960 /* If we are optimizing big endian systems for space, use the load/store
3961 multiple instructions. */
3962 if (BYTES_BIG_ENDIAN
&& optimize_size
)
3963 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
;
3965 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3966 because the hardware doesn't support the instructions used in little
3967 endian mode, and causes an alignment trap. The 750 does not cause an
3968 alignment trap (except when the target is unaligned). */
3970 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
&& TARGET_MULTIPLE
)
3972 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3973 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3974 warning (0, "%qs is not supported on little endian systems",
3978 /* If little-endian, default to -mstrict-align on older processors.
3979 Testing for htm matches power8 and later. */
3980 if (!BYTES_BIG_ENDIAN
3981 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3982 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3984 if (!rs6000_fold_gimple
)
3986 "gimple folding of rs6000 builtins has been disabled.\n");
3988 /* Add some warnings for VSX. */
3991 const char *msg
= NULL
;
3992 if (!TARGET_HARD_FLOAT
)
3994 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3995 msg
= N_("%<-mvsx%> requires hardware floating point");
3998 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3999 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4002 else if (TARGET_AVOID_XFORM
> 0)
4003 msg
= N_("%<-mvsx%> needs indexed addressing");
4004 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
4005 & OPTION_MASK_ALTIVEC
))
4007 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4008 msg
= N_("%<-mvsx%> and %<-mno-altivec%> are incompatible");
4010 msg
= N_("%<-mno-altivec%> disables vsx");
4016 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
4017 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4021 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4022 the -mcpu setting to enable options that conflict. */
4023 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
4024 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
4025 | OPTION_MASK_ALTIVEC
4026 | OPTION_MASK_VSX
)) != 0)
4027 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
4028 | OPTION_MASK_DIRECT_MOVE
)
4029 & ~rs6000_isa_flags_explicit
);
4031 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4032 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
4034 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4035 off all of the options that depend on those flags. */
4036 ignore_masks
= rs6000_disable_incompatible_switches ();
4038 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4039 unless the user explicitly used the -mno-<option> to disable the code. */
4040 if (TARGET_P9_VECTOR
|| TARGET_MODULO
|| TARGET_P9_MISC
)
4041 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4042 else if (TARGET_P9_MINMAX
)
4046 if (cpu_index
== PROCESSOR_POWER9
)
4048 /* legacy behavior: allow -mcpu=power9 with certain
4049 capabilities explicitly disabled. */
4050 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~ignore_masks
);
4053 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4054 "for <xxx> less than power9", "-mcpu");
4056 else if ((ISA_3_0_MASKS_SERVER
& rs6000_isa_flags_explicit
)
4057 != (ISA_3_0_MASKS_SERVER
& rs6000_isa_flags
4058 & rs6000_isa_flags_explicit
))
4059 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4060 were explicitly cleared. */
4061 error ("%qs incompatible with explicitly disabled options",
4064 rs6000_isa_flags
|= ISA_3_0_MASKS_SERVER
;
4066 else if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
4067 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~ignore_masks
);
4068 else if (TARGET_VSX
)
4069 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~ignore_masks
);
4070 else if (TARGET_POPCNTD
)
4071 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~ignore_masks
);
4072 else if (TARGET_DFP
)
4073 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~ignore_masks
);
4074 else if (TARGET_CMPB
)
4075 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~ignore_masks
);
4076 else if (TARGET_FPRND
)
4077 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~ignore_masks
);
4078 else if (TARGET_POPCNTB
)
4079 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~ignore_masks
);
4080 else if (TARGET_ALTIVEC
)
4081 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~ignore_masks
);
4083 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
4085 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
4086 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4087 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
4090 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
4092 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
4093 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4094 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
4097 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
4099 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4100 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4101 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4104 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
4106 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4107 && (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
))
4108 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4109 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
) == 0)
4111 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4112 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4113 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4117 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4119 rs6000_isa_flags
|= OPTION_MASK_VSX
;
4120 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4124 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
4126 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
4127 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4128 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
4131 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4132 silently turn off quad memory mode. */
4133 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
4135 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4136 warning (0, N_("%<-mquad-memory%> requires 64-bit mode"));
4138 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
4139 warning (0, N_("%<-mquad-memory-atomic%> requires 64-bit mode"));
4141 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
4142 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
4145 /* Non-atomic quad memory load/store are disabled for little endian, since
4146 the words are reversed, but atomic operations can still be done by
4147 swapping the words. */
4148 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
4150 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4151 warning (0, N_("%<-mquad-memory%> is not available in little endian "
4154 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
4157 /* Assume if the user asked for normal quad memory instructions, they want
4158 the atomic versions as well, unless they explicity told us not to use quad
4159 word atomic instructions. */
4160 if (TARGET_QUAD_MEMORY
4161 && !TARGET_QUAD_MEMORY_ATOMIC
4162 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
4163 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
4165 /* If we can shrink-wrap the TOC register save separately, then use
4166 -msave-toc-indirect unless explicitly disabled. */
4167 if ((rs6000_isa_flags_explicit
& OPTION_MASK_SAVE_TOC_INDIRECT
) == 0
4168 && flag_shrink_wrap_separate
4169 && optimize_function_for_speed_p (cfun
))
4170 rs6000_isa_flags
|= OPTION_MASK_SAVE_TOC_INDIRECT
;
4172 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4173 generating power8 instructions. Power9 does not optimize power8 fusion
4175 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
4177 if (processor_target_table
[tune_index
].processor
== PROCESSOR_POWER8
)
4178 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4180 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4183 /* Setting additional fusion flags turns on base fusion. */
4184 if (!TARGET_P8_FUSION
&& TARGET_P8_FUSION_SIGN
)
4186 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4188 if (TARGET_P8_FUSION_SIGN
)
4189 error ("%qs requires %qs", "-mpower8-fusion-sign",
4192 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4195 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4198 /* Power8 does not fuse sign extended loads with the addis. If we are
4199 optimizing at high levels for speed, convert a sign extended load into a
4200 zero extending load, and an explicit sign extension. */
4201 if (TARGET_P8_FUSION
4202 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
4203 && optimize_function_for_speed_p (cfun
)
4205 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
4207 /* ISA 3.0 vector instructions include ISA 2.07. */
4208 if (TARGET_P9_VECTOR
&& !TARGET_P8_VECTOR
)
4210 /* We prefer to not mention undocumented options in
4211 error messages. However, if users have managed to select
4212 power9-vector without selecting power8-vector, they
4213 already know about undocumented flags. */
4214 if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) &&
4215 (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
))
4216 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4217 else if ((rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
) == 0)
4219 rs6000_isa_flags
&= ~OPTION_MASK_P9_VECTOR
;
4220 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4221 rs6000_isa_flags_explicit
|= OPTION_MASK_P9_VECTOR
;
4225 /* OPTION_MASK_P9_VECTOR is explicit and
4226 OPTION_MASK_P8_VECTOR is not explicit. */
4227 rs6000_isa_flags
|= OPTION_MASK_P8_VECTOR
;
4228 rs6000_isa_flags_explicit
|= OPTION_MASK_P8_VECTOR
;
4232 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4233 support. If we only have ISA 2.06 support, and the user did not specify
4234 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4235 but we don't enable the full vectorization support */
4236 if (TARGET_ALLOW_MOVMISALIGN
== -1 && TARGET_P8_VECTOR
&& TARGET_DIRECT_MOVE
)
4237 TARGET_ALLOW_MOVMISALIGN
= 1;
4239 else if (TARGET_ALLOW_MOVMISALIGN
&& !TARGET_VSX
)
4241 if (TARGET_ALLOW_MOVMISALIGN
> 0
4242 && global_options_set
.x_TARGET_ALLOW_MOVMISALIGN
)
4243 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4245 TARGET_ALLOW_MOVMISALIGN
= 0;
4248 /* Determine when unaligned vector accesses are permitted, and when
4249 they are preferred over masked Altivec loads. Note that if
4250 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4251 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4253 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4257 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4258 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4260 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4263 else if (!TARGET_ALLOW_MOVMISALIGN
)
4265 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4266 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4267 "-mallow-movmisalign");
4269 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4273 /* Use long double size to select the appropriate long double. We use
4274 TYPE_PRECISION to differentiate the 3 different long double types. We map
4275 128 into the precision used for TFmode. */
4276 int default_long_double_size
= (RS6000_DEFAULT_LONG_DOUBLE_SIZE
== 64
4278 : FLOAT_PRECISION_TFmode
);
4280 /* Set long double size before the IEEE 128-bit tests. */
4281 if (!global_options_set
.x_rs6000_long_double_type_size
)
4283 if (main_target_opt
!= NULL
4284 && (main_target_opt
->x_rs6000_long_double_type_size
4285 != default_long_double_size
))
4286 error ("target attribute or pragma changes long double size");
4288 rs6000_long_double_type_size
= default_long_double_size
;
4290 else if (rs6000_long_double_type_size
== 128)
4291 rs6000_long_double_type_size
= FLOAT_PRECISION_TFmode
;
4292 else if (global_options_set
.x_rs6000_ieeequad
)
4294 if (global_options
.x_rs6000_ieeequad
)
4295 error ("%qs requires %qs", "-mabi=ieeelongdouble", "-mlong-double-128");
4297 error ("%qs requires %qs", "-mabi=ibmlongdouble", "-mlong-double-128");
4300 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4301 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4302 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4303 those systems will not pick up this default. Warn if the user changes the
4304 default unless -Wno-psabi. */
4305 if (!global_options_set
.x_rs6000_ieeequad
)
4306 rs6000_ieeequad
= TARGET_IEEEQUAD_DEFAULT
;
4310 if (global_options
.x_rs6000_ieeequad
4311 && (!TARGET_POPCNTD
|| !TARGET_VSX
))
4312 error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
4314 if (rs6000_ieeequad
!= TARGET_IEEEQUAD_DEFAULT
&& TARGET_LONG_DOUBLE_128
)
4316 static bool warned_change_long_double
;
4317 if (!warned_change_long_double
)
4319 warned_change_long_double
= true;
4320 if (TARGET_IEEEQUAD
)
4321 warning (OPT_Wpsabi
, "Using IEEE extended precision long double");
4323 warning (OPT_Wpsabi
, "Using IBM extended precision long double");
4328 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4329 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4330 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4331 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4332 the keyword as well as the type. */
4333 TARGET_FLOAT128_TYPE
= TARGET_FLOAT128_ENABLE_TYPE
&& TARGET_VSX
;
4335 /* IEEE 128-bit floating point requires VSX support. */
4336 if (TARGET_FLOAT128_KEYWORD
)
4340 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) != 0)
4341 error ("%qs requires VSX support", "%<-mfloat128%>");
4343 TARGET_FLOAT128_TYPE
= 0;
4344 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_KEYWORD
4345 | OPTION_MASK_FLOAT128_HW
);
4347 else if (!TARGET_FLOAT128_TYPE
)
4349 TARGET_FLOAT128_TYPE
= 1;
4350 warning (0, "The %<-mfloat128%> option may not be fully supported");
4354 /* Enable the __float128 keyword under Linux by default. */
4355 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_KEYWORD
4356 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) == 0)
4357 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_KEYWORD
;
4359 /* If we have are supporting the float128 type and full ISA 3.0 support,
4360 enable -mfloat128-hardware by default. However, don't enable the
4361 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4362 because sometimes the compiler wants to put things in an integer
4363 container, and if we don't have __int128 support, it is impossible. */
4364 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_HW
&& TARGET_64BIT
4365 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) == ISA_3_0_MASKS_IEEE
4366 && !(rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
))
4367 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_HW
;
4369 if (TARGET_FLOAT128_HW
4370 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) != ISA_3_0_MASKS_IEEE
)
4372 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4373 error ("%qs requires full ISA 3.0 support", "%<-mfloat128-hardware%>");
4375 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4378 if (TARGET_FLOAT128_HW
&& !TARGET_64BIT
)
4380 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4381 error ("%qs requires %qs", "%<-mfloat128-hardware%>", "-m64");
4383 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4386 /* Print the options after updating the defaults. */
4387 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4388 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
4390 /* E500mc does "better" if we inline more aggressively. Respect the
4391 user's opinion, though. */
4392 if (rs6000_block_move_inline_limit
== 0
4393 && (rs6000_tune
== PROCESSOR_PPCE500MC
4394 || rs6000_tune
== PROCESSOR_PPCE500MC64
4395 || rs6000_tune
== PROCESSOR_PPCE5500
4396 || rs6000_tune
== PROCESSOR_PPCE6500
))
4397 rs6000_block_move_inline_limit
= 128;
4399 /* store_one_arg depends on expand_block_move to handle at least the
4400 size of reg_parm_stack_space. */
4401 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
4402 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
4406 /* If the appropriate debug option is enabled, replace the target hooks
4407 with debug versions that call the real version and then prints
4408 debugging information. */
4409 if (TARGET_DEBUG_COST
)
4411 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
4412 targetm
.address_cost
= rs6000_debug_address_cost
;
4413 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
4416 if (TARGET_DEBUG_ADDR
)
4418 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
4419 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
4420 rs6000_secondary_reload_class_ptr
4421 = rs6000_debug_secondary_reload_class
;
4422 targetm
.secondary_memory_needed
4423 = rs6000_debug_secondary_memory_needed
;
4424 targetm
.can_change_mode_class
4425 = rs6000_debug_can_change_mode_class
;
4426 rs6000_preferred_reload_class_ptr
4427 = rs6000_debug_preferred_reload_class
;
4428 rs6000_legitimize_reload_address_ptr
4429 = rs6000_debug_legitimize_reload_address
;
4430 rs6000_mode_dependent_address_ptr
4431 = rs6000_debug_mode_dependent_address
;
4434 if (rs6000_veclibabi_name
)
4436 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
4437 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
4440 error ("unknown vectorization library ABI type (%qs) for "
4441 "%qs switch", rs6000_veclibabi_name
, "-mveclibabi=");
4447 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4448 target attribute or pragma which automatically enables both options,
4449 unless the altivec ABI was set. This is set by default for 64-bit, but
4451 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4453 TARGET_FLOAT128_TYPE
= 0;
4454 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
4455 | OPTION_MASK_FLOAT128_KEYWORD
)
4456 & ~rs6000_isa_flags_explicit
);
4459 /* Enable Altivec ABI for AIX -maltivec. */
4460 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
4462 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4463 error ("target attribute or pragma changes AltiVec ABI");
4465 rs6000_altivec_abi
= 1;
4468 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4469 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4470 be explicitly overridden in either case. */
4473 if (!global_options_set
.x_rs6000_altivec_abi
4474 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
4476 if (main_target_opt
!= NULL
&&
4477 !main_target_opt
->x_rs6000_altivec_abi
)
4478 error ("target attribute or pragma changes AltiVec ABI");
4480 rs6000_altivec_abi
= 1;
4484 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4485 So far, the only darwin64 targets are also MACH-O. */
4487 && DEFAULT_ABI
== ABI_DARWIN
4490 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
4491 error ("target attribute or pragma changes darwin64 ABI");
4494 rs6000_darwin64_abi
= 1;
4495 /* Default to natural alignment, for better performance. */
4496 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
4500 /* Place FP constants in the constant pool instead of TOC
4501 if section anchors enabled. */
4502 if (flag_section_anchors
4503 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
4504 TARGET_NO_FP_IN_TOC
= 1;
4506 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4507 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
4509 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4510 SUBTARGET_OVERRIDE_OPTIONS
;
4512 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4513 SUBSUBTARGET_OVERRIDE_OPTIONS
;
4515 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4516 SUB3TARGET_OVERRIDE_OPTIONS
;
4519 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4520 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
4522 rs6000_always_hint
= (rs6000_tune
!= PROCESSOR_POWER4
4523 && rs6000_tune
!= PROCESSOR_POWER5
4524 && rs6000_tune
!= PROCESSOR_POWER6
4525 && rs6000_tune
!= PROCESSOR_POWER7
4526 && rs6000_tune
!= PROCESSOR_POWER8
4527 && rs6000_tune
!= PROCESSOR_POWER9
4528 && rs6000_tune
!= PROCESSOR_PPCA2
4529 && rs6000_tune
!= PROCESSOR_CELL
4530 && rs6000_tune
!= PROCESSOR_PPC476
);
4531 rs6000_sched_groups
= (rs6000_tune
== PROCESSOR_POWER4
4532 || rs6000_tune
== PROCESSOR_POWER5
4533 || rs6000_tune
== PROCESSOR_POWER7
4534 || rs6000_tune
== PROCESSOR_POWER8
);
4535 rs6000_align_branch_targets
= (rs6000_tune
== PROCESSOR_POWER4
4536 || rs6000_tune
== PROCESSOR_POWER5
4537 || rs6000_tune
== PROCESSOR_POWER6
4538 || rs6000_tune
== PROCESSOR_POWER7
4539 || rs6000_tune
== PROCESSOR_POWER8
4540 || rs6000_tune
== PROCESSOR_POWER9
4541 || rs6000_tune
== PROCESSOR_PPCE500MC
4542 || rs6000_tune
== PROCESSOR_PPCE500MC64
4543 || rs6000_tune
== PROCESSOR_PPCE5500
4544 || rs6000_tune
== PROCESSOR_PPCE6500
);
4546 /* Allow debug switches to override the above settings. These are set to -1
4547 in rs6000.opt to indicate the user hasn't directly set the switch. */
4548 if (TARGET_ALWAYS_HINT
>= 0)
4549 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
4551 if (TARGET_SCHED_GROUPS
>= 0)
4552 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
4554 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
4555 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
4557 rs6000_sched_restricted_insns_priority
4558 = (rs6000_sched_groups
? 1 : 0);
4560 /* Handle -msched-costly-dep option. */
4561 rs6000_sched_costly_dep
4562 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
4564 if (rs6000_sched_costly_dep_str
)
4566 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
4567 rs6000_sched_costly_dep
= no_dep_costly
;
4568 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
4569 rs6000_sched_costly_dep
= all_deps_costly
;
4570 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
4571 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
4572 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
4573 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
4575 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
4576 atoi (rs6000_sched_costly_dep_str
));
4579 /* Handle -minsert-sched-nops option. */
4580 rs6000_sched_insert_nops
4581 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
4583 if (rs6000_sched_insert_nops_str
)
4585 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
4586 rs6000_sched_insert_nops
= sched_finish_none
;
4587 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
4588 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
4589 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
4590 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
4592 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
4593 atoi (rs6000_sched_insert_nops_str
));
4596 /* Handle stack protector */
4597 if (!global_options_set
.x_rs6000_stack_protector_guard
)
4598 #ifdef TARGET_THREAD_SSP_OFFSET
4599 rs6000_stack_protector_guard
= SSP_TLS
;
4601 rs6000_stack_protector_guard
= SSP_GLOBAL
;
4604 #ifdef TARGET_THREAD_SSP_OFFSET
4605 rs6000_stack_protector_guard_offset
= TARGET_THREAD_SSP_OFFSET
;
4606 rs6000_stack_protector_guard_reg
= TARGET_64BIT
? 13 : 2;
4609 if (global_options_set
.x_rs6000_stack_protector_guard_offset_str
)
4612 const char *str
= rs6000_stack_protector_guard_offset_str
;
4615 long offset
= strtol (str
, &endp
, 0);
4616 if (!*str
|| *endp
|| errno
)
4617 error ("%qs is not a valid number in %qs", str
,
4618 "-mstack-protector-guard-offset=");
4620 if (!IN_RANGE (offset
, -0x8000, 0x7fff)
4621 || (TARGET_64BIT
&& (offset
& 3)))
4622 error ("%qs is not a valid offset in %qs", str
,
4623 "-mstack-protector-guard-offset=");
4625 rs6000_stack_protector_guard_offset
= offset
;
4628 if (global_options_set
.x_rs6000_stack_protector_guard_reg_str
)
4630 const char *str
= rs6000_stack_protector_guard_reg_str
;
4631 int reg
= decode_reg_name (str
);
4633 if (!IN_RANGE (reg
, 1, 31))
4634 error ("%qs is not a valid base register in %qs", str
,
4635 "-mstack-protector-guard-reg=");
4637 rs6000_stack_protector_guard_reg
= reg
;
4640 if (rs6000_stack_protector_guard
== SSP_TLS
4641 && !IN_RANGE (rs6000_stack_protector_guard_reg
, 1, 31))
4642 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4646 #ifdef TARGET_REGNAMES
4647 /* If the user desires alternate register names, copy in the
4648 alternate names now. */
4649 if (TARGET_REGNAMES
)
4650 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
4653 /* Set aix_struct_return last, after the ABI is determined.
4654 If -maix-struct-return or -msvr4-struct-return was explicitly
4655 used, don't override with the ABI default. */
4656 if (!global_options_set
.x_aix_struct_return
)
4657 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
4660 /* IBM XL compiler defaults to unsigned bitfields. */
4661 if (TARGET_XL_COMPAT
)
4662 flag_signed_bitfields
= 0;
4665 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
4666 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
4668 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
4670 /* We can only guarantee the availability of DI pseudo-ops when
4671 assembling for 64-bit targets. */
4674 targetm
.asm_out
.aligned_op
.di
= NULL
;
4675 targetm
.asm_out
.unaligned_op
.di
= NULL
;
4679 /* Set branch target alignment, if not optimizing for size. */
4682 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4683 aligned 8byte to avoid misprediction by the branch predictor. */
4684 if (rs6000_tune
== PROCESSOR_TITAN
4685 || rs6000_tune
== PROCESSOR_CELL
)
4687 if (flag_align_functions
&& !str_align_functions
)
4688 str_align_functions
= "8";
4689 if (flag_align_jumps
&& !str_align_jumps
)
4690 str_align_jumps
= "8";
4691 if (flag_align_loops
&& !str_align_loops
)
4692 str_align_loops
= "8";
4694 if (rs6000_align_branch_targets
)
4696 if (flag_align_functions
&& !str_align_functions
)
4697 str_align_functions
= "16";
4698 if (flag_align_jumps
&& !str_align_jumps
)
4699 str_align_jumps
= "16";
4700 if (flag_align_loops
&& !str_align_loops
)
4702 can_override_loop_align
= 1;
4703 str_align_loops
= "16";
4707 if (flag_align_jumps
&& !str_align_jumps
)
4708 str_align_jumps
= "16";
4709 if (flag_align_loops
&& !str_align_loops
)
4710 str_align_loops
= "16";
4713 /* Arrange to save and restore machine status around nested functions. */
4714 init_machine_status
= rs6000_init_machine_status
;
4716 /* We should always be splitting complex arguments, but we can't break
4717 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4718 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
4719 targetm
.calls
.split_complex_arg
= NULL
;
4721 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4722 if (DEFAULT_ABI
== ABI_AIX
)
4723 targetm
.calls
.custom_function_descriptors
= 0;
4726 /* Initialize rs6000_cost with the appropriate target costs. */
4728 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
4730 switch (rs6000_tune
)
4732 case PROCESSOR_RS64A
:
4733 rs6000_cost
= &rs64a_cost
;
4736 case PROCESSOR_MPCCORE
:
4737 rs6000_cost
= &mpccore_cost
;
4740 case PROCESSOR_PPC403
:
4741 rs6000_cost
= &ppc403_cost
;
4744 case PROCESSOR_PPC405
:
4745 rs6000_cost
= &ppc405_cost
;
4748 case PROCESSOR_PPC440
:
4749 rs6000_cost
= &ppc440_cost
;
4752 case PROCESSOR_PPC476
:
4753 rs6000_cost
= &ppc476_cost
;
4756 case PROCESSOR_PPC601
:
4757 rs6000_cost
= &ppc601_cost
;
4760 case PROCESSOR_PPC603
:
4761 rs6000_cost
= &ppc603_cost
;
4764 case PROCESSOR_PPC604
:
4765 rs6000_cost
= &ppc604_cost
;
4768 case PROCESSOR_PPC604e
:
4769 rs6000_cost
= &ppc604e_cost
;
4772 case PROCESSOR_PPC620
:
4773 rs6000_cost
= &ppc620_cost
;
4776 case PROCESSOR_PPC630
:
4777 rs6000_cost
= &ppc630_cost
;
4780 case PROCESSOR_CELL
:
4781 rs6000_cost
= &ppccell_cost
;
4784 case PROCESSOR_PPC750
:
4785 case PROCESSOR_PPC7400
:
4786 rs6000_cost
= &ppc750_cost
;
4789 case PROCESSOR_PPC7450
:
4790 rs6000_cost
= &ppc7450_cost
;
4793 case PROCESSOR_PPC8540
:
4794 case PROCESSOR_PPC8548
:
4795 rs6000_cost
= &ppc8540_cost
;
4798 case PROCESSOR_PPCE300C2
:
4799 case PROCESSOR_PPCE300C3
:
4800 rs6000_cost
= &ppce300c2c3_cost
;
4803 case PROCESSOR_PPCE500MC
:
4804 rs6000_cost
= &ppce500mc_cost
;
4807 case PROCESSOR_PPCE500MC64
:
4808 rs6000_cost
= &ppce500mc64_cost
;
4811 case PROCESSOR_PPCE5500
:
4812 rs6000_cost
= &ppce5500_cost
;
4815 case PROCESSOR_PPCE6500
:
4816 rs6000_cost
= &ppce6500_cost
;
4819 case PROCESSOR_TITAN
:
4820 rs6000_cost
= &titan_cost
;
4823 case PROCESSOR_POWER4
:
4824 case PROCESSOR_POWER5
:
4825 rs6000_cost
= &power4_cost
;
4828 case PROCESSOR_POWER6
:
4829 rs6000_cost
= &power6_cost
;
4832 case PROCESSOR_POWER7
:
4833 rs6000_cost
= &power7_cost
;
4836 case PROCESSOR_POWER8
:
4837 rs6000_cost
= &power8_cost
;
4840 case PROCESSOR_POWER9
:
4841 rs6000_cost
= &power9_cost
;
4844 case PROCESSOR_PPCA2
:
4845 rs6000_cost
= &ppca2_cost
;
4854 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
4855 rs6000_cost
->simultaneous_prefetches
,
4856 global_options
.x_param_values
,
4857 global_options_set
.x_param_values
);
4858 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
4859 global_options
.x_param_values
,
4860 global_options_set
.x_param_values
);
4861 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
4862 rs6000_cost
->cache_line_size
,
4863 global_options
.x_param_values
,
4864 global_options_set
.x_param_values
);
4865 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
4866 global_options
.x_param_values
,
4867 global_options_set
.x_param_values
);
4869 /* Increase loop peeling limits based on performance analysis. */
4870 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
4871 global_options
.x_param_values
,
4872 global_options_set
.x_param_values
);
4873 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
4874 global_options
.x_param_values
,
4875 global_options_set
.x_param_values
);
4877 /* Use the 'model' -fsched-pressure algorithm by default. */
4878 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
,
4879 SCHED_PRESSURE_MODEL
,
4880 global_options
.x_param_values
,
4881 global_options_set
.x_param_values
);
4883 /* If using typedef char *va_list, signal that
4884 __builtin_va_start (&ap, 0) can be optimized to
4885 ap = __builtin_next_arg (0). */
4886 if (DEFAULT_ABI
!= ABI_V4
)
4887 targetm
.expand_builtin_va_start
= NULL
;
4890 /* If not explicitly specified via option, decide whether to generate indexed
4891 load/store instructions. A value of -1 indicates that the
4892 initial value of this variable has not been overwritten. During
4893 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4894 if (TARGET_AVOID_XFORM
== -1)
4895 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4896 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4897 need indexed accesses and the type used is the scalar type of the element
4898 being loaded or stored. */
4899 TARGET_AVOID_XFORM
= (rs6000_tune
== PROCESSOR_POWER6
&& TARGET_CMPB
4900 && !TARGET_ALTIVEC
);
4902 /* Set the -mrecip options. */
4903 if (rs6000_recip_name
)
4905 char *p
= ASTRDUP (rs6000_recip_name
);
4907 unsigned int mask
, i
;
4910 while ((q
= strtok (p
, ",")) != NULL
)
4921 if (!strcmp (q
, "default"))
4922 mask
= ((TARGET_RECIP_PRECISION
)
4923 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
4926 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
4927 if (!strcmp (q
, recip_options
[i
].string
))
4929 mask
= recip_options
[i
].mask
;
4933 if (i
== ARRAY_SIZE (recip_options
))
4935 error ("unknown option for %<%s=%s%>", "-mrecip", q
);
4943 rs6000_recip_control
&= ~mask
;
4945 rs6000_recip_control
|= mask
;
4949 /* Set the builtin mask of the various options used that could affect which
4950 builtins were used. In the past we used target_flags, but we've run out
4951 of bits, and some options are no longer in target_flags. */
4952 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4953 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4954 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
4955 rs6000_builtin_mask
);
4957 /* Initialize all of the registers. */
4958 rs6000_init_hard_regno_mode_ok (global_init_p
);
4960 /* Save the initial options in case the user does function specific options */
4962 target_option_default_node
= target_option_current_node
4963 = build_target_option_node (&global_options
);
4965 /* If not explicitly specified via option, decide whether to generate the
4966 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4967 if (TARGET_LINK_STACK
== -1)
4968 SET_TARGET_LINK_STACK (rs6000_tune
== PROCESSOR_PPC476
&& flag_pic
);
4970 /* Deprecate use of -mno-speculate-indirect-jumps. */
4971 if (!rs6000_speculate_indirect_jumps
)
4972 warning (0, "%qs is deprecated and not recommended in any circumstances",
4973 "-mno-speculate-indirect-jumps");
4978 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4979 define the target cpu type. */
4982 rs6000_option_override (void)
4984 (void) rs6000_option_override_internal (true);
4988 /* Implement targetm.vectorize.builtin_mask_for_load. */
4990 rs6000_builtin_mask_for_load (void)
4992 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4993 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
4994 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
4995 return altivec_builtin_mask_for_load
;
5000 /* Implement LOOP_ALIGN. */
5002 rs6000_loop_align (rtx label
)
5007 /* Don't override loop alignment if -falign-loops was specified. */
5008 if (!can_override_loop_align
)
5011 bb
= BLOCK_FOR_INSN (label
);
5012 ninsns
= num_loop_insns(bb
->loop_father
);
5014 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5015 if (ninsns
> 4 && ninsns
<= 8
5016 && (rs6000_tune
== PROCESSOR_POWER4
5017 || rs6000_tune
== PROCESSOR_POWER5
5018 || rs6000_tune
== PROCESSOR_POWER6
5019 || rs6000_tune
== PROCESSOR_POWER7
5020 || rs6000_tune
== PROCESSOR_POWER8
))
5021 return align_flags (5);
5026 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5027 after applying N number of iterations. This routine does not determine
5028 how may iterations are required to reach desired alignment. */
5031 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
5038 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
5041 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
5051 /* Assuming that all other types are naturally aligned. CHECKME! */
5056 /* Return true if the vector misalignment factor is supported by the
5059 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
5066 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5069 /* Return if movmisalign pattern is not supported for this mode. */
5070 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
5073 if (misalignment
== -1)
5075 /* Misalignment factor is unknown at compile time but we know
5076 it's word aligned. */
5077 if (rs6000_vector_alignment_reachable (type
, is_packed
))
5079 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
5081 if (element_size
== 64 || element_size
== 32)
5088 /* VSX supports word-aligned vector. */
5089 if (misalignment
% 4 == 0)
5095 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5097 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
5098 tree vectype
, int misalign
)
5103 switch (type_of_cost
)
5113 case cond_branch_not_taken
:
5122 case vec_promote_demote
:
5128 case cond_branch_taken
:
5131 case unaligned_load
:
5132 case vector_gather_load
:
5133 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5136 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5138 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5140 /* Double word aligned. */
5148 /* Double word aligned. */
5152 /* Unknown misalignment. */
5165 /* Misaligned loads are not supported. */
5170 case unaligned_store
:
5171 case vector_scatter_store
:
5172 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5175 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5177 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5179 /* Double word aligned. */
5187 /* Double word aligned. */
5191 /* Unknown misalignment. */
5204 /* Misaligned stores are not supported. */
5210 /* This is a rough approximation assuming non-constant elements
5211 constructed into a vector via element insertion. FIXME:
5212 vec_construct is not granular enough for uniformly good
5213 decisions. If the initialization is a splat, this is
5214 cheaper than we estimate. Improve this someday. */
5215 elem_type
= TREE_TYPE (vectype
);
5216 /* 32-bit vectors loaded into registers are stored as double
5217 precision, so we need 2 permutes, 2 converts, and 1 merge
5218 to construct a vector of short floats from them. */
5219 if (SCALAR_FLOAT_TYPE_P (elem_type
)
5220 && TYPE_PRECISION (elem_type
) == 32)
5222 /* On POWER9, integer vector types are built up in GPRs and then
5223 use a direct move (2 cycles). For POWER8 this is even worse,
5224 as we need two direct moves and a merge, and the direct moves
5226 else if (INTEGRAL_TYPE_P (elem_type
))
5228 if (TARGET_P9_VECTOR
)
5229 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 2;
5231 return TYPE_VECTOR_SUBPARTS (vectype
) - 1 + 5;
5234 /* V2DFmode doesn't need a direct move. */
5242 /* Implement targetm.vectorize.preferred_simd_mode. */
5245 rs6000_preferred_simd_mode (scalar_mode mode
)
5254 if (TARGET_ALTIVEC
|| TARGET_VSX
)
5274 typedef struct _rs6000_cost_data
5276 struct loop
*loop_info
;
5280 /* Test for likely overcommitment of vector hardware resources. If a
5281 loop iteration is relatively large, and too large a percentage of
5282 instructions in the loop are vectorized, the cost model may not
5283 adequately reflect delays from unavailable vector resources.
5284 Penalize the loop body cost for this case. */
5287 rs6000_density_test (rs6000_cost_data
*data
)
5289 const int DENSITY_PCT_THRESHOLD
= 85;
5290 const int DENSITY_SIZE_THRESHOLD
= 70;
5291 const int DENSITY_PENALTY
= 10;
5292 struct loop
*loop
= data
->loop_info
;
5293 basic_block
*bbs
= get_loop_body (loop
);
5294 int nbbs
= loop
->num_nodes
;
5295 loop_vec_info loop_vinfo
= loop_vec_info_for_loop (data
->loop_info
);
5296 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
5299 for (i
= 0; i
< nbbs
; i
++)
5301 basic_block bb
= bbs
[i
];
5302 gimple_stmt_iterator gsi
;
5304 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
5306 gimple
*stmt
= gsi_stmt (gsi
);
5307 stmt_vec_info stmt_info
= loop_vinfo
->lookup_stmt (stmt
);
5309 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
5310 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
5316 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
5318 if (density_pct
> DENSITY_PCT_THRESHOLD
5319 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
5321 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
5322 if (dump_enabled_p ())
5323 dump_printf_loc (MSG_NOTE
, vect_location
,
5324 "density %d%%, cost %d exceeds threshold, penalizing "
5325 "loop body cost by %d%%", density_pct
,
5326 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
5330 /* Implement targetm.vectorize.init_cost. */
5332 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5333 instruction is needed by the vectorization. */
5334 static bool rs6000_vect_nonmem
;
5337 rs6000_init_cost (struct loop
*loop_info
)
5339 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
5340 data
->loop_info
= loop_info
;
5341 data
->cost
[vect_prologue
] = 0;
5342 data
->cost
[vect_body
] = 0;
5343 data
->cost
[vect_epilogue
] = 0;
5344 rs6000_vect_nonmem
= false;
5348 /* Implement targetm.vectorize.add_stmt_cost. */
5351 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
5352 struct _stmt_vec_info
*stmt_info
, int misalign
,
5353 enum vect_cost_model_location where
)
5355 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5356 unsigned retval
= 0;
5358 if (flag_vect_cost_model
)
5360 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
5361 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
5363 /* Statements in an inner loop relative to the loop being
5364 vectorized are weighted more heavily. The value here is
5365 arbitrary and could potentially be improved with analysis. */
5366 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
5367 count
*= 50; /* FIXME. */
5369 retval
= (unsigned) (count
* stmt_cost
);
5370 cost_data
->cost
[where
] += retval
;
5372 /* Check whether we're doing something other than just a copy loop.
5373 Not all such loops may be profitably vectorized; see
5374 rs6000_finish_cost. */
5375 if ((kind
== vec_to_scalar
|| kind
== vec_perm
5376 || kind
== vec_promote_demote
|| kind
== vec_construct
5377 || kind
== scalar_to_vec
)
5378 || (where
== vect_body
&& kind
== vector_stmt
))
5379 rs6000_vect_nonmem
= true;
5385 /* Implement targetm.vectorize.finish_cost. */
5388 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
5389 unsigned *body_cost
, unsigned *epilogue_cost
)
5391 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5393 if (cost_data
->loop_info
)
5394 rs6000_density_test (cost_data
);
5396 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5397 that require versioning for any reason. The vectorization is at
5398 best a wash inside the loop, and the versioning checks make
5399 profitability highly unlikely and potentially quite harmful. */
5400 if (cost_data
->loop_info
)
5402 loop_vec_info vec_info
= loop_vec_info_for_loop (cost_data
->loop_info
);
5403 if (!rs6000_vect_nonmem
5404 && LOOP_VINFO_VECT_FACTOR (vec_info
) == 2
5405 && LOOP_REQUIRES_VERSIONING (vec_info
))
5406 cost_data
->cost
[vect_body
] += 10000;
5409 *prologue_cost
= cost_data
->cost
[vect_prologue
];
5410 *body_cost
= cost_data
->cost
[vect_body
];
5411 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
5414 /* Implement targetm.vectorize.destroy_cost_data. */
5417 rs6000_destroy_cost_data (void *data
)
5422 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5423 library with vectorized intrinsics. */
5426 rs6000_builtin_vectorized_libmass (combined_fn fn
, tree type_out
,
5430 const char *suffix
= NULL
;
5431 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
5434 machine_mode el_mode
, in_mode
;
5437 /* Libmass is suitable for unsafe math only as it does not correctly support
5438 parts of IEEE with the required precision such as denormals. Only support
5439 it if we have VSX to use the simd d2 or f4 functions.
5440 XXX: Add variable length support. */
5441 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
5444 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5445 n
= TYPE_VECTOR_SUBPARTS (type_out
);
5446 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5447 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5448 if (el_mode
!= in_mode
5484 if (el_mode
== DFmode
&& n
== 2)
5486 bdecl
= mathfn_built_in (double_type_node
, fn
);
5487 suffix
= "d2"; /* pow -> powd2 */
5489 else if (el_mode
== SFmode
&& n
== 4)
5491 bdecl
= mathfn_built_in (float_type_node
, fn
);
5492 suffix
= "4"; /* powf -> powf4 */
5504 gcc_assert (suffix
!= NULL
);
5505 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
5509 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
5510 strcat (name
, suffix
);
5513 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
5514 else if (n_args
== 2)
5515 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
5519 /* Build a function declaration for the vectorized function. */
5520 new_fndecl
= build_decl (BUILTINS_LOCATION
,
5521 FUNCTION_DECL
, get_identifier (name
), fntype
);
5522 TREE_PUBLIC (new_fndecl
) = 1;
5523 DECL_EXTERNAL (new_fndecl
) = 1;
5524 DECL_IS_NOVOPS (new_fndecl
) = 1;
5525 TREE_READONLY (new_fndecl
) = 1;
5530 /* Returns a function decl for a vectorized version of the builtin function
5531 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5532 if it is not available. */
5535 rs6000_builtin_vectorized_function (unsigned int fn
, tree type_out
,
5538 machine_mode in_mode
, out_mode
;
5541 if (TARGET_DEBUG_BUILTIN
)
5542 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5543 combined_fn_name (combined_fn (fn
)),
5544 GET_MODE_NAME (TYPE_MODE (type_out
)),
5545 GET_MODE_NAME (TYPE_MODE (type_in
)));
5547 if (TREE_CODE (type_out
) != VECTOR_TYPE
5548 || TREE_CODE (type_in
) != VECTOR_TYPE
)
5551 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5552 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5553 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5554 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5559 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5560 && out_mode
== DFmode
&& out_n
== 2
5561 && in_mode
== DFmode
&& in_n
== 2)
5562 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
5563 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5564 && out_mode
== SFmode
&& out_n
== 4
5565 && in_mode
== SFmode
&& in_n
== 4)
5566 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
5567 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5568 && out_mode
== SFmode
&& out_n
== 4
5569 && in_mode
== SFmode
&& in_n
== 4)
5570 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
5573 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5574 && out_mode
== DFmode
&& out_n
== 2
5575 && in_mode
== DFmode
&& in_n
== 2)
5576 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
5577 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5578 && out_mode
== SFmode
&& out_n
== 4
5579 && in_mode
== SFmode
&& in_n
== 4)
5580 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
5581 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5582 && out_mode
== SFmode
&& out_n
== 4
5583 && in_mode
== SFmode
&& in_n
== 4)
5584 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
5587 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5588 && out_mode
== DFmode
&& out_n
== 2
5589 && in_mode
== DFmode
&& in_n
== 2)
5590 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
5591 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5592 && out_mode
== SFmode
&& out_n
== 4
5593 && in_mode
== SFmode
&& in_n
== 4)
5594 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
5595 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5596 && out_mode
== SFmode
&& out_n
== 4
5597 && in_mode
== SFmode
&& in_n
== 4)
5598 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
5601 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5602 && out_mode
== DFmode
&& out_n
== 2
5603 && in_mode
== DFmode
&& in_n
== 2)
5604 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
5605 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5606 && out_mode
== SFmode
&& out_n
== 4
5607 && in_mode
== SFmode
&& in_n
== 4)
5608 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
5609 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5610 && out_mode
== SFmode
&& out_n
== 4
5611 && in_mode
== SFmode
&& in_n
== 4)
5612 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5615 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5616 && out_mode
== DFmode
&& out_n
== 2
5617 && in_mode
== DFmode
&& in_n
== 2)
5618 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5619 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5620 && out_mode
== SFmode
&& out_n
== 4
5621 && in_mode
== SFmode
&& in_n
== 4)
5622 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5623 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5624 && out_mode
== SFmode
&& out_n
== 4
5625 && in_mode
== SFmode
&& in_n
== 4)
5626 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5629 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5630 && flag_unsafe_math_optimizations
5631 && out_mode
== DFmode
&& out_n
== 2
5632 && in_mode
== DFmode
&& in_n
== 2)
5633 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5634 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5635 && flag_unsafe_math_optimizations
5636 && out_mode
== SFmode
&& out_n
== 4
5637 && in_mode
== SFmode
&& in_n
== 4)
5638 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
5641 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5642 && !flag_trapping_math
5643 && out_mode
== DFmode
&& out_n
== 2
5644 && in_mode
== DFmode
&& in_n
== 2)
5645 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
5646 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5647 && !flag_trapping_math
5648 && out_mode
== SFmode
&& out_n
== 4
5649 && in_mode
== SFmode
&& in_n
== 4)
5650 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
5656 /* Generate calls to libmass if appropriate. */
5657 if (rs6000_veclib_handler
)
5658 return rs6000_veclib_handler (combined_fn (fn
), type_out
, type_in
);
5663 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5666 rs6000_builtin_md_vectorized_function (tree fndecl
, tree type_out
,
5669 machine_mode in_mode
, out_mode
;
5672 if (TARGET_DEBUG_BUILTIN
)
5673 fprintf (stderr
, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5674 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
5675 GET_MODE_NAME (TYPE_MODE (type_out
)),
5676 GET_MODE_NAME (TYPE_MODE (type_in
)));
5678 if (TREE_CODE (type_out
) != VECTOR_TYPE
5679 || TREE_CODE (type_in
) != VECTOR_TYPE
)
5682 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5683 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5684 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5685 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5687 enum rs6000_builtins fn
5688 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
5691 case RS6000_BUILTIN_RSQRTF
:
5692 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5693 && out_mode
== SFmode
&& out_n
== 4
5694 && in_mode
== SFmode
&& in_n
== 4)
5695 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
5697 case RS6000_BUILTIN_RSQRT
:
5698 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5699 && out_mode
== DFmode
&& out_n
== 2
5700 && in_mode
== DFmode
&& in_n
== 2)
5701 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
5703 case RS6000_BUILTIN_RECIPF
:
5704 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5705 && out_mode
== SFmode
&& out_n
== 4
5706 && in_mode
== SFmode
&& in_n
== 4)
5707 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
5709 case RS6000_BUILTIN_RECIP
:
5710 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5711 && out_mode
== DFmode
&& out_n
== 2
5712 && in_mode
== DFmode
&& in_n
== 2)
5713 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
5721 /* Default CPU string for rs6000*_file_start functions. */
5722 static const char *rs6000_default_cpu
;
5724 /* Do anything needed at the start of the asm file. */
5727 rs6000_file_start (void)
5730 const char *start
= buffer
;
5731 FILE *file
= asm_out_file
;
5733 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
5735 default_file_start ();
5737 if (flag_verbose_asm
)
5739 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
5741 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
5743 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
5747 if (global_options_set
.x_rs6000_cpu_index
)
5749 fprintf (file
, "%s -mcpu=%s", start
,
5750 processor_target_table
[rs6000_cpu_index
].name
);
5754 if (global_options_set
.x_rs6000_tune_index
)
5756 fprintf (file
, "%s -mtune=%s", start
,
5757 processor_target_table
[rs6000_tune_index
].name
);
5761 if (PPC405_ERRATUM77
)
5763 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
5767 #ifdef USING_ELFOS_H
5768 switch (rs6000_sdata
)
5770 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
5771 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
5772 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
5773 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
5776 if (rs6000_sdata
&& g_switch_value
)
5778 fprintf (file
, "%s -G %d", start
,
5788 #ifdef USING_ELFOS_H
5789 if (!(rs6000_default_cpu
&& rs6000_default_cpu
[0])
5790 && !global_options_set
.x_rs6000_cpu_index
)
5792 fputs ("\t.machine ", asm_out_file
);
5793 if ((rs6000_isa_flags
& OPTION_MASK_MODULO
) != 0)
5794 fputs ("power9\n", asm_out_file
);
5795 else if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
5796 fputs ("power8\n", asm_out_file
);
5797 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
5798 fputs ("power7\n", asm_out_file
);
5799 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
5800 fputs ("power6\n", asm_out_file
);
5801 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
5802 fputs ("power5\n", asm_out_file
);
5803 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
5804 fputs ("power4\n", asm_out_file
);
5805 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
5806 fputs ("ppc64\n", asm_out_file
);
5808 fputs ("ppc\n", asm_out_file
);
5812 if (DEFAULT_ABI
== ABI_ELFv2
)
5813 fprintf (file
, "\t.abiversion 2\n");
5817 /* Return nonzero if this function is known to have a null epilogue. */
5820 direct_return (void)
5822 if (reload_completed
)
5824 rs6000_stack_t
*info
= rs6000_stack_info ();
5826 if (info
->first_gp_reg_save
== 32
5827 && info
->first_fp_reg_save
== 64
5828 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
5829 && ! info
->lr_save_p
5830 && ! info
->cr_save_p
5831 && info
->vrsave_size
== 0
5839 /* Helper for num_insns_constant. Calculate number of instructions to
5840 load VALUE to a single gpr using combinations of addi, addis, ori,
5841 oris and sldi instructions. */
5844 num_insns_constant_gpr (HOST_WIDE_INT value
)
5846 /* signed constant loadable with addi */
5847 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
5850 /* constant loadable with addis */
5851 else if ((value
& 0xffff) == 0
5852 && (value
>> 31 == -1 || value
>> 31 == 0))
5855 else if (TARGET_POWERPC64
)
5857 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
5858 HOST_WIDE_INT high
= value
>> 31;
5860 if (high
== 0 || high
== -1)
5866 return num_insns_constant_gpr (high
) + 1;
5868 return num_insns_constant_gpr (low
) + 1;
5870 return (num_insns_constant_gpr (high
)
5871 + num_insns_constant_gpr (low
) + 1);
5878 /* Helper for num_insns_constant. Allow constants formed by the
5879 num_insns_constant_gpr sequences, plus li -1, rldicl/rldicr/rlwinm,
5880 and handle modes that require multiple gprs. */
5883 num_insns_constant_multi (HOST_WIDE_INT value
, machine_mode mode
)
5885 int nregs
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5889 HOST_WIDE_INT low
= sext_hwi (value
, BITS_PER_WORD
);
5890 int insns
= num_insns_constant_gpr (low
);
5892 /* We won't get more than 2 from num_insns_constant_gpr
5893 except when TARGET_POWERPC64 and mode is DImode or
5894 wider, so the register mode must be DImode. */
5895 && rs6000_is_valid_and_mask (GEN_INT (low
), DImode
))
5898 value
>>= BITS_PER_WORD
;
5903 /* Return the number of instructions it takes to form a constant in as
5904 many gprs are needed for MODE. */
5907 num_insns_constant (rtx op
, machine_mode mode
)
5911 switch (GET_CODE (op
))
5917 case CONST_WIDE_INT
:
5920 for (int i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
5921 insns
+= num_insns_constant_multi (CONST_WIDE_INT_ELT (op
, i
),
5928 const struct real_value
*rv
= CONST_DOUBLE_REAL_VALUE (op
);
5930 if (mode
== SFmode
|| mode
== SDmode
)
5935 REAL_VALUE_TO_TARGET_DECIMAL32 (*rv
, l
);
5937 REAL_VALUE_TO_TARGET_SINGLE (*rv
, l
);
5938 /* See the first define_split in rs6000.md handling a
5939 const_double_operand. */
5943 else if (mode
== DFmode
|| mode
== DDmode
)
5948 REAL_VALUE_TO_TARGET_DECIMAL64 (*rv
, l
);
5950 REAL_VALUE_TO_TARGET_DOUBLE (*rv
, l
);
5952 /* See the second (32-bit) and third (64-bit) define_split
5953 in rs6000.md handling a const_double_operand. */
5954 val
= (unsigned HOST_WIDE_INT
) l
[WORDS_BIG_ENDIAN
? 0 : 1] << 32;
5955 val
|= l
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffffUL
;
5958 else if (mode
== TFmode
|| mode
== TDmode
5959 || mode
== KFmode
|| mode
== IFmode
)
5965 REAL_VALUE_TO_TARGET_DECIMAL128 (*rv
, l
);
5967 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*rv
, l
);
5969 val
= (unsigned HOST_WIDE_INT
) l
[WORDS_BIG_ENDIAN
? 0 : 3] << 32;
5970 val
|= l
[WORDS_BIG_ENDIAN
? 1 : 2] & 0xffffffffUL
;
5971 insns
= num_insns_constant_multi (val
, DImode
);
5972 val
= (unsigned HOST_WIDE_INT
) l
[WORDS_BIG_ENDIAN
? 2 : 1] << 32;
5973 val
|= l
[WORDS_BIG_ENDIAN
? 3 : 0] & 0xffffffffUL
;
5974 insns
+= num_insns_constant_multi (val
, DImode
);
5986 return num_insns_constant_multi (val
, mode
);
5989 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5990 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5991 corresponding element of the vector, but for V4SFmode, the
5992 corresponding "float" is interpreted as an SImode integer. */
5995 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5999 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6000 gcc_assert (GET_MODE (op
) != V2DImode
6001 && GET_MODE (op
) != V2DFmode
);
6003 tmp
= CONST_VECTOR_ELT (op
, elt
);
6004 if (GET_MODE (op
) == V4SFmode
)
6005 tmp
= gen_lowpart (SImode
, tmp
);
6006 return INTVAL (tmp
);
6009 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6010 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6011 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6012 all items are set to the same value and contain COPIES replicas of the
6013 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6014 operand and the others are set to the value of the operand's msb. */
6017 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
6019 machine_mode mode
= GET_MODE (op
);
6020 machine_mode inner
= GET_MODE_INNER (mode
);
6028 HOST_WIDE_INT splat_val
;
6029 HOST_WIDE_INT msb_val
;
6031 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
6034 nunits
= GET_MODE_NUNITS (mode
);
6035 bitsize
= GET_MODE_BITSIZE (inner
);
6036 mask
= GET_MODE_MASK (inner
);
6038 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6040 msb_val
= val
>= 0 ? 0 : -1;
6042 /* Construct the value to be splatted, if possible. If not, return 0. */
6043 for (i
= 2; i
<= copies
; i
*= 2)
6045 HOST_WIDE_INT small_val
;
6047 small_val
= splat_val
>> bitsize
;
6049 if (splat_val
!= ((HOST_WIDE_INT
)
6050 ((unsigned HOST_WIDE_INT
) small_val
<< bitsize
)
6051 | (small_val
& mask
)))
6053 splat_val
= small_val
;
6056 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6057 if (EASY_VECTOR_15 (splat_val
))
6060 /* Also check if we can splat, and then add the result to itself. Do so if
6061 the value is positive, of if the splat instruction is using OP's mode;
6062 for splat_val < 0, the splat and the add should use the same mode. */
6063 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
6064 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
6067 /* Also check if are loading up the most significant bit which can be done by
6068 loading up -1 and shifting the value left by -1. */
6069 else if (EASY_VECTOR_MSB (splat_val
, inner
))
6075 /* Check if VAL is present in every STEP-th element, and the
6076 other elements are filled with its most significant bit. */
6077 for (i
= 1; i
< nunits
; ++i
)
6079 HOST_WIDE_INT desired_val
;
6080 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
6081 if ((i
& (step
- 1)) == 0)
6084 desired_val
= msb_val
;
6086 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
6093 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6094 instruction, filling in the bottom elements with 0 or -1.
6096 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6097 for the number of zeroes to shift in, or negative for the number of 0xff
6100 OP is a CONST_VECTOR. */
6103 vspltis_shifted (rtx op
)
6105 machine_mode mode
= GET_MODE (op
);
6106 machine_mode inner
= GET_MODE_INNER (mode
);
6114 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
)
6117 /* We need to create pseudo registers to do the shift, so don't recognize
6118 shift vector constants after reload. */
6119 if (!can_create_pseudo_p ())
6122 nunits
= GET_MODE_NUNITS (mode
);
6123 mask
= GET_MODE_MASK (inner
);
6125 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? 0 : nunits
- 1);
6127 /* Check if the value can really be the operand of a vspltis[bhw]. */
6128 if (EASY_VECTOR_15 (val
))
6131 /* Also check if we are loading up the most significant bit which can be done
6132 by loading up -1 and shifting the value left by -1. */
6133 else if (EASY_VECTOR_MSB (val
, inner
))
6139 /* Check if VAL is present in every STEP-th element until we find elements
6140 that are 0 or all 1 bits. */
6141 for (i
= 1; i
< nunits
; ++i
)
6143 unsigned elt
= BYTES_BIG_ENDIAN
? i
: nunits
- 1 - i
;
6144 HOST_WIDE_INT elt_val
= const_vector_elt_as_int (op
, elt
);
6146 /* If the value isn't the splat value, check for the remaining elements
6152 for (j
= i
+1; j
< nunits
; ++j
)
6154 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6155 if (const_vector_elt_as_int (op
, elt2
) != 0)
6159 return (nunits
- i
) * GET_MODE_SIZE (inner
);
6162 else if ((elt_val
& mask
) == mask
)
6164 for (j
= i
+1; j
< nunits
; ++j
)
6166 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6167 if ((const_vector_elt_as_int (op
, elt2
) & mask
) != mask
)
6171 return -((nunits
- i
) * GET_MODE_SIZE (inner
));
6179 /* If all elements are equal, we don't need to do VLSDOI. */
6184 /* Return true if OP is of the given MODE and can be synthesized
6185 with a vspltisb, vspltish or vspltisw. */
6188 easy_altivec_constant (rtx op
, machine_mode mode
)
6190 unsigned step
, copies
;
6192 if (mode
== VOIDmode
)
6193 mode
= GET_MODE (op
);
6194 else if (mode
!= GET_MODE (op
))
6197 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6199 if (mode
== V2DFmode
)
6200 return zero_constant (op
, mode
);
6202 else if (mode
== V2DImode
)
6204 if (!CONST_INT_P (CONST_VECTOR_ELT (op
, 0))
6205 || !CONST_INT_P (CONST_VECTOR_ELT (op
, 1)))
6208 if (zero_constant (op
, mode
))
6211 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
6212 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
6218 /* V1TImode is a special container for TImode. Ignore for now. */
6219 else if (mode
== V1TImode
)
6222 /* Start with a vspltisw. */
6223 step
= GET_MODE_NUNITS (mode
) / 4;
6226 if (vspltis_constant (op
, step
, copies
))
6229 /* Then try with a vspltish. */
6235 if (vspltis_constant (op
, step
, copies
))
6238 /* And finally a vspltisb. */
6244 if (vspltis_constant (op
, step
, copies
))
6247 if (vspltis_shifted (op
) != 0)
6253 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6254 result is OP. Abort if it is not possible. */
6257 gen_easy_altivec_constant (rtx op
)
6259 machine_mode mode
= GET_MODE (op
);
6260 int nunits
= GET_MODE_NUNITS (mode
);
6261 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6262 unsigned step
= nunits
/ 4;
6263 unsigned copies
= 1;
6265 /* Start with a vspltisw. */
6266 if (vspltis_constant (op
, step
, copies
))
6267 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
6269 /* Then try with a vspltish. */
6275 if (vspltis_constant (op
, step
, copies
))
6276 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
6278 /* And finally a vspltisb. */
6284 if (vspltis_constant (op
, step
, copies
))
6285 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
6290 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6291 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6293 Return the number of instructions needed (1 or 2) into the address pointed
6296 Return the constant that is being split via CONSTANT_PTR. */
6299 xxspltib_constant_p (rtx op
,
6304 size_t nunits
= GET_MODE_NUNITS (mode
);
6306 HOST_WIDE_INT value
;
6309 /* Set the returned values to out of bound values. */
6310 *num_insns_ptr
= -1;
6311 *constant_ptr
= 256;
6313 if (!TARGET_P9_VECTOR
)
6316 if (mode
== VOIDmode
)
6317 mode
= GET_MODE (op
);
6319 else if (mode
!= GET_MODE (op
) && GET_MODE (op
) != VOIDmode
)
6322 /* Handle (vec_duplicate <constant>). */
6323 if (GET_CODE (op
) == VEC_DUPLICATE
)
6325 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6326 && mode
!= V2DImode
)
6329 element
= XEXP (op
, 0);
6330 if (!CONST_INT_P (element
))
6333 value
= INTVAL (element
);
6334 if (!IN_RANGE (value
, -128, 127))
6338 /* Handle (const_vector [...]). */
6339 else if (GET_CODE (op
) == CONST_VECTOR
)
6341 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6342 && mode
!= V2DImode
)
6345 element
= CONST_VECTOR_ELT (op
, 0);
6346 if (!CONST_INT_P (element
))
6349 value
= INTVAL (element
);
6350 if (!IN_RANGE (value
, -128, 127))
6353 for (i
= 1; i
< nunits
; i
++)
6355 element
= CONST_VECTOR_ELT (op
, i
);
6356 if (!CONST_INT_P (element
))
6359 if (value
!= INTVAL (element
))
6364 /* Handle integer constants being loaded into the upper part of the VSX
6365 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6366 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6367 else if (CONST_INT_P (op
))
6369 if (!SCALAR_INT_MODE_P (mode
))
6372 value
= INTVAL (op
);
6373 if (!IN_RANGE (value
, -128, 127))
6376 if (!IN_RANGE (value
, -1, 0))
6378 if (!(reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
))
6381 if (EASY_VECTOR_15 (value
))
6389 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6390 sign extend. Special case 0/-1 to allow getting any VSX register instead
6391 of an Altivec register. */
6392 if ((mode
== V4SImode
|| mode
== V8HImode
) && !IN_RANGE (value
, -1, 0)
6393 && EASY_VECTOR_15 (value
))
6396 /* Return # of instructions and the constant byte for XXSPLTIB. */
6397 if (mode
== V16QImode
)
6400 else if (IN_RANGE (value
, -1, 0))
6406 *constant_ptr
= (int) value
;
6411 output_vec_const_move (rtx
*operands
)
6419 mode
= GET_MODE (dest
);
6423 bool dest_vmx_p
= ALTIVEC_REGNO_P (REGNO (dest
));
6424 int xxspltib_value
= 256;
6427 if (zero_constant (vec
, mode
))
6429 if (TARGET_P9_VECTOR
)
6430 return "xxspltib %x0,0";
6432 else if (dest_vmx_p
)
6433 return "vspltisw %0,0";
6436 return "xxlxor %x0,%x0,%x0";
6439 if (all_ones_constant (vec
, mode
))
6441 if (TARGET_P9_VECTOR
)
6442 return "xxspltib %x0,255";
6444 else if (dest_vmx_p
)
6445 return "vspltisw %0,-1";
6447 else if (TARGET_P8_VECTOR
)
6448 return "xxlorc %x0,%x0,%x0";
6454 if (TARGET_P9_VECTOR
6455 && xxspltib_constant_p (vec
, mode
, &num_insns
, &xxspltib_value
))
6459 operands
[2] = GEN_INT (xxspltib_value
& 0xff);
6460 return "xxspltib %x0,%2";
6471 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest
)));
6472 if (zero_constant (vec
, mode
))
6473 return "vspltisw %0,0";
6475 if (all_ones_constant (vec
, mode
))
6476 return "vspltisw %0,-1";
6478 /* Do we need to construct a value using VSLDOI? */
6479 shift
= vspltis_shifted (vec
);
6483 splat_vec
= gen_easy_altivec_constant (vec
);
6484 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
6485 operands
[1] = XEXP (splat_vec
, 0);
6486 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
6489 switch (GET_MODE (splat_vec
))
6492 return "vspltisw %0,%1";
6495 return "vspltish %0,%1";
6498 return "vspltisb %0,%1";
6508 /* Initialize vector TARGET to VALS. */
6511 rs6000_expand_vector_init (rtx target
, rtx vals
)
6513 machine_mode mode
= GET_MODE (target
);
6514 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6515 int n_elts
= GET_MODE_NUNITS (mode
);
6516 int n_var
= 0, one_var
= -1;
6517 bool all_same
= true, all_const_zero
= true;
6521 for (i
= 0; i
< n_elts
; ++i
)
6523 x
= XVECEXP (vals
, 0, i
);
6524 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6525 ++n_var
, one_var
= i
;
6526 else if (x
!= CONST0_RTX (inner_mode
))
6527 all_const_zero
= false;
6529 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6535 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
6536 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
6537 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
6539 /* Zero register. */
6540 emit_move_insn (target
, CONST0_RTX (mode
));
6543 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
6545 /* Splat immediate. */
6546 emit_insn (gen_rtx_SET (target
, const_vec
));
6551 /* Load from constant pool. */
6552 emit_move_insn (target
, const_vec
);
6557 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6558 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
6562 size_t num_elements
= all_same
? 1 : 2;
6563 for (i
= 0; i
< num_elements
; i
++)
6565 op
[i
] = XVECEXP (vals
, 0, i
);
6566 /* Just in case there is a SUBREG with a smaller mode, do a
6568 if (GET_MODE (op
[i
]) != inner_mode
)
6570 rtx tmp
= gen_reg_rtx (inner_mode
);
6571 convert_move (tmp
, op
[i
], 0);
6574 /* Allow load with splat double word. */
6575 else if (MEM_P (op
[i
]))
6578 op
[i
] = force_reg (inner_mode
, op
[i
]);
6580 else if (!REG_P (op
[i
]))
6581 op
[i
] = force_reg (inner_mode
, op
[i
]);
6586 if (mode
== V2DFmode
)
6587 emit_insn (gen_vsx_splat_v2df (target
, op
[0]));
6589 emit_insn (gen_vsx_splat_v2di (target
, op
[0]));
6593 if (mode
== V2DFmode
)
6594 emit_insn (gen_vsx_concat_v2df (target
, op
[0], op
[1]));
6596 emit_insn (gen_vsx_concat_v2di (target
, op
[0], op
[1]));
6601 /* Special case initializing vector int if we are on 64-bit systems with
6602 direct move or we have the ISA 3.0 instructions. */
6603 if (mode
== V4SImode
&& VECTOR_MEM_VSX_P (V4SImode
)
6604 && TARGET_DIRECT_MOVE_64BIT
)
6608 rtx element0
= XVECEXP (vals
, 0, 0);
6609 if (MEM_P (element0
))
6610 element0
= rs6000_force_indexed_or_indirect_mem (element0
);
6612 element0
= force_reg (SImode
, element0
);
6614 if (TARGET_P9_VECTOR
)
6615 emit_insn (gen_vsx_splat_v4si (target
, element0
));
6618 rtx tmp
= gen_reg_rtx (DImode
);
6619 emit_insn (gen_zero_extendsidi2 (tmp
, element0
));
6620 emit_insn (gen_vsx_splat_v4si_di (target
, tmp
));
6629 for (i
= 0; i
< 4; i
++)
6630 elements
[i
] = force_reg (SImode
, XVECEXP (vals
, 0, i
));
6632 emit_insn (gen_vsx_init_v4si (target
, elements
[0], elements
[1],
6633 elements
[2], elements
[3]));
6638 /* With single precision floating point on VSX, know that internally single
6639 precision is actually represented as a double, and either make 2 V2DF
6640 vectors, and convert these vectors to single precision, or do one
6641 conversion, and splat the result to the other elements. */
6642 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (V4SFmode
))
6646 rtx element0
= XVECEXP (vals
, 0, 0);
6648 if (TARGET_P9_VECTOR
)
6650 if (MEM_P (element0
))
6651 element0
= rs6000_force_indexed_or_indirect_mem (element0
);
6653 emit_insn (gen_vsx_splat_v4sf (target
, element0
));
6658 rtx freg
= gen_reg_rtx (V4SFmode
);
6659 rtx sreg
= force_reg (SFmode
, element0
);
6660 rtx cvt
= (TARGET_XSCVDPSPN
6661 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
6662 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
6665 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
,
6671 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
6672 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
6673 rtx flt_even
= gen_reg_rtx (V4SFmode
);
6674 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
6675 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
6676 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
6677 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
6678 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
6680 /* Use VMRGEW if we can instead of doing a permute. */
6681 if (TARGET_P8_VECTOR
)
6683 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op2
));
6684 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op1
, op3
));
6685 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6686 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6687 if (BYTES_BIG_ENDIAN
)
6688 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_even
, flt_odd
));
6690 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_odd
, flt_even
));
6694 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
6695 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
6696 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6697 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6698 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
6704 /* Special case initializing vector short/char that are splats if we are on
6705 64-bit systems with direct move. */
6706 if (all_same
&& TARGET_DIRECT_MOVE_64BIT
6707 && (mode
== V16QImode
|| mode
== V8HImode
))
6709 rtx op0
= XVECEXP (vals
, 0, 0);
6710 rtx di_tmp
= gen_reg_rtx (DImode
);
6713 op0
= force_reg (GET_MODE_INNER (mode
), op0
);
6715 if (mode
== V16QImode
)
6717 emit_insn (gen_zero_extendqidi2 (di_tmp
, op0
));
6718 emit_insn (gen_vsx_vspltb_di (target
, di_tmp
));
6722 if (mode
== V8HImode
)
6724 emit_insn (gen_zero_extendhidi2 (di_tmp
, op0
));
6725 emit_insn (gen_vsx_vsplth_di (target
, di_tmp
));
6730 /* Store value to stack temp. Load vector element. Splat. However, splat
6731 of 64-bit items is not supported on Altivec. */
6732 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
6734 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6735 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
6736 XVECEXP (vals
, 0, 0));
6737 x
= gen_rtx_UNSPEC (VOIDmode
,
6738 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6739 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6741 gen_rtx_SET (target
, mem
),
6743 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
6744 gen_rtx_PARALLEL (VOIDmode
,
6745 gen_rtvec (1, const0_rtx
)));
6746 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
6750 /* One field is non-constant. Load constant then overwrite
6754 rtx copy
= copy_rtx (vals
);
6756 /* Load constant part of vector, substitute neighboring value for
6758 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
6759 rs6000_expand_vector_init (target
, copy
);
6761 /* Insert variable. */
6762 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
6766 /* Construct the vector in memory one field at a time
6767 and load the whole vector. */
6768 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6769 for (i
= 0; i
< n_elts
; i
++)
6770 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
6771 i
* GET_MODE_SIZE (inner_mode
)),
6772 XVECEXP (vals
, 0, i
));
6773 emit_move_insn (target
, mem
);
6776 /* Set field ELT of TARGET to VAL. */
6779 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
6781 machine_mode mode
= GET_MODE (target
);
6782 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6783 rtx reg
= gen_reg_rtx (mode
);
6785 int width
= GET_MODE_SIZE (inner_mode
);
6788 val
= force_reg (GET_MODE (val
), val
);
6790 if (VECTOR_MEM_VSX_P (mode
))
6792 rtx insn
= NULL_RTX
;
6793 rtx elt_rtx
= GEN_INT (elt
);
6795 if (mode
== V2DFmode
)
6796 insn
= gen_vsx_set_v2df (target
, target
, val
, elt_rtx
);
6798 else if (mode
== V2DImode
)
6799 insn
= gen_vsx_set_v2di (target
, target
, val
, elt_rtx
);
6801 else if (TARGET_P9_VECTOR
&& TARGET_POWERPC64
)
6803 if (mode
== V4SImode
)
6804 insn
= gen_vsx_set_v4si_p9 (target
, target
, val
, elt_rtx
);
6805 else if (mode
== V8HImode
)
6806 insn
= gen_vsx_set_v8hi_p9 (target
, target
, val
, elt_rtx
);
6807 else if (mode
== V16QImode
)
6808 insn
= gen_vsx_set_v16qi_p9 (target
, target
, val
, elt_rtx
);
6809 else if (mode
== V4SFmode
)
6810 insn
= gen_vsx_set_v4sf_p9 (target
, target
, val
, elt_rtx
);
6820 /* Simplify setting single element vectors like V1TImode. */
6821 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
6823 emit_move_insn (target
, gen_lowpart (mode
, val
));
6827 /* Load single variable value. */
6828 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6829 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
6830 x
= gen_rtx_UNSPEC (VOIDmode
,
6831 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6832 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6834 gen_rtx_SET (reg
, mem
),
6837 /* Linear sequence. */
6838 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
6839 for (i
= 0; i
< 16; ++i
)
6840 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
6842 /* Set permute mask to insert element into target. */
6843 for (i
= 0; i
< width
; ++i
)
6844 XVECEXP (mask
, 0, elt
*width
+ i
)
6845 = GEN_INT (i
+ 0x10);
6846 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
6848 if (BYTES_BIG_ENDIAN
)
6849 x
= gen_rtx_UNSPEC (mode
,
6850 gen_rtvec (3, target
, reg
,
6851 force_reg (V16QImode
, x
)),
6855 if (TARGET_P9_VECTOR
)
6856 x
= gen_rtx_UNSPEC (mode
,
6857 gen_rtvec (3, reg
, target
,
6858 force_reg (V16QImode
, x
)),
6862 /* Invert selector. We prefer to generate VNAND on P8 so
6863 that future fusion opportunities can kick in, but must
6864 generate VNOR elsewhere. */
6865 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
6866 rtx iorx
= (TARGET_P8_VECTOR
6867 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
6868 : gen_rtx_AND (V16QImode
, notx
, notx
));
6869 rtx tmp
= gen_reg_rtx (V16QImode
);
6870 emit_insn (gen_rtx_SET (tmp
, iorx
));
6872 /* Permute with operands reversed and adjusted selector. */
6873 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
6878 emit_insn (gen_rtx_SET (target
, x
));
6881 /* Extract field ELT from VEC into TARGET. */
6884 rs6000_expand_vector_extract (rtx target
, rtx vec
, rtx elt
)
6886 machine_mode mode
= GET_MODE (vec
);
6887 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6890 if (VECTOR_MEM_VSX_P (mode
) && CONST_INT_P (elt
))
6897 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
6900 emit_insn (gen_vsx_extract_v2df (target
, vec
, elt
));
6903 emit_insn (gen_vsx_extract_v2di (target
, vec
, elt
));
6906 emit_insn (gen_vsx_extract_v4sf (target
, vec
, elt
));
6909 if (TARGET_DIRECT_MOVE_64BIT
)
6911 emit_insn (gen_vsx_extract_v16qi (target
, vec
, elt
));
6917 if (TARGET_DIRECT_MOVE_64BIT
)
6919 emit_insn (gen_vsx_extract_v8hi (target
, vec
, elt
));
6925 if (TARGET_DIRECT_MOVE_64BIT
)
6927 emit_insn (gen_vsx_extract_v4si (target
, vec
, elt
));
6933 else if (VECTOR_MEM_VSX_P (mode
) && !CONST_INT_P (elt
)
6934 && TARGET_DIRECT_MOVE_64BIT
)
6936 if (GET_MODE (elt
) != DImode
)
6938 rtx tmp
= gen_reg_rtx (DImode
);
6939 convert_move (tmp
, elt
, 0);
6942 else if (!REG_P (elt
))
6943 elt
= force_reg (DImode
, elt
);
6948 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
6952 emit_insn (gen_vsx_extract_v2df_var (target
, vec
, elt
));
6956 emit_insn (gen_vsx_extract_v2di_var (target
, vec
, elt
));
6960 emit_insn (gen_vsx_extract_v4sf_var (target
, vec
, elt
));
6964 emit_insn (gen_vsx_extract_v4si_var (target
, vec
, elt
));
6968 emit_insn (gen_vsx_extract_v8hi_var (target
, vec
, elt
));
6972 emit_insn (gen_vsx_extract_v16qi_var (target
, vec
, elt
));
6980 /* Allocate mode-sized buffer. */
6981 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6983 emit_move_insn (mem
, vec
);
6984 if (CONST_INT_P (elt
))
6986 int modulo_elt
= INTVAL (elt
) % GET_MODE_NUNITS (mode
);
6988 /* Add offset to field within buffer matching vector element. */
6989 mem
= adjust_address_nv (mem
, inner_mode
,
6990 modulo_elt
* GET_MODE_SIZE (inner_mode
));
6991 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
6995 unsigned int ele_size
= GET_MODE_SIZE (inner_mode
);
6996 rtx num_ele_m1
= GEN_INT (GET_MODE_NUNITS (mode
) - 1);
6997 rtx new_addr
= gen_reg_rtx (Pmode
);
6999 elt
= gen_rtx_AND (Pmode
, elt
, num_ele_m1
);
7001 elt
= gen_rtx_MULT (Pmode
, elt
, GEN_INT (ele_size
));
7002 new_addr
= gen_rtx_PLUS (Pmode
, XEXP (mem
, 0), elt
);
7003 new_addr
= change_address (mem
, inner_mode
, new_addr
);
7004 emit_move_insn (target
, new_addr
);
7008 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7009 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7010 temporary (BASE_TMP) to fixup the address. Return the new memory address
7011 that is valid for reads or writes to a given register (SCALAR_REG). */
7014 rs6000_adjust_vec_address (rtx scalar_reg
,
7018 machine_mode scalar_mode
)
7020 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7021 rtx addr
= XEXP (mem
, 0);
7026 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7027 gcc_assert (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
);
7029 /* Calculate what we need to add to the address to get the element
7031 if (CONST_INT_P (element
))
7032 element_offset
= GEN_INT (INTVAL (element
) * scalar_size
);
7035 int byte_shift
= exact_log2 (scalar_size
);
7036 gcc_assert (byte_shift
>= 0);
7038 if (byte_shift
== 0)
7039 element_offset
= element
;
7043 if (TARGET_POWERPC64
)
7044 emit_insn (gen_ashldi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
7046 emit_insn (gen_ashlsi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
7048 element_offset
= base_tmp
;
7052 /* Create the new address pointing to the element within the vector. If we
7053 are adding 0, we don't have to change the address. */
7054 if (element_offset
== const0_rtx
)
7057 /* A simple indirect address can be converted into a reg + offset
7059 else if (REG_P (addr
) || SUBREG_P (addr
))
7060 new_addr
= gen_rtx_PLUS (Pmode
, addr
, element_offset
);
7062 /* Optimize D-FORM addresses with constant offset with a constant element, to
7063 include the element offset in the address directly. */
7064 else if (GET_CODE (addr
) == PLUS
)
7066 rtx op0
= XEXP (addr
, 0);
7067 rtx op1
= XEXP (addr
, 1);
7070 gcc_assert (REG_P (op0
) || SUBREG_P (op0
));
7071 if (CONST_INT_P (op1
) && CONST_INT_P (element_offset
))
7073 HOST_WIDE_INT offset
= INTVAL (op1
) + INTVAL (element_offset
);
7074 rtx offset_rtx
= GEN_INT (offset
);
7076 if (IN_RANGE (offset
, -32768, 32767)
7077 && (scalar_size
< 8 || (offset
& 0x3) == 0))
7078 new_addr
= gen_rtx_PLUS (Pmode
, op0
, offset_rtx
);
7081 emit_move_insn (base_tmp
, offset_rtx
);
7082 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7087 bool op1_reg_p
= (REG_P (op1
) || SUBREG_P (op1
));
7088 bool ele_reg_p
= (REG_P (element_offset
) || SUBREG_P (element_offset
));
7090 /* Note, ADDI requires the register being added to be a base
7091 register. If the register was R0, load it up into the temporary
7094 && (ele_reg_p
|| reg_or_subregno (op1
) != FIRST_GPR_REGNO
))
7096 insn
= gen_add3_insn (base_tmp
, op1
, element_offset
);
7097 gcc_assert (insn
!= NULL_RTX
);
7102 && reg_or_subregno (element_offset
) != FIRST_GPR_REGNO
)
7104 insn
= gen_add3_insn (base_tmp
, element_offset
, op1
);
7105 gcc_assert (insn
!= NULL_RTX
);
7111 emit_move_insn (base_tmp
, op1
);
7112 emit_insn (gen_add2_insn (base_tmp
, element_offset
));
7115 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7121 emit_move_insn (base_tmp
, addr
);
7122 new_addr
= gen_rtx_PLUS (Pmode
, base_tmp
, element_offset
);
7125 /* If we have a PLUS, we need to see whether the particular register class
7126 allows for D-FORM or X-FORM addressing. */
7127 if (GET_CODE (new_addr
) == PLUS
)
7129 rtx op1
= XEXP (new_addr
, 1);
7130 addr_mask_type addr_mask
;
7131 unsigned int scalar_regno
= reg_or_subregno (scalar_reg
);
7133 gcc_assert (HARD_REGISTER_NUM_P (scalar_regno
));
7134 if (INT_REGNO_P (scalar_regno
))
7135 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_GPR
];
7137 else if (FP_REGNO_P (scalar_regno
))
7138 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_FPR
];
7140 else if (ALTIVEC_REGNO_P (scalar_regno
))
7141 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_VMX
];
7146 if (REG_P (op1
) || SUBREG_P (op1
))
7147 valid_addr_p
= (addr_mask
& RELOAD_REG_INDEXED
) != 0;
7149 valid_addr_p
= (addr_mask
& RELOAD_REG_OFFSET
) != 0;
7152 else if (REG_P (new_addr
) || SUBREG_P (new_addr
))
7153 valid_addr_p
= true;
7156 valid_addr_p
= false;
7160 emit_move_insn (base_tmp
, new_addr
);
7161 new_addr
= base_tmp
;
7164 return change_address (mem
, scalar_mode
, new_addr
);
7167 /* Split a variable vec_extract operation into the component instructions. */
7170 rs6000_split_vec_extract_var (rtx dest
, rtx src
, rtx element
, rtx tmp_gpr
,
7173 machine_mode mode
= GET_MODE (src
);
7174 machine_mode scalar_mode
= GET_MODE_INNER (GET_MODE (src
));
7175 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7176 int byte_shift
= exact_log2 (scalar_size
);
7178 gcc_assert (byte_shift
>= 0);
7180 /* If we are given a memory address, optimize to load just the element. We
7181 don't have to adjust the vector element number on little endian
7185 int num_elements
= GET_MODE_NUNITS (mode
);
7186 rtx num_ele_m1
= GEN_INT (num_elements
- 1);
7188 emit_insn (gen_anddi3 (element
, element
, num_ele_m1
));
7189 gcc_assert (REG_P (tmp_gpr
));
7190 emit_move_insn (dest
, rs6000_adjust_vec_address (dest
, src
, element
,
7191 tmp_gpr
, scalar_mode
));
7195 else if (REG_P (src
) || SUBREG_P (src
))
7197 int num_elements
= GET_MODE_NUNITS (mode
);
7198 int bits_in_element
= mode_to_bits (GET_MODE_INNER (mode
));
7199 int bit_shift
= 7 - exact_log2 (num_elements
);
7201 unsigned int dest_regno
= reg_or_subregno (dest
);
7202 unsigned int src_regno
= reg_or_subregno (src
);
7203 unsigned int element_regno
= reg_or_subregno (element
);
7205 gcc_assert (REG_P (tmp_gpr
));
7207 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7208 a general purpose register. */
7209 if (TARGET_P9_VECTOR
7210 && (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
7211 && INT_REGNO_P (dest_regno
)
7212 && ALTIVEC_REGNO_P (src_regno
)
7213 && INT_REGNO_P (element_regno
))
7215 rtx dest_si
= gen_rtx_REG (SImode
, dest_regno
);
7216 rtx element_si
= gen_rtx_REG (SImode
, element_regno
);
7218 if (mode
== V16QImode
)
7219 emit_insn (BYTES_BIG_ENDIAN
7220 ? gen_vextublx (dest_si
, element_si
, src
)
7221 : gen_vextubrx (dest_si
, element_si
, src
));
7223 else if (mode
== V8HImode
)
7225 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7226 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const1_rtx
));
7227 emit_insn (BYTES_BIG_ENDIAN
7228 ? gen_vextuhlx (dest_si
, tmp_gpr_si
, src
)
7229 : gen_vextuhrx (dest_si
, tmp_gpr_si
, src
));
7235 rtx tmp_gpr_si
= gen_rtx_REG (SImode
, REGNO (tmp_gpr
));
7236 emit_insn (gen_ashlsi3 (tmp_gpr_si
, element_si
, const2_rtx
));
7237 emit_insn (BYTES_BIG_ENDIAN
7238 ? gen_vextuwlx (dest_si
, tmp_gpr_si
, src
)
7239 : gen_vextuwrx (dest_si
, tmp_gpr_si
, src
));
7246 gcc_assert (REG_P (tmp_altivec
));
7248 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7249 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7250 will shift the element into the upper position (adding 3 to convert a
7251 byte shift into a bit shift). */
7252 if (scalar_size
== 8)
7254 if (!BYTES_BIG_ENDIAN
)
7256 emit_insn (gen_xordi3 (tmp_gpr
, element
, const1_rtx
));
7262 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7264 emit_insn (gen_rtx_SET (tmp_gpr
,
7265 gen_rtx_AND (DImode
,
7266 gen_rtx_ASHIFT (DImode
,
7273 if (!BYTES_BIG_ENDIAN
)
7275 rtx num_ele_m1
= GEN_INT (num_elements
- 1);
7277 emit_insn (gen_anddi3 (tmp_gpr
, element
, num_ele_m1
));
7278 emit_insn (gen_subdi3 (tmp_gpr
, num_ele_m1
, tmp_gpr
));
7284 emit_insn (gen_ashldi3 (tmp_gpr
, element2
, GEN_INT (bit_shift
)));
7287 /* Get the value into the lower byte of the Altivec register where VSLO
7289 if (TARGET_P9_VECTOR
)
7290 emit_insn (gen_vsx_splat_v2di (tmp_altivec
, tmp_gpr
));
7291 else if (can_create_pseudo_p ())
7292 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_gpr
, tmp_gpr
));
7295 rtx tmp_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7296 emit_move_insn (tmp_di
, tmp_gpr
);
7297 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_di
, tmp_di
));
7300 /* Do the VSLO to get the value into the final location. */
7304 emit_insn (gen_vsx_vslo_v2df (dest
, src
, tmp_altivec
));
7308 emit_insn (gen_vsx_vslo_v2di (dest
, src
, tmp_altivec
));
7313 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7314 rtx tmp_altivec_v4sf
= gen_rtx_REG (V4SFmode
, REGNO (tmp_altivec
));
7315 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7316 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7319 emit_insn (gen_vsx_xscvspdp_scalar2 (dest
, tmp_altivec_v4sf
));
7327 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7328 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7329 rtx tmp_gpr_di
= gen_rtx_REG (DImode
, REGNO (dest
));
7330 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7332 emit_move_insn (tmp_gpr_di
, tmp_altivec_di
);
7333 emit_insn (gen_lshrdi3 (tmp_gpr_di
, tmp_gpr_di
,
7334 GEN_INT (64 - bits_in_element
)));
7348 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7349 selects whether the alignment is abi mandated, optional, or
7350 both abi and optional alignment. */
7353 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
7355 if (how
!= align_opt
)
7357 if (TREE_CODE (type
) == VECTOR_TYPE
&& align
< 128)
7361 if (how
!= align_abi
)
7363 if (TREE_CODE (type
) == ARRAY_TYPE
7364 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
7366 if (align
< BITS_PER_WORD
)
7367 align
= BITS_PER_WORD
;
7374 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7375 instructions simply ignore the low bits; VSX memory instructions
7376 are aligned to 4 or 8 bytes. */
7379 rs6000_slow_unaligned_access (machine_mode mode
, unsigned int align
)
7381 return (STRICT_ALIGNMENT
7382 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7383 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && align
< 32)
7384 || ((VECTOR_MODE_P (mode
) || FLOAT128_VECTOR_P (mode
))
7385 && (int) align
< VECTOR_ALIGN (mode
)))));
7388 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7391 rs6000_special_adjust_field_align_p (tree type
, unsigned int computed
)
7393 if (TARGET_ALTIVEC
&& TREE_CODE (type
) == VECTOR_TYPE
)
7395 if (computed
!= 128)
7398 if (!warned
&& warn_psabi
)
7401 inform (input_location
,
7402 "the layout of aggregates containing vectors with"
7403 " %d-byte alignment has changed in GCC 5",
7404 computed
/ BITS_PER_UNIT
);
7407 /* In current GCC there is no special case. */
7414 /* AIX increases natural record alignment to doubleword if the first
7415 field is an FP double while the FP fields remain word aligned. */
7418 rs6000_special_round_type_align (tree type
, unsigned int computed
,
7419 unsigned int specified
)
7421 unsigned int align
= MAX (computed
, specified
);
7422 tree field
= TYPE_FIELDS (type
);
7424 /* Skip all non field decls */
7425 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7426 field
= DECL_CHAIN (field
);
7428 if (field
!= NULL
&& field
!= type
)
7430 type
= TREE_TYPE (field
);
7431 while (TREE_CODE (type
) == ARRAY_TYPE
)
7432 type
= TREE_TYPE (type
);
7434 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
7435 align
= MAX (align
, 64);
7441 /* Darwin increases record alignment to the natural alignment of
7445 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
7446 unsigned int specified
)
7448 unsigned int align
= MAX (computed
, specified
);
7450 if (TYPE_PACKED (type
))
7453 /* Find the first field, looking down into aggregates. */
7455 tree field
= TYPE_FIELDS (type
);
7456 /* Skip all non field decls */
7457 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7458 field
= DECL_CHAIN (field
);
7461 /* A packed field does not contribute any extra alignment. */
7462 if (DECL_PACKED (field
))
7464 type
= TREE_TYPE (field
);
7465 while (TREE_CODE (type
) == ARRAY_TYPE
)
7466 type
= TREE_TYPE (type
);
7467 } while (AGGREGATE_TYPE_P (type
));
7469 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
7470 align
= MAX (align
, TYPE_ALIGN (type
));
7475 /* Return 1 for an operand in small memory on V.4/eabi. */
7478 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
7479 machine_mode mode ATTRIBUTE_UNUSED
)
7484 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
7487 if (DEFAULT_ABI
!= ABI_V4
)
7490 if (SYMBOL_REF_P (op
))
7493 else if (GET_CODE (op
) != CONST
7494 || GET_CODE (XEXP (op
, 0)) != PLUS
7495 || !SYMBOL_REF_P (XEXP (XEXP (op
, 0), 0))
7496 || !CONST_INT_P (XEXP (XEXP (op
, 0), 1)))
7501 rtx sum
= XEXP (op
, 0);
7502 HOST_WIDE_INT summand
;
7504 /* We have to be careful here, because it is the referenced address
7505 that must be 32k from _SDA_BASE_, not just the symbol. */
7506 summand
= INTVAL (XEXP (sum
, 1));
7507 if (summand
< 0 || summand
> g_switch_value
)
7510 sym_ref
= XEXP (sum
, 0);
7513 return SYMBOL_REF_SMALL_P (sym_ref
);
7519 /* Return true if either operand is a general purpose register. */
7522 gpr_or_gpr_p (rtx op0
, rtx op1
)
7524 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
7525 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
7528 /* Return true if this is a move direct operation between GPR registers and
7529 floating point/VSX registers. */
7532 direct_move_p (rtx op0
, rtx op1
)
7536 if (!REG_P (op0
) || !REG_P (op1
))
7539 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
7542 regno0
= REGNO (op0
);
7543 regno1
= REGNO (op1
);
7544 if (!HARD_REGISTER_NUM_P (regno0
) || !HARD_REGISTER_NUM_P (regno1
))
7547 if (INT_REGNO_P (regno0
))
7548 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
7550 else if (INT_REGNO_P (regno1
))
7552 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
7555 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
7562 /* Return true if the OFFSET is valid for the quad address instructions that
7563 use d-form (register + offset) addressing. */
7566 quad_address_offset_p (HOST_WIDE_INT offset
)
7568 return (IN_RANGE (offset
, -32768, 32767) && ((offset
) & 0xf) == 0);
7571 /* Return true if the ADDR is an acceptable address for a quad memory
7572 operation of mode MODE (either LQ/STQ for general purpose registers, or
7573 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7574 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7575 3.0 LXV/STXV instruction. */
7578 quad_address_p (rtx addr
, machine_mode mode
, bool strict
)
7582 if (GET_MODE_SIZE (mode
) != 16)
7585 if (legitimate_indirect_address_p (addr
, strict
))
7588 if (VECTOR_MODE_P (mode
) && !mode_supports_dq_form (mode
))
7591 if (GET_CODE (addr
) != PLUS
)
7594 op0
= XEXP (addr
, 0);
7595 if (!REG_P (op0
) || !INT_REG_OK_FOR_BASE_P (op0
, strict
))
7598 op1
= XEXP (addr
, 1);
7599 if (!CONST_INT_P (op1
))
7602 return quad_address_offset_p (INTVAL (op1
));
7605 /* Return true if this is a load or store quad operation. This function does
7606 not handle the atomic quad memory instructions. */
7609 quad_load_store_p (rtx op0
, rtx op1
)
7613 if (!TARGET_QUAD_MEMORY
)
7616 else if (REG_P (op0
) && MEM_P (op1
))
7617 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
7618 && quad_memory_operand (op1
, GET_MODE (op1
))
7619 && !reg_overlap_mentioned_p (op0
, op1
));
7621 else if (MEM_P (op0
) && REG_P (op1
))
7622 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
7623 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
7628 if (TARGET_DEBUG_ADDR
)
7630 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
7631 ret
? "true" : "false");
7632 debug_rtx (gen_rtx_SET (op0
, op1
));
7638 /* Given an address, return a constant offset term if one exists. */
7641 address_offset (rtx op
)
7643 if (GET_CODE (op
) == PRE_INC
7644 || GET_CODE (op
) == PRE_DEC
)
7646 else if (GET_CODE (op
) == PRE_MODIFY
7647 || GET_CODE (op
) == LO_SUM
)
7650 if (GET_CODE (op
) == CONST
)
7653 if (GET_CODE (op
) == PLUS
)
7656 if (CONST_INT_P (op
))
7662 /* Return true if the MEM operand is a memory operand suitable for use
7663 with a (full width, possibly multiple) gpr load/store. On
7664 powerpc64 this means the offset must be divisible by 4.
7665 Implements 'Y' constraint.
7667 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7668 a constraint function we know the operand has satisfied a suitable
7669 memory predicate. Also accept some odd rtl generated by reload
7670 (see rs6000_legitimize_reload_address for various forms). It is
7671 important that reload rtl be accepted by appropriate constraints
7672 but not by the operand predicate.
7674 Offsetting a lo_sum should not be allowed, except where we know by
7675 alignment that a 32k boundary is not crossed, but see the ???
7676 comment in rs6000_legitimize_reload_address. Note that by
7677 "offsetting" here we mean a further offset to access parts of the
7678 MEM. It's fine to have a lo_sum where the inner address is offset
7679 from a sym, since the same sym+offset will appear in the high part
7680 of the address calculation. */
7683 mem_operand_gpr (rtx op
, machine_mode mode
)
7685 unsigned HOST_WIDE_INT offset
;
7687 rtx addr
= XEXP (op
, 0);
7689 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7691 && (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
7692 && mode_supports_pre_incdec_p (mode
)
7693 && legitimate_indirect_address_p (XEXP (addr
, 0), false))
7696 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7697 if (!rs6000_offsettable_memref_p (op
, mode
, false))
7700 op
= address_offset (addr
);
7704 offset
= INTVAL (op
);
7705 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
7708 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
7712 if (GET_CODE (addr
) == LO_SUM
)
7713 /* For lo_sum addresses, we must allow any offset except one that
7714 causes a wrap, so test only the low 16 bits. */
7715 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
7717 return offset
+ 0x8000 < 0x10000u
- extra
;
7720 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7721 enforce an offset divisible by 4 even for 32-bit. */
7724 mem_operand_ds_form (rtx op
, machine_mode mode
)
7726 unsigned HOST_WIDE_INT offset
;
7728 rtx addr
= XEXP (op
, 0);
7730 if (!offsettable_address_p (false, mode
, addr
))
7733 op
= address_offset (addr
);
7737 offset
= INTVAL (op
);
7738 if ((offset
& 3) != 0)
7741 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
7745 if (GET_CODE (addr
) == LO_SUM
)
7746 /* For lo_sum addresses, we must allow any offset except one that
7747 causes a wrap, so test only the low 16 bits. */
7748 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
7750 return offset
+ 0x8000 < 0x10000u
- extra
;
7753 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7756 reg_offset_addressing_ok_p (machine_mode mode
)
7770 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7771 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7772 a vector mode, if we want to use the VSX registers to move it around,
7773 we need to restrict ourselves to reg+reg addressing. Similarly for
7774 IEEE 128-bit floating point that is passed in a single vector
7776 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
7777 return mode_supports_dq_form (mode
);
7781 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7782 addressing for the LFIWZX and STFIWX instructions. */
7783 if (TARGET_NO_SDMODE_STACK
)
7795 virtual_stack_registers_memory_p (rtx op
)
7800 regnum
= REGNO (op
);
7802 else if (GET_CODE (op
) == PLUS
7803 && REG_P (XEXP (op
, 0))
7804 && CONST_INT_P (XEXP (op
, 1)))
7805 regnum
= REGNO (XEXP (op
, 0));
7810 return (regnum
>= FIRST_VIRTUAL_REGISTER
7811 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
7814 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7815 is known to not straddle a 32k boundary. This function is used
7816 to determine whether -mcmodel=medium code can use TOC pointer
7817 relative addressing for OP. This means the alignment of the TOC
7818 pointer must also be taken into account, and unfortunately that is
7821 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7822 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7826 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
7830 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
7832 if (!SYMBOL_REF_P (op
))
7835 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7837 if (mode_supports_dq_form (mode
))
7840 dsize
= GET_MODE_SIZE (mode
);
7841 decl
= SYMBOL_REF_DECL (op
);
7847 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7848 replacing memory addresses with an anchor plus offset. We
7849 could find the decl by rummaging around in the block->objects
7850 VEC for the given offset but that seems like too much work. */
7851 dalign
= BITS_PER_UNIT
;
7852 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
7853 && SYMBOL_REF_ANCHOR_P (op
)
7854 && SYMBOL_REF_BLOCK (op
) != NULL
)
7856 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
7858 dalign
= block
->alignment
;
7859 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
7861 else if (CONSTANT_POOL_ADDRESS_P (op
))
7863 /* It would be nice to have get_pool_align().. */
7864 machine_mode cmode
= get_pool_mode (op
);
7866 dalign
= GET_MODE_ALIGNMENT (cmode
);
7869 else if (DECL_P (decl
))
7871 dalign
= DECL_ALIGN (decl
);
7875 /* Allow BLKmode when the entire object is known to not
7876 cross a 32k boundary. */
7877 if (!DECL_SIZE_UNIT (decl
))
7880 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
7883 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
7887 dalign
/= BITS_PER_UNIT
;
7888 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7889 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7890 return dalign
>= dsize
;
7896 /* Find how many bits of the alignment we know for this access. */
7897 dalign
/= BITS_PER_UNIT
;
7898 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7899 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7901 lsb
= offset
& -offset
;
7905 return dalign
>= dsize
;
7909 constant_pool_expr_p (rtx op
)
7913 split_const (op
, &base
, &offset
);
7914 return (SYMBOL_REF_P (base
)
7915 && CONSTANT_POOL_ADDRESS_P (base
)
7916 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
7919 /* These are only used to pass through from print_operand/print_operand_address
7920 to rs6000_output_addr_const_extra over the intervening function
7921 output_addr_const which is not target code. */
7922 static const_rtx tocrel_base_oac
, tocrel_offset_oac
;
7924 /* Return true if OP is a toc pointer relative address (the output
7925 of create_TOC_reference). If STRICT, do not match non-split
7926 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7927 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7928 TOCREL_OFFSET_RET respectively. */
7931 toc_relative_expr_p (const_rtx op
, bool strict
, const_rtx
*tocrel_base_ret
,
7932 const_rtx
*tocrel_offset_ret
)
7937 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7939 /* When strict ensure we have everything tidy. */
7941 && !(GET_CODE (op
) == LO_SUM
7942 && REG_P (XEXP (op
, 0))
7943 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
)))
7946 /* When not strict, allow non-split TOC addresses and also allow
7947 (lo_sum (high ..)) TOC addresses created during reload. */
7948 if (GET_CODE (op
) == LO_SUM
)
7952 const_rtx tocrel_base
= op
;
7953 const_rtx tocrel_offset
= const0_rtx
;
7955 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
7957 tocrel_base
= XEXP (op
, 0);
7958 tocrel_offset
= XEXP (op
, 1);
7961 if (tocrel_base_ret
)
7962 *tocrel_base_ret
= tocrel_base
;
7963 if (tocrel_offset_ret
)
7964 *tocrel_offset_ret
= tocrel_offset
;
7966 return (GET_CODE (tocrel_base
) == UNSPEC
7967 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
7968 && REG_P (XVECEXP (tocrel_base
, 0, 1))
7969 && REGNO (XVECEXP (tocrel_base
, 0, 1)) == TOC_REGISTER
);
7972 /* Return true if X is a constant pool address, and also for cmodel=medium
7973 if X is a toc-relative address known to be offsettable within MODE. */
7976 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
7979 const_rtx tocrel_base
, tocrel_offset
;
7980 return (toc_relative_expr_p (x
, strict
, &tocrel_base
, &tocrel_offset
)
7981 && (TARGET_CMODEL
!= CMODEL_MEDIUM
7982 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
7984 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
7985 INTVAL (tocrel_offset
), mode
)));
7989 legitimate_small_data_p (machine_mode mode
, rtx x
)
7991 return (DEFAULT_ABI
== ABI_V4
7992 && !flag_pic
&& !TARGET_TOC
7993 && (SYMBOL_REF_P (x
) || GET_CODE (x
) == CONST
)
7994 && small_data_operand (x
, mode
));
7998 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
7999 bool strict
, bool worst_case
)
8001 unsigned HOST_WIDE_INT offset
;
8004 if (GET_CODE (x
) != PLUS
)
8006 if (!REG_P (XEXP (x
, 0)))
8008 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8010 if (mode_supports_dq_form (mode
))
8011 return quad_address_p (x
, mode
, strict
);
8012 if (!reg_offset_addressing_ok_p (mode
))
8013 return virtual_stack_registers_memory_p (x
);
8014 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
8016 if (!CONST_INT_P (XEXP (x
, 1)))
8019 offset
= INTVAL (XEXP (x
, 1));
8026 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8028 if (VECTOR_MEM_VSX_P (mode
))
8033 if (!TARGET_POWERPC64
)
8035 else if (offset
& 3)
8048 if (!TARGET_POWERPC64
)
8050 else if (offset
& 3)
8059 return offset
< 0x10000 - extra
;
8063 legitimate_indexed_address_p (rtx x
, int strict
)
8067 if (GET_CODE (x
) != PLUS
)
8073 return (REG_P (op0
) && REG_P (op1
)
8074 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
8075 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
8076 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
8077 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
8081 avoiding_indexed_address_p (machine_mode mode
)
8083 /* Avoid indexed addressing for modes that have non-indexed
8084 load/store instruction forms. */
8085 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
8089 legitimate_indirect_address_p (rtx x
, int strict
)
8091 return REG_P (x
) && INT_REG_OK_FOR_BASE_P (x
, strict
);
8095 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
8097 if (!TARGET_MACHO
|| !flag_pic
8098 || mode
!= SImode
|| !MEM_P (x
))
8102 if (GET_CODE (x
) != LO_SUM
)
8104 if (!REG_P (XEXP (x
, 0)))
8106 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
8110 return CONSTANT_P (x
);
8114 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
8116 if (GET_CODE (x
) != LO_SUM
)
8118 if (!REG_P (XEXP (x
, 0)))
8120 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8122 /* quad word addresses are restricted, and we can't use LO_SUM. */
8123 if (mode_supports_dq_form (mode
))
8127 if (TARGET_ELF
|| TARGET_MACHO
)
8131 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
8133 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8134 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8135 recognizes some LO_SUM addresses as valid although this
8136 function says opposite. In most cases, LRA through different
8137 transformations can generate correct code for address reloads.
8138 It cannot manage only some LO_SUM cases. So we need to add
8139 code analogous to one in rs6000_legitimize_reload_address for
8140 LOW_SUM here saying that some addresses are still valid. */
8141 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
8142 && small_toc_ref (x
, VOIDmode
));
8143 if (TARGET_TOC
&& ! large_toc_ok
)
8145 if (GET_MODE_NUNITS (mode
) != 1)
8147 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
8148 && !(/* ??? Assume floating point reg based on mode? */
8149 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
)))
8152 return CONSTANT_P (x
) || large_toc_ok
;
8159 /* Try machine-dependent ways of modifying an illegitimate address
8160 to be legitimate. If we find one, return the new, valid address.
8161 This is used from only one place: `memory_address' in explow.c.
8163 OLDX is the address as it was before break_out_memory_refs was
8164 called. In some cases it is useful to look at this to decide what
8167 It is always safe for this function to do nothing. It exists to
8168 recognize opportunities to optimize the output.
8170 On RS/6000, first check for the sum of a register with a constant
8171 integer that is out of range. If so, generate code to add the
8172 constant with the low-order 16 bits masked to the register and force
8173 this result into another register (this can be done with `cau').
8174 Then generate an address of REG+(CONST&0xffff), allowing for the
8175 possibility of bit 16 being a one.
8177 Then check for the sum of a register and something not constant, try to
8178 load the other things into a register and return the sum. */
8181 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
8186 if (!reg_offset_addressing_ok_p (mode
)
8187 || mode_supports_dq_form (mode
))
8189 if (virtual_stack_registers_memory_p (x
))
8192 /* In theory we should not be seeing addresses of the form reg+0,
8193 but just in case it is generated, optimize it away. */
8194 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
8195 return force_reg (Pmode
, XEXP (x
, 0));
8197 /* For TImode with load/store quad, restrict addresses to just a single
8198 pointer, so it works with both GPRs and VSX registers. */
8199 /* Make sure both operands are registers. */
8200 else if (GET_CODE (x
) == PLUS
8201 && (mode
!= TImode
|| !TARGET_VSX
))
8202 return gen_rtx_PLUS (Pmode
,
8203 force_reg (Pmode
, XEXP (x
, 0)),
8204 force_reg (Pmode
, XEXP (x
, 1)));
8206 return force_reg (Pmode
, x
);
8208 if (SYMBOL_REF_P (x
))
8210 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
8212 return rs6000_legitimize_tls_address (x
, model
);
8224 /* As in legitimate_offset_address_p we do not assume
8225 worst-case. The mode here is just a hint as to the registers
8226 used. A TImode is usually in gprs, but may actually be in
8227 fprs. Leave worst-case scenario for reload to handle via
8228 insn constraints. PTImode is only GPRs. */
8235 if (GET_CODE (x
) == PLUS
8236 && REG_P (XEXP (x
, 0))
8237 && CONST_INT_P (XEXP (x
, 1))
8238 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
8239 >= 0x10000 - extra
))
8241 HOST_WIDE_INT high_int
, low_int
;
8243 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8244 if (low_int
>= 0x8000 - extra
)
8246 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
8247 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8248 GEN_INT (high_int
)), 0);
8249 return plus_constant (Pmode
, sum
, low_int
);
8251 else if (GET_CODE (x
) == PLUS
8252 && REG_P (XEXP (x
, 0))
8253 && !CONST_INT_P (XEXP (x
, 1))
8254 && GET_MODE_NUNITS (mode
) == 1
8255 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8256 || (/* ??? Assume floating point reg based on mode? */
8257 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
)))
8258 && !avoiding_indexed_address_p (mode
))
8260 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8261 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
8263 else if ((TARGET_ELF
8265 || !MACHO_DYNAMIC_NO_PIC_P
8272 && !CONST_WIDE_INT_P (x
)
8273 && !CONST_DOUBLE_P (x
)
8275 && GET_MODE_NUNITS (mode
) == 1
8276 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8277 || (/* ??? Assume floating point reg based on mode? */
8278 TARGET_HARD_FLOAT
&& (mode
== DFmode
|| mode
== DDmode
))))
8280 rtx reg
= gen_reg_rtx (Pmode
);
8282 emit_insn (gen_elf_high (reg
, x
));
8284 emit_insn (gen_macho_high (reg
, x
));
8285 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
8289 && constant_pool_expr_p (x
)
8290 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
8291 return create_TOC_reference (x
, NULL_RTX
);
8296 /* Debug version of rs6000_legitimize_address. */
8298 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
8304 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
8305 insns
= get_insns ();
8311 "\nrs6000_legitimize_address: mode %s, old code %s, "
8312 "new code %s, modified\n",
8313 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
8314 GET_RTX_NAME (GET_CODE (ret
)));
8316 fprintf (stderr
, "Original address:\n");
8319 fprintf (stderr
, "oldx:\n");
8322 fprintf (stderr
, "New address:\n");
8327 fprintf (stderr
, "Insns added:\n");
8328 debug_rtx_list (insns
, 20);
8334 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8335 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
8346 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8347 We need to emit DTP-relative relocations. */
8349 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
8351 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8356 fputs ("\t.long\t", file
);
8359 fputs (DOUBLE_INT_ASM_OP
, file
);
8364 output_addr_const (file
, x
);
8366 fputs ("@dtprel+0x8000", file
);
8367 else if (TARGET_XCOFF
&& SYMBOL_REF_P (x
))
8369 switch (SYMBOL_REF_TLS_MODEL (x
))
8373 case TLS_MODEL_LOCAL_EXEC
:
8374 fputs ("@le", file
);
8376 case TLS_MODEL_INITIAL_EXEC
:
8377 fputs ("@ie", file
);
8379 case TLS_MODEL_GLOBAL_DYNAMIC
:
8380 case TLS_MODEL_LOCAL_DYNAMIC
:
8389 /* Return true if X is a symbol that refers to real (rather than emulated)
8393 rs6000_real_tls_symbol_ref_p (rtx x
)
8395 return (SYMBOL_REF_P (x
)
8396 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
8399 /* In the name of slightly smaller debug output, and to cater to
8400 general assembler lossage, recognize various UNSPEC sequences
8401 and turn them back into a direct symbol reference. */
8404 rs6000_delegitimize_address (rtx orig_x
)
8408 if (GET_CODE (orig_x
) == UNSPEC
&& XINT (orig_x
, 1) == UNSPEC_FUSION_GPR
)
8409 orig_x
= XVECEXP (orig_x
, 0, 0);
8411 orig_x
= delegitimize_mem_from_attrs (orig_x
);
8418 if (TARGET_CMODEL
!= CMODEL_SMALL
&& GET_CODE (y
) == LO_SUM
)
8422 if (GET_CODE (y
) == PLUS
8423 && GET_MODE (y
) == Pmode
8424 && CONST_INT_P (XEXP (y
, 1)))
8426 offset
= XEXP (y
, 1);
8430 if (GET_CODE (y
) == UNSPEC
&& XINT (y
, 1) == UNSPEC_TOCREL
)
8432 y
= XVECEXP (y
, 0, 0);
8435 /* Do not associate thread-local symbols with the original
8436 constant pool symbol. */
8439 && CONSTANT_POOL_ADDRESS_P (y
)
8440 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
8444 if (offset
!= NULL_RTX
)
8445 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
8446 if (!MEM_P (orig_x
))
8449 return replace_equiv_address_nv (orig_x
, y
);
8453 && GET_CODE (orig_x
) == LO_SUM
8454 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
8456 y
= XEXP (XEXP (orig_x
, 1), 0);
8457 if (GET_CODE (y
) == UNSPEC
&& XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
8458 return XVECEXP (y
, 0, 0);
8464 /* Return true if X shouldn't be emitted into the debug info.
8465 The linker doesn't like .toc section references from
8466 .debug_* sections, so reject .toc section symbols. */
8469 rs6000_const_not_ok_for_debug_p (rtx x
)
8471 if (GET_CODE (x
) == UNSPEC
)
8473 if (SYMBOL_REF_P (x
)
8474 && CONSTANT_POOL_ADDRESS_P (x
))
8476 rtx c
= get_pool_constant (x
);
8477 machine_mode cmode
= get_pool_mode (x
);
8478 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
8485 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8488 rs6000_legitimate_combined_insn (rtx_insn
*insn
)
8490 int icode
= INSN_CODE (insn
);
8492 /* Reject creating doloop insns. Combine should not be allowed
8493 to create these for a number of reasons:
8494 1) In a nested loop, if combine creates one of these in an
8495 outer loop and the register allocator happens to allocate ctr
8496 to the outer loop insn, then the inner loop can't use ctr.
8497 Inner loops ought to be more highly optimized.
8498 2) Combine often wants to create one of these from what was
8499 originally a three insn sequence, first combining the three
8500 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8501 allocated ctr, the splitter takes use back to the three insn
8502 sequence. It's better to stop combine at the two insn
8504 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8505 insns, the register allocator sometimes uses floating point
8506 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8507 jump insn and output reloads are not implemented for jumps,
8508 the ctrsi/ctrdi splitters need to handle all possible cases.
8509 That's a pain, and it gets to be seriously difficult when a
8510 splitter that runs after reload needs memory to transfer from
8511 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8512 for the difficult case. It's better to not create problems
8513 in the first place. */
8514 if (icode
!= CODE_FOR_nothing
8515 && (icode
== CODE_FOR_bdz_si
8516 || icode
== CODE_FOR_bdz_di
8517 || icode
== CODE_FOR_bdnz_si
8518 || icode
== CODE_FOR_bdnz_di
8519 || icode
== CODE_FOR_bdztf_si
8520 || icode
== CODE_FOR_bdztf_di
8521 || icode
== CODE_FOR_bdnztf_si
8522 || icode
== CODE_FOR_bdnztf_di
))
8528 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8530 static GTY(()) rtx rs6000_tls_symbol
;
8532 rs6000_tls_get_addr (void)
8534 if (!rs6000_tls_symbol
)
8535 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
8537 return rs6000_tls_symbol
;
8540 /* Construct the SYMBOL_REF for TLS GOT references. */
8542 static GTY(()) rtx rs6000_got_symbol
;
8544 rs6000_got_sym (void)
8546 if (!rs6000_got_symbol
)
8548 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8549 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
8550 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
8553 return rs6000_got_symbol
;
8556 /* AIX Thread-Local Address support. */
8559 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
8561 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
8565 name
= XSTR (addr
, 0);
8566 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8567 or the symbol will be in TLS private data section. */
8568 if (name
[strlen (name
) - 1] != ']'
8569 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
8570 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
8572 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
8573 strcpy (tlsname
, name
);
8575 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
8576 tlsaddr
= copy_rtx (addr
);
8577 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
8582 /* Place addr into TOC constant pool. */
8583 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
8585 /* Output the TOC entry and create the MEM referencing the value. */
8586 if (constant_pool_expr_p (XEXP (sym
, 0))
8587 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
8589 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
8590 mem
= gen_const_mem (Pmode
, tocref
);
8591 set_mem_alias_set (mem
, get_TOC_alias_set ());
8596 /* Use global-dynamic for local-dynamic. */
8597 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
8598 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
8600 /* Create new TOC reference for @m symbol. */
8601 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
8602 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
8603 strcpy (tlsname
, "*LCM");
8604 strcat (tlsname
, name
+ 3);
8605 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
8606 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
8607 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
8608 rtx modmem
= gen_const_mem (Pmode
, tocref
);
8609 set_mem_alias_set (modmem
, get_TOC_alias_set ());
8611 rtx modreg
= gen_reg_rtx (Pmode
);
8612 emit_insn (gen_rtx_SET (modreg
, modmem
));
8614 tmpreg
= gen_reg_rtx (Pmode
);
8615 emit_insn (gen_rtx_SET (tmpreg
, mem
));
8617 dest
= gen_reg_rtx (Pmode
);
8619 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
8621 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
8624 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8625 else if (TARGET_32BIT
)
8627 tlsreg
= gen_reg_rtx (SImode
);
8628 emit_insn (gen_tls_get_tpointer (tlsreg
));
8631 tlsreg
= gen_rtx_REG (DImode
, 13);
8633 /* Load the TOC value into temporary register. */
8634 tmpreg
= gen_reg_rtx (Pmode
);
8635 emit_insn (gen_rtx_SET (tmpreg
, mem
));
8636 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
8637 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
8639 /* Add TOC symbol value to TLS pointer. */
8640 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
8645 /* Output arg setup instructions for a !TARGET_TLS_MARKERS
8646 __tls_get_addr call. */
8649 rs6000_output_tlsargs (rtx
*operands
)
8651 /* Set up operands for output_asm_insn, without modifying OPERANDS. */
8654 /* The set dest of the call, ie. r3, which is also the first arg reg. */
8655 op
[0] = operands
[0];
8656 /* The TLS symbol from global_tlsarg stashed as CALL operand 2. */
8657 op
[1] = XVECEXP (operands
[2], 0, 0);
8658 if (XINT (operands
[2], 1) == UNSPEC_TLSGD
)
8660 /* The GOT register. */
8661 op
[2] = XVECEXP (operands
[2], 0, 1);
8662 if (TARGET_CMODEL
!= CMODEL_SMALL
)
8663 output_asm_insn ("addis %0,%2,%1@got@tlsgd@ha\n\t"
8664 "addi %0,%0,%1@got@tlsgd@l", op
);
8666 output_asm_insn ("addi %0,%2,%1@got@tlsgd", op
);
8668 else if (XINT (operands
[2], 1) == UNSPEC_TLSLD
)
8670 if (TARGET_CMODEL
!= CMODEL_SMALL
)
8671 output_asm_insn ("addis %0,%1,%&@got@tlsld@ha\n\t"
8672 "addi %0,%0,%&@got@tlsld@l", op
);
8674 output_asm_insn ("addi %0,%1,%&@got@tlsld", op
);
8680 /* Passes the tls arg value for global dynamic and local dynamic
8681 emit_library_call_value in rs6000_legitimize_tls_address to
8682 rs6000_call_aix and rs6000_call_sysv. This is used to emit the
8683 marker relocs put on __tls_get_addr calls. */
8684 static rtx global_tlsarg
;
8686 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8687 this (thread-local) address. */
8690 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
8695 return rs6000_legitimize_tls_address_aix (addr
, model
);
8697 dest
= gen_reg_rtx (Pmode
);
8698 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
8704 tlsreg
= gen_rtx_REG (Pmode
, 13);
8705 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
8709 tlsreg
= gen_rtx_REG (Pmode
, 2);
8710 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
8714 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
8718 tmp
= gen_reg_rtx (Pmode
);
8721 tlsreg
= gen_rtx_REG (Pmode
, 13);
8722 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
8726 tlsreg
= gen_rtx_REG (Pmode
, 2);
8727 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
8731 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
8733 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
8738 rtx got
, tga
, tmp1
, tmp2
;
8740 /* We currently use relocations like @got@tlsgd for tls, which
8741 means the linker will handle allocation of tls entries, placing
8742 them in the .got section. So use a pointer to the .got section,
8743 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8744 or to secondary GOT sections used by 32-bit -fPIC. */
8746 got
= gen_rtx_REG (Pmode
, 2);
8750 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
8753 rtx gsym
= rs6000_got_sym ();
8754 got
= gen_reg_rtx (Pmode
);
8756 rs6000_emit_move (got
, gsym
, Pmode
);
8761 tmp1
= gen_reg_rtx (Pmode
);
8762 tmp2
= gen_reg_rtx (Pmode
);
8763 mem
= gen_const_mem (Pmode
, tmp1
);
8764 lab
= gen_label_rtx ();
8765 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
8766 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
8767 if (TARGET_LINK_STACK
)
8768 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
8769 emit_move_insn (tmp2
, mem
);
8770 rtx_insn
*last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
8771 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
8776 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
8778 rtx arg
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addr
, got
),
8780 tga
= rs6000_tls_get_addr ();
8781 global_tlsarg
= arg
;
8782 if (TARGET_TLS_MARKERS
)
8784 rtx argreg
= gen_rtx_REG (Pmode
, 3);
8785 emit_insn (gen_rtx_SET (argreg
, arg
));
8786 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
8790 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
);
8791 global_tlsarg
= NULL_RTX
;
8793 /* Make a note so that the result of this call can be CSEd. */
8794 rtvec vec
= gen_rtvec (1, copy_rtx (arg
));
8795 rtx uns
= gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_TLS_GET_ADDR
);
8796 set_unique_reg_note (get_last_insn (), REG_EQUAL
, uns
);
8798 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
8800 rtx arg
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got
), UNSPEC_TLSLD
);
8801 tga
= rs6000_tls_get_addr ();
8802 tmp1
= gen_reg_rtx (Pmode
);
8803 global_tlsarg
= arg
;
8804 if (TARGET_TLS_MARKERS
)
8806 rtx argreg
= gen_rtx_REG (Pmode
, 3);
8807 emit_insn (gen_rtx_SET (argreg
, arg
));
8808 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
8812 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
);
8813 global_tlsarg
= NULL_RTX
;
8815 /* Make a note so that the result of this call can be CSEd. */
8816 rtvec vec
= gen_rtvec (1, copy_rtx (arg
));
8817 rtx uns
= gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_TLS_GET_ADDR
);
8818 set_unique_reg_note (get_last_insn (), REG_EQUAL
, uns
);
8820 if (rs6000_tls_size
== 16)
8823 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
8825 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
8827 else if (rs6000_tls_size
== 32)
8829 tmp2
= gen_reg_rtx (Pmode
);
8831 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
8833 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
8836 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
8838 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
8842 tmp2
= gen_reg_rtx (Pmode
);
8844 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
8846 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
8848 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
8854 /* IE, or 64-bit offset LE. */
8855 tmp2
= gen_reg_rtx (Pmode
);
8857 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
8859 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
8862 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
8864 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
8872 /* Only create the global variable for the stack protect guard if we are using
8873 the global flavor of that guard. */
8875 rs6000_init_stack_protect_guard (void)
8877 if (rs6000_stack_protector_guard
== SSP_GLOBAL
)
8878 return default_stack_protect_guard ();
8883 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8886 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
8888 if (GET_CODE (x
) == HIGH
8889 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
8892 /* A TLS symbol in the TOC cannot contain a sum. */
8893 if (GET_CODE (x
) == CONST
8894 && GET_CODE (XEXP (x
, 0)) == PLUS
8895 && SYMBOL_REF_P (XEXP (XEXP (x
, 0), 0))
8896 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
8899 /* Do not place an ELF TLS symbol in the constant pool. */
8900 return TARGET_ELF
&& tls_referenced_p (x
);
8903 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8904 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8905 can be addressed relative to the toc pointer. */
8908 use_toc_relative_ref (rtx sym
, machine_mode mode
)
8910 return ((constant_pool_expr_p (sym
)
8911 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
8912 get_pool_mode (sym
)))
8913 || (TARGET_CMODEL
== CMODEL_MEDIUM
8914 && SYMBOL_REF_LOCAL_P (sym
)
8915 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
8918 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
8919 replace the input X, or the original X if no replacement is called for.
8920 The output parameter *WIN is 1 if the calling macro should goto WIN,
8923 For RS/6000, we wish to handle large displacements off a base
8924 register by splitting the addend across an addiu/addis and the mem insn.
8925 This cuts number of extra insns needed from 3 to 1.
8927 On Darwin, we use this to generate code for floating point constants.
8928 A movsf_low is generated so we wind up with 2 instructions rather than 3.
8929 The Darwin code is inside #if TARGET_MACHO because only then are the
8930 machopic_* functions defined. */
8932 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
8933 int opnum
, int type
,
8934 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
8936 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
8937 bool quad_offset_p
= mode_supports_dq_form (mode
);
8939 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
8940 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
8943 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
8944 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)
8945 || (mode
== SFmode
&& recog_data
.operand_mode
[0] == V4SFmode
8946 && TARGET_P9_VECTOR
)
8947 || (mode
== SImode
&& recog_data
.operand_mode
[0] == V4SImode
8948 && TARGET_P9_VECTOR
)))
8949 reg_offset_p
= false;
8951 /* We must recognize output that we have already generated ourselves. */
8952 if (GET_CODE (x
) == PLUS
8953 && GET_CODE (XEXP (x
, 0)) == PLUS
8954 && REG_P (XEXP (XEXP (x
, 0), 0))
8955 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8956 && CONST_INT_P (XEXP (x
, 1)))
8958 if (TARGET_DEBUG_ADDR
)
8960 fprintf (stderr
, "\nlegitimize_reload_address push_reload #1:\n");
8963 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8964 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
8965 opnum
, (enum reload_type
) type
);
8970 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
8971 if (GET_CODE (x
) == LO_SUM
8972 && GET_CODE (XEXP (x
, 0)) == HIGH
)
8974 if (TARGET_DEBUG_ADDR
)
8976 fprintf (stderr
, "\nlegitimize_reload_address push_reload #2:\n");
8979 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8980 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8981 opnum
, (enum reload_type
) type
);
8987 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
8988 && GET_CODE (x
) == LO_SUM
8989 && GET_CODE (XEXP (x
, 0)) == PLUS
8990 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
8991 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
8992 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
8993 && machopic_operand_p (XEXP (x
, 1)))
8995 /* Result of previous invocation of this function on Darwin
8996 floating point constant. */
8997 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8998 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8999 opnum
, (enum reload_type
) type
);
9005 if (TARGET_CMODEL
!= CMODEL_SMALL
9008 && small_toc_ref (x
, VOIDmode
))
9010 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
9011 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
9012 if (TARGET_DEBUG_ADDR
)
9014 fprintf (stderr
, "\nlegitimize_reload_address push_reload #3:\n");
9017 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9018 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9019 opnum
, (enum reload_type
) type
);
9024 if (GET_CODE (x
) == PLUS
9025 && REG_P (XEXP (x
, 0))
9026 && HARD_REGISTER_P (XEXP (x
, 0))
9027 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
9028 && CONST_INT_P (XEXP (x
, 1))
9030 && (quad_offset_p
|| !VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
9032 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
9033 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
9035 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9037 /* Check for 32-bit overflow or quad addresses with one of the
9038 four least significant bits set. */
9039 if (high
+ low
!= val
9040 || (quad_offset_p
&& (low
& 0xf)))
9046 /* Reload the high part into a base reg; leave the low part
9047 in the mem directly. */
9049 x
= gen_rtx_PLUS (GET_MODE (x
),
9050 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
9054 if (TARGET_DEBUG_ADDR
)
9056 fprintf (stderr
, "\nlegitimize_reload_address push_reload #4:\n");
9059 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9060 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
9061 opnum
, (enum reload_type
) type
);
9066 if (SYMBOL_REF_P (x
)
9069 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
9071 && DEFAULT_ABI
== ABI_DARWIN
9072 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
9073 && machopic_symbol_defined_p (x
)
9075 && DEFAULT_ABI
== ABI_V4
9078 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9079 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9081 ??? Assume floating point reg based on mode? This assumption is
9082 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9083 where reload ends up doing a DFmode load of a constant from
9084 mem using two gprs. Unfortunately, at this point reload
9085 hasn't yet selected regs so poking around in reload data
9086 won't help and even if we could figure out the regs reliably,
9087 we'd still want to allow this transformation when the mem is
9088 naturally aligned. Since we say the address is good here, we
9089 can't disable offsets from LO_SUMs in mem_operand_gpr.
9090 FIXME: Allow offset from lo_sum for other modes too, when
9091 mem is sufficiently aligned.
9093 Also disallow this if the type can go in VMX/Altivec registers, since
9094 those registers do not have d-form (reg+offset) address modes. */
9095 && !reg_addr
[mode
].scalar_in_vmx_p
9100 && (mode
!= TImode
|| !TARGET_VSX
)
9102 && (mode
!= DImode
|| TARGET_POWERPC64
)
9103 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
9104 || TARGET_HARD_FLOAT
))
9109 rtx offset
= machopic_gen_offset (x
);
9110 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9111 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
9112 gen_rtx_HIGH (Pmode
, offset
)), offset
);
9116 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9117 gen_rtx_HIGH (Pmode
, x
), x
);
9119 if (TARGET_DEBUG_ADDR
)
9121 fprintf (stderr
, "\nlegitimize_reload_address push_reload #5:\n");
9124 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9125 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9126 opnum
, (enum reload_type
) type
);
9131 /* Reload an offset address wrapped by an AND that represents the
9132 masking of the lower bits. Strip the outer AND and let reload
9133 convert the offset address into an indirect address. For VSX,
9134 force reload to create the address with an AND in a separate
9135 register, because we can't guarantee an altivec register will
9137 if (VECTOR_MEM_ALTIVEC_P (mode
)
9138 && GET_CODE (x
) == AND
9139 && GET_CODE (XEXP (x
, 0)) == PLUS
9140 && REG_P (XEXP (XEXP (x
, 0), 0))
9141 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9142 && CONST_INT_P (XEXP (x
, 1))
9143 && INTVAL (XEXP (x
, 1)) == -16)
9154 && use_toc_relative_ref (x
, mode
))
9156 x
= create_TOC_reference (x
, NULL_RTX
);
9157 if (TARGET_CMODEL
!= CMODEL_SMALL
)
9159 if (TARGET_DEBUG_ADDR
)
9161 fprintf (stderr
, "\nlegitimize_reload_address push_reload #6:\n");
9164 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9165 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9166 opnum
, (enum reload_type
) type
);
9175 /* Debug version of rs6000_legitimize_reload_address. */
9177 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
9178 int opnum
, int type
,
9179 int ind_levels
, int *win
)
9181 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
9184 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9185 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9186 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
9190 fprintf (stderr
, "Same address returned\n");
9192 fprintf (stderr
, "NULL returned\n");
9195 fprintf (stderr
, "New address:\n");
9202 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9203 that is a valid memory address for an instruction.
9204 The MODE argument is the machine mode for the MEM expression
9205 that wants to use this address.
9207 On the RS/6000, there are four valid address: a SYMBOL_REF that
9208 refers to a constant pool entry of an address (or the sum of it
9209 plus a constant), a short (16-bit signed) constant plus a register,
9210 the sum of two registers, or a register indirect, possibly with an
9211 auto-increment. For DFmode, DDmode and DImode with a constant plus
9212 register, we must ensure that both words are addressable or PowerPC64
9213 with offset word aligned.
9215 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9216 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9217 because adjacent memory cells are accessed by adding word-sized offsets
9218 during assembly output. */
9220 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
9222 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
9223 bool quad_offset_p
= mode_supports_dq_form (mode
);
9225 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9226 if (VECTOR_MEM_ALTIVEC_P (mode
)
9227 && GET_CODE (x
) == AND
9228 && CONST_INT_P (XEXP (x
, 1))
9229 && INTVAL (XEXP (x
, 1)) == -16)
9232 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
9234 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
9237 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
9238 && mode_supports_pre_incdec_p (mode
)
9239 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
9241 /* Handle restricted vector d-form offsets in ISA 3.0. */
9244 if (quad_address_p (x
, mode
, reg_ok_strict
))
9247 else if (virtual_stack_registers_memory_p (x
))
9250 else if (reg_offset_p
)
9252 if (legitimate_small_data_p (mode
, x
))
9254 if (legitimate_constant_pool_address_p (x
, mode
,
9255 reg_ok_strict
|| lra_in_progress
))
9259 /* For TImode, if we have TImode in VSX registers, only allow register
9260 indirect addresses. This will allow the values to go in either GPRs
9261 or VSX registers without reloading. The vector types would tend to
9262 go into VSX registers, so we allow REG+REG, while TImode seems
9263 somewhat split, in that some uses are GPR based, and some VSX based. */
9264 /* FIXME: We could loosen this by changing the following to
9265 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9266 but currently we cannot allow REG+REG addressing for TImode. See
9267 PR72827 for complete details on how this ends up hoodwinking DSE. */
9268 if (mode
== TImode
&& TARGET_VSX
)
9270 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9273 && GET_CODE (x
) == PLUS
9274 && REG_P (XEXP (x
, 0))
9275 && (XEXP (x
, 0) == virtual_stack_vars_rtx
9276 || XEXP (x
, 0) == arg_pointer_rtx
)
9277 && CONST_INT_P (XEXP (x
, 1)))
9279 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
9281 if (!FLOAT128_2REG_P (mode
)
9282 && (TARGET_HARD_FLOAT
9284 || (mode
!= DFmode
&& mode
!= DDmode
))
9285 && (TARGET_POWERPC64
|| mode
!= DImode
)
9286 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
9288 && !avoiding_indexed_address_p (mode
)
9289 && legitimate_indexed_address_p (x
, reg_ok_strict
))
9291 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
9292 && mode_supports_pre_modify_p (mode
)
9293 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
9294 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
9295 reg_ok_strict
, false)
9296 || (!avoiding_indexed_address_p (mode
)
9297 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
9298 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
9300 if (reg_offset_p
&& !quad_offset_p
9301 && legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
9306 /* Debug version of rs6000_legitimate_address_p. */
9308 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
9311 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
9313 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9314 "strict = %d, reload = %s, code = %s\n",
9315 ret
? "true" : "false",
9316 GET_MODE_NAME (mode
),
9318 (reload_completed
? "after" : "before"),
9319 GET_RTX_NAME (GET_CODE (x
)));
9325 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9328 rs6000_mode_dependent_address_p (const_rtx addr
,
9329 addr_space_t as ATTRIBUTE_UNUSED
)
9331 return rs6000_mode_dependent_address_ptr (addr
);
9334 /* Go to LABEL if ADDR (a legitimate address expression)
9335 has an effect that depends on the machine mode it is used for.
9337 On the RS/6000 this is true of all integral offsets (since AltiVec
9338 and VSX modes don't allow them) or is a pre-increment or decrement.
9340 ??? Except that due to conceptual problems in offsettable_address_p
9341 we can't really report the problems of integral offsets. So leave
9342 this assuming that the adjustable offset must be valid for the
9343 sub-words of a TFmode operand, which is what we had before. */
9346 rs6000_mode_dependent_address (const_rtx addr
)
9348 switch (GET_CODE (addr
))
9351 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9352 is considered a legitimate address before reload, so there
9353 are no offset restrictions in that case. Note that this
9354 condition is safe in strict mode because any address involving
9355 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9356 been rejected as illegitimate. */
9357 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
9358 && XEXP (addr
, 0) != arg_pointer_rtx
9359 && CONST_INT_P (XEXP (addr
, 1)))
9361 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
9362 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
9367 /* Anything in the constant pool is sufficiently aligned that
9368 all bytes have the same high part address. */
9369 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
9371 /* Auto-increment cases are now treated generically in recog.c. */
9373 return TARGET_UPDATE
;
9375 /* AND is only allowed in Altivec loads. */
9386 /* Debug version of rs6000_mode_dependent_address. */
9388 rs6000_debug_mode_dependent_address (const_rtx addr
)
9390 bool ret
= rs6000_mode_dependent_address (addr
);
9392 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
9393 ret
? "true" : "false");
9399 /* Implement FIND_BASE_TERM. */
9402 rs6000_find_base_term (rtx op
)
9407 if (GET_CODE (base
) == CONST
)
9408 base
= XEXP (base
, 0);
9409 if (GET_CODE (base
) == PLUS
)
9410 base
= XEXP (base
, 0);
9411 if (GET_CODE (base
) == UNSPEC
)
9412 switch (XINT (base
, 1))
9415 case UNSPEC_MACHOPIC_OFFSET
:
9416 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9417 for aliasing purposes. */
9418 return XVECEXP (base
, 0, 0);
9424 /* More elaborate version of recog's offsettable_memref_p predicate
9425 that works around the ??? note of rs6000_mode_dependent_address.
9426 In particular it accepts
9428 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9430 in 32-bit mode, that the recog predicate rejects. */
9433 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
, bool strict
)
9440 /* First mimic offsettable_memref_p. */
9441 if (offsettable_address_p (strict
, GET_MODE (op
), XEXP (op
, 0)))
9444 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9445 the latter predicate knows nothing about the mode of the memory
9446 reference and, therefore, assumes that it is the largest supported
9447 mode (TFmode). As a consequence, legitimate offsettable memory
9448 references are rejected. rs6000_legitimate_offset_address_p contains
9449 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9450 at least with a little bit of help here given that we know the
9451 actual registers used. */
9452 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
9453 || GET_MODE_SIZE (reg_mode
) == 4);
9454 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
9455 strict
, worst_case
);
9458 /* Determine the reassociation width to be used in reassociate_bb.
9459 This takes into account how many parallel operations we
9460 can actually do of a given type, and also the latency.
9464 vect add/sub/mul 2/cycle
9465 fp add/sub/mul 2/cycle
9470 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
9473 switch (rs6000_tune
)
9475 case PROCESSOR_POWER8
:
9476 case PROCESSOR_POWER9
:
9477 if (DECIMAL_FLOAT_MODE_P (mode
))
9479 if (VECTOR_MODE_P (mode
))
9481 if (INTEGRAL_MODE_P (mode
))
9483 if (FLOAT_MODE_P (mode
))
9492 /* Change register usage conditional on target flags. */
9494 rs6000_conditional_register_usage (void)
9498 if (TARGET_DEBUG_TARGET
)
9499 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
9501 /* Set MQ register fixed (already call_used) so that it will not be
9505 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9507 fixed_regs
[13] = call_used_regs
[13]
9508 = call_really_used_regs
[13] = 1;
9510 /* Conditionally disable FPRs. */
9511 if (TARGET_SOFT_FLOAT
)
9512 for (i
= 32; i
< 64; i
++)
9513 fixed_regs
[i
] = call_used_regs
[i
]
9514 = call_really_used_regs
[i
] = 1;
9516 /* The TOC register is not killed across calls in a way that is
9517 visible to the compiler. */
9518 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9519 call_really_used_regs
[2] = 0;
9521 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
9522 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9524 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
9525 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9526 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9527 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9529 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
9530 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9531 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9532 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9534 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
9535 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9536 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9538 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
9540 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
9541 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9542 call_really_used_regs
[VRSAVE_REGNO
] = 1;
9545 if (TARGET_ALTIVEC
|| TARGET_VSX
)
9546 global_regs
[VSCR_REGNO
] = 1;
9548 if (TARGET_ALTIVEC_ABI
)
9550 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
9551 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9553 /* AIX reserves VR20:31 in non-extended ABI mode. */
9555 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
9556 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9561 /* Output insns to set DEST equal to the constant SOURCE as a series of
9562 lis, ori and shl instructions and return TRUE. */
9565 rs6000_emit_set_const (rtx dest
, rtx source
)
9567 machine_mode mode
= GET_MODE (dest
);
9572 gcc_checking_assert (CONST_INT_P (source
));
9573 c
= INTVAL (source
);
9578 emit_insn (gen_rtx_SET (dest
, source
));
9582 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
9584 emit_insn (gen_rtx_SET (copy_rtx (temp
),
9585 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
9586 emit_insn (gen_rtx_SET (dest
,
9587 gen_rtx_IOR (SImode
, copy_rtx (temp
),
9588 GEN_INT (c
& 0xffff))));
9592 if (!TARGET_POWERPC64
)
9596 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
9598 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
9600 emit_move_insn (hi
, GEN_INT (c
>> 32));
9601 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
9602 emit_move_insn (lo
, GEN_INT (c
));
9605 rs6000_emit_set_long_const (dest
, c
);
9612 insn
= get_last_insn ();
9613 set
= single_set (insn
);
9614 if (! CONSTANT_P (SET_SRC (set
)))
9615 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
9620 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9621 Output insns to set DEST equal to the constant C as a series of
9622 lis, ori and shl instructions. */
9625 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
9628 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
9638 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
9639 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
9640 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
9642 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
9643 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
9645 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9647 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9648 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
9650 emit_move_insn (dest
,
9651 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9654 else if (ud3
== 0 && ud4
== 0)
9656 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9658 gcc_assert (ud2
& 0x8000);
9659 emit_move_insn (copy_rtx (temp
),
9660 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
9662 emit_move_insn (copy_rtx (temp
),
9663 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9665 emit_move_insn (dest
,
9666 gen_rtx_ZERO_EXTEND (DImode
,
9667 gen_lowpart (SImode
,
9670 else if ((ud4
== 0xffff && (ud3
& 0x8000))
9671 || (ud4
== 0 && ! (ud3
& 0x8000)))
9673 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9675 emit_move_insn (copy_rtx (temp
),
9676 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
9678 emit_move_insn (copy_rtx (temp
),
9679 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9681 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9682 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
9685 emit_move_insn (dest
,
9686 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9691 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9693 emit_move_insn (copy_rtx (temp
),
9694 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
9696 emit_move_insn (copy_rtx (temp
),
9697 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9700 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
9701 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
9704 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9705 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9706 GEN_INT (ud2
<< 16)));
9708 emit_move_insn (dest
,
9709 gen_rtx_IOR (DImode
, copy_rtx (temp
),
9714 /* Helper for the following. Get rid of [r+r] memory refs
9715 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9718 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
9720 if (MEM_P (operands
[0])
9721 && !REG_P (XEXP (operands
[0], 0))
9722 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
9723 GET_MODE (operands
[0]), false))
9725 = replace_equiv_address (operands
[0],
9726 copy_addr_to_reg (XEXP (operands
[0], 0)));
9728 if (MEM_P (operands
[1])
9729 && !REG_P (XEXP (operands
[1], 0))
9730 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
9731 GET_MODE (operands
[1]), false))
9733 = replace_equiv_address (operands
[1],
9734 copy_addr_to_reg (XEXP (operands
[1], 0)));
9737 /* Generate a vector of constants to permute MODE for a little-endian
9738 storage operation by swapping the two halves of a vector. */
9740 rs6000_const_vec (machine_mode mode
)
9768 v
= rtvec_alloc (subparts
);
9770 for (i
= 0; i
< subparts
/ 2; ++i
)
9771 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
9772 for (i
= subparts
/ 2; i
< subparts
; ++i
)
9773 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
9778 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9781 rs6000_emit_le_vsx_permute (rtx dest
, rtx source
, machine_mode mode
)
9783 /* Scalar permutations are easier to express in integer modes rather than
9784 floating-point modes, so cast them here. We use V1TImode instead
9785 of TImode to ensure that the values don't go through GPRs. */
9786 if (FLOAT128_VECTOR_P (mode
))
9788 dest
= gen_lowpart (V1TImode
, dest
);
9789 source
= gen_lowpart (V1TImode
, source
);
9793 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9795 if (mode
== TImode
|| mode
== V1TImode
)
9796 emit_insn (gen_rtx_SET (dest
, gen_rtx_ROTATE (mode
, source
,
9800 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
9801 emit_insn (gen_rtx_SET (dest
, gen_rtx_VEC_SELECT (mode
, source
, par
)));
9805 /* Emit a little-endian load from vector memory location SOURCE to VSX
9806 register DEST in mode MODE. The load is done with two permuting
9807 insn's that represent an lxvd2x and xxpermdi. */
9809 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
9811 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9813 if (mode
== TImode
|| mode
== V1TImode
)
9816 dest
= gen_lowpart (V2DImode
, dest
);
9817 source
= adjust_address (source
, V2DImode
, 0);
9820 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
9821 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
9822 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
9825 /* Emit a little-endian store to vector memory location DEST from VSX
9826 register SOURCE in mode MODE. The store is done with two permuting
9827 insn's that represent an xxpermdi and an stxvd2x. */
9829 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
9831 /* This should never be called during or after LRA, because it does
9832 not re-permute the source register. It is intended only for use
9834 gcc_assert (!lra_in_progress
&& !reload_completed
);
9836 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9838 if (mode
== TImode
|| mode
== V1TImode
)
9841 dest
= adjust_address (dest
, V2DImode
, 0);
9842 source
= gen_lowpart (V2DImode
, source
);
9845 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
9846 rs6000_emit_le_vsx_permute (tmp
, source
, mode
);
9847 rs6000_emit_le_vsx_permute (dest
, tmp
, mode
);
9850 /* Emit a sequence representing a little-endian VSX load or store,
9851 moving data from SOURCE to DEST in mode MODE. This is done
9852 separately from rs6000_emit_move to ensure it is called only
9853 during expand. LE VSX loads and stores introduced later are
9854 handled with a split. The expand-time RTL generation allows
9855 us to optimize away redundant pairs of register-permutes. */
9857 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
9859 gcc_assert (!BYTES_BIG_ENDIAN
9860 && VECTOR_MEM_VSX_P (mode
)
9861 && !TARGET_P9_VECTOR
9862 && !gpr_or_gpr_p (dest
, source
)
9863 && (MEM_P (source
) ^ MEM_P (dest
)));
9867 gcc_assert (REG_P (dest
) || SUBREG_P (dest
));
9868 rs6000_emit_le_vsx_load (dest
, source
, mode
);
9872 if (!REG_P (source
))
9873 source
= force_reg (mode
, source
);
9874 rs6000_emit_le_vsx_store (dest
, source
, mode
);
9878 /* Return whether a SFmode or SImode move can be done without converting one
9879 mode to another. This arrises when we have:
9881 (SUBREG:SF (REG:SI ...))
9882 (SUBREG:SI (REG:SF ...))
9884 and one of the values is in a floating point/vector register, where SFmode
9885 scalars are stored in DFmode format. */
9888 valid_sf_si_move (rtx dest
, rtx src
, machine_mode mode
)
9890 if (TARGET_ALLOW_SF_SUBREG
)
9893 if (mode
!= SFmode
&& GET_MODE_CLASS (mode
) != MODE_INT
)
9896 if (!SUBREG_P (src
) || !sf_subreg_operand (src
, mode
))
9899 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9900 if (SUBREG_P (dest
))
9902 rtx dest_subreg
= SUBREG_REG (dest
);
9903 rtx src_subreg
= SUBREG_REG (src
);
9904 return GET_MODE (dest_subreg
) == GET_MODE (src_subreg
);
9911 /* Helper function to change moves with:
9913 (SUBREG:SF (REG:SI)) and
9914 (SUBREG:SI (REG:SF))
9916 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9917 values are stored as DFmode values in the VSX registers. We need to convert
9918 the bits before we can use a direct move or operate on the bits in the
9919 vector register as an integer type.
9921 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9924 rs6000_emit_move_si_sf_subreg (rtx dest
, rtx source
, machine_mode mode
)
9926 if (TARGET_DIRECT_MOVE_64BIT
&& !reload_completed
9927 && (!SUBREG_P (dest
) || !sf_subreg_operand (dest
, mode
))
9928 && SUBREG_P (source
) && sf_subreg_operand (source
, mode
))
9930 rtx inner_source
= SUBREG_REG (source
);
9931 machine_mode inner_mode
= GET_MODE (inner_source
);
9933 if (mode
== SImode
&& inner_mode
== SFmode
)
9935 emit_insn (gen_movsi_from_sf (dest
, inner_source
));
9939 if (mode
== SFmode
&& inner_mode
== SImode
)
9941 emit_insn (gen_movsf_from_si (dest
, inner_source
));
9949 /* Emit a move from SOURCE to DEST in mode MODE. */
9951 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
9955 operands
[1] = source
;
9957 if (TARGET_DEBUG_ADDR
)
9960 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9961 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9962 GET_MODE_NAME (mode
),
9965 can_create_pseudo_p ());
9967 fprintf (stderr
, "source:\n");
9971 /* Check that we get CONST_WIDE_INT only when we should. */
9972 if (CONST_WIDE_INT_P (operands
[1])
9973 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9976 #ifdef HAVE_AS_GNU_ATTRIBUTE
9977 /* If we use a long double type, set the flags in .gnu_attribute that say
9978 what the long double type is. This is to allow the linker's warning
9979 message for the wrong long double to be useful, even if the function does
9980 not do a call (for example, doing a 128-bit add on power9 if the long
9981 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9982 used if they aren't the default long dobule type. */
9983 if (rs6000_gnu_attr
&& (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
))
9985 if (TARGET_LONG_DOUBLE_128
&& (mode
== TFmode
|| mode
== TCmode
))
9986 rs6000_passes_float
= rs6000_passes_long_double
= true;
9988 else if (!TARGET_LONG_DOUBLE_128
&& (mode
== DFmode
|| mode
== DCmode
))
9989 rs6000_passes_float
= rs6000_passes_long_double
= true;
9993 /* See if we need to special case SImode/SFmode SUBREG moves. */
9994 if ((mode
== SImode
|| mode
== SFmode
) && SUBREG_P (source
)
9995 && rs6000_emit_move_si_sf_subreg (dest
, source
, mode
))
9998 /* Check if GCC is setting up a block move that will end up using FP
9999 registers as temporaries. We must make sure this is acceptable. */
10000 if (MEM_P (operands
[0])
10001 && MEM_P (operands
[1])
10003 && (rs6000_slow_unaligned_access (DImode
, MEM_ALIGN (operands
[0]))
10004 || rs6000_slow_unaligned_access (DImode
, MEM_ALIGN (operands
[1])))
10005 && ! (rs6000_slow_unaligned_access (SImode
,
10006 (MEM_ALIGN (operands
[0]) > 32
10007 ? 32 : MEM_ALIGN (operands
[0])))
10008 || rs6000_slow_unaligned_access (SImode
,
10009 (MEM_ALIGN (operands
[1]) > 32
10010 ? 32 : MEM_ALIGN (operands
[1]))))
10011 && ! MEM_VOLATILE_P (operands
[0])
10012 && ! MEM_VOLATILE_P (operands
[1]))
10014 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
10015 adjust_address (operands
[1], SImode
, 0));
10016 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
10017 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
10021 if (can_create_pseudo_p () && MEM_P (operands
[0])
10022 && !gpc_reg_operand (operands
[1], mode
))
10023 operands
[1] = force_reg (mode
, operands
[1]);
10025 /* Recognize the case where operand[1] is a reference to thread-local
10026 data and load its address to a register. */
10027 if (tls_referenced_p (operands
[1]))
10029 enum tls_model model
;
10030 rtx tmp
= operands
[1];
10033 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
10035 addend
= XEXP (XEXP (tmp
, 0), 1);
10036 tmp
= XEXP (XEXP (tmp
, 0), 0);
10039 gcc_assert (SYMBOL_REF_P (tmp
));
10040 model
= SYMBOL_REF_TLS_MODEL (tmp
);
10041 gcc_assert (model
!= 0);
10043 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
10046 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
10047 tmp
= force_operand (tmp
, operands
[0]);
10052 /* 128-bit constant floating-point values on Darwin should really be loaded
10053 as two parts. However, this premature splitting is a problem when DFmode
10054 values can go into Altivec registers. */
10055 if (TARGET_MACHO
&& CONST_DOUBLE_P (operands
[1]) && FLOAT128_IBM_P (mode
)
10056 && !reg_addr
[DFmode
].scalar_in_vmx_p
)
10058 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
10059 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
10061 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
10062 GET_MODE_SIZE (DFmode
)),
10063 simplify_gen_subreg (DFmode
, operands
[1], mode
,
10064 GET_MODE_SIZE (DFmode
)),
10069 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10070 p1:SD) if p1 is not of floating point class and p0 is spilled as
10071 we can have no analogous movsd_store for this. */
10072 if (lra_in_progress
&& mode
== DDmode
10073 && REG_P (operands
[0]) && !HARD_REGISTER_P (operands
[0])
10074 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10075 && SUBREG_P (operands
[1]) && REG_P (SUBREG_REG (operands
[1]))
10076 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
10079 int regno
= REGNO (SUBREG_REG (operands
[1]));
10081 if (!HARD_REGISTER_NUM_P (regno
))
10083 cl
= reg_preferred_class (regno
);
10084 regno
= reg_renumber
[regno
];
10086 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
10088 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10091 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
10092 operands
[1] = SUBREG_REG (operands
[1]);
10095 if (lra_in_progress
10097 && REG_P (operands
[0]) && !HARD_REGISTER_P (operands
[0])
10098 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10099 && (REG_P (operands
[1])
10100 || (SUBREG_P (operands
[1]) && REG_P (SUBREG_REG (operands
[1])))))
10102 int regno
= reg_or_subregno (operands
[1]);
10105 if (!HARD_REGISTER_NUM_P (regno
))
10107 cl
= reg_preferred_class (regno
);
10108 gcc_assert (cl
!= NO_REGS
);
10109 regno
= reg_renumber
[regno
];
10111 regno
= ira_class_hard_regs
[cl
][0];
10113 if (FP_REGNO_P (regno
))
10115 if (GET_MODE (operands
[0]) != DDmode
)
10116 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
10117 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
10119 else if (INT_REGNO_P (regno
))
10120 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10125 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10126 p:DD)) if p0 is not of floating point class and p1 is spilled as
10127 we can have no analogous movsd_load for this. */
10128 if (lra_in_progress
&& mode
== DDmode
10129 && SUBREG_P (operands
[0]) && REG_P (SUBREG_REG (operands
[0]))
10130 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
10131 && REG_P (operands
[1]) && !HARD_REGISTER_P (operands
[1])
10132 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10135 int regno
= REGNO (SUBREG_REG (operands
[0]));
10137 if (!HARD_REGISTER_NUM_P (regno
))
10139 cl
= reg_preferred_class (regno
);
10140 regno
= reg_renumber
[regno
];
10142 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
10144 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10147 operands
[0] = SUBREG_REG (operands
[0]);
10148 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
10151 if (lra_in_progress
10153 && (REG_P (operands
[0])
10154 || (SUBREG_P (operands
[0]) && REG_P (SUBREG_REG (operands
[0]))))
10155 && REG_P (operands
[1]) && !HARD_REGISTER_P (operands
[1])
10156 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10158 int regno
= reg_or_subregno (operands
[0]);
10161 if (!HARD_REGISTER_NUM_P (regno
))
10163 cl
= reg_preferred_class (regno
);
10164 gcc_assert (cl
!= NO_REGS
);
10165 regno
= reg_renumber
[regno
];
10167 regno
= ira_class_hard_regs
[cl
][0];
10169 if (FP_REGNO_P (regno
))
10171 if (GET_MODE (operands
[1]) != DDmode
)
10172 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
10173 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
10175 else if (INT_REGNO_P (regno
))
10176 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10182 /* FIXME: In the long term, this switch statement should go away
10183 and be replaced by a sequence of tests based on things like
10189 if (CONSTANT_P (operands
[1])
10190 && !CONST_INT_P (operands
[1]))
10191 operands
[1] = force_const_mem (mode
, operands
[1]);
10198 if (FLOAT128_2REG_P (mode
))
10199 rs6000_eliminate_indexed_memrefs (operands
);
10206 if (CONSTANT_P (operands
[1])
10207 && ! easy_fp_constant (operands
[1], mode
))
10208 operands
[1] = force_const_mem (mode
, operands
[1]);
10218 if (CONSTANT_P (operands
[1])
10219 && !easy_vector_constant (operands
[1], mode
))
10220 operands
[1] = force_const_mem (mode
, operands
[1]);
10225 /* Use default pattern for address of ELF small data */
10228 && DEFAULT_ABI
== ABI_V4
10229 && (SYMBOL_REF_P (operands
[1])
10230 || GET_CODE (operands
[1]) == CONST
)
10231 && small_data_operand (operands
[1], mode
))
10233 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10237 if (DEFAULT_ABI
== ABI_V4
10238 && mode
== Pmode
&& mode
== SImode
10239 && flag_pic
== 1 && got_operand (operands
[1], mode
))
10241 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
10245 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
10249 && CONSTANT_P (operands
[1])
10250 && GET_CODE (operands
[1]) != HIGH
10251 && !CONST_INT_P (operands
[1]))
10253 rtx target
= (!can_create_pseudo_p ()
10255 : gen_reg_rtx (mode
));
10257 /* If this is a function address on -mcall-aixdesc,
10258 convert it to the address of the descriptor. */
10259 if (DEFAULT_ABI
== ABI_AIX
10260 && SYMBOL_REF_P (operands
[1])
10261 && XSTR (operands
[1], 0)[0] == '.')
10263 const char *name
= XSTR (operands
[1], 0);
10265 while (*name
== '.')
10267 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
10268 CONSTANT_POOL_ADDRESS_P (new_ref
)
10269 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
10270 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
10271 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
10272 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
10273 operands
[1] = new_ref
;
10276 if (DEFAULT_ABI
== ABI_DARWIN
)
10279 if (MACHO_DYNAMIC_NO_PIC_P
)
10281 /* Take care of any required data indirection. */
10282 operands
[1] = rs6000_machopic_legitimize_pic_address (
10283 operands
[1], mode
, operands
[0]);
10284 if (operands
[0] != operands
[1])
10285 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10289 emit_insn (gen_macho_high (target
, operands
[1]));
10290 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
10294 emit_insn (gen_elf_high (target
, operands
[1]));
10295 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
10299 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10300 and we have put it in the TOC, we just need to make a TOC-relative
10301 reference to it. */
10303 && SYMBOL_REF_P (operands
[1])
10304 && use_toc_relative_ref (operands
[1], mode
))
10305 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
10306 else if (mode
== Pmode
10307 && CONSTANT_P (operands
[1])
10308 && GET_CODE (operands
[1]) != HIGH
10309 && ((REG_P (operands
[0])
10310 && FP_REGNO_P (REGNO (operands
[0])))
10311 || !CONST_INT_P (operands
[1])
10312 || (num_insns_constant (operands
[1], mode
)
10313 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
10314 && !toc_relative_expr_p (operands
[1], false, NULL
, NULL
)
10315 && (TARGET_CMODEL
== CMODEL_SMALL
10316 || can_create_pseudo_p ()
10317 || (REG_P (operands
[0])
10318 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
10322 /* Darwin uses a special PIC legitimizer. */
10323 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
10326 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
10328 if (operands
[0] != operands
[1])
10329 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10334 /* If we are to limit the number of things we put in the TOC and
10335 this is a symbol plus a constant we can add in one insn,
10336 just put the symbol in the TOC and add the constant. */
10337 if (GET_CODE (operands
[1]) == CONST
10338 && TARGET_NO_SUM_IN_TOC
10339 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
10340 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
10341 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
10342 || SYMBOL_REF_P (XEXP (XEXP (operands
[1], 0), 0)))
10343 && ! side_effects_p (operands
[0]))
10346 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
10347 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
10349 sym
= force_reg (mode
, sym
);
10350 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
10354 operands
[1] = force_const_mem (mode
, operands
[1]);
10357 && SYMBOL_REF_P (XEXP (operands
[1], 0))
10358 && use_toc_relative_ref (XEXP (operands
[1], 0), mode
))
10360 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
10362 operands
[1] = gen_const_mem (mode
, tocref
);
10363 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
10369 if (!VECTOR_MEM_VSX_P (TImode
))
10370 rs6000_eliminate_indexed_memrefs (operands
);
10374 rs6000_eliminate_indexed_memrefs (operands
);
10378 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
10381 /* Above, we may have called force_const_mem which may have returned
10382 an invalid address. If we can, fix this up; otherwise, reload will
10383 have to deal with it. */
10384 if (MEM_P (operands
[1]))
10385 operands
[1] = validize_mem (operands
[1]);
10387 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10390 /* Nonzero if we can use a floating-point register to pass this arg. */
10391 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10392 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10393 && (CUM)->fregno <= FP_ARG_MAX_REG \
10394 && TARGET_HARD_FLOAT)
10396 /* Nonzero if we can use an AltiVec register to pass this arg. */
10397 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10398 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10399 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10400 && TARGET_ALTIVEC_ABI \
10403 /* Walk down the type tree of TYPE counting consecutive base elements.
10404 If *MODEP is VOIDmode, then set it to the first valid floating point
10405 or vector type. If a non-floating point or vector type is found, or
10406 if a floating point or vector type that doesn't match a non-VOIDmode
10407 *MODEP is found, then return -1, otherwise return the count in the
10411 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
10414 HOST_WIDE_INT size
;
10416 switch (TREE_CODE (type
))
10419 mode
= TYPE_MODE (type
);
10420 if (!SCALAR_FLOAT_MODE_P (mode
))
10423 if (*modep
== VOIDmode
)
10426 if (*modep
== mode
)
10432 mode
= TYPE_MODE (TREE_TYPE (type
));
10433 if (!SCALAR_FLOAT_MODE_P (mode
))
10436 if (*modep
== VOIDmode
)
10439 if (*modep
== mode
)
10445 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
10448 /* Use V4SImode as representative of all 128-bit vector types. */
10449 size
= int_size_in_bytes (type
);
10459 if (*modep
== VOIDmode
)
10462 /* Vector modes are considered to be opaque: two vectors are
10463 equivalent for the purposes of being homogeneous aggregates
10464 if they are the same size. */
10465 if (*modep
== mode
)
10473 tree index
= TYPE_DOMAIN (type
);
10475 /* Can't handle incomplete types nor sizes that are not
10477 if (!COMPLETE_TYPE_P (type
)
10478 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10481 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
10484 || !TYPE_MAX_VALUE (index
)
10485 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
10486 || !TYPE_MIN_VALUE (index
)
10487 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
10491 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
10492 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
10494 /* There must be no padding. */
10495 if (wi::to_wide (TYPE_SIZE (type
))
10496 != count
* GET_MODE_BITSIZE (*modep
))
10508 /* Can't handle incomplete types nor sizes that are not
10510 if (!COMPLETE_TYPE_P (type
)
10511 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10514 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10516 if (TREE_CODE (field
) != FIELD_DECL
)
10519 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10522 count
+= sub_count
;
10525 /* There must be no padding. */
10526 if (wi::to_wide (TYPE_SIZE (type
))
10527 != count
* GET_MODE_BITSIZE (*modep
))
10534 case QUAL_UNION_TYPE
:
10536 /* These aren't very interesting except in a degenerate case. */
10541 /* Can't handle incomplete types nor sizes that are not
10543 if (!COMPLETE_TYPE_P (type
)
10544 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10547 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10549 if (TREE_CODE (field
) != FIELD_DECL
)
10552 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10555 count
= count
> sub_count
? count
: sub_count
;
10558 /* There must be no padding. */
10559 if (wi::to_wide (TYPE_SIZE (type
))
10560 != count
* GET_MODE_BITSIZE (*modep
))
10573 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10574 float or vector aggregate that shall be passed in FP/vector registers
10575 according to the ELFv2 ABI, return the homogeneous element mode in
10576 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10578 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10581 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
10582 machine_mode
*elt_mode
,
10585 /* Note that we do not accept complex types at the top level as
10586 homogeneous aggregates; these types are handled via the
10587 targetm.calls.split_complex_arg mechanism. Complex types
10588 can be elements of homogeneous aggregates, however. */
10589 if (TARGET_HARD_FLOAT
&& DEFAULT_ABI
== ABI_ELFv2
&& type
10590 && AGGREGATE_TYPE_P (type
))
10592 machine_mode field_mode
= VOIDmode
;
10593 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
10595 if (field_count
> 0)
10597 int reg_size
= ALTIVEC_OR_VSX_VECTOR_MODE (field_mode
) ? 16 : 8;
10598 int field_size
= ROUND_UP (GET_MODE_SIZE (field_mode
), reg_size
);
10600 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10601 up to AGGR_ARG_NUM_REG registers. */
10602 if (field_count
* field_size
<= AGGR_ARG_NUM_REG
* reg_size
)
10605 *elt_mode
= field_mode
;
10607 *n_elts
= field_count
;
10620 /* Return a nonzero value to say to return the function value in
10621 memory, just as large structures are always returned. TYPE will be
10622 the data type of the value, and FNTYPE will be the type of the
10623 function doing the returning, or @code{NULL} for libcalls.
10625 The AIX ABI for the RS/6000 specifies that all structures are
10626 returned in memory. The Darwin ABI does the same.
10628 For the Darwin 64 Bit ABI, a function result can be returned in
10629 registers or in memory, depending on the size of the return data
10630 type. If it is returned in registers, the value occupies the same
10631 registers as it would if it were the first and only function
10632 argument. Otherwise, the function places its result in memory at
10633 the location pointed to by GPR3.
10635 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10636 but a draft put them in memory, and GCC used to implement the draft
10637 instead of the final standard. Therefore, aix_struct_return
10638 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10639 compatibility can change DRAFT_V4_STRUCT_RET to override the
10640 default, and -m switches get the final word. See
10641 rs6000_option_override_internal for more details.
10643 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10644 long double support is enabled. These values are returned in memory.
10646 int_size_in_bytes returns -1 for variable size objects, which go in
10647 memory always. The cast to unsigned makes -1 > 8. */
10650 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
10652 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10654 && rs6000_darwin64_abi
10655 && TREE_CODE (type
) == RECORD_TYPE
10656 && int_size_in_bytes (type
) > 0)
10658 CUMULATIVE_ARGS valcum
;
10662 valcum
.fregno
= FP_ARG_MIN_REG
;
10663 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
10664 /* Do a trial code generation as if this were going to be passed
10665 as an argument; if any part goes in memory, we return NULL. */
10666 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
10669 /* Otherwise fall through to more conventional ABI rules. */
10672 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10673 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
10677 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10678 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
10679 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
10682 if (AGGREGATE_TYPE_P (type
)
10683 && (aix_struct_return
10684 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
10687 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10688 modes only exist for GCC vector types if -maltivec. */
10689 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
10690 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10693 /* Return synthetic vectors in memory. */
10694 if (TREE_CODE (type
) == VECTOR_TYPE
10695 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10697 static bool warned_for_return_big_vectors
= false;
10698 if (!warned_for_return_big_vectors
)
10700 warning (OPT_Wpsabi
, "GCC vector returned by reference: "
10701 "non-standard ABI extension with no compatibility "
10703 warned_for_return_big_vectors
= true;
10708 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
10709 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
10715 /* Specify whether values returned in registers should be at the most
10716 significant end of a register. We want aggregates returned by
10717 value to match the way aggregates are passed to functions. */
10720 rs6000_return_in_msb (const_tree valtype
)
10722 return (DEFAULT_ABI
== ABI_ELFv2
10723 && BYTES_BIG_ENDIAN
10724 && AGGREGATE_TYPE_P (valtype
)
10725 && (rs6000_function_arg_padding (TYPE_MODE (valtype
), valtype
)
10729 #ifdef HAVE_AS_GNU_ATTRIBUTE
10730 /* Return TRUE if a call to function FNDECL may be one that
10731 potentially affects the function calling ABI of the object file. */
10734 call_ABI_of_interest (tree fndecl
)
10736 if (rs6000_gnu_attr
&& symtab
->state
== EXPANSION
)
10738 struct cgraph_node
*c_node
;
10740 /* Libcalls are always interesting. */
10741 if (fndecl
== NULL_TREE
)
10744 /* Any call to an external function is interesting. */
10745 if (DECL_EXTERNAL (fndecl
))
10748 /* Interesting functions that we are emitting in this object file. */
10749 c_node
= cgraph_node::get (fndecl
);
10750 c_node
= c_node
->ultimate_alias_target ();
10751 return !c_node
->only_called_directly_p ();
10757 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10758 for a call to a function whose data type is FNTYPE.
10759 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10761 For incoming args we set the number of arguments in the prototype large
10762 so we never return a PARALLEL. */
10765 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
10766 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
10767 int libcall
, int n_named_args
,
10769 machine_mode return_mode ATTRIBUTE_UNUSED
)
10771 static CUMULATIVE_ARGS zero_cumulative
;
10773 *cum
= zero_cumulative
;
10775 cum
->fregno
= FP_ARG_MIN_REG
;
10776 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
10777 cum
->prototype
= (fntype
&& prototype_p (fntype
));
10778 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
10779 ? CALL_LIBCALL
: CALL_NORMAL
);
10780 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
10781 cum
->stdarg
= stdarg_p (fntype
);
10782 cum
->libcall
= libcall
;
10784 cum
->nargs_prototype
= 0;
10785 if (incoming
|| cum
->prototype
)
10786 cum
->nargs_prototype
= n_named_args
;
10788 /* Check for a longcall attribute. */
10789 if ((!fntype
&& rs6000_default_long_calls
)
10791 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
10792 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
10793 cum
->call_cookie
|= CALL_LONG
;
10794 else if (DEFAULT_ABI
!= ABI_DARWIN
)
10796 bool is_local
= (fndecl
10797 && !DECL_EXTERNAL (fndecl
)
10798 && !DECL_WEAK (fndecl
)
10799 && (*targetm
.binds_local_p
) (fndecl
));
10805 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype
)))
10806 cum
->call_cookie
|= CALL_LONG
;
10811 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype
))))
10812 cum
->call_cookie
|= CALL_LONG
;
10816 if (TARGET_DEBUG_ARG
)
10818 fprintf (stderr
, "\ninit_cumulative_args:");
10821 tree ret_type
= TREE_TYPE (fntype
);
10822 fprintf (stderr
, " ret code = %s,",
10823 get_tree_code_name (TREE_CODE (ret_type
)));
10826 if (cum
->call_cookie
& CALL_LONG
)
10827 fprintf (stderr
, " longcall,");
10829 fprintf (stderr
, " proto = %d, nargs = %d\n",
10830 cum
->prototype
, cum
->nargs_prototype
);
10833 #ifdef HAVE_AS_GNU_ATTRIBUTE
10834 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
))
10836 cum
->escapes
= call_ABI_of_interest (fndecl
);
10843 return_type
= TREE_TYPE (fntype
);
10844 return_mode
= TYPE_MODE (return_type
);
10847 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
10849 if (return_type
!= NULL
)
10851 if (TREE_CODE (return_type
) == RECORD_TYPE
10852 && TYPE_TRANSPARENT_AGGR (return_type
))
10854 return_type
= TREE_TYPE (first_field (return_type
));
10855 return_mode
= TYPE_MODE (return_type
);
10857 if (AGGREGATE_TYPE_P (return_type
)
10858 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
10860 rs6000_returns_struct
= true;
10862 if (SCALAR_FLOAT_MODE_P (return_mode
))
10864 rs6000_passes_float
= true;
10865 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
10866 && (FLOAT128_IBM_P (return_mode
)
10867 || FLOAT128_IEEE_P (return_mode
)
10868 || (return_type
!= NULL
10869 && (TYPE_MAIN_VARIANT (return_type
)
10870 == long_double_type_node
))))
10871 rs6000_passes_long_double
= true;
10873 /* Note if we passed or return a IEEE 128-bit type. We changed
10874 the mangling for these types, and we may need to make an alias
10875 with the old mangling. */
10876 if (FLOAT128_IEEE_P (return_mode
))
10877 rs6000_passes_ieee128
= true;
10879 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
))
10880 rs6000_passes_vector
= true;
10887 && TARGET_ALTIVEC_ABI
10888 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
10890 error ("cannot return value in vector register because"
10891 " altivec instructions are disabled, use %qs"
10892 " to enable them", "-maltivec");
10896 /* The mode the ABI uses for a word. This is not the same as word_mode
10897 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10899 static scalar_int_mode
10900 rs6000_abi_word_mode (void)
10902 return TARGET_32BIT
? SImode
: DImode
;
10905 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10907 rs6000_offload_options (void)
10910 return xstrdup ("-foffload-abi=lp64");
10912 return xstrdup ("-foffload-abi=ilp32");
10915 /* On rs6000, function arguments are promoted, as are function return
10918 static machine_mode
10919 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
10921 int *punsignedp ATTRIBUTE_UNUSED
,
10924 PROMOTE_MODE (mode
, *punsignedp
, type
);
10929 /* Return true if TYPE must be passed on the stack and not in registers. */
10932 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
10934 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
10935 return must_pass_in_stack_var_size (mode
, type
);
10937 return must_pass_in_stack_var_size_or_pad (mode
, type
);
10941 is_complex_IBM_long_double (machine_mode mode
)
10943 return mode
== ICmode
|| (mode
== TCmode
&& FLOAT128_IBM_P (TCmode
));
10946 /* Whether ABI_V4 passes MODE args to a function in floating point
10950 abi_v4_pass_in_fpr (machine_mode mode
, bool named
)
10952 if (!TARGET_HARD_FLOAT
)
10954 if (mode
== DFmode
)
10956 if (mode
== SFmode
&& named
)
10958 /* ABI_V4 passes complex IBM long double in 8 gprs.
10959 Stupid, but we can't change the ABI now. */
10960 if (is_complex_IBM_long_double (mode
))
10962 if (FLOAT128_2REG_P (mode
))
10964 if (DECIMAL_FLOAT_MODE_P (mode
))
10969 /* Implement TARGET_FUNCTION_ARG_PADDING.
10971 For the AIX ABI structs are always stored left shifted in their
10974 static pad_direction
10975 rs6000_function_arg_padding (machine_mode mode
, const_tree type
)
10977 #ifndef AGGREGATE_PADDING_FIXED
10978 #define AGGREGATE_PADDING_FIXED 0
10980 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10981 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10984 if (!AGGREGATE_PADDING_FIXED
)
10986 /* GCC used to pass structures of the same size as integer types as
10987 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10988 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10989 passed padded downward, except that -mstrict-align further
10990 muddied the water in that multi-component structures of 2 and 4
10991 bytes in size were passed padded upward.
10993 The following arranges for best compatibility with previous
10994 versions of gcc, but removes the -mstrict-align dependency. */
10995 if (BYTES_BIG_ENDIAN
)
10997 HOST_WIDE_INT size
= 0;
10999 if (mode
== BLKmode
)
11001 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
11002 size
= int_size_in_bytes (type
);
11005 size
= GET_MODE_SIZE (mode
);
11007 if (size
== 1 || size
== 2 || size
== 4)
11008 return PAD_DOWNWARD
;
11013 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
11015 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
11019 /* Fall back to the default. */
11020 return default_function_arg_padding (mode
, type
);
11023 /* If defined, a C expression that gives the alignment boundary, in bits,
11024 of an argument with the specified mode and type. If it is not defined,
11025 PARM_BOUNDARY is used for all arguments.
11027 V.4 wants long longs and doubles to be double word aligned. Just
11028 testing the mode size is a boneheaded way to do this as it means
11029 that other types such as complex int are also double word aligned.
11030 However, we're stuck with this because changing the ABI might break
11031 existing library interfaces.
11033 Quadword align Altivec/VSX vectors.
11034 Quadword align large synthetic vector types. */
11036 static unsigned int
11037 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
11039 machine_mode elt_mode
;
11042 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11044 if (DEFAULT_ABI
== ABI_V4
11045 && (GET_MODE_SIZE (mode
) == 8
11046 || (TARGET_HARD_FLOAT
11047 && !is_complex_IBM_long_double (mode
)
11048 && FLOAT128_2REG_P (mode
))))
11050 else if (FLOAT128_VECTOR_P (mode
))
11052 else if (type
&& TREE_CODE (type
) == VECTOR_TYPE
11053 && int_size_in_bytes (type
) >= 8
11054 && int_size_in_bytes (type
) < 16)
11056 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11057 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11058 && int_size_in_bytes (type
) >= 16))
11061 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11062 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11063 -mcompat-align-parm is used. */
11064 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
11065 || DEFAULT_ABI
== ABI_ELFv2
)
11066 && type
&& TYPE_ALIGN (type
) > 64)
11068 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11069 or homogeneous float/vector aggregates here. We already handled
11070 vector aggregates above, but still need to check for float here. */
11071 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
11072 && !SCALAR_FLOAT_MODE_P (elt_mode
));
11074 /* We used to check for BLKmode instead of the above aggregate type
11075 check. Warn when this results in any difference to the ABI. */
11076 if (aggregate_p
!= (mode
== BLKmode
))
11078 static bool warned
;
11079 if (!warned
&& warn_psabi
)
11082 inform (input_location
,
11083 "the ABI of passing aggregates with %d-byte alignment"
11084 " has changed in GCC 5",
11085 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
11093 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11094 implement the "aggregate type" check as a BLKmode check here; this
11095 means certain aggregate types are in fact not aligned. */
11096 if (TARGET_MACHO
&& rs6000_darwin64_abi
11098 && type
&& TYPE_ALIGN (type
) > 64)
11101 return PARM_BOUNDARY
;
11104 /* The offset in words to the start of the parameter save area. */
11106 static unsigned int
11107 rs6000_parm_offset (void)
11109 return (DEFAULT_ABI
== ABI_V4
? 2
11110 : DEFAULT_ABI
== ABI_ELFv2
? 4
11114 /* For a function parm of MODE and TYPE, return the starting word in
11115 the parameter area. NWORDS of the parameter area are already used. */
11117 static unsigned int
11118 rs6000_parm_start (machine_mode mode
, const_tree type
,
11119 unsigned int nwords
)
11121 unsigned int align
;
11123 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
11124 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
11127 /* Compute the size (in words) of a function argument. */
11129 static unsigned long
11130 rs6000_arg_size (machine_mode mode
, const_tree type
)
11132 unsigned long size
;
11134 if (mode
!= BLKmode
)
11135 size
= GET_MODE_SIZE (mode
);
11137 size
= int_size_in_bytes (type
);
11140 return (size
+ 3) >> 2;
11142 return (size
+ 7) >> 3;
11145 /* Use this to flush pending int fields. */
11148 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
11149 HOST_WIDE_INT bitpos
, int final
)
11151 unsigned int startbit
, endbit
;
11152 int intregs
, intoffset
;
11154 /* Handle the situations where a float is taking up the first half
11155 of the GPR, and the other half is empty (typically due to
11156 alignment restrictions). We can detect this by a 8-byte-aligned
11157 int field, or by seeing that this is the final flush for this
11158 argument. Count the word and continue on. */
11159 if (cum
->floats_in_gpr
== 1
11160 && (cum
->intoffset
% 64 == 0
11161 || (cum
->intoffset
== -1 && final
)))
11164 cum
->floats_in_gpr
= 0;
11167 if (cum
->intoffset
== -1)
11170 intoffset
= cum
->intoffset
;
11171 cum
->intoffset
= -1;
11172 cum
->floats_in_gpr
= 0;
11174 if (intoffset
% BITS_PER_WORD
!= 0)
11176 unsigned int bits
= BITS_PER_WORD
- intoffset
% BITS_PER_WORD
;
11177 if (!int_mode_for_size (bits
, 0).exists ())
11179 /* We couldn't find an appropriate mode, which happens,
11180 e.g., in packed structs when there are 3 bytes to load.
11181 Back intoffset back to the beginning of the word in this
11183 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11187 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11188 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11189 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11190 cum
->words
+= intregs
;
11191 /* words should be unsigned. */
11192 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
11194 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
11199 /* The darwin64 ABI calls for us to recurse down through structs,
11200 looking for elements passed in registers. Unfortunately, we have
11201 to track int register count here also because of misalignments
11202 in powerpc alignment mode. */
11205 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
11207 HOST_WIDE_INT startbitpos
)
11211 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11212 if (TREE_CODE (f
) == FIELD_DECL
)
11214 HOST_WIDE_INT bitpos
= startbitpos
;
11215 tree ftype
= TREE_TYPE (f
);
11217 if (ftype
== error_mark_node
)
11219 mode
= TYPE_MODE (ftype
);
11221 if (DECL_SIZE (f
) != 0
11222 && tree_fits_uhwi_p (bit_position (f
)))
11223 bitpos
+= int_bit_position (f
);
11225 /* ??? FIXME: else assume zero offset. */
11227 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11228 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
11229 else if (USE_FP_FOR_ARG_P (cum
, mode
))
11231 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11232 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11233 cum
->fregno
+= n_fpregs
;
11234 /* Single-precision floats present a special problem for
11235 us, because they are smaller than an 8-byte GPR, and so
11236 the structure-packing rules combined with the standard
11237 varargs behavior mean that we want to pack float/float
11238 and float/int combinations into a single register's
11239 space. This is complicated by the arg advance flushing,
11240 which works on arbitrarily large groups of int-type
11242 if (mode
== SFmode
)
11244 if (cum
->floats_in_gpr
== 1)
11246 /* Two floats in a word; count the word and reset
11247 the float count. */
11249 cum
->floats_in_gpr
= 0;
11251 else if (bitpos
% 64 == 0)
11253 /* A float at the beginning of an 8-byte word;
11254 count it and put off adjusting cum->words until
11255 we see if a arg advance flush is going to do it
11257 cum
->floats_in_gpr
++;
11261 /* The float is at the end of a word, preceded
11262 by integer fields, so the arg advance flush
11263 just above has already set cum->words and
11264 everything is taken care of. */
11268 cum
->words
+= n_fpregs
;
11270 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11272 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11276 else if (cum
->intoffset
== -1)
11277 cum
->intoffset
= bitpos
;
11281 /* Check for an item that needs to be considered specially under the darwin 64
11282 bit ABI. These are record types where the mode is BLK or the structure is
11283 8 bytes in size. */
11285 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
11287 return rs6000_darwin64_abi
11288 && ((mode
== BLKmode
11289 && TREE_CODE (type
) == RECORD_TYPE
11290 && int_size_in_bytes (type
) > 0)
11291 || (type
&& TREE_CODE (type
) == RECORD_TYPE
11292 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
11295 /* Update the data in CUM to advance over an argument
11296 of mode MODE and data type TYPE.
11297 (TYPE is null for libcalls where that information may not be available.)
11299 Note that for args passed by reference, function_arg will be called
11300 with MODE and TYPE set to that of the pointer to the arg, not the arg
11304 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
11305 const_tree type
, bool named
, int depth
)
11307 machine_mode elt_mode
;
11310 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11312 /* Only tick off an argument if we're not recursing. */
11314 cum
->nargs_prototype
--;
11316 #ifdef HAVE_AS_GNU_ATTRIBUTE
11317 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
11320 if (SCALAR_FLOAT_MODE_P (mode
))
11322 rs6000_passes_float
= true;
11323 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
11324 && (FLOAT128_IBM_P (mode
)
11325 || FLOAT128_IEEE_P (mode
)
11327 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
)))
11328 rs6000_passes_long_double
= true;
11330 /* Note if we passed or return a IEEE 128-bit type. We changed the
11331 mangling for these types, and we may need to make an alias with
11332 the old mangling. */
11333 if (FLOAT128_IEEE_P (mode
))
11334 rs6000_passes_ieee128
= true;
11336 if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
11337 rs6000_passes_vector
= true;
11341 if (TARGET_ALTIVEC_ABI
11342 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11343 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11344 && int_size_in_bytes (type
) == 16)))
11346 bool stack
= false;
11348 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11350 cum
->vregno
+= n_elts
;
11352 if (!TARGET_ALTIVEC
)
11353 error ("cannot pass argument in vector register because"
11354 " altivec instructions are disabled, use %qs"
11355 " to enable them", "-maltivec");
11357 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11358 even if it is going to be passed in a vector register.
11359 Darwin does the same for variable-argument functions. */
11360 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11362 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
11372 /* Vector parameters must be 16-byte aligned. In 32-bit
11373 mode this means we need to take into account the offset
11374 to the parameter save area. In 64-bit mode, they just
11375 have to start on an even word, since the parameter save
11376 area is 16-byte aligned. */
11378 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11380 align
= cum
->words
& 1;
11381 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
11383 if (TARGET_DEBUG_ARG
)
11385 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
11386 cum
->words
, align
);
11387 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
11388 cum
->nargs_prototype
, cum
->prototype
,
11389 GET_MODE_NAME (mode
));
11393 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11395 int size
= int_size_in_bytes (type
);
11396 /* Variable sized types have size == -1 and are
11397 treated as if consisting entirely of ints.
11398 Pad to 16 byte boundary if needed. */
11399 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11400 && (cum
->words
% 2) != 0)
11402 /* For varargs, we can just go up by the size of the struct. */
11404 cum
->words
+= (size
+ 7) / 8;
11407 /* It is tempting to say int register count just goes up by
11408 sizeof(type)/8, but this is wrong in a case such as
11409 { int; double; int; } [powerpc alignment]. We have to
11410 grovel through the fields for these too. */
11411 cum
->intoffset
= 0;
11412 cum
->floats_in_gpr
= 0;
11413 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
11414 rs6000_darwin64_record_arg_advance_flush (cum
,
11415 size
* BITS_PER_UNIT
, 1);
11417 if (TARGET_DEBUG_ARG
)
11419 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
11420 cum
->words
, TYPE_ALIGN (type
), size
);
11422 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11423 cum
->nargs_prototype
, cum
->prototype
,
11424 GET_MODE_NAME (mode
));
11427 else if (DEFAULT_ABI
== ABI_V4
)
11429 if (abi_v4_pass_in_fpr (mode
, named
))
11431 /* _Decimal128 must use an even/odd register pair. This assumes
11432 that the register number is odd when fregno is odd. */
11433 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11436 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11437 <= FP_ARG_V4_MAX_REG
)
11438 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
11441 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
11442 if (mode
== DFmode
|| FLOAT128_IBM_P (mode
)
11443 || mode
== DDmode
|| mode
== TDmode
)
11444 cum
->words
+= cum
->words
& 1;
11445 cum
->words
+= rs6000_arg_size (mode
, type
);
11450 int n_words
= rs6000_arg_size (mode
, type
);
11451 int gregno
= cum
->sysv_gregno
;
11453 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11454 As does any other 2 word item such as complex int due to a
11455 historical mistake. */
11457 gregno
+= (1 - gregno
) & 1;
11459 /* Multi-reg args are not split between registers and stack. */
11460 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11462 /* Long long is aligned on the stack. So are other 2 word
11463 items such as complex int due to a historical mistake. */
11465 cum
->words
+= cum
->words
& 1;
11466 cum
->words
+= n_words
;
11469 /* Note: continuing to accumulate gregno past when we've started
11470 spilling to the stack indicates the fact that we've started
11471 spilling to the stack to expand_builtin_saveregs. */
11472 cum
->sysv_gregno
= gregno
+ n_words
;
11475 if (TARGET_DEBUG_ARG
)
11477 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11478 cum
->words
, cum
->fregno
);
11479 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
11480 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
11481 fprintf (stderr
, "mode = %4s, named = %d\n",
11482 GET_MODE_NAME (mode
), named
);
11487 int n_words
= rs6000_arg_size (mode
, type
);
11488 int start_words
= cum
->words
;
11489 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
11491 cum
->words
= align_words
+ n_words
;
11493 if (SCALAR_FLOAT_MODE_P (elt_mode
) && TARGET_HARD_FLOAT
)
11495 /* _Decimal128 must be passed in an even/odd float register pair.
11496 This assumes that the register number is odd when fregno is
11498 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11500 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
11503 if (TARGET_DEBUG_ARG
)
11505 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11506 cum
->words
, cum
->fregno
);
11507 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
11508 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
11509 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
11510 named
, align_words
- start_words
, depth
);
11516 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
11517 const_tree type
, bool named
)
11519 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
11523 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11524 structure between cum->intoffset and bitpos to integer registers. */
11527 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
11528 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
11531 unsigned int regno
;
11532 unsigned int startbit
, endbit
;
11533 int this_regno
, intregs
, intoffset
;
11536 if (cum
->intoffset
== -1)
11539 intoffset
= cum
->intoffset
;
11540 cum
->intoffset
= -1;
11542 /* If this is the trailing part of a word, try to only load that
11543 much into the register. Otherwise load the whole register. Note
11544 that in the latter case we may pick up unwanted bits. It's not a
11545 problem at the moment but may wish to revisit. */
11547 if (intoffset
% BITS_PER_WORD
!= 0)
11549 unsigned int bits
= BITS_PER_WORD
- intoffset
% BITS_PER_WORD
;
11550 if (!int_mode_for_size (bits
, 0).exists (&mode
))
11552 /* We couldn't find an appropriate mode, which happens,
11553 e.g., in packed structs when there are 3 bytes to load.
11554 Back intoffset back to the beginning of the word in this
11556 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11563 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11564 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11565 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11566 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
11568 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
11569 cum
->use_stack
= 1;
11571 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
11575 intoffset
/= BITS_PER_UNIT
;
11578 regno
= GP_ARG_MIN_REG
+ this_regno
;
11579 reg
= gen_rtx_REG (mode
, regno
);
11581 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
11584 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
11588 while (intregs
> 0);
11591 /* Recursive workhorse for the following. */
11594 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
11595 HOST_WIDE_INT startbitpos
, rtx rvec
[],
11600 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11601 if (TREE_CODE (f
) == FIELD_DECL
)
11603 HOST_WIDE_INT bitpos
= startbitpos
;
11604 tree ftype
= TREE_TYPE (f
);
11606 if (ftype
== error_mark_node
)
11608 mode
= TYPE_MODE (ftype
);
11610 if (DECL_SIZE (f
) != 0
11611 && tree_fits_uhwi_p (bit_position (f
)))
11612 bitpos
+= int_bit_position (f
);
11614 /* ??? FIXME: else assume zero offset. */
11616 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11617 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
11618 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
11620 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11624 case E_SCmode
: mode
= SFmode
; break;
11625 case E_DCmode
: mode
= DFmode
; break;
11626 case E_TCmode
: mode
= TFmode
; break;
11630 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
11631 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
11633 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
11634 && (mode
== TFmode
|| mode
== TDmode
));
11635 /* Long double or _Decimal128 split over regs and memory. */
11636 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
11640 = gen_rtx_EXPR_LIST (VOIDmode
,
11641 gen_rtx_REG (mode
, cum
->fregno
++),
11642 GEN_INT (bitpos
/ BITS_PER_UNIT
));
11643 if (FLOAT128_2REG_P (mode
))
11646 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11648 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
11650 = gen_rtx_EXPR_LIST (VOIDmode
,
11651 gen_rtx_REG (mode
, cum
->vregno
++),
11652 GEN_INT (bitpos
/ BITS_PER_UNIT
));
11654 else if (cum
->intoffset
== -1)
11655 cum
->intoffset
= bitpos
;
11659 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11660 the register(s) to be used for each field and subfield of a struct
11661 being passed by value, along with the offset of where the
11662 register's value may be found in the block. FP fields go in FP
11663 register, vector fields go in vector registers, and everything
11664 else goes in int registers, packed as in memory.
11666 This code is also used for function return values. RETVAL indicates
11667 whether this is the case.
11669 Much of this is taken from the SPARC V9 port, which has a similar
11670 calling convention. */
11673 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
11674 bool named
, bool retval
)
11676 rtx rvec
[FIRST_PSEUDO_REGISTER
];
11677 int k
= 1, kbase
= 1;
11678 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
11679 /* This is a copy; modifications are not visible to our caller. */
11680 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
11681 CUMULATIVE_ARGS
*cum
= ©_cum
;
11683 /* Pad to 16 byte boundary if needed. */
11684 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11685 && (cum
->words
% 2) != 0)
11688 cum
->intoffset
= 0;
11689 cum
->use_stack
= 0;
11690 cum
->named
= named
;
11692 /* Put entries into rvec[] for individual FP and vector fields, and
11693 for the chunks of memory that go in int regs. Note we start at
11694 element 1; 0 is reserved for an indication of using memory, and
11695 may or may not be filled in below. */
11696 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
11697 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
11699 /* If any part of the struct went on the stack put all of it there.
11700 This hack is because the generic code for
11701 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11702 parts of the struct are not at the beginning. */
11703 if (cum
->use_stack
)
11706 return NULL_RTX
; /* doesn't go in registers at all */
11708 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11710 if (k
> 1 || cum
->use_stack
)
11711 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
11716 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11719 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
11724 rtx rvec
[GP_ARG_NUM_REG
+ 1];
11726 if (align_words
>= GP_ARG_NUM_REG
)
11729 n_units
= rs6000_arg_size (mode
, type
);
11731 /* Optimize the simple case where the arg fits in one gpr, except in
11732 the case of BLKmode due to assign_parms assuming that registers are
11733 BITS_PER_WORD wide. */
11735 || (n_units
== 1 && mode
!= BLKmode
))
11736 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
11739 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
11740 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11741 using a magic NULL_RTX component.
11742 This is not strictly correct. Only some of the arg belongs in
11743 memory, not all of it. However, the normal scheme using
11744 function_arg_partial_nregs can result in unusual subregs, eg.
11745 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11746 store the whole arg to memory is often more efficient than code
11747 to store pieces, and we know that space is available in the right
11748 place for the whole arg. */
11749 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11754 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
11755 rtx off
= GEN_INT (i
++ * 4);
11756 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11758 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
11760 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
11763 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11764 but must also be copied into the parameter save area starting at
11765 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11766 to the GPRs and/or memory. Return the number of elements used. */
11769 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
11770 int align_words
, rtx
*rvec
)
11774 if (align_words
< GP_ARG_NUM_REG
)
11776 int n_words
= rs6000_arg_size (mode
, type
);
11778 if (align_words
+ n_words
> GP_ARG_NUM_REG
11780 || (TARGET_32BIT
&& TARGET_POWERPC64
))
11782 /* If this is partially on the stack, then we only
11783 include the portion actually in registers here. */
11784 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
11787 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
11789 /* Not all of the arg fits in gprs. Say that it goes in memory
11790 too, using a magic NULL_RTX component. Also see comment in
11791 rs6000_mixed_function_arg for why the normal
11792 function_arg_partial_nregs scheme doesn't work in this case. */
11793 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11798 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
11799 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
11800 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11802 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
11806 /* The whole arg fits in gprs. */
11807 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
11808 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
11813 /* It's entirely in memory. */
11814 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
11820 /* RVEC is a vector of K components of an argument of mode MODE.
11821 Construct the final function_arg return value from it. */
11824 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
11826 gcc_assert (k
>= 1);
11828 /* Avoid returning a PARALLEL in the trivial cases. */
11831 if (XEXP (rvec
[0], 0) == NULL_RTX
)
11834 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
11835 return XEXP (rvec
[0], 0);
11838 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
11841 /* Determine where to put an argument to a function.
11842 Value is zero to push the argument on the stack,
11843 or a hard register in which to store the argument.
11845 MODE is the argument's machine mode.
11846 TYPE is the data type of the argument (as a tree).
11847 This is null for libcalls where that information may
11849 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11850 the preceding args and about the function being called. It is
11851 not modified in this routine.
11852 NAMED is nonzero if this argument is a named parameter
11853 (otherwise it is an extra parameter matching an ellipsis).
11855 On RS/6000 the first eight words of non-FP are normally in registers
11856 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11857 Under V.4, the first 8 FP args are in registers.
11859 If this is floating-point and no prototype is specified, we use
11860 both an FP and integer register (or possibly FP reg and stack). Library
11861 functions (when CALL_LIBCALL is set) always have the proper types for args,
11862 so we can pass the FP value just in one register. emit_library_function
11863 doesn't support PARALLEL anyway.
11865 Note that for args passed by reference, function_arg will be called
11866 with MODE and TYPE set to that of the pointer to the arg, not the arg
11870 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
11871 const_tree type
, bool named
)
11873 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11874 enum rs6000_abi abi
= DEFAULT_ABI
;
11875 machine_mode elt_mode
;
11878 /* Return a marker to indicate whether CR1 needs to set or clear the
11879 bit that V.4 uses to say fp args were passed in registers.
11880 Assume that we don't need the marker for software floating point,
11881 or compiler generated library calls. */
11882 if (mode
== VOIDmode
)
11885 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
11887 || (cum
->nargs_prototype
< 0
11888 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
)))
11889 && TARGET_HARD_FLOAT
)
11890 return GEN_INT (cum
->call_cookie
11891 | ((cum
->fregno
== FP_ARG_MIN_REG
)
11892 ? CALL_V4_SET_FP_ARGS
11893 : CALL_V4_CLEAR_FP_ARGS
));
11895 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
11898 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11900 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11902 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
11903 if (rslt
!= NULL_RTX
)
11905 /* Else fall through to usual handling. */
11908 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11910 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
11914 /* Do we also need to pass this argument in the parameter save area?
11915 Library support functions for IEEE 128-bit are assumed to not need the
11916 value passed both in GPRs and in vector registers. */
11917 if (TARGET_64BIT
&& !cum
->prototype
11918 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
11920 int align_words
= ROUND_UP (cum
->words
, 2);
11921 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
11924 /* Describe where this argument goes in the vector registers. */
11925 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
11927 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
11928 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
11929 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11932 return rs6000_finish_function_arg (mode
, rvec
, k
);
11934 else if (TARGET_ALTIVEC_ABI
11935 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
11936 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11937 && int_size_in_bytes (type
) == 16)))
11939 if (named
|| abi
== ABI_V4
)
11943 /* Vector parameters to varargs functions under AIX or Darwin
11944 get passed in memory and possibly also in GPRs. */
11945 int align
, align_words
, n_words
;
11946 machine_mode part_mode
;
11948 /* Vector parameters must be 16-byte aligned. In 32-bit
11949 mode this means we need to take into account the offset
11950 to the parameter save area. In 64-bit mode, they just
11951 have to start on an even word, since the parameter save
11952 area is 16-byte aligned. */
11954 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11956 align
= cum
->words
& 1;
11957 align_words
= cum
->words
+ align
;
11959 /* Out of registers? Memory, then. */
11960 if (align_words
>= GP_ARG_NUM_REG
)
11963 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11964 return rs6000_mixed_function_arg (mode
, type
, align_words
);
11966 /* The vector value goes in GPRs. Only the part of the
11967 value in GPRs is reported here. */
11969 n_words
= rs6000_arg_size (mode
, type
);
11970 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
11971 /* Fortunately, there are only two possibilities, the value
11972 is either wholly in GPRs or half in GPRs and half not. */
11973 part_mode
= DImode
;
11975 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
11979 else if (abi
== ABI_V4
)
11981 if (abi_v4_pass_in_fpr (mode
, named
))
11983 /* _Decimal128 must use an even/odd register pair. This assumes
11984 that the register number is odd when fregno is odd. */
11985 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11988 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11989 <= FP_ARG_V4_MAX_REG
)
11990 return gen_rtx_REG (mode
, cum
->fregno
);
11996 int n_words
= rs6000_arg_size (mode
, type
);
11997 int gregno
= cum
->sysv_gregno
;
11999 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12000 As does any other 2 word item such as complex int due to a
12001 historical mistake. */
12003 gregno
+= (1 - gregno
) & 1;
12005 /* Multi-reg args are not split between registers and stack. */
12006 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
12009 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12010 return rs6000_mixed_function_arg (mode
, type
,
12011 gregno
- GP_ARG_MIN_REG
);
12012 return gen_rtx_REG (mode
, gregno
);
12017 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12019 /* _Decimal128 must be passed in an even/odd float register pair.
12020 This assumes that the register number is odd when fregno is odd. */
12021 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
12024 if (USE_FP_FOR_ARG_P (cum
, elt_mode
)
12025 && !(TARGET_AIX
&& !TARGET_ELF
12026 && type
!= NULL
&& AGGREGATE_TYPE_P (type
)))
12028 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
12031 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12034 /* Do we also need to pass this argument in the parameter
12036 if (type
&& (cum
->nargs_prototype
<= 0
12037 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12038 && TARGET_XL_COMPAT
12039 && align_words
>= GP_ARG_NUM_REG
)))
12040 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
12042 /* Describe where this argument goes in the fprs. */
12043 for (i
= 0; i
< n_elts
12044 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
12046 /* Check if the argument is split over registers and memory.
12047 This can only ever happen for long double or _Decimal128;
12048 complex types are handled via split_complex_arg. */
12049 machine_mode fmode
= elt_mode
;
12050 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
12052 gcc_assert (FLOAT128_2REG_P (fmode
));
12053 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
12056 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
12057 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
12058 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12061 /* If there were not enough FPRs to hold the argument, the rest
12062 usually goes into memory. However, if the current position
12063 is still within the register parameter area, a portion may
12064 actually have to go into GPRs.
12066 Note that it may happen that the portion of the argument
12067 passed in the first "half" of the first GPR was already
12068 passed in the last FPR as well.
12070 For unnamed arguments, we already set up GPRs to cover the
12071 whole argument in rs6000_psave_function_arg, so there is
12072 nothing further to do at this point. */
12073 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
12074 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
12075 && cum
->nargs_prototype
> 0)
12077 static bool warned
;
12079 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
12080 int n_words
= rs6000_arg_size (mode
, type
);
12082 align_words
+= fpr_words
;
12083 n_words
-= fpr_words
;
12087 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
12088 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
12089 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12091 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
12093 if (!warned
&& warn_psabi
)
12096 inform (input_location
,
12097 "the ABI of passing homogeneous float aggregates"
12098 " has changed in GCC 5");
12102 return rs6000_finish_function_arg (mode
, rvec
, k
);
12104 else if (align_words
< GP_ARG_NUM_REG
)
12106 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12107 return rs6000_mixed_function_arg (mode
, type
, align_words
);
12109 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12116 /* For an arg passed partly in registers and partly in memory, this is
12117 the number of bytes passed in registers. For args passed entirely in
12118 registers or entirely in memory, zero. When an arg is described by a
12119 PARALLEL, perhaps using more than one register type, this function
12120 returns the number of bytes used by the first element of the PARALLEL. */
12123 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
12124 tree type
, bool named
)
12126 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12127 bool passed_in_gprs
= true;
12130 machine_mode elt_mode
;
12133 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
12135 if (DEFAULT_ABI
== ABI_V4
)
12138 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
12140 /* If we are passing this arg in the fixed parameter save area (gprs or
12141 memory) as well as VRs, we do not use the partial bytes mechanism;
12142 instead, rs6000_function_arg will return a PARALLEL including a memory
12143 element as necessary. Library support functions for IEEE 128-bit are
12144 assumed to not need the value passed both in GPRs and in vector
12146 if (TARGET_64BIT
&& !cum
->prototype
12147 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
12150 /* Otherwise, we pass in VRs only. Check for partial copies. */
12151 passed_in_gprs
= false;
12152 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
12153 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
12156 /* In this complicated case we just disable the partial_nregs code. */
12157 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
12160 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12162 if (USE_FP_FOR_ARG_P (cum
, elt_mode
)
12163 && !(TARGET_AIX
&& !TARGET_ELF
12164 && type
!= NULL
&& AGGREGATE_TYPE_P (type
)))
12166 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12168 /* If we are passing this arg in the fixed parameter save area
12169 (gprs or memory) as well as FPRs, we do not use the partial
12170 bytes mechanism; instead, rs6000_function_arg will return a
12171 PARALLEL including a memory element as necessary. */
12173 && (cum
->nargs_prototype
<= 0
12174 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12175 && TARGET_XL_COMPAT
12176 && align_words
>= GP_ARG_NUM_REG
)))
12179 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12180 passed_in_gprs
= false;
12181 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
12183 /* Compute number of bytes / words passed in FPRs. If there
12184 is still space available in the register parameter area
12185 *after* that amount, a part of the argument will be passed
12186 in GPRs. In that case, the total amount passed in any
12187 registers is equal to the amount that would have been passed
12188 in GPRs if everything were passed there, so we fall back to
12189 the GPR code below to compute the appropriate value. */
12190 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
12191 * MIN (8, GET_MODE_SIZE (elt_mode
)));
12192 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
12194 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
12195 passed_in_gprs
= true;
12202 && align_words
< GP_ARG_NUM_REG
12203 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
12204 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
12206 if (ret
!= 0 && TARGET_DEBUG_ARG
)
12207 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
12212 /* A C expression that indicates when an argument must be passed by
12213 reference. If nonzero for an argument, a copy of that argument is
12214 made in memory and a pointer to the argument is passed instead of
12215 the argument itself. The pointer is passed in whatever way is
12216 appropriate for passing a pointer to that type.
12218 Under V.4, aggregates and long double are passed by reference.
12220 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12221 reference unless the AltiVec vector extension ABI is in force.
12223 As an extension to all ABIs, variable sized types are passed by
12227 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
12228 machine_mode mode
, const_tree type
,
12229 bool named ATTRIBUTE_UNUSED
)
12234 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
12235 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
12237 if (TARGET_DEBUG_ARG
)
12238 fprintf (stderr
, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12242 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
12244 if (TARGET_DEBUG_ARG
)
12245 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
12249 if (int_size_in_bytes (type
) < 0)
12251 if (TARGET_DEBUG_ARG
)
12252 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
12256 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12257 modes only exist for GCC vector types if -maltivec. */
12258 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12260 if (TARGET_DEBUG_ARG
)
12261 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
12265 /* Pass synthetic vectors in memory. */
12266 if (TREE_CODE (type
) == VECTOR_TYPE
12267 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
12269 static bool warned_for_pass_big_vectors
= false;
12270 if (TARGET_DEBUG_ARG
)
12271 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
12272 if (!warned_for_pass_big_vectors
)
12274 warning (OPT_Wpsabi
, "GCC vector passed by reference: "
12275 "non-standard ABI extension with no compatibility "
12277 warned_for_pass_big_vectors
= true;
12285 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12286 already processes. Return true if the parameter must be passed
12287 (fully or partially) on the stack. */
12290 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
12296 /* Catch errors. */
12297 if (type
== NULL
|| type
== error_mark_node
)
12300 /* Handle types with no storage requirement. */
12301 if (TYPE_MODE (type
) == VOIDmode
)
12304 /* Handle complex types. */
12305 if (TREE_CODE (type
) == COMPLEX_TYPE
)
12306 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
12307 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
12309 /* Handle transparent aggregates. */
12310 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
12311 && TYPE_TRANSPARENT_AGGR (type
))
12312 type
= TREE_TYPE (first_field (type
));
12314 /* See if this arg was passed by invisible reference. */
12315 if (pass_by_reference (get_cumulative_args (args_so_far
),
12316 TYPE_MODE (type
), type
, true))
12317 type
= build_pointer_type (type
);
12319 /* Find mode as it is passed by the ABI. */
12320 unsignedp
= TYPE_UNSIGNED (type
);
12321 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
12323 /* If we must pass in stack, we need a stack. */
12324 if (rs6000_must_pass_in_stack (mode
, type
))
12327 /* If there is no incoming register, we need a stack. */
12328 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
12329 if (entry_parm
== NULL
)
12332 /* Likewise if we need to pass both in registers and on the stack. */
12333 if (GET_CODE (entry_parm
) == PARALLEL
12334 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
12337 /* Also true if we're partially in registers and partially not. */
12338 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
12341 /* Update info on where next arg arrives in registers. */
12342 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
12346 /* Return true if FUN has no prototype, has a variable argument
12347 list, or passes any parameter in memory. */
12350 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
12352 tree fntype
, result
;
12353 CUMULATIVE_ARGS args_so_far_v
;
12354 cumulative_args_t args_so_far
;
12357 /* Must be a libcall, all of which only use reg parms. */
12362 fntype
= TREE_TYPE (fun
);
12364 /* Varargs functions need the parameter save area. */
12365 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
12368 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
12369 args_so_far
= pack_cumulative_args (&args_so_far_v
);
12371 /* When incoming, we will have been passed the function decl.
12372 It is necessary to use the decl to handle K&R style functions,
12373 where TYPE_ARG_TYPES may not be available. */
12376 gcc_assert (DECL_P (fun
));
12377 result
= DECL_RESULT (fun
);
12380 result
= TREE_TYPE (fntype
);
12382 if (result
&& aggregate_value_p (result
, fntype
))
12384 if (!TYPE_P (result
))
12385 result
= TREE_TYPE (result
);
12386 result
= build_pointer_type (result
);
12387 rs6000_parm_needs_stack (args_so_far
, result
);
12394 for (parm
= DECL_ARGUMENTS (fun
);
12395 parm
&& parm
!= void_list_node
;
12396 parm
= TREE_CHAIN (parm
))
12397 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
12402 function_args_iterator args_iter
;
12405 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
12406 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
12413 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12414 usually a constant depending on the ABI. However, in the ELFv2 ABI
12415 the register parameter area is optional when calling a function that
12416 has a prototype is scope, has no variable argument list, and passes
12417 all parameters in registers. */
12420 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
12422 int reg_parm_stack_space
;
12424 switch (DEFAULT_ABI
)
12427 reg_parm_stack_space
= 0;
12432 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12436 /* ??? Recomputing this every time is a bit expensive. Is there
12437 a place to cache this information? */
12438 if (rs6000_function_parms_need_stack (fun
, incoming
))
12439 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12441 reg_parm_stack_space
= 0;
12445 return reg_parm_stack_space
;
12449 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
12452 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
12457 for (i
= 0; i
< nregs
; i
++)
12459 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
12460 if (reload_completed
)
12462 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
12465 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
12466 i
* GET_MODE_SIZE (reg_mode
));
12469 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
12473 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
12477 /* Perform any needed actions needed for a function that is receiving a
12478 variable number of arguments.
12482 MODE and TYPE are the mode and type of the current parameter.
12484 PRETEND_SIZE is a variable that should be set to the amount of stack
12485 that must be pushed by the prolog to pretend that our caller pushed
12488 Normally, this macro will push all remaining incoming registers on the
12489 stack and set PRETEND_SIZE to the length of the registers pushed. */
12492 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
12493 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
12496 CUMULATIVE_ARGS next_cum
;
12497 int reg_size
= TARGET_32BIT
? 4 : 8;
12498 rtx save_area
= NULL_RTX
, mem
;
12499 int first_reg_offset
;
12500 alias_set_type set
;
12502 /* Skip the last named argument. */
12503 next_cum
= *get_cumulative_args (cum
);
12504 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
12506 if (DEFAULT_ABI
== ABI_V4
)
12508 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
12512 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
12513 HOST_WIDE_INT offset
= 0;
12515 /* Try to optimize the size of the varargs save area.
12516 The ABI requires that ap.reg_save_area is doubleword
12517 aligned, but we don't need to allocate space for all
12518 the bytes, only those to which we actually will save
12520 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
12521 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
12522 if (TARGET_HARD_FLOAT
12523 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
12524 && cfun
->va_list_fpr_size
)
12527 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
12528 * UNITS_PER_FP_WORD
;
12529 if (cfun
->va_list_fpr_size
12530 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12531 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
12533 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12534 * UNITS_PER_FP_WORD
;
12538 offset
= -((first_reg_offset
* reg_size
) & ~7);
12539 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
12541 gpr_reg_num
= cfun
->va_list_gpr_size
;
12542 if (reg_size
== 4 && (first_reg_offset
& 1))
12545 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
12548 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
12549 * UNITS_PER_FP_WORD
12550 - (int) (GP_ARG_NUM_REG
* reg_size
);
12552 if (gpr_size
+ fpr_size
)
12555 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
12556 gcc_assert (MEM_P (reg_save_area
));
12557 reg_save_area
= XEXP (reg_save_area
, 0);
12558 if (GET_CODE (reg_save_area
) == PLUS
)
12560 gcc_assert (XEXP (reg_save_area
, 0)
12561 == virtual_stack_vars_rtx
);
12562 gcc_assert (CONST_INT_P (XEXP (reg_save_area
, 1)));
12563 offset
+= INTVAL (XEXP (reg_save_area
, 1));
12566 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
12569 cfun
->machine
->varargs_save_offset
= offset
;
12570 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
12575 first_reg_offset
= next_cum
.words
;
12576 save_area
= crtl
->args
.internal_arg_pointer
;
12578 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
12579 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
12582 set
= get_varargs_alias_set ();
12583 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
12584 && cfun
->va_list_gpr_size
)
12586 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
12588 if (va_list_gpr_counter_field
)
12589 /* V4 va_list_gpr_size counts number of registers needed. */
12590 n_gpr
= cfun
->va_list_gpr_size
;
12592 /* char * va_list instead counts number of bytes needed. */
12593 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
12598 mem
= gen_rtx_MEM (BLKmode
,
12599 plus_constant (Pmode
, save_area
,
12600 first_reg_offset
* reg_size
));
12601 MEM_NOTRAP_P (mem
) = 1;
12602 set_mem_alias_set (mem
, set
);
12603 set_mem_align (mem
, BITS_PER_WORD
);
12605 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
12609 /* Save FP registers if needed. */
12610 if (DEFAULT_ABI
== ABI_V4
12611 && TARGET_HARD_FLOAT
12613 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
12614 && cfun
->va_list_fpr_size
)
12616 int fregno
= next_cum
.fregno
, nregs
;
12617 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
12618 rtx lab
= gen_label_rtx ();
12619 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
12620 * UNITS_PER_FP_WORD
);
12623 (gen_rtx_SET (pc_rtx
,
12624 gen_rtx_IF_THEN_ELSE (VOIDmode
,
12625 gen_rtx_NE (VOIDmode
, cr1
,
12627 gen_rtx_LABEL_REF (VOIDmode
, lab
),
12631 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
12632 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
12634 mem
= gen_rtx_MEM (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
12635 plus_constant (Pmode
, save_area
, off
));
12636 MEM_NOTRAP_P (mem
) = 1;
12637 set_mem_alias_set (mem
, set
);
12638 set_mem_align (mem
, GET_MODE_ALIGNMENT (
12639 TARGET_HARD_FLOAT
? DFmode
: SFmode
));
12640 emit_move_insn (mem
, gen_rtx_REG (
12641 TARGET_HARD_FLOAT
? DFmode
: SFmode
, fregno
));
12648 /* Create the va_list data type. */
12651 rs6000_build_builtin_va_list (void)
12653 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
12655 /* For AIX, prefer 'char *' because that's what the system
12656 header files like. */
12657 if (DEFAULT_ABI
!= ABI_V4
)
12658 return build_pointer_type (char_type_node
);
12660 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
12661 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
12662 get_identifier ("__va_list_tag"), record
);
12664 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
12665 unsigned_char_type_node
);
12666 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
12667 unsigned_char_type_node
);
12668 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12669 every user file. */
12670 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12671 get_identifier ("reserved"), short_unsigned_type_node
);
12672 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12673 get_identifier ("overflow_arg_area"),
12675 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
12676 get_identifier ("reg_save_area"),
12679 va_list_gpr_counter_field
= f_gpr
;
12680 va_list_fpr_counter_field
= f_fpr
;
12682 DECL_FIELD_CONTEXT (f_gpr
) = record
;
12683 DECL_FIELD_CONTEXT (f_fpr
) = record
;
12684 DECL_FIELD_CONTEXT (f_res
) = record
;
12685 DECL_FIELD_CONTEXT (f_ovf
) = record
;
12686 DECL_FIELD_CONTEXT (f_sav
) = record
;
12688 TYPE_STUB_DECL (record
) = type_decl
;
12689 TYPE_NAME (record
) = type_decl
;
12690 TYPE_FIELDS (record
) = f_gpr
;
12691 DECL_CHAIN (f_gpr
) = f_fpr
;
12692 DECL_CHAIN (f_fpr
) = f_res
;
12693 DECL_CHAIN (f_res
) = f_ovf
;
12694 DECL_CHAIN (f_ovf
) = f_sav
;
12696 layout_type (record
);
12698 /* The correct type is an array type of one element. */
12699 return build_array_type (record
, build_index_type (size_zero_node
));
12702 /* Implement va_start. */
12705 rs6000_va_start (tree valist
, rtx nextarg
)
12707 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
12708 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
12709 tree gpr
, fpr
, ovf
, sav
, t
;
12711 /* Only SVR4 needs something special. */
12712 if (DEFAULT_ABI
!= ABI_V4
)
12714 std_expand_builtin_va_start (valist
, nextarg
);
12718 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12719 f_fpr
= DECL_CHAIN (f_gpr
);
12720 f_res
= DECL_CHAIN (f_fpr
);
12721 f_ovf
= DECL_CHAIN (f_res
);
12722 f_sav
= DECL_CHAIN (f_ovf
);
12724 valist
= build_simple_mem_ref (valist
);
12725 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12726 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
12728 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
12730 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
12733 /* Count number of gp and fp argument registers used. */
12734 words
= crtl
->args
.info
.words
;
12735 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
12737 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
12740 if (TARGET_DEBUG_ARG
)
12741 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
12742 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
12743 words
, n_gpr
, n_fpr
);
12745 if (cfun
->va_list_gpr_size
)
12747 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
12748 build_int_cst (NULL_TREE
, n_gpr
));
12749 TREE_SIDE_EFFECTS (t
) = 1;
12750 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12753 if (cfun
->va_list_fpr_size
)
12755 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
12756 build_int_cst (NULL_TREE
, n_fpr
));
12757 TREE_SIDE_EFFECTS (t
) = 1;
12758 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12760 #ifdef HAVE_AS_GNU_ATTRIBUTE
12761 if (call_ABI_of_interest (cfun
->decl
))
12762 rs6000_passes_float
= true;
12766 /* Find the overflow area. */
12767 t
= make_tree (TREE_TYPE (ovf
), crtl
->args
.internal_arg_pointer
);
12769 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
12770 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
12771 TREE_SIDE_EFFECTS (t
) = 1;
12772 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12774 /* If there were no va_arg invocations, don't set up the register
12776 if (!cfun
->va_list_gpr_size
12777 && !cfun
->va_list_fpr_size
12778 && n_gpr
< GP_ARG_NUM_REG
12779 && n_fpr
< FP_ARG_V4_MAX_REG
)
12782 /* Find the register save area. */
12783 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
12784 if (cfun
->machine
->varargs_save_offset
)
12785 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
12786 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
12787 TREE_SIDE_EFFECTS (t
) = 1;
12788 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12791 /* Implement va_arg. */
12794 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
12795 gimple_seq
*post_p
)
12797 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
12798 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
12799 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
12800 tree lab_false
, lab_over
, addr
;
12802 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
12806 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
12808 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
12809 return build_va_arg_indirect_ref (t
);
12812 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12813 earlier version of gcc, with the property that it always applied alignment
12814 adjustments to the va-args (even for zero-sized types). The cheapest way
12815 to deal with this is to replicate the effect of the part of
12816 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12818 We don't need to check for pass-by-reference because of the test above.
12819 We can return a simplifed answer, since we know there's no offset to add. */
12822 && rs6000_darwin64_abi
)
12823 || DEFAULT_ABI
== ABI_ELFv2
12824 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
12825 && integer_zerop (TYPE_SIZE (type
)))
12827 unsigned HOST_WIDE_INT align
, boundary
;
12828 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
12829 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
12830 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
12831 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
12832 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
12833 boundary
/= BITS_PER_UNIT
;
12834 if (boundary
> align
)
12837 /* This updates arg ptr by the amount that would be necessary
12838 to align the zero-sized (but not zero-alignment) item. */
12839 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
12840 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
12841 gimplify_and_add (t
, pre_p
);
12843 t
= fold_convert (sizetype
, valist_tmp
);
12844 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
12845 fold_convert (TREE_TYPE (valist
),
12846 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
12847 size_int (-boundary
))));
12848 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
12849 gimplify_and_add (t
, pre_p
);
12851 /* Since it is zero-sized there's no increment for the item itself. */
12852 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
12853 return build_va_arg_indirect_ref (valist_tmp
);
12856 if (DEFAULT_ABI
!= ABI_V4
)
12858 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
12860 tree elem_type
= TREE_TYPE (type
);
12861 machine_mode elem_mode
= TYPE_MODE (elem_type
);
12862 int elem_size
= GET_MODE_SIZE (elem_mode
);
12864 if (elem_size
< UNITS_PER_WORD
)
12866 tree real_part
, imag_part
;
12867 gimple_seq post
= NULL
;
12869 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
12871 /* Copy the value into a temporary, lest the formal temporary
12872 be reused out from under us. */
12873 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
12874 gimple_seq_add_seq (pre_p
, post
);
12876 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
12879 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
12883 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
12886 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12887 f_fpr
= DECL_CHAIN (f_gpr
);
12888 f_res
= DECL_CHAIN (f_fpr
);
12889 f_ovf
= DECL_CHAIN (f_res
);
12890 f_sav
= DECL_CHAIN (f_ovf
);
12892 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12893 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
12895 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
12897 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
12900 size
= int_size_in_bytes (type
);
12901 rsize
= (size
+ 3) / 4;
12902 int pad
= 4 * rsize
- size
;
12905 machine_mode mode
= TYPE_MODE (type
);
12906 if (abi_v4_pass_in_fpr (mode
, false))
12908 /* FP args go in FP registers, if present. */
12910 n_reg
= (size
+ 7) / 8;
12911 sav_ofs
= (TARGET_HARD_FLOAT
? 8 : 4) * 4;
12912 sav_scale
= (TARGET_HARD_FLOAT
? 8 : 4);
12913 if (mode
!= SFmode
&& mode
!= SDmode
)
12918 /* Otherwise into GP registers. */
12927 /* Pull the value out of the saved registers.... */
12930 addr
= create_tmp_var (ptr_type_node
, "addr");
12932 /* AltiVec vectors never go in registers when -mabi=altivec. */
12933 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12937 lab_false
= create_artificial_label (input_location
);
12938 lab_over
= create_artificial_label (input_location
);
12940 /* Long long is aligned in the registers. As are any other 2 gpr
12941 item such as complex int due to a historical mistake. */
12943 if (n_reg
== 2 && reg
== gpr
)
12946 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12947 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
12948 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
12949 unshare_expr (reg
), u
);
12951 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12952 reg number is 0 for f1, so we want to make it odd. */
12953 else if (reg
== fpr
&& mode
== TDmode
)
12955 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12956 build_int_cst (TREE_TYPE (reg
), 1));
12957 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
12960 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
12961 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
12962 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
12963 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
12964 gimplify_and_add (t
, pre_p
);
12968 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
12970 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12971 build_int_cst (TREE_TYPE (reg
), n_reg
));
12972 u
= fold_convert (sizetype
, u
);
12973 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
12974 t
= fold_build_pointer_plus (t
, u
);
12976 /* _Decimal32 varargs are located in the second word of the 64-bit
12977 FP register for 32-bit binaries. */
12978 if (TARGET_32BIT
&& TARGET_HARD_FLOAT
&& mode
== SDmode
)
12979 t
= fold_build_pointer_plus_hwi (t
, size
);
12981 /* Args are passed right-aligned. */
12982 if (BYTES_BIG_ENDIAN
)
12983 t
= fold_build_pointer_plus_hwi (t
, pad
);
12985 gimplify_assign (addr
, t
, pre_p
);
12987 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
12989 stmt
= gimple_build_label (lab_false
);
12990 gimple_seq_add_stmt (pre_p
, stmt
);
12992 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
12994 /* Ensure that we don't find any more args in regs.
12995 Alignment has taken care of for special cases. */
12996 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
13000 /* ... otherwise out of the overflow area. */
13002 /* Care for on-stack alignment if needed. */
13006 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
13007 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
13008 build_int_cst (TREE_TYPE (t
), -align
));
13011 /* Args are passed right-aligned. */
13012 if (BYTES_BIG_ENDIAN
)
13013 t
= fold_build_pointer_plus_hwi (t
, pad
);
13015 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
13017 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
13019 t
= fold_build_pointer_plus_hwi (t
, size
);
13020 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
13024 stmt
= gimple_build_label (lab_over
);
13025 gimple_seq_add_stmt (pre_p
, stmt
);
13028 if (STRICT_ALIGNMENT
13029 && (TYPE_ALIGN (type
)
13030 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
13032 /* The value (of type complex double, for example) may not be
13033 aligned in memory in the saved registers, so copy via a
13034 temporary. (This is the same code as used for SPARC.) */
13035 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
13036 tree dest_addr
= build_fold_addr_expr (tmp
);
13038 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
13039 3, dest_addr
, addr
, size_int (rsize
* 4));
13040 TREE_ADDRESSABLE (tmp
) = 1;
13042 gimplify_and_add (copy
, pre_p
);
13046 addr
= fold_convert (ptrtype
, addr
);
13047 return build_va_arg_indirect_ref (addr
);
13053 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
13056 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
13057 const char *attr_string
= "";
13059 gcc_assert (name
!= NULL
);
13060 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
13062 if (rs6000_builtin_decls
[(int)code
])
13063 fatal_error (input_location
,
13064 "internal error: builtin function %qs already processed",
13067 rs6000_builtin_decls
[(int)code
] = t
=
13068 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
13070 /* Set any special attributes. */
13071 if ((classify
& RS6000_BTC_CONST
) != 0)
13073 /* const function, function only depends on the inputs. */
13074 TREE_READONLY (t
) = 1;
13075 TREE_NOTHROW (t
) = 1;
13076 attr_string
= ", const";
13078 else if ((classify
& RS6000_BTC_PURE
) != 0)
13080 /* pure function, function can read global memory, but does not set any
13082 DECL_PURE_P (t
) = 1;
13083 TREE_NOTHROW (t
) = 1;
13084 attr_string
= ", pure";
13086 else if ((classify
& RS6000_BTC_FP
) != 0)
13088 /* Function is a math function. If rounding mode is on, then treat the
13089 function as not reading global memory, but it can have arbitrary side
13090 effects. If it is off, then assume the function is a const function.
13091 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13092 builtin-attribute.def that is used for the math functions. */
13093 TREE_NOTHROW (t
) = 1;
13094 if (flag_rounding_math
)
13096 DECL_PURE_P (t
) = 1;
13097 DECL_IS_NOVOPS (t
) = 1;
13098 attr_string
= ", fp, pure";
13102 TREE_READONLY (t
) = 1;
13103 attr_string
= ", fp, const";
13106 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
13107 gcc_unreachable ();
13109 if (TARGET_DEBUG_BUILTIN
)
13110 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
13111 (int)code
, name
, attr_string
);
13114 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13116 #undef RS6000_BUILTIN_0
13117 #undef RS6000_BUILTIN_1
13118 #undef RS6000_BUILTIN_2
13119 #undef RS6000_BUILTIN_3
13120 #undef RS6000_BUILTIN_A
13121 #undef RS6000_BUILTIN_D
13122 #undef RS6000_BUILTIN_H
13123 #undef RS6000_BUILTIN_P
13124 #undef RS6000_BUILTIN_X
13126 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13127 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13128 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13129 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13130 { MASK, ICODE, NAME, ENUM },
13132 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13133 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13134 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13135 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13136 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13138 static const struct builtin_description bdesc_3arg
[] =
13140 #include "rs6000-builtin.def"
13143 /* DST operations: void foo (void *, const int, const char). */
13145 #undef RS6000_BUILTIN_0
13146 #undef RS6000_BUILTIN_1
13147 #undef RS6000_BUILTIN_2
13148 #undef RS6000_BUILTIN_3
13149 #undef RS6000_BUILTIN_A
13150 #undef RS6000_BUILTIN_D
13151 #undef RS6000_BUILTIN_H
13152 #undef RS6000_BUILTIN_P
13153 #undef RS6000_BUILTIN_X
13155 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13156 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13157 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13158 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13159 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13160 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13161 { MASK, ICODE, NAME, ENUM },
13163 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13164 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13165 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13167 static const struct builtin_description bdesc_dst
[] =
13169 #include "rs6000-builtin.def"
13172 /* Simple binary operations: VECc = foo (VECa, VECb). */
13174 #undef RS6000_BUILTIN_0
13175 #undef RS6000_BUILTIN_1
13176 #undef RS6000_BUILTIN_2
13177 #undef RS6000_BUILTIN_3
13178 #undef RS6000_BUILTIN_A
13179 #undef RS6000_BUILTIN_D
13180 #undef RS6000_BUILTIN_H
13181 #undef RS6000_BUILTIN_P
13182 #undef RS6000_BUILTIN_X
13184 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13185 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13186 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13187 { MASK, ICODE, NAME, ENUM },
13189 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13190 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13191 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13192 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13193 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13194 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13196 static const struct builtin_description bdesc_2arg
[] =
13198 #include "rs6000-builtin.def"
13201 #undef RS6000_BUILTIN_0
13202 #undef RS6000_BUILTIN_1
13203 #undef RS6000_BUILTIN_2
13204 #undef RS6000_BUILTIN_3
13205 #undef RS6000_BUILTIN_A
13206 #undef RS6000_BUILTIN_D
13207 #undef RS6000_BUILTIN_H
13208 #undef RS6000_BUILTIN_P
13209 #undef RS6000_BUILTIN_X
13211 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13212 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13213 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13214 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13215 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13216 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13217 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13218 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13219 { MASK, ICODE, NAME, ENUM },
13221 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13223 /* AltiVec predicates. */
13225 static const struct builtin_description bdesc_altivec_preds
[] =
13227 #include "rs6000-builtin.def"
13230 /* ABS* operations. */
13232 #undef RS6000_BUILTIN_0
13233 #undef RS6000_BUILTIN_1
13234 #undef RS6000_BUILTIN_2
13235 #undef RS6000_BUILTIN_3
13236 #undef RS6000_BUILTIN_A
13237 #undef RS6000_BUILTIN_D
13238 #undef RS6000_BUILTIN_H
13239 #undef RS6000_BUILTIN_P
13240 #undef RS6000_BUILTIN_X
13242 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13243 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13244 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13245 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13246 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13247 { MASK, ICODE, NAME, ENUM },
13249 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13250 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13251 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13252 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13254 static const struct builtin_description bdesc_abs
[] =
13256 #include "rs6000-builtin.def"
13259 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13262 #undef RS6000_BUILTIN_0
13263 #undef RS6000_BUILTIN_1
13264 #undef RS6000_BUILTIN_2
13265 #undef RS6000_BUILTIN_3
13266 #undef RS6000_BUILTIN_A
13267 #undef RS6000_BUILTIN_D
13268 #undef RS6000_BUILTIN_H
13269 #undef RS6000_BUILTIN_P
13270 #undef RS6000_BUILTIN_X
13272 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13273 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13274 { MASK, ICODE, NAME, ENUM },
13276 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13277 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13278 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13279 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13280 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13281 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13282 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13284 static const struct builtin_description bdesc_1arg
[] =
13286 #include "rs6000-builtin.def"
13289 /* Simple no-argument operations: result = __builtin_darn_32 () */
13291 #undef RS6000_BUILTIN_0
13292 #undef RS6000_BUILTIN_1
13293 #undef RS6000_BUILTIN_2
13294 #undef RS6000_BUILTIN_3
13295 #undef RS6000_BUILTIN_A
13296 #undef RS6000_BUILTIN_D
13297 #undef RS6000_BUILTIN_H
13298 #undef RS6000_BUILTIN_P
13299 #undef RS6000_BUILTIN_X
13301 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13302 { MASK, ICODE, NAME, ENUM },
13304 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13305 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13306 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13307 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13308 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13309 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13310 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13311 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13313 static const struct builtin_description bdesc_0arg
[] =
13315 #include "rs6000-builtin.def"
13318 /* HTM builtins. */
13319 #undef RS6000_BUILTIN_0
13320 #undef RS6000_BUILTIN_1
13321 #undef RS6000_BUILTIN_2
13322 #undef RS6000_BUILTIN_3
13323 #undef RS6000_BUILTIN_A
13324 #undef RS6000_BUILTIN_D
13325 #undef RS6000_BUILTIN_H
13326 #undef RS6000_BUILTIN_P
13327 #undef RS6000_BUILTIN_X
13329 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13330 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13331 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13332 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13333 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13334 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13335 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13336 { MASK, ICODE, NAME, ENUM },
13338 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13339 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13341 static const struct builtin_description bdesc_htm
[] =
13343 #include "rs6000-builtin.def"
13346 #undef RS6000_BUILTIN_0
13347 #undef RS6000_BUILTIN_1
13348 #undef RS6000_BUILTIN_2
13349 #undef RS6000_BUILTIN_3
13350 #undef RS6000_BUILTIN_A
13351 #undef RS6000_BUILTIN_D
13352 #undef RS6000_BUILTIN_H
13353 #undef RS6000_BUILTIN_P
13355 /* Return true if a builtin function is overloaded. */
13357 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
13359 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
13363 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode
)
13365 return rs6000_builtin_info
[(int)fncode
].name
;
13368 /* Expand an expression EXP that calls a builtin without arguments. */
13370 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
13373 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13375 if (icode
== CODE_FOR_nothing
)
13376 /* Builtin not supported on this processor. */
13379 if (icode
== CODE_FOR_rs6000_mffsl
13380 && rs6000_isa_flags
& OPTION_MASK_SOFT_FLOAT
)
13382 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
13387 || GET_MODE (target
) != tmode
13388 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13389 target
= gen_reg_rtx (tmode
);
13391 pat
= GEN_FCN (icode
) (target
);
13401 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
13404 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13405 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13406 rtx op0
= expand_normal (arg0
);
13407 rtx op1
= expand_normal (arg1
);
13408 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13409 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13411 if (icode
== CODE_FOR_nothing
)
13412 /* Builtin not supported on this processor. */
13415 /* If we got invalid arguments bail out before generating bad rtl. */
13416 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13419 if (!CONST_INT_P (op0
)
13420 || INTVAL (op0
) > 255
13421 || INTVAL (op0
) < 0)
13423 error ("argument 1 must be an 8-bit field value");
13427 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13428 op0
= copy_to_mode_reg (mode0
, op0
);
13430 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13431 op1
= copy_to_mode_reg (mode1
, op1
);
13433 pat
= GEN_FCN (icode
) (op0
, op1
);
13442 rs6000_expand_mtfsb_builtin (enum insn_code icode
, tree exp
)
13445 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13446 rtx op0
= expand_normal (arg0
);
13448 if (icode
== CODE_FOR_nothing
)
13449 /* Builtin not supported on this processor. */
13452 if (rs6000_isa_flags
& OPTION_MASK_SOFT_FLOAT
)
13454 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
13455 "%<-msoft-float%>");
13459 /* If we got invalid arguments bail out before generating bad rtl. */
13460 if (arg0
== error_mark_node
)
13463 /* Only allow bit numbers 0 to 31. */
13464 if (!u5bit_cint_operand (op0
, VOIDmode
))
13466 error ("Argument must be a constant between 0 and 31.");
13470 pat
= GEN_FCN (icode
) (op0
);
13479 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode
, tree exp
)
13482 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13483 rtx op0
= expand_normal (arg0
);
13484 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13486 if (icode
== CODE_FOR_nothing
)
13487 /* Builtin not supported on this processor. */
13490 if (rs6000_isa_flags
& OPTION_MASK_SOFT_FLOAT
)
13492 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
13496 /* If we got invalid arguments bail out before generating bad rtl. */
13497 if (arg0
== error_mark_node
)
13500 /* If the argument is a constant, check the range. Argument can only be a
13501 2-bit value. Unfortunately, can't check the range of the value at
13502 compile time if the argument is a variable. The least significant two
13503 bits of the argument, regardless of type, are used to set the rounding
13504 mode. All other bits are ignored. */
13505 if (CONST_INT_P (op0
) && !const_0_to_3_operand(op0
, VOIDmode
))
13507 error ("Argument must be a value between 0 and 3.");
13511 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13512 op0
= copy_to_mode_reg (mode0
, op0
);
13514 pat
= GEN_FCN (icode
) (op0
);
13522 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode
, tree exp
)
13525 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13526 rtx op0
= expand_normal (arg0
);
13527 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13530 /* Builtin not supported in 32-bit mode. */
13531 fatal_error (input_location
,
13532 "%<__builtin_set_fpscr_drn%> is not supported "
13533 "in 32-bit mode.");
13535 if (rs6000_isa_flags
& OPTION_MASK_SOFT_FLOAT
)
13537 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
13541 if (icode
== CODE_FOR_nothing
)
13542 /* Builtin not supported on this processor. */
13545 /* If we got invalid arguments bail out before generating bad rtl. */
13546 if (arg0
== error_mark_node
)
13549 /* If the argument is a constant, check the range. Agrument can only be a
13550 3-bit value. Unfortunately, can't check the range of the value at
13551 compile time if the argument is a variable. The least significant two
13552 bits of the argument, regardless of type, are used to set the rounding
13553 mode. All other bits are ignored. */
13554 if (CONST_INT_P (op0
) && !const_0_to_7_operand(op0
, VOIDmode
))
13556 error ("Argument must be a value between 0 and 7.");
13560 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13561 op0
= copy_to_mode_reg (mode0
, op0
);
13563 pat
= GEN_FCN (icode
) (op0
);
13572 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13575 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13576 rtx op0
= expand_normal (arg0
);
13577 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13578 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13580 if (icode
== CODE_FOR_nothing
)
13581 /* Builtin not supported on this processor. */
13584 /* If we got invalid arguments bail out before generating bad rtl. */
13585 if (arg0
== error_mark_node
)
13588 if (icode
== CODE_FOR_altivec_vspltisb
13589 || icode
== CODE_FOR_altivec_vspltish
13590 || icode
== CODE_FOR_altivec_vspltisw
)
13592 /* Only allow 5-bit *signed* literals. */
13593 if (!CONST_INT_P (op0
)
13594 || INTVAL (op0
) > 15
13595 || INTVAL (op0
) < -16)
13597 error ("argument 1 must be a 5-bit signed literal");
13598 return CONST0_RTX (tmode
);
13603 || GET_MODE (target
) != tmode
13604 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13605 target
= gen_reg_rtx (tmode
);
13607 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13608 op0
= copy_to_mode_reg (mode0
, op0
);
13610 pat
= GEN_FCN (icode
) (target
, op0
);
13619 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
13621 rtx pat
, scratch1
, scratch2
;
13622 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13623 rtx op0
= expand_normal (arg0
);
13624 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13625 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13627 /* If we have invalid arguments, bail out before generating bad rtl. */
13628 if (arg0
== error_mark_node
)
13632 || GET_MODE (target
) != tmode
13633 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13634 target
= gen_reg_rtx (tmode
);
13636 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13637 op0
= copy_to_mode_reg (mode0
, op0
);
13639 scratch1
= gen_reg_rtx (mode0
);
13640 scratch2
= gen_reg_rtx (mode0
);
13642 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
13651 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13654 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13655 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13656 rtx op0
= expand_normal (arg0
);
13657 rtx op1
= expand_normal (arg1
);
13658 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13659 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13660 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13662 if (icode
== CODE_FOR_nothing
)
13663 /* Builtin not supported on this processor. */
13666 /* If we got invalid arguments bail out before generating bad rtl. */
13667 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13670 if (icode
== CODE_FOR_unpackv1ti
13671 || icode
== CODE_FOR_unpackkf
13672 || icode
== CODE_FOR_unpacktf
13673 || icode
== CODE_FOR_unpackif
13674 || icode
== CODE_FOR_unpacktd
)
13676 /* Only allow 1-bit unsigned literals. */
13678 if (TREE_CODE (arg1
) != INTEGER_CST
13679 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
13681 error ("argument 2 must be a 1-bit unsigned literal");
13682 return CONST0_RTX (tmode
);
13685 else if (icode
== CODE_FOR_altivec_vspltw
)
13687 /* Only allow 2-bit unsigned literals. */
13689 if (TREE_CODE (arg1
) != INTEGER_CST
13690 || TREE_INT_CST_LOW (arg1
) & ~3)
13692 error ("argument 2 must be a 2-bit unsigned literal");
13693 return CONST0_RTX (tmode
);
13696 else if (icode
== CODE_FOR_altivec_vsplth
)
13698 /* Only allow 3-bit unsigned literals. */
13700 if (TREE_CODE (arg1
) != INTEGER_CST
13701 || TREE_INT_CST_LOW (arg1
) & ~7)
13703 error ("argument 2 must be a 3-bit unsigned literal");
13704 return CONST0_RTX (tmode
);
13707 else if (icode
== CODE_FOR_altivec_vspltb
)
13709 /* Only allow 4-bit unsigned literals. */
13711 if (TREE_CODE (arg1
) != INTEGER_CST
13712 || TREE_INT_CST_LOW (arg1
) & ~15)
13714 error ("argument 2 must be a 4-bit unsigned literal");
13715 return CONST0_RTX (tmode
);
13718 else if (icode
== CODE_FOR_altivec_vcfux
13719 || icode
== CODE_FOR_altivec_vcfsx
13720 || icode
== CODE_FOR_altivec_vctsxs
13721 || icode
== CODE_FOR_altivec_vctuxs
)
13723 /* Only allow 5-bit unsigned literals. */
13725 if (TREE_CODE (arg1
) != INTEGER_CST
13726 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13728 error ("argument 2 must be a 5-bit unsigned literal");
13729 return CONST0_RTX (tmode
);
13732 else if (icode
== CODE_FOR_dfptstsfi_eq_dd
13733 || icode
== CODE_FOR_dfptstsfi_lt_dd
13734 || icode
== CODE_FOR_dfptstsfi_gt_dd
13735 || icode
== CODE_FOR_dfptstsfi_unordered_dd
13736 || icode
== CODE_FOR_dfptstsfi_eq_td
13737 || icode
== CODE_FOR_dfptstsfi_lt_td
13738 || icode
== CODE_FOR_dfptstsfi_gt_td
13739 || icode
== CODE_FOR_dfptstsfi_unordered_td
)
13741 /* Only allow 6-bit unsigned literals. */
13743 if (TREE_CODE (arg0
) != INTEGER_CST
13744 || !IN_RANGE (TREE_INT_CST_LOW (arg0
), 0, 63))
13746 error ("argument 1 must be a 6-bit unsigned literal");
13747 return CONST0_RTX (tmode
);
13750 else if (icode
== CODE_FOR_xststdcqp_kf
13751 || icode
== CODE_FOR_xststdcqp_tf
13752 || icode
== CODE_FOR_xststdcdp
13753 || icode
== CODE_FOR_xststdcsp
13754 || icode
== CODE_FOR_xvtstdcdp
13755 || icode
== CODE_FOR_xvtstdcsp
)
13757 /* Only allow 7-bit unsigned literals. */
13759 if (TREE_CODE (arg1
) != INTEGER_CST
13760 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 127))
13762 error ("argument 2 must be a 7-bit unsigned literal");
13763 return CONST0_RTX (tmode
);
13768 || GET_MODE (target
) != tmode
13769 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13770 target
= gen_reg_rtx (tmode
);
13772 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13773 op0
= copy_to_mode_reg (mode0
, op0
);
13774 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13775 op1
= copy_to_mode_reg (mode1
, op1
);
13777 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13786 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13789 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
13790 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13791 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13792 rtx op0
= expand_normal (arg0
);
13793 rtx op1
= expand_normal (arg1
);
13794 machine_mode tmode
= SImode
;
13795 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13796 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13799 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
13801 error ("argument 1 of %qs must be a constant",
13802 "__builtin_altivec_predicate");
13806 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
13808 gcc_assert (mode0
== mode1
);
13810 /* If we have invalid arguments, bail out before generating bad rtl. */
13811 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13815 || GET_MODE (target
) != tmode
13816 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13817 target
= gen_reg_rtx (tmode
);
13819 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13820 op0
= copy_to_mode_reg (mode0
, op0
);
13821 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13822 op1
= copy_to_mode_reg (mode1
, op1
);
13824 /* Note that for many of the relevant operations (e.g. cmpne or
13825 cmpeq) with float or double operands, it makes more sense for the
13826 mode of the allocated scratch register to select a vector of
13827 integer. But the choice to copy the mode of operand 0 was made
13828 long ago and there are no plans to change it. */
13829 scratch
= gen_reg_rtx (mode0
);
13831 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13836 /* The vec_any* and vec_all* predicates use the same opcodes for two
13837 different operations, but the bits in CR6 will be different
13838 depending on what information we want. So we have to play tricks
13839 with CR6 to get the right bits out.
13841 If you think this is disgusting, look at the specs for the
13842 AltiVec predicates. */
13844 switch (cr6_form_int
)
13847 emit_insn (gen_cr6_test_for_zero (target
));
13850 emit_insn (gen_cr6_test_for_zero_reverse (target
));
13853 emit_insn (gen_cr6_test_for_lt (target
));
13856 emit_insn (gen_cr6_test_for_lt_reverse (target
));
13859 error ("argument 1 of %qs is out of range",
13860 "__builtin_altivec_predicate");
13868 swap_endian_selector_for_mode (machine_mode mode
)
13870 unsigned int swap1
[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13871 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13872 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13873 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13875 unsigned int *swaparray
, i
;
13895 gcc_unreachable ();
13898 for (i
= 0; i
< 16; ++i
)
13899 perm
[i
] = GEN_INT (swaparray
[i
]);
13901 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
,
13902 gen_rtvec_v (16, perm
)));
13906 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
13909 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13910 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13911 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13912 machine_mode mode0
= Pmode
;
13913 machine_mode mode1
= Pmode
;
13914 rtx op0
= expand_normal (arg0
);
13915 rtx op1
= expand_normal (arg1
);
13917 if (icode
== CODE_FOR_nothing
)
13918 /* Builtin not supported on this processor. */
13921 /* If we got invalid arguments bail out before generating bad rtl. */
13922 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13926 || GET_MODE (target
) != tmode
13927 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13928 target
= gen_reg_rtx (tmode
);
13930 op1
= copy_to_mode_reg (mode1
, op1
);
13932 /* For LVX, express the RTL accurately by ANDing the address with -16.
13933 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13934 so the raw address is fine. */
13935 if (icode
== CODE_FOR_altivec_lvx_v1ti
13936 || icode
== CODE_FOR_altivec_lvx_v2df
13937 || icode
== CODE_FOR_altivec_lvx_v2di
13938 || icode
== CODE_FOR_altivec_lvx_v4sf
13939 || icode
== CODE_FOR_altivec_lvx_v4si
13940 || icode
== CODE_FOR_altivec_lvx_v8hi
13941 || icode
== CODE_FOR_altivec_lvx_v16qi
)
13944 if (op0
== const0_rtx
)
13948 op0
= copy_to_mode_reg (mode0
, op0
);
13949 rawaddr
= gen_rtx_PLUS (Pmode
, op1
, op0
);
13951 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
13952 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, addr
);
13954 emit_insn (gen_rtx_SET (target
, addr
));
13958 if (op0
== const0_rtx
)
13959 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
13962 op0
= copy_to_mode_reg (mode0
, op0
);
13963 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
,
13964 gen_rtx_PLUS (Pmode
, op1
, op0
));
13967 pat
= GEN_FCN (icode
) (target
, addr
);
13977 altivec_expand_stxvl_builtin (enum insn_code icode
, tree exp
)
13980 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13981 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13982 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13983 rtx op0
= expand_normal (arg0
);
13984 rtx op1
= expand_normal (arg1
);
13985 rtx op2
= expand_normal (arg2
);
13986 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13987 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13988 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
13990 if (icode
== CODE_FOR_nothing
)
13991 /* Builtin not supported on this processor. */
13994 /* If we got invalid arguments bail out before generating bad rtl. */
13995 if (arg0
== error_mark_node
13996 || arg1
== error_mark_node
13997 || arg2
== error_mark_node
)
14000 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14001 op0
= copy_to_mode_reg (mode0
, op0
);
14002 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14003 op1
= copy_to_mode_reg (mode1
, op1
);
14004 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
14005 op2
= copy_to_mode_reg (mode2
, op2
);
14007 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
14015 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
14017 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14018 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14019 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14020 rtx op0
= expand_normal (arg0
);
14021 rtx op1
= expand_normal (arg1
);
14022 rtx op2
= expand_normal (arg2
);
14023 rtx pat
, addr
, rawaddr
;
14024 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14025 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
14026 machine_mode mode1
= Pmode
;
14027 machine_mode mode2
= Pmode
;
14029 /* Invalid arguments. Bail before doing anything stoopid! */
14030 if (arg0
== error_mark_node
14031 || arg1
== error_mark_node
14032 || arg2
== error_mark_node
)
14035 op2
= copy_to_mode_reg (mode2
, op2
);
14037 /* For STVX, express the RTL accurately by ANDing the address with -16.
14038 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14039 so the raw address is fine. */
14040 if (icode
== CODE_FOR_altivec_stvx_v2df
14041 || icode
== CODE_FOR_altivec_stvx_v2di
14042 || icode
== CODE_FOR_altivec_stvx_v4sf
14043 || icode
== CODE_FOR_altivec_stvx_v4si
14044 || icode
== CODE_FOR_altivec_stvx_v8hi
14045 || icode
== CODE_FOR_altivec_stvx_v16qi
)
14047 if (op1
== const0_rtx
)
14051 op1
= copy_to_mode_reg (mode1
, op1
);
14052 rawaddr
= gen_rtx_PLUS (Pmode
, op2
, op1
);
14055 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
14056 addr
= gen_rtx_MEM (tmode
, addr
);
14058 op0
= copy_to_mode_reg (tmode
, op0
);
14060 emit_insn (gen_rtx_SET (addr
, op0
));
14064 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
14065 op0
= copy_to_mode_reg (smode
, op0
);
14067 if (op1
== const0_rtx
)
14068 addr
= gen_rtx_MEM (tmode
, op2
);
14071 op1
= copy_to_mode_reg (mode1
, op1
);
14072 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op2
, op1
));
14075 pat
= GEN_FCN (icode
) (addr
, op0
);
14083 /* Return the appropriate SPR number associated with the given builtin. */
14084 static inline HOST_WIDE_INT
14085 htm_spr_num (enum rs6000_builtins code
)
14087 if (code
== HTM_BUILTIN_GET_TFHAR
14088 || code
== HTM_BUILTIN_SET_TFHAR
)
14090 else if (code
== HTM_BUILTIN_GET_TFIAR
14091 || code
== HTM_BUILTIN_SET_TFIAR
)
14093 else if (code
== HTM_BUILTIN_GET_TEXASR
14094 || code
== HTM_BUILTIN_SET_TEXASR
)
14096 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
14097 || code
== HTM_BUILTIN_SET_TEXASRU
);
14098 return TEXASRU_SPR
;
14101 /* Return the appropriate SPR regno associated with the given builtin. */
14102 static inline HOST_WIDE_INT
14103 htm_spr_regno (enum rs6000_builtins code
)
14105 if (code
== HTM_BUILTIN_GET_TFHAR
14106 || code
== HTM_BUILTIN_SET_TFHAR
)
14107 return TFHAR_REGNO
;
14108 else if (code
== HTM_BUILTIN_GET_TFIAR
14109 || code
== HTM_BUILTIN_SET_TFIAR
)
14110 return TFIAR_REGNO
;
14111 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
14112 || code
== HTM_BUILTIN_SET_TEXASR
14113 || code
== HTM_BUILTIN_GET_TEXASRU
14114 || code
== HTM_BUILTIN_SET_TEXASRU
);
14115 return TEXASR_REGNO
;
14118 /* Return the correct ICODE value depending on whether we are
14119 setting or reading the HTM SPRs. */
14120 static inline enum insn_code
14121 rs6000_htm_spr_icode (bool nonvoid
)
14124 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
14126 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
14129 /* Expand the HTM builtin in EXP and store the result in TARGET.
14130 Store true in *EXPANDEDP if we found a builtin to expand. */
14132 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
14134 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14135 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
14136 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14137 const struct builtin_description
*d
;
14142 if (!TARGET_POWERPC64
14143 && (fcode
== HTM_BUILTIN_TABORTDC
14144 || fcode
== HTM_BUILTIN_TABORTDCI
))
14146 size_t uns_fcode
= (size_t)fcode
;
14147 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
14148 error ("builtin %qs is only valid in 64-bit mode", name
);
14152 /* Expand the HTM builtins. */
14154 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14155 if (d
->code
== fcode
)
14157 rtx op
[MAX_HTM_OPERANDS
], pat
;
14160 call_expr_arg_iterator iter
;
14161 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
14162 enum insn_code icode
= d
->icode
;
14163 const struct insn_operand_data
*insn_op
;
14164 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
14168 icode
= rs6000_htm_spr_icode (nonvoid
);
14169 insn_op
= &insn_data
[icode
].operand
[0];
14173 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: E_SImode
;
14175 || GET_MODE (target
) != tmode
14176 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
14177 target
= gen_reg_rtx (tmode
);
14179 op
[nopnds
++] = target
;
14182 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
14184 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
14187 insn_op
= &insn_data
[icode
].operand
[nopnds
];
14189 op
[nopnds
] = expand_normal (arg
);
14191 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
14193 if (!strcmp (insn_op
->constraint
, "n"))
14195 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
14196 if (!CONST_INT_P (op
[nopnds
]))
14197 error ("argument %d must be an unsigned literal", arg_num
);
14199 error ("argument %d is an unsigned literal that is "
14200 "out of range", arg_num
);
14203 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
14209 /* Handle the builtins for extended mnemonics. These accept
14210 no arguments, but map to builtins that take arguments. */
14213 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
14214 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
14215 op
[nopnds
++] = GEN_INT (1);
14217 attr
|= RS6000_BTC_UNARY
;
14219 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
14220 op
[nopnds
++] = GEN_INT (0);
14222 attr
|= RS6000_BTC_UNARY
;
14228 /* If this builtin accesses SPRs, then pass in the appropriate
14229 SPR number and SPR regno as the last two operands. */
14232 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
14233 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
14234 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
14236 /* If this builtin accesses a CR, then pass in a scratch
14237 CR as the last operand. */
14238 else if (attr
& RS6000_BTC_CR
)
14239 { cr
= gen_reg_rtx (CCmode
);
14245 int expected_nopnds
= 0;
14246 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
14247 expected_nopnds
= 1;
14248 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
14249 expected_nopnds
= 2;
14250 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
14251 expected_nopnds
= 3;
14252 if (!(attr
& RS6000_BTC_VOID
))
14253 expected_nopnds
+= 1;
14255 expected_nopnds
+= 2;
14257 gcc_assert (nopnds
== expected_nopnds
14258 && nopnds
<= MAX_HTM_OPERANDS
);
14264 pat
= GEN_FCN (icode
) (op
[0]);
14267 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
14270 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
14273 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
14276 gcc_unreachable ();
14282 if (attr
& RS6000_BTC_CR
)
14284 if (fcode
== HTM_BUILTIN_TBEGIN
)
14286 /* Emit code to set TARGET to true or false depending on
14287 whether the tbegin. instruction successfully or failed
14288 to start a transaction. We do this by placing the 1's
14289 complement of CR's EQ bit into TARGET. */
14290 rtx scratch
= gen_reg_rtx (SImode
);
14291 emit_insn (gen_rtx_SET (scratch
,
14292 gen_rtx_EQ (SImode
, cr
,
14294 emit_insn (gen_rtx_SET (target
,
14295 gen_rtx_XOR (SImode
, scratch
,
14300 /* Emit code to copy the 4-bit condition register field
14301 CR into the least significant end of register TARGET. */
14302 rtx scratch1
= gen_reg_rtx (SImode
);
14303 rtx scratch2
= gen_reg_rtx (SImode
);
14304 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
14305 emit_insn (gen_movcc (subreg
, cr
));
14306 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
14307 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
14316 *expandedp
= false;
14320 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14323 cpu_expand_builtin (enum rs6000_builtins fcode
, tree exp ATTRIBUTE_UNUSED
,
14326 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14327 if (fcode
== RS6000_BUILTIN_CPU_INIT
)
14330 if (target
== 0 || GET_MODE (target
) != SImode
)
14331 target
= gen_reg_rtx (SImode
);
14333 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14334 tree arg
= TREE_OPERAND (CALL_EXPR_ARG (exp
, 0), 0);
14335 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14336 to a STRING_CST. */
14337 if (TREE_CODE (arg
) == ARRAY_REF
14338 && TREE_CODE (TREE_OPERAND (arg
, 0)) == STRING_CST
14339 && TREE_CODE (TREE_OPERAND (arg
, 1)) == INTEGER_CST
14340 && compare_tree_int (TREE_OPERAND (arg
, 1), 0) == 0)
14341 arg
= TREE_OPERAND (arg
, 0);
14343 if (TREE_CODE (arg
) != STRING_CST
)
14345 error ("builtin %qs only accepts a string argument",
14346 rs6000_builtin_info
[(size_t) fcode
].name
);
14350 if (fcode
== RS6000_BUILTIN_CPU_IS
)
14352 const char *cpu
= TREE_STRING_POINTER (arg
);
14353 rtx cpuid
= NULL_RTX
;
14354 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_is_info
); i
++)
14355 if (strcmp (cpu
, cpu_is_info
[i
].cpu
) == 0)
14357 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14358 cpuid
= GEN_INT (cpu_is_info
[i
].cpuid
+ _DL_FIRST_PLATFORM
);
14361 if (cpuid
== NULL_RTX
)
14363 /* Invalid CPU argument. */
14364 error ("cpu %qs is an invalid argument to builtin %qs",
14365 cpu
, rs6000_builtin_info
[(size_t) fcode
].name
);
14369 rtx platform
= gen_reg_rtx (SImode
);
14370 rtx tcbmem
= gen_const_mem (SImode
,
14371 gen_rtx_PLUS (Pmode
,
14372 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14373 GEN_INT (TCB_PLATFORM_OFFSET
)));
14374 emit_move_insn (platform
, tcbmem
);
14375 emit_insn (gen_eqsi3 (target
, platform
, cpuid
));
14377 else if (fcode
== RS6000_BUILTIN_CPU_SUPPORTS
)
14379 const char *hwcap
= TREE_STRING_POINTER (arg
);
14380 rtx mask
= NULL_RTX
;
14382 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_supports_info
); i
++)
14383 if (strcmp (hwcap
, cpu_supports_info
[i
].hwcap
) == 0)
14385 mask
= GEN_INT (cpu_supports_info
[i
].mask
);
14386 hwcap_offset
= TCB_HWCAP_OFFSET (cpu_supports_info
[i
].id
);
14389 if (mask
== NULL_RTX
)
14391 /* Invalid HWCAP argument. */
14392 error ("%s %qs is an invalid argument to builtin %qs",
14393 "hwcap", hwcap
, rs6000_builtin_info
[(size_t) fcode
].name
);
14397 rtx tcb_hwcap
= gen_reg_rtx (SImode
);
14398 rtx tcbmem
= gen_const_mem (SImode
,
14399 gen_rtx_PLUS (Pmode
,
14400 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14401 GEN_INT (hwcap_offset
)));
14402 emit_move_insn (tcb_hwcap
, tcbmem
);
14403 rtx scratch1
= gen_reg_rtx (SImode
);
14404 emit_insn (gen_rtx_SET (scratch1
, gen_rtx_AND (SImode
, tcb_hwcap
, mask
)));
14405 rtx scratch2
= gen_reg_rtx (SImode
);
14406 emit_insn (gen_eqsi3 (scratch2
, scratch1
, const0_rtx
));
14407 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (SImode
, scratch2
, const1_rtx
)));
14410 gcc_unreachable ();
14412 /* Record that we have expanded a CPU builtin, so that we can later
14413 emit a reference to the special symbol exported by LIBC to ensure we
14414 do not link against an old LIBC that doesn't support this feature. */
14415 cpu_builtin_p
= true;
14418 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14419 "capability bits", rs6000_builtin_info
[(size_t) fcode
].name
);
14421 /* For old LIBCs, always return FALSE. */
14422 emit_move_insn (target
, GEN_INT (0));
14423 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14429 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
14432 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14433 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14434 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14435 rtx op0
= expand_normal (arg0
);
14436 rtx op1
= expand_normal (arg1
);
14437 rtx op2
= expand_normal (arg2
);
14438 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14439 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14440 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14441 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
14443 if (icode
== CODE_FOR_nothing
)
14444 /* Builtin not supported on this processor. */
14447 /* If we got invalid arguments bail out before generating bad rtl. */
14448 if (arg0
== error_mark_node
14449 || arg1
== error_mark_node
14450 || arg2
== error_mark_node
)
14453 /* Check and prepare argument depending on the instruction code.
14455 Note that a switch statement instead of the sequence of tests
14456 would be incorrect as many of the CODE_FOR values could be
14457 CODE_FOR_nothing and that would yield multiple alternatives
14458 with identical values. We'd never reach here at runtime in
14460 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
14461 || icode
== CODE_FOR_altivec_vsldoi_v2df
14462 || icode
== CODE_FOR_altivec_vsldoi_v4si
14463 || icode
== CODE_FOR_altivec_vsldoi_v8hi
14464 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
14466 /* Only allow 4-bit unsigned literals. */
14468 if (TREE_CODE (arg2
) != INTEGER_CST
14469 || TREE_INT_CST_LOW (arg2
) & ~0xf)
14471 error ("argument 3 must be a 4-bit unsigned literal");
14472 return CONST0_RTX (tmode
);
14475 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
14476 || icode
== CODE_FOR_vsx_xxpermdi_v2di
14477 || icode
== CODE_FOR_vsx_xxpermdi_v2df_be
14478 || icode
== CODE_FOR_vsx_xxpermdi_v2di_be
14479 || icode
== CODE_FOR_vsx_xxpermdi_v1ti
14480 || icode
== CODE_FOR_vsx_xxpermdi_v4sf
14481 || icode
== CODE_FOR_vsx_xxpermdi_v4si
14482 || icode
== CODE_FOR_vsx_xxpermdi_v8hi
14483 || icode
== CODE_FOR_vsx_xxpermdi_v16qi
14484 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
14485 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
14486 || icode
== CODE_FOR_vsx_xxsldwi_v4si
14487 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
14488 || icode
== CODE_FOR_vsx_xxsldwi_v2di
14489 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
14491 /* Only allow 2-bit unsigned literals. */
14493 if (TREE_CODE (arg2
) != INTEGER_CST
14494 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14496 error ("argument 3 must be a 2-bit unsigned literal");
14497 return CONST0_RTX (tmode
);
14500 else if (icode
== CODE_FOR_vsx_set_v2df
14501 || icode
== CODE_FOR_vsx_set_v2di
14502 || icode
== CODE_FOR_bcdadd
14503 || icode
== CODE_FOR_bcdadd_lt
14504 || icode
== CODE_FOR_bcdadd_eq
14505 || icode
== CODE_FOR_bcdadd_gt
14506 || icode
== CODE_FOR_bcdsub
14507 || icode
== CODE_FOR_bcdsub_lt
14508 || icode
== CODE_FOR_bcdsub_eq
14509 || icode
== CODE_FOR_bcdsub_gt
)
14511 /* Only allow 1-bit unsigned literals. */
14513 if (TREE_CODE (arg2
) != INTEGER_CST
14514 || TREE_INT_CST_LOW (arg2
) & ~0x1)
14516 error ("argument 3 must be a 1-bit unsigned literal");
14517 return CONST0_RTX (tmode
);
14520 else if (icode
== CODE_FOR_dfp_ddedpd_dd
14521 || icode
== CODE_FOR_dfp_ddedpd_td
)
14523 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14525 if (TREE_CODE (arg0
) != INTEGER_CST
14526 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14528 error ("argument 1 must be 0 or 2");
14529 return CONST0_RTX (tmode
);
14532 else if (icode
== CODE_FOR_dfp_denbcd_dd
14533 || icode
== CODE_FOR_dfp_denbcd_td
)
14535 /* Only allow 1-bit unsigned literals. */
14537 if (TREE_CODE (arg0
) != INTEGER_CST
14538 || TREE_INT_CST_LOW (arg0
) & ~0x1)
14540 error ("argument 1 must be a 1-bit unsigned literal");
14541 return CONST0_RTX (tmode
);
14544 else if (icode
== CODE_FOR_dfp_dscli_dd
14545 || icode
== CODE_FOR_dfp_dscli_td
14546 || icode
== CODE_FOR_dfp_dscri_dd
14547 || icode
== CODE_FOR_dfp_dscri_td
)
14549 /* Only allow 6-bit unsigned literals. */
14551 if (TREE_CODE (arg1
) != INTEGER_CST
14552 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
14554 error ("argument 2 must be a 6-bit unsigned literal");
14555 return CONST0_RTX (tmode
);
14558 else if (icode
== CODE_FOR_crypto_vshasigmaw
14559 || icode
== CODE_FOR_crypto_vshasigmad
)
14561 /* Check whether the 2nd and 3rd arguments are integer constants and in
14562 range and prepare arguments. */
14564 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (wi::to_wide (arg1
), 2))
14566 error ("argument 2 must be 0 or 1");
14567 return CONST0_RTX (tmode
);
14571 if (TREE_CODE (arg2
) != INTEGER_CST
14572 || wi::geu_p (wi::to_wide (arg2
), 16))
14574 error ("argument 3 must be in the range 0..15");
14575 return CONST0_RTX (tmode
);
14580 || GET_MODE (target
) != tmode
14581 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14582 target
= gen_reg_rtx (tmode
);
14584 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14585 op0
= copy_to_mode_reg (mode0
, op0
);
14586 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14587 op1
= copy_to_mode_reg (mode1
, op1
);
14588 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
14589 op2
= copy_to_mode_reg (mode2
, op2
);
14591 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
14600 /* Expand the dst builtins. */
14602 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
14605 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14606 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14607 tree arg0
, arg1
, arg2
;
14608 machine_mode mode0
, mode1
;
14609 rtx pat
, op0
, op1
, op2
;
14610 const struct builtin_description
*d
;
14613 *expandedp
= false;
14615 /* Handle DST variants. */
14617 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14618 if (d
->code
== fcode
)
14620 arg0
= CALL_EXPR_ARG (exp
, 0);
14621 arg1
= CALL_EXPR_ARG (exp
, 1);
14622 arg2
= CALL_EXPR_ARG (exp
, 2);
14623 op0
= expand_normal (arg0
);
14624 op1
= expand_normal (arg1
);
14625 op2
= expand_normal (arg2
);
14626 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14627 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14629 /* Invalid arguments, bail out before generating bad rtl. */
14630 if (arg0
== error_mark_node
14631 || arg1
== error_mark_node
14632 || arg2
== error_mark_node
)
14637 if (TREE_CODE (arg2
) != INTEGER_CST
14638 || TREE_INT_CST_LOW (arg2
) & ~0x3)
14640 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
14644 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
14645 op0
= copy_to_mode_reg (Pmode
, op0
);
14646 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
14647 op1
= copy_to_mode_reg (mode1
, op1
);
14649 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
14659 /* Expand vec_init builtin. */
14661 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
14663 machine_mode tmode
= TYPE_MODE (type
);
14664 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
14665 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
14667 gcc_assert (VECTOR_MODE_P (tmode
));
14668 gcc_assert (n_elt
== call_expr_nargs (exp
));
14670 if (!target
|| !register_operand (target
, tmode
))
14671 target
= gen_reg_rtx (tmode
);
14673 /* If we have a vector compromised of a single element, such as V1TImode, do
14674 the initialization directly. */
14675 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
14677 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
14678 emit_move_insn (target
, gen_lowpart (tmode
, x
));
14682 rtvec v
= rtvec_alloc (n_elt
);
14684 for (i
= 0; i
< n_elt
; ++i
)
14686 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
14687 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
14690 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
14696 /* Return the integer constant in ARG. Constrain it to be in the range
14697 of the subparts of VEC_TYPE; issue an error if not. */
14700 get_element_number (tree vec_type
, tree arg
)
14702 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
14704 if (!tree_fits_uhwi_p (arg
)
14705 || (elt
= tree_to_uhwi (arg
), elt
> max
))
14707 error ("selector must be an integer constant in the range 0..%wi", max
);
14714 /* Expand vec_set builtin. */
14716 altivec_expand_vec_set_builtin (tree exp
)
14718 machine_mode tmode
, mode1
;
14719 tree arg0
, arg1
, arg2
;
14723 arg0
= CALL_EXPR_ARG (exp
, 0);
14724 arg1
= CALL_EXPR_ARG (exp
, 1);
14725 arg2
= CALL_EXPR_ARG (exp
, 2);
14727 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
14728 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
14729 gcc_assert (VECTOR_MODE_P (tmode
));
14731 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
14732 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
14733 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
14735 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
14736 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
14738 op0
= force_reg (tmode
, op0
);
14739 op1
= force_reg (mode1
, op1
);
14741 rs6000_expand_vector_set (op0
, op1
, elt
);
14746 /* Expand vec_ext builtin. */
14748 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
14750 machine_mode tmode
, mode0
;
14755 arg0
= CALL_EXPR_ARG (exp
, 0);
14756 arg1
= CALL_EXPR_ARG (exp
, 1);
14758 op0
= expand_normal (arg0
);
14759 op1
= expand_normal (arg1
);
14761 if (TREE_CODE (arg1
) == INTEGER_CST
)
14763 unsigned HOST_WIDE_INT elt
;
14764 unsigned HOST_WIDE_INT size
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0
));
14765 unsigned int truncated_selector
;
14766 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
14767 returns low-order bits of INTEGER_CST for modulo indexing. */
14768 elt
= TREE_INT_CST_LOW (arg1
);
14769 truncated_selector
= elt
% size
;
14770 op1
= GEN_INT (truncated_selector
);
14773 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
14774 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
14775 gcc_assert (VECTOR_MODE_P (mode0
));
14777 op0
= force_reg (mode0
, op0
);
14779 if (optimize
|| !target
|| !register_operand (target
, tmode
))
14780 target
= gen_reg_rtx (tmode
);
14782 rs6000_expand_vector_extract (target
, op0
, op1
);
14787 /* Expand the builtin in EXP and store the result in TARGET. Store
14788 true in *EXPANDEDP if we found a builtin to expand. */
14790 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
14792 const struct builtin_description
*d
;
14794 enum insn_code icode
;
14795 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14796 tree arg0
, arg1
, arg2
;
14798 machine_mode tmode
, mode0
;
14799 enum rs6000_builtins fcode
14800 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14802 if (rs6000_overloaded_builtin_p (fcode
))
14805 error ("unresolved overload for Altivec builtin %qF", fndecl
);
14807 /* Given it is invalid, just generate a normal call. */
14808 return expand_call (exp
, target
, false);
14811 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
14819 case ALTIVEC_BUILTIN_STVX_V2DF
:
14820 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
14821 case ALTIVEC_BUILTIN_STVX_V2DI
:
14822 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
14823 case ALTIVEC_BUILTIN_STVX_V4SF
:
14824 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
14825 case ALTIVEC_BUILTIN_STVX
:
14826 case ALTIVEC_BUILTIN_STVX_V4SI
:
14827 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
14828 case ALTIVEC_BUILTIN_STVX_V8HI
:
14829 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
14830 case ALTIVEC_BUILTIN_STVX_V16QI
:
14831 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
14832 case ALTIVEC_BUILTIN_STVEBX
:
14833 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
14834 case ALTIVEC_BUILTIN_STVEHX
:
14835 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
14836 case ALTIVEC_BUILTIN_STVEWX
:
14837 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
14838 case ALTIVEC_BUILTIN_STVXL_V2DF
:
14839 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
14840 case ALTIVEC_BUILTIN_STVXL_V2DI
:
14841 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
14842 case ALTIVEC_BUILTIN_STVXL_V4SF
:
14843 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
14844 case ALTIVEC_BUILTIN_STVXL
:
14845 case ALTIVEC_BUILTIN_STVXL_V4SI
:
14846 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
14847 case ALTIVEC_BUILTIN_STVXL_V8HI
:
14848 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
14849 case ALTIVEC_BUILTIN_STVXL_V16QI
:
14850 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
14852 case ALTIVEC_BUILTIN_STVLX
:
14853 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
14854 case ALTIVEC_BUILTIN_STVLXL
:
14855 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
14856 case ALTIVEC_BUILTIN_STVRX
:
14857 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
14858 case ALTIVEC_BUILTIN_STVRXL
:
14859 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
14861 case P9V_BUILTIN_STXVL
:
14862 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl
, exp
);
14864 case P9V_BUILTIN_XST_LEN_R
:
14865 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r
, exp
);
14867 case VSX_BUILTIN_STXVD2X_V1TI
:
14868 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
14869 case VSX_BUILTIN_STXVD2X_V2DF
:
14870 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
14871 case VSX_BUILTIN_STXVD2X_V2DI
:
14872 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
14873 case VSX_BUILTIN_STXVW4X_V4SF
:
14874 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
14875 case VSX_BUILTIN_STXVW4X_V4SI
:
14876 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
14877 case VSX_BUILTIN_STXVW4X_V8HI
:
14878 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
14879 case VSX_BUILTIN_STXVW4X_V16QI
:
14880 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
14882 /* For the following on big endian, it's ok to use any appropriate
14883 unaligned-supporting store, so use a generic expander. For
14884 little-endian, the exact element-reversing instruction must
14886 case VSX_BUILTIN_ST_ELEMREV_V1TI
:
14888 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v1ti
14889 : CODE_FOR_vsx_st_elemrev_v1ti
);
14890 return altivec_expand_stv_builtin (code
, exp
);
14892 case VSX_BUILTIN_ST_ELEMREV_V2DF
:
14894 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2df
14895 : CODE_FOR_vsx_st_elemrev_v2df
);
14896 return altivec_expand_stv_builtin (code
, exp
);
14898 case VSX_BUILTIN_ST_ELEMREV_V2DI
:
14900 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2di
14901 : CODE_FOR_vsx_st_elemrev_v2di
);
14902 return altivec_expand_stv_builtin (code
, exp
);
14904 case VSX_BUILTIN_ST_ELEMREV_V4SF
:
14906 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4sf
14907 : CODE_FOR_vsx_st_elemrev_v4sf
);
14908 return altivec_expand_stv_builtin (code
, exp
);
14910 case VSX_BUILTIN_ST_ELEMREV_V4SI
:
14912 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4si
14913 : CODE_FOR_vsx_st_elemrev_v4si
);
14914 return altivec_expand_stv_builtin (code
, exp
);
14916 case VSX_BUILTIN_ST_ELEMREV_V8HI
:
14918 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v8hi
14919 : CODE_FOR_vsx_st_elemrev_v8hi
);
14920 return altivec_expand_stv_builtin (code
, exp
);
14922 case VSX_BUILTIN_ST_ELEMREV_V16QI
:
14924 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v16qi
14925 : CODE_FOR_vsx_st_elemrev_v16qi
);
14926 return altivec_expand_stv_builtin (code
, exp
);
14929 case ALTIVEC_BUILTIN_MFVSCR
:
14930 icode
= CODE_FOR_altivec_mfvscr
;
14931 tmode
= insn_data
[icode
].operand
[0].mode
;
14934 || GET_MODE (target
) != tmode
14935 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14936 target
= gen_reg_rtx (tmode
);
14938 pat
= GEN_FCN (icode
) (target
);
14944 case ALTIVEC_BUILTIN_MTVSCR
:
14945 icode
= CODE_FOR_altivec_mtvscr
;
14946 arg0
= CALL_EXPR_ARG (exp
, 0);
14947 op0
= expand_normal (arg0
);
14948 mode0
= insn_data
[icode
].operand
[0].mode
;
14950 /* If we got invalid arguments bail out before generating bad rtl. */
14951 if (arg0
== error_mark_node
)
14954 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
14955 op0
= copy_to_mode_reg (mode0
, op0
);
14957 pat
= GEN_FCN (icode
) (op0
);
14962 case ALTIVEC_BUILTIN_DSSALL
:
14963 emit_insn (gen_altivec_dssall ());
14966 case ALTIVEC_BUILTIN_DSS
:
14967 icode
= CODE_FOR_altivec_dss
;
14968 arg0
= CALL_EXPR_ARG (exp
, 0);
14970 op0
= expand_normal (arg0
);
14971 mode0
= insn_data
[icode
].operand
[0].mode
;
14973 /* If we got invalid arguments bail out before generating bad rtl. */
14974 if (arg0
== error_mark_node
)
14977 if (TREE_CODE (arg0
) != INTEGER_CST
14978 || TREE_INT_CST_LOW (arg0
) & ~0x3)
14980 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14984 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
14985 op0
= copy_to_mode_reg (mode0
, op0
);
14987 emit_insn (gen_altivec_dss (op0
));
14990 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
14991 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
14992 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
14993 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
14994 case VSX_BUILTIN_VEC_INIT_V2DF
:
14995 case VSX_BUILTIN_VEC_INIT_V2DI
:
14996 case VSX_BUILTIN_VEC_INIT_V1TI
:
14997 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
14999 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
15000 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
15001 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
15002 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
15003 case VSX_BUILTIN_VEC_SET_V2DF
:
15004 case VSX_BUILTIN_VEC_SET_V2DI
:
15005 case VSX_BUILTIN_VEC_SET_V1TI
:
15006 return altivec_expand_vec_set_builtin (exp
);
15008 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
15009 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
15010 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
15011 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
15012 case VSX_BUILTIN_VEC_EXT_V2DF
:
15013 case VSX_BUILTIN_VEC_EXT_V2DI
:
15014 case VSX_BUILTIN_VEC_EXT_V1TI
:
15015 return altivec_expand_vec_ext_builtin (exp
, target
);
15017 case P9V_BUILTIN_VEC_EXTRACT4B
:
15018 arg1
= CALL_EXPR_ARG (exp
, 1);
15021 /* Generate a normal call if it is invalid. */
15022 if (arg1
== error_mark_node
)
15023 return expand_call (exp
, target
, false);
15025 if (TREE_CODE (arg1
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg1
) > 12)
15027 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15028 return expand_call (exp
, target
, false);
15032 case P9V_BUILTIN_VEC_INSERT4B
:
15033 arg2
= CALL_EXPR_ARG (exp
, 2);
15036 /* Generate a normal call if it is invalid. */
15037 if (arg2
== error_mark_node
)
15038 return expand_call (exp
, target
, false);
15040 if (TREE_CODE (arg2
) != INTEGER_CST
|| TREE_INT_CST_LOW (arg2
) > 12)
15042 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15043 return expand_call (exp
, target
, false);
15049 /* Fall through. */
15052 /* Expand abs* operations. */
15054 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
15055 if (d
->code
== fcode
)
15056 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
15058 /* Expand the AltiVec predicates. */
15059 d
= bdesc_altivec_preds
;
15060 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
15061 if (d
->code
== fcode
)
15062 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
15064 /* LV* are funky. We initialized them differently. */
15067 case ALTIVEC_BUILTIN_LVSL
:
15068 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
15069 exp
, target
, false);
15070 case ALTIVEC_BUILTIN_LVSR
:
15071 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
15072 exp
, target
, false);
15073 case ALTIVEC_BUILTIN_LVEBX
:
15074 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
15075 exp
, target
, false);
15076 case ALTIVEC_BUILTIN_LVEHX
:
15077 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
15078 exp
, target
, false);
15079 case ALTIVEC_BUILTIN_LVEWX
:
15080 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
15081 exp
, target
, false);
15082 case ALTIVEC_BUILTIN_LVXL_V2DF
:
15083 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
15084 exp
, target
, false);
15085 case ALTIVEC_BUILTIN_LVXL_V2DI
:
15086 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
15087 exp
, target
, false);
15088 case ALTIVEC_BUILTIN_LVXL_V4SF
:
15089 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
15090 exp
, target
, false);
15091 case ALTIVEC_BUILTIN_LVXL
:
15092 case ALTIVEC_BUILTIN_LVXL_V4SI
:
15093 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
15094 exp
, target
, false);
15095 case ALTIVEC_BUILTIN_LVXL_V8HI
:
15096 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
15097 exp
, target
, false);
15098 case ALTIVEC_BUILTIN_LVXL_V16QI
:
15099 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
15100 exp
, target
, false);
15101 case ALTIVEC_BUILTIN_LVX_V1TI
:
15102 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti
,
15103 exp
, target
, false);
15104 case ALTIVEC_BUILTIN_LVX_V2DF
:
15105 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
15106 exp
, target
, false);
15107 case ALTIVEC_BUILTIN_LVX_V2DI
:
15108 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
15109 exp
, target
, false);
15110 case ALTIVEC_BUILTIN_LVX_V4SF
:
15111 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
15112 exp
, target
, false);
15113 case ALTIVEC_BUILTIN_LVX
:
15114 case ALTIVEC_BUILTIN_LVX_V4SI
:
15115 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
15116 exp
, target
, false);
15117 case ALTIVEC_BUILTIN_LVX_V8HI
:
15118 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
15119 exp
, target
, false);
15120 case ALTIVEC_BUILTIN_LVX_V16QI
:
15121 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
15122 exp
, target
, false);
15123 case ALTIVEC_BUILTIN_LVLX
:
15124 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
15125 exp
, target
, true);
15126 case ALTIVEC_BUILTIN_LVLXL
:
15127 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
15128 exp
, target
, true);
15129 case ALTIVEC_BUILTIN_LVRX
:
15130 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
15131 exp
, target
, true);
15132 case ALTIVEC_BUILTIN_LVRXL
:
15133 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
15134 exp
, target
, true);
15135 case VSX_BUILTIN_LXVD2X_V1TI
:
15136 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
15137 exp
, target
, false);
15138 case VSX_BUILTIN_LXVD2X_V2DF
:
15139 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
15140 exp
, target
, false);
15141 case VSX_BUILTIN_LXVD2X_V2DI
:
15142 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
15143 exp
, target
, false);
15144 case VSX_BUILTIN_LXVW4X_V4SF
:
15145 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
15146 exp
, target
, false);
15147 case VSX_BUILTIN_LXVW4X_V4SI
:
15148 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
15149 exp
, target
, false);
15150 case VSX_BUILTIN_LXVW4X_V8HI
:
15151 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
15152 exp
, target
, false);
15153 case VSX_BUILTIN_LXVW4X_V16QI
:
15154 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
15155 exp
, target
, false);
15156 /* For the following on big endian, it's ok to use any appropriate
15157 unaligned-supporting load, so use a generic expander. For
15158 little-endian, the exact element-reversing instruction must
15160 case VSX_BUILTIN_LD_ELEMREV_V2DF
:
15162 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2df
15163 : CODE_FOR_vsx_ld_elemrev_v2df
);
15164 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15166 case VSX_BUILTIN_LD_ELEMREV_V1TI
:
15168 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v1ti
15169 : CODE_FOR_vsx_ld_elemrev_v1ti
);
15170 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15172 case VSX_BUILTIN_LD_ELEMREV_V2DI
:
15174 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2di
15175 : CODE_FOR_vsx_ld_elemrev_v2di
);
15176 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15178 case VSX_BUILTIN_LD_ELEMREV_V4SF
:
15180 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4sf
15181 : CODE_FOR_vsx_ld_elemrev_v4sf
);
15182 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15184 case VSX_BUILTIN_LD_ELEMREV_V4SI
:
15186 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4si
15187 : CODE_FOR_vsx_ld_elemrev_v4si
);
15188 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15190 case VSX_BUILTIN_LD_ELEMREV_V8HI
:
15192 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v8hi
15193 : CODE_FOR_vsx_ld_elemrev_v8hi
);
15194 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15196 case VSX_BUILTIN_LD_ELEMREV_V16QI
:
15198 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v16qi
15199 : CODE_FOR_vsx_ld_elemrev_v16qi
);
15200 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15205 /* Fall through. */
15208 *expandedp
= false;
15212 /* Check whether a builtin function is supported in this target
15215 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode
)
15217 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[fncode
].mask
;
15218 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
15224 /* Raise an error message for a builtin function that is called without the
15225 appropriate target options being set. */
15228 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
15230 size_t uns_fncode
= (size_t) fncode
;
15231 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
15232 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
15234 gcc_assert (name
!= NULL
);
15235 if ((fnmask
& RS6000_BTM_CELL
) != 0)
15236 error ("builtin function %qs is only valid for the cell processor", name
);
15237 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
15238 error ("builtin function %qs requires the %qs option", name
, "-mvsx");
15239 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
15240 error ("builtin function %qs requires the %qs option", name
, "-mhtm");
15241 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
15242 error ("builtin function %qs requires the %qs option", name
, "-maltivec");
15243 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
15244 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
15245 error ("builtin function %qs requires the %qs and %qs options",
15246 name
, "-mhard-dfp", "-mpower8-vector");
15247 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
15248 error ("builtin function %qs requires the %qs option", name
, "-mhard-dfp");
15249 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
15250 error ("builtin function %qs requires the %qs option", name
,
15251 "-mpower8-vector");
15252 else if ((fnmask
& (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
15253 == (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
15254 error ("builtin function %qs requires the %qs and %qs options",
15255 name
, "-mcpu=power9", "-m64");
15256 else if ((fnmask
& RS6000_BTM_P9_VECTOR
) != 0)
15257 error ("builtin function %qs requires the %qs option", name
,
15259 else if ((fnmask
& (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
15260 == (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
15261 error ("builtin function %qs requires the %qs and %qs options",
15262 name
, "-mcpu=power9", "-m64");
15263 else if ((fnmask
& RS6000_BTM_P9_MISC
) == RS6000_BTM_P9_MISC
)
15264 error ("builtin function %qs requires the %qs option", name
,
15266 else if ((fnmask
& RS6000_BTM_LDBL128
) == RS6000_BTM_LDBL128
)
15268 if (!TARGET_HARD_FLOAT
)
15269 error ("builtin function %qs requires the %qs option", name
,
15272 error ("builtin function %qs requires the %qs option", name
,
15273 TARGET_IEEEQUAD
? "-mabi=ibmlongdouble" : "-mlong-double-128");
15275 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
15276 error ("builtin function %qs requires the %qs option", name
,
15278 else if ((fnmask
& RS6000_BTM_FLOAT128_HW
) != 0)
15279 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
15281 else if ((fnmask
& RS6000_BTM_FLOAT128
) != 0)
15282 error ("builtin function %qs requires the %qs option", name
,
15284 else if ((fnmask
& (RS6000_BTM_POPCNTD
| RS6000_BTM_POWERPC64
))
15285 == (RS6000_BTM_POPCNTD
| RS6000_BTM_POWERPC64
))
15286 error ("builtin function %qs requires the %qs (or newer), and "
15287 "%qs or %qs options",
15288 name
, "-mcpu=power7", "-m64", "-mpowerpc64");
15290 error ("builtin function %qs is not supported with the current options",
15294 /* Target hook for early folding of built-ins, shamelessly stolen
15298 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED
,
15299 int n_args ATTRIBUTE_UNUSED
,
15300 tree
*args ATTRIBUTE_UNUSED
,
15301 bool ignore ATTRIBUTE_UNUSED
)
15303 #ifdef SUBTARGET_FOLD_BUILTIN
15304 return SUBTARGET_FOLD_BUILTIN (fndecl
, n_args
, args
, ignore
);
15310 /* Helper function to sort out which built-ins may be valid without having
15313 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code
)
15317 case ALTIVEC_BUILTIN_STVX_V16QI
:
15318 case ALTIVEC_BUILTIN_STVX_V8HI
:
15319 case ALTIVEC_BUILTIN_STVX_V4SI
:
15320 case ALTIVEC_BUILTIN_STVX_V4SF
:
15321 case ALTIVEC_BUILTIN_STVX_V2DI
:
15322 case ALTIVEC_BUILTIN_STVX_V2DF
:
15323 case VSX_BUILTIN_STXVW4X_V16QI
:
15324 case VSX_BUILTIN_STXVW4X_V8HI
:
15325 case VSX_BUILTIN_STXVW4X_V4SF
:
15326 case VSX_BUILTIN_STXVW4X_V4SI
:
15327 case VSX_BUILTIN_STXVD2X_V2DF
:
15328 case VSX_BUILTIN_STXVD2X_V2DI
:
15335 /* Helper function to handle the gimple folding of a vector compare
15336 operation. This sets up true/false vectors, and uses the
15337 VEC_COND_EXPR operation.
15338 CODE indicates which comparison is to be made. (EQ, GT, ...).
15339 TYPE indicates the type of the result. */
15341 fold_build_vec_cmp (tree_code code
, tree type
,
15342 tree arg0
, tree arg1
)
15344 tree cmp_type
= build_same_sized_truth_vector_type (type
);
15345 tree zero_vec
= build_zero_cst (type
);
15346 tree minus_one_vec
= build_minus_one_cst (type
);
15347 tree cmp
= fold_build2 (code
, cmp_type
, arg0
, arg1
);
15348 return fold_build3 (VEC_COND_EXPR
, type
, cmp
, minus_one_vec
, zero_vec
);
15351 /* Helper function to handle the in-between steps for the
15352 vector compare built-ins. */
15354 fold_compare_helper (gimple_stmt_iterator
*gsi
, tree_code code
, gimple
*stmt
)
15356 tree arg0
= gimple_call_arg (stmt
, 0);
15357 tree arg1
= gimple_call_arg (stmt
, 1);
15358 tree lhs
= gimple_call_lhs (stmt
);
15359 tree cmp
= fold_build_vec_cmp (code
, TREE_TYPE (lhs
), arg0
, arg1
);
15360 gimple
*g
= gimple_build_assign (lhs
, cmp
);
15361 gimple_set_location (g
, gimple_location (stmt
));
15362 gsi_replace (gsi
, g
, true);
15365 /* Helper function to map V2DF and V4SF types to their
15366 integral equivalents (V2DI and V4SI). */
15367 tree
map_to_integral_tree_type (tree input_tree_type
)
15369 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type
)))
15370 return input_tree_type
;
15373 if (types_compatible_p (TREE_TYPE (input_tree_type
),
15374 TREE_TYPE (V2DF_type_node
)))
15375 return V2DI_type_node
;
15376 else if (types_compatible_p (TREE_TYPE (input_tree_type
),
15377 TREE_TYPE (V4SF_type_node
)))
15378 return V4SI_type_node
;
15380 gcc_unreachable ();
15384 /* Helper function to handle the vector merge[hl] built-ins. The
15385 implementation difference between h and l versions for this code are in
15386 the values used when building of the permute vector for high word versus
15387 low word merge. The variance is keyed off the use_high parameter. */
15389 fold_mergehl_helper (gimple_stmt_iterator
*gsi
, gimple
*stmt
, int use_high
)
15391 tree arg0
= gimple_call_arg (stmt
, 0);
15392 tree arg1
= gimple_call_arg (stmt
, 1);
15393 tree lhs
= gimple_call_lhs (stmt
);
15394 tree lhs_type
= TREE_TYPE (lhs
);
15395 int n_elts
= TYPE_VECTOR_SUBPARTS (lhs_type
);
15396 int midpoint
= n_elts
/ 2;
15402 /* The permute_type will match the lhs for integral types. For double and
15403 float types, the permute type needs to map to the V2 or V4 type that
15406 permute_type
= map_to_integral_tree_type (lhs_type
);
15407 tree_vector_builder
elts (permute_type
, VECTOR_CST_NELTS (arg0
), 1);
15409 for (int i
= 0; i
< midpoint
; i
++)
15411 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15413 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15414 offset
+ n_elts
+ i
));
15417 tree permute
= elts
.build ();
15419 gimple
*g
= gimple_build_assign (lhs
, VEC_PERM_EXPR
, arg0
, arg1
, permute
);
15420 gimple_set_location (g
, gimple_location (stmt
));
15421 gsi_replace (gsi
, g
, true);
15424 /* Helper function to handle the vector merge[eo] built-ins. */
15426 fold_mergeeo_helper (gimple_stmt_iterator
*gsi
, gimple
*stmt
, int use_odd
)
15428 tree arg0
= gimple_call_arg (stmt
, 0);
15429 tree arg1
= gimple_call_arg (stmt
, 1);
15430 tree lhs
= gimple_call_lhs (stmt
);
15431 tree lhs_type
= TREE_TYPE (lhs
);
15432 int n_elts
= TYPE_VECTOR_SUBPARTS (lhs_type
);
15434 /* The permute_type will match the lhs for integral types. For double and
15435 float types, the permute type needs to map to the V2 or V4 type that
15438 permute_type
= map_to_integral_tree_type (lhs_type
);
15440 tree_vector_builder
elts (permute_type
, VECTOR_CST_NELTS (arg0
), 1);
15442 /* Build the permute vector. */
15443 for (int i
= 0; i
< n_elts
/ 2; i
++)
15445 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15447 elts
.safe_push (build_int_cst (TREE_TYPE (permute_type
),
15448 2*i
+ use_odd
+ n_elts
));
15451 tree permute
= elts
.build ();
15453 gimple
*g
= gimple_build_assign (lhs
, VEC_PERM_EXPR
, arg0
, arg1
, permute
);
15454 gimple_set_location (g
, gimple_location (stmt
));
15455 gsi_replace (gsi
, g
, true);
15458 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15459 a constant, use rs6000_fold_builtin.) */
15462 rs6000_gimple_fold_builtin (gimple_stmt_iterator
*gsi
)
15464 gimple
*stmt
= gsi_stmt (*gsi
);
15465 tree fndecl
= gimple_call_fndecl (stmt
);
15466 gcc_checking_assert (fndecl
&& DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
);
15467 enum rs6000_builtins fn_code
15468 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15469 tree arg0
, arg1
, lhs
, temp
;
15470 enum tree_code bcode
;
15473 size_t uns_fncode
= (size_t) fn_code
;
15474 enum insn_code icode
= rs6000_builtin_info
[uns_fncode
].icode
;
15475 const char *fn_name1
= rs6000_builtin_info
[uns_fncode
].name
;
15476 const char *fn_name2
= (icode
!= CODE_FOR_nothing
)
15477 ? get_insn_name ((int) icode
)
15480 if (TARGET_DEBUG_BUILTIN
)
15481 fprintf (stderr
, "rs6000_gimple_fold_builtin %d %s %s\n",
15482 fn_code
, fn_name1
, fn_name2
);
15484 if (!rs6000_fold_gimple
)
15487 /* Prevent gimple folding for code that does not have a LHS, unless it is
15488 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15489 if (!gimple_call_lhs (stmt
) && !rs6000_builtin_valid_without_lhs (fn_code
))
15492 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15493 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fncode
].mask
;
15494 bool func_valid_p
= (rs6000_builtin_mask
& mask
) == mask
;
15500 /* Flavors of vec_add. We deliberately don't expand
15501 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15502 TImode, resulting in much poorer code generation. */
15503 case ALTIVEC_BUILTIN_VADDUBM
:
15504 case ALTIVEC_BUILTIN_VADDUHM
:
15505 case ALTIVEC_BUILTIN_VADDUWM
:
15506 case P8V_BUILTIN_VADDUDM
:
15507 case ALTIVEC_BUILTIN_VADDFP
:
15508 case VSX_BUILTIN_XVADDDP
:
15511 arg0
= gimple_call_arg (stmt
, 0);
15512 arg1
= gimple_call_arg (stmt
, 1);
15513 lhs
= gimple_call_lhs (stmt
);
15514 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs
)))
15515 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs
))))
15517 /* Ensure the binary operation is performed in a type
15518 that wraps if it is integral type. */
15519 gimple_seq stmts
= NULL
;
15520 tree type
= unsigned_type_for (TREE_TYPE (lhs
));
15521 tree uarg0
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15523 tree uarg1
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15525 tree res
= gimple_build (&stmts
, gimple_location (stmt
), bcode
,
15526 type
, uarg0
, uarg1
);
15527 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15528 g
= gimple_build_assign (lhs
, VIEW_CONVERT_EXPR
,
15529 build1 (VIEW_CONVERT_EXPR
,
15530 TREE_TYPE (lhs
), res
));
15531 gsi_replace (gsi
, g
, true);
15534 g
= gimple_build_assign (lhs
, bcode
, arg0
, arg1
);
15535 gimple_set_location (g
, gimple_location (stmt
));
15536 gsi_replace (gsi
, g
, true);
15538 /* Flavors of vec_sub. We deliberately don't expand
15539 P8V_BUILTIN_VSUBUQM. */
15540 case ALTIVEC_BUILTIN_VSUBUBM
:
15541 case ALTIVEC_BUILTIN_VSUBUHM
:
15542 case ALTIVEC_BUILTIN_VSUBUWM
:
15543 case P8V_BUILTIN_VSUBUDM
:
15544 case ALTIVEC_BUILTIN_VSUBFP
:
15545 case VSX_BUILTIN_XVSUBDP
:
15546 bcode
= MINUS_EXPR
;
15548 case VSX_BUILTIN_XVMULSP
:
15549 case VSX_BUILTIN_XVMULDP
:
15550 arg0
= gimple_call_arg (stmt
, 0);
15551 arg1
= gimple_call_arg (stmt
, 1);
15552 lhs
= gimple_call_lhs (stmt
);
15553 g
= gimple_build_assign (lhs
, MULT_EXPR
, arg0
, arg1
);
15554 gimple_set_location (g
, gimple_location (stmt
));
15555 gsi_replace (gsi
, g
, true);
15557 /* Even element flavors of vec_mul (signed). */
15558 case ALTIVEC_BUILTIN_VMULESB
:
15559 case ALTIVEC_BUILTIN_VMULESH
:
15560 case P8V_BUILTIN_VMULESW
:
15561 /* Even element flavors of vec_mul (unsigned). */
15562 case ALTIVEC_BUILTIN_VMULEUB
:
15563 case ALTIVEC_BUILTIN_VMULEUH
:
15564 case P8V_BUILTIN_VMULEUW
:
15565 arg0
= gimple_call_arg (stmt
, 0);
15566 arg1
= gimple_call_arg (stmt
, 1);
15567 lhs
= gimple_call_lhs (stmt
);
15568 g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_EVEN_EXPR
, arg0
, arg1
);
15569 gimple_set_location (g
, gimple_location (stmt
));
15570 gsi_replace (gsi
, g
, true);
15572 /* Odd element flavors of vec_mul (signed). */
15573 case ALTIVEC_BUILTIN_VMULOSB
:
15574 case ALTIVEC_BUILTIN_VMULOSH
:
15575 case P8V_BUILTIN_VMULOSW
:
15576 /* Odd element flavors of vec_mul (unsigned). */
15577 case ALTIVEC_BUILTIN_VMULOUB
:
15578 case ALTIVEC_BUILTIN_VMULOUH
:
15579 case P8V_BUILTIN_VMULOUW
:
15580 arg0
= gimple_call_arg (stmt
, 0);
15581 arg1
= gimple_call_arg (stmt
, 1);
15582 lhs
= gimple_call_lhs (stmt
);
15583 g
= gimple_build_assign (lhs
, VEC_WIDEN_MULT_ODD_EXPR
, arg0
, arg1
);
15584 gimple_set_location (g
, gimple_location (stmt
));
15585 gsi_replace (gsi
, g
, true);
15587 /* Flavors of vec_div (Integer). */
15588 case VSX_BUILTIN_DIV_V2DI
:
15589 case VSX_BUILTIN_UDIV_V2DI
:
15590 arg0
= gimple_call_arg (stmt
, 0);
15591 arg1
= gimple_call_arg (stmt
, 1);
15592 lhs
= gimple_call_lhs (stmt
);
15593 g
= gimple_build_assign (lhs
, TRUNC_DIV_EXPR
, arg0
, arg1
);
15594 gimple_set_location (g
, gimple_location (stmt
));
15595 gsi_replace (gsi
, g
, true);
15597 /* Flavors of vec_div (Float). */
15598 case VSX_BUILTIN_XVDIVSP
:
15599 case VSX_BUILTIN_XVDIVDP
:
15600 arg0
= gimple_call_arg (stmt
, 0);
15601 arg1
= gimple_call_arg (stmt
, 1);
15602 lhs
= gimple_call_lhs (stmt
);
15603 g
= gimple_build_assign (lhs
, RDIV_EXPR
, arg0
, arg1
);
15604 gimple_set_location (g
, gimple_location (stmt
));
15605 gsi_replace (gsi
, g
, true);
15607 /* Flavors of vec_and. */
15608 case ALTIVEC_BUILTIN_VAND
:
15609 arg0
= gimple_call_arg (stmt
, 0);
15610 arg1
= gimple_call_arg (stmt
, 1);
15611 lhs
= gimple_call_lhs (stmt
);
15612 g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, arg1
);
15613 gimple_set_location (g
, gimple_location (stmt
));
15614 gsi_replace (gsi
, g
, true);
15616 /* Flavors of vec_andc. */
15617 case ALTIVEC_BUILTIN_VANDC
:
15618 arg0
= gimple_call_arg (stmt
, 0);
15619 arg1
= gimple_call_arg (stmt
, 1);
15620 lhs
= gimple_call_lhs (stmt
);
15621 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15622 g
= gimple_build_assign (temp
, BIT_NOT_EXPR
, arg1
);
15623 gimple_set_location (g
, gimple_location (stmt
));
15624 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15625 g
= gimple_build_assign (lhs
, BIT_AND_EXPR
, arg0
, temp
);
15626 gimple_set_location (g
, gimple_location (stmt
));
15627 gsi_replace (gsi
, g
, true);
15629 /* Flavors of vec_nand. */
15630 case P8V_BUILTIN_VEC_NAND
:
15631 case P8V_BUILTIN_NAND_V16QI
:
15632 case P8V_BUILTIN_NAND_V8HI
:
15633 case P8V_BUILTIN_NAND_V4SI
:
15634 case P8V_BUILTIN_NAND_V4SF
:
15635 case P8V_BUILTIN_NAND_V2DF
:
15636 case P8V_BUILTIN_NAND_V2DI
:
15637 arg0
= gimple_call_arg (stmt
, 0);
15638 arg1
= gimple_call_arg (stmt
, 1);
15639 lhs
= gimple_call_lhs (stmt
);
15640 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15641 g
= gimple_build_assign (temp
, BIT_AND_EXPR
, arg0
, arg1
);
15642 gimple_set_location (g
, gimple_location (stmt
));
15643 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15644 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15645 gimple_set_location (g
, gimple_location (stmt
));
15646 gsi_replace (gsi
, g
, true);
15648 /* Flavors of vec_or. */
15649 case ALTIVEC_BUILTIN_VOR
:
15650 arg0
= gimple_call_arg (stmt
, 0);
15651 arg1
= gimple_call_arg (stmt
, 1);
15652 lhs
= gimple_call_lhs (stmt
);
15653 g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, arg1
);
15654 gimple_set_location (g
, gimple_location (stmt
));
15655 gsi_replace (gsi
, g
, true);
15657 /* flavors of vec_orc. */
15658 case P8V_BUILTIN_ORC_V16QI
:
15659 case P8V_BUILTIN_ORC_V8HI
:
15660 case P8V_BUILTIN_ORC_V4SI
:
15661 case P8V_BUILTIN_ORC_V4SF
:
15662 case P8V_BUILTIN_ORC_V2DF
:
15663 case P8V_BUILTIN_ORC_V2DI
:
15664 arg0
= gimple_call_arg (stmt
, 0);
15665 arg1
= gimple_call_arg (stmt
, 1);
15666 lhs
= gimple_call_lhs (stmt
);
15667 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15668 g
= gimple_build_assign (temp
, BIT_NOT_EXPR
, arg1
);
15669 gimple_set_location (g
, gimple_location (stmt
));
15670 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15671 g
= gimple_build_assign (lhs
, BIT_IOR_EXPR
, arg0
, temp
);
15672 gimple_set_location (g
, gimple_location (stmt
));
15673 gsi_replace (gsi
, g
, true);
15675 /* Flavors of vec_xor. */
15676 case ALTIVEC_BUILTIN_VXOR
:
15677 arg0
= gimple_call_arg (stmt
, 0);
15678 arg1
= gimple_call_arg (stmt
, 1);
15679 lhs
= gimple_call_lhs (stmt
);
15680 g
= gimple_build_assign (lhs
, BIT_XOR_EXPR
, arg0
, arg1
);
15681 gimple_set_location (g
, gimple_location (stmt
));
15682 gsi_replace (gsi
, g
, true);
15684 /* Flavors of vec_nor. */
15685 case ALTIVEC_BUILTIN_VNOR
:
15686 arg0
= gimple_call_arg (stmt
, 0);
15687 arg1
= gimple_call_arg (stmt
, 1);
15688 lhs
= gimple_call_lhs (stmt
);
15689 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15690 g
= gimple_build_assign (temp
, BIT_IOR_EXPR
, arg0
, arg1
);
15691 gimple_set_location (g
, gimple_location (stmt
));
15692 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15693 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15694 gimple_set_location (g
, gimple_location (stmt
));
15695 gsi_replace (gsi
, g
, true);
15697 /* flavors of vec_abs. */
15698 case ALTIVEC_BUILTIN_ABS_V16QI
:
15699 case ALTIVEC_BUILTIN_ABS_V8HI
:
15700 case ALTIVEC_BUILTIN_ABS_V4SI
:
15701 case ALTIVEC_BUILTIN_ABS_V4SF
:
15702 case P8V_BUILTIN_ABS_V2DI
:
15703 case VSX_BUILTIN_XVABSDP
:
15704 arg0
= gimple_call_arg (stmt
, 0);
15705 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0
)))
15706 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0
))))
15708 lhs
= gimple_call_lhs (stmt
);
15709 g
= gimple_build_assign (lhs
, ABS_EXPR
, arg0
);
15710 gimple_set_location (g
, gimple_location (stmt
));
15711 gsi_replace (gsi
, g
, true);
15713 /* flavors of vec_min. */
15714 case VSX_BUILTIN_XVMINDP
:
15715 case P8V_BUILTIN_VMINSD
:
15716 case P8V_BUILTIN_VMINUD
:
15717 case ALTIVEC_BUILTIN_VMINSB
:
15718 case ALTIVEC_BUILTIN_VMINSH
:
15719 case ALTIVEC_BUILTIN_VMINSW
:
15720 case ALTIVEC_BUILTIN_VMINUB
:
15721 case ALTIVEC_BUILTIN_VMINUH
:
15722 case ALTIVEC_BUILTIN_VMINUW
:
15723 case ALTIVEC_BUILTIN_VMINFP
:
15724 arg0
= gimple_call_arg (stmt
, 0);
15725 arg1
= gimple_call_arg (stmt
, 1);
15726 lhs
= gimple_call_lhs (stmt
);
15727 g
= gimple_build_assign (lhs
, MIN_EXPR
, arg0
, arg1
);
15728 gimple_set_location (g
, gimple_location (stmt
));
15729 gsi_replace (gsi
, g
, true);
15731 /* flavors of vec_max. */
15732 case VSX_BUILTIN_XVMAXDP
:
15733 case P8V_BUILTIN_VMAXSD
:
15734 case P8V_BUILTIN_VMAXUD
:
15735 case ALTIVEC_BUILTIN_VMAXSB
:
15736 case ALTIVEC_BUILTIN_VMAXSH
:
15737 case ALTIVEC_BUILTIN_VMAXSW
:
15738 case ALTIVEC_BUILTIN_VMAXUB
:
15739 case ALTIVEC_BUILTIN_VMAXUH
:
15740 case ALTIVEC_BUILTIN_VMAXUW
:
15741 case ALTIVEC_BUILTIN_VMAXFP
:
15742 arg0
= gimple_call_arg (stmt
, 0);
15743 arg1
= gimple_call_arg (stmt
, 1);
15744 lhs
= gimple_call_lhs (stmt
);
15745 g
= gimple_build_assign (lhs
, MAX_EXPR
, arg0
, arg1
);
15746 gimple_set_location (g
, gimple_location (stmt
));
15747 gsi_replace (gsi
, g
, true);
15749 /* Flavors of vec_eqv. */
15750 case P8V_BUILTIN_EQV_V16QI
:
15751 case P8V_BUILTIN_EQV_V8HI
:
15752 case P8V_BUILTIN_EQV_V4SI
:
15753 case P8V_BUILTIN_EQV_V4SF
:
15754 case P8V_BUILTIN_EQV_V2DF
:
15755 case P8V_BUILTIN_EQV_V2DI
:
15756 arg0
= gimple_call_arg (stmt
, 0);
15757 arg1
= gimple_call_arg (stmt
, 1);
15758 lhs
= gimple_call_lhs (stmt
);
15759 temp
= create_tmp_reg_or_ssa_name (TREE_TYPE (arg1
));
15760 g
= gimple_build_assign (temp
, BIT_XOR_EXPR
, arg0
, arg1
);
15761 gimple_set_location (g
, gimple_location (stmt
));
15762 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15763 g
= gimple_build_assign (lhs
, BIT_NOT_EXPR
, temp
);
15764 gimple_set_location (g
, gimple_location (stmt
));
15765 gsi_replace (gsi
, g
, true);
15767 /* Flavors of vec_rotate_left. */
15768 case ALTIVEC_BUILTIN_VRLB
:
15769 case ALTIVEC_BUILTIN_VRLH
:
15770 case ALTIVEC_BUILTIN_VRLW
:
15771 case P8V_BUILTIN_VRLD
:
15772 arg0
= gimple_call_arg (stmt
, 0);
15773 arg1
= gimple_call_arg (stmt
, 1);
15774 lhs
= gimple_call_lhs (stmt
);
15775 g
= gimple_build_assign (lhs
, LROTATE_EXPR
, arg0
, arg1
);
15776 gimple_set_location (g
, gimple_location (stmt
));
15777 gsi_replace (gsi
, g
, true);
15779 /* Flavors of vector shift right algebraic.
15780 vec_sra{b,h,w} -> vsra{b,h,w}. */
15781 case ALTIVEC_BUILTIN_VSRAB
:
15782 case ALTIVEC_BUILTIN_VSRAH
:
15783 case ALTIVEC_BUILTIN_VSRAW
:
15784 case P8V_BUILTIN_VSRAD
:
15786 arg0
= gimple_call_arg (stmt
, 0);
15787 arg1
= gimple_call_arg (stmt
, 1);
15788 lhs
= gimple_call_lhs (stmt
);
15789 tree arg1_type
= TREE_TYPE (arg1
);
15790 tree unsigned_arg1_type
= unsigned_type_for (TREE_TYPE (arg1
));
15791 tree unsigned_element_type
= unsigned_type_for (TREE_TYPE (arg1_type
));
15792 location_t loc
= gimple_location (stmt
);
15793 /* Force arg1 into the range valid matching the arg0 type. */
15794 /* Build a vector consisting of the max valid bit-size values. */
15795 int n_elts
= VECTOR_CST_NELTS (arg1
);
15796 tree element_size
= build_int_cst (unsigned_element_type
,
15798 tree_vector_builder
elts (unsigned_arg1_type
, n_elts
, 1);
15799 for (int i
= 0; i
< n_elts
; i
++)
15800 elts
.safe_push (element_size
);
15801 tree modulo_tree
= elts
.build ();
15802 /* Modulo the provided shift value against that vector. */
15803 gimple_seq stmts
= NULL
;
15804 tree unsigned_arg1
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15805 unsigned_arg1_type
, arg1
);
15806 tree new_arg1
= gimple_build (&stmts
, loc
, TRUNC_MOD_EXPR
,
15807 unsigned_arg1_type
, unsigned_arg1
,
15809 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15810 /* And finally, do the shift. */
15811 g
= gimple_build_assign (lhs
, RSHIFT_EXPR
, arg0
, new_arg1
);
15812 gimple_set_location (g
, loc
);
15813 gsi_replace (gsi
, g
, true);
15816 /* Flavors of vector shift left.
15817 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15818 case ALTIVEC_BUILTIN_VSLB
:
15819 case ALTIVEC_BUILTIN_VSLH
:
15820 case ALTIVEC_BUILTIN_VSLW
:
15821 case P8V_BUILTIN_VSLD
:
15824 gimple_seq stmts
= NULL
;
15825 arg0
= gimple_call_arg (stmt
, 0);
15826 tree arg0_type
= TREE_TYPE (arg0
);
15827 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type
))
15828 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type
)))
15830 arg1
= gimple_call_arg (stmt
, 1);
15831 tree arg1_type
= TREE_TYPE (arg1
);
15832 tree unsigned_arg1_type
= unsigned_type_for (TREE_TYPE (arg1
));
15833 tree unsigned_element_type
= unsigned_type_for (TREE_TYPE (arg1_type
));
15834 loc
= gimple_location (stmt
);
15835 lhs
= gimple_call_lhs (stmt
);
15836 /* Force arg1 into the range valid matching the arg0 type. */
15837 /* Build a vector consisting of the max valid bit-size values. */
15838 int n_elts
= VECTOR_CST_NELTS (arg1
);
15839 int tree_size_in_bits
= TREE_INT_CST_LOW (size_in_bytes (arg1_type
))
15841 tree element_size
= build_int_cst (unsigned_element_type
,
15842 tree_size_in_bits
/ n_elts
);
15843 tree_vector_builder
elts (unsigned_type_for (arg1_type
), n_elts
, 1);
15844 for (int i
= 0; i
< n_elts
; i
++)
15845 elts
.safe_push (element_size
);
15846 tree modulo_tree
= elts
.build ();
15847 /* Modulo the provided shift value against that vector. */
15848 tree unsigned_arg1
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15849 unsigned_arg1_type
, arg1
);
15850 tree new_arg1
= gimple_build (&stmts
, loc
, TRUNC_MOD_EXPR
,
15851 unsigned_arg1_type
, unsigned_arg1
,
15853 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15854 /* And finally, do the shift. */
15855 g
= gimple_build_assign (lhs
, LSHIFT_EXPR
, arg0
, new_arg1
);
15856 gimple_set_location (g
, gimple_location (stmt
));
15857 gsi_replace (gsi
, g
, true);
15860 /* Flavors of vector shift right. */
15861 case ALTIVEC_BUILTIN_VSRB
:
15862 case ALTIVEC_BUILTIN_VSRH
:
15863 case ALTIVEC_BUILTIN_VSRW
:
15864 case P8V_BUILTIN_VSRD
:
15866 arg0
= gimple_call_arg (stmt
, 0);
15867 arg1
= gimple_call_arg (stmt
, 1);
15868 lhs
= gimple_call_lhs (stmt
);
15869 tree arg1_type
= TREE_TYPE (arg1
);
15870 tree unsigned_arg1_type
= unsigned_type_for (TREE_TYPE (arg1
));
15871 tree unsigned_element_type
= unsigned_type_for (TREE_TYPE (arg1_type
));
15872 location_t loc
= gimple_location (stmt
);
15873 gimple_seq stmts
= NULL
;
15874 /* Convert arg0 to unsigned. */
15876 = gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15877 unsigned_type_for (TREE_TYPE (arg0
)), arg0
);
15878 /* Force arg1 into the range valid matching the arg0 type. */
15879 /* Build a vector consisting of the max valid bit-size values. */
15880 int n_elts
= VECTOR_CST_NELTS (arg1
);
15881 tree element_size
= build_int_cst (unsigned_element_type
,
15883 tree_vector_builder
elts (unsigned_arg1_type
, n_elts
, 1);
15884 for (int i
= 0; i
< n_elts
; i
++)
15885 elts
.safe_push (element_size
);
15886 tree modulo_tree
= elts
.build ();
15887 /* Modulo the provided shift value against that vector. */
15888 tree unsigned_arg1
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
,
15889 unsigned_arg1_type
, arg1
);
15890 tree new_arg1
= gimple_build (&stmts
, loc
, TRUNC_MOD_EXPR
,
15891 unsigned_arg1_type
, unsigned_arg1
,
15893 /* Do the shift. */
15895 = gimple_build (&stmts
, RSHIFT_EXPR
,
15896 TREE_TYPE (arg0_unsigned
), arg0_unsigned
, new_arg1
);
15897 /* Convert result back to the lhs type. */
15898 res
= gimple_build (&stmts
, VIEW_CONVERT_EXPR
, TREE_TYPE (lhs
), res
);
15899 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15900 update_call_from_tree (gsi
, res
);
15903 /* Vector loads. */
15904 case ALTIVEC_BUILTIN_LVX_V16QI
:
15905 case ALTIVEC_BUILTIN_LVX_V8HI
:
15906 case ALTIVEC_BUILTIN_LVX_V4SI
:
15907 case ALTIVEC_BUILTIN_LVX_V4SF
:
15908 case ALTIVEC_BUILTIN_LVX_V2DI
:
15909 case ALTIVEC_BUILTIN_LVX_V2DF
:
15910 case ALTIVEC_BUILTIN_LVX_V1TI
:
15912 arg0
= gimple_call_arg (stmt
, 0); // offset
15913 arg1
= gimple_call_arg (stmt
, 1); // address
15914 lhs
= gimple_call_lhs (stmt
);
15915 location_t loc
= gimple_location (stmt
);
15916 /* Since arg1 may be cast to a different type, just use ptr_type_node
15917 here instead of trying to enforce TBAA on pointer types. */
15918 tree arg1_type
= ptr_type_node
;
15919 tree lhs_type
= TREE_TYPE (lhs
);
15920 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15921 the tree using the value from arg0. The resulting type will match
15922 the type of arg1. */
15923 gimple_seq stmts
= NULL
;
15924 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg0
);
15925 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15926 arg1_type
, arg1
, temp_offset
);
15927 /* Mask off any lower bits from the address. */
15928 tree aligned_addr
= gimple_build (&stmts
, loc
, BIT_AND_EXPR
,
15929 arg1_type
, temp_addr
,
15930 build_int_cst (arg1_type
, -16));
15931 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15932 if (!is_gimple_mem_ref_addr (aligned_addr
))
15934 tree t
= make_ssa_name (TREE_TYPE (aligned_addr
));
15935 gimple
*g
= gimple_build_assign (t
, aligned_addr
);
15936 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15939 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15940 take an offset, but since we've already incorporated the offset
15941 above, here we just pass in a zero. */
15943 = gimple_build_assign (lhs
, build2 (MEM_REF
, lhs_type
, aligned_addr
,
15944 build_int_cst (arg1_type
, 0)));
15945 gimple_set_location (g
, loc
);
15946 gsi_replace (gsi
, g
, true);
15949 /* Vector stores. */
15950 case ALTIVEC_BUILTIN_STVX_V16QI
:
15951 case ALTIVEC_BUILTIN_STVX_V8HI
:
15952 case ALTIVEC_BUILTIN_STVX_V4SI
:
15953 case ALTIVEC_BUILTIN_STVX_V4SF
:
15954 case ALTIVEC_BUILTIN_STVX_V2DI
:
15955 case ALTIVEC_BUILTIN_STVX_V2DF
:
15957 arg0
= gimple_call_arg (stmt
, 0); /* Value to be stored. */
15958 arg1
= gimple_call_arg (stmt
, 1); /* Offset. */
15959 tree arg2
= gimple_call_arg (stmt
, 2); /* Store-to address. */
15960 location_t loc
= gimple_location (stmt
);
15961 tree arg0_type
= TREE_TYPE (arg0
);
15962 /* Use ptr_type_node (no TBAA) for the arg2_type.
15963 FIXME: (Richard) "A proper fix would be to transition this type as
15964 seen from the frontend to GIMPLE, for example in a similar way we
15965 do for MEM_REFs by piggy-backing that on an extra argument, a
15966 constant zero pointer of the alias pointer type to use (which would
15967 also serve as a type indicator of the store itself). I'd use a
15968 target specific internal function for this (not sure if we can have
15969 those target specific, but I guess if it's folded away then that's
15970 fine) and get away with the overload set." */
15971 tree arg2_type
= ptr_type_node
;
15972 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15973 the tree using the value from arg0. The resulting type will match
15974 the type of arg2. */
15975 gimple_seq stmts
= NULL
;
15976 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg1
);
15977 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
15978 arg2_type
, arg2
, temp_offset
);
15979 /* Mask off any lower bits from the address. */
15980 tree aligned_addr
= gimple_build (&stmts
, loc
, BIT_AND_EXPR
,
15981 arg2_type
, temp_addr
,
15982 build_int_cst (arg2_type
, -16));
15983 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
15984 if (!is_gimple_mem_ref_addr (aligned_addr
))
15986 tree t
= make_ssa_name (TREE_TYPE (aligned_addr
));
15987 gimple
*g
= gimple_build_assign (t
, aligned_addr
);
15988 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
15991 /* The desired gimple result should be similar to:
15992 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15994 = gimple_build_assign (build2 (MEM_REF
, arg0_type
, aligned_addr
,
15995 build_int_cst (arg2_type
, 0)), arg0
);
15996 gimple_set_location (g
, loc
);
15997 gsi_replace (gsi
, g
, true);
16001 /* unaligned Vector loads. */
16002 case VSX_BUILTIN_LXVW4X_V16QI
:
16003 case VSX_BUILTIN_LXVW4X_V8HI
:
16004 case VSX_BUILTIN_LXVW4X_V4SF
:
16005 case VSX_BUILTIN_LXVW4X_V4SI
:
16006 case VSX_BUILTIN_LXVD2X_V2DF
:
16007 case VSX_BUILTIN_LXVD2X_V2DI
:
16009 arg0
= gimple_call_arg (stmt
, 0); // offset
16010 arg1
= gimple_call_arg (stmt
, 1); // address
16011 lhs
= gimple_call_lhs (stmt
);
16012 location_t loc
= gimple_location (stmt
);
16013 /* Since arg1 may be cast to a different type, just use ptr_type_node
16014 here instead of trying to enforce TBAA on pointer types. */
16015 tree arg1_type
= ptr_type_node
;
16016 tree lhs_type
= TREE_TYPE (lhs
);
16017 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
16018 required alignment (power) is 4 bytes regardless of data type. */
16019 tree align_ltype
= build_aligned_type (lhs_type
, 4);
16020 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16021 the tree using the value from arg0. The resulting type will match
16022 the type of arg1. */
16023 gimple_seq stmts
= NULL
;
16024 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg0
);
16025 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
16026 arg1_type
, arg1
, temp_offset
);
16027 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
16028 if (!is_gimple_mem_ref_addr (temp_addr
))
16030 tree t
= make_ssa_name (TREE_TYPE (temp_addr
));
16031 gimple
*g
= gimple_build_assign (t
, temp_addr
);
16032 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
16035 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
16036 take an offset, but since we've already incorporated the offset
16037 above, here we just pass in a zero. */
16039 g
= gimple_build_assign (lhs
, build2 (MEM_REF
, align_ltype
, temp_addr
,
16040 build_int_cst (arg1_type
, 0)));
16041 gimple_set_location (g
, loc
);
16042 gsi_replace (gsi
, g
, true);
16046 /* unaligned Vector stores. */
16047 case VSX_BUILTIN_STXVW4X_V16QI
:
16048 case VSX_BUILTIN_STXVW4X_V8HI
:
16049 case VSX_BUILTIN_STXVW4X_V4SF
:
16050 case VSX_BUILTIN_STXVW4X_V4SI
:
16051 case VSX_BUILTIN_STXVD2X_V2DF
:
16052 case VSX_BUILTIN_STXVD2X_V2DI
:
16054 arg0
= gimple_call_arg (stmt
, 0); /* Value to be stored. */
16055 arg1
= gimple_call_arg (stmt
, 1); /* Offset. */
16056 tree arg2
= gimple_call_arg (stmt
, 2); /* Store-to address. */
16057 location_t loc
= gimple_location (stmt
);
16058 tree arg0_type
= TREE_TYPE (arg0
);
16059 /* Use ptr_type_node (no TBAA) for the arg2_type. */
16060 tree arg2_type
= ptr_type_node
;
16061 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
16062 required alignment (power) is 4 bytes regardless of data type. */
16063 tree align_stype
= build_aligned_type (arg0_type
, 4);
16064 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16065 the tree using the value from arg1. */
16066 gimple_seq stmts
= NULL
;
16067 tree temp_offset
= gimple_convert (&stmts
, loc
, sizetype
, arg1
);
16068 tree temp_addr
= gimple_build (&stmts
, loc
, POINTER_PLUS_EXPR
,
16069 arg2_type
, arg2
, temp_offset
);
16070 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
16071 if (!is_gimple_mem_ref_addr (temp_addr
))
16073 tree t
= make_ssa_name (TREE_TYPE (temp_addr
));
16074 gimple
*g
= gimple_build_assign (t
, temp_addr
);
16075 gsi_insert_before (gsi
, g
, GSI_SAME_STMT
);
16079 g
= gimple_build_assign (build2 (MEM_REF
, align_stype
, temp_addr
,
16080 build_int_cst (arg2_type
, 0)), arg0
);
16081 gimple_set_location (g
, loc
);
16082 gsi_replace (gsi
, g
, true);
16086 /* Vector Fused multiply-add (fma). */
16087 case ALTIVEC_BUILTIN_VMADDFP
:
16088 case VSX_BUILTIN_XVMADDDP
:
16089 case ALTIVEC_BUILTIN_VMLADDUHM
:
16091 arg0
= gimple_call_arg (stmt
, 0);
16092 arg1
= gimple_call_arg (stmt
, 1);
16093 tree arg2
= gimple_call_arg (stmt
, 2);
16094 lhs
= gimple_call_lhs (stmt
);
16095 gcall
*g
= gimple_build_call_internal (IFN_FMA
, 3, arg0
, arg1
, arg2
);
16096 gimple_call_set_lhs (g
, lhs
);
16097 gimple_call_set_nothrow (g
, true);
16098 gimple_set_location (g
, gimple_location (stmt
));
16099 gsi_replace (gsi
, g
, true);
16103 /* Vector compares; EQ, NE, GE, GT, LE. */
16104 case ALTIVEC_BUILTIN_VCMPEQUB
:
16105 case ALTIVEC_BUILTIN_VCMPEQUH
:
16106 case ALTIVEC_BUILTIN_VCMPEQUW
:
16107 case P8V_BUILTIN_VCMPEQUD
:
16108 fold_compare_helper (gsi
, EQ_EXPR
, stmt
);
16111 case P9V_BUILTIN_CMPNEB
:
16112 case P9V_BUILTIN_CMPNEH
:
16113 case P9V_BUILTIN_CMPNEW
:
16114 fold_compare_helper (gsi
, NE_EXPR
, stmt
);
16117 case VSX_BUILTIN_CMPGE_16QI
:
16118 case VSX_BUILTIN_CMPGE_U16QI
:
16119 case VSX_BUILTIN_CMPGE_8HI
:
16120 case VSX_BUILTIN_CMPGE_U8HI
:
16121 case VSX_BUILTIN_CMPGE_4SI
:
16122 case VSX_BUILTIN_CMPGE_U4SI
:
16123 case VSX_BUILTIN_CMPGE_2DI
:
16124 case VSX_BUILTIN_CMPGE_U2DI
:
16125 fold_compare_helper (gsi
, GE_EXPR
, stmt
);
16128 case ALTIVEC_BUILTIN_VCMPGTSB
:
16129 case ALTIVEC_BUILTIN_VCMPGTUB
:
16130 case ALTIVEC_BUILTIN_VCMPGTSH
:
16131 case ALTIVEC_BUILTIN_VCMPGTUH
:
16132 case ALTIVEC_BUILTIN_VCMPGTSW
:
16133 case ALTIVEC_BUILTIN_VCMPGTUW
:
16134 case P8V_BUILTIN_VCMPGTUD
:
16135 case P8V_BUILTIN_VCMPGTSD
:
16136 fold_compare_helper (gsi
, GT_EXPR
, stmt
);
16139 case VSX_BUILTIN_CMPLE_16QI
:
16140 case VSX_BUILTIN_CMPLE_U16QI
:
16141 case VSX_BUILTIN_CMPLE_8HI
:
16142 case VSX_BUILTIN_CMPLE_U8HI
:
16143 case VSX_BUILTIN_CMPLE_4SI
:
16144 case VSX_BUILTIN_CMPLE_U4SI
:
16145 case VSX_BUILTIN_CMPLE_2DI
:
16146 case VSX_BUILTIN_CMPLE_U2DI
:
16147 fold_compare_helper (gsi
, LE_EXPR
, stmt
);
16150 /* flavors of vec_splat_[us]{8,16,32}. */
16151 case ALTIVEC_BUILTIN_VSPLTISB
:
16152 case ALTIVEC_BUILTIN_VSPLTISH
:
16153 case ALTIVEC_BUILTIN_VSPLTISW
:
16155 arg0
= gimple_call_arg (stmt
, 0);
16156 lhs
= gimple_call_lhs (stmt
);
16158 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
16159 5-bit signed constant in range -16 to +15. */
16160 if (TREE_CODE (arg0
) != INTEGER_CST
16161 || !IN_RANGE (TREE_INT_CST_LOW (arg0
), -16, 15))
16163 gimple_seq stmts
= NULL
;
16164 location_t loc
= gimple_location (stmt
);
16165 tree splat_value
= gimple_convert (&stmts
, loc
,
16166 TREE_TYPE (TREE_TYPE (lhs
)), arg0
);
16167 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
16168 tree splat_tree
= build_vector_from_val (TREE_TYPE (lhs
), splat_value
);
16169 g
= gimple_build_assign (lhs
, splat_tree
);
16170 gimple_set_location (g
, gimple_location (stmt
));
16171 gsi_replace (gsi
, g
, true);
16175 /* Flavors of vec_splat. */
16176 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
16177 case ALTIVEC_BUILTIN_VSPLTB
:
16178 case ALTIVEC_BUILTIN_VSPLTH
:
16179 case ALTIVEC_BUILTIN_VSPLTW
:
16180 case VSX_BUILTIN_XXSPLTD_V2DI
:
16181 case VSX_BUILTIN_XXSPLTD_V2DF
:
16183 arg0
= gimple_call_arg (stmt
, 0); /* input vector. */
16184 arg1
= gimple_call_arg (stmt
, 1); /* index into arg0. */
16185 /* Only fold the vec_splat_*() if arg1 is both a constant value and
16186 is a valid index into the arg0 vector. */
16187 unsigned int n_elts
= VECTOR_CST_NELTS (arg0
);
16188 if (TREE_CODE (arg1
) != INTEGER_CST
16189 || TREE_INT_CST_LOW (arg1
) > (n_elts
-1))
16191 lhs
= gimple_call_lhs (stmt
);
16192 tree lhs_type
= TREE_TYPE (lhs
);
16193 tree arg0_type
= TREE_TYPE (arg0
);
16195 if (TREE_CODE (arg0
) == VECTOR_CST
)
16196 splat
= VECTOR_CST_ELT (arg0
, TREE_INT_CST_LOW (arg1
));
16199 /* Determine (in bits) the length and start location of the
16200 splat value for a call to the tree_vec_extract helper. */
16201 int splat_elem_size
= TREE_INT_CST_LOW (size_in_bytes (arg0_type
))
16202 * BITS_PER_UNIT
/ n_elts
;
16203 int splat_start_bit
= TREE_INT_CST_LOW (arg1
) * splat_elem_size
;
16204 tree len
= build_int_cst (bitsizetype
, splat_elem_size
);
16205 tree start
= build_int_cst (bitsizetype
, splat_start_bit
);
16206 splat
= tree_vec_extract (gsi
, TREE_TYPE (lhs_type
), arg0
,
16209 /* And finally, build the new vector. */
16210 tree splat_tree
= build_vector_from_val (lhs_type
, splat
);
16211 g
= gimple_build_assign (lhs
, splat_tree
);
16212 gimple_set_location (g
, gimple_location (stmt
));
16213 gsi_replace (gsi
, g
, true);
16217 /* vec_mergel (integrals). */
16218 case ALTIVEC_BUILTIN_VMRGLH
:
16219 case ALTIVEC_BUILTIN_VMRGLW
:
16220 case VSX_BUILTIN_XXMRGLW_4SI
:
16221 case ALTIVEC_BUILTIN_VMRGLB
:
16222 case VSX_BUILTIN_VEC_MERGEL_V2DI
:
16223 case VSX_BUILTIN_XXMRGLW_4SF
:
16224 case VSX_BUILTIN_VEC_MERGEL_V2DF
:
16225 fold_mergehl_helper (gsi
, stmt
, 1);
16227 /* vec_mergeh (integrals). */
16228 case ALTIVEC_BUILTIN_VMRGHH
:
16229 case ALTIVEC_BUILTIN_VMRGHW
:
16230 case VSX_BUILTIN_XXMRGHW_4SI
:
16231 case ALTIVEC_BUILTIN_VMRGHB
:
16232 case VSX_BUILTIN_VEC_MERGEH_V2DI
:
16233 case VSX_BUILTIN_XXMRGHW_4SF
:
16234 case VSX_BUILTIN_VEC_MERGEH_V2DF
:
16235 fold_mergehl_helper (gsi
, stmt
, 0);
16238 /* Flavors of vec_mergee. */
16239 case P8V_BUILTIN_VMRGEW_V4SI
:
16240 case P8V_BUILTIN_VMRGEW_V2DI
:
16241 case P8V_BUILTIN_VMRGEW_V4SF
:
16242 case P8V_BUILTIN_VMRGEW_V2DF
:
16243 fold_mergeeo_helper (gsi
, stmt
, 0);
16245 /* Flavors of vec_mergeo. */
16246 case P8V_BUILTIN_VMRGOW_V4SI
:
16247 case P8V_BUILTIN_VMRGOW_V2DI
:
16248 case P8V_BUILTIN_VMRGOW_V4SF
:
16249 case P8V_BUILTIN_VMRGOW_V2DF
:
16250 fold_mergeeo_helper (gsi
, stmt
, 1);
16253 /* d = vec_pack (a, b) */
16254 case P8V_BUILTIN_VPKUDUM
:
16255 case ALTIVEC_BUILTIN_VPKUHUM
:
16256 case ALTIVEC_BUILTIN_VPKUWUM
:
16258 arg0
= gimple_call_arg (stmt
, 0);
16259 arg1
= gimple_call_arg (stmt
, 1);
16260 lhs
= gimple_call_lhs (stmt
);
16261 gimple
*g
= gimple_build_assign (lhs
, VEC_PACK_TRUNC_EXPR
, arg0
, arg1
);
16262 gimple_set_location (g
, gimple_location (stmt
));
16263 gsi_replace (gsi
, g
, true);
16267 /* d = vec_unpackh (a) */
16268 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
16269 in this code is sensitive to endian-ness, and needs to be inverted to
16270 handle both LE and BE targets. */
16271 case ALTIVEC_BUILTIN_VUPKHSB
:
16272 case ALTIVEC_BUILTIN_VUPKHSH
:
16273 case P8V_BUILTIN_VUPKHSW
:
16275 arg0
= gimple_call_arg (stmt
, 0);
16276 lhs
= gimple_call_lhs (stmt
);
16277 if (BYTES_BIG_ENDIAN
)
16278 g
= gimple_build_assign (lhs
, VEC_UNPACK_HI_EXPR
, arg0
);
16280 g
= gimple_build_assign (lhs
, VEC_UNPACK_LO_EXPR
, arg0
);
16281 gimple_set_location (g
, gimple_location (stmt
));
16282 gsi_replace (gsi
, g
, true);
16285 /* d = vec_unpackl (a) */
16286 case ALTIVEC_BUILTIN_VUPKLSB
:
16287 case ALTIVEC_BUILTIN_VUPKLSH
:
16288 case P8V_BUILTIN_VUPKLSW
:
16290 arg0
= gimple_call_arg (stmt
, 0);
16291 lhs
= gimple_call_lhs (stmt
);
16292 if (BYTES_BIG_ENDIAN
)
16293 g
= gimple_build_assign (lhs
, VEC_UNPACK_LO_EXPR
, arg0
);
16295 g
= gimple_build_assign (lhs
, VEC_UNPACK_HI_EXPR
, arg0
);
16296 gimple_set_location (g
, gimple_location (stmt
));
16297 gsi_replace (gsi
, g
, true);
16300 /* There is no gimple type corresponding with pixel, so just return. */
16301 case ALTIVEC_BUILTIN_VUPKHPX
:
16302 case ALTIVEC_BUILTIN_VUPKLPX
:
16306 case ALTIVEC_BUILTIN_VPERM_16QI
:
16307 case ALTIVEC_BUILTIN_VPERM_8HI
:
16308 case ALTIVEC_BUILTIN_VPERM_4SI
:
16309 case ALTIVEC_BUILTIN_VPERM_2DI
:
16310 case ALTIVEC_BUILTIN_VPERM_4SF
:
16311 case ALTIVEC_BUILTIN_VPERM_2DF
:
16313 arg0
= gimple_call_arg (stmt
, 0);
16314 arg1
= gimple_call_arg (stmt
, 1);
16315 tree permute
= gimple_call_arg (stmt
, 2);
16316 lhs
= gimple_call_lhs (stmt
);
16317 location_t loc
= gimple_location (stmt
);
16318 gimple_seq stmts
= NULL
;
16319 // convert arg0 and arg1 to match the type of the permute
16320 // for the VEC_PERM_EXPR operation.
16321 tree permute_type
= (TREE_TYPE (permute
));
16322 tree arg0_ptype
= gimple_convert (&stmts
, loc
, permute_type
, arg0
);
16323 tree arg1_ptype
= gimple_convert (&stmts
, loc
, permute_type
, arg1
);
16324 tree lhs_ptype
= gimple_build (&stmts
, loc
, VEC_PERM_EXPR
,
16325 permute_type
, arg0_ptype
, arg1_ptype
,
16327 // Convert the result back to the desired lhs type upon completion.
16328 tree temp
= gimple_convert (&stmts
, loc
, TREE_TYPE (lhs
), lhs_ptype
);
16329 gsi_insert_seq_before (gsi
, stmts
, GSI_SAME_STMT
);
16330 g
= gimple_build_assign (lhs
, temp
);
16331 gimple_set_location (g
, loc
);
16332 gsi_replace (gsi
, g
, true);
16337 if (TARGET_DEBUG_BUILTIN
)
16338 fprintf (stderr
, "gimple builtin intrinsic not matched:%d %s %s\n",
16339 fn_code
, fn_name1
, fn_name2
);
16346 /* Expand an expression EXP that calls a built-in function,
16347 with result going to TARGET if that's convenient
16348 (and in mode MODE if that's convenient).
16349 SUBTARGET may be used as the target for computing one of EXP's operands.
16350 IGNORE is nonzero if the value is to be ignored. */
16353 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
16354 machine_mode mode ATTRIBUTE_UNUSED
,
16355 int ignore ATTRIBUTE_UNUSED
)
16357 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
16358 enum rs6000_builtins fcode
16359 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
16360 size_t uns_fcode
= (size_t)fcode
;
16361 const struct builtin_description
*d
;
16365 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
16366 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
16367 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
16369 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16370 floating point type, depending on whether long double is the IBM extended
16371 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16372 we only define one variant of the built-in function, and switch the code
16373 when defining it, rather than defining two built-ins and using the
16374 overload table in rs6000-c.c to switch between the two. If we don't have
16375 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16376 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16377 if (FLOAT128_IEEE_P (TFmode
))
16383 case CODE_FOR_sqrtkf2_odd
: icode
= CODE_FOR_sqrttf2_odd
; break;
16384 case CODE_FOR_trunckfdf2_odd
: icode
= CODE_FOR_trunctfdf2_odd
; break;
16385 case CODE_FOR_addkf3_odd
: icode
= CODE_FOR_addtf3_odd
; break;
16386 case CODE_FOR_subkf3_odd
: icode
= CODE_FOR_subtf3_odd
; break;
16387 case CODE_FOR_mulkf3_odd
: icode
= CODE_FOR_multf3_odd
; break;
16388 case CODE_FOR_divkf3_odd
: icode
= CODE_FOR_divtf3_odd
; break;
16389 case CODE_FOR_fmakf4_odd
: icode
= CODE_FOR_fmatf4_odd
; break;
16390 case CODE_FOR_xsxexpqp_kf
: icode
= CODE_FOR_xsxexpqp_tf
; break;
16391 case CODE_FOR_xsxsigqp_kf
: icode
= CODE_FOR_xsxsigqp_tf
; break;
16392 case CODE_FOR_xststdcnegqp_kf
: icode
= CODE_FOR_xststdcnegqp_tf
; break;
16393 case CODE_FOR_xsiexpqp_kf
: icode
= CODE_FOR_xsiexpqp_tf
; break;
16394 case CODE_FOR_xsiexpqpf_kf
: icode
= CODE_FOR_xsiexpqpf_tf
; break;
16395 case CODE_FOR_xststdcqp_kf
: icode
= CODE_FOR_xststdcqp_tf
; break;
16398 if (TARGET_DEBUG_BUILTIN
)
16400 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
16401 const char *name2
= (icode
!= CODE_FOR_nothing
)
16402 ? get_insn_name ((int) icode
)
16406 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
16408 default: name3
= "unknown"; break;
16409 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
16410 case RS6000_BTC_UNARY
: name3
= "unary"; break;
16411 case RS6000_BTC_BINARY
: name3
= "binary"; break;
16412 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
16413 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
16414 case RS6000_BTC_ABS
: name3
= "abs"; break;
16415 case RS6000_BTC_DST
: name3
= "dst"; break;
16420 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16421 (name1
) ? name1
: "---", fcode
,
16422 (name2
) ? name2
: "---", (int) icode
,
16424 func_valid_p
? "" : ", not valid");
16429 rs6000_invalid_builtin (fcode
);
16431 /* Given it is invalid, just generate a normal call. */
16432 return expand_call (exp
, target
, ignore
);
16437 case RS6000_BUILTIN_RECIP
:
16438 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
16440 case RS6000_BUILTIN_RECIPF
:
16441 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
16443 case RS6000_BUILTIN_RSQRTF
:
16444 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
16446 case RS6000_BUILTIN_RSQRT
:
16447 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
16449 case POWER7_BUILTIN_BPERMD
:
16450 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
16451 ? CODE_FOR_bpermd_di
16452 : CODE_FOR_bpermd_si
), exp
, target
);
16454 case RS6000_BUILTIN_GET_TB
:
16455 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
16458 case RS6000_BUILTIN_MFTB
:
16459 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
16460 ? CODE_FOR_rs6000_mftb_di
16461 : CODE_FOR_rs6000_mftb_si
),
16464 case RS6000_BUILTIN_MFFS
:
16465 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
16467 case RS6000_BUILTIN_MTFSB0
:
16468 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0
, exp
);
16470 case RS6000_BUILTIN_MTFSB1
:
16471 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1
, exp
);
16473 case RS6000_BUILTIN_SET_FPSCR_RN
:
16474 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn
,
16477 case RS6000_BUILTIN_SET_FPSCR_DRN
:
16479 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn
,
16482 case RS6000_BUILTIN_MFFSL
:
16483 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl
, target
);
16485 case RS6000_BUILTIN_MTFSF
:
16486 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
16488 case RS6000_BUILTIN_CPU_INIT
:
16489 case RS6000_BUILTIN_CPU_IS
:
16490 case RS6000_BUILTIN_CPU_SUPPORTS
:
16491 return cpu_expand_builtin (fcode
, exp
, target
);
16493 case MISC_BUILTIN_SPEC_BARRIER
:
16495 emit_insn (gen_speculation_barrier ());
16499 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
16500 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
16502 int icode2
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
16503 : (int) CODE_FOR_altivec_lvsl_direct
);
16504 machine_mode tmode
= insn_data
[icode2
].operand
[0].mode
;
16505 machine_mode mode
= insn_data
[icode2
].operand
[1].mode
;
16509 gcc_assert (TARGET_ALTIVEC
);
16511 arg
= CALL_EXPR_ARG (exp
, 0);
16512 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
16513 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
16514 addr
= memory_address (mode
, op
);
16515 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
16519 /* For the load case need to negate the address. */
16520 op
= gen_reg_rtx (GET_MODE (addr
));
16521 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
16523 op
= gen_rtx_MEM (mode
, op
);
16526 || GET_MODE (target
) != tmode
16527 || ! (*insn_data
[icode2
].operand
[0].predicate
) (target
, tmode
))
16528 target
= gen_reg_rtx (tmode
);
16530 pat
= GEN_FCN (icode2
) (target
, op
);
16538 case ALTIVEC_BUILTIN_VCFUX
:
16539 case ALTIVEC_BUILTIN_VCFSX
:
16540 case ALTIVEC_BUILTIN_VCTUXS
:
16541 case ALTIVEC_BUILTIN_VCTSXS
:
16542 /* FIXME: There's got to be a nicer way to handle this case than
16543 constructing a new CALL_EXPR. */
16544 if (call_expr_nargs (exp
) == 1)
16546 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
16547 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
16551 /* For the pack and unpack int128 routines, fix up the builtin so it
16552 uses the correct IBM128 type. */
16553 case MISC_BUILTIN_PACK_IF
:
16554 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
16556 icode
= CODE_FOR_packtf
;
16557 fcode
= MISC_BUILTIN_PACK_TF
;
16558 uns_fcode
= (size_t)fcode
;
16562 case MISC_BUILTIN_UNPACK_IF
:
16563 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
16565 icode
= CODE_FOR_unpacktf
;
16566 fcode
= MISC_BUILTIN_UNPACK_TF
;
16567 uns_fcode
= (size_t)fcode
;
16575 if (TARGET_ALTIVEC
)
16577 ret
= altivec_expand_builtin (exp
, target
, &success
);
16584 ret
= htm_expand_builtin (exp
, target
, &success
);
16590 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
16591 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16592 gcc_assert (attr
== RS6000_BTC_UNARY
16593 || attr
== RS6000_BTC_BINARY
16594 || attr
== RS6000_BTC_TERNARY
16595 || attr
== RS6000_BTC_SPECIAL
);
16597 /* Handle simple unary operations. */
16599 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
16600 if (d
->code
== fcode
)
16601 return rs6000_expand_unop_builtin (icode
, exp
, target
);
16603 /* Handle simple binary operations. */
16605 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
16606 if (d
->code
== fcode
)
16607 return rs6000_expand_binop_builtin (icode
, exp
, target
);
16609 /* Handle simple ternary operations. */
16611 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
16612 if (d
->code
== fcode
)
16613 return rs6000_expand_ternop_builtin (icode
, exp
, target
);
16615 /* Handle simple no-argument operations. */
16617 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
16618 if (d
->code
== fcode
)
16619 return rs6000_expand_zeroop_builtin (icode
, target
);
16621 gcc_unreachable ();
16624 /* Create a builtin vector type with a name. Taking care not to give
16625 the canonical type a name. */
16628 rs6000_vector_type (const char *name
, tree elt_type
, unsigned num_elts
)
16630 tree result
= build_vector_type (elt_type
, num_elts
);
16632 /* Copy so we don't give the canonical type a name. */
16633 result
= build_variant_type_copy (result
);
16635 add_builtin_type (name
, result
);
16641 rs6000_init_builtins (void)
16647 if (TARGET_DEBUG_BUILTIN
)
16648 fprintf (stderr
, "rs6000_init_builtins%s%s\n",
16649 (TARGET_ALTIVEC
) ? ", altivec" : "",
16650 (TARGET_VSX
) ? ", vsx" : "");
16652 V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
? "__vector long"
16653 : "__vector long long",
16654 intDI_type_node
, 2);
16655 V2DF_type_node
= rs6000_vector_type ("__vector double", double_type_node
, 2);
16656 V4SI_type_node
= rs6000_vector_type ("__vector signed int",
16657 intSI_type_node
, 4);
16658 V4SF_type_node
= rs6000_vector_type ("__vector float", float_type_node
, 4);
16659 V8HI_type_node
= rs6000_vector_type ("__vector signed short",
16660 intHI_type_node
, 8);
16661 V16QI_type_node
= rs6000_vector_type ("__vector signed char",
16662 intQI_type_node
, 16);
16664 unsigned_V16QI_type_node
= rs6000_vector_type ("__vector unsigned char",
16665 unsigned_intQI_type_node
, 16);
16666 unsigned_V8HI_type_node
= rs6000_vector_type ("__vector unsigned short",
16667 unsigned_intHI_type_node
, 8);
16668 unsigned_V4SI_type_node
= rs6000_vector_type ("__vector unsigned int",
16669 unsigned_intSI_type_node
, 4);
16670 unsigned_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16671 ? "__vector unsigned long"
16672 : "__vector unsigned long long",
16673 unsigned_intDI_type_node
, 2);
16675 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
16677 const_str_type_node
16678 = build_pointer_type (build_qualified_type (char_type_node
,
16681 /* We use V1TI mode as a special container to hold __int128_t items that
16682 must live in VSX registers. */
16683 if (intTI_type_node
)
16685 V1TI_type_node
= rs6000_vector_type ("__vector __int128",
16686 intTI_type_node
, 1);
16687 unsigned_V1TI_type_node
16688 = rs6000_vector_type ("__vector unsigned __int128",
16689 unsigned_intTI_type_node
, 1);
16692 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16693 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16694 'vector unsigned short'. */
16696 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
16697 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16698 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
16699 bool_long_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
16700 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16702 long_integer_type_internal_node
= long_integer_type_node
;
16703 long_unsigned_type_internal_node
= long_unsigned_type_node
;
16704 long_long_integer_type_internal_node
= long_long_integer_type_node
;
16705 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
16706 intQI_type_internal_node
= intQI_type_node
;
16707 uintQI_type_internal_node
= unsigned_intQI_type_node
;
16708 intHI_type_internal_node
= intHI_type_node
;
16709 uintHI_type_internal_node
= unsigned_intHI_type_node
;
16710 intSI_type_internal_node
= intSI_type_node
;
16711 uintSI_type_internal_node
= unsigned_intSI_type_node
;
16712 intDI_type_internal_node
= intDI_type_node
;
16713 uintDI_type_internal_node
= unsigned_intDI_type_node
;
16714 intTI_type_internal_node
= intTI_type_node
;
16715 uintTI_type_internal_node
= unsigned_intTI_type_node
;
16716 float_type_internal_node
= float_type_node
;
16717 double_type_internal_node
= double_type_node
;
16718 long_double_type_internal_node
= long_double_type_node
;
16719 dfloat64_type_internal_node
= dfloat64_type_node
;
16720 dfloat128_type_internal_node
= dfloat128_type_node
;
16721 void_type_internal_node
= void_type_node
;
16723 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16724 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16725 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16726 format that uses a pair of doubles, depending on the switches and
16729 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16730 floating point, we need make sure the type is non-zero or else self-test
16731 fails during bootstrap.
16733 Always create __ibm128 as a separate type, even if the current long double
16734 format is IBM extended double.
16736 For IEEE 128-bit floating point, always create the type __ieee128. If the
16737 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16739 if (TARGET_FLOAT128_TYPE
)
16741 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
)
16742 ibm128_float_type_node
= long_double_type_node
;
16745 ibm128_float_type_node
= make_node (REAL_TYPE
);
16746 TYPE_PRECISION (ibm128_float_type_node
) = 128;
16747 SET_TYPE_MODE (ibm128_float_type_node
, IFmode
);
16748 layout_type (ibm128_float_type_node
);
16751 lang_hooks
.types
.register_builtin_type (ibm128_float_type_node
,
16754 if (TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
)
16755 ieee128_float_type_node
= long_double_type_node
;
16757 ieee128_float_type_node
= float128_type_node
;
16759 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
16764 ieee128_float_type_node
= ibm128_float_type_node
= long_double_type_node
;
16766 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16768 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
16769 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
16770 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
16771 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
16772 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
16773 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
16774 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
16775 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
16776 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
16777 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
16778 builtin_mode_to_type
[IFmode
][0] = ibm128_float_type_node
;
16779 builtin_mode_to_type
[KFmode
][0] = ieee128_float_type_node
;
16780 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
16781 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
16782 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
16783 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
16784 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
16785 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
16786 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
16787 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
16788 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
16789 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
16790 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
16791 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
16792 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
16793 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
16794 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
16796 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
16797 TYPE_NAME (bool_char_type_node
) = tdecl
;
16799 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
16800 TYPE_NAME (bool_short_type_node
) = tdecl
;
16802 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
16803 TYPE_NAME (bool_int_type_node
) = tdecl
;
16805 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
16806 TYPE_NAME (pixel_type_node
) = tdecl
;
16808 bool_V16QI_type_node
= rs6000_vector_type ("__vector __bool char",
16809 bool_char_type_node
, 16);
16810 bool_V8HI_type_node
= rs6000_vector_type ("__vector __bool short",
16811 bool_short_type_node
, 8);
16812 bool_V4SI_type_node
= rs6000_vector_type ("__vector __bool int",
16813 bool_int_type_node
, 4);
16814 bool_V2DI_type_node
= rs6000_vector_type (TARGET_POWERPC64
16815 ? "__vector __bool long"
16816 : "__vector __bool long long",
16817 bool_long_long_type_node
, 2);
16818 pixel_V8HI_type_node
= rs6000_vector_type ("__vector __pixel",
16819 pixel_type_node
, 8);
16821 /* Create Altivec and VSX builtins on machines with at least the
16822 general purpose extensions (970 and newer) to allow the use of
16823 the target attribute. */
16824 if (TARGET_EXTRA_BUILTINS
)
16825 altivec_init_builtins ();
16827 htm_init_builtins ();
16829 if (TARGET_EXTRA_BUILTINS
)
16830 rs6000_common_init_builtins ();
16832 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
16833 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
16834 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
16836 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
16837 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
16838 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
16840 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
16841 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
16842 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
16844 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
16845 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
16846 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
16848 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
16849 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
16850 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
16851 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
16853 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16855 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
16858 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16861 ftype
= build_function_type_list (unsigned_intSI_type_node
,
16863 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
16865 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
16866 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
16868 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
16869 def_builtin ("__builtin_mffsl", ftype
, RS6000_BUILTIN_MFFSL
);
16871 ftype
= build_function_type_list (void_type_node
,
16874 def_builtin ("__builtin_mtfsb0", ftype
, RS6000_BUILTIN_MTFSB0
);
16876 ftype
= build_function_type_list (void_type_node
,
16879 def_builtin ("__builtin_mtfsb1", ftype
, RS6000_BUILTIN_MTFSB1
);
16881 ftype
= build_function_type_list (void_type_node
,
16884 def_builtin ("__builtin_set_fpscr_rn", ftype
, RS6000_BUILTIN_SET_FPSCR_RN
);
16886 ftype
= build_function_type_list (void_type_node
,
16889 def_builtin ("__builtin_set_fpscr_drn", ftype
, RS6000_BUILTIN_SET_FPSCR_DRN
);
16891 ftype
= build_function_type_list (void_type_node
,
16892 intSI_type_node
, double_type_node
,
16894 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
16896 ftype
= build_function_type_list (void_type_node
, NULL_TREE
);
16897 def_builtin ("__builtin_cpu_init", ftype
, RS6000_BUILTIN_CPU_INIT
);
16898 def_builtin ("__builtin_ppc_speculation_barrier", ftype
,
16899 MISC_BUILTIN_SPEC_BARRIER
);
16901 ftype
= build_function_type_list (bool_int_type_node
, const_ptr_type_node
,
16903 def_builtin ("__builtin_cpu_is", ftype
, RS6000_BUILTIN_CPU_IS
);
16904 def_builtin ("__builtin_cpu_supports", ftype
, RS6000_BUILTIN_CPU_SUPPORTS
);
16906 /* AIX libm provides clog as __clog. */
16907 if (TARGET_XCOFF
&&
16908 (tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
16909 set_user_assembler_name (tdecl
, "__clog");
16911 #ifdef SUBTARGET_INIT_BUILTINS
16912 SUBTARGET_INIT_BUILTINS
;
16916 /* Returns the rs6000 builtin decl for CODE. */
16919 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
16921 HOST_WIDE_INT fnmask
;
16923 if (code
>= RS6000_BUILTIN_COUNT
)
16924 return error_mark_node
;
16926 fnmask
= rs6000_builtin_info
[code
].mask
;
16927 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
16929 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
16930 return error_mark_node
;
16933 return rs6000_builtin_decls
[code
];
16937 altivec_init_builtins (void)
16939 const struct builtin_description
*d
;
16943 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
16945 tree pvoid_type_node
= build_pointer_type (void_type_node
);
16947 tree pcvoid_type_node
16948 = build_pointer_type (build_qualified_type (void_type_node
,
16951 tree int_ftype_opaque
16952 = build_function_type_list (integer_type_node
,
16953 opaque_V4SI_type_node
, NULL_TREE
);
16954 tree opaque_ftype_opaque
16955 = build_function_type_list (integer_type_node
, NULL_TREE
);
16956 tree opaque_ftype_opaque_int
16957 = build_function_type_list (opaque_V4SI_type_node
,
16958 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
16959 tree opaque_ftype_opaque_opaque_int
16960 = build_function_type_list (opaque_V4SI_type_node
,
16961 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16962 integer_type_node
, NULL_TREE
);
16963 tree opaque_ftype_opaque_opaque_opaque
16964 = build_function_type_list (opaque_V4SI_type_node
,
16965 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16966 opaque_V4SI_type_node
, NULL_TREE
);
16967 tree opaque_ftype_opaque_opaque
16968 = build_function_type_list (opaque_V4SI_type_node
,
16969 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
16971 tree int_ftype_int_opaque_opaque
16972 = build_function_type_list (integer_type_node
,
16973 integer_type_node
, opaque_V4SI_type_node
,
16974 opaque_V4SI_type_node
, NULL_TREE
);
16975 tree int_ftype_int_v4si_v4si
16976 = build_function_type_list (integer_type_node
,
16977 integer_type_node
, V4SI_type_node
,
16978 V4SI_type_node
, NULL_TREE
);
16979 tree int_ftype_int_v2di_v2di
16980 = build_function_type_list (integer_type_node
,
16981 integer_type_node
, V2DI_type_node
,
16982 V2DI_type_node
, NULL_TREE
);
16983 tree void_ftype_v4si
16984 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
16985 tree v8hi_ftype_void
16986 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
16987 tree void_ftype_void
16988 = build_function_type_list (void_type_node
, NULL_TREE
);
16989 tree void_ftype_int
16990 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
16992 tree opaque_ftype_long_pcvoid
16993 = build_function_type_list (opaque_V4SI_type_node
,
16994 long_integer_type_node
, pcvoid_type_node
,
16996 tree v16qi_ftype_long_pcvoid
16997 = build_function_type_list (V16QI_type_node
,
16998 long_integer_type_node
, pcvoid_type_node
,
17000 tree v8hi_ftype_long_pcvoid
17001 = build_function_type_list (V8HI_type_node
,
17002 long_integer_type_node
, pcvoid_type_node
,
17004 tree v4si_ftype_long_pcvoid
17005 = build_function_type_list (V4SI_type_node
,
17006 long_integer_type_node
, pcvoid_type_node
,
17008 tree v4sf_ftype_long_pcvoid
17009 = build_function_type_list (V4SF_type_node
,
17010 long_integer_type_node
, pcvoid_type_node
,
17012 tree v2df_ftype_long_pcvoid
17013 = build_function_type_list (V2DF_type_node
,
17014 long_integer_type_node
, pcvoid_type_node
,
17016 tree v2di_ftype_long_pcvoid
17017 = build_function_type_list (V2DI_type_node
,
17018 long_integer_type_node
, pcvoid_type_node
,
17020 tree v1ti_ftype_long_pcvoid
17021 = build_function_type_list (V1TI_type_node
,
17022 long_integer_type_node
, pcvoid_type_node
,
17025 tree void_ftype_opaque_long_pvoid
17026 = build_function_type_list (void_type_node
,
17027 opaque_V4SI_type_node
, long_integer_type_node
,
17028 pvoid_type_node
, NULL_TREE
);
17029 tree void_ftype_v4si_long_pvoid
17030 = build_function_type_list (void_type_node
,
17031 V4SI_type_node
, long_integer_type_node
,
17032 pvoid_type_node
, NULL_TREE
);
17033 tree void_ftype_v16qi_long_pvoid
17034 = build_function_type_list (void_type_node
,
17035 V16QI_type_node
, long_integer_type_node
,
17036 pvoid_type_node
, NULL_TREE
);
17038 tree void_ftype_v16qi_pvoid_long
17039 = build_function_type_list (void_type_node
,
17040 V16QI_type_node
, pvoid_type_node
,
17041 long_integer_type_node
, NULL_TREE
);
17043 tree void_ftype_v8hi_long_pvoid
17044 = build_function_type_list (void_type_node
,
17045 V8HI_type_node
, long_integer_type_node
,
17046 pvoid_type_node
, NULL_TREE
);
17047 tree void_ftype_v4sf_long_pvoid
17048 = build_function_type_list (void_type_node
,
17049 V4SF_type_node
, long_integer_type_node
,
17050 pvoid_type_node
, NULL_TREE
);
17051 tree void_ftype_v2df_long_pvoid
17052 = build_function_type_list (void_type_node
,
17053 V2DF_type_node
, long_integer_type_node
,
17054 pvoid_type_node
, NULL_TREE
);
17055 tree void_ftype_v1ti_long_pvoid
17056 = build_function_type_list (void_type_node
,
17057 V1TI_type_node
, long_integer_type_node
,
17058 pvoid_type_node
, NULL_TREE
);
17059 tree void_ftype_v2di_long_pvoid
17060 = build_function_type_list (void_type_node
,
17061 V2DI_type_node
, long_integer_type_node
,
17062 pvoid_type_node
, NULL_TREE
);
17063 tree int_ftype_int_v8hi_v8hi
17064 = build_function_type_list (integer_type_node
,
17065 integer_type_node
, V8HI_type_node
,
17066 V8HI_type_node
, NULL_TREE
);
17067 tree int_ftype_int_v16qi_v16qi
17068 = build_function_type_list (integer_type_node
,
17069 integer_type_node
, V16QI_type_node
,
17070 V16QI_type_node
, NULL_TREE
);
17071 tree int_ftype_int_v4sf_v4sf
17072 = build_function_type_list (integer_type_node
,
17073 integer_type_node
, V4SF_type_node
,
17074 V4SF_type_node
, NULL_TREE
);
17075 tree int_ftype_int_v2df_v2df
17076 = build_function_type_list (integer_type_node
,
17077 integer_type_node
, V2DF_type_node
,
17078 V2DF_type_node
, NULL_TREE
);
17079 tree v2di_ftype_v2di
17080 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
17081 tree v4si_ftype_v4si
17082 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
17083 tree v8hi_ftype_v8hi
17084 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
17085 tree v16qi_ftype_v16qi
17086 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
17087 tree v4sf_ftype_v4sf
17088 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
17089 tree v2df_ftype_v2df
17090 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
17091 tree void_ftype_pcvoid_int_int
17092 = build_function_type_list (void_type_node
,
17093 pcvoid_type_node
, integer_type_node
,
17094 integer_type_node
, NULL_TREE
);
17096 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
17097 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
17098 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
17099 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
17100 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
17101 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
17102 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
17103 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
17104 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
17105 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
17106 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
17107 ALTIVEC_BUILTIN_LVXL_V2DF
);
17108 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
17109 ALTIVEC_BUILTIN_LVXL_V2DI
);
17110 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
17111 ALTIVEC_BUILTIN_LVXL_V4SF
);
17112 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
17113 ALTIVEC_BUILTIN_LVXL_V4SI
);
17114 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
17115 ALTIVEC_BUILTIN_LVXL_V8HI
);
17116 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
17117 ALTIVEC_BUILTIN_LVXL_V16QI
);
17118 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
17119 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid
,
17120 ALTIVEC_BUILTIN_LVX_V1TI
);
17121 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
17122 ALTIVEC_BUILTIN_LVX_V2DF
);
17123 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
17124 ALTIVEC_BUILTIN_LVX_V2DI
);
17125 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
17126 ALTIVEC_BUILTIN_LVX_V4SF
);
17127 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
17128 ALTIVEC_BUILTIN_LVX_V4SI
);
17129 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
17130 ALTIVEC_BUILTIN_LVX_V8HI
);
17131 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
17132 ALTIVEC_BUILTIN_LVX_V16QI
);
17133 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
17134 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
17135 ALTIVEC_BUILTIN_STVX_V2DF
);
17136 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
17137 ALTIVEC_BUILTIN_STVX_V2DI
);
17138 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
17139 ALTIVEC_BUILTIN_STVX_V4SF
);
17140 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
17141 ALTIVEC_BUILTIN_STVX_V4SI
);
17142 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
17143 ALTIVEC_BUILTIN_STVX_V8HI
);
17144 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
17145 ALTIVEC_BUILTIN_STVX_V16QI
);
17146 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
17147 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
17148 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
17149 ALTIVEC_BUILTIN_STVXL_V2DF
);
17150 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
17151 ALTIVEC_BUILTIN_STVXL_V2DI
);
17152 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
17153 ALTIVEC_BUILTIN_STVXL_V4SF
);
17154 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
17155 ALTIVEC_BUILTIN_STVXL_V4SI
);
17156 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
17157 ALTIVEC_BUILTIN_STVXL_V8HI
);
17158 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
17159 ALTIVEC_BUILTIN_STVXL_V16QI
);
17160 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
17161 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
17162 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
17163 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
17164 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
17165 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
17166 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
17167 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
17168 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
17169 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
17170 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
17171 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
17172 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
17173 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
17174 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
17175 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
17177 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
17178 VSX_BUILTIN_LXVD2X_V2DF
);
17179 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
17180 VSX_BUILTIN_LXVD2X_V2DI
);
17181 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
17182 VSX_BUILTIN_LXVW4X_V4SF
);
17183 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
17184 VSX_BUILTIN_LXVW4X_V4SI
);
17185 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
17186 VSX_BUILTIN_LXVW4X_V8HI
);
17187 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
17188 VSX_BUILTIN_LXVW4X_V16QI
);
17189 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
17190 VSX_BUILTIN_STXVD2X_V2DF
);
17191 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
17192 VSX_BUILTIN_STXVD2X_V2DI
);
17193 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
17194 VSX_BUILTIN_STXVW4X_V4SF
);
17195 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
17196 VSX_BUILTIN_STXVW4X_V4SI
);
17197 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
17198 VSX_BUILTIN_STXVW4X_V8HI
);
17199 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
17200 VSX_BUILTIN_STXVW4X_V16QI
);
17202 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid
,
17203 VSX_BUILTIN_LD_ELEMREV_V2DF
);
17204 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid
,
17205 VSX_BUILTIN_LD_ELEMREV_V2DI
);
17206 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid
,
17207 VSX_BUILTIN_LD_ELEMREV_V4SF
);
17208 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid
,
17209 VSX_BUILTIN_LD_ELEMREV_V4SI
);
17210 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid
,
17211 VSX_BUILTIN_LD_ELEMREV_V8HI
);
17212 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid
,
17213 VSX_BUILTIN_LD_ELEMREV_V16QI
);
17214 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid
,
17215 VSX_BUILTIN_ST_ELEMREV_V2DF
);
17216 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid
,
17217 VSX_BUILTIN_ST_ELEMREV_V1TI
);
17218 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid
,
17219 VSX_BUILTIN_ST_ELEMREV_V2DI
);
17220 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid
,
17221 VSX_BUILTIN_ST_ELEMREV_V4SF
);
17222 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid
,
17223 VSX_BUILTIN_ST_ELEMREV_V4SI
);
17224 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid
,
17225 VSX_BUILTIN_ST_ELEMREV_V8HI
);
17226 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid
,
17227 VSX_BUILTIN_ST_ELEMREV_V16QI
);
17229 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
17230 VSX_BUILTIN_VEC_LD
);
17231 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
17232 VSX_BUILTIN_VEC_ST
);
17233 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid
,
17234 VSX_BUILTIN_VEC_XL
);
17235 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid
,
17236 VSX_BUILTIN_VEC_XL_BE
);
17237 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid
,
17238 VSX_BUILTIN_VEC_XST
);
17239 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid
,
17240 VSX_BUILTIN_VEC_XST_BE
);
17242 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
17243 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
17244 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
17246 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
17247 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
17248 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
17249 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
17250 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
17251 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
17252 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
17253 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
17254 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
17255 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
17256 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
17257 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
17259 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque
,
17260 ALTIVEC_BUILTIN_VEC_ADDE
);
17261 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque
,
17262 ALTIVEC_BUILTIN_VEC_ADDEC
);
17263 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque
,
17264 ALTIVEC_BUILTIN_VEC_CMPNE
);
17265 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque
,
17266 ALTIVEC_BUILTIN_VEC_MUL
);
17267 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque
,
17268 ALTIVEC_BUILTIN_VEC_SUBE
);
17269 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque
,
17270 ALTIVEC_BUILTIN_VEC_SUBEC
);
17272 /* Cell builtins. */
17273 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
17274 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
17275 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
17276 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
17278 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
17279 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
17280 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
17281 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
17283 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
17284 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
17285 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
17286 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
17288 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
17289 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
17290 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
17291 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
17293 if (TARGET_P9_VECTOR
)
17295 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long
,
17296 P9V_BUILTIN_STXVL
);
17297 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long
,
17298 P9V_BUILTIN_XST_LEN_R
);
17301 /* Add the DST variants. */
17303 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
17305 HOST_WIDE_INT mask
= d
->mask
;
17307 /* It is expected that these dst built-in functions may have
17308 d->icode equal to CODE_FOR_nothing. */
17309 if ((mask
& builtin_mask
) != mask
)
17311 if (TARGET_DEBUG_BUILTIN
)
17312 fprintf (stderr
, "altivec_init_builtins, skip dst %s\n",
17316 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
17319 /* Initialize the predicates. */
17320 d
= bdesc_altivec_preds
;
17321 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
17323 machine_mode mode1
;
17325 HOST_WIDE_INT mask
= d
->mask
;
17327 if ((mask
& builtin_mask
) != mask
)
17329 if (TARGET_DEBUG_BUILTIN
)
17330 fprintf (stderr
, "altivec_init_builtins, skip predicate %s\n",
17335 if (rs6000_overloaded_builtin_p (d
->code
))
17339 /* Cannot define builtin if the instruction is disabled. */
17340 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17341 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
17347 type
= int_ftype_int_opaque_opaque
;
17350 type
= int_ftype_int_v2di_v2di
;
17353 type
= int_ftype_int_v4si_v4si
;
17356 type
= int_ftype_int_v8hi_v8hi
;
17359 type
= int_ftype_int_v16qi_v16qi
;
17362 type
= int_ftype_int_v4sf_v4sf
;
17365 type
= int_ftype_int_v2df_v2df
;
17368 gcc_unreachable ();
17371 def_builtin (d
->name
, type
, d
->code
);
17374 /* Initialize the abs* operators. */
17376 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
17378 machine_mode mode0
;
17380 HOST_WIDE_INT mask
= d
->mask
;
17382 if ((mask
& builtin_mask
) != mask
)
17384 if (TARGET_DEBUG_BUILTIN
)
17385 fprintf (stderr
, "altivec_init_builtins, skip abs %s\n",
17390 /* Cannot define builtin if the instruction is disabled. */
17391 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
17392 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
17397 type
= v2di_ftype_v2di
;
17400 type
= v4si_ftype_v4si
;
17403 type
= v8hi_ftype_v8hi
;
17406 type
= v16qi_ftype_v16qi
;
17409 type
= v4sf_ftype_v4sf
;
17412 type
= v2df_ftype_v2df
;
17415 gcc_unreachable ();
17418 def_builtin (d
->name
, type
, d
->code
);
17421 /* Initialize target builtin that implements
17422 targetm.vectorize.builtin_mask_for_load. */
17424 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
17425 v16qi_ftype_long_pcvoid
,
17426 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
17427 BUILT_IN_MD
, NULL
, NULL_TREE
);
17428 TREE_READONLY (decl
) = 1;
17429 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17430 altivec_builtin_mask_for_load
= decl
;
17432 /* Access to the vec_init patterns. */
17433 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
17434 integer_type_node
, integer_type_node
,
17435 integer_type_node
, NULL_TREE
);
17436 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
17438 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
17439 short_integer_type_node
,
17440 short_integer_type_node
,
17441 short_integer_type_node
,
17442 short_integer_type_node
,
17443 short_integer_type_node
,
17444 short_integer_type_node
,
17445 short_integer_type_node
, NULL_TREE
);
17446 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
17448 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
17449 char_type_node
, char_type_node
,
17450 char_type_node
, char_type_node
,
17451 char_type_node
, char_type_node
,
17452 char_type_node
, char_type_node
,
17453 char_type_node
, char_type_node
,
17454 char_type_node
, char_type_node
,
17455 char_type_node
, char_type_node
,
17456 char_type_node
, NULL_TREE
);
17457 def_builtin ("__builtin_vec_init_v16qi", ftype
,
17458 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
17460 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
17461 float_type_node
, float_type_node
,
17462 float_type_node
, NULL_TREE
);
17463 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
17465 /* VSX builtins. */
17466 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
17467 double_type_node
, NULL_TREE
);
17468 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
17470 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
17471 intDI_type_node
, NULL_TREE
);
17472 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
17474 /* Access to the vec_set patterns. */
17475 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
17477 integer_type_node
, NULL_TREE
);
17478 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
17480 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
17482 integer_type_node
, NULL_TREE
);
17483 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
17485 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
17487 integer_type_node
, NULL_TREE
);
17488 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
17490 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
17492 integer_type_node
, NULL_TREE
);
17493 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
17495 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
17497 integer_type_node
, NULL_TREE
);
17498 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
17500 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
17502 integer_type_node
, NULL_TREE
);
17503 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
17505 /* Access to the vec_extract patterns. */
17506 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
17507 integer_type_node
, NULL_TREE
);
17508 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
17510 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
17511 integer_type_node
, NULL_TREE
);
17512 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
17514 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
17515 integer_type_node
, NULL_TREE
);
17516 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
17518 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
17519 integer_type_node
, NULL_TREE
);
17520 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
17522 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
17523 integer_type_node
, NULL_TREE
);
17524 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
17526 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
17527 integer_type_node
, NULL_TREE
);
17528 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
17531 if (V1TI_type_node
)
17533 tree v1ti_ftype_long_pcvoid
17534 = build_function_type_list (V1TI_type_node
,
17535 long_integer_type_node
, pcvoid_type_node
,
17537 tree void_ftype_v1ti_long_pvoid
17538 = build_function_type_list (void_type_node
,
17539 V1TI_type_node
, long_integer_type_node
,
17540 pvoid_type_node
, NULL_TREE
);
17541 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid
,
17542 VSX_BUILTIN_LD_ELEMREV_V1TI
);
17543 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
17544 VSX_BUILTIN_LXVD2X_V1TI
);
17545 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
17546 VSX_BUILTIN_STXVD2X_V1TI
);
17547 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
17548 NULL_TREE
, NULL_TREE
);
17549 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
17550 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
17552 integer_type_node
, NULL_TREE
);
17553 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
17554 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
17555 integer_type_node
, NULL_TREE
);
17556 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
17562 htm_init_builtins (void)
17564 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17565 const struct builtin_description
*d
;
17569 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
17571 tree op
[MAX_HTM_OPERANDS
], type
;
17572 HOST_WIDE_INT mask
= d
->mask
;
17573 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
17574 bool void_func
= (attr
& RS6000_BTC_VOID
);
17575 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
17577 tree gpr_type_node
;
17581 /* It is expected that these htm built-in functions may have
17582 d->icode equal to CODE_FOR_nothing. */
17584 if (TARGET_32BIT
&& TARGET_POWERPC64
)
17585 gpr_type_node
= long_long_unsigned_type_node
;
17587 gpr_type_node
= long_unsigned_type_node
;
17589 if (attr
& RS6000_BTC_SPR
)
17591 rettype
= gpr_type_node
;
17592 argtype
= gpr_type_node
;
17594 else if (d
->code
== HTM_BUILTIN_TABORTDC
17595 || d
->code
== HTM_BUILTIN_TABORTDCI
)
17597 rettype
= unsigned_type_node
;
17598 argtype
= gpr_type_node
;
17602 rettype
= unsigned_type_node
;
17603 argtype
= unsigned_type_node
;
17606 if ((mask
& builtin_mask
) != mask
)
17608 if (TARGET_DEBUG_BUILTIN
)
17609 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
17615 if (TARGET_DEBUG_BUILTIN
)
17616 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
17617 (long unsigned) i
);
17621 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
17623 if (attr_args
== RS6000_BTC_UNARY
)
17624 op
[nopnds
++] = argtype
;
17625 else if (attr_args
== RS6000_BTC_BINARY
)
17627 op
[nopnds
++] = argtype
;
17628 op
[nopnds
++] = argtype
;
17630 else if (attr_args
== RS6000_BTC_TERNARY
)
17632 op
[nopnds
++] = argtype
;
17633 op
[nopnds
++] = argtype
;
17634 op
[nopnds
++] = argtype
;
17640 type
= build_function_type_list (op
[0], NULL_TREE
);
17643 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
17646 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
17649 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
17653 gcc_unreachable ();
17656 def_builtin (d
->name
, type
, d
->code
);
17660 /* Hash function for builtin functions with up to 3 arguments and a return
17663 builtin_hasher::hash (builtin_hash_struct
*bh
)
17668 for (i
= 0; i
< 4; i
++)
17670 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
17671 ret
= (ret
* 2) + bh
->uns_p
[i
];
17677 /* Compare builtin hash entries H1 and H2 for equivalence. */
17679 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
17681 return ((p1
->mode
[0] == p2
->mode
[0])
17682 && (p1
->mode
[1] == p2
->mode
[1])
17683 && (p1
->mode
[2] == p2
->mode
[2])
17684 && (p1
->mode
[3] == p2
->mode
[3])
17685 && (p1
->uns_p
[0] == p2
->uns_p
[0])
17686 && (p1
->uns_p
[1] == p2
->uns_p
[1])
17687 && (p1
->uns_p
[2] == p2
->uns_p
[2])
17688 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
17691 /* Map types for builtin functions with an explicit return type and up to 3
17692 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17693 of the argument. */
17695 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
17696 machine_mode mode_arg1
, machine_mode mode_arg2
,
17697 enum rs6000_builtins builtin
, const char *name
)
17699 struct builtin_hash_struct h
;
17700 struct builtin_hash_struct
*h2
;
17703 tree ret_type
= NULL_TREE
;
17704 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
17706 /* Create builtin_hash_table. */
17707 if (builtin_hash_table
== NULL
)
17708 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
17710 h
.type
= NULL_TREE
;
17711 h
.mode
[0] = mode_ret
;
17712 h
.mode
[1] = mode_arg0
;
17713 h
.mode
[2] = mode_arg1
;
17714 h
.mode
[3] = mode_arg2
;
17720 /* If the builtin is a type that produces unsigned results or takes unsigned
17721 arguments, and it is returned as a decl for the vectorizer (such as
17722 widening multiplies, permute), make sure the arguments and return value
17723 are type correct. */
17726 /* unsigned 1 argument functions. */
17727 case CRYPTO_BUILTIN_VSBOX
:
17728 case CRYPTO_BUILTIN_VSBOX_BE
:
17729 case P8V_BUILTIN_VGBBD
:
17730 case MISC_BUILTIN_CDTBCD
:
17731 case MISC_BUILTIN_CBCDTD
:
17736 /* unsigned 2 argument functions. */
17737 case ALTIVEC_BUILTIN_VMULEUB
:
17738 case ALTIVEC_BUILTIN_VMULEUH
:
17739 case P8V_BUILTIN_VMULEUW
:
17740 case ALTIVEC_BUILTIN_VMULOUB
:
17741 case ALTIVEC_BUILTIN_VMULOUH
:
17742 case P8V_BUILTIN_VMULOUW
:
17743 case CRYPTO_BUILTIN_VCIPHER
:
17744 case CRYPTO_BUILTIN_VCIPHER_BE
:
17745 case CRYPTO_BUILTIN_VCIPHERLAST
:
17746 case CRYPTO_BUILTIN_VCIPHERLAST_BE
:
17747 case CRYPTO_BUILTIN_VNCIPHER
:
17748 case CRYPTO_BUILTIN_VNCIPHER_BE
:
17749 case CRYPTO_BUILTIN_VNCIPHERLAST
:
17750 case CRYPTO_BUILTIN_VNCIPHERLAST_BE
:
17751 case CRYPTO_BUILTIN_VPMSUMB
:
17752 case CRYPTO_BUILTIN_VPMSUMH
:
17753 case CRYPTO_BUILTIN_VPMSUMW
:
17754 case CRYPTO_BUILTIN_VPMSUMD
:
17755 case CRYPTO_BUILTIN_VPMSUM
:
17756 case MISC_BUILTIN_ADDG6S
:
17757 case MISC_BUILTIN_DIVWEU
:
17758 case MISC_BUILTIN_DIVDEU
:
17759 case VSX_BUILTIN_UDIV_V2DI
:
17760 case ALTIVEC_BUILTIN_VMAXUB
:
17761 case ALTIVEC_BUILTIN_VMINUB
:
17762 case ALTIVEC_BUILTIN_VMAXUH
:
17763 case ALTIVEC_BUILTIN_VMINUH
:
17764 case ALTIVEC_BUILTIN_VMAXUW
:
17765 case ALTIVEC_BUILTIN_VMINUW
:
17766 case P8V_BUILTIN_VMAXUD
:
17767 case P8V_BUILTIN_VMINUD
:
17773 /* unsigned 3 argument functions. */
17774 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
17775 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
17776 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
17777 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
17778 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
17779 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
17780 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
17781 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
17782 case VSX_BUILTIN_VPERM_16QI_UNS
:
17783 case VSX_BUILTIN_VPERM_8HI_UNS
:
17784 case VSX_BUILTIN_VPERM_4SI_UNS
:
17785 case VSX_BUILTIN_VPERM_2DI_UNS
:
17786 case VSX_BUILTIN_XXSEL_16QI_UNS
:
17787 case VSX_BUILTIN_XXSEL_8HI_UNS
:
17788 case VSX_BUILTIN_XXSEL_4SI_UNS
:
17789 case VSX_BUILTIN_XXSEL_2DI_UNS
:
17790 case CRYPTO_BUILTIN_VPERMXOR
:
17791 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
17792 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
17793 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
17794 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
17795 case CRYPTO_BUILTIN_VSHASIGMAW
:
17796 case CRYPTO_BUILTIN_VSHASIGMAD
:
17797 case CRYPTO_BUILTIN_VSHASIGMA
:
17804 /* signed permute functions with unsigned char mask. */
17805 case ALTIVEC_BUILTIN_VPERM_16QI
:
17806 case ALTIVEC_BUILTIN_VPERM_8HI
:
17807 case ALTIVEC_BUILTIN_VPERM_4SI
:
17808 case ALTIVEC_BUILTIN_VPERM_4SF
:
17809 case ALTIVEC_BUILTIN_VPERM_2DI
:
17810 case ALTIVEC_BUILTIN_VPERM_2DF
:
17811 case VSX_BUILTIN_VPERM_16QI
:
17812 case VSX_BUILTIN_VPERM_8HI
:
17813 case VSX_BUILTIN_VPERM_4SI
:
17814 case VSX_BUILTIN_VPERM_4SF
:
17815 case VSX_BUILTIN_VPERM_2DI
:
17816 case VSX_BUILTIN_VPERM_2DF
:
17820 /* unsigned args, signed return. */
17821 case VSX_BUILTIN_XVCVUXDSP
:
17822 case VSX_BUILTIN_XVCVUXDDP_UNS
:
17823 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
17827 /* signed args, unsigned return. */
17828 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
17829 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
17830 case MISC_BUILTIN_UNPACK_TD
:
17831 case MISC_BUILTIN_UNPACK_V1TI
:
17835 /* unsigned arguments, bool return (compares). */
17836 case ALTIVEC_BUILTIN_VCMPEQUB
:
17837 case ALTIVEC_BUILTIN_VCMPEQUH
:
17838 case ALTIVEC_BUILTIN_VCMPEQUW
:
17839 case P8V_BUILTIN_VCMPEQUD
:
17840 case VSX_BUILTIN_CMPGE_U16QI
:
17841 case VSX_BUILTIN_CMPGE_U8HI
:
17842 case VSX_BUILTIN_CMPGE_U4SI
:
17843 case VSX_BUILTIN_CMPGE_U2DI
:
17844 case ALTIVEC_BUILTIN_VCMPGTUB
:
17845 case ALTIVEC_BUILTIN_VCMPGTUH
:
17846 case ALTIVEC_BUILTIN_VCMPGTUW
:
17847 case P8V_BUILTIN_VCMPGTUD
:
17852 /* unsigned arguments for 128-bit pack instructions. */
17853 case MISC_BUILTIN_PACK_TD
:
17854 case MISC_BUILTIN_PACK_V1TI
:
17859 /* unsigned second arguments (vector shift right). */
17860 case ALTIVEC_BUILTIN_VSRB
:
17861 case ALTIVEC_BUILTIN_VSRH
:
17862 case ALTIVEC_BUILTIN_VSRW
:
17863 case P8V_BUILTIN_VSRD
:
17871 /* Figure out how many args are present. */
17872 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
17875 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
17876 if (!ret_type
&& h
.uns_p
[0])
17877 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
17880 fatal_error (input_location
,
17881 "internal error: builtin function %qs had an unexpected "
17882 "return type %qs", name
, GET_MODE_NAME (h
.mode
[0]));
17884 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
17885 arg_type
[i
] = NULL_TREE
;
17887 for (i
= 0; i
< num_args
; i
++)
17889 int m
= (int) h
.mode
[i
+1];
17890 int uns_p
= h
.uns_p
[i
+1];
17892 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
17893 if (!arg_type
[i
] && uns_p
)
17894 arg_type
[i
] = builtin_mode_to_type
[m
][0];
17897 fatal_error (input_location
,
17898 "internal error: builtin function %qs, argument %d "
17899 "had unexpected argument type %qs", name
, i
,
17900 GET_MODE_NAME (m
));
17903 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
17904 if (*found
== NULL
)
17906 h2
= ggc_alloc
<builtin_hash_struct
> ();
17910 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
17911 arg_type
[2], NULL_TREE
);
17914 return (*found
)->type
;
17918 rs6000_common_init_builtins (void)
17920 const struct builtin_description
*d
;
17923 tree opaque_ftype_opaque
= NULL_TREE
;
17924 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
17925 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
17926 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17928 /* Create Altivec and VSX builtins on machines with at least the
17929 general purpose extensions (970 and newer) to allow the use of
17930 the target attribute. */
17932 if (TARGET_EXTRA_BUILTINS
)
17933 builtin_mask
|= RS6000_BTM_COMMON
;
17935 /* Add the ternary operators. */
17937 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
17940 HOST_WIDE_INT mask
= d
->mask
;
17942 if ((mask
& builtin_mask
) != mask
)
17944 if (TARGET_DEBUG_BUILTIN
)
17945 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
17949 if (rs6000_overloaded_builtin_p (d
->code
))
17951 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
17952 type
= opaque_ftype_opaque_opaque_opaque
17953 = build_function_type_list (opaque_V4SI_type_node
,
17954 opaque_V4SI_type_node
,
17955 opaque_V4SI_type_node
,
17956 opaque_V4SI_type_node
,
17961 enum insn_code icode
= d
->icode
;
17964 if (TARGET_DEBUG_BUILTIN
)
17965 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17971 if (icode
== CODE_FOR_nothing
)
17973 if (TARGET_DEBUG_BUILTIN
)
17974 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
17980 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
17981 insn_data
[icode
].operand
[1].mode
,
17982 insn_data
[icode
].operand
[2].mode
,
17983 insn_data
[icode
].operand
[3].mode
,
17987 def_builtin (d
->name
, type
, d
->code
);
17990 /* Add the binary operators. */
17992 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
17994 machine_mode mode0
, mode1
, mode2
;
17996 HOST_WIDE_INT mask
= d
->mask
;
17998 if ((mask
& builtin_mask
) != mask
)
18000 if (TARGET_DEBUG_BUILTIN
)
18001 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
18005 if (rs6000_overloaded_builtin_p (d
->code
))
18007 if (! (type
= opaque_ftype_opaque_opaque
))
18008 type
= opaque_ftype_opaque_opaque
18009 = build_function_type_list (opaque_V4SI_type_node
,
18010 opaque_V4SI_type_node
,
18011 opaque_V4SI_type_node
,
18016 enum insn_code icode
= d
->icode
;
18019 if (TARGET_DEBUG_BUILTIN
)
18020 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18026 if (icode
== CODE_FOR_nothing
)
18028 if (TARGET_DEBUG_BUILTIN
)
18029 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
18035 mode0
= insn_data
[icode
].operand
[0].mode
;
18036 mode1
= insn_data
[icode
].operand
[1].mode
;
18037 mode2
= insn_data
[icode
].operand
[2].mode
;
18039 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
18043 def_builtin (d
->name
, type
, d
->code
);
18046 /* Add the simple unary operators. */
18048 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
18050 machine_mode mode0
, mode1
;
18052 HOST_WIDE_INT mask
= d
->mask
;
18054 if ((mask
& builtin_mask
) != mask
)
18056 if (TARGET_DEBUG_BUILTIN
)
18057 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
18061 if (rs6000_overloaded_builtin_p (d
->code
))
18063 if (! (type
= opaque_ftype_opaque
))
18064 type
= opaque_ftype_opaque
18065 = build_function_type_list (opaque_V4SI_type_node
,
18066 opaque_V4SI_type_node
,
18071 enum insn_code icode
= d
->icode
;
18074 if (TARGET_DEBUG_BUILTIN
)
18075 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18081 if (icode
== CODE_FOR_nothing
)
18083 if (TARGET_DEBUG_BUILTIN
)
18084 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
18090 mode0
= insn_data
[icode
].operand
[0].mode
;
18091 mode1
= insn_data
[icode
].operand
[1].mode
;
18093 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
18097 def_builtin (d
->name
, type
, d
->code
);
18100 /* Add the simple no-argument operators. */
18102 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
18104 machine_mode mode0
;
18106 HOST_WIDE_INT mask
= d
->mask
;
18108 if ((mask
& builtin_mask
) != mask
)
18110 if (TARGET_DEBUG_BUILTIN
)
18111 fprintf (stderr
, "rs6000_builtin, skip no-argument %s\n", d
->name
);
18114 if (rs6000_overloaded_builtin_p (d
->code
))
18116 if (!opaque_ftype_opaque
)
18117 opaque_ftype_opaque
18118 = build_function_type_list (opaque_V4SI_type_node
, NULL_TREE
);
18119 type
= opaque_ftype_opaque
;
18123 enum insn_code icode
= d
->icode
;
18126 if (TARGET_DEBUG_BUILTIN
)
18127 fprintf (stderr
, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18128 (long unsigned) i
);
18131 if (icode
== CODE_FOR_nothing
)
18133 if (TARGET_DEBUG_BUILTIN
)
18135 "rs6000_builtin, skip no-argument %s (no code)\n",
18139 mode0
= insn_data
[icode
].operand
[0].mode
;
18140 type
= builtin_function_type (mode0
, VOIDmode
, VOIDmode
, VOIDmode
,
18143 def_builtin (d
->name
, type
, d
->code
);
18147 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18149 init_float128_ibm (machine_mode mode
)
18151 if (!TARGET_XL_COMPAT
)
18153 set_optab_libfunc (add_optab
, mode
, "__gcc_qadd");
18154 set_optab_libfunc (sub_optab
, mode
, "__gcc_qsub");
18155 set_optab_libfunc (smul_optab
, mode
, "__gcc_qmul");
18156 set_optab_libfunc (sdiv_optab
, mode
, "__gcc_qdiv");
18158 if (!TARGET_HARD_FLOAT
)
18160 set_optab_libfunc (neg_optab
, mode
, "__gcc_qneg");
18161 set_optab_libfunc (eq_optab
, mode
, "__gcc_qeq");
18162 set_optab_libfunc (ne_optab
, mode
, "__gcc_qne");
18163 set_optab_libfunc (gt_optab
, mode
, "__gcc_qgt");
18164 set_optab_libfunc (ge_optab
, mode
, "__gcc_qge");
18165 set_optab_libfunc (lt_optab
, mode
, "__gcc_qlt");
18166 set_optab_libfunc (le_optab
, mode
, "__gcc_qle");
18167 set_optab_libfunc (unord_optab
, mode
, "__gcc_qunord");
18169 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__gcc_stoq");
18170 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__gcc_dtoq");
18171 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__gcc_qtos");
18172 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__gcc_qtod");
18173 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__gcc_qtoi");
18174 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__gcc_qtou");
18175 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__gcc_itoq");
18176 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__gcc_utoq");
18181 set_optab_libfunc (add_optab
, mode
, "_xlqadd");
18182 set_optab_libfunc (sub_optab
, mode
, "_xlqsub");
18183 set_optab_libfunc (smul_optab
, mode
, "_xlqmul");
18184 set_optab_libfunc (sdiv_optab
, mode
, "_xlqdiv");
18187 /* Add various conversions for IFmode to use the traditional TFmode
18189 if (mode
== IFmode
)
18191 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdtf");
18192 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddtf");
18193 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctdtf");
18194 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunctfsd");
18195 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunctfdd");
18196 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtftd");
18198 if (TARGET_POWERPC64
)
18200 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixtfti");
18201 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunstfti");
18202 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattitf");
18203 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntitf");
18208 /* Create a decl for either complex long double multiply or complex long double
18209 divide when long double is IEEE 128-bit floating point. We can't use
18210 __multc3 and __divtc3 because the original long double using IBM extended
18211 double used those names. The complex multiply/divide functions are encoded
18212 as builtin functions with a complex result and 4 scalar inputs. */
18215 create_complex_muldiv (const char *name
, built_in_function fncode
, tree fntype
)
18217 tree fndecl
= add_builtin_function (name
, fntype
, fncode
, BUILT_IN_NORMAL
,
18220 set_builtin_decl (fncode
, fndecl
, true);
18222 if (TARGET_DEBUG_BUILTIN
)
18223 fprintf (stderr
, "create complex %s, fncode: %d\n", name
, (int) fncode
);
18228 /* Set up IEEE 128-bit floating point routines. Use different names if the
18229 arguments can be passed in a vector register. The historical PowerPC
18230 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18231 continue to use that if we aren't using vector registers to pass IEEE
18232 128-bit floating point. */
18235 init_float128_ieee (machine_mode mode
)
18237 if (FLOAT128_VECTOR_P (mode
))
18239 static bool complex_muldiv_init_p
= false;
18241 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
18242 we have clone or target attributes, this will be called a second
18243 time. We want to create the built-in function only once. */
18244 if (mode
== TFmode
&& TARGET_IEEEQUAD
&& !complex_muldiv_init_p
)
18246 complex_muldiv_init_p
= true;
18247 built_in_function fncode_mul
=
18248 (built_in_function
) (BUILT_IN_COMPLEX_MUL_MIN
+ TCmode
18249 - MIN_MODE_COMPLEX_FLOAT
);
18250 built_in_function fncode_div
=
18251 (built_in_function
) (BUILT_IN_COMPLEX_DIV_MIN
+ TCmode
18252 - MIN_MODE_COMPLEX_FLOAT
);
18254 tree fntype
= build_function_type_list (complex_long_double_type_node
,
18255 long_double_type_node
,
18256 long_double_type_node
,
18257 long_double_type_node
,
18258 long_double_type_node
,
18261 create_complex_muldiv ("__mulkc3", fncode_mul
, fntype
);
18262 create_complex_muldiv ("__divkc3", fncode_div
, fntype
);
18265 set_optab_libfunc (add_optab
, mode
, "__addkf3");
18266 set_optab_libfunc (sub_optab
, mode
, "__subkf3");
18267 set_optab_libfunc (neg_optab
, mode
, "__negkf2");
18268 set_optab_libfunc (smul_optab
, mode
, "__mulkf3");
18269 set_optab_libfunc (sdiv_optab
, mode
, "__divkf3");
18270 set_optab_libfunc (sqrt_optab
, mode
, "__sqrtkf2");
18271 set_optab_libfunc (abs_optab
, mode
, "__abskf2");
18272 set_optab_libfunc (powi_optab
, mode
, "__powikf2");
18274 set_optab_libfunc (eq_optab
, mode
, "__eqkf2");
18275 set_optab_libfunc (ne_optab
, mode
, "__nekf2");
18276 set_optab_libfunc (gt_optab
, mode
, "__gtkf2");
18277 set_optab_libfunc (ge_optab
, mode
, "__gekf2");
18278 set_optab_libfunc (lt_optab
, mode
, "__ltkf2");
18279 set_optab_libfunc (le_optab
, mode
, "__lekf2");
18280 set_optab_libfunc (unord_optab
, mode
, "__unordkf2");
18282 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__extendsfkf2");
18283 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__extenddfkf2");
18284 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__trunckfsf2");
18285 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__trunckfdf2");
18287 set_conv_libfunc (sext_optab
, mode
, IFmode
, "__trunctfkf2");
18288 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18289 set_conv_libfunc (sext_optab
, mode
, TFmode
, "__trunctfkf2");
18291 set_conv_libfunc (trunc_optab
, IFmode
, mode
, "__extendkftf2");
18292 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18293 set_conv_libfunc (trunc_optab
, TFmode
, mode
, "__extendkftf2");
18295 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdkf");
18296 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddkf");
18297 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctdkf");
18298 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunckfsd");
18299 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunckfdd");
18300 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendkftd");
18302 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__fixkfsi");
18303 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__fixunskfsi");
18304 set_conv_libfunc (sfix_optab
, DImode
, mode
, "__fixkfdi");
18305 set_conv_libfunc (ufix_optab
, DImode
, mode
, "__fixunskfdi");
18307 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__floatsikf");
18308 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__floatunsikf");
18309 set_conv_libfunc (sfloat_optab
, mode
, DImode
, "__floatdikf");
18310 set_conv_libfunc (ufloat_optab
, mode
, DImode
, "__floatundikf");
18312 if (TARGET_POWERPC64
)
18314 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixkfti");
18315 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunskfti");
18316 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattikf");
18317 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntikf");
18323 set_optab_libfunc (add_optab
, mode
, "_q_add");
18324 set_optab_libfunc (sub_optab
, mode
, "_q_sub");
18325 set_optab_libfunc (neg_optab
, mode
, "_q_neg");
18326 set_optab_libfunc (smul_optab
, mode
, "_q_mul");
18327 set_optab_libfunc (sdiv_optab
, mode
, "_q_div");
18328 if (TARGET_PPC_GPOPT
)
18329 set_optab_libfunc (sqrt_optab
, mode
, "_q_sqrt");
18331 set_optab_libfunc (eq_optab
, mode
, "_q_feq");
18332 set_optab_libfunc (ne_optab
, mode
, "_q_fne");
18333 set_optab_libfunc (gt_optab
, mode
, "_q_fgt");
18334 set_optab_libfunc (ge_optab
, mode
, "_q_fge");
18335 set_optab_libfunc (lt_optab
, mode
, "_q_flt");
18336 set_optab_libfunc (le_optab
, mode
, "_q_fle");
18338 set_conv_libfunc (sext_optab
, mode
, SFmode
, "_q_stoq");
18339 set_conv_libfunc (sext_optab
, mode
, DFmode
, "_q_dtoq");
18340 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "_q_qtos");
18341 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "_q_qtod");
18342 set_conv_libfunc (sfix_optab
, SImode
, mode
, "_q_qtoi");
18343 set_conv_libfunc (ufix_optab
, SImode
, mode
, "_q_qtou");
18344 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "_q_itoq");
18345 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "_q_utoq");
18350 rs6000_init_libfuncs (void)
18352 /* __float128 support. */
18353 if (TARGET_FLOAT128_TYPE
)
18355 init_float128_ibm (IFmode
);
18356 init_float128_ieee (KFmode
);
18359 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18360 if (TARGET_LONG_DOUBLE_128
)
18362 if (!TARGET_IEEEQUAD
)
18363 init_float128_ibm (TFmode
);
18365 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18367 init_float128_ieee (TFmode
);
18371 /* Emit a potentially record-form instruction, setting DST from SRC.
18372 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18373 signed comparison of DST with zero. If DOT is 1, the generated RTL
18374 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18375 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18376 a separate COMPARE. */
18379 rs6000_emit_dot_insn (rtx dst
, rtx src
, int dot
, rtx ccreg
)
18383 emit_move_insn (dst
, src
);
18387 if (cc_reg_not_cr0_operand (ccreg
, CCmode
))
18389 emit_move_insn (dst
, src
);
18390 emit_move_insn (ccreg
, gen_rtx_COMPARE (CCmode
, dst
, const0_rtx
));
18394 rtx ccset
= gen_rtx_SET (ccreg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
));
18397 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, dst
);
18398 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, clobber
)));
18402 rtx set
= gen_rtx_SET (dst
, src
);
18403 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, set
)));
18408 /* A validation routine: say whether CODE, a condition code, and MODE
18409 match. The other alternatives either don't make sense or should
18410 never be generated. */
18413 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
18415 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
18416 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
18417 && GET_MODE_CLASS (mode
) == MODE_CC
);
18419 /* These don't make sense. */
18420 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
18421 || mode
!= CCUNSmode
);
18423 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
18424 || mode
== CCUNSmode
);
18426 gcc_assert (mode
== CCFPmode
18427 || (code
!= ORDERED
&& code
!= UNORDERED
18428 && code
!= UNEQ
&& code
!= LTGT
18429 && code
!= UNGT
&& code
!= UNLT
18430 && code
!= UNGE
&& code
!= UNLE
));
18432 /* These should never be generated except for
18433 flag_finite_math_only. */
18434 gcc_assert (mode
!= CCFPmode
18435 || flag_finite_math_only
18436 || (code
!= LE
&& code
!= GE
18437 && code
!= UNEQ
&& code
!= LTGT
18438 && code
!= UNGT
&& code
!= UNLT
));
18440 /* These are invalid; the information is not there. */
18441 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
18445 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18446 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18447 not zero, store there the bit offset (counted from the right) where
18448 the single stretch of 1 bits begins; and similarly for B, the bit
18449 offset where it ends. */
18452 rs6000_is_valid_mask (rtx mask
, int *b
, int *e
, machine_mode mode
)
18454 unsigned HOST_WIDE_INT val
= INTVAL (mask
);
18455 unsigned HOST_WIDE_INT bit
;
18457 int n
= GET_MODE_PRECISION (mode
);
18459 if (mode
!= DImode
&& mode
!= SImode
)
18462 if (INTVAL (mask
) >= 0)
18465 ne
= exact_log2 (bit
);
18466 nb
= exact_log2 (val
+ bit
);
18468 else if (val
+ 1 == 0)
18477 nb
= exact_log2 (bit
);
18478 ne
= exact_log2 (val
+ bit
);
18483 ne
= exact_log2 (bit
);
18484 if (val
+ bit
== 0)
18492 if (nb
< 0 || ne
< 0 || nb
>= n
|| ne
>= n
)
18503 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18504 or rldicr instruction, to implement an AND with it in mode MODE. */
18507 rs6000_is_valid_and_mask (rtx mask
, machine_mode mode
)
18511 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18514 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18516 if (mode
== DImode
)
18517 return (ne
== 0 || nb
== 63 || (nb
< 32 && ne
<= nb
));
18519 /* For SImode, rlwinm can do everything. */
18520 if (mode
== SImode
)
18521 return (nb
< 32 && ne
< 32);
18526 /* Return the instruction template for an AND with mask in mode MODE, with
18527 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18530 rs6000_insn_for_and_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18534 if (!rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
))
18535 gcc_unreachable ();
18537 if (mode
== DImode
&& ne
== 0)
18539 operands
[3] = GEN_INT (63 - nb
);
18541 return "rldicl. %0,%1,0,%3";
18542 return "rldicl %0,%1,0,%3";
18545 if (mode
== DImode
&& nb
== 63)
18547 operands
[3] = GEN_INT (63 - ne
);
18549 return "rldicr. %0,%1,0,%3";
18550 return "rldicr %0,%1,0,%3";
18553 if (nb
< 32 && ne
< 32)
18555 operands
[3] = GEN_INT (31 - nb
);
18556 operands
[4] = GEN_INT (31 - ne
);
18558 return "rlwinm. %0,%1,0,%3,%4";
18559 return "rlwinm %0,%1,0,%3,%4";
18562 gcc_unreachable ();
18565 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18566 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18567 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18570 rs6000_is_valid_shift_mask (rtx mask
, rtx shift
, machine_mode mode
)
18574 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18577 int n
= GET_MODE_PRECISION (mode
);
18580 if (CONST_INT_P (XEXP (shift
, 1)))
18582 sh
= INTVAL (XEXP (shift
, 1));
18583 if (sh
< 0 || sh
>= n
)
18587 rtx_code code
= GET_CODE (shift
);
18589 /* Convert any shift by 0 to a rotate, to simplify below code. */
18593 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18594 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18596 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18602 /* DImode rotates need rld*. */
18603 if (mode
== DImode
&& code
== ROTATE
)
18604 return (nb
== 63 || ne
== 0 || ne
== sh
);
18606 /* SImode rotates need rlw*. */
18607 if (mode
== SImode
&& code
== ROTATE
)
18608 return (nb
< 32 && ne
< 32 && sh
< 32);
18610 /* Wrap-around masks are only okay for rotates. */
18614 /* Variable shifts are only okay for rotates. */
18618 /* Don't allow ASHIFT if the mask is wrong for that. */
18619 if (code
== ASHIFT
&& ne
< sh
)
18622 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18623 if the mask is wrong for that. */
18624 if (nb
< 32 && ne
< 32 && sh
< 32
18625 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18628 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18629 if the mask is wrong for that. */
18630 if (code
== LSHIFTRT
)
18632 if (nb
== 63 || ne
== 0 || ne
== sh
)
18633 return !(code
== LSHIFTRT
&& nb
>= sh
);
18638 /* Return the instruction template for a shift with mask in mode MODE, with
18639 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18642 rs6000_insn_for_shift_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18646 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18647 gcc_unreachable ();
18649 if (mode
== DImode
&& ne
== 0)
18651 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18652 operands
[2] = GEN_INT (64 - INTVAL (operands
[2]));
18653 operands
[3] = GEN_INT (63 - nb
);
18655 return "rld%I2cl. %0,%1,%2,%3";
18656 return "rld%I2cl %0,%1,%2,%3";
18659 if (mode
== DImode
&& nb
== 63)
18661 operands
[3] = GEN_INT (63 - ne
);
18663 return "rld%I2cr. %0,%1,%2,%3";
18664 return "rld%I2cr %0,%1,%2,%3";
18668 && GET_CODE (operands
[4]) != LSHIFTRT
18669 && CONST_INT_P (operands
[2])
18670 && ne
== INTVAL (operands
[2]))
18672 operands
[3] = GEN_INT (63 - nb
);
18674 return "rld%I2c. %0,%1,%2,%3";
18675 return "rld%I2c %0,%1,%2,%3";
18678 if (nb
< 32 && ne
< 32)
18680 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18681 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
18682 operands
[3] = GEN_INT (31 - nb
);
18683 operands
[4] = GEN_INT (31 - ne
);
18684 /* This insn can also be a 64-bit rotate with mask that really makes
18685 it just a shift right (with mask); the %h below are to adjust for
18686 that situation (shift count is >= 32 in that case). */
18688 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18689 return "rlw%I2nm %0,%1,%h2,%3,%4";
18692 gcc_unreachable ();
18695 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18696 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18697 ASHIFT, or LSHIFTRT) in mode MODE. */
18700 rs6000_is_valid_insert_mask (rtx mask
, rtx shift
, machine_mode mode
)
18704 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
18707 int n
= GET_MODE_PRECISION (mode
);
18709 int sh
= INTVAL (XEXP (shift
, 1));
18710 if (sh
< 0 || sh
>= n
)
18713 rtx_code code
= GET_CODE (shift
);
18715 /* Convert any shift by 0 to a rotate, to simplify below code. */
18719 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18720 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
18722 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
18728 /* DImode rotates need rldimi. */
18729 if (mode
== DImode
&& code
== ROTATE
)
18732 /* SImode rotates need rlwimi. */
18733 if (mode
== SImode
&& code
== ROTATE
)
18734 return (nb
< 32 && ne
< 32 && sh
< 32);
18736 /* Wrap-around masks are only okay for rotates. */
18740 /* Don't allow ASHIFT if the mask is wrong for that. */
18741 if (code
== ASHIFT
&& ne
< sh
)
18744 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18745 if the mask is wrong for that. */
18746 if (nb
< 32 && ne
< 32 && sh
< 32
18747 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
18750 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18751 if the mask is wrong for that. */
18752 if (code
== LSHIFTRT
)
18755 return !(code
== LSHIFTRT
&& nb
>= sh
);
18760 /* Return the instruction template for an insert with mask in mode MODE, with
18761 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18764 rs6000_insn_for_insert_mask (machine_mode mode
, rtx
*operands
, bool dot
)
18768 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
18769 gcc_unreachable ();
18771 /* Prefer rldimi because rlwimi is cracked. */
18772 if (TARGET_POWERPC64
18773 && (!dot
|| mode
== DImode
)
18774 && GET_CODE (operands
[4]) != LSHIFTRT
18775 && ne
== INTVAL (operands
[2]))
18777 operands
[3] = GEN_INT (63 - nb
);
18779 return "rldimi. %0,%1,%2,%3";
18780 return "rldimi %0,%1,%2,%3";
18783 if (nb
< 32 && ne
< 32)
18785 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
18786 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
18787 operands
[3] = GEN_INT (31 - nb
);
18788 operands
[4] = GEN_INT (31 - ne
);
18790 return "rlwimi. %0,%1,%2,%3,%4";
18791 return "rlwimi %0,%1,%2,%3,%4";
18794 gcc_unreachable ();
18797 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18798 using two machine instructions. */
18801 rs6000_is_valid_2insn_and (rtx c
, machine_mode mode
)
18803 /* There are two kinds of AND we can handle with two insns:
18804 1) those we can do with two rl* insn;
18807 We do not handle that last case yet. */
18809 /* If there is just one stretch of ones, we can do it. */
18810 if (rs6000_is_valid_mask (c
, NULL
, NULL
, mode
))
18813 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18814 one insn, we can do the whole thing with two. */
18815 unsigned HOST_WIDE_INT val
= INTVAL (c
);
18816 unsigned HOST_WIDE_INT bit1
= val
& -val
;
18817 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
18818 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
18819 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
18820 return rs6000_is_valid_and_mask (GEN_INT (val
+ bit3
- bit2
), mode
);
18823 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18824 If EXPAND is true, split rotate-and-mask instructions we generate to
18825 their constituent parts as well (this is used during expand); if DOT
18826 is 1, make the last insn a record-form instruction clobbering the
18827 destination GPR and setting the CC reg (from operands[3]); if 2, set
18828 that GPR as well as the CC reg. */
18831 rs6000_emit_2insn_and (machine_mode mode
, rtx
*operands
, bool expand
, int dot
)
18833 gcc_assert (!(expand
&& dot
));
18835 unsigned HOST_WIDE_INT val
= INTVAL (operands
[2]);
18837 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18838 shift right. This generates better code than doing the masks without
18839 shifts, or shifting first right and then left. */
18841 if (rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
) && nb
>= ne
)
18843 gcc_assert (mode
== DImode
);
18845 int shift
= 63 - nb
;
18848 rtx tmp1
= gen_reg_rtx (DImode
);
18849 rtx tmp2
= gen_reg_rtx (DImode
);
18850 emit_insn (gen_ashldi3 (tmp1
, operands
[1], GEN_INT (shift
)));
18851 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (val
<< shift
)));
18852 emit_insn (gen_lshrdi3 (operands
[0], tmp2
, GEN_INT (shift
)));
18856 rtx tmp
= gen_rtx_ASHIFT (mode
, operands
[1], GEN_INT (shift
));
18857 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (val
<< shift
));
18858 emit_move_insn (operands
[0], tmp
);
18859 tmp
= gen_rtx_LSHIFTRT (mode
, operands
[0], GEN_INT (shift
));
18860 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18865 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18866 that does the rest. */
18867 unsigned HOST_WIDE_INT bit1
= val
& -val
;
18868 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
18869 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
18870 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
18872 unsigned HOST_WIDE_INT mask1
= -bit3
+ bit2
- 1;
18873 unsigned HOST_WIDE_INT mask2
= val
+ bit3
- bit2
;
18875 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2
), mode
));
18877 /* Two "no-rotate"-and-mask instructions, for SImode. */
18878 if (rs6000_is_valid_and_mask (GEN_INT (mask1
), mode
))
18880 gcc_assert (mode
== SImode
);
18882 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
18883 rtx tmp
= gen_rtx_AND (mode
, operands
[1], GEN_INT (mask1
));
18884 emit_move_insn (reg
, tmp
);
18885 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
18886 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18890 gcc_assert (mode
== DImode
);
18892 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18893 insns; we have to do the first in SImode, because it wraps. */
18894 if (mask2
<= 0xffffffff
18895 && rs6000_is_valid_and_mask (GEN_INT (mask1
), SImode
))
18897 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
18898 rtx tmp
= gen_rtx_AND (SImode
, gen_lowpart (SImode
, operands
[1]),
18900 rtx reg_low
= gen_lowpart (SImode
, reg
);
18901 emit_move_insn (reg_low
, tmp
);
18902 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
18903 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18907 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18908 at the top end), rotate back and clear the other hole. */
18909 int right
= exact_log2 (bit3
);
18910 int left
= 64 - right
;
18912 /* Rotate the mask too. */
18913 mask1
= (mask1
>> right
) | ((bit2
- 1) << left
);
18917 rtx tmp1
= gen_reg_rtx (DImode
);
18918 rtx tmp2
= gen_reg_rtx (DImode
);
18919 rtx tmp3
= gen_reg_rtx (DImode
);
18920 emit_insn (gen_rotldi3 (tmp1
, operands
[1], GEN_INT (left
)));
18921 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (mask1
)));
18922 emit_insn (gen_rotldi3 (tmp3
, tmp2
, GEN_INT (right
)));
18923 emit_insn (gen_anddi3 (operands
[0], tmp3
, GEN_INT (mask2
)));
18927 rtx tmp
= gen_rtx_ROTATE (mode
, operands
[1], GEN_INT (left
));
18928 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask1
));
18929 emit_move_insn (operands
[0], tmp
);
18930 tmp
= gen_rtx_ROTATE (mode
, operands
[0], GEN_INT (right
));
18931 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask2
));
18932 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
18936 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18937 for lfq and stfq insns iff the registers are hard registers. */
18940 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
18942 /* We might have been passed a SUBREG. */
18943 if (!REG_P (reg1
) || !REG_P (reg2
))
18946 /* We might have been passed non floating point registers. */
18947 if (!FP_REGNO_P (REGNO (reg1
))
18948 || !FP_REGNO_P (REGNO (reg2
)))
18951 return (REGNO (reg1
) == REGNO (reg2
) - 1);
18954 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18955 addr1 and addr2 must be in consecutive memory locations
18956 (addr2 == addr1 + 8). */
18959 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
18962 unsigned int reg1
, reg2
;
18963 int offset1
, offset2
;
18965 /* The mems cannot be volatile. */
18966 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
18969 addr1
= XEXP (mem1
, 0);
18970 addr2
= XEXP (mem2
, 0);
18972 /* Extract an offset (if used) from the first addr. */
18973 if (GET_CODE (addr1
) == PLUS
)
18975 /* If not a REG, return zero. */
18976 if (!REG_P (XEXP (addr1
, 0)))
18980 reg1
= REGNO (XEXP (addr1
, 0));
18981 /* The offset must be constant! */
18982 if (!CONST_INT_P (XEXP (addr1
, 1)))
18984 offset1
= INTVAL (XEXP (addr1
, 1));
18987 else if (!REG_P (addr1
))
18991 reg1
= REGNO (addr1
);
18992 /* This was a simple (mem (reg)) expression. Offset is 0. */
18996 /* And now for the second addr. */
18997 if (GET_CODE (addr2
) == PLUS
)
18999 /* If not a REG, return zero. */
19000 if (!REG_P (XEXP (addr2
, 0)))
19004 reg2
= REGNO (XEXP (addr2
, 0));
19005 /* The offset must be constant. */
19006 if (!CONST_INT_P (XEXP (addr2
, 1)))
19008 offset2
= INTVAL (XEXP (addr2
, 1));
19011 else if (!REG_P (addr2
))
19015 reg2
= REGNO (addr2
);
19016 /* This was a simple (mem (reg)) expression. Offset is 0. */
19020 /* Both of these must have the same base register. */
19024 /* The offset for the second addr must be 8 more than the first addr. */
19025 if (offset2
!= offset1
+ 8)
19028 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
19033 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
19034 need to use DDmode, in all other cases we can use the same mode. */
19035 static machine_mode
19036 rs6000_secondary_memory_needed_mode (machine_mode mode
)
19038 if (lra_in_progress
&& mode
== SDmode
)
19043 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
19044 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
19045 only work on the traditional altivec registers, note if an altivec register
19048 static enum rs6000_reg_type
19049 register_to_reg_type (rtx reg
, bool *is_altivec
)
19051 HOST_WIDE_INT regno
;
19052 enum reg_class rclass
;
19054 if (SUBREG_P (reg
))
19055 reg
= SUBREG_REG (reg
);
19058 return NO_REG_TYPE
;
19060 regno
= REGNO (reg
);
19061 if (!HARD_REGISTER_NUM_P (regno
))
19063 if (!lra_in_progress
&& !reload_completed
)
19064 return PSEUDO_REG_TYPE
;
19066 regno
= true_regnum (reg
);
19067 if (regno
< 0 || !HARD_REGISTER_NUM_P (regno
))
19068 return PSEUDO_REG_TYPE
;
19071 gcc_assert (regno
>= 0);
19073 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
19074 *is_altivec
= true;
19076 rclass
= rs6000_regno_regclass
[regno
];
19077 return reg_class_to_reg_type
[(int)rclass
];
19080 /* Helper function to return the cost of adding a TOC entry address. */
19083 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
19087 if (TARGET_CMODEL
!= CMODEL_SMALL
)
19088 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
19091 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
19096 /* Helper function for rs6000_secondary_reload to determine whether the memory
19097 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
19098 needs reloading. Return negative if the memory is not handled by the memory
19099 helper functions and to try a different reload method, 0 if no additional
19100 instructions are need, and positive to give the extra cost for the
19104 rs6000_secondary_reload_memory (rtx addr
,
19105 enum reg_class rclass
,
19108 int extra_cost
= 0;
19109 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
19110 addr_mask_type addr_mask
;
19111 const char *type
= NULL
;
19112 const char *fail_msg
= NULL
;
19114 if (GPR_REG_CLASS_P (rclass
))
19115 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
19117 else if (rclass
== FLOAT_REGS
)
19118 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
19120 else if (rclass
== ALTIVEC_REGS
)
19121 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
19123 /* For the combined VSX_REGS, turn off Altivec AND -16. */
19124 else if (rclass
== VSX_REGS
)
19125 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
19126 & ~RELOAD_REG_AND_M16
);
19128 /* If the register allocator hasn't made up its mind yet on the register
19129 class to use, settle on defaults to use. */
19130 else if (rclass
== NO_REGS
)
19132 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
]
19133 & ~RELOAD_REG_AND_M16
);
19135 if ((addr_mask
& RELOAD_REG_MULTIPLE
) != 0)
19136 addr_mask
&= ~(RELOAD_REG_INDEXED
19137 | RELOAD_REG_PRE_INCDEC
19138 | RELOAD_REG_PRE_MODIFY
);
19144 /* If the register isn't valid in this register class, just return now. */
19145 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
19147 if (TARGET_DEBUG_ADDR
)
19150 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19151 "not valid in class\n",
19152 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
19159 switch (GET_CODE (addr
))
19161 /* Does the register class supports auto update forms for this mode? We
19162 don't need a scratch register, since the powerpc only supports
19163 PRE_INC, PRE_DEC, and PRE_MODIFY. */
19166 reg
= XEXP (addr
, 0);
19167 if (!base_reg_operand (addr
, GET_MODE (reg
)))
19169 fail_msg
= "no base register #1";
19173 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
19181 reg
= XEXP (addr
, 0);
19182 plus_arg1
= XEXP (addr
, 1);
19183 if (!base_reg_operand (reg
, GET_MODE (reg
))
19184 || GET_CODE (plus_arg1
) != PLUS
19185 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
19187 fail_msg
= "bad PRE_MODIFY";
19191 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
19198 /* Do we need to simulate AND -16 to clear the bottom address bits used
19199 in VMX load/stores? Only allow the AND for vector sizes. */
19201 and_arg
= XEXP (addr
, 0);
19202 if (GET_MODE_SIZE (mode
) != 16
19203 || !CONST_INT_P (XEXP (addr
, 1))
19204 || INTVAL (XEXP (addr
, 1)) != -16)
19206 fail_msg
= "bad Altivec AND #1";
19210 if (rclass
!= ALTIVEC_REGS
)
19212 if (legitimate_indirect_address_p (and_arg
, false))
19215 else if (legitimate_indexed_address_p (and_arg
, false))
19220 fail_msg
= "bad Altivec AND #2";
19228 /* If this is an indirect address, make sure it is a base register. */
19231 if (!legitimate_indirect_address_p (addr
, false))
19238 /* If this is an indexed address, make sure the register class can handle
19239 indexed addresses for this mode. */
19241 plus_arg0
= XEXP (addr
, 0);
19242 plus_arg1
= XEXP (addr
, 1);
19244 /* (plus (plus (reg) (constant)) (constant)) is generated during
19245 push_reload processing, so handle it now. */
19246 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
19248 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19255 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19256 push_reload processing, so handle it now. */
19257 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
19259 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19262 type
= "indexed #2";
19266 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
19268 fail_msg
= "no base register #2";
19272 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
19274 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
19275 || !legitimate_indexed_address_p (addr
, false))
19282 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0
19283 && CONST_INT_P (plus_arg1
))
19285 if (!quad_address_offset_p (INTVAL (plus_arg1
)))
19288 type
= "vector d-form offset";
19292 /* Make sure the register class can handle offset addresses. */
19293 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
19295 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19298 type
= "offset #2";
19304 fail_msg
= "bad PLUS";
19311 /* Quad offsets are restricted and can't handle normal addresses. */
19312 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19315 type
= "vector d-form lo_sum";
19318 else if (!legitimate_lo_sum_address_p (mode
, addr
, false))
19320 fail_msg
= "bad LO_SUM";
19324 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19331 /* Static addresses need to create a TOC entry. */
19335 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19338 type
= "vector d-form lo_sum #2";
19344 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
19348 /* TOC references look like offsetable memory. */
19350 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
19352 fail_msg
= "bad UNSPEC";
19356 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
19359 type
= "vector d-form lo_sum #3";
19362 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
19365 type
= "toc reference";
19371 fail_msg
= "bad address";
19376 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
19378 if (extra_cost
< 0)
19380 "rs6000_secondary_reload_memory error: mode = %s, "
19381 "class = %s, addr_mask = '%s', %s\n",
19382 GET_MODE_NAME (mode
),
19383 reg_class_names
[rclass
],
19384 rs6000_debug_addr_mask (addr_mask
, false),
19385 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
19389 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19390 "addr_mask = '%s', extra cost = %d, %s\n",
19391 GET_MODE_NAME (mode
),
19392 reg_class_names
[rclass
],
19393 rs6000_debug_addr_mask (addr_mask
, false),
19395 (type
) ? type
: "<none>");
19403 /* Helper function for rs6000_secondary_reload to return true if a move to a
19404 different register classe is really a simple move. */
19407 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
19408 enum rs6000_reg_type from_type
,
19411 int size
= GET_MODE_SIZE (mode
);
19413 /* Add support for various direct moves available. In this function, we only
19414 look at cases where we don't need any extra registers, and one or more
19415 simple move insns are issued. Originally small integers are not allowed
19416 in FPR/VSX registers. Single precision binary floating is not a simple
19417 move because we need to convert to the single precision memory layout.
19418 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19419 need special direct move handling, which we do not support yet. */
19420 if (TARGET_DIRECT_MOVE
19421 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19422 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19424 if (TARGET_POWERPC64
)
19426 /* ISA 2.07: MTVSRD or MVFVSRD. */
19430 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19431 if (size
== 16 && TARGET_P9_VECTOR
&& mode
!= TDmode
)
19435 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19436 if (TARGET_P8_VECTOR
)
19438 if (mode
== SImode
)
19441 if (TARGET_P9_VECTOR
&& (mode
== HImode
|| mode
== QImode
))
19445 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19446 if (mode
== SDmode
)
19450 /* Power6+: MFTGPR or MFFGPR. */
19451 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
19452 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
19453 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19456 /* Move to/from SPR. */
19457 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
19458 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
19459 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
19465 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19466 special direct moves that involve allocating an extra register, return the
19467 insn code of the helper function if there is such a function or
19468 CODE_FOR_nothing if not. */
19471 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
19472 enum rs6000_reg_type from_type
,
19474 secondary_reload_info
*sri
,
19478 enum insn_code icode
= CODE_FOR_nothing
;
19480 int size
= GET_MODE_SIZE (mode
);
19482 if (TARGET_POWERPC64
&& size
== 16)
19484 /* Handle moving 128-bit values from GPRs to VSX point registers on
19485 ISA 2.07 (power8, power9) when running in 64-bit mode using
19486 XXPERMDI to glue the two 64-bit values back together. */
19487 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19489 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
19490 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19493 /* Handle moving 128-bit values from VSX point registers to GPRs on
19494 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19495 bottom 64-bit value. */
19496 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19498 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
19499 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19503 else if (TARGET_POWERPC64
&& mode
== SFmode
)
19505 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
19507 cost
= 3; /* xscvdpspn, mfvsrd, and. */
19508 icode
= reg_addr
[mode
].reload_gpr_vsx
;
19511 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
19513 cost
= 2; /* mtvsrz, xscvspdpn. */
19514 icode
= reg_addr
[mode
].reload_vsx_gpr
;
19518 else if (!TARGET_POWERPC64
&& size
== 8)
19520 /* Handle moving 64-bit values from GPRs to floating point registers on
19521 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19522 32-bit values back together. Altivec register classes must be handled
19523 specially since a different instruction is used, and the secondary
19524 reload support requires a single instruction class in the scratch
19525 register constraint. However, right now TFmode is not allowed in
19526 Altivec registers, so the pattern will never match. */
19527 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
19529 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
19530 icode
= reg_addr
[mode
].reload_fpr_gpr
;
19534 if (icode
!= CODE_FOR_nothing
)
19539 sri
->icode
= icode
;
19540 sri
->extra_cost
= cost
;
19547 /* Return whether a move between two register classes can be done either
19548 directly (simple move) or via a pattern that uses a single extra temporary
19549 (using ISA 2.07's direct move in this case. */
19552 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
19553 enum rs6000_reg_type from_type
,
19555 secondary_reload_info
*sri
,
19558 /* Fall back to load/store reloads if either type is not a register. */
19559 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
19562 /* If we haven't allocated registers yet, assume the move can be done for the
19563 standard register types. */
19564 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
19565 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
19566 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
19569 /* Moves to the same set of registers is a simple move for non-specialized
19571 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
19574 /* Check whether a simple move can be done directly. */
19575 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
19579 sri
->icode
= CODE_FOR_nothing
;
19580 sri
->extra_cost
= 0;
19585 /* Now check if we can do it in a few steps. */
19586 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
19590 /* Inform reload about cases where moving X with a mode MODE to a register in
19591 RCLASS requires an extra scratch or immediate register. Return the class
19592 needed for the immediate register.
19594 For VSX and Altivec, we may need a register to convert sp+offset into
19597 For misaligned 64-bit gpr loads and stores we need a register to
19598 convert an offset address to indirect. */
19601 rs6000_secondary_reload (bool in_p
,
19603 reg_class_t rclass_i
,
19605 secondary_reload_info
*sri
)
19607 enum reg_class rclass
= (enum reg_class
) rclass_i
;
19608 reg_class_t ret
= ALL_REGS
;
19609 enum insn_code icode
;
19610 bool default_p
= false;
19611 bool done_p
= false;
19613 /* Allow subreg of memory before/during reload. */
19614 bool memory_p
= (MEM_P (x
)
19615 || (!reload_completed
&& SUBREG_P (x
)
19616 && MEM_P (SUBREG_REG (x
))));
19618 sri
->icode
= CODE_FOR_nothing
;
19619 sri
->t_icode
= CODE_FOR_nothing
;
19620 sri
->extra_cost
= 0;
19622 ? reg_addr
[mode
].reload_load
19623 : reg_addr
[mode
].reload_store
);
19625 if (REG_P (x
) || register_operand (x
, mode
))
19627 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
19628 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
19629 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
19632 std::swap (to_type
, from_type
);
19634 /* Can we do a direct move of some sort? */
19635 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
19638 icode
= (enum insn_code
)sri
->icode
;
19645 /* Make sure 0.0 is not reloaded or forced into memory. */
19646 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
19653 /* If this is a scalar floating point value and we want to load it into the
19654 traditional Altivec registers, do it via a move via a traditional floating
19655 point register, unless we have D-form addressing. Also make sure that
19656 non-zero constants use a FPR. */
19657 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
19658 && !mode_supports_vmx_dform (mode
)
19659 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
19660 && (memory_p
|| CONST_DOUBLE_P (x
)))
19667 /* Handle reload of load/stores if we have reload helper functions. */
19668 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
19670 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
19673 if (extra_cost
>= 0)
19677 if (extra_cost
> 0)
19679 sri
->extra_cost
= extra_cost
;
19680 sri
->icode
= icode
;
19685 /* Handle unaligned loads and stores of integer registers. */
19686 if (!done_p
&& TARGET_POWERPC64
19687 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19689 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
19691 rtx addr
= XEXP (x
, 0);
19692 rtx off
= address_offset (addr
);
19694 if (off
!= NULL_RTX
)
19696 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19697 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19699 /* We need a secondary reload when our legitimate_address_p
19700 says the address is good (as otherwise the entire address
19701 will be reloaded), and the offset is not a multiple of
19702 four or we have an address wrap. Address wrap will only
19703 occur for LO_SUMs since legitimate_offset_address_p
19704 rejects addresses for 16-byte mems that will wrap. */
19705 if (GET_CODE (addr
) == LO_SUM
19706 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19707 && ((offset
& 3) != 0
19708 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
19709 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
19710 && (offset
& 3) != 0))
19712 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19714 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
19715 : CODE_FOR_reload_di_load
);
19717 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
19718 : CODE_FOR_reload_di_store
);
19719 sri
->extra_cost
= 2;
19730 if (!done_p
&& !TARGET_POWERPC64
19731 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
19733 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
19735 rtx addr
= XEXP (x
, 0);
19736 rtx off
= address_offset (addr
);
19738 if (off
!= NULL_RTX
)
19740 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
19741 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
19743 /* We need a secondary reload when our legitimate_address_p
19744 says the address is good (as otherwise the entire address
19745 will be reloaded), and we have a wrap.
19747 legitimate_lo_sum_address_p allows LO_SUM addresses to
19748 have any offset so test for wrap in the low 16 bits.
19750 legitimate_offset_address_p checks for the range
19751 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19752 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19753 [0x7ff4,0x7fff] respectively, so test for the
19754 intersection of these ranges, [0x7ffc,0x7fff] and
19755 [0x7ff4,0x7ff7] respectively.
19757 Note that the address we see here may have been
19758 manipulated by legitimize_reload_address. */
19759 if (GET_CODE (addr
) == LO_SUM
19760 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
19761 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
19764 sri
->icode
= CODE_FOR_reload_si_load
;
19766 sri
->icode
= CODE_FOR_reload_si_store
;
19767 sri
->extra_cost
= 2;
19782 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
19784 gcc_assert (ret
!= ALL_REGS
);
19786 if (TARGET_DEBUG_ADDR
)
19789 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19791 reg_class_names
[ret
],
19792 in_p
? "true" : "false",
19793 reg_class_names
[rclass
],
19794 GET_MODE_NAME (mode
));
19796 if (reload_completed
)
19797 fputs (", after reload", stderr
);
19800 fputs (", done_p not set", stderr
);
19803 fputs (", default secondary reload", stderr
);
19805 if (sri
->icode
!= CODE_FOR_nothing
)
19806 fprintf (stderr
, ", reload func = %s, extra cost = %d",
19807 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
19809 else if (sri
->extra_cost
> 0)
19810 fprintf (stderr
, ", extra cost = %d", sri
->extra_cost
);
19812 fputs ("\n", stderr
);
19819 /* Better tracing for rs6000_secondary_reload_inner. */
19822 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
19827 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
19829 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
19830 store_p
? "store" : "load");
19833 set
= gen_rtx_SET (mem
, reg
);
19835 set
= gen_rtx_SET (reg
, mem
);
19837 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
19838 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
19841 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
19842 ATTRIBUTE_NORETURN
;
19845 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
19848 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
19849 gcc_unreachable ();
19852 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19853 reload helper functions. These were identified in
19854 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19855 reload, it calls the insns:
19856 reload_<RELOAD:mode>_<P:mptrsize>_store
19857 reload_<RELOAD:mode>_<P:mptrsize>_load
19859 which in turn calls this function, to do whatever is necessary to create
19860 valid addresses. */
19863 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
19865 int regno
= true_regnum (reg
);
19866 machine_mode mode
= GET_MODE (reg
);
19867 addr_mask_type addr_mask
;
19870 rtx op_reg
, op0
, op1
;
19875 if (regno
< 0 || !HARD_REGISTER_NUM_P (regno
) || !MEM_P (mem
)
19876 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
19877 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19879 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
19880 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
19882 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
19883 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
19885 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
19886 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
19889 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19891 /* Make sure the mode is valid in this register class. */
19892 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
19893 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19895 if (TARGET_DEBUG_ADDR
)
19896 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
19898 new_addr
= addr
= XEXP (mem
, 0);
19899 switch (GET_CODE (addr
))
19901 /* Does the register class support auto update forms for this mode? If
19902 not, do the update now. We don't need a scratch register, since the
19903 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19906 op_reg
= XEXP (addr
, 0);
19907 if (!base_reg_operand (op_reg
, Pmode
))
19908 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19910 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
19912 int delta
= GET_MODE_SIZE (mode
);
19913 if (GET_CODE (addr
) == PRE_DEC
)
19915 emit_insn (gen_add2_insn (op_reg
, GEN_INT (delta
)));
19921 op0
= XEXP (addr
, 0);
19922 op1
= XEXP (addr
, 1);
19923 if (!base_reg_operand (op0
, Pmode
)
19924 || GET_CODE (op1
) != PLUS
19925 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
19926 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19928 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
19930 emit_insn (gen_rtx_SET (op0
, op1
));
19935 /* Do we need to simulate AND -16 to clear the bottom address bits used
19936 in VMX load/stores? */
19938 op0
= XEXP (addr
, 0);
19939 op1
= XEXP (addr
, 1);
19940 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
19942 if (REG_P (op0
) || SUBREG_P (op0
))
19945 else if (GET_CODE (op1
) == PLUS
)
19947 emit_insn (gen_rtx_SET (scratch
, op1
));
19952 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19954 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
19955 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
19956 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
19957 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
19958 new_addr
= scratch
;
19962 /* If this is an indirect address, make sure it is a base register. */
19965 if (!base_reg_operand (addr
, GET_MODE (addr
)))
19967 emit_insn (gen_rtx_SET (scratch
, addr
));
19968 new_addr
= scratch
;
19972 /* If this is an indexed address, make sure the register class can handle
19973 indexed addresses for this mode. */
19975 op0
= XEXP (addr
, 0);
19976 op1
= XEXP (addr
, 1);
19977 if (!base_reg_operand (op0
, Pmode
))
19978 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
19980 else if (int_reg_operand (op1
, Pmode
))
19982 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
19984 emit_insn (gen_rtx_SET (scratch
, addr
));
19985 new_addr
= scratch
;
19989 else if (mode_supports_dq_form (mode
) && CONST_INT_P (op1
))
19991 if (((addr_mask
& RELOAD_REG_QUAD_OFFSET
) == 0)
19992 || !quad_address_p (addr
, mode
, false))
19994 emit_insn (gen_rtx_SET (scratch
, addr
));
19995 new_addr
= scratch
;
19999 /* Make sure the register class can handle offset addresses. */
20000 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
20002 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20004 emit_insn (gen_rtx_SET (scratch
, addr
));
20005 new_addr
= scratch
;
20010 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20015 op0
= XEXP (addr
, 0);
20016 op1
= XEXP (addr
, 1);
20017 if (!base_reg_operand (op0
, Pmode
))
20018 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20020 else if (int_reg_operand (op1
, Pmode
))
20022 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
20024 emit_insn (gen_rtx_SET (scratch
, addr
));
20025 new_addr
= scratch
;
20029 /* Quad offsets are restricted and can't handle normal addresses. */
20030 else if (mode_supports_dq_form (mode
))
20032 emit_insn (gen_rtx_SET (scratch
, addr
));
20033 new_addr
= scratch
;
20036 /* Make sure the register class can handle offset addresses. */
20037 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
20039 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20041 emit_insn (gen_rtx_SET (scratch
, addr
));
20042 new_addr
= scratch
;
20047 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20054 rs6000_emit_move (scratch
, addr
, Pmode
);
20055 new_addr
= scratch
;
20059 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
20062 /* Adjust the address if it changed. */
20063 if (addr
!= new_addr
)
20065 mem
= replace_equiv_address_nv (mem
, new_addr
);
20066 if (TARGET_DEBUG_ADDR
)
20067 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
20070 /* Now create the move. */
20072 emit_insn (gen_rtx_SET (mem
, reg
));
20074 emit_insn (gen_rtx_SET (reg
, mem
));
20079 /* Convert reloads involving 64-bit gprs and misaligned offset
20080 addressing, or multiple 32-bit gprs and offsets that are too large,
20081 to use indirect addressing. */
20084 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
20086 int regno
= true_regnum (reg
);
20087 enum reg_class rclass
;
20089 rtx scratch_or_premodify
= scratch
;
20091 if (TARGET_DEBUG_ADDR
)
20093 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
20094 store_p
? "store" : "load");
20095 fprintf (stderr
, "reg:\n");
20097 fprintf (stderr
, "mem:\n");
20099 fprintf (stderr
, "scratch:\n");
20100 debug_rtx (scratch
);
20103 gcc_assert (regno
>= 0 && HARD_REGISTER_NUM_P (regno
));
20104 gcc_assert (MEM_P (mem
));
20105 rclass
= REGNO_REG_CLASS (regno
);
20106 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
20107 addr
= XEXP (mem
, 0);
20109 if (GET_CODE (addr
) == PRE_MODIFY
)
20111 gcc_assert (REG_P (XEXP (addr
, 0))
20112 && GET_CODE (XEXP (addr
, 1)) == PLUS
20113 && XEXP (XEXP (addr
, 1), 0) == XEXP (addr
, 0));
20114 scratch_or_premodify
= XEXP (addr
, 0);
20115 addr
= XEXP (addr
, 1);
20117 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
20119 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
20121 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
20123 /* Now create the move. */
20125 emit_insn (gen_rtx_SET (mem
, reg
));
20127 emit_insn (gen_rtx_SET (reg
, mem
));
20132 /* Given an rtx X being reloaded into a reg required to be
20133 in class CLASS, return the class of reg to actually use.
20134 In general this is just CLASS; but on some machines
20135 in some cases it is preferable to use a more restrictive class.
20137 On the RS/6000, we have to return NO_REGS when we want to reload a
20138 floating-point CONST_DOUBLE to force it to be copied to memory.
20140 We also don't want to reload integer values into floating-point
20141 registers if we can at all help it. In fact, this can
20142 cause reload to die, if it tries to generate a reload of CTR
20143 into a FP register and discovers it doesn't have the memory location
20146 ??? Would it be a good idea to have reload do the converse, that is
20147 try to reload floating modes into FP registers if possible?
20150 static enum reg_class
20151 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
20153 machine_mode mode
= GET_MODE (x
);
20154 bool is_constant
= CONSTANT_P (x
);
20156 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
20157 reload class for it. */
20158 if ((rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
20159 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
) == 0)
20162 if ((rclass
== FLOAT_REGS
|| rclass
== VSX_REGS
)
20163 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
] & RELOAD_REG_VALID
) == 0)
20166 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
20167 the reloading of address expressions using PLUS into floating point
20169 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
20173 /* Zero is always allowed in all VSX registers. */
20174 if (x
== CONST0_RTX (mode
))
20177 /* If this is a vector constant that can be formed with a few Altivec
20178 instructions, we want altivec registers. */
20179 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
20180 return ALTIVEC_REGS
;
20182 /* If this is an integer constant that can easily be loaded into
20183 vector registers, allow it. */
20184 if (CONST_INT_P (x
))
20186 HOST_WIDE_INT value
= INTVAL (x
);
20188 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20189 2.06 can generate it in the Altivec registers with
20193 if (TARGET_P8_VECTOR
)
20195 else if (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
20196 return ALTIVEC_REGS
;
20201 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20202 a sign extend in the Altivec registers. */
20203 if (IN_RANGE (value
, -128, 127) && TARGET_P9_VECTOR
20204 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
))
20205 return ALTIVEC_REGS
;
20208 /* Force constant to memory. */
20212 /* D-form addressing can easily reload the value. */
20213 if (mode_supports_vmx_dform (mode
)
20214 || mode_supports_dq_form (mode
))
20217 /* If this is a scalar floating point value and we don't have D-form
20218 addressing, prefer the traditional floating point registers so that we
20219 can use D-form (register+offset) addressing. */
20220 if (rclass
== VSX_REGS
20221 && (mode
== SFmode
|| GET_MODE_SIZE (mode
) == 8))
20224 /* Prefer the Altivec registers if Altivec is handling the vector
20225 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20227 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
20228 || mode
== V1TImode
)
20229 return ALTIVEC_REGS
;
20234 if (is_constant
|| GET_CODE (x
) == PLUS
)
20236 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
20237 return GENERAL_REGS
;
20238 if (reg_class_subset_p (BASE_REGS
, rclass
))
20243 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== GEN_OR_FLOAT_REGS
)
20244 return GENERAL_REGS
;
20249 /* Debug version of rs6000_preferred_reload_class. */
20250 static enum reg_class
20251 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
20253 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
20256 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20258 reg_class_names
[ret
], reg_class_names
[rclass
],
20259 GET_MODE_NAME (GET_MODE (x
)));
20265 /* If we are copying between FP or AltiVec registers and anything else, we need
20266 a memory location. The exception is when we are targeting ppc64 and the
20267 move to/from fpr to gpr instructions are available. Also, under VSX, you
20268 can copy vector registers from the FP register set to the Altivec register
20269 set and vice versa. */
20272 rs6000_secondary_memory_needed (machine_mode mode
,
20273 reg_class_t from_class
,
20274 reg_class_t to_class
)
20276 enum rs6000_reg_type from_type
, to_type
;
20277 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
20278 || (to_class
== ALTIVEC_REGS
));
20280 /* If a simple/direct move is available, we don't need secondary memory */
20281 from_type
= reg_class_to_reg_type
[(int)from_class
];
20282 to_type
= reg_class_to_reg_type
[(int)to_class
];
20284 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
20285 (secondary_reload_info
*)0, altivec_p
))
20288 /* If we have a floating point or vector register class, we need to use
20289 memory to transfer the data. */
20290 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
20296 /* Debug version of rs6000_secondary_memory_needed. */
20298 rs6000_debug_secondary_memory_needed (machine_mode mode
,
20299 reg_class_t from_class
,
20300 reg_class_t to_class
)
20302 bool ret
= rs6000_secondary_memory_needed (mode
, from_class
, to_class
);
20305 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20306 "to_class = %s, mode = %s\n",
20307 ret
? "true" : "false",
20308 reg_class_names
[from_class
],
20309 reg_class_names
[to_class
],
20310 GET_MODE_NAME (mode
));
20315 /* Return the register class of a scratch register needed to copy IN into
20316 or out of a register in RCLASS in MODE. If it can be done directly,
20317 NO_REGS is returned. */
20319 static enum reg_class
20320 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
20325 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
20327 && MACHOPIC_INDIRECT
20331 /* We cannot copy a symbolic operand directly into anything
20332 other than BASE_REGS for TARGET_ELF. So indicate that a
20333 register from BASE_REGS is needed as an intermediate
20336 On Darwin, pic addresses require a load from memory, which
20337 needs a base register. */
20338 if (rclass
!= BASE_REGS
20339 && (SYMBOL_REF_P (in
)
20340 || GET_CODE (in
) == HIGH
20341 || GET_CODE (in
) == LABEL_REF
20342 || GET_CODE (in
) == CONST
))
20348 regno
= REGNO (in
);
20349 if (!HARD_REGISTER_NUM_P (regno
))
20351 regno
= true_regnum (in
);
20352 if (!HARD_REGISTER_NUM_P (regno
))
20356 else if (SUBREG_P (in
))
20358 regno
= true_regnum (in
);
20359 if (!HARD_REGISTER_NUM_P (regno
))
20365 /* If we have VSX register moves, prefer moving scalar values between
20366 Altivec registers and GPR by going via an FPR (and then via memory)
20367 instead of reloading the secondary memory address for Altivec moves. */
20369 && GET_MODE_SIZE (mode
) < 16
20370 && !mode_supports_vmx_dform (mode
)
20371 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
20372 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
20373 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
20374 && (regno
>= 0 && INT_REGNO_P (regno
)))))
20377 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20379 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
20380 || (regno
>= 0 && INT_REGNO_P (regno
)))
20383 /* Constants, memory, and VSX registers can go into VSX registers (both the
20384 traditional floating point and the altivec registers). */
20385 if (rclass
== VSX_REGS
20386 && (regno
== -1 || VSX_REGNO_P (regno
)))
20389 /* Constants, memory, and FP registers can go into FP registers. */
20390 if ((regno
== -1 || FP_REGNO_P (regno
))
20391 && (rclass
== FLOAT_REGS
|| rclass
== GEN_OR_FLOAT_REGS
))
20392 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
20394 /* Memory, and AltiVec registers can go into AltiVec registers. */
20395 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
20396 && rclass
== ALTIVEC_REGS
)
20399 /* We can copy among the CR registers. */
20400 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
20401 && regno
>= 0 && CR_REGNO_P (regno
))
20404 /* Otherwise, we need GENERAL_REGS. */
20405 return GENERAL_REGS
;
20408 /* Debug version of rs6000_secondary_reload_class. */
20409 static enum reg_class
20410 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
20411 machine_mode mode
, rtx in
)
20413 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
20415 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20416 "mode = %s, input rtx:\n",
20417 reg_class_names
[ret
], reg_class_names
[rclass
],
20418 GET_MODE_NAME (mode
));
20424 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20427 rs6000_can_change_mode_class (machine_mode from
,
20429 reg_class_t rclass
)
20431 unsigned from_size
= GET_MODE_SIZE (from
);
20432 unsigned to_size
= GET_MODE_SIZE (to
);
20434 if (from_size
!= to_size
)
20436 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
20438 if (reg_classes_intersect_p (xclass
, rclass
))
20440 unsigned to_nregs
= hard_regno_nregs (FIRST_FPR_REGNO
, to
);
20441 unsigned from_nregs
= hard_regno_nregs (FIRST_FPR_REGNO
, from
);
20442 bool to_float128_vector_p
= FLOAT128_VECTOR_P (to
);
20443 bool from_float128_vector_p
= FLOAT128_VECTOR_P (from
);
20445 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20446 single register under VSX because the scalar part of the register
20447 is in the upper 64-bits, and not the lower 64-bits. Types like
20448 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20449 IEEE floating point can't overlap, and neither can small
20452 if (to_float128_vector_p
&& from_float128_vector_p
)
20455 else if (to_float128_vector_p
|| from_float128_vector_p
)
20458 /* TDmode in floating-mode registers must always go into a register
20459 pair with the most significant word in the even-numbered register
20460 to match ISA requirements. In little-endian mode, this does not
20461 match subreg numbering, so we cannot allow subregs. */
20462 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
20465 if (from_size
< 8 || to_size
< 8)
20468 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
20471 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
20480 /* Since the VSX register set includes traditional floating point registers
20481 and altivec registers, just check for the size being different instead of
20482 trying to check whether the modes are vector modes. Otherwise it won't
20483 allow say DF and DI to change classes. For types like TFmode and TDmode
20484 that take 2 64-bit registers, rather than a single 128-bit register, don't
20485 allow subregs of those types to other 128 bit types. */
20486 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
20488 unsigned num_regs
= (from_size
+ 15) / 16;
20489 if (hard_regno_nregs (FIRST_FPR_REGNO
, to
) > num_regs
20490 || hard_regno_nregs (FIRST_FPR_REGNO
, from
) > num_regs
)
20493 return (from_size
== 8 || from_size
== 16);
20496 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
20497 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
20503 /* Debug version of rs6000_can_change_mode_class. */
20505 rs6000_debug_can_change_mode_class (machine_mode from
,
20507 reg_class_t rclass
)
20509 bool ret
= rs6000_can_change_mode_class (from
, to
, rclass
);
20512 "rs6000_can_change_mode_class, return %s, from = %s, "
20513 "to = %s, rclass = %s\n",
20514 ret
? "true" : "false",
20515 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
20516 reg_class_names
[rclass
]);
20521 /* Return a string to do a move operation of 128 bits of data. */
20524 rs6000_output_move_128bit (rtx operands
[])
20526 rtx dest
= operands
[0];
20527 rtx src
= operands
[1];
20528 machine_mode mode
= GET_MODE (dest
);
20531 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
20532 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
20536 dest_regno
= REGNO (dest
);
20537 dest_gpr_p
= INT_REGNO_P (dest_regno
);
20538 dest_fp_p
= FP_REGNO_P (dest_regno
);
20539 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
20540 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
20545 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
20550 src_regno
= REGNO (src
);
20551 src_gpr_p
= INT_REGNO_P (src_regno
);
20552 src_fp_p
= FP_REGNO_P (src_regno
);
20553 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
20554 src_vsx_p
= src_fp_p
| src_vmx_p
;
20559 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
20562 /* Register moves. */
20563 if (dest_regno
>= 0 && src_regno
>= 0)
20570 if (TARGET_DIRECT_MOVE_128
&& src_vsx_p
)
20571 return (WORDS_BIG_ENDIAN
20572 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20573 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20575 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
20579 else if (TARGET_VSX
&& dest_vsx_p
)
20582 return "xxlor %x0,%x1,%x1";
20584 else if (TARGET_DIRECT_MOVE_128
&& src_gpr_p
)
20585 return (WORDS_BIG_ENDIAN
20586 ? "mtvsrdd %x0,%1,%L1"
20587 : "mtvsrdd %x0,%L1,%1");
20589 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
20593 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
20594 return "vor %0,%1,%1";
20596 else if (dest_fp_p
&& src_fp_p
)
20601 else if (dest_regno
>= 0 && MEM_P (src
))
20605 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20611 else if (TARGET_ALTIVEC
&& dest_vmx_p
20612 && altivec_indexed_or_indirect_operand (src
, mode
))
20613 return "lvx %0,%y1";
20615 else if (TARGET_VSX
&& dest_vsx_p
)
20617 if (mode_supports_dq_form (mode
)
20618 && quad_address_p (XEXP (src
, 0), mode
, true))
20619 return "lxv %x0,%1";
20621 else if (TARGET_P9_VECTOR
)
20622 return "lxvx %x0,%y1";
20624 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20625 return "lxvw4x %x0,%y1";
20628 return "lxvd2x %x0,%y1";
20631 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
20632 return "lvx %0,%y1";
20634 else if (dest_fp_p
)
20639 else if (src_regno
>= 0 && MEM_P (dest
))
20643 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
20644 return "stq %1,%0";
20649 else if (TARGET_ALTIVEC
&& src_vmx_p
20650 && altivec_indexed_or_indirect_operand (dest
, mode
))
20651 return "stvx %1,%y0";
20653 else if (TARGET_VSX
&& src_vsx_p
)
20655 if (mode_supports_dq_form (mode
)
20656 && quad_address_p (XEXP (dest
, 0), mode
, true))
20657 return "stxv %x1,%0";
20659 else if (TARGET_P9_VECTOR
)
20660 return "stxvx %x1,%y0";
20662 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
20663 return "stxvw4x %x1,%y0";
20666 return "stxvd2x %x1,%y0";
20669 else if (TARGET_ALTIVEC
&& src_vmx_p
)
20670 return "stvx %1,%y0";
20677 else if (dest_regno
>= 0
20678 && (CONST_INT_P (src
)
20679 || CONST_WIDE_INT_P (src
)
20680 || CONST_DOUBLE_P (src
)
20681 || GET_CODE (src
) == CONST_VECTOR
))
20686 else if ((dest_vmx_p
&& TARGET_ALTIVEC
)
20687 || (dest_vsx_p
&& TARGET_VSX
))
20688 return output_vec_const_move (operands
);
20691 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest
, src
));
20694 /* Validate a 128-bit move. */
20696 rs6000_move_128bit_ok_p (rtx operands
[])
20698 machine_mode mode
= GET_MODE (operands
[0]);
20699 return (gpc_reg_operand (operands
[0], mode
)
20700 || gpc_reg_operand (operands
[1], mode
));
20703 /* Return true if a 128-bit move needs to be split. */
20705 rs6000_split_128bit_ok_p (rtx operands
[])
20707 if (!reload_completed
)
20710 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
20713 if (quad_load_store_p (operands
[0], operands
[1]))
20720 /* Given a comparison operation, return the bit number in CCR to test. We
20721 know this is a valid comparison.
20723 SCC_P is 1 if this is for an scc. That means that %D will have been
20724 used instead of %C, so the bits will be in different places.
20726 Return -1 if OP isn't a valid comparison for some reason. */
20729 ccr_bit (rtx op
, int scc_p
)
20731 enum rtx_code code
= GET_CODE (op
);
20732 machine_mode cc_mode
;
20737 if (!COMPARISON_P (op
))
20740 reg
= XEXP (op
, 0);
20742 if (!REG_P (reg
) || !CR_REGNO_P (REGNO (reg
)))
20745 cc_mode
= GET_MODE (reg
);
20746 cc_regnum
= REGNO (reg
);
20747 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
20749 validate_condition_mode (code
, cc_mode
);
20751 /* When generating a sCOND operation, only positive conditions are
20770 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
20772 return base_bit
+ 2;
20773 case GT
: case GTU
: case UNLE
:
20774 return base_bit
+ 1;
20775 case LT
: case LTU
: case UNGE
:
20777 case ORDERED
: case UNORDERED
:
20778 return base_bit
+ 3;
20781 /* If scc, we will have done a cror to put the bit in the
20782 unordered position. So test that bit. For integer, this is ! LT
20783 unless this is an scc insn. */
20784 return scc_p
? base_bit
+ 3 : base_bit
;
20787 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
20794 /* Return the GOT register. */
20797 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
20799 /* The second flow pass currently (June 1999) can't update
20800 regs_ever_live without disturbing other parts of the compiler, so
20801 update it here to make the prolog/epilogue code happy. */
20802 if (!can_create_pseudo_p ()
20803 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
20804 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
20806 crtl
->uses_pic_offset_table
= 1;
20808 return pic_offset_table_rtx
;
20811 static rs6000_stack_t stack_info
;
20813 /* Function to init struct machine_function.
20814 This will be called, via a pointer variable,
20815 from push_function_context. */
20817 static struct machine_function
*
20818 rs6000_init_machine_status (void)
20820 stack_info
.reload_completed
= 0;
20821 return ggc_cleared_alloc
<machine_function
> ();
20824 #define INT_P(X) (CONST_INT_P (X) && GET_MODE (X) == VOIDmode)
20826 /* Write out a function code label. */
20829 rs6000_output_function_entry (FILE *file
, const char *fname
)
20831 if (fname
[0] != '.')
20833 switch (DEFAULT_ABI
)
20836 gcc_unreachable ();
20842 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
20852 RS6000_OUTPUT_BASENAME (file
, fname
);
20855 /* Print an operand. Recognize special options, documented below. */
20858 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20859 only introduced by the linker, when applying the sda21
20861 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20862 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20864 #define SMALL_DATA_RELOC "sda21"
20865 #define SMALL_DATA_REG 0
20869 print_operand (FILE *file
, rtx x
, int code
)
20872 unsigned HOST_WIDE_INT uval
;
20876 /* %a is output_address. */
20878 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20882 /* Like 'J' but get to the GT bit only. */
20883 if (!REG_P (x
) || !CR_REGNO_P (REGNO (x
)))
20885 output_operand_lossage ("invalid %%D value");
20889 /* Bit 1 is GT bit. */
20890 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
20892 /* Add one for shift count in rlinm for scc. */
20893 fprintf (file
, "%d", i
+ 1);
20897 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20900 output_operand_lossage ("invalid %%e value");
20905 if ((uval
& 0xffff) == 0 && uval
!= 0)
20910 /* X is a CR register. Print the number of the EQ bit of the CR */
20911 if (!REG_P (x
) || !CR_REGNO_P (REGNO (x
)))
20912 output_operand_lossage ("invalid %%E value");
20914 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
20918 /* X is a CR register. Print the shift count needed to move it
20919 to the high-order four bits. */
20920 if (!REG_P (x
) || !CR_REGNO_P (REGNO (x
)))
20921 output_operand_lossage ("invalid %%f value");
20923 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
20927 /* Similar, but print the count for the rotate in the opposite
20929 if (!REG_P (x
) || !CR_REGNO_P (REGNO (x
)))
20930 output_operand_lossage ("invalid %%F value");
20932 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
20936 /* X is a constant integer. If it is negative, print "m",
20937 otherwise print "z". This is to make an aze or ame insn. */
20938 if (!CONST_INT_P (x
))
20939 output_operand_lossage ("invalid %%G value");
20940 else if (INTVAL (x
) >= 0)
20947 /* If constant, output low-order five bits. Otherwise, write
20950 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
20952 print_operand (file
, x
, 0);
20956 /* If constant, output low-order six bits. Otherwise, write
20959 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
20961 print_operand (file
, x
, 0);
20965 /* Print `i' if this is a constant, else nothing. */
20971 /* Write the bit number in CCR for jump. */
20972 i
= ccr_bit (x
, 0);
20974 output_operand_lossage ("invalid %%j code");
20976 fprintf (file
, "%d", i
);
20980 /* Similar, but add one for shift count in rlinm for scc and pass
20981 scc flag to `ccr_bit'. */
20982 i
= ccr_bit (x
, 1);
20984 output_operand_lossage ("invalid %%J code");
20986 /* If we want bit 31, write a shift count of zero, not 32. */
20987 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
20991 /* X must be a constant. Write the 1's complement of the
20994 output_operand_lossage ("invalid %%k value");
20996 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
21000 /* X must be a symbolic constant on ELF. Write an
21001 expression suitable for an 'addi' that adds in the low 16
21002 bits of the MEM. */
21003 if (GET_CODE (x
) == CONST
)
21005 if (GET_CODE (XEXP (x
, 0)) != PLUS
21006 || (!SYMBOL_REF_P (XEXP (XEXP (x
, 0), 0))
21007 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
21008 || !CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
21009 output_operand_lossage ("invalid %%K value");
21011 print_operand_address (file
, x
);
21012 fputs ("@l", file
);
21015 /* %l is output_asm_label. */
21018 /* Write second word of DImode or DFmode reference. Works on register
21019 or non-indexed memory only. */
21021 fputs (reg_names
[REGNO (x
) + 1], file
);
21022 else if (MEM_P (x
))
21024 machine_mode mode
= GET_MODE (x
);
21025 /* Handle possible auto-increment. Since it is pre-increment and
21026 we have already done it, we can just use an offset of word. */
21027 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21028 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21029 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
21031 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21032 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
21035 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
,
21039 if (small_data_operand (x
, GET_MODE (x
)))
21040 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21041 reg_names
[SMALL_DATA_REG
]);
21045 case 'N': /* Unused */
21046 /* Write the number of elements in the vector times 4. */
21047 if (GET_CODE (x
) != PARALLEL
)
21048 output_operand_lossage ("invalid %%N value");
21050 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
21053 case 'O': /* Unused */
21054 /* Similar, but subtract 1 first. */
21055 if (GET_CODE (x
) != PARALLEL
)
21056 output_operand_lossage ("invalid %%O value");
21058 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
21062 /* X is a CONST_INT that is a power of two. Output the logarithm. */
21065 || (i
= exact_log2 (INTVAL (x
))) < 0)
21066 output_operand_lossage ("invalid %%p value");
21068 fprintf (file
, "%d", i
);
21072 /* The operand must be an indirect memory reference. The result
21073 is the register name. */
21074 if (!MEM_P (x
) || !REG_P (XEXP (x
, 0))
21075 || REGNO (XEXP (x
, 0)) >= 32)
21076 output_operand_lossage ("invalid %%P value");
21078 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
21082 /* This outputs the logical code corresponding to a boolean
21083 expression. The expression may have one or both operands
21084 negated (if one, only the first one). For condition register
21085 logical operations, it will also treat the negated
21086 CR codes as NOTs, but not handle NOTs of them. */
21088 const char *const *t
= 0;
21090 enum rtx_code code
= GET_CODE (x
);
21091 static const char * const tbl
[3][3] = {
21092 { "and", "andc", "nor" },
21093 { "or", "orc", "nand" },
21094 { "xor", "eqv", "xor" } };
21098 else if (code
== IOR
)
21100 else if (code
== XOR
)
21103 output_operand_lossage ("invalid %%q value");
21105 if (GET_CODE (XEXP (x
, 0)) != NOT
)
21109 if (GET_CODE (XEXP (x
, 1)) == NOT
)
21120 if (! TARGET_MFCRF
)
21126 /* X is a CR register. Print the mask for `mtcrf'. */
21127 if (!REG_P (x
) || !CR_REGNO_P (REGNO (x
)))
21128 output_operand_lossage ("invalid %%R value");
21130 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
21134 /* Low 5 bits of 32 - value */
21136 output_operand_lossage ("invalid %%s value");
21138 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
21142 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
21143 if (!REG_P (x
) || !CR_REGNO_P (REGNO (x
)))
21145 output_operand_lossage ("invalid %%t value");
21149 /* Bit 3 is OV bit. */
21150 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
21152 /* If we want bit 31, write a shift count of zero, not 32. */
21153 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
21157 /* Print the symbolic name of a branch target register. */
21158 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PLTSEQ
)
21159 x
= XVECEXP (x
, 0, 0);
21160 if (!REG_P (x
) || (REGNO (x
) != LR_REGNO
21161 && REGNO (x
) != CTR_REGNO
))
21162 output_operand_lossage ("invalid %%T value");
21163 else if (REGNO (x
) == LR_REGNO
)
21164 fputs ("lr", file
);
21166 fputs ("ctr", file
);
21170 /* High-order or low-order 16 bits of constant, whichever is non-zero,
21171 for use in unsigned operand. */
21174 output_operand_lossage ("invalid %%u value");
21179 if ((uval
& 0xffff) == 0)
21182 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
21186 /* High-order 16 bits of constant for use in signed operand. */
21188 output_operand_lossage ("invalid %%v value");
21190 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
21191 (INTVAL (x
) >> 16) & 0xffff);
21195 /* Print `u' if this has an auto-increment or auto-decrement. */
21197 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
21198 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
21199 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
21204 /* Print the trap code for this operand. */
21205 switch (GET_CODE (x
))
21208 fputs ("eq", file
); /* 4 */
21211 fputs ("ne", file
); /* 24 */
21214 fputs ("lt", file
); /* 16 */
21217 fputs ("le", file
); /* 20 */
21220 fputs ("gt", file
); /* 8 */
21223 fputs ("ge", file
); /* 12 */
21226 fputs ("llt", file
); /* 2 */
21229 fputs ("lle", file
); /* 6 */
21232 fputs ("lgt", file
); /* 1 */
21235 fputs ("lge", file
); /* 5 */
21238 output_operand_lossage ("invalid %%V value");
21243 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21246 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
21247 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
21249 print_operand (file
, x
, 0);
21253 /* X is a FPR or Altivec register used in a VSX context. */
21254 if (!REG_P (x
) || !VSX_REGNO_P (REGNO (x
)))
21255 output_operand_lossage ("invalid %%x value");
21258 int reg
= REGNO (x
);
21259 int vsx_reg
= (FP_REGNO_P (reg
)
21261 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
21263 #ifdef TARGET_REGNAMES
21264 if (TARGET_REGNAMES
)
21265 fprintf (file
, "%%vs%d", vsx_reg
);
21268 fprintf (file
, "%d", vsx_reg
);
21274 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
21275 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
21276 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
21281 /* Like 'L', for third word of TImode/PTImode */
21283 fputs (reg_names
[REGNO (x
) + 2], file
);
21284 else if (MEM_P (x
))
21286 machine_mode mode
= GET_MODE (x
);
21287 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21288 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21289 output_address (mode
, plus_constant (Pmode
,
21290 XEXP (XEXP (x
, 0), 0), 8));
21291 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21292 output_address (mode
, plus_constant (Pmode
,
21293 XEXP (XEXP (x
, 0), 0), 8));
21295 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 8), 0));
21296 if (small_data_operand (x
, GET_MODE (x
)))
21297 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21298 reg_names
[SMALL_DATA_REG
]);
21303 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PLTSEQ
)
21304 x
= XVECEXP (x
, 0, 1);
21305 /* X is a SYMBOL_REF. Write out the name preceded by a
21306 period and without any trailing data in brackets. Used for function
21307 names. If we are configured for System V (or the embedded ABI) on
21308 the PowerPC, do not emit the period, since those systems do not use
21309 TOCs and the like. */
21310 if (!SYMBOL_REF_P (x
))
21312 output_operand_lossage ("invalid %%z value");
21316 /* For macho, check to see if we need a stub. */
21319 const char *name
= XSTR (x
, 0);
21321 if (darwin_emit_branch_islands
21322 && MACHOPIC_INDIRECT
21323 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
21324 name
= machopic_indirection_name (x
, /*stub_p=*/true);
21326 assemble_name (file
, name
);
21328 else if (!DOT_SYMBOLS
)
21329 assemble_name (file
, XSTR (x
, 0));
21331 rs6000_output_function_entry (file
, XSTR (x
, 0));
21335 /* Like 'L', for last word of TImode/PTImode. */
21337 fputs (reg_names
[REGNO (x
) + 3], file
);
21338 else if (MEM_P (x
))
21340 machine_mode mode
= GET_MODE (x
);
21341 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
21342 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21343 output_address (mode
, plus_constant (Pmode
,
21344 XEXP (XEXP (x
, 0), 0), 12));
21345 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21346 output_address (mode
, plus_constant (Pmode
,
21347 XEXP (XEXP (x
, 0), 0), 12));
21349 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 12), 0));
21350 if (small_data_operand (x
, GET_MODE (x
)))
21351 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21352 reg_names
[SMALL_DATA_REG
]);
21356 /* Print AltiVec memory operand. */
21361 gcc_assert (MEM_P (x
));
21365 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x
))
21366 && GET_CODE (tmp
) == AND
21367 && CONST_INT_P (XEXP (tmp
, 1))
21368 && INTVAL (XEXP (tmp
, 1)) == -16)
21369 tmp
= XEXP (tmp
, 0);
21370 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
21371 && GET_CODE (tmp
) == PRE_MODIFY
)
21372 tmp
= XEXP (tmp
, 1);
21374 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
21377 if (GET_CODE (tmp
) != PLUS
21378 || !REG_P (XEXP (tmp
, 0))
21379 || !REG_P (XEXP (tmp
, 1)))
21381 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21385 if (REGNO (XEXP (tmp
, 0)) == 0)
21386 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
21387 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
21389 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
21390 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
21397 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
21398 else if (MEM_P (x
))
21400 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21401 know the width from the mode. */
21402 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
21403 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
21404 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21405 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
21406 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
21407 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
21408 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
21409 output_address (GET_MODE (x
), XEXP (XEXP (x
, 0), 1));
21411 output_address (GET_MODE (x
), XEXP (x
, 0));
21413 else if (toc_relative_expr_p (x
, false,
21414 &tocrel_base_oac
, &tocrel_offset_oac
))
21415 /* This hack along with a corresponding hack in
21416 rs6000_output_addr_const_extra arranges to output addends
21417 where the assembler expects to find them. eg.
21418 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21419 without this hack would be output as "x@toc+4". We
21421 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21422 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
21423 output_addr_const (file
, XVECEXP (x
, 0, 0));
21424 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PLTSEQ
)
21425 output_addr_const (file
, XVECEXP (x
, 0, 1));
21427 output_addr_const (file
, x
);
21431 if (const char *name
= get_some_local_dynamic_name ())
21432 assemble_name (file
, name
);
21434 output_operand_lossage ("'%%&' used without any "
21435 "local dynamic TLS references");
21439 output_operand_lossage ("invalid %%xn code");
21443 /* Print the address of an operand. */
21446 print_operand_address (FILE *file
, rtx x
)
21449 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
21450 else if (SYMBOL_REF_P (x
) || GET_CODE (x
) == CONST
21451 || GET_CODE (x
) == LABEL_REF
)
21453 output_addr_const (file
, x
);
21454 if (small_data_operand (x
, GET_MODE (x
)))
21455 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
21456 reg_names
[SMALL_DATA_REG
]);
21458 gcc_assert (!TARGET_TOC
);
21460 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21461 && REG_P (XEXP (x
, 1)))
21463 if (REGNO (XEXP (x
, 0)) == 0)
21464 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
21465 reg_names
[ REGNO (XEXP (x
, 0)) ]);
21467 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
21468 reg_names
[ REGNO (XEXP (x
, 1)) ]);
21470 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
21471 && CONST_INT_P (XEXP (x
, 1)))
21472 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
21473 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
21475 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21476 && CONSTANT_P (XEXP (x
, 1)))
21478 fprintf (file
, "lo16(");
21479 output_addr_const (file
, XEXP (x
, 1));
21480 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21484 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
21485 && CONSTANT_P (XEXP (x
, 1)))
21487 output_addr_const (file
, XEXP (x
, 1));
21488 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
21491 else if (toc_relative_expr_p (x
, false, &tocrel_base_oac
, &tocrel_offset_oac
))
21493 /* This hack along with a corresponding hack in
21494 rs6000_output_addr_const_extra arranges to output addends
21495 where the assembler expects to find them. eg.
21497 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21498 without this hack would be output as "x@toc+8@l(9)". We
21499 want "x+8@toc@l(9)". */
21500 output_addr_const (file
, CONST_CAST_RTX (tocrel_base_oac
));
21501 if (GET_CODE (x
) == LO_SUM
)
21502 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
21504 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base_oac
, 0, 1))]);
21507 output_addr_const (file
, x
);
21510 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21513 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
21515 if (GET_CODE (x
) == UNSPEC
)
21516 switch (XINT (x
, 1))
21518 case UNSPEC_TOCREL
:
21519 gcc_checking_assert (SYMBOL_REF_P (XVECEXP (x
, 0, 0))
21520 && REG_P (XVECEXP (x
, 0, 1))
21521 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
21522 output_addr_const (file
, XVECEXP (x
, 0, 0));
21523 if (x
== tocrel_base_oac
&& tocrel_offset_oac
!= const0_rtx
)
21525 if (INTVAL (tocrel_offset_oac
) >= 0)
21526 fprintf (file
, "+");
21527 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset_oac
));
21529 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
21532 assemble_name (file
, toc_label_name
);
21535 else if (TARGET_ELF
)
21536 fputs ("@toc", file
);
21540 case UNSPEC_MACHOPIC_OFFSET
:
21541 output_addr_const (file
, XVECEXP (x
, 0, 0));
21543 machopic_output_function_base_name (file
);
21550 /* Target hook for assembling integer objects. The PowerPC version has
21551 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21552 is defined. It also needs to handle DI-mode objects on 64-bit
21556 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
21558 #ifdef RELOCATABLE_NEEDS_FIXUP
21559 /* Special handling for SI values. */
21560 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
21562 static int recurse
= 0;
21564 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21565 the .fixup section. Since the TOC section is already relocated, we
21566 don't need to mark it here. We used to skip the text section, but it
21567 should never be valid for relocated addresses to be placed in the text
21569 if (DEFAULT_ABI
== ABI_V4
21570 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
21571 && in_section
!= toc_section
21573 && !CONST_SCALAR_INT_P (x
)
21579 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
21581 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
21582 fprintf (asm_out_file
, "\t.long\t(");
21583 output_addr_const (asm_out_file
, x
);
21584 fprintf (asm_out_file
, ")@fixup\n");
21585 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
21586 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
21587 fprintf (asm_out_file
, "\t.long\t");
21588 assemble_name (asm_out_file
, buf
);
21589 fprintf (asm_out_file
, "\n\t.previous\n");
21593 /* Remove initial .'s to turn a -mcall-aixdesc function
21594 address into the address of the descriptor, not the function
21596 else if (SYMBOL_REF_P (x
)
21597 && XSTR (x
, 0)[0] == '.'
21598 && DEFAULT_ABI
== ABI_AIX
)
21600 const char *name
= XSTR (x
, 0);
21601 while (*name
== '.')
21604 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
21608 #endif /* RELOCATABLE_NEEDS_FIXUP */
21609 return default_assemble_integer (x
, size
, aligned_p
);
21612 /* Return a template string for assembly to emit when making an
21613 external call. FUNOP is the call mem argument operand number. */
21615 static const char *
21616 rs6000_call_template_1 (rtx
*operands
, unsigned int funop
, bool sibcall
)
21618 /* -Wformat-overflow workaround, without which gcc thinks that %u
21619 might produce 10 digits. */
21620 gcc_assert (funop
<= MAX_RECOG_OPERANDS
);
21624 if (TARGET_TLS_MARKERS
&& GET_CODE (operands
[funop
+ 1]) == UNSPEC
)
21626 if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSGD
)
21627 sprintf (arg
, "(%%%u@tlsgd)", funop
+ 1);
21628 else if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSLD
)
21629 sprintf (arg
, "(%%&@tlsld)");
21631 gcc_unreachable ();
21634 /* The magic 32768 offset here corresponds to the offset of
21635 r30 in .got2, as given by LCTOC1. See sysv4.h:toc_section. */
21637 sprintf (z
, "%%z%u%s", funop
,
21638 (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
== 2
21641 static char str
[32]; /* 2 spare */
21642 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21643 sprintf (str
, "b%s %s%s%s", sibcall
? "" : "l", z
, arg
,
21644 sibcall
? "" : "\n\tnop");
21645 else if (DEFAULT_ABI
== ABI_V4
)
21646 sprintf (str
, "b%s %s%s%s", sibcall
? "" : "l", z
, arg
,
21647 flag_pic
? "@plt" : "");
21649 /* If/when we remove the mlongcall opt, we can share the AIX/ELGv2 case. */
21650 else if (DEFAULT_ABI
== ABI_DARWIN
)
21652 /* The cookie is in operand func+2. */
21653 gcc_checking_assert (GET_CODE (operands
[funop
+ 2]) == CONST_INT
);
21654 int cookie
= INTVAL (operands
[funop
+ 2]);
21655 if (cookie
& CALL_LONG
)
21657 tree funname
= get_identifier (XSTR (operands
[funop
], 0));
21658 tree labelname
= get_prev_label (funname
);
21659 gcc_checking_assert (labelname
&& !sibcall
);
21661 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21662 instruction will reach 'foo', otherwise link as 'bl L42'".
21663 "L42" should be a 'branch island', that will do a far jump to
21664 'foo'. Branch islands are generated in
21665 macho_branch_islands(). */
21666 sprintf (str
, "jbsr %%z%u,%.10s", funop
,
21667 IDENTIFIER_POINTER (labelname
));
21670 /* Same as AIX or ELFv2, except to keep backwards compat, no nop
21672 sprintf (str
, "b%s %s%s", sibcall
? "" : "l", z
, arg
);
21676 gcc_unreachable ();
21681 rs6000_call_template (rtx
*operands
, unsigned int funop
)
21683 return rs6000_call_template_1 (operands
, funop
, false);
21687 rs6000_sibcall_template (rtx
*operands
, unsigned int funop
)
21689 return rs6000_call_template_1 (operands
, funop
, true);
21692 /* As above, for indirect calls. */
21694 static const char *
21695 rs6000_indirect_call_template_1 (rtx
*operands
, unsigned int funop
,
21698 /* -Wformat-overflow workaround, without which gcc thinks that %u
21699 might produce 10 digits. Note that -Wformat-overflow will not
21700 currently warn here for str[], so do not rely on a warning to
21701 ensure str[] is correctly sized. */
21702 gcc_assert (funop
<= MAX_RECOG_OPERANDS
);
21704 /* Currently, funop is either 0 or 1. The maximum string is always
21705 a !speculate 64-bit __tls_get_addr call.
21709 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21710 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21712 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21713 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21720 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21721 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21723 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21724 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21731 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21732 . 35 .reloc .,R_PPC64_PLTSEQ,%z1+32768\n\t
21734 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21735 . 36 .reloc .,R_PPC64_PLTCALL,%z1+32768\n\t
21739 static char str
[160]; /* 8 spare */
21741 const char *ptrload
= TARGET_64BIT
? "d" : "wz";
21743 if (DEFAULT_ABI
== ABI_AIX
)
21746 ptrload
, funop
+ 2);
21748 /* We don't need the extra code to stop indirect call speculation if
21750 bool speculate
= (TARGET_MACHO
21751 || rs6000_speculate_indirect_jumps
21752 || (REG_P (operands
[funop
])
21753 && REGNO (operands
[funop
]) == LR_REGNO
));
21755 if (TARGET_PLTSEQ
&& GET_CODE (operands
[funop
]) == UNSPEC
)
21757 const char *rel64
= TARGET_64BIT
? "64" : "";
21760 if (TARGET_TLS_MARKERS
&& GET_CODE (operands
[funop
+ 1]) == UNSPEC
)
21762 if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSGD
)
21763 sprintf (tls
, ".reloc .,R_PPC%s_TLSGD,%%%u\n\t",
21765 else if (XINT (operands
[funop
+ 1], 1) == UNSPEC_TLSLD
)
21766 sprintf (tls
, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21769 gcc_unreachable ();
21772 const char *addend
= (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
21773 && flag_pic
== 2 ? "+32768" : "");
21777 "%s.reloc .,R_PPC%s_PLTSEQ,%%z%u%s\n\t",
21778 tls
, rel64
, funop
, addend
);
21779 s
+= sprintf (s
, "crset 2\n\t");
21782 "%s.reloc .,R_PPC%s_PLTCALL,%%z%u%s\n\t",
21783 tls
, rel64
, funop
, addend
);
21785 else if (!speculate
)
21786 s
+= sprintf (s
, "crset 2\n\t");
21788 if (DEFAULT_ABI
== ABI_AIX
)
21794 funop
, ptrload
, funop
+ 3);
21799 funop
, ptrload
, funop
+ 3);
21801 else if (DEFAULT_ABI
== ABI_ELFv2
)
21807 funop
, ptrload
, funop
+ 2);
21812 funop
, ptrload
, funop
+ 2);
21819 funop
, sibcall
? "" : "l");
21823 funop
, sibcall
? "" : "l", sibcall
? "\n\tb $" : "");
21829 rs6000_indirect_call_template (rtx
*operands
, unsigned int funop
)
21831 return rs6000_indirect_call_template_1 (operands
, funop
, false);
21835 rs6000_indirect_sibcall_template (rtx
*operands
, unsigned int funop
)
21837 return rs6000_indirect_call_template_1 (operands
, funop
, true);
21841 /* Output indirect call insns.
21842 WHICH is 0 for tocsave, 1 for plt16_ha, 2 for plt16_lo, 3 for mtctr. */
21844 rs6000_pltseq_template (rtx
*operands
, int which
)
21846 const char *rel64
= TARGET_64BIT
? "64" : "";
21849 if (TARGET_TLS_MARKERS
&& GET_CODE (operands
[3]) == UNSPEC
)
21851 if (XINT (operands
[3], 1) == UNSPEC_TLSGD
)
21852 sprintf (tls
, ".reloc .,R_PPC%s_TLSGD,%%3\n\t",
21854 else if (XINT (operands
[3], 1) == UNSPEC_TLSLD
)
21855 sprintf (tls
, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21858 gcc_unreachable ();
21861 gcc_assert (DEFAULT_ABI
== ABI_ELFv2
|| DEFAULT_ABI
== ABI_V4
);
21862 static char str
[96]; /* 15 spare */
21863 const char *off
= WORDS_BIG_ENDIAN
? "+2" : "";
21864 const char *addend
= (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
21865 && flag_pic
== 2 ? "+32768" : "");
21870 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2\n\t"
21872 tls
, rel64
, TARGET_64BIT
? "d 2,24(1)" : "w 2,12(1)");
21875 if (DEFAULT_ABI
== ABI_V4
&& !flag_pic
)
21877 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2\n\t"
21882 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2%s\n\t"
21884 tls
, off
, rel64
, addend
);
21888 "%s.reloc .%s,R_PPC%s_PLT16_LO%s,%%z2%s\n\t"
21890 tls
, off
, rel64
, TARGET_64BIT
? "_DS" : "", addend
,
21891 TARGET_64BIT
? "d" : "wz");
21895 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2%s\n\t"
21897 tls
, rel64
, addend
);
21900 gcc_unreachable ();
21906 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21907 /* Emit an assembler directive to set symbol visibility for DECL to
21908 VISIBILITY_TYPE. */
21911 rs6000_assemble_visibility (tree decl
, int vis
)
21916 /* Functions need to have their entry point symbol visibility set as
21917 well as their descriptor symbol visibility. */
21918 if (DEFAULT_ABI
== ABI_AIX
21920 && TREE_CODE (decl
) == FUNCTION_DECL
)
21922 static const char * const visibility_types
[] = {
21923 NULL
, "protected", "hidden", "internal"
21926 const char *name
, *type
;
21928 name
= ((* targetm
.strip_name_encoding
)
21929 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
21930 type
= visibility_types
[vis
];
21932 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
21933 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
21936 default_assemble_visibility (decl
, vis
);
21941 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
21943 /* Reversal of FP compares takes care -- an ordered compare
21944 becomes an unordered compare and vice versa. */
21945 if (mode
== CCFPmode
21946 && (!flag_finite_math_only
21947 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
21948 || code
== UNEQ
|| code
== LTGT
))
21949 return reverse_condition_maybe_unordered (code
);
21951 return reverse_condition (code
);
21954 /* Generate a compare for CODE. Return a brand-new rtx that
21955 represents the result of the compare. */
21958 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
21960 machine_mode comp_mode
;
21961 rtx compare_result
;
21962 enum rtx_code code
= GET_CODE (cmp
);
21963 rtx op0
= XEXP (cmp
, 0);
21964 rtx op1
= XEXP (cmp
, 1);
21966 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
21967 comp_mode
= CCmode
;
21968 else if (FLOAT_MODE_P (mode
))
21969 comp_mode
= CCFPmode
;
21970 else if (code
== GTU
|| code
== LTU
21971 || code
== GEU
|| code
== LEU
)
21972 comp_mode
= CCUNSmode
;
21973 else if ((code
== EQ
|| code
== NE
)
21974 && unsigned_reg_p (op0
)
21975 && (unsigned_reg_p (op1
)
21976 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
21977 /* These are unsigned values, perhaps there will be a later
21978 ordering compare that can be shared with this one. */
21979 comp_mode
= CCUNSmode
;
21981 comp_mode
= CCmode
;
21983 /* If we have an unsigned compare, make sure we don't have a signed value as
21985 if (comp_mode
== CCUNSmode
&& CONST_INT_P (op1
)
21986 && INTVAL (op1
) < 0)
21988 op0
= copy_rtx_if_shared (op0
);
21989 op1
= force_reg (GET_MODE (op0
), op1
);
21990 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
21993 /* First, the compare. */
21994 compare_result
= gen_reg_rtx (comp_mode
);
21996 /* IEEE 128-bit support in VSX registers when we do not have hardware
21998 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
22000 rtx libfunc
= NULL_RTX
;
22001 bool check_nan
= false;
22008 libfunc
= optab_libfunc (eq_optab
, mode
);
22013 libfunc
= optab_libfunc (ge_optab
, mode
);
22018 libfunc
= optab_libfunc (le_optab
, mode
);
22023 libfunc
= optab_libfunc (unord_optab
, mode
);
22024 code
= (code
== UNORDERED
) ? NE
: EQ
;
22030 libfunc
= optab_libfunc (ge_optab
, mode
);
22031 code
= (code
== UNGE
) ? GE
: GT
;
22037 libfunc
= optab_libfunc (le_optab
, mode
);
22038 code
= (code
== UNLE
) ? LE
: LT
;
22044 libfunc
= optab_libfunc (eq_optab
, mode
);
22045 code
= (code
= UNEQ
) ? EQ
: NE
;
22049 gcc_unreachable ();
22052 gcc_assert (libfunc
);
22055 dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
22056 SImode
, op0
, mode
, op1
, mode
);
22058 /* The library signals an exception for signalling NaNs, so we need to
22059 handle isgreater, etc. by first checking isordered. */
22062 rtx ne_rtx
, normal_dest
, unord_dest
;
22063 rtx unord_func
= optab_libfunc (unord_optab
, mode
);
22064 rtx join_label
= gen_label_rtx ();
22065 rtx join_ref
= gen_rtx_LABEL_REF (VOIDmode
, join_label
);
22066 rtx unord_cmp
= gen_reg_rtx (comp_mode
);
22069 /* Test for either value being a NaN. */
22070 gcc_assert (unord_func
);
22071 unord_dest
= emit_library_call_value (unord_func
, NULL_RTX
, LCT_CONST
,
22072 SImode
, op0
, mode
, op1
, mode
);
22074 /* Set value (0) if either value is a NaN, and jump to the join
22076 dest
= gen_reg_rtx (SImode
);
22077 emit_move_insn (dest
, const1_rtx
);
22078 emit_insn (gen_rtx_SET (unord_cmp
,
22079 gen_rtx_COMPARE (comp_mode
, unord_dest
,
22082 ne_rtx
= gen_rtx_NE (comp_mode
, unord_cmp
, const0_rtx
);
22083 emit_jump_insn (gen_rtx_SET (pc_rtx
,
22084 gen_rtx_IF_THEN_ELSE (VOIDmode
, ne_rtx
,
22088 /* Do the normal comparison, knowing that the values are not
22090 normal_dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
22091 SImode
, op0
, mode
, op1
, mode
);
22093 emit_insn (gen_cstoresi4 (dest
,
22094 gen_rtx_fmt_ee (code
, SImode
, normal_dest
,
22096 normal_dest
, const0_rtx
));
22098 /* Join NaN and non-Nan paths. Compare dest against 0. */
22099 emit_label (join_label
);
22103 emit_insn (gen_rtx_SET (compare_result
,
22104 gen_rtx_COMPARE (comp_mode
, dest
, const0_rtx
)));
22109 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
22110 CLOBBERs to match cmptf_internal2 pattern. */
22111 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
22112 && FLOAT128_IBM_P (GET_MODE (op0
))
22113 && TARGET_HARD_FLOAT
)
22114 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22116 gen_rtx_SET (compare_result
,
22117 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
22118 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22119 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22120 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22121 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22122 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22123 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22124 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22125 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
22126 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
22127 else if (GET_CODE (op1
) == UNSPEC
22128 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
22130 rtx op1b
= XVECEXP (op1
, 0, 0);
22131 comp_mode
= CCEQmode
;
22132 compare_result
= gen_reg_rtx (CCEQmode
);
22134 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
22136 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
22139 emit_insn (gen_rtx_SET (compare_result
,
22140 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
22143 /* Some kinds of FP comparisons need an OR operation;
22144 under flag_finite_math_only we don't bother. */
22145 if (FLOAT_MODE_P (mode
)
22146 && (!FLOAT128_IEEE_P (mode
) || TARGET_FLOAT128_HW
)
22147 && !flag_finite_math_only
22148 && (code
== LE
|| code
== GE
22149 || code
== UNEQ
|| code
== LTGT
22150 || code
== UNGT
|| code
== UNLT
))
22152 enum rtx_code or1
, or2
;
22153 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
22154 rtx or_result
= gen_reg_rtx (CCEQmode
);
22158 case LE
: or1
= LT
; or2
= EQ
; break;
22159 case GE
: or1
= GT
; or2
= EQ
; break;
22160 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
22161 case LTGT
: or1
= LT
; or2
= GT
; break;
22162 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
22163 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
22164 default: gcc_unreachable ();
22166 validate_condition_mode (or1
, comp_mode
);
22167 validate_condition_mode (or2
, comp_mode
);
22168 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
22169 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
22170 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
22171 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
22173 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
22175 compare_result
= or_result
;
22179 validate_condition_mode (code
, GET_MODE (compare_result
));
22181 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
22185 /* Return the diagnostic message string if the binary operation OP is
22186 not permitted on TYPE1 and TYPE2, NULL otherwise. */
22189 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED
,
22193 machine_mode mode1
= TYPE_MODE (type1
);
22194 machine_mode mode2
= TYPE_MODE (type2
);
22196 /* For complex modes, use the inner type. */
22197 if (COMPLEX_MODE_P (mode1
))
22198 mode1
= GET_MODE_INNER (mode1
);
22200 if (COMPLEX_MODE_P (mode2
))
22201 mode2
= GET_MODE_INNER (mode2
);
22203 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
22204 double to intermix unless -mfloat128-convert. */
22205 if (mode1
== mode2
)
22208 if (!TARGET_FLOAT128_CVT
)
22210 if ((mode1
== KFmode
&& mode2
== IFmode
)
22211 || (mode1
== IFmode
&& mode2
== KFmode
))
22212 return N_("__float128 and __ibm128 cannot be used in the same "
22215 if (TARGET_IEEEQUAD
22216 && ((mode1
== IFmode
&& mode2
== TFmode
)
22217 || (mode1
== TFmode
&& mode2
== IFmode
)))
22218 return N_("__ibm128 and long double cannot be used in the same "
22221 if (!TARGET_IEEEQUAD
22222 && ((mode1
== KFmode
&& mode2
== TFmode
)
22223 || (mode1
== TFmode
&& mode2
== KFmode
)))
22224 return N_("__float128 and long double cannot be used in the same "
22232 /* Expand floating point conversion to/from __float128 and __ibm128. */
22235 rs6000_expand_float128_convert (rtx dest
, rtx src
, bool unsigned_p
)
22237 machine_mode dest_mode
= GET_MODE (dest
);
22238 machine_mode src_mode
= GET_MODE (src
);
22239 convert_optab cvt
= unknown_optab
;
22240 bool do_move
= false;
22241 rtx libfunc
= NULL_RTX
;
22243 typedef rtx (*rtx_2func_t
) (rtx
, rtx
);
22244 rtx_2func_t hw_convert
= (rtx_2func_t
)0;
22248 rtx_2func_t from_df
;
22249 rtx_2func_t from_sf
;
22250 rtx_2func_t from_si_sign
;
22251 rtx_2func_t from_si_uns
;
22252 rtx_2func_t from_di_sign
;
22253 rtx_2func_t from_di_uns
;
22256 rtx_2func_t to_si_sign
;
22257 rtx_2func_t to_si_uns
;
22258 rtx_2func_t to_di_sign
;
22259 rtx_2func_t to_di_uns
;
22260 } hw_conversions
[2] = {
22261 /* convertions to/from KFmode */
22263 gen_extenddfkf2_hw
, /* KFmode <- DFmode. */
22264 gen_extendsfkf2_hw
, /* KFmode <- SFmode. */
22265 gen_float_kfsi2_hw
, /* KFmode <- SImode (signed). */
22266 gen_floatuns_kfsi2_hw
, /* KFmode <- SImode (unsigned). */
22267 gen_float_kfdi2_hw
, /* KFmode <- DImode (signed). */
22268 gen_floatuns_kfdi2_hw
, /* KFmode <- DImode (unsigned). */
22269 gen_trunckfdf2_hw
, /* DFmode <- KFmode. */
22270 gen_trunckfsf2_hw
, /* SFmode <- KFmode. */
22271 gen_fix_kfsi2_hw
, /* SImode <- KFmode (signed). */
22272 gen_fixuns_kfsi2_hw
, /* SImode <- KFmode (unsigned). */
22273 gen_fix_kfdi2_hw
, /* DImode <- KFmode (signed). */
22274 gen_fixuns_kfdi2_hw
, /* DImode <- KFmode (unsigned). */
22277 /* convertions to/from TFmode */
22279 gen_extenddftf2_hw
, /* TFmode <- DFmode. */
22280 gen_extendsftf2_hw
, /* TFmode <- SFmode. */
22281 gen_float_tfsi2_hw
, /* TFmode <- SImode (signed). */
22282 gen_floatuns_tfsi2_hw
, /* TFmode <- SImode (unsigned). */
22283 gen_float_tfdi2_hw
, /* TFmode <- DImode (signed). */
22284 gen_floatuns_tfdi2_hw
, /* TFmode <- DImode (unsigned). */
22285 gen_trunctfdf2_hw
, /* DFmode <- TFmode. */
22286 gen_trunctfsf2_hw
, /* SFmode <- TFmode. */
22287 gen_fix_tfsi2_hw
, /* SImode <- TFmode (signed). */
22288 gen_fixuns_tfsi2_hw
, /* SImode <- TFmode (unsigned). */
22289 gen_fix_tfdi2_hw
, /* DImode <- TFmode (signed). */
22290 gen_fixuns_tfdi2_hw
, /* DImode <- TFmode (unsigned). */
22294 if (dest_mode
== src_mode
)
22295 gcc_unreachable ();
22297 /* Eliminate memory operations. */
22299 src
= force_reg (src_mode
, src
);
22303 rtx tmp
= gen_reg_rtx (dest_mode
);
22304 rs6000_expand_float128_convert (tmp
, src
, unsigned_p
);
22305 rs6000_emit_move (dest
, tmp
, dest_mode
);
22309 /* Convert to IEEE 128-bit floating point. */
22310 if (FLOAT128_IEEE_P (dest_mode
))
22312 if (dest_mode
== KFmode
)
22314 else if (dest_mode
== TFmode
)
22317 gcc_unreachable ();
22323 hw_convert
= hw_conversions
[kf_or_tf
].from_df
;
22328 hw_convert
= hw_conversions
[kf_or_tf
].from_sf
;
22334 if (FLOAT128_IBM_P (src_mode
))
22343 cvt
= ufloat_optab
;
22344 hw_convert
= hw_conversions
[kf_or_tf
].from_si_uns
;
22348 cvt
= sfloat_optab
;
22349 hw_convert
= hw_conversions
[kf_or_tf
].from_si_sign
;
22356 cvt
= ufloat_optab
;
22357 hw_convert
= hw_conversions
[kf_or_tf
].from_di_uns
;
22361 cvt
= sfloat_optab
;
22362 hw_convert
= hw_conversions
[kf_or_tf
].from_di_sign
;
22367 gcc_unreachable ();
22371 /* Convert from IEEE 128-bit floating point. */
22372 else if (FLOAT128_IEEE_P (src_mode
))
22374 if (src_mode
== KFmode
)
22376 else if (src_mode
== TFmode
)
22379 gcc_unreachable ();
22385 hw_convert
= hw_conversions
[kf_or_tf
].to_df
;
22390 hw_convert
= hw_conversions
[kf_or_tf
].to_sf
;
22396 if (FLOAT128_IBM_P (dest_mode
))
22406 hw_convert
= hw_conversions
[kf_or_tf
].to_si_uns
;
22411 hw_convert
= hw_conversions
[kf_or_tf
].to_si_sign
;
22419 hw_convert
= hw_conversions
[kf_or_tf
].to_di_uns
;
22424 hw_convert
= hw_conversions
[kf_or_tf
].to_di_sign
;
22429 gcc_unreachable ();
22433 /* Both IBM format. */
22434 else if (FLOAT128_IBM_P (dest_mode
) && FLOAT128_IBM_P (src_mode
))
22438 gcc_unreachable ();
22440 /* Handle conversion between TFmode/KFmode/IFmode. */
22442 emit_insn (gen_rtx_SET (dest
, gen_rtx_FLOAT_EXTEND (dest_mode
, src
)));
22444 /* Handle conversion if we have hardware support. */
22445 else if (TARGET_FLOAT128_HW
&& hw_convert
)
22446 emit_insn ((hw_convert
) (dest
, src
));
22448 /* Call an external function to do the conversion. */
22449 else if (cvt
!= unknown_optab
)
22451 libfunc
= convert_optab_libfunc (cvt
, dest_mode
, src_mode
);
22452 gcc_assert (libfunc
!= NULL_RTX
);
22454 dest2
= emit_library_call_value (libfunc
, dest
, LCT_CONST
, dest_mode
,
22457 gcc_assert (dest2
!= NULL_RTX
);
22458 if (!rtx_equal_p (dest
, dest2
))
22459 emit_move_insn (dest
, dest2
);
22463 gcc_unreachable ();
22469 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22470 can be used as that dest register. Return the dest register. */
22473 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
22475 if (op2
== const0_rtx
)
22478 if (GET_CODE (scratch
) == SCRATCH
)
22479 scratch
= gen_reg_rtx (mode
);
22481 if (logical_operand (op2
, mode
))
22482 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
22484 emit_insn (gen_rtx_SET (scratch
,
22485 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
22491 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
22494 machine_mode op_mode
;
22495 enum rtx_code cond_code
;
22496 rtx result
= operands
[0];
22498 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
22499 cond_code
= GET_CODE (condition_rtx
);
22501 if (cond_code
== NE
22502 || cond_code
== GE
|| cond_code
== LE
22503 || cond_code
== GEU
|| cond_code
== LEU
22504 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
22506 rtx not_result
= gen_reg_rtx (CCEQmode
);
22507 rtx not_op
, rev_cond_rtx
;
22508 machine_mode cc_mode
;
22510 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
22512 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
22513 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
22514 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
22515 emit_insn (gen_rtx_SET (not_result
, not_op
));
22516 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
22519 op_mode
= GET_MODE (XEXP (operands
[1], 0));
22520 if (op_mode
== VOIDmode
)
22521 op_mode
= GET_MODE (XEXP (operands
[1], 1));
22523 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
22525 PUT_MODE (condition_rtx
, DImode
);
22526 convert_move (result
, condition_rtx
, 0);
22530 PUT_MODE (condition_rtx
, SImode
);
22531 emit_insn (gen_rtx_SET (result
, condition_rtx
));
22535 /* Emit a branch of kind CODE to location LOC. */
22538 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
22540 rtx condition_rtx
, loc_ref
;
22542 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
22543 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
22544 emit_jump_insn (gen_rtx_SET (pc_rtx
,
22545 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
22546 loc_ref
, pc_rtx
)));
22549 /* Return the string to output a conditional branch to LABEL, which is
22550 the operand template of the label, or NULL if the branch is really a
22551 conditional return.
22553 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22554 condition code register and its mode specifies what kind of
22555 comparison we made.
22557 REVERSED is nonzero if we should reverse the sense of the comparison.
22559 INSN is the insn. */
22562 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
22564 static char string
[64];
22565 enum rtx_code code
= GET_CODE (op
);
22566 rtx cc_reg
= XEXP (op
, 0);
22567 machine_mode mode
= GET_MODE (cc_reg
);
22568 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
22569 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
22570 int really_reversed
= reversed
^ need_longbranch
;
22576 validate_condition_mode (code
, mode
);
22578 /* Work out which way this really branches. We could use
22579 reverse_condition_maybe_unordered here always but this
22580 makes the resulting assembler clearer. */
22581 if (really_reversed
)
22583 /* Reversal of FP compares takes care -- an ordered compare
22584 becomes an unordered compare and vice versa. */
22585 if (mode
== CCFPmode
)
22586 code
= reverse_condition_maybe_unordered (code
);
22588 code
= reverse_condition (code
);
22593 /* Not all of these are actually distinct opcodes, but
22594 we distinguish them for clarity of the resulting assembler. */
22595 case NE
: case LTGT
:
22596 ccode
= "ne"; break;
22597 case EQ
: case UNEQ
:
22598 ccode
= "eq"; break;
22600 ccode
= "ge"; break;
22601 case GT
: case GTU
: case UNGT
:
22602 ccode
= "gt"; break;
22604 ccode
= "le"; break;
22605 case LT
: case LTU
: case UNLT
:
22606 ccode
= "lt"; break;
22607 case UNORDERED
: ccode
= "un"; break;
22608 case ORDERED
: ccode
= "nu"; break;
22609 case UNGE
: ccode
= "nl"; break;
22610 case UNLE
: ccode
= "ng"; break;
22612 gcc_unreachable ();
22615 /* Maybe we have a guess as to how likely the branch is. */
22617 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
22618 if (note
!= NULL_RTX
)
22620 /* PROB is the difference from 50%. */
22621 int prob
= profile_probability::from_reg_br_prob_note (XINT (note
, 0))
22622 .to_reg_br_prob_base () - REG_BR_PROB_BASE
/ 2;
22624 /* Only hint for highly probable/improbable branches on newer cpus when
22625 we have real profile data, as static prediction overrides processor
22626 dynamic prediction. For older cpus we may as well always hint, but
22627 assume not taken for branches that are very close to 50% as a
22628 mispredicted taken branch is more expensive than a
22629 mispredicted not-taken branch. */
22630 if (rs6000_always_hint
22631 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
22632 && (profile_status_for_fn (cfun
) != PROFILE_GUESSED
)
22633 && br_prob_note_reliable_p (note
)))
22635 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
22636 && ((prob
> 0) ^ need_longbranch
))
22644 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
22646 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
22648 /* We need to escape any '%' characters in the reg_names string.
22649 Assume they'd only be the first character.... */
22650 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
22652 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
22656 /* If the branch distance was too far, we may have to use an
22657 unconditional branch to go the distance. */
22658 if (need_longbranch
)
22659 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
22661 s
+= sprintf (s
, ",%s", label
);
22667 /* Return insn for VSX or Altivec comparisons. */
22670 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
22673 machine_mode mode
= GET_MODE (op0
);
22681 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
22692 mask
= gen_reg_rtx (mode
);
22693 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
22700 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22701 DMODE is expected destination mode. This is a recursive function. */
22704 rs6000_emit_vector_compare (enum rtx_code rcode
,
22706 machine_mode dmode
)
22709 bool swap_operands
= false;
22710 bool try_again
= false;
22712 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
22713 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
22715 /* See if the comparison works as is. */
22716 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22724 swap_operands
= true;
22729 swap_operands
= true;
22737 /* Invert condition and try again.
22738 e.g., A != B becomes ~(A==B). */
22740 enum rtx_code rev_code
;
22741 enum insn_code nor_code
;
22744 rev_code
= reverse_condition_maybe_unordered (rcode
);
22745 if (rev_code
== UNKNOWN
)
22748 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
22749 if (nor_code
== CODE_FOR_nothing
)
22752 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
22756 mask
= gen_reg_rtx (dmode
);
22757 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
22765 /* Try GT/GTU/LT/LTU OR EQ */
22768 enum insn_code ior_code
;
22769 enum rtx_code new_code
;
22790 gcc_unreachable ();
22793 ior_code
= optab_handler (ior_optab
, dmode
);
22794 if (ior_code
== CODE_FOR_nothing
)
22797 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
22801 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
22805 mask
= gen_reg_rtx (dmode
);
22806 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
22817 std::swap (op0
, op1
);
22819 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
22824 /* You only get two chances. */
22828 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22829 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22830 operands for the relation operation COND. */
22833 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
22834 rtx cond
, rtx cc_op0
, rtx cc_op1
)
22836 machine_mode dest_mode
= GET_MODE (dest
);
22837 machine_mode mask_mode
= GET_MODE (cc_op0
);
22838 enum rtx_code rcode
= GET_CODE (cond
);
22839 machine_mode cc_mode
= CCmode
;
22842 bool invert_move
= false;
22844 if (VECTOR_UNIT_NONE_P (dest_mode
))
22847 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
22848 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
22852 /* Swap operands if we can, and fall back to doing the operation as
22853 specified, and doing a NOR to invert the test. */
22859 /* Invert condition and try again.
22860 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22861 invert_move
= true;
22862 rcode
= reverse_condition_maybe_unordered (rcode
);
22863 if (rcode
== UNKNOWN
)
22869 if (GET_MODE_CLASS (mask_mode
) == MODE_VECTOR_INT
)
22871 /* Invert condition to avoid compound test. */
22872 invert_move
= true;
22873 rcode
= reverse_condition (rcode
);
22881 /* Mark unsigned tests with CCUNSmode. */
22882 cc_mode
= CCUNSmode
;
22884 /* Invert condition to avoid compound test if necessary. */
22885 if (rcode
== GEU
|| rcode
== LEU
)
22887 invert_move
= true;
22888 rcode
= reverse_condition (rcode
);
22896 /* Get the vector mask for the given relational operations. */
22897 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
22903 std::swap (op_true
, op_false
);
22905 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22906 if (GET_MODE_CLASS (dest_mode
) == MODE_VECTOR_INT
22907 && (GET_CODE (op_true
) == CONST_VECTOR
22908 || GET_CODE (op_false
) == CONST_VECTOR
))
22910 rtx constant_0
= CONST0_RTX (dest_mode
);
22911 rtx constant_m1
= CONSTM1_RTX (dest_mode
);
22913 if (op_true
== constant_m1
&& op_false
== constant_0
)
22915 emit_move_insn (dest
, mask
);
22919 else if (op_true
== constant_0
&& op_false
== constant_m1
)
22921 emit_insn (gen_rtx_SET (dest
, gen_rtx_NOT (dest_mode
, mask
)));
22925 /* If we can't use the vector comparison directly, perhaps we can use
22926 the mask for the true or false fields, instead of loading up a
22928 if (op_true
== constant_m1
)
22931 if (op_false
== constant_0
)
22935 if (!REG_P (op_true
) && !SUBREG_P (op_true
))
22936 op_true
= force_reg (dest_mode
, op_true
);
22938 if (!REG_P (op_false
) && !SUBREG_P (op_false
))
22939 op_false
= force_reg (dest_mode
, op_false
);
22941 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
22942 CONST0_RTX (dest_mode
));
22943 emit_insn (gen_rtx_SET (dest
,
22944 gen_rtx_IF_THEN_ELSE (dest_mode
,
22951 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22952 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22953 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22954 hardware has no such operation. */
22957 rs6000_emit_p9_fp_minmax (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22959 enum rtx_code code
= GET_CODE (op
);
22960 rtx op0
= XEXP (op
, 0);
22961 rtx op1
= XEXP (op
, 1);
22962 machine_mode compare_mode
= GET_MODE (op0
);
22963 machine_mode result_mode
= GET_MODE (dest
);
22964 bool max_p
= false;
22966 if (result_mode
!= compare_mode
)
22969 if (code
== GE
|| code
== GT
)
22971 else if (code
== LE
|| code
== LT
)
22976 if (rtx_equal_p (op0
, true_cond
) && rtx_equal_p (op1
, false_cond
))
22979 else if (rtx_equal_p (op1
, true_cond
) && rtx_equal_p (op0
, false_cond
))
22985 rs6000_emit_minmax (dest
, max_p
? SMAX
: SMIN
, op0
, op1
);
22989 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22990 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22991 operands of the last comparison is nonzero/true, FALSE_COND if it is
22992 zero/false. Return 0 if the hardware has no such operation. */
22995 rs6000_emit_p9_fp_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
22997 enum rtx_code code
= GET_CODE (op
);
22998 rtx op0
= XEXP (op
, 0);
22999 rtx op1
= XEXP (op
, 1);
23000 machine_mode result_mode
= GET_MODE (dest
);
23005 if (!can_create_pseudo_p ())
23018 code
= swap_condition (code
);
23019 std::swap (op0
, op1
);
23026 /* Generate: [(parallel [(set (dest)
23027 (if_then_else (op (cmp1) (cmp2))
23030 (clobber (scratch))])]. */
23032 compare_rtx
= gen_rtx_fmt_ee (code
, CCFPmode
, op0
, op1
);
23033 cmove_rtx
= gen_rtx_SET (dest
,
23034 gen_rtx_IF_THEN_ELSE (result_mode
,
23039 clobber_rtx
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (V2DImode
));
23040 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
23041 gen_rtvec (2, cmove_rtx
, clobber_rtx
)));
23046 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
23047 operands of the last comparison is nonzero/true, FALSE_COND if it
23048 is zero/false. Return 0 if the hardware has no such operation. */
23051 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
23053 enum rtx_code code
= GET_CODE (op
);
23054 rtx op0
= XEXP (op
, 0);
23055 rtx op1
= XEXP (op
, 1);
23056 machine_mode compare_mode
= GET_MODE (op0
);
23057 machine_mode result_mode
= GET_MODE (dest
);
23059 bool is_against_zero
;
23061 /* These modes should always match. */
23062 if (GET_MODE (op1
) != compare_mode
23063 /* In the isel case however, we can use a compare immediate, so
23064 op1 may be a small constant. */
23065 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
23067 if (GET_MODE (true_cond
) != result_mode
)
23069 if (GET_MODE (false_cond
) != result_mode
)
23072 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
23073 if (TARGET_P9_MINMAX
23074 && (compare_mode
== SFmode
|| compare_mode
== DFmode
)
23075 && (result_mode
== SFmode
|| result_mode
== DFmode
))
23077 if (rs6000_emit_p9_fp_minmax (dest
, op
, true_cond
, false_cond
))
23080 if (rs6000_emit_p9_fp_cmove (dest
, op
, true_cond
, false_cond
))
23084 /* Don't allow using floating point comparisons for integer results for
23086 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
23089 /* First, work out if the hardware can do this at all, or
23090 if it's too slow.... */
23091 if (!FLOAT_MODE_P (compare_mode
))
23094 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
23098 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
23100 /* A floating-point subtract might overflow, underflow, or produce
23101 an inexact result, thus changing the floating-point flags, so it
23102 can't be generated if we care about that. It's safe if one side
23103 of the construct is zero, since then no subtract will be
23105 if (SCALAR_FLOAT_MODE_P (compare_mode
)
23106 && flag_trapping_math
&& ! is_against_zero
)
23109 /* Eliminate half of the comparisons by switching operands, this
23110 makes the remaining code simpler. */
23111 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
23112 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
23114 code
= reverse_condition_maybe_unordered (code
);
23116 true_cond
= false_cond
;
23120 /* UNEQ and LTGT take four instructions for a comparison with zero,
23121 it'll probably be faster to use a branch here too. */
23122 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
23125 /* We're going to try to implement comparisons by performing
23126 a subtract, then comparing against zero. Unfortunately,
23127 Inf - Inf is NaN which is not zero, and so if we don't
23128 know that the operand is finite and the comparison
23129 would treat EQ different to UNORDERED, we can't do it. */
23130 if (HONOR_INFINITIES (compare_mode
)
23131 && code
!= GT
&& code
!= UNGE
23132 && (!CONST_DOUBLE_P (op1
)
23133 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1
)))
23134 /* Constructs of the form (a OP b ? a : b) are safe. */
23135 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
23136 || (! rtx_equal_p (op0
, true_cond
)
23137 && ! rtx_equal_p (op1
, true_cond
))))
23140 /* At this point we know we can use fsel. */
23142 /* Reduce the comparison to a comparison against zero. */
23143 if (! is_against_zero
)
23145 temp
= gen_reg_rtx (compare_mode
);
23146 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
23148 op1
= CONST0_RTX (compare_mode
);
23151 /* If we don't care about NaNs we can reduce some of the comparisons
23152 down to faster ones. */
23153 if (! HONOR_NANS (compare_mode
))
23159 true_cond
= false_cond
;
23172 /* Now, reduce everything down to a GE. */
23179 temp
= gen_reg_rtx (compare_mode
);
23180 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
23185 temp
= gen_reg_rtx (compare_mode
);
23186 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
23191 temp
= gen_reg_rtx (compare_mode
);
23192 emit_insn (gen_rtx_SET (temp
,
23193 gen_rtx_NEG (compare_mode
,
23194 gen_rtx_ABS (compare_mode
, op0
))));
23199 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
23200 temp
= gen_reg_rtx (result_mode
);
23201 emit_insn (gen_rtx_SET (temp
,
23202 gen_rtx_IF_THEN_ELSE (result_mode
,
23203 gen_rtx_GE (VOIDmode
,
23205 true_cond
, false_cond
)));
23206 false_cond
= true_cond
;
23209 temp
= gen_reg_rtx (compare_mode
);
23210 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
23215 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
23216 temp
= gen_reg_rtx (result_mode
);
23217 emit_insn (gen_rtx_SET (temp
,
23218 gen_rtx_IF_THEN_ELSE (result_mode
,
23219 gen_rtx_GE (VOIDmode
,
23221 true_cond
, false_cond
)));
23222 true_cond
= false_cond
;
23225 temp
= gen_reg_rtx (compare_mode
);
23226 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
23231 gcc_unreachable ();
23234 emit_insn (gen_rtx_SET (dest
,
23235 gen_rtx_IF_THEN_ELSE (result_mode
,
23236 gen_rtx_GE (VOIDmode
,
23238 true_cond
, false_cond
)));
23242 /* Same as above, but for ints (isel). */
23245 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
23247 rtx condition_rtx
, cr
;
23248 machine_mode mode
= GET_MODE (dest
);
23249 enum rtx_code cond_code
;
23250 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
23253 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
23256 /* We still have to do the compare, because isel doesn't do a
23257 compare, it just looks at the CRx bits set by a previous compare
23259 condition_rtx
= rs6000_generate_compare (op
, mode
);
23260 cond_code
= GET_CODE (condition_rtx
);
23261 cr
= XEXP (condition_rtx
, 0);
23262 signedp
= GET_MODE (cr
) == CCmode
;
23264 isel_func
= (mode
== SImode
23265 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
23266 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
23270 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
23271 /* isel handles these directly. */
23275 /* We need to swap the sense of the comparison. */
23277 std::swap (false_cond
, true_cond
);
23278 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
23283 false_cond
= force_reg (mode
, false_cond
);
23284 if (true_cond
!= const0_rtx
)
23285 true_cond
= force_reg (mode
, true_cond
);
23287 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
23293 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
23295 machine_mode mode
= GET_MODE (op0
);
23299 /* VSX/altivec have direct min/max insns. */
23300 if ((code
== SMAX
|| code
== SMIN
)
23301 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
23302 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
23304 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
23308 if (code
== SMAX
|| code
== SMIN
)
23313 if (code
== SMAX
|| code
== UMAX
)
23314 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
23315 op0
, op1
, mode
, 0);
23317 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
23318 op1
, op0
, mode
, 0);
23319 gcc_assert (target
);
23320 if (target
!= dest
)
23321 emit_move_insn (dest
, target
);
23324 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23325 COND is true. Mark the jump as unlikely to be taken. */
23328 emit_unlikely_jump (rtx cond
, rtx label
)
23330 rtx x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
23331 rtx_insn
*insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
23332 add_reg_br_prob_note (insn
, profile_probability::very_unlikely ());
23335 /* A subroutine of the atomic operation splitters. Emit a load-locked
23336 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23337 the zero_extend operation. */
23340 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
23342 rtx (*fn
) (rtx
, rtx
) = NULL
;
23347 fn
= gen_load_lockedqi
;
23350 fn
= gen_load_lockedhi
;
23353 if (GET_MODE (mem
) == QImode
)
23354 fn
= gen_load_lockedqi_si
;
23355 else if (GET_MODE (mem
) == HImode
)
23356 fn
= gen_load_lockedhi_si
;
23358 fn
= gen_load_lockedsi
;
23361 fn
= gen_load_lockeddi
;
23364 fn
= gen_load_lockedti
;
23367 gcc_unreachable ();
23369 emit_insn (fn (reg
, mem
));
23372 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23373 instruction in MODE. */
23376 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
23378 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
23383 fn
= gen_store_conditionalqi
;
23386 fn
= gen_store_conditionalhi
;
23389 fn
= gen_store_conditionalsi
;
23392 fn
= gen_store_conditionaldi
;
23395 fn
= gen_store_conditionalti
;
23398 gcc_unreachable ();
23401 /* Emit sync before stwcx. to address PPC405 Erratum. */
23402 if (PPC405_ERRATUM77
)
23403 emit_insn (gen_hwsync ());
23405 emit_insn (fn (res
, mem
, val
));
23408 /* Expand barriers before and after a load_locked/store_cond sequence. */
23411 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
23413 rtx addr
= XEXP (mem
, 0);
23415 if (!legitimate_indirect_address_p (addr
, reload_completed
)
23416 && !legitimate_indexed_address_p (addr
, reload_completed
))
23418 addr
= force_reg (Pmode
, addr
);
23419 mem
= replace_equiv_address_nv (mem
, addr
);
23424 case MEMMODEL_RELAXED
:
23425 case MEMMODEL_CONSUME
:
23426 case MEMMODEL_ACQUIRE
:
23428 case MEMMODEL_RELEASE
:
23429 case MEMMODEL_ACQ_REL
:
23430 emit_insn (gen_lwsync ());
23432 case MEMMODEL_SEQ_CST
:
23433 emit_insn (gen_hwsync ());
23436 gcc_unreachable ();
23442 rs6000_post_atomic_barrier (enum memmodel model
)
23446 case MEMMODEL_RELAXED
:
23447 case MEMMODEL_CONSUME
:
23448 case MEMMODEL_RELEASE
:
23450 case MEMMODEL_ACQUIRE
:
23451 case MEMMODEL_ACQ_REL
:
23452 case MEMMODEL_SEQ_CST
:
23453 emit_insn (gen_isync ());
23456 gcc_unreachable ();
23460 /* A subroutine of the various atomic expanders. For sub-word operations,
23461 we must adjust things to operate on SImode. Given the original MEM,
23462 return a new aligned memory. Also build and return the quantities by
23463 which to shift and mask. */
23466 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
23468 rtx addr
, align
, shift
, mask
, mem
;
23469 HOST_WIDE_INT shift_mask
;
23470 machine_mode mode
= GET_MODE (orig_mem
);
23472 /* For smaller modes, we have to implement this via SImode. */
23473 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
23475 addr
= XEXP (orig_mem
, 0);
23476 addr
= force_reg (GET_MODE (addr
), addr
);
23478 /* Aligned memory containing subword. Generate a new memory. We
23479 do not want any of the existing MEM_ATTR data, as we're now
23480 accessing memory outside the original object. */
23481 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
23482 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23483 mem
= gen_rtx_MEM (SImode
, align
);
23484 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
23485 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
23486 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
23488 /* Shift amount for subword relative to aligned word. */
23489 shift
= gen_reg_rtx (SImode
);
23490 addr
= gen_lowpart (SImode
, addr
);
23491 rtx tmp
= gen_reg_rtx (SImode
);
23492 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
23493 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
23494 if (BYTES_BIG_ENDIAN
)
23495 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
23496 shift
, 1, OPTAB_LIB_WIDEN
);
23499 /* Mask for insertion. */
23500 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
23501 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23507 /* A subroutine of the various atomic expanders. For sub-word operands,
23508 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23511 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
23515 x
= gen_reg_rtx (SImode
);
23516 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
23517 gen_rtx_NOT (SImode
, mask
),
23520 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
23525 /* A subroutine of the various atomic expanders. For sub-word operands,
23526 extract WIDE to NARROW via SHIFT. */
23529 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
23531 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
23532 wide
, 1, OPTAB_LIB_WIDEN
);
23533 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
23536 /* Expand an atomic compare and swap operation. */
23539 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
23541 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
23542 rtx label1
, label2
, x
, mask
, shift
;
23543 machine_mode mode
, orig_mode
;
23544 enum memmodel mod_s
, mod_f
;
23547 boolval
= operands
[0];
23548 retval
= operands
[1];
23550 oldval
= operands
[3];
23551 newval
= operands
[4];
23552 is_weak
= (INTVAL (operands
[5]) != 0);
23553 mod_s
= memmodel_base (INTVAL (operands
[6]));
23554 mod_f
= memmodel_base (INTVAL (operands
[7]));
23555 orig_mode
= mode
= GET_MODE (mem
);
23557 mask
= shift
= NULL_RTX
;
23558 if (mode
== QImode
|| mode
== HImode
)
23560 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23561 lwarx and shift/mask operations. With power8, we need to do the
23562 comparison in SImode, but the store is still done in QI/HImode. */
23563 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
23565 if (!TARGET_SYNC_HI_QI
)
23567 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23569 /* Shift and mask OLDVAL into position with the word. */
23570 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
23571 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23573 /* Shift and mask NEWVAL into position within the word. */
23574 newval
= convert_modes (SImode
, mode
, newval
, 1);
23575 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
23576 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23579 /* Prepare to adjust the return value. */
23580 retval
= gen_reg_rtx (SImode
);
23583 else if (reg_overlap_mentioned_p (retval
, oldval
))
23584 oldval
= copy_to_reg (oldval
);
23586 if (mode
!= TImode
&& !reg_or_short_operand (oldval
, mode
))
23587 oldval
= copy_to_mode_reg (mode
, oldval
);
23589 if (reg_overlap_mentioned_p (retval
, newval
))
23590 newval
= copy_to_reg (newval
);
23592 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
23597 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23598 emit_label (XEXP (label1
, 0));
23600 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23602 emit_load_locked (mode
, retval
, mem
);
23606 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
23607 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23609 cond
= gen_reg_rtx (CCmode
);
23610 /* If we have TImode, synthesize a comparison. */
23611 if (mode
!= TImode
)
23612 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
23615 rtx xor1_result
= gen_reg_rtx (DImode
);
23616 rtx xor2_result
= gen_reg_rtx (DImode
);
23617 rtx or_result
= gen_reg_rtx (DImode
);
23618 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
23619 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
23620 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
23621 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
23623 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
23624 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
23625 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
23626 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
23629 emit_insn (gen_rtx_SET (cond
, x
));
23631 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23632 emit_unlikely_jump (x
, label2
);
23636 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
23638 emit_store_conditional (orig_mode
, cond
, mem
, x
);
23642 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23643 emit_unlikely_jump (x
, label1
);
23646 if (!is_mm_relaxed (mod_f
))
23647 emit_label (XEXP (label2
, 0));
23649 rs6000_post_atomic_barrier (mod_s
);
23651 if (is_mm_relaxed (mod_f
))
23652 emit_label (XEXP (label2
, 0));
23655 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
23656 else if (mode
!= GET_MODE (operands
[1]))
23657 convert_move (operands
[1], retval
, 1);
23659 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23660 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
23661 emit_insn (gen_rtx_SET (boolval
, x
));
23664 /* Expand an atomic exchange operation. */
23667 rs6000_expand_atomic_exchange (rtx operands
[])
23669 rtx retval
, mem
, val
, cond
;
23671 enum memmodel model
;
23672 rtx label
, x
, mask
, shift
;
23674 retval
= operands
[0];
23677 model
= memmodel_base (INTVAL (operands
[3]));
23678 mode
= GET_MODE (mem
);
23680 mask
= shift
= NULL_RTX
;
23681 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
23683 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23685 /* Shift and mask VAL into position with the word. */
23686 val
= convert_modes (SImode
, mode
, val
, 1);
23687 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23688 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23690 /* Prepare to adjust the return value. */
23691 retval
= gen_reg_rtx (SImode
);
23695 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23697 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
23698 emit_label (XEXP (label
, 0));
23700 emit_load_locked (mode
, retval
, mem
);
23704 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
23706 cond
= gen_reg_rtx (CCmode
);
23707 emit_store_conditional (mode
, cond
, mem
, x
);
23709 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23710 emit_unlikely_jump (x
, label
);
23712 rs6000_post_atomic_barrier (model
);
23715 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
23718 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23719 to perform. MEM is the memory on which to operate. VAL is the second
23720 operand of the binary operator. BEFORE and AFTER are optional locations to
23721 return the value of MEM either before of after the operation. MODEL_RTX
23722 is a CONST_INT containing the memory model to use. */
23725 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
23726 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
23728 enum memmodel model
= memmodel_base (INTVAL (model_rtx
));
23729 machine_mode mode
= GET_MODE (mem
);
23730 machine_mode store_mode
= mode
;
23731 rtx label
, x
, cond
, mask
, shift
;
23732 rtx before
= orig_before
, after
= orig_after
;
23734 mask
= shift
= NULL_RTX
;
23735 /* On power8, we want to use SImode for the operation. On previous systems,
23736 use the operation in a subword and shift/mask to get the proper byte or
23738 if (mode
== QImode
|| mode
== HImode
)
23740 if (TARGET_SYNC_HI_QI
)
23742 val
= convert_modes (SImode
, mode
, val
, 1);
23744 /* Prepare to adjust the return value. */
23745 before
= gen_reg_rtx (SImode
);
23747 after
= gen_reg_rtx (SImode
);
23752 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
23754 /* Shift and mask VAL into position with the word. */
23755 val
= convert_modes (SImode
, mode
, val
, 1);
23756 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
23757 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23763 /* We've already zero-extended VAL. That is sufficient to
23764 make certain that it does not affect other bits. */
23769 /* If we make certain that all of the other bits in VAL are
23770 set, that will be sufficient to not affect other bits. */
23771 x
= gen_rtx_NOT (SImode
, mask
);
23772 x
= gen_rtx_IOR (SImode
, x
, val
);
23773 emit_insn (gen_rtx_SET (val
, x
));
23780 /* These will all affect bits outside the field and need
23781 adjustment via MASK within the loop. */
23785 gcc_unreachable ();
23788 /* Prepare to adjust the return value. */
23789 before
= gen_reg_rtx (SImode
);
23791 after
= gen_reg_rtx (SImode
);
23792 store_mode
= mode
= SImode
;
23796 mem
= rs6000_pre_atomic_barrier (mem
, model
);
23798 label
= gen_label_rtx ();
23799 emit_label (label
);
23800 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
23802 if (before
== NULL_RTX
)
23803 before
= gen_reg_rtx (mode
);
23805 emit_load_locked (mode
, before
, mem
);
23809 x
= expand_simple_binop (mode
, AND
, before
, val
,
23810 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23811 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
23815 after
= expand_simple_binop (mode
, code
, before
, val
,
23816 after
, 1, OPTAB_LIB_WIDEN
);
23822 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
23823 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
23824 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
23826 else if (store_mode
!= mode
)
23827 x
= convert_modes (store_mode
, mode
, x
, 1);
23829 cond
= gen_reg_rtx (CCmode
);
23830 emit_store_conditional (store_mode
, cond
, mem
, x
);
23832 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
23833 emit_unlikely_jump (x
, label
);
23835 rs6000_post_atomic_barrier (model
);
23839 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23840 then do the calcuations in a SImode register. */
23842 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
23844 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
23846 else if (store_mode
!= mode
)
23848 /* QImode/HImode on machines with lbarx/lharx where we do the native
23849 operation and then do the calcuations in a SImode register. */
23851 convert_move (orig_before
, before
, 1);
23853 convert_move (orig_after
, after
, 1);
23855 else if (orig_after
&& after
!= orig_after
)
23856 emit_move_insn (orig_after
, after
);
23859 /* Emit instructions to move SRC to DST. Called by splitters for
23860 multi-register moves. It will emit at most one instruction for
23861 each register that is accessed; that is, it won't emit li/lis pairs
23862 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23866 rs6000_split_multireg_move (rtx dst
, rtx src
)
23868 /* The register number of the first register being moved. */
23870 /* The mode that is to be moved. */
23872 /* The mode that the move is being done in, and its size. */
23873 machine_mode reg_mode
;
23875 /* The number of registers that will be moved. */
23878 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
23879 mode
= GET_MODE (dst
);
23880 nregs
= hard_regno_nregs (reg
, mode
);
23881 if (FP_REGNO_P (reg
))
23882 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
23883 (TARGET_HARD_FLOAT
? DFmode
: SFmode
);
23884 else if (ALTIVEC_REGNO_P (reg
))
23885 reg_mode
= V16QImode
;
23887 reg_mode
= word_mode
;
23888 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
23890 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
23892 /* TDmode residing in FP registers is special, since the ISA requires that
23893 the lower-numbered word of a register pair is always the most significant
23894 word, even in little-endian mode. This does not match the usual subreg
23895 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23896 the appropriate constituent registers "by hand" in little-endian mode.
23898 Note we do not need to check for destructive overlap here since TDmode
23899 can only reside in even/odd register pairs. */
23900 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
23905 for (i
= 0; i
< nregs
; i
++)
23907 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
23908 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
23910 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
23911 i
* reg_mode_size
);
23913 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
23914 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
23916 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
23917 i
* reg_mode_size
);
23919 emit_insn (gen_rtx_SET (p_dst
, p_src
));
23925 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
23927 /* Move register range backwards, if we might have destructive
23930 for (i
= nregs
- 1; i
>= 0; i
--)
23931 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
23932 i
* reg_mode_size
),
23933 simplify_gen_subreg (reg_mode
, src
, mode
,
23934 i
* reg_mode_size
)));
23940 bool used_update
= false;
23941 rtx restore_basereg
= NULL_RTX
;
23943 if (MEM_P (src
) && INT_REGNO_P (reg
))
23947 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
23948 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
23951 breg
= XEXP (XEXP (src
, 0), 0);
23952 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
23953 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
23954 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
23955 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
23956 src
= replace_equiv_address (src
, breg
);
23958 else if (! rs6000_offsettable_memref_p (src
, reg_mode
, true))
23960 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
23962 rtx basereg
= XEXP (XEXP (src
, 0), 0);
23965 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
23966 emit_insn (gen_rtx_SET (ndst
,
23967 gen_rtx_MEM (reg_mode
,
23969 used_update
= true;
23972 emit_insn (gen_rtx_SET (basereg
,
23973 XEXP (XEXP (src
, 0), 1)));
23974 src
= replace_equiv_address (src
, basereg
);
23978 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
23979 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
23980 src
= replace_equiv_address (src
, basereg
);
23984 breg
= XEXP (src
, 0);
23985 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
23986 breg
= XEXP (breg
, 0);
23988 /* If the base register we are using to address memory is
23989 also a destination reg, then change that register last. */
23991 && REGNO (breg
) >= REGNO (dst
)
23992 && REGNO (breg
) < REGNO (dst
) + nregs
)
23993 j
= REGNO (breg
) - REGNO (dst
);
23995 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
23999 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
24000 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
24003 breg
= XEXP (XEXP (dst
, 0), 0);
24004 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
24005 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
24006 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
24008 /* We have to update the breg before doing the store.
24009 Use store with update, if available. */
24013 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
24014 emit_insn (TARGET_32BIT
24015 ? (TARGET_POWERPC64
24016 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
24017 : gen_movsi_si_update (breg
, breg
, delta_rtx
, nsrc
))
24018 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
24019 used_update
= true;
24022 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
24023 dst
= replace_equiv_address (dst
, breg
);
24025 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
, true)
24026 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
24028 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
24030 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
24033 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
24034 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
24037 used_update
= true;
24040 emit_insn (gen_rtx_SET (basereg
,
24041 XEXP (XEXP (dst
, 0), 1)));
24042 dst
= replace_equiv_address (dst
, basereg
);
24046 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
24047 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
24048 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
24050 && REG_P (offsetreg
)
24051 && REGNO (basereg
) != REGNO (offsetreg
));
24052 if (REGNO (basereg
) == 0)
24054 rtx tmp
= offsetreg
;
24055 offsetreg
= basereg
;
24058 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
24059 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
24060 dst
= replace_equiv_address (dst
, basereg
);
24063 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
24064 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
, true));
24067 for (i
= 0; i
< nregs
; i
++)
24069 /* Calculate index to next subword. */
24074 /* If compiler already emitted move of first word by
24075 store with update, no need to do anything. */
24076 if (j
== 0 && used_update
)
24079 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
24080 j
* reg_mode_size
),
24081 simplify_gen_subreg (reg_mode
, src
, mode
,
24082 j
* reg_mode_size
)));
24084 if (restore_basereg
!= NULL_RTX
)
24085 emit_insn (restore_basereg
);
24090 /* This page contains routines that are used to determine what the
24091 function prologue and epilogue code will do and write them out. */
24093 /* Determine whether the REG is really used. */
24096 save_reg_p (int reg
)
24098 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
&& !TARGET_SINGLE_PIC_BASE
)
24100 /* When calling eh_return, we must return true for all the cases
24101 where conditional_register_usage marks the PIC offset reg
24102 call used or fixed. */
24103 if (crtl
->calls_eh_return
24104 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
)
24105 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
24106 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
24109 /* We need to mark the PIC offset register live for the same
24110 conditions as it is set up in rs6000_emit_prologue, or
24111 otherwise it won't be saved before we clobber it. */
24112 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
24113 && !constant_pool_empty_p ())
24116 if (DEFAULT_ABI
== ABI_V4
24117 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
24118 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
24121 if (DEFAULT_ABI
== ABI_DARWIN
24122 && flag_pic
&& crtl
->uses_pic_offset_table
)
24126 return !call_used_regs
[reg
] && df_regs_ever_live_p (reg
);
24129 /* Return the first fixed-point register that is required to be
24130 saved. 32 if none. */
24133 first_reg_to_save (void)
24137 /* Find lowest numbered live register. */
24138 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
24139 if (save_reg_p (first_reg
))
24145 /* Similar, for FP regs. */
24148 first_fp_reg_to_save (void)
24152 /* Find lowest numbered live register. */
24153 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
24154 if (save_reg_p (first_reg
))
24160 /* Similar, for AltiVec regs. */
24163 first_altivec_reg_to_save (void)
24167 /* Stack frame remains as is unless we are in AltiVec ABI. */
24168 if (! TARGET_ALTIVEC_ABI
)
24169 return LAST_ALTIVEC_REGNO
+ 1;
24171 /* On Darwin, the unwind routines are compiled without
24172 TARGET_ALTIVEC, and use save_world to save/restore the
24173 altivec registers when necessary. */
24174 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
24175 && ! TARGET_ALTIVEC
)
24176 return FIRST_ALTIVEC_REGNO
+ 20;
24178 /* Find lowest numbered live register. */
24179 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24180 if (save_reg_p (i
))
24186 /* Return a 32-bit mask of the AltiVec registers we need to set in
24187 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
24188 the 32-bit word is 0. */
24190 static unsigned int
24191 compute_vrsave_mask (void)
24193 unsigned int i
, mask
= 0;
24195 /* On Darwin, the unwind routines are compiled without
24196 TARGET_ALTIVEC, and use save_world to save/restore the
24197 call-saved altivec registers when necessary. */
24198 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
24199 && ! TARGET_ALTIVEC
)
24202 /* First, find out if we use _any_ altivec registers. */
24203 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24204 if (df_regs_ever_live_p (i
))
24205 mask
|= ALTIVEC_REG_BIT (i
);
24210 /* Next, remove the argument registers from the set. These must
24211 be in the VRSAVE mask set by the caller, so we don't need to add
24212 them in again. More importantly, the mask we compute here is
24213 used to generate CLOBBERs in the set_vrsave insn, and we do not
24214 wish the argument registers to die. */
24215 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
24216 mask
&= ~ALTIVEC_REG_BIT (i
);
24218 /* Similarly, remove the return value from the set. */
24221 diddle_return_value (is_altivec_return_reg
, &yes
);
24223 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
24229 /* For a very restricted set of circumstances, we can cut down the
24230 size of prologues/epilogues by calling our own save/restore-the-world
24234 compute_save_world_info (rs6000_stack_t
*info
)
24236 info
->world_save_p
= 1;
24238 = (WORLD_SAVE_P (info
)
24239 && DEFAULT_ABI
== ABI_DARWIN
24240 && !cfun
->has_nonlocal_label
24241 && info
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
24242 && info
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
24243 && info
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
24244 && info
->cr_save_p
);
24246 /* This will not work in conjunction with sibcalls. Make sure there
24247 are none. (This check is expensive, but seldom executed.) */
24248 if (WORLD_SAVE_P (info
))
24251 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
24252 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
24254 info
->world_save_p
= 0;
24259 if (WORLD_SAVE_P (info
))
24261 /* Even if we're not touching VRsave, make sure there's room on the
24262 stack for it, if it looks like we're calling SAVE_WORLD, which
24263 will attempt to save it. */
24264 info
->vrsave_size
= 4;
24266 /* If we are going to save the world, we need to save the link register too. */
24267 info
->lr_save_p
= 1;
24269 /* "Save" the VRsave register too if we're saving the world. */
24270 if (info
->vrsave_mask
== 0)
24271 info
->vrsave_mask
= compute_vrsave_mask ();
24273 /* Because the Darwin register save/restore routines only handle
24274 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24276 gcc_assert (info
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
24277 && (info
->first_altivec_reg_save
24278 >= FIRST_SAVED_ALTIVEC_REGNO
));
24286 is_altivec_return_reg (rtx reg
, void *xyes
)
24288 bool *yes
= (bool *) xyes
;
24289 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
24294 /* Return whether REG is a global user reg or has been specifed by
24295 -ffixed-REG. We should not restore these, and so cannot use
24296 lmw or out-of-line restore functions if there are any. We also
24297 can't save them (well, emit frame notes for them), because frame
24298 unwinding during exception handling will restore saved registers. */
24301 fixed_reg_p (int reg
)
24303 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24304 backend sets it, overriding anything the user might have given. */
24305 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
24306 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
)
24307 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
24308 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
24311 return fixed_regs
[reg
];
24314 /* Determine the strategy for savings/restoring registers. */
24317 SAVE_MULTIPLE
= 0x1,
24318 SAVE_INLINE_GPRS
= 0x2,
24319 SAVE_INLINE_FPRS
= 0x4,
24320 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x8,
24321 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x10,
24322 SAVE_INLINE_VRS
= 0x20,
24323 REST_MULTIPLE
= 0x100,
24324 REST_INLINE_GPRS
= 0x200,
24325 REST_INLINE_FPRS
= 0x400,
24326 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x800,
24327 REST_INLINE_VRS
= 0x1000
24331 rs6000_savres_strategy (rs6000_stack_t
*info
,
24332 bool using_static_chain_p
)
24336 /* Select between in-line and out-of-line save and restore of regs.
24337 First, all the obvious cases where we don't use out-of-line. */
24338 if (crtl
->calls_eh_return
24339 || cfun
->machine
->ra_need_lr
)
24340 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
24341 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
24342 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
24344 if (info
->first_gp_reg_save
== 32)
24345 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24347 if (info
->first_fp_reg_save
== 64)
24348 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24350 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1)
24351 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24353 /* Define cutoff for using out-of-line functions to save registers. */
24354 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
24356 if (!optimize_size
)
24358 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24359 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24360 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24364 /* Prefer out-of-line restore if it will exit. */
24365 if (info
->first_fp_reg_save
> 61)
24366 strategy
|= SAVE_INLINE_FPRS
;
24367 if (info
->first_gp_reg_save
> 29)
24369 if (info
->first_fp_reg_save
== 64)
24370 strategy
|= SAVE_INLINE_GPRS
;
24372 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24374 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
24375 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24378 else if (DEFAULT_ABI
== ABI_DARWIN
)
24380 if (info
->first_fp_reg_save
> 60)
24381 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24382 if (info
->first_gp_reg_save
> 29)
24383 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24384 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24388 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
24389 if ((flag_shrink_wrap_separate
&& optimize_function_for_speed_p (cfun
))
24390 || info
->first_fp_reg_save
> 61)
24391 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
24392 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24393 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
24396 /* Don't bother to try to save things out-of-line if r11 is occupied
24397 by the static chain. It would require too much fiddling and the
24398 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24399 pointer on Darwin, and AIX uses r1 or r12. */
24400 if (using_static_chain_p
24401 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
24402 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
24404 | SAVE_INLINE_VRS
);
24406 /* Don't ever restore fixed regs. That means we can't use the
24407 out-of-line register restore functions if a fixed reg is in the
24408 range of regs restored. */
24409 if (!(strategy
& REST_INLINE_FPRS
))
24410 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
24413 strategy
|= REST_INLINE_FPRS
;
24417 /* We can only use the out-of-line routines to restore fprs if we've
24418 saved all the registers from first_fp_reg_save in the prologue.
24419 Otherwise, we risk loading garbage. Of course, if we have saved
24420 out-of-line then we know we haven't skipped any fprs. */
24421 if ((strategy
& SAVE_INLINE_FPRS
)
24422 && !(strategy
& REST_INLINE_FPRS
))
24423 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
24424 if (!save_reg_p (i
))
24426 strategy
|= REST_INLINE_FPRS
;
24430 /* Similarly, for altivec regs. */
24431 if (!(strategy
& REST_INLINE_VRS
))
24432 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
24435 strategy
|= REST_INLINE_VRS
;
24439 if ((strategy
& SAVE_INLINE_VRS
)
24440 && !(strategy
& REST_INLINE_VRS
))
24441 for (int i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
24442 if (!save_reg_p (i
))
24444 strategy
|= REST_INLINE_VRS
;
24448 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24449 saved is an out-of-line save or restore. Set up the value for
24450 the next test (excluding out-of-line gprs). */
24451 bool lr_save_p
= (info
->lr_save_p
24452 || !(strategy
& SAVE_INLINE_FPRS
)
24453 || !(strategy
& SAVE_INLINE_VRS
)
24454 || !(strategy
& REST_INLINE_FPRS
)
24455 || !(strategy
& REST_INLINE_VRS
));
24457 if (TARGET_MULTIPLE
24458 && !TARGET_POWERPC64
24459 && info
->first_gp_reg_save
< 31
24460 && !(flag_shrink_wrap
24461 && flag_shrink_wrap_separate
24462 && optimize_function_for_speed_p (cfun
)))
24465 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24466 if (save_reg_p (i
))
24470 /* Don't use store multiple if only one reg needs to be
24471 saved. This can occur for example when the ABI_V4 pic reg
24472 (r30) needs to be saved to make calls, but r31 is not
24474 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24477 /* Prefer store multiple for saves over out-of-line
24478 routines, since the store-multiple instruction will
24479 always be smaller. */
24480 strategy
|= SAVE_INLINE_GPRS
| SAVE_MULTIPLE
;
24482 /* The situation is more complicated with load multiple.
24483 We'd prefer to use the out-of-line routines for restores,
24484 since the "exit" out-of-line routines can handle the
24485 restore of LR and the frame teardown. However if doesn't
24486 make sense to use the out-of-line routine if that is the
24487 only reason we'd need to save LR, and we can't use the
24488 "exit" out-of-line gpr restore if we have saved some
24489 fprs; In those cases it is advantageous to use load
24490 multiple when available. */
24491 if (info
->first_fp_reg_save
!= 64 || !lr_save_p
)
24492 strategy
|= REST_INLINE_GPRS
| REST_MULTIPLE
;
24496 /* Using the "exit" out-of-line routine does not improve code size
24497 if using it would require lr to be saved and if only saving one
24499 else if (!lr_save_p
&& info
->first_gp_reg_save
> 29)
24500 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
24502 /* Don't ever restore fixed regs. */
24503 if ((strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
24504 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24505 if (fixed_reg_p (i
))
24507 strategy
|= REST_INLINE_GPRS
;
24508 strategy
&= ~REST_MULTIPLE
;
24512 /* We can only use load multiple or the out-of-line routines to
24513 restore gprs if we've saved all the registers from
24514 first_gp_reg_save. Otherwise, we risk loading garbage.
24515 Of course, if we have saved out-of-line or used stmw then we know
24516 we haven't skipped any gprs. */
24517 if ((strategy
& (SAVE_INLINE_GPRS
| SAVE_MULTIPLE
)) == SAVE_INLINE_GPRS
24518 && (strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
24519 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
24520 if (!save_reg_p (i
))
24522 strategy
|= REST_INLINE_GPRS
;
24523 strategy
&= ~REST_MULTIPLE
;
24527 if (TARGET_ELF
&& TARGET_64BIT
)
24529 if (!(strategy
& SAVE_INLINE_FPRS
))
24530 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
24531 else if (!(strategy
& SAVE_INLINE_GPRS
)
24532 && info
->first_fp_reg_save
== 64)
24533 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
24535 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
24536 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
24538 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
24539 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
24544 /* Calculate the stack information for the current function. This is
24545 complicated by having two separate calling sequences, the AIX calling
24546 sequence and the V.4 calling sequence.
24548 AIX (and Darwin/Mac OS X) stack frames look like:
24550 SP----> +---------------------------------------+
24551 | back chain to caller | 0 0
24552 +---------------------------------------+
24553 | saved CR | 4 8 (8-11)
24554 +---------------------------------------+
24556 +---------------------------------------+
24557 | reserved for compilers | 12 24
24558 +---------------------------------------+
24559 | reserved for binders | 16 32
24560 +---------------------------------------+
24561 | saved TOC pointer | 20 40
24562 +---------------------------------------+
24563 | Parameter save area (+padding*) (P) | 24 48
24564 +---------------------------------------+
24565 | Alloca space (A) | 24+P etc.
24566 +---------------------------------------+
24567 | Local variable space (L) | 24+P+A
24568 +---------------------------------------+
24569 | Float/int conversion temporary (X) | 24+P+A+L
24570 +---------------------------------------+
24571 | Save area for AltiVec registers (W) | 24+P+A+L+X
24572 +---------------------------------------+
24573 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24574 +---------------------------------------+
24575 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24576 +---------------------------------------+
24577 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24578 +---------------------------------------+
24579 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24580 +---------------------------------------+
24581 old SP->| back chain to caller's caller |
24582 +---------------------------------------+
24584 * If the alloca area is present, the parameter save area is
24585 padded so that the former starts 16-byte aligned.
24587 The required alignment for AIX configurations is two words (i.e., 8
24590 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24592 SP----> +---------------------------------------+
24593 | Back chain to caller | 0
24594 +---------------------------------------+
24595 | Save area for CR | 8
24596 +---------------------------------------+
24598 +---------------------------------------+
24599 | Saved TOC pointer | 24
24600 +---------------------------------------+
24601 | Parameter save area (+padding*) (P) | 32
24602 +---------------------------------------+
24603 | Alloca space (A) | 32+P
24604 +---------------------------------------+
24605 | Local variable space (L) | 32+P+A
24606 +---------------------------------------+
24607 | Save area for AltiVec registers (W) | 32+P+A+L
24608 +---------------------------------------+
24609 | AltiVec alignment padding (Y) | 32+P+A+L+W
24610 +---------------------------------------+
24611 | Save area for GP registers (G) | 32+P+A+L+W+Y
24612 +---------------------------------------+
24613 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24614 +---------------------------------------+
24615 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24616 +---------------------------------------+
24618 * If the alloca area is present, the parameter save area is
24619 padded so that the former starts 16-byte aligned.
24621 V.4 stack frames look like:
24623 SP----> +---------------------------------------+
24624 | back chain to caller | 0
24625 +---------------------------------------+
24626 | caller's saved LR | 4
24627 +---------------------------------------+
24628 | Parameter save area (+padding*) (P) | 8
24629 +---------------------------------------+
24630 | Alloca space (A) | 8+P
24631 +---------------------------------------+
24632 | Varargs save area (V) | 8+P+A
24633 +---------------------------------------+
24634 | Local variable space (L) | 8+P+A+V
24635 +---------------------------------------+
24636 | Float/int conversion temporary (X) | 8+P+A+V+L
24637 +---------------------------------------+
24638 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24639 +---------------------------------------+
24640 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24641 +---------------------------------------+
24642 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24643 +---------------------------------------+
24644 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24645 +---------------------------------------+
24646 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24647 +---------------------------------------+
24648 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24649 +---------------------------------------+
24650 old SP->| back chain to caller's caller |
24651 +---------------------------------------+
24653 * If the alloca area is present and the required alignment is
24654 16 bytes, the parameter save area is padded so that the
24655 alloca area starts 16-byte aligned.
24657 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24658 given. (But note below and in sysv4.h that we require only 8 and
24659 may round up the size of our stack frame anyways. The historical
24660 reason is early versions of powerpc-linux which didn't properly
24661 align the stack at program startup. A happy side-effect is that
24662 -mno-eabi libraries can be used with -meabi programs.)
24664 The EABI configuration defaults to the V.4 layout. However,
24665 the stack alignment requirements may differ. If -mno-eabi is not
24666 given, the required stack alignment is 8 bytes; if -mno-eabi is
24667 given, the required alignment is 16 bytes. (But see V.4 comment
24670 #ifndef ABI_STACK_BOUNDARY
24671 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24674 static rs6000_stack_t
*
24675 rs6000_stack_info (void)
24677 /* We should never be called for thunks, we are not set up for that. */
24678 gcc_assert (!cfun
->is_thunk
);
24680 rs6000_stack_t
*info
= &stack_info
;
24681 int reg_size
= TARGET_32BIT
? 4 : 8;
24686 HOST_WIDE_INT non_fixed_size
;
24687 bool using_static_chain_p
;
24689 if (reload_completed
&& info
->reload_completed
)
24692 memset (info
, 0, sizeof (*info
));
24693 info
->reload_completed
= reload_completed
;
24695 /* Select which calling sequence. */
24696 info
->abi
= DEFAULT_ABI
;
24698 /* Calculate which registers need to be saved & save area size. */
24699 info
->first_gp_reg_save
= first_reg_to_save ();
24700 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24701 even if it currently looks like we won't. Reload may need it to
24702 get at a constant; if so, it will have already created a constant
24703 pool entry for it. */
24704 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
24705 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
24706 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
24707 && crtl
->uses_const_pool
24708 && info
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
24709 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
24711 first_gp
= info
->first_gp_reg_save
;
24713 info
->gp_size
= reg_size
* (32 - first_gp
);
24715 info
->first_fp_reg_save
= first_fp_reg_to_save ();
24716 info
->fp_size
= 8 * (64 - info
->first_fp_reg_save
);
24718 info
->first_altivec_reg_save
= first_altivec_reg_to_save ();
24719 info
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
24720 - info
->first_altivec_reg_save
);
24722 /* Does this function call anything? */
24723 info
->calls_p
= (!crtl
->is_leaf
|| cfun
->machine
->ra_needs_full_frame
);
24725 /* Determine if we need to save the condition code registers. */
24726 if (save_reg_p (CR2_REGNO
)
24727 || save_reg_p (CR3_REGNO
)
24728 || save_reg_p (CR4_REGNO
))
24730 info
->cr_save_p
= 1;
24731 if (DEFAULT_ABI
== ABI_V4
)
24732 info
->cr_size
= reg_size
;
24735 /* If the current function calls __builtin_eh_return, then we need
24736 to allocate stack space for registers that will hold data for
24737 the exception handler. */
24738 if (crtl
->calls_eh_return
)
24741 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
24744 ehrd_size
= i
* UNITS_PER_WORD
;
24749 /* In the ELFv2 ABI, we also need to allocate space for separate
24750 CR field save areas if the function calls __builtin_eh_return. */
24751 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24753 /* This hard-codes that we have three call-saved CR fields. */
24754 ehcr_size
= 3 * reg_size
;
24755 /* We do *not* use the regular CR save mechanism. */
24756 info
->cr_save_p
= 0;
24761 /* Determine various sizes. */
24762 info
->reg_size
= reg_size
;
24763 info
->fixed_size
= RS6000_SAVE_AREA
;
24764 info
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
24765 if (cfun
->calls_alloca
)
24767 RS6000_ALIGN (crtl
->outgoing_args_size
+ info
->fixed_size
,
24768 STACK_BOUNDARY
/ BITS_PER_UNIT
) - info
->fixed_size
;
24770 info
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
24771 TARGET_ALTIVEC
? 16 : 8);
24772 if (FRAME_GROWS_DOWNWARD
)
24774 += RS6000_ALIGN (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
,
24775 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
24776 - (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
);
24778 if (TARGET_ALTIVEC_ABI
)
24779 info
->vrsave_mask
= compute_vrsave_mask ();
24781 if (TARGET_ALTIVEC_VRSAVE
&& info
->vrsave_mask
)
24782 info
->vrsave_size
= 4;
24784 compute_save_world_info (info
);
24786 /* Calculate the offsets. */
24787 switch (DEFAULT_ABI
)
24791 gcc_unreachable ();
24796 info
->fp_save_offset
= -info
->fp_size
;
24797 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24799 if (TARGET_ALTIVEC_ABI
)
24801 info
->vrsave_save_offset
= info
->gp_save_offset
- info
->vrsave_size
;
24803 /* Align stack so vector save area is on a quadword boundary.
24804 The padding goes above the vectors. */
24805 if (info
->altivec_size
!= 0)
24806 info
->altivec_padding_size
= info
->vrsave_save_offset
& 0xF;
24808 info
->altivec_save_offset
= info
->vrsave_save_offset
24809 - info
->altivec_padding_size
24810 - info
->altivec_size
;
24811 gcc_assert (info
->altivec_size
== 0
24812 || info
->altivec_save_offset
% 16 == 0);
24814 /* Adjust for AltiVec case. */
24815 info
->ehrd_offset
= info
->altivec_save_offset
- ehrd_size
;
24818 info
->ehrd_offset
= info
->gp_save_offset
- ehrd_size
;
24820 info
->ehcr_offset
= info
->ehrd_offset
- ehcr_size
;
24821 info
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
24822 info
->lr_save_offset
= 2*reg_size
;
24826 info
->fp_save_offset
= -info
->fp_size
;
24827 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
24828 info
->cr_save_offset
= info
->gp_save_offset
- info
->cr_size
;
24830 if (TARGET_ALTIVEC_ABI
)
24832 info
->vrsave_save_offset
= info
->cr_save_offset
- info
->vrsave_size
;
24834 /* Align stack so vector save area is on a quadword boundary. */
24835 if (info
->altivec_size
!= 0)
24836 info
->altivec_padding_size
= 16 - (-info
->vrsave_save_offset
% 16);
24838 info
->altivec_save_offset
= info
->vrsave_save_offset
24839 - info
->altivec_padding_size
24840 - info
->altivec_size
;
24842 /* Adjust for AltiVec case. */
24843 info
->ehrd_offset
= info
->altivec_save_offset
;
24846 info
->ehrd_offset
= info
->cr_save_offset
;
24848 info
->ehrd_offset
-= ehrd_size
;
24849 info
->lr_save_offset
= reg_size
;
24852 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
24853 info
->save_size
= RS6000_ALIGN (info
->fp_size
24855 + info
->altivec_size
24856 + info
->altivec_padding_size
24860 + info
->vrsave_size
,
24863 non_fixed_size
= info
->vars_size
+ info
->parm_size
+ info
->save_size
;
24865 info
->total_size
= RS6000_ALIGN (non_fixed_size
+ info
->fixed_size
,
24866 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
24868 /* Determine if we need to save the link register. */
24870 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24872 && !TARGET_PROFILE_KERNEL
)
24873 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
24874 #ifdef TARGET_RELOCATABLE
24875 || (DEFAULT_ABI
== ABI_V4
24876 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
24877 && !constant_pool_empty_p ())
24879 || rs6000_ra_ever_killed ())
24880 info
->lr_save_p
= 1;
24882 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
24883 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
24884 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
24885 info
->savres_strategy
= rs6000_savres_strategy (info
, using_static_chain_p
);
24887 if (!(info
->savres_strategy
& SAVE_INLINE_GPRS
)
24888 || !(info
->savres_strategy
& SAVE_INLINE_FPRS
)
24889 || !(info
->savres_strategy
& SAVE_INLINE_VRS
)
24890 || !(info
->savres_strategy
& REST_INLINE_GPRS
)
24891 || !(info
->savres_strategy
& REST_INLINE_FPRS
)
24892 || !(info
->savres_strategy
& REST_INLINE_VRS
))
24893 info
->lr_save_p
= 1;
24895 if (info
->lr_save_p
)
24896 df_set_regs_ever_live (LR_REGNO
, true);
24898 /* Determine if we need to allocate any stack frame:
24900 For AIX we need to push the stack if a frame pointer is needed
24901 (because the stack might be dynamically adjusted), if we are
24902 debugging, if we make calls, or if the sum of fp_save, gp_save,
24903 and local variables are more than the space needed to save all
24904 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24905 + 18*8 = 288 (GPR13 reserved).
24907 For V.4 we don't have the stack cushion that AIX uses, but assume
24908 that the debugger can handle stackless frames. */
24913 else if (DEFAULT_ABI
== ABI_V4
)
24914 info
->push_p
= non_fixed_size
!= 0;
24916 else if (frame_pointer_needed
)
24919 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
24923 info
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
24929 debug_stack_info (rs6000_stack_t
*info
)
24931 const char *abi_string
;
24934 info
= rs6000_stack_info ();
24936 fprintf (stderr
, "\nStack information for function %s:\n",
24937 ((current_function_decl
&& DECL_NAME (current_function_decl
))
24938 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
24943 default: abi_string
= "Unknown"; break;
24944 case ABI_NONE
: abi_string
= "NONE"; break;
24945 case ABI_AIX
: abi_string
= "AIX"; break;
24946 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
24947 case ABI_DARWIN
: abi_string
= "Darwin"; break;
24948 case ABI_V4
: abi_string
= "V.4"; break;
24951 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
24953 if (TARGET_ALTIVEC_ABI
)
24954 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
24956 if (info
->first_gp_reg_save
!= 32)
24957 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
24959 if (info
->first_fp_reg_save
!= 64)
24960 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
24962 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
24963 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
24964 info
->first_altivec_reg_save
);
24966 if (info
->lr_save_p
)
24967 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
24969 if (info
->cr_save_p
)
24970 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
24972 if (info
->vrsave_mask
)
24973 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
24976 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
24979 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
24982 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
24985 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
24987 if (info
->altivec_size
)
24988 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
24989 info
->altivec_save_offset
);
24991 if (info
->vrsave_size
)
24992 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
24993 info
->vrsave_save_offset
);
24995 if (info
->lr_save_p
)
24996 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
24998 if (info
->cr_save_p
)
24999 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
25001 if (info
->varargs_save_offset
)
25002 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
25004 if (info
->total_size
)
25005 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
25008 if (info
->vars_size
)
25009 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
25012 if (info
->parm_size
)
25013 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
25015 if (info
->fixed_size
)
25016 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
25019 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
25022 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
25024 if (info
->altivec_size
)
25025 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
25027 if (info
->vrsave_size
)
25028 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
25030 if (info
->altivec_padding_size
)
25031 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
25032 info
->altivec_padding_size
);
25035 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
25037 if (info
->save_size
)
25038 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
25040 if (info
->reg_size
!= 4)
25041 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
25043 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
25045 fprintf (stderr
, "\n");
25049 rs6000_return_addr (int count
, rtx frame
)
25051 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
25052 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
25054 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
25056 cfun
->machine
->ra_needs_full_frame
= 1;
25059 /* FRAME is set to frame_pointer_rtx by the generic code, but that
25060 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
25061 frame
= stack_pointer_rtx
;
25062 rtx prev_frame_addr
= memory_address (Pmode
, frame
);
25063 rtx prev_frame
= copy_to_reg (gen_rtx_MEM (Pmode
, prev_frame_addr
));
25064 rtx lr_save_off
= plus_constant (Pmode
,
25065 prev_frame
, RETURN_ADDRESS_OFFSET
);
25066 rtx lr_save_addr
= memory_address (Pmode
, lr_save_off
);
25067 return gen_rtx_MEM (Pmode
, lr_save_addr
);
25070 cfun
->machine
->ra_need_lr
= 1;
25071 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
25074 /* Say whether a function is a candidate for sibcall handling or not. */
25077 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
25081 /* The sibcall epilogue may clobber the static chain register.
25082 ??? We could work harder and avoid that, but it's probably
25083 not worth the hassle in practice. */
25084 if (CALL_EXPR_STATIC_CHAIN (exp
))
25088 fntype
= TREE_TYPE (decl
);
25090 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
25092 /* We can't do it if the called function has more vector parameters
25093 than the current function; there's nowhere to put the VRsave code. */
25094 if (TARGET_ALTIVEC_ABI
25095 && TARGET_ALTIVEC_VRSAVE
25096 && !(decl
&& decl
== current_function_decl
))
25098 function_args_iterator args_iter
;
25102 /* Functions with vector parameters are required to have a
25103 prototype, so the argument type info must be available
25105 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
25106 if (TREE_CODE (type
) == VECTOR_TYPE
25107 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
25110 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
25111 if (TREE_CODE (type
) == VECTOR_TYPE
25112 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
25119 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
25120 functions, because the callee may have a different TOC pointer to
25121 the caller and there's no way to ensure we restore the TOC when
25122 we return. With the secure-plt SYSV ABI we can't make non-local
25123 calls when -fpic/PIC because the plt call stubs use r30. */
25124 if (DEFAULT_ABI
== ABI_DARWIN
25125 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25127 && !DECL_EXTERNAL (decl
)
25128 && !DECL_WEAK (decl
)
25129 && (*targetm
.binds_local_p
) (decl
))
25130 || (DEFAULT_ABI
== ABI_V4
25131 && (!TARGET_SECURE_PLT
25134 && (*targetm
.binds_local_p
) (decl
)))))
25136 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
25138 if (!lookup_attribute ("longcall", attr_list
)
25139 || lookup_attribute ("shortcall", attr_list
))
25147 rs6000_ra_ever_killed (void)
25153 if (cfun
->is_thunk
)
25156 if (cfun
->machine
->lr_save_state
)
25157 return cfun
->machine
->lr_save_state
- 1;
25159 /* regs_ever_live has LR marked as used if any sibcalls are present,
25160 but this should not force saving and restoring in the
25161 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
25162 clobbers LR, so that is inappropriate. */
25164 /* Also, the prologue can generate a store into LR that
25165 doesn't really count, like this:
25168 bcl to set PIC register
25172 When we're called from the epilogue, we need to avoid counting
25173 this as a store. */
25175 push_topmost_sequence ();
25176 top
= get_insns ();
25177 pop_topmost_sequence ();
25178 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
25180 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
25186 if (!SIBLING_CALL_P (insn
))
25189 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
25191 else if (set_of (reg
, insn
) != NULL_RTX
25192 && !prologue_epilogue_contains (insn
))
25199 /* Emit instructions needed to load the TOC register.
25200 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
25201 a constant pool; or for SVR4 -fpic. */
25204 rs6000_emit_load_toc_table (int fromprolog
)
25207 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
25209 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
25212 rtx lab
, tmp1
, tmp2
, got
;
25214 lab
= gen_label_rtx ();
25215 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
25216 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25219 got
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25223 got
= rs6000_got_sym ();
25224 tmp1
= tmp2
= dest
;
25227 tmp1
= gen_reg_rtx (Pmode
);
25228 tmp2
= gen_reg_rtx (Pmode
);
25230 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
25231 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
25232 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
25233 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
25235 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
25237 emit_insn (gen_load_toc_v4_pic_si ());
25238 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25240 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
25243 rtx temp0
= (fromprolog
25244 ? gen_rtx_REG (Pmode
, 0)
25245 : gen_reg_rtx (Pmode
));
25251 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
25252 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25254 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
25255 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
25257 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
25258 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25259 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
25265 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25267 lab
= gen_label_rtx ();
25268 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
25269 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
25270 if (TARGET_LINK_STACK
)
25271 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
25272 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
25274 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
25276 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
25278 /* This is for AIX code running in non-PIC ELF32. */
25279 rtx realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
25282 emit_insn (gen_elf_high (dest
, realsym
));
25283 emit_insn (gen_elf_low (dest
, dest
, realsym
));
25287 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
25290 emit_insn (gen_load_toc_aix_si (dest
));
25292 emit_insn (gen_load_toc_aix_di (dest
));
25296 /* Emit instructions to restore the link register after determining where
25297 its value has been stored. */
25300 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
25302 rs6000_stack_t
*info
= rs6000_stack_info ();
25305 operands
[0] = source
;
25306 operands
[1] = scratch
;
25308 if (info
->lr_save_p
)
25310 rtx frame_rtx
= stack_pointer_rtx
;
25311 HOST_WIDE_INT sp_offset
= 0;
25314 if (frame_pointer_needed
25315 || cfun
->calls_alloca
25316 || info
->total_size
> 32767)
25318 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
25319 emit_move_insn (operands
[1], tmp
);
25320 frame_rtx
= operands
[1];
25322 else if (info
->push_p
)
25323 sp_offset
= info
->total_size
;
25325 tmp
= plus_constant (Pmode
, frame_rtx
,
25326 info
->lr_save_offset
+ sp_offset
);
25327 tmp
= gen_frame_mem (Pmode
, tmp
);
25328 emit_move_insn (tmp
, operands
[0]);
25331 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
25333 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25334 state of lr_save_p so any change from here on would be a bug. In
25335 particular, stop rs6000_ra_ever_killed from considering the SET
25336 of lr we may have added just above. */
25337 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
25340 static GTY(()) alias_set_type set
= -1;
25343 get_TOC_alias_set (void)
25346 set
= new_alias_set ();
25350 /* This returns nonzero if the current function uses the TOC. This is
25351 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25352 is generated by the ABI_V4 load_toc_* patterns.
25353 Return 2 instead of 1 if the load_toc_* pattern is in the function
25354 partition that doesn't start the function. */
25362 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
25366 rtx pat
= PATTERN (insn
);
25369 if (GET_CODE (pat
) == PARALLEL
)
25370 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
25372 rtx sub
= XVECEXP (pat
, 0, i
);
25373 if (GET_CODE (sub
) == USE
)
25375 sub
= XEXP (sub
, 0);
25376 if (GET_CODE (sub
) == UNSPEC
25377 && XINT (sub
, 1) == UNSPEC_TOC
)
25382 else if (crtl
->has_bb_partition
25384 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
25392 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
25394 rtx tocrel
, tocreg
, hi
;
25396 if (TARGET_DEBUG_ADDR
)
25398 if (SYMBOL_REF_P (symbol
))
25399 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25403 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
25404 GET_RTX_NAME (GET_CODE (symbol
)));
25405 debug_rtx (symbol
);
25409 if (!can_create_pseudo_p ())
25410 df_set_regs_ever_live (TOC_REGISTER
, true);
25412 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
25413 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
25414 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
25417 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
25418 if (largetoc_reg
!= NULL
)
25420 emit_move_insn (largetoc_reg
, hi
);
25423 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
25426 /* Issue assembly directives that create a reference to the given DWARF
25427 FRAME_TABLE_LABEL from the current function section. */
25429 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
25431 fprintf (asm_out_file
, "\t.ref %s\n",
25432 (* targetm
.strip_name_encoding
) (frame_table_label
));
25435 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25436 and the change to the stack pointer. */
25439 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
25446 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
25447 if (hard_frame_needed
)
25448 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
25449 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
25450 || (hard_frame_needed
25451 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
25454 p
= rtvec_alloc (i
);
25457 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
25458 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
25461 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
25464 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25465 and set the appropriate attributes for the generated insn. Return the
25466 first insn which adjusts the stack pointer or the last insn before
25467 the stack adjustment loop.
25469 SIZE_INT is used to create the CFI note for the allocation.
25471 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25472 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25474 ORIG_SP contains the backchain value that must be stored at *sp. */
25477 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int
, rtx orig_sp
)
25481 rtx size_rtx
= GEN_INT (-size_int
);
25482 if (size_int
> 32767)
25484 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
25485 /* Need a note here so that try_split doesn't get confused. */
25486 if (get_last_insn () == NULL_RTX
)
25487 emit_note (NOTE_INSN_DELETED
);
25488 insn
= emit_move_insn (tmp_reg
, size_rtx
);
25489 try_split (PATTERN (insn
), insn
, 0);
25490 size_rtx
= tmp_reg
;
25494 insn
= emit_insn (gen_movsi_update_stack (stack_pointer_rtx
,
25499 insn
= emit_insn (gen_movdi_update_stack (stack_pointer_rtx
,
25503 rtx par
= PATTERN (insn
);
25504 gcc_assert (GET_CODE (par
) == PARALLEL
);
25505 rtx set
= XVECEXP (par
, 0, 0);
25506 gcc_assert (GET_CODE (set
) == SET
);
25507 rtx mem
= SET_DEST (set
);
25508 gcc_assert (MEM_P (mem
));
25509 MEM_NOTRAP_P (mem
) = 1;
25510 set_mem_alias_set (mem
, get_frame_alias_set ());
25512 RTX_FRAME_RELATED_P (insn
) = 1;
25513 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25514 gen_rtx_SET (stack_pointer_rtx
,
25515 gen_rtx_PLUS (Pmode
,
25517 GEN_INT (-size_int
))));
25519 /* Emit a blockage to ensure the allocation/probing insns are
25520 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25521 note for similar reasons. */
25522 if (flag_stack_clash_protection
)
25524 add_reg_note (insn
, REG_STACK_CHECK
, const0_rtx
);
25525 emit_insn (gen_blockage ());
25531 static HOST_WIDE_INT
25532 get_stack_clash_protection_probe_interval (void)
25534 return (HOST_WIDE_INT_1U
25535 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
));
25538 static HOST_WIDE_INT
25539 get_stack_clash_protection_guard_size (void)
25541 return (HOST_WIDE_INT_1U
25542 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE
));
25545 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25546 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25548 COPY_REG, if non-null, should contain a copy of the original
25549 stack pointer at exit from this function.
25551 This is subtly different than the Ada probing in that it tries hard to
25552 prevent attacks that jump the stack guard. Thus it is never allowed to
25553 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25554 space without a suitable probe. */
25556 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size
,
25559 rtx orig_sp
= copy_reg
;
25561 HOST_WIDE_INT probe_interval
= get_stack_clash_protection_probe_interval ();
25563 /* Round the size down to a multiple of PROBE_INTERVAL. */
25564 HOST_WIDE_INT rounded_size
= ROUND_DOWN (orig_size
, probe_interval
);
25566 /* If explicitly requested,
25567 or the rounded size is not the same as the original size
25568 or the the rounded size is greater than a page,
25569 then we will need a copy of the original stack pointer. */
25570 if (rounded_size
!= orig_size
25571 || rounded_size
> probe_interval
25574 /* If the caller did not request a copy of the incoming stack
25575 pointer, then we use r0 to hold the copy. */
25577 orig_sp
= gen_rtx_REG (Pmode
, 0);
25578 emit_move_insn (orig_sp
, stack_pointer_rtx
);
25581 /* There's three cases here.
25583 One is a single probe which is the most common and most efficiently
25584 implemented as it does not have to have a copy of the original
25585 stack pointer if there are no residuals.
25587 Second is unrolled allocation/probes which we use if there's just
25588 a few of them. It needs to save the original stack pointer into a
25589 temporary for use as a source register in the allocation/probe.
25591 Last is a loop. This is the most uncommon case and least efficient. */
25592 rtx_insn
*retval
= NULL
;
25593 if (rounded_size
== probe_interval
)
25595 retval
= rs6000_emit_allocate_stack_1 (probe_interval
, stack_pointer_rtx
);
25597 dump_stack_clash_frame_info (PROBE_INLINE
, rounded_size
!= orig_size
);
25599 else if (rounded_size
<= 8 * probe_interval
)
25601 /* The ABI requires using the store with update insns to allocate
25602 space and store the backchain into the stack
25604 So we save the current stack pointer into a temporary, then
25605 emit the store-with-update insns to store the saved stack pointer
25606 into the right location in each new page. */
25607 for (int i
= 0; i
< rounded_size
; i
+= probe_interval
)
25610 = rs6000_emit_allocate_stack_1 (probe_interval
, orig_sp
);
25612 /* Save the first stack adjustment in RETVAL. */
25617 dump_stack_clash_frame_info (PROBE_INLINE
, rounded_size
!= orig_size
);
25621 /* Compute the ending address. */
25623 = copy_reg
? gen_rtx_REG (Pmode
, 0) : gen_rtx_REG (Pmode
, 12);
25624 rtx rs
= GEN_INT (-rounded_size
);
25626 if (add_operand (rs
, Pmode
))
25627 insn
= emit_insn (gen_add3_insn (end_addr
, stack_pointer_rtx
, rs
));
25630 emit_move_insn (end_addr
, GEN_INT (-rounded_size
));
25631 insn
= emit_insn (gen_add3_insn (end_addr
, end_addr
,
25632 stack_pointer_rtx
));
25633 /* Describe the effect of INSN to the CFI engine. */
25634 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25635 gen_rtx_SET (end_addr
,
25636 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
25639 RTX_FRAME_RELATED_P (insn
) = 1;
25641 /* Emit the loop. */
25643 retval
= emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx
,
25644 stack_pointer_rtx
, orig_sp
,
25647 retval
= emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx
,
25648 stack_pointer_rtx
, orig_sp
,
25650 RTX_FRAME_RELATED_P (retval
) = 1;
25651 /* Describe the effect of INSN to the CFI engine. */
25652 add_reg_note (retval
, REG_FRAME_RELATED_EXPR
,
25653 gen_rtx_SET (stack_pointer_rtx
, end_addr
));
25655 /* Emit a blockage to ensure the allocation/probing insns are
25656 not optimized, combined, removed, etc. Other cases handle this
25657 within their call to rs6000_emit_allocate_stack_1. */
25658 emit_insn (gen_blockage ());
25660 dump_stack_clash_frame_info (PROBE_LOOP
, rounded_size
!= orig_size
);
25663 if (orig_size
!= rounded_size
)
25665 /* Allocate (and implicitly probe) any residual space. */
25666 HOST_WIDE_INT residual
= orig_size
- rounded_size
;
25668 rtx_insn
*insn
= rs6000_emit_allocate_stack_1 (residual
, orig_sp
);
25670 /* If the residual was the only allocation, then we can return the
25671 allocating insn. */
25679 /* Emit the correct code for allocating stack space, as insns.
25680 If COPY_REG, make sure a copy of the old frame is left there.
25681 The generated code may use hard register 0 as a temporary. */
25684 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
25687 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
25688 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
25689 rtx todec
= gen_int_mode (-size
, Pmode
);
25691 if (INTVAL (todec
) != -size
)
25693 warning (0, "stack frame too large");
25694 emit_insn (gen_trap ());
25698 if (crtl
->limit_stack
)
25700 if (REG_P (stack_limit_rtx
)
25701 && REGNO (stack_limit_rtx
) > 1
25702 && REGNO (stack_limit_rtx
) <= 31)
25705 = gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
));
25708 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
, const0_rtx
));
25710 else if (SYMBOL_REF_P (stack_limit_rtx
)
25712 && DEFAULT_ABI
== ABI_V4
25715 rtx toload
= gen_rtx_CONST (VOIDmode
,
25716 gen_rtx_PLUS (Pmode
,
25720 emit_insn (gen_elf_high (tmp_reg
, toload
));
25721 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
25722 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
25726 warning (0, "stack limit expression is not supported");
25729 if (flag_stack_clash_protection
)
25731 if (size
< get_stack_clash_protection_guard_size ())
25732 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME
, true);
25735 rtx_insn
*insn
= rs6000_emit_probe_stack_range_stack_clash (size
,
25738 /* If we asked for a copy with an offset, then we still need add in
25740 if (copy_reg
&& copy_off
)
25741 emit_insn (gen_add3_insn (copy_reg
, copy_reg
, GEN_INT (copy_off
)));
25749 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
25751 emit_move_insn (copy_reg
, stack_reg
);
25754 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25755 it now and set the alias set/attributes. The above gen_*_update
25756 calls will generate a PARALLEL with the MEM set being the first
25758 insn
= rs6000_emit_allocate_stack_1 (size
, stack_reg
);
25762 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25764 #if PROBE_INTERVAL > 32768
25765 #error Cannot use indexed addressing mode for stack probing
25768 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25769 inclusive. These are offsets from the current stack pointer. */
25772 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
25774 /* See if we have a constant small number of probes to generate. If so,
25775 that's the easy case. */
25776 if (first
+ size
<= 32768)
25780 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25781 it exceeds SIZE. If only one probe is needed, this will not
25782 generate any code. Then probe at FIRST + SIZE. */
25783 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
25784 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25787 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
25791 /* Otherwise, do the same as above, but in a loop. Note that we must be
25792 extra careful with variables wrapping around because we might be at
25793 the very top (or the very bottom) of the address space and we have
25794 to be able to handle this case properly; in particular, we use an
25795 equality test for the loop condition. */
25798 HOST_WIDE_INT rounded_size
;
25799 rtx r12
= gen_rtx_REG (Pmode
, 12);
25800 rtx r0
= gen_rtx_REG (Pmode
, 0);
25802 /* Sanity check for the addressing mode we're going to use. */
25803 gcc_assert (first
<= 32768);
25805 /* Step 1: round SIZE to the previous multiple of the interval. */
25807 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
25810 /* Step 2: compute initial and final value of the loop counter. */
25812 /* TEST_ADDR = SP + FIRST. */
25813 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
25816 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25817 if (rounded_size
> 32768)
25819 emit_move_insn (r0
, GEN_INT (-rounded_size
));
25820 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
25823 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
25827 /* Step 3: the loop
25831 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25834 while (TEST_ADDR != LAST_ADDR)
25836 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25837 until it is equal to ROUNDED_SIZE. */
25840 emit_insn (gen_probe_stack_rangedi (r12
, r12
, stack_pointer_rtx
, r0
));
25842 emit_insn (gen_probe_stack_rangesi (r12
, r12
, stack_pointer_rtx
, r0
));
25845 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25846 that SIZE is equal to ROUNDED_SIZE. */
25848 if (size
!= rounded_size
)
25849 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
25853 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25854 addresses, not offsets. */
25856 static const char *
25857 output_probe_stack_range_1 (rtx reg1
, rtx reg2
)
25859 static int labelno
= 0;
25863 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
25866 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
25868 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25870 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
25871 output_asm_insn ("addi %0,%0,%1", xops
);
25873 /* Probe at TEST_ADDR. */
25874 xops
[1] = gen_rtx_REG (Pmode
, 0);
25875 output_asm_insn ("stw %1,0(%0)", xops
);
25877 /* Test if TEST_ADDR == LAST_ADDR. */
25880 output_asm_insn ("cmpd 0,%0,%1", xops
);
25882 output_asm_insn ("cmpw 0,%0,%1", xops
);
25885 fputs ("\tbne 0,", asm_out_file
);
25886 assemble_name_raw (asm_out_file
, loop_lab
);
25887 fputc ('\n', asm_out_file
);
25892 /* This function is called when rs6000_frame_related is processing
25893 SETs within a PARALLEL, and returns whether the REGNO save ought to
25894 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25895 for out-of-line register save functions, store multiple, and the
25896 Darwin world_save. They may contain registers that don't really
25900 interesting_frame_related_regno (unsigned int regno
)
25902 /* Saves apparently of r0 are actually saving LR. It doesn't make
25903 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25904 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25905 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25906 as frame related. */
25909 /* If we see CR2 then we are here on a Darwin world save. Saves of
25910 CR2 signify the whole CR is being saved. This is a long-standing
25911 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25912 that CR needs to be saved. */
25913 if (regno
== CR2_REGNO
)
25915 /* Omit frame info for any user-defined global regs. If frame info
25916 is supplied for them, frame unwinding will restore a user reg.
25917 Also omit frame info for any reg we don't need to save, as that
25918 bloats frame info and can cause problems with shrink wrapping.
25919 Since global regs won't be seen as needing to be saved, both of
25920 these conditions are covered by save_reg_p. */
25921 return save_reg_p (regno
);
25924 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25925 addresses, not offsets.
25927 REG2 contains the backchain that must be stored into *sp at each allocation.
25929 This is subtly different than the Ada probing above in that it tries hard
25930 to prevent attacks that jump the stack guard. Thus, it is never allowed
25931 to allocate more than PROBE_INTERVAL bytes of stack space without a
25934 static const char *
25935 output_probe_stack_range_stack_clash (rtx reg1
, rtx reg2
, rtx reg3
)
25937 static int labelno
= 0;
25941 HOST_WIDE_INT probe_interval
= get_stack_clash_protection_probe_interval ();
25943 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
25945 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
25947 /* This allocates and probes. */
25950 xops
[2] = GEN_INT (-probe_interval
);
25952 output_asm_insn ("stdu %1,%2(%0)", xops
);
25954 output_asm_insn ("stwu %1,%2(%0)", xops
);
25956 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25960 output_asm_insn ("cmpd 0,%0,%1", xops
);
25962 output_asm_insn ("cmpw 0,%0,%1", xops
);
25964 fputs ("\tbne 0,", asm_out_file
);
25965 assemble_name_raw (asm_out_file
, loop_lab
);
25966 fputc ('\n', asm_out_file
);
25971 /* Wrapper around the output_probe_stack_range routines. */
25973 output_probe_stack_range (rtx reg1
, rtx reg2
, rtx reg3
)
25975 if (flag_stack_clash_protection
)
25976 return output_probe_stack_range_stack_clash (reg1
, reg2
, reg3
);
25978 return output_probe_stack_range_1 (reg1
, reg3
);
25981 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25982 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25983 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25984 deduce these equivalences by itself so it wasn't necessary to hold
25985 its hand so much. Don't be tempted to always supply d2_f_d_e with
25986 the actual cfa register, ie. r31 when we are using a hard frame
25987 pointer. That fails when saving regs off r1, and sched moves the
25988 r31 setup past the reg saves. */
25991 rs6000_frame_related (rtx_insn
*insn
, rtx reg
, HOST_WIDE_INT val
,
25992 rtx reg2
, rtx repl2
)
25996 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
25998 gcc_checking_assert (val
== 0);
26002 repl
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
26005 rtx pat
= PATTERN (insn
);
26006 if (!repl
&& !reg2
)
26008 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
26009 if (GET_CODE (pat
) == PARALLEL
)
26010 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
26011 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
26013 rtx set
= XVECEXP (pat
, 0, i
);
26015 if (!REG_P (SET_SRC (set
))
26016 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
26017 RTX_FRAME_RELATED_P (set
) = 1;
26019 RTX_FRAME_RELATED_P (insn
) = 1;
26023 /* We expect that 'pat' is either a SET or a PARALLEL containing
26024 SETs (and possibly other stuff). In a PARALLEL, all the SETs
26025 are important so they all have to be marked RTX_FRAME_RELATED_P.
26026 Call simplify_replace_rtx on the SETs rather than the whole insn
26027 so as to leave the other stuff alone (for example USE of r12). */
26029 set_used_flags (pat
);
26030 if (GET_CODE (pat
) == SET
)
26033 pat
= simplify_replace_rtx (pat
, reg
, repl
);
26035 pat
= simplify_replace_rtx (pat
, reg2
, repl2
);
26037 else if (GET_CODE (pat
) == PARALLEL
)
26039 pat
= shallow_copy_rtx (pat
);
26040 XVEC (pat
, 0) = shallow_copy_rtvec (XVEC (pat
, 0));
26042 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
26043 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
26045 rtx set
= XVECEXP (pat
, 0, i
);
26048 set
= simplify_replace_rtx (set
, reg
, repl
);
26050 set
= simplify_replace_rtx (set
, reg2
, repl2
);
26051 XVECEXP (pat
, 0, i
) = set
;
26053 if (!REG_P (SET_SRC (set
))
26054 || interesting_frame_related_regno (REGNO (SET_SRC (set
))))
26055 RTX_FRAME_RELATED_P (set
) = 1;
26059 gcc_unreachable ();
26061 RTX_FRAME_RELATED_P (insn
) = 1;
26062 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, copy_rtx_if_shared (pat
));
26067 /* Returns an insn that has a vrsave set operation with the
26068 appropriate CLOBBERs. */
26071 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
26074 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
26075 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
26078 = gen_rtx_SET (vrsave
,
26079 gen_rtx_UNSPEC_VOLATILE (SImode
,
26080 gen_rtvec (2, reg
, vrsave
),
26081 UNSPECV_SET_VRSAVE
));
26085 /* We need to clobber the registers in the mask so the scheduler
26086 does not move sets to VRSAVE before sets of AltiVec registers.
26088 However, if the function receives nonlocal gotos, reload will set
26089 all call saved registers live. We will end up with:
26091 (set (reg 999) (mem))
26092 (parallel [ (set (reg vrsave) (unspec blah))
26093 (clobber (reg 999))])
26095 The clobber will cause the store into reg 999 to be dead, and
26096 flow will attempt to delete an epilogue insn. In this case, we
26097 need an unspec use/set of the register. */
26099 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
26100 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
26102 if (!epiloguep
|| call_used_regs
[i
])
26103 clobs
[nclobs
++] = gen_hard_reg_clobber (V4SImode
, i
);
26106 rtx reg
= gen_rtx_REG (V4SImode
, i
);
26109 = gen_rtx_SET (reg
,
26110 gen_rtx_UNSPEC (V4SImode
,
26111 gen_rtvec (1, reg
), 27));
26115 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
26117 for (i
= 0; i
< nclobs
; ++i
)
26118 XVECEXP (insn
, 0, i
) = clobs
[i
];
26124 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
26128 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
26129 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
26130 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
26134 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
26136 return gen_frame_set (reg
, frame_reg
, offset
, false);
26140 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
26142 return gen_frame_set (reg
, frame_reg
, offset
, true);
26145 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
26146 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
26149 emit_frame_save (rtx frame_reg
, machine_mode mode
,
26150 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
26154 /* Some cases that need register indexed addressing. */
26155 gcc_checking_assert (!(TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
26156 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
)));
26158 reg
= gen_rtx_REG (mode
, regno
);
26159 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
26160 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
26161 NULL_RTX
, NULL_RTX
);
26164 /* Emit an offset memory reference suitable for a frame store, while
26165 converting to a valid addressing mode. */
26168 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
26170 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, GEN_INT (offset
)));
26173 #ifndef TARGET_FIX_AND_CONTINUE
26174 #define TARGET_FIX_AND_CONTINUE 0
26177 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
26178 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
26179 #define LAST_SAVRES_REGISTER 31
26180 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
26191 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
26193 /* Temporary holding space for an out-of-line register save/restore
26195 static char savres_routine_name
[30];
26197 /* Return the name for an out-of-line register save/restore routine.
26198 We are saving/restoring GPRs if GPR is true. */
26201 rs6000_savres_routine_name (int regno
, int sel
)
26203 const char *prefix
= "";
26204 const char *suffix
= "";
26206 /* Different targets are supposed to define
26207 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
26208 routine name could be defined with:
26210 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
26212 This is a nice idea in practice, but in reality, things are
26213 complicated in several ways:
26215 - ELF targets have save/restore routines for GPRs.
26217 - PPC64 ELF targets have routines for save/restore of GPRs that
26218 differ in what they do with the link register, so having a set
26219 prefix doesn't work. (We only use one of the save routines at
26220 the moment, though.)
26222 - PPC32 elf targets have "exit" versions of the restore routines
26223 that restore the link register and can save some extra space.
26224 These require an extra suffix. (There are also "tail" versions
26225 of the restore routines and "GOT" versions of the save routines,
26226 but we don't generate those at present. Same problems apply,
26229 We deal with all this by synthesizing our own prefix/suffix and
26230 using that for the simple sprintf call shown above. */
26231 if (DEFAULT_ABI
== ABI_V4
)
26236 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
26237 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
26238 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
26239 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
26240 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26241 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
26245 if ((sel
& SAVRES_LR
))
26248 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26250 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
26251 /* No out-of-line save/restore routines for GPRs on AIX. */
26252 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
26256 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
26257 prefix
= ((sel
& SAVRES_SAVE
)
26258 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
26259 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
26260 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
26262 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26263 if ((sel
& SAVRES_LR
))
26264 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
26268 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
26269 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
26272 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26273 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
26278 if (DEFAULT_ABI
== ABI_DARWIN
)
26280 /* The Darwin approach is (slightly) different, in order to be
26281 compatible with code generated by the system toolchain. There is a
26282 single symbol for the start of save sequence, and the code here
26283 embeds an offset into that code on the basis of the first register
26285 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
26286 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
26287 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
26288 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
26289 (regno
- 13) * 4, prefix
, regno
);
26290 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
26291 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
26292 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
26293 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26294 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
26295 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
26300 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
26302 return savres_routine_name
;
26305 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26306 We are saving/restoring GPRs if GPR is true. */
26309 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
26311 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26312 ? info
->first_gp_reg_save
26313 : (sel
& SAVRES_REG
) == SAVRES_FPR
26314 ? info
->first_fp_reg_save
- 32
26315 : (sel
& SAVRES_REG
) == SAVRES_VR
26316 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
26321 /* Don't generate bogus routine names. */
26322 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
26323 && regno
<= LAST_SAVRES_REGISTER
26324 && select
>= 0 && select
<= 12);
26326 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
26332 name
= rs6000_savres_routine_name (regno
, sel
);
26334 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
26335 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
26336 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
26342 /* Emit a sequence of insns, including a stack tie if needed, for
26343 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26344 reset the stack pointer, but move the base of the frame into
26345 reg UPDT_REGNO for use by out-of-line register restore routines. */
26348 rs6000_emit_stack_reset (rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
26349 unsigned updt_regno
)
26351 /* If there is nothing to do, don't do anything. */
26352 if (frame_off
== 0 && REGNO (frame_reg_rtx
) == updt_regno
)
26355 rtx updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
26357 /* This blockage is needed so that sched doesn't decide to move
26358 the sp change before the register restores. */
26359 if (DEFAULT_ABI
== ABI_V4
)
26360 return emit_insn (gen_stack_restore_tie (updt_reg_rtx
, frame_reg_rtx
,
26361 GEN_INT (frame_off
)));
26363 /* If we are restoring registers out-of-line, we will be using the
26364 "exit" variants of the restore routines, which will reset the
26365 stack for us. But we do need to point updt_reg into the
26366 right place for those routines. */
26367 if (frame_off
!= 0)
26368 return emit_insn (gen_add3_insn (updt_reg_rtx
,
26369 frame_reg_rtx
, GEN_INT (frame_off
)));
26371 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
26376 /* Return the register number used as a pointer by out-of-line
26377 save/restore functions. */
26379 static inline unsigned
26380 ptr_regno_for_savres (int sel
)
26382 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26383 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
26384 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
26387 /* Construct a parallel rtx describing the effect of a call to an
26388 out-of-line register save/restore routine, and emit the insn
26389 or jump_insn as appropriate. */
26392 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
26393 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
26394 machine_mode reg_mode
, int sel
)
26397 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
26398 int reg_size
= GET_MODE_SIZE (reg_mode
);
26405 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26406 ? info
->first_gp_reg_save
26407 : (sel
& SAVRES_REG
) == SAVRES_FPR
26408 ? info
->first_fp_reg_save
26409 : (sel
& SAVRES_REG
) == SAVRES_VR
26410 ? info
->first_altivec_reg_save
26412 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
26414 : (sel
& SAVRES_REG
) == SAVRES_FPR
26416 : (sel
& SAVRES_REG
) == SAVRES_VR
26417 ? LAST_ALTIVEC_REGNO
+ 1
26419 n_regs
= end_reg
- start_reg
;
26420 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
26421 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
26424 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26425 RTVEC_ELT (p
, offset
++) = ret_rtx
;
26427 RTVEC_ELT (p
, offset
++) = gen_hard_reg_clobber (Pmode
, LR_REGNO
);
26429 sym
= rs6000_savres_routine_sym (info
, sel
);
26430 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
26432 use_reg
= ptr_regno_for_savres (sel
);
26433 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
26435 /* Vector regs are saved/restored using [reg+reg] addressing. */
26436 RTVEC_ELT (p
, offset
++) = gen_hard_reg_clobber (Pmode
, use_reg
);
26437 RTVEC_ELT (p
, offset
++)
26438 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
26441 RTVEC_ELT (p
, offset
++)
26442 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
26444 for (i
= 0; i
< end_reg
- start_reg
; i
++)
26445 RTVEC_ELT (p
, i
+ offset
)
26446 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
26447 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
26448 (sel
& SAVRES_SAVE
) != 0);
26450 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26451 RTVEC_ELT (p
, i
+ offset
)
26452 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
26454 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
26456 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
26458 insn
= emit_jump_insn (par
);
26459 JUMP_LABEL (insn
) = ret_rtx
;
26462 insn
= emit_insn (par
);
26466 /* Emit prologue code to store CR fields that need to be saved into REG. This
26467 function should only be called when moving the non-volatile CRs to REG, it
26468 is not a general purpose routine to move the entire set of CRs to REG.
26469 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26473 rs6000_emit_prologue_move_from_cr (rtx reg
)
26475 /* Only the ELFv2 ABI allows storing only selected fields. */
26476 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
26478 int i
, cr_reg
[8], count
= 0;
26480 /* Collect CR fields that must be saved. */
26481 for (i
= 0; i
< 8; i
++)
26482 if (save_reg_p (CR0_REGNO
+ i
))
26483 cr_reg
[count
++] = i
;
26485 /* If it's just a single one, use mfcrf. */
26488 rtvec p
= rtvec_alloc (1);
26489 rtvec r
= rtvec_alloc (2);
26490 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
26491 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
26493 = gen_rtx_SET (reg
,
26494 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
26496 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26500 /* ??? It might be better to handle count == 2 / 3 cases here
26501 as well, using logical operations to combine the values. */
26504 emit_insn (gen_prologue_movesi_from_cr (reg
));
26507 /* Return whether the split-stack arg pointer (r12) is used. */
26510 split_stack_arg_pointer_used_p (void)
26512 /* If the pseudo holding the arg pointer is no longer a pseudo,
26513 then the arg pointer is used. */
26514 if (cfun
->machine
->split_stack_arg_pointer
!= NULL_RTX
26515 && (!REG_P (cfun
->machine
->split_stack_arg_pointer
)
26516 || HARD_REGISTER_P (cfun
->machine
->split_stack_arg_pointer
)))
26519 /* Unfortunately we also need to do some code scanning, since
26520 r12 may have been substituted for the pseudo. */
26522 basic_block bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
;
26523 FOR_BB_INSNS (bb
, insn
)
26524 if (NONDEBUG_INSN_P (insn
))
26526 /* A call destroys r12. */
26531 FOR_EACH_INSN_USE (use
, insn
)
26533 rtx x
= DF_REF_REG (use
);
26534 if (REG_P (x
) && REGNO (x
) == 12)
26538 FOR_EACH_INSN_DEF (def
, insn
)
26540 rtx x
= DF_REF_REG (def
);
26541 if (REG_P (x
) && REGNO (x
) == 12)
26545 return bitmap_bit_p (DF_LR_OUT (bb
), 12);
26548 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26551 rs6000_global_entry_point_needed_p (void)
26553 /* Only needed for the ELFv2 ABI. */
26554 if (DEFAULT_ABI
!= ABI_ELFv2
)
26557 /* With -msingle-pic-base, we assume the whole program shares the same
26558 TOC, so no global entry point prologues are needed anywhere. */
26559 if (TARGET_SINGLE_PIC_BASE
)
26562 /* Ensure we have a global entry point for thunks. ??? We could
26563 avoid that if the target routine doesn't need a global entry point,
26564 but we do not know whether this is the case at this point. */
26565 if (cfun
->is_thunk
)
26568 /* For regular functions, rs6000_emit_prologue sets this flag if the
26569 routine ever uses the TOC pointer. */
26570 return cfun
->machine
->r2_setup_needed
;
26573 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26575 rs6000_get_separate_components (void)
26577 rs6000_stack_t
*info
= rs6000_stack_info ();
26579 if (WORLD_SAVE_P (info
))
26582 gcc_assert (!(info
->savres_strategy
& SAVE_MULTIPLE
)
26583 && !(info
->savres_strategy
& REST_MULTIPLE
));
26585 /* Component 0 is the save/restore of LR (done via GPR0).
26586 Component 2 is the save of the TOC (GPR2).
26587 Components 13..31 are the save/restore of GPR13..GPR31.
26588 Components 46..63 are the save/restore of FPR14..FPR31. */
26590 cfun
->machine
->n_components
= 64;
26592 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26593 bitmap_clear (components
);
26595 int reg_size
= TARGET_32BIT
? 4 : 8;
26596 int fp_reg_size
= 8;
26598 /* The GPRs we need saved to the frame. */
26599 if ((info
->savres_strategy
& SAVE_INLINE_GPRS
)
26600 && (info
->savres_strategy
& REST_INLINE_GPRS
))
26602 int offset
= info
->gp_save_offset
;
26604 offset
+= info
->total_size
;
26606 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26608 if (IN_RANGE (offset
, -0x8000, 0x7fff)
26609 && save_reg_p (regno
))
26610 bitmap_set_bit (components
, regno
);
26612 offset
+= reg_size
;
26616 /* Don't mess with the hard frame pointer. */
26617 if (frame_pointer_needed
)
26618 bitmap_clear_bit (components
, HARD_FRAME_POINTER_REGNUM
);
26620 /* Don't mess with the fixed TOC register. */
26621 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
26622 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
26623 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
26624 bitmap_clear_bit (components
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
26626 /* The FPRs we need saved to the frame. */
26627 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
)
26628 && (info
->savres_strategy
& REST_INLINE_FPRS
))
26630 int offset
= info
->fp_save_offset
;
26632 offset
+= info
->total_size
;
26634 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26636 if (IN_RANGE (offset
, -0x8000, 0x7fff) && save_reg_p (regno
))
26637 bitmap_set_bit (components
, regno
);
26639 offset
+= fp_reg_size
;
26643 /* Optimize LR save and restore if we can. This is component 0. Any
26644 out-of-line register save/restore routines need LR. */
26645 if (info
->lr_save_p
26646 && !(flag_pic
&& (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
26647 && (info
->savres_strategy
& SAVE_INLINE_GPRS
)
26648 && (info
->savres_strategy
& REST_INLINE_GPRS
)
26649 && (info
->savres_strategy
& SAVE_INLINE_FPRS
)
26650 && (info
->savres_strategy
& REST_INLINE_FPRS
)
26651 && (info
->savres_strategy
& SAVE_INLINE_VRS
)
26652 && (info
->savres_strategy
& REST_INLINE_VRS
))
26654 int offset
= info
->lr_save_offset
;
26656 offset
+= info
->total_size
;
26657 if (IN_RANGE (offset
, -0x8000, 0x7fff))
26658 bitmap_set_bit (components
, 0);
26661 /* Optimize saving the TOC. This is component 2. */
26662 if (cfun
->machine
->save_toc_in_prologue
)
26663 bitmap_set_bit (components
, 2);
26668 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26670 rs6000_components_for_bb (basic_block bb
)
26672 rs6000_stack_t
*info
= rs6000_stack_info ();
26674 bitmap in
= DF_LIVE_IN (bb
);
26675 bitmap gen
= &DF_LIVE_BB_INFO (bb
)->gen
;
26676 bitmap kill
= &DF_LIVE_BB_INFO (bb
)->kill
;
26678 sbitmap components
= sbitmap_alloc (cfun
->machine
->n_components
);
26679 bitmap_clear (components
);
26681 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26684 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
26685 if (bitmap_bit_p (in
, regno
)
26686 || bitmap_bit_p (gen
, regno
)
26687 || bitmap_bit_p (kill
, regno
))
26688 bitmap_set_bit (components
, regno
);
26691 for (unsigned regno
= info
->first_fp_reg_save
; regno
< 64; regno
++)
26692 if (bitmap_bit_p (in
, regno
)
26693 || bitmap_bit_p (gen
, regno
)
26694 || bitmap_bit_p (kill
, regno
))
26695 bitmap_set_bit (components
, regno
);
26697 /* The link register. */
26698 if (bitmap_bit_p (in
, LR_REGNO
)
26699 || bitmap_bit_p (gen
, LR_REGNO
)
26700 || bitmap_bit_p (kill
, LR_REGNO
))
26701 bitmap_set_bit (components
, 0);
26703 /* The TOC save. */
26704 if (bitmap_bit_p (in
, TOC_REGNUM
)
26705 || bitmap_bit_p (gen
, TOC_REGNUM
)
26706 || bitmap_bit_p (kill
, TOC_REGNUM
))
26707 bitmap_set_bit (components
, 2);
26712 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26714 rs6000_disqualify_components (sbitmap components
, edge e
,
26715 sbitmap edge_components
, bool /*is_prologue*/)
26717 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26718 live where we want to place that code. */
26719 if (bitmap_bit_p (edge_components
, 0)
26720 && bitmap_bit_p (DF_LIVE_IN (e
->dest
), 0))
26723 fprintf (dump_file
, "Disqualifying LR because GPR0 is live "
26724 "on entry to bb %d\n", e
->dest
->index
);
26725 bitmap_clear_bit (components
, 0);
26729 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26731 rs6000_emit_prologue_components (sbitmap components
)
26733 rs6000_stack_t
*info
= rs6000_stack_info ();
26734 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26735 ? HARD_FRAME_POINTER_REGNUM
26736 : STACK_POINTER_REGNUM
);
26738 machine_mode reg_mode
= Pmode
;
26739 int reg_size
= TARGET_32BIT
? 4 : 8;
26740 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26741 int fp_reg_size
= 8;
26743 /* Prologue for LR. */
26744 if (bitmap_bit_p (components
, 0))
26746 rtx lr
= gen_rtx_REG (reg_mode
, LR_REGNO
);
26747 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26748 rtx_insn
*insn
= emit_move_insn (reg
, lr
);
26749 RTX_FRAME_RELATED_P (insn
) = 1;
26750 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (reg
, lr
));
26752 int offset
= info
->lr_save_offset
;
26754 offset
+= info
->total_size
;
26756 insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26757 RTX_FRAME_RELATED_P (insn
) = 1;
26758 rtx mem
= copy_rtx (SET_DEST (single_set (insn
)));
26759 add_reg_note (insn
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, lr
));
26762 /* Prologue for TOC. */
26763 if (bitmap_bit_p (components
, 2))
26765 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
26766 rtx sp_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26767 emit_insn (gen_frame_store (reg
, sp_reg
, RS6000_TOC_SAVE_SLOT
));
26770 /* Prologue for the GPRs. */
26771 int offset
= info
->gp_save_offset
;
26773 offset
+= info
->total_size
;
26775 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26777 if (bitmap_bit_p (components
, i
))
26779 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26780 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26781 RTX_FRAME_RELATED_P (insn
) = 1;
26782 rtx set
= copy_rtx (single_set (insn
));
26783 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26786 offset
+= reg_size
;
26789 /* Prologue for the FPRs. */
26790 offset
= info
->fp_save_offset
;
26792 offset
+= info
->total_size
;
26794 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26796 if (bitmap_bit_p (components
, i
))
26798 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26799 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
26800 RTX_FRAME_RELATED_P (insn
) = 1;
26801 rtx set
= copy_rtx (single_set (insn
));
26802 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
26805 offset
+= fp_reg_size
;
26809 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26811 rs6000_emit_epilogue_components (sbitmap components
)
26813 rs6000_stack_t
*info
= rs6000_stack_info ();
26814 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
26815 ? HARD_FRAME_POINTER_REGNUM
26816 : STACK_POINTER_REGNUM
);
26818 machine_mode reg_mode
= Pmode
;
26819 int reg_size
= TARGET_32BIT
? 4 : 8;
26821 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26822 int fp_reg_size
= 8;
26824 /* Epilogue for the FPRs. */
26825 int offset
= info
->fp_save_offset
;
26827 offset
+= info
->total_size
;
26829 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26831 if (bitmap_bit_p (components
, i
))
26833 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
26834 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26835 RTX_FRAME_RELATED_P (insn
) = 1;
26836 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26839 offset
+= fp_reg_size
;
26842 /* Epilogue for the GPRs. */
26843 offset
= info
->gp_save_offset
;
26845 offset
+= info
->total_size
;
26847 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26849 if (bitmap_bit_p (components
, i
))
26851 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26852 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26853 RTX_FRAME_RELATED_P (insn
) = 1;
26854 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
26857 offset
+= reg_size
;
26860 /* Epilogue for LR. */
26861 if (bitmap_bit_p (components
, 0))
26863 int offset
= info
->lr_save_offset
;
26865 offset
+= info
->total_size
;
26867 rtx reg
= gen_rtx_REG (reg_mode
, 0);
26868 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
26870 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
26871 insn
= emit_move_insn (lr
, reg
);
26872 RTX_FRAME_RELATED_P (insn
) = 1;
26873 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
26877 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26879 rs6000_set_handled_components (sbitmap components
)
26881 rs6000_stack_t
*info
= rs6000_stack_info ();
26883 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
26884 if (bitmap_bit_p (components
, i
))
26885 cfun
->machine
->gpr_is_wrapped_separately
[i
] = true;
26887 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
26888 if (bitmap_bit_p (components
, i
))
26889 cfun
->machine
->fpr_is_wrapped_separately
[i
- 32] = true;
26891 if (bitmap_bit_p (components
, 0))
26892 cfun
->machine
->lr_is_wrapped_separately
= true;
26894 if (bitmap_bit_p (components
, 2))
26895 cfun
->machine
->toc_is_wrapped_separately
= true;
26898 /* VRSAVE is a bit vector representing which AltiVec registers
26899 are used. The OS uses this to determine which vector
26900 registers to save on a context switch. We need to save
26901 VRSAVE on the stack frame, add whatever AltiVec registers we
26902 used in this function, and do the corresponding magic in the
26905 emit_vrsave_prologue (rs6000_stack_t
*info
, int save_regno
,
26906 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26908 /* Get VRSAVE into a GPR. */
26909 rtx reg
= gen_rtx_REG (SImode
, save_regno
);
26910 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
26912 emit_insn (gen_get_vrsave_internal (reg
));
26914 emit_insn (gen_rtx_SET (reg
, vrsave
));
26917 int offset
= info
->vrsave_save_offset
+ frame_off
;
26918 emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
26920 /* Include the registers in the mask. */
26921 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT (info
->vrsave_mask
)));
26923 emit_insn (generate_set_vrsave (reg
, info
, 0));
26926 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26927 called, it left the arg pointer to the old stack in r29. Otherwise, the
26928 arg pointer is the top of the current frame. */
26930 emit_split_stack_prologue (rs6000_stack_t
*info
, rtx_insn
*sp_adjust
,
26931 HOST_WIDE_INT frame_off
, rtx frame_reg_rtx
)
26933 cfun
->machine
->split_stack_argp_used
= true;
26937 rtx r12
= gen_rtx_REG (Pmode
, 12);
26938 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26939 rtx set_r12
= gen_rtx_SET (r12
, sp_reg_rtx
);
26940 emit_insn_before (set_r12
, sp_adjust
);
26942 else if (frame_off
!= 0 || REGNO (frame_reg_rtx
) != 12)
26944 rtx r12
= gen_rtx_REG (Pmode
, 12);
26945 if (frame_off
== 0)
26946 emit_move_insn (r12
, frame_reg_rtx
);
26948 emit_insn (gen_add3_insn (r12
, frame_reg_rtx
, GEN_INT (frame_off
)));
26953 rtx r12
= gen_rtx_REG (Pmode
, 12);
26954 rtx r29
= gen_rtx_REG (Pmode
, 29);
26955 rtx cr7
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
26956 rtx not_more
= gen_label_rtx ();
26959 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
26960 gen_rtx_GEU (VOIDmode
, cr7
, const0_rtx
),
26961 gen_rtx_LABEL_REF (VOIDmode
, not_more
),
26963 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
26964 JUMP_LABEL (jump
) = not_more
;
26965 LABEL_NUSES (not_more
) += 1;
26966 emit_move_insn (r12
, r29
);
26967 emit_label (not_more
);
26971 /* Emit function prologue as insns. */
26974 rs6000_emit_prologue (void)
26976 rs6000_stack_t
*info
= rs6000_stack_info ();
26977 machine_mode reg_mode
= Pmode
;
26978 int reg_size
= TARGET_32BIT
? 4 : 8;
26979 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
26980 int fp_reg_size
= 8;
26981 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26982 rtx frame_reg_rtx
= sp_reg_rtx
;
26983 unsigned int cr_save_regno
;
26984 rtx cr_save_rtx
= NULL_RTX
;
26987 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
26988 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
26989 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
26990 int using_split_stack
= (flag_split_stack
26991 && (lookup_attribute ("no_split_stack",
26992 DECL_ATTRIBUTES (cfun
->decl
))
26995 /* Offset to top of frame for frame_reg and sp respectively. */
26996 HOST_WIDE_INT frame_off
= 0;
26997 HOST_WIDE_INT sp_off
= 0;
26998 /* sp_adjust is the stack adjusting instruction, tracked so that the
26999 insn setting up the split-stack arg pointer can be emitted just
27000 prior to it, when r12 is not used here for other purposes. */
27001 rtx_insn
*sp_adjust
= 0;
27004 /* Track and check usage of r0, r11, r12. */
27005 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
27006 #define START_USE(R) do \
27008 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27009 reg_inuse |= 1 << (R); \
27011 #define END_USE(R) do \
27013 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
27014 reg_inuse &= ~(1 << (R)); \
27016 #define NOT_INUSE(R) do \
27018 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27021 #define START_USE(R) do {} while (0)
27022 #define END_USE(R) do {} while (0)
27023 #define NOT_INUSE(R) do {} while (0)
27026 if (DEFAULT_ABI
== ABI_ELFv2
27027 && !TARGET_SINGLE_PIC_BASE
)
27029 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
27031 /* With -mminimal-toc we may generate an extra use of r2 below. */
27032 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
27033 && !constant_pool_empty_p ())
27034 cfun
->machine
->r2_setup_needed
= true;
27038 if (flag_stack_usage_info
)
27039 current_function_static_stack_size
= info
->total_size
;
27041 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
27043 HOST_WIDE_INT size
= info
->total_size
;
27045 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
27047 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
27048 rs6000_emit_probe_stack_range (get_stack_check_protect (),
27049 size
- get_stack_check_protect ());
27052 rs6000_emit_probe_stack_range (get_stack_check_protect (), size
);
27055 if (TARGET_FIX_AND_CONTINUE
)
27057 /* gdb on darwin arranges to forward a function from the old
27058 address by modifying the first 5 instructions of the function
27059 to branch to the overriding function. This is necessary to
27060 permit function pointers that point to the old function to
27061 actually forward to the new function. */
27062 emit_insn (gen_nop ());
27063 emit_insn (gen_nop ());
27064 emit_insn (gen_nop ());
27065 emit_insn (gen_nop ());
27066 emit_insn (gen_nop ());
27069 /* Handle world saves specially here. */
27070 if (WORLD_SAVE_P (info
))
27077 /* save_world expects lr in r0. */
27078 reg0
= gen_rtx_REG (Pmode
, 0);
27079 if (info
->lr_save_p
)
27081 insn
= emit_move_insn (reg0
,
27082 gen_rtx_REG (Pmode
, LR_REGNO
));
27083 RTX_FRAME_RELATED_P (insn
) = 1;
27086 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
27087 assumptions about the offsets of various bits of the stack
27089 gcc_assert (info
->gp_save_offset
== -220
27090 && info
->fp_save_offset
== -144
27091 && info
->lr_save_offset
== 8
27092 && info
->cr_save_offset
== 4
27095 && (!crtl
->calls_eh_return
27096 || info
->ehrd_offset
== -432)
27097 && info
->vrsave_save_offset
== -224
27098 && info
->altivec_save_offset
== -416);
27100 treg
= gen_rtx_REG (SImode
, 11);
27101 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
27103 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
27104 in R11. It also clobbers R12, so beware! */
27106 /* Preserve CR2 for save_world prologues */
27108 sz
+= 32 - info
->first_gp_reg_save
;
27109 sz
+= 64 - info
->first_fp_reg_save
;
27110 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
27111 p
= rtvec_alloc (sz
);
27113 RTVEC_ELT (p
, j
++) = gen_hard_reg_clobber (SImode
, LR_REGNO
);
27114 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
27115 gen_rtx_SYMBOL_REF (Pmode
,
27117 /* We do floats first so that the instruction pattern matches
27119 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
27121 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
27122 info
->first_fp_reg_save
+ i
),
27124 info
->fp_save_offset
+ frame_off
+ 8 * i
);
27125 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
27127 = gen_frame_store (gen_rtx_REG (V4SImode
,
27128 info
->first_altivec_reg_save
+ i
),
27130 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
27131 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
27133 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
27135 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
27137 /* CR register traditionally saved as CR2. */
27139 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
27140 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
27141 /* Explain about use of R0. */
27142 if (info
->lr_save_p
)
27144 = gen_frame_store (reg0
,
27145 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
27146 /* Explain what happens to the stack pointer. */
27148 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
27149 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
27152 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27153 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27154 treg
, GEN_INT (-info
->total_size
));
27155 sp_off
= frame_off
= info
->total_size
;
27158 strategy
= info
->savres_strategy
;
27160 /* For V.4, update stack before we do any saving and set back pointer. */
27161 if (! WORLD_SAVE_P (info
)
27163 && (DEFAULT_ABI
== ABI_V4
27164 || crtl
->calls_eh_return
))
27166 bool need_r11
= (!(strategy
& SAVE_INLINE_FPRS
)
27167 || !(strategy
& SAVE_INLINE_GPRS
)
27168 || !(strategy
& SAVE_INLINE_VRS
));
27169 int ptr_regno
= -1;
27170 rtx ptr_reg
= NULL_RTX
;
27173 if (info
->total_size
< 32767)
27174 frame_off
= info
->total_size
;
27177 else if (info
->cr_save_p
27179 || info
->first_fp_reg_save
< 64
27180 || info
->first_gp_reg_save
< 32
27181 || info
->altivec_size
!= 0
27182 || info
->vrsave_size
!= 0
27183 || crtl
->calls_eh_return
)
27187 /* The prologue won't be saving any regs so there is no need
27188 to set up a frame register to access any frame save area.
27189 We also won't be using frame_off anywhere below, but set
27190 the correct value anyway to protect against future
27191 changes to this function. */
27192 frame_off
= info
->total_size
;
27194 if (ptr_regno
!= -1)
27196 /* Set up the frame offset to that needed by the first
27197 out-of-line save function. */
27198 START_USE (ptr_regno
);
27199 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27200 frame_reg_rtx
= ptr_reg
;
27201 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
27202 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
27203 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
27204 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
27205 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
27206 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
27207 frame_off
= -ptr_off
;
27209 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
27211 if (REGNO (frame_reg_rtx
) == 12)
27213 sp_off
= info
->total_size
;
27214 if (frame_reg_rtx
!= sp_reg_rtx
)
27215 rs6000_emit_stack_tie (frame_reg_rtx
, false);
27218 /* If we use the link register, get it into r0. */
27219 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
27220 && !cfun
->machine
->lr_is_wrapped_separately
)
27222 rtx addr
, reg
, mem
;
27224 reg
= gen_rtx_REG (Pmode
, 0);
27226 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
27227 RTX_FRAME_RELATED_P (insn
) = 1;
27229 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
27230 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
27232 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27233 GEN_INT (info
->lr_save_offset
+ frame_off
));
27234 mem
= gen_rtx_MEM (Pmode
, addr
);
27235 /* This should not be of rs6000_sr_alias_set, because of
27236 __builtin_return_address. */
27238 insn
= emit_move_insn (mem
, reg
);
27239 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27240 NULL_RTX
, NULL_RTX
);
27245 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
27246 r12 will be needed by out-of-line gpr save. */
27247 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27248 && !(strategy
& (SAVE_INLINE_GPRS
27249 | SAVE_NOINLINE_GPRS_SAVES_LR
))
27251 if (!WORLD_SAVE_P (info
)
27253 && REGNO (frame_reg_rtx
) != cr_save_regno
27254 && !(using_static_chain_p
&& cr_save_regno
== 11)
27255 && !(using_split_stack
&& cr_save_regno
== 12 && sp_adjust
))
27257 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
27258 START_USE (cr_save_regno
);
27259 rs6000_emit_prologue_move_from_cr (cr_save_rtx
);
27262 /* Do any required saving of fpr's. If only one or two to save, do
27263 it ourselves. Otherwise, call function. */
27264 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
27266 int offset
= info
->fp_save_offset
+ frame_off
;
27267 for (int i
= info
->first_fp_reg_save
; i
< 64; i
++)
27270 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
27271 emit_frame_save (frame_reg_rtx
, fp_reg_mode
, i
, offset
,
27272 sp_off
- frame_off
);
27274 offset
+= fp_reg_size
;
27277 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
27279 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
27280 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27281 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27282 rtx ptr_reg
= frame_reg_rtx
;
27284 if (REGNO (frame_reg_rtx
) == ptr_regno
)
27285 gcc_checking_assert (frame_off
== 0);
27288 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27289 NOT_INUSE (ptr_regno
);
27290 emit_insn (gen_add3_insn (ptr_reg
,
27291 frame_reg_rtx
, GEN_INT (frame_off
)));
27293 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
27294 info
->fp_save_offset
,
27295 info
->lr_save_offset
,
27297 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
27298 NULL_RTX
, NULL_RTX
);
27303 /* Save GPRs. This is done as a PARALLEL if we are using
27304 the store-multiple instructions. */
27305 if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
27307 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
27308 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
27309 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27310 rtx ptr_reg
= frame_reg_rtx
;
27311 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
27312 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
27315 if (ptr_regno
== 12)
27318 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27320 /* Need to adjust r11 (r12) if we saved any FPRs. */
27321 if (end_save
+ frame_off
!= 0)
27323 rtx offset
= GEN_INT (end_save
+ frame_off
);
27326 frame_off
= -end_save
;
27328 NOT_INUSE (ptr_regno
);
27329 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27331 else if (!ptr_set_up
)
27333 NOT_INUSE (ptr_regno
);
27334 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27336 ptr_off
= -end_save
;
27337 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
27338 info
->gp_save_offset
+ ptr_off
,
27339 info
->lr_save_offset
+ ptr_off
,
27341 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
27342 NULL_RTX
, NULL_RTX
);
27346 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_MULTIPLE
))
27350 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
27351 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
27353 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
27355 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
27356 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27357 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27358 NULL_RTX
, NULL_RTX
);
27360 else if (!WORLD_SAVE_P (info
))
27362 int offset
= info
->gp_save_offset
+ frame_off
;
27363 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
27366 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
27367 emit_frame_save (frame_reg_rtx
, reg_mode
, i
, offset
,
27368 sp_off
- frame_off
);
27370 offset
+= reg_size
;
27374 if (crtl
->calls_eh_return
)
27381 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
27382 if (regno
== INVALID_REGNUM
)
27386 p
= rtvec_alloc (i
);
27390 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
27391 if (regno
== INVALID_REGNUM
)
27395 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
27397 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
27398 RTVEC_ELT (p
, i
) = set
;
27399 RTX_FRAME_RELATED_P (set
) = 1;
27402 insn
= emit_insn (gen_blockage ());
27403 RTX_FRAME_RELATED_P (insn
) = 1;
27404 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
27407 /* In AIX ABI we need to make sure r2 is really saved. */
27408 if (TARGET_AIX
&& crtl
->calls_eh_return
)
27410 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
27411 rtx join_insn
, note
;
27412 rtx_insn
*save_insn
;
27413 long toc_restore_insn
;
27415 tmp_reg
= gen_rtx_REG (Pmode
, 11);
27416 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
27417 if (using_static_chain_p
)
27420 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
27424 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
27425 /* Peek at instruction to which this function returns. If it's
27426 restoring r2, then we know we've already saved r2. We can't
27427 unconditionally save r2 because the value we have will already
27428 be updated if we arrived at this function via a plt call or
27429 toc adjusting stub. */
27430 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
27431 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
27432 + RS6000_TOC_SAVE_SLOT
);
27433 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
27434 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
27435 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
27436 validate_condition_mode (EQ
, CCUNSmode
);
27437 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
27438 emit_insn (gen_rtx_SET (compare_result
,
27439 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
27440 toc_save_done
= gen_label_rtx ();
27441 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
27442 gen_rtx_EQ (VOIDmode
, compare_result
,
27444 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
27446 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
27447 JUMP_LABEL (jump
) = toc_save_done
;
27448 LABEL_NUSES (toc_save_done
) += 1;
27450 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
27451 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
27452 sp_off
- frame_off
);
27454 emit_label (toc_save_done
);
27456 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27457 have a CFG that has different saves along different paths.
27458 Move the note to a dummy blockage insn, which describes that
27459 R2 is unconditionally saved after the label. */
27460 /* ??? An alternate representation might be a special insn pattern
27461 containing both the branch and the store. That might let the
27462 code that minimizes the number of DW_CFA_advance opcodes better
27463 freedom in placing the annotations. */
27464 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
27466 remove_note (save_insn
, note
);
27468 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
27469 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
27470 RTX_FRAME_RELATED_P (save_insn
) = 0;
27472 join_insn
= emit_insn (gen_blockage ());
27473 REG_NOTES (join_insn
) = note
;
27474 RTX_FRAME_RELATED_P (join_insn
) = 1;
27476 if (using_static_chain_p
)
27478 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
27485 /* Save CR if we use any that must be preserved. */
27486 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
27488 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27489 GEN_INT (info
->cr_save_offset
+ frame_off
));
27490 rtx mem
= gen_frame_mem (SImode
, addr
);
27492 /* If we didn't copy cr before, do so now using r0. */
27493 if (cr_save_rtx
== NULL_RTX
)
27496 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
27497 rs6000_emit_prologue_move_from_cr (cr_save_rtx
);
27500 /* Saving CR requires a two-instruction sequence: one instruction
27501 to move the CR to a general-purpose register, and a second
27502 instruction that stores the GPR to memory.
27504 We do not emit any DWARF CFI records for the first of these,
27505 because we cannot properly represent the fact that CR is saved in
27506 a register. One reason is that we cannot express that multiple
27507 CR fields are saved; another reason is that on 64-bit, the size
27508 of the CR register in DWARF (4 bytes) differs from the size of
27509 a general-purpose register.
27511 This means if any intervening instruction were to clobber one of
27512 the call-saved CR fields, we'd have incorrect CFI. To prevent
27513 this from happening, we mark the store to memory as a use of
27514 those CR fields, which prevents any such instruction from being
27515 scheduled in between the two instructions. */
27520 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
27521 for (i
= 0; i
< 8; i
++)
27522 if (save_reg_p (CR0_REGNO
+ i
))
27523 crsave_v
[n_crsave
++]
27524 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
27526 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
27527 gen_rtvec_v (n_crsave
, crsave_v
)));
27528 END_USE (REGNO (cr_save_rtx
));
27530 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27531 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27532 so we need to construct a frame expression manually. */
27533 RTX_FRAME_RELATED_P (insn
) = 1;
27535 /* Update address to be stack-pointer relative, like
27536 rs6000_frame_related would do. */
27537 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
27538 GEN_INT (info
->cr_save_offset
+ sp_off
));
27539 mem
= gen_frame_mem (SImode
, addr
);
27541 if (DEFAULT_ABI
== ABI_ELFv2
)
27543 /* In the ELFv2 ABI we generate separate CFI records for each
27544 CR field that was actually saved. They all point to the
27545 same 32-bit stack slot. */
27549 for (i
= 0; i
< 8; i
++)
27550 if (save_reg_p (CR0_REGNO
+ i
))
27553 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
27555 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
27559 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27560 gen_rtx_PARALLEL (VOIDmode
,
27561 gen_rtvec_v (n_crframe
, crframe
)));
27565 /* In other ABIs, by convention, we use a single CR regnum to
27566 represent the fact that all call-saved CR fields are saved.
27567 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27568 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
27569 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
27573 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27574 *separate* slots if the routine calls __builtin_eh_return, so
27575 that they can be independently restored by the unwinder. */
27576 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
27578 int i
, cr_off
= info
->ehcr_offset
;
27581 /* ??? We might get better performance by using multiple mfocrf
27583 crsave
= gen_rtx_REG (SImode
, 0);
27584 emit_insn (gen_prologue_movesi_from_cr (crsave
));
27586 for (i
= 0; i
< 8; i
++)
27587 if (!call_used_regs
[CR0_REGNO
+ i
])
27589 rtvec p
= rtvec_alloc (2);
27591 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
27593 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
27595 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27597 RTX_FRAME_RELATED_P (insn
) = 1;
27598 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
27599 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
27600 sp_reg_rtx
, cr_off
+ sp_off
));
27602 cr_off
+= reg_size
;
27606 /* If we are emitting stack probes, but allocate no stack, then
27607 just note that in the dump file. */
27608 if (flag_stack_clash_protection
27611 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME
, false);
27613 /* Update stack and set back pointer unless this is V.4,
27614 for which it was done previously. */
27615 if (!WORLD_SAVE_P (info
) && info
->push_p
27616 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
27618 rtx ptr_reg
= NULL
;
27621 /* If saving altivec regs we need to be able to address all save
27622 locations using a 16-bit offset. */
27623 if ((strategy
& SAVE_INLINE_VRS
) == 0
27624 || (info
->altivec_size
!= 0
27625 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
27626 + info
->total_size
- frame_off
) > 32767)
27627 || (info
->vrsave_size
!= 0
27628 && (info
->vrsave_save_offset
27629 + info
->total_size
- frame_off
) > 32767))
27631 int sel
= SAVRES_SAVE
| SAVRES_VR
;
27632 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
27634 if (using_static_chain_p
27635 && ptr_regno
== STATIC_CHAIN_REGNUM
)
27637 if (REGNO (frame_reg_rtx
) != ptr_regno
)
27638 START_USE (ptr_regno
);
27639 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
27640 frame_reg_rtx
= ptr_reg
;
27641 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
27642 frame_off
= -ptr_off
;
27644 else if (REGNO (frame_reg_rtx
) == 1)
27645 frame_off
= info
->total_size
;
27646 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
27648 if (REGNO (frame_reg_rtx
) == 12)
27650 sp_off
= info
->total_size
;
27651 if (frame_reg_rtx
!= sp_reg_rtx
)
27652 rs6000_emit_stack_tie (frame_reg_rtx
, false);
27655 /* Set frame pointer, if needed. */
27656 if (frame_pointer_needed
)
27658 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
27660 RTX_FRAME_RELATED_P (insn
) = 1;
27663 /* Save AltiVec registers if needed. Save here because the red zone does
27664 not always include AltiVec registers. */
27665 if (!WORLD_SAVE_P (info
)
27666 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
27668 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
27670 /* Oddly, the vector save/restore functions point r0 at the end
27671 of the save area, then use r11 or r12 to load offsets for
27672 [reg+reg] addressing. */
27673 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
27674 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
27675 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
27677 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
27679 if (scratch_regno
== 12)
27681 if (end_save
+ frame_off
!= 0)
27683 rtx offset
= GEN_INT (end_save
+ frame_off
);
27685 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
27688 emit_move_insn (ptr_reg
, frame_reg_rtx
);
27690 ptr_off
= -end_save
;
27691 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
27692 info
->altivec_save_offset
+ ptr_off
,
27693 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
27694 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
27695 NULL_RTX
, NULL_RTX
);
27696 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
27698 /* The oddity mentioned above clobbered our frame reg. */
27699 emit_move_insn (frame_reg_rtx
, ptr_reg
);
27700 frame_off
= ptr_off
;
27703 else if (!WORLD_SAVE_P (info
)
27704 && info
->altivec_size
!= 0)
27708 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
27709 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
27711 rtx areg
, savereg
, mem
;
27712 HOST_WIDE_INT offset
;
27714 offset
= (info
->altivec_save_offset
+ frame_off
27715 + 16 * (i
- info
->first_altivec_reg_save
));
27717 savereg
= gen_rtx_REG (V4SImode
, i
);
27719 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
27721 mem
= gen_frame_mem (V4SImode
,
27722 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
27723 GEN_INT (offset
)));
27724 insn
= emit_insn (gen_rtx_SET (mem
, savereg
));
27730 areg
= gen_rtx_REG (Pmode
, 0);
27731 emit_move_insn (areg
, GEN_INT (offset
));
27733 /* AltiVec addressing mode is [reg+reg]. */
27734 mem
= gen_frame_mem (V4SImode
,
27735 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
27737 /* Rather than emitting a generic move, force use of the stvx
27738 instruction, which we always want on ISA 2.07 (power8) systems.
27739 In particular we don't want xxpermdi/stxvd2x for little
27741 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
27744 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
27745 areg
, GEN_INT (offset
));
27749 /* VRSAVE is a bit vector representing which AltiVec registers
27750 are used. The OS uses this to determine which vector
27751 registers to save on a context switch. We need to save
27752 VRSAVE on the stack frame, add whatever AltiVec registers we
27753 used in this function, and do the corresponding magic in the
27756 if (!WORLD_SAVE_P (info
) && info
->vrsave_size
!= 0)
27758 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27759 be using r12 as frame_reg_rtx and r11 as the static chain
27760 pointer for nested functions. */
27761 int save_regno
= 12;
27762 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27763 && !using_static_chain_p
)
27765 else if (using_split_stack
|| REGNO (frame_reg_rtx
) == 12)
27768 if (using_static_chain_p
)
27771 NOT_INUSE (save_regno
);
27773 emit_vrsave_prologue (info
, save_regno
, frame_off
, frame_reg_rtx
);
27776 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27777 if (!TARGET_SINGLE_PIC_BASE
27778 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
27779 && !constant_pool_empty_p ())
27780 || (DEFAULT_ABI
== ABI_V4
27781 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
27782 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
27784 /* If emit_load_toc_table will use the link register, we need to save
27785 it. We use R12 for this purpose because emit_load_toc_table
27786 can use register 0. This allows us to use a plain 'blr' to return
27787 from the procedure more often. */
27788 int save_LR_around_toc_setup
= (TARGET_ELF
27789 && DEFAULT_ABI
== ABI_V4
27791 && ! info
->lr_save_p
27792 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
27793 if (save_LR_around_toc_setup
)
27795 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27796 rtx tmp
= gen_rtx_REG (Pmode
, 12);
27799 insn
= emit_move_insn (tmp
, lr
);
27800 RTX_FRAME_RELATED_P (insn
) = 1;
27802 rs6000_emit_load_toc_table (TRUE
);
27804 insn
= emit_move_insn (lr
, tmp
);
27805 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27806 RTX_FRAME_RELATED_P (insn
) = 1;
27809 rs6000_emit_load_toc_table (TRUE
);
27813 if (!TARGET_SINGLE_PIC_BASE
27814 && DEFAULT_ABI
== ABI_DARWIN
27815 && flag_pic
&& crtl
->uses_pic_offset_table
)
27817 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27818 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
27820 /* Save and restore LR locally around this call (in R0). */
27821 if (!info
->lr_save_p
)
27822 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
27824 emit_insn (gen_load_macho_picbase (src
));
27826 emit_move_insn (gen_rtx_REG (Pmode
,
27827 RS6000_PIC_OFFSET_TABLE_REGNUM
),
27830 if (!info
->lr_save_p
)
27831 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
27835 /* If we need to, save the TOC register after doing the stack setup.
27836 Do not emit eh frame info for this save. The unwinder wants info,
27837 conceptually attached to instructions in this function, about
27838 register values in the caller of this function. This R2 may have
27839 already been changed from the value in the caller.
27840 We don't attempt to write accurate DWARF EH frame info for R2
27841 because code emitted by gcc for a (non-pointer) function call
27842 doesn't save and restore R2. Instead, R2 is managed out-of-line
27843 by a linker generated plt call stub when the function resides in
27844 a shared library. This behavior is costly to describe in DWARF,
27845 both in terms of the size of DWARF info and the time taken in the
27846 unwinder to interpret it. R2 changes, apart from the
27847 calls_eh_return case earlier in this function, are handled by
27848 linux-unwind.h frob_update_context. */
27849 if (rs6000_save_toc_in_prologue_p ()
27850 && !cfun
->machine
->toc_is_wrapped_separately
)
27852 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
27853 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
27856 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27857 if (using_split_stack
&& split_stack_arg_pointer_used_p ())
27858 emit_split_stack_prologue (info
, sp_adjust
, frame_off
, frame_reg_rtx
);
27861 /* Output .extern statements for the save/restore routines we use. */
27864 rs6000_output_savres_externs (FILE *file
)
27866 rs6000_stack_t
*info
= rs6000_stack_info ();
27868 if (TARGET_DEBUG_STACK
)
27869 debug_stack_info (info
);
27871 /* Write .extern for any function we will call to save and restore
27873 if (info
->first_fp_reg_save
< 64
27878 int regno
= info
->first_fp_reg_save
- 32;
27880 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
27882 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
27883 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27884 name
= rs6000_savres_routine_name (regno
, sel
);
27885 fprintf (file
, "\t.extern %s\n", name
);
27887 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
27889 bool lr
= (info
->savres_strategy
27890 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
27891 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27892 name
= rs6000_savres_routine_name (regno
, sel
);
27893 fprintf (file
, "\t.extern %s\n", name
);
27898 /* Write function prologue. */
27901 rs6000_output_function_prologue (FILE *file
)
27903 if (!cfun
->is_thunk
)
27904 rs6000_output_savres_externs (file
);
27906 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27907 immediately after the global entry point label. */
27908 if (rs6000_global_entry_point_needed_p ())
27910 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
27912 (*targetm
.asm_out
.internal_label
) (file
, "LCF", rs6000_pic_labelno
);
27914 if (TARGET_CMODEL
!= CMODEL_LARGE
)
27916 /* In the small and medium code models, we assume the TOC is less
27917 2 GB away from the text section, so it can be computed via the
27918 following two-instruction sequence. */
27921 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27922 fprintf (file
, "0:\taddis 2,12,.TOC.-");
27923 assemble_name (file
, buf
);
27924 fprintf (file
, "@ha\n");
27925 fprintf (file
, "\taddi 2,2,.TOC.-");
27926 assemble_name (file
, buf
);
27927 fprintf (file
, "@l\n");
27931 /* In the large code model, we allow arbitrary offsets between the
27932 TOC and the text section, so we have to load the offset from
27933 memory. The data field is emitted directly before the global
27934 entry point in rs6000_elf_declare_function_name. */
27937 #ifdef HAVE_AS_ENTRY_MARKERS
27938 /* If supported by the linker, emit a marker relocation. If the
27939 total code size of the final executable or shared library
27940 happens to fit into 2 GB after all, the linker will replace
27941 this code sequence with the sequence for the small or medium
27943 fprintf (file
, "\t.reloc .,R_PPC64_ENTRY\n");
27945 fprintf (file
, "\tld 2,");
27946 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
27947 assemble_name (file
, buf
);
27948 fprintf (file
, "-");
27949 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27950 assemble_name (file
, buf
);
27951 fprintf (file
, "(12)\n");
27952 fprintf (file
, "\tadd 2,2,12\n");
27955 fputs ("\t.localentry\t", file
);
27956 assemble_name (file
, name
);
27957 fputs (",.-", file
);
27958 assemble_name (file
, name
);
27959 fputs ("\n", file
);
27962 /* Output -mprofile-kernel code. This needs to be done here instead of
27963 in output_function_profile since it must go after the ELFv2 ABI
27964 local entry point. */
27965 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
27967 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
27968 gcc_assert (!TARGET_32BIT
);
27970 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
27972 /* In the ELFv2 ABI we have no compiler stack word. It must be
27973 the resposibility of _mcount to preserve the static chain
27974 register if required. */
27975 if (DEFAULT_ABI
!= ABI_ELFv2
27976 && cfun
->static_chain_decl
!= NULL
)
27978 asm_fprintf (file
, "\tstd %s,24(%s)\n",
27979 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27980 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27981 asm_fprintf (file
, "\tld %s,24(%s)\n",
27982 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
27985 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
27988 rs6000_pic_labelno
++;
27991 /* -mprofile-kernel code calls mcount before the function prolog,
27992 so a profiled leaf function should stay a leaf function. */
27994 rs6000_keep_leaf_when_profiled ()
27996 return TARGET_PROFILE_KERNEL
;
27999 /* Non-zero if vmx regs are restored before the frame pop, zero if
28000 we restore after the pop when possible. */
28001 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
28003 /* Restoring cr is a two step process: loading a reg from the frame
28004 save, then moving the reg to cr. For ABI_V4 we must let the
28005 unwinder know that the stack location is no longer valid at or
28006 before the stack deallocation, but we can't emit a cfa_restore for
28007 cr at the stack deallocation like we do for other registers.
28008 The trouble is that it is possible for the move to cr to be
28009 scheduled after the stack deallocation. So say exactly where cr
28010 is located on each of the two insns. */
28013 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
28015 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
28016 rtx reg
= gen_rtx_REG (SImode
, regno
);
28017 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
28019 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
28021 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
28022 rtx set
= gen_rtx_SET (reg
, cr
);
28024 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
28025 RTX_FRAME_RELATED_P (insn
) = 1;
28030 /* Reload CR from REG. */
28033 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
28038 if (using_mfcr_multiple
)
28040 for (i
= 0; i
< 8; i
++)
28041 if (save_reg_p (CR0_REGNO
+ i
))
28043 gcc_assert (count
);
28046 if (using_mfcr_multiple
&& count
> 1)
28052 p
= rtvec_alloc (count
);
28055 for (i
= 0; i
< 8; i
++)
28056 if (save_reg_p (CR0_REGNO
+ i
))
28058 rtvec r
= rtvec_alloc (2);
28059 RTVEC_ELT (r
, 0) = reg
;
28060 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
28061 RTVEC_ELT (p
, ndx
) =
28062 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
28063 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
28066 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28067 gcc_assert (ndx
== count
);
28069 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28070 CR field separately. */
28071 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
28073 for (i
= 0; i
< 8; i
++)
28074 if (save_reg_p (CR0_REGNO
+ i
))
28075 add_reg_note (insn
, REG_CFA_RESTORE
,
28076 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
28078 RTX_FRAME_RELATED_P (insn
) = 1;
28082 for (i
= 0; i
< 8; i
++)
28083 if (save_reg_p (CR0_REGNO
+ i
))
28085 rtx insn
= emit_insn (gen_movsi_to_cr_one
28086 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
28088 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28089 CR field separately, attached to the insn that in fact
28090 restores this particular CR field. */
28091 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
28093 add_reg_note (insn
, REG_CFA_RESTORE
,
28094 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
28096 RTX_FRAME_RELATED_P (insn
) = 1;
28100 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
28101 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
28102 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
28104 rtx_insn
*insn
= get_last_insn ();
28105 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
28107 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
28108 RTX_FRAME_RELATED_P (insn
) = 1;
28112 /* Like cr, the move to lr instruction can be scheduled after the
28113 stack deallocation, but unlike cr, its stack frame save is still
28114 valid. So we only need to emit the cfa_restore on the correct
28118 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
28120 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
28121 rtx reg
= gen_rtx_REG (Pmode
, regno
);
28123 emit_move_insn (reg
, mem
);
28127 restore_saved_lr (int regno
, bool exit_func
)
28129 rtx reg
= gen_rtx_REG (Pmode
, regno
);
28130 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
28131 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
28133 if (!exit_func
&& flag_shrink_wrap
)
28135 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
28136 RTX_FRAME_RELATED_P (insn
) = 1;
28141 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
28143 if (DEFAULT_ABI
== ABI_ELFv2
)
28146 for (i
= 0; i
< 8; i
++)
28147 if (save_reg_p (CR0_REGNO
+ i
))
28149 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
28150 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
28154 else if (info
->cr_save_p
)
28155 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
28156 gen_rtx_REG (SImode
, CR2_REGNO
),
28159 if (info
->lr_save_p
)
28160 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
28161 gen_rtx_REG (Pmode
, LR_REGNO
),
28163 return cfa_restores
;
28166 /* Return true if OFFSET from stack pointer can be clobbered by signals.
28167 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
28168 below stack pointer not cloberred by signals. */
28171 offset_below_red_zone_p (HOST_WIDE_INT offset
)
28173 return offset
< (DEFAULT_ABI
== ABI_V4
28175 : TARGET_32BIT
? -220 : -288);
28178 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
28181 emit_cfa_restores (rtx cfa_restores
)
28183 rtx_insn
*insn
= get_last_insn ();
28184 rtx
*loc
= ®_NOTES (insn
);
28187 loc
= &XEXP (*loc
, 1);
28188 *loc
= cfa_restores
;
28189 RTX_FRAME_RELATED_P (insn
) = 1;
28192 /* Emit function epilogue as insns. */
28195 rs6000_emit_epilogue (int sibcall
)
28197 rs6000_stack_t
*info
;
28198 int restoring_GPRs_inline
;
28199 int restoring_FPRs_inline
;
28200 int using_load_multiple
;
28201 int using_mtcr_multiple
;
28202 int use_backchain_to_restore_sp
;
28205 HOST_WIDE_INT frame_off
= 0;
28206 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
28207 rtx frame_reg_rtx
= sp_reg_rtx
;
28208 rtx cfa_restores
= NULL_RTX
;
28210 rtx cr_save_reg
= NULL_RTX
;
28211 machine_mode reg_mode
= Pmode
;
28212 int reg_size
= TARGET_32BIT
? 4 : 8;
28213 machine_mode fp_reg_mode
= TARGET_HARD_FLOAT
? DFmode
: SFmode
;
28214 int fp_reg_size
= 8;
28217 unsigned ptr_regno
;
28219 info
= rs6000_stack_info ();
28221 strategy
= info
->savres_strategy
;
28222 using_load_multiple
= strategy
& REST_MULTIPLE
;
28223 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
28224 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
28225 using_mtcr_multiple
= (rs6000_tune
== PROCESSOR_PPC601
28226 || rs6000_tune
== PROCESSOR_PPC603
28227 || rs6000_tune
== PROCESSOR_PPC750
28229 /* Restore via the backchain when we have a large frame, since this
28230 is more efficient than an addis, addi pair. The second condition
28231 here will not trigger at the moment; We don't actually need a
28232 frame pointer for alloca, but the generic parts of the compiler
28233 give us one anyway. */
28234 use_backchain_to_restore_sp
= (info
->total_size
+ (info
->lr_save_p
28235 ? info
->lr_save_offset
28237 || (cfun
->calls_alloca
28238 && !frame_pointer_needed
));
28239 restore_lr
= (info
->lr_save_p
28240 && (restoring_FPRs_inline
28241 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
28242 && (restoring_GPRs_inline
28243 || info
->first_fp_reg_save
< 64)
28244 && !cfun
->machine
->lr_is_wrapped_separately
);
28247 if (WORLD_SAVE_P (info
))
28251 const char *alloc_rname
;
28254 /* eh_rest_world_r10 will return to the location saved in the LR
28255 stack slot (which is not likely to be our caller.)
28256 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28257 rest_world is similar, except any R10 parameter is ignored.
28258 The exception-handling stuff that was here in 2.95 is no
28259 longer necessary. */
28262 + 32 - info
->first_gp_reg_save
28263 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
28264 + 63 + 1 - info
->first_fp_reg_save
);
28266 strcpy (rname
, ((crtl
->calls_eh_return
) ?
28267 "*eh_rest_world_r10" : "*rest_world"));
28268 alloc_rname
= ggc_strdup (rname
);
28271 RTVEC_ELT (p
, j
++) = ret_rtx
;
28273 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
28274 /* The instruction pattern requires a clobber here;
28275 it is shared with the restVEC helper. */
28276 RTVEC_ELT (p
, j
++) = gen_hard_reg_clobber (Pmode
, 11);
28279 /* CR register traditionally saved as CR2. */
28280 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
28282 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
28283 if (flag_shrink_wrap
)
28285 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
28286 gen_rtx_REG (Pmode
, LR_REGNO
),
28288 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28292 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28294 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
28296 = gen_frame_load (reg
,
28297 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
28298 if (flag_shrink_wrap
28299 && save_reg_p (info
->first_gp_reg_save
+ i
))
28300 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28302 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
28304 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
28306 = gen_frame_load (reg
,
28307 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
28308 if (flag_shrink_wrap
28309 && save_reg_p (info
->first_altivec_reg_save
+ i
))
28310 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28312 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
28314 rtx reg
= gen_rtx_REG (TARGET_HARD_FLOAT
? DFmode
: SFmode
,
28315 info
->first_fp_reg_save
+ i
);
28317 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
28318 if (flag_shrink_wrap
28319 && save_reg_p (info
->first_fp_reg_save
+ i
))
28320 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28322 RTVEC_ELT (p
, j
++) = gen_hard_reg_clobber (Pmode
, 0);
28323 RTVEC_ELT (p
, j
++) = gen_hard_reg_clobber (SImode
, 12);
28324 RTVEC_ELT (p
, j
++) = gen_hard_reg_clobber (SImode
, 7);
28325 RTVEC_ELT (p
, j
++) = gen_hard_reg_clobber (SImode
, 8);
28327 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
28328 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28330 if (flag_shrink_wrap
)
28332 REG_NOTES (insn
) = cfa_restores
;
28333 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28334 RTX_FRAME_RELATED_P (insn
) = 1;
28339 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28341 frame_off
= info
->total_size
;
28343 /* Restore AltiVec registers if we must do so before adjusting the
28345 if (info
->altivec_size
!= 0
28346 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28347 || (DEFAULT_ABI
!= ABI_V4
28348 && offset_below_red_zone_p (info
->altivec_save_offset
))))
28351 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
28353 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
28354 if (use_backchain_to_restore_sp
)
28356 int frame_regno
= 11;
28358 if ((strategy
& REST_INLINE_VRS
) == 0)
28360 /* Of r11 and r12, select the one not clobbered by an
28361 out-of-line restore function for the frame register. */
28362 frame_regno
= 11 + 12 - scratch_regno
;
28364 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
28365 emit_move_insn (frame_reg_rtx
,
28366 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28369 else if (frame_pointer_needed
)
28370 frame_reg_rtx
= hard_frame_pointer_rtx
;
28372 if ((strategy
& REST_INLINE_VRS
) == 0)
28374 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28376 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28377 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28379 if (end_save
+ frame_off
!= 0)
28381 rtx offset
= GEN_INT (end_save
+ frame_off
);
28383 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28386 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28388 ptr_off
= -end_save
;
28389 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28390 info
->altivec_save_offset
+ ptr_off
,
28391 0, V4SImode
, SAVRES_VR
);
28395 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28396 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28398 rtx addr
, areg
, mem
, insn
;
28399 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28400 HOST_WIDE_INT offset
28401 = (info
->altivec_save_offset
+ frame_off
28402 + 16 * (i
- info
->first_altivec_reg_save
));
28404 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
28406 mem
= gen_frame_mem (V4SImode
,
28407 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28408 GEN_INT (offset
)));
28409 insn
= gen_rtx_SET (reg
, mem
);
28413 areg
= gen_rtx_REG (Pmode
, 0);
28414 emit_move_insn (areg
, GEN_INT (offset
));
28416 /* AltiVec addressing mode is [reg+reg]. */
28417 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
28418 mem
= gen_frame_mem (V4SImode
, addr
);
28420 /* Rather than emitting a generic move, force use of the
28421 lvx instruction, which we always want. In particular we
28422 don't want lxvd2x/xxpermdi for little endian. */
28423 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
28426 (void) emit_insn (insn
);
28430 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28431 if (((strategy
& REST_INLINE_VRS
) == 0
28432 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
28433 && (flag_shrink_wrap
28434 || (offset_below_red_zone_p
28435 (info
->altivec_save_offset
28436 + 16 * (i
- info
->first_altivec_reg_save
))))
28439 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28440 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28444 /* Restore VRSAVE if we must do so before adjusting the stack. */
28445 if (info
->vrsave_size
!= 0
28446 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28447 || (DEFAULT_ABI
!= ABI_V4
28448 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
28452 if (frame_reg_rtx
== sp_reg_rtx
)
28454 if (use_backchain_to_restore_sp
)
28456 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28457 emit_move_insn (frame_reg_rtx
,
28458 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28461 else if (frame_pointer_needed
)
28462 frame_reg_rtx
= hard_frame_pointer_rtx
;
28465 reg
= gen_rtx_REG (SImode
, 12);
28466 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28467 info
->vrsave_save_offset
+ frame_off
));
28469 emit_insn (generate_set_vrsave (reg
, info
, 1));
28473 /* If we have a large stack frame, restore the old stack pointer
28474 using the backchain. */
28475 if (use_backchain_to_restore_sp
)
28477 if (frame_reg_rtx
== sp_reg_rtx
)
28479 /* Under V.4, don't reset the stack pointer until after we're done
28480 loading the saved registers. */
28481 if (DEFAULT_ABI
== ABI_V4
)
28482 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28484 insn
= emit_move_insn (frame_reg_rtx
,
28485 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
28488 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28489 && DEFAULT_ABI
== ABI_V4
)
28490 /* frame_reg_rtx has been set up by the altivec restore. */
28494 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
28495 frame_reg_rtx
= sp_reg_rtx
;
28498 /* If we have a frame pointer, we can restore the old stack pointer
28500 else if (frame_pointer_needed
)
28502 frame_reg_rtx
= sp_reg_rtx
;
28503 if (DEFAULT_ABI
== ABI_V4
)
28504 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
28505 /* Prevent reordering memory accesses against stack pointer restore. */
28506 else if (cfun
->calls_alloca
28507 || offset_below_red_zone_p (-info
->total_size
))
28508 rs6000_emit_stack_tie (frame_reg_rtx
, true);
28510 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
28511 GEN_INT (info
->total_size
)));
28514 else if (info
->push_p
28515 && DEFAULT_ABI
!= ABI_V4
28516 && !crtl
->calls_eh_return
)
28518 /* Prevent reordering memory accesses against stack pointer restore. */
28519 if (cfun
->calls_alloca
28520 || offset_below_red_zone_p (-info
->total_size
))
28521 rs6000_emit_stack_tie (frame_reg_rtx
, false);
28522 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
28523 GEN_INT (info
->total_size
)));
28526 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
28530 REG_NOTES (insn
) = cfa_restores
;
28531 cfa_restores
= NULL_RTX
;
28533 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28534 RTX_FRAME_RELATED_P (insn
) = 1;
28537 /* Restore AltiVec registers if we have not done so already. */
28538 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28539 && info
->altivec_size
!= 0
28540 && (DEFAULT_ABI
== ABI_V4
28541 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
28545 if ((strategy
& REST_INLINE_VRS
) == 0)
28547 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28549 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28550 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
28551 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28553 if (end_save
+ frame_off
!= 0)
28555 rtx offset
= GEN_INT (end_save
+ frame_off
);
28557 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28560 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28562 ptr_off
= -end_save
;
28563 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28564 info
->altivec_save_offset
+ ptr_off
,
28565 0, V4SImode
, SAVRES_VR
);
28566 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
28568 /* Frame reg was clobbered by out-of-line save. Restore it
28569 from ptr_reg, and if we are calling out-of-line gpr or
28570 fpr restore set up the correct pointer and offset. */
28571 unsigned newptr_regno
= 1;
28572 if (!restoring_GPRs_inline
)
28574 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28575 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28576 newptr_regno
= ptr_regno_for_savres (sel
);
28577 end_save
= info
->gp_save_offset
+ info
->gp_size
;
28579 else if (!restoring_FPRs_inline
)
28581 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
28582 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28583 newptr_regno
= ptr_regno_for_savres (sel
);
28584 end_save
= info
->fp_save_offset
+ info
->fp_size
;
28587 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
28588 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
28590 if (end_save
+ ptr_off
!= 0)
28592 rtx offset
= GEN_INT (end_save
+ ptr_off
);
28594 frame_off
= -end_save
;
28596 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
28599 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
28604 frame_off
= ptr_off
;
28605 emit_move_insn (frame_reg_rtx
, ptr_reg
);
28611 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28612 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28614 rtx addr
, areg
, mem
, insn
;
28615 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28616 HOST_WIDE_INT offset
28617 = (info
->altivec_save_offset
+ frame_off
28618 + 16 * (i
- info
->first_altivec_reg_save
));
28620 if (TARGET_P9_VECTOR
&& quad_address_offset_p (offset
))
28622 mem
= gen_frame_mem (V4SImode
,
28623 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28624 GEN_INT (offset
)));
28625 insn
= gen_rtx_SET (reg
, mem
);
28629 areg
= gen_rtx_REG (Pmode
, 0);
28630 emit_move_insn (areg
, GEN_INT (offset
));
28632 /* AltiVec addressing mode is [reg+reg]. */
28633 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
28634 mem
= gen_frame_mem (V4SImode
, addr
);
28636 /* Rather than emitting a generic move, force use of the
28637 lvx instruction, which we always want. In particular we
28638 don't want lxvd2x/xxpermdi for little endian. */
28639 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
28642 (void) emit_insn (insn
);
28646 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28647 if (((strategy
& REST_INLINE_VRS
) == 0
28648 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
28649 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28652 rtx reg
= gen_rtx_REG (V4SImode
, i
);
28653 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28657 /* Restore VRSAVE if we have not done so already. */
28658 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28659 && info
->vrsave_size
!= 0
28660 && (DEFAULT_ABI
== ABI_V4
28661 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
28665 reg
= gen_rtx_REG (SImode
, 12);
28666 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28667 info
->vrsave_save_offset
+ frame_off
));
28669 emit_insn (generate_set_vrsave (reg
, info
, 1));
28672 /* If we exit by an out-of-line restore function on ABI_V4 then that
28673 function will deallocate the stack, so we don't need to worry
28674 about the unwinder restoring cr from an invalid stack frame
28676 exit_func
= (!restoring_FPRs_inline
28677 || (!restoring_GPRs_inline
28678 && info
->first_fp_reg_save
== 64));
28680 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28681 *separate* slots if the routine calls __builtin_eh_return, so
28682 that they can be independently restored by the unwinder. */
28683 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
28685 int i
, cr_off
= info
->ehcr_offset
;
28687 for (i
= 0; i
< 8; i
++)
28688 if (!call_used_regs
[CR0_REGNO
+ i
])
28690 rtx reg
= gen_rtx_REG (SImode
, 0);
28691 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28692 cr_off
+ frame_off
));
28694 insn
= emit_insn (gen_movsi_to_cr_one
28695 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
28697 if (!exit_func
&& flag_shrink_wrap
)
28699 add_reg_note (insn
, REG_CFA_RESTORE
,
28700 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
28702 RTX_FRAME_RELATED_P (insn
) = 1;
28705 cr_off
+= reg_size
;
28709 /* Get the old lr if we saved it. If we are restoring registers
28710 out-of-line, then the out-of-line routines can do this for us. */
28711 if (restore_lr
&& restoring_GPRs_inline
)
28712 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28714 /* Get the old cr if we saved it. */
28715 if (info
->cr_save_p
)
28717 unsigned cr_save_regno
= 12;
28719 if (!restoring_GPRs_inline
)
28721 /* Ensure we don't use the register used by the out-of-line
28722 gpr register restore below. */
28723 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
28724 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28725 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
28727 if (gpr_ptr_regno
== 12)
28728 cr_save_regno
= 11;
28729 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
28731 else if (REGNO (frame_reg_rtx
) == 12)
28732 cr_save_regno
= 11;
28734 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
28735 info
->cr_save_offset
+ frame_off
,
28739 /* Set LR here to try to overlap restores below. */
28740 if (restore_lr
&& restoring_GPRs_inline
)
28741 restore_saved_lr (0, exit_func
);
28743 /* Load exception handler data registers, if needed. */
28744 if (crtl
->calls_eh_return
)
28746 unsigned int i
, regno
;
28750 rtx reg
= gen_rtx_REG (reg_mode
, 2);
28751 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
28752 frame_off
+ RS6000_TOC_SAVE_SLOT
));
28759 regno
= EH_RETURN_DATA_REGNO (i
);
28760 if (regno
== INVALID_REGNUM
)
28763 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
28764 info
->ehrd_offset
+ frame_off
28765 + reg_size
* (int) i
);
28767 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
28771 /* Restore GPRs. This is done as a PARALLEL if we are using
28772 the load-multiple instructions. */
28773 if (!restoring_GPRs_inline
)
28775 /* We are jumping to an out-of-line function. */
28777 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
28778 bool can_use_exit
= end_save
== 0;
28779 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
28782 /* Emit stack reset code if we need it. */
28783 ptr_regno
= ptr_regno_for_savres (sel
);
28784 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28786 rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28787 else if (end_save
+ frame_off
!= 0)
28788 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
28789 GEN_INT (end_save
+ frame_off
)));
28790 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
28791 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28792 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28793 frame_off
= -end_save
;
28795 if (can_use_exit
&& info
->cr_save_p
)
28796 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
28798 ptr_off
= -end_save
;
28799 rs6000_emit_savres_rtx (info
, ptr_reg
,
28800 info
->gp_save_offset
+ ptr_off
,
28801 info
->lr_save_offset
+ ptr_off
,
28804 else if (using_load_multiple
)
28807 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
28808 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28810 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
28812 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
28813 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28817 int offset
= info
->gp_save_offset
+ frame_off
;
28818 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28821 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28823 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28824 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28827 offset
+= reg_size
;
28831 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28833 /* If the frame pointer was used then we can't delay emitting
28834 a REG_CFA_DEF_CFA note. This must happen on the insn that
28835 restores the frame pointer, r31. We may have already emitted
28836 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28837 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28838 be harmless if emitted. */
28839 if (frame_pointer_needed
)
28841 insn
= get_last_insn ();
28842 add_reg_note (insn
, REG_CFA_DEF_CFA
,
28843 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
28844 RTX_FRAME_RELATED_P (insn
) = 1;
28847 /* Set up cfa_restores. We always need these when
28848 shrink-wrapping. If not shrink-wrapping then we only need
28849 the cfa_restore when the stack location is no longer valid.
28850 The cfa_restores must be emitted on or before the insn that
28851 invalidates the stack, and of course must not be emitted
28852 before the insn that actually does the restore. The latter
28853 is why it is a bad idea to emit the cfa_restores as a group
28854 on the last instruction here that actually does a restore:
28855 That insn may be reordered with respect to others doing
28857 if (flag_shrink_wrap
28858 && !restoring_GPRs_inline
28859 && info
->first_fp_reg_save
== 64)
28860 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28862 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
28864 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28866 rtx reg
= gen_rtx_REG (reg_mode
, i
);
28867 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
28871 if (!restoring_GPRs_inline
28872 && info
->first_fp_reg_save
== 64)
28874 /* We are jumping to an out-of-line function. */
28876 emit_cfa_restores (cfa_restores
);
28880 if (restore_lr
&& !restoring_GPRs_inline
)
28882 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28883 restore_saved_lr (0, exit_func
);
28886 /* Restore fpr's if we need to do it without calling a function. */
28887 if (restoring_FPRs_inline
)
28889 int offset
= info
->fp_save_offset
+ frame_off
;
28890 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
28893 && !cfun
->machine
->fpr_is_wrapped_separately
[i
- 32])
28895 rtx reg
= gen_rtx_REG (fp_reg_mode
, i
);
28896 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
28897 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
28898 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
28902 offset
+= fp_reg_size
;
28906 /* If we saved cr, restore it here. Just those that were used. */
28907 if (info
->cr_save_p
)
28908 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
28910 /* If this is V.4, unwind the stack pointer after all of the loads
28911 have been done, or set up r11 if we are restoring fp out of line. */
28913 if (!restoring_FPRs_inline
)
28915 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28916 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28917 ptr_regno
= ptr_regno_for_savres (sel
);
28920 insn
= rs6000_emit_stack_reset (frame_reg_rtx
, frame_off
, ptr_regno
);
28921 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28924 if (insn
&& restoring_FPRs_inline
)
28928 REG_NOTES (insn
) = cfa_restores
;
28929 cfa_restores
= NULL_RTX
;
28931 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
28932 RTX_FRAME_RELATED_P (insn
) = 1;
28935 if (crtl
->calls_eh_return
)
28937 rtx sa
= EH_RETURN_STACKADJ_RTX
;
28938 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
28941 if (!sibcall
&& restoring_FPRs_inline
)
28945 /* We can't hang the cfa_restores off a simple return,
28946 since the shrink-wrap code sometimes uses an existing
28947 return. This means there might be a path from
28948 pre-prologue code to this return, and dwarf2cfi code
28949 wants the eh_frame unwinder state to be the same on
28950 all paths to any point. So we need to emit the
28951 cfa_restores before the return. For -m64 we really
28952 don't need epilogue cfa_restores at all, except for
28953 this irritating dwarf2cfi with shrink-wrap
28954 requirement; The stack red-zone means eh_frame info
28955 from the prologue telling the unwinder to restore
28956 from the stack is perfectly good right to the end of
28958 emit_insn (gen_blockage ());
28959 emit_cfa_restores (cfa_restores
);
28960 cfa_restores
= NULL_RTX
;
28963 emit_jump_insn (targetm
.gen_simple_return ());
28966 if (!sibcall
&& !restoring_FPRs_inline
)
28968 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28969 rtvec p
= rtvec_alloc (3 + !!lr
+ 64 - info
->first_fp_reg_save
);
28971 RTVEC_ELT (p
, elt
++) = ret_rtx
;
28973 RTVEC_ELT (p
, elt
++) = gen_hard_reg_clobber (Pmode
, LR_REGNO
);
28975 /* We have to restore more than two FP registers, so branch to the
28976 restore function. It will return to our caller. */
28981 if (flag_shrink_wrap
)
28982 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
28984 sym
= rs6000_savres_routine_sym (info
, SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
28985 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, sym
);
28986 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
28987 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
28989 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
28991 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
28993 RTVEC_ELT (p
, elt
++)
28994 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
28995 if (flag_shrink_wrap
28996 && save_reg_p (info
->first_fp_reg_save
+ i
))
28997 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
29000 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
29006 /* Ensure the cfa_restores are hung off an insn that won't
29007 be reordered above other restores. */
29008 emit_insn (gen_blockage ());
29010 emit_cfa_restores (cfa_restores
);
29014 /* Write function epilogue. */
29017 rs6000_output_function_epilogue (FILE *file
)
29020 macho_branch_islands ();
29023 rtx_insn
*insn
= get_last_insn ();
29024 rtx_insn
*deleted_debug_label
= NULL
;
29026 /* Mach-O doesn't support labels at the end of objects, so if
29027 it looks like we might want one, take special action.
29029 First, collect any sequence of deleted debug labels. */
29032 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
29034 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
29035 notes only, instead set their CODE_LABEL_NUMBER to -1,
29036 otherwise there would be code generation differences
29037 in between -g and -g0. */
29038 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
29039 deleted_debug_label
= insn
;
29040 insn
= PREV_INSN (insn
);
29043 /* Second, if we have:
29046 then this needs to be detected, so skip past the barrier. */
29048 if (insn
&& BARRIER_P (insn
))
29049 insn
= PREV_INSN (insn
);
29051 /* Up to now we've only seen notes or barriers. */
29056 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
))
29057 /* Trailing label: <barrier>. */
29058 fputs ("\tnop\n", file
);
29061 /* Lastly, see if we have a completely empty function body. */
29062 while (insn
&& ! INSN_P (insn
))
29063 insn
= PREV_INSN (insn
);
29064 /* If we don't find any insns, we've got an empty function body;
29065 I.e. completely empty - without a return or branch. This is
29066 taken as the case where a function body has been removed
29067 because it contains an inline __builtin_unreachable(). GCC
29068 states that reaching __builtin_unreachable() means UB so we're
29069 not obliged to do anything special; however, we want
29070 non-zero-sized function bodies. To meet this, and help the
29071 user out, let's trap the case. */
29073 fputs ("\ttrap\n", file
);
29076 else if (deleted_debug_label
)
29077 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
29078 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
29079 CODE_LABEL_NUMBER (insn
) = -1;
29083 /* Output a traceback table here. See /usr/include/sys/debug.h for info
29086 We don't output a traceback table if -finhibit-size-directive was
29087 used. The documentation for -finhibit-size-directive reads
29088 ``don't output a @code{.size} assembler directive, or anything
29089 else that would cause trouble if the function is split in the
29090 middle, and the two halves are placed at locations far apart in
29091 memory.'' The traceback table has this property, since it
29092 includes the offset from the start of the function to the
29093 traceback table itself.
29095 System V.4 Powerpc's (and the embedded ABI derived from it) use a
29096 different traceback table. */
29097 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29098 && ! flag_inhibit_size_directive
29099 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
29101 const char *fname
= NULL
;
29102 const char *language_string
= lang_hooks
.name
;
29103 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
29105 int optional_tbtab
;
29106 rs6000_stack_t
*info
= rs6000_stack_info ();
29108 if (rs6000_traceback
== traceback_full
)
29109 optional_tbtab
= 1;
29110 else if (rs6000_traceback
== traceback_part
)
29111 optional_tbtab
= 0;
29113 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
29115 if (optional_tbtab
)
29117 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
29118 while (*fname
== '.') /* V.4 encodes . in the name */
29121 /* Need label immediately before tbtab, so we can compute
29122 its offset from the function start. */
29123 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
29124 ASM_OUTPUT_LABEL (file
, fname
);
29127 /* The .tbtab pseudo-op can only be used for the first eight
29128 expressions, since it can't handle the possibly variable
29129 length fields that follow. However, if you omit the optional
29130 fields, the assembler outputs zeros for all optional fields
29131 anyways, giving each variable length field is minimum length
29132 (as defined in sys/debug.h). Thus we cannot use the .tbtab
29133 pseudo-op at all. */
29135 /* An all-zero word flags the start of the tbtab, for debuggers
29136 that have to find it by searching forward from the entry
29137 point or from the current pc. */
29138 fputs ("\t.long 0\n", file
);
29140 /* Tbtab format type. Use format type 0. */
29141 fputs ("\t.byte 0,", file
);
29143 /* Language type. Unfortunately, there does not seem to be any
29144 official way to discover the language being compiled, so we
29145 use language_string.
29146 C is 0. Fortran is 1. Ada is 3. C++ is 9.
29147 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
29148 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
29149 numbers either, so for now use 0. */
29151 || ! strcmp (language_string
, "GNU GIMPLE")
29152 || ! strcmp (language_string
, "GNU Go")
29153 || ! strcmp (language_string
, "GNU D")
29154 || ! strcmp (language_string
, "libgccjit"))
29156 else if (! strcmp (language_string
, "GNU F77")
29157 || lang_GNU_Fortran ())
29159 else if (! strcmp (language_string
, "GNU Ada"))
29161 else if (lang_GNU_CXX ()
29162 || ! strcmp (language_string
, "GNU Objective-C++"))
29164 else if (! strcmp (language_string
, "GNU Java"))
29166 else if (! strcmp (language_string
, "GNU Objective-C"))
29169 gcc_unreachable ();
29170 fprintf (file
, "%d,", i
);
29172 /* 8 single bit fields: global linkage (not set for C extern linkage,
29173 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
29174 from start of procedure stored in tbtab, internal function, function
29175 has controlled storage, function has no toc, function uses fp,
29176 function logs/aborts fp operations. */
29177 /* Assume that fp operations are used if any fp reg must be saved. */
29178 fprintf (file
, "%d,",
29179 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
29181 /* 6 bitfields: function is interrupt handler, name present in
29182 proc table, function calls alloca, on condition directives
29183 (controls stack walks, 3 bits), saves condition reg, saves
29185 /* The `function calls alloca' bit seems to be set whenever reg 31 is
29186 set up as a frame pointer, even when there is no alloca call. */
29187 fprintf (file
, "%d,",
29188 ((optional_tbtab
<< 6)
29189 | ((optional_tbtab
& frame_pointer_needed
) << 5)
29190 | (info
->cr_save_p
<< 1)
29191 | (info
->lr_save_p
)));
29193 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
29195 fprintf (file
, "%d,",
29196 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
29198 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
29199 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
29201 if (optional_tbtab
)
29203 /* Compute the parameter info from the function decl argument
29206 int next_parm_info_bit
= 31;
29208 for (decl
= DECL_ARGUMENTS (current_function_decl
);
29209 decl
; decl
= DECL_CHAIN (decl
))
29211 rtx parameter
= DECL_INCOMING_RTL (decl
);
29212 machine_mode mode
= GET_MODE (parameter
);
29214 if (REG_P (parameter
))
29216 if (SCALAR_FLOAT_MODE_P (mode
))
29239 gcc_unreachable ();
29242 /* If only one bit will fit, don't or in this entry. */
29243 if (next_parm_info_bit
> 0)
29244 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
29245 next_parm_info_bit
-= 2;
29249 fixed_parms
+= ((GET_MODE_SIZE (mode
)
29250 + (UNITS_PER_WORD
- 1))
29252 next_parm_info_bit
-= 1;
29258 /* Number of fixed point parameters. */
29259 /* This is actually the number of words of fixed point parameters; thus
29260 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29261 fprintf (file
, "%d,", fixed_parms
);
29263 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29265 /* This is actually the number of fp registers that hold parameters;
29266 and thus the maximum value is 13. */
29267 /* Set parameters on stack bit if parameters are not in their original
29268 registers, regardless of whether they are on the stack? Xlc
29269 seems to set the bit when not optimizing. */
29270 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
29272 if (optional_tbtab
)
29274 /* Optional fields follow. Some are variable length. */
29276 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29277 float, 11 double float. */
29278 /* There is an entry for each parameter in a register, in the order
29279 that they occur in the parameter list. Any intervening arguments
29280 on the stack are ignored. If the list overflows a long (max
29281 possible length 34 bits) then completely leave off all elements
29283 /* Only emit this long if there was at least one parameter. */
29284 if (fixed_parms
|| float_parms
)
29285 fprintf (file
, "\t.long %d\n", parm_info
);
29287 /* Offset from start of code to tb table. */
29288 fputs ("\t.long ", file
);
29289 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
29290 RS6000_OUTPUT_BASENAME (file
, fname
);
29292 rs6000_output_function_entry (file
, fname
);
29295 /* Interrupt handler mask. */
29296 /* Omit this long, since we never set the interrupt handler bit
29299 /* Number of CTL (controlled storage) anchors. */
29300 /* Omit this long, since the has_ctl bit is never set above. */
29302 /* Displacement into stack of each CTL anchor. */
29303 /* Omit this list of longs, because there are no CTL anchors. */
29305 /* Length of function name. */
29308 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
29310 /* Function name. */
29311 assemble_string (fname
, strlen (fname
));
29313 /* Register for alloca automatic storage; this is always reg 31.
29314 Only emit this if the alloca bit was set above. */
29315 if (frame_pointer_needed
)
29316 fputs ("\t.byte 31\n", file
);
29318 fputs ("\t.align 2\n", file
);
29322 /* Arrange to define .LCTOC1 label, if not already done. */
29326 if (!toc_initialized
)
29328 switch_to_section (toc_section
);
29329 switch_to_section (current_function_section ());
29334 /* -fsplit-stack support. */
29336 /* A SYMBOL_REF for __morestack. */
29337 static GTY(()) rtx morestack_ref
;
29340 gen_add3_const (rtx rt
, rtx ra
, long c
)
29343 return gen_adddi3 (rt
, ra
, GEN_INT (c
));
29345 return gen_addsi3 (rt
, ra
, GEN_INT (c
));
29348 /* Emit -fsplit-stack prologue, which goes before the regular function
29349 prologue (at local entry point in the case of ELFv2). */
29352 rs6000_expand_split_stack_prologue (void)
29354 rs6000_stack_t
*info
= rs6000_stack_info ();
29355 unsigned HOST_WIDE_INT allocate
;
29356 long alloc_hi
, alloc_lo
;
29357 rtx r0
, r1
, r12
, lr
, ok_label
, compare
, jump
, call_fusage
;
29360 gcc_assert (flag_split_stack
&& reload_completed
);
29365 if (global_regs
[29])
29367 error ("%qs uses register r29", "%<-fsplit-stack%>");
29368 inform (DECL_SOURCE_LOCATION (global_regs_decl
[29]),
29369 "conflicts with %qD", global_regs_decl
[29]);
29372 allocate
= info
->total_size
;
29373 if (allocate
> (unsigned HOST_WIDE_INT
) 1 << 31)
29375 sorry ("Stack frame larger than 2G is not supported for "
29376 "%<-fsplit-stack%>");
29379 if (morestack_ref
== NULL_RTX
)
29381 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
29382 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
29383 | SYMBOL_FLAG_FUNCTION
);
29386 r0
= gen_rtx_REG (Pmode
, 0);
29387 r1
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29388 r12
= gen_rtx_REG (Pmode
, 12);
29389 emit_insn (gen_load_split_stack_limit (r0
));
29390 /* Always emit two insns here to calculate the requested stack,
29391 so that the linker can edit them when adjusting size for calling
29392 non-split-stack code. */
29393 alloc_hi
= (-allocate
+ 0x8000) & ~0xffffL
;
29394 alloc_lo
= -allocate
- alloc_hi
;
29397 emit_insn (gen_add3_const (r12
, r1
, alloc_hi
));
29399 emit_insn (gen_add3_const (r12
, r12
, alloc_lo
));
29401 emit_insn (gen_nop ());
29405 emit_insn (gen_add3_const (r12
, r1
, alloc_lo
));
29406 emit_insn (gen_nop ());
29409 compare
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
29410 emit_insn (gen_rtx_SET (compare
, gen_rtx_COMPARE (CCUNSmode
, r12
, r0
)));
29411 ok_label
= gen_label_rtx ();
29412 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
29413 gen_rtx_GEU (VOIDmode
, compare
, const0_rtx
),
29414 gen_rtx_LABEL_REF (VOIDmode
, ok_label
),
29416 insn
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
29417 JUMP_LABEL (insn
) = ok_label
;
29418 /* Mark the jump as very likely to be taken. */
29419 add_reg_br_prob_note (insn
, profile_probability::very_likely ());
29421 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
29422 insn
= emit_move_insn (r0
, lr
);
29423 RTX_FRAME_RELATED_P (insn
) = 1;
29424 insn
= emit_insn (gen_frame_store (r0
, r1
, info
->lr_save_offset
));
29425 RTX_FRAME_RELATED_P (insn
) = 1;
29427 insn
= emit_call_insn (gen_call (gen_rtx_MEM (SImode
, morestack_ref
),
29428 const0_rtx
, const0_rtx
));
29429 call_fusage
= NULL_RTX
;
29430 use_reg (&call_fusage
, r12
);
29431 /* Say the call uses r0, even though it doesn't, to stop regrename
29432 from twiddling with the insns saving lr, trashing args for cfun.
29433 The insns restoring lr are similarly protected by making
29434 split_stack_return use r0. */
29435 use_reg (&call_fusage
, r0
);
29436 add_function_usage_to (insn
, call_fusage
);
29437 /* Indicate that this function can't jump to non-local gotos. */
29438 make_reg_eh_region_note_nothrow_nononlocal (insn
);
29439 emit_insn (gen_frame_load (r0
, r1
, info
->lr_save_offset
));
29440 insn
= emit_move_insn (lr
, r0
);
29441 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
29442 RTX_FRAME_RELATED_P (insn
) = 1;
29443 emit_insn (gen_split_stack_return ());
29445 emit_label (ok_label
);
29446 LABEL_NUSES (ok_label
) = 1;
29449 /* Return the internal arg pointer used for function incoming
29450 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29451 to copy it to a pseudo in order for it to be preserved over calls
29452 and suchlike. We'd really like to use a pseudo here for the
29453 internal arg pointer but data-flow analysis is not prepared to
29454 accept pseudos as live at the beginning of a function. */
29457 rs6000_internal_arg_pointer (void)
29459 if (flag_split_stack
29460 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
29464 if (cfun
->machine
->split_stack_arg_pointer
== NULL_RTX
)
29468 cfun
->machine
->split_stack_arg_pointer
= gen_reg_rtx (Pmode
);
29469 REG_POINTER (cfun
->machine
->split_stack_arg_pointer
) = 1;
29471 /* Put the pseudo initialization right after the note at the
29472 beginning of the function. */
29473 pat
= gen_rtx_SET (cfun
->machine
->split_stack_arg_pointer
,
29474 gen_rtx_REG (Pmode
, 12));
29475 push_topmost_sequence ();
29476 emit_insn_after (pat
, get_insns ());
29477 pop_topmost_sequence ();
29479 rtx ret
= plus_constant (Pmode
, cfun
->machine
->split_stack_arg_pointer
,
29480 FIRST_PARM_OFFSET (current_function_decl
));
29481 return copy_to_reg (ret
);
29483 return virtual_incoming_args_rtx
;
29486 /* We may have to tell the dataflow pass that the split stack prologue
29487 is initializing a register. */
29490 rs6000_live_on_entry (bitmap regs
)
29492 if (flag_split_stack
)
29493 bitmap_set_bit (regs
, 12);
29496 /* Emit -fsplit-stack dynamic stack allocation space check. */
29499 rs6000_split_stack_space_check (rtx size
, rtx label
)
29501 rtx sp
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
29502 rtx limit
= gen_reg_rtx (Pmode
);
29503 rtx requested
= gen_reg_rtx (Pmode
);
29504 rtx cmp
= gen_reg_rtx (CCUNSmode
);
29507 emit_insn (gen_load_split_stack_limit (limit
));
29508 if (CONST_INT_P (size
))
29509 emit_insn (gen_add3_insn (requested
, sp
, GEN_INT (-INTVAL (size
))));
29512 size
= force_reg (Pmode
, size
);
29513 emit_move_insn (requested
, gen_rtx_MINUS (Pmode
, sp
, size
));
29515 emit_insn (gen_rtx_SET (cmp
, gen_rtx_COMPARE (CCUNSmode
, requested
, limit
)));
29516 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
29517 gen_rtx_GEU (VOIDmode
, cmp
, const0_rtx
),
29518 gen_rtx_LABEL_REF (VOIDmode
, label
),
29520 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
29521 JUMP_LABEL (jump
) = label
;
29524 /* A C compound statement that outputs the assembler code for a thunk
29525 function, used to implement C++ virtual function calls with
29526 multiple inheritance. The thunk acts as a wrapper around a virtual
29527 function, adjusting the implicit object parameter before handing
29528 control off to the real function.
29530 First, emit code to add the integer DELTA to the location that
29531 contains the incoming first argument. Assume that this argument
29532 contains a pointer, and is the one used to pass the `this' pointer
29533 in C++. This is the incoming argument *before* the function
29534 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29535 values of all other incoming arguments.
29537 After the addition, emit code to jump to FUNCTION, which is a
29538 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29539 not touch the return address. Hence returning from FUNCTION will
29540 return to whoever called the current `thunk'.
29542 The effect must be as if FUNCTION had been called directly with the
29543 adjusted first argument. This macro is responsible for emitting
29544 all of the code for a thunk function; output_function_prologue()
29545 and output_function_epilogue() are not invoked.
29547 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29548 been extracted from it.) It might possibly be useful on some
29549 targets, but probably not.
29551 If you do not define this macro, the target-independent code in the
29552 C++ frontend will generate a less efficient heavyweight thunk that
29553 calls FUNCTION instead of jumping to it. The generic approach does
29554 not support varargs. */
29557 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
29558 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
29561 rtx this_rtx
, funexp
;
29564 reload_completed
= 1;
29565 epilogue_completed
= 1;
29567 /* Mark the end of the (empty) prologue. */
29568 emit_note (NOTE_INSN_PROLOGUE_END
);
29570 /* Find the "this" pointer. If the function returns a structure,
29571 the structure return pointer is in r3. */
29572 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
29573 this_rtx
= gen_rtx_REG (Pmode
, 4);
29575 this_rtx
= gen_rtx_REG (Pmode
, 3);
29577 /* Apply the constant offset, if required. */
29579 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
29581 /* Apply the offset from the vtable, if required. */
29584 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
29585 rtx tmp
= gen_rtx_REG (Pmode
, 12);
29587 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
29588 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
29590 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
29591 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
29595 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
29597 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
29599 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
29602 /* Generate a tail call to the target function. */
29603 if (!TREE_USED (function
))
29605 assemble_external (function
);
29606 TREE_USED (function
) = 1;
29608 funexp
= XEXP (DECL_RTL (function
), 0);
29609 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
29612 if (MACHOPIC_INDIRECT
)
29613 funexp
= machopic_indirect_call_target (funexp
);
29616 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29617 generate sibcall RTL explicitly. */
29618 insn
= emit_call_insn (
29619 gen_rtx_PARALLEL (VOIDmode
,
29621 gen_rtx_CALL (VOIDmode
,
29622 funexp
, const0_rtx
),
29623 gen_rtx_USE (VOIDmode
, const0_rtx
),
29624 simple_return_rtx
)));
29625 SIBLING_CALL_P (insn
) = 1;
29628 /* Run just enough of rest_of_compilation to get the insns emitted.
29629 There's not really enough bulk here to make other passes such as
29630 instruction scheduling worth while. Note that use_thunk calls
29631 assemble_start_function and assemble_end_function. */
29632 insn
= get_insns ();
29633 shorten_branches (insn
);
29634 final_start_function (insn
, file
, 1);
29635 final (insn
, file
, 1);
29636 final_end_function ();
29638 reload_completed
= 0;
29639 epilogue_completed
= 0;
29642 /* A quick summary of the various types of 'constant-pool tables'
29645 Target Flags Name One table per
29646 AIX (none) AIX TOC object file
29647 AIX -mfull-toc AIX TOC object file
29648 AIX -mminimal-toc AIX minimal TOC translation unit
29649 SVR4/EABI (none) SVR4 SDATA object file
29650 SVR4/EABI -fpic SVR4 pic object file
29651 SVR4/EABI -fPIC SVR4 PIC translation unit
29652 SVR4/EABI -mrelocatable EABI TOC function
29653 SVR4/EABI -maix AIX TOC object file
29654 SVR4/EABI -maix -mminimal-toc
29655 AIX minimal TOC translation unit
29657 Name Reg. Set by entries contains:
29658 made by addrs? fp? sum?
29660 AIX TOC 2 crt0 as Y option option
29661 AIX minimal TOC 30 prolog gcc Y Y option
29662 SVR4 SDATA 13 crt0 gcc N Y N
29663 SVR4 pic 30 prolog ld Y not yet N
29664 SVR4 PIC 30 prolog gcc Y option option
29665 EABI TOC 30 prolog gcc Y option option
29669 /* Hash functions for the hash table. */
29672 rs6000_hash_constant (rtx k
)
29674 enum rtx_code code
= GET_CODE (k
);
29675 machine_mode mode
= GET_MODE (k
);
29676 unsigned result
= (code
<< 3) ^ mode
;
29677 const char *format
;
29680 format
= GET_RTX_FORMAT (code
);
29681 flen
= strlen (format
);
29687 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
29689 case CONST_WIDE_INT
:
29692 flen
= CONST_WIDE_INT_NUNITS (k
);
29693 for (i
= 0; i
< flen
; i
++)
29694 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
29699 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
29709 for (; fidx
< flen
; fidx
++)
29710 switch (format
[fidx
])
29715 const char *str
= XSTR (k
, fidx
);
29716 len
= strlen (str
);
29717 result
= result
* 613 + len
;
29718 for (i
= 0; i
< len
; i
++)
29719 result
= result
* 613 + (unsigned) str
[i
];
29724 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
29728 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
29731 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
29732 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
29736 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
29737 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
29744 gcc_unreachable ();
29751 toc_hasher::hash (toc_hash_struct
*thc
)
29753 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
29756 /* Compare H1 and H2 for equivalence. */
29759 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
29764 if (h1
->key_mode
!= h2
->key_mode
)
29767 return rtx_equal_p (r1
, r2
);
29770 /* These are the names given by the C++ front-end to vtables, and
29771 vtable-like objects. Ideally, this logic should not be here;
29772 instead, there should be some programmatic way of inquiring as
29773 to whether or not an object is a vtable. */
29775 #define VTABLE_NAME_P(NAME) \
29776 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29777 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29778 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29779 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29780 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29782 #ifdef NO_DOLLAR_IN_LABEL
29783 /* Return a GGC-allocated character string translating dollar signs in
29784 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29787 rs6000_xcoff_strip_dollar (const char *name
)
29793 q
= (const char *) strchr (name
, '$');
29795 if (q
== 0 || q
== name
)
29798 len
= strlen (name
);
29799 strip
= XALLOCAVEC (char, len
+ 1);
29800 strcpy (strip
, name
);
29801 p
= strip
+ (q
- name
);
29805 p
= strchr (p
+ 1, '$');
29808 return ggc_alloc_string (strip
, len
);
29813 rs6000_output_symbol_ref (FILE *file
, rtx x
)
29815 const char *name
= XSTR (x
, 0);
29817 /* Currently C++ toc references to vtables can be emitted before it
29818 is decided whether the vtable is public or private. If this is
29819 the case, then the linker will eventually complain that there is
29820 a reference to an unknown section. Thus, for vtables only,
29821 we emit the TOC reference to reference the identifier and not the
29823 if (VTABLE_NAME_P (name
))
29825 RS6000_OUTPUT_BASENAME (file
, name
);
29828 assemble_name (file
, name
);
29831 /* Output a TOC entry. We derive the entry name from what is being
29835 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
29838 const char *name
= buf
;
29840 HOST_WIDE_INT offset
= 0;
29842 gcc_assert (!TARGET_NO_TOC
);
29844 /* When the linker won't eliminate them, don't output duplicate
29845 TOC entries (this happens on AIX if there is any kind of TOC,
29846 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29848 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
29850 struct toc_hash_struct
*h
;
29852 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29853 time because GGC is not initialized at that point. */
29854 if (toc_hash_table
== NULL
)
29855 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
29857 h
= ggc_alloc
<toc_hash_struct
> ();
29859 h
->key_mode
= mode
;
29860 h
->labelno
= labelno
;
29862 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
29863 if (*found
== NULL
)
29865 else /* This is indeed a duplicate.
29866 Set this label equal to that label. */
29868 fputs ("\t.set ", file
);
29869 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29870 fprintf (file
, "%d,", labelno
);
29871 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
29872 fprintf (file
, "%d\n", ((*found
)->labelno
));
29875 if (TARGET_XCOFF
&& SYMBOL_REF_P (x
)
29876 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
29877 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
29879 fputs ("\t.set ", file
);
29880 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29881 fprintf (file
, "%d,", labelno
);
29882 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
29883 fprintf (file
, "%d\n", ((*found
)->labelno
));
29890 /* If we're going to put a double constant in the TOC, make sure it's
29891 aligned properly when strict alignment is on. */
29892 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
29893 && STRICT_ALIGNMENT
29894 && GET_MODE_BITSIZE (mode
) >= 64
29895 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
29896 ASM_OUTPUT_ALIGN (file
, 3);
29899 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
29901 /* Handle FP constants specially. Note that if we have a minimal
29902 TOC, things we put here aren't actually in the TOC, so we can allow
29904 if (CONST_DOUBLE_P (x
)
29905 && (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
29906 || GET_MODE (x
) == IFmode
|| GET_MODE (x
) == KFmode
))
29910 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29911 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29913 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29917 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29918 fputs (DOUBLE_INT_ASM_OP
, file
);
29920 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29921 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29922 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29923 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
29924 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29925 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
29926 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
29927 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
29932 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29933 fputs ("\t.long ", file
);
29935 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29936 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29937 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29938 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29939 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
29940 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
29944 else if (CONST_DOUBLE_P (x
)
29945 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
29949 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29950 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29952 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
29956 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29957 fputs (DOUBLE_INT_ASM_OP
, file
);
29959 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29960 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29961 fprintf (file
, "0x%lx%08lx\n",
29962 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
29963 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
29968 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29969 fputs ("\t.long ", file
);
29971 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
29972 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29973 fprintf (file
, "0x%lx,0x%lx\n",
29974 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
29978 else if (CONST_DOUBLE_P (x
)
29979 && (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
29983 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
29984 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29986 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
29990 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
29991 fputs (DOUBLE_INT_ASM_OP
, file
);
29993 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
29994 if (WORDS_BIG_ENDIAN
)
29995 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
29997 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
30002 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
30003 fputs ("\t.long ", file
);
30005 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
30006 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
30010 else if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
30012 unsigned HOST_WIDE_INT low
;
30013 HOST_WIDE_INT high
;
30015 low
= INTVAL (x
) & 0xffffffff;
30016 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
30018 /* TOC entries are always Pmode-sized, so when big-endian
30019 smaller integer constants in the TOC need to be padded.
30020 (This is still a win over putting the constants in
30021 a separate constant pool, because then we'd have
30022 to have both a TOC entry _and_ the actual constant.)
30024 For a 32-bit target, CONST_INT values are loaded and shifted
30025 entirely within `low' and can be stored in one TOC entry. */
30027 /* It would be easy to make this work, but it doesn't now. */
30028 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
30030 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
30033 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
30034 high
= (HOST_WIDE_INT
) low
>> 32;
30040 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
30041 fputs (DOUBLE_INT_ASM_OP
, file
);
30043 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
30044 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
30045 fprintf (file
, "0x%lx%08lx\n",
30046 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
30051 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
30053 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
30054 fputs ("\t.long ", file
);
30056 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
30057 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
30058 fprintf (file
, "0x%lx,0x%lx\n",
30059 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
30063 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
30064 fputs ("\t.long ", file
);
30066 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
30067 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
30073 if (GET_CODE (x
) == CONST
)
30075 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
30076 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)));
30078 base
= XEXP (XEXP (x
, 0), 0);
30079 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
30082 switch (GET_CODE (base
))
30085 name
= XSTR (base
, 0);
30089 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
30090 CODE_LABEL_NUMBER (XEXP (base
, 0)));
30094 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
30098 gcc_unreachable ();
30101 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
30102 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
30105 fputs ("\t.tc ", file
);
30106 RS6000_OUTPUT_BASENAME (file
, name
);
30109 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
30111 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
30113 /* Mark large TOC symbols on AIX with [TE] so they are mapped
30114 after other TOC symbols, reducing overflow of small TOC access
30115 to [TC] symbols. */
30116 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
30117 ? "[TE]," : "[TC],", file
);
30120 /* Currently C++ toc references to vtables can be emitted before it
30121 is decided whether the vtable is public or private. If this is
30122 the case, then the linker will eventually complain that there is
30123 a TOC reference to an unknown section. Thus, for vtables only,
30124 we emit the TOC reference to reference the symbol and not the
30126 if (VTABLE_NAME_P (name
))
30128 RS6000_OUTPUT_BASENAME (file
, name
);
30130 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
30131 else if (offset
> 0)
30132 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
30135 output_addr_const (file
, x
);
30138 if (TARGET_XCOFF
&& SYMBOL_REF_P (base
))
30140 switch (SYMBOL_REF_TLS_MODEL (base
))
30144 case TLS_MODEL_LOCAL_EXEC
:
30145 fputs ("@le", file
);
30147 case TLS_MODEL_INITIAL_EXEC
:
30148 fputs ("@ie", file
);
30150 /* Use global-dynamic for local-dynamic. */
30151 case TLS_MODEL_GLOBAL_DYNAMIC
:
30152 case TLS_MODEL_LOCAL_DYNAMIC
:
30154 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
30155 fputs ("\t.tc .", file
);
30156 RS6000_OUTPUT_BASENAME (file
, name
);
30157 fputs ("[TC],", file
);
30158 output_addr_const (file
, x
);
30159 fputs ("@m", file
);
30162 gcc_unreachable ();
30170 /* Output an assembler pseudo-op to write an ASCII string of N characters
30171 starting at P to FILE.
30173 On the RS/6000, we have to do this using the .byte operation and
30174 write out special characters outside the quoted string.
30175 Also, the assembler is broken; very long strings are truncated,
30176 so we must artificially break them up early. */
30179 output_ascii (FILE *file
, const char *p
, int n
)
30182 int i
, count_string
;
30183 const char *for_string
= "\t.byte \"";
30184 const char *for_decimal
= "\t.byte ";
30185 const char *to_close
= NULL
;
30188 for (i
= 0; i
< n
; i
++)
30191 if (c
>= ' ' && c
< 0177)
30194 fputs (for_string
, file
);
30197 /* Write two quotes to get one. */
30205 for_decimal
= "\"\n\t.byte ";
30209 if (count_string
>= 512)
30211 fputs (to_close
, file
);
30213 for_string
= "\t.byte \"";
30214 for_decimal
= "\t.byte ";
30222 fputs (for_decimal
, file
);
30223 fprintf (file
, "%d", c
);
30225 for_string
= "\n\t.byte \"";
30226 for_decimal
= ", ";
30232 /* Now close the string if we have written one. Then end the line. */
30234 fputs (to_close
, file
);
30237 /* Generate a unique section name for FILENAME for a section type
30238 represented by SECTION_DESC. Output goes into BUF.
30240 SECTION_DESC can be any string, as long as it is different for each
30241 possible section type.
30243 We name the section in the same manner as xlc. The name begins with an
30244 underscore followed by the filename (after stripping any leading directory
30245 names) with the last period replaced by the string SECTION_DESC. If
30246 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30250 rs6000_gen_section_name (char **buf
, const char *filename
,
30251 const char *section_desc
)
30253 const char *q
, *after_last_slash
, *last_period
= 0;
30257 after_last_slash
= filename
;
30258 for (q
= filename
; *q
; q
++)
30261 after_last_slash
= q
+ 1;
30262 else if (*q
== '.')
30266 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
30267 *buf
= (char *) xmalloc (len
);
30272 for (q
= after_last_slash
; *q
; q
++)
30274 if (q
== last_period
)
30276 strcpy (p
, section_desc
);
30277 p
+= strlen (section_desc
);
30281 else if (ISALNUM (*q
))
30285 if (last_period
== 0)
30286 strcpy (p
, section_desc
);
30291 /* Emit profile function. */
30294 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
30296 /* Non-standard profiling for kernels, which just saves LR then calls
30297 _mcount without worrying about arg saves. The idea is to change
30298 the function prologue as little as possible as it isn't easy to
30299 account for arg save/restore code added just for _mcount. */
30300 if (TARGET_PROFILE_KERNEL
)
30303 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
30305 #ifndef NO_PROFILE_COUNTERS
30306 # define NO_PROFILE_COUNTERS 0
30308 if (NO_PROFILE_COUNTERS
)
30309 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
30310 LCT_NORMAL
, VOIDmode
);
30314 const char *label_name
;
30317 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
30318 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
30319 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
30321 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
30322 LCT_NORMAL
, VOIDmode
, fun
, Pmode
);
30325 else if (DEFAULT_ABI
== ABI_DARWIN
)
30327 const char *mcount_name
= RS6000_MCOUNT
;
30328 int caller_addr_regno
= LR_REGNO
;
30330 /* Be conservative and always set this, at least for now. */
30331 crtl
->uses_pic_offset_table
= 1;
30334 /* For PIC code, set up a stub and collect the caller's address
30335 from r0, which is where the prologue puts it. */
30336 if (MACHOPIC_INDIRECT
30337 && crtl
->uses_pic_offset_table
)
30338 caller_addr_regno
= 0;
30340 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
30341 LCT_NORMAL
, VOIDmode
,
30342 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
30346 /* Write function profiler code. */
30349 output_function_profiler (FILE *file
, int labelno
)
30353 switch (DEFAULT_ABI
)
30356 gcc_unreachable ();
30361 warning (0, "no profiling of 64-bit code for this ABI");
30364 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
30365 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
30366 if (NO_PROFILE_COUNTERS
)
30368 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30369 reg_names
[0], reg_names
[1]);
30371 else if (TARGET_SECURE_PLT
&& flag_pic
)
30373 if (TARGET_LINK_STACK
)
30376 get_ppc476_thunk_name (name
);
30377 asm_fprintf (file
, "\tbl %s\n", name
);
30380 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
30381 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30382 reg_names
[0], reg_names
[1]);
30383 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
30384 asm_fprintf (file
, "\taddis %s,%s,",
30385 reg_names
[12], reg_names
[12]);
30386 assemble_name (file
, buf
);
30387 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
30388 assemble_name (file
, buf
);
30389 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
30391 else if (flag_pic
== 1)
30393 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
30394 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30395 reg_names
[0], reg_names
[1]);
30396 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
30397 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
30398 assemble_name (file
, buf
);
30399 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
30401 else if (flag_pic
> 1)
30403 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30404 reg_names
[0], reg_names
[1]);
30405 /* Now, we need to get the address of the label. */
30406 if (TARGET_LINK_STACK
)
30409 get_ppc476_thunk_name (name
);
30410 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
30411 assemble_name (file
, buf
);
30412 fputs ("-.\n1:", file
);
30413 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
30414 asm_fprintf (file
, "\taddi %s,%s,4\n",
30415 reg_names
[11], reg_names
[11]);
30419 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
30420 assemble_name (file
, buf
);
30421 fputs ("-.\n1:", file
);
30422 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
30424 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
30425 reg_names
[0], reg_names
[11]);
30426 asm_fprintf (file
, "\tadd %s,%s,%s\n",
30427 reg_names
[0], reg_names
[0], reg_names
[11]);
30431 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
30432 assemble_name (file
, buf
);
30433 fputs ("@ha\n", file
);
30434 asm_fprintf (file
, "\tstw %s,4(%s)\n",
30435 reg_names
[0], reg_names
[1]);
30436 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
30437 assemble_name (file
, buf
);
30438 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
30441 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30442 fprintf (file
, "\tbl %s%s\n",
30443 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
30449 /* Don't do anything, done in output_profile_hook (). */
30456 /* The following variable value is the last issued insn. */
30458 static rtx_insn
*last_scheduled_insn
;
30460 /* The following variable helps to balance issuing of load and
30461 store instructions */
30463 static int load_store_pendulum
;
30465 /* The following variable helps pair divide insns during scheduling. */
30466 static int divide_cnt
;
30467 /* The following variable helps pair and alternate vector and vector load
30468 insns during scheduling. */
30469 static int vec_pairing
;
30472 /* Power4 load update and store update instructions are cracked into a
30473 load or store and an integer insn which are executed in the same cycle.
30474 Branches have their own dispatch slot which does not count against the
30475 GCC issue rate, but it changes the program flow so there are no other
30476 instructions to issue in this cycle. */
30479 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
30481 last_scheduled_insn
= insn
;
30482 if (GET_CODE (PATTERN (insn
)) == USE
30483 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30485 cached_can_issue_more
= more
;
30486 return cached_can_issue_more
;
30489 if (insn_terminates_group_p (insn
, current_group
))
30491 cached_can_issue_more
= 0;
30492 return cached_can_issue_more
;
30495 /* If no reservation, but reach here */
30496 if (recog_memoized (insn
) < 0)
30499 if (rs6000_sched_groups
)
30501 if (is_microcoded_insn (insn
))
30502 cached_can_issue_more
= 0;
30503 else if (is_cracked_insn (insn
))
30504 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
30506 cached_can_issue_more
= more
- 1;
30508 return cached_can_issue_more
;
30511 if (rs6000_tune
== PROCESSOR_CELL
&& is_nonpipeline_insn (insn
))
30514 cached_can_issue_more
= more
- 1;
30515 return cached_can_issue_more
;
30519 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
30521 int r
= rs6000_variable_issue_1 (insn
, more
);
30523 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
30527 /* Adjust the cost of a scheduling dependency. Return the new cost of
30528 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30531 rs6000_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
30534 enum attr_type attr_type
;
30536 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
30543 /* Data dependency; DEP_INSN writes a register that INSN reads
30544 some cycles later. */
30546 /* Separate a load from a narrower, dependent store. */
30547 if ((rs6000_sched_groups
|| rs6000_tune
== PROCESSOR_POWER9
)
30548 && GET_CODE (PATTERN (insn
)) == SET
30549 && GET_CODE (PATTERN (dep_insn
)) == SET
30550 && MEM_P (XEXP (PATTERN (insn
), 1))
30551 && MEM_P (XEXP (PATTERN (dep_insn
), 0))
30552 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
30553 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
30556 attr_type
= get_attr_type (insn
);
30561 /* Tell the first scheduling pass about the latency between
30562 a mtctr and bctr (and mtlr and br/blr). The first
30563 scheduling pass will not know about this latency since
30564 the mtctr instruction, which has the latency associated
30565 to it, will be generated by reload. */
30568 /* Leave some extra cycles between a compare and its
30569 dependent branch, to inhibit expensive mispredicts. */
30570 if ((rs6000_tune
== PROCESSOR_PPC603
30571 || rs6000_tune
== PROCESSOR_PPC604
30572 || rs6000_tune
== PROCESSOR_PPC604e
30573 || rs6000_tune
== PROCESSOR_PPC620
30574 || rs6000_tune
== PROCESSOR_PPC630
30575 || rs6000_tune
== PROCESSOR_PPC750
30576 || rs6000_tune
== PROCESSOR_PPC7400
30577 || rs6000_tune
== PROCESSOR_PPC7450
30578 || rs6000_tune
== PROCESSOR_PPCE5500
30579 || rs6000_tune
== PROCESSOR_PPCE6500
30580 || rs6000_tune
== PROCESSOR_POWER4
30581 || rs6000_tune
== PROCESSOR_POWER5
30582 || rs6000_tune
== PROCESSOR_POWER7
30583 || rs6000_tune
== PROCESSOR_POWER8
30584 || rs6000_tune
== PROCESSOR_POWER9
30585 || rs6000_tune
== PROCESSOR_CELL
)
30586 && recog_memoized (dep_insn
)
30587 && (INSN_CODE (dep_insn
) >= 0))
30589 switch (get_attr_type (dep_insn
))
30592 case TYPE_FPCOMPARE
:
30593 case TYPE_CR_LOGICAL
:
30597 if (get_attr_dot (dep_insn
) == DOT_YES
)
30602 if (get_attr_dot (dep_insn
) == DOT_YES
30603 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
30614 if ((rs6000_tune
== PROCESSOR_POWER6
)
30615 && recog_memoized (dep_insn
)
30616 && (INSN_CODE (dep_insn
) >= 0))
30619 if (GET_CODE (PATTERN (insn
)) != SET
)
30620 /* If this happens, we have to extend this to schedule
30621 optimally. Return default for now. */
30624 /* Adjust the cost for the case where the value written
30625 by a fixed point operation is used as the address
30626 gen value on a store. */
30627 switch (get_attr_type (dep_insn
))
30632 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30633 return get_attr_sign_extend (dep_insn
)
30634 == SIGN_EXTEND_YES
? 6 : 4;
30639 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30640 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30650 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30658 if (get_attr_update (dep_insn
) == UPDATE_YES
30659 && ! rs6000_store_data_bypass_p (dep_insn
, insn
))
30665 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30671 if (! rs6000_store_data_bypass_p (dep_insn
, insn
))
30672 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30682 if ((rs6000_tune
== PROCESSOR_POWER6
)
30683 && recog_memoized (dep_insn
)
30684 && (INSN_CODE (dep_insn
) >= 0))
30687 /* Adjust the cost for the case where the value written
30688 by a fixed point instruction is used within the address
30689 gen portion of a subsequent load(u)(x) */
30690 switch (get_attr_type (dep_insn
))
30695 if (set_to_load_agen (dep_insn
, insn
))
30696 return get_attr_sign_extend (dep_insn
)
30697 == SIGN_EXTEND_YES
? 6 : 4;
30702 if (set_to_load_agen (dep_insn
, insn
))
30703 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
30713 if (set_to_load_agen (dep_insn
, insn
))
30721 if (get_attr_update (dep_insn
) == UPDATE_YES
30722 && set_to_load_agen (dep_insn
, insn
))
30728 if (set_to_load_agen (dep_insn
, insn
))
30734 if (set_to_load_agen (dep_insn
, insn
))
30735 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
30745 if ((rs6000_tune
== PROCESSOR_POWER6
)
30746 && get_attr_update (insn
) == UPDATE_NO
30747 && recog_memoized (dep_insn
)
30748 && (INSN_CODE (dep_insn
) >= 0)
30749 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
30756 /* Fall out to return default cost. */
30760 case REG_DEP_OUTPUT
:
30761 /* Output dependency; DEP_INSN writes a register that INSN writes some
30763 if ((rs6000_tune
== PROCESSOR_POWER6
)
30764 && recog_memoized (dep_insn
)
30765 && (INSN_CODE (dep_insn
) >= 0))
30767 attr_type
= get_attr_type (insn
);
30772 case TYPE_FPSIMPLE
:
30773 if (get_attr_type (dep_insn
) == TYPE_FP
30774 || get_attr_type (dep_insn
) == TYPE_FPSIMPLE
)
30778 if (get_attr_update (insn
) == UPDATE_NO
30779 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
30786 /* Fall through, no cost for output dependency. */
30790 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30795 gcc_unreachable ();
30801 /* Debug version of rs6000_adjust_cost. */
30804 rs6000_debug_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
30805 int cost
, unsigned int dw
)
30807 int ret
= rs6000_adjust_cost (insn
, dep_type
, dep_insn
, cost
, dw
);
30815 default: dep
= "unknown depencency"; break;
30816 case REG_DEP_TRUE
: dep
= "data dependency"; break;
30817 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
30818 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
30822 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30823 "%s, insn:\n", ret
, cost
, dep
);
30831 /* The function returns a true if INSN is microcoded.
30832 Return false otherwise. */
30835 is_microcoded_insn (rtx_insn
*insn
)
30837 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30838 || GET_CODE (PATTERN (insn
)) == USE
30839 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30842 if (rs6000_tune
== PROCESSOR_CELL
)
30843 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
30845 if (rs6000_sched_groups
30846 && (rs6000_tune
== PROCESSOR_POWER4
|| rs6000_tune
== PROCESSOR_POWER5
))
30848 enum attr_type type
= get_attr_type (insn
);
30849 if ((type
== TYPE_LOAD
30850 && get_attr_update (insn
) == UPDATE_YES
30851 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
30852 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
30853 && get_attr_update (insn
) == UPDATE_YES
30854 && get_attr_indexed (insn
) == INDEXED_YES
)
30855 || type
== TYPE_MFCR
)
30862 /* The function returns true if INSN is cracked into 2 instructions
30863 by the processor (and therefore occupies 2 issue slots). */
30866 is_cracked_insn (rtx_insn
*insn
)
30868 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30869 || GET_CODE (PATTERN (insn
)) == USE
30870 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30873 if (rs6000_sched_groups
30874 && (rs6000_tune
== PROCESSOR_POWER4
|| rs6000_tune
== PROCESSOR_POWER5
))
30876 enum attr_type type
= get_attr_type (insn
);
30877 if ((type
== TYPE_LOAD
30878 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
30879 && get_attr_update (insn
) == UPDATE_NO
)
30880 || (type
== TYPE_LOAD
30881 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
30882 && get_attr_update (insn
) == UPDATE_YES
30883 && get_attr_indexed (insn
) == INDEXED_NO
)
30884 || (type
== TYPE_STORE
30885 && get_attr_update (insn
) == UPDATE_YES
30886 && get_attr_indexed (insn
) == INDEXED_NO
)
30887 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
30888 && get_attr_update (insn
) == UPDATE_YES
)
30889 || (type
== TYPE_CR_LOGICAL
30890 && get_attr_cr_logical_3op (insn
) == CR_LOGICAL_3OP_YES
)
30891 || (type
== TYPE_EXTS
30892 && get_attr_dot (insn
) == DOT_YES
)
30893 || (type
== TYPE_SHIFT
30894 && get_attr_dot (insn
) == DOT_YES
30895 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
30896 || (type
== TYPE_MUL
30897 && get_attr_dot (insn
) == DOT_YES
)
30898 || type
== TYPE_DIV
30899 || (type
== TYPE_INSERT
30900 && get_attr_size (insn
) == SIZE_32
))
30907 /* The function returns true if INSN can be issued only from
30908 the branch slot. */
30911 is_branch_slot_insn (rtx_insn
*insn
)
30913 if (!insn
|| !NONDEBUG_INSN_P (insn
)
30914 || GET_CODE (PATTERN (insn
)) == USE
30915 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
30918 if (rs6000_sched_groups
)
30920 enum attr_type type
= get_attr_type (insn
);
30921 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
30929 /* The function returns true if out_inst sets a value that is
30930 used in the address generation computation of in_insn */
30932 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
30934 rtx out_set
, in_set
;
30936 /* For performance reasons, only handle the simple case where
30937 both loads are a single_set. */
30938 out_set
= single_set (out_insn
);
30941 in_set
= single_set (in_insn
);
30943 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
30949 /* Try to determine base/offset/size parts of the given MEM.
30950 Return true if successful, false if all the values couldn't
30953 This function only looks for REG or REG+CONST address forms.
30954 REG+REG address form will return false. */
30957 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
30958 HOST_WIDE_INT
*size
)
30961 if MEM_SIZE_KNOWN_P (mem
)
30962 *size
= MEM_SIZE (mem
);
30966 addr_rtx
= (XEXP (mem
, 0));
30967 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
30968 addr_rtx
= XEXP (addr_rtx
, 1);
30971 while (GET_CODE (addr_rtx
) == PLUS
30972 && CONST_INT_P (XEXP (addr_rtx
, 1)))
30974 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
30975 addr_rtx
= XEXP (addr_rtx
, 0);
30977 if (!REG_P (addr_rtx
))
30984 /* The function returns true if the target storage location of
30985 mem1 is adjacent to the target storage location of mem2 */
30986 /* Return 1 if memory locations are adjacent. */
30989 adjacent_mem_locations (rtx mem1
, rtx mem2
)
30992 HOST_WIDE_INT off1
, size1
, off2
, size2
;
30994 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
30995 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
30996 return ((REGNO (reg1
) == REGNO (reg2
))
30997 && ((off1
+ size1
== off2
)
30998 || (off2
+ size2
== off1
)));
31003 /* This function returns true if it can be determined that the two MEM
31004 locations overlap by at least 1 byte based on base reg/offset/size. */
31007 mem_locations_overlap (rtx mem1
, rtx mem2
)
31010 HOST_WIDE_INT off1
, size1
, off2
, size2
;
31012 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
31013 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
31014 return ((REGNO (reg1
) == REGNO (reg2
))
31015 && (((off1
<= off2
) && (off1
+ size1
> off2
))
31016 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
31021 /* A C statement (sans semicolon) to update the integer scheduling
31022 priority INSN_PRIORITY (INSN). Increase the priority to execute the
31023 INSN earlier, reduce the priority to execute INSN later. Do not
31024 define this macro if you do not need to adjust the scheduling
31025 priorities of insns. */
31028 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
31030 rtx load_mem
, str_mem
;
31031 /* On machines (like the 750) which have asymmetric integer units,
31032 where one integer unit can do multiply and divides and the other
31033 can't, reduce the priority of multiply/divide so it is scheduled
31034 before other integer operations. */
31037 if (! INSN_P (insn
))
31040 if (GET_CODE (PATTERN (insn
)) == USE
)
31043 switch (rs6000_tune
) {
31044 case PROCESSOR_PPC750
:
31045 switch (get_attr_type (insn
))
31052 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
31053 priority
, priority
);
31054 if (priority
>= 0 && priority
< 0x01000000)
31061 if (insn_must_be_first_in_group (insn
)
31062 && reload_completed
31063 && current_sched_info
->sched_max_insns_priority
31064 && rs6000_sched_restricted_insns_priority
)
31067 /* Prioritize insns that can be dispatched only in the first
31069 if (rs6000_sched_restricted_insns_priority
== 1)
31070 /* Attach highest priority to insn. This means that in
31071 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
31072 precede 'priority' (critical path) considerations. */
31073 return current_sched_info
->sched_max_insns_priority
;
31074 else if (rs6000_sched_restricted_insns_priority
== 2)
31075 /* Increase priority of insn by a minimal amount. This means that in
31076 haifa-sched.c:ready_sort(), only 'priority' (critical path)
31077 considerations precede dispatch-slot restriction considerations. */
31078 return (priority
+ 1);
31081 if (rs6000_tune
== PROCESSOR_POWER6
31082 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
31083 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
31084 /* Attach highest priority to insn if the scheduler has just issued two
31085 stores and this instruction is a load, or two loads and this instruction
31086 is a store. Power6 wants loads and stores scheduled alternately
31088 return current_sched_info
->sched_max_insns_priority
;
31093 /* Return true if the instruction is nonpipelined on the Cell. */
31095 is_nonpipeline_insn (rtx_insn
*insn
)
31097 enum attr_type type
;
31098 if (!insn
|| !NONDEBUG_INSN_P (insn
)
31099 || GET_CODE (PATTERN (insn
)) == USE
31100 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31103 type
= get_attr_type (insn
);
31104 if (type
== TYPE_MUL
31105 || type
== TYPE_DIV
31106 || type
== TYPE_SDIV
31107 || type
== TYPE_DDIV
31108 || type
== TYPE_SSQRT
31109 || type
== TYPE_DSQRT
31110 || type
== TYPE_MFCR
31111 || type
== TYPE_MFCRF
31112 || type
== TYPE_MFJMPR
)
31120 /* Return how many instructions the machine can issue per cycle. */
31123 rs6000_issue_rate (void)
31125 /* Unless scheduling for register pressure, use issue rate of 1 for
31126 first scheduling pass to decrease degradation. */
31127 if (!reload_completed
&& !flag_sched_pressure
)
31130 switch (rs6000_tune
) {
31131 case PROCESSOR_RS64A
:
31132 case PROCESSOR_PPC601
: /* ? */
31133 case PROCESSOR_PPC7450
:
31135 case PROCESSOR_PPC440
:
31136 case PROCESSOR_PPC603
:
31137 case PROCESSOR_PPC750
:
31138 case PROCESSOR_PPC7400
:
31139 case PROCESSOR_PPC8540
:
31140 case PROCESSOR_PPC8548
:
31141 case PROCESSOR_CELL
:
31142 case PROCESSOR_PPCE300C2
:
31143 case PROCESSOR_PPCE300C3
:
31144 case PROCESSOR_PPCE500MC
:
31145 case PROCESSOR_PPCE500MC64
:
31146 case PROCESSOR_PPCE5500
:
31147 case PROCESSOR_PPCE6500
:
31148 case PROCESSOR_TITAN
:
31150 case PROCESSOR_PPC476
:
31151 case PROCESSOR_PPC604
:
31152 case PROCESSOR_PPC604e
:
31153 case PROCESSOR_PPC620
:
31154 case PROCESSOR_PPC630
:
31156 case PROCESSOR_POWER4
:
31157 case PROCESSOR_POWER5
:
31158 case PROCESSOR_POWER6
:
31159 case PROCESSOR_POWER7
:
31161 case PROCESSOR_POWER8
:
31163 case PROCESSOR_POWER9
:
31170 /* Return how many instructions to look ahead for better insn
31174 rs6000_use_sched_lookahead (void)
31176 switch (rs6000_tune
)
31178 case PROCESSOR_PPC8540
:
31179 case PROCESSOR_PPC8548
:
31182 case PROCESSOR_CELL
:
31183 return (reload_completed
? 8 : 0);
31190 /* We are choosing insn from the ready queue. Return zero if INSN can be
31193 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
31195 if (ready_index
== 0)
31198 if (rs6000_tune
!= PROCESSOR_CELL
)
31201 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
31203 if (!reload_completed
31204 || is_nonpipeline_insn (insn
)
31205 || is_microcoded_insn (insn
))
31211 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
31212 and return true. */
31215 find_mem_ref (rtx pat
, rtx
*mem_ref
)
31220 /* stack_tie does not produce any real memory traffic. */
31221 if (tie_operand (pat
, VOIDmode
))
31230 /* Recursively process the pattern. */
31231 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
31233 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
31237 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
31240 else if (fmt
[i
] == 'E')
31241 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
31243 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
31251 /* Determine if PAT is a PATTERN of a load insn. */
31254 is_load_insn1 (rtx pat
, rtx
*load_mem
)
31256 if (!pat
|| pat
== NULL_RTX
)
31259 if (GET_CODE (pat
) == SET
)
31260 return find_mem_ref (SET_SRC (pat
), load_mem
);
31262 if (GET_CODE (pat
) == PARALLEL
)
31266 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
31267 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
31274 /* Determine if INSN loads from memory. */
31277 is_load_insn (rtx insn
, rtx
*load_mem
)
31279 if (!insn
|| !INSN_P (insn
))
31285 return is_load_insn1 (PATTERN (insn
), load_mem
);
31288 /* Determine if PAT is a PATTERN of a store insn. */
31291 is_store_insn1 (rtx pat
, rtx
*str_mem
)
31293 if (!pat
|| pat
== NULL_RTX
)
31296 if (GET_CODE (pat
) == SET
)
31297 return find_mem_ref (SET_DEST (pat
), str_mem
);
31299 if (GET_CODE (pat
) == PARALLEL
)
31303 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
31304 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
31311 /* Determine if INSN stores to memory. */
31314 is_store_insn (rtx insn
, rtx
*str_mem
)
31316 if (!insn
|| !INSN_P (insn
))
31319 return is_store_insn1 (PATTERN (insn
), str_mem
);
31322 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31325 is_power9_pairable_vec_type (enum attr_type type
)
31329 case TYPE_VECSIMPLE
:
31330 case TYPE_VECCOMPLEX
:
31334 case TYPE_VECFLOAT
:
31336 case TYPE_VECDOUBLE
:
31344 /* Returns whether the dependence between INSN and NEXT is considered
31345 costly by the given target. */
31348 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
31352 rtx load_mem
, str_mem
;
31354 /* If the flag is not enabled - no dependence is considered costly;
31355 allow all dependent insns in the same group.
31356 This is the most aggressive option. */
31357 if (rs6000_sched_costly_dep
== no_dep_costly
)
31360 /* If the flag is set to 1 - a dependence is always considered costly;
31361 do not allow dependent instructions in the same group.
31362 This is the most conservative option. */
31363 if (rs6000_sched_costly_dep
== all_deps_costly
)
31366 insn
= DEP_PRO (dep
);
31367 next
= DEP_CON (dep
);
31369 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
31370 && is_load_insn (next
, &load_mem
)
31371 && is_store_insn (insn
, &str_mem
))
31372 /* Prevent load after store in the same group. */
31375 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
31376 && is_load_insn (next
, &load_mem
)
31377 && is_store_insn (insn
, &str_mem
)
31378 && DEP_TYPE (dep
) == REG_DEP_TRUE
31379 && mem_locations_overlap(str_mem
, load_mem
))
31380 /* Prevent load after store in the same group if it is a true
31384 /* The flag is set to X; dependences with latency >= X are considered costly,
31385 and will not be scheduled in the same group. */
31386 if (rs6000_sched_costly_dep
<= max_dep_latency
31387 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
31393 /* Return the next insn after INSN that is found before TAIL is reached,
31394 skipping any "non-active" insns - insns that will not actually occupy
31395 an issue slot. Return NULL_RTX if such an insn is not found. */
31398 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
31400 if (insn
== NULL_RTX
|| insn
== tail
)
31405 insn
= NEXT_INSN (insn
);
31406 if (insn
== NULL_RTX
|| insn
== tail
)
31410 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
31411 || (NONJUMP_INSN_P (insn
)
31412 && GET_CODE (PATTERN (insn
)) != USE
31413 && GET_CODE (PATTERN (insn
)) != CLOBBER
31414 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
31420 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31423 power9_sched_reorder2 (rtx_insn
**ready
, int lastpos
)
31428 enum attr_type type
, type2
;
31430 type
= get_attr_type (last_scheduled_insn
);
31432 /* Try to issue fixed point divides back-to-back in pairs so they will be
31433 routed to separate execution units and execute in parallel. */
31434 if (type
== TYPE_DIV
&& divide_cnt
== 0)
31436 /* First divide has been scheduled. */
31439 /* Scan the ready list looking for another divide, if found move it
31440 to the end of the list so it is chosen next. */
31444 if (recog_memoized (ready
[pos
]) >= 0
31445 && get_attr_type (ready
[pos
]) == TYPE_DIV
)
31448 for (i
= pos
; i
< lastpos
; i
++)
31449 ready
[i
] = ready
[i
+ 1];
31450 ready
[lastpos
] = tmp
;
31458 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31461 /* The best dispatch throughput for vector and vector load insns can be
31462 achieved by interleaving a vector and vector load such that they'll
31463 dispatch to the same superslice. If this pairing cannot be achieved
31464 then it is best to pair vector insns together and vector load insns
31467 To aid in this pairing, vec_pairing maintains the current state with
31468 the following values:
31470 0 : Initial state, no vecload/vector pairing has been started.
31472 1 : A vecload or vector insn has been issued and a candidate for
31473 pairing has been found and moved to the end of the ready
31475 if (type
== TYPE_VECLOAD
)
31477 /* Issued a vecload. */
31478 if (vec_pairing
== 0)
31480 int vecload_pos
= -1;
31481 /* We issued a single vecload, look for a vector insn to pair it
31482 with. If one isn't found, try to pair another vecload. */
31486 if (recog_memoized (ready
[pos
]) >= 0)
31488 type2
= get_attr_type (ready
[pos
]);
31489 if (is_power9_pairable_vec_type (type2
))
31491 /* Found a vector insn to pair with, move it to the
31492 end of the ready list so it is scheduled next. */
31494 for (i
= pos
; i
< lastpos
; i
++)
31495 ready
[i
] = ready
[i
+ 1];
31496 ready
[lastpos
] = tmp
;
31498 return cached_can_issue_more
;
31500 else if (type2
== TYPE_VECLOAD
&& vecload_pos
== -1)
31501 /* Remember position of first vecload seen. */
31506 if (vecload_pos
>= 0)
31508 /* Didn't find a vector to pair with but did find a vecload,
31509 move it to the end of the ready list. */
31510 tmp
= ready
[vecload_pos
];
31511 for (i
= vecload_pos
; i
< lastpos
; i
++)
31512 ready
[i
] = ready
[i
+ 1];
31513 ready
[lastpos
] = tmp
;
31515 return cached_can_issue_more
;
31519 else if (is_power9_pairable_vec_type (type
))
31521 /* Issued a vector operation. */
31522 if (vec_pairing
== 0)
31525 /* We issued a single vector insn, look for a vecload to pair it
31526 with. If one isn't found, try to pair another vector. */
31530 if (recog_memoized (ready
[pos
]) >= 0)
31532 type2
= get_attr_type (ready
[pos
]);
31533 if (type2
== TYPE_VECLOAD
)
31535 /* Found a vecload insn to pair with, move it to the
31536 end of the ready list so it is scheduled next. */
31538 for (i
= pos
; i
< lastpos
; i
++)
31539 ready
[i
] = ready
[i
+ 1];
31540 ready
[lastpos
] = tmp
;
31542 return cached_can_issue_more
;
31544 else if (is_power9_pairable_vec_type (type2
)
31546 /* Remember position of first vector insn seen. */
31553 /* Didn't find a vecload to pair with but did find a vector
31554 insn, move it to the end of the ready list. */
31555 tmp
= ready
[vec_pos
];
31556 for (i
= vec_pos
; i
< lastpos
; i
++)
31557 ready
[i
] = ready
[i
+ 1];
31558 ready
[lastpos
] = tmp
;
31560 return cached_can_issue_more
;
31565 /* We've either finished a vec/vecload pair, couldn't find an insn to
31566 continue the current pair, or the last insn had nothing to do with
31567 with pairing. In any case, reset the state. */
31571 return cached_can_issue_more
;
31574 /* We are about to begin issuing insns for this clock cycle. */
31577 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
31578 rtx_insn
**ready ATTRIBUTE_UNUSED
,
31579 int *pn_ready ATTRIBUTE_UNUSED
,
31580 int clock_var ATTRIBUTE_UNUSED
)
31582 int n_ready
= *pn_ready
;
31585 fprintf (dump
, "// rs6000_sched_reorder :\n");
31587 /* Reorder the ready list, if the second to last ready insn
31588 is a nonepipeline insn. */
31589 if (rs6000_tune
== PROCESSOR_CELL
&& n_ready
> 1)
31591 if (is_nonpipeline_insn (ready
[n_ready
- 1])
31592 && (recog_memoized (ready
[n_ready
- 2]) > 0))
31593 /* Simply swap first two insns. */
31594 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
31597 if (rs6000_tune
== PROCESSOR_POWER6
)
31598 load_store_pendulum
= 0;
31600 return rs6000_issue_rate ();
31603 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31606 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
31607 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
31610 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
31612 /* For Power6, we need to handle some special cases to try and keep the
31613 store queue from overflowing and triggering expensive flushes.
31615 This code monitors how load and store instructions are being issued
31616 and skews the ready list one way or the other to increase the likelihood
31617 that a desired instruction is issued at the proper time.
31619 A couple of things are done. First, we maintain a "load_store_pendulum"
31620 to track the current state of load/store issue.
31622 - If the pendulum is at zero, then no loads or stores have been
31623 issued in the current cycle so we do nothing.
31625 - If the pendulum is 1, then a single load has been issued in this
31626 cycle and we attempt to locate another load in the ready list to
31629 - If the pendulum is -2, then two stores have already been
31630 issued in this cycle, so we increase the priority of the first load
31631 in the ready list to increase it's likelihood of being chosen first
31634 - If the pendulum is -1, then a single store has been issued in this
31635 cycle and we attempt to locate another store in the ready list to
31636 issue with it, preferring a store to an adjacent memory location to
31637 facilitate store pairing in the store queue.
31639 - If the pendulum is 2, then two loads have already been
31640 issued in this cycle, so we increase the priority of the first store
31641 in the ready list to increase it's likelihood of being chosen first
31644 - If the pendulum < -2 or > 2, then do nothing.
31646 Note: This code covers the most common scenarios. There exist non
31647 load/store instructions which make use of the LSU and which
31648 would need to be accounted for to strictly model the behavior
31649 of the machine. Those instructions are currently unaccounted
31650 for to help minimize compile time overhead of this code.
31652 if (rs6000_tune
== PROCESSOR_POWER6
&& last_scheduled_insn
)
31657 rtx load_mem
, str_mem
;
31659 if (is_store_insn (last_scheduled_insn
, &str_mem
))
31660 /* Issuing a store, swing the load_store_pendulum to the left */
31661 load_store_pendulum
--;
31662 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
31663 /* Issuing a load, swing the load_store_pendulum to the right */
31664 load_store_pendulum
++;
31666 return cached_can_issue_more
;
31668 /* If the pendulum is balanced, or there is only one instruction on
31669 the ready list, then all is well, so return. */
31670 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
31671 return cached_can_issue_more
;
31673 if (load_store_pendulum
== 1)
31675 /* A load has been issued in this cycle. Scan the ready list
31676 for another load to issue with it */
31681 if (is_load_insn (ready
[pos
], &load_mem
))
31683 /* Found a load. Move it to the head of the ready list,
31684 and adjust it's priority so that it is more likely to
31687 for (i
=pos
; i
<*pn_ready
-1; i
++)
31688 ready
[i
] = ready
[i
+ 1];
31689 ready
[*pn_ready
-1] = tmp
;
31691 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31692 INSN_PRIORITY (tmp
)++;
31698 else if (load_store_pendulum
== -2)
31700 /* Two stores have been issued in this cycle. Increase the
31701 priority of the first load in the ready list to favor it for
31702 issuing in the next cycle. */
31707 if (is_load_insn (ready
[pos
], &load_mem
)
31709 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31711 INSN_PRIORITY (ready
[pos
])++;
31713 /* Adjust the pendulum to account for the fact that a load
31714 was found and increased in priority. This is to prevent
31715 increasing the priority of multiple loads */
31716 load_store_pendulum
--;
31723 else if (load_store_pendulum
== -1)
31725 /* A store has been issued in this cycle. Scan the ready list for
31726 another store to issue with it, preferring a store to an adjacent
31728 int first_store_pos
= -1;
31734 if (is_store_insn (ready
[pos
], &str_mem
))
31737 /* Maintain the index of the first store found on the
31739 if (first_store_pos
== -1)
31740 first_store_pos
= pos
;
31742 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
31743 && adjacent_mem_locations (str_mem
, str_mem2
))
31745 /* Found an adjacent store. Move it to the head of the
31746 ready list, and adjust it's priority so that it is
31747 more likely to stay there */
31749 for (i
=pos
; i
<*pn_ready
-1; i
++)
31750 ready
[i
] = ready
[i
+ 1];
31751 ready
[*pn_ready
-1] = tmp
;
31753 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31754 INSN_PRIORITY (tmp
)++;
31756 first_store_pos
= -1;
31764 if (first_store_pos
>= 0)
31766 /* An adjacent store wasn't found, but a non-adjacent store was,
31767 so move the non-adjacent store to the front of the ready
31768 list, and adjust its priority so that it is more likely to
31770 tmp
= ready
[first_store_pos
];
31771 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
31772 ready
[i
] = ready
[i
+ 1];
31773 ready
[*pn_ready
-1] = tmp
;
31774 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
31775 INSN_PRIORITY (tmp
)++;
31778 else if (load_store_pendulum
== 2)
31780 /* Two loads have been issued in this cycle. Increase the priority
31781 of the first store in the ready list to favor it for issuing in
31787 if (is_store_insn (ready
[pos
], &str_mem
)
31789 && INSN_PRIORITY_KNOWN (ready
[pos
]))
31791 INSN_PRIORITY (ready
[pos
])++;
31793 /* Adjust the pendulum to account for the fact that a store
31794 was found and increased in priority. This is to prevent
31795 increasing the priority of multiple stores */
31796 load_store_pendulum
++;
31805 /* Do Power9 dependent reordering if necessary. */
31806 if (rs6000_tune
== PROCESSOR_POWER9
&& last_scheduled_insn
31807 && recog_memoized (last_scheduled_insn
) >= 0)
31808 return power9_sched_reorder2 (ready
, *pn_ready
- 1);
31810 return cached_can_issue_more
;
31813 /* Return whether the presence of INSN causes a dispatch group termination
31814 of group WHICH_GROUP.
31816 If WHICH_GROUP == current_group, this function will return true if INSN
31817 causes the termination of the current group (i.e, the dispatch group to
31818 which INSN belongs). This means that INSN will be the last insn in the
31819 group it belongs to.
31821 If WHICH_GROUP == previous_group, this function will return true if INSN
31822 causes the termination of the previous group (i.e, the dispatch group that
31823 precedes the group to which INSN belongs). This means that INSN will be
31824 the first insn in the group it belongs to). */
31827 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
31834 first
= insn_must_be_first_in_group (insn
);
31835 last
= insn_must_be_last_in_group (insn
);
31840 if (which_group
== current_group
)
31842 else if (which_group
== previous_group
)
31850 insn_must_be_first_in_group (rtx_insn
*insn
)
31852 enum attr_type type
;
31856 || DEBUG_INSN_P (insn
)
31857 || GET_CODE (PATTERN (insn
)) == USE
31858 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31861 switch (rs6000_tune
)
31863 case PROCESSOR_POWER5
:
31864 if (is_cracked_insn (insn
))
31867 case PROCESSOR_POWER4
:
31868 if (is_microcoded_insn (insn
))
31871 if (!rs6000_sched_groups
)
31874 type
= get_attr_type (insn
);
31881 case TYPE_CR_LOGICAL
:
31894 case PROCESSOR_POWER6
:
31895 type
= get_attr_type (insn
);
31904 case TYPE_FPCOMPARE
:
31915 if (get_attr_dot (insn
) == DOT_NO
31916 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31921 if (get_attr_size (insn
) == SIZE_32
)
31929 if (get_attr_update (insn
) == UPDATE_YES
)
31937 case PROCESSOR_POWER7
:
31938 type
= get_attr_type (insn
);
31942 case TYPE_CR_LOGICAL
:
31956 if (get_attr_dot (insn
) == DOT_YES
)
31961 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31962 || get_attr_update (insn
) == UPDATE_YES
)
31969 if (get_attr_update (insn
) == UPDATE_YES
)
31977 case PROCESSOR_POWER8
:
31978 type
= get_attr_type (insn
);
31982 case TYPE_CR_LOGICAL
:
31990 case TYPE_VECSTORE
:
31997 if (get_attr_dot (insn
) == DOT_YES
)
32002 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
32003 || get_attr_update (insn
) == UPDATE_YES
)
32008 if (get_attr_update (insn
) == UPDATE_YES
32009 && get_attr_indexed (insn
) == INDEXED_YES
)
32025 insn_must_be_last_in_group (rtx_insn
*insn
)
32027 enum attr_type type
;
32031 || DEBUG_INSN_P (insn
)
32032 || GET_CODE (PATTERN (insn
)) == USE
32033 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
32036 switch (rs6000_tune
) {
32037 case PROCESSOR_POWER4
:
32038 case PROCESSOR_POWER5
:
32039 if (is_microcoded_insn (insn
))
32042 if (is_branch_slot_insn (insn
))
32046 case PROCESSOR_POWER6
:
32047 type
= get_attr_type (insn
);
32055 case TYPE_FPCOMPARE
:
32066 if (get_attr_dot (insn
) == DOT_NO
32067 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
32072 if (get_attr_size (insn
) == SIZE_32
)
32080 case PROCESSOR_POWER7
:
32081 type
= get_attr_type (insn
);
32091 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
32092 && get_attr_update (insn
) == UPDATE_YES
)
32097 if (get_attr_update (insn
) == UPDATE_YES
32098 && get_attr_indexed (insn
) == INDEXED_YES
)
32106 case PROCESSOR_POWER8
:
32107 type
= get_attr_type (insn
);
32119 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
32120 && get_attr_update (insn
) == UPDATE_YES
)
32125 if (get_attr_update (insn
) == UPDATE_YES
32126 && get_attr_indexed (insn
) == INDEXED_YES
)
32141 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
32142 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
32145 is_costly_group (rtx
*group_insns
, rtx next_insn
)
32148 int issue_rate
= rs6000_issue_rate ();
32150 for (i
= 0; i
< issue_rate
; i
++)
32152 sd_iterator_def sd_it
;
32154 rtx insn
= group_insns
[i
];
32159 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
32161 rtx next
= DEP_CON (dep
);
32163 if (next
== next_insn
32164 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
32172 /* Utility of the function redefine_groups.
32173 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
32174 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
32175 to keep it "far" (in a separate group) from GROUP_INSNS, following
32176 one of the following schemes, depending on the value of the flag
32177 -minsert_sched_nops = X:
32178 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
32179 in order to force NEXT_INSN into a separate group.
32180 (2) X < sched_finish_regroup_exact: insert exactly X nops.
32181 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
32182 insertion (has a group just ended, how many vacant issue slots remain in the
32183 last group, and how many dispatch groups were encountered so far). */
32186 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
32187 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
32192 int issue_rate
= rs6000_issue_rate ();
32193 bool end
= *group_end
;
32196 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
32197 return can_issue_more
;
32199 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
32200 return can_issue_more
;
32202 force
= is_costly_group (group_insns
, next_insn
);
32204 return can_issue_more
;
32206 if (sched_verbose
> 6)
32207 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
32208 *group_count
,can_issue_more
);
32210 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
32213 can_issue_more
= 0;
32215 /* Since only a branch can be issued in the last issue_slot, it is
32216 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
32217 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
32218 in this case the last nop will start a new group and the branch
32219 will be forced to the new group. */
32220 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
32223 /* Do we have a special group ending nop? */
32224 if (rs6000_tune
== PROCESSOR_POWER6
|| rs6000_tune
== PROCESSOR_POWER7
32225 || rs6000_tune
== PROCESSOR_POWER8
)
32227 nop
= gen_group_ending_nop ();
32228 emit_insn_before (nop
, next_insn
);
32229 can_issue_more
= 0;
32232 while (can_issue_more
> 0)
32235 emit_insn_before (nop
, next_insn
);
32243 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
32245 int n_nops
= rs6000_sched_insert_nops
;
32247 /* Nops can't be issued from the branch slot, so the effective
32248 issue_rate for nops is 'issue_rate - 1'. */
32249 if (can_issue_more
== 0)
32250 can_issue_more
= issue_rate
;
32252 if (can_issue_more
== 0)
32254 can_issue_more
= issue_rate
- 1;
32257 for (i
= 0; i
< issue_rate
; i
++)
32259 group_insns
[i
] = 0;
32266 emit_insn_before (nop
, next_insn
);
32267 if (can_issue_more
== issue_rate
- 1) /* new group begins */
32270 if (can_issue_more
== 0)
32272 can_issue_more
= issue_rate
- 1;
32275 for (i
= 0; i
< issue_rate
; i
++)
32277 group_insns
[i
] = 0;
32283 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32286 /* Is next_insn going to start a new group? */
32289 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
32290 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
32291 || (can_issue_more
< issue_rate
&&
32292 insn_terminates_group_p (next_insn
, previous_group
)));
32293 if (*group_end
&& end
)
32296 if (sched_verbose
> 6)
32297 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
32298 *group_count
, can_issue_more
);
32299 return can_issue_more
;
32302 return can_issue_more
;
32305 /* This function tries to synch the dispatch groups that the compiler "sees"
32306 with the dispatch groups that the processor dispatcher is expected to
32307 form in practice. It tries to achieve this synchronization by forcing the
32308 estimated processor grouping on the compiler (as opposed to the function
32309 'pad_goups' which tries to force the scheduler's grouping on the processor).
32311 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32312 examines the (estimated) dispatch groups that will be formed by the processor
32313 dispatcher. It marks these group boundaries to reflect the estimated
32314 processor grouping, overriding the grouping that the scheduler had marked.
32315 Depending on the value of the flag '-minsert-sched-nops' this function can
32316 force certain insns into separate groups or force a certain distance between
32317 them by inserting nops, for example, if there exists a "costly dependence"
32320 The function estimates the group boundaries that the processor will form as
32321 follows: It keeps track of how many vacant issue slots are available after
32322 each insn. A subsequent insn will start a new group if one of the following
32324 - no more vacant issue slots remain in the current dispatch group.
32325 - only the last issue slot, which is the branch slot, is vacant, but the next
32326 insn is not a branch.
32327 - only the last 2 or less issue slots, including the branch slot, are vacant,
32328 which means that a cracked insn (which occupies two issue slots) can't be
32329 issued in this group.
32330 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32331 start a new group. */
32334 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
32337 rtx_insn
*insn
, *next_insn
;
32339 int can_issue_more
;
32342 int group_count
= 0;
32346 issue_rate
= rs6000_issue_rate ();
32347 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
32348 for (i
= 0; i
< issue_rate
; i
++)
32350 group_insns
[i
] = 0;
32352 can_issue_more
= issue_rate
;
32354 insn
= get_next_active_insn (prev_head_insn
, tail
);
32357 while (insn
!= NULL_RTX
)
32359 slot
= (issue_rate
- can_issue_more
);
32360 group_insns
[slot
] = insn
;
32362 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
32363 if (insn_terminates_group_p (insn
, current_group
))
32364 can_issue_more
= 0;
32366 next_insn
= get_next_active_insn (insn
, tail
);
32367 if (next_insn
== NULL_RTX
)
32368 return group_count
+ 1;
32370 /* Is next_insn going to start a new group? */
32372 = (can_issue_more
== 0
32373 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
32374 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
32375 || (can_issue_more
< issue_rate
&&
32376 insn_terminates_group_p (next_insn
, previous_group
)));
32378 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
32379 next_insn
, &group_end
, can_issue_more
,
32385 can_issue_more
= 0;
32386 for (i
= 0; i
< issue_rate
; i
++)
32388 group_insns
[i
] = 0;
32392 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
32393 PUT_MODE (next_insn
, VOIDmode
);
32394 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
32395 PUT_MODE (next_insn
, TImode
);
32398 if (can_issue_more
== 0)
32399 can_issue_more
= issue_rate
;
32402 return group_count
;
32405 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32406 dispatch group boundaries that the scheduler had marked. Pad with nops
32407 any dispatch groups which have vacant issue slots, in order to force the
32408 scheduler's grouping on the processor dispatcher. The function
32409 returns the number of dispatch groups found. */
32412 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
32415 rtx_insn
*insn
, *next_insn
;
32418 int can_issue_more
;
32420 int group_count
= 0;
32422 /* Initialize issue_rate. */
32423 issue_rate
= rs6000_issue_rate ();
32424 can_issue_more
= issue_rate
;
32426 insn
= get_next_active_insn (prev_head_insn
, tail
);
32427 next_insn
= get_next_active_insn (insn
, tail
);
32429 while (insn
!= NULL_RTX
)
32432 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
32434 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
32436 if (next_insn
== NULL_RTX
)
32441 /* If the scheduler had marked group termination at this location
32442 (between insn and next_insn), and neither insn nor next_insn will
32443 force group termination, pad the group with nops to force group
32446 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
32447 && !insn_terminates_group_p (insn
, current_group
)
32448 && !insn_terminates_group_p (next_insn
, previous_group
))
32450 if (!is_branch_slot_insn (next_insn
))
32453 while (can_issue_more
)
32456 emit_insn_before (nop
, next_insn
);
32461 can_issue_more
= issue_rate
;
32466 next_insn
= get_next_active_insn (insn
, tail
);
32469 return group_count
;
32472 /* We're beginning a new block. Initialize data structures as necessary. */
32475 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
32476 int sched_verbose ATTRIBUTE_UNUSED
,
32477 int max_ready ATTRIBUTE_UNUSED
)
32479 last_scheduled_insn
= NULL
;
32480 load_store_pendulum
= 0;
32485 /* The following function is called at the end of scheduling BB.
32486 After reload, it inserts nops at insn group bundling. */
32489 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
32494 fprintf (dump
, "=== Finishing schedule.\n");
32496 if (reload_completed
&& rs6000_sched_groups
)
32498 /* Do not run sched_finish hook when selective scheduling enabled. */
32499 if (sel_sched_p ())
32502 if (rs6000_sched_insert_nops
== sched_finish_none
)
32505 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
32506 n_groups
= pad_groups (dump
, sched_verbose
,
32507 current_sched_info
->prev_head
,
32508 current_sched_info
->next_tail
);
32510 n_groups
= redefine_groups (dump
, sched_verbose
,
32511 current_sched_info
->prev_head
,
32512 current_sched_info
->next_tail
);
32514 if (sched_verbose
>= 6)
32516 fprintf (dump
, "ngroups = %d\n", n_groups
);
32517 print_rtl (dump
, current_sched_info
->prev_head
);
32518 fprintf (dump
, "Done finish_sched\n");
32523 struct rs6000_sched_context
32525 short cached_can_issue_more
;
32526 rtx_insn
*last_scheduled_insn
;
32527 int load_store_pendulum
;
32532 typedef struct rs6000_sched_context rs6000_sched_context_def
;
32533 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
32535 /* Allocate store for new scheduling context. */
32537 rs6000_alloc_sched_context (void)
32539 return xmalloc (sizeof (rs6000_sched_context_def
));
32542 /* If CLEAN_P is true then initializes _SC with clean data,
32543 and from the global context otherwise. */
32545 rs6000_init_sched_context (void *_sc
, bool clean_p
)
32547 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32551 sc
->cached_can_issue_more
= 0;
32552 sc
->last_scheduled_insn
= NULL
;
32553 sc
->load_store_pendulum
= 0;
32554 sc
->divide_cnt
= 0;
32555 sc
->vec_pairing
= 0;
32559 sc
->cached_can_issue_more
= cached_can_issue_more
;
32560 sc
->last_scheduled_insn
= last_scheduled_insn
;
32561 sc
->load_store_pendulum
= load_store_pendulum
;
32562 sc
->divide_cnt
= divide_cnt
;
32563 sc
->vec_pairing
= vec_pairing
;
32567 /* Sets the global scheduling context to the one pointed to by _SC. */
32569 rs6000_set_sched_context (void *_sc
)
32571 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
32573 gcc_assert (sc
!= NULL
);
32575 cached_can_issue_more
= sc
->cached_can_issue_more
;
32576 last_scheduled_insn
= sc
->last_scheduled_insn
;
32577 load_store_pendulum
= sc
->load_store_pendulum
;
32578 divide_cnt
= sc
->divide_cnt
;
32579 vec_pairing
= sc
->vec_pairing
;
32584 rs6000_free_sched_context (void *_sc
)
32586 gcc_assert (_sc
!= NULL
);
32592 rs6000_sched_can_speculate_insn (rtx_insn
*insn
)
32594 switch (get_attr_type (insn
))
32609 /* Length in units of the trampoline for entering a nested function. */
32612 rs6000_trampoline_size (void)
32616 switch (DEFAULT_ABI
)
32619 gcc_unreachable ();
32622 ret
= (TARGET_32BIT
) ? 12 : 24;
32626 gcc_assert (!TARGET_32BIT
);
32632 ret
= (TARGET_32BIT
) ? 40 : 48;
32639 /* Emit RTL insns to initialize the variable parts of a trampoline.
32640 FNADDR is an RTX for the address of the function's pure code.
32641 CXT is an RTX for the static chain value for the function. */
32644 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
32646 int regsize
= (TARGET_32BIT
) ? 4 : 8;
32647 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
32648 rtx ctx_reg
= force_reg (Pmode
, cxt
);
32649 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
32651 switch (DEFAULT_ABI
)
32654 gcc_unreachable ();
32656 /* Under AIX, just build the 3 word function descriptor */
32659 rtx fnmem
, fn_reg
, toc_reg
;
32661 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32662 error ("you cannot take the address of a nested function if you use "
32663 "the %qs option", "-mno-pointers-to-nested-functions");
32665 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
32666 fn_reg
= gen_reg_rtx (Pmode
);
32667 toc_reg
= gen_reg_rtx (Pmode
);
32669 /* Macro to shorten the code expansions below. */
32670 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32672 m_tramp
= replace_equiv_address (m_tramp
, addr
);
32674 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
32675 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
32676 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
32677 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
32678 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
32684 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32688 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
32689 LCT_NORMAL
, VOIDmode
,
32691 GEN_INT (rs6000_trampoline_size ()), SImode
,
32699 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32700 identifier as an argument, so the front end shouldn't look it up. */
32703 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
32705 return is_attribute_p ("altivec", attr_id
);
32708 /* Handle the "altivec" attribute. The attribute may have
32709 arguments as follows:
32711 __attribute__((altivec(vector__)))
32712 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32713 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32715 and may appear more than once (e.g., 'vector bool char') in a
32716 given declaration. */
32719 rs6000_handle_altivec_attribute (tree
*node
,
32720 tree name ATTRIBUTE_UNUSED
,
32722 int flags ATTRIBUTE_UNUSED
,
32723 bool *no_add_attrs
)
32725 tree type
= *node
, result
= NULL_TREE
;
32729 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
32730 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
32731 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
32734 while (POINTER_TYPE_P (type
)
32735 || TREE_CODE (type
) == FUNCTION_TYPE
32736 || TREE_CODE (type
) == METHOD_TYPE
32737 || TREE_CODE (type
) == ARRAY_TYPE
)
32738 type
= TREE_TYPE (type
);
32740 mode
= TYPE_MODE (type
);
32742 /* Check for invalid AltiVec type qualifiers. */
32743 if (type
== long_double_type_node
)
32744 error ("use of %<long double%> in AltiVec types is invalid");
32745 else if (type
== boolean_type_node
)
32746 error ("use of boolean types in AltiVec types is invalid");
32747 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
32748 error ("use of %<complex%> in AltiVec types is invalid");
32749 else if (DECIMAL_FLOAT_MODE_P (mode
))
32750 error ("use of decimal floating point types in AltiVec types is invalid");
32751 else if (!TARGET_VSX
)
32753 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
32756 error ("use of %<long%> in AltiVec types is invalid for "
32757 "64-bit code without %qs", "-mvsx");
32758 else if (rs6000_warn_altivec_long
)
32759 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32762 else if (type
== long_long_unsigned_type_node
32763 || type
== long_long_integer_type_node
)
32764 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32766 else if (type
== double_type_node
)
32767 error ("use of %<double%> in AltiVec types is invalid without %qs",
32771 switch (altivec_type
)
32774 unsigned_p
= TYPE_UNSIGNED (type
);
32778 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
32781 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
32784 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
32787 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
32790 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
32792 case E_SFmode
: result
= V4SF_type_node
; break;
32793 case E_DFmode
: result
= V2DF_type_node
; break;
32794 /* If the user says 'vector int bool', we may be handed the 'bool'
32795 attribute _before_ the 'vector' attribute, and so select the
32796 proper type in the 'b' case below. */
32797 case E_V4SImode
: case E_V8HImode
: case E_V16QImode
: case E_V4SFmode
:
32798 case E_V2DImode
: case E_V2DFmode
:
32806 case E_DImode
: case E_V2DImode
: result
= bool_V2DI_type_node
; break;
32807 case E_SImode
: case E_V4SImode
: result
= bool_V4SI_type_node
; break;
32808 case E_HImode
: case E_V8HImode
: result
= bool_V8HI_type_node
; break;
32809 case E_QImode
: case E_V16QImode
: result
= bool_V16QI_type_node
;
32816 case E_V8HImode
: result
= pixel_V8HI_type_node
;
32822 /* Propagate qualifiers attached to the element type
32823 onto the vector type. */
32824 if (result
&& result
!= type
&& TYPE_QUALS (type
))
32825 result
= build_qualified_type (result
, TYPE_QUALS (type
));
32827 *no_add_attrs
= true; /* No need to hang on to the attribute. */
32830 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
32835 /* AltiVec defines five built-in scalar types that serve as vector
32836 elements; we must teach the compiler how to mangle them. The 128-bit
32837 floating point mangling is target-specific as well. */
32839 static const char *
32840 rs6000_mangle_type (const_tree type
)
32842 type
= TYPE_MAIN_VARIANT (type
);
32844 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
32845 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
32848 if (type
== bool_char_type_node
) return "U6__boolc";
32849 if (type
== bool_short_type_node
) return "U6__bools";
32850 if (type
== pixel_type_node
) return "u7__pixel";
32851 if (type
== bool_int_type_node
) return "U6__booli";
32852 if (type
== bool_long_long_type_node
) return "U6__boolx";
32854 if (SCALAR_FLOAT_TYPE_P (type
) && FLOAT128_IBM_P (TYPE_MODE (type
)))
32856 if (SCALAR_FLOAT_TYPE_P (type
) && FLOAT128_IEEE_P (TYPE_MODE (type
)))
32857 return ieee128_mangling_gcc_8_1
? "U10__float128" : "u9__ieee128";
32859 /* For all other types, use the default mangling. */
32863 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32864 struct attribute_spec.handler. */
32867 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
32868 tree args ATTRIBUTE_UNUSED
,
32869 int flags ATTRIBUTE_UNUSED
,
32870 bool *no_add_attrs
)
32872 if (TREE_CODE (*node
) != FUNCTION_TYPE
32873 && TREE_CODE (*node
) != FIELD_DECL
32874 && TREE_CODE (*node
) != TYPE_DECL
)
32876 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
32878 *no_add_attrs
= true;
32884 /* Set longcall attributes on all functions declared when
32885 rs6000_default_long_calls is true. */
32887 rs6000_set_default_type_attributes (tree type
)
32889 if (rs6000_default_long_calls
32890 && (TREE_CODE (type
) == FUNCTION_TYPE
32891 || TREE_CODE (type
) == METHOD_TYPE
))
32892 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
32894 TYPE_ATTRIBUTES (type
));
32897 darwin_set_default_type_attributes (type
);
32901 /* Return a reference suitable for calling a function with the
32902 longcall attribute. */
32905 rs6000_longcall_ref (rtx call_ref
, rtx arg
)
32907 /* System V adds '.' to the internal name, so skip them. */
32908 const char *call_name
= XSTR (call_ref
, 0);
32909 if (*call_name
== '.')
32911 while (*call_name
== '.')
32914 tree node
= get_identifier (call_name
);
32915 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
32920 rtx base
= const0_rtx
;
32922 if (DEFAULT_ABI
== ABI_ELFv2
)
32924 base
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
32930 base
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
32933 /* Reg must match that used by linker PLT stubs. For ELFv2, r12
32934 may be used by a function global entry point. For SysV4, r11
32935 is used by __glink_PLTresolve lazy resolver entry. */
32936 rtx reg
= gen_rtx_REG (Pmode
, regno
);
32937 rtx hi
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (3, base
, call_ref
, arg
),
32939 rtx lo
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (3, reg
, call_ref
, arg
),
32941 emit_insn (gen_rtx_SET (reg
, hi
));
32942 emit_insn (gen_rtx_SET (reg
, lo
));
32946 return force_reg (Pmode
, call_ref
);
32949 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32950 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32953 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32954 struct attribute_spec.handler. */
32956 rs6000_handle_struct_attribute (tree
*node
, tree name
,
32957 tree args ATTRIBUTE_UNUSED
,
32958 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
32961 if (DECL_P (*node
))
32963 if (TREE_CODE (*node
) == TYPE_DECL
)
32964 type
= &TREE_TYPE (*node
);
32969 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
32970 || TREE_CODE (*type
) == UNION_TYPE
)))
32972 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
32973 *no_add_attrs
= true;
32976 else if ((is_attribute_p ("ms_struct", name
)
32977 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
32978 || ((is_attribute_p ("gcc_struct", name
)
32979 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
32981 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
32983 *no_add_attrs
= true;
32990 rs6000_ms_bitfield_layout_p (const_tree record_type
)
32992 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
32993 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
32994 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
32997 #ifdef USING_ELFOS_H
32999 /* A get_unnamed_section callback, used for switching to toc_section. */
33002 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
33004 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
33005 && TARGET_MINIMAL_TOC
)
33007 if (!toc_initialized
)
33009 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
33010 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
33011 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
33012 fprintf (asm_out_file
, "\t.tc ");
33013 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
33014 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
33015 fprintf (asm_out_file
, "\n");
33017 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
33018 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
33019 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
33020 fprintf (asm_out_file
, " = .+32768\n");
33021 toc_initialized
= 1;
33024 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
33026 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
33028 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
33029 if (!toc_initialized
)
33031 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
33032 toc_initialized
= 1;
33037 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
33038 if (!toc_initialized
)
33040 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
33041 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
33042 fprintf (asm_out_file
, " = .+32768\n");
33043 toc_initialized
= 1;
33048 /* Implement TARGET_ASM_INIT_SECTIONS. */
33051 rs6000_elf_asm_init_sections (void)
33054 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
33057 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
33058 SDATA2_SECTION_ASM_OP
);
33061 /* Implement TARGET_SELECT_RTX_SECTION. */
33064 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
33065 unsigned HOST_WIDE_INT align
)
33067 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
33068 return toc_section
;
33070 return default_elf_select_rtx_section (mode
, x
, align
);
33073 /* For a SYMBOL_REF, set generic flags and then perform some
33074 target-specific processing.
33076 When the AIX ABI is requested on a non-AIX system, replace the
33077 function name with the real name (with a leading .) rather than the
33078 function descriptor name. This saves a lot of overriding code to
33079 read the prefixes. */
33081 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
33083 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
33085 default_encode_section_info (decl
, rtl
, first
);
33088 && TREE_CODE (decl
) == FUNCTION_DECL
33090 && DEFAULT_ABI
== ABI_AIX
)
33092 rtx sym_ref
= XEXP (rtl
, 0);
33093 size_t len
= strlen (XSTR (sym_ref
, 0));
33094 char *str
= XALLOCAVEC (char, len
+ 2);
33096 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
33097 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
33102 compare_section_name (const char *section
, const char *templ
)
33106 len
= strlen (templ
);
33107 return (strncmp (section
, templ
, len
) == 0
33108 && (section
[len
] == 0 || section
[len
] == '.'));
33112 rs6000_elf_in_small_data_p (const_tree decl
)
33114 if (rs6000_sdata
== SDATA_NONE
)
33117 /* We want to merge strings, so we never consider them small data. */
33118 if (TREE_CODE (decl
) == STRING_CST
)
33121 /* Functions are never in the small data area. */
33122 if (TREE_CODE (decl
) == FUNCTION_DECL
)
33125 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
33127 const char *section
= DECL_SECTION_NAME (decl
);
33128 if (compare_section_name (section
, ".sdata")
33129 || compare_section_name (section
, ".sdata2")
33130 || compare_section_name (section
, ".gnu.linkonce.s")
33131 || compare_section_name (section
, ".sbss")
33132 || compare_section_name (section
, ".sbss2")
33133 || compare_section_name (section
, ".gnu.linkonce.sb")
33134 || strcmp (section
, ".PPC.EMB.sdata0") == 0
33135 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
33140 /* If we are told not to put readonly data in sdata, then don't. */
33141 if (TREE_READONLY (decl
) && rs6000_sdata
!= SDATA_EABI
33142 && !rs6000_readonly_in_sdata
)
33145 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
33148 && size
<= g_switch_value
33149 /* If it's not public, and we're not going to reference it there,
33150 there's no need to put it in the small data section. */
33151 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
33158 #endif /* USING_ELFOS_H */
33160 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
33163 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
33165 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
33168 /* Do not place thread-local symbols refs in the object blocks. */
33171 rs6000_use_blocks_for_decl_p (const_tree decl
)
33173 return !DECL_THREAD_LOCAL_P (decl
);
33176 /* Return a REG that occurs in ADDR with coefficient 1.
33177 ADDR can be effectively incremented by incrementing REG.
33179 r0 is special and we must not select it as an address
33180 register by this routine since our caller will try to
33181 increment the returned register via an "la" instruction. */
33184 find_addr_reg (rtx addr
)
33186 while (GET_CODE (addr
) == PLUS
)
33188 if (REG_P (XEXP (addr
, 0))
33189 && REGNO (XEXP (addr
, 0)) != 0)
33190 addr
= XEXP (addr
, 0);
33191 else if (REG_P (XEXP (addr
, 1))
33192 && REGNO (XEXP (addr
, 1)) != 0)
33193 addr
= XEXP (addr
, 1);
33194 else if (CONSTANT_P (XEXP (addr
, 0)))
33195 addr
= XEXP (addr
, 1);
33196 else if (CONSTANT_P (XEXP (addr
, 1)))
33197 addr
= XEXP (addr
, 0);
33199 gcc_unreachable ();
33201 gcc_assert (REG_P (addr
) && REGNO (addr
) != 0);
33206 rs6000_fatal_bad_address (rtx op
)
33208 fatal_insn ("bad address", op
);
33213 typedef struct branch_island_d
{
33214 tree function_name
;
33220 static vec
<branch_island
, va_gc
> *branch_islands
;
33222 /* Remember to generate a branch island for far calls to the given
33226 add_compiler_branch_island (tree label_name
, tree function_name
,
33229 branch_island bi
= {function_name
, label_name
, line_number
};
33230 vec_safe_push (branch_islands
, bi
);
33233 /* Generate far-jump branch islands for everything recorded in
33234 branch_islands. Invoked immediately after the last instruction of
33235 the epilogue has been emitted; the branch islands must be appended
33236 to, and contiguous with, the function body. Mach-O stubs are
33237 generated in machopic_output_stub(). */
33240 macho_branch_islands (void)
33244 while (!vec_safe_is_empty (branch_islands
))
33246 branch_island
*bi
= &branch_islands
->last ();
33247 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
33248 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
33249 char name_buf
[512];
33250 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33251 if (name
[0] == '*' || name
[0] == '&')
33252 strcpy (name_buf
, name
+1);
33256 strcpy (name_buf
+1, name
);
33258 strcpy (tmp_buf
, "\n");
33259 strcat (tmp_buf
, label
);
33260 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33261 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
33262 dbxout_stabd (N_SLINE
, bi
->line_number
);
33263 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33266 if (TARGET_LINK_STACK
)
33269 get_ppc476_thunk_name (name
);
33270 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
33271 strcat (tmp_buf
, name
);
33272 strcat (tmp_buf
, "\n");
33273 strcat (tmp_buf
, label
);
33274 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
33278 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
33279 strcat (tmp_buf
, label
);
33280 strcat (tmp_buf
, "_pic\n");
33281 strcat (tmp_buf
, label
);
33282 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
33285 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
33286 strcat (tmp_buf
, name_buf
);
33287 strcat (tmp_buf
, " - ");
33288 strcat (tmp_buf
, label
);
33289 strcat (tmp_buf
, "_pic)\n");
33291 strcat (tmp_buf
, "\tmtlr r0\n");
33293 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
33294 strcat (tmp_buf
, name_buf
);
33295 strcat (tmp_buf
, " - ");
33296 strcat (tmp_buf
, label
);
33297 strcat (tmp_buf
, "_pic)\n");
33299 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
33303 strcat (tmp_buf
, ":\nlis r12,hi16(");
33304 strcat (tmp_buf
, name_buf
);
33305 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
33306 strcat (tmp_buf
, name_buf
);
33307 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
33309 output_asm_insn (tmp_buf
, 0);
33310 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33311 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
33312 dbxout_stabd (N_SLINE
, bi
->line_number
);
33313 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33314 branch_islands
->pop ();
33318 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33319 already there or not. */
33322 no_previous_def (tree function_name
)
33327 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
33328 if (function_name
== bi
->function_name
)
33333 /* GET_PREV_LABEL gets the label name from the previous definition of
33337 get_prev_label (tree function_name
)
33342 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
33343 if (function_name
== bi
->function_name
)
33344 return bi
->label_name
;
33348 /* Generate PIC and indirect symbol stubs. */
33351 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
33353 unsigned int length
;
33354 char *symbol_name
, *lazy_ptr_name
;
33355 char *local_label_0
;
33356 static int label
= 0;
33358 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33359 symb
= (*targetm
.strip_name_encoding
) (symb
);
33362 length
= strlen (symb
);
33363 symbol_name
= XALLOCAVEC (char, length
+ 32);
33364 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
33366 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
33367 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
33370 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
33372 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
33376 fprintf (file
, "\t.align 5\n");
33378 fprintf (file
, "%s:\n", stub
);
33379 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33382 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33383 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
33385 fprintf (file
, "\tmflr r0\n");
33386 if (TARGET_LINK_STACK
)
33389 get_ppc476_thunk_name (name
);
33390 fprintf (file
, "\tbl %s\n", name
);
33391 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
33395 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
33396 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
33398 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
33399 lazy_ptr_name
, local_label_0
);
33400 fprintf (file
, "\tmtlr r0\n");
33401 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
33402 (TARGET_64BIT
? "ldu" : "lwzu"),
33403 lazy_ptr_name
, local_label_0
);
33404 fprintf (file
, "\tmtctr r12\n");
33405 fprintf (file
, "\tbctr\n");
33409 fprintf (file
, "\t.align 4\n");
33411 fprintf (file
, "%s:\n", stub
);
33412 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33414 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
33415 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
33416 (TARGET_64BIT
? "ldu" : "lwzu"),
33418 fprintf (file
, "\tmtctr r12\n");
33419 fprintf (file
, "\tbctr\n");
33422 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
33423 fprintf (file
, "%s:\n", lazy_ptr_name
);
33424 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
33425 fprintf (file
, "%sdyld_stub_binding_helper\n",
33426 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
33429 /* Legitimize PIC addresses. If the address is already
33430 position-independent, we return ORIG. Newly generated
33431 position-independent addresses go into a reg. This is REG if non
33432 zero, otherwise we allocate register(s) as necessary. */
33434 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33437 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
33442 if (reg
== NULL
&& !reload_completed
)
33443 reg
= gen_reg_rtx (Pmode
);
33445 if (GET_CODE (orig
) == CONST
)
33449 if (GET_CODE (XEXP (orig
, 0)) == PLUS
33450 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
33453 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
33455 /* Use a different reg for the intermediate value, as
33456 it will be marked UNCHANGING. */
33457 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
33458 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
33461 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
33464 if (CONST_INT_P (offset
))
33466 if (SMALL_INT (offset
))
33467 return plus_constant (Pmode
, base
, INTVAL (offset
));
33468 else if (!reload_completed
)
33469 offset
= force_reg (Pmode
, offset
);
33472 rtx mem
= force_const_mem (Pmode
, orig
);
33473 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
33476 return gen_rtx_PLUS (Pmode
, base
, offset
);
33479 /* Fall back on generic machopic code. */
33480 return machopic_legitimize_pic_address (orig
, mode
, reg
);
33483 /* Output a .machine directive for the Darwin assembler, and call
33484 the generic start_file routine. */
33487 rs6000_darwin_file_start (void)
33489 static const struct
33493 HOST_WIDE_INT if_set
;
33495 { "ppc64", "ppc64", MASK_64BIT
},
33496 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
33497 { "power4", "ppc970", 0 },
33498 { "G5", "ppc970", 0 },
33499 { "7450", "ppc7450", 0 },
33500 { "7400", "ppc7400", MASK_ALTIVEC
},
33501 { "G4", "ppc7400", 0 },
33502 { "750", "ppc750", 0 },
33503 { "740", "ppc750", 0 },
33504 { "G3", "ppc750", 0 },
33505 { "604e", "ppc604e", 0 },
33506 { "604", "ppc604", 0 },
33507 { "603e", "ppc603", 0 },
33508 { "603", "ppc603", 0 },
33509 { "601", "ppc601", 0 },
33510 { NULL
, "ppc", 0 } };
33511 const char *cpu_id
= "";
33514 rs6000_file_start ();
33515 darwin_file_start ();
33517 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33519 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
33520 cpu_id
= rs6000_default_cpu
;
33522 if (global_options_set
.x_rs6000_cpu_index
)
33523 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
33525 /* Look through the mapping array. Pick the first name that either
33526 matches the argument, has a bit set in IF_SET that is also set
33527 in the target flags, or has a NULL name. */
33530 while (mapping
[i
].arg
!= NULL
33531 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
33532 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
33535 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
33538 #endif /* TARGET_MACHO */
33542 rs6000_elf_reloc_rw_mask (void)
33546 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
33552 /* Record an element in the table of global constructors. SYMBOL is
33553 a SYMBOL_REF of the function to be called; PRIORITY is a number
33554 between 0 and MAX_INIT_PRIORITY.
33556 This differs from default_named_section_asm_out_constructor in
33557 that we have special handling for -mrelocatable. */
33559 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
33561 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
33563 const char *section
= ".ctors";
33566 if (priority
!= DEFAULT_INIT_PRIORITY
)
33568 sprintf (buf
, ".ctors.%.5u",
33569 /* Invert the numbering so the linker puts us in the proper
33570 order; constructors are run from right to left, and the
33571 linker sorts in increasing order. */
33572 MAX_INIT_PRIORITY
- priority
);
33576 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33577 assemble_align (POINTER_SIZE
);
33579 if (DEFAULT_ABI
== ABI_V4
33580 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33582 fputs ("\t.long (", asm_out_file
);
33583 output_addr_const (asm_out_file
, symbol
);
33584 fputs (")@fixup\n", asm_out_file
);
33587 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33590 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
33592 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
33594 const char *section
= ".dtors";
33597 if (priority
!= DEFAULT_INIT_PRIORITY
)
33599 sprintf (buf
, ".dtors.%.5u",
33600 /* Invert the numbering so the linker puts us in the proper
33601 order; constructors are run from right to left, and the
33602 linker sorts in increasing order. */
33603 MAX_INIT_PRIORITY
- priority
);
33607 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
33608 assemble_align (POINTER_SIZE
);
33610 if (DEFAULT_ABI
== ABI_V4
33611 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
33613 fputs ("\t.long (", asm_out_file
);
33614 output_addr_const (asm_out_file
, symbol
);
33615 fputs (")@fixup\n", asm_out_file
);
33618 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
33622 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
33624 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
33626 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
33627 ASM_OUTPUT_LABEL (file
, name
);
33628 fputs (DOUBLE_INT_ASM_OP
, file
);
33629 rs6000_output_function_entry (file
, name
);
33630 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
33633 fputs ("\t.size\t", file
);
33634 assemble_name (file
, name
);
33635 fputs (",24\n\t.type\t.", file
);
33636 assemble_name (file
, name
);
33637 fputs (",@function\n", file
);
33638 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
33640 fputs ("\t.globl\t.", file
);
33641 assemble_name (file
, name
);
33646 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33647 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33648 rs6000_output_function_entry (file
, name
);
33649 fputs (":\n", file
);
33654 if (DEFAULT_ABI
== ABI_V4
33655 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
33656 && !TARGET_SECURE_PLT
33657 && (!constant_pool_empty_p () || crtl
->profile
)
33658 && (uses_toc
= uses_TOC ()))
33663 switch_to_other_text_partition ();
33664 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33666 fprintf (file
, "\t.long ");
33667 assemble_name (file
, toc_label_name
);
33670 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33671 assemble_name (file
, buf
);
33674 switch_to_other_text_partition ();
33677 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
33678 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
33680 if (TARGET_CMODEL
== CMODEL_LARGE
&& rs6000_global_entry_point_needed_p ())
33684 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
33686 fprintf (file
, "\t.quad .TOC.-");
33687 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
33688 assemble_name (file
, buf
);
33692 if (DEFAULT_ABI
== ABI_AIX
)
33694 const char *desc_name
, *orig_name
;
33696 orig_name
= (*targetm
.strip_name_encoding
) (name
);
33697 desc_name
= orig_name
;
33698 while (*desc_name
== '.')
33701 if (TREE_PUBLIC (decl
))
33702 fprintf (file
, "\t.globl %s\n", desc_name
);
33704 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
33705 fprintf (file
, "%s:\n", desc_name
);
33706 fprintf (file
, "\t.long %s\n", orig_name
);
33707 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
33708 fputs ("\t.long 0\n", file
);
33709 fprintf (file
, "\t.previous\n");
33711 ASM_OUTPUT_LABEL (file
, name
);
33714 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
33716 rs6000_elf_file_end (void)
33718 #ifdef HAVE_AS_GNU_ATTRIBUTE
33719 /* ??? The value emitted depends on options active at file end.
33720 Assume anyone using #pragma or attributes that might change
33721 options knows what they are doing. */
33722 if ((TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
33723 && rs6000_passes_float
)
33727 if (TARGET_HARD_FLOAT
)
33731 if (rs6000_passes_long_double
)
33733 if (!TARGET_LONG_DOUBLE_128
)
33735 else if (TARGET_IEEEQUAD
)
33740 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", fp
);
33742 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
33744 if (rs6000_passes_vector
)
33745 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
33746 (TARGET_ALTIVEC_ABI
? 2 : 1));
33747 if (rs6000_returns_struct
)
33748 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
33749 aix_struct_return
? 2 : 1);
33752 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33753 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
33754 file_end_indicate_exec_stack ();
33757 if (flag_split_stack
)
33758 file_end_indicate_split_stack ();
33762 /* We have expanded a CPU builtin, so we need to emit a reference to
33763 the special symbol that LIBC uses to declare it supports the
33764 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33765 switch_to_section (data_section
);
33766 fprintf (asm_out_file
, "\t.align %u\n", TARGET_32BIT
? 2 : 3);
33767 fprintf (asm_out_file
, "\t%s %s\n",
33768 TARGET_32BIT
? ".long" : ".quad", tcb_verification_symbol
);
33775 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33776 #define HAVE_XCOFF_DWARF_EXTRAS 0
33779 static enum unwind_info_type
33780 rs6000_xcoff_debug_unwind_info (void)
33786 rs6000_xcoff_asm_output_anchor (rtx symbol
)
33790 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
33791 SYMBOL_REF_BLOCK_OFFSET (symbol
));
33792 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
33793 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
33794 fprintf (asm_out_file
, ",");
33795 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
33796 fprintf (asm_out_file
, "\n");
33800 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
33802 fputs (GLOBAL_ASM_OP
, stream
);
33803 RS6000_OUTPUT_BASENAME (stream
, name
);
33804 putc ('\n', stream
);
33807 /* A get_unnamed_decl callback, used for read-only sections. PTR
33808 points to the section string variable. */
33811 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
33813 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
33814 *(const char *const *) directive
,
33815 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33818 /* Likewise for read-write sections. */
33821 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
33823 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
33824 *(const char *const *) directive
,
33825 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33829 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
33831 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
33832 *(const char *const *) directive
,
33833 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
33836 /* A get_unnamed_section callback, used for switching to toc_section. */
33839 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
33841 if (TARGET_MINIMAL_TOC
)
33843 /* toc_section is always selected at least once from
33844 rs6000_xcoff_file_start, so this is guaranteed to
33845 always be defined once and only once in each file. */
33846 if (!toc_initialized
)
33848 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
33849 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
33850 toc_initialized
= 1;
33852 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
33853 (TARGET_32BIT
? "" : ",3"));
33856 fputs ("\t.toc\n", asm_out_file
);
33859 /* Implement TARGET_ASM_INIT_SECTIONS. */
33862 rs6000_xcoff_asm_init_sections (void)
33864 read_only_data_section
33865 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33866 &xcoff_read_only_section_name
);
33868 private_data_section
33869 = get_unnamed_section (SECTION_WRITE
,
33870 rs6000_xcoff_output_readwrite_section_asm_op
,
33871 &xcoff_private_data_section_name
);
33873 read_only_private_data_section
33874 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
33875 &xcoff_private_rodata_section_name
);
33878 = get_unnamed_section (SECTION_TLS
,
33879 rs6000_xcoff_output_tls_section_asm_op
,
33880 &xcoff_tls_data_section_name
);
33882 tls_private_data_section
33883 = get_unnamed_section (SECTION_TLS
,
33884 rs6000_xcoff_output_tls_section_asm_op
,
33885 &xcoff_private_data_section_name
);
33888 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
33890 readonly_data_section
= read_only_data_section
;
33894 rs6000_xcoff_reloc_rw_mask (void)
33900 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
33901 tree decl ATTRIBUTE_UNUSED
)
33904 static const char * const suffix
[5] = { "PR", "RO", "RW", "TL", "XO" };
33906 if (flags
& SECTION_EXCLUDE
)
33908 else if (flags
& SECTION_DEBUG
)
33910 fprintf (asm_out_file
, "\t.dwsect %s\n", name
);
33913 else if (flags
& SECTION_CODE
)
33915 else if (flags
& SECTION_TLS
)
33917 else if (flags
& SECTION_WRITE
)
33922 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
33923 (flags
& SECTION_CODE
) ? "." : "",
33924 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
33927 #define IN_NAMED_SECTION(DECL) \
33928 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33929 && DECL_SECTION_NAME (DECL) != NULL)
33932 rs6000_xcoff_select_section (tree decl
, int reloc
,
33933 unsigned HOST_WIDE_INT align
)
33935 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33937 if (align
> BIGGEST_ALIGNMENT
)
33939 resolve_unique_section (decl
, reloc
, true);
33940 if (IN_NAMED_SECTION (decl
))
33941 return get_named_section (decl
, NULL
, reloc
);
33944 if (decl_readonly_section (decl
, reloc
))
33946 if (TREE_PUBLIC (decl
))
33947 return read_only_data_section
;
33949 return read_only_private_data_section
;
33954 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
33956 if (TREE_PUBLIC (decl
))
33957 return tls_data_section
;
33958 else if (bss_initializer_p (decl
))
33960 /* Convert to COMMON to emit in BSS. */
33961 DECL_COMMON (decl
) = 1;
33962 return tls_comm_section
;
33965 return tls_private_data_section
;
33969 if (TREE_PUBLIC (decl
))
33970 return data_section
;
33972 return private_data_section
;
33977 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
33981 /* Use select_section for private data and uninitialized data with
33982 alignment <= BIGGEST_ALIGNMENT. */
33983 if (!TREE_PUBLIC (decl
)
33984 || DECL_COMMON (decl
)
33985 || (DECL_INITIAL (decl
) == NULL_TREE
33986 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
33987 || DECL_INITIAL (decl
) == error_mark_node
33988 || (flag_zero_initialized_in_bss
33989 && initializer_zerop (DECL_INITIAL (decl
))))
33992 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
33993 name
= (*targetm
.strip_name_encoding
) (name
);
33994 set_decl_section_name (decl
, name
);
33997 /* Select section for constant in constant pool.
33999 On RS/6000, all constants are in the private read-only data area.
34000 However, if this is being placed in the TOC it must be output as a
34004 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
34005 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
34007 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
34008 return toc_section
;
34010 return read_only_private_data_section
;
34013 /* Remove any trailing [DS] or the like from the symbol name. */
34015 static const char *
34016 rs6000_xcoff_strip_name_encoding (const char *name
)
34021 len
= strlen (name
);
34022 if (name
[len
- 1] == ']')
34023 return ggc_alloc_string (name
, len
- 4);
34028 /* Section attributes. AIX is always PIC. */
34030 static unsigned int
34031 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
34033 unsigned int align
;
34034 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
34036 /* Align to at least UNIT size. */
34037 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
34038 align
= MIN_UNITS_PER_WORD
;
34040 /* Increase alignment of large objects if not already stricter. */
34041 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
34042 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
34043 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
34045 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
34048 /* Output at beginning of assembler file.
34050 Initialize the section names for the RS/6000 at this point.
34052 Specify filename, including full path, to assembler.
34054 We want to go into the TOC section so at least one .toc will be emitted.
34055 Also, in order to output proper .bs/.es pairs, we need at least one static
34056 [RW] section emitted.
34058 Finally, declare mcount when profiling to make the assembler happy. */
34061 rs6000_xcoff_file_start (void)
34063 rs6000_gen_section_name (&xcoff_bss_section_name
,
34064 main_input_filename
, ".bss_");
34065 rs6000_gen_section_name (&xcoff_private_data_section_name
,
34066 main_input_filename
, ".rw_");
34067 rs6000_gen_section_name (&xcoff_private_rodata_section_name
,
34068 main_input_filename
, ".rop_");
34069 rs6000_gen_section_name (&xcoff_read_only_section_name
,
34070 main_input_filename
, ".ro_");
34071 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
34072 main_input_filename
, ".tls_");
34073 rs6000_gen_section_name (&xcoff_tbss_section_name
,
34074 main_input_filename
, ".tbss_[UL]");
34076 fputs ("\t.file\t", asm_out_file
);
34077 output_quoted_string (asm_out_file
, main_input_filename
);
34078 fputc ('\n', asm_out_file
);
34079 if (write_symbols
!= NO_DEBUG
)
34080 switch_to_section (private_data_section
);
34081 switch_to_section (toc_section
);
34082 switch_to_section (text_section
);
34084 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
34085 rs6000_file_start ();
34088 /* Output at end of assembler file.
34089 On the RS/6000, referencing data should automatically pull in text. */
34092 rs6000_xcoff_file_end (void)
34094 switch_to_section (text_section
);
34095 fputs ("_section_.text:\n", asm_out_file
);
34096 switch_to_section (data_section
);
34097 fputs (TARGET_32BIT
34098 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
34102 struct declare_alias_data
34105 bool function_descriptor
;
34108 /* Declare alias N. A helper function for for_node_and_aliases. */
34111 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
34113 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
34114 /* Main symbol is output specially, because varasm machinery does part of
34115 the job for us - we do not need to declare .globl/lglobs and such. */
34116 if (!n
->alias
|| n
->weakref
)
34119 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
34122 /* Prevent assemble_alias from trying to use .set pseudo operation
34123 that does not behave as expected by the middle-end. */
34124 TREE_ASM_WRITTEN (n
->decl
) = true;
34126 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
34127 char *buffer
= (char *) alloca (strlen (name
) + 2);
34129 int dollar_inside
= 0;
34131 strcpy (buffer
, name
);
34132 p
= strchr (buffer
, '$');
34136 p
= strchr (p
+ 1, '$');
34138 if (TREE_PUBLIC (n
->decl
))
34140 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
34142 if (dollar_inside
) {
34143 if (data
->function_descriptor
)
34144 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
34145 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
34147 if (data
->function_descriptor
)
34149 fputs ("\t.globl .", data
->file
);
34150 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
34151 putc ('\n', data
->file
);
34153 fputs ("\t.globl ", data
->file
);
34154 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
34155 putc ('\n', data
->file
);
34157 #ifdef ASM_WEAKEN_DECL
34158 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
34159 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
34166 if (data
->function_descriptor
)
34167 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
34168 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
34170 if (data
->function_descriptor
)
34172 fputs ("\t.lglobl .", data
->file
);
34173 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
34174 putc ('\n', data
->file
);
34176 fputs ("\t.lglobl ", data
->file
);
34177 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
34178 putc ('\n', data
->file
);
34180 if (data
->function_descriptor
)
34181 fputs (".", data
->file
);
34182 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
34183 fputs (":\n", data
->file
);
34188 #ifdef HAVE_GAS_HIDDEN
34189 /* Helper function to calculate visibility of a DECL
34190 and return the value as a const string. */
34192 static const char *
34193 rs6000_xcoff_visibility (tree decl
)
34195 static const char * const visibility_types
[] = {
34196 "", ",protected", ",hidden", ",internal"
34199 enum symbol_visibility vis
= DECL_VISIBILITY (decl
);
34200 return visibility_types
[vis
];
34205 /* This macro produces the initial definition of a function name.
34206 On the RS/6000, we need to place an extra '.' in the function name and
34207 output the function descriptor.
34208 Dollar signs are converted to underscores.
34210 The csect for the function will have already been created when
34211 text_section was selected. We do have to go back to that csect, however.
34213 The third and fourth parameters to the .function pseudo-op (16 and 044)
34214 are placeholders which no longer have any use.
34216 Because AIX assembler's .set command has unexpected semantics, we output
34217 all aliases as alternative labels in front of the definition. */
34220 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
34222 char *buffer
= (char *) alloca (strlen (name
) + 1);
34224 int dollar_inside
= 0;
34225 struct declare_alias_data data
= {file
, false};
34227 strcpy (buffer
, name
);
34228 p
= strchr (buffer
, '$');
34232 p
= strchr (p
+ 1, '$');
34234 if (TREE_PUBLIC (decl
))
34236 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
34238 if (dollar_inside
) {
34239 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
34240 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
34242 fputs ("\t.globl .", file
);
34243 RS6000_OUTPUT_BASENAME (file
, buffer
);
34244 #ifdef HAVE_GAS_HIDDEN
34245 fputs (rs6000_xcoff_visibility (decl
), file
);
34252 if (dollar_inside
) {
34253 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
34254 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
34256 fputs ("\t.lglobl .", file
);
34257 RS6000_OUTPUT_BASENAME (file
, buffer
);
34260 fputs ("\t.csect ", file
);
34261 RS6000_OUTPUT_BASENAME (file
, buffer
);
34262 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
34263 RS6000_OUTPUT_BASENAME (file
, buffer
);
34264 fputs (":\n", file
);
34265 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
34267 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
34268 RS6000_OUTPUT_BASENAME (file
, buffer
);
34269 fputs (", TOC[tc0], 0\n", file
);
34271 switch_to_section (function_section (decl
));
34273 RS6000_OUTPUT_BASENAME (file
, buffer
);
34274 fputs (":\n", file
);
34275 data
.function_descriptor
= true;
34276 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
34278 if (!DECL_IGNORED_P (decl
))
34280 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
34281 xcoffout_declare_function (file
, decl
, buffer
);
34282 else if (write_symbols
== DWARF2_DEBUG
)
34284 name
= (*targetm
.strip_name_encoding
) (name
);
34285 fprintf (file
, "\t.function .%s,.%s,2,0\n", name
, name
);
34292 /* Output assembly language to globalize a symbol from a DECL,
34293 possibly with visibility. */
34296 rs6000_xcoff_asm_globalize_decl_name (FILE *stream
, tree decl
)
34298 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
34299 fputs (GLOBAL_ASM_OP
, stream
);
34300 RS6000_OUTPUT_BASENAME (stream
, name
);
34301 #ifdef HAVE_GAS_HIDDEN
34302 fputs (rs6000_xcoff_visibility (decl
), stream
);
34304 putc ('\n', stream
);
34307 /* Output assembly language to define a symbol as COMMON from a DECL,
34308 possibly with visibility. */
34311 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream
,
34312 tree decl ATTRIBUTE_UNUSED
,
34314 unsigned HOST_WIDE_INT size
,
34315 unsigned HOST_WIDE_INT align
)
34317 unsigned HOST_WIDE_INT align2
= 2;
34320 align2
= floor_log2 (align
/ BITS_PER_UNIT
);
34324 fputs (COMMON_ASM_OP
, stream
);
34325 RS6000_OUTPUT_BASENAME (stream
, name
);
34328 "," HOST_WIDE_INT_PRINT_UNSIGNED
"," HOST_WIDE_INT_PRINT_UNSIGNED
,
34331 #ifdef HAVE_GAS_HIDDEN
34333 fputs (rs6000_xcoff_visibility (decl
), stream
);
34335 putc ('\n', stream
);
34338 /* This macro produces the initial definition of a object (variable) name.
34339 Because AIX assembler's .set command has unexpected semantics, we output
34340 all aliases as alternative labels in front of the definition. */
34343 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
34345 struct declare_alias_data data
= {file
, false};
34346 RS6000_OUTPUT_BASENAME (file
, name
);
34347 fputs (":\n", file
);
34348 symtab_node::get_create (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
34352 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34355 rs6000_asm_output_dwarf_pcrel (FILE *file
, int size
, const char *label
)
34357 fputs (integer_asm_op (size
, FALSE
), file
);
34358 assemble_name (file
, label
);
34359 fputs ("-$", file
);
34362 /* Output a symbol offset relative to the dbase for the current object.
34363 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34366 __gcc_unwind_dbase is embedded in all executables/libraries through
34367 libgcc/config/rs6000/crtdbase.S. */
34370 rs6000_asm_output_dwarf_datarel (FILE *file
, int size
, const char *label
)
34372 fputs (integer_asm_op (size
, FALSE
), file
);
34373 assemble_name (file
, label
);
34374 fputs("-__gcc_unwind_dbase", file
);
34379 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
34383 const char *symname
;
34385 default_encode_section_info (decl
, rtl
, first
);
34387 /* Careful not to prod global register variables. */
34390 symbol
= XEXP (rtl
, 0);
34391 if (!SYMBOL_REF_P (symbol
))
34394 flags
= SYMBOL_REF_FLAGS (symbol
);
34396 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
34397 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
34399 SYMBOL_REF_FLAGS (symbol
) = flags
;
34401 /* Append mapping class to extern decls. */
34402 symname
= XSTR (symbol
, 0);
34403 if (decl
/* sync condition with assemble_external () */
34404 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
34405 && ((TREE_CODE (decl
) == VAR_DECL
&& !DECL_THREAD_LOCAL_P (decl
))
34406 || TREE_CODE (decl
) == FUNCTION_DECL
)
34407 && symname
[strlen (symname
) - 1] != ']')
34409 char *newname
= (char *) alloca (strlen (symname
) + 5);
34410 strcpy (newname
, symname
);
34411 strcat (newname
, (TREE_CODE (decl
) == FUNCTION_DECL
34412 ? "[DS]" : "[UA]"));
34413 XSTR (symbol
, 0) = ggc_strdup (newname
);
34416 #endif /* HAVE_AS_TLS */
34417 #endif /* TARGET_XCOFF */
34420 rs6000_asm_weaken_decl (FILE *stream
, tree decl
,
34421 const char *name
, const char *val
)
34423 fputs ("\t.weak\t", stream
);
34424 RS6000_OUTPUT_BASENAME (stream
, name
);
34425 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
34426 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
34429 fputs ("[DS]", stream
);
34430 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34432 fputs (rs6000_xcoff_visibility (decl
), stream
);
34434 fputs ("\n\t.weak\t.", stream
);
34435 RS6000_OUTPUT_BASENAME (stream
, name
);
34437 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34439 fputs (rs6000_xcoff_visibility (decl
), stream
);
34441 fputc ('\n', stream
);
34444 #ifdef ASM_OUTPUT_DEF
34445 ASM_OUTPUT_DEF (stream
, name
, val
);
34447 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
34448 && DEFAULT_ABI
== ABI_AIX
&& DOT_SYMBOLS
)
34450 fputs ("\t.set\t.", stream
);
34451 RS6000_OUTPUT_BASENAME (stream
, name
);
34452 fputs (",.", stream
);
34453 RS6000_OUTPUT_BASENAME (stream
, val
);
34454 fputc ('\n', stream
);
34460 /* Return true if INSN should not be copied. */
34463 rs6000_cannot_copy_insn_p (rtx_insn
*insn
)
34465 return recog_memoized (insn
) >= 0
34466 && get_attr_cannot_copy (insn
);
34469 /* Compute a (partial) cost for rtx X. Return true if the complete
34470 cost has been computed, and false if subexpressions should be
34471 scanned. In either case, *TOTAL contains the cost result. */
34474 rs6000_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
34475 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
34477 int code
= GET_CODE (x
);
34481 /* On the RS/6000, if it is valid in the insn, it is free. */
34483 if (((outer_code
== SET
34484 || outer_code
== PLUS
34485 || outer_code
== MINUS
)
34486 && (satisfies_constraint_I (x
)
34487 || satisfies_constraint_L (x
)))
34488 || (outer_code
== AND
34489 && (satisfies_constraint_K (x
)
34491 ? satisfies_constraint_L (x
)
34492 : satisfies_constraint_J (x
))))
34493 || ((outer_code
== IOR
|| outer_code
== XOR
)
34494 && (satisfies_constraint_K (x
)
34496 ? satisfies_constraint_L (x
)
34497 : satisfies_constraint_J (x
))))
34498 || outer_code
== ASHIFT
34499 || outer_code
== ASHIFTRT
34500 || outer_code
== LSHIFTRT
34501 || outer_code
== ROTATE
34502 || outer_code
== ROTATERT
34503 || outer_code
== ZERO_EXTRACT
34504 || (outer_code
== MULT
34505 && satisfies_constraint_I (x
))
34506 || ((outer_code
== DIV
|| outer_code
== UDIV
34507 || outer_code
== MOD
|| outer_code
== UMOD
)
34508 && exact_log2 (INTVAL (x
)) >= 0)
34509 || (outer_code
== COMPARE
34510 && (satisfies_constraint_I (x
)
34511 || satisfies_constraint_K (x
)))
34512 || ((outer_code
== EQ
|| outer_code
== NE
)
34513 && (satisfies_constraint_I (x
)
34514 || satisfies_constraint_K (x
)
34516 ? satisfies_constraint_L (x
)
34517 : satisfies_constraint_J (x
))))
34518 || (outer_code
== GTU
34519 && satisfies_constraint_I (x
))
34520 || (outer_code
== LTU
34521 && satisfies_constraint_P (x
)))
34526 else if ((outer_code
== PLUS
34527 && reg_or_add_cint_operand (x
, VOIDmode
))
34528 || (outer_code
== MINUS
34529 && reg_or_sub_cint_operand (x
, VOIDmode
))
34530 || ((outer_code
== SET
34531 || outer_code
== IOR
34532 || outer_code
== XOR
)
34534 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
34536 *total
= COSTS_N_INSNS (1);
34542 case CONST_WIDE_INT
:
34546 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34550 /* When optimizing for size, MEM should be slightly more expensive
34551 than generating address, e.g., (plus (reg) (const)).
34552 L1 cache latency is about two instructions. */
34553 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34554 if (rs6000_slow_unaligned_access (mode
, MEM_ALIGN (x
)))
34555 *total
+= COSTS_N_INSNS (100);
34564 if (FLOAT_MODE_P (mode
))
34565 *total
= rs6000_cost
->fp
;
34567 *total
= COSTS_N_INSNS (1);
34571 if (CONST_INT_P (XEXP (x
, 1))
34572 && satisfies_constraint_I (XEXP (x
, 1)))
34574 if (INTVAL (XEXP (x
, 1)) >= -256
34575 && INTVAL (XEXP (x
, 1)) <= 255)
34576 *total
= rs6000_cost
->mulsi_const9
;
34578 *total
= rs6000_cost
->mulsi_const
;
34580 else if (mode
== SFmode
)
34581 *total
= rs6000_cost
->fp
;
34582 else if (FLOAT_MODE_P (mode
))
34583 *total
= rs6000_cost
->dmul
;
34584 else if (mode
== DImode
)
34585 *total
= rs6000_cost
->muldi
;
34587 *total
= rs6000_cost
->mulsi
;
34591 if (mode
== SFmode
)
34592 *total
= rs6000_cost
->fp
;
34594 *total
= rs6000_cost
->dmul
;
34599 if (FLOAT_MODE_P (mode
))
34601 *total
= mode
== DFmode
? rs6000_cost
->ddiv
34602 : rs6000_cost
->sdiv
;
34609 if (CONST_INT_P (XEXP (x
, 1))
34610 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
34612 if (code
== DIV
|| code
== MOD
)
34614 *total
= COSTS_N_INSNS (2);
34617 *total
= COSTS_N_INSNS (1);
34621 if (GET_MODE (XEXP (x
, 1)) == DImode
)
34622 *total
= rs6000_cost
->divdi
;
34624 *total
= rs6000_cost
->divsi
;
34626 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34627 if (!TARGET_MODULO
&& (code
== MOD
|| code
== UMOD
))
34628 *total
+= COSTS_N_INSNS (2);
34632 *total
= COSTS_N_INSNS (TARGET_CTZ
? 1 : 4);
34636 *total
= COSTS_N_INSNS (4);
34640 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
34644 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
34648 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
34651 *total
= COSTS_N_INSNS (1);
34655 if (CONST_INT_P (XEXP (x
, 1)))
34657 rtx left
= XEXP (x
, 0);
34658 rtx_code left_code
= GET_CODE (left
);
34660 /* rotate-and-mask: 1 insn. */
34661 if ((left_code
== ROTATE
34662 || left_code
== ASHIFT
34663 || left_code
== LSHIFTRT
)
34664 && rs6000_is_valid_shift_mask (XEXP (x
, 1), left
, mode
))
34666 *total
= rtx_cost (XEXP (left
, 0), mode
, left_code
, 0, speed
);
34667 if (!CONST_INT_P (XEXP (left
, 1)))
34668 *total
+= rtx_cost (XEXP (left
, 1), SImode
, left_code
, 1, speed
);
34669 *total
+= COSTS_N_INSNS (1);
34673 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34674 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
34675 if (rs6000_is_valid_and_mask (XEXP (x
, 1), mode
)
34676 || (val
& 0xffff) == val
34677 || (val
& 0xffff0000) == val
34678 || ((val
& 0xffff) == 0 && mode
== SImode
))
34680 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34681 *total
+= COSTS_N_INSNS (1);
34686 if (rs6000_is_valid_2insn_and (XEXP (x
, 1), mode
))
34688 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
34689 *total
+= COSTS_N_INSNS (2);
34694 *total
= COSTS_N_INSNS (1);
34699 *total
= COSTS_N_INSNS (1);
34705 *total
= COSTS_N_INSNS (1);
34709 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34710 the sign extend and shift separately within the insn. */
34711 if (TARGET_EXTSWSLI
&& mode
== DImode
34712 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
34713 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == SImode
)
34724 /* Handle mul_highpart. */
34725 if (outer_code
== TRUNCATE
34726 && GET_CODE (XEXP (x
, 0)) == MULT
)
34728 if (mode
== DImode
)
34729 *total
= rs6000_cost
->muldi
;
34731 *total
= rs6000_cost
->mulsi
;
34734 else if (outer_code
== AND
)
34737 *total
= COSTS_N_INSNS (1);
34742 if (MEM_P (XEXP (x
, 0)))
34745 *total
= COSTS_N_INSNS (1);
34751 if (!FLOAT_MODE_P (mode
))
34753 *total
= COSTS_N_INSNS (1);
34759 case UNSIGNED_FLOAT
:
34762 case FLOAT_TRUNCATE
:
34763 *total
= rs6000_cost
->fp
;
34767 if (mode
== DFmode
)
34768 *total
= rs6000_cost
->sfdf_convert
;
34770 *total
= rs6000_cost
->fp
;
34774 switch (XINT (x
, 1))
34777 *total
= rs6000_cost
->fp
;
34789 *total
= COSTS_N_INSNS (1);
34792 else if (FLOAT_MODE_P (mode
) && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
)
34794 *total
= rs6000_cost
->fp
;
34803 /* Carry bit requires mode == Pmode.
34804 NEG or PLUS already counted so only add one. */
34806 && (outer_code
== NEG
|| outer_code
== PLUS
))
34808 *total
= COSTS_N_INSNS (1);
34816 if (outer_code
== SET
)
34818 if (XEXP (x
, 1) == const0_rtx
)
34820 *total
= COSTS_N_INSNS (2);
34825 *total
= COSTS_N_INSNS (3);
34830 if (outer_code
== COMPARE
)
34844 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34847 rs6000_debug_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
34848 int opno
, int *total
, bool speed
)
34850 bool ret
= rs6000_rtx_costs (x
, mode
, outer_code
, opno
, total
, speed
);
34853 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34854 "opno = %d, total = %d, speed = %s, x:\n",
34855 ret
? "complete" : "scan inner",
34856 GET_MODE_NAME (mode
),
34857 GET_RTX_NAME (outer_code
),
34860 speed
? "true" : "false");
34868 rs6000_insn_cost (rtx_insn
*insn
, bool speed
)
34870 if (recog_memoized (insn
) < 0)
34874 return get_attr_length (insn
);
34876 int cost
= get_attr_cost (insn
);
34880 int n
= get_attr_length (insn
) / 4;
34881 enum attr_type type
= get_attr_type (insn
);
34888 cost
= COSTS_N_INSNS (n
+ 1);
34892 switch (get_attr_size (insn
))
34895 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi_const9
;
34898 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi_const
;
34901 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->mulsi
;
34904 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->muldi
;
34907 gcc_unreachable ();
34911 switch (get_attr_size (insn
))
34914 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->divsi
;
34917 cost
= COSTS_N_INSNS (n
- 1) + rs6000_cost
->divdi
;
34920 gcc_unreachable ();
34925 cost
= n
* rs6000_cost
->fp
;
34928 cost
= n
* rs6000_cost
->dmul
;
34931 cost
= n
* rs6000_cost
->sdiv
;
34934 cost
= n
* rs6000_cost
->ddiv
;
34941 cost
= COSTS_N_INSNS (n
+ 2);
34945 cost
= COSTS_N_INSNS (n
);
34951 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34954 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
34955 addr_space_t as
, bool speed
)
34957 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
34959 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34960 ret
, speed
? "true" : "false");
34967 /* A C expression returning the cost of moving data from a register of class
34968 CLASS1 to one of CLASS2. */
34971 rs6000_register_move_cost (machine_mode mode
,
34972 reg_class_t from
, reg_class_t to
)
34976 if (TARGET_DEBUG_COST
)
34979 /* Moves from/to GENERAL_REGS. */
34980 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
34981 || reg_classes_intersect_p (from
, GENERAL_REGS
))
34983 reg_class_t rclass
= from
;
34985 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
34988 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
34989 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
34990 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
34992 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34994 else if (rclass
== CR_REGS
)
34997 /* For those processors that have slow LR/CTR moves, make them more
34998 expensive than memory in order to bias spills to memory .*/
34999 else if ((rs6000_tune
== PROCESSOR_POWER6
35000 || rs6000_tune
== PROCESSOR_POWER7
35001 || rs6000_tune
== PROCESSOR_POWER8
35002 || rs6000_tune
== PROCESSOR_POWER9
)
35003 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
35004 ret
= 6 * hard_regno_nregs (0, mode
);
35007 /* A move will cost one instruction per GPR moved. */
35008 ret
= 2 * hard_regno_nregs (0, mode
);
35011 /* If we have VSX, we can easily move between FPR or Altivec registers. */
35012 else if (VECTOR_MEM_VSX_P (mode
)
35013 && reg_classes_intersect_p (to
, VSX_REGS
)
35014 && reg_classes_intersect_p (from
, VSX_REGS
))
35015 ret
= 2 * hard_regno_nregs (FIRST_FPR_REGNO
, mode
);
35017 /* Moving between two similar registers is just one instruction. */
35018 else if (reg_classes_intersect_p (to
, from
))
35019 ret
= (FLOAT128_2REG_P (mode
)) ? 4 : 2;
35021 /* Everything else has to go through GENERAL_REGS. */
35023 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
35024 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
35026 if (TARGET_DEBUG_COST
)
35028 if (dbg_cost_ctrl
== 1)
35030 "rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n",
35031 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
35032 reg_class_names
[to
]);
35039 /* A C expressions returning the cost of moving data of MODE from a register to
35043 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
35044 bool in ATTRIBUTE_UNUSED
)
35048 if (TARGET_DEBUG_COST
)
35051 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
35052 ret
= 4 * hard_regno_nregs (0, mode
);
35053 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
35054 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
35055 ret
= 4 * hard_regno_nregs (32, mode
);
35056 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
35057 ret
= 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO
, mode
);
35059 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
35061 if (TARGET_DEBUG_COST
)
35063 if (dbg_cost_ctrl
== 1)
35065 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
35066 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
35073 /* Returns a code for a target-specific builtin that implements
35074 reciprocal of the function, or NULL_TREE if not available. */
35077 rs6000_builtin_reciprocal (tree fndecl
)
35079 switch (DECL_FUNCTION_CODE (fndecl
))
35081 case VSX_BUILTIN_XVSQRTDP
:
35082 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
35085 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
35087 case VSX_BUILTIN_XVSQRTSP
:
35088 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
35091 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
35098 /* Load up a constant. If the mode is a vector mode, splat the value across
35099 all of the vector elements. */
35102 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
35106 if (mode
== SFmode
|| mode
== DFmode
)
35108 rtx d
= const_double_from_real_value (dconst
, mode
);
35109 reg
= force_reg (mode
, d
);
35111 else if (mode
== V4SFmode
)
35113 rtx d
= const_double_from_real_value (dconst
, SFmode
);
35114 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
35115 reg
= gen_reg_rtx (mode
);
35116 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
35118 else if (mode
== V2DFmode
)
35120 rtx d
= const_double_from_real_value (dconst
, DFmode
);
35121 rtvec v
= gen_rtvec (2, d
, d
);
35122 reg
= gen_reg_rtx (mode
);
35123 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
35126 gcc_unreachable ();
35131 /* Generate an FMA instruction. */
35134 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
35136 machine_mode mode
= GET_MODE (target
);
35139 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
35140 gcc_assert (dst
!= NULL
);
35143 emit_move_insn (target
, dst
);
35146 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
35149 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
35151 machine_mode mode
= GET_MODE (dst
);
35154 /* This is a tad more complicated, since the fnma_optab is for
35155 a different expression: fma(-m1, m2, a), which is the same
35156 thing except in the case of signed zeros.
35158 Fortunately we know that if FMA is supported that FNMSUB is
35159 also supported in the ISA. Just expand it directly. */
35161 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
35163 r
= gen_rtx_NEG (mode
, a
);
35164 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
35165 r
= gen_rtx_NEG (mode
, r
);
35166 emit_insn (gen_rtx_SET (dst
, r
));
35169 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
35170 add a reg_note saying that this was a division. Support both scalar and
35171 vector divide. Assumes no trapping math and finite arguments. */
35174 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
35176 machine_mode mode
= GET_MODE (dst
);
35177 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
35180 /* Low precision estimates guarantee 5 bits of accuracy. High
35181 precision estimates guarantee 14 bits of accuracy. SFmode
35182 requires 23 bits of accuracy. DFmode requires 52 bits of
35183 accuracy. Each pass at least doubles the accuracy, leading
35184 to the following. */
35185 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
35186 if (mode
== DFmode
|| mode
== V2DFmode
)
35189 enum insn_code code
= optab_handler (smul_optab
, mode
);
35190 insn_gen_fn gen_mul
= GEN_FCN (code
);
35192 gcc_assert (code
!= CODE_FOR_nothing
);
35194 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
35196 /* x0 = 1./d estimate */
35197 x0
= gen_reg_rtx (mode
);
35198 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
35201 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35204 /* e0 = 1. - d * x0 */
35205 e0
= gen_reg_rtx (mode
);
35206 rs6000_emit_nmsub (e0
, d
, x0
, one
);
35208 /* x1 = x0 + e0 * x0 */
35209 x1
= gen_reg_rtx (mode
);
35210 rs6000_emit_madd (x1
, e0
, x0
, x0
);
35212 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
35213 ++i
, xprev
= xnext
, eprev
= enext
) {
35215 /* enext = eprev * eprev */
35216 enext
= gen_reg_rtx (mode
);
35217 emit_insn (gen_mul (enext
, eprev
, eprev
));
35219 /* xnext = xprev + enext * xprev */
35220 xnext
= gen_reg_rtx (mode
);
35221 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
35227 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35229 /* u = n * xprev */
35230 u
= gen_reg_rtx (mode
);
35231 emit_insn (gen_mul (u
, n
, xprev
));
35233 /* v = n - (d * u) */
35234 v
= gen_reg_rtx (mode
);
35235 rs6000_emit_nmsub (v
, d
, u
, n
);
35237 /* dst = (v * xprev) + u */
35238 rs6000_emit_madd (dst
, v
, xprev
, u
);
35241 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
35244 /* Goldschmidt's Algorithm for single/double-precision floating point
35245 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35248 rs6000_emit_swsqrt (rtx dst
, rtx src
, bool recip
)
35250 machine_mode mode
= GET_MODE (src
);
35251 rtx e
= gen_reg_rtx (mode
);
35252 rtx g
= gen_reg_rtx (mode
);
35253 rtx h
= gen_reg_rtx (mode
);
35255 /* Low precision estimates guarantee 5 bits of accuracy. High
35256 precision estimates guarantee 14 bits of accuracy. SFmode
35257 requires 23 bits of accuracy. DFmode requires 52 bits of
35258 accuracy. Each pass at least doubles the accuracy, leading
35259 to the following. */
35260 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
35261 if (mode
== DFmode
|| mode
== V2DFmode
)
35266 enum insn_code code
= optab_handler (smul_optab
, mode
);
35267 insn_gen_fn gen_mul
= GEN_FCN (code
);
35269 gcc_assert (code
!= CODE_FOR_nothing
);
35271 mhalf
= rs6000_load_constant_and_splat (mode
, dconsthalf
);
35273 /* e = rsqrt estimate */
35274 emit_insn (gen_rtx_SET (e
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
35277 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35280 rtx zero
= force_reg (mode
, CONST0_RTX (mode
));
35282 if (mode
== SFmode
)
35284 rtx target
= emit_conditional_move (e
, GT
, src
, zero
, mode
,
35287 emit_move_insn (e
, target
);
35291 rtx cond
= gen_rtx_GT (VOIDmode
, e
, zero
);
35292 rs6000_emit_vector_cond_expr (e
, e
, zero
, cond
, src
, zero
);
35296 /* g = sqrt estimate. */
35297 emit_insn (gen_mul (g
, e
, src
));
35298 /* h = 1/(2*sqrt) estimate. */
35299 emit_insn (gen_mul (h
, e
, mhalf
));
35305 rtx t
= gen_reg_rtx (mode
);
35306 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
35307 /* Apply correction directly to 1/rsqrt estimate. */
35308 rs6000_emit_madd (dst
, e
, t
, e
);
35312 for (i
= 0; i
< passes
; i
++)
35314 rtx t1
= gen_reg_rtx (mode
);
35315 rtx g1
= gen_reg_rtx (mode
);
35316 rtx h1
= gen_reg_rtx (mode
);
35318 rs6000_emit_nmsub (t1
, g
, h
, mhalf
);
35319 rs6000_emit_madd (g1
, g
, t1
, g
);
35320 rs6000_emit_madd (h1
, h
, t1
, h
);
35325 /* Multiply by 2 for 1/rsqrt. */
35326 emit_insn (gen_add3_insn (dst
, h
, h
));
35331 rtx t
= gen_reg_rtx (mode
);
35332 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
35333 rs6000_emit_madd (dst
, g
, t
, g
);
35339 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35340 (Power7) targets. DST is the target, and SRC is the argument operand. */
35343 rs6000_emit_popcount (rtx dst
, rtx src
)
35345 machine_mode mode
= GET_MODE (dst
);
35348 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35349 if (TARGET_POPCNTD
)
35351 if (mode
== SImode
)
35352 emit_insn (gen_popcntdsi2 (dst
, src
));
35354 emit_insn (gen_popcntddi2 (dst
, src
));
35358 tmp1
= gen_reg_rtx (mode
);
35360 if (mode
== SImode
)
35362 emit_insn (gen_popcntbsi2 (tmp1
, src
));
35363 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
35365 tmp2
= force_reg (SImode
, tmp2
);
35366 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
35370 emit_insn (gen_popcntbdi2 (tmp1
, src
));
35371 tmp2
= expand_mult (DImode
, tmp1
,
35372 GEN_INT ((HOST_WIDE_INT
)
35373 0x01010101 << 32 | 0x01010101),
35375 tmp2
= force_reg (DImode
, tmp2
);
35376 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
35381 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35382 target, and SRC is the argument operand. */
35385 rs6000_emit_parity (rtx dst
, rtx src
)
35387 machine_mode mode
= GET_MODE (dst
);
35390 tmp
= gen_reg_rtx (mode
);
35392 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35395 if (mode
== SImode
)
35397 emit_insn (gen_popcntbsi2 (tmp
, src
));
35398 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
35402 emit_insn (gen_popcntbdi2 (tmp
, src
));
35403 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
35408 if (mode
== SImode
)
35410 /* Is mult+shift >= shift+xor+shift+xor? */
35411 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
35413 rtx tmp1
, tmp2
, tmp3
, tmp4
;
35415 tmp1
= gen_reg_rtx (SImode
);
35416 emit_insn (gen_popcntbsi2 (tmp1
, src
));
35418 tmp2
= gen_reg_rtx (SImode
);
35419 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
35420 tmp3
= gen_reg_rtx (SImode
);
35421 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
35423 tmp4
= gen_reg_rtx (SImode
);
35424 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
35425 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
35428 rs6000_emit_popcount (tmp
, src
);
35429 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
35433 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35434 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
35436 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
35438 tmp1
= gen_reg_rtx (DImode
);
35439 emit_insn (gen_popcntbdi2 (tmp1
, src
));
35441 tmp2
= gen_reg_rtx (DImode
);
35442 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
35443 tmp3
= gen_reg_rtx (DImode
);
35444 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
35446 tmp4
= gen_reg_rtx (DImode
);
35447 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
35448 tmp5
= gen_reg_rtx (DImode
);
35449 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
35451 tmp6
= gen_reg_rtx (DImode
);
35452 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
35453 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
35456 rs6000_emit_popcount (tmp
, src
);
35457 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
35461 /* Expand an Altivec constant permutation for little endian mode.
35462 OP0 and OP1 are the input vectors and TARGET is the output vector.
35463 SEL specifies the constant permutation vector.
35465 There are two issues: First, the two input operands must be
35466 swapped so that together they form a double-wide array in LE
35467 order. Second, the vperm instruction has surprising behavior
35468 in LE mode: it interprets the elements of the source vectors
35469 in BE mode ("left to right") and interprets the elements of
35470 the destination vector in LE mode ("right to left"). To
35471 correct for this, we must subtract each element of the permute
35472 control vector from 31.
35474 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35475 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35476 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35477 serve as the permute control vector. Then, in BE mode,
35481 places the desired result in vr9. However, in LE mode the
35482 vector contents will be
35484 vr10 = 00000003 00000002 00000001 00000000
35485 vr11 = 00000007 00000006 00000005 00000004
35487 The result of the vperm using the same permute control vector is
35489 vr9 = 05000000 07000000 01000000 03000000
35491 That is, the leftmost 4 bytes of vr10 are interpreted as the
35492 source for the rightmost 4 bytes of vr9, and so on.
35494 If we change the permute control vector to
35496 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35504 vr9 = 00000006 00000004 00000002 00000000. */
35507 altivec_expand_vec_perm_const_le (rtx target
, rtx op0
, rtx op1
,
35508 const vec_perm_indices
&sel
)
35512 rtx constv
, unspec
;
35514 /* Unpack and adjust the constant selector. */
35515 for (i
= 0; i
< 16; ++i
)
35517 unsigned int elt
= 31 - (sel
[i
] & 31);
35518 perm
[i
] = GEN_INT (elt
);
35521 /* Expand to a permute, swapping the inputs and using the
35522 adjusted selector. */
35524 op0
= force_reg (V16QImode
, op0
);
35526 op1
= force_reg (V16QImode
, op1
);
35528 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
35529 constv
= force_reg (V16QImode
, constv
);
35530 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
35532 if (!REG_P (target
))
35534 rtx tmp
= gen_reg_rtx (V16QImode
);
35535 emit_move_insn (tmp
, unspec
);
35539 emit_move_insn (target
, unspec
);
35542 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35543 permute control vector. But here it's not a constant, so we must
35544 generate a vector NAND or NOR to do the adjustment. */
35547 altivec_expand_vec_perm_le (rtx operands
[4])
35549 rtx notx
, iorx
, unspec
;
35550 rtx target
= operands
[0];
35551 rtx op0
= operands
[1];
35552 rtx op1
= operands
[2];
35553 rtx sel
= operands
[3];
35555 rtx norreg
= gen_reg_rtx (V16QImode
);
35556 machine_mode mode
= GET_MODE (target
);
35558 /* Get everything in regs so the pattern matches. */
35560 op0
= force_reg (mode
, op0
);
35562 op1
= force_reg (mode
, op1
);
35564 sel
= force_reg (V16QImode
, sel
);
35565 if (!REG_P (target
))
35566 tmp
= gen_reg_rtx (mode
);
35568 if (TARGET_P9_VECTOR
)
35570 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, sel
),
35575 /* Invert the selector with a VNAND if available, else a VNOR.
35576 The VNAND is preferred for future fusion opportunities. */
35577 notx
= gen_rtx_NOT (V16QImode
, sel
);
35578 iorx
= (TARGET_P8_VECTOR
35579 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
35580 : gen_rtx_AND (V16QImode
, notx
, notx
));
35581 emit_insn (gen_rtx_SET (norreg
, iorx
));
35583 /* Permute with operands reversed and adjusted selector. */
35584 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
35588 /* Copy into target, possibly by way of a register. */
35589 if (!REG_P (target
))
35591 emit_move_insn (tmp
, unspec
);
35595 emit_move_insn (target
, unspec
);
35598 /* Expand an Altivec constant permutation. Return true if we match
35599 an efficient implementation; false to fall back to VPERM.
35601 OP0 and OP1 are the input vectors and TARGET is the output vector.
35602 SEL specifies the constant permutation vector. */
35605 altivec_expand_vec_perm_const (rtx target
, rtx op0
, rtx op1
,
35606 const vec_perm_indices
&sel
)
35608 struct altivec_perm_insn
{
35609 HOST_WIDE_INT mask
;
35610 enum insn_code impl
;
35611 unsigned char perm
[16];
35613 static const struct altivec_perm_insn patterns
[] = {
35614 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
35615 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35616 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
35617 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35618 { OPTION_MASK_ALTIVEC
,
35619 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
35620 : CODE_FOR_altivec_vmrglb_direct
),
35621 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35622 { OPTION_MASK_ALTIVEC
,
35623 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
35624 : CODE_FOR_altivec_vmrglh_direct
),
35625 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35626 { OPTION_MASK_ALTIVEC
,
35627 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
35628 : CODE_FOR_altivec_vmrglw_direct
),
35629 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35630 { OPTION_MASK_ALTIVEC
,
35631 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
35632 : CODE_FOR_altivec_vmrghb_direct
),
35633 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35634 { OPTION_MASK_ALTIVEC
,
35635 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
35636 : CODE_FOR_altivec_vmrghh_direct
),
35637 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35638 { OPTION_MASK_ALTIVEC
,
35639 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
35640 : CODE_FOR_altivec_vmrghw_direct
),
35641 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35642 { OPTION_MASK_P8_VECTOR
,
35643 (BYTES_BIG_ENDIAN
? CODE_FOR_p8_vmrgew_v4sf_direct
35644 : CODE_FOR_p8_vmrgow_v4sf_direct
),
35645 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35646 { OPTION_MASK_P8_VECTOR
,
35647 (BYTES_BIG_ENDIAN
? CODE_FOR_p8_vmrgow_v4sf_direct
35648 : CODE_FOR_p8_vmrgew_v4sf_direct
),
35649 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35652 unsigned int i
, j
, elt
, which
;
35653 unsigned char perm
[16];
35657 /* Unpack the constant selector. */
35658 for (i
= which
= 0; i
< 16; ++i
)
35661 which
|= (elt
< 16 ? 1 : 2);
35665 /* Simplify the constant selector based on operands. */
35669 gcc_unreachable ();
35673 if (!rtx_equal_p (op0
, op1
))
35678 for (i
= 0; i
< 16; ++i
)
35690 /* Look for splat patterns. */
35695 for (i
= 0; i
< 16; ++i
)
35696 if (perm
[i
] != elt
)
35700 if (!BYTES_BIG_ENDIAN
)
35702 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
35708 for (i
= 0; i
< 16; i
+= 2)
35709 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
35713 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
35714 x
= gen_reg_rtx (V8HImode
);
35715 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
35717 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35724 for (i
= 0; i
< 16; i
+= 4)
35726 || perm
[i
+ 1] != elt
+ 1
35727 || perm
[i
+ 2] != elt
+ 2
35728 || perm
[i
+ 3] != elt
+ 3)
35732 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
35733 x
= gen_reg_rtx (V4SImode
);
35734 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
35736 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35742 /* Look for merge and pack patterns. */
35743 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
35747 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
35750 elt
= patterns
[j
].perm
[0];
35751 if (perm
[0] == elt
)
35753 else if (perm
[0] == elt
+ 16)
35757 for (i
= 1; i
< 16; ++i
)
35759 elt
= patterns
[j
].perm
[i
];
35761 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
35762 else if (one_vec
&& elt
>= 16)
35764 if (perm
[i
] != elt
)
35769 enum insn_code icode
= patterns
[j
].impl
;
35770 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
35771 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
35773 /* For little-endian, don't use vpkuwum and vpkuhum if the
35774 underlying vector type is not V4SI and V8HI, respectively.
35775 For example, using vpkuwum with a V8HI picks up the even
35776 halfwords (BE numbering) when the even halfwords (LE
35777 numbering) are what we need. */
35778 if (!BYTES_BIG_ENDIAN
35779 && icode
== CODE_FOR_altivec_vpkuwum_direct
35781 && GET_MODE (op0
) != V4SImode
)
35783 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
35785 if (!BYTES_BIG_ENDIAN
35786 && icode
== CODE_FOR_altivec_vpkuhum_direct
35788 && GET_MODE (op0
) != V8HImode
)
35790 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
35793 /* For little-endian, the two input operands must be swapped
35794 (or swapped back) to ensure proper right-to-left numbering
35796 if (swapped
^ !BYTES_BIG_ENDIAN
)
35797 std::swap (op0
, op1
);
35798 if (imode
!= V16QImode
)
35800 op0
= gen_lowpart (imode
, op0
);
35801 op1
= gen_lowpart (imode
, op1
);
35803 if (omode
== V16QImode
)
35806 x
= gen_reg_rtx (omode
);
35807 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
35808 if (omode
!= V16QImode
)
35809 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
35814 if (!BYTES_BIG_ENDIAN
)
35816 altivec_expand_vec_perm_const_le (target
, op0
, op1
, sel
);
35823 /* Expand a VSX Permute Doubleword constant permutation.
35824 Return true if we match an efficient implementation. */
35827 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
35828 unsigned char perm0
, unsigned char perm1
)
35832 /* If both selectors come from the same operand, fold to single op. */
35833 if ((perm0
& 2) == (perm1
& 2))
35840 /* If both operands are equal, fold to simpler permutation. */
35841 if (rtx_equal_p (op0
, op1
))
35844 perm1
= (perm1
& 1) + 2;
35846 /* If the first selector comes from the second operand, swap. */
35847 else if (perm0
& 2)
35853 std::swap (op0
, op1
);
35855 /* If the second selector does not come from the second operand, fail. */
35856 else if ((perm1
& 2) == 0)
35860 if (target
!= NULL
)
35862 machine_mode vmode
, dmode
;
35865 vmode
= GET_MODE (target
);
35866 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
35867 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4).require ();
35868 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
35869 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
35870 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
35871 emit_insn (gen_rtx_SET (target
, x
));
35876 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35879 rs6000_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
,
35880 rtx op1
, const vec_perm_indices
&sel
)
35882 bool testing_p
= !target
;
35884 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35885 if (TARGET_ALTIVEC
&& testing_p
)
35888 /* Check for ps_merge* or xxpermdi insns. */
35889 if ((vmode
== V2DFmode
|| vmode
== V2DImode
) && VECTOR_MEM_VSX_P (vmode
))
35893 op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
35894 op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
35896 if (rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, sel
[0], sel
[1]))
35900 if (TARGET_ALTIVEC
)
35902 /* Force the target-independent code to lower to V16QImode. */
35903 if (vmode
!= V16QImode
)
35905 if (altivec_expand_vec_perm_const (target
, op0
, op1
, sel
))
35912 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35913 OP0 and OP1 are the input vectors and TARGET is the output vector.
35914 PERM specifies the constant permutation vector. */
35917 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
35918 machine_mode vmode
, const vec_perm_builder
&perm
)
35920 rtx x
= expand_vec_perm_const (vmode
, op0
, op1
, perm
, BLKmode
, target
);
35922 emit_move_insn (target
, x
);
35925 /* Expand an extract even operation. */
35928 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
35930 machine_mode vmode
= GET_MODE (target
);
35931 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
35932 vec_perm_builder
perm (nelt
, nelt
, 1);
35934 for (i
= 0; i
< nelt
; i
++)
35935 perm
.quick_push (i
* 2);
35937 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, perm
);
35940 /* Expand a vector interleave operation. */
35943 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
35945 machine_mode vmode
= GET_MODE (target
);
35946 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
35947 vec_perm_builder
perm (nelt
, nelt
, 1);
35949 high
= (highp
? 0 : nelt
/ 2);
35950 for (i
= 0; i
< nelt
/ 2; i
++)
35952 perm
.quick_push (i
+ high
);
35953 perm
.quick_push (i
+ nelt
+ high
);
35956 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, perm
);
35959 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35961 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
35963 HOST_WIDE_INT
hwi_scale (scale
);
35964 REAL_VALUE_TYPE r_pow
;
35965 rtvec v
= rtvec_alloc (2);
35967 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
35968 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
35969 elt
= const_double_from_real_value (r_pow
, DFmode
);
35970 RTVEC_ELT (v
, 0) = elt
;
35971 RTVEC_ELT (v
, 1) = elt
;
35972 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
35973 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
35976 /* Return an RTX representing where to find the function value of a
35977 function returning MODE. */
35979 rs6000_complex_function_value (machine_mode mode
)
35981 unsigned int regno
;
35983 machine_mode inner
= GET_MODE_INNER (mode
);
35984 unsigned int inner_bytes
= GET_MODE_UNIT_SIZE (mode
);
35986 if (TARGET_FLOAT128_TYPE
35988 || (mode
== TCmode
&& TARGET_IEEEQUAD
)))
35989 regno
= ALTIVEC_ARG_RETURN
;
35991 else if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
35992 regno
= FP_ARG_RETURN
;
35996 regno
= GP_ARG_RETURN
;
35998 /* 32-bit is OK since it'll go in r3/r4. */
35999 if (TARGET_32BIT
&& inner_bytes
>= 4)
36000 return gen_rtx_REG (mode
, regno
);
36003 if (inner_bytes
>= 8)
36004 return gen_rtx_REG (mode
, regno
);
36006 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
36008 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
36009 GEN_INT (inner_bytes
));
36010 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
36013 /* Return an rtx describing a return value of MODE as a PARALLEL
36014 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
36015 stride REG_STRIDE. */
36018 rs6000_parallel_return (machine_mode mode
,
36019 int n_elts
, machine_mode elt_mode
,
36020 unsigned int regno
, unsigned int reg_stride
)
36022 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
36025 for (i
= 0; i
< n_elts
; i
++)
36027 rtx r
= gen_rtx_REG (elt_mode
, regno
);
36028 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
36029 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
36030 regno
+= reg_stride
;
36036 /* Target hook for TARGET_FUNCTION_VALUE.
36038 An integer value is in r3 and a floating-point value is in fp1,
36039 unless -msoft-float. */
36042 rs6000_function_value (const_tree valtype
,
36043 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
36044 bool outgoing ATTRIBUTE_UNUSED
)
36047 unsigned int regno
;
36048 machine_mode elt_mode
;
36051 /* Special handling for structs in darwin64. */
36053 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
36055 CUMULATIVE_ARGS valcum
;
36059 valcum
.fregno
= FP_ARG_MIN_REG
;
36060 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
36061 /* Do a trial code generation as if this were going to be passed as
36062 an argument; if any part goes in memory, we return NULL. */
36063 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
36066 /* Otherwise fall through to standard ABI rules. */
36069 mode
= TYPE_MODE (valtype
);
36071 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
36072 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
36074 int first_reg
, n_regs
;
36076 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode
))
36078 /* _Decimal128 must use even/odd register pairs. */
36079 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
36080 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
36084 first_reg
= ALTIVEC_ARG_RETURN
;
36088 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
36091 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
36092 if (TARGET_32BIT
&& TARGET_POWERPC64
)
36101 int count
= GET_MODE_SIZE (mode
) / 4;
36102 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
36105 if ((INTEGRAL_TYPE_P (valtype
)
36106 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
36107 || POINTER_TYPE_P (valtype
))
36108 mode
= TARGET_32BIT
? SImode
: DImode
;
36110 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
36111 /* _Decimal128 must use an even/odd register pair. */
36112 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
36113 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
36114 && !FLOAT128_VECTOR_P (mode
))
36115 regno
= FP_ARG_RETURN
;
36116 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
36117 && targetm
.calls
.split_complex_arg
)
36118 return rs6000_complex_function_value (mode
);
36119 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36120 return register is used in both cases, and we won't see V2DImode/V2DFmode
36121 for pure altivec, combine the two cases. */
36122 else if ((TREE_CODE (valtype
) == VECTOR_TYPE
|| FLOAT128_VECTOR_P (mode
))
36123 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
36124 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
36125 regno
= ALTIVEC_ARG_RETURN
;
36127 regno
= GP_ARG_RETURN
;
36129 return gen_rtx_REG (mode
, regno
);
36132 /* Define how to find the value returned by a library function
36133 assuming the value has mode MODE. */
36135 rs6000_libcall_value (machine_mode mode
)
36137 unsigned int regno
;
36139 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
36140 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
36141 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
36143 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
)
36144 /* _Decimal128 must use an even/odd register pair. */
36145 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
36146 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && TARGET_HARD_FLOAT
)
36147 regno
= FP_ARG_RETURN
;
36148 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36149 return register is used in both cases, and we won't see V2DImode/V2DFmode
36150 for pure altivec, combine the two cases. */
36151 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
36152 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
36153 regno
= ALTIVEC_ARG_RETURN
;
36154 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
36155 return rs6000_complex_function_value (mode
);
36157 regno
= GP_ARG_RETURN
;
36159 return gen_rtx_REG (mode
, regno
);
36162 /* Compute register pressure classes. We implement the target hook to avoid
36163 IRA picking something like GEN_OR_FLOAT_REGS as a pressure class, which can
36164 lead to incorrect estimates of number of available registers and therefor
36165 increased register pressure/spill. */
36167 rs6000_compute_pressure_classes (enum reg_class
*pressure_classes
)
36172 pressure_classes
[n
++] = GENERAL_REGS
;
36174 pressure_classes
[n
++] = VSX_REGS
;
36177 if (TARGET_ALTIVEC
)
36178 pressure_classes
[n
++] = ALTIVEC_REGS
;
36179 if (TARGET_HARD_FLOAT
)
36180 pressure_classes
[n
++] = FLOAT_REGS
;
36182 pressure_classes
[n
++] = CR_REGS
;
36183 pressure_classes
[n
++] = SPECIAL_REGS
;
36188 /* Given FROM and TO register numbers, say whether this elimination is allowed.
36189 Frame pointer elimination is automatically handled.
36191 For the RS/6000, if frame pointer elimination is being done, we would like
36192 to convert ap into fp, not sp.
36194 We need r30 if -mminimal-toc was specified, and there are constant pool
36198 rs6000_can_eliminate (const int from
, const int to
)
36200 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
36201 ? ! frame_pointer_needed
36202 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
36203 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
36204 || constant_pool_empty_p ()
36208 /* Define the offset between two registers, FROM to be eliminated and its
36209 replacement TO, at the start of a routine. */
36211 rs6000_initial_elimination_offset (int from
, int to
)
36213 rs6000_stack_t
*info
= rs6000_stack_info ();
36214 HOST_WIDE_INT offset
;
36216 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
36217 offset
= info
->push_p
? 0 : -info
->total_size
;
36218 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
36220 offset
= info
->push_p
? 0 : -info
->total_size
;
36221 if (FRAME_GROWS_DOWNWARD
)
36222 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
36224 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
36225 offset
= FRAME_GROWS_DOWNWARD
36226 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
36228 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
36229 offset
= info
->total_size
;
36230 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
36231 offset
= info
->push_p
? info
->total_size
: 0;
36232 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
36235 gcc_unreachable ();
36240 /* Fill in sizes of registers used by unwinder. */
36243 rs6000_init_dwarf_reg_sizes_extra (tree address
)
36245 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
36248 machine_mode mode
= TYPE_MODE (char_type_node
);
36249 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
36250 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
36251 rtx value
= gen_int_mode (16, mode
);
36253 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36254 The unwinder still needs to know the size of Altivec registers. */
36256 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
36258 int column
= DWARF_REG_TO_UNWIND_COLUMN
36259 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
36260 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
36262 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
36267 /* Map internal gcc register numbers to debug format register numbers.
36268 FORMAT specifies the type of debug register number to use:
36269 0 -- debug information, except for frame-related sections
36270 1 -- DWARF .debug_frame section
36271 2 -- DWARF .eh_frame section */
36274 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
36276 /* On some platforms, we use the standard DWARF register
36277 numbering for .debug_info and .debug_frame. */
36278 if ((format
== 0 && write_symbols
== DWARF2_DEBUG
) || format
== 1)
36280 #ifdef RS6000_USE_DWARF_NUMBERING
36283 if (FP_REGNO_P (regno
))
36284 return regno
- FIRST_FPR_REGNO
+ 32;
36285 if (ALTIVEC_REGNO_P (regno
))
36286 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
36287 if (regno
== LR_REGNO
)
36289 if (regno
== CTR_REGNO
)
36291 if (regno
== CA_REGNO
)
36292 return 101; /* XER */
36293 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36294 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36295 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36296 to the DWARF reg for CR. */
36297 if (format
== 1 && regno
== CR2_REGNO
)
36299 if (CR_REGNO_P (regno
))
36300 return regno
- CR0_REGNO
+ 86;
36301 if (regno
== VRSAVE_REGNO
)
36303 if (regno
== VSCR_REGNO
)
36305 if (regno
== TFHAR_REGNO
)
36307 if (regno
== TFIAR_REGNO
)
36309 if (regno
== TEXASR_REGNO
)
36312 /* These do not make much sense. */
36313 if (regno
== FRAME_POINTER_REGNUM
)
36315 if (regno
== ARG_POINTER_REGNUM
)
36320 gcc_unreachable ();
36324 /* We use the GCC 7 (and before) internal number for non-DWARF debug
36325 information, and also for .eh_frame. */
36326 /* Translate the regnos to their numbers in GCC 7 (and before). */
36329 if (FP_REGNO_P (regno
))
36330 return regno
- FIRST_FPR_REGNO
+ 32;
36331 if (ALTIVEC_REGNO_P (regno
))
36332 return regno
- FIRST_ALTIVEC_REGNO
+ 77;
36333 if (regno
== LR_REGNO
)
36335 if (regno
== CTR_REGNO
)
36337 if (regno
== CA_REGNO
)
36338 return 76; /* XER */
36339 if (CR_REGNO_P (regno
))
36340 return regno
- CR0_REGNO
+ 68;
36341 if (regno
== VRSAVE_REGNO
)
36343 if (regno
== VSCR_REGNO
)
36345 if (regno
== TFHAR_REGNO
)
36347 if (regno
== TFIAR_REGNO
)
36349 if (regno
== TEXASR_REGNO
)
36352 if (regno
== FRAME_POINTER_REGNUM
)
36354 if (regno
== ARG_POINTER_REGNUM
)
36359 gcc_unreachable ();
36362 /* target hook eh_return_filter_mode */
36363 static scalar_int_mode
36364 rs6000_eh_return_filter_mode (void)
36366 return TARGET_32BIT
? SImode
: word_mode
;
36369 /* Target hook for translate_mode_attribute. */
36370 static machine_mode
36371 rs6000_translate_mode_attribute (machine_mode mode
)
36373 if ((FLOAT128_IEEE_P (mode
)
36374 && ieee128_float_type_node
== long_double_type_node
)
36375 || (FLOAT128_IBM_P (mode
)
36376 && ibm128_float_type_node
== long_double_type_node
))
36377 return COMPLEX_MODE_P (mode
) ? E_TCmode
: E_TFmode
;
36381 /* Target hook for scalar_mode_supported_p. */
36383 rs6000_scalar_mode_supported_p (scalar_mode mode
)
36385 /* -m32 does not support TImode. This is the default, from
36386 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36387 same ABI as for -m32. But default_scalar_mode_supported_p allows
36388 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36389 for -mpowerpc64. */
36390 if (TARGET_32BIT
&& mode
== TImode
)
36393 if (DECIMAL_FLOAT_MODE_P (mode
))
36394 return default_decimal_float_supported_p ();
36395 else if (TARGET_FLOAT128_TYPE
&& (mode
== KFmode
|| mode
== IFmode
))
36398 return default_scalar_mode_supported_p (mode
);
36401 /* Target hook for vector_mode_supported_p. */
36403 rs6000_vector_mode_supported_p (machine_mode mode
)
36405 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36406 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36408 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
) && !FLOAT128_IEEE_P (mode
))
36415 /* Target hook for floatn_mode. */
36416 static opt_scalar_float_mode
36417 rs6000_floatn_mode (int n
, bool extended
)
36427 if (TARGET_FLOAT128_TYPE
)
36428 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36430 return opt_scalar_float_mode ();
36433 return opt_scalar_float_mode ();
36436 /* Those are the only valid _FloatNx types. */
36437 gcc_unreachable ();
36451 if (TARGET_FLOAT128_TYPE
)
36452 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36454 return opt_scalar_float_mode ();
36457 return opt_scalar_float_mode ();
36463 /* Target hook for c_mode_for_suffix. */
36464 static machine_mode
36465 rs6000_c_mode_for_suffix (char suffix
)
36467 if (TARGET_FLOAT128_TYPE
)
36469 if (suffix
== 'q' || suffix
== 'Q')
36470 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
36472 /* At the moment, we are not defining a suffix for IBM extended double.
36473 If/when the default for -mabi=ieeelongdouble is changed, and we want
36474 to support __ibm128 constants in legacy library code, we may need to
36475 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36476 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36477 __float80 constants. */
36483 /* Target hook for invalid_arg_for_unprototyped_fn. */
36484 static const char *
36485 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
36487 return (!rs6000_darwin64_abi
36489 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
36490 && (funcdecl
== NULL_TREE
36491 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
36492 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
36493 ? N_("AltiVec argument passed to unprototyped function")
36497 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36498 setup by using __stack_chk_fail_local hidden function instead of
36499 calling __stack_chk_fail directly. Otherwise it is better to call
36500 __stack_chk_fail directly. */
36502 static tree ATTRIBUTE_UNUSED
36503 rs6000_stack_protect_fail (void)
36505 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
36506 ? default_hidden_stack_protect_fail ()
36507 : default_external_stack_protect_fail ();
36510 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36513 static unsigned HOST_WIDE_INT
36514 rs6000_asan_shadow_offset (void)
36516 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
36520 /* Mask options that we want to support inside of attribute((target)) and
36521 #pragma GCC target operations. Note, we do not include things like
36522 64/32-bit, endianness, hard/soft floating point, etc. that would have
36523 different calling sequences. */
36525 struct rs6000_opt_mask
{
36526 const char *name
; /* option name */
36527 HOST_WIDE_INT mask
; /* mask to set */
36528 bool invert
; /* invert sense of mask */
36529 bool valid_target
; /* option is a target option */
36532 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
36534 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
36535 { "cmpb", OPTION_MASK_CMPB
, false, true },
36536 { "crypto", OPTION_MASK_CRYPTO
, false, true },
36537 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
36538 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
36539 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX
,
36541 { "float128", OPTION_MASK_FLOAT128_KEYWORD
, false, true },
36542 { "float128-hardware", OPTION_MASK_FLOAT128_HW
, false, true },
36543 { "fprnd", OPTION_MASK_FPRND
, false, true },
36544 { "hard-dfp", OPTION_MASK_DFP
, false, true },
36545 { "htm", OPTION_MASK_HTM
, false, true },
36546 { "isel", OPTION_MASK_ISEL
, false, true },
36547 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
36548 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
36549 { "modulo", OPTION_MASK_MODULO
, false, true },
36550 { "mulhw", OPTION_MASK_MULHW
, false, true },
36551 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
36552 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
36553 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
36554 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
36555 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
36556 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
36557 { "power9-minmax", OPTION_MASK_P9_MINMAX
, false, true },
36558 { "power9-misc", OPTION_MASK_P9_MISC
, false, true },
36559 { "power9-vector", OPTION_MASK_P9_VECTOR
, false, true },
36560 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
36561 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
36562 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
36563 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
36564 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
36565 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
36566 { "string", 0, false, true },
36567 { "update", OPTION_MASK_NO_UPDATE
, true , true },
36568 { "vsx", OPTION_MASK_VSX
, false, true },
36569 #ifdef OPTION_MASK_64BIT
36571 { "aix64", OPTION_MASK_64BIT
, false, false },
36572 { "aix32", OPTION_MASK_64BIT
, true, false },
36574 { "64", OPTION_MASK_64BIT
, false, false },
36575 { "32", OPTION_MASK_64BIT
, true, false },
36578 #ifdef OPTION_MASK_EABI
36579 { "eabi", OPTION_MASK_EABI
, false, false },
36581 #ifdef OPTION_MASK_LITTLE_ENDIAN
36582 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
36583 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
36585 #ifdef OPTION_MASK_RELOCATABLE
36586 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
36588 #ifdef OPTION_MASK_STRICT_ALIGN
36589 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
36591 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
36592 { "string", 0, false, false },
36595 /* Builtin mask mapping for printing the flags. */
36596 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
36598 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
36599 { "vsx", RS6000_BTM_VSX
, false, false },
36600 { "fre", RS6000_BTM_FRE
, false, false },
36601 { "fres", RS6000_BTM_FRES
, false, false },
36602 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
36603 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
36604 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
36605 { "cell", RS6000_BTM_CELL
, false, false },
36606 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
36607 { "power9-vector", RS6000_BTM_P9_VECTOR
, false, false },
36608 { "power9-misc", RS6000_BTM_P9_MISC
, false, false },
36609 { "crypto", RS6000_BTM_CRYPTO
, false, false },
36610 { "htm", RS6000_BTM_HTM
, false, false },
36611 { "hard-dfp", RS6000_BTM_DFP
, false, false },
36612 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
36613 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
36614 { "powerpc64", RS6000_BTM_POWERPC64
, false, false },
36615 { "float128", RS6000_BTM_FLOAT128
, false, false },
36616 { "float128-hw", RS6000_BTM_FLOAT128_HW
,false, false },
36619 /* Option variables that we want to support inside attribute((target)) and
36620 #pragma GCC target operations. */
36622 struct rs6000_opt_var
{
36623 const char *name
; /* option name */
36624 size_t global_offset
; /* offset of the option in global_options. */
36625 size_t target_offset
; /* offset of the option in target options. */
36628 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
36631 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
36632 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
36633 { "avoid-indexed-addresses",
36634 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
36635 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
36637 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
36638 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
36639 { "optimize-swaps",
36640 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
36641 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
36642 { "allow-movmisalign",
36643 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
36644 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
36646 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
36647 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
36649 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
36650 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
36651 { "align-branch-targets",
36652 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
36653 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
36655 offsetof (struct gcc_options
, x_tls_markers
),
36656 offsetof (struct cl_target_option
, x_tls_markers
), },
36658 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36659 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36661 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
36662 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
36663 { "speculate-indirect-jumps",
36664 offsetof (struct gcc_options
, x_rs6000_speculate_indirect_jumps
),
36665 offsetof (struct cl_target_option
, x_rs6000_speculate_indirect_jumps
), },
36668 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36669 parsing. Return true if there were no errors. */
36672 rs6000_inner_target_options (tree args
, bool attr_p
)
36676 if (args
== NULL_TREE
)
36679 else if (TREE_CODE (args
) == STRING_CST
)
36681 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36684 while ((q
= strtok (p
, ",")) != NULL
)
36686 bool error_p
= false;
36687 bool not_valid_p
= false;
36688 const char *cpu_opt
= NULL
;
36691 if (strncmp (q
, "cpu=", 4) == 0)
36693 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
36694 if (cpu_index
>= 0)
36695 rs6000_cpu_index
= cpu_index
;
36702 else if (strncmp (q
, "tune=", 5) == 0)
36704 int tune_index
= rs6000_cpu_name_lookup (q
+5);
36705 if (tune_index
>= 0)
36706 rs6000_tune_index
= tune_index
;
36716 bool invert
= false;
36720 if (strncmp (r
, "no-", 3) == 0)
36726 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
36727 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
36729 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
36731 if (!rs6000_opt_masks
[i
].valid_target
)
36732 not_valid_p
= true;
36736 rs6000_isa_flags_explicit
|= mask
;
36738 /* VSX needs altivec, so -mvsx automagically sets
36739 altivec and disables -mavoid-indexed-addresses. */
36742 if (mask
== OPTION_MASK_VSX
)
36744 mask
|= OPTION_MASK_ALTIVEC
;
36745 TARGET_AVOID_XFORM
= 0;
36749 if (rs6000_opt_masks
[i
].invert
)
36753 rs6000_isa_flags
&= ~mask
;
36755 rs6000_isa_flags
|= mask
;
36760 if (error_p
&& !not_valid_p
)
36762 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
36763 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
36765 size_t j
= rs6000_opt_vars
[i
].global_offset
;
36766 *((int *) ((char *)&global_options
+ j
)) = !invert
;
36768 not_valid_p
= false;
36776 const char *eprefix
, *esuffix
;
36781 eprefix
= "__attribute__((__target__(";
36786 eprefix
= "#pragma GCC target ";
36791 error ("invalid cpu %qs for %s%qs%s", cpu_opt
, eprefix
,
36793 else if (not_valid_p
)
36794 error ("%s%qs%s is not allowed", eprefix
, q
, esuffix
);
36796 error ("%s%qs%s is invalid", eprefix
, q
, esuffix
);
36801 else if (TREE_CODE (args
) == TREE_LIST
)
36805 tree value
= TREE_VALUE (args
);
36808 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
36812 args
= TREE_CHAIN (args
);
36814 while (args
!= NULL_TREE
);
36819 error ("attribute %<target%> argument not a string");
36826 /* Print out the target options as a list for -mdebug=target. */
36829 rs6000_debug_target_options (tree args
, const char *prefix
)
36831 if (args
== NULL_TREE
)
36832 fprintf (stderr
, "%s<NULL>", prefix
);
36834 else if (TREE_CODE (args
) == STRING_CST
)
36836 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
36839 while ((q
= strtok (p
, ",")) != NULL
)
36842 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
36847 else if (TREE_CODE (args
) == TREE_LIST
)
36851 tree value
= TREE_VALUE (args
);
36854 rs6000_debug_target_options (value
, prefix
);
36857 args
= TREE_CHAIN (args
);
36859 while (args
!= NULL_TREE
);
36863 gcc_unreachable ();
36869 /* Hook to validate attribute((target("..."))). */
36872 rs6000_valid_attribute_p (tree fndecl
,
36873 tree
ARG_UNUSED (name
),
36877 struct cl_target_option cur_target
;
36880 tree new_target
, new_optimize
;
36881 tree func_optimize
;
36883 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
36885 if (TARGET_DEBUG_TARGET
)
36887 tree tname
= DECL_NAME (fndecl
);
36888 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
36890 fprintf (stderr
, "function: %.*s\n",
36891 (int) IDENTIFIER_LENGTH (tname
),
36892 IDENTIFIER_POINTER (tname
));
36894 fprintf (stderr
, "function: unknown\n");
36896 fprintf (stderr
, "args:");
36897 rs6000_debug_target_options (args
, " ");
36898 fprintf (stderr
, "\n");
36901 fprintf (stderr
, "flags: 0x%x\n", flags
);
36903 fprintf (stderr
, "--------------------\n");
36906 /* attribute((target("default"))) does nothing, beyond
36907 affecting multi-versioning. */
36908 if (TREE_VALUE (args
)
36909 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
36910 && TREE_CHAIN (args
) == NULL_TREE
36911 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args
)), "default") == 0)
36914 old_optimize
= build_optimization_node (&global_options
);
36915 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
36917 /* If the function changed the optimization levels as well as setting target
36918 options, start with the optimizations specified. */
36919 if (func_optimize
&& func_optimize
!= old_optimize
)
36920 cl_optimization_restore (&global_options
,
36921 TREE_OPTIMIZATION (func_optimize
));
36923 /* The target attributes may also change some optimization flags, so update
36924 the optimization options if necessary. */
36925 cl_target_option_save (&cur_target
, &global_options
);
36926 rs6000_cpu_index
= rs6000_tune_index
= -1;
36927 ret
= rs6000_inner_target_options (args
, true);
36929 /* Set up any additional state. */
36932 ret
= rs6000_option_override_internal (false);
36933 new_target
= build_target_option_node (&global_options
);
36938 new_optimize
= build_optimization_node (&global_options
);
36945 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
36947 if (old_optimize
!= new_optimize
)
36948 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
36951 cl_target_option_restore (&global_options
, &cur_target
);
36953 if (old_optimize
!= new_optimize
)
36954 cl_optimization_restore (&global_options
,
36955 TREE_OPTIMIZATION (old_optimize
));
36961 /* Hook to validate the current #pragma GCC target and set the state, and
36962 update the macros based on what was changed. If ARGS is NULL, then
36963 POP_TARGET is used to reset the options. */
36966 rs6000_pragma_target_parse (tree args
, tree pop_target
)
36968 tree prev_tree
= build_target_option_node (&global_options
);
36970 struct cl_target_option
*prev_opt
, *cur_opt
;
36971 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
36972 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
36974 if (TARGET_DEBUG_TARGET
)
36976 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
36977 fprintf (stderr
, "args:");
36978 rs6000_debug_target_options (args
, " ");
36979 fprintf (stderr
, "\n");
36983 fprintf (stderr
, "pop_target:\n");
36984 debug_tree (pop_target
);
36987 fprintf (stderr
, "pop_target: <NULL>\n");
36989 fprintf (stderr
, "--------------------\n");
36994 cur_tree
= ((pop_target
)
36996 : target_option_default_node
);
36997 cl_target_option_restore (&global_options
,
36998 TREE_TARGET_OPTION (cur_tree
));
37002 rs6000_cpu_index
= rs6000_tune_index
= -1;
37003 if (!rs6000_inner_target_options (args
, false)
37004 || !rs6000_option_override_internal (false)
37005 || (cur_tree
= build_target_option_node (&global_options
))
37008 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
37009 fprintf (stderr
, "invalid pragma\n");
37015 target_option_current_node
= cur_tree
;
37016 rs6000_activate_target_options (target_option_current_node
);
37018 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
37019 change the macros that are defined. */
37020 if (rs6000_target_modify_macros_ptr
)
37022 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
37023 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
37024 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
37026 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
37027 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
37028 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
37030 diff_bumask
= (prev_bumask
^ cur_bumask
);
37031 diff_flags
= (prev_flags
^ cur_flags
);
37033 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
37035 /* Delete old macros. */
37036 rs6000_target_modify_macros_ptr (false,
37037 prev_flags
& diff_flags
,
37038 prev_bumask
& diff_bumask
);
37040 /* Define new macros. */
37041 rs6000_target_modify_macros_ptr (true,
37042 cur_flags
& diff_flags
,
37043 cur_bumask
& diff_bumask
);
37051 /* Remember the last target of rs6000_set_current_function. */
37052 static GTY(()) tree rs6000_previous_fndecl
;
37054 /* Restore target's globals from NEW_TREE and invalidate the
37055 rs6000_previous_fndecl cache. */
37058 rs6000_activate_target_options (tree new_tree
)
37060 cl_target_option_restore (&global_options
, TREE_TARGET_OPTION (new_tree
));
37061 if (TREE_TARGET_GLOBALS (new_tree
))
37062 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
37063 else if (new_tree
== target_option_default_node
)
37064 restore_target_globals (&default_target_globals
);
37066 TREE_TARGET_GLOBALS (new_tree
) = save_target_globals_default_opts ();
37067 rs6000_previous_fndecl
= NULL_TREE
;
37070 /* Establish appropriate back-end context for processing the function
37071 FNDECL. The argument might be NULL to indicate processing at top
37072 level, outside of any function scope. */
37074 rs6000_set_current_function (tree fndecl
)
37076 if (TARGET_DEBUG_TARGET
)
37078 fprintf (stderr
, "\n==================== rs6000_set_current_function");
37081 fprintf (stderr
, ", fndecl %s (%p)",
37082 (DECL_NAME (fndecl
)
37083 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
37084 : "<unknown>"), (void *)fndecl
);
37086 if (rs6000_previous_fndecl
)
37087 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
37089 fprintf (stderr
, "\n");
37092 /* Only change the context if the function changes. This hook is called
37093 several times in the course of compiling a function, and we don't want to
37094 slow things down too much or call target_reinit when it isn't safe. */
37095 if (fndecl
== rs6000_previous_fndecl
)
37099 if (rs6000_previous_fndecl
== NULL_TREE
)
37100 old_tree
= target_option_current_node
;
37101 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
))
37102 old_tree
= DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
);
37104 old_tree
= target_option_default_node
;
37107 if (fndecl
== NULL_TREE
)
37109 if (old_tree
!= target_option_current_node
)
37110 new_tree
= target_option_current_node
;
37112 new_tree
= NULL_TREE
;
37116 new_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
37117 if (new_tree
== NULL_TREE
)
37118 new_tree
= target_option_default_node
;
37121 if (TARGET_DEBUG_TARGET
)
37125 fprintf (stderr
, "\nnew fndecl target specific options:\n");
37126 debug_tree (new_tree
);
37131 fprintf (stderr
, "\nold fndecl target specific options:\n");
37132 debug_tree (old_tree
);
37135 if (old_tree
!= NULL_TREE
|| new_tree
!= NULL_TREE
)
37136 fprintf (stderr
, "--------------------\n");
37139 if (new_tree
&& old_tree
!= new_tree
)
37140 rs6000_activate_target_options (new_tree
);
37143 rs6000_previous_fndecl
= fndecl
;
37147 /* Save the current options */
37150 rs6000_function_specific_save (struct cl_target_option
*ptr
,
37151 struct gcc_options
*opts
)
37153 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
37154 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
37157 /* Restore the current options */
37160 rs6000_function_specific_restore (struct gcc_options
*opts
,
37161 struct cl_target_option
*ptr
)
37164 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
37165 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
37166 (void) rs6000_option_override_internal (false);
37169 /* Print the current options */
37172 rs6000_function_specific_print (FILE *file
, int indent
,
37173 struct cl_target_option
*ptr
)
37175 rs6000_print_isa_options (file
, indent
, "Isa options set",
37176 ptr
->x_rs6000_isa_flags
);
37178 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
37179 ptr
->x_rs6000_isa_flags_explicit
);
37182 /* Helper function to print the current isa or misc options on a line. */
37185 rs6000_print_options_internal (FILE *file
,
37187 const char *string
,
37188 HOST_WIDE_INT flags
,
37189 const char *prefix
,
37190 const struct rs6000_opt_mask
*opts
,
37191 size_t num_elements
)
37194 size_t start_column
= 0;
37196 size_t max_column
= 120;
37197 size_t prefix_len
= strlen (prefix
);
37198 size_t comma_len
= 0;
37199 const char *comma
= "";
37202 start_column
+= fprintf (file
, "%*s", indent
, "");
37206 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
37210 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
37212 /* Print the various mask options. */
37213 cur_column
= start_column
;
37214 for (i
= 0; i
< num_elements
; i
++)
37216 bool invert
= opts
[i
].invert
;
37217 const char *name
= opts
[i
].name
;
37218 const char *no_str
= "";
37219 HOST_WIDE_INT mask
= opts
[i
].mask
;
37220 size_t len
= comma_len
+ prefix_len
+ strlen (name
);
37224 if ((flags
& mask
) == 0)
37227 len
+= sizeof ("no-") - 1;
37235 if ((flags
& mask
) != 0)
37238 len
+= sizeof ("no-") - 1;
37245 if (cur_column
> max_column
)
37247 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
37248 cur_column
= start_column
+ len
;
37252 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
, name
);
37254 comma_len
= sizeof (", ") - 1;
37257 fputs ("\n", file
);
37260 /* Helper function to print the current isa options on a line. */
37263 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
37264 HOST_WIDE_INT flags
)
37266 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
37267 &rs6000_opt_masks
[0],
37268 ARRAY_SIZE (rs6000_opt_masks
));
37272 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
37273 HOST_WIDE_INT flags
)
37275 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
37276 &rs6000_builtin_mask_names
[0],
37277 ARRAY_SIZE (rs6000_builtin_mask_names
));
37280 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37281 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37282 -mupper-regs-df, etc.).
37284 If the user used -mno-power8-vector, we need to turn off all of the implicit
37285 ISA 2.07 and 3.0 options that relate to the vector unit.
37287 If the user used -mno-power9-vector, we need to turn off all of the implicit
37288 ISA 3.0 options that relate to the vector unit.
37290 This function does not handle explicit options such as the user specifying
37291 -mdirect-move. These are handled in rs6000_option_override_internal, and
37292 the appropriate error is given if needed.
37294 We return a mask of all of the implicit options that should not be enabled
37297 static HOST_WIDE_INT
37298 rs6000_disable_incompatible_switches (void)
37300 HOST_WIDE_INT ignore_masks
= rs6000_isa_flags_explicit
;
37303 static const struct {
37304 const HOST_WIDE_INT no_flag
; /* flag explicitly turned off. */
37305 const HOST_WIDE_INT dep_flags
; /* flags that depend on this option. */
37306 const char *const name
; /* name of the switch. */
37308 { OPTION_MASK_P9_VECTOR
, OTHER_P9_VECTOR_MASKS
, "power9-vector" },
37309 { OPTION_MASK_P8_VECTOR
, OTHER_P8_VECTOR_MASKS
, "power8-vector" },
37310 { OPTION_MASK_VSX
, OTHER_VSX_VECTOR_MASKS
, "vsx" },
37313 for (i
= 0; i
< ARRAY_SIZE (flags
); i
++)
37315 HOST_WIDE_INT no_flag
= flags
[i
].no_flag
;
37317 if ((rs6000_isa_flags
& no_flag
) == 0
37318 && (rs6000_isa_flags_explicit
& no_flag
) != 0)
37320 HOST_WIDE_INT dep_flags
= flags
[i
].dep_flags
;
37321 HOST_WIDE_INT set_flags
= (rs6000_isa_flags_explicit
37327 for (j
= 0; j
< ARRAY_SIZE (rs6000_opt_masks
); j
++)
37328 if ((set_flags
& rs6000_opt_masks
[j
].mask
) != 0)
37330 set_flags
&= ~rs6000_opt_masks
[j
].mask
;
37331 error ("%<-mno-%s%> turns off %<-m%s%>",
37333 rs6000_opt_masks
[j
].name
);
37336 gcc_assert (!set_flags
);
37339 rs6000_isa_flags
&= ~dep_flags
;
37340 ignore_masks
|= no_flag
| dep_flags
;
37344 return ignore_masks
;
37348 /* Helper function for printing the function name when debugging. */
37350 static const char *
37351 get_decl_name (tree fn
)
37358 name
= DECL_NAME (fn
);
37360 return "<no-name>";
37362 return IDENTIFIER_POINTER (name
);
37365 /* Return the clone id of the target we are compiling code for in a target
37366 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37367 the priority list for the target clones (ordered from lowest to
37371 rs6000_clone_priority (tree fndecl
)
37373 tree fn_opts
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
37374 HOST_WIDE_INT isa_masks
;
37375 int ret
= CLONE_DEFAULT
;
37376 tree attrs
= lookup_attribute ("target", DECL_ATTRIBUTES (fndecl
));
37377 const char *attrs_str
= NULL
;
37379 attrs
= TREE_VALUE (TREE_VALUE (attrs
));
37380 attrs_str
= TREE_STRING_POINTER (attrs
);
37382 /* Return priority zero for default function. Return the ISA needed for the
37383 function if it is not the default. */
37384 if (strcmp (attrs_str
, "default") != 0)
37386 if (fn_opts
== NULL_TREE
)
37387 fn_opts
= target_option_default_node
;
37389 if (!fn_opts
|| !TREE_TARGET_OPTION (fn_opts
))
37390 isa_masks
= rs6000_isa_flags
;
37392 isa_masks
= TREE_TARGET_OPTION (fn_opts
)->x_rs6000_isa_flags
;
37394 for (ret
= CLONE_MAX
- 1; ret
!= 0; ret
--)
37395 if ((rs6000_clone_map
[ret
].isa_mask
& isa_masks
) != 0)
37399 if (TARGET_DEBUG_TARGET
)
37400 fprintf (stderr
, "rs6000_get_function_version_priority (%s) => %d\n",
37401 get_decl_name (fndecl
), ret
);
37406 /* This compares the priority of target features in function DECL1 and DECL2.
37407 It returns positive value if DECL1 is higher priority, negative value if
37408 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37409 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37412 rs6000_compare_version_priority (tree decl1
, tree decl2
)
37414 int priority1
= rs6000_clone_priority (decl1
);
37415 int priority2
= rs6000_clone_priority (decl2
);
37416 int ret
= priority1
- priority2
;
37418 if (TARGET_DEBUG_TARGET
)
37419 fprintf (stderr
, "rs6000_compare_version_priority (%s, %s) => %d\n",
37420 get_decl_name (decl1
), get_decl_name (decl2
), ret
);
37425 /* Make a dispatcher declaration for the multi-versioned function DECL.
37426 Calls to DECL function will be replaced with calls to the dispatcher
37427 by the front-end. Returns the decl of the dispatcher function. */
37430 rs6000_get_function_versions_dispatcher (void *decl
)
37432 tree fn
= (tree
) decl
;
37433 struct cgraph_node
*node
= NULL
;
37434 struct cgraph_node
*default_node
= NULL
;
37435 struct cgraph_function_version_info
*node_v
= NULL
;
37436 struct cgraph_function_version_info
*first_v
= NULL
;
37438 tree dispatch_decl
= NULL
;
37440 struct cgraph_function_version_info
*default_version_info
= NULL
;
37441 gcc_assert (fn
!= NULL
&& DECL_FUNCTION_VERSIONED (fn
));
37443 if (TARGET_DEBUG_TARGET
)
37444 fprintf (stderr
, "rs6000_get_function_versions_dispatcher (%s)\n",
37445 get_decl_name (fn
));
37447 node
= cgraph_node::get (fn
);
37448 gcc_assert (node
!= NULL
);
37450 node_v
= node
->function_version ();
37451 gcc_assert (node_v
!= NULL
);
37453 if (node_v
->dispatcher_resolver
!= NULL
)
37454 return node_v
->dispatcher_resolver
;
37456 /* Find the default version and make it the first node. */
37458 /* Go to the beginning of the chain. */
37459 while (first_v
->prev
!= NULL
)
37460 first_v
= first_v
->prev
;
37462 default_version_info
= first_v
;
37463 while (default_version_info
!= NULL
)
37465 const tree decl2
= default_version_info
->this_node
->decl
;
37466 if (is_function_default_version (decl2
))
37468 default_version_info
= default_version_info
->next
;
37471 /* If there is no default node, just return NULL. */
37472 if (default_version_info
== NULL
)
37475 /* Make default info the first node. */
37476 if (first_v
!= default_version_info
)
37478 default_version_info
->prev
->next
= default_version_info
->next
;
37479 if (default_version_info
->next
)
37480 default_version_info
->next
->prev
= default_version_info
->prev
;
37481 first_v
->prev
= default_version_info
;
37482 default_version_info
->next
= first_v
;
37483 default_version_info
->prev
= NULL
;
37486 default_node
= default_version_info
->this_node
;
37488 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37489 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
37490 "target_clones attribute needs GLIBC (2.23 and newer) that "
37491 "exports hardware capability bits");
37494 if (targetm
.has_ifunc_p ())
37496 struct cgraph_function_version_info
*it_v
= NULL
;
37497 struct cgraph_node
*dispatcher_node
= NULL
;
37498 struct cgraph_function_version_info
*dispatcher_version_info
= NULL
;
37500 /* Right now, the dispatching is done via ifunc. */
37501 dispatch_decl
= make_dispatcher_decl (default_node
->decl
);
37503 dispatcher_node
= cgraph_node::get_create (dispatch_decl
);
37504 gcc_assert (dispatcher_node
!= NULL
);
37505 dispatcher_node
->dispatcher_function
= 1;
37506 dispatcher_version_info
37507 = dispatcher_node
->insert_new_function_version ();
37508 dispatcher_version_info
->next
= default_version_info
;
37509 dispatcher_node
->definition
= 1;
37511 /* Set the dispatcher for all the versions. */
37512 it_v
= default_version_info
;
37513 while (it_v
!= NULL
)
37515 it_v
->dispatcher_resolver
= dispatch_decl
;
37521 error_at (DECL_SOURCE_LOCATION (default_node
->decl
),
37522 "multiversioning needs ifunc which is not supported "
37527 return dispatch_decl
;
37530 /* Make the resolver function decl to dispatch the versions of a multi-
37531 versioned function, DEFAULT_DECL. Create an empty basic block in the
37532 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37536 make_resolver_func (const tree default_decl
,
37537 const tree dispatch_decl
,
37538 basic_block
*empty_bb
)
37540 /* Make the resolver function static. The resolver function returns
37542 tree decl_name
= clone_function_name (default_decl
, "resolver");
37543 const char *resolver_name
= IDENTIFIER_POINTER (decl_name
);
37544 tree type
= build_function_type_list (ptr_type_node
, NULL_TREE
);
37545 tree decl
= build_fn_decl (resolver_name
, type
);
37546 SET_DECL_ASSEMBLER_NAME (decl
, decl_name
);
37548 DECL_NAME (decl
) = decl_name
;
37549 TREE_USED (decl
) = 1;
37550 DECL_ARTIFICIAL (decl
) = 1;
37551 DECL_IGNORED_P (decl
) = 0;
37552 TREE_PUBLIC (decl
) = 0;
37553 DECL_UNINLINABLE (decl
) = 1;
37555 /* Resolver is not external, body is generated. */
37556 DECL_EXTERNAL (decl
) = 0;
37557 DECL_EXTERNAL (dispatch_decl
) = 0;
37559 DECL_CONTEXT (decl
) = NULL_TREE
;
37560 DECL_INITIAL (decl
) = make_node (BLOCK
);
37561 DECL_STATIC_CONSTRUCTOR (decl
) = 0;
37563 /* Build result decl and add to function_decl. */
37564 tree t
= build_decl (UNKNOWN_LOCATION
, RESULT_DECL
, NULL_TREE
, ptr_type_node
);
37565 DECL_CONTEXT (t
) = decl
;
37566 DECL_ARTIFICIAL (t
) = 1;
37567 DECL_IGNORED_P (t
) = 1;
37568 DECL_RESULT (decl
) = t
;
37570 gimplify_function_tree (decl
);
37571 push_cfun (DECL_STRUCT_FUNCTION (decl
));
37572 *empty_bb
= init_lowered_empty_function (decl
, false,
37573 profile_count::uninitialized ());
37575 cgraph_node::add_new_function (decl
, true);
37576 symtab
->call_cgraph_insertion_hooks (cgraph_node::get_create (decl
));
37580 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37581 DECL_ATTRIBUTES (dispatch_decl
)
37582 = make_attribute ("ifunc", resolver_name
, DECL_ATTRIBUTES (dispatch_decl
));
37584 cgraph_node::create_same_body_alias (dispatch_decl
, decl
);
37589 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37590 return a pointer to VERSION_DECL if we are running on a machine that
37591 supports the index CLONE_ISA hardware architecture bits. This function will
37592 be called during version dispatch to decide which function version to
37593 execute. It returns the basic block at the end, to which more conditions
37597 add_condition_to_bb (tree function_decl
, tree version_decl
,
37598 int clone_isa
, basic_block new_bb
)
37600 push_cfun (DECL_STRUCT_FUNCTION (function_decl
));
37602 gcc_assert (new_bb
!= NULL
);
37603 gimple_seq gseq
= bb_seq (new_bb
);
37606 tree convert_expr
= build1 (CONVERT_EXPR
, ptr_type_node
,
37607 build_fold_addr_expr (version_decl
));
37608 tree result_var
= create_tmp_var (ptr_type_node
);
37609 gimple
*convert_stmt
= gimple_build_assign (result_var
, convert_expr
);
37610 gimple
*return_stmt
= gimple_build_return (result_var
);
37612 if (clone_isa
== CLONE_DEFAULT
)
37614 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37615 gimple_seq_add_stmt (&gseq
, return_stmt
);
37616 set_bb_seq (new_bb
, gseq
);
37617 gimple_set_bb (convert_stmt
, new_bb
);
37618 gimple_set_bb (return_stmt
, new_bb
);
37623 tree bool_zero
= build_int_cst (bool_int_type_node
, 0);
37624 tree cond_var
= create_tmp_var (bool_int_type_node
);
37625 tree predicate_decl
= rs6000_builtin_decls
[(int) RS6000_BUILTIN_CPU_SUPPORTS
];
37626 const char *arg_str
= rs6000_clone_map
[clone_isa
].name
;
37627 tree predicate_arg
= build_string_literal (strlen (arg_str
) + 1, arg_str
);
37628 gimple
*call_cond_stmt
= gimple_build_call (predicate_decl
, 1, predicate_arg
);
37629 gimple_call_set_lhs (call_cond_stmt
, cond_var
);
37631 gimple_set_block (call_cond_stmt
, DECL_INITIAL (function_decl
));
37632 gimple_set_bb (call_cond_stmt
, new_bb
);
37633 gimple_seq_add_stmt (&gseq
, call_cond_stmt
);
37635 gimple
*if_else_stmt
= gimple_build_cond (NE_EXPR
, cond_var
, bool_zero
,
37636 NULL_TREE
, NULL_TREE
);
37637 gimple_set_block (if_else_stmt
, DECL_INITIAL (function_decl
));
37638 gimple_set_bb (if_else_stmt
, new_bb
);
37639 gimple_seq_add_stmt (&gseq
, if_else_stmt
);
37641 gimple_seq_add_stmt (&gseq
, convert_stmt
);
37642 gimple_seq_add_stmt (&gseq
, return_stmt
);
37643 set_bb_seq (new_bb
, gseq
);
37645 basic_block bb1
= new_bb
;
37646 edge e12
= split_block (bb1
, if_else_stmt
);
37647 basic_block bb2
= e12
->dest
;
37648 e12
->flags
&= ~EDGE_FALLTHRU
;
37649 e12
->flags
|= EDGE_TRUE_VALUE
;
37651 edge e23
= split_block (bb2
, return_stmt
);
37652 gimple_set_bb (convert_stmt
, bb2
);
37653 gimple_set_bb (return_stmt
, bb2
);
37655 basic_block bb3
= e23
->dest
;
37656 make_edge (bb1
, bb3
, EDGE_FALSE_VALUE
);
37659 make_edge (bb2
, EXIT_BLOCK_PTR_FOR_FN (cfun
), 0);
37665 /* This function generates the dispatch function for multi-versioned functions.
37666 DISPATCH_DECL is the function which will contain the dispatch logic.
37667 FNDECLS are the function choices for dispatch, and is a tree chain.
37668 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37669 code is generated. */
37672 dispatch_function_versions (tree dispatch_decl
,
37674 basic_block
*empty_bb
)
37678 vec
<tree
> *fndecls
;
37679 tree clones
[CLONE_MAX
];
37681 if (TARGET_DEBUG_TARGET
)
37682 fputs ("dispatch_function_versions, top\n", stderr
);
37684 gcc_assert (dispatch_decl
!= NULL
37685 && fndecls_p
!= NULL
37686 && empty_bb
!= NULL
);
37688 /* fndecls_p is actually a vector. */
37689 fndecls
= static_cast<vec
<tree
> *> (fndecls_p
);
37691 /* At least one more version other than the default. */
37692 gcc_assert (fndecls
->length () >= 2);
37694 /* The first version in the vector is the default decl. */
37695 memset ((void *) clones
, '\0', sizeof (clones
));
37696 clones
[CLONE_DEFAULT
] = (*fndecls
)[0];
37698 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37699 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37700 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37701 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37702 to insert the code here to do the call. */
37704 for (ix
= 1; fndecls
->iterate (ix
, &ele
); ++ix
)
37706 int priority
= rs6000_clone_priority (ele
);
37707 if (!clones
[priority
])
37708 clones
[priority
] = ele
;
37711 for (ix
= CLONE_MAX
- 1; ix
>= 0; ix
--)
37714 if (TARGET_DEBUG_TARGET
)
37715 fprintf (stderr
, "dispatch_function_versions, clone %d, %s\n",
37716 ix
, get_decl_name (clones
[ix
]));
37718 *empty_bb
= add_condition_to_bb (dispatch_decl
, clones
[ix
], ix
,
37725 /* Generate the dispatching code body to dispatch multi-versioned function
37726 DECL. The target hook is called to process the "target" attributes and
37727 provide the code to dispatch the right function at run-time. NODE points
37728 to the dispatcher decl whose body will be created. */
37731 rs6000_generate_version_dispatcher_body (void *node_p
)
37734 basic_block empty_bb
;
37735 struct cgraph_node
*node
= (cgraph_node
*) node_p
;
37736 struct cgraph_function_version_info
*ninfo
= node
->function_version ();
37738 if (ninfo
->dispatcher_resolver
)
37739 return ninfo
->dispatcher_resolver
;
37741 /* node is going to be an alias, so remove the finalized bit. */
37742 node
->definition
= false;
37744 /* The first version in the chain corresponds to the default version. */
37745 ninfo
->dispatcher_resolver
= resolver
37746 = make_resolver_func (ninfo
->next
->this_node
->decl
, node
->decl
, &empty_bb
);
37748 if (TARGET_DEBUG_TARGET
)
37749 fprintf (stderr
, "rs6000_get_function_versions_dispatcher, %s\n",
37750 get_decl_name (resolver
));
37752 push_cfun (DECL_STRUCT_FUNCTION (resolver
));
37753 auto_vec
<tree
, 2> fn_ver_vec
;
37755 for (struct cgraph_function_version_info
*vinfo
= ninfo
->next
;
37757 vinfo
= vinfo
->next
)
37759 struct cgraph_node
*version
= vinfo
->this_node
;
37760 /* Check for virtual functions here again, as by this time it should
37761 have been determined if this function needs a vtable index or
37762 not. This happens for methods in derived classes that override
37763 virtual methods in base classes but are not explicitly marked as
37765 if (DECL_VINDEX (version
->decl
))
37766 sorry ("Virtual function multiversioning not supported");
37768 fn_ver_vec
.safe_push (version
->decl
);
37771 dispatch_function_versions (resolver
, &fn_ver_vec
, &empty_bb
);
37772 cgraph_edge::rebuild_edges ();
37778 /* Hook to determine if one function can safely inline another. */
37781 rs6000_can_inline_p (tree caller
, tree callee
)
37784 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
37785 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
37787 /* If callee has no option attributes, then it is ok to inline. */
37791 /* If caller has no option attributes, but callee does then it is not ok to
37793 else if (!caller_tree
)
37798 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
37799 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
37801 /* Callee's options should a subset of the caller's, i.e. a vsx function
37802 can inline an altivec function but a non-vsx function can't inline a
37804 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
37805 == callee_opts
->x_rs6000_isa_flags
)
37809 if (TARGET_DEBUG_TARGET
)
37810 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37811 get_decl_name (caller
), get_decl_name (callee
),
37812 (ret
? "can" : "cannot"));
37817 /* Allocate a stack temp and fixup the address so it meets the particular
37818 memory requirements (either offetable or REG+REG addressing). */
37821 rs6000_allocate_stack_temp (machine_mode mode
,
37822 bool offsettable_p
,
37825 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
37826 rtx addr
= XEXP (stack
, 0);
37827 int strict_p
= reload_completed
;
37829 if (!legitimate_indirect_address_p (addr
, strict_p
))
37832 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
37833 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37835 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
37836 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
37842 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37843 convert to such a form to deal with memory reference instructions
37844 like STFIWX and LDBRX that only take reg+reg addressing. */
37847 rs6000_force_indexed_or_indirect_mem (rtx x
)
37849 machine_mode mode
= GET_MODE (x
);
37851 gcc_assert (MEM_P (x
));
37852 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x
, mode
))
37854 rtx addr
= XEXP (x
, 0);
37855 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
37857 rtx reg
= XEXP (addr
, 0);
37858 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
37859 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
37860 gcc_assert (REG_P (reg
));
37861 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
37864 else if (GET_CODE (addr
) == PRE_MODIFY
)
37866 rtx reg
= XEXP (addr
, 0);
37867 rtx expr
= XEXP (addr
, 1);
37868 gcc_assert (REG_P (reg
));
37869 gcc_assert (GET_CODE (expr
) == PLUS
);
37870 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
37874 x
= replace_equiv_address (x
, force_reg (Pmode
, addr
));
37880 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37882 On the RS/6000, all integer constants are acceptable, most won't be valid
37883 for particular insns, though. Only easy FP constants are acceptable. */
37886 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
37888 if (TARGET_ELF
&& tls_referenced_p (x
))
37891 if (CONST_DOUBLE_P (x
))
37892 return easy_fp_constant (x
, mode
);
37894 if (GET_CODE (x
) == CONST_VECTOR
)
37895 return easy_vector_constant (x
, mode
);
37901 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37904 chain_already_loaded (rtx_insn
*last
)
37906 for (; last
!= NULL
; last
= PREV_INSN (last
))
37908 if (NONJUMP_INSN_P (last
))
37910 rtx patt
= PATTERN (last
);
37912 if (GET_CODE (patt
) == SET
)
37914 rtx lhs
= XEXP (patt
, 0);
37916 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
37924 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37927 rs6000_call_aix (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
37929 rtx func
= func_desc
;
37930 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
37931 rtx toc_load
= NULL_RTX
;
37932 rtx toc_restore
= NULL_RTX
;
37934 rtx abi_reg
= NULL_RTX
;
37938 bool is_pltseq_longcall
;
37941 tlsarg
= global_tlsarg
;
37943 /* Handle longcall attributes. */
37944 is_pltseq_longcall
= false;
37945 if ((INTVAL (cookie
) & CALL_LONG
) != 0
37946 && GET_CODE (func_desc
) == SYMBOL_REF
)
37948 func
= rs6000_longcall_ref (func_desc
, tlsarg
);
37950 is_pltseq_longcall
= true;
37953 /* Handle indirect calls. */
37954 if (!SYMBOL_REF_P (func
)
37955 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func
)))
37957 /* Save the TOC into its reserved slot before the call,
37958 and prepare to restore it after the call. */
37959 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
37960 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
37961 gen_rtvec (1, stack_toc_offset
),
37963 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
37965 /* Can we optimize saving the TOC in the prologue or
37966 do we need to do it at every call? */
37967 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
37968 cfun
->machine
->save_toc_in_prologue
= true;
37971 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
37972 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
37973 gen_rtx_PLUS (Pmode
, stack_ptr
,
37974 stack_toc_offset
));
37975 MEM_VOLATILE_P (stack_toc_mem
) = 1;
37976 if (is_pltseq_longcall
)
37978 /* Use USPEC_PLTSEQ here to emit every instruction in an
37979 inline PLT call sequence with a reloc, enabling the
37980 linker to edit the sequence back to a direct call
37981 when that makes sense. */
37982 rtvec v
= gen_rtvec (3, toc_reg
, func_desc
, tlsarg
);
37983 rtx mark_toc_reg
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
37984 emit_insn (gen_rtx_SET (stack_toc_mem
, mark_toc_reg
));
37987 emit_move_insn (stack_toc_mem
, toc_reg
);
37990 if (DEFAULT_ABI
== ABI_ELFv2
)
37992 /* A function pointer in the ELFv2 ABI is just a plain address, but
37993 the ABI requires it to be loaded into r12 before the call. */
37994 func_addr
= gen_rtx_REG (Pmode
, 12);
37995 if (!rtx_equal_p (func_addr
, func
))
37996 emit_move_insn (func_addr
, func
);
37997 abi_reg
= func_addr
;
37998 /* Indirect calls via CTR are strongly preferred over indirect
37999 calls via LR, so move the address there. Needed to mark
38000 this insn for linker plt sequence editing too. */
38001 func_addr
= gen_rtx_REG (Pmode
, CTR_REGNO
);
38002 if (is_pltseq_longcall
)
38004 rtvec v
= gen_rtvec (3, abi_reg
, func_desc
, tlsarg
);
38005 rtx mark_func
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
38006 emit_insn (gen_rtx_SET (func_addr
, mark_func
));
38007 v
= gen_rtvec (2, func_addr
, func_desc
);
38008 func_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
38011 emit_move_insn (func_addr
, abi_reg
);
38015 /* A function pointer under AIX is a pointer to a data area whose
38016 first word contains the actual address of the function, whose
38017 second word contains a pointer to its TOC, and whose third word
38018 contains a value to place in the static chain register (r11).
38019 Note that if we load the static chain, our "trampoline" need
38020 not have any executable code. */
38022 /* Load up address of the actual function. */
38023 func
= force_reg (Pmode
, func
);
38024 func_addr
= gen_reg_rtx (Pmode
);
38025 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func
));
38027 /* Indirect calls via CTR are strongly preferred over indirect
38028 calls via LR, so move the address there. */
38029 rtx ctr_reg
= gen_rtx_REG (Pmode
, CTR_REGNO
);
38030 emit_move_insn (ctr_reg
, func_addr
);
38031 func_addr
= ctr_reg
;
38033 /* Prepare to load the TOC of the called function. Note that the
38034 TOC load must happen immediately before the actual call so
38035 that unwinding the TOC registers works correctly. See the
38036 comment in frob_update_context. */
38037 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
38038 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
38039 gen_rtx_PLUS (Pmode
, func
,
38041 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
38043 /* If we have a static chain, load it up. But, if the call was
38044 originally direct, the 3rd word has not been written since no
38045 trampoline has been built, so we ought not to load it, lest we
38046 override a static chain value. */
38047 if (!(GET_CODE (func_desc
) == SYMBOL_REF
38048 && SYMBOL_REF_FUNCTION_P (func_desc
))
38049 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
38050 && !chain_already_loaded (get_current_sequence ()->next
->last
))
38052 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
38053 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
38054 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
38055 gen_rtx_PLUS (Pmode
, func
,
38057 emit_move_insn (sc_reg
, func_sc_mem
);
38064 /* Direct calls use the TOC: for local calls, the callee will
38065 assume the TOC register is set; for non-local calls, the
38066 PLT stub needs the TOC register. */
38071 /* Create the call. */
38072 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), tlsarg
);
38073 if (value
!= NULL_RTX
)
38074 call
[0] = gen_rtx_SET (value
, call
[0]);
38078 call
[n_call
++] = toc_load
;
38080 call
[n_call
++] = toc_restore
;
38082 call
[n_call
++] = gen_hard_reg_clobber (Pmode
, LR_REGNO
);
38084 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
38085 insn
= emit_call_insn (insn
);
38087 /* Mention all registers defined by the ABI to hold information
38088 as uses in CALL_INSN_FUNCTION_USAGE. */
38090 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
38093 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
38096 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
38101 gcc_assert (INTVAL (cookie
) == 0);
38104 tlsarg
= global_tlsarg
;
38106 /* Create the call. */
38107 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), tlsarg
);
38108 if (value
!= NULL_RTX
)
38109 call
[0] = gen_rtx_SET (value
, call
[0]);
38111 call
[1] = simple_return_rtx
;
38113 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
38114 insn
= emit_call_insn (insn
);
38116 /* Note use of the TOC register. */
38117 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
38120 /* Expand code to perform a call under the SYSV4 ABI. */
38123 rs6000_call_sysv (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
38125 rtx func
= func_desc
;
38129 rtx abi_reg
= NULL_RTX
;
38133 tlsarg
= global_tlsarg
;
38135 /* Handle longcall attributes. */
38136 if ((INTVAL (cookie
) & CALL_LONG
) != 0
38137 && GET_CODE (func_desc
) == SYMBOL_REF
)
38139 func
= rs6000_longcall_ref (func_desc
, tlsarg
);
38140 /* If the longcall was implemented as an inline PLT call using
38141 PLT unspecs then func will be REG:r11. If not, func will be
38142 a pseudo reg. The inline PLT call sequence supports lazy
38143 linking (and longcalls to functions in dlopen'd libraries).
38144 The other style of longcalls don't. The lazy linking entry
38145 to the dynamic symbol resolver requires r11 be the function
38146 address (as it is for linker generated PLT stubs). Ensure
38147 r11 stays valid to the bctrl by marking r11 used by the call. */
38152 /* Handle indirect calls. */
38153 if (GET_CODE (func
) != SYMBOL_REF
)
38155 func
= force_reg (Pmode
, func
);
38157 /* Indirect calls via CTR are strongly preferred over indirect
38158 calls via LR, so move the address there. That can't be left
38159 to reload because we want to mark every instruction in an
38160 inline PLT call sequence with a reloc, enabling the linker to
38161 edit the sequence back to a direct call when that makes sense. */
38162 func_addr
= gen_rtx_REG (Pmode
, CTR_REGNO
);
38165 rtvec v
= gen_rtvec (3, func
, func_desc
, tlsarg
);
38166 rtx mark_func
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
38167 emit_insn (gen_rtx_SET (func_addr
, mark_func
));
38168 v
= gen_rtvec (2, func_addr
, func_desc
);
38169 func_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
38172 emit_move_insn (func_addr
, func
);
38177 /* Create the call. */
38178 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), tlsarg
);
38179 if (value
!= NULL_RTX
)
38180 call
[0] = gen_rtx_SET (value
, call
[0]);
38182 call
[1] = gen_rtx_USE (VOIDmode
, cookie
);
38184 if (TARGET_SECURE_PLT
38186 && GET_CODE (func_addr
) == SYMBOL_REF
38187 && !SYMBOL_REF_LOCAL_P (func_addr
))
38188 call
[n
++] = gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
);
38190 call
[n
++] = gen_hard_reg_clobber (Pmode
, LR_REGNO
);
38192 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n
, call
));
38193 insn
= emit_call_insn (insn
);
38195 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
38198 /* Expand code to perform a sibling call under the SysV4 ABI. */
38201 rs6000_sibcall_sysv (rtx value
, rtx func_desc
, rtx tlsarg
, rtx cookie
)
38203 rtx func
= func_desc
;
38207 rtx abi_reg
= NULL_RTX
;
38210 tlsarg
= global_tlsarg
;
38212 /* Handle longcall attributes. */
38213 if ((INTVAL (cookie
) & CALL_LONG
) != 0
38214 && GET_CODE (func_desc
) == SYMBOL_REF
)
38216 func
= rs6000_longcall_ref (func_desc
, tlsarg
);
38217 /* If the longcall was implemented as an inline PLT call using
38218 PLT unspecs then func will be REG:r11. If not, func will be
38219 a pseudo reg. The inline PLT call sequence supports lazy
38220 linking (and longcalls to functions in dlopen'd libraries).
38221 The other style of longcalls don't. The lazy linking entry
38222 to the dynamic symbol resolver requires r11 be the function
38223 address (as it is for linker generated PLT stubs). Ensure
38224 r11 stays valid to the bctr by marking r11 used by the call. */
38229 /* Handle indirect calls. */
38230 if (GET_CODE (func
) != SYMBOL_REF
)
38232 func
= force_reg (Pmode
, func
);
38234 /* Indirect sibcalls must go via CTR. That can't be left to
38235 reload because we want to mark every instruction in an inline
38236 PLT call sequence with a reloc, enabling the linker to edit
38237 the sequence back to a direct call when that makes sense. */
38238 func_addr
= gen_rtx_REG (Pmode
, CTR_REGNO
);
38241 rtvec v
= gen_rtvec (3, func
, func_desc
, tlsarg
);
38242 rtx mark_func
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
38243 emit_insn (gen_rtx_SET (func_addr
, mark_func
));
38244 v
= gen_rtvec (2, func_addr
, func_desc
);
38245 func_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_PLTSEQ
);
38248 emit_move_insn (func_addr
, func
);
38253 /* Create the call. */
38254 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), tlsarg
);
38255 if (value
!= NULL_RTX
)
38256 call
[0] = gen_rtx_SET (value
, call
[0]);
38258 call
[1] = gen_rtx_USE (VOIDmode
, cookie
);
38259 call
[2] = simple_return_rtx
;
38261 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (3, call
));
38262 insn
= emit_call_insn (insn
);
38264 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
38269 /* Expand code to perform a call under the Darwin ABI.
38270 Modulo handling of mlongcall, this is much the same as sysv.
38271 if/when the longcall optimisation is removed, we could drop this
38272 code and use the sysv case (taking care to avoid the tls stuff).
38274 We can use this for sibcalls too, if needed. */
38277 rs6000_call_darwin_1 (rtx value
, rtx func_desc
, rtx tlsarg
,
38278 rtx cookie
, bool sibcall
)
38280 rtx func
= func_desc
;
38284 int cookie_val
= INTVAL (cookie
);
38285 bool make_island
= false;
38287 /* Handle longcall attributes, there are two cases for Darwin:
38288 1) Newer linkers are capable of synthesising any branch islands needed.
38289 2) We need a helper branch island synthesised by the compiler.
38290 The second case has mostly been retired and we don't use it for m64.
38291 In fact, it's is an optimisation, we could just indirect as sysv does..
38292 ... however, backwards compatibility for now.
38293 If we're going to use this, then we need to keep the CALL_LONG bit set,
38294 so that we can pick up the special insn form later. */
38295 if ((cookie_val
& CALL_LONG
) != 0
38296 && GET_CODE (func_desc
) == SYMBOL_REF
)
38298 if (darwin_emit_branch_islands
&& TARGET_32BIT
)
38299 make_island
= true; /* Do nothing yet, retain the CALL_LONG flag. */
38302 /* The linker is capable of doing this, but the user explicitly
38303 asked for -mlongcall, so we'll do the 'normal' version. */
38304 func
= rs6000_longcall_ref (func_desc
, NULL_RTX
);
38305 cookie_val
&= ~CALL_LONG
; /* Handled, zap it. */
38309 /* Handle indirect calls. */
38310 if (GET_CODE (func
) != SYMBOL_REF
)
38312 func
= force_reg (Pmode
, func
);
38314 /* Indirect calls via CTR are strongly preferred over indirect
38315 calls via LR, and are required for indirect sibcalls, so move
38316 the address there. */
38317 func_addr
= gen_rtx_REG (Pmode
, CTR_REGNO
);
38318 emit_move_insn (func_addr
, func
);
38323 /* Create the call. */
38324 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), tlsarg
);
38325 if (value
!= NULL_RTX
)
38326 call
[0] = gen_rtx_SET (value
, call
[0]);
38328 call
[1] = gen_rtx_USE (VOIDmode
, GEN_INT (cookie_val
));
38331 call
[2] = simple_return_rtx
;
38333 call
[2] = gen_hard_reg_clobber (Pmode
, LR_REGNO
);
38335 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (3, call
));
38336 insn
= emit_call_insn (insn
);
38337 /* Now we have the debug info in the insn, we can set up the branch island
38338 if we're using one. */
38341 tree funname
= get_identifier (XSTR (func_desc
, 0));
38343 if (no_previous_def (funname
))
38345 rtx label_rtx
= gen_label_rtx ();
38346 char *label_buf
, temp_buf
[256];
38347 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
38348 CODE_LABEL_NUMBER (label_rtx
));
38349 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
38350 tree labelname
= get_identifier (label_buf
);
38351 add_compiler_branch_island (labelname
, funname
,
38352 insn_line ((const rtx_insn
*)insn
));
38359 rs6000_call_darwin (rtx value ATTRIBUTE_UNUSED
, rtx func_desc ATTRIBUTE_UNUSED
,
38360 rtx tlsarg ATTRIBUTE_UNUSED
, rtx cookie ATTRIBUTE_UNUSED
)
38363 rs6000_call_darwin_1 (value
, func_desc
, tlsarg
, cookie
, false);
38371 rs6000_sibcall_darwin (rtx value ATTRIBUTE_UNUSED
, rtx func_desc ATTRIBUTE_UNUSED
,
38372 rtx tlsarg ATTRIBUTE_UNUSED
, rtx cookie ATTRIBUTE_UNUSED
)
38375 rs6000_call_darwin_1 (value
, func_desc
, tlsarg
, cookie
, true);
38382 /* Return whether we need to always update the saved TOC pointer when we update
38383 the stack pointer. */
38386 rs6000_save_toc_in_prologue_p (void)
38388 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
38391 #ifdef HAVE_GAS_HIDDEN
38392 # define USE_HIDDEN_LINKONCE 1
38394 # define USE_HIDDEN_LINKONCE 0
38397 /* Fills in the label name that should be used for a 476 link stack thunk. */
38400 get_ppc476_thunk_name (char name
[32])
38402 gcc_assert (TARGET_LINK_STACK
);
38404 if (USE_HIDDEN_LINKONCE
)
38405 sprintf (name
, "__ppc476.get_thunk");
38407 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
38410 /* This function emits the simple thunk routine that is used to preserve
38411 the link stack on the 476 cpu. */
38413 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
38415 rs6000_code_end (void)
38420 if (!TARGET_LINK_STACK
)
38423 get_ppc476_thunk_name (name
);
38425 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
38426 build_function_type_list (void_type_node
, NULL_TREE
));
38427 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
38428 NULL_TREE
, void_type_node
);
38429 TREE_PUBLIC (decl
) = 1;
38430 TREE_STATIC (decl
) = 1;
38433 if (USE_HIDDEN_LINKONCE
&& !TARGET_XCOFF
)
38435 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
38436 targetm
.asm_out
.unique_section (decl
, 0);
38437 switch_to_section (get_named_section (decl
, NULL
, 0));
38438 DECL_WEAK (decl
) = 1;
38439 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
38440 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
38441 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
38442 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
38447 switch_to_section (text_section
);
38448 ASM_OUTPUT_LABEL (asm_out_file
, name
);
38451 DECL_INITIAL (decl
) = make_node (BLOCK
);
38452 current_function_decl
= decl
;
38453 allocate_struct_function (decl
, false);
38454 init_function_start (decl
);
38455 first_function_block_is_cold
= false;
38456 /* Make sure unwind info is emitted for the thunk if needed. */
38457 final_start_function (emit_barrier (), asm_out_file
, 1);
38459 fputs ("\tblr\n", asm_out_file
);
38461 final_end_function ();
38462 init_insn_lengths ();
38463 free_after_compilation (cfun
);
38465 current_function_decl
= NULL
;
38468 /* Add r30 to hard reg set if the prologue sets it up and it is not
38469 pic_offset_table_rtx. */
38472 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
38474 if (!TARGET_SINGLE_PIC_BASE
38476 && TARGET_MINIMAL_TOC
38477 && !constant_pool_empty_p ())
38478 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
38479 if (cfun
->machine
->split_stack_argp_used
)
38480 add_to_hard_reg_set (&set
->set
, Pmode
, 12);
38482 /* Make sure the hard reg set doesn't include r2, which was possibly added
38483 via PIC_OFFSET_TABLE_REGNUM. */
38485 remove_from_hard_reg_set (&set
->set
, Pmode
, TOC_REGNUM
);
38489 /* Helper function for rs6000_split_logical to emit a logical instruction after
38490 spliting the operation to single GPR registers.
38492 DEST is the destination register.
38493 OP1 and OP2 are the input source registers.
38494 CODE is the base operation (AND, IOR, XOR, NOT).
38495 MODE is the machine mode.
38496 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38497 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38498 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38501 rs6000_split_logical_inner (rtx dest
,
38504 enum rtx_code code
,
38506 bool complement_final_p
,
38507 bool complement_op1_p
,
38508 bool complement_op2_p
)
38512 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38513 if (op2
&& CONST_INT_P (op2
)
38514 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
38515 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
38517 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
38518 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
38520 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38525 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
38529 else if (value
== mask
)
38531 if (!rtx_equal_p (dest
, op1
))
38532 emit_insn (gen_rtx_SET (dest
, op1
));
38537 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38538 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38539 else if (code
== IOR
|| code
== XOR
)
38543 if (!rtx_equal_p (dest
, op1
))
38544 emit_insn (gen_rtx_SET (dest
, op1
));
38550 if (code
== AND
&& mode
== SImode
38551 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
38553 emit_insn (gen_andsi3 (dest
, op1
, op2
));
38557 if (complement_op1_p
)
38558 op1
= gen_rtx_NOT (mode
, op1
);
38560 if (complement_op2_p
)
38561 op2
= gen_rtx_NOT (mode
, op2
);
38563 /* For canonical RTL, if only one arm is inverted it is the first. */
38564 if (!complement_op1_p
&& complement_op2_p
)
38565 std::swap (op1
, op2
);
38567 bool_rtx
= ((code
== NOT
)
38568 ? gen_rtx_NOT (mode
, op1
)
38569 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
38571 if (complement_final_p
)
38572 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
38574 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
38577 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38578 operations are split immediately during RTL generation to allow for more
38579 optimizations of the AND/IOR/XOR.
38581 OPERANDS is an array containing the destination and two input operands.
38582 CODE is the base operation (AND, IOR, XOR, NOT).
38583 MODE is the machine mode.
38584 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38585 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38586 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38587 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38588 formation of the AND instructions. */
38591 rs6000_split_logical_di (rtx operands
[3],
38592 enum rtx_code code
,
38593 bool complement_final_p
,
38594 bool complement_op1_p
,
38595 bool complement_op2_p
)
38597 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
38598 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
38599 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
38600 enum hi_lo
{ hi
= 0, lo
= 1 };
38601 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
38604 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
38605 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
38606 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
38607 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
38610 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
38613 if (!CONST_INT_P (operands
[2]))
38615 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
38616 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
38620 HOST_WIDE_INT value
= INTVAL (operands
[2]);
38621 HOST_WIDE_INT value_hi_lo
[2];
38623 gcc_assert (!complement_final_p
);
38624 gcc_assert (!complement_op1_p
);
38625 gcc_assert (!complement_op2_p
);
38627 value_hi_lo
[hi
] = value
>> 32;
38628 value_hi_lo
[lo
] = value
& lower_32bits
;
38630 for (i
= 0; i
< 2; i
++)
38632 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
38634 if (sub_value
& sign_bit
)
38635 sub_value
|= upper_32bits
;
38637 op2_hi_lo
[i
] = GEN_INT (sub_value
);
38639 /* If this is an AND instruction, check to see if we need to load
38640 the value in a register. */
38641 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
38642 && !and_operand (op2_hi_lo
[i
], SImode
))
38643 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
38648 for (i
= 0; i
< 2; i
++)
38650 /* Split large IOR/XOR operations. */
38651 if ((code
== IOR
|| code
== XOR
)
38652 && CONST_INT_P (op2_hi_lo
[i
])
38653 && !complement_final_p
38654 && !complement_op1_p
38655 && !complement_op2_p
38656 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
38658 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
38659 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
38660 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
38661 rtx tmp
= gen_reg_rtx (SImode
);
38663 /* Make sure the constant is sign extended. */
38664 if ((hi_16bits
& sign_bit
) != 0)
38665 hi_16bits
|= upper_32bits
;
38667 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
38668 code
, SImode
, false, false, false);
38670 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
38671 code
, SImode
, false, false, false);
38674 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
38675 code
, SImode
, complement_final_p
,
38676 complement_op1_p
, complement_op2_p
);
38682 /* Split the insns that make up boolean operations operating on multiple GPR
38683 registers. The boolean MD patterns ensure that the inputs either are
38684 exactly the same as the output registers, or there is no overlap.
38686 OPERANDS is an array containing the destination and two input operands.
38687 CODE is the base operation (AND, IOR, XOR, NOT).
38688 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38689 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38690 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38693 rs6000_split_logical (rtx operands
[3],
38694 enum rtx_code code
,
38695 bool complement_final_p
,
38696 bool complement_op1_p
,
38697 bool complement_op2_p
)
38699 machine_mode mode
= GET_MODE (operands
[0]);
38700 machine_mode sub_mode
;
38702 int sub_size
, regno0
, regno1
, nregs
, i
;
38704 /* If this is DImode, use the specialized version that can run before
38705 register allocation. */
38706 if (mode
== DImode
&& !TARGET_POWERPC64
)
38708 rs6000_split_logical_di (operands
, code
, complement_final_p
,
38709 complement_op1_p
, complement_op2_p
);
38715 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
38716 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
38717 sub_size
= GET_MODE_SIZE (sub_mode
);
38718 regno0
= REGNO (op0
);
38719 regno1
= REGNO (op1
);
38721 gcc_assert (reload_completed
);
38722 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38723 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38725 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
38726 gcc_assert (nregs
> 1);
38728 if (op2
&& REG_P (op2
))
38729 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38731 for (i
= 0; i
< nregs
; i
++)
38733 int offset
= i
* sub_size
;
38734 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
38735 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
38736 rtx sub_op2
= ((code
== NOT
)
38738 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
38740 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
38741 complement_final_p
, complement_op1_p
,
38749 /* Return true if the peephole2 can combine a load involving a combination of
38750 an addis instruction and a load with an offset that can be fused together on
38754 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
38755 rtx addis_value
, /* addis value. */
38756 rtx target
, /* target register that is loaded. */
38757 rtx mem
) /* bottom part of the memory addr. */
38762 /* Validate arguments. */
38763 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
38766 if (!base_reg_operand (target
, GET_MODE (target
)))
38769 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
38772 /* Allow sign/zero extension. */
38773 if (GET_CODE (mem
) == ZERO_EXTEND
38774 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
38775 mem
= XEXP (mem
, 0);
38780 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
38783 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
38784 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
38787 /* Validate that the register used to load the high value is either the
38788 register being loaded, or we can safely replace its use.
38790 This function is only called from the peephole2 pass and we assume that
38791 there are 2 instructions in the peephole (addis and load), so we want to
38792 check if the target register was not used in the memory address and the
38793 register to hold the addis result is dead after the peephole. */
38794 if (REGNO (addis_reg
) != REGNO (target
))
38796 if (reg_mentioned_p (target
, mem
))
38799 if (!peep2_reg_dead_p (2, addis_reg
))
38802 /* If the target register being loaded is the stack pointer, we must
38803 avoid loading any other value into it, even temporarily. */
38804 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
38808 base_reg
= XEXP (addr
, 0);
38809 return REGNO (addis_reg
) == REGNO (base_reg
);
38812 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38813 sequence. We adjust the addis register to use the target register. If the
38814 load sign extends, we adjust the code to do the zero extending load, and an
38815 explicit sign extension later since the fusion only covers zero extending
38819 operands[0] register set with addis (to be replaced with target)
38820 operands[1] value set via addis
38821 operands[2] target register being loaded
38822 operands[3] D-form memory reference using operands[0]. */
38825 expand_fusion_gpr_load (rtx
*operands
)
38827 rtx addis_value
= operands
[1];
38828 rtx target
= operands
[2];
38829 rtx orig_mem
= operands
[3];
38830 rtx new_addr
, new_mem
, orig_addr
, offset
;
38831 enum rtx_code plus_or_lo_sum
;
38832 machine_mode target_mode
= GET_MODE (target
);
38833 machine_mode extend_mode
= target_mode
;
38834 machine_mode ptr_mode
= Pmode
;
38835 enum rtx_code extend
= UNKNOWN
;
38837 if (GET_CODE (orig_mem
) == ZERO_EXTEND
38838 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
38840 extend
= GET_CODE (orig_mem
);
38841 orig_mem
= XEXP (orig_mem
, 0);
38842 target_mode
= GET_MODE (orig_mem
);
38845 gcc_assert (MEM_P (orig_mem
));
38847 orig_addr
= XEXP (orig_mem
, 0);
38848 plus_or_lo_sum
= GET_CODE (orig_addr
);
38849 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
38851 offset
= XEXP (orig_addr
, 1);
38852 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
38853 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
38855 if (extend
!= UNKNOWN
)
38856 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
38858 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
38859 UNSPEC_FUSION_GPR
);
38860 emit_insn (gen_rtx_SET (target
, new_mem
));
38862 if (extend
== SIGN_EXTEND
)
38864 int sub_off
= ((BYTES_BIG_ENDIAN
)
38865 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
38868 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
38870 emit_insn (gen_rtx_SET (target
,
38871 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
38877 /* Emit the addis instruction that will be part of a fused instruction
38881 emit_fusion_addis (rtx target
, rtx addis_value
)
38884 const char *addis_str
= NULL
;
38886 /* Emit the addis instruction. */
38887 fuse_ops
[0] = target
;
38888 if (satisfies_constraint_L (addis_value
))
38890 fuse_ops
[1] = addis_value
;
38891 addis_str
= "lis %0,%v1";
38894 else if (GET_CODE (addis_value
) == PLUS
)
38896 rtx op0
= XEXP (addis_value
, 0);
38897 rtx op1
= XEXP (addis_value
, 1);
38899 if (REG_P (op0
) && CONST_INT_P (op1
)
38900 && satisfies_constraint_L (op1
))
38904 addis_str
= "addis %0,%1,%v2";
38908 else if (GET_CODE (addis_value
) == HIGH
)
38910 rtx value
= XEXP (addis_value
, 0);
38911 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
38913 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
38914 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
38916 addis_str
= "addis %0,%2,%1@toc@ha";
38918 else if (TARGET_XCOFF
)
38919 addis_str
= "addis %0,%1@u(%2)";
38922 gcc_unreachable ();
38925 else if (GET_CODE (value
) == PLUS
)
38927 rtx op0
= XEXP (value
, 0);
38928 rtx op1
= XEXP (value
, 1);
38930 if (GET_CODE (op0
) == UNSPEC
38931 && XINT (op0
, 1) == UNSPEC_TOCREL
38932 && CONST_INT_P (op1
))
38934 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
38935 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
38938 addis_str
= "addis %0,%2,%1+%3@toc@ha";
38940 else if (TARGET_XCOFF
)
38941 addis_str
= "addis %0,%1+%3@u(%2)";
38944 gcc_unreachable ();
38948 else if (satisfies_constraint_L (value
))
38950 fuse_ops
[1] = value
;
38951 addis_str
= "lis %0,%v1";
38954 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
38956 fuse_ops
[1] = value
;
38957 addis_str
= "lis %0,%1@ha";
38962 fatal_insn ("Could not generate addis value for fusion", addis_value
);
38964 output_asm_insn (addis_str
, fuse_ops
);
38967 /* Emit a D-form load or store instruction that is the second instruction
38968 of a fusion sequence. */
38971 emit_fusion_load (rtx load_reg
, rtx addis_reg
, rtx offset
, const char *insn_str
)
38974 char insn_template
[80];
38976 fuse_ops
[0] = load_reg
;
38977 fuse_ops
[1] = addis_reg
;
38979 if (CONST_INT_P (offset
) && satisfies_constraint_I (offset
))
38981 sprintf (insn_template
, "%s %%0,%%2(%%1)", insn_str
);
38982 fuse_ops
[2] = offset
;
38983 output_asm_insn (insn_template
, fuse_ops
);
38986 else if (GET_CODE (offset
) == UNSPEC
38987 && XINT (offset
, 1) == UNSPEC_TOCREL
)
38990 sprintf (insn_template
, "%s %%0,%%2@toc@l(%%1)", insn_str
);
38992 else if (TARGET_XCOFF
)
38993 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
38996 gcc_unreachable ();
38998 fuse_ops
[2] = XVECEXP (offset
, 0, 0);
38999 output_asm_insn (insn_template
, fuse_ops
);
39002 else if (GET_CODE (offset
) == PLUS
39003 && GET_CODE (XEXP (offset
, 0)) == UNSPEC
39004 && XINT (XEXP (offset
, 0), 1) == UNSPEC_TOCREL
39005 && CONST_INT_P (XEXP (offset
, 1)))
39007 rtx tocrel_unspec
= XEXP (offset
, 0);
39009 sprintf (insn_template
, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str
);
39011 else if (TARGET_XCOFF
)
39012 sprintf (insn_template
, "%s %%0,%%2+%%3@l(%%1)", insn_str
);
39015 gcc_unreachable ();
39017 fuse_ops
[2] = XVECEXP (tocrel_unspec
, 0, 0);
39018 fuse_ops
[3] = XEXP (offset
, 1);
39019 output_asm_insn (insn_template
, fuse_ops
);
39022 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (offset
))
39024 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
39026 fuse_ops
[2] = offset
;
39027 output_asm_insn (insn_template
, fuse_ops
);
39031 fatal_insn ("Unable to generate load/store offset for fusion", offset
);
39036 /* Given an address, convert it into the addis and load offset parts. Addresses
39037 created during the peephole2 process look like:
39038 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
39039 (unspec [(...)] UNSPEC_TOCREL)) */
39042 fusion_split_address (rtx addr
, rtx
*p_hi
, rtx
*p_lo
)
39046 if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
39048 hi
= XEXP (addr
, 0);
39049 lo
= XEXP (addr
, 1);
39052 gcc_unreachable ();
39058 /* Return a string to fuse an addis instruction with a gpr load to the same
39059 register that we loaded up the addis instruction. The address that is used
39060 is the logical address that was formed during peephole2:
39061 (lo_sum (high) (low-part))
39063 The code is complicated, so we call output_asm_insn directly, and just
39067 emit_fusion_gpr_load (rtx target
, rtx mem
)
39072 const char *load_str
= NULL
;
39075 if (GET_CODE (mem
) == ZERO_EXTEND
)
39076 mem
= XEXP (mem
, 0);
39078 gcc_assert (REG_P (target
) && MEM_P (mem
));
39080 addr
= XEXP (mem
, 0);
39081 fusion_split_address (addr
, &addis_value
, &load_offset
);
39083 /* Now emit the load instruction to the same register. */
39084 mode
= GET_MODE (mem
);
39102 gcc_assert (TARGET_POWERPC64
);
39107 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target
, mem
));
39110 /* Emit the addis instruction. */
39111 emit_fusion_addis (target
, addis_value
);
39113 /* Emit the D-form load instruction. */
39114 emit_fusion_load (target
, target
, load_offset
, load_str
);
39120 #ifdef RS6000_GLIBC_ATOMIC_FENV
39121 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
39122 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
39125 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
39128 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
39130 if (!TARGET_HARD_FLOAT
)
39132 #ifdef RS6000_GLIBC_ATOMIC_FENV
39133 if (atomic_hold_decl
== NULL_TREE
)
39136 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
39137 get_identifier ("__atomic_feholdexcept"),
39138 build_function_type_list (void_type_node
,
39139 double_ptr_type_node
,
39141 TREE_PUBLIC (atomic_hold_decl
) = 1;
39142 DECL_EXTERNAL (atomic_hold_decl
) = 1;
39145 if (atomic_clear_decl
== NULL_TREE
)
39148 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
39149 get_identifier ("__atomic_feclearexcept"),
39150 build_function_type_list (void_type_node
,
39152 TREE_PUBLIC (atomic_clear_decl
) = 1;
39153 DECL_EXTERNAL (atomic_clear_decl
) = 1;
39156 tree const_double
= build_qualified_type (double_type_node
,
39158 tree const_double_ptr
= build_pointer_type (const_double
);
39159 if (atomic_update_decl
== NULL_TREE
)
39162 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
39163 get_identifier ("__atomic_feupdateenv"),
39164 build_function_type_list (void_type_node
,
39167 TREE_PUBLIC (atomic_update_decl
) = 1;
39168 DECL_EXTERNAL (atomic_update_decl
) = 1;
39171 tree fenv_var
= create_tmp_var_raw (double_type_node
);
39172 TREE_ADDRESSABLE (fenv_var
) = 1;
39173 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
39175 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
39176 *clear
= build_call_expr (atomic_clear_decl
, 0);
39177 *update
= build_call_expr (atomic_update_decl
, 1,
39178 fold_convert (const_double_ptr
, fenv_addr
));
39183 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
39184 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
39185 tree call_mffs
= build_call_expr (mffs
, 0);
39187 /* Generates the equivalent of feholdexcept (&fenv_var)
39189 *fenv_var = __builtin_mffs ();
39191 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
39192 __builtin_mtfsf (0xff, fenv_hold); */
39194 /* Mask to clear everything except for the rounding modes and non-IEEE
39195 arithmetic flag. */
39196 const unsigned HOST_WIDE_INT hold_exception_mask
=
39197 HOST_WIDE_INT_C (0xffffffff00000007);
39199 tree fenv_var
= create_tmp_var_raw (double_type_node
);
39201 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
39203 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
39204 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
39205 build_int_cst (uint64_type_node
,
39206 hold_exception_mask
));
39208 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
39211 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
39212 build_int_cst (unsigned_type_node
, 0xff),
39215 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
39217 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
39219 double fenv_clear = __builtin_mffs ();
39220 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39221 __builtin_mtfsf (0xff, fenv_clear); */
39223 /* Mask to clear everything except for the rounding modes and non-IEEE
39224 arithmetic flag. */
39225 const unsigned HOST_WIDE_INT clear_exception_mask
=
39226 HOST_WIDE_INT_C (0xffffffff00000000);
39228 tree fenv_clear
= create_tmp_var_raw (double_type_node
);
39230 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
39232 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
39233 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
39235 build_int_cst (uint64_type_node
,
39236 clear_exception_mask
));
39238 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
39239 fenv_clear_llu_and
);
39241 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
39242 build_int_cst (unsigned_type_node
, 0xff),
39245 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
39247 /* Generates the equivalent of feupdateenv (&fenv_var)
39249 double old_fenv = __builtin_mffs ();
39250 double fenv_update;
39251 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39252 (*(uint64_t*)fenv_var 0x1ff80fff);
39253 __builtin_mtfsf (0xff, fenv_update); */
39255 const unsigned HOST_WIDE_INT update_exception_mask
=
39256 HOST_WIDE_INT_C (0xffffffff1fffff00);
39257 const unsigned HOST_WIDE_INT new_exception_mask
=
39258 HOST_WIDE_INT_C (0x1ff80fff);
39260 tree old_fenv
= create_tmp_var_raw (double_type_node
);
39261 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
39263 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
39264 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
39265 build_int_cst (uint64_type_node
,
39266 update_exception_mask
));
39268 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
39269 build_int_cst (uint64_type_node
,
39270 new_exception_mask
));
39272 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
39273 old_llu_and
, new_llu_and
);
39275 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
39278 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
39279 build_int_cst (unsigned_type_node
, 0xff),
39280 fenv_update_mtfsf
);
39282 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
39286 rs6000_generate_float2_double_code (rtx dst
, rtx src1
, rtx src2
)
39288 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
39290 rtx_tmp0
= gen_reg_rtx (V2DFmode
);
39291 rtx_tmp1
= gen_reg_rtx (V2DFmode
);
39293 /* The destination of the vmrgew instruction layout is:
39294 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39295 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39296 vmrgew instruction will be correct. */
39297 if (BYTES_BIG_ENDIAN
)
39299 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0
, src1
, src2
,
39301 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1
, src1
, src2
,
39306 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0
, src1
, src2
, GEN_INT (3)));
39307 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1
, src1
, src2
, GEN_INT (0)));
39310 rtx_tmp2
= gen_reg_rtx (V4SFmode
);
39311 rtx_tmp3
= gen_reg_rtx (V4SFmode
);
39313 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2
, rtx_tmp0
));
39314 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3
, rtx_tmp1
));
39316 if (BYTES_BIG_ENDIAN
)
39317 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp2
, rtx_tmp3
));
39319 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp3
, rtx_tmp2
));
39323 rs6000_generate_float2_code (bool signed_convert
, rtx dst
, rtx src1
, rtx src2
)
39325 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
39327 rtx_tmp0
= gen_reg_rtx (V2DImode
);
39328 rtx_tmp1
= gen_reg_rtx (V2DImode
);
39330 /* The destination of the vmrgew instruction layout is:
39331 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39332 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39333 vmrgew instruction will be correct. */
39334 if (BYTES_BIG_ENDIAN
)
39336 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
39337 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
39341 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0
, src1
, src2
, GEN_INT (3)));
39342 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1
, src1
, src2
, GEN_INT (0)));
39345 rtx_tmp2
= gen_reg_rtx (V4SFmode
);
39346 rtx_tmp3
= gen_reg_rtx (V4SFmode
);
39348 if (signed_convert
)
39350 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2
, rtx_tmp0
));
39351 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3
, rtx_tmp1
));
39355 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2
, rtx_tmp0
));
39356 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3
, rtx_tmp1
));
39359 if (BYTES_BIG_ENDIAN
)
39360 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp2
, rtx_tmp3
));
39362 emit_insn (gen_p8_vmrgew_v4sf (dst
, rtx_tmp3
, rtx_tmp2
));
39366 rs6000_generate_vsigned2_code (bool signed_convert
, rtx dst
, rtx src1
,
39369 rtx rtx_tmp0
, rtx_tmp1
, rtx_tmp2
, rtx_tmp3
;
39371 rtx_tmp0
= gen_reg_rtx (V2DFmode
);
39372 rtx_tmp1
= gen_reg_rtx (V2DFmode
);
39374 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0
, src1
, src2
, GEN_INT (0)));
39375 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1
, src1
, src2
, GEN_INT (3)));
39377 rtx_tmp2
= gen_reg_rtx (V4SImode
);
39378 rtx_tmp3
= gen_reg_rtx (V4SImode
);
39380 if (signed_convert
)
39382 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2
, rtx_tmp0
));
39383 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3
, rtx_tmp1
));
39387 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2
, rtx_tmp0
));
39388 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3
, rtx_tmp1
));
39391 emit_insn (gen_p8_vmrgew_v4si (dst
, rtx_tmp2
, rtx_tmp3
));
39394 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39397 rs6000_optab_supported_p (int op
, machine_mode mode1
, machine_mode
,
39398 optimization_type opt_type
)
39403 return (opt_type
== OPTIMIZE_FOR_SPEED
39404 && RS6000_RECIP_AUTO_RSQRTE_P (mode1
));
39411 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39413 static HOST_WIDE_INT
39414 rs6000_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
39416 if (TREE_CODE (exp
) == STRING_CST
39417 && (STRICT_ALIGNMENT
|| !optimize_size
))
39418 return MAX (align
, BITS_PER_WORD
);
39422 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39424 static HOST_WIDE_INT
39425 rs6000_starting_frame_offset (void)
39427 if (FRAME_GROWS_DOWNWARD
)
39429 return RS6000_STARTING_FRAME_OFFSET
;
39433 /* Create an alias for a mangled name where we have changed the mangling (in
39434 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
39435 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
39437 #if TARGET_ELF && RS6000_WEAK
39439 rs6000_globalize_decl_name (FILE * stream
, tree decl
)
39441 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
39443 targetm
.asm_out
.globalize_label (stream
, name
);
39445 if (rs6000_passes_ieee128
&& name
[0] == '_' && name
[1] == 'Z')
39447 tree save_asm_name
= DECL_ASSEMBLER_NAME (decl
);
39448 const char *old_name
;
39450 ieee128_mangling_gcc_8_1
= true;
39451 lang_hooks
.set_decl_assembler_name (decl
);
39452 old_name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
39453 SET_DECL_ASSEMBLER_NAME (decl
, save_asm_name
);
39454 ieee128_mangling_gcc_8_1
= false;
39456 if (strcmp (name
, old_name
) != 0)
39458 fprintf (stream
, "\t.weak %s\n", old_name
);
39459 fprintf (stream
, "\t.set %s,%s\n", old_name
, name
);
39466 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
39467 function names from <foo>l to <foo>f128 if the default long double type is
39468 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
39469 include file switches the names on systems that support long double as IEEE
39470 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
39471 In the future, glibc will export names like __ieee128_sinf128 and we can
39472 switch to using those instead of using sinf128, which pollutes the user's
39475 This will switch the names for Fortran math functions as well (which doesn't
39476 use math.h). However, Fortran needs other changes to the compiler and
39477 library before you can switch the real*16 type at compile time.
39479 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
39480 only do this if the default is that long double is IBM extended double, and
39481 the user asked for IEEE 128-bit. */
39484 rs6000_mangle_decl_assembler_name (tree decl
, tree id
)
39486 if (!TARGET_IEEEQUAD_DEFAULT
&& TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
39487 && TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_IS_BUILTIN (decl
) )
39489 size_t len
= IDENTIFIER_LENGTH (id
);
39490 const char *name
= IDENTIFIER_POINTER (id
);
39492 if (name
[len
- 1] == 'l')
39494 bool uses_ieee128_p
= false;
39495 tree type
= TREE_TYPE (decl
);
39496 machine_mode ret_mode
= TYPE_MODE (type
);
39498 /* See if the function returns a IEEE 128-bit floating point type or
39500 if (ret_mode
== TFmode
|| ret_mode
== TCmode
)
39501 uses_ieee128_p
= true;
39504 function_args_iterator args_iter
;
39507 /* See if the function passes a IEEE 128-bit floating point type
39508 or complex type. */
39509 FOREACH_FUNCTION_ARGS (type
, arg
, args_iter
)
39511 machine_mode arg_mode
= TYPE_MODE (arg
);
39512 if (arg_mode
== TFmode
|| arg_mode
== TCmode
)
39514 uses_ieee128_p
= true;
39520 /* If we passed or returned an IEEE 128-bit floating point type,
39521 change the name. */
39522 if (uses_ieee128_p
)
39524 char *name2
= (char *) alloca (len
+ 4);
39525 memcpy (name2
, name
, len
- 1);
39526 strcpy (name2
+ len
- 1, "f128");
39527 id
= get_identifier (name2
);
39536 struct gcc_target targetm
= TARGET_INITIALIZER
;
39538 #include "gt-rs6000.h"