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8540.md: New file.
[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5
6 ;; This file is part of GNU CC.
7
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;; `unspec' values used in rs6000.md:
26 ;; Number Use
27 ;; 0 frsp for POWER machines
28 ;; 0/v blockage
29 ;; 5 used to tie the stack contents and the stack pointer
30 ;; 6 address of a word pointing to the TOC
31 ;; 7 address of the TOC (more-or-less)
32 ;; 8 movsi_got
33 ;; 9/v eh_reg_restore
34 ;; 10 fctiwz
35 ;; 15 load_macho_picbase
36 ;; 16 macho_correct_pic
37 ;; 19 movesi_from_cr
38 ;; 20 movsi_to_cr
39 \f
40 ;; Define an insn type attribute. This is used in function unit delay
41 ;; computations.
42 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,mult_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
43 (const_string "integer"))
44
45 ;; Length (in bytes).
46 ; '(pc)' in the following doesn't include the instruction itself; it is
47 ; calculated as if the instruction had zero size.
48 (define_attr "length" ""
49 (if_then_else (eq_attr "type" "branch")
50 (if_then_else (and (ge (minus (match_dup 0) (pc))
51 (const_int -32768))
52 (lt (minus (match_dup 0) (pc))
53 (const_int 32764)))
54 (const_int 4)
55 (const_int 8))
56 (const_int 4)))
57
58 ;; Processor type -- this attribute must exactly match the processor_type
59 ;; enumeration in rs6000.h.
60
61 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
62 (const (symbol_ref "rs6000_cpu_attr")))
63
64 (automata_option "ndfa")
65
66 (include "rios1.md")
67 (include "rios2.md")
68 (include "rs64.md")
69 (include "mpc.md")
70 (include "40x.md")
71 (include "603.md")
72 (include "6xx.md")
73 (include "7xx.md")
74 (include "7450.md")
75 (include "8540.md")
76 (include "power4.md")
77
78 \f
79 ;; Start with fixed-point load and store insns. Here we put only the more
80 ;; complex forms. Basic data transfer is done later.
81
82 (define_expand "zero_extendqidi2"
83 [(set (match_operand:DI 0 "gpc_reg_operand" "")
84 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
85 "TARGET_POWERPC64"
86 "")
87
88 (define_insn ""
89 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
90 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
91 "TARGET_POWERPC64"
92 "@
93 lbz%U1%X1 %0,%1
94 rldicl %0,%1,0,56"
95 [(set_attr "type" "load,*")])
96
97 (define_insn ""
98 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
99 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
100 (const_int 0)))
101 (clobber (match_scratch:DI 2 "=r,r"))]
102 "TARGET_POWERPC64"
103 "@
104 rldicl. %2,%1,0,56
105 #"
106 [(set_attr "type" "compare")
107 (set_attr "length" "4,8")])
108
109 (define_split
110 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
111 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
112 (const_int 0)))
113 (clobber (match_scratch:DI 2 ""))]
114 "TARGET_POWERPC64 && reload_completed"
115 [(set (match_dup 2)
116 (zero_extend:DI (match_dup 1)))
117 (set (match_dup 0)
118 (compare:CC (match_dup 2)
119 (const_int 0)))]
120 "")
121
122 (define_insn ""
123 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
124 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
125 (const_int 0)))
126 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
127 (zero_extend:DI (match_dup 1)))]
128 "TARGET_POWERPC64"
129 "@
130 rldicl. %0,%1,0,56
131 #"
132 [(set_attr "type" "compare")
133 (set_attr "length" "4,8")])
134
135 (define_split
136 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
137 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
138 (const_int 0)))
139 (set (match_operand:DI 0 "gpc_reg_operand" "")
140 (zero_extend:DI (match_dup 1)))]
141 "TARGET_POWERPC64 && reload_completed"
142 [(set (match_dup 0)
143 (zero_extend:DI (match_dup 1)))
144 (set (match_dup 2)
145 (compare:CC (match_dup 0)
146 (const_int 0)))]
147 "")
148
149 (define_insn "extendqidi2"
150 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
151 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
152 "TARGET_POWERPC64"
153 "extsb %0,%1")
154
155 (define_insn ""
156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
157 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
158 (const_int 0)))
159 (clobber (match_scratch:DI 2 "=r,r"))]
160 "TARGET_POWERPC64"
161 "@
162 extsb. %2,%1
163 #"
164 [(set_attr "type" "compare")
165 (set_attr "length" "4,8")])
166
167 (define_split
168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
169 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
170 (const_int 0)))
171 (clobber (match_scratch:DI 2 ""))]
172 "TARGET_POWERPC64 && reload_completed"
173 [(set (match_dup 2)
174 (sign_extend:DI (match_dup 1)))
175 (set (match_dup 0)
176 (compare:CC (match_dup 2)
177 (const_int 0)))]
178 "")
179
180 (define_insn ""
181 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
182 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
183 (const_int 0)))
184 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
185 (sign_extend:DI (match_dup 1)))]
186 "TARGET_POWERPC64"
187 "@
188 extsb. %0,%1
189 #"
190 [(set_attr "type" "compare")
191 (set_attr "length" "4,8")])
192
193 (define_split
194 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
195 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
196 (const_int 0)))
197 (set (match_operand:DI 0 "gpc_reg_operand" "")
198 (sign_extend:DI (match_dup 1)))]
199 "TARGET_POWERPC64 && reload_completed"
200 [(set (match_dup 0)
201 (sign_extend:DI (match_dup 1)))
202 (set (match_dup 2)
203 (compare:CC (match_dup 0)
204 (const_int 0)))]
205 "")
206
207 (define_expand "zero_extendhidi2"
208 [(set (match_operand:DI 0 "gpc_reg_operand" "")
209 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
210 "TARGET_POWERPC64"
211 "")
212
213 (define_insn ""
214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
215 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
216 "TARGET_POWERPC64"
217 "@
218 lhz%U1%X1 %0,%1
219 rldicl %0,%1,0,48"
220 [(set_attr "type" "load,*")])
221
222 (define_insn ""
223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
224 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
225 (const_int 0)))
226 (clobber (match_scratch:DI 2 "=r,r"))]
227 "TARGET_POWERPC64"
228 "@
229 rldicl. %2,%1,0,48
230 #"
231 [(set_attr "type" "compare")
232 (set_attr "length" "4,8")])
233
234 (define_split
235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
236 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
237 (const_int 0)))
238 (clobber (match_scratch:DI 2 ""))]
239 "TARGET_POWERPC64 && reload_completed"
240 [(set (match_dup 2)
241 (zero_extend:DI (match_dup 1)))
242 (set (match_dup 0)
243 (compare:CC (match_dup 2)
244 (const_int 0)))]
245 "")
246
247 (define_insn ""
248 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
249 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
250 (const_int 0)))
251 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
252 (zero_extend:DI (match_dup 1)))]
253 "TARGET_POWERPC64"
254 "@
255 rldicl. %0,%1,0,48
256 #"
257 [(set_attr "type" "compare")
258 (set_attr "length" "4,8")])
259
260 (define_split
261 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
262 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
263 (const_int 0)))
264 (set (match_operand:DI 0 "gpc_reg_operand" "")
265 (zero_extend:DI (match_dup 1)))]
266 "TARGET_POWERPC64 && reload_completed"
267 [(set (match_dup 0)
268 (zero_extend:DI (match_dup 1)))
269 (set (match_dup 2)
270 (compare:CC (match_dup 0)
271 (const_int 0)))]
272 "")
273
274 (define_expand "extendhidi2"
275 [(set (match_operand:DI 0 "gpc_reg_operand" "")
276 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
277 "TARGET_POWERPC64"
278 "")
279
280 (define_insn ""
281 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
282 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
283 "TARGET_POWERPC64"
284 "@
285 lha%U1%X1 %0,%1
286 extsh %0,%1"
287 [(set_attr "type" "load_ext,*")])
288
289 (define_insn ""
290 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
291 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
292 (const_int 0)))
293 (clobber (match_scratch:DI 2 "=r,r"))]
294 "TARGET_POWERPC64"
295 "@
296 extsh. %2,%1
297 #"
298 [(set_attr "type" "compare")
299 (set_attr "length" "4,8")])
300
301 (define_split
302 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
303 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
304 (const_int 0)))
305 (clobber (match_scratch:DI 2 ""))]
306 "TARGET_POWERPC64 && reload_completed"
307 [(set (match_dup 2)
308 (sign_extend:DI (match_dup 1)))
309 (set (match_dup 0)
310 (compare:CC (match_dup 2)
311 (const_int 0)))]
312 "")
313
314 (define_insn ""
315 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
316 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
317 (const_int 0)))
318 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
319 (sign_extend:DI (match_dup 1)))]
320 "TARGET_POWERPC64"
321 "@
322 extsh. %0,%1
323 #"
324 [(set_attr "type" "compare")
325 (set_attr "length" "4,8")])
326
327 (define_split
328 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
329 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
330 (const_int 0)))
331 (set (match_operand:DI 0 "gpc_reg_operand" "")
332 (sign_extend:DI (match_dup 1)))]
333 "TARGET_POWERPC64 && reload_completed"
334 [(set (match_dup 0)
335 (sign_extend:DI (match_dup 1)))
336 (set (match_dup 2)
337 (compare:CC (match_dup 0)
338 (const_int 0)))]
339 "")
340
341 (define_expand "zero_extendsidi2"
342 [(set (match_operand:DI 0 "gpc_reg_operand" "")
343 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
344 "TARGET_POWERPC64"
345 "")
346
347 (define_insn ""
348 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
349 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
350 "TARGET_POWERPC64"
351 "@
352 lwz%U1%X1 %0,%1
353 rldicl %0,%1,0,32"
354 [(set_attr "type" "load,*")])
355
356 (define_insn ""
357 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
358 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
359 (const_int 0)))
360 (clobber (match_scratch:DI 2 "=r,r"))]
361 "TARGET_POWERPC64"
362 "@
363 rldicl. %2,%1,0,32
364 #"
365 [(set_attr "type" "compare")
366 (set_attr "length" "4,8")])
367
368 (define_split
369 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
370 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
371 (const_int 0)))
372 (clobber (match_scratch:DI 2 ""))]
373 "TARGET_POWERPC64 && reload_completed"
374 [(set (match_dup 2)
375 (zero_extend:DI (match_dup 1)))
376 (set (match_dup 0)
377 (compare:CC (match_dup 2)
378 (const_int 0)))]
379 "")
380
381 (define_insn ""
382 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
383 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
384 (const_int 0)))
385 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
386 (zero_extend:DI (match_dup 1)))]
387 "TARGET_POWERPC64"
388 "@
389 rldicl. %0,%1,0,32
390 #"
391 [(set_attr "type" "compare")
392 (set_attr "length" "4,8")])
393
394 (define_split
395 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
396 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
397 (const_int 0)))
398 (set (match_operand:DI 0 "gpc_reg_operand" "")
399 (zero_extend:DI (match_dup 1)))]
400 "TARGET_POWERPC64 && reload_completed"
401 [(set (match_dup 0)
402 (zero_extend:DI (match_dup 1)))
403 (set (match_dup 2)
404 (compare:CC (match_dup 0)
405 (const_int 0)))]
406 "")
407
408 (define_expand "extendsidi2"
409 [(set (match_operand:DI 0 "gpc_reg_operand" "")
410 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
411 "TARGET_POWERPC64"
412 "")
413
414 (define_insn ""
415 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
416 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
417 "TARGET_POWERPC64"
418 "@
419 lwa%U1%X1 %0,%1
420 extsw %0,%1"
421 [(set_attr "type" "load_ext,*")])
422
423 (define_insn ""
424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
425 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
426 (const_int 0)))
427 (clobber (match_scratch:DI 2 "=r,r"))]
428 "TARGET_POWERPC64"
429 "@
430 extsw. %2,%1
431 #"
432 [(set_attr "type" "compare")
433 (set_attr "length" "4,8")])
434
435 (define_split
436 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
437 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
438 (const_int 0)))
439 (clobber (match_scratch:DI 2 ""))]
440 "TARGET_POWERPC64 && reload_completed"
441 [(set (match_dup 2)
442 (sign_extend:DI (match_dup 1)))
443 (set (match_dup 0)
444 (compare:CC (match_dup 2)
445 (const_int 0)))]
446 "")
447
448 (define_insn ""
449 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
450 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
451 (const_int 0)))
452 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
453 (sign_extend:DI (match_dup 1)))]
454 "TARGET_POWERPC64"
455 "@
456 extsw. %0,%1
457 #"
458 [(set_attr "type" "compare")
459 (set_attr "length" "4,8")])
460
461 (define_split
462 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
463 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
464 (const_int 0)))
465 (set (match_operand:DI 0 "gpc_reg_operand" "")
466 (sign_extend:DI (match_dup 1)))]
467 "TARGET_POWERPC64 && reload_completed"
468 [(set (match_dup 0)
469 (sign_extend:DI (match_dup 1)))
470 (set (match_dup 2)
471 (compare:CC (match_dup 0)
472 (const_int 0)))]
473 "")
474
475 (define_expand "zero_extendqisi2"
476 [(set (match_operand:SI 0 "gpc_reg_operand" "")
477 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
478 ""
479 "")
480
481 (define_insn ""
482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
483 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
484 ""
485 "@
486 lbz%U1%X1 %0,%1
487 {rlinm|rlwinm} %0,%1,0,0xff"
488 [(set_attr "type" "load,*")])
489
490 (define_insn ""
491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
492 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
493 (const_int 0)))
494 (clobber (match_scratch:SI 2 "=r,r"))]
495 ""
496 "@
497 {andil.|andi.} %2,%1,0xff
498 #"
499 [(set_attr "type" "compare")
500 (set_attr "length" "4,8")])
501
502 (define_split
503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
504 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
505 (const_int 0)))
506 (clobber (match_scratch:SI 2 ""))]
507 "reload_completed"
508 [(set (match_dup 2)
509 (zero_extend:SI (match_dup 1)))
510 (set (match_dup 0)
511 (compare:CC (match_dup 2)
512 (const_int 0)))]
513 "")
514
515 (define_insn ""
516 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
517 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
518 (const_int 0)))
519 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
520 (zero_extend:SI (match_dup 1)))]
521 ""
522 "@
523 {andil.|andi.} %0,%1,0xff
524 #"
525 [(set_attr "type" "compare")
526 (set_attr "length" "4,8")])
527
528 (define_split
529 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
530 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
531 (const_int 0)))
532 (set (match_operand:SI 0 "gpc_reg_operand" "")
533 (zero_extend:SI (match_dup 1)))]
534 "reload_completed"
535 [(set (match_dup 0)
536 (zero_extend:SI (match_dup 1)))
537 (set (match_dup 2)
538 (compare:CC (match_dup 0)
539 (const_int 0)))]
540 "")
541
542 (define_expand "extendqisi2"
543 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
544 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
545 ""
546 "
547 {
548 if (TARGET_POWERPC)
549 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
550 else if (TARGET_POWER)
551 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
552 else
553 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
554 DONE;
555 }")
556
557 (define_insn "extendqisi2_ppc"
558 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
559 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
560 "TARGET_POWERPC"
561 "extsb %0,%1")
562
563 (define_insn ""
564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
565 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
566 (const_int 0)))
567 (clobber (match_scratch:SI 2 "=r,r"))]
568 "TARGET_POWERPC"
569 "@
570 extsb. %2,%1
571 #"
572 [(set_attr "type" "compare")
573 (set_attr "length" "4,8")])
574
575 (define_split
576 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
577 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
578 (const_int 0)))
579 (clobber (match_scratch:SI 2 ""))]
580 "TARGET_POWERPC && reload_completed"
581 [(set (match_dup 2)
582 (sign_extend:SI (match_dup 1)))
583 (set (match_dup 0)
584 (compare:CC (match_dup 2)
585 (const_int 0)))]
586 "")
587
588 (define_insn ""
589 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
590 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
591 (const_int 0)))
592 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
593 (sign_extend:SI (match_dup 1)))]
594 "TARGET_POWERPC"
595 "@
596 extsb. %0,%1
597 #"
598 [(set_attr "type" "compare")
599 (set_attr "length" "4,8")])
600
601 (define_split
602 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
603 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
604 (const_int 0)))
605 (set (match_operand:SI 0 "gpc_reg_operand" "")
606 (sign_extend:SI (match_dup 1)))]
607 "TARGET_POWERPC && reload_completed"
608 [(set (match_dup 0)
609 (sign_extend:SI (match_dup 1)))
610 (set (match_dup 2)
611 (compare:CC (match_dup 0)
612 (const_int 0)))]
613 "")
614
615 (define_expand "extendqisi2_power"
616 [(parallel [(set (match_dup 2)
617 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
618 (const_int 24)))
619 (clobber (scratch:SI))])
620 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
621 (ashiftrt:SI (match_dup 2)
622 (const_int 24)))
623 (clobber (scratch:SI))])]
624 "TARGET_POWER"
625 "
626 { operands[1] = gen_lowpart (SImode, operands[1]);
627 operands[2] = gen_reg_rtx (SImode); }")
628
629 (define_expand "extendqisi2_no_power"
630 [(set (match_dup 2)
631 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
632 (const_int 24)))
633 (set (match_operand:SI 0 "gpc_reg_operand" "")
634 (ashiftrt:SI (match_dup 2)
635 (const_int 24)))]
636 "! TARGET_POWER && ! TARGET_POWERPC"
637 "
638 { operands[1] = gen_lowpart (SImode, operands[1]);
639 operands[2] = gen_reg_rtx (SImode); }")
640
641 (define_expand "zero_extendqihi2"
642 [(set (match_operand:HI 0 "gpc_reg_operand" "")
643 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
644 ""
645 "")
646
647 (define_insn ""
648 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
649 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
650 ""
651 "@
652 lbz%U1%X1 %0,%1
653 {rlinm|rlwinm} %0,%1,0,0xff"
654 [(set_attr "type" "load,*")])
655
656 (define_insn ""
657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
658 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
659 (const_int 0)))
660 (clobber (match_scratch:HI 2 "=r,r"))]
661 ""
662 "@
663 {andil.|andi.} %2,%1,0xff
664 #"
665 [(set_attr "type" "compare")
666 (set_attr "length" "4,8")])
667
668 (define_split
669 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
670 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
671 (const_int 0)))
672 (clobber (match_scratch:HI 2 ""))]
673 "reload_completed"
674 [(set (match_dup 2)
675 (zero_extend:HI (match_dup 1)))
676 (set (match_dup 0)
677 (compare:CC (match_dup 2)
678 (const_int 0)))]
679 "")
680
681 (define_insn ""
682 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
683 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
684 (const_int 0)))
685 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
686 (zero_extend:HI (match_dup 1)))]
687 ""
688 "@
689 {andil.|andi.} %0,%1,0xff
690 #"
691 [(set_attr "type" "compare")
692 (set_attr "length" "4,8")])
693
694 (define_split
695 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
696 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
697 (const_int 0)))
698 (set (match_operand:HI 0 "gpc_reg_operand" "")
699 (zero_extend:HI (match_dup 1)))]
700 "reload_completed"
701 [(set (match_dup 0)
702 (zero_extend:HI (match_dup 1)))
703 (set (match_dup 2)
704 (compare:CC (match_dup 0)
705 (const_int 0)))]
706 "")
707
708 (define_expand "extendqihi2"
709 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
710 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
711 ""
712 "
713 {
714 if (TARGET_POWERPC)
715 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
716 else if (TARGET_POWER)
717 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
718 else
719 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
720 DONE;
721 }")
722
723 (define_insn "extendqihi2_ppc"
724 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
725 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
726 "TARGET_POWERPC"
727 "extsb %0,%1")
728
729 (define_insn ""
730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
731 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
732 (const_int 0)))
733 (clobber (match_scratch:HI 2 "=r,r"))]
734 "TARGET_POWERPC"
735 "@
736 extsb. %2,%1
737 #"
738 [(set_attr "type" "compare")
739 (set_attr "length" "4,8")])
740
741 (define_split
742 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
743 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
744 (const_int 0)))
745 (clobber (match_scratch:HI 2 ""))]
746 "TARGET_POWERPC && reload_completed"
747 [(set (match_dup 2)
748 (sign_extend:HI (match_dup 1)))
749 (set (match_dup 0)
750 (compare:CC (match_dup 2)
751 (const_int 0)))]
752 "")
753
754 (define_insn ""
755 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
756 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
757 (const_int 0)))
758 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
759 (sign_extend:HI (match_dup 1)))]
760 "TARGET_POWERPC"
761 "@
762 extsb. %0,%1
763 #"
764 [(set_attr "type" "compare")
765 (set_attr "length" "4,8")])
766
767 (define_split
768 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
769 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
770 (const_int 0)))
771 (set (match_operand:HI 0 "gpc_reg_operand" "")
772 (sign_extend:HI (match_dup 1)))]
773 "TARGET_POWERPC && reload_completed"
774 [(set (match_dup 0)
775 (sign_extend:HI (match_dup 1)))
776 (set (match_dup 2)
777 (compare:CC (match_dup 0)
778 (const_int 0)))]
779 "")
780
781 (define_expand "extendqihi2_power"
782 [(parallel [(set (match_dup 2)
783 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
784 (const_int 24)))
785 (clobber (scratch:SI))])
786 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
787 (ashiftrt:SI (match_dup 2)
788 (const_int 24)))
789 (clobber (scratch:SI))])]
790 "TARGET_POWER"
791 "
792 { operands[0] = gen_lowpart (SImode, operands[0]);
793 operands[1] = gen_lowpart (SImode, operands[1]);
794 operands[2] = gen_reg_rtx (SImode); }")
795
796 (define_expand "extendqihi2_no_power"
797 [(set (match_dup 2)
798 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
799 (const_int 24)))
800 (set (match_operand:HI 0 "gpc_reg_operand" "")
801 (ashiftrt:SI (match_dup 2)
802 (const_int 24)))]
803 "! TARGET_POWER && ! TARGET_POWERPC"
804 "
805 { operands[0] = gen_lowpart (SImode, operands[0]);
806 operands[1] = gen_lowpart (SImode, operands[1]);
807 operands[2] = gen_reg_rtx (SImode); }")
808
809 (define_expand "zero_extendhisi2"
810 [(set (match_operand:SI 0 "gpc_reg_operand" "")
811 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
812 ""
813 "")
814
815 (define_insn ""
816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
817 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
818 ""
819 "@
820 lhz%U1%X1 %0,%1
821 {rlinm|rlwinm} %0,%1,0,0xffff"
822 [(set_attr "type" "load,*")])
823
824 (define_insn ""
825 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
826 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
827 (const_int 0)))
828 (clobber (match_scratch:SI 2 "=r,r"))]
829 ""
830 "@
831 {andil.|andi.} %2,%1,0xffff
832 #"
833 [(set_attr "type" "compare")
834 (set_attr "length" "4,8")])
835
836 (define_split
837 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
838 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
839 (const_int 0)))
840 (clobber (match_scratch:SI 2 ""))]
841 "reload_completed"
842 [(set (match_dup 2)
843 (zero_extend:SI (match_dup 1)))
844 (set (match_dup 0)
845 (compare:CC (match_dup 2)
846 (const_int 0)))]
847 "")
848
849 (define_insn ""
850 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
851 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
852 (const_int 0)))
853 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
854 (zero_extend:SI (match_dup 1)))]
855 ""
856 "@
857 {andil.|andi.} %0,%1,0xffff
858 #"
859 [(set_attr "type" "compare")
860 (set_attr "length" "4,8")])
861
862 (define_split
863 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (set (match_operand:SI 0 "gpc_reg_operand" "")
867 (zero_extend:SI (match_dup 1)))]
868 "reload_completed"
869 [(set (match_dup 0)
870 (zero_extend:SI (match_dup 1)))
871 (set (match_dup 2)
872 (compare:CC (match_dup 0)
873 (const_int 0)))]
874 "")
875
876 (define_expand "extendhisi2"
877 [(set (match_operand:SI 0 "gpc_reg_operand" "")
878 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
879 ""
880 "")
881
882 (define_insn ""
883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
884 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
885 ""
886 "@
887 lha%U1%X1 %0,%1
888 {exts|extsh} %0,%1"
889 [(set_attr "type" "load_ext,*")])
890
891 (define_insn ""
892 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
893 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
894 (const_int 0)))
895 (clobber (match_scratch:SI 2 "=r,r"))]
896 ""
897 "@
898 {exts.|extsh.} %2,%1
899 #"
900 [(set_attr "type" "compare")
901 (set_attr "length" "4,8")])
902
903 (define_split
904 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
905 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
906 (const_int 0)))
907 (clobber (match_scratch:SI 2 ""))]
908 "reload_completed"
909 [(set (match_dup 2)
910 (sign_extend:SI (match_dup 1)))
911 (set (match_dup 0)
912 (compare:CC (match_dup 2)
913 (const_int 0)))]
914 "")
915
916 (define_insn ""
917 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
918 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
919 (const_int 0)))
920 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
921 (sign_extend:SI (match_dup 1)))]
922 ""
923 "@
924 {exts.|extsh.} %0,%1
925 #"
926 [(set_attr "type" "compare")
927 (set_attr "length" "4,8")])
928 \f
929 (define_split
930 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
931 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
932 (const_int 0)))
933 (set (match_operand:SI 0 "gpc_reg_operand" "")
934 (sign_extend:SI (match_dup 1)))]
935 "reload_completed"
936 [(set (match_dup 0)
937 (sign_extend:SI (match_dup 1)))
938 (set (match_dup 2)
939 (compare:CC (match_dup 0)
940 (const_int 0)))]
941 "")
942
943 ;; Fixed-point arithmetic insns.
944
945 ;; Discourage ai/addic because of carry but provide it in an alternative
946 ;; allowing register zero as source.
947 (define_expand "addsi3"
948 [(set (match_operand:SI 0 "gpc_reg_operand" "")
949 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
950 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
951 ""
952 "
953 {
954 if (GET_CODE (operands[2]) == CONST_INT
955 && ! add_operand (operands[2], SImode))
956 {
957 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
958 ? operands[0] : gen_reg_rtx (SImode));
959
960 HOST_WIDE_INT val = INTVAL (operands[2]);
961 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
962 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
963
964 /* The ordering here is important for the prolog expander.
965 When space is allocated from the stack, adding 'low' first may
966 produce a temporary deallocation (which would be bad). */
967 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
968 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
969 DONE;
970 }
971 }")
972
973 (define_insn "*addsi3_internal1"
974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
975 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
976 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
977 ""
978 "@
979 {cax|add} %0,%1,%2
980 {cal %0,%2(%1)|addi %0,%1,%2}
981 {ai|addic} %0,%1,%2
982 {cau|addis} %0,%1,%v2"
983 [(set_attr "length" "4,4,4,4")])
984
985 (define_insn "addsi3_high"
986 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
987 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
988 (high:SI (match_operand 2 "" ""))))]
989 "TARGET_MACHO && !TARGET_64BIT"
990 "{cau|addis} %0,%1,ha16(%2)"
991 [(set_attr "length" "4")])
992
993 (define_insn "*addsi3_internal2"
994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
995 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
996 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
997 (const_int 0)))
998 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
999 "! TARGET_POWERPC64"
1000 "@
1001 {cax.|add.} %3,%1,%2
1002 {ai.|addic.} %3,%1,%2
1003 #
1004 #"
1005 [(set_attr "type" "fast_compare,compare,compare,compare")
1006 (set_attr "length" "4,4,8,8")])
1007
1008 (define_split
1009 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1010 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1011 (match_operand:SI 2 "reg_or_short_operand" ""))
1012 (const_int 0)))
1013 (clobber (match_scratch:SI 3 ""))]
1014 "! TARGET_POWERPC64 && reload_completed"
1015 [(set (match_dup 3)
1016 (plus:SI (match_dup 1)
1017 (match_dup 2)))
1018 (set (match_dup 0)
1019 (compare:CC (match_dup 3)
1020 (const_int 0)))]
1021 "")
1022
1023 (define_insn "*addsi3_internal3"
1024 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1025 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1026 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1027 (const_int 0)))
1028 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1029 (plus:SI (match_dup 1)
1030 (match_dup 2)))]
1031 "! TARGET_POWERPC64"
1032 "@
1033 {cax.|add.} %0,%1,%2
1034 {ai.|addic.} %0,%1,%2
1035 #
1036 #"
1037 [(set_attr "type" "fast_compare,compare,compare,compare")
1038 (set_attr "length" "4,4,8,8")])
1039
1040 (define_split
1041 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1042 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1043 (match_operand:SI 2 "reg_or_short_operand" ""))
1044 (const_int 0)))
1045 (set (match_operand:SI 0 "gpc_reg_operand" "")
1046 (plus:SI (match_dup 1) (match_dup 2)))]
1047 "! TARGET_POWERPC64 && reload_completed"
1048 [(set (match_dup 0)
1049 (plus:SI (match_dup 1)
1050 (match_dup 2)))
1051 (set (match_dup 3)
1052 (compare:CC (match_dup 0)
1053 (const_int 0)))]
1054 "")
1055
1056 ;; Split an add that we can't do in one insn into two insns, each of which
1057 ;; does one 16-bit part. This is used by combine. Note that the low-order
1058 ;; add should be last in case the result gets used in an address.
1059
1060 (define_split
1061 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1062 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1063 (match_operand:SI 2 "non_add_cint_operand" "")))]
1064 ""
1065 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1066 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1067 "
1068 {
1069 HOST_WIDE_INT val = INTVAL (operands[2]);
1070 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1071 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1072
1073 operands[3] = GEN_INT (rest);
1074 operands[4] = GEN_INT (low);
1075 }")
1076
1077 (define_insn "one_cmplsi2"
1078 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1079 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1080 ""
1081 "nor %0,%1,%1")
1082
1083 (define_insn ""
1084 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1085 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1086 (const_int 0)))
1087 (clobber (match_scratch:SI 2 "=r,r"))]
1088 "! TARGET_POWERPC64"
1089 "@
1090 nor. %2,%1,%1
1091 #"
1092 [(set_attr "type" "compare")
1093 (set_attr "length" "4,8")])
1094
1095 (define_split
1096 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1097 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1098 (const_int 0)))
1099 (clobber (match_scratch:SI 2 ""))]
1100 "! TARGET_POWERPC64 && reload_completed"
1101 [(set (match_dup 2)
1102 (not:SI (match_dup 1)))
1103 (set (match_dup 0)
1104 (compare:CC (match_dup 2)
1105 (const_int 0)))]
1106 "")
1107
1108 (define_insn ""
1109 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1110 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1111 (const_int 0)))
1112 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1113 (not:SI (match_dup 1)))]
1114 "! TARGET_POWERPC64"
1115 "@
1116 nor. %0,%1,%1
1117 #"
1118 [(set_attr "type" "compare")
1119 (set_attr "length" "4,8")])
1120
1121 (define_split
1122 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1123 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1124 (const_int 0)))
1125 (set (match_operand:SI 0 "gpc_reg_operand" "")
1126 (not:SI (match_dup 1)))]
1127 "! TARGET_POWERPC64 && reload_completed"
1128 [(set (match_dup 0)
1129 (not:SI (match_dup 1)))
1130 (set (match_dup 2)
1131 (compare:CC (match_dup 0)
1132 (const_int 0)))]
1133 "")
1134
1135 (define_insn ""
1136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1137 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1138 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1139 "! TARGET_POWERPC"
1140 "{sf%I1|subf%I1c} %0,%2,%1")
1141
1142 (define_insn ""
1143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1144 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1145 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1146 "TARGET_POWERPC"
1147 "@
1148 subf %0,%2,%1
1149 subfic %0,%2,%1")
1150
1151 (define_insn ""
1152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1153 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1154 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1155 (const_int 0)))
1156 (clobber (match_scratch:SI 3 "=r,r"))]
1157 "! TARGET_POWERPC"
1158 "@
1159 {sf.|subfc.} %3,%2,%1
1160 #"
1161 [(set_attr "type" "compare")
1162 (set_attr "length" "4,8")])
1163
1164 (define_insn ""
1165 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1166 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1167 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1168 (const_int 0)))
1169 (clobber (match_scratch:SI 3 "=r,r"))]
1170 "TARGET_POWERPC && ! TARGET_POWERPC64"
1171 "@
1172 subf. %3,%2,%1
1173 #"
1174 [(set_attr "type" "fast_compare")
1175 (set_attr "length" "4,8")])
1176
1177 (define_split
1178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1179 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1180 (match_operand:SI 2 "gpc_reg_operand" ""))
1181 (const_int 0)))
1182 (clobber (match_scratch:SI 3 ""))]
1183 "! TARGET_POWERPC64 && reload_completed"
1184 [(set (match_dup 3)
1185 (minus:SI (match_dup 1)
1186 (match_dup 2)))
1187 (set (match_dup 0)
1188 (compare:CC (match_dup 3)
1189 (const_int 0)))]
1190 "")
1191
1192 (define_insn ""
1193 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1194 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1195 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1196 (const_int 0)))
1197 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1198 (minus:SI (match_dup 1) (match_dup 2)))]
1199 "! TARGET_POWERPC"
1200 "@
1201 {sf.|subfc.} %0,%2,%1
1202 #"
1203 [(set_attr "type" "compare")
1204 (set_attr "length" "4,8")])
1205
1206 (define_insn ""
1207 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1208 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1209 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1210 (const_int 0)))
1211 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1212 (minus:SI (match_dup 1)
1213 (match_dup 2)))]
1214 "TARGET_POWERPC && ! TARGET_POWERPC64"
1215 "@
1216 subf. %0,%2,%1
1217 #"
1218 [(set_attr "type" "fast_compare")
1219 (set_attr "length" "4,8")])
1220
1221 (define_split
1222 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1223 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1224 (match_operand:SI 2 "gpc_reg_operand" ""))
1225 (const_int 0)))
1226 (set (match_operand:SI 0 "gpc_reg_operand" "")
1227 (minus:SI (match_dup 1)
1228 (match_dup 2)))]
1229 "! TARGET_POWERPC64 && reload_completed"
1230 [(set (match_dup 0)
1231 (minus:SI (match_dup 1)
1232 (match_dup 2)))
1233 (set (match_dup 3)
1234 (compare:CC (match_dup 0)
1235 (const_int 0)))]
1236 "")
1237
1238 (define_expand "subsi3"
1239 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1240 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1241 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1242 ""
1243 "
1244 {
1245 if (GET_CODE (operands[2]) == CONST_INT)
1246 {
1247 emit_insn (gen_addsi3 (operands[0], operands[1],
1248 negate_rtx (SImode, operands[2])));
1249 DONE;
1250 }
1251 }")
1252
1253 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1254 ;; instruction and some auxiliary computations. Then we just have a single
1255 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1256 ;; combine.
1257
1258 (define_expand "sminsi3"
1259 [(set (match_dup 3)
1260 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1261 (match_operand:SI 2 "reg_or_short_operand" ""))
1262 (const_int 0)
1263 (minus:SI (match_dup 2) (match_dup 1))))
1264 (set (match_operand:SI 0 "gpc_reg_operand" "")
1265 (minus:SI (match_dup 2) (match_dup 3)))]
1266 "TARGET_POWER || TARGET_ISEL"
1267 "
1268 {
1269 if (TARGET_ISEL)
1270 {
1271 operands[2] = force_reg (SImode, operands[2]);
1272 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1273 DONE;
1274 }
1275
1276 operands[3] = gen_reg_rtx (SImode);
1277 }")
1278
1279 (define_split
1280 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1281 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1282 (match_operand:SI 2 "reg_or_short_operand" "")))
1283 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1284 "TARGET_POWER"
1285 [(set (match_dup 3)
1286 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1287 (const_int 0)
1288 (minus:SI (match_dup 2) (match_dup 1))))
1289 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1290 "")
1291
1292 (define_expand "smaxsi3"
1293 [(set (match_dup 3)
1294 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1295 (match_operand:SI 2 "reg_or_short_operand" ""))
1296 (const_int 0)
1297 (minus:SI (match_dup 2) (match_dup 1))))
1298 (set (match_operand:SI 0 "gpc_reg_operand" "")
1299 (plus:SI (match_dup 3) (match_dup 1)))]
1300 "TARGET_POWER || TARGET_ISEL"
1301 "
1302 {
1303 if (TARGET_ISEL)
1304 {
1305 operands[2] = force_reg (SImode, operands[2]);
1306 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1307 DONE;
1308 }
1309 operands[3] = gen_reg_rtx (SImode);
1310 }")
1311
1312 (define_split
1313 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1314 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1315 (match_operand:SI 2 "reg_or_short_operand" "")))
1316 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1317 "TARGET_POWER"
1318 [(set (match_dup 3)
1319 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1320 (const_int 0)
1321 (minus:SI (match_dup 2) (match_dup 1))))
1322 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1323 "")
1324
1325 (define_expand "uminsi3"
1326 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1327 (match_dup 5)))
1328 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1329 (match_dup 5)))
1330 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1331 (const_int 0)
1332 (minus:SI (match_dup 4) (match_dup 3))))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "")
1334 (minus:SI (match_dup 2) (match_dup 3)))]
1335 "TARGET_POWER || TARGET_ISEL"
1336 "
1337 {
1338 if (TARGET_ISEL)
1339 {
1340 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1341 DONE;
1342 }
1343 operands[3] = gen_reg_rtx (SImode);
1344 operands[4] = gen_reg_rtx (SImode);
1345 operands[5] = GEN_INT (-2147483647 - 1);
1346 }")
1347
1348 (define_expand "umaxsi3"
1349 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1350 (match_dup 5)))
1351 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1352 (match_dup 5)))
1353 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1354 (const_int 0)
1355 (minus:SI (match_dup 4) (match_dup 3))))
1356 (set (match_operand:SI 0 "gpc_reg_operand" "")
1357 (plus:SI (match_dup 3) (match_dup 1)))]
1358 "TARGET_POWER || TARGET_ISEL"
1359 "
1360 {
1361 if (TARGET_ISEL)
1362 {
1363 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1364 DONE;
1365 }
1366 operands[3] = gen_reg_rtx (SImode);
1367 operands[4] = gen_reg_rtx (SImode);
1368 operands[5] = GEN_INT (-2147483647 - 1);
1369 }")
1370
1371 (define_insn ""
1372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1373 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1374 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1375 (const_int 0)
1376 (minus:SI (match_dup 2) (match_dup 1))))]
1377 "TARGET_POWER"
1378 "doz%I2 %0,%1,%2")
1379
1380 (define_insn ""
1381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1382 (compare:CC
1383 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1384 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1385 (const_int 0)
1386 (minus:SI (match_dup 2) (match_dup 1)))
1387 (const_int 0)))
1388 (clobber (match_scratch:SI 3 "=r,r"))]
1389 "TARGET_POWER"
1390 "@
1391 doz%I2. %3,%1,%2
1392 #"
1393 [(set_attr "type" "delayed_compare")
1394 (set_attr "length" "4,8")])
1395
1396 (define_split
1397 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1398 (compare:CC
1399 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1400 (match_operand:SI 2 "reg_or_short_operand" ""))
1401 (const_int 0)
1402 (minus:SI (match_dup 2) (match_dup 1)))
1403 (const_int 0)))
1404 (clobber (match_scratch:SI 3 ""))]
1405 "TARGET_POWER && reload_completed"
1406 [(set (match_dup 3)
1407 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1408 (const_int 0)
1409 (minus:SI (match_dup 2) (match_dup 1))))
1410 (set (match_dup 0)
1411 (compare:CC (match_dup 3)
1412 (const_int 0)))]
1413 "")
1414
1415 (define_insn ""
1416 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1417 (compare:CC
1418 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1419 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1420 (const_int 0)
1421 (minus:SI (match_dup 2) (match_dup 1)))
1422 (const_int 0)))
1423 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1424 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1425 (const_int 0)
1426 (minus:SI (match_dup 2) (match_dup 1))))]
1427 "TARGET_POWER"
1428 "@
1429 doz%I2. %0,%1,%2
1430 #"
1431 [(set_attr "type" "delayed_compare")
1432 (set_attr "length" "4,8")])
1433
1434 (define_split
1435 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1436 (compare:CC
1437 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1438 (match_operand:SI 2 "reg_or_short_operand" ""))
1439 (const_int 0)
1440 (minus:SI (match_dup 2) (match_dup 1)))
1441 (const_int 0)))
1442 (set (match_operand:SI 0 "gpc_reg_operand" "")
1443 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1444 (const_int 0)
1445 (minus:SI (match_dup 2) (match_dup 1))))]
1446 "TARGET_POWER && reload_completed"
1447 [(set (match_dup 0)
1448 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1449 (const_int 0)
1450 (minus:SI (match_dup 2) (match_dup 1))))
1451 (set (match_dup 3)
1452 (compare:CC (match_dup 0)
1453 (const_int 0)))]
1454 "")
1455
1456 ;; We don't need abs with condition code because such comparisons should
1457 ;; never be done.
1458 (define_expand "abssi2"
1459 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1460 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1461 ""
1462 "
1463 {
1464 if (TARGET_ISEL)
1465 {
1466 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1467 DONE;
1468 }
1469 else if (! TARGET_POWER)
1470 {
1471 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1472 DONE;
1473 }
1474 }")
1475
1476 (define_insn "*abssi2_power"
1477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1478 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1479 "TARGET_POWER"
1480 "abs %0,%1")
1481
1482 (define_insn_and_split "abssi2_isel"
1483 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1484 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1485 (clobber (match_scratch:SI 2 "=b"))
1486 (clobber (match_scratch:CC 3 "=y"))]
1487 "TARGET_ISEL"
1488 "#"
1489 "&& reload_completed"
1490 [(set (match_dup 2) (neg:SI (match_dup 1)))
1491 (set (match_dup 3)
1492 (compare:CC (match_dup 1)
1493 (const_int 0)))
1494 (set (match_dup 0)
1495 (if_then_else:SI (ge (match_dup 3)
1496 (const_int 0))
1497 (match_dup 1)
1498 (match_dup 2)))]
1499 "")
1500
1501 (define_insn_and_split "abssi2_nopower"
1502 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1503 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1504 (clobber (match_scratch:SI 2 "=&r,&r"))]
1505 "! TARGET_POWER && ! TARGET_ISEL"
1506 "#"
1507 "&& reload_completed"
1508 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1509 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1510 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1511 "")
1512
1513 (define_insn "*nabs_power"
1514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1515 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1516 "TARGET_POWER"
1517 "nabs %0,%1")
1518
1519 (define_insn_and_split "*nabs_nopower"
1520 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1521 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1522 (clobber (match_scratch:SI 2 "=&r,&r"))]
1523 "! TARGET_POWER"
1524 "#"
1525 "&& reload_completed"
1526 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1527 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1528 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1529 "")
1530
1531 (define_insn "negsi2"
1532 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1533 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1534 ""
1535 "neg %0,%1")
1536
1537 (define_insn ""
1538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1539 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1540 (const_int 0)))
1541 (clobber (match_scratch:SI 2 "=r,r"))]
1542 "! TARGET_POWERPC64"
1543 "@
1544 neg. %2,%1
1545 #"
1546 [(set_attr "type" "fast_compare")
1547 (set_attr "length" "4,8")])
1548
1549 (define_split
1550 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1551 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1552 (const_int 0)))
1553 (clobber (match_scratch:SI 2 ""))]
1554 "! TARGET_POWERPC64 && reload_completed"
1555 [(set (match_dup 2)
1556 (neg:SI (match_dup 1)))
1557 (set (match_dup 0)
1558 (compare:CC (match_dup 2)
1559 (const_int 0)))]
1560 "")
1561
1562 (define_insn ""
1563 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1564 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1565 (const_int 0)))
1566 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1567 (neg:SI (match_dup 1)))]
1568 "! TARGET_POWERPC64"
1569 "@
1570 neg. %0,%1
1571 #"
1572 [(set_attr "type" "fast_compare")
1573 (set_attr "length" "4,8")])
1574
1575 (define_split
1576 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1577 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1578 (const_int 0)))
1579 (set (match_operand:SI 0 "gpc_reg_operand" "")
1580 (neg:SI (match_dup 1)))]
1581 "! TARGET_POWERPC64 && reload_completed"
1582 [(set (match_dup 0)
1583 (neg:SI (match_dup 1)))
1584 (set (match_dup 2)
1585 (compare:CC (match_dup 0)
1586 (const_int 0)))]
1587 "")
1588
1589 (define_insn "clzsi2"
1590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1591 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1592 ""
1593 "{cntlz|cntlzw} %0,%1")
1594
1595 (define_expand "ctzsi2"
1596 [(set (match_dup 2)
1597 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1598 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1599 (match_dup 2)))
1600 (clobber (scratch:CC))])
1601 (set (match_dup 4) (clz:SI (match_dup 3)))
1602 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1603 (minus:SI (const_int 31) (match_dup 4)))]
1604 ""
1605 {
1606 operands[2] = gen_reg_rtx (SImode);
1607 operands[3] = gen_reg_rtx (SImode);
1608 operands[4] = gen_reg_rtx (SImode);
1609 })
1610
1611 (define_expand "ffssi2"
1612 [(set (match_dup 2)
1613 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1614 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1615 (match_dup 2)))
1616 (clobber (scratch:CC))])
1617 (set (match_dup 4) (clz:SI (match_dup 3)))
1618 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1619 (minus:SI (const_int 32) (match_dup 4)))]
1620 ""
1621 {
1622 operands[2] = gen_reg_rtx (SImode);
1623 operands[3] = gen_reg_rtx (SImode);
1624 operands[4] = gen_reg_rtx (SImode);
1625 })
1626
1627 (define_expand "mulsi3"
1628 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1629 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1630 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1631 ""
1632 "
1633 {
1634 if (TARGET_POWER)
1635 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1636 else
1637 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1638 DONE;
1639 }")
1640
1641 (define_insn "mulsi3_mq"
1642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1643 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1644 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1645 (clobber (match_scratch:SI 3 "=q,q"))]
1646 "TARGET_POWER"
1647 "@
1648 {muls|mullw} %0,%1,%2
1649 {muli|mulli} %0,%1,%2"
1650 [(set (attr "type")
1651 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1652 (const_string "imul3")
1653 (match_operand:SI 2 "short_cint_operand" "")
1654 (const_string "imul2")]
1655 (const_string "imul")))])
1656
1657 (define_insn "mulsi3_no_mq"
1658 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1659 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1660 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1661 "! TARGET_POWER"
1662 "@
1663 {muls|mullw} %0,%1,%2
1664 {muli|mulli} %0,%1,%2"
1665 [(set (attr "type")
1666 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1667 (const_string "imul3")
1668 (match_operand:SI 2 "short_cint_operand" "")
1669 (const_string "imul2")]
1670 (const_string "imul")))])
1671
1672 (define_insn ""
1673 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1674 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1675 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1676 (const_int 0)))
1677 (clobber (match_scratch:SI 3 "=r,r"))
1678 (clobber (match_scratch:SI 4 "=q,q"))]
1679 "TARGET_POWER"
1680 "@
1681 {muls.|mullw.} %3,%1,%2
1682 #"
1683 [(set_attr "type" "mult_compare")
1684 (set_attr "length" "4,8")])
1685
1686 (define_split
1687 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1688 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1689 (match_operand:SI 2 "gpc_reg_operand" ""))
1690 (const_int 0)))
1691 (clobber (match_scratch:SI 3 ""))
1692 (clobber (match_scratch:SI 4 ""))]
1693 "TARGET_POWER && reload_completed"
1694 [(parallel [(set (match_dup 3)
1695 (mult:SI (match_dup 1) (match_dup 2)))
1696 (clobber (match_dup 4))])
1697 (set (match_dup 0)
1698 (compare:CC (match_dup 3)
1699 (const_int 0)))]
1700 "")
1701
1702 (define_insn ""
1703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1704 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1705 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1706 (const_int 0)))
1707 (clobber (match_scratch:SI 3 "=r,r"))]
1708 "! TARGET_POWER"
1709 "@
1710 {muls.|mullw.} %3,%1,%2
1711 #"
1712 [(set_attr "type" "mult_compare")
1713 (set_attr "length" "4,8")])
1714
1715 (define_split
1716 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1717 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1718 (match_operand:SI 2 "gpc_reg_operand" ""))
1719 (const_int 0)))
1720 (clobber (match_scratch:SI 3 ""))]
1721 "! TARGET_POWER && reload_completed"
1722 [(set (match_dup 3)
1723 (mult:SI (match_dup 1) (match_dup 2)))
1724 (set (match_dup 0)
1725 (compare:CC (match_dup 3)
1726 (const_int 0)))]
1727 "")
1728
1729 (define_insn ""
1730 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1732 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1733 (const_int 0)))
1734 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1735 (mult:SI (match_dup 1) (match_dup 2)))
1736 (clobber (match_scratch:SI 4 "=q,q"))]
1737 "TARGET_POWER"
1738 "@
1739 {muls.|mullw.} %0,%1,%2
1740 #"
1741 [(set_attr "type" "mult_compare")
1742 (set_attr "length" "4,8")])
1743
1744 (define_split
1745 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1746 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1747 (match_operand:SI 2 "gpc_reg_operand" ""))
1748 (const_int 0)))
1749 (set (match_operand:SI 0 "gpc_reg_operand" "")
1750 (mult:SI (match_dup 1) (match_dup 2)))
1751 (clobber (match_scratch:SI 4 ""))]
1752 "TARGET_POWER && reload_completed"
1753 [(parallel [(set (match_dup 0)
1754 (mult:SI (match_dup 1) (match_dup 2)))
1755 (clobber (match_dup 4))])
1756 (set (match_dup 3)
1757 (compare:CC (match_dup 0)
1758 (const_int 0)))]
1759 "")
1760
1761 (define_insn ""
1762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1763 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1764 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1765 (const_int 0)))
1766 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1767 (mult:SI (match_dup 1) (match_dup 2)))]
1768 "! TARGET_POWER"
1769 "@
1770 {muls.|mullw.} %0,%1,%2
1771 #"
1772 [(set_attr "type" "mult_compare")
1773 (set_attr "length" "4,8")])
1774
1775 (define_split
1776 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1777 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1778 (match_operand:SI 2 "gpc_reg_operand" ""))
1779 (const_int 0)))
1780 (set (match_operand:SI 0 "gpc_reg_operand" "")
1781 (mult:SI (match_dup 1) (match_dup 2)))]
1782 "! TARGET_POWER && reload_completed"
1783 [(set (match_dup 0)
1784 (mult:SI (match_dup 1) (match_dup 2)))
1785 (set (match_dup 3)
1786 (compare:CC (match_dup 0)
1787 (const_int 0)))]
1788 "")
1789
1790 ;; Operand 1 is divided by operand 2; quotient goes to operand
1791 ;; 0 and remainder to operand 3.
1792 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1793
1794 (define_expand "divmodsi4"
1795 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1796 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1797 (match_operand:SI 2 "gpc_reg_operand" "")))
1798 (set (match_operand:SI 3 "register_operand" "")
1799 (mod:SI (match_dup 1) (match_dup 2)))])]
1800 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1801 "
1802 {
1803 if (! TARGET_POWER && ! TARGET_POWERPC)
1804 {
1805 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1806 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1807 emit_insn (gen_divss_call ());
1808 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1809 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1810 DONE;
1811 }
1812 }")
1813
1814 (define_insn "*divmodsi4_internal"
1815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1816 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1817 (match_operand:SI 2 "gpc_reg_operand" "r")))
1818 (set (match_operand:SI 3 "register_operand" "=q")
1819 (mod:SI (match_dup 1) (match_dup 2)))]
1820 "TARGET_POWER"
1821 "divs %0,%1,%2"
1822 [(set_attr "type" "idiv")])
1823
1824 (define_expand "udivsi3"
1825 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1826 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1827 (match_operand:SI 2 "gpc_reg_operand" "")))]
1828 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1829 "
1830 {
1831 if (! TARGET_POWER && ! TARGET_POWERPC)
1832 {
1833 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1834 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1835 emit_insn (gen_quous_call ());
1836 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1837 DONE;
1838 }
1839 else if (TARGET_POWER)
1840 {
1841 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1842 DONE;
1843 }
1844 }")
1845
1846 (define_insn "udivsi3_mq"
1847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1848 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1849 (match_operand:SI 2 "gpc_reg_operand" "r")))
1850 (clobber (match_scratch:SI 3 "=q"))]
1851 "TARGET_POWERPC && TARGET_POWER"
1852 "divwu %0,%1,%2"
1853 [(set_attr "type" "idiv")])
1854
1855 (define_insn "*udivsi3_no_mq"
1856 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1857 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1858 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1859 "TARGET_POWERPC && ! TARGET_POWER"
1860 "divwu %0,%1,%2"
1861 [(set_attr "type" "idiv")])
1862
1863 ;; For powers of two we can do srai/aze for divide and then adjust for
1864 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1865 ;; used; for PowerPC, force operands into register and do a normal divide;
1866 ;; for AIX common-mode, use quoss call on register operands.
1867 (define_expand "divsi3"
1868 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1869 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1870 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1871 ""
1872 "
1873 {
1874 if (GET_CODE (operands[2]) == CONST_INT
1875 && INTVAL (operands[2]) > 0
1876 && exact_log2 (INTVAL (operands[2])) >= 0)
1877 ;
1878 else if (TARGET_POWERPC)
1879 {
1880 operands[2] = force_reg (SImode, operands[2]);
1881 if (TARGET_POWER)
1882 {
1883 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1884 DONE;
1885 }
1886 }
1887 else if (TARGET_POWER)
1888 FAIL;
1889 else
1890 {
1891 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1892 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1893 emit_insn (gen_quoss_call ());
1894 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1895 DONE;
1896 }
1897 }")
1898
1899 (define_insn "divsi3_mq"
1900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1901 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1902 (match_operand:SI 2 "gpc_reg_operand" "r")))
1903 (clobber (match_scratch:SI 3 "=q"))]
1904 "TARGET_POWERPC && TARGET_POWER"
1905 "divw %0,%1,%2"
1906 [(set_attr "type" "idiv")])
1907
1908 (define_insn "*divsi3_no_mq"
1909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1910 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1911 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1912 "TARGET_POWERPC && ! TARGET_POWER"
1913 "divw %0,%1,%2"
1914 [(set_attr "type" "idiv")])
1915
1916 (define_expand "modsi3"
1917 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1918 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1919 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1920 ""
1921 "
1922 {
1923 int i;
1924 rtx temp1;
1925 rtx temp2;
1926
1927 if (GET_CODE (operands[2]) != CONST_INT
1928 || INTVAL (operands[2]) <= 0
1929 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1930 FAIL;
1931
1932 temp1 = gen_reg_rtx (SImode);
1933 temp2 = gen_reg_rtx (SImode);
1934
1935 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1936 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1937 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1938 DONE;
1939 }")
1940
1941 (define_insn ""
1942 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1943 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1944 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1945 ""
1946 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1947 [(set_attr "length" "8")])
1948
1949 (define_insn ""
1950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1951 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1952 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1953 (const_int 0)))
1954 (clobber (match_scratch:SI 3 "=r,r"))]
1955 ""
1956 "@
1957 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1958 #"
1959 [(set_attr "type" "compare")
1960 (set_attr "length" "8,12")])
1961
1962 (define_split
1963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1964 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1965 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1966 (const_int 0)))
1967 (clobber (match_scratch:SI 3 ""))]
1968 "reload_completed"
1969 [(set (match_dup 3)
1970 (div:SI (match_dup 1) (match_dup 2)))
1971 (set (match_dup 0)
1972 (compare:CC (match_dup 3)
1973 (const_int 0)))]
1974 "")
1975
1976 (define_insn ""
1977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1978 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1979 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1980 (const_int 0)))
1981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1982 (div:SI (match_dup 1) (match_dup 2)))]
1983 ""
1984 "@
1985 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
1986 #"
1987 [(set_attr "type" "compare")
1988 (set_attr "length" "8,12")])
1989
1990 (define_split
1991 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1992 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1993 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1994 (const_int 0)))
1995 (set (match_operand:SI 0 "gpc_reg_operand" "")
1996 (div:SI (match_dup 1) (match_dup 2)))]
1997 "reload_completed"
1998 [(set (match_dup 0)
1999 (div:SI (match_dup 1) (match_dup 2)))
2000 (set (match_dup 3)
2001 (compare:CC (match_dup 0)
2002 (const_int 0)))]
2003 "")
2004
2005 (define_insn ""
2006 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2007 (udiv:SI
2008 (plus:DI (ashift:DI
2009 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2010 (const_int 32))
2011 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2012 (match_operand:SI 3 "gpc_reg_operand" "r")))
2013 (set (match_operand:SI 2 "register_operand" "=*q")
2014 (umod:SI
2015 (plus:DI (ashift:DI
2016 (zero_extend:DI (match_dup 1)) (const_int 32))
2017 (zero_extend:DI (match_dup 4)))
2018 (match_dup 3)))]
2019 "TARGET_POWER"
2020 "div %0,%1,%3"
2021 [(set_attr "type" "idiv")])
2022
2023 ;; To do unsigned divide we handle the cases of the divisor looking like a
2024 ;; negative number. If it is a constant that is less than 2**31, we don't
2025 ;; have to worry about the branches. So make a few subroutines here.
2026 ;;
2027 ;; First comes the normal case.
2028 (define_expand "udivmodsi4_normal"
2029 [(set (match_dup 4) (const_int 0))
2030 (parallel [(set (match_operand:SI 0 "" "")
2031 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2032 (const_int 32))
2033 (zero_extend:DI (match_operand:SI 1 "" "")))
2034 (match_operand:SI 2 "" "")))
2035 (set (match_operand:SI 3 "" "")
2036 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2037 (const_int 32))
2038 (zero_extend:DI (match_dup 1)))
2039 (match_dup 2)))])]
2040 "TARGET_POWER"
2041 "
2042 { operands[4] = gen_reg_rtx (SImode); }")
2043
2044 ;; This handles the branches.
2045 (define_expand "udivmodsi4_tests"
2046 [(set (match_operand:SI 0 "" "") (const_int 0))
2047 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2048 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2049 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2050 (label_ref (match_operand:SI 4 "" "")) (pc)))
2051 (set (match_dup 0) (const_int 1))
2052 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2053 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2054 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2055 (label_ref (match_dup 4)) (pc)))]
2056 "TARGET_POWER"
2057 "
2058 { operands[5] = gen_reg_rtx (CCUNSmode);
2059 operands[6] = gen_reg_rtx (CCmode);
2060 }")
2061
2062 (define_expand "udivmodsi4"
2063 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2064 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2065 (match_operand:SI 2 "reg_or_cint_operand" "")))
2066 (set (match_operand:SI 3 "gpc_reg_operand" "")
2067 (umod:SI (match_dup 1) (match_dup 2)))])]
2068 ""
2069 "
2070 {
2071 rtx label = 0;
2072
2073 if (! TARGET_POWER)
2074 {
2075 if (! TARGET_POWERPC)
2076 {
2077 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2078 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2079 emit_insn (gen_divus_call ());
2080 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2081 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2082 DONE;
2083 }
2084 else
2085 FAIL;
2086 }
2087
2088 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2089 {
2090 operands[2] = force_reg (SImode, operands[2]);
2091 label = gen_label_rtx ();
2092 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2093 operands[3], label));
2094 }
2095 else
2096 operands[2] = force_reg (SImode, operands[2]);
2097
2098 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2099 operands[3]));
2100 if (label)
2101 emit_label (label);
2102
2103 DONE;
2104 }")
2105
2106 ;; AIX architecture-independent common-mode multiply (DImode),
2107 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2108 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2109 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2110 ;; assumed unused if generating common-mode, so ignore.
2111 (define_insn "mulh_call"
2112 [(set (reg:SI 3)
2113 (truncate:SI
2114 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2115 (sign_extend:DI (reg:SI 4)))
2116 (const_int 32))))
2117 (clobber (match_scratch:SI 0 "=l"))]
2118 "! TARGET_POWER && ! TARGET_POWERPC"
2119 "bla __mulh"
2120 [(set_attr "type" "imul")])
2121
2122 (define_insn "mull_call"
2123 [(set (reg:DI 3)
2124 (mult:DI (sign_extend:DI (reg:SI 3))
2125 (sign_extend:DI (reg:SI 4))))
2126 (clobber (match_scratch:SI 0 "=l"))
2127 (clobber (reg:SI 0))]
2128 "! TARGET_POWER && ! TARGET_POWERPC"
2129 "bla __mull"
2130 [(set_attr "type" "imul")])
2131
2132 (define_insn "divss_call"
2133 [(set (reg:SI 3)
2134 (div:SI (reg:SI 3) (reg:SI 4)))
2135 (set (reg:SI 4)
2136 (mod:SI (reg:SI 3) (reg:SI 4)))
2137 (clobber (match_scratch:SI 0 "=l"))
2138 (clobber (reg:SI 0))]
2139 "! TARGET_POWER && ! TARGET_POWERPC"
2140 "bla __divss"
2141 [(set_attr "type" "idiv")])
2142
2143 (define_insn "divus_call"
2144 [(set (reg:SI 3)
2145 (udiv:SI (reg:SI 3) (reg:SI 4)))
2146 (set (reg:SI 4)
2147 (umod:SI (reg:SI 3) (reg:SI 4)))
2148 (clobber (match_scratch:SI 0 "=l"))
2149 (clobber (reg:SI 0))
2150 (clobber (match_scratch:CC 1 "=x"))
2151 (clobber (reg:CC 69))]
2152 "! TARGET_POWER && ! TARGET_POWERPC"
2153 "bla __divus"
2154 [(set_attr "type" "idiv")])
2155
2156 (define_insn "quoss_call"
2157 [(set (reg:SI 3)
2158 (div:SI (reg:SI 3) (reg:SI 4)))
2159 (clobber (match_scratch:SI 0 "=l"))]
2160 "! TARGET_POWER && ! TARGET_POWERPC"
2161 "bla __quoss"
2162 [(set_attr "type" "idiv")])
2163
2164 (define_insn "quous_call"
2165 [(set (reg:SI 3)
2166 (udiv:SI (reg:SI 3) (reg:SI 4)))
2167 (clobber (match_scratch:SI 0 "=l"))
2168 (clobber (reg:SI 0))
2169 (clobber (match_scratch:CC 1 "=x"))
2170 (clobber (reg:CC 69))]
2171 "! TARGET_POWER && ! TARGET_POWERPC"
2172 "bla __quous"
2173 [(set_attr "type" "idiv")])
2174 \f
2175 ;; Logical instructions
2176 ;; The logical instructions are mostly combined by using match_operator,
2177 ;; but the plain AND insns are somewhat different because there is no
2178 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2179 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2180
2181 (define_insn "andsi3"
2182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2183 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2184 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2185 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2186 ""
2187 "@
2188 and %0,%1,%2
2189 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2190 {andil.|andi.} %0,%1,%b2
2191 {andiu.|andis.} %0,%1,%u2")
2192
2193 ;; Note to set cr's other than cr0 we do the and immediate and then
2194 ;; the test again -- this avoids a mfcr which on the higher end
2195 ;; machines causes an execution serialization
2196
2197 (define_insn "*andsi3_internal2"
2198 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2199 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2200 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2201 (const_int 0)))
2202 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2203 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2204 "! TARGET_POWERPC64"
2205 "@
2206 and. %3,%1,%2
2207 {andil.|andi.} %3,%1,%b2
2208 {andiu.|andis.} %3,%1,%u2
2209 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2210 #
2211 #
2212 #
2213 #"
2214 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2215 (set_attr "length" "4,4,4,4,8,8,8,8")])
2216
2217 (define_insn "*andsi3_internal3"
2218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2219 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2220 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2221 (const_int 0)))
2222 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2223 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2224 "TARGET_POWERPC64"
2225 "@
2226 #
2227 {andil.|andi.} %3,%1,%b2
2228 {andiu.|andis.} %3,%1,%u2
2229 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2230 #
2231 #
2232 #
2233 #"
2234 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2235 (set_attr "length" "8,4,4,4,8,8,8,8")])
2236
2237 (define_split
2238 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2239 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2240 (match_operand:SI 2 "and_operand" ""))
2241 (const_int 0)))
2242 (clobber (match_scratch:SI 3 ""))
2243 (clobber (match_scratch:CC 4 ""))]
2244 "reload_completed"
2245 [(parallel [(set (match_dup 3)
2246 (and:SI (match_dup 1)
2247 (match_dup 2)))
2248 (clobber (match_dup 4))])
2249 (set (match_dup 0)
2250 (compare:CC (match_dup 3)
2251 (const_int 0)))]
2252 "")
2253
2254 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2255 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2256
2257 (define_split
2258 [(set (match_operand:CC 0 "cc_reg_operand" "")
2259 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2260 (match_operand:SI 2 "gpc_reg_operand" ""))
2261 (const_int 0)))
2262 (clobber (match_scratch:SI 3 ""))
2263 (clobber (match_scratch:CC 4 ""))]
2264 "TARGET_POWERPC64 && reload_completed"
2265 [(parallel [(set (match_dup 3)
2266 (and:SI (match_dup 1)
2267 (match_dup 2)))
2268 (clobber (match_dup 4))])
2269 (set (match_dup 0)
2270 (compare:CC (match_dup 3)
2271 (const_int 0)))]
2272 "")
2273
2274 (define_insn "*andsi3_internal4"
2275 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2276 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2277 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2278 (const_int 0)))
2279 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2280 (and:SI (match_dup 1)
2281 (match_dup 2)))
2282 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2283 "! TARGET_POWERPC64"
2284 "@
2285 and. %0,%1,%2
2286 {andil.|andi.} %0,%1,%b2
2287 {andiu.|andis.} %0,%1,%u2
2288 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2289 #
2290 #
2291 #
2292 #"
2293 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2294 (set_attr "length" "4,4,4,4,8,8,8,8")])
2295
2296 (define_insn "*andsi3_internal5"
2297 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2298 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2299 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2300 (const_int 0)))
2301 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2302 (and:SI (match_dup 1)
2303 (match_dup 2)))
2304 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2305 "TARGET_POWERPC64"
2306 "@
2307 #
2308 {andil.|andi.} %0,%1,%b2
2309 {andiu.|andis.} %0,%1,%u2
2310 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2311 #
2312 #
2313 #
2314 #"
2315 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2316 (set_attr "length" "8,4,4,4,8,8,8,8")])
2317
2318 (define_split
2319 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2320 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2321 (match_operand:SI 2 "and_operand" ""))
2322 (const_int 0)))
2323 (set (match_operand:SI 0 "gpc_reg_operand" "")
2324 (and:SI (match_dup 1)
2325 (match_dup 2)))
2326 (clobber (match_scratch:CC 4 ""))]
2327 "reload_completed"
2328 [(parallel [(set (match_dup 0)
2329 (and:SI (match_dup 1)
2330 (match_dup 2)))
2331 (clobber (match_dup 4))])
2332 (set (match_dup 3)
2333 (compare:CC (match_dup 0)
2334 (const_int 0)))]
2335 "")
2336
2337 (define_split
2338 [(set (match_operand:CC 3 "cc_reg_operand" "")
2339 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2340 (match_operand:SI 2 "gpc_reg_operand" ""))
2341 (const_int 0)))
2342 (set (match_operand:SI 0 "gpc_reg_operand" "")
2343 (and:SI (match_dup 1)
2344 (match_dup 2)))
2345 (clobber (match_scratch:CC 4 ""))]
2346 "TARGET_POWERPC64 && reload_completed"
2347 [(parallel [(set (match_dup 0)
2348 (and:SI (match_dup 1)
2349 (match_dup 2)))
2350 (clobber (match_dup 4))])
2351 (set (match_dup 3)
2352 (compare:CC (match_dup 0)
2353 (const_int 0)))]
2354 "")
2355
2356 ;; Handle the PowerPC64 rlwinm corner case
2357
2358 (define_insn_and_split "*andsi3_internal6"
2359 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2360 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2361 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2362 "TARGET_POWERPC64"
2363 "#"
2364 "TARGET_POWERPC64"
2365 [(set (match_dup 0)
2366 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2367 (match_dup 4)))
2368 (set (match_dup 0)
2369 (rotate:SI (match_dup 0) (match_dup 5)))]
2370 "
2371 {
2372 int mb = extract_MB (operands[2]);
2373 int me = extract_ME (operands[2]);
2374 operands[3] = GEN_INT (me + 1);
2375 operands[5] = GEN_INT (32 - (me + 1));
2376 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2377 }"
2378 [(set_attr "length" "8")])
2379
2380 (define_insn_and_split "*andsi3_internal7"
2381 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2382 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2383 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2384 (const_int 0)))
2385 (clobber (match_scratch:SI 3 "=r,r"))]
2386 "TARGET_POWERPC64"
2387 "#"
2388 "TARGET_POWERPC64"
2389 [(parallel [(set (match_dup 2)
2390 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2391 (match_dup 5))
2392 (const_int 0)))
2393 (clobber (match_dup 3))])]
2394 "
2395 {
2396 int mb = extract_MB (operands[1]);
2397 int me = extract_ME (operands[1]);
2398 operands[4] = GEN_INT (me + 1);
2399 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2400 }"
2401 [(set_attr "type" "delayed_compare,compare")
2402 (set_attr "length" "4,8")])
2403
2404 (define_insn_and_split "*andsi3_internal8"
2405 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2406 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2407 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2408 (const_int 0)))
2409 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2410 (and:SI (match_dup 1)
2411 (match_dup 2)))]
2412 "TARGET_POWERPC64"
2413 "#"
2414 "TARGET_POWERPC64"
2415 [(parallel [(set (match_dup 3)
2416 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2417 (match_dup 5))
2418 (const_int 0)))
2419 (set (match_dup 0)
2420 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2421 (match_dup 5)))])
2422 (set (match_dup 0)
2423 (rotate:SI (match_dup 0) (match_dup 6)))]
2424 "
2425 {
2426 int mb = extract_MB (operands[2]);
2427 int me = extract_ME (operands[2]);
2428 operands[4] = GEN_INT (me + 1);
2429 operands[6] = GEN_INT (32 - (me + 1));
2430 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2431 }"
2432 [(set_attr "type" "delayed_compare,compare")
2433 (set_attr "length" "8,12")])
2434
2435 (define_expand "iorsi3"
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2437 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2438 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2439 ""
2440 "
2441 {
2442 if (GET_CODE (operands[2]) == CONST_INT
2443 && ! logical_operand (operands[2], SImode))
2444 {
2445 HOST_WIDE_INT value = INTVAL (operands[2]);
2446 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2447 ? operands[0] : gen_reg_rtx (SImode));
2448
2449 emit_insn (gen_iorsi3 (tmp, operands[1],
2450 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2451 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2452 DONE;
2453 }
2454 }")
2455
2456 (define_expand "xorsi3"
2457 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2458 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2459 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2460 ""
2461 "
2462 {
2463 if (GET_CODE (operands[2]) == CONST_INT
2464 && ! logical_operand (operands[2], SImode))
2465 {
2466 HOST_WIDE_INT value = INTVAL (operands[2]);
2467 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2468 ? operands[0] : gen_reg_rtx (SImode));
2469
2470 emit_insn (gen_xorsi3 (tmp, operands[1],
2471 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2472 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2473 DONE;
2474 }
2475 }")
2476
2477 (define_insn "*boolsi3_internal1"
2478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2479 (match_operator:SI 3 "boolean_or_operator"
2480 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2481 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2482 ""
2483 "@
2484 %q3 %0,%1,%2
2485 {%q3il|%q3i} %0,%1,%b2
2486 {%q3iu|%q3is} %0,%1,%u2")
2487
2488 (define_insn "*boolsi3_internal2"
2489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2490 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2491 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2492 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2493 (const_int 0)))
2494 (clobber (match_scratch:SI 3 "=r,r"))]
2495 "! TARGET_POWERPC64"
2496 "@
2497 %q4. %3,%1,%2
2498 #"
2499 [(set_attr "type" "compare")
2500 (set_attr "length" "4,8")])
2501
2502 (define_split
2503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2504 (compare:CC (match_operator:SI 4 "boolean_operator"
2505 [(match_operand:SI 1 "gpc_reg_operand" "")
2506 (match_operand:SI 2 "gpc_reg_operand" "")])
2507 (const_int 0)))
2508 (clobber (match_scratch:SI 3 ""))]
2509 "! TARGET_POWERPC64 && reload_completed"
2510 [(set (match_dup 3) (match_dup 4))
2511 (set (match_dup 0)
2512 (compare:CC (match_dup 3)
2513 (const_int 0)))]
2514 "")
2515
2516 (define_insn "*boolsi3_internal3"
2517 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2518 (compare:CC (match_operator:SI 4 "boolean_operator"
2519 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2520 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2521 (const_int 0)))
2522 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2523 (match_dup 4))]
2524 "! TARGET_POWERPC64"
2525 "@
2526 %q4. %0,%1,%2
2527 #"
2528 [(set_attr "type" "compare")
2529 (set_attr "length" "4,8")])
2530
2531 (define_split
2532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2533 (compare:CC (match_operator:SI 4 "boolean_operator"
2534 [(match_operand:SI 1 "gpc_reg_operand" "")
2535 (match_operand:SI 2 "gpc_reg_operand" "")])
2536 (const_int 0)))
2537 (set (match_operand:SI 0 "gpc_reg_operand" "")
2538 (match_dup 4))]
2539 "! TARGET_POWERPC64 && reload_completed"
2540 [(set (match_dup 0) (match_dup 4))
2541 (set (match_dup 3)
2542 (compare:CC (match_dup 0)
2543 (const_int 0)))]
2544 "")
2545
2546 ;; Split a logical operation that we can't do in one insn into two insns,
2547 ;; each of which does one 16-bit part. This is used by combine.
2548
2549 (define_split
2550 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2551 (match_operator:SI 3 "boolean_or_operator"
2552 [(match_operand:SI 1 "gpc_reg_operand" "")
2553 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2554 ""
2555 [(set (match_dup 0) (match_dup 4))
2556 (set (match_dup 0) (match_dup 5))]
2557 "
2558 {
2559 rtx i;
2560 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2561 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2562 operands[1], i);
2563 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2564 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2565 operands[0], i);
2566 }")
2567
2568 (define_insn "*boolcsi3_internal1"
2569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2570 (match_operator:SI 3 "boolean_operator"
2571 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2572 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2573 ""
2574 "%q3 %0,%2,%1")
2575
2576 (define_insn "*boolcsi3_internal2"
2577 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2578 (compare:CC (match_operator:SI 4 "boolean_operator"
2579 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2580 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2581 (const_int 0)))
2582 (clobber (match_scratch:SI 3 "=r,r"))]
2583 "! TARGET_POWERPC64"
2584 "@
2585 %q4. %3,%2,%1
2586 #"
2587 [(set_attr "type" "compare")
2588 (set_attr "length" "4,8")])
2589
2590 (define_split
2591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2592 (compare:CC (match_operator:SI 4 "boolean_operator"
2593 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2594 (match_operand:SI 2 "gpc_reg_operand" "")])
2595 (const_int 0)))
2596 (clobber (match_scratch:SI 3 ""))]
2597 "! TARGET_POWERPC64 && reload_completed"
2598 [(set (match_dup 3) (match_dup 4))
2599 (set (match_dup 0)
2600 (compare:CC (match_dup 3)
2601 (const_int 0)))]
2602 "")
2603
2604 (define_insn "*boolcsi3_internal3"
2605 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2606 (compare:CC (match_operator:SI 4 "boolean_operator"
2607 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2608 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2609 (const_int 0)))
2610 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2611 (match_dup 4))]
2612 "! TARGET_POWERPC64"
2613 "@
2614 %q4. %0,%2,%1
2615 #"
2616 [(set_attr "type" "compare")
2617 (set_attr "length" "4,8")])
2618
2619 (define_split
2620 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2621 (compare:CC (match_operator:SI 4 "boolean_operator"
2622 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2623 (match_operand:SI 2 "gpc_reg_operand" "")])
2624 (const_int 0)))
2625 (set (match_operand:SI 0 "gpc_reg_operand" "")
2626 (match_dup 4))]
2627 "! TARGET_POWERPC64 && reload_completed"
2628 [(set (match_dup 0) (match_dup 4))
2629 (set (match_dup 3)
2630 (compare:CC (match_dup 0)
2631 (const_int 0)))]
2632 "")
2633
2634 (define_insn "*boolccsi3_internal1"
2635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2636 (match_operator:SI 3 "boolean_operator"
2637 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2638 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2639 ""
2640 "%q3 %0,%1,%2")
2641
2642 (define_insn "*boolccsi3_internal2"
2643 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2644 (compare:CC (match_operator:SI 4 "boolean_operator"
2645 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2646 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2647 (const_int 0)))
2648 (clobber (match_scratch:SI 3 "=r,r"))]
2649 "! TARGET_POWERPC64"
2650 "@
2651 %q4. %3,%1,%2
2652 #"
2653 [(set_attr "type" "compare")
2654 (set_attr "length" "4,8")])
2655
2656 (define_split
2657 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2658 (compare:CC (match_operator:SI 4 "boolean_operator"
2659 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2660 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2661 (const_int 0)))
2662 (clobber (match_scratch:SI 3 ""))]
2663 "! TARGET_POWERPC64 && reload_completed"
2664 [(set (match_dup 3) (match_dup 4))
2665 (set (match_dup 0)
2666 (compare:CC (match_dup 3)
2667 (const_int 0)))]
2668 "")
2669
2670 (define_insn "*boolccsi3_internal3"
2671 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2672 (compare:CC (match_operator:SI 4 "boolean_operator"
2673 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2674 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2675 (const_int 0)))
2676 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2677 (match_dup 4))]
2678 "! TARGET_POWERPC64"
2679 "@
2680 %q4. %0,%1,%2
2681 #"
2682 [(set_attr "type" "compare")
2683 (set_attr "length" "4,8")])
2684
2685 (define_split
2686 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2687 (compare:CC (match_operator:SI 4 "boolean_operator"
2688 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2689 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2690 (const_int 0)))
2691 (set (match_operand:SI 0 "gpc_reg_operand" "")
2692 (match_dup 4))]
2693 "! TARGET_POWERPC64 && reload_completed"
2694 [(set (match_dup 0) (match_dup 4))
2695 (set (match_dup 3)
2696 (compare:CC (match_dup 0)
2697 (const_int 0)))]
2698 "")
2699
2700 ;; maskir insn. We need four forms because things might be in arbitrary
2701 ;; orders. Don't define forms that only set CR fields because these
2702 ;; would modify an input register.
2703
2704 (define_insn "*maskir_internal1"
2705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2706 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2707 (match_operand:SI 1 "gpc_reg_operand" "0"))
2708 (and:SI (match_dup 2)
2709 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2710 "TARGET_POWER"
2711 "maskir %0,%3,%2")
2712
2713 (define_insn "*maskir_internal2"
2714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2715 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2716 (match_operand:SI 1 "gpc_reg_operand" "0"))
2717 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2718 (match_dup 2))))]
2719 "TARGET_POWER"
2720 "maskir %0,%3,%2")
2721
2722 (define_insn "*maskir_internal3"
2723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2724 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2725 (match_operand:SI 3 "gpc_reg_operand" "r"))
2726 (and:SI (not:SI (match_dup 2))
2727 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2728 "TARGET_POWER"
2729 "maskir %0,%3,%2")
2730
2731 (define_insn "*maskir_internal4"
2732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2733 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2734 (match_operand:SI 2 "gpc_reg_operand" "r"))
2735 (and:SI (not:SI (match_dup 2))
2736 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2737 "TARGET_POWER"
2738 "maskir %0,%3,%2")
2739
2740 (define_insn "*maskir_internal5"
2741 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2742 (compare:CC
2743 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2744 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2745 (and:SI (match_dup 2)
2746 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2747 (const_int 0)))
2748 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2749 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2750 (and:SI (match_dup 2) (match_dup 3))))]
2751 "TARGET_POWER"
2752 "@
2753 maskir. %0,%3,%2
2754 #"
2755 [(set_attr "type" "compare")
2756 (set_attr "length" "4,8")])
2757
2758 (define_split
2759 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2760 (compare:CC
2761 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2762 (match_operand:SI 1 "gpc_reg_operand" ""))
2763 (and:SI (match_dup 2)
2764 (match_operand:SI 3 "gpc_reg_operand" "")))
2765 (const_int 0)))
2766 (set (match_operand:SI 0 "gpc_reg_operand" "")
2767 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2768 (and:SI (match_dup 2) (match_dup 3))))]
2769 "TARGET_POWER && reload_completed"
2770 [(set (match_dup 0)
2771 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2772 (and:SI (match_dup 2) (match_dup 3))))
2773 (set (match_dup 4)
2774 (compare:CC (match_dup 0)
2775 (const_int 0)))]
2776 "")
2777
2778 (define_insn "*maskir_internal6"
2779 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2780 (compare:CC
2781 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2782 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2783 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2784 (match_dup 2)))
2785 (const_int 0)))
2786 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2787 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2788 (and:SI (match_dup 3) (match_dup 2))))]
2789 "TARGET_POWER"
2790 "@
2791 maskir. %0,%3,%2
2792 #"
2793 [(set_attr "type" "compare")
2794 (set_attr "length" "4,8")])
2795
2796 (define_split
2797 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2798 (compare:CC
2799 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2800 (match_operand:SI 1 "gpc_reg_operand" ""))
2801 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2802 (match_dup 2)))
2803 (const_int 0)))
2804 (set (match_operand:SI 0 "gpc_reg_operand" "")
2805 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2806 (and:SI (match_dup 3) (match_dup 2))))]
2807 "TARGET_POWER && reload_completed"
2808 [(set (match_dup 0)
2809 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2810 (and:SI (match_dup 3) (match_dup 2))))
2811 (set (match_dup 4)
2812 (compare:CC (match_dup 0)
2813 (const_int 0)))]
2814 "")
2815
2816 (define_insn "*maskir_internal7"
2817 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2818 (compare:CC
2819 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2820 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2821 (and:SI (not:SI (match_dup 2))
2822 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2823 (const_int 0)))
2824 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2825 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2826 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2827 "TARGET_POWER"
2828 "@
2829 maskir. %0,%3,%2
2830 #"
2831 [(set_attr "type" "compare")
2832 (set_attr "length" "4,8")])
2833
2834 (define_split
2835 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2836 (compare:CC
2837 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2838 (match_operand:SI 3 "gpc_reg_operand" ""))
2839 (and:SI (not:SI (match_dup 2))
2840 (match_operand:SI 1 "gpc_reg_operand" "")))
2841 (const_int 0)))
2842 (set (match_operand:SI 0 "gpc_reg_operand" "")
2843 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2844 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2845 "TARGET_POWER && reload_completed"
2846 [(set (match_dup 0)
2847 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2848 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2849 (set (match_dup 4)
2850 (compare:CC (match_dup 0)
2851 (const_int 0)))]
2852 "")
2853
2854 (define_insn "*maskir_internal8"
2855 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2856 (compare:CC
2857 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2858 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2859 (and:SI (not:SI (match_dup 2))
2860 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2861 (const_int 0)))
2862 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2863 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2864 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2865 "TARGET_POWER"
2866 "@
2867 maskir. %0,%3,%2
2868 #"
2869 [(set_attr "type" "compare")
2870 (set_attr "length" "4,8")])
2871
2872 (define_split
2873 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2874 (compare:CC
2875 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2876 (match_operand:SI 2 "gpc_reg_operand" ""))
2877 (and:SI (not:SI (match_dup 2))
2878 (match_operand:SI 1 "gpc_reg_operand" "")))
2879 (const_int 0)))
2880 (set (match_operand:SI 0 "gpc_reg_operand" "")
2881 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2882 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2883 "TARGET_POWER && reload_completed"
2884 [(set (match_dup 0)
2885 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2886 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2887 (set (match_dup 4)
2888 (compare:CC (match_dup 0)
2889 (const_int 0)))]
2890 "")
2891 \f
2892 ;; Rotate and shift insns, in all their variants. These support shifts,
2893 ;; field inserts and extracts, and various combinations thereof.
2894 (define_expand "insv"
2895 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2896 (match_operand:SI 1 "const_int_operand" "")
2897 (match_operand:SI 2 "const_int_operand" ""))
2898 (match_operand 3 "gpc_reg_operand" ""))]
2899 ""
2900 "
2901 {
2902 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2903 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2904 compiler if the address of the structure is taken later. */
2905 if (GET_CODE (operands[0]) == SUBREG
2906 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2907 FAIL;
2908
2909 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2910 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2911 else
2912 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2913 DONE;
2914 }")
2915
2916 (define_insn "insvsi"
2917 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2918 (match_operand:SI 1 "const_int_operand" "i")
2919 (match_operand:SI 2 "const_int_operand" "i"))
2920 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2921 ""
2922 "*
2923 {
2924 int start = INTVAL (operands[2]) & 31;
2925 int size = INTVAL (operands[1]) & 31;
2926
2927 operands[4] = GEN_INT (32 - start - size);
2928 operands[1] = GEN_INT (start + size - 1);
2929 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2930 }")
2931
2932 (define_insn "*insvsi_internal1"
2933 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2934 (match_operand:SI 1 "const_int_operand" "i")
2935 (match_operand:SI 2 "const_int_operand" "i"))
2936 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2937 (match_operand:SI 4 "const_int_operand" "i")))]
2938 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2939 "*
2940 {
2941 int shift = INTVAL (operands[4]) & 31;
2942 int start = INTVAL (operands[2]) & 31;
2943 int size = INTVAL (operands[1]) & 31;
2944
2945 operands[4] = GEN_INT (shift - start - size);
2946 operands[1] = GEN_INT (start + size - 1);
2947 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2948 }")
2949
2950 (define_insn "*insvsi_internal2"
2951 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2952 (match_operand:SI 1 "const_int_operand" "i")
2953 (match_operand:SI 2 "const_int_operand" "i"))
2954 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2955 (match_operand:SI 4 "const_int_operand" "i")))]
2956 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2957 "*
2958 {
2959 int shift = INTVAL (operands[4]) & 31;
2960 int start = INTVAL (operands[2]) & 31;
2961 int size = INTVAL (operands[1]) & 31;
2962
2963 operands[4] = GEN_INT (32 - shift - start - size);
2964 operands[1] = GEN_INT (start + size - 1);
2965 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2966 }")
2967
2968 (define_insn "*insvsi_internal3"
2969 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2970 (match_operand:SI 1 "const_int_operand" "i")
2971 (match_operand:SI 2 "const_int_operand" "i"))
2972 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2973 (match_operand:SI 4 "const_int_operand" "i")))]
2974 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2975 "*
2976 {
2977 int shift = INTVAL (operands[4]) & 31;
2978 int start = INTVAL (operands[2]) & 31;
2979 int size = INTVAL (operands[1]) & 31;
2980
2981 operands[4] = GEN_INT (32 - shift - start - size);
2982 operands[1] = GEN_INT (start + size - 1);
2983 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2984 }")
2985
2986 (define_insn "*insvsi_internal4"
2987 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2988 (match_operand:SI 1 "const_int_operand" "i")
2989 (match_operand:SI 2 "const_int_operand" "i"))
2990 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2991 (match_operand:SI 4 "const_int_operand" "i")
2992 (match_operand:SI 5 "const_int_operand" "i")))]
2993 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2994 "*
2995 {
2996 int extract_start = INTVAL (operands[5]) & 31;
2997 int extract_size = INTVAL (operands[4]) & 31;
2998 int insert_start = INTVAL (operands[2]) & 31;
2999 int insert_size = INTVAL (operands[1]) & 31;
3000
3001 /* Align extract field with insert field */
3002 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3003 operands[1] = GEN_INT (insert_start + insert_size - 1);
3004 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3005 }")
3006
3007 (define_insn "insvdi"
3008 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3009 (match_operand:SI 1 "const_int_operand" "i")
3010 (match_operand:SI 2 "const_int_operand" "i"))
3011 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3012 "TARGET_POWERPC64"
3013 "*
3014 {
3015 int start = INTVAL (operands[2]) & 63;
3016 int size = INTVAL (operands[1]) & 63;
3017
3018 operands[1] = GEN_INT (64 - start - size);
3019 return \"rldimi %0,%3,%H1,%H2\";
3020 }")
3021
3022 (define_expand "extzv"
3023 [(set (match_operand 0 "gpc_reg_operand" "")
3024 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3025 (match_operand:SI 2 "const_int_operand" "")
3026 (match_operand:SI 3 "const_int_operand" "")))]
3027 ""
3028 "
3029 {
3030 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3031 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3032 compiler if the address of the structure is taken later. */
3033 if (GET_CODE (operands[0]) == SUBREG
3034 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3035 FAIL;
3036
3037 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3038 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3039 else
3040 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3041 DONE;
3042 }")
3043
3044 (define_insn "extzvsi"
3045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3046 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3047 (match_operand:SI 2 "const_int_operand" "i")
3048 (match_operand:SI 3 "const_int_operand" "i")))]
3049 ""
3050 "*
3051 {
3052 int start = INTVAL (operands[3]) & 31;
3053 int size = INTVAL (operands[2]) & 31;
3054
3055 if (start + size >= 32)
3056 operands[3] = const0_rtx;
3057 else
3058 operands[3] = GEN_INT (start + size);
3059 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3060 }")
3061
3062 (define_insn "*extzvsi_internal1"
3063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3064 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3065 (match_operand:SI 2 "const_int_operand" "i,i")
3066 (match_operand:SI 3 "const_int_operand" "i,i"))
3067 (const_int 0)))
3068 (clobber (match_scratch:SI 4 "=r,r"))]
3069 ""
3070 "*
3071 {
3072 int start = INTVAL (operands[3]) & 31;
3073 int size = INTVAL (operands[2]) & 31;
3074
3075 /* Force split for non-cc0 compare. */
3076 if (which_alternative == 1)
3077 return \"#\";
3078
3079 /* If the bit-field being tested fits in the upper or lower half of a
3080 word, it is possible to use andiu. or andil. to test it. This is
3081 useful because the condition register set-use delay is smaller for
3082 andi[ul]. than for rlinm. This doesn't work when the starting bit
3083 position is 0 because the LT and GT bits may be set wrong. */
3084
3085 if ((start > 0 && start + size <= 16) || start >= 16)
3086 {
3087 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3088 - (1 << (16 - (start & 15) - size))));
3089 if (start < 16)
3090 return \"{andiu.|andis.} %4,%1,%3\";
3091 else
3092 return \"{andil.|andi.} %4,%1,%3\";
3093 }
3094
3095 if (start + size >= 32)
3096 operands[3] = const0_rtx;
3097 else
3098 operands[3] = GEN_INT (start + size);
3099 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3100 }"
3101 [(set_attr "type" "compare")
3102 (set_attr "length" "4,8")])
3103
3104 (define_split
3105 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3106 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3107 (match_operand:SI 2 "const_int_operand" "")
3108 (match_operand:SI 3 "const_int_operand" ""))
3109 (const_int 0)))
3110 (clobber (match_scratch:SI 4 ""))]
3111 "reload_completed"
3112 [(set (match_dup 4)
3113 (zero_extract:SI (match_dup 1) (match_dup 2)
3114 (match_dup 3)))
3115 (set (match_dup 0)
3116 (compare:CC (match_dup 4)
3117 (const_int 0)))]
3118 "")
3119
3120 (define_insn "*extzvsi_internal2"
3121 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3122 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3123 (match_operand:SI 2 "const_int_operand" "i,i")
3124 (match_operand:SI 3 "const_int_operand" "i,i"))
3125 (const_int 0)))
3126 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3127 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3128 ""
3129 "*
3130 {
3131 int start = INTVAL (operands[3]) & 31;
3132 int size = INTVAL (operands[2]) & 31;
3133
3134 /* Force split for non-cc0 compare. */
3135 if (which_alternative == 1)
3136 return \"#\";
3137
3138 /* Since we are using the output value, we can't ignore any need for
3139 a shift. The bit-field must end at the LSB. */
3140 if (start >= 16 && start + size == 32)
3141 {
3142 operands[3] = GEN_INT ((1 << size) - 1);
3143 return \"{andil.|andi.} %0,%1,%3\";
3144 }
3145
3146 if (start + size >= 32)
3147 operands[3] = const0_rtx;
3148 else
3149 operands[3] = GEN_INT (start + size);
3150 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3151 }"
3152 [(set_attr "type" "compare")
3153 (set_attr "length" "4,8")])
3154
3155 (define_split
3156 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3157 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3158 (match_operand:SI 2 "const_int_operand" "")
3159 (match_operand:SI 3 "const_int_operand" ""))
3160 (const_int 0)))
3161 (set (match_operand:SI 0 "gpc_reg_operand" "")
3162 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3163 "reload_completed"
3164 [(set (match_dup 0)
3165 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3166 (set (match_dup 4)
3167 (compare:CC (match_dup 0)
3168 (const_int 0)))]
3169 "")
3170
3171 (define_insn "extzvdi"
3172 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3173 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3174 (match_operand:SI 2 "const_int_operand" "i")
3175 (match_operand:SI 3 "const_int_operand" "i")))]
3176 "TARGET_POWERPC64"
3177 "*
3178 {
3179 int start = INTVAL (operands[3]) & 63;
3180 int size = INTVAL (operands[2]) & 63;
3181
3182 if (start + size >= 64)
3183 operands[3] = const0_rtx;
3184 else
3185 operands[3] = GEN_INT (start + size);
3186 operands[2] = GEN_INT (64 - size);
3187 return \"rldicl %0,%1,%3,%2\";
3188 }")
3189
3190 (define_insn "*extzvdi_internal1"
3191 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3192 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3193 (match_operand:SI 2 "const_int_operand" "i")
3194 (match_operand:SI 3 "const_int_operand" "i"))
3195 (const_int 0)))
3196 (clobber (match_scratch:DI 4 "=r"))]
3197 "TARGET_POWERPC64"
3198 "*
3199 {
3200 int start = INTVAL (operands[3]) & 63;
3201 int size = INTVAL (operands[2]) & 63;
3202
3203 if (start + size >= 64)
3204 operands[3] = const0_rtx;
3205 else
3206 operands[3] = GEN_INT (start + size);
3207 operands[2] = GEN_INT (64 - size);
3208 return \"rldicl. %4,%1,%3,%2\";
3209 }")
3210
3211 (define_insn "*extzvdi_internal2"
3212 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3213 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3214 (match_operand:SI 2 "const_int_operand" "i")
3215 (match_operand:SI 3 "const_int_operand" "i"))
3216 (const_int 0)))
3217 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3218 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3219 "TARGET_POWERPC64"
3220 "*
3221 {
3222 int start = INTVAL (operands[3]) & 63;
3223 int size = INTVAL (operands[2]) & 63;
3224
3225 if (start + size >= 64)
3226 operands[3] = const0_rtx;
3227 else
3228 operands[3] = GEN_INT (start + size);
3229 operands[2] = GEN_INT (64 - size);
3230 return \"rldicl. %0,%1,%3,%2\";
3231 }")
3232
3233 (define_insn "rotlsi3"
3234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3235 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3236 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3237 ""
3238 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3239
3240 (define_insn "*rotlsi3_internal2"
3241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3242 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3243 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3244 (const_int 0)))
3245 (clobber (match_scratch:SI 3 "=r,r"))]
3246 ""
3247 "@
3248 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3249 #"
3250 [(set_attr "type" "delayed_compare")
3251 (set_attr "length" "4,8")])
3252
3253 (define_split
3254 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3255 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3256 (match_operand:SI 2 "reg_or_cint_operand" ""))
3257 (const_int 0)))
3258 (clobber (match_scratch:SI 3 ""))]
3259 "reload_completed"
3260 [(set (match_dup 3)
3261 (rotate:SI (match_dup 1) (match_dup 2)))
3262 (set (match_dup 0)
3263 (compare:CC (match_dup 3)
3264 (const_int 0)))]
3265 "")
3266
3267 (define_insn "*rotlsi3_internal3"
3268 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3269 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3270 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3271 (const_int 0)))
3272 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3273 (rotate:SI (match_dup 1) (match_dup 2)))]
3274 ""
3275 "@
3276 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3277 #"
3278 [(set_attr "type" "delayed_compare")
3279 (set_attr "length" "4,8")])
3280
3281 (define_split
3282 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3283 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3284 (match_operand:SI 2 "reg_or_cint_operand" ""))
3285 (const_int 0)))
3286 (set (match_operand:SI 0 "gpc_reg_operand" "")
3287 (rotate:SI (match_dup 1) (match_dup 2)))]
3288 "reload_completed"
3289 [(set (match_dup 0)
3290 (rotate:SI (match_dup 1) (match_dup 2)))
3291 (set (match_dup 3)
3292 (compare:CC (match_dup 0)
3293 (const_int 0)))]
3294 "")
3295
3296 (define_insn "*rotlsi3_internal4"
3297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3298 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3299 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3300 (match_operand:SI 3 "mask_operand" "n")))]
3301 ""
3302 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3303
3304 (define_insn "*rotlsi3_internal5"
3305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3306 (compare:CC (and:SI
3307 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3309 (match_operand:SI 3 "mask_operand" "n,n"))
3310 (const_int 0)))
3311 (clobber (match_scratch:SI 4 "=r,r"))]
3312 ""
3313 "@
3314 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3315 #"
3316 [(set_attr "type" "delayed_compare")
3317 (set_attr "length" "4,8")])
3318
3319 (define_split
3320 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3321 (compare:CC (and:SI
3322 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3323 (match_operand:SI 2 "reg_or_cint_operand" ""))
3324 (match_operand:SI 3 "mask_operand" ""))
3325 (const_int 0)))
3326 (clobber (match_scratch:SI 4 ""))]
3327 "reload_completed"
3328 [(set (match_dup 4)
3329 (and:SI (rotate:SI (match_dup 1)
3330 (match_dup 2))
3331 (match_dup 3)))
3332 (set (match_dup 0)
3333 (compare:CC (match_dup 4)
3334 (const_int 0)))]
3335 "")
3336
3337 (define_insn "*rotlsi3_internal6"
3338 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3339 (compare:CC (and:SI
3340 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3341 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3342 (match_operand:SI 3 "mask_operand" "n,n"))
3343 (const_int 0)))
3344 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3345 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3346 ""
3347 "@
3348 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3349 #"
3350 [(set_attr "type" "delayed_compare")
3351 (set_attr "length" "4,8")])
3352
3353 (define_split
3354 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3355 (compare:CC (and:SI
3356 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3357 (match_operand:SI 2 "reg_or_cint_operand" ""))
3358 (match_operand:SI 3 "mask_operand" ""))
3359 (const_int 0)))
3360 (set (match_operand:SI 0 "gpc_reg_operand" "")
3361 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3362 "reload_completed"
3363 [(set (match_dup 0)
3364 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3365 (set (match_dup 4)
3366 (compare:CC (match_dup 0)
3367 (const_int 0)))]
3368 "")
3369
3370 (define_insn "*rotlsi3_internal7"
3371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3372 (zero_extend:SI
3373 (subreg:QI
3374 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3375 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3376 ""
3377 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3378
3379 (define_insn "*rotlsi3_internal8"
3380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3381 (compare:CC (zero_extend:SI
3382 (subreg:QI
3383 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3384 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3385 (const_int 0)))
3386 (clobber (match_scratch:SI 3 "=r,r"))]
3387 ""
3388 "@
3389 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3390 #"
3391 [(set_attr "type" "delayed_compare")
3392 (set_attr "length" "4,8")])
3393
3394 (define_split
3395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3396 (compare:CC (zero_extend:SI
3397 (subreg:QI
3398 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3399 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3400 (const_int 0)))
3401 (clobber (match_scratch:SI 3 ""))]
3402 "reload_completed"
3403 [(set (match_dup 3)
3404 (zero_extend:SI (subreg:QI
3405 (rotate:SI (match_dup 1)
3406 (match_dup 2)) 0)))
3407 (set (match_dup 0)
3408 (compare:CC (match_dup 3)
3409 (const_int 0)))]
3410 "")
3411
3412 (define_insn "*rotlsi3_internal9"
3413 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3414 (compare:CC (zero_extend:SI
3415 (subreg:QI
3416 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3417 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3418 (const_int 0)))
3419 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3420 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3421 ""
3422 "@
3423 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3424 #"
3425 [(set_attr "type" "delayed_compare")
3426 (set_attr "length" "4,8")])
3427
3428 (define_split
3429 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3430 (compare:CC (zero_extend:SI
3431 (subreg:QI
3432 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3433 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3434 (const_int 0)))
3435 (set (match_operand:SI 0 "gpc_reg_operand" "")
3436 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3437 "reload_completed"
3438 [(set (match_dup 0)
3439 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3440 (set (match_dup 3)
3441 (compare:CC (match_dup 0)
3442 (const_int 0)))]
3443 "")
3444
3445 (define_insn "*rotlsi3_internal10"
3446 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3447 (zero_extend:SI
3448 (subreg:HI
3449 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3450 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3451 ""
3452 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3453
3454 (define_insn "*rotlsi3_internal11"
3455 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3456 (compare:CC (zero_extend:SI
3457 (subreg:HI
3458 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3459 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3460 (const_int 0)))
3461 (clobber (match_scratch:SI 3 "=r,r"))]
3462 ""
3463 "@
3464 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3465 #"
3466 [(set_attr "type" "delayed_compare")
3467 (set_attr "length" "4,8")])
3468
3469 (define_split
3470 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3471 (compare:CC (zero_extend:SI
3472 (subreg:HI
3473 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3474 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3475 (const_int 0)))
3476 (clobber (match_scratch:SI 3 ""))]
3477 "reload_completed"
3478 [(set (match_dup 3)
3479 (zero_extend:SI (subreg:HI
3480 (rotate:SI (match_dup 1)
3481 (match_dup 2)) 0)))
3482 (set (match_dup 0)
3483 (compare:CC (match_dup 3)
3484 (const_int 0)))]
3485 "")
3486
3487 (define_insn "*rotlsi3_internal12"
3488 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3489 (compare:CC (zero_extend:SI
3490 (subreg:HI
3491 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3492 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3493 (const_int 0)))
3494 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3495 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3496 ""
3497 "@
3498 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3499 #"
3500 [(set_attr "type" "delayed_compare")
3501 (set_attr "length" "4,8")])
3502
3503 (define_split
3504 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3505 (compare:CC (zero_extend:SI
3506 (subreg:HI
3507 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3508 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3509 (const_int 0)))
3510 (set (match_operand:SI 0 "gpc_reg_operand" "")
3511 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3512 "reload_completed"
3513 [(set (match_dup 0)
3514 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3515 (set (match_dup 3)
3516 (compare:CC (match_dup 0)
3517 (const_int 0)))]
3518 "")
3519
3520 ;; Note that we use "sle." instead of "sl." so that we can set
3521 ;; SHIFT_COUNT_TRUNCATED.
3522
3523 (define_expand "ashlsi3"
3524 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3525 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3526 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3527 ""
3528 "
3529 {
3530 if (TARGET_POWER)
3531 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3532 else
3533 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3534 DONE;
3535 }")
3536
3537 (define_insn "ashlsi3_power"
3538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3539 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3540 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3541 (clobber (match_scratch:SI 3 "=q,X"))]
3542 "TARGET_POWER"
3543 "@
3544 sle %0,%1,%2
3545 {sli|slwi} %0,%1,%h2")
3546
3547 (define_insn "ashlsi3_no_power"
3548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3549 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3550 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3551 "! TARGET_POWER"
3552 "{sl|slw}%I2 %0,%1,%h2")
3553
3554 (define_insn ""
3555 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3556 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3557 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3558 (const_int 0)))
3559 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3560 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3561 "TARGET_POWER"
3562 "@
3563 sle. %3,%1,%2
3564 {sli.|slwi.} %3,%1,%h2
3565 #
3566 #"
3567 [(set_attr "type" "delayed_compare")
3568 (set_attr "length" "4,4,8,8")])
3569
3570 (define_split
3571 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3572 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3573 (match_operand:SI 2 "reg_or_cint_operand" ""))
3574 (const_int 0)))
3575 (clobber (match_scratch:SI 3 ""))
3576 (clobber (match_scratch:SI 4 ""))]
3577 "TARGET_POWER && reload_completed"
3578 [(parallel [(set (match_dup 3)
3579 (ashift:SI (match_dup 1) (match_dup 2)))
3580 (clobber (match_dup 4))])
3581 (set (match_dup 0)
3582 (compare:CC (match_dup 3)
3583 (const_int 0)))]
3584 "")
3585
3586 (define_insn ""
3587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3588 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3589 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3590 (const_int 0)))
3591 (clobber (match_scratch:SI 3 "=r,r"))]
3592 "! TARGET_POWER && ! TARGET_POWERPC64"
3593 "@
3594 {sl|slw}%I2. %3,%1,%h2
3595 #"
3596 [(set_attr "type" "delayed_compare")
3597 (set_attr "length" "4,8")])
3598
3599 (define_split
3600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3601 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3602 (match_operand:SI 2 "reg_or_cint_operand" ""))
3603 (const_int 0)))
3604 (clobber (match_scratch:SI 3 ""))]
3605 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3606 [(set (match_dup 3)
3607 (ashift:SI (match_dup 1) (match_dup 2)))
3608 (set (match_dup 0)
3609 (compare:CC (match_dup 3)
3610 (const_int 0)))]
3611 "")
3612
3613 (define_insn ""
3614 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3615 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3616 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3617 (const_int 0)))
3618 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3619 (ashift:SI (match_dup 1) (match_dup 2)))
3620 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3621 "TARGET_POWER"
3622 "@
3623 sle. %0,%1,%2
3624 {sli.|slwi.} %0,%1,%h2
3625 #
3626 #"
3627 [(set_attr "type" "delayed_compare")
3628 (set_attr "length" "4,4,8,8")])
3629
3630 (define_split
3631 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3632 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3633 (match_operand:SI 2 "reg_or_cint_operand" ""))
3634 (const_int 0)))
3635 (set (match_operand:SI 0 "gpc_reg_operand" "")
3636 (ashift:SI (match_dup 1) (match_dup 2)))
3637 (clobber (match_scratch:SI 4 ""))]
3638 "TARGET_POWER && reload_completed"
3639 [(parallel [(set (match_dup 0)
3640 (ashift:SI (match_dup 1) (match_dup 2)))
3641 (clobber (match_dup 4))])
3642 (set (match_dup 3)
3643 (compare:CC (match_dup 0)
3644 (const_int 0)))]
3645 "")
3646
3647 (define_insn ""
3648 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3649 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3650 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3651 (const_int 0)))
3652 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3653 (ashift:SI (match_dup 1) (match_dup 2)))]
3654 "! TARGET_POWER && ! TARGET_POWERPC64"
3655 "@
3656 {sl|slw}%I2. %0,%1,%h2
3657 #"
3658 [(set_attr "type" "delayed_compare")
3659 (set_attr "length" "4,8")])
3660
3661 (define_split
3662 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3663 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3664 (match_operand:SI 2 "reg_or_cint_operand" ""))
3665 (const_int 0)))
3666 (set (match_operand:SI 0 "gpc_reg_operand" "")
3667 (ashift:SI (match_dup 1) (match_dup 2)))]
3668 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3669 [(set (match_dup 0)
3670 (ashift:SI (match_dup 1) (match_dup 2)))
3671 (set (match_dup 3)
3672 (compare:CC (match_dup 0)
3673 (const_int 0)))]
3674 "")
3675
3676 (define_insn ""
3677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3678 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3679 (match_operand:SI 2 "const_int_operand" "i"))
3680 (match_operand:SI 3 "mask_operand" "n")))]
3681 "includes_lshift_p (operands[2], operands[3])"
3682 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3683
3684 (define_insn ""
3685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3686 (compare:CC
3687 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3688 (match_operand:SI 2 "const_int_operand" "i,i"))
3689 (match_operand:SI 3 "mask_operand" "n,n"))
3690 (const_int 0)))
3691 (clobber (match_scratch:SI 4 "=r,r"))]
3692 "includes_lshift_p (operands[2], operands[3])"
3693 "@
3694 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3695 #"
3696 [(set_attr "type" "delayed_compare")
3697 (set_attr "length" "4,8")])
3698
3699 (define_split
3700 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3701 (compare:CC
3702 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3703 (match_operand:SI 2 "const_int_operand" ""))
3704 (match_operand:SI 3 "mask_operand" ""))
3705 (const_int 0)))
3706 (clobber (match_scratch:SI 4 ""))]
3707 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3708 [(set (match_dup 4)
3709 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3710 (match_dup 3)))
3711 (set (match_dup 0)
3712 (compare:CC (match_dup 4)
3713 (const_int 0)))]
3714 "")
3715
3716 (define_insn ""
3717 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3718 (compare:CC
3719 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3720 (match_operand:SI 2 "const_int_operand" "i,i"))
3721 (match_operand:SI 3 "mask_operand" "n,n"))
3722 (const_int 0)))
3723 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3724 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3725 "includes_lshift_p (operands[2], operands[3])"
3726 "@
3727 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3728 #"
3729 [(set_attr "type" "delayed_compare")
3730 (set_attr "length" "4,8")])
3731
3732 (define_split
3733 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3734 (compare:CC
3735 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3736 (match_operand:SI 2 "const_int_operand" ""))
3737 (match_operand:SI 3 "mask_operand" ""))
3738 (const_int 0)))
3739 (set (match_operand:SI 0 "gpc_reg_operand" "")
3740 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3741 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3742 [(set (match_dup 0)
3743 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3744 (set (match_dup 4)
3745 (compare:CC (match_dup 0)
3746 (const_int 0)))]
3747 "")
3748
3749 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3750 ;; "sli x,x,0".
3751 (define_expand "lshrsi3"
3752 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3753 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3754 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3755 ""
3756 "
3757 {
3758 if (TARGET_POWER)
3759 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3760 else
3761 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3762 DONE;
3763 }")
3764
3765 (define_insn "lshrsi3_power"
3766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3767 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3768 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3769 (clobber (match_scratch:SI 3 "=q,X,X"))]
3770 "TARGET_POWER"
3771 "@
3772 sre %0,%1,%2
3773 mr %0,%1
3774 {s%A2i|s%A2wi} %0,%1,%h2")
3775
3776 (define_insn "lshrsi3_no_power"
3777 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3778 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3779 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3780 "! TARGET_POWER"
3781 "@
3782 mr %0,%1
3783 {sr|srw}%I2 %0,%1,%h2")
3784
3785 (define_insn ""
3786 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3787 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3788 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3789 (const_int 0)))
3790 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3791 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3792 "TARGET_POWER"
3793 "@
3794 sre. %3,%1,%2
3795 mr. %1,%1
3796 {s%A2i.|s%A2wi.} %3,%1,%h2
3797 #
3798 #
3799 #"
3800 [(set_attr "type" "delayed_compare")
3801 (set_attr "length" "4,4,4,8,8,8")])
3802
3803 (define_split
3804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3805 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3806 (match_operand:SI 2 "reg_or_cint_operand" ""))
3807 (const_int 0)))
3808 (clobber (match_scratch:SI 3 ""))
3809 (clobber (match_scratch:SI 4 ""))]
3810 "TARGET_POWER && reload_completed"
3811 [(parallel [(set (match_dup 3)
3812 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3813 (clobber (match_dup 4))])
3814 (set (match_dup 0)
3815 (compare:CC (match_dup 3)
3816 (const_int 0)))]
3817 "")
3818
3819 (define_insn ""
3820 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3821 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3822 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3823 (const_int 0)))
3824 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3825 "! TARGET_POWER && ! TARGET_POWERPC64"
3826 "@
3827 mr. %1,%1
3828 {sr|srw}%I2. %3,%1,%h2
3829 #
3830 #"
3831 [(set_attr "type" "delayed_compare")
3832 (set_attr "length" "4,4,8,8")])
3833
3834 (define_split
3835 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3836 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3837 (match_operand:SI 2 "reg_or_cint_operand" ""))
3838 (const_int 0)))
3839 (clobber (match_scratch:SI 3 ""))]
3840 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3841 [(set (match_dup 3)
3842 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3843 (set (match_dup 0)
3844 (compare:CC (match_dup 3)
3845 (const_int 0)))]
3846 "")
3847
3848 (define_insn ""
3849 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3850 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3851 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3852 (const_int 0)))
3853 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3854 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3855 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3856 "TARGET_POWER"
3857 "@
3858 sre. %0,%1,%2
3859 mr. %0,%1
3860 {s%A2i.|s%A2wi.} %0,%1,%h2
3861 #
3862 #
3863 #"
3864 [(set_attr "type" "delayed_compare")
3865 (set_attr "length" "4,4,4,8,8,8")])
3866
3867 (define_split
3868 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3869 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3870 (match_operand:SI 2 "reg_or_cint_operand" ""))
3871 (const_int 0)))
3872 (set (match_operand:SI 0 "gpc_reg_operand" "")
3873 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3874 (clobber (match_scratch:SI 4 ""))]
3875 "TARGET_POWER && reload_completed"
3876 [(parallel [(set (match_dup 0)
3877 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3878 (clobber (match_dup 4))])
3879 (set (match_dup 3)
3880 (compare:CC (match_dup 0)
3881 (const_int 0)))]
3882 "")
3883
3884 (define_insn ""
3885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3888 (const_int 0)))
3889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3890 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3891 "! TARGET_POWER && ! TARGET_POWERPC64"
3892 "@
3893 mr. %0,%1
3894 {sr|srw}%I2. %0,%1,%h2
3895 #
3896 #"
3897 [(set_attr "type" "delayed_compare")
3898 (set_attr "length" "4,4,8,8")])
3899
3900 (define_split
3901 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3902 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3903 (match_operand:SI 2 "reg_or_cint_operand" ""))
3904 (const_int 0)))
3905 (set (match_operand:SI 0 "gpc_reg_operand" "")
3906 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3907 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3908 [(set (match_dup 0)
3909 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3910 (set (match_dup 3)
3911 (compare:CC (match_dup 0)
3912 (const_int 0)))]
3913 "")
3914
3915 (define_insn ""
3916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3917 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3918 (match_operand:SI 2 "const_int_operand" "i"))
3919 (match_operand:SI 3 "mask_operand" "n")))]
3920 "includes_rshift_p (operands[2], operands[3])"
3921 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3922
3923 (define_insn ""
3924 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3925 (compare:CC
3926 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3927 (match_operand:SI 2 "const_int_operand" "i,i"))
3928 (match_operand:SI 3 "mask_operand" "n,n"))
3929 (const_int 0)))
3930 (clobber (match_scratch:SI 4 "=r,r"))]
3931 "includes_rshift_p (operands[2], operands[3])"
3932 "@
3933 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3934 #"
3935 [(set_attr "type" "delayed_compare")
3936 (set_attr "length" "4,8")])
3937
3938 (define_split
3939 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3940 (compare:CC
3941 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3942 (match_operand:SI 2 "const_int_operand" ""))
3943 (match_operand:SI 3 "mask_operand" ""))
3944 (const_int 0)))
3945 (clobber (match_scratch:SI 4 ""))]
3946 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3947 [(set (match_dup 4)
3948 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3949 (match_dup 3)))
3950 (set (match_dup 0)
3951 (compare:CC (match_dup 4)
3952 (const_int 0)))]
3953 "")
3954
3955 (define_insn ""
3956 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3957 (compare:CC
3958 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3959 (match_operand:SI 2 "const_int_operand" "i,i"))
3960 (match_operand:SI 3 "mask_operand" "n,n"))
3961 (const_int 0)))
3962 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3963 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3964 "includes_rshift_p (operands[2], operands[3])"
3965 "@
3966 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3967 #"
3968 [(set_attr "type" "delayed_compare")
3969 (set_attr "length" "4,8")])
3970
3971 (define_split
3972 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3973 (compare:CC
3974 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3975 (match_operand:SI 2 "const_int_operand" ""))
3976 (match_operand:SI 3 "mask_operand" ""))
3977 (const_int 0)))
3978 (set (match_operand:SI 0 "gpc_reg_operand" "")
3979 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3980 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3981 [(set (match_dup 0)
3982 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3983 (set (match_dup 4)
3984 (compare:CC (match_dup 0)
3985 (const_int 0)))]
3986 "")
3987
3988 (define_insn ""
3989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3990 (zero_extend:SI
3991 (subreg:QI
3992 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3993 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
3994 "includes_rshift_p (operands[2], GEN_INT (255))"
3995 "{rlinm|rlwinm} %0,%1,%s2,0xff")
3996
3997 (define_insn ""
3998 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3999 (compare:CC
4000 (zero_extend:SI
4001 (subreg:QI
4002 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4003 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4004 (const_int 0)))
4005 (clobber (match_scratch:SI 3 "=r,r"))]
4006 "includes_rshift_p (operands[2], GEN_INT (255))"
4007 "@
4008 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4009 #"
4010 [(set_attr "type" "delayed_compare")
4011 (set_attr "length" "4,8")])
4012
4013 (define_split
4014 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4015 (compare:CC
4016 (zero_extend:SI
4017 (subreg:QI
4018 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4019 (match_operand:SI 2 "const_int_operand" "")) 0))
4020 (const_int 0)))
4021 (clobber (match_scratch:SI 3 ""))]
4022 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4023 [(set (match_dup 3)
4024 (zero_extend:SI (subreg:QI
4025 (lshiftrt:SI (match_dup 1)
4026 (match_dup 2)) 0)))
4027 (set (match_dup 0)
4028 (compare:CC (match_dup 3)
4029 (const_int 0)))]
4030 "")
4031
4032 (define_insn ""
4033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4034 (compare:CC
4035 (zero_extend:SI
4036 (subreg:QI
4037 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4038 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4039 (const_int 0)))
4040 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4041 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4042 "includes_rshift_p (operands[2], GEN_INT (255))"
4043 "@
4044 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4045 #"
4046 [(set_attr "type" "delayed_compare")
4047 (set_attr "length" "4,8")])
4048
4049 (define_split
4050 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4051 (compare:CC
4052 (zero_extend:SI
4053 (subreg:QI
4054 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4055 (match_operand:SI 2 "const_int_operand" "")) 0))
4056 (const_int 0)))
4057 (set (match_operand:SI 0 "gpc_reg_operand" "")
4058 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4059 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4060 [(set (match_dup 0)
4061 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4062 (set (match_dup 3)
4063 (compare:CC (match_dup 0)
4064 (const_int 0)))]
4065 "")
4066
4067 (define_insn ""
4068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4069 (zero_extend:SI
4070 (subreg:HI
4071 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4072 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4073 "includes_rshift_p (operands[2], GEN_INT (65535))"
4074 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4075
4076 (define_insn ""
4077 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4078 (compare:CC
4079 (zero_extend:SI
4080 (subreg:HI
4081 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4082 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4083 (const_int 0)))
4084 (clobber (match_scratch:SI 3 "=r,r"))]
4085 "includes_rshift_p (operands[2], GEN_INT (65535))"
4086 "@
4087 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4088 #"
4089 [(set_attr "type" "delayed_compare")
4090 (set_attr "length" "4,8")])
4091
4092 (define_split
4093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4094 (compare:CC
4095 (zero_extend:SI
4096 (subreg:HI
4097 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4098 (match_operand:SI 2 "const_int_operand" "")) 0))
4099 (const_int 0)))
4100 (clobber (match_scratch:SI 3 ""))]
4101 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4102 [(set (match_dup 3)
4103 (zero_extend:SI (subreg:HI
4104 (lshiftrt:SI (match_dup 1)
4105 (match_dup 2)) 0)))
4106 (set (match_dup 0)
4107 (compare:CC (match_dup 3)
4108 (const_int 0)))]
4109 "")
4110
4111 (define_insn ""
4112 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4113 (compare:CC
4114 (zero_extend:SI
4115 (subreg:HI
4116 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4117 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4118 (const_int 0)))
4119 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4120 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4121 "includes_rshift_p (operands[2], GEN_INT (65535))"
4122 "@
4123 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4124 #"
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4127
4128 (define_split
4129 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4130 (compare:CC
4131 (zero_extend:SI
4132 (subreg:HI
4133 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" "")) 0))
4135 (const_int 0)))
4136 (set (match_operand:SI 0 "gpc_reg_operand" "")
4137 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4138 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4139 [(set (match_dup 0)
4140 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4141 (set (match_dup 3)
4142 (compare:CC (match_dup 0)
4143 (const_int 0)))]
4144 "")
4145
4146 (define_insn ""
4147 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4148 (const_int 1)
4149 (match_operand:SI 1 "gpc_reg_operand" "r"))
4150 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4151 (const_int 31)))]
4152 "TARGET_POWER"
4153 "rrib %0,%1,%2")
4154
4155 (define_insn ""
4156 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4157 (const_int 1)
4158 (match_operand:SI 1 "gpc_reg_operand" "r"))
4159 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4160 (const_int 31)))]
4161 "TARGET_POWER"
4162 "rrib %0,%1,%2")
4163
4164 (define_insn ""
4165 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4166 (const_int 1)
4167 (match_operand:SI 1 "gpc_reg_operand" "r"))
4168 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4169 (const_int 1)
4170 (const_int 0)))]
4171 "TARGET_POWER"
4172 "rrib %0,%1,%2")
4173
4174 (define_expand "ashrsi3"
4175 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4176 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4177 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4178 ""
4179 "
4180 {
4181 if (TARGET_POWER)
4182 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4183 else
4184 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4185 DONE;
4186 }")
4187
4188 (define_insn "ashrsi3_power"
4189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4190 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4191 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4192 (clobber (match_scratch:SI 3 "=q,X"))]
4193 "TARGET_POWER"
4194 "@
4195 srea %0,%1,%2
4196 {srai|srawi} %0,%1,%h2")
4197
4198 (define_insn "ashrsi3_no_power"
4199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4200 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4201 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4202 "! TARGET_POWER"
4203 "{sra|sraw}%I2 %0,%1,%h2")
4204
4205 (define_insn ""
4206 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4207 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4208 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4209 (const_int 0)))
4210 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4211 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4212 "TARGET_POWER"
4213 "@
4214 srea. %3,%1,%2
4215 {srai.|srawi.} %3,%1,%h2
4216 #
4217 #"
4218 [(set_attr "type" "delayed_compare")
4219 (set_attr "length" "4,4,8,8")])
4220
4221 (define_split
4222 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4223 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4224 (match_operand:SI 2 "reg_or_cint_operand" ""))
4225 (const_int 0)))
4226 (clobber (match_scratch:SI 3 ""))
4227 (clobber (match_scratch:SI 4 ""))]
4228 "TARGET_POWER && reload_completed"
4229 [(parallel [(set (match_dup 3)
4230 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4231 (clobber (match_dup 4))])
4232 (set (match_dup 0)
4233 (compare:CC (match_dup 3)
4234 (const_int 0)))]
4235 "")
4236
4237 (define_insn ""
4238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4239 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4240 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4241 (const_int 0)))
4242 (clobber (match_scratch:SI 3 "=r,r"))]
4243 "! TARGET_POWER"
4244 "@
4245 {sra|sraw}%I2. %3,%1,%h2
4246 #"
4247 [(set_attr "type" "delayed_compare")
4248 (set_attr "length" "4,8")])
4249
4250 (define_split
4251 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4252 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4253 (match_operand:SI 2 "reg_or_cint_operand" ""))
4254 (const_int 0)))
4255 (clobber (match_scratch:SI 3 ""))]
4256 "! TARGET_POWER && reload_completed"
4257 [(set (match_dup 3)
4258 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4259 (set (match_dup 0)
4260 (compare:CC (match_dup 3)
4261 (const_int 0)))]
4262 "")
4263
4264 (define_insn ""
4265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4266 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4267 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4268 (const_int 0)))
4269 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4270 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4271 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4272 "TARGET_POWER"
4273 "@
4274 srea. %0,%1,%2
4275 {srai.|srawi.} %0,%1,%h2
4276 #
4277 #"
4278 [(set_attr "type" "delayed_compare")
4279 (set_attr "length" "4,4,8,8")])
4280
4281 (define_split
4282 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4283 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4284 (match_operand:SI 2 "reg_or_cint_operand" ""))
4285 (const_int 0)))
4286 (set (match_operand:SI 0 "gpc_reg_operand" "")
4287 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4288 (clobber (match_scratch:SI 4 ""))]
4289 "TARGET_POWER && reload_completed"
4290 [(parallel [(set (match_dup 0)
4291 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4292 (clobber (match_dup 4))])
4293 (set (match_dup 3)
4294 (compare:CC (match_dup 0)
4295 (const_int 0)))]
4296 "")
4297
4298 (define_insn ""
4299 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4300 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4301 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4302 (const_int 0)))
4303 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4304 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4305 "! TARGET_POWER"
4306 "@
4307 {sra|sraw}%I2. %0,%1,%h2
4308 #"
4309 [(set_attr "type" "delayed_compare")
4310 (set_attr "length" "4,8")])
4311 \f
4312 (define_split
4313 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4314 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4315 (match_operand:SI 2 "reg_or_cint_operand" ""))
4316 (const_int 0)))
4317 (set (match_operand:SI 0 "gpc_reg_operand" "")
4318 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4319 "! TARGET_POWER && reload_completed"
4320 [(set (match_dup 0)
4321 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4322 (set (match_dup 3)
4323 (compare:CC (match_dup 0)
4324 (const_int 0)))]
4325 "")
4326
4327 ;; Floating-point insns, excluding normal data motion.
4328 ;;
4329 ;; PowerPC has a full set of single-precision floating point instructions.
4330 ;;
4331 ;; For the POWER architecture, we pretend that we have both SFmode and
4332 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4333 ;; The only conversions we will do will be when storing to memory. In that
4334 ;; case, we will use the "frsp" instruction before storing.
4335 ;;
4336 ;; Note that when we store into a single-precision memory location, we need to
4337 ;; use the frsp insn first. If the register being stored isn't dead, we
4338 ;; need a scratch register for the frsp. But this is difficult when the store
4339 ;; is done by reload. It is not incorrect to do the frsp on the register in
4340 ;; this case, we just lose precision that we would have otherwise gotten but
4341 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4342
4343 (define_insn "extendsfdf2"
4344 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4345 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4346 "TARGET_HARD_FLOAT && TARGET_FPRS"
4347 "*
4348 {
4349 if (REGNO (operands[0]) == REGNO (operands[1]))
4350 return \"\";
4351 else
4352 return \"fmr %0,%1\";
4353 }"
4354 [(set_attr "type" "fp")])
4355
4356 (define_insn "truncdfsf2"
4357 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4358 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4359 "TARGET_HARD_FLOAT && TARGET_FPRS"
4360 "frsp %0,%1"
4361 [(set_attr "type" "fp")])
4362
4363 (define_insn "aux_truncdfsf2"
4364 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4365 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
4366 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4367 "frsp %0,%1"
4368 [(set_attr "type" "fp")])
4369
4370 (define_expand "negsf2"
4371 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4372 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4373 "TARGET_HARD_FLOAT"
4374 "")
4375
4376 (define_insn "*negsf2"
4377 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4378 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4379 "TARGET_HARD_FLOAT && TARGET_FPRS"
4380 "fneg %0,%1"
4381 [(set_attr "type" "fp")])
4382
4383 (define_expand "abssf2"
4384 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4385 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4386 "TARGET_HARD_FLOAT"
4387 "")
4388
4389 (define_insn "*abssf2"
4390 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4391 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4392 "TARGET_HARD_FLOAT && TARGET_FPRS"
4393 "fabs %0,%1"
4394 [(set_attr "type" "fp")])
4395
4396 (define_insn ""
4397 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4398 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4399 "TARGET_HARD_FLOAT && TARGET_FPRS"
4400 "fnabs %0,%1"
4401 [(set_attr "type" "fp")])
4402
4403 (define_expand "addsf3"
4404 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4405 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4406 (match_operand:SF 2 "gpc_reg_operand" "")))]
4407 "TARGET_HARD_FLOAT"
4408 "")
4409
4410 (define_insn ""
4411 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4412 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4413 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4414 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4415 "fadds %0,%1,%2"
4416 [(set_attr "type" "fp")])
4417
4418 (define_insn ""
4419 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4420 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4421 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4422 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4423 "{fa|fadd} %0,%1,%2"
4424 [(set_attr "type" "fp")])
4425
4426 (define_expand "subsf3"
4427 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4428 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4429 (match_operand:SF 2 "gpc_reg_operand" "")))]
4430 "TARGET_HARD_FLOAT"
4431 "")
4432
4433 (define_insn ""
4434 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4435 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4436 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4437 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4438 "fsubs %0,%1,%2"
4439 [(set_attr "type" "fp")])
4440
4441 (define_insn ""
4442 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4443 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4444 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4445 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4446 "{fs|fsub} %0,%1,%2"
4447 [(set_attr "type" "fp")])
4448
4449 (define_expand "mulsf3"
4450 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4451 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4452 (match_operand:SF 2 "gpc_reg_operand" "")))]
4453 "TARGET_HARD_FLOAT"
4454 "")
4455
4456 (define_insn ""
4457 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4458 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4459 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4460 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4461 "fmuls %0,%1,%2"
4462 [(set_attr "type" "fp")])
4463
4464 (define_insn ""
4465 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4466 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4467 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4468 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4469 "{fm|fmul} %0,%1,%2"
4470 [(set_attr "type" "dmul")])
4471
4472 (define_expand "divsf3"
4473 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4474 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4475 (match_operand:SF 2 "gpc_reg_operand" "")))]
4476 "TARGET_HARD_FLOAT"
4477 "")
4478
4479 (define_insn ""
4480 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4481 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4482 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4483 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4484 "fdivs %0,%1,%2"
4485 [(set_attr "type" "sdiv")])
4486
4487 (define_insn ""
4488 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4489 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4490 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4491 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4492 "{fd|fdiv} %0,%1,%2"
4493 [(set_attr "type" "ddiv")])
4494
4495 (define_insn ""
4496 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4497 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4498 (match_operand:SF 2 "gpc_reg_operand" "f"))
4499 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4500 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4501 "fmadds %0,%1,%2,%3"
4502 [(set_attr "type" "fp")])
4503
4504 (define_insn ""
4505 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4506 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4507 (match_operand:SF 2 "gpc_reg_operand" "f"))
4508 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4509 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4510 "{fma|fmadd} %0,%1,%2,%3"
4511 [(set_attr "type" "dmul")])
4512
4513 (define_insn ""
4514 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4515 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4516 (match_operand:SF 2 "gpc_reg_operand" "f"))
4517 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4518 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4519 "fmsubs %0,%1,%2,%3"
4520 [(set_attr "type" "fp")])
4521
4522 (define_insn ""
4523 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4524 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4525 (match_operand:SF 2 "gpc_reg_operand" "f"))
4526 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4527 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4528 "{fms|fmsub} %0,%1,%2,%3"
4529 [(set_attr "type" "dmul")])
4530
4531 (define_insn ""
4532 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4533 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4534 (match_operand:SF 2 "gpc_reg_operand" "f"))
4535 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4536 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4537 && HONOR_SIGNED_ZEROS (SFmode)"
4538 "fnmadds %0,%1,%2,%3"
4539 [(set_attr "type" "fp")])
4540
4541 (define_insn ""
4542 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4543 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4544 (match_operand:SF 2 "gpc_reg_operand" "f"))
4545 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4546 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4547 && ! HONOR_SIGNED_ZEROS (SFmode)"
4548 "fnmadds %0,%1,%2,%3"
4549 [(set_attr "type" "fp")])
4550
4551 (define_insn ""
4552 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4553 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4554 (match_operand:SF 2 "gpc_reg_operand" "f"))
4555 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4556 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4557 "{fnma|fnmadd} %0,%1,%2,%3"
4558 [(set_attr "type" "dmul")])
4559
4560 (define_insn ""
4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4563 (match_operand:SF 2 "gpc_reg_operand" "f"))
4564 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4565 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4566 && ! HONOR_SIGNED_ZEROS (SFmode)"
4567 "{fnma|fnmadd} %0,%1,%2,%3"
4568 [(set_attr "type" "dmul")])
4569
4570 (define_insn ""
4571 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4572 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4573 (match_operand:SF 2 "gpc_reg_operand" "f"))
4574 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4575 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4576 && HONOR_SIGNED_ZEROS (SFmode)"
4577 "fnmsubs %0,%1,%2,%3"
4578 [(set_attr "type" "fp")])
4579
4580 (define_insn ""
4581 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4582 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4583 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4584 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4585 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4586 && ! HONOR_SIGNED_ZEROS (SFmode)"
4587 "fnmsubs %0,%1,%2,%3"
4588 [(set_attr "type" "fp")])
4589
4590 (define_insn ""
4591 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4592 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4593 (match_operand:SF 2 "gpc_reg_operand" "f"))
4594 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4595 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4596 "{fnms|fnmsub} %0,%1,%2,%3"
4597 [(set_attr "type" "dmul")])
4598
4599 (define_insn ""
4600 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4601 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4602 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4603 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4604 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4605 && ! HONOR_SIGNED_ZEROS (SFmode)"
4606 "{fnms|fnmsub} %0,%1,%2,%3"
4607 [(set_attr "type" "fp")])
4608
4609 (define_expand "sqrtsf2"
4610 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4611 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4612 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4613 "")
4614
4615 (define_insn ""
4616 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4617 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4618 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4619 "fsqrts %0,%1"
4620 [(set_attr "type" "ssqrt")])
4621
4622 (define_insn ""
4623 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4624 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4625 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4626 "fsqrt %0,%1"
4627 [(set_attr "type" "dsqrt")])
4628
4629 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4630 ;; fsel instruction and some auxiliary computations. Then we just have a
4631 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4632 ;; combine.
4633 (define_expand "maxsf3"
4634 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4635 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4636 (match_operand:SF 2 "gpc_reg_operand" ""))
4637 (match_dup 1)
4638 (match_dup 2)))]
4639 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4640 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4641
4642 (define_expand "minsf3"
4643 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4644 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4645 (match_operand:SF 2 "gpc_reg_operand" ""))
4646 (match_dup 2)
4647 (match_dup 1)))]
4648 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4649 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4650
4651 (define_split
4652 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4653 (match_operator:SF 3 "min_max_operator"
4654 [(match_operand:SF 1 "gpc_reg_operand" "")
4655 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4656 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4657 [(const_int 0)]
4658 "
4659 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4660 operands[1], operands[2]);
4661 DONE;
4662 }")
4663
4664 (define_expand "movsicc"
4665 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4666 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4667 (match_operand:SI 2 "gpc_reg_operand" "")
4668 (match_operand:SI 3 "gpc_reg_operand" "")))]
4669 "TARGET_ISEL"
4670 "
4671 {
4672 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4673 DONE;
4674 else
4675 FAIL;
4676 }")
4677
4678 ;; We use the BASE_REGS for the isel input operands because, if rA is
4679 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4680 ;; because we may switch the operands and rB may end up being rA.
4681 ;;
4682 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4683 ;; leave out the mode in operand 4 and use one pattern, but reload can
4684 ;; change the mode underneath our feet and then gets confused trying
4685 ;; to reload the value.
4686 (define_insn "isel_signed"
4687 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4688 (if_then_else:SI
4689 (match_operator 1 "comparison_operator"
4690 [(match_operand:CC 4 "cc_reg_operand" "y")
4691 (const_int 0)])
4692 (match_operand:SI 2 "gpc_reg_operand" "b")
4693 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4694 "TARGET_ISEL"
4695 "*
4696 { return output_isel (operands); }"
4697 [(set_attr "length" "4")])
4698
4699 (define_insn "isel_unsigned"
4700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4701 (if_then_else:SI
4702 (match_operator 1 "comparison_operator"
4703 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4704 (const_int 0)])
4705 (match_operand:SI 2 "gpc_reg_operand" "b")
4706 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4707 "TARGET_ISEL"
4708 "*
4709 { return output_isel (operands); }"
4710 [(set_attr "length" "4")])
4711
4712 (define_expand "movsfcc"
4713 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4714 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4715 (match_operand:SF 2 "gpc_reg_operand" "")
4716 (match_operand:SF 3 "gpc_reg_operand" "")))]
4717 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4718 "
4719 {
4720 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4721 DONE;
4722 else
4723 FAIL;
4724 }")
4725
4726 (define_insn "*fselsfsf4"
4727 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4728 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4729 (match_operand:SF 4 "zero_fp_constant" "F"))
4730 (match_operand:SF 2 "gpc_reg_operand" "f")
4731 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4732 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4733 "fsel %0,%1,%2,%3"
4734 [(set_attr "type" "fp")])
4735
4736 (define_insn "*fseldfsf4"
4737 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4738 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4739 (match_operand:DF 4 "zero_fp_constant" "F"))
4740 (match_operand:SF 2 "gpc_reg_operand" "f")
4741 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4742 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4743 "fsel %0,%1,%2,%3"
4744 [(set_attr "type" "fp")])
4745
4746 (define_insn "negdf2"
4747 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4748 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4749 "TARGET_HARD_FLOAT && TARGET_FPRS"
4750 "fneg %0,%1"
4751 [(set_attr "type" "fp")])
4752
4753 (define_insn "absdf2"
4754 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4755 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4756 "TARGET_HARD_FLOAT && TARGET_FPRS"
4757 "fabs %0,%1"
4758 [(set_attr "type" "fp")])
4759
4760 (define_insn ""
4761 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4762 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4763 "TARGET_HARD_FLOAT && TARGET_FPRS"
4764 "fnabs %0,%1"
4765 [(set_attr "type" "fp")])
4766
4767 (define_insn "adddf3"
4768 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4769 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4770 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4771 "TARGET_HARD_FLOAT && TARGET_FPRS"
4772 "{fa|fadd} %0,%1,%2"
4773 [(set_attr "type" "fp")])
4774
4775 (define_insn "subdf3"
4776 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4777 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4778 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4779 "TARGET_HARD_FLOAT && TARGET_FPRS"
4780 "{fs|fsub} %0,%1,%2"
4781 [(set_attr "type" "fp")])
4782
4783 (define_insn "muldf3"
4784 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4785 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4786 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4787 "TARGET_HARD_FLOAT && TARGET_FPRS"
4788 "{fm|fmul} %0,%1,%2"
4789 [(set_attr "type" "dmul")])
4790
4791 (define_insn "divdf3"
4792 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4793 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4794 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4795 "TARGET_HARD_FLOAT && TARGET_FPRS"
4796 "{fd|fdiv} %0,%1,%2"
4797 [(set_attr "type" "ddiv")])
4798
4799 (define_insn ""
4800 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4801 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4802 (match_operand:DF 2 "gpc_reg_operand" "f"))
4803 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4804 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4805 "{fma|fmadd} %0,%1,%2,%3"
4806 [(set_attr "type" "dmul")])
4807
4808 (define_insn ""
4809 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4810 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4811 (match_operand:DF 2 "gpc_reg_operand" "f"))
4812 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4813 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4814 "{fms|fmsub} %0,%1,%2,%3"
4815 [(set_attr "type" "dmul")])
4816
4817 (define_insn ""
4818 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4819 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4820 (match_operand:DF 2 "gpc_reg_operand" "f"))
4821 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4822 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4823 && HONOR_SIGNED_ZEROS (DFmode)"
4824 "{fnma|fnmadd} %0,%1,%2,%3"
4825 [(set_attr "type" "dmul")])
4826
4827 (define_insn ""
4828 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4829 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4830 (match_operand:DF 2 "gpc_reg_operand" "f"))
4831 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4832 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4833 && ! HONOR_SIGNED_ZEROS (DFmode)"
4834 "{fnma|fnmadd} %0,%1,%2,%3"
4835 [(set_attr "type" "dmul")])
4836
4837 (define_insn ""
4838 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4839 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4840 (match_operand:DF 2 "gpc_reg_operand" "f"))
4841 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4842 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4843 && HONOR_SIGNED_ZEROS (DFmode)"
4844 "{fnms|fnmsub} %0,%1,%2,%3"
4845 [(set_attr "type" "dmul")])
4846
4847 (define_insn ""
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4849 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4850 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4851 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4852 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4853 && ! HONOR_SIGNED_ZEROS (DFmode)"
4854 "{fnms|fnmsub} %0,%1,%2,%3"
4855 [(set_attr "type" "dmul")])
4856
4857 (define_insn "sqrtdf2"
4858 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4859 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4860 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4861 "fsqrt %0,%1"
4862 [(set_attr "type" "dsqrt")])
4863
4864 ;; The conditional move instructions allow us to perform max and min
4865 ;; operations even when
4866
4867 (define_expand "maxdf3"
4868 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4869 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4870 (match_operand:DF 2 "gpc_reg_operand" ""))
4871 (match_dup 1)
4872 (match_dup 2)))]
4873 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4874 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4875
4876 (define_expand "mindf3"
4877 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4878 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4879 (match_operand:DF 2 "gpc_reg_operand" ""))
4880 (match_dup 2)
4881 (match_dup 1)))]
4882 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4883 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4884
4885 (define_split
4886 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4887 (match_operator:DF 3 "min_max_operator"
4888 [(match_operand:DF 1 "gpc_reg_operand" "")
4889 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4890 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4891 [(const_int 0)]
4892 "
4893 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4894 operands[1], operands[2]);
4895 DONE;
4896 }")
4897
4898 (define_expand "movdfcc"
4899 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4900 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4901 (match_operand:DF 2 "gpc_reg_operand" "")
4902 (match_operand:DF 3 "gpc_reg_operand" "")))]
4903 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4904 "
4905 {
4906 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4907 DONE;
4908 else
4909 FAIL;
4910 }")
4911
4912 (define_insn "*fseldfdf4"
4913 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4914 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4915 (match_operand:DF 4 "zero_fp_constant" "F"))
4916 (match_operand:DF 2 "gpc_reg_operand" "f")
4917 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4918 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4919 "fsel %0,%1,%2,%3"
4920 [(set_attr "type" "fp")])
4921
4922 (define_insn "*fselsfdf4"
4923 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4924 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4925 (match_operand:SF 4 "zero_fp_constant" "F"))
4926 (match_operand:DF 2 "gpc_reg_operand" "f")
4927 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4928 "TARGET_PPC_GFXOPT"
4929 "fsel %0,%1,%2,%3"
4930 [(set_attr "type" "fp")])
4931 \f
4932 ;; Conversions to and from floating-point.
4933
4934 (define_expand "fixunssfsi2"
4935 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4936 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))]
4937 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4938 "")
4939
4940 (define_expand "fix_truncsfsi2"
4941 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4942 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4943 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4944 "")
4945
4946 ; For each of these conversions, there is a define_expand, a define_insn
4947 ; with a '#' template, and a define_split (with C code). The idea is
4948 ; to allow constant folding with the template of the define_insn,
4949 ; then to have the insns split later (between sched1 and final).
4950
4951 (define_expand "floatsidf2"
4952 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4953 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4954 (use (match_dup 2))
4955 (use (match_dup 3))
4956 (clobber (match_dup 4))
4957 (clobber (match_dup 5))
4958 (clobber (match_dup 6))])]
4959 "TARGET_HARD_FLOAT && TARGET_FPRS"
4960 "
4961 {
4962 if (TARGET_POWERPC64)
4963 {
4964 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4965 rtx t1 = gen_reg_rtx (DImode);
4966 rtx t2 = gen_reg_rtx (DImode);
4967 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4968 DONE;
4969 }
4970
4971 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
4972 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
4973 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
4974 operands[5] = gen_reg_rtx (DFmode);
4975 operands[6] = gen_reg_rtx (SImode);
4976 }")
4977
4978 (define_insn "*floatsidf2_internal"
4979 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
4980 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
4981 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
4982 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
4983 (clobber (match_operand:DF 4 "memory_operand" "=o"))
4984 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
4985 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
4986 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
4987 "#"
4988 [(set_attr "length" "24")])
4989
4990 (define_split
4991 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4992 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4993 (use (match_operand:SI 2 "gpc_reg_operand" ""))
4994 (use (match_operand:DF 3 "gpc_reg_operand" ""))
4995 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
4996 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
4997 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
4998 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
4999 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5000 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5001 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5002 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5003 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5004 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5005 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5006 "
5007 {
5008 rtx lowword, highword;
5009 if (GET_CODE (operands[4]) != MEM)
5010 abort();
5011 highword = XEXP (operands[4], 0);
5012 lowword = plus_constant (highword, 4);
5013 if (! WORDS_BIG_ENDIAN)
5014 {
5015 rtx tmp;
5016 tmp = highword; highword = lowword; lowword = tmp;
5017 }
5018
5019 emit_insn (gen_xorsi3 (operands[6], operands[1],
5020 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5021 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5022 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5023 emit_move_insn (operands[5], operands[4]);
5024 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5025 DONE;
5026 }")
5027
5028 (define_expand "floatunssisf2"
5029 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5030 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5031 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5032 "")
5033
5034 (define_expand "floatunssidf2"
5035 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5036 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5037 (use (match_dup 2))
5038 (use (match_dup 3))
5039 (clobber (match_dup 4))
5040 (clobber (match_dup 5))])]
5041 "TARGET_HARD_FLOAT && TARGET_FPRS"
5042 "
5043 {
5044 if (TARGET_POWERPC64)
5045 {
5046 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5047 rtx t1 = gen_reg_rtx (DImode);
5048 rtx t2 = gen_reg_rtx (DImode);
5049 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5050 t1, t2));
5051 DONE;
5052 }
5053
5054 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5055 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5056 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5057 operands[5] = gen_reg_rtx (DFmode);
5058 }")
5059
5060 (define_insn "*floatunssidf2_internal"
5061 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5062 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5063 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5064 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5065 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5066 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5067 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5068 "#"
5069 [(set_attr "length" "20")])
5070
5071 (define_split
5072 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5073 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5074 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5075 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5076 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5077 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5078 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5079 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5080 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5081 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5082 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5083 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5084 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5085 "
5086 {
5087 rtx lowword, highword;
5088 if (GET_CODE (operands[4]) != MEM)
5089 abort();
5090 highword = XEXP (operands[4], 0);
5091 lowword = plus_constant (highword, 4);
5092 if (! WORDS_BIG_ENDIAN)
5093 {
5094 rtx tmp;
5095 tmp = highword; highword = lowword; lowword = tmp;
5096 }
5097
5098 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5099 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5100 emit_move_insn (operands[5], operands[4]);
5101 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5102 DONE;
5103 }")
5104
5105 (define_expand "fix_truncdfsi2"
5106 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5107 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5108 (clobber (match_dup 2))
5109 (clobber (match_dup 3))])]
5110 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5111 "
5112 {
5113 operands[2] = gen_reg_rtx (DImode);
5114 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5115 }")
5116
5117 (define_insn "*fix_truncdfsi2_internal"
5118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5119 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5120 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5121 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5122 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5123 "#"
5124 [(set_attr "length" "16")])
5125
5126 (define_split
5127 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5128 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5129 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5130 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5131 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5132 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5133 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5134 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5135 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5136 "
5137 {
5138 rtx lowword;
5139 if (GET_CODE (operands[3]) != MEM)
5140 abort();
5141 lowword = XEXP (operands[3], 0);
5142 if (WORDS_BIG_ENDIAN)
5143 lowword = plus_constant (lowword, 4);
5144
5145 emit_insn (gen_fctiwz (operands[2], operands[1]));
5146 emit_move_insn (operands[3], operands[2]);
5147 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5148 DONE;
5149 }")
5150
5151 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5152 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5153 ; because the first makes it clear that operand 0 is not live
5154 ; before the instruction.
5155 (define_insn "fctiwz"
5156 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5157 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
5158 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5159 "{fcirz|fctiwz} %0,%1"
5160 [(set_attr "type" "fp")])
5161
5162 (define_expand "floatsisf2"
5163 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5164 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5165 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5166 "")
5167
5168 (define_insn "floatdidf2"
5169 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5170 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5171 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5172 "fcfid %0,%1"
5173 [(set_attr "type" "fp")])
5174
5175 (define_insn_and_split "floatsidf_ppc64"
5176 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5177 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5178 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5179 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5180 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5181 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5182 "#"
5183 ""
5184 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5185 (set (match_dup 2) (match_dup 3))
5186 (set (match_dup 4) (match_dup 2))
5187 (set (match_dup 0) (float:DF (match_dup 4)))]
5188 "")
5189
5190 (define_insn_and_split "floatunssidf_ppc64"
5191 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5192 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5193 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5194 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5195 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5196 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5197 "#"
5198 ""
5199 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5200 (set (match_dup 2) (match_dup 3))
5201 (set (match_dup 4) (match_dup 2))
5202 (set (match_dup 0) (float:DF (match_dup 4)))]
5203 "")
5204
5205 (define_insn "fix_truncdfdi2"
5206 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5207 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5208 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5209 "fctidz %0,%1"
5210 [(set_attr "type" "fp")])
5211
5212 (define_expand "floatdisf2"
5213 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5214 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5215 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5216 "
5217 {
5218 if (!flag_unsafe_math_optimizations)
5219 {
5220 rtx label = gen_label_rtx ();
5221 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5222 emit_label (label);
5223 }
5224 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5225 DONE;
5226 }")
5227
5228 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5229 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5230 ;; from double rounding.
5231 (define_insn_and_split "floatdisf2_internal1"
5232 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5233 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5234 (clobber (match_scratch:DF 2 "=f"))]
5235 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5236 "#"
5237 "&& reload_completed"
5238 [(set (match_dup 2)
5239 (float:DF (match_dup 1)))
5240 (set (match_dup 0)
5241 (float_truncate:SF (match_dup 2)))]
5242 "")
5243
5244 ;; Twiddles bits to avoid double rounding.
5245 ;; Bits that might be truncated when converting to DFmode are replaced
5246 ;; by a bit that won't be lost at that stage, but is below the SFmode
5247 ;; rounding position.
5248 (define_expand "floatdisf2_internal2"
5249 [(parallel [(set (match_dup 4)
5250 (compare:CC (and:DI (match_operand:DI 0 "" "")
5251 (const_int 2047))
5252 (const_int 0)))
5253 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5254 (clobber (match_scratch:CC 7 ""))])
5255 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5256 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5257 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5258 (label_ref (match_operand:DI 1 "" ""))
5259 (pc)))
5260 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5261 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5262 (label_ref (match_dup 1))
5263 (pc)))
5264 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5265 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5266 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5267 "
5268 {
5269 operands[2] = gen_reg_rtx (DImode);
5270 operands[3] = gen_reg_rtx (DImode);
5271 operands[4] = gen_reg_rtx (CCmode);
5272 operands[5] = gen_reg_rtx (CCUNSmode);
5273 }")
5274 \f
5275 ;; Define the DImode operations that can be done in a small number
5276 ;; of instructions. The & constraints are to prevent the register
5277 ;; allocator from allocating registers that overlap with the inputs
5278 ;; (for example, having an input in 7,8 and an output in 6,7). We
5279 ;; also allow for the output being the same as one of the inputs.
5280
5281 (define_insn "*adddi3_noppc64"
5282 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5283 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5284 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5285 "! TARGET_POWERPC64"
5286 "*
5287 {
5288 if (WORDS_BIG_ENDIAN)
5289 return (GET_CODE (operands[2])) != CONST_INT
5290 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5291 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5292 else
5293 return (GET_CODE (operands[2])) != CONST_INT
5294 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5295 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5296 }"
5297 [(set_attr "length" "8")])
5298
5299 (define_insn "*subdi3_noppc64"
5300 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5301 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5302 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5303 "! TARGET_POWERPC64"
5304 "*
5305 {
5306 if (WORDS_BIG_ENDIAN)
5307 return (GET_CODE (operands[1]) != CONST_INT)
5308 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5309 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5310 else
5311 return (GET_CODE (operands[1]) != CONST_INT)
5312 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5313 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5314 }"
5315 [(set_attr "length" "8")])
5316
5317 (define_insn "*negdi2_noppc64"
5318 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5319 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5320 "! TARGET_POWERPC64"
5321 "*
5322 {
5323 return (WORDS_BIG_ENDIAN)
5324 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5325 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5326 }"
5327 [(set_attr "length" "8")])
5328
5329 (define_expand "mulsidi3"
5330 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5331 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5332 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5333 "! TARGET_POWERPC64"
5334 "
5335 {
5336 if (! TARGET_POWER && ! TARGET_POWERPC)
5337 {
5338 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5339 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5340 emit_insn (gen_mull_call ());
5341 if (WORDS_BIG_ENDIAN)
5342 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5343 else
5344 {
5345 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5346 gen_rtx_REG (SImode, 3));
5347 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5348 gen_rtx_REG (SImode, 4));
5349 }
5350 DONE;
5351 }
5352 else if (TARGET_POWER)
5353 {
5354 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5355 DONE;
5356 }
5357 }")
5358
5359 (define_insn "mulsidi3_mq"
5360 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5361 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5362 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5363 (clobber (match_scratch:SI 3 "=q"))]
5364 "TARGET_POWER"
5365 "mul %0,%1,%2\;mfmq %L0"
5366 [(set_attr "type" "imul")
5367 (set_attr "length" "8")])
5368
5369 (define_insn "*mulsidi3_no_mq"
5370 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5371 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5372 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5373 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5374 "*
5375 {
5376 return (WORDS_BIG_ENDIAN)
5377 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5378 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5379 }"
5380 [(set_attr "type" "imul")
5381 (set_attr "length" "8")])
5382
5383 (define_split
5384 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5385 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5386 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5387 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5388 [(set (match_dup 3)
5389 (truncate:SI
5390 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5391 (sign_extend:DI (match_dup 2)))
5392 (const_int 32))))
5393 (set (match_dup 4)
5394 (mult:SI (match_dup 1)
5395 (match_dup 2)))]
5396 "
5397 {
5398 int endian = (WORDS_BIG_ENDIAN == 0);
5399 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5400 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5401 }")
5402
5403 (define_expand "umulsidi3"
5404 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5405 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5406 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5407 "TARGET_POWERPC && ! TARGET_POWERPC64"
5408 "
5409 {
5410 if (TARGET_POWER)
5411 {
5412 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5413 DONE;
5414 }
5415 }")
5416
5417 (define_insn "umulsidi3_mq"
5418 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5419 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5420 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5421 (clobber (match_scratch:SI 3 "=q"))]
5422 "TARGET_POWERPC && TARGET_POWER"
5423 "*
5424 {
5425 return (WORDS_BIG_ENDIAN)
5426 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5427 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5428 }"
5429 [(set_attr "type" "imul")
5430 (set_attr "length" "8")])
5431
5432 (define_insn "*umulsidi3_no_mq"
5433 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5434 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5435 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5436 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5437 "*
5438 {
5439 return (WORDS_BIG_ENDIAN)
5440 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5441 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5442 }"
5443 [(set_attr "type" "imul")
5444 (set_attr "length" "8")])
5445
5446 (define_split
5447 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5448 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5449 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5450 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5451 [(set (match_dup 3)
5452 (truncate:SI
5453 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5454 (zero_extend:DI (match_dup 2)))
5455 (const_int 32))))
5456 (set (match_dup 4)
5457 (mult:SI (match_dup 1)
5458 (match_dup 2)))]
5459 "
5460 {
5461 int endian = (WORDS_BIG_ENDIAN == 0);
5462 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5463 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5464 }")
5465
5466 (define_expand "smulsi3_highpart"
5467 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5468 (truncate:SI
5469 (lshiftrt:DI (mult:DI (sign_extend:DI
5470 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5471 (sign_extend:DI
5472 (match_operand:SI 2 "gpc_reg_operand" "r")))
5473 (const_int 32))))]
5474 ""
5475 "
5476 {
5477 if (! TARGET_POWER && ! TARGET_POWERPC)
5478 {
5479 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5480 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5481 emit_insn (gen_mulh_call ());
5482 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5483 DONE;
5484 }
5485 else if (TARGET_POWER)
5486 {
5487 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5488 DONE;
5489 }
5490 }")
5491
5492 (define_insn "smulsi3_highpart_mq"
5493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5494 (truncate:SI
5495 (lshiftrt:DI (mult:DI (sign_extend:DI
5496 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5497 (sign_extend:DI
5498 (match_operand:SI 2 "gpc_reg_operand" "r")))
5499 (const_int 32))))
5500 (clobber (match_scratch:SI 3 "=q"))]
5501 "TARGET_POWER"
5502 "mul %0,%1,%2"
5503 [(set_attr "type" "imul")])
5504
5505 (define_insn "*smulsi3_highpart_no_mq"
5506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5507 (truncate:SI
5508 (lshiftrt:DI (mult:DI (sign_extend:DI
5509 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5510 (sign_extend:DI
5511 (match_operand:SI 2 "gpc_reg_operand" "r")))
5512 (const_int 32))))]
5513 "TARGET_POWERPC && ! TARGET_POWER"
5514 "mulhw %0,%1,%2"
5515 [(set_attr "type" "imul")])
5516
5517 (define_expand "umulsi3_highpart"
5518 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5519 (truncate:SI
5520 (lshiftrt:DI (mult:DI (zero_extend:DI
5521 (match_operand:SI 1 "gpc_reg_operand" ""))
5522 (zero_extend:DI
5523 (match_operand:SI 2 "gpc_reg_operand" "")))
5524 (const_int 32))))]
5525 "TARGET_POWERPC"
5526 "
5527 {
5528 if (TARGET_POWER)
5529 {
5530 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5531 DONE;
5532 }
5533 }")
5534
5535 (define_insn "umulsi3_highpart_mq"
5536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5537 (truncate:SI
5538 (lshiftrt:DI (mult:DI (zero_extend:DI
5539 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5540 (zero_extend:DI
5541 (match_operand:SI 2 "gpc_reg_operand" "r")))
5542 (const_int 32))))
5543 (clobber (match_scratch:SI 3 "=q"))]
5544 "TARGET_POWERPC && TARGET_POWER"
5545 "mulhwu %0,%1,%2"
5546 [(set_attr "type" "imul")])
5547
5548 (define_insn "*umulsi3_highpart_no_mq"
5549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5550 (truncate:SI
5551 (lshiftrt:DI (mult:DI (zero_extend:DI
5552 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5553 (zero_extend:DI
5554 (match_operand:SI 2 "gpc_reg_operand" "r")))
5555 (const_int 32))))]
5556 "TARGET_POWERPC && ! TARGET_POWER"
5557 "mulhwu %0,%1,%2"
5558 [(set_attr "type" "imul")])
5559
5560 ;; If operands 0 and 2 are in the same register, we have a problem. But
5561 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5562 ;; why we have the strange constraints below.
5563 (define_insn "ashldi3_power"
5564 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5565 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5566 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5567 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5568 "TARGET_POWER"
5569 "@
5570 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5571 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5572 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5573 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5574 [(set_attr "length" "8")])
5575
5576 (define_insn "lshrdi3_power"
5577 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5578 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5579 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5580 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5581 "TARGET_POWER"
5582 "@
5583 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5584 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5585 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5586 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5587 [(set_attr "length" "8")])
5588
5589 ;; Shift by a variable amount is too complex to be worth open-coding. We
5590 ;; just handle shifts by constants.
5591 (define_insn "ashrdi3_power"
5592 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5593 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5594 (match_operand:SI 2 "const_int_operand" "M,i")))
5595 (clobber (match_scratch:SI 3 "=X,q"))]
5596 "TARGET_POWER"
5597 "@
5598 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5599 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5600 [(set_attr "length" "8")])
5601
5602 (define_insn "ashrdi3_no_power"
5603 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5604 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5605 (match_operand:SI 2 "const_int_operand" "M,i")))]
5606 "TARGET_32BIT && !TARGET_POWER"
5607 "@
5608 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5609 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5610 [(set_attr "length" "8,12")])
5611 \f
5612 ;; PowerPC64 DImode operations.
5613
5614 (define_expand "adddi3"
5615 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5616 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5617 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5618 ""
5619 "
5620 {
5621 if (! TARGET_POWERPC64)
5622 {
5623 if (non_short_cint_operand (operands[2], DImode))
5624 FAIL;
5625 }
5626 else
5627 if (GET_CODE (operands[2]) == CONST_INT
5628 && ! add_operand (operands[2], DImode))
5629 {
5630 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5631 ? operands[0] : gen_reg_rtx (DImode));
5632
5633 HOST_WIDE_INT val = INTVAL (operands[2]);
5634 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5635 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5636
5637 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5638 FAIL;
5639
5640 /* The ordering here is important for the prolog expander.
5641 When space is allocated from the stack, adding 'low' first may
5642 produce a temporary deallocation (which would be bad). */
5643 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5644 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5645 DONE;
5646 }
5647 }")
5648
5649 ;; Discourage ai/addic because of carry but provide it in an alternative
5650 ;; allowing register zero as source.
5651
5652 (define_insn "*adddi3_internal1"
5653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5654 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5655 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5656 "TARGET_POWERPC64"
5657 "@
5658 add %0,%1,%2
5659 addi %0,%1,%2
5660 addic %0,%1,%2
5661 addis %0,%1,%v2")
5662
5663 (define_insn "*adddi3_internal2"
5664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5665 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5666 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5667 (const_int 0)))
5668 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5669 "TARGET_POWERPC64"
5670 "@
5671 add. %3,%1,%2
5672 addic. %3,%1,%2
5673 #
5674 #"
5675 [(set_attr "type" "fast_compare,compare,compare,compare")
5676 (set_attr "length" "4,4,8,8")])
5677
5678 (define_split
5679 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5680 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5681 (match_operand:DI 2 "reg_or_short_operand" ""))
5682 (const_int 0)))
5683 (clobber (match_scratch:DI 3 ""))]
5684 "TARGET_POWERPC64 && reload_completed"
5685 [(set (match_dup 3)
5686 (plus:DI (match_dup 1) (match_dup 2)))
5687 (set (match_dup 0)
5688 (compare:CC (match_dup 3)
5689 (const_int 0)))]
5690 "")
5691
5692 (define_insn "*adddi3_internal3"
5693 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5694 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5695 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5696 (const_int 0)))
5697 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5698 (plus:DI (match_dup 1) (match_dup 2)))]
5699 "TARGET_POWERPC64"
5700 "@
5701 add. %0,%1,%2
5702 addic. %0,%1,%2
5703 #
5704 #"
5705 [(set_attr "type" "fast_compare,compare,compare,compare")
5706 (set_attr "length" "4,4,8,8")])
5707
5708 (define_split
5709 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5710 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5711 (match_operand:DI 2 "reg_or_short_operand" ""))
5712 (const_int 0)))
5713 (set (match_operand:DI 0 "gpc_reg_operand" "")
5714 (plus:DI (match_dup 1) (match_dup 2)))]
5715 "TARGET_POWERPC64 && reload_completed"
5716 [(set (match_dup 0)
5717 (plus:DI (match_dup 1) (match_dup 2)))
5718 (set (match_dup 3)
5719 (compare:CC (match_dup 0)
5720 (const_int 0)))]
5721 "")
5722
5723 ;; Split an add that we can't do in one insn into two insns, each of which
5724 ;; does one 16-bit part. This is used by combine. Note that the low-order
5725 ;; add should be last in case the result gets used in an address.
5726
5727 (define_split
5728 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5729 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5730 (match_operand:DI 2 "non_add_cint_operand" "")))]
5731 "TARGET_POWERPC64"
5732 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5733 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5734 "
5735 {
5736 HOST_WIDE_INT val = INTVAL (operands[2]);
5737 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5738 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5739
5740 operands[4] = GEN_INT (low);
5741 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5742 operands[3] = GEN_INT (rest);
5743 else if (! no_new_pseudos)
5744 {
5745 operands[3] = gen_reg_rtx (DImode);
5746 emit_move_insn (operands[3], operands[2]);
5747 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5748 DONE;
5749 }
5750 else
5751 FAIL;
5752 }")
5753
5754 (define_insn "one_cmpldi2"
5755 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5756 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5757 "TARGET_POWERPC64"
5758 "nor %0,%1,%1")
5759
5760 (define_insn ""
5761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5762 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5763 (const_int 0)))
5764 (clobber (match_scratch:DI 2 "=r,r"))]
5765 "TARGET_POWERPC64"
5766 "@
5767 nor. %2,%1,%1
5768 #"
5769 [(set_attr "type" "compare")
5770 (set_attr "length" "4,8")])
5771
5772 (define_split
5773 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5774 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5775 (const_int 0)))
5776 (clobber (match_scratch:DI 2 ""))]
5777 "TARGET_POWERPC64 && reload_completed"
5778 [(set (match_dup 2)
5779 (not:DI (match_dup 1)))
5780 (set (match_dup 0)
5781 (compare:CC (match_dup 2)
5782 (const_int 0)))]
5783 "")
5784
5785 (define_insn ""
5786 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5787 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5788 (const_int 0)))
5789 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5790 (not:DI (match_dup 1)))]
5791 "TARGET_POWERPC64"
5792 "@
5793 nor. %0,%1,%1
5794 #"
5795 [(set_attr "type" "compare")
5796 (set_attr "length" "4,8")])
5797
5798 (define_split
5799 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5800 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5801 (const_int 0)))
5802 (set (match_operand:DI 0 "gpc_reg_operand" "")
5803 (not:DI (match_dup 1)))]
5804 "TARGET_POWERPC64 && reload_completed"
5805 [(set (match_dup 0)
5806 (not:DI (match_dup 1)))
5807 (set (match_dup 2)
5808 (compare:CC (match_dup 0)
5809 (const_int 0)))]
5810 "")
5811
5812 (define_insn ""
5813 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5814 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5815 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5816 "TARGET_POWERPC64"
5817 "@
5818 subf %0,%2,%1
5819 subfic %0,%2,%1")
5820
5821 (define_insn ""
5822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5823 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5824 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5825 (const_int 0)))
5826 (clobber (match_scratch:DI 3 "=r,r"))]
5827 "TARGET_POWERPC64"
5828 "@
5829 subf. %3,%2,%1
5830 #"
5831 [(set_attr "type" "fast_compare")
5832 (set_attr "length" "4,8")])
5833
5834 (define_split
5835 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5836 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5837 (match_operand:DI 2 "gpc_reg_operand" ""))
5838 (const_int 0)))
5839 (clobber (match_scratch:DI 3 ""))]
5840 "TARGET_POWERPC64 && reload_completed"
5841 [(set (match_dup 3)
5842 (minus:DI (match_dup 1) (match_dup 2)))
5843 (set (match_dup 0)
5844 (compare:CC (match_dup 3)
5845 (const_int 0)))]
5846 "")
5847
5848 (define_insn ""
5849 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5850 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5851 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5852 (const_int 0)))
5853 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5854 (minus:DI (match_dup 1) (match_dup 2)))]
5855 "TARGET_POWERPC64"
5856 "@
5857 subf. %0,%2,%1
5858 #"
5859 [(set_attr "type" "fast_compare")
5860 (set_attr "length" "4,8")])
5861
5862 (define_split
5863 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5864 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5865 (match_operand:DI 2 "gpc_reg_operand" ""))
5866 (const_int 0)))
5867 (set (match_operand:DI 0 "gpc_reg_operand" "")
5868 (minus:DI (match_dup 1) (match_dup 2)))]
5869 "TARGET_POWERPC64 && reload_completed"
5870 [(set (match_dup 0)
5871 (minus:DI (match_dup 1) (match_dup 2)))
5872 (set (match_dup 3)
5873 (compare:CC (match_dup 0)
5874 (const_int 0)))]
5875 "")
5876
5877 (define_expand "subdi3"
5878 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5879 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5880 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5881 ""
5882 "
5883 {
5884 if (GET_CODE (operands[2]) == CONST_INT)
5885 {
5886 emit_insn (gen_adddi3 (operands[0], operands[1],
5887 negate_rtx (DImode, operands[2])));
5888 DONE;
5889 }
5890 }")
5891
5892 (define_insn_and_split "absdi2"
5893 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5894 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5895 (clobber (match_scratch:DI 2 "=&r,&r"))]
5896 "TARGET_POWERPC64"
5897 "#"
5898 "&& reload_completed"
5899 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5900 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5901 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5902 "")
5903
5904 (define_insn_and_split "*nabsdi2"
5905 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5906 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5907 (clobber (match_scratch:DI 2 "=&r,&r"))]
5908 "TARGET_POWERPC64"
5909 "#"
5910 "&& reload_completed"
5911 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5912 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5913 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5914 "")
5915
5916 (define_expand "negdi2"
5917 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5918 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5919 ""
5920 "")
5921
5922 (define_insn ""
5923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5924 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5925 "TARGET_POWERPC64"
5926 "neg %0,%1")
5927
5928 (define_insn ""
5929 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5930 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5931 (const_int 0)))
5932 (clobber (match_scratch:DI 2 "=r,r"))]
5933 "TARGET_POWERPC64"
5934 "@
5935 neg. %2,%1
5936 #"
5937 [(set_attr "type" "fast_compare")
5938 (set_attr "length" "4,8")])
5939
5940 (define_split
5941 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5942 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5943 (const_int 0)))
5944 (clobber (match_scratch:DI 2 ""))]
5945 "TARGET_POWERPC64 && reload_completed"
5946 [(set (match_dup 2)
5947 (neg:DI (match_dup 1)))
5948 (set (match_dup 0)
5949 (compare:CC (match_dup 2)
5950 (const_int 0)))]
5951 "")
5952
5953 (define_insn ""
5954 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5955 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5956 (const_int 0)))
5957 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5958 (neg:DI (match_dup 1)))]
5959 "TARGET_POWERPC64"
5960 "@
5961 neg. %0,%1
5962 #"
5963 [(set_attr "type" "fast_compare")
5964 (set_attr "length" "4,8")])
5965
5966 (define_split
5967 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5968 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5969 (const_int 0)))
5970 (set (match_operand:DI 0 "gpc_reg_operand" "")
5971 (neg:DI (match_dup 1)))]
5972 "TARGET_POWERPC64 && reload_completed"
5973 [(set (match_dup 0)
5974 (neg:DI (match_dup 1)))
5975 (set (match_dup 2)
5976 (compare:CC (match_dup 0)
5977 (const_int 0)))]
5978 "")
5979
5980 (define_insn "clzdi2"
5981 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5982 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5983 "TARGET_POWERPC64"
5984 "cntlzd %0,%1")
5985
5986 (define_expand "ctzdi2"
5987 [(set (match_dup 2)
5988 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
5989 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
5990 (match_dup 2)))
5991 (clobber (scratch:CC))])
5992 (set (match_dup 4) (clz:DI (match_dup 3)))
5993 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5994 (minus:DI (const_int 63) (match_dup 4)))]
5995 "TARGET_POWERPC64"
5996 {
5997 operands[2] = gen_reg_rtx (DImode);
5998 operands[3] = gen_reg_rtx (DImode);
5999 operands[4] = gen_reg_rtx (DImode);
6000 })
6001
6002 (define_expand "ffsdi2"
6003 [(set (match_dup 2)
6004 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6005 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6006 (match_dup 2)))
6007 (clobber (scratch:CC))])
6008 (set (match_dup 4) (clz:DI (match_dup 3)))
6009 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6010 (minus:DI (const_int 64) (match_dup 4)))]
6011 "TARGET_POWERPC64"
6012 {
6013 operands[2] = gen_reg_rtx (DImode);
6014 operands[3] = gen_reg_rtx (DImode);
6015 operands[4] = gen_reg_rtx (DImode);
6016 })
6017
6018 (define_insn "muldi3"
6019 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6020 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6021 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6022 "TARGET_POWERPC64"
6023 "mulld %0,%1,%2"
6024 [(set_attr "type" "lmul")])
6025
6026 (define_insn "smuldi3_highpart"
6027 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6028 (truncate:DI
6029 (lshiftrt:TI (mult:TI (sign_extend:TI
6030 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6031 (sign_extend:TI
6032 (match_operand:DI 2 "gpc_reg_operand" "r")))
6033 (const_int 64))))]
6034 "TARGET_POWERPC64"
6035 "mulhd %0,%1,%2"
6036 [(set_attr "type" "lmul")])
6037
6038 (define_insn "umuldi3_highpart"
6039 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6040 (truncate:DI
6041 (lshiftrt:TI (mult:TI (zero_extend:TI
6042 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6043 (zero_extend:TI
6044 (match_operand:DI 2 "gpc_reg_operand" "r")))
6045 (const_int 64))))]
6046 "TARGET_POWERPC64"
6047 "mulhdu %0,%1,%2"
6048 [(set_attr "type" "lmul")])
6049
6050 (define_expand "divdi3"
6051 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6052 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6053 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6054 "TARGET_POWERPC64"
6055 "
6056 {
6057 if (GET_CODE (operands[2]) == CONST_INT
6058 && INTVAL (operands[2]) > 0
6059 && exact_log2 (INTVAL (operands[2])) >= 0)
6060 ;
6061 else
6062 operands[2] = force_reg (DImode, operands[2]);
6063 }")
6064
6065 (define_expand "moddi3"
6066 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6067 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6068 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6069 "TARGET_POWERPC64"
6070 "
6071 {
6072 int i;
6073 rtx temp1;
6074 rtx temp2;
6075
6076 if (GET_CODE (operands[2]) != CONST_INT
6077 || INTVAL (operands[2]) <= 0
6078 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6079 FAIL;
6080
6081 temp1 = gen_reg_rtx (DImode);
6082 temp2 = gen_reg_rtx (DImode);
6083
6084 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6085 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6086 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6087 DONE;
6088 }")
6089
6090 (define_insn ""
6091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6092 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6093 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6094 "TARGET_POWERPC64"
6095 "sradi %0,%1,%p2\;addze %0,%0"
6096 [(set_attr "length" "8")])
6097
6098 (define_insn ""
6099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6100 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6101 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6102 (const_int 0)))
6103 (clobber (match_scratch:DI 3 "=r,r"))]
6104 "TARGET_POWERPC64"
6105 "@
6106 sradi %3,%1,%p2\;addze. %3,%3
6107 #"
6108 [(set_attr "type" "compare")
6109 (set_attr "length" "8,12")])
6110
6111 (define_split
6112 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6113 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6114 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6115 (const_int 0)))
6116 (clobber (match_scratch:DI 3 ""))]
6117 "TARGET_POWERPC64 && reload_completed"
6118 [(set (match_dup 3)
6119 (div:DI (match_dup 1) (match_dup 2)))
6120 (set (match_dup 0)
6121 (compare:CC (match_dup 3)
6122 (const_int 0)))]
6123 "")
6124
6125 (define_insn ""
6126 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6127 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6128 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6129 (const_int 0)))
6130 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6131 (div:DI (match_dup 1) (match_dup 2)))]
6132 "TARGET_POWERPC64"
6133 "@
6134 sradi %0,%1,%p2\;addze. %0,%0
6135 #"
6136 [(set_attr "type" "compare")
6137 (set_attr "length" "8,12")])
6138
6139 (define_split
6140 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6141 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6142 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6143 (const_int 0)))
6144 (set (match_operand:DI 0 "gpc_reg_operand" "")
6145 (div:DI (match_dup 1) (match_dup 2)))]
6146 "TARGET_POWERPC64 && reload_completed"
6147 [(set (match_dup 0)
6148 (div:DI (match_dup 1) (match_dup 2)))
6149 (set (match_dup 3)
6150 (compare:CC (match_dup 0)
6151 (const_int 0)))]
6152 "")
6153
6154 (define_insn ""
6155 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6156 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6157 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6158 "TARGET_POWERPC64"
6159 "divd %0,%1,%2"
6160 [(set_attr "type" "ldiv")])
6161
6162 (define_insn "udivdi3"
6163 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6164 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6165 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6166 "TARGET_POWERPC64"
6167 "divdu %0,%1,%2"
6168 [(set_attr "type" "ldiv")])
6169
6170 (define_insn "rotldi3"
6171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6172 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6173 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6174 "TARGET_POWERPC64"
6175 "rld%I2cl %0,%1,%H2,0")
6176
6177 (define_insn "*rotldi3_internal2"
6178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6179 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6180 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6181 (const_int 0)))
6182 (clobber (match_scratch:DI 3 "=r,r"))]
6183 "TARGET_POWERPC64"
6184 "@
6185 rld%I2cl. %3,%1,%H2,0
6186 #"
6187 [(set_attr "type" "delayed_compare")
6188 (set_attr "length" "4,8")])
6189
6190 (define_split
6191 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6192 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6193 (match_operand:DI 2 "reg_or_cint_operand" ""))
6194 (const_int 0)))
6195 (clobber (match_scratch:DI 3 ""))]
6196 "TARGET_POWERPC64 && reload_completed"
6197 [(set (match_dup 3)
6198 (rotate:DI (match_dup 1) (match_dup 2)))
6199 (set (match_dup 0)
6200 (compare:CC (match_dup 3)
6201 (const_int 0)))]
6202 "")
6203
6204 (define_insn "*rotldi3_internal3"
6205 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6206 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6207 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6208 (const_int 0)))
6209 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6210 (rotate:DI (match_dup 1) (match_dup 2)))]
6211 "TARGET_POWERPC64"
6212 "@
6213 rld%I2cl. %0,%1,%H2,0
6214 #"
6215 [(set_attr "type" "delayed_compare")
6216 (set_attr "length" "4,8")])
6217
6218 (define_split
6219 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6220 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6221 (match_operand:DI 2 "reg_or_cint_operand" ""))
6222 (const_int 0)))
6223 (set (match_operand:DI 0 "gpc_reg_operand" "")
6224 (rotate:DI (match_dup 1) (match_dup 2)))]
6225 "TARGET_POWERPC64 && reload_completed"
6226 [(set (match_dup 0)
6227 (rotate:DI (match_dup 1) (match_dup 2)))
6228 (set (match_dup 3)
6229 (compare:CC (match_dup 0)
6230 (const_int 0)))]
6231 "")
6232
6233 (define_insn "*rotldi3_internal4"
6234 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6235 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6236 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6237 (match_operand:DI 3 "mask64_operand" "n")))]
6238 "TARGET_POWERPC64"
6239 "rld%I2c%B3 %0,%1,%H2,%S3")
6240
6241 (define_insn "*rotldi3_internal5"
6242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6243 (compare:CC (and:DI
6244 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6245 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6246 (match_operand:DI 3 "mask64_operand" "n,n"))
6247 (const_int 0)))
6248 (clobber (match_scratch:DI 4 "=r,r"))]
6249 "TARGET_POWERPC64"
6250 "@
6251 rld%I2c%B3. %4,%1,%H2,%S3
6252 #"
6253 [(set_attr "type" "delayed_compare")
6254 (set_attr "length" "4,8")])
6255
6256 (define_split
6257 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6258 (compare:CC (and:DI
6259 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6260 (match_operand:DI 2 "reg_or_cint_operand" ""))
6261 (match_operand:DI 3 "mask64_operand" ""))
6262 (const_int 0)))
6263 (clobber (match_scratch:DI 4 ""))]
6264 "TARGET_POWERPC64 && reload_completed"
6265 [(set (match_dup 4)
6266 (and:DI (rotate:DI (match_dup 1)
6267 (match_dup 2))
6268 (match_dup 3)))
6269 (set (match_dup 0)
6270 (compare:CC (match_dup 4)
6271 (const_int 0)))]
6272 "")
6273
6274 (define_insn "*rotldi3_internal6"
6275 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6276 (compare:CC (and:DI
6277 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6278 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6279 (match_operand:DI 3 "mask64_operand" "n,n"))
6280 (const_int 0)))
6281 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6282 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6283 "TARGET_POWERPC64"
6284 "@
6285 rld%I2c%B3. %0,%1,%H2,%S3
6286 #"
6287 [(set_attr "type" "delayed_compare")
6288 (set_attr "length" "4,8")])
6289
6290 (define_split
6291 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6292 (compare:CC (and:DI
6293 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6294 (match_operand:DI 2 "reg_or_cint_operand" ""))
6295 (match_operand:DI 3 "mask64_operand" ""))
6296 (const_int 0)))
6297 (set (match_operand:DI 0 "gpc_reg_operand" "")
6298 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6299 "TARGET_POWERPC64 && reload_completed"
6300 [(set (match_dup 0)
6301 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6302 (set (match_dup 4)
6303 (compare:CC (match_dup 0)
6304 (const_int 0)))]
6305 "")
6306
6307 (define_insn "*rotldi3_internal7"
6308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6309 (zero_extend:DI
6310 (subreg:QI
6311 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6312 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6313 "TARGET_POWERPC64"
6314 "rld%I2cl %0,%1,%H2,56")
6315
6316 (define_insn "*rotldi3_internal8"
6317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6318 (compare:CC (zero_extend:DI
6319 (subreg:QI
6320 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6321 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6322 (const_int 0)))
6323 (clobber (match_scratch:DI 3 "=r,r"))]
6324 "TARGET_POWERPC64"
6325 "@
6326 rld%I2cl. %3,%1,%H2,56
6327 #"
6328 [(set_attr "type" "delayed_compare")
6329 (set_attr "length" "4,8")])
6330
6331 (define_split
6332 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6333 (compare:CC (zero_extend:DI
6334 (subreg:QI
6335 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6336 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6337 (const_int 0)))
6338 (clobber (match_scratch:DI 3 ""))]
6339 "TARGET_POWERPC64 && reload_completed"
6340 [(set (match_dup 3)
6341 (zero_extend:DI (subreg:QI
6342 (rotate:DI (match_dup 1)
6343 (match_dup 2)) 0)))
6344 (set (match_dup 0)
6345 (compare:CC (match_dup 3)
6346 (const_int 0)))]
6347 "")
6348
6349 (define_insn "*rotldi3_internal9"
6350 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6351 (compare:CC (zero_extend:DI
6352 (subreg:QI
6353 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6354 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6355 (const_int 0)))
6356 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6357 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6358 "TARGET_POWERPC64"
6359 "@
6360 rld%I2cl. %0,%1,%H2,56
6361 #"
6362 [(set_attr "type" "delayed_compare")
6363 (set_attr "length" "4,8")])
6364
6365 (define_split
6366 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6367 (compare:CC (zero_extend:DI
6368 (subreg:QI
6369 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6370 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6371 (const_int 0)))
6372 (set (match_operand:DI 0 "gpc_reg_operand" "")
6373 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6374 "TARGET_POWERPC64 && reload_completed"
6375 [(set (match_dup 0)
6376 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6377 (set (match_dup 3)
6378 (compare:CC (match_dup 0)
6379 (const_int 0)))]
6380 "")
6381
6382 (define_insn "*rotldi3_internal10"
6383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6384 (zero_extend:DI
6385 (subreg:HI
6386 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6387 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6388 "TARGET_POWERPC64"
6389 "rld%I2cl %0,%1,%H2,48")
6390
6391 (define_insn "*rotldi3_internal11"
6392 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6393 (compare:CC (zero_extend:DI
6394 (subreg:HI
6395 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6396 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6397 (const_int 0)))
6398 (clobber (match_scratch:DI 3 "=r,r"))]
6399 "TARGET_POWERPC64"
6400 "@
6401 rld%I2cl. %3,%1,%H2,48
6402 #"
6403 [(set_attr "type" "delayed_compare")
6404 (set_attr "length" "4,8")])
6405
6406 (define_split
6407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6408 (compare:CC (zero_extend:DI
6409 (subreg:HI
6410 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6411 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6412 (const_int 0)))
6413 (clobber (match_scratch:DI 3 ""))]
6414 "TARGET_POWERPC64 && reload_completed"
6415 [(set (match_dup 3)
6416 (zero_extend:DI (subreg:HI
6417 (rotate:DI (match_dup 1)
6418 (match_dup 2)) 0)))
6419 (set (match_dup 0)
6420 (compare:CC (match_dup 3)
6421 (const_int 0)))]
6422 "")
6423
6424 (define_insn "*rotldi3_internal12"
6425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6426 (compare:CC (zero_extend:DI
6427 (subreg:HI
6428 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6429 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6430 (const_int 0)))
6431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6432 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6433 "TARGET_POWERPC64"
6434 "@
6435 rld%I2cl. %0,%1,%H2,48
6436 #"
6437 [(set_attr "type" "delayed_compare")
6438 (set_attr "length" "4,8")])
6439
6440 (define_split
6441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6442 (compare:CC (zero_extend:DI
6443 (subreg:HI
6444 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6445 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6446 (const_int 0)))
6447 (set (match_operand:DI 0 "gpc_reg_operand" "")
6448 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6449 "TARGET_POWERPC64 && reload_completed"
6450 [(set (match_dup 0)
6451 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6452 (set (match_dup 3)
6453 (compare:CC (match_dup 0)
6454 (const_int 0)))]
6455 "")
6456
6457 (define_insn "*rotldi3_internal13"
6458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6459 (zero_extend:DI
6460 (subreg:SI
6461 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6462 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6463 "TARGET_POWERPC64"
6464 "rld%I2cl %0,%1,%H2,32")
6465
6466 (define_insn "*rotldi3_internal14"
6467 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6468 (compare:CC (zero_extend:DI
6469 (subreg:SI
6470 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6471 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6472 (const_int 0)))
6473 (clobber (match_scratch:DI 3 "=r,r"))]
6474 "TARGET_POWERPC64"
6475 "@
6476 rld%I2cl. %3,%1,%H2,32
6477 #"
6478 [(set_attr "type" "delayed_compare")
6479 (set_attr "length" "4,8")])
6480
6481 (define_split
6482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6483 (compare:CC (zero_extend:DI
6484 (subreg:SI
6485 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6486 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6487 (const_int 0)))
6488 (clobber (match_scratch:DI 3 ""))]
6489 "TARGET_POWERPC64 && reload_completed"
6490 [(set (match_dup 3)
6491 (zero_extend:DI (subreg:SI
6492 (rotate:DI (match_dup 1)
6493 (match_dup 2)) 0)))
6494 (set (match_dup 0)
6495 (compare:CC (match_dup 3)
6496 (const_int 0)))]
6497 "")
6498
6499 (define_insn "*rotldi3_internal15"
6500 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6501 (compare:CC (zero_extend:DI
6502 (subreg:SI
6503 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6504 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6505 (const_int 0)))
6506 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6507 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6508 "TARGET_POWERPC64"
6509 "@
6510 rld%I2cl. %0,%1,%H2,32
6511 #"
6512 [(set_attr "type" "delayed_compare")
6513 (set_attr "length" "4,8")])
6514
6515 (define_split
6516 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6517 (compare:CC (zero_extend:DI
6518 (subreg:SI
6519 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6520 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6521 (const_int 0)))
6522 (set (match_operand:DI 0 "gpc_reg_operand" "")
6523 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6524 "TARGET_POWERPC64 && reload_completed"
6525 [(set (match_dup 0)
6526 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6527 (set (match_dup 3)
6528 (compare:CC (match_dup 0)
6529 (const_int 0)))]
6530 "")
6531
6532 (define_expand "ashldi3"
6533 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6534 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6535 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6536 "TARGET_POWERPC64 || TARGET_POWER"
6537 "
6538 {
6539 if (TARGET_POWERPC64)
6540 ;
6541 else if (TARGET_POWER)
6542 {
6543 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6544 DONE;
6545 }
6546 else
6547 FAIL;
6548 }")
6549
6550 (define_insn "*ashldi3_internal1"
6551 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6552 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6553 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6554 "TARGET_POWERPC64"
6555 "sld%I2 %0,%1,%H2"
6556 [(set_attr "length" "8")])
6557
6558 (define_insn "*ashldi3_internal2"
6559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6560 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6561 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6562 (const_int 0)))
6563 (clobber (match_scratch:DI 3 "=r,r"))]
6564 "TARGET_POWERPC64"
6565 "@
6566 sld%I2. %3,%1,%H2
6567 #"
6568 [(set_attr "type" "delayed_compare")
6569 (set_attr "length" "4,8")])
6570
6571 (define_split
6572 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6573 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6574 (match_operand:SI 2 "reg_or_cint_operand" ""))
6575 (const_int 0)))
6576 (clobber (match_scratch:DI 3 ""))]
6577 "TARGET_POWERPC64 && reload_completed"
6578 [(set (match_dup 3)
6579 (ashift:DI (match_dup 1) (match_dup 2)))
6580 (set (match_dup 0)
6581 (compare:CC (match_dup 3)
6582 (const_int 0)))]
6583 "")
6584
6585 (define_insn "*ashldi3_internal3"
6586 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6587 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6588 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6589 (const_int 0)))
6590 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6591 (ashift:DI (match_dup 1) (match_dup 2)))]
6592 "TARGET_POWERPC64"
6593 "@
6594 sld%I2. %0,%1,%H2
6595 #"
6596 [(set_attr "type" "delayed_compare")
6597 (set_attr "length" "4,8")])
6598
6599 (define_split
6600 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6601 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6602 (match_operand:SI 2 "reg_or_cint_operand" ""))
6603 (const_int 0)))
6604 (set (match_operand:DI 0 "gpc_reg_operand" "")
6605 (ashift:DI (match_dup 1) (match_dup 2)))]
6606 "TARGET_POWERPC64 && reload_completed"
6607 [(set (match_dup 0)
6608 (ashift:DI (match_dup 1) (match_dup 2)))
6609 (set (match_dup 3)
6610 (compare:CC (match_dup 0)
6611 (const_int 0)))]
6612 "")
6613
6614 (define_insn "*ashldi3_internal4"
6615 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6616 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6617 (match_operand:SI 2 "const_int_operand" "i"))
6618 (match_operand:DI 3 "const_int_operand" "n")))]
6619 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6620 "rldic %0,%1,%H2,%W3")
6621
6622 (define_insn "ashldi3_internal5"
6623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6624 (compare:CC
6625 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6626 (match_operand:SI 2 "const_int_operand" "i,i"))
6627 (match_operand:DI 3 "const_int_operand" "n,n"))
6628 (const_int 0)))
6629 (clobber (match_scratch:DI 4 "=r,r"))]
6630 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6631 "@
6632 rldic. %4,%1,%H2,%W3
6633 #"
6634 [(set_attr "type" "delayed_compare")
6635 (set_attr "length" "4,8")])
6636
6637 (define_split
6638 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6639 (compare:CC
6640 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6641 (match_operand:SI 2 "const_int_operand" ""))
6642 (match_operand:DI 3 "const_int_operand" ""))
6643 (const_int 0)))
6644 (clobber (match_scratch:DI 4 ""))]
6645 "TARGET_POWERPC64 && reload_completed
6646 && includes_rldic_lshift_p (operands[2], operands[3])"
6647 [(set (match_dup 4)
6648 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6649 (match_dup 3)))
6650 (set (match_dup 0)
6651 (compare:CC (match_dup 4)
6652 (const_int 0)))]
6653 "")
6654
6655 (define_insn "*ashldi3_internal6"
6656 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6657 (compare:CC
6658 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6659 (match_operand:SI 2 "const_int_operand" "i,i"))
6660 (match_operand:DI 3 "const_int_operand" "n,n"))
6661 (const_int 0)))
6662 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6663 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6664 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6665 "@
6666 rldic. %0,%1,%H2,%W3
6667 #"
6668 [(set_attr "type" "delayed_compare")
6669 (set_attr "length" "4,8")])
6670
6671 (define_split
6672 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6673 (compare:CC
6674 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6675 (match_operand:SI 2 "const_int_operand" ""))
6676 (match_operand:DI 3 "const_int_operand" ""))
6677 (const_int 0)))
6678 (set (match_operand:DI 0 "gpc_reg_operand" "")
6679 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6680 "TARGET_POWERPC64 && reload_completed
6681 && includes_rldic_lshift_p (operands[2], operands[3])"
6682 [(set (match_dup 0)
6683 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6684 (match_dup 3)))
6685 (set (match_dup 4)
6686 (compare:CC (match_dup 0)
6687 (const_int 0)))]
6688 "")
6689
6690 (define_insn "*ashldi3_internal7"
6691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6692 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6693 (match_operand:SI 2 "const_int_operand" "i"))
6694 (match_operand:DI 3 "mask64_operand" "n")))]
6695 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6696 "rldicr %0,%1,%H2,%S3")
6697
6698 (define_insn "ashldi3_internal8"
6699 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6700 (compare:CC
6701 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6702 (match_operand:SI 2 "const_int_operand" "i,i"))
6703 (match_operand:DI 3 "mask64_operand" "n,n"))
6704 (const_int 0)))
6705 (clobber (match_scratch:DI 4 "=r,r"))]
6706 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6707 "@
6708 rldicr. %4,%1,%H2,%S3
6709 #"
6710 [(set_attr "type" "delayed_compare")
6711 (set_attr "length" "4,8")])
6712
6713 (define_split
6714 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6715 (compare:CC
6716 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6717 (match_operand:SI 2 "const_int_operand" ""))
6718 (match_operand:DI 3 "mask64_operand" ""))
6719 (const_int 0)))
6720 (clobber (match_scratch:DI 4 ""))]
6721 "TARGET_POWERPC64 && reload_completed
6722 && includes_rldicr_lshift_p (operands[2], operands[3])"
6723 [(set (match_dup 4)
6724 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6725 (match_dup 3)))
6726 (set (match_dup 0)
6727 (compare:CC (match_dup 4)
6728 (const_int 0)))]
6729 "")
6730
6731 (define_insn "*ashldi3_internal9"
6732 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6733 (compare:CC
6734 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6735 (match_operand:SI 2 "const_int_operand" "i,i"))
6736 (match_operand:DI 3 "mask64_operand" "n,n"))
6737 (const_int 0)))
6738 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6739 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6740 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6741 "@
6742 rldicr. %0,%1,%H2,%S3
6743 #"
6744 [(set_attr "type" "delayed_compare")
6745 (set_attr "length" "4,8")])
6746
6747 (define_split
6748 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6749 (compare:CC
6750 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6751 (match_operand:SI 2 "const_int_operand" ""))
6752 (match_operand:DI 3 "mask64_operand" ""))
6753 (const_int 0)))
6754 (set (match_operand:DI 0 "gpc_reg_operand" "")
6755 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6756 "TARGET_POWERPC64 && reload_completed
6757 && includes_rldicr_lshift_p (operands[2], operands[3])"
6758 [(set (match_dup 0)
6759 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6760 (match_dup 3)))
6761 (set (match_dup 4)
6762 (compare:CC (match_dup 0)
6763 (const_int 0)))]
6764 "")
6765
6766 (define_expand "lshrdi3"
6767 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6768 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6769 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6770 "TARGET_POWERPC64 || TARGET_POWER"
6771 "
6772 {
6773 if (TARGET_POWERPC64)
6774 ;
6775 else if (TARGET_POWER)
6776 {
6777 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6778 DONE;
6779 }
6780 else
6781 FAIL;
6782 }")
6783
6784 (define_insn "*lshrdi3_internal1"
6785 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6786 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6787 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6788 "TARGET_POWERPC64"
6789 "srd%I2 %0,%1,%H2")
6790
6791 (define_insn "*lshrdi3_internal2"
6792 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6793 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6794 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6795 (const_int 0)))
6796 (clobber (match_scratch:DI 3 "=r,r"))]
6797 "TARGET_POWERPC64"
6798 "@
6799 srd%I2. %3,%1,%H2
6800 #"
6801 [(set_attr "type" "delayed_compare")
6802 (set_attr "length" "4,8")])
6803
6804 (define_split
6805 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6806 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6807 (match_operand:SI 2 "reg_or_cint_operand" ""))
6808 (const_int 0)))
6809 (clobber (match_scratch:DI 3 ""))]
6810 "TARGET_POWERPC64 && reload_completed"
6811 [(set (match_dup 3)
6812 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6813 (set (match_dup 0)
6814 (compare:CC (match_dup 3)
6815 (const_int 0)))]
6816 "")
6817
6818 (define_insn "*lshrdi3_internal3"
6819 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6820 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6821 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6822 (const_int 0)))
6823 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6824 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6825 "TARGET_POWERPC64"
6826 "@
6827 srd%I2. %0,%1,%H2
6828 #"
6829 [(set_attr "type" "delayed_compare")
6830 (set_attr "length" "4,8")])
6831
6832 (define_split
6833 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6834 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6835 (match_operand:SI 2 "reg_or_cint_operand" ""))
6836 (const_int 0)))
6837 (set (match_operand:DI 0 "gpc_reg_operand" "")
6838 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6839 "TARGET_POWERPC64 && reload_completed"
6840 [(set (match_dup 0)
6841 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6842 (set (match_dup 3)
6843 (compare:CC (match_dup 0)
6844 (const_int 0)))]
6845 "")
6846
6847 (define_expand "ashrdi3"
6848 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6849 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6850 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6851 ""
6852 "
6853 {
6854 if (TARGET_POWERPC64)
6855 ;
6856 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6857 {
6858 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6859 DONE;
6860 }
6861 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
6862 {
6863 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6864 DONE;
6865 }
6866 else
6867 FAIL;
6868 }")
6869
6870 (define_insn "*ashrdi3_internal1"
6871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6872 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6873 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6874 "TARGET_POWERPC64"
6875 "srad%I2 %0,%1,%H2")
6876
6877 (define_insn "*ashrdi3_internal2"
6878 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6879 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6880 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6881 (const_int 0)))
6882 (clobber (match_scratch:DI 3 "=r,r"))]
6883 "TARGET_POWERPC64"
6884 "@
6885 srad%I2. %3,%1,%H2
6886 #"
6887 [(set_attr "type" "delayed_compare")
6888 (set_attr "length" "4,8")])
6889
6890 (define_split
6891 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6892 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6893 (match_operand:SI 2 "reg_or_cint_operand" ""))
6894 (const_int 0)))
6895 (clobber (match_scratch:DI 3 ""))]
6896 "TARGET_POWERPC64 && reload_completed"
6897 [(set (match_dup 3)
6898 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6899 (set (match_dup 0)
6900 (compare:CC (match_dup 3)
6901 (const_int 0)))]
6902 "")
6903
6904 (define_insn "*ashrdi3_internal3"
6905 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6906 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6907 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6908 (const_int 0)))
6909 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6910 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6911 "TARGET_POWERPC64"
6912 "@
6913 srad%I2. %0,%1,%H2
6914 #"
6915 [(set_attr "type" "delayed_compare")
6916 (set_attr "length" "4,8")])
6917
6918 (define_split
6919 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6920 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6921 (match_operand:SI 2 "reg_or_cint_operand" ""))
6922 (const_int 0)))
6923 (set (match_operand:DI 0 "gpc_reg_operand" "")
6924 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6925 "TARGET_POWERPC64 && reload_completed"
6926 [(set (match_dup 0)
6927 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6928 (set (match_dup 3)
6929 (compare:CC (match_dup 0)
6930 (const_int 0)))]
6931 "")
6932
6933 (define_insn "anddi3"
6934 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
6935 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
6936 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
6937 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
6938 "TARGET_POWERPC64"
6939 "@
6940 and %0,%1,%2
6941 rldic%B2 %0,%1,0,%S2
6942 andi. %0,%1,%b2
6943 andis. %0,%1,%u2
6944 #"
6945 [(set_attr "length" "4,4,4,4,8")])
6946
6947 (define_split
6948 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6949 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6950 (match_operand:DI 2 "mask64_2_operand" "")))
6951 (clobber (match_scratch:CC 3 ""))]
6952 "TARGET_POWERPC64
6953 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6954 && !mask64_operand (operands[2], DImode)"
6955 [(set (match_dup 0)
6956 (and:DI (rotate:DI (match_dup 1)
6957 (match_dup 4))
6958 (match_dup 5)))
6959 (set (match_dup 0)
6960 (and:DI (rotate:DI (match_dup 0)
6961 (match_dup 6))
6962 (match_dup 7)))]
6963 "
6964 {
6965 build_mask64_2_operands (operands[2], &operands[4]);
6966 }")
6967
6968 (define_insn "*anddi3_internal2"
6969 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6970 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6971 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6972 (const_int 0)))
6973 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6974 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6975 "TARGET_POWERPC64"
6976 "@
6977 and. %3,%1,%2
6978 rldic%B2. %3,%1,0,%S2
6979 andi. %3,%1,%b2
6980 andis. %3,%1,%u2
6981 #
6982 #
6983 #
6984 #
6985 #
6986 #"
6987 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6988 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6989
6990 (define_split
6991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6992 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6993 (match_operand:DI 2 "and64_operand" ""))
6994 (const_int 0)))
6995 (clobber (match_scratch:DI 3 ""))
6996 (clobber (match_scratch:CC 4 ""))]
6997 "TARGET_POWERPC64 && reload_completed"
6998 [(parallel [(set (match_dup 3)
6999 (and:DI (match_dup 1)
7000 (match_dup 2)))
7001 (clobber (match_dup 4))])
7002 (set (match_dup 0)
7003 (compare:CC (match_dup 3)
7004 (const_int 0)))]
7005 "")
7006
7007 (define_split
7008 [(set (match_operand:CC 0 "cc_reg_operand" "")
7009 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7010 (match_operand:DI 2 "mask64_2_operand" ""))
7011 (const_int 0)))
7012 (clobber (match_scratch:DI 3 ""))
7013 (clobber (match_scratch:CC 4 ""))]
7014 "TARGET_POWERPC64 && reload_completed
7015 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7016 && !mask64_operand (operands[2], DImode)"
7017 [(set (match_dup 3)
7018 (and:DI (rotate:DI (match_dup 1)
7019 (match_dup 5))
7020 (match_dup 6)))
7021 (parallel [(set (match_dup 0)
7022 (compare:CC (and:DI (rotate:DI (match_dup 3)
7023 (match_dup 7))
7024 (match_dup 8))
7025 (const_int 0)))
7026 (clobber (match_dup 3))])]
7027 "
7028 {
7029 build_mask64_2_operands (operands[2], &operands[5]);
7030 }")
7031
7032 (define_insn "*anddi3_internal3"
7033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7034 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7035 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7036 (const_int 0)))
7037 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7038 (and:DI (match_dup 1) (match_dup 2)))
7039 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7040 "TARGET_POWERPC64"
7041 "@
7042 and. %0,%1,%2
7043 rldic%B2. %0,%1,0,%S2
7044 andi. %0,%1,%b2
7045 andis. %0,%1,%u2
7046 #
7047 #
7048 #
7049 #
7050 #
7051 #"
7052 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7053 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7054
7055 (define_split
7056 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7057 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7058 (match_operand:DI 2 "and64_operand" ""))
7059 (const_int 0)))
7060 (set (match_operand:DI 0 "gpc_reg_operand" "")
7061 (and:DI (match_dup 1) (match_dup 2)))
7062 (clobber (match_scratch:CC 4 ""))]
7063 "TARGET_POWERPC64 && reload_completed"
7064 [(parallel [(set (match_dup 0)
7065 (and:DI (match_dup 1) (match_dup 2)))
7066 (clobber (match_dup 4))])
7067 (set (match_dup 3)
7068 (compare:CC (match_dup 0)
7069 (const_int 0)))]
7070 "")
7071
7072 (define_split
7073 [(set (match_operand:CC 3 "cc_reg_operand" "")
7074 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7075 (match_operand:DI 2 "mask64_2_operand" ""))
7076 (const_int 0)))
7077 (set (match_operand:DI 0 "gpc_reg_operand" "")
7078 (and:DI (match_dup 1) (match_dup 2)))
7079 (clobber (match_scratch:CC 4 ""))]
7080 "TARGET_POWERPC64 && reload_completed
7081 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7082 && !mask64_operand (operands[2], DImode)"
7083 [(set (match_dup 0)
7084 (and:DI (rotate:DI (match_dup 1)
7085 (match_dup 5))
7086 (match_dup 6)))
7087 (parallel [(set (match_dup 3)
7088 (compare:CC (and:DI (rotate:DI (match_dup 0)
7089 (match_dup 7))
7090 (match_dup 8))
7091 (const_int 0)))
7092 (set (match_dup 0)
7093 (and:DI (rotate:DI (match_dup 0)
7094 (match_dup 7))
7095 (match_dup 8)))])]
7096 "
7097 {
7098 build_mask64_2_operands (operands[2], &operands[5]);
7099 }")
7100
7101 (define_expand "iordi3"
7102 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7103 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7104 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7105 "TARGET_POWERPC64"
7106 "
7107 {
7108 if (non_logical_cint_operand (operands[2], DImode))
7109 {
7110 HOST_WIDE_INT value;
7111 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7112 ? operands[0] : gen_reg_rtx (DImode));
7113
7114 if (GET_CODE (operands[2]) == CONST_INT)
7115 {
7116 value = INTVAL (operands[2]);
7117 emit_insn (gen_iordi3 (tmp, operands[1],
7118 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7119 }
7120 else
7121 {
7122 value = CONST_DOUBLE_LOW (operands[2]);
7123 emit_insn (gen_iordi3 (tmp, operands[1],
7124 immed_double_const (value
7125 & (~ (HOST_WIDE_INT) 0xffff),
7126 0, DImode)));
7127 }
7128
7129 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7130 DONE;
7131 }
7132 }")
7133
7134 (define_expand "xordi3"
7135 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7136 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7137 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7138 "TARGET_POWERPC64"
7139 "
7140 {
7141 if (non_logical_cint_operand (operands[2], DImode))
7142 {
7143 HOST_WIDE_INT value;
7144 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7145 ? operands[0] : gen_reg_rtx (DImode));
7146
7147 if (GET_CODE (operands[2]) == CONST_INT)
7148 {
7149 value = INTVAL (operands[2]);
7150 emit_insn (gen_xordi3 (tmp, operands[1],
7151 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7152 }
7153 else
7154 {
7155 value = CONST_DOUBLE_LOW (operands[2]);
7156 emit_insn (gen_xordi3 (tmp, operands[1],
7157 immed_double_const (value
7158 & (~ (HOST_WIDE_INT) 0xffff),
7159 0, DImode)));
7160 }
7161
7162 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7163 DONE;
7164 }
7165 }")
7166
7167 (define_insn "*booldi3_internal1"
7168 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7169 (match_operator:DI 3 "boolean_or_operator"
7170 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7171 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7172 "TARGET_POWERPC64"
7173 "@
7174 %q3 %0,%1,%2
7175 %q3i %0,%1,%b2
7176 %q3is %0,%1,%u2")
7177
7178 (define_insn "*booldi3_internal2"
7179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7180 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7181 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7182 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7183 (const_int 0)))
7184 (clobber (match_scratch:DI 3 "=r,r"))]
7185 "TARGET_POWERPC64"
7186 "@
7187 %q4. %3,%1,%2
7188 #"
7189 [(set_attr "type" "compare")
7190 (set_attr "length" "4,8")])
7191
7192 (define_split
7193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7194 (compare:CC (match_operator:DI 4 "boolean_operator"
7195 [(match_operand:DI 1 "gpc_reg_operand" "")
7196 (match_operand:DI 2 "gpc_reg_operand" "")])
7197 (const_int 0)))
7198 (clobber (match_scratch:DI 3 ""))]
7199 "TARGET_POWERPC64 && reload_completed"
7200 [(set (match_dup 3) (match_dup 4))
7201 (set (match_dup 0)
7202 (compare:CC (match_dup 3)
7203 (const_int 0)))]
7204 "")
7205
7206 (define_insn "*booldi3_internal3"
7207 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7208 (compare:CC (match_operator:DI 4 "boolean_operator"
7209 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7210 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7211 (const_int 0)))
7212 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7213 (match_dup 4))]
7214 "TARGET_POWERPC64"
7215 "@
7216 %q4. %0,%1,%2
7217 #"
7218 [(set_attr "type" "compare")
7219 (set_attr "length" "4,8")])
7220
7221 (define_split
7222 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7223 (compare:CC (match_operator:DI 4 "boolean_operator"
7224 [(match_operand:DI 1 "gpc_reg_operand" "")
7225 (match_operand:DI 2 "gpc_reg_operand" "")])
7226 (const_int 0)))
7227 (set (match_operand:DI 0 "gpc_reg_operand" "")
7228 (match_dup 4))]
7229 "TARGET_POWERPC64 && reload_completed"
7230 [(set (match_dup 0) (match_dup 4))
7231 (set (match_dup 3)
7232 (compare:CC (match_dup 0)
7233 (const_int 0)))]
7234 "")
7235
7236 ;; Split a logical operation that we can't do in one insn into two insns,
7237 ;; each of which does one 16-bit part. This is used by combine.
7238
7239 (define_split
7240 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7241 (match_operator:DI 3 "boolean_or_operator"
7242 [(match_operand:DI 1 "gpc_reg_operand" "")
7243 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7244 "TARGET_POWERPC64"
7245 [(set (match_dup 0) (match_dup 4))
7246 (set (match_dup 0) (match_dup 5))]
7247 "
7248 {
7249 rtx i3,i4;
7250
7251 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7252 {
7253 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7254 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7255 0, DImode);
7256 i4 = GEN_INT (value & 0xffff);
7257 }
7258 else
7259 {
7260 i3 = GEN_INT (INTVAL (operands[2])
7261 & (~ (HOST_WIDE_INT) 0xffff));
7262 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7263 }
7264 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7265 operands[1], i3);
7266 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7267 operands[0], i4);
7268 }")
7269
7270 (define_insn "*boolcdi3_internal1"
7271 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7272 (match_operator:DI 3 "boolean_operator"
7273 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7274 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7275 "TARGET_POWERPC64"
7276 "%q3 %0,%2,%1")
7277
7278 (define_insn "*boolcdi3_internal2"
7279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7280 (compare:CC (match_operator:DI 4 "boolean_operator"
7281 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7282 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7283 (const_int 0)))
7284 (clobber (match_scratch:DI 3 "=r,r"))]
7285 "TARGET_POWERPC64"
7286 "@
7287 %q4. %3,%2,%1
7288 #"
7289 [(set_attr "type" "compare")
7290 (set_attr "length" "4,8")])
7291
7292 (define_split
7293 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7294 (compare:CC (match_operator:DI 4 "boolean_operator"
7295 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7296 (match_operand:DI 2 "gpc_reg_operand" "")])
7297 (const_int 0)))
7298 (clobber (match_scratch:DI 3 ""))]
7299 "TARGET_POWERPC64 && reload_completed"
7300 [(set (match_dup 3) (match_dup 4))
7301 (set (match_dup 0)
7302 (compare:CC (match_dup 3)
7303 (const_int 0)))]
7304 "")
7305
7306 (define_insn "*boolcdi3_internal3"
7307 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7308 (compare:CC (match_operator:DI 4 "boolean_operator"
7309 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7310 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7311 (const_int 0)))
7312 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7313 (match_dup 4))]
7314 "TARGET_POWERPC64"
7315 "@
7316 %q4. %0,%2,%1
7317 #"
7318 [(set_attr "type" "compare")
7319 (set_attr "length" "4,8")])
7320
7321 (define_split
7322 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7323 (compare:CC (match_operator:DI 4 "boolean_operator"
7324 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7325 (match_operand:DI 2 "gpc_reg_operand" "")])
7326 (const_int 0)))
7327 (set (match_operand:DI 0 "gpc_reg_operand" "")
7328 (match_dup 4))]
7329 "TARGET_POWERPC64 && reload_completed"
7330 [(set (match_dup 0) (match_dup 4))
7331 (set (match_dup 3)
7332 (compare:CC (match_dup 0)
7333 (const_int 0)))]
7334 "")
7335
7336 (define_insn "*boolccdi3_internal1"
7337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7338 (match_operator:DI 3 "boolean_operator"
7339 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7340 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7341 "TARGET_POWERPC64"
7342 "%q3 %0,%1,%2")
7343
7344 (define_insn "*boolccdi3_internal2"
7345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7346 (compare:CC (match_operator:DI 4 "boolean_operator"
7347 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7348 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7349 (const_int 0)))
7350 (clobber (match_scratch:DI 3 "=r,r"))]
7351 "TARGET_POWERPC64"
7352 "@
7353 %q4. %3,%1,%2
7354 #"
7355 [(set_attr "type" "compare")
7356 (set_attr "length" "4,8")])
7357
7358 (define_split
7359 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7360 (compare:CC (match_operator:DI 4 "boolean_operator"
7361 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7362 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7363 (const_int 0)))
7364 (clobber (match_scratch:DI 3 ""))]
7365 "TARGET_POWERPC64 && reload_completed"
7366 [(set (match_dup 3) (match_dup 4))
7367 (set (match_dup 0)
7368 (compare:CC (match_dup 3)
7369 (const_int 0)))]
7370 "")
7371
7372 (define_insn "*boolccdi3_internal3"
7373 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7374 (compare:CC (match_operator:DI 4 "boolean_operator"
7375 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7376 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7377 (const_int 0)))
7378 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7379 (match_dup 4))]
7380 "TARGET_POWERPC64"
7381 "@
7382 %q4. %0,%1,%2
7383 #"
7384 [(set_attr "type" "compare")
7385 (set_attr "length" "4,8")])
7386
7387 (define_split
7388 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7389 (compare:CC (match_operator:DI 4 "boolean_operator"
7390 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7391 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7392 (const_int 0)))
7393 (set (match_operand:DI 0 "gpc_reg_operand" "")
7394 (match_dup 4))]
7395 "TARGET_POWERPC64 && reload_completed"
7396 [(set (match_dup 0) (match_dup 4))
7397 (set (match_dup 3)
7398 (compare:CC (match_dup 0)
7399 (const_int 0)))]
7400 "")
7401 \f
7402 ;; Now define ways of moving data around.
7403
7404 ;; Elf specific ways of loading addresses for non-PIC code.
7405 ;; The output of this could be r0, but we make a very strong
7406 ;; preference for a base register because it will usually
7407 ;; be needed there.
7408 (define_insn "elf_high"
7409 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7410 (high:SI (match_operand 1 "" "")))]
7411 "TARGET_ELF && ! TARGET_64BIT"
7412 "{liu|lis} %0,%1@ha")
7413
7414 (define_insn "elf_low"
7415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7416 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7417 (match_operand 2 "" "")))]
7418 "TARGET_ELF && ! TARGET_64BIT"
7419 "@
7420 {cal|la} %0,%2@l(%1)
7421 {ai|addic} %0,%1,%K2")
7422
7423 ;; Mach-O PIC trickery.
7424 (define_insn "macho_high"
7425 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7426 (high:SI (match_operand 1 "" "")))]
7427 "TARGET_MACHO && ! TARGET_64BIT"
7428 "{liu|lis} %0,ha16(%1)")
7429
7430 (define_insn "macho_low"
7431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7432 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7433 (match_operand 2 "" "")))]
7434 "TARGET_MACHO && ! TARGET_64BIT"
7435 "@
7436 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7437 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7438
7439 ;; Set up a register with a value from the GOT table
7440
7441 (define_expand "movsi_got"
7442 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7443 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7444 (match_dup 2)] 8))]
7445 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7446 "
7447 {
7448 if (GET_CODE (operands[1]) == CONST)
7449 {
7450 rtx offset = const0_rtx;
7451 HOST_WIDE_INT value;
7452
7453 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7454 value = INTVAL (offset);
7455 if (value != 0)
7456 {
7457 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7458 emit_insn (gen_movsi_got (tmp, operands[1]));
7459 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7460 DONE;
7461 }
7462 }
7463
7464 operands[2] = rs6000_got_register (operands[1]);
7465 }")
7466
7467 (define_insn "*movsi_got_internal"
7468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7469 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7470 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
7471 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7472 "{l|lwz} %0,%a1@got(%2)"
7473 [(set_attr "type" "load")])
7474
7475 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7476 ;; didn't get allocated to a hard register.
7477 (define_split
7478 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7479 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7480 (match_operand:SI 2 "memory_operand" "")] 8))]
7481 "DEFAULT_ABI == ABI_V4
7482 && flag_pic == 1
7483 && (reload_in_progress || reload_completed)"
7484 [(set (match_dup 0) (match_dup 2))
7485 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
7486 "")
7487
7488 ;; For SI, we special-case integers that can't be loaded in one insn. We
7489 ;; do the load 16-bits at a time. We could do this by loading from memory,
7490 ;; and this is even supposed to be faster, but it is simpler not to get
7491 ;; integers in the TOC.
7492 (define_expand "movsi"
7493 [(set (match_operand:SI 0 "general_operand" "")
7494 (match_operand:SI 1 "any_operand" ""))]
7495 ""
7496 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7497
7498 (define_insn "movsi_low"
7499 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7500 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7501 (match_operand 2 "" ""))))]
7502 "TARGET_MACHO && ! TARGET_64BIT"
7503 "{l|lwz} %0,lo16(%2)(%1)"
7504 [(set_attr "type" "load")
7505 (set_attr "length" "4")])
7506
7507 (define_insn "movsi_low_st"
7508 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7509 (match_operand 2 "" "")))
7510 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7511 "TARGET_MACHO && ! TARGET_64BIT"
7512 "{st|stw} %0,lo16(%2)(%1)"
7513 [(set_attr "type" "store")
7514 (set_attr "length" "4")])
7515
7516 (define_insn "movdf_low"
7517 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7518 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7519 (match_operand 2 "" ""))))]
7520 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7521 "*
7522 {
7523 switch (which_alternative)
7524 {
7525 case 0:
7526 return \"lfd %0,lo16(%2)(%1)\";
7527 case 1:
7528 {
7529 rtx operands2[4];
7530 operands2[0] = operands[0];
7531 operands2[1] = operands[1];
7532 operands2[2] = operands[2];
7533 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7534 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7535 #if TARGET_MACHO
7536 if (MACHO_DYNAMIC_NO_PIC_P)
7537 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7538 else
7539 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7540 although in practice it almost always is. */
7541 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7542 #endif
7543 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7544 }
7545 default:
7546 abort();
7547 }
7548 }"
7549 [(set_attr "type" "load")
7550 (set_attr "length" "4,12")])
7551
7552 (define_insn "movdf_low_st"
7553 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7554 (match_operand 2 "" "")))
7555 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7556 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7557 "stfd %0,lo16(%2)(%1)"
7558 [(set_attr "type" "store")
7559 (set_attr "length" "4")])
7560
7561 (define_insn "movsf_low"
7562 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7563 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7564 (match_operand 2 "" ""))))]
7565 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7566 "@
7567 lfs %0,lo16(%2)(%1)
7568 {l|lwz} %0,lo16(%2)(%1)"
7569 [(set_attr "type" "load")
7570 (set_attr "length" "4")])
7571
7572 (define_insn "movsf_low_st"
7573 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7574 (match_operand 2 "" "")))
7575 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7576 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7577 "@
7578 stfs %0,lo16(%2)(%1)
7579 {st|stw} %0,lo16(%2)(%1)"
7580 [(set_attr "type" "store")
7581 (set_attr "length" "4")])
7582
7583 (define_insn "*movsi_internal1"
7584 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7585 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7586 "gpc_reg_operand (operands[0], SImode)
7587 || gpc_reg_operand (operands[1], SImode)"
7588 "@
7589 mr %0,%1
7590 {cal|la} %0,%a1
7591 {l%U1%X1|lwz%U1%X1} %0,%1
7592 {st%U0%X0|stw%U0%X0} %1,%0
7593 {lil|li} %0,%1
7594 {liu|lis} %0,%v1
7595 #
7596 {cal|la} %0,%a1
7597 mf%1 %0
7598 mt%0 %1
7599 mt%0 %1
7600 mt%0 %1
7601 {cror 0,0,0|nop}"
7602 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
7603 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7604
7605 ;; Split a load of a large constant into the appropriate two-insn
7606 ;; sequence.
7607
7608 (define_split
7609 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7610 (match_operand:SI 1 "const_int_operand" ""))]
7611 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7612 && (INTVAL (operands[1]) & 0xffff) != 0"
7613 [(set (match_dup 0)
7614 (match_dup 2))
7615 (set (match_dup 0)
7616 (ior:SI (match_dup 0)
7617 (match_dup 3)))]
7618 "
7619 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7620
7621 if (tem == operands[0])
7622 DONE;
7623 else
7624 FAIL;
7625 }")
7626
7627 (define_insn "*movsi_internal2"
7628 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
7629 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
7630 (const_int 0)))
7631 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
7632 "! TARGET_POWERPC64"
7633 "@
7634 mr. %0,%1
7635 #"
7636 [(set_attr "type" "compare")
7637 (set_attr "length" "4,8")])
7638 \f
7639 (define_split
7640 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7641 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7642 (const_int 0)))
7643 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7644 "! TARGET_POWERPC64 && reload_completed"
7645 [(set (match_dup 0) (match_dup 1))
7646 (set (match_dup 2)
7647 (compare:CC (match_dup 0)
7648 (const_int 0)))]
7649 "")
7650
7651 (define_expand "movhi"
7652 [(set (match_operand:HI 0 "general_operand" "")
7653 (match_operand:HI 1 "any_operand" ""))]
7654 ""
7655 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7656
7657 (define_insn "*movhi_internal"
7658 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7659 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7660 "gpc_reg_operand (operands[0], HImode)
7661 || gpc_reg_operand (operands[1], HImode)"
7662 "@
7663 mr %0,%1
7664 lhz%U1%X1 %0,%1
7665 sth%U0%X0 %1,%0
7666 {lil|li} %0,%w1
7667 mf%1 %0
7668 mt%0 %1
7669 mt%0 %1
7670 {cror 0,0,0|nop}"
7671 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7672
7673 (define_expand "movqi"
7674 [(set (match_operand:QI 0 "general_operand" "")
7675 (match_operand:QI 1 "any_operand" ""))]
7676 ""
7677 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7678
7679 (define_insn "*movqi_internal"
7680 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7681 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7682 "gpc_reg_operand (operands[0], QImode)
7683 || gpc_reg_operand (operands[1], QImode)"
7684 "@
7685 mr %0,%1
7686 lbz%U1%X1 %0,%1
7687 stb%U0%X0 %1,%0
7688 {lil|li} %0,%1
7689 mf%1 %0
7690 mt%0 %1
7691 mt%0 %1
7692 {cror 0,0,0|nop}"
7693 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7694 \f
7695 ;; Here is how to move condition codes around. When we store CC data in
7696 ;; an integer register or memory, we store just the high-order 4 bits.
7697 ;; This lets us not shift in the most common case of CR0.
7698 (define_expand "movcc"
7699 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7700 (match_operand:CC 1 "nonimmediate_operand" ""))]
7701 ""
7702 "")
7703
7704 (define_insn "*movcc_internal1"
7705 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7706 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7707 "register_operand (operands[0], CCmode)
7708 || register_operand (operands[1], CCmode)"
7709 "@
7710 mcrf %0,%1
7711 mtcrf 128,%1
7712 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7713 mfcr %0
7714 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7715 mr %0,%1
7716 mf%1 %0
7717 mt%0 %1
7718 mt%0 %1
7719 {l%U1%X1|lwz%U1%X1} %0,%1
7720 {st%U0%U1|stw%U0%U1} %1,%0"
7721 [(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,*,*,mtjmpr,load,store")
7722 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7723 \f
7724 ;; For floating-point, we normally deal with the floating-point registers
7725 ;; unless -msoft-float is used. The sole exception is that parameter passing
7726 ;; can produce floating-point values in fixed-point registers. Unless the
7727 ;; value is a simple constant or already in memory, we deal with this by
7728 ;; allocating memory and copying the value explicitly via that memory location.
7729 (define_expand "movsf"
7730 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7731 (match_operand:SF 1 "any_operand" ""))]
7732 ""
7733 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7734
7735 (define_split
7736 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7737 (match_operand:SF 1 "const_double_operand" ""))]
7738 "reload_completed
7739 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7740 || (GET_CODE (operands[0]) == SUBREG
7741 && GET_CODE (SUBREG_REG (operands[0])) == REG
7742 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7743 [(set (match_dup 2) (match_dup 3))]
7744 "
7745 {
7746 long l;
7747 REAL_VALUE_TYPE rv;
7748
7749 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7750 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7751
7752 if (! TARGET_POWERPC64)
7753 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7754 else
7755 operands[2] = gen_lowpart (SImode, operands[0]);
7756
7757 operands[3] = gen_int_mode (l, SImode);
7758 }")
7759
7760 (define_insn "*movsf_hardfloat"
7761 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
7762 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
7763 "(gpc_reg_operand (operands[0], SFmode)
7764 || gpc_reg_operand (operands[1], SFmode))
7765 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7766 "@
7767 mr %0,%1
7768 {l%U1%X1|lwz%U1%X1} %0,%1
7769 {st%U0%X0|stw%U0%X0} %1,%0
7770 fmr %0,%1
7771 lfs%U1%X1 %0,%1
7772 stfs%U0%X0 %1,%0
7773 mt%0 %1
7774 mt%0 %1
7775 mf%1 %0
7776 #
7777 #"
7778 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
7779 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7780
7781 (define_insn "*movsf_softfloat"
7782 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r")
7783 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn"))]
7784 "(gpc_reg_operand (operands[0], SFmode)
7785 || gpc_reg_operand (operands[1], SFmode))
7786 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7787 "@
7788 mr %0,%1
7789 mt%0 %1
7790 mt%0 %1
7791 mf%1 %0
7792 {l%U1%X1|lwz%U1%X1} %0,%1
7793 {st%U0%X0|stw%U0%X0} %1,%0
7794 {lil|li} %0,%1
7795 {liu|lis} %0,%v1
7796 {cal|la} %0,%a1
7797 #
7798 #"
7799 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*")
7800 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7801
7802 \f
7803 (define_expand "movdf"
7804 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7805 (match_operand:DF 1 "any_operand" ""))]
7806 ""
7807 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7808
7809 (define_split
7810 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7811 (match_operand:DF 1 "const_int_operand" ""))]
7812 "! TARGET_POWERPC64 && reload_completed
7813 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7814 || (GET_CODE (operands[0]) == SUBREG
7815 && GET_CODE (SUBREG_REG (operands[0])) == REG
7816 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7817 [(set (match_dup 2) (match_dup 4))
7818 (set (match_dup 3) (match_dup 1))]
7819 "
7820 {
7821 int endian = (WORDS_BIG_ENDIAN == 0);
7822 HOST_WIDE_INT value = INTVAL (operands[1]);
7823
7824 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7825 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7826 #if HOST_BITS_PER_WIDE_INT == 32
7827 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7828 #else
7829 operands[4] = GEN_INT (value >> 32);
7830 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7831 #endif
7832 }")
7833
7834 (define_split
7835 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7836 (match_operand:DF 1 "const_double_operand" ""))]
7837 "! TARGET_POWERPC64 && reload_completed
7838 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7839 || (GET_CODE (operands[0]) == SUBREG
7840 && GET_CODE (SUBREG_REG (operands[0])) == REG
7841 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7842 [(set (match_dup 2) (match_dup 4))
7843 (set (match_dup 3) (match_dup 5))]
7844 "
7845 {
7846 int endian = (WORDS_BIG_ENDIAN == 0);
7847 long l[2];
7848 REAL_VALUE_TYPE rv;
7849
7850 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7851 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7852
7853 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7854 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7855 operands[4] = gen_int_mode (l[endian], SImode);
7856 operands[5] = gen_int_mode (l[1 - endian], SImode);
7857 }")
7858
7859 (define_split
7860 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7861 (match_operand:DF 1 "easy_fp_constant" ""))]
7862 "TARGET_POWERPC64 && reload_completed
7863 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7864 || (GET_CODE (operands[0]) == SUBREG
7865 && GET_CODE (SUBREG_REG (operands[0])) == REG
7866 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7867 [(set (match_dup 2) (match_dup 3))]
7868 "
7869 {
7870 int endian = (WORDS_BIG_ENDIAN == 0);
7871 long l[2];
7872 REAL_VALUE_TYPE rv;
7873 #if HOST_BITS_PER_WIDE_INT >= 64
7874 HOST_WIDE_INT val;
7875 #endif
7876
7877 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7878 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7879
7880 operands[2] = gen_lowpart (DImode, operands[0]);
7881 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7882 #if HOST_BITS_PER_WIDE_INT >= 64
7883 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7884 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7885
7886 operands[3] = gen_int_mode (val, DImode);
7887 #else
7888 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7889 #endif
7890 }")
7891
7892 ;; Don't have reload use general registers to load a constant. First,
7893 ;; it might not work if the output operand is the equivalent of
7894 ;; a non-offsettable memref, but also it is less efficient than loading
7895 ;; the constant into an FP register, since it will probably be used there.
7896 ;; The "??" is a kludge until we can figure out a more reasonable way
7897 ;; of handling these non-offsettable values.
7898 (define_insn "*movdf_hardfloat32"
7899 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7900 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7901 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7902 && (gpc_reg_operand (operands[0], DFmode)
7903 || gpc_reg_operand (operands[1], DFmode))"
7904 "*
7905 {
7906 switch (which_alternative)
7907 {
7908 default:
7909 abort ();
7910 case 0:
7911 /* We normally copy the low-numbered register first. However, if
7912 the first register operand 0 is the same as the second register
7913 of operand 1, we must copy in the opposite order. */
7914 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7915 return \"mr %L0,%L1\;mr %0,%1\";
7916 else
7917 return \"mr %0,%1\;mr %L0,%L1\";
7918 case 1:
7919 if (offsettable_memref_p (operands[1])
7920 || (GET_CODE (operands[1]) == MEM
7921 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7922 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7923 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
7924 {
7925 /* If the low-address word is used in the address, we must load
7926 it last. Otherwise, load it first. Note that we cannot have
7927 auto-increment in that case since the address register is
7928 known to be dead. */
7929 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7930 operands[1], 0))
7931 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7932 else
7933 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7934 }
7935 else
7936 {
7937 rtx addreg;
7938
7939 addreg = find_addr_reg (XEXP (operands[1], 0));
7940 if (refers_to_regno_p (REGNO (operands[0]),
7941 REGNO (operands[0]) + 1,
7942 operands[1], 0))
7943 {
7944 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7945 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7946 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7947 return \"{lx|lwzx} %0,%1\";
7948 }
7949 else
7950 {
7951 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7952 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7953 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7954 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7955 return \"\";
7956 }
7957 }
7958 case 2:
7959 if (offsettable_memref_p (operands[0])
7960 || (GET_CODE (operands[0]) == MEM
7961 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7962 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7963 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
7964 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7965 else
7966 {
7967 rtx addreg;
7968
7969 addreg = find_addr_reg (XEXP (operands[0], 0));
7970 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7971 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7972 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7973 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7974 return \"\";
7975 }
7976 case 3:
7977 return \"fmr %0,%1\";
7978 case 4:
7979 return \"lfd%U1%X1 %0,%1\";
7980 case 5:
7981 return \"stfd%U0%X0 %1,%0\";
7982 case 6:
7983 case 7:
7984 case 8:
7985 return \"#\";
7986 }
7987 }"
7988 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
7989 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7990
7991 (define_insn "*movdf_softfloat32"
7992 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7993 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7994 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7995 && (gpc_reg_operand (operands[0], DFmode)
7996 || gpc_reg_operand (operands[1], DFmode))"
7997 "*
7998 {
7999 switch (which_alternative)
8000 {
8001 default:
8002 abort ();
8003 case 0:
8004 /* We normally copy the low-numbered register first. However, if
8005 the first register operand 0 is the same as the second register of
8006 operand 1, we must copy in the opposite order. */
8007 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8008 return \"mr %L0,%L1\;mr %0,%1\";
8009 else
8010 return \"mr %0,%1\;mr %L0,%L1\";
8011 case 1:
8012 /* If the low-address word is used in the address, we must load
8013 it last. Otherwise, load it first. Note that we cannot have
8014 auto-increment in that case since the address register is
8015 known to be dead. */
8016 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8017 operands[1], 0))
8018 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8019 else
8020 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8021 case 2:
8022 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8023 case 3:
8024 case 4:
8025 case 5:
8026 return \"#\";
8027 }
8028 }"
8029 [(set_attr "type" "*,load,store,*,*,*")
8030 (set_attr "length" "8,8,8,8,12,16")])
8031
8032 (define_insn "*movdf_hardfloat64"
8033 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r")
8034 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))]
8035 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8036 && (gpc_reg_operand (operands[0], DFmode)
8037 || gpc_reg_operand (operands[1], DFmode))"
8038 "@
8039 mr %0,%1
8040 ld%U1%X1 %0,%1
8041 std%U0%X0 %1,%0
8042 fmr %0,%1
8043 lfd%U1%X1 %0,%1
8044 stfd%U0%X0 %1,%0
8045 mt%0 %1
8046 mf%1 %0
8047 #
8048 #
8049 #"
8050 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8051 (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
8052
8053 (define_insn "*movdf_softfloat64"
8054 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r")
8055 (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))]
8056 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8057 && (gpc_reg_operand (operands[0], DFmode)
8058 || gpc_reg_operand (operands[1], DFmode))"
8059 "@
8060 mr %0,%1
8061 mt%0 %1
8062 mf%1 %0
8063 ld%U1%X1 %0,%1
8064 std%U0%X0 %1,%0
8065 #
8066 #
8067 #"
8068 [(set_attr "type" "*,*,*,load,store,*,*,*")
8069 (set_attr "length" "4,4,4,4,4,8,12,16")])
8070 \f
8071 (define_expand "movtf"
8072 [(set (match_operand:TF 0 "general_operand" "")
8073 (match_operand:TF 1 "any_operand" ""))]
8074 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8075 && TARGET_LONG_DOUBLE_128"
8076 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8077
8078 (define_insn "*movtf_internal"
8079 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r")
8080 (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))]
8081 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8082 && TARGET_LONG_DOUBLE_128
8083 && (gpc_reg_operand (operands[0], TFmode)
8084 || gpc_reg_operand (operands[1], TFmode))"
8085 "*
8086 {
8087 switch (which_alternative)
8088 {
8089 default:
8090 abort ();
8091 case 0:
8092 /* We normally copy the low-numbered register first. However, if
8093 the first register operand 0 is the same as the second register of
8094 operand 1, we must copy in the opposite order. */
8095 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8096 return \"fmr %L0,%L1\;fmr %0,%1\";
8097 else
8098 return \"fmr %0,%1\;fmr %L0,%L1\";
8099 case 1:
8100 return \"lfd %0,%1\;lfd %L0,%Y1\";
8101 case 2:
8102 return \"stfd %1,%0\;stfd %L1,%Y0\";
8103 case 3:
8104 case 4:
8105 case 5:
8106 return \"#\";
8107 }
8108 }"
8109 [(set_attr "type" "fp,fpload,fpstore,*,*,*")
8110 (set_attr "length" "8,8,8,12,16,20")])
8111
8112 (define_split
8113 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8114 (match_operand:TF 1 "easy_fp_constant" ""))]
8115 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8116 && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64
8117 && TARGET_LONG_DOUBLE_128 && reload_completed
8118 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8119 || (GET_CODE (operands[0]) == SUBREG
8120 && GET_CODE (SUBREG_REG (operands[0])) == REG
8121 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8122 [(set (match_dup 2) (match_dup 6))
8123 (set (match_dup 3) (match_dup 7))
8124 (set (match_dup 4) (match_dup 8))
8125 (set (match_dup 5) (match_dup 9))]
8126 "
8127 {
8128 long l[4];
8129 REAL_VALUE_TYPE rv;
8130
8131 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8132 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8133
8134 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
8135 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
8136 operands[4] = operand_subword (operands[0], 2, 0, TFmode);
8137 operands[5] = operand_subword (operands[0], 3, 0, TFmode);
8138 operands[6] = gen_int_mode (l[0], SImode);
8139 operands[7] = gen_int_mode (l[1], SImode);
8140 operands[8] = gen_int_mode (l[2], SImode);
8141 operands[9] = gen_int_mode (l[3], SImode);
8142 }")
8143
8144 (define_split
8145 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8146 (match_operand:TF 1 "easy_fp_constant" ""))]
8147 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8148 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8149 && TARGET_LONG_DOUBLE_128 && reload_completed
8150 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8151 || (GET_CODE (operands[0]) == SUBREG
8152 && GET_CODE (SUBREG_REG (operands[0])) == REG
8153 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8154 [(set (match_dup 2) (match_dup 4))
8155 (set (match_dup 3) (match_dup 5))]
8156 "
8157 {
8158 long l[4];
8159 REAL_VALUE_TYPE rv;
8160 #if HOST_BITS_PER_WIDE_INT >= 64
8161 HOST_WIDE_INT val;
8162 #endif
8163
8164 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8165 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8166
8167 operands[2] = gen_lowpart (DImode, operands[0]);
8168 operands[3] = gen_highpart (DImode, operands[0]);
8169 #if HOST_BITS_PER_WIDE_INT >= 64
8170 val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32
8171 | ((HOST_WIDE_INT)(unsigned long)l[1]));
8172 operands[4] = gen_int_mode (val, DImode);
8173
8174 val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32
8175 | ((HOST_WIDE_INT)(unsigned long)l[3]));
8176 operands[5] = gen_int_mode (val, DImode);
8177 #else
8178 operands[4] = immed_double_const (l[1], l[0], DImode);
8179 operands[5] = immed_double_const (l[3], l[2], DImode);
8180 #endif
8181 }")
8182
8183 (define_insn "extenddftf2"
8184 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8185 (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
8186 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8187 && TARGET_LONG_DOUBLE_128"
8188 "*
8189 {
8190 if (REGNO (operands[0]) == REGNO (operands[1]))
8191 return \"fsub %L0,%L0,%L0\";
8192 else
8193 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8194 }"
8195 [(set_attr "type" "fp")])
8196
8197 (define_insn "extendsftf2"
8198 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8199 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
8200 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8201 && TARGET_LONG_DOUBLE_128"
8202 "*
8203 {
8204 if (REGNO (operands[0]) == REGNO (operands[1]))
8205 return \"fsub %L0,%L0,%L0\";
8206 else
8207 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8208 }"
8209 [(set_attr "type" "fp")])
8210
8211 (define_insn "trunctfdf2"
8212 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8213 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8214 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8215 && TARGET_LONG_DOUBLE_128"
8216 "fadd %0,%1,%L1"
8217 [(set_attr "type" "fp")
8218 (set_attr "length" "8")])
8219
8220 (define_insn_and_split "trunctfsf2"
8221 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8222 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8223 (clobber (match_scratch:DF 2 "=f"))]
8224 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
8225 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8226 "#"
8227 "&& reload_completed"
8228 [(set (match_dup 2)
8229 (float_truncate:DF (match_dup 1)))
8230 (set (match_dup 0)
8231 (float_truncate:SF (match_dup 2)))]
8232 "")
8233
8234 (define_insn_and_split "floatditf2"
8235 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8236 (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
8237 (clobber (match_scratch:DF 2 "=f"))]
8238 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
8239 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8240 "#"
8241 "&& reload_completed"
8242 [(set (match_dup 2)
8243 (float:DF (match_dup 1)))
8244 (set (match_dup 0)
8245 (float_extend:TF (match_dup 2)))]
8246 "")
8247
8248 (define_insn_and_split "floatsitf2"
8249 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8250 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
8251 (clobber (match_scratch:DF 2 "=f"))]
8252 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8253 && TARGET_LONG_DOUBLE_128"
8254 "#"
8255 "&& reload_completed"
8256 [(set (match_dup 2)
8257 (float:DF (match_dup 1)))
8258 (set (match_dup 0)
8259 (float_extend:TF (match_dup 2)))]
8260 "")
8261
8262 (define_insn_and_split "fix_trunctfdi2"
8263 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
8264 (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))
8265 (clobber (match_scratch:DF 2 "=f"))]
8266 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
8267 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8268 "#"
8269 "&& reload_completed"
8270 [(set (match_dup 2)
8271 (float_truncate:DF (match_dup 1)))
8272 (set (match_dup 0)
8273 (fix:DI (match_dup 2)))]
8274 "")
8275
8276 (define_insn_and_split "fix_trunctfsi2"
8277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8278 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8279 (clobber (match_scratch:DF 2 "=f"))]
8280 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8281 && TARGET_LONG_DOUBLE_128"
8282 "#"
8283 "&& reload_completed"
8284 [(set (match_dup 2)
8285 (float_truncate:DF (match_dup 1)))
8286 (set (match_dup 0)
8287 (fix:SI (match_dup 2)))]
8288 "")
8289
8290 (define_insn "negtf2"
8291 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8292 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8293 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8294 && TARGET_LONG_DOUBLE_128"
8295 "*
8296 {
8297 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8298 return \"fneg %L0,%L1\;fneg %0,%1\";
8299 else
8300 return \"fneg %0,%1\;fneg %L0,%L1\";
8301 }"
8302 [(set_attr "type" "fp")
8303 (set_attr "length" "8")])
8304
8305 (define_insn "abstf2"
8306 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8307 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8308 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8309 && TARGET_LONG_DOUBLE_128"
8310 "*
8311 {
8312 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8313 return \"fabs %L0,%L1\;fabs %0,%1\";
8314 else
8315 return \"fabs %0,%1\;fabs %L0,%L1\";
8316 }"
8317 [(set_attr "type" "fp")
8318 (set_attr "length" "8")])
8319
8320 (define_insn ""
8321 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8322 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
8323 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8324 && TARGET_LONG_DOUBLE_128"
8325 "*
8326 {
8327 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8328 return \"fnabs %L0,%L1\;fnabs %0,%1\";
8329 else
8330 return \"fnabs %0,%1\;fnabs %L0,%L1\";
8331 }"
8332 [(set_attr "type" "fp")
8333 (set_attr "length" "8")])
8334 \f
8335 ;; Next come the multi-word integer load and store and the load and store
8336 ;; multiple insns.
8337 (define_expand "movdi"
8338 [(set (match_operand:DI 0 "general_operand" "")
8339 (match_operand:DI 1 "any_operand" ""))]
8340 ""
8341 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8342
8343 (define_insn "*movdi_internal32"
8344 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8345 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8346 "! TARGET_POWERPC64
8347 && (gpc_reg_operand (operands[0], DImode)
8348 || gpc_reg_operand (operands[1], DImode))"
8349 "*
8350 {
8351 switch (which_alternative)
8352 {
8353 default:
8354 abort ();
8355 case 0:
8356 /* We normally copy the low-numbered register first. However, if
8357 the first register operand 0 is the same as the second register of
8358 operand 1, we must copy in the opposite order. */
8359 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8360 return \"mr %L0,%L1\;mr %0,%1\";
8361 else
8362 return \"mr %0,%1\;mr %L0,%L1\";
8363 case 1:
8364 /* If the low-address word is used in the address, we must load it
8365 last. Otherwise, load it first. Note that we cannot have
8366 auto-increment in that case since the address register is known to be
8367 dead. */
8368 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8369 operands[1], 0))
8370 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8371 else
8372 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8373 case 2:
8374 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8375 case 3:
8376 return \"fmr %0,%1\";
8377 case 4:
8378 return \"lfd%U1%X1 %0,%1\";
8379 case 5:
8380 return \"stfd%U0%X0 %1,%0\";
8381 case 6:
8382 case 7:
8383 case 8:
8384 case 9:
8385 case 10:
8386 return \"#\";
8387 }
8388 }"
8389 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
8390 (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")])
8391
8392 (define_split
8393 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8394 (match_operand:DI 1 "const_int_operand" ""))]
8395 "! TARGET_POWERPC64 && reload_completed"
8396 [(set (match_dup 2) (match_dup 4))
8397 (set (match_dup 3) (match_dup 1))]
8398 "
8399 {
8400 HOST_WIDE_INT value = INTVAL (operands[1]);
8401 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8402 DImode);
8403 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8404 DImode);
8405 #if HOST_BITS_PER_WIDE_INT == 32
8406 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8407 #else
8408 operands[4] = GEN_INT (value >> 32);
8409 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8410 #endif
8411 }")
8412
8413 (define_split
8414 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8415 (match_operand:DI 1 "const_double_operand" ""))]
8416 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
8417 [(set (match_dup 2) (match_dup 4))
8418 (set (match_dup 3) (match_dup 5))]
8419 "
8420 {
8421 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8422 DImode);
8423 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8424 DImode);
8425 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8426 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8427 }")
8428
8429 (define_split
8430 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8431 (match_operand:TI 1 "const_double_operand" ""))]
8432 "TARGET_POWERPC64"
8433 [(set (match_dup 2) (match_dup 4))
8434 (set (match_dup 3) (match_dup 5))]
8435 "
8436 {
8437 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8438 TImode);
8439 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8440 TImode);
8441 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8442 {
8443 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8444 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8445 }
8446 else if (GET_CODE (operands[1]) == CONST_INT)
8447 {
8448 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8449 operands[5] = operands[1];
8450 }
8451 else
8452 FAIL;
8453 }")
8454
8455 (define_insn "*movdi_internal64"
8456 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
8457 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8458 "TARGET_POWERPC64
8459 && (gpc_reg_operand (operands[0], DImode)
8460 || gpc_reg_operand (operands[1], DImode))"
8461 "@
8462 mr %0,%1
8463 ld%U1%X1 %0,%1
8464 std%U0%X0 %1,%0
8465 li %0,%1
8466 lis %0,%v1
8467 #
8468 {cal|la} %0,%a1
8469 fmr %0,%1
8470 lfd%U1%X1 %0,%1
8471 stfd%U0%X0 %1,%0
8472 mf%1 %0
8473 mt%0 %1
8474 {cror 0,0,0|nop}"
8475 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
8476 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8477
8478 ;; immediate value valid for a single instruction hiding in a const_double
8479 (define_insn ""
8480 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8481 (match_operand:DI 1 "const_double_operand" "F"))]
8482 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8483 && GET_CODE (operands[1]) == CONST_DOUBLE
8484 && num_insns_constant (operands[1], DImode) == 1"
8485 "*
8486 {
8487 return ((unsigned HOST_WIDE_INT)
8488 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8489 ? \"li %0,%1\" : \"lis %0,%v1\";
8490 }")
8491
8492 ;; Generate all one-bits and clear left or right.
8493 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8494 (define_split
8495 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8496 (match_operand:DI 1 "mask64_operand" ""))]
8497 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8498 [(set (match_dup 0) (const_int -1))
8499 (set (match_dup 0)
8500 (and:DI (rotate:DI (match_dup 0)
8501 (const_int 0))
8502 (match_dup 1)))]
8503 "")
8504
8505 ;; Split a load of a large constant into the appropriate five-instruction
8506 ;; sequence. Handle anything in a constant number of insns.
8507 ;; When non-easy constants can go in the TOC, this should use
8508 ;; easy_fp_constant predicate.
8509 (define_split
8510 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8511 (match_operand:DI 1 "const_int_operand" ""))]
8512 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8513 [(set (match_dup 0) (match_dup 2))
8514 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8515 "
8516 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8517
8518 if (tem == operands[0])
8519 DONE;
8520 else
8521 FAIL;
8522 }")
8523
8524 (define_split
8525 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8526 (match_operand:DI 1 "const_double_operand" ""))]
8527 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8528 [(set (match_dup 0) (match_dup 2))
8529 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8530 "
8531 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8532
8533 if (tem == operands[0])
8534 DONE;
8535 else
8536 FAIL;
8537 }")
8538
8539 ;; Split a load of a large constant into the appropriate five-instruction
8540 (define_insn "*movdi_internal2"
8541 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8542 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
8543 (const_int 0)))
8544 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8545 "TARGET_POWERPC64"
8546 "@
8547 mr. %0,%1
8548 #"
8549 [(set_attr "type" "compare")
8550 (set_attr "length" "4,8")])
8551
8552 (define_split
8553 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8554 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8555 (const_int 0)))
8556 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8557 "TARGET_POWERPC64 && reload_completed"
8558 [(set (match_dup 0) (match_dup 1))
8559 (set (match_dup 2)
8560 (compare:CC (match_dup 0)
8561 (const_int 0)))]
8562 "")
8563 \f
8564 ;; TImode is similar, except that we usually want to compute the address into
8565 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8566 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8567 (define_expand "movti"
8568 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8569 (match_operand:TI 1 "general_operand" ""))
8570 (clobber (scratch:SI))])]
8571 "TARGET_STRING || TARGET_POWERPC64"
8572 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8573
8574 ;; We say that MQ is clobbered in the last alternative because the first
8575 ;; alternative would never get used otherwise since it would need a reload
8576 ;; while the 2nd alternative would not. We put memory cases first so they
8577 ;; are preferred. Otherwise, we'd try to reload the output instead of
8578 ;; giving the SCRATCH mq.
8579 (define_insn "*movti_power"
8580 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8581 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8582 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8583 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8584 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8585 "*
8586 {
8587 switch (which_alternative)
8588 {
8589 default:
8590 abort ();
8591
8592 case 0:
8593 return \"{stsi|stswi} %1,%P0,16\";
8594 case 1:
8595 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8596 case 2:
8597 /* Normally copy registers with lowest numbered register copied first.
8598 But copy in the other order if the first register of the output
8599 is the second, third, or fourth register in the input. */
8600 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8601 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8602 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8603 else
8604 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8605 case 3:
8606 /* If the address is not used in the output, we can use lsi. Otherwise,
8607 fall through to generating four loads. */
8608 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8609 return \"{lsi|lswi} %0,%P1,16\";
8610 /* ... fall through ... */
8611 case 4:
8612 /* If the address register is the same as the register for the lowest-
8613 addressed word, load it last. Similarly for the next two words.
8614 Otherwise load lowest address to highest. */
8615 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8616 operands[1], 0))
8617 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8618 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8619 REGNO (operands[0]) + 2, operands[1], 0))
8620 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8621 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8622 REGNO (operands[0]) + 3, operands[1], 0))
8623 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8624 else
8625 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8626 }
8627 }"
8628 [(set_attr "type" "store,store,*,load,load")
8629 (set_attr "length" "4,16,16,4,16")])
8630
8631 (define_insn "*movti_string"
8632 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8633 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8634 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8635 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8636 "*
8637 {
8638 switch (which_alternative)
8639 {
8640 default:
8641 abort ();
8642
8643 case 0:
8644 return \"{stsi|stswi} %1,%P0,16\";
8645 case 1:
8646 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8647 case 2:
8648 /* Normally copy registers with lowest numbered register copied first.
8649 But copy in the other order if the first register of the output
8650 is the second, third, or fourth register in the input. */
8651 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8652 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8653 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8654 else
8655 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8656 case 3:
8657 /* If the address is not used in the output, we can use lsi. Otherwise,
8658 fall through to generating four loads. */
8659 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8660 return \"{lsi|lswi} %0,%P1,16\";
8661 /* ... fall through ... */
8662 case 4:
8663 /* If the address register is the same as the register for the lowest-
8664 addressed word, load it last. Similarly for the next two words.
8665 Otherwise load lowest address to highest. */
8666 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8667 operands[1], 0))
8668 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8669 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8670 REGNO (operands[0]) + 2, operands[1], 0))
8671 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8672 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8673 REGNO (operands[0]) + 3, operands[1], 0))
8674 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8675 else
8676 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8677 }
8678 }"
8679 [(set_attr "type" "store,store,*,load,load")
8680 (set_attr "length" "4,16,16,4,16")])
8681
8682 (define_insn "*movti_ppc64"
8683 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
8684 (match_operand:TI 1 "input_operand" "r,m,r"))]
8685 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8686 || gpc_reg_operand (operands[1], TImode))"
8687 "*
8688 {
8689 switch (which_alternative)
8690 {
8691 default:
8692 abort ();
8693 case 0:
8694 /* We normally copy the low-numbered register first. However, if
8695 the first register operand 0 is the same as the second register of
8696 operand 1, we must copy in the opposite order. */
8697 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8698 return \"mr %L0,%L1\;mr %0,%1\";
8699 else
8700 return \"mr %0,%1\;mr %L0,%L1\";
8701 case 1:
8702 /* If the low-address word is used in the address, we must load it
8703 last. Otherwise, load it first. Note that we cannot have
8704 auto-increment in that case since the address register is known to be
8705 dead. */
8706 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8707 operands[1], 0))
8708 return \"ld %L0,%L1\;ld %0,%1\";
8709 else
8710 return \"ld%U1 %0,%1\;ld %L0,%L1\";
8711 case 2:
8712 return \"std%U0 %1,%0\;std %L1,%L0\";
8713 }
8714 }"
8715 [(set_attr "type" "*,load,store")
8716 (set_attr "length" "8,8,8")])
8717 \f
8718 (define_expand "load_multiple"
8719 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8720 (match_operand:SI 1 "" ""))
8721 (use (match_operand:SI 2 "" ""))])]
8722 "TARGET_STRING && !TARGET_POWERPC64"
8723 "
8724 {
8725 int regno;
8726 int count;
8727 rtx op1;
8728 int i;
8729
8730 /* Support only loading a constant number of fixed-point registers from
8731 memory and only bother with this if more than two; the machine
8732 doesn't support more than eight. */
8733 if (GET_CODE (operands[2]) != CONST_INT
8734 || INTVAL (operands[2]) <= 2
8735 || INTVAL (operands[2]) > 8
8736 || GET_CODE (operands[1]) != MEM
8737 || GET_CODE (operands[0]) != REG
8738 || REGNO (operands[0]) >= 32)
8739 FAIL;
8740
8741 count = INTVAL (operands[2]);
8742 regno = REGNO (operands[0]);
8743
8744 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8745 op1 = replace_equiv_address (operands[1],
8746 force_reg (SImode, XEXP (operands[1], 0)));
8747
8748 for (i = 0; i < count; i++)
8749 XVECEXP (operands[3], 0, i)
8750 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8751 adjust_address_nv (op1, SImode, i * 4));
8752 }")
8753
8754 (define_insn "*ldmsi8"
8755 [(match_parallel 0 "load_multiple_operation"
8756 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8757 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8758 (set (match_operand:SI 3 "gpc_reg_operand" "")
8759 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8760 (set (match_operand:SI 4 "gpc_reg_operand" "")
8761 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8762 (set (match_operand:SI 5 "gpc_reg_operand" "")
8763 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8764 (set (match_operand:SI 6 "gpc_reg_operand" "")
8765 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8766 (set (match_operand:SI 7 "gpc_reg_operand" "")
8767 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8768 (set (match_operand:SI 8 "gpc_reg_operand" "")
8769 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8770 (set (match_operand:SI 9 "gpc_reg_operand" "")
8771 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8772 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8773 "*
8774 { return rs6000_output_load_multiple (operands); }"
8775 [(set_attr "type" "load")
8776 (set_attr "length" "32")])
8777
8778 (define_insn "*ldmsi7"
8779 [(match_parallel 0 "load_multiple_operation"
8780 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8781 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8782 (set (match_operand:SI 3 "gpc_reg_operand" "")
8783 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8784 (set (match_operand:SI 4 "gpc_reg_operand" "")
8785 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8786 (set (match_operand:SI 5 "gpc_reg_operand" "")
8787 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8788 (set (match_operand:SI 6 "gpc_reg_operand" "")
8789 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8790 (set (match_operand:SI 7 "gpc_reg_operand" "")
8791 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8792 (set (match_operand:SI 8 "gpc_reg_operand" "")
8793 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8794 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8795 "*
8796 { return rs6000_output_load_multiple (operands); }"
8797 [(set_attr "type" "load")
8798 (set_attr "length" "32")])
8799
8800 (define_insn "*ldmsi6"
8801 [(match_parallel 0 "load_multiple_operation"
8802 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8803 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8804 (set (match_operand:SI 3 "gpc_reg_operand" "")
8805 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8806 (set (match_operand:SI 4 "gpc_reg_operand" "")
8807 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8808 (set (match_operand:SI 5 "gpc_reg_operand" "")
8809 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8810 (set (match_operand:SI 6 "gpc_reg_operand" "")
8811 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8812 (set (match_operand:SI 7 "gpc_reg_operand" "")
8813 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8814 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8815 "*
8816 { return rs6000_output_load_multiple (operands); }"
8817 [(set_attr "type" "load")
8818 (set_attr "length" "32")])
8819
8820 (define_insn "*ldmsi5"
8821 [(match_parallel 0 "load_multiple_operation"
8822 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8823 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8824 (set (match_operand:SI 3 "gpc_reg_operand" "")
8825 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8826 (set (match_operand:SI 4 "gpc_reg_operand" "")
8827 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8828 (set (match_operand:SI 5 "gpc_reg_operand" "")
8829 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8830 (set (match_operand:SI 6 "gpc_reg_operand" "")
8831 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8832 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8833 "*
8834 { return rs6000_output_load_multiple (operands); }"
8835 [(set_attr "type" "load")
8836 (set_attr "length" "32")])
8837
8838 (define_insn "*ldmsi4"
8839 [(match_parallel 0 "load_multiple_operation"
8840 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8841 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8842 (set (match_operand:SI 3 "gpc_reg_operand" "")
8843 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8844 (set (match_operand:SI 4 "gpc_reg_operand" "")
8845 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8846 (set (match_operand:SI 5 "gpc_reg_operand" "")
8847 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8848 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8849 "*
8850 { return rs6000_output_load_multiple (operands); }"
8851 [(set_attr "type" "load")
8852 (set_attr "length" "32")])
8853
8854 (define_insn "*ldmsi3"
8855 [(match_parallel 0 "load_multiple_operation"
8856 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8857 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8858 (set (match_operand:SI 3 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8860 (set (match_operand:SI 4 "gpc_reg_operand" "")
8861 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8862 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8863 "*
8864 { return rs6000_output_load_multiple (operands); }"
8865 [(set_attr "type" "load")
8866 (set_attr "length" "32")])
8867
8868 (define_expand "store_multiple"
8869 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8870 (match_operand:SI 1 "" ""))
8871 (clobber (scratch:SI))
8872 (use (match_operand:SI 2 "" ""))])]
8873 "TARGET_STRING && !TARGET_POWERPC64"
8874 "
8875 {
8876 int regno;
8877 int count;
8878 rtx to;
8879 rtx op0;
8880 int i;
8881
8882 /* Support only storing a constant number of fixed-point registers to
8883 memory and only bother with this if more than two; the machine
8884 doesn't support more than eight. */
8885 if (GET_CODE (operands[2]) != CONST_INT
8886 || INTVAL (operands[2]) <= 2
8887 || INTVAL (operands[2]) > 8
8888 || GET_CODE (operands[0]) != MEM
8889 || GET_CODE (operands[1]) != REG
8890 || REGNO (operands[1]) >= 32)
8891 FAIL;
8892
8893 count = INTVAL (operands[2]);
8894 regno = REGNO (operands[1]);
8895
8896 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8897 to = force_reg (SImode, XEXP (operands[0], 0));
8898 op0 = replace_equiv_address (operands[0], to);
8899
8900 XVECEXP (operands[3], 0, 0)
8901 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8902 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8903 gen_rtx_SCRATCH (SImode));
8904
8905 for (i = 1; i < count; i++)
8906 XVECEXP (operands[3], 0, i + 1)
8907 = gen_rtx_SET (VOIDmode,
8908 adjust_address_nv (op0, SImode, i * 4),
8909 gen_rtx_REG (SImode, regno + i));
8910 }")
8911
8912 (define_insn "*store_multiple_power"
8913 [(match_parallel 0 "store_multiple_operation"
8914 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8915 (match_operand:SI 2 "gpc_reg_operand" "r"))
8916 (clobber (match_scratch:SI 3 "=q"))])]
8917 "TARGET_STRING && TARGET_POWER"
8918 "{stsi|stswi} %2,%P1,%O0"
8919 [(set_attr "type" "store")])
8920
8921 (define_insn "*stmsi8"
8922 [(match_parallel 0 "store_multiple_operation"
8923 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8924 (match_operand:SI 2 "gpc_reg_operand" "r"))
8925 (clobber (match_scratch:SI 3 "X"))
8926 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8927 (match_operand:SI 4 "gpc_reg_operand" "r"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8929 (match_operand:SI 5 "gpc_reg_operand" "r"))
8930 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8931 (match_operand:SI 6 "gpc_reg_operand" "r"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8933 (match_operand:SI 7 "gpc_reg_operand" "r"))
8934 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8935 (match_operand:SI 8 "gpc_reg_operand" "r"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8937 (match_operand:SI 9 "gpc_reg_operand" "r"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8939 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8940 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8941 "{stsi|stswi} %2,%1,%O0"
8942 [(set_attr "type" "store")])
8943
8944 (define_insn "*stmsi7"
8945 [(match_parallel 0 "store_multiple_operation"
8946 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8947 (match_operand:SI 2 "gpc_reg_operand" "r"))
8948 (clobber (match_scratch:SI 3 "X"))
8949 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8950 (match_operand:SI 4 "gpc_reg_operand" "r"))
8951 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8952 (match_operand:SI 5 "gpc_reg_operand" "r"))
8953 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8954 (match_operand:SI 6 "gpc_reg_operand" "r"))
8955 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8956 (match_operand:SI 7 "gpc_reg_operand" "r"))
8957 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8958 (match_operand:SI 8 "gpc_reg_operand" "r"))
8959 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8960 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8961 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8962 "{stsi|stswi} %2,%1,%O0"
8963 [(set_attr "type" "store")])
8964
8965 (define_insn "*stmsi6"
8966 [(match_parallel 0 "store_multiple_operation"
8967 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8968 (match_operand:SI 2 "gpc_reg_operand" "r"))
8969 (clobber (match_scratch:SI 3 "X"))
8970 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8971 (match_operand:SI 4 "gpc_reg_operand" "r"))
8972 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8973 (match_operand:SI 5 "gpc_reg_operand" "r"))
8974 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8975 (match_operand:SI 6 "gpc_reg_operand" "r"))
8976 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8977 (match_operand:SI 7 "gpc_reg_operand" "r"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8979 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8980 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8981 "{stsi|stswi} %2,%1,%O0"
8982 [(set_attr "type" "store")])
8983
8984 (define_insn "*stmsi5"
8985 [(match_parallel 0 "store_multiple_operation"
8986 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8987 (match_operand:SI 2 "gpc_reg_operand" "r"))
8988 (clobber (match_scratch:SI 3 "X"))
8989 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8990 (match_operand:SI 4 "gpc_reg_operand" "r"))
8991 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8992 (match_operand:SI 5 "gpc_reg_operand" "r"))
8993 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8994 (match_operand:SI 6 "gpc_reg_operand" "r"))
8995 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8996 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8997 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8998 "{stsi|stswi} %2,%1,%O0"
8999 [(set_attr "type" "store")])
9000
9001 (define_insn "*stmsi4"
9002 [(match_parallel 0 "store_multiple_operation"
9003 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9004 (match_operand:SI 2 "gpc_reg_operand" "r"))
9005 (clobber (match_scratch:SI 3 "X"))
9006 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9007 (match_operand:SI 4 "gpc_reg_operand" "r"))
9008 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9009 (match_operand:SI 5 "gpc_reg_operand" "r"))
9010 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9011 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9012 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9013 "{stsi|stswi} %2,%1,%O0"
9014 [(set_attr "type" "store")])
9015
9016 (define_insn "*stmsi3"
9017 [(match_parallel 0 "store_multiple_operation"
9018 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9019 (match_operand:SI 2 "gpc_reg_operand" "r"))
9020 (clobber (match_scratch:SI 3 "X"))
9021 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9022 (match_operand:SI 4 "gpc_reg_operand" "r"))
9023 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9024 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9025 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9026 "{stsi|stswi} %2,%1,%O0"
9027 [(set_attr "type" "store")])
9028 \f
9029 ;; String/block move insn.
9030 ;; Argument 0 is the destination
9031 ;; Argument 1 is the source
9032 ;; Argument 2 is the length
9033 ;; Argument 3 is the alignment
9034
9035 (define_expand "movstrsi"
9036 [(parallel [(set (match_operand:BLK 0 "" "")
9037 (match_operand:BLK 1 "" ""))
9038 (use (match_operand:SI 2 "" ""))
9039 (use (match_operand:SI 3 "" ""))])]
9040 ""
9041 "
9042 {
9043 if (expand_block_move (operands))
9044 DONE;
9045 else
9046 FAIL;
9047 }")
9048
9049 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9050 ;; register allocator doesn't have a clue about allocating 8 word registers.
9051 ;; rD/rS = r5 is preferred, efficient form.
9052 (define_expand "movstrsi_8reg"
9053 [(parallel [(set (match_operand 0 "" "")
9054 (match_operand 1 "" ""))
9055 (use (match_operand 2 "" ""))
9056 (use (match_operand 3 "" ""))
9057 (clobber (reg:SI 5))
9058 (clobber (reg:SI 6))
9059 (clobber (reg:SI 7))
9060 (clobber (reg:SI 8))
9061 (clobber (reg:SI 9))
9062 (clobber (reg:SI 10))
9063 (clobber (reg:SI 11))
9064 (clobber (reg:SI 12))
9065 (clobber (match_scratch:SI 4 ""))])]
9066 "TARGET_STRING"
9067 "")
9068
9069 (define_insn ""
9070 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9071 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9072 (use (match_operand:SI 2 "immediate_operand" "i"))
9073 (use (match_operand:SI 3 "immediate_operand" "i"))
9074 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9075 (clobber (reg:SI 6))
9076 (clobber (reg:SI 7))
9077 (clobber (reg:SI 8))
9078 (clobber (reg:SI 9))
9079 (clobber (reg:SI 10))
9080 (clobber (reg:SI 11))
9081 (clobber (reg:SI 12))
9082 (clobber (match_scratch:SI 5 "=q"))]
9083 "TARGET_STRING && TARGET_POWER
9084 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9085 || INTVAL (operands[2]) == 0)
9086 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9087 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9088 && REGNO (operands[4]) == 5"
9089 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9090 [(set_attr "type" "load")
9091 (set_attr "length" "8")])
9092
9093 (define_insn ""
9094 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9095 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9096 (use (match_operand:SI 2 "immediate_operand" "i"))
9097 (use (match_operand:SI 3 "immediate_operand" "i"))
9098 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9099 (clobber (reg:SI 6))
9100 (clobber (reg:SI 7))
9101 (clobber (reg:SI 8))
9102 (clobber (reg:SI 9))
9103 (clobber (reg:SI 10))
9104 (clobber (reg:SI 11))
9105 (clobber (reg:SI 12))
9106 (clobber (match_scratch:SI 5 "X"))]
9107 "TARGET_STRING && ! TARGET_POWER
9108 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9109 || INTVAL (operands[2]) == 0)
9110 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9111 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9112 && REGNO (operands[4]) == 5"
9113 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9114 [(set_attr "type" "load")
9115 (set_attr "length" "8")])
9116
9117 (define_insn ""
9118 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9119 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9120 (use (match_operand:SI 2 "immediate_operand" "i"))
9121 (use (match_operand:SI 3 "immediate_operand" "i"))
9122 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9123 (clobber (reg:SI 6))
9124 (clobber (reg:SI 7))
9125 (clobber (reg:SI 8))
9126 (clobber (reg:SI 9))
9127 (clobber (reg:SI 10))
9128 (clobber (reg:SI 11))
9129 (clobber (reg:SI 12))
9130 (clobber (match_scratch:SI 5 "X"))]
9131 "TARGET_STRING && TARGET_POWERPC64
9132 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9133 || INTVAL (operands[2]) == 0)
9134 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9135 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9136 && REGNO (operands[4]) == 5"
9137 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9138 [(set_attr "type" "load")
9139 (set_attr "length" "8")])
9140
9141 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9142 ;; register allocator doesn't have a clue about allocating 6 word registers.
9143 ;; rD/rS = r5 is preferred, efficient form.
9144 (define_expand "movstrsi_6reg"
9145 [(parallel [(set (match_operand 0 "" "")
9146 (match_operand 1 "" ""))
9147 (use (match_operand 2 "" ""))
9148 (use (match_operand 3 "" ""))
9149 (clobber (reg:SI 5))
9150 (clobber (reg:SI 6))
9151 (clobber (reg:SI 7))
9152 (clobber (reg:SI 8))
9153 (clobber (reg:SI 9))
9154 (clobber (reg:SI 10))
9155 (clobber (match_scratch:SI 4 ""))])]
9156 "TARGET_STRING"
9157 "")
9158
9159 (define_insn ""
9160 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9161 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9162 (use (match_operand:SI 2 "immediate_operand" "i"))
9163 (use (match_operand:SI 3 "immediate_operand" "i"))
9164 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9165 (clobber (reg:SI 6))
9166 (clobber (reg:SI 7))
9167 (clobber (reg:SI 8))
9168 (clobber (reg:SI 9))
9169 (clobber (reg:SI 10))
9170 (clobber (match_scratch:SI 5 "=q"))]
9171 "TARGET_STRING && TARGET_POWER
9172 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9173 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9174 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9175 && REGNO (operands[4]) == 5"
9176 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9177 [(set_attr "type" "load")
9178 (set_attr "length" "8")])
9179
9180 (define_insn ""
9181 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9182 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9183 (use (match_operand:SI 2 "immediate_operand" "i"))
9184 (use (match_operand:SI 3 "immediate_operand" "i"))
9185 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9186 (clobber (reg:SI 6))
9187 (clobber (reg:SI 7))
9188 (clobber (reg:SI 8))
9189 (clobber (reg:SI 9))
9190 (clobber (reg:SI 10))
9191 (clobber (match_scratch:SI 5 "X"))]
9192 "TARGET_STRING && ! TARGET_POWER
9193 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9194 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9195 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9196 && REGNO (operands[4]) == 5"
9197 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9198 [(set_attr "type" "load")
9199 (set_attr "length" "8")])
9200
9201 (define_insn ""
9202 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9203 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9204 (use (match_operand:SI 2 "immediate_operand" "i"))
9205 (use (match_operand:SI 3 "immediate_operand" "i"))
9206 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9207 (clobber (reg:SI 6))
9208 (clobber (reg:SI 7))
9209 (clobber (reg:SI 8))
9210 (clobber (reg:SI 9))
9211 (clobber (reg:SI 10))
9212 (clobber (match_scratch:SI 5 "X"))]
9213 "TARGET_STRING && TARGET_POWERPC64
9214 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9215 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9216 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9217 && REGNO (operands[4]) == 5"
9218 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9219 [(set_attr "type" "load")
9220 (set_attr "length" "8")])
9221
9222 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9223 ;; problems with TImode.
9224 ;; rD/rS = r5 is preferred, efficient form.
9225 (define_expand "movstrsi_4reg"
9226 [(parallel [(set (match_operand 0 "" "")
9227 (match_operand 1 "" ""))
9228 (use (match_operand 2 "" ""))
9229 (use (match_operand 3 "" ""))
9230 (clobber (reg:SI 5))
9231 (clobber (reg:SI 6))
9232 (clobber (reg:SI 7))
9233 (clobber (reg:SI 8))
9234 (clobber (match_scratch:SI 4 ""))])]
9235 "TARGET_STRING"
9236 "")
9237
9238 (define_insn ""
9239 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9240 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9241 (use (match_operand:SI 2 "immediate_operand" "i"))
9242 (use (match_operand:SI 3 "immediate_operand" "i"))
9243 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9244 (clobber (reg:SI 6))
9245 (clobber (reg:SI 7))
9246 (clobber (reg:SI 8))
9247 (clobber (match_scratch:SI 5 "=q"))]
9248 "TARGET_STRING && TARGET_POWER
9249 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9250 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9251 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9252 && REGNO (operands[4]) == 5"
9253 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9254 [(set_attr "type" "load")
9255 (set_attr "length" "8")])
9256
9257 (define_insn ""
9258 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9259 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9260 (use (match_operand:SI 2 "immediate_operand" "i"))
9261 (use (match_operand:SI 3 "immediate_operand" "i"))
9262 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9263 (clobber (reg:SI 6))
9264 (clobber (reg:SI 7))
9265 (clobber (reg:SI 8))
9266 (clobber (match_scratch:SI 5 "X"))]
9267 "TARGET_STRING && ! TARGET_POWER
9268 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9269 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9270 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9271 && REGNO (operands[4]) == 5"
9272 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9273 [(set_attr "type" "load")
9274 (set_attr "length" "8")])
9275
9276 (define_insn ""
9277 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9278 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9279 (use (match_operand:SI 2 "immediate_operand" "i"))
9280 (use (match_operand:SI 3 "immediate_operand" "i"))
9281 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9282 (clobber (reg:SI 6))
9283 (clobber (reg:SI 7))
9284 (clobber (reg:SI 8))
9285 (clobber (match_scratch:SI 5 "X"))]
9286 "TARGET_STRING && TARGET_POWERPC64
9287 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9288 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9289 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9290 && REGNO (operands[4]) == 5"
9291 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9292 [(set_attr "type" "load")
9293 (set_attr "length" "8")])
9294
9295 ;; Move up to 8 bytes at a time.
9296 (define_expand "movstrsi_2reg"
9297 [(parallel [(set (match_operand 0 "" "")
9298 (match_operand 1 "" ""))
9299 (use (match_operand 2 "" ""))
9300 (use (match_operand 3 "" ""))
9301 (clobber (match_scratch:DI 4 ""))
9302 (clobber (match_scratch:SI 5 ""))])]
9303 "TARGET_STRING && ! TARGET_POWERPC64"
9304 "")
9305
9306 (define_insn ""
9307 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9308 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9309 (use (match_operand:SI 2 "immediate_operand" "i"))
9310 (use (match_operand:SI 3 "immediate_operand" "i"))
9311 (clobber (match_scratch:DI 4 "=&r"))
9312 (clobber (match_scratch:SI 5 "=q"))]
9313 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9314 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9315 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9316 [(set_attr "type" "load")
9317 (set_attr "length" "8")])
9318
9319 (define_insn ""
9320 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9321 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9322 (use (match_operand:SI 2 "immediate_operand" "i"))
9323 (use (match_operand:SI 3 "immediate_operand" "i"))
9324 (clobber (match_scratch:DI 4 "=&r"))
9325 (clobber (match_scratch:SI 5 "X"))]
9326 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9327 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9328 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9329 [(set_attr "type" "load")
9330 (set_attr "length" "8")])
9331
9332 ;; Move up to 4 bytes at a time.
9333 (define_expand "movstrsi_1reg"
9334 [(parallel [(set (match_operand 0 "" "")
9335 (match_operand 1 "" ""))
9336 (use (match_operand 2 "" ""))
9337 (use (match_operand 3 "" ""))
9338 (clobber (match_scratch:SI 4 ""))
9339 (clobber (match_scratch:SI 5 ""))])]
9340 "TARGET_STRING"
9341 "")
9342
9343 (define_insn ""
9344 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9345 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9346 (use (match_operand:SI 2 "immediate_operand" "i"))
9347 (use (match_operand:SI 3 "immediate_operand" "i"))
9348 (clobber (match_scratch:SI 4 "=&r"))
9349 (clobber (match_scratch:SI 5 "=q"))]
9350 "TARGET_STRING && TARGET_POWER
9351 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9352 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9353 [(set_attr "type" "load")
9354 (set_attr "length" "8")])
9355
9356 (define_insn ""
9357 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9358 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9359 (use (match_operand:SI 2 "immediate_operand" "i"))
9360 (use (match_operand:SI 3 "immediate_operand" "i"))
9361 (clobber (match_scratch:SI 4 "=&r"))
9362 (clobber (match_scratch:SI 5 "X"))]
9363 "TARGET_STRING && ! TARGET_POWER
9364 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9365 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9366 [(set_attr "type" "load")
9367 (set_attr "length" "8")])
9368
9369 (define_insn ""
9370 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9371 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9372 (use (match_operand:SI 2 "immediate_operand" "i"))
9373 (use (match_operand:SI 3 "immediate_operand" "i"))
9374 (clobber (match_scratch:SI 4 "=&r"))
9375 (clobber (match_scratch:SI 5 "X"))]
9376 "TARGET_STRING && TARGET_POWERPC64
9377 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9378 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9379 [(set_attr "type" "load")
9380 (set_attr "length" "8")])
9381
9382 \f
9383 ;; Define insns that do load or store with update. Some of these we can
9384 ;; get by using pre-decrement or pre-increment, but the hardware can also
9385 ;; do cases where the increment is not the size of the object.
9386 ;;
9387 ;; In all these cases, we use operands 0 and 1 for the register being
9388 ;; incremented because those are the operands that local-alloc will
9389 ;; tie and these are the pair most likely to be tieable (and the ones
9390 ;; that will benefit the most).
9391
9392 (define_insn "*movdi_update1"
9393 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9394 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9395 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9396 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9397 (plus:DI (match_dup 1) (match_dup 2)))]
9398 "TARGET_POWERPC64 && TARGET_UPDATE"
9399 "@
9400 ldux %3,%0,%2
9401 ldu %3,%2(%0)"
9402 [(set_attr "type" "load_ux,load_u")])
9403
9404 (define_insn "movdi_update"
9405 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9406 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9407 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9408 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9409 (plus:DI (match_dup 1) (match_dup 2)))]
9410 "TARGET_POWERPC64 && TARGET_UPDATE"
9411 "@
9412 stdux %3,%0,%2
9413 stdu %3,%2(%0)"
9414 [(set_attr "type" "store_ux,store_u")])
9415
9416 (define_insn "*movsi_update1"
9417 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9418 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9419 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9420 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9421 (plus:SI (match_dup 1) (match_dup 2)))]
9422 "TARGET_UPDATE"
9423 "@
9424 {lux|lwzux} %3,%0,%2
9425 {lu|lwzu} %3,%2(%0)"
9426 [(set_attr "type" "load_ux,load_u")])
9427
9428 (define_insn "*movsi_update2"
9429 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9430 (sign_extend:DI
9431 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9432 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9433 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9434 (plus:DI (match_dup 1) (match_dup 2)))]
9435 "TARGET_POWERPC64"
9436 "lwaux %3,%0,%2"
9437 [(set_attr "type" "load_ext_ux")])
9438
9439 (define_insn "movsi_update"
9440 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9441 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9442 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9443 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9444 (plus:SI (match_dup 1) (match_dup 2)))]
9445 "TARGET_UPDATE"
9446 "@
9447 {stux|stwux} %3,%0,%2
9448 {stu|stwu} %3,%2(%0)"
9449 [(set_attr "type" "store_ux,store_u")])
9450
9451 (define_insn "*movhi_update1"
9452 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9453 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9454 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9455 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9456 (plus:SI (match_dup 1) (match_dup 2)))]
9457 "TARGET_UPDATE"
9458 "@
9459 lhzux %3,%0,%2
9460 lhzu %3,%2(%0)"
9461 [(set_attr "type" "load_ux,load_u")])
9462
9463 (define_insn "*movhi_update2"
9464 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9465 (zero_extend:SI
9466 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9467 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9468 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9469 (plus:SI (match_dup 1) (match_dup 2)))]
9470 "TARGET_UPDATE"
9471 "@
9472 lhzux %3,%0,%2
9473 lhzu %3,%2(%0)"
9474 [(set_attr "type" "load_ux,load_u")])
9475
9476 (define_insn "*movhi_update3"
9477 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9478 (sign_extend:SI
9479 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9480 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9481 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9482 (plus:SI (match_dup 1) (match_dup 2)))]
9483 "TARGET_UPDATE"
9484 "@
9485 lhaux %3,%0,%2
9486 lhau %3,%2(%0)"
9487 [(set_attr "type" "load_ext_ux,load_ext_u")])
9488
9489 (define_insn "*movhi_update4"
9490 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9491 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9492 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9493 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9494 (plus:SI (match_dup 1) (match_dup 2)))]
9495 "TARGET_UPDATE"
9496 "@
9497 sthux %3,%0,%2
9498 sthu %3,%2(%0)"
9499 [(set_attr "type" "store_ux,store_u")])
9500
9501 (define_insn "*movqi_update1"
9502 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9503 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9504 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9505 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9506 (plus:SI (match_dup 1) (match_dup 2)))]
9507 "TARGET_UPDATE"
9508 "@
9509 lbzux %3,%0,%2
9510 lbzu %3,%2(%0)"
9511 [(set_attr "type" "load_ux,load_u")])
9512
9513 (define_insn "*movqi_update2"
9514 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9515 (zero_extend:SI
9516 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9517 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9518 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9519 (plus:SI (match_dup 1) (match_dup 2)))]
9520 "TARGET_UPDATE"
9521 "@
9522 lbzux %3,%0,%2
9523 lbzu %3,%2(%0)"
9524 [(set_attr "type" "load_ux,load_u")])
9525
9526 (define_insn "*movqi_update3"
9527 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9528 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9529 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9530 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9531 (plus:SI (match_dup 1) (match_dup 2)))]
9532 "TARGET_UPDATE"
9533 "@
9534 stbux %3,%0,%2
9535 stbu %3,%2(%0)"
9536 [(set_attr "type" "store_ux,store_u")])
9537
9538 (define_insn "*movsf_update1"
9539 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9540 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9541 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9542 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9543 (plus:SI (match_dup 1) (match_dup 2)))]
9544 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9545 "@
9546 lfsux %3,%0,%2
9547 lfsu %3,%2(%0)"
9548 [(set_attr "type" "fpload_ux,fpload_u")])
9549
9550 (define_insn "*movsf_update2"
9551 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9552 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9553 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9554 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9555 (plus:SI (match_dup 1) (match_dup 2)))]
9556 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9557 "@
9558 stfsux %3,%0,%2
9559 stfsu %3,%2(%0)"
9560 [(set_attr "type" "fpstore_ux,fpstore_u")])
9561
9562 (define_insn "*movsf_update3"
9563 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9564 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9565 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9566 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9567 (plus:SI (match_dup 1) (match_dup 2)))]
9568 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9569 "@
9570 {lux|lwzux} %3,%0,%2
9571 {lu|lwzu} %3,%2(%0)"
9572 [(set_attr "type" "load_ux,load_u")])
9573
9574 (define_insn "*movsf_update4"
9575 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9576 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9577 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9578 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9579 (plus:SI (match_dup 1) (match_dup 2)))]
9580 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9581 "@
9582 {stux|stwux} %3,%0,%2
9583 {stu|stwu} %3,%2(%0)"
9584 [(set_attr "type" "store_ux,store_u")])
9585
9586 (define_insn "*movdf_update1"
9587 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9588 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9589 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9590 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9591 (plus:SI (match_dup 1) (match_dup 2)))]
9592 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9593 "@
9594 lfdux %3,%0,%2
9595 lfdu %3,%2(%0)"
9596 [(set_attr "type" "fpload_ux,fpload_u")])
9597
9598 (define_insn "*movdf_update2"
9599 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9600 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9601 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9602 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9603 (plus:SI (match_dup 1) (match_dup 2)))]
9604 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9605 "@
9606 stfdux %3,%0,%2
9607 stfdu %3,%2(%0)"
9608 [(set_attr "type" "fpstore_ux,fpstore_u")])
9609
9610 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9611
9612 (define_peephole
9613 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9614 (match_operand:DF 1 "memory_operand" ""))
9615 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9616 (match_operand:DF 3 "memory_operand" ""))]
9617 "TARGET_POWER2
9618 && TARGET_HARD_FLOAT && TARGET_FPRS
9619 && registers_ok_for_quad_peep (operands[0], operands[2])
9620 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9621 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9622 "lfq%U1%X1 %0,%1")
9623
9624 (define_peephole
9625 [(set (match_operand:DF 0 "memory_operand" "")
9626 (match_operand:DF 1 "gpc_reg_operand" "f"))
9627 (set (match_operand:DF 2 "memory_operand" "")
9628 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9629 "TARGET_POWER2
9630 && TARGET_HARD_FLOAT && TARGET_FPRS
9631 && registers_ok_for_quad_peep (operands[1], operands[3])
9632 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9633 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9634 "stfq%U0%X0 %1,%0")
9635 \f
9636 ;; Next come insns related to the calling sequence.
9637 ;;
9638 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9639 ;; We move the back-chain and decrement the stack pointer.
9640
9641 (define_expand "allocate_stack"
9642 [(set (match_operand 0 "gpc_reg_operand" "=r")
9643 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9644 (set (reg 1)
9645 (minus (reg 1) (match_dup 1)))]
9646 ""
9647 "
9648 { rtx chain = gen_reg_rtx (Pmode);
9649 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9650 rtx neg_op0;
9651
9652 emit_move_insn (chain, stack_bot);
9653
9654 /* Check stack bounds if necessary. */
9655 if (current_function_limit_stack)
9656 {
9657 rtx available;
9658 available = expand_binop (Pmode, sub_optab,
9659 stack_pointer_rtx, stack_limit_rtx,
9660 NULL_RTX, 1, OPTAB_WIDEN);
9661 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9662 }
9663
9664 if (GET_CODE (operands[1]) != CONST_INT
9665 || INTVAL (operands[1]) < -32767
9666 || INTVAL (operands[1]) > 32768)
9667 {
9668 neg_op0 = gen_reg_rtx (Pmode);
9669 if (TARGET_32BIT)
9670 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9671 else
9672 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9673 }
9674 else
9675 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9676
9677 if (TARGET_UPDATE)
9678 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9679 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9680
9681 else
9682 {
9683 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9684 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9685 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9686 }
9687
9688 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9689 DONE;
9690 }")
9691
9692 ;; These patterns say how to save and restore the stack pointer. We need not
9693 ;; save the stack pointer at function level since we are careful to
9694 ;; preserve the backchain. At block level, we have to restore the backchain
9695 ;; when we restore the stack pointer.
9696 ;;
9697 ;; For nonlocal gotos, we must save both the stack pointer and its
9698 ;; backchain and restore both. Note that in the nonlocal case, the
9699 ;; save area is a memory location.
9700
9701 (define_expand "save_stack_function"
9702 [(match_operand 0 "any_operand" "")
9703 (match_operand 1 "any_operand" "")]
9704 ""
9705 "DONE;")
9706
9707 (define_expand "restore_stack_function"
9708 [(match_operand 0 "any_operand" "")
9709 (match_operand 1 "any_operand" "")]
9710 ""
9711 "DONE;")
9712
9713 (define_expand "restore_stack_block"
9714 [(use (match_operand 0 "register_operand" ""))
9715 (set (match_dup 2) (match_dup 3))
9716 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9717 (set (match_dup 3) (match_dup 2))]
9718 ""
9719 "
9720 {
9721 operands[2] = gen_reg_rtx (Pmode);
9722 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9723 }")
9724
9725 (define_expand "save_stack_nonlocal"
9726 [(match_operand 0 "memory_operand" "")
9727 (match_operand 1 "register_operand" "")]
9728 ""
9729 "
9730 {
9731 rtx temp = gen_reg_rtx (Pmode);
9732
9733 /* Copy the backchain to the first word, sp to the second. */
9734 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9735 emit_move_insn (operand_subword (operands[0], 0, 0,
9736 (TARGET_32BIT ? DImode : TImode)),
9737 temp);
9738 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
9739 operands[1]);
9740 DONE;
9741 }")
9742
9743 (define_expand "restore_stack_nonlocal"
9744 [(match_operand 0 "register_operand" "")
9745 (match_operand 1 "memory_operand" "")]
9746 ""
9747 "
9748 {
9749 rtx temp = gen_reg_rtx (Pmode);
9750
9751 /* Restore the backchain from the first word, sp from the second. */
9752 emit_move_insn (temp,
9753 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
9754 emit_move_insn (operands[0],
9755 operand_subword (operands[1], 1, 0,
9756 (TARGET_32BIT ? DImode : TImode)));
9757 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9758 DONE;
9759 }")
9760 \f
9761 ;; TOC register handling.
9762
9763 ;; Code to initialize the TOC register...
9764
9765 (define_insn "load_toc_aix_si"
9766 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9767 (unspec:SI [(const_int 0)] 7))
9768 (use (reg:SI 2))])]
9769 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9770 "*
9771 {
9772 char buf[30];
9773 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9774 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9775 operands[2] = gen_rtx_REG (Pmode, 2);
9776 return \"{l|lwz} %0,%1(%2)\";
9777 }"
9778 [(set_attr "type" "load")])
9779
9780 (define_insn "load_toc_aix_di"
9781 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9782 (unspec:DI [(const_int 0)] 7))
9783 (use (reg:DI 2))])]
9784 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9785 "*
9786 {
9787 char buf[30];
9788 #ifdef TARGET_RELOCATABLE
9789 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9790 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9791 #else
9792 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9793 #endif
9794 if (TARGET_ELF)
9795 strcat (buf, \"@toc\");
9796 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9797 operands[2] = gen_rtx_REG (Pmode, 2);
9798 return \"ld %0,%1(%2)\";
9799 }"
9800 [(set_attr "type" "load")])
9801
9802 (define_insn "load_toc_v4_pic_si"
9803 [(set (match_operand:SI 0 "register_operand" "=l")
9804 (unspec:SI [(const_int 0)] 7))]
9805 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9806 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9807 [(set_attr "type" "branch")
9808 (set_attr "length" "4")])
9809
9810 (define_insn "load_toc_v4_PIC_1"
9811 [(set (match_operand:SI 0 "register_operand" "=l")
9812 (match_operand:SI 1 "immediate_operand" "s"))
9813 (unspec [(match_dup 1)] 7)]
9814 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9815 "bcl 20,31,%1\\n%1:"
9816 [(set_attr "type" "branch")
9817 (set_attr "length" "4")])
9818
9819 (define_insn "load_toc_v4_PIC_1b"
9820 [(set (match_operand:SI 0 "register_operand" "=l")
9821 (match_operand:SI 1 "immediate_operand" "s"))
9822 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
9823 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9824 "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:"
9825 [(set_attr "type" "branch")
9826 (set_attr "length" "8")])
9827
9828 (define_insn "load_toc_v4_PIC_2"
9829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9830 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9831 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9832 (match_operand:SI 3 "immediate_operand" "s")))))]
9833 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9834 "{l|lwz} %0,%2-%3(%1)"
9835 [(set_attr "type" "load")])
9836
9837 (define_insn "load_macho_picbase"
9838 [(set (match_operand:SI 0 "register_operand" "=l")
9839 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 15))]
9840 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
9841 "bcl 20,31,%1\\n%1:"
9842 [(set_attr "type" "branch")
9843 (set_attr "length" "4")])
9844
9845 (define_insn "macho_correct_pic"
9846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9847 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9848 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
9849 (match_operand:SI 3 "immediate_operand" "s")]
9850 16)))]
9851 "DEFAULT_ABI == ABI_DARWIN"
9852 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
9853 [(set_attr "length" "8")])
9854
9855 ;; If the TOC is shared over a translation unit, as happens with all
9856 ;; the kinds of PIC that we support, we need to restore the TOC
9857 ;; pointer only when jumping over units of translation.
9858 ;; On Darwin, we need to reload the picbase.
9859
9860 (define_expand "builtin_setjmp_receiver"
9861 [(use (label_ref (match_operand 0 "" "")))]
9862 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9863 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9864 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9865 "
9866 {
9867 #if TARGET_MACHO
9868 if (DEFAULT_ABI == ABI_DARWIN)
9869 {
9870 const char *picbase = machopic_function_base_name ();
9871 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
9872 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9873 rtx tmplabrtx;
9874 char tmplab[20];
9875
9876 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9877 CODE_LABEL_NUMBER (operands[0]));
9878 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (tmplab, -1));
9879
9880 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9881 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9882 }
9883 else
9884 #endif
9885 rs6000_emit_load_toc_table (FALSE);
9886 DONE;
9887 }")
9888 \f
9889 ;; A function pointer under AIX is a pointer to a data area whose first word
9890 ;; contains the actual address of the function, whose second word contains a
9891 ;; pointer to its TOC, and whose third word contains a value to place in the
9892 ;; static chain register (r11). Note that if we load the static chain, our
9893 ;; "trampoline" need not have any executable code.
9894
9895 (define_expand "call_indirect_aix32"
9896 [(set (match_dup 2)
9897 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9898 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9899 (reg:SI 2))
9900 (set (reg:SI 2)
9901 (mem:SI (plus:SI (match_dup 0)
9902 (const_int 4))))
9903 (set (reg:SI 11)
9904 (mem:SI (plus:SI (match_dup 0)
9905 (const_int 8))))
9906 (parallel [(call (mem:SI (match_dup 2))
9907 (match_operand 1 "" ""))
9908 (use (reg:SI 2))
9909 (use (reg:SI 11))
9910 (set (reg:SI 2)
9911 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9912 (clobber (scratch:SI))])]
9913 "TARGET_32BIT"
9914 "
9915 { operands[2] = gen_reg_rtx (SImode); }")
9916
9917 (define_expand "call_indirect_aix64"
9918 [(set (match_dup 2)
9919 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9920 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9921 (reg:DI 2))
9922 (set (reg:DI 2)
9923 (mem:DI (plus:DI (match_dup 0)
9924 (const_int 8))))
9925 (set (reg:DI 11)
9926 (mem:DI (plus:DI (match_dup 0)
9927 (const_int 16))))
9928 (parallel [(call (mem:SI (match_dup 2))
9929 (match_operand 1 "" ""))
9930 (use (reg:DI 2))
9931 (use (reg:DI 11))
9932 (set (reg:DI 2)
9933 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9934 (clobber (scratch:SI))])]
9935 "TARGET_64BIT"
9936 "
9937 { operands[2] = gen_reg_rtx (DImode); }")
9938
9939 (define_expand "call_value_indirect_aix32"
9940 [(set (match_dup 3)
9941 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9942 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9943 (reg:SI 2))
9944 (set (reg:SI 2)
9945 (mem:SI (plus:SI (match_dup 1)
9946 (const_int 4))))
9947 (set (reg:SI 11)
9948 (mem:SI (plus:SI (match_dup 1)
9949 (const_int 8))))
9950 (parallel [(set (match_operand 0 "" "")
9951 (call (mem:SI (match_dup 3))
9952 (match_operand 2 "" "")))
9953 (use (reg:SI 2))
9954 (use (reg:SI 11))
9955 (set (reg:SI 2)
9956 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9957 (clobber (scratch:SI))])]
9958 "TARGET_32BIT"
9959 "
9960 { operands[3] = gen_reg_rtx (SImode); }")
9961
9962 (define_expand "call_value_indirect_aix64"
9963 [(set (match_dup 3)
9964 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9965 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9966 (reg:DI 2))
9967 (set (reg:DI 2)
9968 (mem:DI (plus:DI (match_dup 1)
9969 (const_int 8))))
9970 (set (reg:DI 11)
9971 (mem:DI (plus:DI (match_dup 1)
9972 (const_int 16))))
9973 (parallel [(set (match_operand 0 "" "")
9974 (call (mem:SI (match_dup 3))
9975 (match_operand 2 "" "")))
9976 (use (reg:DI 2))
9977 (use (reg:DI 11))
9978 (set (reg:DI 2)
9979 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9980 (clobber (scratch:SI))])]
9981 "TARGET_64BIT"
9982 "
9983 { operands[3] = gen_reg_rtx (DImode); }")
9984
9985 ;; Now the definitions for the call and call_value insns
9986 (define_expand "call"
9987 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9988 (match_operand 1 "" ""))
9989 (use (match_operand 2 "" ""))
9990 (clobber (scratch:SI))])]
9991 ""
9992 "
9993 {
9994 #if TARGET_MACHO
9995 if (MACHOPIC_INDIRECT)
9996 operands[0] = machopic_indirect_call_target (operands[0]);
9997 #endif
9998
9999 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10000 abort ();
10001
10002 operands[0] = XEXP (operands[0], 0);
10003
10004 if (GET_CODE (operands[0]) != SYMBOL_REF
10005 || (INTVAL (operands[2]) & CALL_LONG) != 0)
10006 {
10007 if (INTVAL (operands[2]) & CALL_LONG)
10008 operands[0] = rs6000_longcall_ref (operands[0]);
10009
10010 if (DEFAULT_ABI == ABI_V4
10011 || DEFAULT_ABI == ABI_AIX_NODESC
10012 || DEFAULT_ABI == ABI_DARWIN)
10013 operands[0] = force_reg (Pmode, operands[0]);
10014
10015 else if (DEFAULT_ABI == ABI_AIX)
10016 {
10017 /* AIX function pointers are really pointers to a three word
10018 area. */
10019 emit_call_insn (TARGET_32BIT
10020 ? gen_call_indirect_aix32 (force_reg (SImode,
10021 operands[0]),
10022 operands[1])
10023 : gen_call_indirect_aix64 (force_reg (DImode,
10024 operands[0]),
10025 operands[1]));
10026 DONE;
10027 }
10028 else
10029 abort ();
10030 }
10031 }")
10032
10033 (define_expand "call_value"
10034 [(parallel [(set (match_operand 0 "" "")
10035 (call (mem:SI (match_operand 1 "address_operand" ""))
10036 (match_operand 2 "" "")))
10037 (use (match_operand 3 "" ""))
10038 (clobber (scratch:SI))])]
10039 ""
10040 "
10041 {
10042 #if TARGET_MACHO
10043 if (MACHOPIC_INDIRECT)
10044 operands[1] = machopic_indirect_call_target (operands[1]);
10045 #endif
10046
10047 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10048 abort ();
10049
10050 operands[1] = XEXP (operands[1], 0);
10051
10052 if (GET_CODE (operands[1]) != SYMBOL_REF
10053 || (INTVAL (operands[3]) & CALL_LONG) != 0)
10054 {
10055 if (INTVAL (operands[3]) & CALL_LONG)
10056 operands[1] = rs6000_longcall_ref (operands[1]);
10057
10058 if (DEFAULT_ABI == ABI_V4
10059 || DEFAULT_ABI == ABI_AIX_NODESC
10060 || DEFAULT_ABI == ABI_DARWIN)
10061 operands[0] = force_reg (Pmode, operands[0]);
10062
10063 else if (DEFAULT_ABI == ABI_AIX)
10064 {
10065 /* AIX function pointers are really pointers to a three word
10066 area. */
10067 emit_call_insn (TARGET_32BIT
10068 ? gen_call_value_indirect_aix32 (operands[0],
10069 force_reg (SImode,
10070 operands[1]),
10071 operands[2])
10072 : gen_call_value_indirect_aix64 (operands[0],
10073 force_reg (DImode,
10074 operands[1]),
10075 operands[2]));
10076 DONE;
10077 }
10078 else
10079 abort ();
10080 }
10081 }")
10082
10083 ;; Call to function in current module. No TOC pointer reload needed.
10084 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10085 ;; either the function was not prototyped, or it was prototyped as a
10086 ;; variable argument function. It is > 0 if FP registers were passed
10087 ;; and < 0 if they were not.
10088
10089 (define_insn "*call_local32"
10090 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10091 (match_operand 1 "" "g,g"))
10092 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10093 (clobber (match_scratch:SI 3 "=l,l"))]
10094 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10095 "*
10096 {
10097 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10098 output_asm_insn (\"crxor 6,6,6\", operands);
10099
10100 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10101 output_asm_insn (\"creqv 6,6,6\", operands);
10102
10103 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10104 }"
10105 [(set_attr "type" "branch")
10106 (set_attr "length" "4,8")])
10107
10108 (define_insn "*call_local64"
10109 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10110 (match_operand 1 "" "g,g"))
10111 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10112 (clobber (match_scratch:SI 3 "=l,l"))]
10113 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10114 "*
10115 {
10116 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10117 output_asm_insn (\"crxor 6,6,6\", operands);
10118
10119 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10120 output_asm_insn (\"creqv 6,6,6\", operands);
10121
10122 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10123 }"
10124 [(set_attr "type" "branch")
10125 (set_attr "length" "4,8")])
10126
10127 (define_insn "*call_value_local32"
10128 [(set (match_operand 0 "" "")
10129 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10130 (match_operand 2 "" "g,g")))
10131 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10132 (clobber (match_scratch:SI 4 "=l,l"))]
10133 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10134 "*
10135 {
10136 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10137 output_asm_insn (\"crxor 6,6,6\", operands);
10138
10139 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10140 output_asm_insn (\"creqv 6,6,6\", operands);
10141
10142 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10143 }"
10144 [(set_attr "type" "branch")
10145 (set_attr "length" "4,8")])
10146
10147
10148 (define_insn "*call_value_local64"
10149 [(set (match_operand 0 "" "")
10150 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10151 (match_operand 2 "" "g,g")))
10152 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10153 (clobber (match_scratch:SI 4 "=l,l"))]
10154 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10155 "*
10156 {
10157 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10158 output_asm_insn (\"crxor 6,6,6\", operands);
10159
10160 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10161 output_asm_insn (\"creqv 6,6,6\", operands);
10162
10163 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10164 }"
10165 [(set_attr "type" "branch")
10166 (set_attr "length" "4,8")])
10167
10168 ;; Call to function which may be in another module. Restore the TOC
10169 ;; pointer (r2) after the call unless this is System V.
10170 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10171 ;; either the function was not prototyped, or it was prototyped as a
10172 ;; variable argument function. It is > 0 if FP registers were passed
10173 ;; and < 0 if they were not.
10174
10175 (define_insn "*call_indirect_nonlocal_aix32"
10176 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10177 (match_operand 1 "" "g"))
10178 (use (reg:SI 2))
10179 (use (reg:SI 11))
10180 (set (reg:SI 2)
10181 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10182 (clobber (match_scratch:SI 2 "=l"))]
10183 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10184 "b%T0l\;{l|lwz} 2,20(1)"
10185 [(set_attr "type" "jmpreg")
10186 (set_attr "length" "8")])
10187
10188 (define_insn "*call_nonlocal_aix32"
10189 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10190 (match_operand 1 "" "g"))
10191 (use (match_operand:SI 2 "immediate_operand" "O"))
10192 (clobber (match_scratch:SI 3 "=l"))]
10193 "TARGET_32BIT
10194 && DEFAULT_ABI == ABI_AIX
10195 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10196 "bl %z0\;%."
10197 [(set_attr "type" "branch")
10198 (set_attr "length" "8")])
10199
10200 (define_insn "*call_indirect_nonlocal_aix64"
10201 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10202 (match_operand 1 "" "g"))
10203 (use (reg:DI 2))
10204 (use (reg:DI 11))
10205 (set (reg:DI 2)
10206 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10207 (clobber (match_scratch:SI 2 "=l"))]
10208 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10209 "b%T0l\;ld 2,40(1)"
10210 [(set_attr "type" "jmpreg")
10211 (set_attr "length" "8")])
10212
10213 (define_insn "*call_nonlocal_aix64"
10214 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10215 (match_operand 1 "" "g"))
10216 (use (match_operand:SI 2 "immediate_operand" "O"))
10217 (clobber (match_scratch:SI 3 "=l"))]
10218 "TARGET_64BIT
10219 && DEFAULT_ABI == ABI_AIX
10220 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10221 "bl %z0\;%."
10222 [(set_attr "type" "branch")
10223 (set_attr "length" "8")])
10224
10225 (define_insn "*call_value_indirect_nonlocal_aix32"
10226 [(set (match_operand 0 "" "")
10227 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10228 (match_operand 2 "" "g")))
10229 (use (reg:SI 2))
10230 (use (reg:SI 11))
10231 (set (reg:SI 2)
10232 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10233 (clobber (match_scratch:SI 3 "=l"))]
10234 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10235 "b%T1l\;{l|lwz} 2,20(1)"
10236 [(set_attr "type" "jmpreg")
10237 (set_attr "length" "8")])
10238
10239 (define_insn "*call_value_nonlocal_aix32"
10240 [(set (match_operand 0 "" "")
10241 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10242 (match_operand 2 "" "g")))
10243 (use (match_operand:SI 3 "immediate_operand" "O"))
10244 (clobber (match_scratch:SI 4 "=l"))]
10245 "TARGET_32BIT
10246 && DEFAULT_ABI == ABI_AIX
10247 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10248 "bl %z1\;%."
10249 [(set_attr "type" "branch")
10250 (set_attr "length" "8")])
10251
10252 (define_insn "*call_value_indirect_nonlocal_aix64"
10253 [(set (match_operand 0 "" "")
10254 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10255 (match_operand 2 "" "g")))
10256 (use (reg:DI 2))
10257 (use (reg:DI 11))
10258 (set (reg:DI 2)
10259 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10260 (clobber (match_scratch:SI 3 "=l"))]
10261 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10262 "b%T1l\;ld 2,40(1)"
10263 [(set_attr "type" "jmpreg")
10264 (set_attr "length" "8")])
10265
10266 (define_insn "*call_value_nonlocal_aix64"
10267 [(set (match_operand 0 "" "")
10268 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10269 (match_operand 2 "" "g")))
10270 (use (match_operand:SI 3 "immediate_operand" "O"))
10271 (clobber (match_scratch:SI 4 "=l"))]
10272 "TARGET_64BIT
10273 && DEFAULT_ABI == ABI_AIX
10274 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10275 "bl %z1\;%."
10276 [(set_attr "type" "branch")
10277 (set_attr "length" "8")])
10278
10279 ;; A function pointer under System V is just a normal pointer
10280 ;; operands[0] is the function pointer
10281 ;; operands[1] is the stack size to clean up
10282 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10283 ;; which indicates how to set cr1
10284
10285 (define_insn "*call_indirect_nonlocal_sysv"
10286 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10287 (match_operand 1 "" "g,g"))
10288 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10289 (clobber (match_scratch:SI 3 "=l,l"))]
10290 "DEFAULT_ABI == ABI_AIX_NODESC
10291 || DEFAULT_ABI == ABI_V4
10292 || DEFAULT_ABI == ABI_DARWIN"
10293 {
10294 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10295 output_asm_insn ("crxor 6,6,6", operands);
10296
10297 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10298 output_asm_insn ("creqv 6,6,6", operands);
10299
10300 return "b%T0l";
10301 }
10302 [(set_attr "type" "jmpreg,jmpreg")
10303 (set_attr "length" "4,8")])
10304
10305 (define_insn "*call_nonlocal_sysv"
10306 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10307 (match_operand 1 "" "g,g"))
10308 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10309 (clobber (match_scratch:SI 3 "=l,l"))]
10310 "(DEFAULT_ABI == ABI_AIX_NODESC
10311 || DEFAULT_ABI == ABI_V4
10312 || DEFAULT_ABI == ABI_DARWIN)
10313 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10314 {
10315 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10316 output_asm_insn ("crxor 6,6,6", operands);
10317
10318 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10319 output_asm_insn ("creqv 6,6,6", operands);
10320
10321 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10322 }
10323 [(set_attr "type" "branch,branch")
10324 (set_attr "length" "4,8")])
10325
10326 (define_insn "*call_value_indirect_nonlocal_sysv"
10327 [(set (match_operand 0 "" "")
10328 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10329 (match_operand 2 "" "g,g")))
10330 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10331 (clobber (match_scratch:SI 4 "=l,l"))]
10332 "DEFAULT_ABI == ABI_AIX_NODESC
10333 || DEFAULT_ABI == ABI_V4
10334 || DEFAULT_ABI == ABI_DARWIN"
10335 {
10336 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10337 output_asm_insn ("crxor 6,6,6", operands);
10338
10339 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10340 output_asm_insn ("creqv 6,6,6", operands);
10341
10342 return "b%T1l";
10343 }
10344 [(set_attr "type" "jmpreg,jmpreg")
10345 (set_attr "length" "4,8")])
10346
10347 (define_insn "*call_value_nonlocal_sysv"
10348 [(set (match_operand 0 "" "")
10349 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10350 (match_operand 2 "" "g,g")))
10351 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10352 (clobber (match_scratch:SI 4 "=l,l"))]
10353 "(DEFAULT_ABI == ABI_AIX_NODESC
10354 || DEFAULT_ABI == ABI_V4
10355 || DEFAULT_ABI == ABI_DARWIN)
10356 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10357 {
10358 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10359 output_asm_insn ("crxor 6,6,6", operands);
10360
10361 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10362 output_asm_insn ("creqv 6,6,6", operands);
10363
10364 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10365 }
10366 [(set_attr "type" "branch,branch")
10367 (set_attr "length" "4,8")])
10368
10369 ;; Call subroutine returning any type.
10370 (define_expand "untyped_call"
10371 [(parallel [(call (match_operand 0 "" "")
10372 (const_int 0))
10373 (match_operand 1 "" "")
10374 (match_operand 2 "" "")])]
10375 ""
10376 "
10377 {
10378 int i;
10379
10380 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10381
10382 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10383 {
10384 rtx set = XVECEXP (operands[2], 0, i);
10385 emit_move_insn (SET_DEST (set), SET_SRC (set));
10386 }
10387
10388 /* The optimizer does not know that the call sets the function value
10389 registers we stored in the result block. We avoid problems by
10390 claiming that all hard registers are used and clobbered at this
10391 point. */
10392 emit_insn (gen_blockage ());
10393
10394 DONE;
10395 }")
10396
10397 ;; sibling call patterns
10398 (define_expand "sibcall"
10399 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10400 (match_operand 1 "" ""))
10401 (use (match_operand 2 "" ""))
10402 (use (match_operand 3 "" ""))
10403 (return)])]
10404 ""
10405 "
10406 {
10407 #if TARGET_MACHO
10408 if (MACHOPIC_INDIRECT)
10409 operands[0] = machopic_indirect_call_target (operands[0]);
10410 #endif
10411
10412 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10413 abort ();
10414
10415 operands[0] = XEXP (operands[0], 0);
10416 operands[3] = gen_reg_rtx (SImode);
10417
10418 }")
10419
10420 ;; this and similar patterns must be marked as using LR, otherwise
10421 ;; dataflow will try to delete the store into it. This is true
10422 ;; even when the actual reg to jump to is in CTR, when LR was
10423 ;; saved and restored around the PIC-setting BCL.
10424 (define_insn "*sibcall_local32"
10425 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10426 (match_operand 1 "" "g,g"))
10427 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10428 (use (match_operand:SI 3 "register_operand" "l,l"))
10429 (return)]
10430 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10431 "*
10432 {
10433 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10434 output_asm_insn (\"crxor 6,6,6\", operands);
10435
10436 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10437 output_asm_insn (\"creqv 6,6,6\", operands);
10438
10439 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10440 }"
10441 [(set_attr "type" "branch")
10442 (set_attr "length" "4,8")])
10443
10444 (define_insn "*sibcall_local64"
10445 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10446 (match_operand 1 "" "g,g"))
10447 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10448 (use (match_operand:SI 3 "register_operand" "l,l"))
10449 (return)]
10450 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10451 "*
10452 {
10453 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10454 output_asm_insn (\"crxor 6,6,6\", operands);
10455
10456 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10457 output_asm_insn (\"creqv 6,6,6\", operands);
10458
10459 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10460 }"
10461 [(set_attr "type" "branch")
10462 (set_attr "length" "4,8")])
10463
10464 (define_insn "*sibcall_value_local32"
10465 [(set (match_operand 0 "" "")
10466 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10467 (match_operand 2 "" "g,g")))
10468 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10469 (use (match_operand:SI 4 "register_operand" "l,l"))
10470 (return)]
10471 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10472 "*
10473 {
10474 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10475 output_asm_insn (\"crxor 6,6,6\", operands);
10476
10477 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10478 output_asm_insn (\"creqv 6,6,6\", operands);
10479
10480 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10481 }"
10482 [(set_attr "type" "branch")
10483 (set_attr "length" "4,8")])
10484
10485
10486 (define_insn "*sibcall_value_local64"
10487 [(set (match_operand 0 "" "")
10488 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10489 (match_operand 2 "" "g,g")))
10490 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10491 (use (match_operand:SI 4 "register_operand" "l,l"))
10492 (return)]
10493 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10494 "*
10495 {
10496 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10497 output_asm_insn (\"crxor 6,6,6\", operands);
10498
10499 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10500 output_asm_insn (\"creqv 6,6,6\", operands);
10501
10502 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10503 }"
10504 [(set_attr "type" "branch")
10505 (set_attr "length" "4,8")])
10506
10507 (define_insn "*sibcall_nonlocal_aix32"
10508 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10509 (match_operand 1 "" "g"))
10510 (use (match_operand:SI 2 "immediate_operand" "O"))
10511 (use (match_operand:SI 3 "register_operand" "l"))
10512 (return)]
10513 "TARGET_32BIT
10514 && DEFAULT_ABI == ABI_AIX
10515 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10516 "b %z0"
10517 [(set_attr "type" "branch")
10518 (set_attr "length" "4")])
10519
10520 (define_insn "*sibcall_nonlocal_aix64"
10521 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10522 (match_operand 1 "" "g"))
10523 (use (match_operand:SI 2 "immediate_operand" "O"))
10524 (use (match_operand:SI 3 "register_operand" "l"))
10525 (return)]
10526 "TARGET_64BIT
10527 && DEFAULT_ABI == ABI_AIX
10528 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10529 "b %z0"
10530 [(set_attr "type" "branch")
10531 (set_attr "length" "4")])
10532
10533 (define_insn "*sibcall_value_nonlocal_aix32"
10534 [(set (match_operand 0 "" "")
10535 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10536 (match_operand 2 "" "g")))
10537 (use (match_operand:SI 3 "immediate_operand" "O"))
10538 (use (match_operand:SI 4 "register_operand" "l"))
10539 (return)]
10540 "TARGET_32BIT
10541 && DEFAULT_ABI == ABI_AIX
10542 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10543 "b %z1"
10544 [(set_attr "type" "branch")
10545 (set_attr "length" "4")])
10546
10547 (define_insn "*sibcall_value_nonlocal_aix64"
10548 [(set (match_operand 0 "" "")
10549 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10550 (match_operand 2 "" "g")))
10551 (use (match_operand:SI 3 "immediate_operand" "O"))
10552 (use (match_operand:SI 4 "register_operand" "l"))
10553 (return)]
10554 "TARGET_64BIT
10555 && DEFAULT_ABI == ABI_AIX
10556 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10557 "b %z1"
10558 [(set_attr "type" "branch")
10559 (set_attr "length" "4")])
10560
10561 (define_insn "*sibcall_nonlocal_sysv"
10562 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10563 (match_operand 1 "" ""))
10564 (use (match_operand 2 "immediate_operand" "O,n"))
10565 (use (match_operand:SI 3 "register_operand" "l,l"))
10566 (return)]
10567 "(DEFAULT_ABI == ABI_DARWIN
10568 || DEFAULT_ABI == ABI_V4
10569 || DEFAULT_ABI == ABI_AIX_NODESC)
10570 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10571 "*
10572 {
10573 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10574 output_asm_insn (\"crxor 6,6,6\", operands);
10575
10576 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10577 output_asm_insn (\"creqv 6,6,6\", operands);
10578
10579 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10580 }"
10581 [(set_attr "type" "branch,branch")
10582 (set_attr "length" "4,8")])
10583
10584 (define_expand "sibcall_value"
10585 [(parallel [(set (match_operand 0 "register_operand" "")
10586 (call (mem:SI (match_operand 1 "address_operand" ""))
10587 (match_operand 2 "" "")))
10588 (use (match_operand 3 "" ""))
10589 (use (match_operand 4 "" ""))
10590 (return)])]
10591 ""
10592 "
10593 {
10594 #if TARGET_MACHO
10595 if (MACHOPIC_INDIRECT)
10596 operands[1] = machopic_indirect_call_target (operands[1]);
10597 #endif
10598
10599 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10600 abort ();
10601
10602 operands[1] = XEXP (operands[1], 0);
10603 operands[4] = gen_reg_rtx (SImode);
10604
10605 }")
10606
10607 (define_insn "*sibcall_value_nonlocal_sysv"
10608 [(set (match_operand 0 "" "")
10609 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10610 (match_operand 2 "" "")))
10611 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10612 (use (match_operand:SI 4 "register_operand" "l,l"))
10613 (return)]
10614 "(DEFAULT_ABI == ABI_DARWIN
10615 || DEFAULT_ABI == ABI_V4
10616 || DEFAULT_ABI == ABI_AIX_NODESC)
10617 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10618 "*
10619 {
10620 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10621 output_asm_insn (\"crxor 6,6,6\", operands);
10622
10623 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10624 output_asm_insn (\"creqv 6,6,6\", operands);
10625
10626 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10627 }"
10628 [(set_attr "type" "branch,branch")
10629 (set_attr "length" "4,8")])
10630
10631 (define_expand "sibcall_epilogue"
10632 [(use (const_int 0))]
10633 "TARGET_SCHED_PROLOG"
10634 "
10635 {
10636 rs6000_emit_epilogue (TRUE);
10637 DONE;
10638 }")
10639
10640 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10641 ;; all of memory. This blocks insns from being moved across this point.
10642
10643 (define_insn "blockage"
10644 [(unspec_volatile [(const_int 0)] 0)]
10645 ""
10646 "")
10647 \f
10648 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10649 ;; signed & unsigned, and one type of branch.
10650 ;;
10651 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10652 ;; insns, and branches. We store the operands of compares until we see
10653 ;; how it is used.
10654 (define_expand "cmpsi"
10655 [(set (cc0)
10656 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10657 (match_operand:SI 1 "reg_or_short_operand" "")))]
10658 ""
10659 "
10660 {
10661 /* Take care of the possibility that operands[1] might be negative but
10662 this might be a logical operation. That insn doesn't exist. */
10663 if (GET_CODE (operands[1]) == CONST_INT
10664 && INTVAL (operands[1]) < 0)
10665 operands[1] = force_reg (SImode, operands[1]);
10666
10667 rs6000_compare_op0 = operands[0];
10668 rs6000_compare_op1 = operands[1];
10669 rs6000_compare_fp_p = 0;
10670 DONE;
10671 }")
10672
10673 (define_expand "cmpdi"
10674 [(set (cc0)
10675 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10676 (match_operand:DI 1 "reg_or_short_operand" "")))]
10677 "TARGET_POWERPC64"
10678 "
10679 {
10680 /* Take care of the possibility that operands[1] might be negative but
10681 this might be a logical operation. That insn doesn't exist. */
10682 if (GET_CODE (operands[1]) == CONST_INT
10683 && INTVAL (operands[1]) < 0)
10684 operands[1] = force_reg (DImode, operands[1]);
10685
10686 rs6000_compare_op0 = operands[0];
10687 rs6000_compare_op1 = operands[1];
10688 rs6000_compare_fp_p = 0;
10689 DONE;
10690 }")
10691
10692 (define_expand "cmpsf"
10693 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10694 (match_operand:SF 1 "gpc_reg_operand" "")))]
10695 "TARGET_HARD_FLOAT"
10696 "
10697 {
10698 rs6000_compare_op0 = operands[0];
10699 rs6000_compare_op1 = operands[1];
10700 rs6000_compare_fp_p = 1;
10701 DONE;
10702 }")
10703
10704 (define_expand "cmpdf"
10705 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10706 (match_operand:DF 1 "gpc_reg_operand" "")))]
10707 "TARGET_HARD_FLOAT && TARGET_FPRS"
10708 "
10709 {
10710 rs6000_compare_op0 = operands[0];
10711 rs6000_compare_op1 = operands[1];
10712 rs6000_compare_fp_p = 1;
10713 DONE;
10714 }")
10715
10716 (define_expand "cmptf"
10717 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10718 (match_operand:TF 1 "gpc_reg_operand" "")))]
10719 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
10720 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10721 "
10722 {
10723 rs6000_compare_op0 = operands[0];
10724 rs6000_compare_op1 = operands[1];
10725 rs6000_compare_fp_p = 1;
10726 DONE;
10727 }")
10728
10729 (define_expand "beq"
10730 [(use (match_operand 0 "" ""))]
10731 ""
10732 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10733
10734 (define_expand "bne"
10735 [(use (match_operand 0 "" ""))]
10736 ""
10737 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10738
10739 (define_expand "bge"
10740 [(use (match_operand 0 "" ""))]
10741 ""
10742 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10743
10744 (define_expand "bgt"
10745 [(use (match_operand 0 "" ""))]
10746 ""
10747 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10748
10749 (define_expand "ble"
10750 [(use (match_operand 0 "" ""))]
10751 ""
10752 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10753
10754 (define_expand "blt"
10755 [(use (match_operand 0 "" ""))]
10756 ""
10757 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10758
10759 (define_expand "bgeu"
10760 [(use (match_operand 0 "" ""))]
10761 ""
10762 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10763
10764 (define_expand "bgtu"
10765 [(use (match_operand 0 "" ""))]
10766 ""
10767 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10768
10769 (define_expand "bleu"
10770 [(use (match_operand 0 "" ""))]
10771 ""
10772 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10773
10774 (define_expand "bltu"
10775 [(use (match_operand 0 "" ""))]
10776 ""
10777 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10778
10779 (define_expand "bunordered"
10780 [(use (match_operand 0 "" ""))]
10781 ""
10782 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10783
10784 (define_expand "bordered"
10785 [(use (match_operand 0 "" ""))]
10786 ""
10787 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10788
10789 (define_expand "buneq"
10790 [(use (match_operand 0 "" ""))]
10791 ""
10792 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10793
10794 (define_expand "bunge"
10795 [(use (match_operand 0 "" ""))]
10796 ""
10797 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10798
10799 (define_expand "bungt"
10800 [(use (match_operand 0 "" ""))]
10801 ""
10802 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10803
10804 (define_expand "bunle"
10805 [(use (match_operand 0 "" ""))]
10806 ""
10807 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10808
10809 (define_expand "bunlt"
10810 [(use (match_operand 0 "" ""))]
10811 ""
10812 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10813
10814 (define_expand "bltgt"
10815 [(use (match_operand 0 "" ""))]
10816 ""
10817 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10818
10819 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10820 ;; For SEQ, likewise, except that comparisons with zero should be done
10821 ;; with an scc insns. However, due to the order that combine see the
10822 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10823 ;; the cases we don't want to handle.
10824 (define_expand "seq"
10825 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10826 ""
10827 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10828
10829 (define_expand "sne"
10830 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10831 ""
10832 "
10833 {
10834 if (! rs6000_compare_fp_p)
10835 FAIL;
10836
10837 rs6000_emit_sCOND (NE, operands[0]);
10838 DONE;
10839 }")
10840
10841 ;; A > 0 is best done using the portable sequence, so fail in that case.
10842 (define_expand "sgt"
10843 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10844 ""
10845 "
10846 {
10847 if (! rs6000_compare_fp_p
10848 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10849 FAIL;
10850
10851 rs6000_emit_sCOND (GT, operands[0]);
10852 DONE;
10853 }")
10854
10855 ;; A < 0 is best done in the portable way for A an integer.
10856 (define_expand "slt"
10857 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10858 ""
10859 "
10860 {
10861 if (! rs6000_compare_fp_p
10862 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10863 FAIL;
10864
10865 rs6000_emit_sCOND (LT, operands[0]);
10866 DONE;
10867 }")
10868
10869 ;; A >= 0 is best done the portable way for A an integer.
10870 (define_expand "sge"
10871 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10872 ""
10873 "
10874 {
10875 if (! rs6000_compare_fp_p
10876 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10877 FAIL;
10878
10879 rs6000_emit_sCOND (GE, operands[0]);
10880 DONE;
10881 }")
10882
10883 ;; A <= 0 is best done the portable way for A an integer.
10884 (define_expand "sle"
10885 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10886 ""
10887 "
10888 {
10889 if (! rs6000_compare_fp_p
10890 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10891 FAIL;
10892
10893 rs6000_emit_sCOND (LE, operands[0]);
10894 DONE;
10895 }")
10896
10897 (define_expand "sgtu"
10898 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10899 ""
10900 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10901
10902 (define_expand "sltu"
10903 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10904 ""
10905 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10906
10907 (define_expand "sgeu"
10908 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10909 ""
10910 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10911
10912 (define_expand "sleu"
10913 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10914 ""
10915 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10916 \f
10917 ;; Here are the actual compare insns.
10918 (define_insn "*cmpsi_internal1"
10919 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10920 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10921 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10922 ""
10923 "{cmp%I2|cmpw%I2} %0,%1,%2"
10924 [(set_attr "type" "cmp")])
10925
10926 (define_insn "*cmpdi_internal1"
10927 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10928 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
10929 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10930 "TARGET_POWERPC64"
10931 "cmpd%I2 %0,%1,%2"
10932 [(set_attr "type" "cmp")])
10933
10934 ;; If we are comparing a register for equality with a large constant,
10935 ;; we can do this with an XOR followed by a compare. But we need a scratch
10936 ;; register for the result of the XOR.
10937
10938 (define_split
10939 [(set (match_operand:CC 0 "cc_reg_operand" "")
10940 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10941 (match_operand:SI 2 "non_short_cint_operand" "")))
10942 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10943 "find_single_use (operands[0], insn, 0)
10944 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10945 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10946 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10947 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10948 "
10949 {
10950 /* Get the constant we are comparing against, C, and see what it looks like
10951 sign-extended to 16 bits. Then see what constant could be XOR'ed
10952 with C to get the sign-extended value. */
10953
10954 HOST_WIDE_INT c = INTVAL (operands[2]);
10955 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10956 HOST_WIDE_INT xorv = c ^ sextc;
10957
10958 operands[4] = GEN_INT (xorv);
10959 operands[5] = GEN_INT (sextc);
10960 }")
10961
10962 (define_insn "*cmpsi_internal2"
10963 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10964 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10965 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10966 ""
10967 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10968 [(set_attr "type" "cmp")])
10969
10970 (define_insn "*cmpdi_internal2"
10971 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10972 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10973 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10974 ""
10975 "cmpld%I2 %0,%1,%b2"
10976 [(set_attr "type" "cmp")])
10977
10978 ;; The following two insns don't exist as single insns, but if we provide
10979 ;; them, we can swap an add and compare, which will enable us to overlap more
10980 ;; of the required delay between a compare and branch. We generate code for
10981 ;; them by splitting.
10982
10983 (define_insn ""
10984 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10985 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10986 (match_operand:SI 2 "short_cint_operand" "i")))
10987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10988 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10989 ""
10990 "#"
10991 [(set_attr "length" "8")])
10992
10993 (define_insn ""
10994 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10995 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10996 (match_operand:SI 2 "u_short_cint_operand" "i")))
10997 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10998 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10999 ""
11000 "#"
11001 [(set_attr "length" "8")])
11002
11003 (define_split
11004 [(set (match_operand:CC 3 "cc_reg_operand" "")
11005 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11006 (match_operand:SI 2 "short_cint_operand" "")))
11007 (set (match_operand:SI 0 "gpc_reg_operand" "")
11008 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11009 ""
11010 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11011 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11012
11013 (define_split
11014 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11015 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11016 (match_operand:SI 2 "u_short_cint_operand" "")))
11017 (set (match_operand:SI 0 "gpc_reg_operand" "")
11018 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11019 ""
11020 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11021 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11022
11023 (define_insn "*cmpsf_internal1"
11024 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11025 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11026 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11027 "TARGET_HARD_FLOAT && TARGET_FPRS"
11028 "fcmpu %0,%1,%2"
11029 [(set_attr "type" "fpcompare")])
11030
11031 (define_insn "*cmpdf_internal1"
11032 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11033 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11034 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11035 "TARGET_HARD_FLOAT && TARGET_FPRS"
11036 "fcmpu %0,%1,%2"
11037 [(set_attr "type" "fpcompare")])
11038
11039 ;; Only need to compare second words if first words equal
11040 (define_insn "*cmptf_internal1"
11041 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11042 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11043 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11044 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
11045 && TARGET_LONG_DOUBLE_128"
11046 "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2"
11047 [(set_attr "type" "fpcompare")
11048 (set_attr "length" "12")])
11049 \f
11050 ;; Now we have the scc insns. We can do some combinations because of the
11051 ;; way the machine works.
11052 ;;
11053 ;; Note that this is probably faster if we can put an insn between the
11054 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11055 ;; cases the insns below which don't use an intermediate CR field will
11056 ;; be used instead.
11057 (define_insn ""
11058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11059 (match_operator:SI 1 "scc_comparison_operator"
11060 [(match_operand 2 "cc_reg_operand" "y")
11061 (const_int 0)]))]
11062 ""
11063 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
11064 [(set_attr "type" "mfcr")
11065 (set_attr "length" "12")])
11066
11067 ;; Same as above, but get the OV/ORDERED bit.
11068 (define_insn "move_from_CR_ov_bit"
11069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11070 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 724))]
11071 "TARGET_ISEL"
11072 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11073 [(set_attr "type" "mfcr")
11074 (set_attr "length" "12")])
11075
11076 (define_insn ""
11077 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11078 (match_operator:DI 1 "scc_comparison_operator"
11079 [(match_operand 2 "cc_reg_operand" "y")
11080 (const_int 0)]))]
11081 "TARGET_POWERPC64"
11082 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
11083 [(set_attr "type" "mfcr")
11084 (set_attr "length" "12")])
11085
11086 (define_insn ""
11087 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11088 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11089 [(match_operand 2 "cc_reg_operand" "y,y")
11090 (const_int 0)])
11091 (const_int 0)))
11092 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11093 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11094 "! TARGET_POWERPC64"
11095 "@
11096 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
11097 #"
11098 [(set_attr "type" "delayed_compare")
11099 (set_attr "length" "12,16")])
11100
11101 (define_split
11102 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11103 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11104 [(match_operand 2 "cc_reg_operand" "")
11105 (const_int 0)])
11106 (const_int 0)))
11107 (set (match_operand:SI 3 "gpc_reg_operand" "")
11108 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11109 "! TARGET_POWERPC64 && reload_completed"
11110 [(set (match_dup 3)
11111 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11112 (set (match_dup 0)
11113 (compare:CC (match_dup 3)
11114 (const_int 0)))]
11115 "")
11116
11117 (define_insn ""
11118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11119 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11120 [(match_operand 2 "cc_reg_operand" "y")
11121 (const_int 0)])
11122 (match_operand:SI 3 "const_int_operand" "n")))]
11123 ""
11124 "*
11125 {
11126 int is_bit = ccr_bit (operands[1], 1);
11127 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11128 int count;
11129
11130 if (is_bit >= put_bit)
11131 count = is_bit - put_bit;
11132 else
11133 count = 32 - (put_bit - is_bit);
11134
11135 operands[4] = GEN_INT (count);
11136 operands[5] = GEN_INT (put_bit);
11137
11138 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11139 }"
11140 [(set_attr "type" "mfcr")
11141 (set_attr "length" "12")])
11142
11143 (define_insn ""
11144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11145 (compare:CC
11146 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11147 [(match_operand 2 "cc_reg_operand" "y,y")
11148 (const_int 0)])
11149 (match_operand:SI 3 "const_int_operand" "n,n"))
11150 (const_int 0)))
11151 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11152 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11153 (match_dup 3)))]
11154 ""
11155 "*
11156 {
11157 int is_bit = ccr_bit (operands[1], 1);
11158 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11159 int count;
11160
11161 /* Force split for non-cc0 compare. */
11162 if (which_alternative == 1)
11163 return \"#\";
11164
11165 if (is_bit >= put_bit)
11166 count = is_bit - put_bit;
11167 else
11168 count = 32 - (put_bit - is_bit);
11169
11170 operands[5] = GEN_INT (count);
11171 operands[6] = GEN_INT (put_bit);
11172
11173 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11174 }"
11175 [(set_attr "type" "delayed_compare")
11176 (set_attr "length" "12,16")])
11177
11178 (define_split
11179 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11180 (compare:CC
11181 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11182 [(match_operand 2 "cc_reg_operand" "")
11183 (const_int 0)])
11184 (match_operand:SI 3 "const_int_operand" ""))
11185 (const_int 0)))
11186 (set (match_operand:SI 4 "gpc_reg_operand" "")
11187 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11188 (match_dup 3)))]
11189 "reload_completed"
11190 [(set (match_dup 4)
11191 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11192 (match_dup 3)))
11193 (set (match_dup 0)
11194 (compare:CC (match_dup 4)
11195 (const_int 0)))]
11196 "")
11197
11198 ;; There is a 3 cycle delay between consecutive mfcr instructions
11199 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11200
11201 (define_peephole
11202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11203 (match_operator:SI 1 "scc_comparison_operator"
11204 [(match_operand 2 "cc_reg_operand" "y")
11205 (const_int 0)]))
11206 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11207 (match_operator:SI 4 "scc_comparison_operator"
11208 [(match_operand 5 "cc_reg_operand" "y")
11209 (const_int 0)]))]
11210 "REGNO (operands[2]) != REGNO (operands[5])"
11211 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11212 [(set_attr "type" "mfcr")
11213 (set_attr "length" "20")])
11214
11215 (define_peephole
11216 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11217 (match_operator:DI 1 "scc_comparison_operator"
11218 [(match_operand 2 "cc_reg_operand" "y")
11219 (const_int 0)]))
11220 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11221 (match_operator:DI 4 "scc_comparison_operator"
11222 [(match_operand 5 "cc_reg_operand" "y")
11223 (const_int 0)]))]
11224 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11225 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11226 [(set_attr "type" "mfcr")
11227 (set_attr "length" "20")])
11228
11229 ;; There are some scc insns that can be done directly, without a compare.
11230 ;; These are faster because they don't involve the communications between
11231 ;; the FXU and branch units. In fact, we will be replacing all of the
11232 ;; integer scc insns here or in the portable methods in emit_store_flag.
11233 ;;
11234 ;; Also support (neg (scc ..)) since that construct is used to replace
11235 ;; branches, (plus (scc ..) ..) since that construct is common and
11236 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11237 ;; cases where it is no more expensive than (neg (scc ..)).
11238
11239 ;; Have reload force a constant into a register for the simple insns that
11240 ;; otherwise won't accept constants. We do this because it is faster than
11241 ;; the cmp/mfcr sequence we would otherwise generate.
11242
11243 (define_insn ""
11244 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11245 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11246 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11247 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11248 "! TARGET_POWERPC64"
11249 "@
11250 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11251 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11252 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11253 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11254 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11255 [(set_attr "length" "12,8,12,12,12")])
11256
11257 (define_insn ""
11258 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11259 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11260 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11261 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11262 "TARGET_POWERPC64"
11263 "@
11264 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11265 subfic %3,%1,0\;adde %0,%3,%1
11266 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11267 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11268 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11269 [(set_attr "length" "12,8,12,12,12")])
11270
11271 (define_insn ""
11272 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11273 (compare:CC
11274 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11275 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11276 (const_int 0)))
11277 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11278 (eq:SI (match_dup 1) (match_dup 2)))
11279 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11280 "! TARGET_POWERPC64"
11281 "@
11282 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11283 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11284 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11285 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11286 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11287 #
11288 #
11289 #
11290 #
11291 #"
11292 [(set_attr "type" "compare")
11293 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11294
11295 (define_split
11296 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11297 (compare:CC
11298 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11299 (match_operand:SI 2 "reg_or_cint_operand" ""))
11300 (const_int 0)))
11301 (set (match_operand:SI 0 "gpc_reg_operand" "")
11302 (eq:SI (match_dup 1) (match_dup 2)))
11303 (clobber (match_scratch:SI 3 ""))]
11304 "! TARGET_POWERPC64 && reload_completed"
11305 [(parallel [(set (match_dup 0)
11306 (eq:SI (match_dup 1) (match_dup 2)))
11307 (clobber (match_dup 3))])
11308 (set (match_dup 4)
11309 (compare:CC (match_dup 0)
11310 (const_int 0)))]
11311 "")
11312
11313 (define_insn ""
11314 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11315 (compare:CC
11316 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11317 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11318 (const_int 0)))
11319 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11320 (eq:DI (match_dup 1) (match_dup 2)))
11321 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11322 "TARGET_POWERPC64"
11323 "@
11324 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11325 subfic %3,%1,0\;adde. %0,%3,%1
11326 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11327 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11328 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11329 #
11330 #
11331 #
11332 #
11333 #"
11334 [(set_attr "type" "compare")
11335 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11336
11337 (define_split
11338 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11339 (compare:CC
11340 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11341 (match_operand:DI 2 "reg_or_cint_operand" ""))
11342 (const_int 0)))
11343 (set (match_operand:DI 0 "gpc_reg_operand" "")
11344 (eq:DI (match_dup 1) (match_dup 2)))
11345 (clobber (match_scratch:DI 3 ""))]
11346 "TARGET_POWERPC64 && reload_completed"
11347 [(parallel [(set (match_dup 0)
11348 (eq:DI (match_dup 1) (match_dup 2)))
11349 (clobber (match_dup 3))])
11350 (set (match_dup 4)
11351 (compare:CC (match_dup 0)
11352 (const_int 0)))]
11353 "")
11354
11355 ;; We have insns of the form shown by the first define_insn below. If
11356 ;; there is something inside the comparison operation, we must split it.
11357 (define_split
11358 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11359 (plus:SI (match_operator 1 "comparison_operator"
11360 [(match_operand:SI 2 "" "")
11361 (match_operand:SI 3
11362 "reg_or_cint_operand" "")])
11363 (match_operand:SI 4 "gpc_reg_operand" "")))
11364 (clobber (match_operand:SI 5 "register_operand" ""))]
11365 "! gpc_reg_operand (operands[2], SImode)"
11366 [(set (match_dup 5) (match_dup 2))
11367 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11368 (match_dup 4)))])
11369
11370 (define_insn ""
11371 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11372 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11373 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11374 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11375 "! TARGET_POWERPC64"
11376 "@
11377 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11378 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11379 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11380 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11381 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11382 [(set_attr "length" "12,8,12,12,12")])
11383
11384 (define_insn ""
11385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11386 (compare:CC
11387 (plus:SI
11388 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11389 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11390 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11391 (const_int 0)))
11392 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11393 "! TARGET_POWERPC64"
11394 "@
11395 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11396 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11397 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11398 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11399 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11400 #
11401 #
11402 #
11403 #
11404 #"
11405 [(set_attr "type" "compare")
11406 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11407
11408 (define_split
11409 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11410 (compare:CC
11411 (plus:SI
11412 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11413 (match_operand:SI 2 "reg_or_cint_operand" ""))
11414 (match_operand:SI 3 "gpc_reg_operand" ""))
11415 (const_int 0)))
11416 (clobber (match_scratch:SI 4 ""))]
11417 "! TARGET_POWERPC64 && reload_completed"
11418 [(set (match_dup 4)
11419 (plus:SI (eq:SI (match_dup 1)
11420 (match_dup 2))
11421 (match_dup 3)))
11422 (set (match_dup 0)
11423 (compare:CC (match_dup 4)
11424 (const_int 0)))]
11425 "")
11426
11427 (define_insn ""
11428 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11429 (compare:CC
11430 (plus:SI
11431 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11432 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11433 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11434 (const_int 0)))
11435 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11436 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11437 "! TARGET_POWERPC64"
11438 "@
11439 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11440 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11441 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11442 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11443 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11444 #
11445 #
11446 #
11447 #
11448 #"
11449 [(set_attr "type" "compare")
11450 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11451
11452 (define_split
11453 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11454 (compare:CC
11455 (plus:SI
11456 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11457 (match_operand:SI 2 "reg_or_cint_operand" ""))
11458 (match_operand:SI 3 "gpc_reg_operand" ""))
11459 (const_int 0)))
11460 (set (match_operand:SI 0 "gpc_reg_operand" "")
11461 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11462 "! TARGET_POWERPC64 && reload_completed"
11463 [(set (match_dup 0)
11464 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11465 (set (match_dup 4)
11466 (compare:CC (match_dup 0)
11467 (const_int 0)))]
11468 "")
11469
11470 (define_insn ""
11471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11472 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11473 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11474 "! TARGET_POWERPC64"
11475 "@
11476 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11477 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11478 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11479 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11480 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11481 [(set_attr "length" "12,8,12,12,12")])
11482
11483 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11484 ;; since it nabs/sr is just as fast.
11485 (define_insn "*ne0"
11486 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11487 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11488 (const_int 31)))
11489 (clobber (match_scratch:SI 2 "=&r"))]
11490 "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL"
11491 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11492 [(set_attr "length" "8")])
11493
11494 (define_insn ""
11495 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11496 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11497 (const_int 63)))
11498 (clobber (match_scratch:DI 2 "=&r"))]
11499 "TARGET_POWERPC64"
11500 "addic %2,%1,-1\;subfe %0,%2,%1"
11501 [(set_attr "length" "8")])
11502
11503 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11504 (define_insn ""
11505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11506 (plus:SI (lshiftrt:SI
11507 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11508 (const_int 31))
11509 (match_operand:SI 2 "gpc_reg_operand" "r")))
11510 (clobber (match_scratch:SI 3 "=&r"))]
11511 "! TARGET_POWERPC64"
11512 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11513 [(set_attr "length" "8")])
11514
11515 (define_insn ""
11516 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11517 (plus:DI (lshiftrt:DI
11518 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11519 (const_int 63))
11520 (match_operand:DI 2 "gpc_reg_operand" "r")))
11521 (clobber (match_scratch:DI 3 "=&r"))]
11522 "TARGET_POWERPC64"
11523 "addic %3,%1,-1\;addze %0,%2"
11524 [(set_attr "length" "8")])
11525
11526 (define_insn ""
11527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11528 (compare:CC
11529 (plus:SI (lshiftrt:SI
11530 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11531 (const_int 31))
11532 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11533 (const_int 0)))
11534 (clobber (match_scratch:SI 3 "=&r,&r"))
11535 (clobber (match_scratch:SI 4 "=X,&r"))]
11536 "! TARGET_POWERPC64"
11537 "@
11538 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11539 #"
11540 [(set_attr "type" "compare")
11541 (set_attr "length" "8,12")])
11542
11543 (define_split
11544 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11545 (compare:CC
11546 (plus:SI (lshiftrt:SI
11547 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11548 (const_int 31))
11549 (match_operand:SI 2 "gpc_reg_operand" ""))
11550 (const_int 0)))
11551 (clobber (match_scratch:SI 3 ""))
11552 (clobber (match_scratch:SI 4 ""))]
11553 "! TARGET_POWERPC64 && reload_completed"
11554 [(parallel [(set (match_dup 3)
11555 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11556 (const_int 31))
11557 (match_dup 2)))
11558 (clobber (match_dup 4))])
11559 (set (match_dup 0)
11560 (compare:CC (match_dup 3)
11561 (const_int 0)))]
11562 "")
11563
11564 (define_insn ""
11565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11566 (compare:CC
11567 (plus:DI (lshiftrt:DI
11568 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11569 (const_int 63))
11570 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11571 (const_int 0)))
11572 (clobber (match_scratch:DI 3 "=&r,&r"))]
11573 "TARGET_POWERPC64"
11574 "@
11575 addic %3,%1,-1\;addze. %3,%2
11576 #"
11577 [(set_attr "type" "compare")
11578 (set_attr "length" "8,12")])
11579
11580 (define_split
11581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11582 (compare:CC
11583 (plus:DI (lshiftrt:DI
11584 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11585 (const_int 63))
11586 (match_operand:DI 2 "gpc_reg_operand" ""))
11587 (const_int 0)))
11588 (clobber (match_scratch:DI 3 ""))]
11589 "TARGET_POWERPC64 && reload_completed"
11590 [(set (match_dup 3)
11591 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11592 (const_int 63))
11593 (match_dup 2)))
11594 (set (match_dup 0)
11595 (compare:CC (match_dup 3)
11596 (const_int 0)))]
11597 "")
11598
11599 (define_insn ""
11600 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11601 (compare:CC
11602 (plus:SI (lshiftrt:SI
11603 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11604 (const_int 31))
11605 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11606 (const_int 0)))
11607 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11608 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11609 (match_dup 2)))
11610 (clobber (match_scratch:SI 3 "=&r,&r"))]
11611 "! TARGET_POWERPC64"
11612 "@
11613 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11614 #"
11615 [(set_attr "type" "compare")
11616 (set_attr "length" "8,12")])
11617
11618 (define_split
11619 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11620 (compare:CC
11621 (plus:SI (lshiftrt:SI
11622 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11623 (const_int 31))
11624 (match_operand:SI 2 "gpc_reg_operand" ""))
11625 (const_int 0)))
11626 (set (match_operand:SI 0 "gpc_reg_operand" "")
11627 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11628 (match_dup 2)))
11629 (clobber (match_scratch:SI 3 ""))]
11630 "! TARGET_POWERPC64 && reload_completed"
11631 [(parallel [(set (match_dup 0)
11632 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11633 (match_dup 2)))
11634 (clobber (match_dup 3))])
11635 (set (match_dup 4)
11636 (compare:CC (match_dup 0)
11637 (const_int 0)))]
11638 "")
11639
11640 (define_insn ""
11641 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11642 (compare:CC
11643 (plus:DI (lshiftrt:DI
11644 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11645 (const_int 63))
11646 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11647 (const_int 0)))
11648 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11649 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11650 (match_dup 2)))
11651 (clobber (match_scratch:DI 3 "=&r,&r"))]
11652 "TARGET_POWERPC64"
11653 "@
11654 addic %3,%1,-1\;addze. %0,%2
11655 #"
11656 [(set_attr "type" "compare")
11657 (set_attr "length" "8,12")])
11658
11659 (define_split
11660 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11661 (compare:CC
11662 (plus:DI (lshiftrt:DI
11663 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11664 (const_int 63))
11665 (match_operand:DI 2 "gpc_reg_operand" ""))
11666 (const_int 0)))
11667 (set (match_operand:DI 0 "gpc_reg_operand" "")
11668 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11669 (match_dup 2)))
11670 (clobber (match_scratch:DI 3 ""))]
11671 "TARGET_POWERPC64 && reload_completed"
11672 [(parallel [(set (match_dup 0)
11673 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11674 (match_dup 2)))
11675 (clobber (match_dup 3))])
11676 (set (match_dup 4)
11677 (compare:CC (match_dup 0)
11678 (const_int 0)))]
11679 "")
11680
11681 (define_insn ""
11682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11683 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11684 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11685 (clobber (match_scratch:SI 3 "=r,X"))]
11686 "TARGET_POWER"
11687 "@
11688 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11689 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11690 [(set_attr "length" "12")])
11691
11692 (define_insn ""
11693 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11694 (compare:CC
11695 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11696 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11697 (const_int 0)))
11698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11699 (le:SI (match_dup 1) (match_dup 2)))
11700 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11701 "TARGET_POWER"
11702 "@
11703 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11704 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11705 #
11706 #"
11707 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11708 (set_attr "length" "12,12,16,16")])
11709
11710 (define_split
11711 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11712 (compare:CC
11713 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11714 (match_operand:SI 2 "reg_or_short_operand" ""))
11715 (const_int 0)))
11716 (set (match_operand:SI 0 "gpc_reg_operand" "")
11717 (le:SI (match_dup 1) (match_dup 2)))
11718 (clobber (match_scratch:SI 3 ""))]
11719 "TARGET_POWER && reload_completed"
11720 [(parallel [(set (match_dup 0)
11721 (le:SI (match_dup 1) (match_dup 2)))
11722 (clobber (match_dup 3))])
11723 (set (match_dup 4)
11724 (compare:CC (match_dup 0)
11725 (const_int 0)))]
11726 "")
11727
11728 (define_insn ""
11729 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11730 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11731 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11732 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11733 "TARGET_POWER"
11734 "@
11735 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11736 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11737 [(set_attr "length" "12")])
11738
11739 (define_insn ""
11740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11741 (compare:CC
11742 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11743 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11744 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11745 (const_int 0)))
11746 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11747 "TARGET_POWER"
11748 "@
11749 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11750 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11751 #
11752 #"
11753 [(set_attr "type" "compare")
11754 (set_attr "length" "12,12,16,16")])
11755
11756 (define_split
11757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11758 (compare:CC
11759 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11760 (match_operand:SI 2 "reg_or_short_operand" ""))
11761 (match_operand:SI 3 "gpc_reg_operand" ""))
11762 (const_int 0)))
11763 (clobber (match_scratch:SI 4 ""))]
11764 "TARGET_POWER && reload_completed"
11765 [(set (match_dup 4)
11766 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11767 (match_dup 3)))
11768 (set (match_dup 0)
11769 (compare:CC (match_dup 4)
11770 (const_int 0)))]
11771 "")
11772
11773 (define_insn ""
11774 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11775 (compare:CC
11776 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11777 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11778 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11779 (const_int 0)))
11780 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11781 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11782 "TARGET_POWER"
11783 "@
11784 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11785 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11786 #
11787 #"
11788 [(set_attr "type" "compare")
11789 (set_attr "length" "12,12,16,16")])
11790
11791 (define_split
11792 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11793 (compare:CC
11794 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11795 (match_operand:SI 2 "reg_or_short_operand" ""))
11796 (match_operand:SI 3 "gpc_reg_operand" ""))
11797 (const_int 0)))
11798 (set (match_operand:SI 0 "gpc_reg_operand" "")
11799 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11800 "TARGET_POWER && reload_completed"
11801 [(set (match_dup 0)
11802 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11803 (set (match_dup 4)
11804 (compare:CC (match_dup 0)
11805 (const_int 0)))]
11806 "")
11807
11808 (define_insn ""
11809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11810 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11811 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11812 "TARGET_POWER"
11813 "@
11814 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11815 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11816 [(set_attr "length" "12")])
11817
11818 (define_insn ""
11819 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11820 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11821 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11822 "! TARGET_POWERPC64"
11823 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11824 [(set_attr "length" "12")])
11825
11826 (define_insn ""
11827 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11828 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11829 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11830 "TARGET_POWERPC64"
11831 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11832 [(set_attr "length" "12")])
11833
11834 (define_insn ""
11835 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11836 (compare:CC
11837 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11838 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11839 (const_int 0)))
11840 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11841 (leu:DI (match_dup 1) (match_dup 2)))]
11842 "TARGET_POWERPC64"
11843 "@
11844 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11845 #"
11846 [(set_attr "type" "compare")
11847 (set_attr "length" "12,16")])
11848
11849 (define_split
11850 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11851 (compare:CC
11852 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11853 (match_operand:DI 2 "reg_or_short_operand" ""))
11854 (const_int 0)))
11855 (set (match_operand:DI 0 "gpc_reg_operand" "")
11856 (leu:DI (match_dup 1) (match_dup 2)))]
11857 "TARGET_POWERPC64 && reload_completed"
11858 [(set (match_dup 0)
11859 (leu:DI (match_dup 1) (match_dup 2)))
11860 (set (match_dup 3)
11861 (compare:CC (match_dup 0)
11862 (const_int 0)))]
11863 "")
11864
11865 (define_insn ""
11866 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11867 (compare:CC
11868 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11869 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11870 (const_int 0)))
11871 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11872 (leu:SI (match_dup 1) (match_dup 2)))]
11873 "! TARGET_POWERPC64"
11874 "@
11875 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11876 #"
11877 [(set_attr "type" "compare")
11878 (set_attr "length" "12,16")])
11879
11880 (define_split
11881 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11882 (compare:CC
11883 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11884 (match_operand:SI 2 "reg_or_short_operand" ""))
11885 (const_int 0)))
11886 (set (match_operand:SI 0 "gpc_reg_operand" "")
11887 (leu:SI (match_dup 1) (match_dup 2)))]
11888 "! TARGET_POWERPC64 && reload_completed"
11889 [(set (match_dup 0)
11890 (leu:SI (match_dup 1) (match_dup 2)))
11891 (set (match_dup 3)
11892 (compare:CC (match_dup 0)
11893 (const_int 0)))]
11894 "")
11895
11896 (define_insn ""
11897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11898 (compare:CC
11899 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11900 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11901 (const_int 0)))
11902 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11903 (leu:DI (match_dup 1) (match_dup 2)))]
11904 "TARGET_POWERPC64"
11905 "@
11906 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11907 #"
11908 [(set_attr "type" "compare")
11909 (set_attr "length" "12,16")])
11910
11911 (define_insn ""
11912 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11913 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11914 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11915 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11916 "! TARGET_POWERPC64"
11917 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11918 [(set_attr "length" "8")])
11919
11920 (define_insn ""
11921 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11922 (compare:CC
11923 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11924 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11925 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11926 (const_int 0)))
11927 (clobber (match_scratch:SI 4 "=&r,&r"))]
11928 "! TARGET_POWERPC64"
11929 "@
11930 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11931 #"
11932 [(set_attr "type" "compare")
11933 (set_attr "length" "8,12")])
11934
11935 (define_split
11936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11937 (compare:CC
11938 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11939 (match_operand:SI 2 "reg_or_short_operand" ""))
11940 (match_operand:SI 3 "gpc_reg_operand" ""))
11941 (const_int 0)))
11942 (clobber (match_scratch:SI 4 ""))]
11943 "! TARGET_POWERPC64 && reload_completed"
11944 [(set (match_dup 4)
11945 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11946 (match_dup 3)))
11947 (set (match_dup 0)
11948 (compare:CC (match_dup 4)
11949 (const_int 0)))]
11950 "")
11951
11952 (define_insn ""
11953 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11954 (compare:CC
11955 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11956 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11957 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11958 (const_int 0)))
11959 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11960 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11961 "! TARGET_POWERPC64"
11962 "@
11963 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11964 #"
11965 [(set_attr "type" "compare")
11966 (set_attr "length" "8,12")])
11967
11968 (define_split
11969 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11970 (compare:CC
11971 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11972 (match_operand:SI 2 "reg_or_short_operand" ""))
11973 (match_operand:SI 3 "gpc_reg_operand" ""))
11974 (const_int 0)))
11975 (set (match_operand:SI 0 "gpc_reg_operand" "")
11976 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11977 "! TARGET_POWERPC64 && reload_completed"
11978 [(set (match_dup 0)
11979 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11980 (set (match_dup 4)
11981 (compare:CC (match_dup 0)
11982 (const_int 0)))]
11983 "")
11984
11985 (define_insn ""
11986 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11987 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11988 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11989 "! TARGET_POWERPC64"
11990 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11991 [(set_attr "length" "12")])
11992
11993 (define_insn ""
11994 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11995 (and:SI (neg:SI
11996 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11997 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11998 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11999 "! TARGET_POWERPC64"
12000 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12001 [(set_attr "length" "12")])
12002
12003 (define_insn ""
12004 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12005 (compare:CC
12006 (and:SI (neg:SI
12007 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12008 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12009 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12010 (const_int 0)))
12011 (clobber (match_scratch:SI 4 "=&r,&r"))]
12012 "! TARGET_POWERPC64"
12013 "@
12014 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12015 #"
12016 [(set_attr "type" "compare")
12017 (set_attr "length" "12,16")])
12018
12019 (define_split
12020 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12021 (compare:CC
12022 (and:SI (neg:SI
12023 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12024 (match_operand:SI 2 "reg_or_short_operand" "")))
12025 (match_operand:SI 3 "gpc_reg_operand" ""))
12026 (const_int 0)))
12027 (clobber (match_scratch:SI 4 ""))]
12028 "! TARGET_POWERPC64 && reload_completed"
12029 [(set (match_dup 4)
12030 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12031 (match_dup 3)))
12032 (set (match_dup 0)
12033 (compare:CC (match_dup 4)
12034 (const_int 0)))]
12035 "")
12036
12037 (define_insn ""
12038 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12039 (compare:CC
12040 (and:SI (neg:SI
12041 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12042 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12043 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12044 (const_int 0)))
12045 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12046 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12047 "! TARGET_POWERPC64"
12048 "@
12049 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12050 #"
12051 [(set_attr "type" "compare")
12052 (set_attr "length" "12,16")])
12053
12054 (define_split
12055 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12056 (compare:CC
12057 (and:SI (neg:SI
12058 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12059 (match_operand:SI 2 "reg_or_short_operand" "")))
12060 (match_operand:SI 3 "gpc_reg_operand" ""))
12061 (const_int 0)))
12062 (set (match_operand:SI 0 "gpc_reg_operand" "")
12063 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12064 "! TARGET_POWERPC64 && reload_completed"
12065 [(set (match_dup 0)
12066 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12067 (match_dup 3)))
12068 (set (match_dup 4)
12069 (compare:CC (match_dup 0)
12070 (const_int 0)))]
12071 "")
12072
12073 (define_insn ""
12074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12075 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12076 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12077 "TARGET_POWER"
12078 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12079 [(set_attr "length" "12")])
12080
12081 (define_insn ""
12082 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12083 (compare:CC
12084 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12085 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12086 (const_int 0)))
12087 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12088 (lt:SI (match_dup 1) (match_dup 2)))]
12089 "TARGET_POWER"
12090 "@
12091 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12092 #"
12093 [(set_attr "type" "delayed_compare")
12094 (set_attr "length" "12,16")])
12095
12096 (define_split
12097 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12098 (compare:CC
12099 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12100 (match_operand:SI 2 "reg_or_short_operand" ""))
12101 (const_int 0)))
12102 (set (match_operand:SI 0 "gpc_reg_operand" "")
12103 (lt:SI (match_dup 1) (match_dup 2)))]
12104 "TARGET_POWER && reload_completed"
12105 [(set (match_dup 0)
12106 (lt:SI (match_dup 1) (match_dup 2)))
12107 (set (match_dup 3)
12108 (compare:CC (match_dup 0)
12109 (const_int 0)))]
12110 "")
12111
12112 (define_insn ""
12113 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12114 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12115 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12116 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12117 "TARGET_POWER"
12118 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12119 [(set_attr "length" "12")])
12120
12121 (define_insn ""
12122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12123 (compare:CC
12124 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12125 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12126 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12127 (const_int 0)))
12128 (clobber (match_scratch:SI 4 "=&r,&r"))]
12129 "TARGET_POWER"
12130 "@
12131 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12132 #"
12133 [(set_attr "type" "compare")
12134 (set_attr "length" "12,16")])
12135
12136 (define_split
12137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12138 (compare:CC
12139 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12140 (match_operand:SI 2 "reg_or_short_operand" ""))
12141 (match_operand:SI 3 "gpc_reg_operand" ""))
12142 (const_int 0)))
12143 (clobber (match_scratch:SI 4 ""))]
12144 "TARGET_POWER && reload_completed"
12145 [(set (match_dup 4)
12146 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12147 (match_dup 3)))
12148 (set (match_dup 0)
12149 (compare:CC (match_dup 4)
12150 (const_int 0)))]
12151 "")
12152
12153 (define_insn ""
12154 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12155 (compare:CC
12156 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12157 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12158 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12159 (const_int 0)))
12160 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12161 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12162 "TARGET_POWER"
12163 "@
12164 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12165 #"
12166 [(set_attr "type" "compare")
12167 (set_attr "length" "12,16")])
12168
12169 (define_split
12170 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12171 (compare:CC
12172 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12173 (match_operand:SI 2 "reg_or_short_operand" ""))
12174 (match_operand:SI 3 "gpc_reg_operand" ""))
12175 (const_int 0)))
12176 (set (match_operand:SI 0 "gpc_reg_operand" "")
12177 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12178 "TARGET_POWER && reload_completed"
12179 [(set (match_dup 0)
12180 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12181 (set (match_dup 4)
12182 (compare:CC (match_dup 0)
12183 (const_int 0)))]
12184 "")
12185
12186 (define_insn ""
12187 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12188 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12189 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12190 "TARGET_POWER"
12191 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12192 [(set_attr "length" "12")])
12193
12194 (define_insn ""
12195 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12196 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12197 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12198 "! TARGET_POWERPC64"
12199 "@
12200 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12201 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12202 [(set_attr "length" "12")])
12203
12204 (define_insn ""
12205 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12206 (compare:CC
12207 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12208 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12209 (const_int 0)))
12210 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12211 (ltu:SI (match_dup 1) (match_dup 2)))]
12212 "! TARGET_POWERPC64"
12213 "@
12214 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12215 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12216 #
12217 #"
12218 [(set_attr "type" "compare")
12219 (set_attr "length" "12,12,16,16")])
12220
12221 (define_split
12222 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12223 (compare:CC
12224 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12225 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12226 (const_int 0)))
12227 (set (match_operand:SI 0 "gpc_reg_operand" "")
12228 (ltu:SI (match_dup 1) (match_dup 2)))]
12229 "! TARGET_POWERPC64 && reload_completed"
12230 [(set (match_dup 0)
12231 (ltu:SI (match_dup 1) (match_dup 2)))
12232 (set (match_dup 3)
12233 (compare:CC (match_dup 0)
12234 (const_int 0)))]
12235 "")
12236
12237 (define_insn ""
12238 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12239 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12240 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12241 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12242 "! TARGET_POWERPC64"
12243 "@
12244 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12245 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12246 [(set_attr "length" "12")])
12247
12248 (define_insn ""
12249 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12250 (compare:CC
12251 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12252 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12253 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12254 (const_int 0)))
12255 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12256 "! TARGET_POWERPC64"
12257 "@
12258 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12259 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12260 #
12261 #"
12262 [(set_attr "type" "compare")
12263 (set_attr "length" "12,12,16,16")])
12264
12265 (define_split
12266 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12267 (compare:CC
12268 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12269 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12270 (match_operand:SI 3 "gpc_reg_operand" ""))
12271 (const_int 0)))
12272 (clobber (match_scratch:SI 4 ""))]
12273 "! TARGET_POWERPC64 && reload_completed"
12274 [(set (match_dup 4)
12275 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12276 (match_dup 3)))
12277 (set (match_dup 0)
12278 (compare:CC (match_dup 4)
12279 (const_int 0)))]
12280 "")
12281
12282 (define_insn ""
12283 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12284 (compare:CC
12285 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12286 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12287 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12288 (const_int 0)))
12289 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12290 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12291 "! TARGET_POWERPC64"
12292 "@
12293 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12294 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12295 #
12296 #"
12297 [(set_attr "type" "compare")
12298 (set_attr "length" "12,12,16,16")])
12299
12300 (define_split
12301 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12302 (compare:CC
12303 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12304 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12305 (match_operand:SI 3 "gpc_reg_operand" ""))
12306 (const_int 0)))
12307 (set (match_operand:SI 0 "gpc_reg_operand" "")
12308 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12309 "! TARGET_POWERPC64 && reload_completed"
12310 [(set (match_dup 0)
12311 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12312 (set (match_dup 4)
12313 (compare:CC (match_dup 0)
12314 (const_int 0)))]
12315 "")
12316
12317 (define_insn ""
12318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12319 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12320 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12321 "! TARGET_POWERPC64"
12322 "@
12323 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12324 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12325 [(set_attr "length" "8")])
12326
12327 (define_insn ""
12328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12329 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12330 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12331 (clobber (match_scratch:SI 3 "=r"))]
12332 "TARGET_POWER"
12333 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12334 [(set_attr "length" "12")])
12335
12336 (define_insn ""
12337 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12338 (compare:CC
12339 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12340 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12341 (const_int 0)))
12342 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12343 (ge:SI (match_dup 1) (match_dup 2)))
12344 (clobber (match_scratch:SI 3 "=r,r"))]
12345 "TARGET_POWER"
12346 "@
12347 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12348 #"
12349 [(set_attr "type" "compare")
12350 (set_attr "length" "12,16")])
12351
12352 (define_split
12353 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12354 (compare:CC
12355 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12356 (match_operand:SI 2 "reg_or_short_operand" ""))
12357 (const_int 0)))
12358 (set (match_operand:SI 0 "gpc_reg_operand" "")
12359 (ge:SI (match_dup 1) (match_dup 2)))
12360 (clobber (match_scratch:SI 3 ""))]
12361 "TARGET_POWER && reload_completed"
12362 [(parallel [(set (match_dup 0)
12363 (ge:SI (match_dup 1) (match_dup 2)))
12364 (clobber (match_dup 3))])
12365 (set (match_dup 4)
12366 (compare:CC (match_dup 0)
12367 (const_int 0)))]
12368 "")
12369
12370 (define_insn ""
12371 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12372 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12373 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12374 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12375 "TARGET_POWER"
12376 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12377 [(set_attr "length" "12")])
12378
12379 (define_insn ""
12380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12381 (compare:CC
12382 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12383 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12384 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12385 (const_int 0)))
12386 (clobber (match_scratch:SI 4 "=&r,&r"))]
12387 "TARGET_POWER"
12388 "@
12389 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12390 #"
12391 [(set_attr "type" "compare")
12392 (set_attr "length" "12,16")])
12393
12394 (define_split
12395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12396 (compare:CC
12397 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12398 (match_operand:SI 2 "reg_or_short_operand" ""))
12399 (match_operand:SI 3 "gpc_reg_operand" ""))
12400 (const_int 0)))
12401 (clobber (match_scratch:SI 4 ""))]
12402 "TARGET_POWER && reload_completed"
12403 [(set (match_dup 4)
12404 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12405 (match_dup 3)))
12406 (set (match_dup 0)
12407 (compare:CC (match_dup 4)
12408 (const_int 0)))]
12409 "")
12410
12411 (define_insn ""
12412 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12413 (compare:CC
12414 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12415 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12416 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12417 (const_int 0)))
12418 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12419 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12420 "TARGET_POWER"
12421 "@
12422 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12423 #"
12424 [(set_attr "type" "compare")
12425 (set_attr "length" "12,16")])
12426
12427 (define_split
12428 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12429 (compare:CC
12430 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12431 (match_operand:SI 2 "reg_or_short_operand" ""))
12432 (match_operand:SI 3 "gpc_reg_operand" ""))
12433 (const_int 0)))
12434 (set (match_operand:SI 0 "gpc_reg_operand" "")
12435 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12436 "TARGET_POWER && reload_completed"
12437 [(set (match_dup 0)
12438 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12439 (set (match_dup 4)
12440 (compare:CC (match_dup 0)
12441 (const_int 0)))]
12442 "")
12443
12444 (define_insn ""
12445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12446 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12447 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12448 "TARGET_POWER"
12449 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12450 [(set_attr "length" "12")])
12451
12452 (define_insn ""
12453 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12454 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12455 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12456 "! TARGET_POWERPC64"
12457 "@
12458 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12459 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12460 [(set_attr "length" "12")])
12461
12462 (define_insn ""
12463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12464 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12465 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12466 "TARGET_POWERPC64"
12467 "@
12468 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12469 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12470 [(set_attr "length" "12")])
12471
12472 (define_insn ""
12473 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12474 (compare:CC
12475 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12476 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12477 (const_int 0)))
12478 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12479 (geu:SI (match_dup 1) (match_dup 2)))]
12480 "! TARGET_POWERPC64"
12481 "@
12482 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12483 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12484 #
12485 #"
12486 [(set_attr "type" "compare")
12487 (set_attr "length" "12,12,16,16")])
12488
12489 (define_split
12490 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12491 (compare:CC
12492 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12493 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12494 (const_int 0)))
12495 (set (match_operand:SI 0 "gpc_reg_operand" "")
12496 (geu:SI (match_dup 1) (match_dup 2)))]
12497 "! TARGET_POWERPC64 && reload_completed"
12498 [(set (match_dup 0)
12499 (geu:SI (match_dup 1) (match_dup 2)))
12500 (set (match_dup 3)
12501 (compare:CC (match_dup 0)
12502 (const_int 0)))]
12503 "")
12504
12505 (define_insn ""
12506 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12507 (compare:CC
12508 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12509 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12510 (const_int 0)))
12511 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12512 (geu:DI (match_dup 1) (match_dup 2)))]
12513 "TARGET_POWERPC64"
12514 "@
12515 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12516 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12517 #
12518 #"
12519 [(set_attr "type" "compare")
12520 (set_attr "length" "12,12,16,16")])
12521
12522 (define_split
12523 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12524 (compare:CC
12525 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12526 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12527 (const_int 0)))
12528 (set (match_operand:DI 0 "gpc_reg_operand" "")
12529 (geu:DI (match_dup 1) (match_dup 2)))]
12530 "TARGET_POWERPC64 && reload_completed"
12531 [(set (match_dup 0)
12532 (geu:DI (match_dup 1) (match_dup 2)))
12533 (set (match_dup 3)
12534 (compare:CC (match_dup 0)
12535 (const_int 0)))]
12536 "")
12537
12538 (define_insn ""
12539 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12540 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12541 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12542 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12543 "! TARGET_POWERPC64"
12544 "@
12545 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12546 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12547 [(set_attr "length" "8")])
12548
12549 (define_insn ""
12550 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12551 (compare:CC
12552 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12553 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12554 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12555 (const_int 0)))
12556 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12557 "! TARGET_POWERPC64"
12558 "@
12559 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12560 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12561 #
12562 #"
12563 [(set_attr "type" "compare")
12564 (set_attr "length" "8,8,12,12")])
12565
12566 (define_split
12567 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12568 (compare:CC
12569 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12570 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12571 (match_operand:SI 3 "gpc_reg_operand" ""))
12572 (const_int 0)))
12573 (clobber (match_scratch:SI 4 ""))]
12574 "! TARGET_POWERPC64 && reload_completed"
12575 [(set (match_dup 4)
12576 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12577 (match_dup 3)))
12578 (set (match_dup 0)
12579 (compare:CC (match_dup 4)
12580 (const_int 0)))]
12581 "")
12582
12583 (define_insn ""
12584 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12585 (compare:CC
12586 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12587 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12588 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12589 (const_int 0)))
12590 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12591 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12592 "! TARGET_POWERPC64"
12593 "@
12594 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12595 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12596 #
12597 #"
12598 [(set_attr "type" "compare")
12599 (set_attr "length" "8,8,12,12")])
12600
12601 (define_split
12602 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12603 (compare:CC
12604 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12605 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12606 (match_operand:SI 3 "gpc_reg_operand" ""))
12607 (const_int 0)))
12608 (set (match_operand:SI 0 "gpc_reg_operand" "")
12609 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12610 "! TARGET_POWERPC64 && reload_completed"
12611 [(set (match_dup 0)
12612 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12613 (set (match_dup 4)
12614 (compare:CC (match_dup 0)
12615 (const_int 0)))]
12616 "")
12617
12618 (define_insn ""
12619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12620 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12621 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12622 "! TARGET_POWERPC64"
12623 "@
12624 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12625 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12626 [(set_attr "length" "12")])
12627
12628 (define_insn ""
12629 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12630 (and:SI (neg:SI
12631 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12632 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12633 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12634 "! TARGET_POWERPC64"
12635 "@
12636 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12637 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12638 [(set_attr "length" "12")])
12639
12640 (define_insn ""
12641 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12642 (compare:CC
12643 (and:SI (neg:SI
12644 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12645 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12646 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12647 (const_int 0)))
12648 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12649 "! TARGET_POWERPC64"
12650 "@
12651 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12652 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12653 #
12654 #"
12655 [(set_attr "type" "compare")
12656 (set_attr "length" "12,12,16,16")])
12657
12658 (define_split
12659 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12660 (compare:CC
12661 (and:SI (neg:SI
12662 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12663 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12664 (match_operand:SI 3 "gpc_reg_operand" ""))
12665 (const_int 0)))
12666 (clobber (match_scratch:SI 4 ""))]
12667 "! TARGET_POWERPC64 && reload_completed"
12668 [(set (match_dup 4)
12669 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12670 (match_dup 3)))
12671 (set (match_dup 0)
12672 (compare:CC (match_dup 4)
12673 (const_int 0)))]
12674 "")
12675
12676 (define_insn ""
12677 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12678 (compare:CC
12679 (and:SI (neg:SI
12680 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12681 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12682 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12683 (const_int 0)))
12684 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12685 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12686 "! TARGET_POWERPC64"
12687 "@
12688 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12689 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12690 #
12691 #"
12692 [(set_attr "type" "compare")
12693 (set_attr "length" "12,12,16,16")])
12694
12695 (define_split
12696 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12697 (compare:CC
12698 (and:SI (neg:SI
12699 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12700 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12701 (match_operand:SI 3 "gpc_reg_operand" ""))
12702 (const_int 0)))
12703 (set (match_operand:SI 0 "gpc_reg_operand" "")
12704 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12705 "! TARGET_POWERPC64 && reload_completed"
12706 [(set (match_dup 0)
12707 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12708 (set (match_dup 4)
12709 (compare:CC (match_dup 0)
12710 (const_int 0)))]
12711 "")
12712
12713 (define_insn ""
12714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12715 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12716 (const_int 0)))]
12717 "! TARGET_POWERPC64"
12718 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12719 [(set_attr "length" "12")])
12720
12721 (define_insn ""
12722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12723 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12724 (const_int 0)))]
12725 "TARGET_POWERPC64"
12726 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12727 [(set_attr "length" "12")])
12728
12729 (define_insn ""
12730 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12731 (compare:CC
12732 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12733 (const_int 0))
12734 (const_int 0)))
12735 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12736 (gt:SI (match_dup 1) (const_int 0)))]
12737 "! TARGET_POWERPC64"
12738 "@
12739 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12740 #"
12741 [(set_attr "type" "delayed_compare")
12742 (set_attr "length" "12,16")])
12743
12744 (define_split
12745 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12746 (compare:CC
12747 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12748 (const_int 0))
12749 (const_int 0)))
12750 (set (match_operand:SI 0 "gpc_reg_operand" "")
12751 (gt:SI (match_dup 1) (const_int 0)))]
12752 "! TARGET_POWERPC64 && reload_completed"
12753 [(set (match_dup 0)
12754 (gt:SI (match_dup 1) (const_int 0)))
12755 (set (match_dup 2)
12756 (compare:CC (match_dup 0)
12757 (const_int 0)))]
12758 "")
12759
12760 (define_insn ""
12761 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12762 (compare:CC
12763 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12764 (const_int 0))
12765 (const_int 0)))
12766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12767 (gt:DI (match_dup 1) (const_int 0)))]
12768 "TARGET_POWERPC64"
12769 "@
12770 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12771 #"
12772 [(set_attr "type" "delayed_compare")
12773 (set_attr "length" "12,16")])
12774
12775 (define_split
12776 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12777 (compare:CC
12778 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12779 (const_int 0))
12780 (const_int 0)))
12781 (set (match_operand:DI 0 "gpc_reg_operand" "")
12782 (gt:DI (match_dup 1) (const_int 0)))]
12783 "TARGET_POWERPC64 && reload_completed"
12784 [(set (match_dup 0)
12785 (gt:DI (match_dup 1) (const_int 0)))
12786 (set (match_dup 2)
12787 (compare:CC (match_dup 0)
12788 (const_int 0)))]
12789 "")
12790
12791 (define_insn ""
12792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12793 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12794 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12795 "TARGET_POWER"
12796 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12797 [(set_attr "length" "12")])
12798
12799 (define_insn ""
12800 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12801 (compare:CC
12802 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12803 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12804 (const_int 0)))
12805 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12806 (gt:SI (match_dup 1) (match_dup 2)))]
12807 "TARGET_POWER"
12808 "@
12809 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12810 #"
12811 [(set_attr "type" "delayed_compare")
12812 (set_attr "length" "12,16")])
12813
12814 (define_split
12815 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12816 (compare:CC
12817 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12818 (match_operand:SI 2 "reg_or_short_operand" ""))
12819 (const_int 0)))
12820 (set (match_operand:SI 0 "gpc_reg_operand" "")
12821 (gt:SI (match_dup 1) (match_dup 2)))]
12822 "TARGET_POWER && reload_completed"
12823 [(set (match_dup 0)
12824 (gt:SI (match_dup 1) (match_dup 2)))
12825 (set (match_dup 3)
12826 (compare:CC (match_dup 0)
12827 (const_int 0)))]
12828 "")
12829
12830 (define_insn ""
12831 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12832 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12833 (const_int 0))
12834 (match_operand:SI 2 "gpc_reg_operand" "r")))]
12835 "! TARGET_POWERPC64"
12836 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12837 [(set_attr "length" "12")])
12838
12839 (define_insn ""
12840 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
12841 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12842 (const_int 0))
12843 (match_operand:DI 2 "gpc_reg_operand" "r")))]
12844 "TARGET_POWERPC64"
12845 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12846 [(set_attr "length" "12")])
12847
12848 (define_insn ""
12849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12850 (compare:CC
12851 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12852 (const_int 0))
12853 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12854 (const_int 0)))
12855 (clobber (match_scratch:SI 3 "=&r,&r"))]
12856 "! TARGET_POWERPC64"
12857 "@
12858 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12859 #"
12860 [(set_attr "type" "compare")
12861 (set_attr "length" "12,16")])
12862
12863 (define_split
12864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12865 (compare:CC
12866 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12867 (const_int 0))
12868 (match_operand:SI 2 "gpc_reg_operand" ""))
12869 (const_int 0)))
12870 (clobber (match_scratch:SI 3 ""))]
12871 "! TARGET_POWERPC64 && reload_completed"
12872 [(set (match_dup 3)
12873 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12874 (match_dup 2)))
12875 (set (match_dup 0)
12876 (compare:CC (match_dup 3)
12877 (const_int 0)))]
12878 "")
12879
12880 (define_insn ""
12881 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12882 (compare:CC
12883 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12884 (const_int 0))
12885 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12886 (const_int 0)))
12887 (clobber (match_scratch:DI 3 "=&r,&r"))]
12888 "TARGET_POWERPC64"
12889 "@
12890 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12891 #"
12892 [(set_attr "type" "compare")
12893 (set_attr "length" "12,16")])
12894
12895 (define_split
12896 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12897 (compare:CC
12898 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12899 (const_int 0))
12900 (match_operand:DI 2 "gpc_reg_operand" ""))
12901 (const_int 0)))
12902 (clobber (match_scratch:DI 3 ""))]
12903 "TARGET_POWERPC64 && reload_completed"
12904 [(set (match_dup 3)
12905 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12906 (match_dup 2)))
12907 (set (match_dup 0)
12908 (compare:CC (match_dup 3)
12909 (const_int 0)))]
12910 "")
12911
12912 (define_insn ""
12913 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12914 (compare:CC
12915 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12916 (const_int 0))
12917 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12918 (const_int 0)))
12919 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12920 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12921 "! TARGET_POWERPC64"
12922 "@
12923 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12924 #"
12925 [(set_attr "type" "compare")
12926 (set_attr "length" "12,16")])
12927
12928 (define_split
12929 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12930 (compare:CC
12931 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12932 (const_int 0))
12933 (match_operand:SI 2 "gpc_reg_operand" ""))
12934 (const_int 0)))
12935 (set (match_operand:SI 0 "gpc_reg_operand" "")
12936 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12937 "! TARGET_POWERPC64 && reload_completed"
12938 [(set (match_dup 0)
12939 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12940 (set (match_dup 3)
12941 (compare:CC (match_dup 0)
12942 (const_int 0)))]
12943 "")
12944
12945 (define_insn ""
12946 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12947 (compare:CC
12948 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12949 (const_int 0))
12950 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12951 (const_int 0)))
12952 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12953 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12954 "TARGET_POWERPC64"
12955 "@
12956 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12957 #"
12958 [(set_attr "type" "compare")
12959 (set_attr "length" "12,16")])
12960
12961 (define_split
12962 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12963 (compare:CC
12964 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12965 (const_int 0))
12966 (match_operand:DI 2 "gpc_reg_operand" ""))
12967 (const_int 0)))
12968 (set (match_operand:DI 0 "gpc_reg_operand" "")
12969 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12970 "TARGET_POWERPC64 && reload_completed"
12971 [(set (match_dup 0)
12972 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12973 (set (match_dup 3)
12974 (compare:CC (match_dup 0)
12975 (const_int 0)))]
12976 "")
12977
12978 (define_insn ""
12979 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12980 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12981 (match_operand:SI 2 "reg_or_short_operand" "r"))
12982 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12983 "TARGET_POWER"
12984 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12985 [(set_attr "length" "12")])
12986
12987 (define_insn ""
12988 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12989 (compare:CC
12990 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12991 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12992 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12993 (const_int 0)))
12994 (clobber (match_scratch:SI 4 "=&r,&r"))]
12995 "TARGET_POWER"
12996 "@
12997 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12998 #"
12999 [(set_attr "type" "compare")
13000 (set_attr "length" "12,16")])
13001
13002 (define_split
13003 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13004 (compare:CC
13005 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13006 (match_operand:SI 2 "reg_or_short_operand" ""))
13007 (match_operand:SI 3 "gpc_reg_operand" ""))
13008 (const_int 0)))
13009 (clobber (match_scratch:SI 4 ""))]
13010 "TARGET_POWER && reload_completed"
13011 [(set (match_dup 4)
13012 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13013 (set (match_dup 0)
13014 (compare:CC (match_dup 4)
13015 (const_int 0)))]
13016 "")
13017
13018 (define_insn ""
13019 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13020 (compare:CC
13021 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13022 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13023 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13024 (const_int 0)))
13025 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13026 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13027 "TARGET_POWER"
13028 "@
13029 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13030 #"
13031 [(set_attr "type" "compare")
13032 (set_attr "length" "12,16")])
13033
13034 (define_split
13035 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13036 (compare:CC
13037 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13038 (match_operand:SI 2 "reg_or_short_operand" ""))
13039 (match_operand:SI 3 "gpc_reg_operand" ""))
13040 (const_int 0)))
13041 (set (match_operand:SI 0 "gpc_reg_operand" "")
13042 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13043 "TARGET_POWER && reload_completed"
13044 [(set (match_dup 0)
13045 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13046 (set (match_dup 4)
13047 (compare:CC (match_dup 0)
13048 (const_int 0)))]
13049 "")
13050
13051 (define_insn ""
13052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13053 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13054 (const_int 0))))]
13055 "! TARGET_POWERPC64"
13056 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13057 [(set_attr "length" "12")])
13058
13059 (define_insn ""
13060 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13061 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13062 (const_int 0))))]
13063 "TARGET_POWERPC64"
13064 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13065 [(set_attr "length" "12")])
13066
13067 (define_insn ""
13068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13069 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13070 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13071 "TARGET_POWER"
13072 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13073 [(set_attr "length" "12")])
13074
13075 (define_insn ""
13076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13077 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13078 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13079 "! TARGET_POWERPC64"
13080 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13081 [(set_attr "length" "12")])
13082
13083 (define_insn ""
13084 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13085 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13086 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13087 "TARGET_POWERPC64"
13088 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13089 [(set_attr "length" "12")])
13090
13091 (define_insn ""
13092 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13093 (compare:CC
13094 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13095 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13096 (const_int 0)))
13097 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13098 (gtu:SI (match_dup 1) (match_dup 2)))]
13099 "! TARGET_POWERPC64"
13100 "@
13101 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13102 #"
13103 [(set_attr "type" "compare")
13104 (set_attr "length" "12,16")])
13105
13106 (define_split
13107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13108 (compare:CC
13109 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13110 (match_operand:SI 2 "reg_or_short_operand" ""))
13111 (const_int 0)))
13112 (set (match_operand:SI 0 "gpc_reg_operand" "")
13113 (gtu:SI (match_dup 1) (match_dup 2)))]
13114 "! TARGET_POWERPC64 && reload_completed"
13115 [(set (match_dup 0)
13116 (gtu:SI (match_dup 1) (match_dup 2)))
13117 (set (match_dup 3)
13118 (compare:CC (match_dup 0)
13119 (const_int 0)))]
13120 "")
13121
13122 (define_insn ""
13123 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13124 (compare:CC
13125 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13126 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13127 (const_int 0)))
13128 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13129 (gtu:DI (match_dup 1) (match_dup 2)))]
13130 "TARGET_POWERPC64"
13131 "@
13132 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13133 #"
13134 [(set_attr "type" "compare")
13135 (set_attr "length" "12,16")])
13136
13137 (define_split
13138 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13139 (compare:CC
13140 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13141 (match_operand:DI 2 "reg_or_short_operand" ""))
13142 (const_int 0)))
13143 (set (match_operand:DI 0 "gpc_reg_operand" "")
13144 (gtu:DI (match_dup 1) (match_dup 2)))]
13145 "TARGET_POWERPC64 && reload_completed"
13146 [(set (match_dup 0)
13147 (gtu:DI (match_dup 1) (match_dup 2)))
13148 (set (match_dup 3)
13149 (compare:CC (match_dup 0)
13150 (const_int 0)))]
13151 "")
13152
13153 (define_insn ""
13154 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13155 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13156 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13157 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13158 "! TARGET_POWERPC64"
13159 "@
13160 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13161 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13162 [(set_attr "length" "8,12")])
13163
13164 (define_insn ""
13165 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13166 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13167 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13168 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13169 "TARGET_POWERPC64"
13170 "@
13171 addic %0,%1,%k2\;addze %0,%3
13172 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13173 [(set_attr "length" "8,12")])
13174
13175 (define_insn ""
13176 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13177 (compare:CC
13178 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13179 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13180 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13181 (const_int 0)))
13182 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13183 "! TARGET_POWERPC64"
13184 "@
13185 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13186 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13187 #
13188 #"
13189 [(set_attr "type" "compare")
13190 (set_attr "length" "8,12,12,16")])
13191
13192 (define_split
13193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13194 (compare:CC
13195 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13196 (match_operand:SI 2 "reg_or_short_operand" ""))
13197 (match_operand:SI 3 "gpc_reg_operand" ""))
13198 (const_int 0)))
13199 (clobber (match_scratch:SI 4 ""))]
13200 "! TARGET_POWERPC64 && reload_completed"
13201 [(set (match_dup 4)
13202 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13203 (match_dup 3)))
13204 (set (match_dup 0)
13205 (compare:CC (match_dup 4)
13206 (const_int 0)))]
13207 "")
13208
13209 (define_insn ""
13210 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13211 (compare:CC
13212 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13213 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13214 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13215 (const_int 0)))
13216 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13217 "TARGET_POWERPC64"
13218 "@
13219 addic %4,%1,%k2\;addze. %4,%3
13220 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13221 #
13222 #"
13223 [(set_attr "type" "compare")
13224 (set_attr "length" "8,12,12,16")])
13225
13226 (define_split
13227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13228 (compare:CC
13229 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13230 (match_operand:DI 2 "reg_or_short_operand" ""))
13231 (match_operand:DI 3 "gpc_reg_operand" ""))
13232 (const_int 0)))
13233 (clobber (match_scratch:DI 4 ""))]
13234 "TARGET_POWERPC64 && reload_completed"
13235 [(set (match_dup 4)
13236 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13237 (match_dup 3)))
13238 (set (match_dup 0)
13239 (compare:CC (match_dup 4)
13240 (const_int 0)))]
13241 "")
13242
13243 (define_insn ""
13244 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13245 (compare:CC
13246 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13247 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13248 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13249 (const_int 0)))
13250 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13251 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13252 "! TARGET_POWERPC64"
13253 "@
13254 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13255 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13256 #
13257 #"
13258 [(set_attr "type" "compare")
13259 (set_attr "length" "8,12,12,16")])
13260
13261 (define_split
13262 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13263 (compare:CC
13264 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13265 (match_operand:SI 2 "reg_or_short_operand" ""))
13266 (match_operand:SI 3 "gpc_reg_operand" ""))
13267 (const_int 0)))
13268 (set (match_operand:SI 0 "gpc_reg_operand" "")
13269 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13270 "! TARGET_POWERPC64 && reload_completed"
13271 [(set (match_dup 0)
13272 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13273 (set (match_dup 4)
13274 (compare:CC (match_dup 0)
13275 (const_int 0)))]
13276 "")
13277
13278 (define_insn ""
13279 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13280 (compare:CC
13281 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13282 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13283 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13284 (const_int 0)))
13285 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13286 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13287 "TARGET_POWERPC64"
13288 "@
13289 addic %0,%1,%k2\;addze. %0,%3
13290 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13291 #
13292 #"
13293 [(set_attr "type" "compare")
13294 (set_attr "length" "8,12,12,16")])
13295
13296 (define_split
13297 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13298 (compare:CC
13299 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13300 (match_operand:DI 2 "reg_or_short_operand" ""))
13301 (match_operand:DI 3 "gpc_reg_operand" ""))
13302 (const_int 0)))
13303 (set (match_operand:DI 0 "gpc_reg_operand" "")
13304 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13305 "TARGET_POWERPC64 && reload_completed"
13306 [(set (match_dup 0)
13307 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13308 (set (match_dup 4)
13309 (compare:CC (match_dup 0)
13310 (const_int 0)))]
13311 "")
13312
13313 (define_insn ""
13314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13315 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13316 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13317 "! TARGET_POWERPC64"
13318 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13319 [(set_attr "length" "8")])
13320
13321 (define_insn ""
13322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13323 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13324 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13325 "TARGET_POWERPC64"
13326 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13327 [(set_attr "length" "8")])
13328 \f
13329 ;; Define both directions of branch and return. If we need a reload
13330 ;; register, we'd rather use CR0 since it is much easier to copy a
13331 ;; register CC value to there.
13332
13333 (define_insn ""
13334 [(set (pc)
13335 (if_then_else (match_operator 1 "branch_comparison_operator"
13336 [(match_operand 2
13337 "cc_reg_operand" "y")
13338 (const_int 0)])
13339 (label_ref (match_operand 0 "" ""))
13340 (pc)))]
13341 ""
13342 "*
13343 {
13344 return output_cbranch (operands[1], \"%l0\", 0, insn);
13345 }"
13346 [(set_attr "type" "branch")])
13347
13348 (define_insn ""
13349 [(set (pc)
13350 (if_then_else (match_operator 0 "branch_comparison_operator"
13351 [(match_operand 1
13352 "cc_reg_operand" "y")
13353 (const_int 0)])
13354 (return)
13355 (pc)))]
13356 "direct_return ()"
13357 "*
13358 {
13359 return output_cbranch (operands[0], NULL, 0, insn);
13360 }"
13361 [(set_attr "type" "branch")
13362 (set_attr "length" "4")])
13363
13364 (define_insn ""
13365 [(set (pc)
13366 (if_then_else (match_operator 1 "branch_comparison_operator"
13367 [(match_operand 2
13368 "cc_reg_operand" "y")
13369 (const_int 0)])
13370 (pc)
13371 (label_ref (match_operand 0 "" ""))))]
13372 ""
13373 "*
13374 {
13375 return output_cbranch (operands[1], \"%l0\", 1, insn);
13376 }"
13377 [(set_attr "type" "branch")])
13378
13379 (define_insn ""
13380 [(set (pc)
13381 (if_then_else (match_operator 0 "branch_comparison_operator"
13382 [(match_operand 1
13383 "cc_reg_operand" "y")
13384 (const_int 0)])
13385 (pc)
13386 (return)))]
13387 "direct_return ()"
13388 "*
13389 {
13390 return output_cbranch (operands[0], NULL, 1, insn);
13391 }"
13392 [(set_attr "type" "branch")
13393 (set_attr "length" "4")])
13394
13395 ;; Logic on condition register values.
13396
13397 ; This pattern matches things like
13398 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13399 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13400 ; (const_int 1)))
13401 ; which are generated by the branch logic.
13402 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13403
13404 (define_insn ""
13405 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13406 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13407 [(match_operator:SI 2
13408 "branch_positive_comparison_operator"
13409 [(match_operand 3
13410 "cc_reg_operand" "y,y")
13411 (const_int 0)])
13412 (match_operator:SI 4
13413 "branch_positive_comparison_operator"
13414 [(match_operand 5
13415 "cc_reg_operand" "0,y")
13416 (const_int 0)])])
13417 (const_int 1)))]
13418 ""
13419 "cr%q1 %E0,%j2,%j4"
13420 [(set_attr "type" "cr_logical,delayed_cr")])
13421
13422 ; Why is the constant -1 here, but 1 in the previous pattern?
13423 ; Because ~1 has all but the low bit set.
13424 (define_insn ""
13425 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13426 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13427 [(not:SI (match_operator:SI 2
13428 "branch_positive_comparison_operator"
13429 [(match_operand 3
13430 "cc_reg_operand" "y,y")
13431 (const_int 0)]))
13432 (match_operator:SI 4
13433 "branch_positive_comparison_operator"
13434 [(match_operand 5
13435 "cc_reg_operand" "0,y")
13436 (const_int 0)])])
13437 (const_int -1)))]
13438 ""
13439 "cr%q1 %E0,%j2,%j4"
13440 [(set_attr "type" "cr_logical,delayed_cr")])
13441
13442 (define_insn ""
13443 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13444 (compare:CCEQ (match_operator:SI 1
13445 "branch_positive_comparison_operator"
13446 [(match_operand 2
13447 "cc_reg_operand" "0,y")
13448 (const_int 0)])
13449 (const_int 0)))]
13450 "!TARGET_SPE"
13451 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13452 [(set_attr "type" "cr_logical,delayed_cr")])
13453
13454 ;; If we are comparing the result of two comparisons, this can be done
13455 ;; using creqv or crxor.
13456
13457 (define_insn_and_split ""
13458 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13459 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13460 [(match_operand 2 "cc_reg_operand" "y")
13461 (const_int 0)])
13462 (match_operator 3 "branch_comparison_operator"
13463 [(match_operand 4 "cc_reg_operand" "y")
13464 (const_int 0)])))]
13465 ""
13466 "#"
13467 ""
13468 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13469 (match_dup 5)))]
13470 "
13471 {
13472 int positive_1, positive_2;
13473
13474 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13475 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13476
13477 if (! positive_1)
13478 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
13479 GET_CODE (operands[1])),
13480 SImode,
13481 operands[2], const0_rtx);
13482 else if (GET_MODE (operands[1]) != SImode)
13483 operands[1] = gen_rtx (GET_CODE (operands[1]),
13484 SImode,
13485 operands[2], const0_rtx);
13486
13487 if (! positive_2)
13488 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
13489 GET_CODE (operands[3])),
13490 SImode,
13491 operands[4], const0_rtx);
13492 else if (GET_MODE (operands[3]) != SImode)
13493 operands[3] = gen_rtx (GET_CODE (operands[3]),
13494 SImode,
13495 operands[4], const0_rtx);
13496
13497 if (positive_1 == positive_2)
13498 {
13499 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13500 operands[5] = constm1_rtx;
13501 }
13502 else
13503 {
13504 operands[5] = const1_rtx;
13505 }
13506 }")
13507
13508 ;; Unconditional branch and return.
13509
13510 (define_insn "jump"
13511 [(set (pc)
13512 (label_ref (match_operand 0 "" "")))]
13513 ""
13514 "b %l0"
13515 [(set_attr "type" "branch")])
13516
13517 (define_insn "return"
13518 [(return)]
13519 "direct_return ()"
13520 "{br|blr}"
13521 [(set_attr "type" "jmpreg")])
13522
13523 (define_expand "indirect_jump"
13524 [(set (pc) (match_operand 0 "register_operand" ""))]
13525 ""
13526 "
13527 {
13528 if (TARGET_32BIT)
13529 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13530 else
13531 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13532 DONE;
13533 }")
13534
13535 (define_insn "indirect_jumpsi"
13536 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13537 "TARGET_32BIT"
13538 "@
13539 bctr
13540 {br|blr}"
13541 [(set_attr "type" "jmpreg")])
13542
13543 (define_insn "indirect_jumpdi"
13544 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13545 "TARGET_64BIT"
13546 "@
13547 bctr
13548 blr"
13549 [(set_attr "type" "jmpreg")])
13550
13551 ;; Table jump for switch statements:
13552 (define_expand "tablejump"
13553 [(use (match_operand 0 "" ""))
13554 (use (label_ref (match_operand 1 "" "")))]
13555 ""
13556 "
13557 {
13558 if (TARGET_32BIT)
13559 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13560 else
13561 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13562 DONE;
13563 }")
13564
13565 (define_expand "tablejumpsi"
13566 [(set (match_dup 3)
13567 (plus:SI (match_operand:SI 0 "" "")
13568 (match_dup 2)))
13569 (parallel [(set (pc) (match_dup 3))
13570 (use (label_ref (match_operand 1 "" "")))])]
13571 "TARGET_32BIT"
13572 "
13573 { operands[0] = force_reg (SImode, operands[0]);
13574 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13575 operands[3] = gen_reg_rtx (SImode);
13576 }")
13577
13578 (define_expand "tablejumpdi"
13579 [(set (match_dup 4)
13580 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13581 (set (match_dup 3)
13582 (plus:DI (match_dup 4)
13583 (match_dup 2)))
13584 (parallel [(set (pc) (match_dup 3))
13585 (use (label_ref (match_operand 1 "" "")))])]
13586 "TARGET_64BIT"
13587 "
13588 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13589 operands[3] = gen_reg_rtx (DImode);
13590 operands[4] = gen_reg_rtx (DImode);
13591 }")
13592
13593 (define_insn ""
13594 [(set (pc)
13595 (match_operand:SI 0 "register_operand" "c,*l"))
13596 (use (label_ref (match_operand 1 "" "")))]
13597 "TARGET_32BIT"
13598 "@
13599 bctr
13600 {br|blr}"
13601 [(set_attr "type" "jmpreg")])
13602
13603 (define_insn ""
13604 [(set (pc)
13605 (match_operand:DI 0 "register_operand" "c,*l"))
13606 (use (label_ref (match_operand 1 "" "")))]
13607 "TARGET_64BIT"
13608 "@
13609 bctr
13610 blr"
13611 [(set_attr "type" "jmpreg")])
13612
13613 (define_insn "nop"
13614 [(const_int 0)]
13615 ""
13616 "{cror 0,0,0|nop}")
13617 \f
13618 ;; Define the subtract-one-and-jump insns, starting with the template
13619 ;; so loop.c knows what to generate.
13620
13621 (define_expand "doloop_end"
13622 [(use (match_operand 0 "" "")) ; loop pseudo
13623 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13624 (use (match_operand 2 "" "")) ; max iterations
13625 (use (match_operand 3 "" "")) ; loop level
13626 (use (match_operand 4 "" ""))] ; label
13627 ""
13628 "
13629 {
13630 /* Only use this on innermost loops. */
13631 if (INTVAL (operands[3]) > 1)
13632 FAIL;
13633 if (TARGET_POWERPC64)
13634 {
13635 if (GET_MODE (operands[0]) != DImode)
13636 FAIL;
13637 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13638 }
13639 else
13640 {
13641 if (GET_MODE (operands[0]) != SImode)
13642 FAIL;
13643 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13644 }
13645 DONE;
13646 }")
13647
13648 (define_expand "ctrsi"
13649 [(parallel [(set (pc)
13650 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13651 (const_int 1))
13652 (label_ref (match_operand 1 "" ""))
13653 (pc)))
13654 (set (match_dup 0)
13655 (plus:SI (match_dup 0)
13656 (const_int -1)))
13657 (clobber (match_scratch:CC 2 ""))
13658 (clobber (match_scratch:SI 3 ""))])]
13659 "! TARGET_POWERPC64"
13660 "")
13661
13662 (define_expand "ctrdi"
13663 [(parallel [(set (pc)
13664 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13665 (const_int 1))
13666 (label_ref (match_operand 1 "" ""))
13667 (pc)))
13668 (set (match_dup 0)
13669 (plus:DI (match_dup 0)
13670 (const_int -1)))
13671 (clobber (match_scratch:CC 2 ""))
13672 (clobber (match_scratch:DI 3 ""))])]
13673 "TARGET_POWERPC64"
13674 "")
13675
13676 ;; We need to be able to do this for any operand, including MEM, or we
13677 ;; will cause reload to blow up since we don't allow output reloads on
13678 ;; JUMP_INSNs.
13679 ;; For the length attribute to be calculated correctly, the
13680 ;; label MUST be operand 0.
13681
13682 (define_insn "*ctrsi_internal1"
13683 [(set (pc)
13684 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
13685 (const_int 1))
13686 (label_ref (match_operand 0 "" ""))
13687 (pc)))
13688 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13689 (plus:SI (match_dup 1)
13690 (const_int -1)))
13691 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13692 (clobber (match_scratch:SI 4 "=X,X,r"))]
13693 "! TARGET_POWERPC64"
13694 "*
13695 {
13696 if (which_alternative != 0)
13697 return \"#\";
13698 else if (get_attr_length (insn) == 4)
13699 return \"{bdn|bdnz} %l0\";
13700 else
13701 return \"bdz $+8\;b %l0\";
13702 }"
13703 [(set_attr "type" "branch")
13704 (set_attr "length" "4,12,16")])
13705
13706 (define_insn "*ctrsi_internal2"
13707 [(set (pc)
13708 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
13709 (const_int 1))
13710 (pc)
13711 (label_ref (match_operand 0 "" ""))))
13712 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13713 (plus:SI (match_dup 1)
13714 (const_int -1)))
13715 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13716 (clobber (match_scratch:SI 4 "=X,X,r"))]
13717 "! TARGET_POWERPC64"
13718 "*
13719 {
13720 if (which_alternative != 0)
13721 return \"#\";
13722 else if (get_attr_length (insn) == 4)
13723 return \"bdz %l0\";
13724 else
13725 return \"{bdn|bdnz} $+8\;b %l0\";
13726 }"
13727 [(set_attr "type" "branch")
13728 (set_attr "length" "4,12,16")])
13729
13730 (define_insn "*ctrdi_internal1"
13731 [(set (pc)
13732 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
13733 (const_int 1))
13734 (label_ref (match_operand 0 "" ""))
13735 (pc)))
13736 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13737 (plus:DI (match_dup 1)
13738 (const_int -1)))
13739 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13740 (clobber (match_scratch:DI 4 "=X,X,r"))]
13741 "TARGET_POWERPC64"
13742 "*
13743 {
13744 if (which_alternative != 0)
13745 return \"#\";
13746 else if (get_attr_length (insn) == 4)
13747 return \"{bdn|bdnz} %l0\";
13748 else
13749 return \"bdz $+8\;b %l0\";
13750 }"
13751 [(set_attr "type" "branch")
13752 (set_attr "length" "4,12,16")])
13753
13754 (define_insn "*ctrdi_internal2"
13755 [(set (pc)
13756 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
13757 (const_int 1))
13758 (pc)
13759 (label_ref (match_operand 0 "" ""))))
13760 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13761 (plus:DI (match_dup 1)
13762 (const_int -1)))
13763 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13764 (clobber (match_scratch:DI 4 "=X,X,r"))]
13765 "TARGET_POWERPC64"
13766 "*
13767 {
13768 if (which_alternative != 0)
13769 return \"#\";
13770 else if (get_attr_length (insn) == 4)
13771 return \"bdz %l0\";
13772 else
13773 return \"{bdn|bdnz} $+8\;b %l0\";
13774 }"
13775 [(set_attr "type" "branch")
13776 (set_attr "length" "4,12,16")])
13777
13778 ;; Similar, but we can use GE since we have a REG_NONNEG.
13779
13780 (define_insn "*ctrsi_internal3"
13781 [(set (pc)
13782 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
13783 (const_int 0))
13784 (label_ref (match_operand 0 "" ""))
13785 (pc)))
13786 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13787 (plus:SI (match_dup 1)
13788 (const_int -1)))
13789 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13790 (clobber (match_scratch:SI 4 "=X,X,r"))]
13791 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13792 "*
13793 {
13794 if (which_alternative != 0)
13795 return \"#\";
13796 else if (get_attr_length (insn) == 4)
13797 return \"{bdn|bdnz} %l0\";
13798 else
13799 return \"bdz $+8\;b %l0\";
13800 }"
13801 [(set_attr "type" "branch")
13802 (set_attr "length" "4,12,16")])
13803
13804 (define_insn "*ctrsi_internal4"
13805 [(set (pc)
13806 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
13807 (const_int 0))
13808 (pc)
13809 (label_ref (match_operand 0 "" ""))))
13810 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13811 (plus:SI (match_dup 1)
13812 (const_int -1)))
13813 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13814 (clobber (match_scratch:SI 4 "=X,X,r"))]
13815 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13816 "*
13817 {
13818 if (which_alternative != 0)
13819 return \"#\";
13820 else if (get_attr_length (insn) == 4)
13821 return \"bdz %l0\";
13822 else
13823 return \"{bdn|bdnz} $+8\;b %l0\";
13824 }"
13825 [(set_attr "type" "branch")
13826 (set_attr "length" "4,12,16")])
13827
13828 (define_insn "*ctrdi_internal3"
13829 [(set (pc)
13830 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
13831 (const_int 0))
13832 (label_ref (match_operand 0 "" ""))
13833 (pc)))
13834 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13835 (plus:DI (match_dup 1)
13836 (const_int -1)))
13837 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13838 (clobber (match_scratch:DI 4 "=X,X,r"))]
13839 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13840 "*
13841 {
13842 if (which_alternative != 0)
13843 return \"#\";
13844 else if (get_attr_length (insn) == 4)
13845 return \"{bdn|bdnz} %l0\";
13846 else
13847 return \"bdz $+8\;b %l0\";
13848 }"
13849 [(set_attr "type" "branch")
13850 (set_attr "length" "4,12,16")])
13851
13852 (define_insn "*ctrdi_internal4"
13853 [(set (pc)
13854 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
13855 (const_int 0))
13856 (pc)
13857 (label_ref (match_operand 0 "" ""))))
13858 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13859 (plus:DI (match_dup 1)
13860 (const_int -1)))
13861 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13862 (clobber (match_scratch:DI 4 "=X,X,r"))]
13863 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13864 "*
13865 {
13866 if (which_alternative != 0)
13867 return \"#\";
13868 else if (get_attr_length (insn) == 4)
13869 return \"bdz %l0\";
13870 else
13871 return \"{bdn|bdnz} $+8\;b %l0\";
13872 }"
13873 [(set_attr "type" "branch")
13874 (set_attr "length" "4,12,16")])
13875
13876 ;; Similar but use EQ
13877
13878 (define_insn "*ctrsi_internal5"
13879 [(set (pc)
13880 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13881 (const_int 1))
13882 (label_ref (match_operand 0 "" ""))
13883 (pc)))
13884 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13885 (plus:SI (match_dup 1)
13886 (const_int -1)))
13887 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13888 (clobber (match_scratch:SI 4 "=X,X,r"))]
13889 "! TARGET_POWERPC64"
13890 "*
13891 {
13892 if (which_alternative != 0)
13893 return \"#\";
13894 else if (get_attr_length (insn) == 4)
13895 return \"bdz %l0\";
13896 else
13897 return \"{bdn|bdnz} $+8\;b %l0\";
13898 }"
13899 [(set_attr "type" "branch")
13900 (set_attr "length" "4,12,16")])
13901
13902 (define_insn "*ctrsi_internal6"
13903 [(set (pc)
13904 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13905 (const_int 1))
13906 (pc)
13907 (label_ref (match_operand 0 "" ""))))
13908 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13909 (plus:SI (match_dup 1)
13910 (const_int -1)))
13911 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13912 (clobber (match_scratch:SI 4 "=X,X,r"))]
13913 "! TARGET_POWERPC64"
13914 "*
13915 {
13916 if (which_alternative != 0)
13917 return \"#\";
13918 else if (get_attr_length (insn) == 4)
13919 return \"{bdn|bdnz} %l0\";
13920 else
13921 return \"bdz $+8\;b %l0\";
13922 }"
13923 [(set_attr "type" "branch")
13924 (set_attr "length" "4,12,16")])
13925
13926 (define_insn "*ctrdi_internal5"
13927 [(set (pc)
13928 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
13929 (const_int 1))
13930 (label_ref (match_operand 0 "" ""))
13931 (pc)))
13932 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13933 (plus:DI (match_dup 1)
13934 (const_int -1)))
13935 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13936 (clobber (match_scratch:DI 4 "=X,X,r"))]
13937 "TARGET_POWERPC64"
13938 "*
13939 {
13940 if (which_alternative != 0)
13941 return \"#\";
13942 else if (get_attr_length (insn) == 4)
13943 return \"bdz %l0\";
13944 else
13945 return \"{bdn|bdnz} $+8\;b %l0\";
13946 }"
13947 [(set_attr "type" "branch")
13948 (set_attr "length" "4,12,16")])
13949
13950 (define_insn "*ctrdi_internal6"
13951 [(set (pc)
13952 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
13953 (const_int 1))
13954 (pc)
13955 (label_ref (match_operand 0 "" ""))))
13956 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
13957 (plus:DI (match_dup 1)
13958 (const_int -1)))
13959 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13960 (clobber (match_scratch:DI 4 "=X,X,r"))]
13961 "TARGET_POWERPC64"
13962 "*
13963 {
13964 if (which_alternative != 0)
13965 return \"#\";
13966 else if (get_attr_length (insn) == 4)
13967 return \"{bdn|bdnz} %l0\";
13968 else
13969 return \"bdz $+8\;b %l0\";
13970 }"
13971 [(set_attr "type" "branch")
13972 (set_attr "length" "4,12,16")])
13973
13974 ;; Now the splitters if we could not allocate the CTR register
13975
13976 (define_split
13977 [(set (pc)
13978 (if_then_else (match_operator 2 "comparison_operator"
13979 [(match_operand:SI 1 "gpc_reg_operand" "")
13980 (const_int 1)])
13981 (match_operand 5 "" "")
13982 (match_operand 6 "" "")))
13983 (set (match_operand:SI 0 "gpc_reg_operand" "")
13984 (plus:SI (match_dup 1)
13985 (const_int -1)))
13986 (clobber (match_scratch:CC 3 ""))
13987 (clobber (match_scratch:SI 4 ""))]
13988 "! TARGET_POWERPC64 && reload_completed"
13989 [(parallel [(set (match_dup 3)
13990 (compare:CC (plus:SI (match_dup 1)
13991 (const_int -1))
13992 (const_int 0)))
13993 (set (match_dup 0)
13994 (plus:SI (match_dup 1)
13995 (const_int -1)))])
13996 (set (pc) (if_then_else (match_dup 7)
13997 (match_dup 5)
13998 (match_dup 6)))]
13999 "
14000 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14001 const0_rtx); }")
14002
14003 (define_split
14004 [(set (pc)
14005 (if_then_else (match_operator 2 "comparison_operator"
14006 [(match_operand:SI 1 "gpc_reg_operand" "")
14007 (const_int 1)])
14008 (match_operand 5 "" "")
14009 (match_operand 6 "" "")))
14010 (set (match_operand:SI 0 "nonimmediate_operand" "")
14011 (plus:SI (match_dup 1) (const_int -1)))
14012 (clobber (match_scratch:CC 3 ""))
14013 (clobber (match_scratch:SI 4 ""))]
14014 "! TARGET_POWERPC64 && reload_completed
14015 && ! gpc_reg_operand (operands[0], SImode)"
14016 [(parallel [(set (match_dup 3)
14017 (compare:CC (plus:SI (match_dup 1)
14018 (const_int -1))
14019 (const_int 0)))
14020 (set (match_dup 4)
14021 (plus:SI (match_dup 1)
14022 (const_int -1)))])
14023 (set (match_dup 0)
14024 (match_dup 4))
14025 (set (pc) (if_then_else (match_dup 7)
14026 (match_dup 5)
14027 (match_dup 6)))]
14028 "
14029 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14030 const0_rtx); }")
14031 (define_split
14032 [(set (pc)
14033 (if_then_else (match_operator 2 "comparison_operator"
14034 [(match_operand:DI 1 "gpc_reg_operand" "")
14035 (const_int 1)])
14036 (match_operand 5 "" "")
14037 (match_operand 6 "" "")))
14038 (set (match_operand:DI 0 "gpc_reg_operand" "")
14039 (plus:DI (match_dup 1)
14040 (const_int -1)))
14041 (clobber (match_scratch:CC 3 ""))
14042 (clobber (match_scratch:DI 4 ""))]
14043 "TARGET_POWERPC64 && reload_completed"
14044 [(parallel [(set (match_dup 3)
14045 (compare:CC (plus:DI (match_dup 1)
14046 (const_int -1))
14047 (const_int 0)))
14048 (set (match_dup 0)
14049 (plus:DI (match_dup 1)
14050 (const_int -1)))])
14051 (set (pc) (if_then_else (match_dup 7)
14052 (match_dup 5)
14053 (match_dup 6)))]
14054 "
14055 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14056 const0_rtx); }")
14057
14058 (define_split
14059 [(set (pc)
14060 (if_then_else (match_operator 2 "comparison_operator"
14061 [(match_operand:DI 1 "gpc_reg_operand" "")
14062 (const_int 1)])
14063 (match_operand 5 "" "")
14064 (match_operand 6 "" "")))
14065 (set (match_operand:DI 0 "nonimmediate_operand" "")
14066 (plus:DI (match_dup 1) (const_int -1)))
14067 (clobber (match_scratch:CC 3 ""))
14068 (clobber (match_scratch:DI 4 ""))]
14069 "TARGET_POWERPC64 && reload_completed
14070 && ! gpc_reg_operand (operands[0], DImode)"
14071 [(parallel [(set (match_dup 3)
14072 (compare:CC (plus:DI (match_dup 1)
14073 (const_int -1))
14074 (const_int 0)))
14075 (set (match_dup 4)
14076 (plus:DI (match_dup 1)
14077 (const_int -1)))])
14078 (set (match_dup 0)
14079 (match_dup 4))
14080 (set (pc) (if_then_else (match_dup 7)
14081 (match_dup 5)
14082 (match_dup 6)))]
14083 "
14084 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14085 const0_rtx); }")
14086
14087 \f
14088 (define_insn "trap"
14089 [(trap_if (const_int 1) (const_int 0))]
14090 ""
14091 "{t 31,0,0|trap}")
14092
14093 (define_expand "conditional_trap"
14094 [(trap_if (match_operator 0 "trap_comparison_operator"
14095 [(match_dup 2) (match_dup 3)])
14096 (match_operand 1 "const_int_operand" ""))]
14097 ""
14098 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14099 operands[2] = rs6000_compare_op0;
14100 operands[3] = rs6000_compare_op1;")
14101
14102 (define_insn ""
14103 [(trap_if (match_operator 0 "trap_comparison_operator"
14104 [(match_operand:SI 1 "register_operand" "r")
14105 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14106 (const_int 0))]
14107 ""
14108 "{t|tw}%V0%I2 %1,%2")
14109
14110 (define_insn ""
14111 [(trap_if (match_operator 0 "trap_comparison_operator"
14112 [(match_operand:DI 1 "register_operand" "r")
14113 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14114 (const_int 0))]
14115 "TARGET_POWERPC64"
14116 "td%V0%I2 %1,%2")
14117 \f
14118 ;; Insns related to generating the function prologue and epilogue.
14119
14120 (define_expand "prologue"
14121 [(use (const_int 0))]
14122 "TARGET_SCHED_PROLOG"
14123 "
14124 {
14125 rs6000_emit_prologue ();
14126 DONE;
14127 }")
14128
14129 (define_insn "movesi_from_cr"
14130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14131 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14132 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
14133 ""
14134 "mfcr %0"
14135 [(set_attr "type" "mfcr")])
14136
14137 (define_insn "*stmw"
14138 [(match_parallel 0 "stmw_operation"
14139 [(set (match_operand:SI 1 "memory_operand" "=m")
14140 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14141 "TARGET_MULTIPLE"
14142 "{stm|stmw} %2,%1")
14143
14144 (define_insn "*save_fpregs_si"
14145 [(match_parallel 0 "any_operand"
14146 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14147 (use (match_operand:SI 2 "call_operand" "s"))
14148 (set (match_operand:DF 3 "memory_operand" "=m")
14149 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14150 "TARGET_32BIT"
14151 "bl %z2")
14152
14153 (define_insn "*save_fpregs_di"
14154 [(match_parallel 0 "any_operand"
14155 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14156 (use (match_operand:DI 2 "call_operand" "s"))
14157 (set (match_operand:DF 3 "memory_operand" "=m")
14158 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14159 "TARGET_64BIT"
14160 "bl %z2")
14161
14162 ; These are to explain that changes to the stack pointer should
14163 ; not be moved over stores to stack memory.
14164 (define_insn "stack_tie"
14165 [(set (match_operand:BLK 0 "memory_operand" "+m")
14166 (unspec:BLK [(match_dup 0)] 5))]
14167 ""
14168 ""
14169 [(set_attr "length" "0")])
14170
14171
14172 (define_expand "epilogue"
14173 [(use (const_int 0))]
14174 "TARGET_SCHED_PROLOG"
14175 "
14176 {
14177 rs6000_emit_epilogue (FALSE);
14178 DONE;
14179 }")
14180
14181 ; On some processors, doing the mtcrf one CC register at a time is
14182 ; faster (like on the 604e). On others, doing them all at once is
14183 ; faster; for instance, on the 601 and 750.
14184
14185 (define_expand "movsi_to_cr_one"
14186 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14187 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14188 (match_dup 2)] 20))]
14189 ""
14190 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14191
14192 (define_insn "*movsi_to_cr"
14193 [(match_parallel 0 "mtcrf_operation"
14194 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14195 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14196 (match_operand 3 "immediate_operand" "n")]
14197 20))])]
14198 ""
14199 "*
14200 {
14201 int mask = 0;
14202 int i;
14203 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14204 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14205 operands[4] = GEN_INT (mask);
14206 return \"mtcrf %4,%2\";
14207 }"
14208 [(set_attr "type" "mtcr")])
14209
14210 (define_insn "*mtcrfsi"
14211 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14212 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14213 (match_operand 2 "immediate_operand" "n")] 20))]
14214 "GET_CODE (operands[0]) == REG
14215 && CR_REGNO_P (REGNO (operands[0]))
14216 && GET_CODE (operands[2]) == CONST_INT
14217 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14218 "mtcrf %R0,%1"
14219 [(set_attr "type" "mtcr")])
14220
14221 ; The load-multiple instructions have similar properties.
14222 ; Note that "load_multiple" is a name known to the machine-independent
14223 ; code that actually corresponds to the powerpc load-string.
14224
14225 (define_insn "*lmw"
14226 [(match_parallel 0 "lmw_operation"
14227 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14228 (match_operand:SI 2 "memory_operand" "m"))])]
14229 "TARGET_MULTIPLE"
14230 "{lm|lmw} %1,%2")
14231
14232 (define_insn "*return_internal_si"
14233 [(return)
14234 (use (match_operand:SI 0 "register_operand" "lc"))]
14235 "TARGET_32BIT"
14236 "b%T0"
14237 [(set_attr "type" "jmpreg")])
14238
14239 (define_insn "*return_internal_di"
14240 [(return)
14241 (use (match_operand:DI 0 "register_operand" "lc"))]
14242 "TARGET_64BIT"
14243 "b%T0"
14244 [(set_attr "type" "jmpreg")])
14245
14246 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14247 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14248
14249 (define_insn "*return_and_restore_fpregs_si"
14250 [(match_parallel 0 "any_operand"
14251 [(return)
14252 (use (match_operand:SI 1 "register_operand" "l"))
14253 (use (match_operand:SI 2 "call_operand" "s"))
14254 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14255 (match_operand:DF 4 "memory_operand" "m"))])]
14256 "TARGET_32BIT"
14257 "b %z2")
14258
14259 (define_insn "*return_and_restore_fpregs_di"
14260 [(match_parallel 0 "any_operand"
14261 [(return)
14262 (use (match_operand:DI 1 "register_operand" "l"))
14263 (use (match_operand:DI 2 "call_operand" "s"))
14264 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14265 (match_operand:DF 4 "memory_operand" "m"))])]
14266 "TARGET_64BIT"
14267 "b %z2")
14268
14269 ; This is used in compiling the unwind routines.
14270 (define_expand "eh_return"
14271 [(use (match_operand 0 "general_operand" ""))
14272 (use (match_operand 1 "general_operand" ""))]
14273 ""
14274 "
14275 {
14276 #if TARGET_AIX
14277 rs6000_emit_eh_toc_restore (operands[0]);
14278 #endif
14279 if (TARGET_32BIT)
14280 emit_insn (gen_eh_set_lr_si (operands[1]));
14281 else
14282 emit_insn (gen_eh_set_lr_di (operands[1]));
14283 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
14284 DONE;
14285 }")
14286
14287 ; We can't expand this before we know where the link register is stored.
14288 (define_insn "eh_set_lr_si"
14289 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
14290 (clobber (match_scratch:SI 1 "=&b"))]
14291 "TARGET_32BIT"
14292 "#")
14293
14294 (define_insn "eh_set_lr_di"
14295 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
14296 (clobber (match_scratch:DI 1 "=&b"))]
14297 "TARGET_64BIT"
14298 "#")
14299
14300 (define_split
14301 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
14302 (clobber (match_scratch 1 ""))]
14303 "reload_completed"
14304 [(const_int 0)]
14305 "
14306 {
14307 rs6000_stack_t *info = rs6000_stack_info ();
14308
14309 if (info->lr_save_p)
14310 {
14311 rtx frame_rtx = stack_pointer_rtx;
14312 int sp_offset = 0;
14313 rtx tmp;
14314
14315 if (frame_pointer_needed
14316 || current_function_calls_alloca
14317 || info->total_size > 32767)
14318 {
14319 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
14320 frame_rtx = operands[1];
14321 }
14322 else if (info->push_p)
14323 sp_offset = info->total_size;
14324
14325 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14326 tmp = gen_rtx_MEM (Pmode, tmp);
14327 emit_move_insn (tmp, operands[0]);
14328 }
14329 else
14330 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14331 DONE;
14332 }")
14333
14334 (define_insn "prefetch"
14335 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14336 (match_operand:SI 1 "const_int_operand" "n")
14337 (match_operand:SI 2 "const_int_operand" "n"))]
14338 "TARGET_POWERPC"
14339 "*
14340 {
14341 if (GET_CODE (operands[0]) == REG)
14342 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14343 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14344 }"
14345 [(set_attr "type" "load")])
14346
14347 (include "altivec.md")
14348 (include "spe.md")