projects / gcc.git / blob
? search:


25fed1ffa8f34fb1d23b08c3166955dd69c3cada
[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2012 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 ;; This file is part of GCC.
6
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22
23 ;;
24 ;; REGNOS
25 ;;
26
27 (define_constants
28 [(STACK_POINTER_REGNUM 1)
29 (TOC_REGNUM 2)
30 (STATIC_CHAIN_REGNUM 11)
31 (HARD_FRAME_POINTER_REGNUM 31)
32 (LR_REGNO 65)
33 (CTR_REGNO 66)
34 (ARG_POINTER_REGNUM 67)
35 (CR0_REGNO 68)
36 (CR1_REGNO 69)
37 (CR2_REGNO 70)
38 (CR3_REGNO 71)
39 (CR4_REGNO 72)
40 (CR5_REGNO 73)
41 (CR6_REGNO 74)
42 (CR7_REGNO 75)
43 (MAX_CR_REGNO 75)
44 (CA_REGNO 76)
45 (FIRST_ALTIVEC_REGNO 77)
46 (LAST_ALTIVEC_REGNO 108)
47 (VRSAVE_REGNO 109)
48 (VSCR_REGNO 110)
49 (SPE_ACC_REGNO 111)
50 (SPEFSCR_REGNO 112)
51 (FRAME_POINTER_REGNUM 113)
52
53 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
54 (TOC_SAVE_OFFSET_32BIT 20)
55 (TOC_SAVE_OFFSET_64BIT 40)
56
57 ; Function TOC offset in the AIX function descriptor.
58 (AIX_FUNC_DESC_TOC_32BIT 4)
59 (AIX_FUNC_DESC_TOC_64BIT 8)
60
61 ; Static chain offset in the AIX function descriptor.
62 (AIX_FUNC_DESC_SC_32BIT 8)
63 (AIX_FUNC_DESC_SC_64BIT 16)
64 ])
65
66 ;;
67 ;; UNSPEC usage
68 ;;
69
70 (define_c_enum "unspec"
71 [UNSPEC_FRSP ; frsp for POWER machines
72 UNSPEC_PROBE_STACK ; probe stack memory reference
73 UNSPEC_TOCPTR ; address of a word pointing to the TOC
74 UNSPEC_TOC ; address of the TOC (more-or-less)
75 UNSPEC_MOVSI_GOT
76 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
77 UNSPEC_FCTIWZ
78 UNSPEC_FRIM
79 UNSPEC_FRIN
80 UNSPEC_FRIP
81 UNSPEC_FRIZ
82 UNSPEC_LD_MPIC ; load_macho_picbase
83 UNSPEC_MPIC_CORRECT ; macho_correct_pic
84 UNSPEC_TLSGD
85 UNSPEC_TLSLD
86 UNSPEC_MOVESI_FROM_CR
87 UNSPEC_MOVESI_TO_CR
88 UNSPEC_TLSDTPREL
89 UNSPEC_TLSDTPRELHA
90 UNSPEC_TLSDTPRELLO
91 UNSPEC_TLSGOTDTPREL
92 UNSPEC_TLSTPREL
93 UNSPEC_TLSTPRELHA
94 UNSPEC_TLSTPRELLO
95 UNSPEC_TLSGOTTPREL
96 UNSPEC_TLSTLS
97 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
98 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
99 UNSPEC_STFIWX
100 UNSPEC_POPCNTB
101 UNSPEC_FRES
102 UNSPEC_SP_SET
103 UNSPEC_SP_TEST
104 UNSPEC_SYNC
105 UNSPEC_LWSYNC
106 UNSPEC_SYNC_OP
107 UNSPEC_ATOMIC
108 UNSPEC_CMPXCHG
109 UNSPEC_XCHG
110 UNSPEC_AND
111 UNSPEC_DLMZB
112 UNSPEC_DLMZB_CR
113 UNSPEC_DLMZB_STRLEN
114 UNSPEC_RSQRT
115 UNSPEC_TOCREL
116 UNSPEC_MACHOPIC_OFFSET
117 UNSPEC_BPERM
118 UNSPEC_COPYSIGN
119 UNSPEC_PARITY
120 UNSPEC_FCTIW
121 UNSPEC_FCTID
122 UNSPEC_LFIWAX
123 UNSPEC_LFIWZX
124 UNSPEC_FCTIWUZ
125 UNSPEC_GRP_END_NOP
126 ])
127
128 ;;
129 ;; UNSPEC_VOLATILE usage
130 ;;
131
132 (define_c_enum "unspecv"
133 [UNSPECV_BLOCK
134 UNSPECV_LL ; load-locked
135 UNSPECV_SC ; store-conditional
136 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
137 UNSPECV_EH_RR ; eh_reg_restore
138 UNSPECV_ISYNC ; isync instruction
139 UNSPECV_MFTB ; move from time base
140 ])
141
142 \f
143 ;; Define an insn type attribute. This is used in function unit delay
144 ;; computations.
145 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
146 (const_string "integer"))
147
148 ;; Define floating point instruction sub-types for use with Xfpu.md
149 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
150
151 ;; Length (in bytes).
152 ; '(pc)' in the following doesn't include the instruction itself; it is
153 ; calculated as if the instruction had zero size.
154 (define_attr "length" ""
155 (if_then_else (eq_attr "type" "branch")
156 (if_then_else (and (ge (minus (match_dup 0) (pc))
157 (const_int -32768))
158 (lt (minus (match_dup 0) (pc))
159 (const_int 32764)))
160 (const_int 4)
161 (const_int 8))
162 (const_int 4)))
163
164 ;; Processor type -- this attribute must exactly match the processor_type
165 ;; enumeration in rs6000.h.
166
167 (define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
168 (const (symbol_ref "rs6000_cpu_attr")))
169
170
171 ;; If this instruction is microcoded on the CELL processor
172 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
173 (define_attr "cell_micro" "not,conditional,always"
174 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
175 (const_string "always")
176 (const_string "not")))
177
178 (automata_option "ndfa")
179
180 (include "rs64.md")
181 (include "mpc.md")
182 (include "40x.md")
183 (include "440.md")
184 (include "476.md")
185 (include "601.md")
186 (include "603.md")
187 (include "6xx.md")
188 (include "7xx.md")
189 (include "7450.md")
190 (include "8540.md")
191 (include "e300c2c3.md")
192 (include "e500mc.md")
193 (include "e500mc64.md")
194 (include "e5500.md")
195 (include "e6500.md")
196 (include "power4.md")
197 (include "power5.md")
198 (include "power6.md")
199 (include "power7.md")
200 (include "cell.md")
201 (include "xfpu.md")
202 (include "a2.md")
203 (include "titan.md")
204
205 (include "predicates.md")
206 (include "constraints.md")
207
208 (include "darwin.md")
209
210 \f
211 ;; Mode iterators
212
213 ; This mode iterator allows :GPR to be used to indicate the allowable size
214 ; of whole values in GPRs.
215 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
216
217 ; Any supported integer mode.
218 (define_mode_iterator INT [QI HI SI DI TI])
219
220 ; Any supported integer mode that fits in one register.
221 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
222
223 ; extend modes for DImode
224 (define_mode_iterator QHSI [QI HI SI])
225
226 ; SImode or DImode, even if DImode doesn't fit in GPRs.
227 (define_mode_iterator SDI [SI DI])
228
229 ; The size of a pointer. Also, the size of the value that a record-condition
230 ; (one with a '.') will compare; and the size used for arithmetic carries.
231 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
232
233 ; Any hardware-supported floating-point mode
234 (define_mode_iterator FP [
235 (SF "TARGET_HARD_FLOAT
236 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
237 (DF "TARGET_HARD_FLOAT
238 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
239 (TF "!TARGET_IEEEQUAD
240 && TARGET_HARD_FLOAT
241 && (TARGET_FPRS || TARGET_E500_DOUBLE)
242 && TARGET_LONG_DOUBLE_128")
243 (DD "TARGET_DFP")
244 (TD "TARGET_DFP")])
245
246 ; Any fma capable floating-point mode.
247 (define_mode_iterator FMA_F [
248 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
249 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
250 || VECTOR_UNIT_VSX_P (DFmode)")
251 (V2SF "TARGET_PAIRED_FLOAT")
252 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
253 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
254 ])
255
256 ; These modes do not fit in integer registers in 32-bit mode.
257 ; but on e500v2, the gpr are 64 bit registers
258 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
259
260 ; Iterator for reciprocal estimate instructions
261 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
262
263 ; Iterator for just SF/DF
264 (define_mode_iterator SFDF [SF DF])
265
266 ; Conditional returns.
267 (define_code_iterator any_return [return simple_return])
268 (define_code_attr return_pred [(return "direct_return ()")
269 (simple_return "1")])
270 (define_code_attr return_str [(return "") (simple_return "simple_")])
271
272 ; Various instructions that come in SI and DI forms.
273 ; A generic w/d attribute, for things like cmpw/cmpd.
274 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
275
276 ; DImode bits
277 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
278
279 ;; ISEL/ISEL64 target selection
280 (define_mode_attr sel [(SI "") (DI "64")])
281
282 ;; Suffix for reload patterns
283 (define_mode_attr ptrsize [(SI "32bit")
284 (DI "64bit")])
285
286 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
287 (DI "TARGET_64BIT")])
288
289 (define_mode_attr mptrsize [(SI "si")
290 (DI "di")])
291
292 (define_mode_attr ptrload [(SI "lwz")
293 (DI "ld")])
294
295 (define_mode_attr rreg [(SF "f")
296 (DF "ws")
297 (V4SF "wf")
298 (V2DF "wd")])
299
300 (define_mode_attr rreg2 [(SF "f")
301 (DF "d")])
302
303 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
304 (DF "TARGET_FCFID")])
305
306 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
307 (DF "TARGET_E500_DOUBLE")])
308
309 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
310 (DF "TARGET_DOUBLE_FLOAT")])
311 \f
312 ;; Start with fixed-point load and store insns. Here we put only the more
313 ;; complex forms. Basic data transfer is done later.
314
315 (define_expand "zero_extend<mode>di2"
316 [(set (match_operand:DI 0 "gpc_reg_operand" "")
317 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
318 "TARGET_POWERPC64"
319 "")
320
321 (define_insn "*zero_extend<mode>di2_internal1"
322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
323 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
324 "TARGET_POWERPC64"
325 "@
326 l<wd>z%U1%X1 %0,%1
327 rldicl %0,%1,0,<dbits>"
328 [(set_attr "type" "load,*")])
329
330 (define_insn "*zero_extend<mode>di2_internal2"
331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
332 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
333 (const_int 0)))
334 (clobber (match_scratch:DI 2 "=r,r"))]
335 "TARGET_64BIT"
336 "@
337 rldicl. %2,%1,0,<dbits>
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
341
342 (define_split
343 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
344 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (clobber (match_scratch:DI 2 ""))]
347 "TARGET_POWERPC64 && reload_completed"
348 [(set (match_dup 2)
349 (zero_extend:DI (match_dup 1)))
350 (set (match_dup 0)
351 (compare:CC (match_dup 2)
352 (const_int 0)))]
353 "")
354
355 (define_insn "*zero_extend<mode>di2_internal3"
356 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
358 (const_int 0)))
359 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
360 (zero_extend:DI (match_dup 1)))]
361 "TARGET_64BIT"
362 "@
363 rldicl. %0,%1,0,<dbits>
364 #"
365 [(set_attr "type" "compare")
366 (set_attr "length" "4,8")])
367
368 (define_split
369 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
370 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
371 (const_int 0)))
372 (set (match_operand:DI 0 "gpc_reg_operand" "")
373 (zero_extend:DI (match_dup 1)))]
374 "TARGET_POWERPC64 && reload_completed"
375 [(set (match_dup 0)
376 (zero_extend:DI (match_dup 1)))
377 (set (match_dup 2)
378 (compare:CC (match_dup 0)
379 (const_int 0)))]
380 "")
381
382 (define_insn "extendqidi2"
383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
384 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
385 "TARGET_POWERPC64"
386 "extsb %0,%1"
387 [(set_attr "type" "exts")])
388
389 (define_insn ""
390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (clobber (match_scratch:DI 2 "=r,r"))]
394 "TARGET_64BIT"
395 "@
396 extsb. %2,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
400
401 (define_split
402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (clobber (match_scratch:DI 2 ""))]
406 "TARGET_POWERPC64 && reload_completed"
407 [(set (match_dup 2)
408 (sign_extend:DI (match_dup 1)))
409 (set (match_dup 0)
410 (compare:CC (match_dup 2)
411 (const_int 0)))]
412 "")
413
414 (define_insn ""
415 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
416 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
417 (const_int 0)))
418 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
419 (sign_extend:DI (match_dup 1)))]
420 "TARGET_64BIT"
421 "@
422 extsb. %0,%1
423 #"
424 [(set_attr "type" "compare")
425 (set_attr "length" "4,8")])
426
427 (define_split
428 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
429 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_POWERPC64 && reload_completed"
434 [(set (match_dup 0)
435 (sign_extend:DI (match_dup 1)))
436 (set (match_dup 2)
437 (compare:CC (match_dup 0)
438 (const_int 0)))]
439 "")
440
441 (define_expand "extendhidi2"
442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
443 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
444 "TARGET_POWERPC64"
445 "")
446
447 (define_insn ""
448 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
449 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
450 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
451 "@
452 lha%U1%X1 %0,%1
453 extsh %0,%1"
454 [(set_attr "type" "load_ext,exts")])
455
456 (define_insn ""
457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
458 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
459 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
460 "extsh %0,%1"
461 [(set_attr "type" "exts")])
462
463 (define_insn ""
464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
465 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (clobber (match_scratch:DI 2 "=r,r"))]
468 "TARGET_64BIT"
469 "@
470 extsh. %2,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
474
475 (define_split
476 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (clobber (match_scratch:DI 2 ""))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 2)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 0)
484 (compare:CC (match_dup 2)
485 (const_int 0)))]
486 "")
487
488 (define_insn ""
489 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
490 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
491 (const_int 0)))
492 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_64BIT"
495 "@
496 extsh. %0,%1
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
500
501 (define_split
502 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
503 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (set (match_operand:DI 0 "gpc_reg_operand" "")
506 (sign_extend:DI (match_dup 1)))]
507 "TARGET_POWERPC64 && reload_completed"
508 [(set (match_dup 0)
509 (sign_extend:DI (match_dup 1)))
510 (set (match_dup 2)
511 (compare:CC (match_dup 0)
512 (const_int 0)))]
513 "")
514
515 (define_expand "extendsidi2"
516 [(set (match_operand:DI 0 "gpc_reg_operand" "")
517 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
518 "TARGET_POWERPC64"
519 "")
520
521 (define_insn ""
522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
523 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
524 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
525 "@
526 lwa%U1%X1 %0,%1
527 extsw %0,%1"
528 [(set_attr "type" "load_ext,exts")])
529
530 (define_insn ""
531 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
532 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
533 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
534 "extsw %0,%1"
535 [(set_attr "type" "exts")])
536
537 (define_insn ""
538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
540 (const_int 0)))
541 (clobber (match_scratch:DI 2 "=r,r"))]
542 "TARGET_64BIT"
543 "@
544 extsw. %2,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
548
549 (define_split
550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (clobber (match_scratch:DI 2 ""))]
554 "TARGET_POWERPC64 && reload_completed"
555 [(set (match_dup 2)
556 (sign_extend:DI (match_dup 1)))
557 (set (match_dup 0)
558 (compare:CC (match_dup 2)
559 (const_int 0)))]
560 "")
561
562 (define_insn ""
563 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
567 (sign_extend:DI (match_dup 1)))]
568 "TARGET_64BIT"
569 "@
570 extsw. %0,%1
571 #"
572 [(set_attr "type" "compare")
573 (set_attr "length" "4,8")])
574
575 (define_split
576 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
577 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
578 (const_int 0)))
579 (set (match_operand:DI 0 "gpc_reg_operand" "")
580 (sign_extend:DI (match_dup 1)))]
581 "TARGET_POWERPC64 && reload_completed"
582 [(set (match_dup 0)
583 (sign_extend:DI (match_dup 1)))
584 (set (match_dup 2)
585 (compare:CC (match_dup 0)
586 (const_int 0)))]
587 "")
588
589 (define_expand "zero_extendqisi2"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "")
591 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
592 ""
593 "")
594
595 (define_insn ""
596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
601 rlwinm %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
603
604 (define_insn ""
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (clobber (match_scratch:SI 2 "=r,r"))]
609 ""
610 "@
611 andi. %2,%1,0xff
612 #"
613 [(set_attr "type" "fast_compare,compare")
614 (set_attr "length" "4,8")])
615
616 (define_split
617 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
618 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:SI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:SI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
628
629 (define_insn ""
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:SI (match_dup 1)))]
635 ""
636 "@
637 andi. %0,%1,0xff
638 #"
639 [(set_attr "type" "fast_compare,compare")
640 (set_attr "length" "4,8")])
641
642 (define_split
643 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
644 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:SI 0 "gpc_reg_operand" "")
647 (zero_extend:SI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:SI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
655
656 (define_insn "extendqisi2"
657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
658 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
659 ""
660 "extsb %0,%1"
661 [(set_attr "type" "exts")])
662
663 (define_insn ""
664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
665 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
666 (const_int 0)))
667 (clobber (match_scratch:SI 2 "=r,r"))]
668 ""
669 "@
670 extsb. %2,%1
671 #"
672 [(set_attr "type" "compare")
673 (set_attr "length" "4,8")])
674
675 (define_split
676 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
677 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
678 (const_int 0)))
679 (clobber (match_scratch:SI 2 ""))]
680 "reload_completed"
681 [(set (match_dup 2)
682 (sign_extend:SI (match_dup 1)))
683 (set (match_dup 0)
684 (compare:CC (match_dup 2)
685 (const_int 0)))]
686 "")
687
688 (define_insn ""
689 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
690 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
693 (sign_extend:SI (match_dup 1)))]
694 ""
695 "@
696 extsb. %0,%1
697 #"
698 [(set_attr "type" "compare")
699 (set_attr "length" "4,8")])
700
701 (define_split
702 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
703 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
704 (const_int 0)))
705 (set (match_operand:SI 0 "gpc_reg_operand" "")
706 (sign_extend:SI (match_dup 1)))]
707 "reload_completed"
708 [(set (match_dup 0)
709 (sign_extend:SI (match_dup 1)))
710 (set (match_dup 2)
711 (compare:CC (match_dup 0)
712 (const_int 0)))]
713 "")
714
715 (define_insn ""
716 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
717 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
718 ""
719 "@
720 lbz%U1%X1 %0,%1
721 rlwinm %0,%1,0,0xff"
722 [(set_attr "type" "load,*")])
723
724 (define_insn ""
725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
726 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
727 (const_int 0)))
728 (clobber (match_scratch:HI 2 "=r,r"))]
729 ""
730 "@
731 andi. %2,%1,0xff
732 #"
733 [(set_attr "type" "fast_compare,compare")
734 (set_attr "length" "4,8")])
735
736 (define_split
737 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
738 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
739 (const_int 0)))
740 (clobber (match_scratch:HI 2 ""))]
741 "reload_completed"
742 [(set (match_dup 2)
743 (zero_extend:HI (match_dup 1)))
744 (set (match_dup 0)
745 (compare:CC (match_dup 2)
746 (const_int 0)))]
747 "")
748
749 (define_insn ""
750 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
751 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
752 (const_int 0)))
753 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
754 (zero_extend:HI (match_dup 1)))]
755 ""
756 "@
757 andi. %0,%1,0xff
758 #"
759 [(set_attr "type" "fast_compare,compare")
760 (set_attr "length" "4,8")])
761
762 (define_split
763 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
764 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
765 (const_int 0)))
766 (set (match_operand:HI 0 "gpc_reg_operand" "")
767 (zero_extend:HI (match_dup 1)))]
768 "reload_completed"
769 [(set (match_dup 0)
770 (zero_extend:HI (match_dup 1)))
771 (set (match_dup 2)
772 (compare:CC (match_dup 0)
773 (const_int 0)))]
774 "")
775
776 (define_insn "extendqihi2"
777 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
778 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
779 ""
780 "extsb %0,%1"
781 [(set_attr "type" "exts")])
782
783 (define_insn ""
784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
785 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
786 (const_int 0)))
787 (clobber (match_scratch:HI 2 "=r,r"))]
788 ""
789 "@
790 extsb. %2,%1
791 #"
792 [(set_attr "type" "compare")
793 (set_attr "length" "4,8")])
794
795 (define_split
796 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
797 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
798 (const_int 0)))
799 (clobber (match_scratch:HI 2 ""))]
800 "reload_completed"
801 [(set (match_dup 2)
802 (sign_extend:HI (match_dup 1)))
803 (set (match_dup 0)
804 (compare:CC (match_dup 2)
805 (const_int 0)))]
806 "")
807
808 (define_insn ""
809 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
810 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
811 (const_int 0)))
812 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
813 (sign_extend:HI (match_dup 1)))]
814 ""
815 "@
816 extsb. %0,%1
817 #"
818 [(set_attr "type" "compare")
819 (set_attr "length" "4,8")])
820
821 (define_split
822 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
823 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
824 (const_int 0)))
825 (set (match_operand:HI 0 "gpc_reg_operand" "")
826 (sign_extend:HI (match_dup 1)))]
827 "reload_completed"
828 [(set (match_dup 0)
829 (sign_extend:HI (match_dup 1)))
830 (set (match_dup 2)
831 (compare:CC (match_dup 0)
832 (const_int 0)))]
833 "")
834
835 (define_expand "zero_extendhisi2"
836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
838 ""
839 "")
840
841 (define_insn ""
842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
844 ""
845 "@
846 lhz%U1%X1 %0,%1
847 rlwinm %0,%1,0,0xffff"
848 [(set_attr "type" "load,*")])
849
850 (define_insn ""
851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
853 (const_int 0)))
854 (clobber (match_scratch:SI 2 "=r,r"))]
855 ""
856 "@
857 andi. %2,%1,0xffff
858 #"
859 [(set_attr "type" "fast_compare,compare")
860 (set_attr "length" "4,8")])
861
862 (define_split
863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (clobber (match_scratch:SI 2 ""))]
867 "reload_completed"
868 [(set (match_dup 2)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 0)
871 (compare:CC (match_dup 2)
872 (const_int 0)))]
873 "")
874
875 (define_insn ""
876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
878 (const_int 0)))
879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
880 (zero_extend:SI (match_dup 1)))]
881 ""
882 "@
883 andi. %0,%1,0xffff
884 #"
885 [(set_attr "type" "fast_compare,compare")
886 (set_attr "length" "4,8")])
887
888 (define_split
889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
894 "reload_completed"
895 [(set (match_dup 0)
896 (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 "")
901
902 (define_expand "extendhisi2"
903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
905 ""
906 "")
907
908 (define_insn ""
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
911 "rs6000_gen_cell_microcode"
912 "@
913 lha%U1%X1 %0,%1
914 extsh %0,%1"
915 [(set_attr "type" "load_ext,exts")])
916
917 (define_insn ""
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
920 "!rs6000_gen_cell_microcode"
921 "extsh %0,%1"
922 [(set_attr "type" "exts")])
923
924 (define_insn ""
925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
926 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
927 (const_int 0)))
928 (clobber (match_scratch:SI 2 "=r,r"))]
929 ""
930 "@
931 extsh. %2,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
935
936 (define_split
937 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
938 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
939 (const_int 0)))
940 (clobber (match_scratch:SI 2 ""))]
941 "reload_completed"
942 [(set (match_dup 2)
943 (sign_extend:SI (match_dup 1)))
944 (set (match_dup 0)
945 (compare:CC (match_dup 2)
946 (const_int 0)))]
947 "")
948
949 (define_insn ""
950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
954 (sign_extend:SI (match_dup 1)))]
955 ""
956 "@
957 extsh. %0,%1
958 #"
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
961
962 (define_split
963 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
965 (const_int 0)))
966 (set (match_operand:SI 0 "gpc_reg_operand" "")
967 (sign_extend:SI (match_dup 1)))]
968 "reload_completed"
969 [(set (match_dup 0)
970 (sign_extend:SI (match_dup 1)))
971 (set (match_dup 2)
972 (compare:CC (match_dup 0)
973 (const_int 0)))]
974 "")
975 \f
976 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
977
978 (define_insn "*macchwc"
979 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
980 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
981 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (const_int 16))
983 (sign_extend:SI
984 (match_operand:HI 1 "gpc_reg_operand" "r")))
985 (match_operand:SI 4 "gpc_reg_operand" "0"))
986 (const_int 0)))
987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
988 (plus:SI (mult:SI (ashiftrt:SI
989 (match_dup 2)
990 (const_int 16))
991 (sign_extend:SI
992 (match_dup 1)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "macchw. %0,%1,%2"
996 [(set_attr "type" "imul3")])
997
998 (define_insn "*macchw"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (ashiftrt:SI
1001 (match_operand:SI 2 "gpc_reg_operand" "r")
1002 (const_int 16))
1003 (sign_extend:SI
1004 (match_operand:HI 1 "gpc_reg_operand" "r")))
1005 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1006 "TARGET_MULHW"
1007 "macchw %0,%1,%2"
1008 [(set_attr "type" "imul3")])
1009
1010 (define_insn "*macchwuc"
1011 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1012 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1013 (match_operand:SI 2 "gpc_reg_operand" "r")
1014 (const_int 16))
1015 (zero_extend:SI
1016 (match_operand:HI 1 "gpc_reg_operand" "r")))
1017 (match_operand:SI 4 "gpc_reg_operand" "0"))
1018 (const_int 0)))
1019 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1020 (plus:SI (mult:SI (lshiftrt:SI
1021 (match_dup 2)
1022 (const_int 16))
1023 (zero_extend:SI
1024 (match_dup 1)))
1025 (match_dup 4)))]
1026 "TARGET_MULHW"
1027 "macchwu. %0,%1,%2"
1028 [(set_attr "type" "imul3")])
1029
1030 (define_insn "*macchwu"
1031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1032 (plus:SI (mult:SI (lshiftrt:SI
1033 (match_operand:SI 2 "gpc_reg_operand" "r")
1034 (const_int 16))
1035 (zero_extend:SI
1036 (match_operand:HI 1 "gpc_reg_operand" "r")))
1037 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1038 "TARGET_MULHW"
1039 "macchwu %0,%1,%2"
1040 [(set_attr "type" "imul3")])
1041
1042 (define_insn "*machhwc"
1043 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1044 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1045 (match_operand:SI 1 "gpc_reg_operand" "%r")
1046 (const_int 16))
1047 (ashiftrt:SI
1048 (match_operand:SI 2 "gpc_reg_operand" "r")
1049 (const_int 16)))
1050 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (const_int 0)))
1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (ashiftrt:SI
1054 (match_dup 1)
1055 (const_int 16))
1056 (ashiftrt:SI
1057 (match_dup 2)
1058 (const_int 16)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "machhw. %0,%1,%2"
1062 [(set_attr "type" "imul3")])
1063
1064 (define_insn "*machhw"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (ashiftrt:SI
1067 (match_operand:SI 1 "gpc_reg_operand" "%r")
1068 (const_int 16))
1069 (ashiftrt:SI
1070 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (const_int 16)))
1072 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1073 "TARGET_MULHW"
1074 "machhw %0,%1,%2"
1075 [(set_attr "type" "imul3")])
1076
1077 (define_insn "*machhwuc"
1078 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1079 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1080 (match_operand:SI 1 "gpc_reg_operand" "%r")
1081 (const_int 16))
1082 (lshiftrt:SI
1083 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (const_int 16)))
1085 (match_operand:SI 4 "gpc_reg_operand" "0"))
1086 (const_int 0)))
1087 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1088 (plus:SI (mult:SI (lshiftrt:SI
1089 (match_dup 1)
1090 (const_int 16))
1091 (lshiftrt:SI
1092 (match_dup 2)
1093 (const_int 16)))
1094 (match_dup 4)))]
1095 "TARGET_MULHW"
1096 "machhwu. %0,%1,%2"
1097 [(set_attr "type" "imul3")])
1098
1099 (define_insn "*machhwu"
1100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (lshiftrt:SI
1102 (match_operand:SI 1 "gpc_reg_operand" "%r")
1103 (const_int 16))
1104 (lshiftrt:SI
1105 (match_operand:SI 2 "gpc_reg_operand" "r")
1106 (const_int 16)))
1107 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1108 "TARGET_MULHW"
1109 "machhwu %0,%1,%2"
1110 [(set_attr "type" "imul3")])
1111
1112 (define_insn "*maclhwc"
1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1114 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1115 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1116 (sign_extend:SI
1117 (match_operand:HI 2 "gpc_reg_operand" "r")))
1118 (match_operand:SI 4 "gpc_reg_operand" "0"))
1119 (const_int 0)))
1120 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1121 (plus:SI (mult:SI (sign_extend:SI
1122 (match_dup 1))
1123 (sign_extend:SI
1124 (match_dup 2)))
1125 (match_dup 4)))]
1126 "TARGET_MULHW"
1127 "maclhw. %0,%1,%2"
1128 [(set_attr "type" "imul3")])
1129
1130 (define_insn "*maclhw"
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1132 (plus:SI (mult:SI (sign_extend:SI
1133 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1134 (sign_extend:SI
1135 (match_operand:HI 2 "gpc_reg_operand" "r")))
1136 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1137 "TARGET_MULHW"
1138 "maclhw %0,%1,%2"
1139 [(set_attr "type" "imul3")])
1140
1141 (define_insn "*maclhwuc"
1142 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1143 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1144 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1145 (zero_extend:SI
1146 (match_operand:HI 2 "gpc_reg_operand" "r")))
1147 (match_operand:SI 4 "gpc_reg_operand" "0"))
1148 (const_int 0)))
1149 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1150 (plus:SI (mult:SI (zero_extend:SI
1151 (match_dup 1))
1152 (zero_extend:SI
1153 (match_dup 2)))
1154 (match_dup 4)))]
1155 "TARGET_MULHW"
1156 "maclhwu. %0,%1,%2"
1157 [(set_attr "type" "imul3")])
1158
1159 (define_insn "*maclhwu"
1160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (plus:SI (mult:SI (zero_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (zero_extend:SI
1164 (match_operand:HI 2 "gpc_reg_operand" "r")))
1165 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1166 "TARGET_MULHW"
1167 "maclhwu %0,%1,%2"
1168 [(set_attr "type" "imul3")])
1169
1170 (define_insn "*nmacchwc"
1171 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1172 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1173 (mult:SI (ashiftrt:SI
1174 (match_operand:SI 2 "gpc_reg_operand" "r")
1175 (const_int 16))
1176 (sign_extend:SI
1177 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (minus:SI (match_dup 4)
1181 (mult:SI (ashiftrt:SI
1182 (match_dup 2)
1183 (const_int 16))
1184 (sign_extend:SI
1185 (match_dup 1)))))]
1186 "TARGET_MULHW"
1187 "nmacchw. %0,%1,%2"
1188 [(set_attr "type" "imul3")])
1189
1190 (define_insn "*nmacchw"
1191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1192 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1193 (mult:SI (ashiftrt:SI
1194 (match_operand:SI 2 "gpc_reg_operand" "r")
1195 (const_int 16))
1196 (sign_extend:SI
1197 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1198 "TARGET_MULHW"
1199 "nmacchw %0,%1,%2"
1200 [(set_attr "type" "imul3")])
1201
1202 (define_insn "*nmachhwc"
1203 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1204 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1205 (mult:SI (ashiftrt:SI
1206 (match_operand:SI 1 "gpc_reg_operand" "%r")
1207 (const_int 16))
1208 (ashiftrt:SI
1209 (match_operand:SI 2 "gpc_reg_operand" "r")
1210 (const_int 16))))
1211 (const_int 0)))
1212 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 (minus:SI (match_dup 4)
1214 (mult:SI (ashiftrt:SI
1215 (match_dup 1)
1216 (const_int 16))
1217 (ashiftrt:SI
1218 (match_dup 2)
1219 (const_int 16)))))]
1220 "TARGET_MULHW"
1221 "nmachhw. %0,%1,%2"
1222 [(set_attr "type" "imul3")])
1223
1224 (define_insn "*nmachhw"
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1227 (mult:SI (ashiftrt:SI
1228 (match_operand:SI 1 "gpc_reg_operand" "%r")
1229 (const_int 16))
1230 (ashiftrt:SI
1231 (match_operand:SI 2 "gpc_reg_operand" "r")
1232 (const_int 16)))))]
1233 "TARGET_MULHW"
1234 "nmachhw %0,%1,%2"
1235 [(set_attr "type" "imul3")])
1236
1237 (define_insn "*nmaclhwc"
1238 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1239 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1240 (mult:SI (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1242 (sign_extend:SI
1243 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1244 (const_int 0)))
1245 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1246 (minus:SI (match_dup 4)
1247 (mult:SI (sign_extend:SI
1248 (match_dup 1))
1249 (sign_extend:SI
1250 (match_dup 2)))))]
1251 "TARGET_MULHW"
1252 "nmaclhw. %0,%1,%2"
1253 [(set_attr "type" "imul3")])
1254
1255 (define_insn "*nmaclhw"
1256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1257 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1258 (mult:SI (sign_extend:SI
1259 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1260 (sign_extend:SI
1261 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1262 "TARGET_MULHW"
1263 "nmaclhw %0,%1,%2"
1264 [(set_attr "type" "imul3")])
1265
1266 (define_insn "*mulchwc"
1267 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1268 (compare:CC (mult:SI (ashiftrt:SI
1269 (match_operand:SI 2 "gpc_reg_operand" "r")
1270 (const_int 16))
1271 (sign_extend:SI
1272 (match_operand:HI 1 "gpc_reg_operand" "r")))
1273 (const_int 0)))
1274 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (ashiftrt:SI
1276 (match_dup 2)
1277 (const_int 16))
1278 (sign_extend:SI
1279 (match_dup 1))))]
1280 "TARGET_MULHW"
1281 "mulchw. %0,%1,%2"
1282 [(set_attr "type" "imul3")])
1283
1284 (define_insn "*mulchw"
1285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1286 (mult:SI (ashiftrt:SI
1287 (match_operand:SI 2 "gpc_reg_operand" "r")
1288 (const_int 16))
1289 (sign_extend:SI
1290 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1291 "TARGET_MULHW"
1292 "mulchw %0,%1,%2"
1293 [(set_attr "type" "imul3")])
1294
1295 (define_insn "*mulchwuc"
1296 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1297 (compare:CC (mult:SI (lshiftrt:SI
1298 (match_operand:SI 2 "gpc_reg_operand" "r")
1299 (const_int 16))
1300 (zero_extend:SI
1301 (match_operand:HI 1 "gpc_reg_operand" "r")))
1302 (const_int 0)))
1303 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1304 (mult:SI (lshiftrt:SI
1305 (match_dup 2)
1306 (const_int 16))
1307 (zero_extend:SI
1308 (match_dup 1))))]
1309 "TARGET_MULHW"
1310 "mulchwu. %0,%1,%2"
1311 [(set_attr "type" "imul3")])
1312
1313 (define_insn "*mulchwu"
1314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))
1318 (zero_extend:SI
1319 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1320 "TARGET_MULHW"
1321 "mulchwu %0,%1,%2"
1322 [(set_attr "type" "imul3")])
1323
1324 (define_insn "*mulhhwc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (ashiftrt:SI
1327 (match_operand:SI 1 "gpc_reg_operand" "%r")
1328 (const_int 16))
1329 (ashiftrt:SI
1330 (match_operand:SI 2 "gpc_reg_operand" "r")
1331 (const_int 16)))
1332 (const_int 0)))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (mult:SI (ashiftrt:SI
1335 (match_dup 1)
1336 (const_int 16))
1337 (ashiftrt:SI
1338 (match_dup 2)
1339 (const_int 16))))]
1340 "TARGET_MULHW"
1341 "mulhhw. %0,%1,%2"
1342 [(set_attr "type" "imul3")])
1343
1344 (define_insn "*mulhhw"
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (ashiftrt:SI
1347 (match_operand:SI 1 "gpc_reg_operand" "%r")
1348 (const_int 16))
1349 (ashiftrt:SI
1350 (match_operand:SI 2 "gpc_reg_operand" "r")
1351 (const_int 16))))]
1352 "TARGET_MULHW"
1353 "mulhhw %0,%1,%2"
1354 [(set_attr "type" "imul3")])
1355
1356 (define_insn "*mulhhwuc"
1357 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1358 (compare:CC (mult:SI (lshiftrt:SI
1359 (match_operand:SI 1 "gpc_reg_operand" "%r")
1360 (const_int 16))
1361 (lshiftrt:SI
1362 (match_operand:SI 2 "gpc_reg_operand" "r")
1363 (const_int 16)))
1364 (const_int 0)))
1365 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (lshiftrt:SI
1367 (match_dup 1)
1368 (const_int 16))
1369 (lshiftrt:SI
1370 (match_dup 2)
1371 (const_int 16))))]
1372 "TARGET_MULHW"
1373 "mulhhwu. %0,%1,%2"
1374 [(set_attr "type" "imul3")])
1375
1376 (define_insn "*mulhhwu"
1377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1378 (mult:SI (lshiftrt:SI
1379 (match_operand:SI 1 "gpc_reg_operand" "%r")
1380 (const_int 16))
1381 (lshiftrt:SI
1382 (match_operand:SI 2 "gpc_reg_operand" "r")
1383 (const_int 16))))]
1384 "TARGET_MULHW"
1385 "mulhhwu %0,%1,%2"
1386 [(set_attr "type" "imul3")])
1387
1388 (define_insn "*mullhwc"
1389 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1390 (compare:CC (mult:SI (sign_extend:SI
1391 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1392 (sign_extend:SI
1393 (match_operand:HI 2 "gpc_reg_operand" "r")))
1394 (const_int 0)))
1395 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (sign_extend:SI
1397 (match_dup 1))
1398 (sign_extend:SI
1399 (match_dup 2))))]
1400 "TARGET_MULHW"
1401 "mullhw. %0,%1,%2"
1402 [(set_attr "type" "imul3")])
1403
1404 (define_insn "*mullhw"
1405 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1406 (mult:SI (sign_extend:SI
1407 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1408 (sign_extend:SI
1409 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1410 "TARGET_MULHW"
1411 "mullhw %0,%1,%2"
1412 [(set_attr "type" "imul3")])
1413
1414 (define_insn "*mullhwuc"
1415 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1416 (compare:CC (mult:SI (zero_extend:SI
1417 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1418 (zero_extend:SI
1419 (match_operand:HI 2 "gpc_reg_operand" "r")))
1420 (const_int 0)))
1421 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1422 (mult:SI (zero_extend:SI
1423 (match_dup 1))
1424 (zero_extend:SI
1425 (match_dup 2))))]
1426 "TARGET_MULHW"
1427 "mullhwu. %0,%1,%2"
1428 [(set_attr "type" "imul3")])
1429
1430 (define_insn "*mullhwu"
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (mult:SI (zero_extend:SI
1433 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1434 (zero_extend:SI
1435 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1436 "TARGET_MULHW"
1437 "mullhwu %0,%1,%2"
1438 [(set_attr "type" "imul3")])
1439 \f
1440 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1441 (define_insn "dlmzb"
1442 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1443 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1444 (match_operand:SI 2 "gpc_reg_operand" "r")]
1445 UNSPEC_DLMZB_CR))
1446 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1447 (unspec:SI [(match_dup 1)
1448 (match_dup 2)]
1449 UNSPEC_DLMZB))]
1450 "TARGET_DLMZB"
1451 "dlmzb. %0,%1,%2")
1452
1453 (define_expand "strlensi"
1454 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1455 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1456 (match_operand:QI 2 "const_int_operand" "")
1457 (match_operand 3 "const_int_operand" "")]
1458 UNSPEC_DLMZB_STRLEN))
1459 (clobber (match_scratch:CC 4 "=x"))]
1460 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1461 {
1462 rtx result = operands[0];
1463 rtx src = operands[1];
1464 rtx search_char = operands[2];
1465 rtx align = operands[3];
1466 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1467 rtx loop_label, end_label, mem, cr0, cond;
1468 if (search_char != const0_rtx
1469 || GET_CODE (align) != CONST_INT
1470 || INTVAL (align) < 8)
1471 FAIL;
1472 word1 = gen_reg_rtx (SImode);
1473 word2 = gen_reg_rtx (SImode);
1474 scratch_dlmzb = gen_reg_rtx (SImode);
1475 scratch_string = gen_reg_rtx (Pmode);
1476 loop_label = gen_label_rtx ();
1477 end_label = gen_label_rtx ();
1478 addr = force_reg (Pmode, XEXP (src, 0));
1479 emit_move_insn (scratch_string, addr);
1480 emit_label (loop_label);
1481 mem = change_address (src, SImode, scratch_string);
1482 emit_move_insn (word1, mem);
1483 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1484 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1485 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1486 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1487 emit_jump_insn (gen_rtx_SET (VOIDmode,
1488 pc_rtx,
1489 gen_rtx_IF_THEN_ELSE (VOIDmode,
1490 cond,
1491 gen_rtx_LABEL_REF
1492 (VOIDmode,
1493 end_label),
1494 pc_rtx)));
1495 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1496 emit_jump_insn (gen_rtx_SET (VOIDmode,
1497 pc_rtx,
1498 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1499 emit_barrier ();
1500 emit_label (end_label);
1501 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1502 emit_insn (gen_subsi3 (result, scratch_string, addr));
1503 emit_insn (gen_subsi3 (result, result, const1_rtx));
1504 DONE;
1505 })
1506 \f
1507 ;; Fixed-point arithmetic insns.
1508
1509 (define_expand "add<mode>3"
1510 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1511 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1512 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1513 ""
1514 {
1515 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1516 {
1517 if (non_short_cint_operand (operands[2], DImode))
1518 FAIL;
1519 }
1520 else if (GET_CODE (operands[2]) == CONST_INT
1521 && ! add_operand (operands[2], <MODE>mode))
1522 {
1523 rtx tmp = ((!can_create_pseudo_p ()
1524 || rtx_equal_p (operands[0], operands[1]))
1525 ? operands[0] : gen_reg_rtx (<MODE>mode));
1526
1527 HOST_WIDE_INT val = INTVAL (operands[2]);
1528 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1529 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1530
1531 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1532 FAIL;
1533
1534 /* The ordering here is important for the prolog expander.
1535 When space is allocated from the stack, adding 'low' first may
1536 produce a temporary deallocation (which would be bad). */
1537 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1538 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1539 DONE;
1540 }
1541 })
1542
1543 ;; Discourage ai/addic because of carry but provide it in an alternative
1544 ;; allowing register zero as source.
1545 (define_insn "*add<mode>3_internal1"
1546 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1547 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1548 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1549 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1550 "@
1551 add %0,%1,%2
1552 addi %0,%1,%2
1553 addic %0,%1,%2
1554 addis %0,%1,%v2"
1555 [(set_attr "length" "4,4,4,4")])
1556
1557 (define_insn "addsi3_high"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1560 (high:SI (match_operand 2 "" ""))))]
1561 "TARGET_MACHO && !TARGET_64BIT"
1562 "addis %0,%1,ha16(%2)"
1563 [(set_attr "length" "4")])
1564
1565 (define_insn "*add<mode>3_internal2"
1566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1568 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1569 (const_int 0)))
1570 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1571 ""
1572 "@
1573 add. %3,%1,%2
1574 addic. %3,%1,%2
1575 #
1576 #"
1577 [(set_attr "type" "fast_compare,compare,compare,compare")
1578 (set_attr "length" "4,4,8,8")])
1579
1580 (define_split
1581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1582 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1583 (match_operand:GPR 2 "reg_or_short_operand" ""))
1584 (const_int 0)))
1585 (clobber (match_scratch:GPR 3 ""))]
1586 "reload_completed"
1587 [(set (match_dup 3)
1588 (plus:GPR (match_dup 1)
1589 (match_dup 2)))
1590 (set (match_dup 0)
1591 (compare:CC (match_dup 3)
1592 (const_int 0)))]
1593 "")
1594
1595 (define_insn "*add<mode>3_internal3"
1596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1599 (const_int 0)))
1600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1601 (plus:P (match_dup 1)
1602 (match_dup 2)))]
1603 ""
1604 "@
1605 add. %0,%1,%2
1606 addic. %0,%1,%2
1607 #
1608 #"
1609 [(set_attr "type" "fast_compare,compare,compare,compare")
1610 (set_attr "length" "4,4,8,8")])
1611
1612 (define_split
1613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1614 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1615 (match_operand:P 2 "reg_or_short_operand" ""))
1616 (const_int 0)))
1617 (set (match_operand:P 0 "gpc_reg_operand" "")
1618 (plus:P (match_dup 1) (match_dup 2)))]
1619 "reload_completed"
1620 [(set (match_dup 0)
1621 (plus:P (match_dup 1)
1622 (match_dup 2)))
1623 (set (match_dup 3)
1624 (compare:CC (match_dup 0)
1625 (const_int 0)))]
1626 "")
1627
1628 ;; Split an add that we can't do in one insn into two insns, each of which
1629 ;; does one 16-bit part. This is used by combine. Note that the low-order
1630 ;; add should be last in case the result gets used in an address.
1631
1632 (define_split
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1634 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1635 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1636 ""
1637 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1638 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1639 {
1640 HOST_WIDE_INT val = INTVAL (operands[2]);
1641 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1642 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1643
1644 operands[4] = GEN_INT (low);
1645 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1646 operands[3] = GEN_INT (rest);
1647 else if (can_create_pseudo_p ())
1648 {
1649 operands[3] = gen_reg_rtx (DImode);
1650 emit_move_insn (operands[3], operands[2]);
1651 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1652 DONE;
1653 }
1654 else
1655 FAIL;
1656 })
1657
1658 (define_insn "one_cmpl<mode>2"
1659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1660 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1661 ""
1662 "nor %0,%1,%1")
1663
1664 (define_insn ""
1665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1666 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1667 (const_int 0)))
1668 (clobber (match_scratch:P 2 "=r,r"))]
1669 ""
1670 "@
1671 nor. %2,%1,%1
1672 #"
1673 [(set_attr "type" "fast_compare,compare")
1674 (set_attr "length" "4,8")])
1675
1676 (define_split
1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1679 (const_int 0)))
1680 (clobber (match_scratch:P 2 ""))]
1681 "reload_completed"
1682 [(set (match_dup 2)
1683 (not:P (match_dup 1)))
1684 (set (match_dup 0)
1685 (compare:CC (match_dup 2)
1686 (const_int 0)))]
1687 "")
1688
1689 (define_insn ""
1690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1692 (const_int 0)))
1693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1694 (not:P (match_dup 1)))]
1695 ""
1696 "@
1697 nor. %0,%1,%1
1698 #"
1699 [(set_attr "type" "fast_compare,compare")
1700 (set_attr "length" "4,8")])
1701
1702 (define_split
1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1705 (const_int 0)))
1706 (set (match_operand:P 0 "gpc_reg_operand" "")
1707 (not:P (match_dup 1)))]
1708 "reload_completed"
1709 [(set (match_dup 0)
1710 (not:P (match_dup 1)))
1711 (set (match_dup 2)
1712 (compare:CC (match_dup 0)
1713 (const_int 0)))]
1714 "")
1715
1716 (define_insn ""
1717 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1718 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1719 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1720 ""
1721 "@
1722 subf %0,%2,%1
1723 subfic %0,%2,%1")
1724
1725 (define_insn ""
1726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1728 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1729 (const_int 0)))
1730 (clobber (match_scratch:P 3 "=r,r"))]
1731 ""
1732 "@
1733 subf. %3,%2,%1
1734 #"
1735 [(set_attr "type" "fast_compare")
1736 (set_attr "length" "4,8")])
1737
1738 (define_split
1739 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1740 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1741 (match_operand:P 2 "gpc_reg_operand" ""))
1742 (const_int 0)))
1743 (clobber (match_scratch:P 3 ""))]
1744 "reload_completed"
1745 [(set (match_dup 3)
1746 (minus:P (match_dup 1)
1747 (match_dup 2)))
1748 (set (match_dup 0)
1749 (compare:CC (match_dup 3)
1750 (const_int 0)))]
1751 "")
1752
1753 (define_insn ""
1754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1755 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1756 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1757 (const_int 0)))
1758 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1759 (minus:P (match_dup 1)
1760 (match_dup 2)))]
1761 ""
1762 "@
1763 subf. %0,%2,%1
1764 #"
1765 [(set_attr "type" "fast_compare")
1766 (set_attr "length" "4,8")])
1767
1768 (define_split
1769 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1770 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1771 (match_operand:P 2 "gpc_reg_operand" ""))
1772 (const_int 0)))
1773 (set (match_operand:P 0 "gpc_reg_operand" "")
1774 (minus:P (match_dup 1)
1775 (match_dup 2)))]
1776 "reload_completed"
1777 [(set (match_dup 0)
1778 (minus:P (match_dup 1)
1779 (match_dup 2)))
1780 (set (match_dup 3)
1781 (compare:CC (match_dup 0)
1782 (const_int 0)))]
1783 "")
1784
1785 (define_expand "sub<mode>3"
1786 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1787 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1788 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1789 ""
1790 "
1791 {
1792 if (GET_CODE (operands[2]) == CONST_INT)
1793 {
1794 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1795 negate_rtx (<MODE>mode, operands[2])));
1796 DONE;
1797 }
1798 }")
1799
1800 (define_expand "neg<mode>2"
1801 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1802 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1803 ""
1804 "")
1805
1806 (define_insn "*neg<mode>2_internal"
1807 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1808 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1809 ""
1810 "neg %0,%1")
1811
1812 (define_insn ""
1813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1814 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1815 (const_int 0)))
1816 (clobber (match_scratch:P 2 "=r,r"))]
1817 ""
1818 "@
1819 neg. %2,%1
1820 #"
1821 [(set_attr "type" "fast_compare")
1822 (set_attr "length" "4,8")])
1823
1824 (define_split
1825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1826 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1827 (const_int 0)))
1828 (clobber (match_scratch:P 2 ""))]
1829 "reload_completed"
1830 [(set (match_dup 2)
1831 (neg:P (match_dup 1)))
1832 (set (match_dup 0)
1833 (compare:CC (match_dup 2)
1834 (const_int 0)))]
1835 "")
1836
1837 (define_insn ""
1838 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1839 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1840 (const_int 0)))
1841 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1842 (neg:P (match_dup 1)))]
1843 ""
1844 "@
1845 neg. %0,%1
1846 #"
1847 [(set_attr "type" "fast_compare")
1848 (set_attr "length" "4,8")])
1849
1850 (define_split
1851 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1852 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1853 (const_int 0)))
1854 (set (match_operand:P 0 "gpc_reg_operand" "")
1855 (neg:P (match_dup 1)))]
1856 "reload_completed"
1857 [(set (match_dup 0)
1858 (neg:P (match_dup 1)))
1859 (set (match_dup 2)
1860 (compare:CC (match_dup 0)
1861 (const_int 0)))]
1862 "")
1863
1864 (define_insn "clz<mode>2"
1865 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1866 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1867 ""
1868 "cntlz<wd> %0,%1"
1869 [(set_attr "type" "cntlz")])
1870
1871 (define_expand "ctz<mode>2"
1872 [(set (match_dup 2)
1873 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1874 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1875 (match_dup 2)))
1876 (clobber (scratch:CC))])
1877 (set (match_dup 4) (clz:GPR (match_dup 3)))
1878 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1879 (minus:GPR (match_dup 5) (match_dup 4)))]
1880 ""
1881 {
1882 operands[2] = gen_reg_rtx (<MODE>mode);
1883 operands[3] = gen_reg_rtx (<MODE>mode);
1884 operands[4] = gen_reg_rtx (<MODE>mode);
1885 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1886 })
1887
1888 (define_expand "ffs<mode>2"
1889 [(set (match_dup 2)
1890 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1891 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1892 (match_dup 2)))
1893 (clobber (scratch:CC))])
1894 (set (match_dup 4) (clz:GPR (match_dup 3)))
1895 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1896 (minus:GPR (match_dup 5) (match_dup 4)))]
1897 ""
1898 {
1899 operands[2] = gen_reg_rtx (<MODE>mode);
1900 operands[3] = gen_reg_rtx (<MODE>mode);
1901 operands[4] = gen_reg_rtx (<MODE>mode);
1902 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1903 })
1904
1905 (define_insn "popcntb<mode>2"
1906 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1907 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1908 UNSPEC_POPCNTB))]
1909 "TARGET_POPCNTB"
1910 "popcntb %0,%1"
1911 [(set_attr "length" "4")
1912 (set_attr "type" "popcnt")])
1913
1914 (define_insn "popcntd<mode>2"
1915 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1916 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1917 "TARGET_POPCNTD"
1918 "popcnt<wd> %0,%1"
1919 [(set_attr "length" "4")
1920 (set_attr "type" "popcnt")])
1921
1922 (define_expand "popcount<mode>2"
1923 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1924 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1925 "TARGET_POPCNTB || TARGET_POPCNTD"
1926 {
1927 rs6000_emit_popcount (operands[0], operands[1]);
1928 DONE;
1929 })
1930
1931 (define_insn "parity<mode>2_cmpb"
1932 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1933 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1934 "TARGET_CMPB && TARGET_POPCNTB"
1935 "prty<wd> %0,%1")
1936
1937 (define_expand "parity<mode>2"
1938 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1939 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1940 "TARGET_POPCNTB"
1941 {
1942 rs6000_emit_parity (operands[0], operands[1]);
1943 DONE;
1944 })
1945
1946 ;; Since the hardware zeros the upper part of the register, save generating the
1947 ;; AND immediate if we are converting to unsigned
1948 (define_insn "*bswaphi2_extenddi"
1949 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1950 (zero_extend:DI
1951 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1952 "TARGET_POWERPC64"
1953 "lhbrx %0,%y1"
1954 [(set_attr "length" "4")
1955 (set_attr "type" "load")])
1956
1957 (define_insn "*bswaphi2_extendsi"
1958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1959 (zero_extend:SI
1960 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1961 ""
1962 "lhbrx %0,%y1"
1963 [(set_attr "length" "4")
1964 (set_attr "type" "load")])
1965
1966 (define_expand "bswaphi2"
1967 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1968 (bswap:HI
1969 (match_operand:HI 1 "reg_or_mem_operand" "")))
1970 (clobber (match_scratch:SI 2 ""))])]
1971 ""
1972 {
1973 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1974 operands[1] = force_reg (HImode, operands[1]);
1975 })
1976
1977 (define_insn "bswaphi2_internal"
1978 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1979 (bswap:HI
1980 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1981 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1982 ""
1983 "@
1984 lhbrx %0,%y1
1985 sthbrx %1,%y0
1986 #"
1987 [(set_attr "length" "4,4,12")
1988 (set_attr "type" "load,store,*")])
1989
1990 (define_split
1991 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1992 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1993 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1994 "reload_completed"
1995 [(set (match_dup 3)
1996 (zero_extract:SI (match_dup 4)
1997 (const_int 8)
1998 (const_int 16)))
1999 (set (match_dup 2)
2000 (and:SI (ashift:SI (match_dup 4)
2001 (const_int 8))
2002 (const_int 65280))) ;; 0xff00
2003 (set (match_dup 3)
2004 (ior:SI (match_dup 3)
2005 (match_dup 2)))]
2006 "
2007 {
2008 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2009 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2010 }")
2011
2012 (define_insn "*bswapsi2_extenddi"
2013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2014 (zero_extend:DI
2015 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2016 "TARGET_POWERPC64"
2017 "lwbrx %0,%y1"
2018 [(set_attr "length" "4")
2019 (set_attr "type" "load")])
2020
2021 (define_expand "bswapsi2"
2022 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2023 (bswap:SI
2024 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2025 ""
2026 {
2027 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2028 operands[1] = force_reg (SImode, operands[1]);
2029 })
2030
2031 (define_insn "*bswapsi2_internal"
2032 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2033 (bswap:SI
2034 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2035 ""
2036 "@
2037 lwbrx %0,%y1
2038 stwbrx %1,%y0
2039 #"
2040 [(set_attr "length" "4,4,12")
2041 (set_attr "type" "load,store,*")])
2042
2043 (define_split
2044 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2045 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2046 "reload_completed"
2047 [(set (match_dup 0)
2048 (rotate:SI (match_dup 1) (const_int 8)))
2049 (set (zero_extract:SI (match_dup 0)
2050 (const_int 8)
2051 (const_int 0))
2052 (match_dup 1))
2053 (set (zero_extract:SI (match_dup 0)
2054 (const_int 8)
2055 (const_int 16))
2056 (rotate:SI (match_dup 1)
2057 (const_int 16)))]
2058 "")
2059
2060 (define_expand "bswapdi2"
2061 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2062 (bswap:DI
2063 (match_operand:DI 1 "reg_or_mem_operand" "")))
2064 (clobber (match_scratch:DI 2 ""))
2065 (clobber (match_scratch:DI 3 ""))
2066 (clobber (match_scratch:DI 4 ""))])]
2067 ""
2068 {
2069 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2070 operands[1] = force_reg (DImode, operands[1]);
2071
2072 if (!TARGET_POWERPC64)
2073 {
2074 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2075 that uses 64-bit registers needs the same scratch registers as 64-bit
2076 mode. */
2077 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2078 DONE;
2079 }
2080 })
2081
2082 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2083 (define_insn "*bswapdi2_ldbrx"
2084 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2085 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2086 (clobber (match_scratch:DI 2 "=X,X,&r"))
2087 (clobber (match_scratch:DI 3 "=X,X,&r"))
2088 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2089 "TARGET_POWERPC64 && TARGET_LDBRX
2090 && (REG_P (operands[0]) || REG_P (operands[1]))"
2091 "@
2092 ldbrx %0,%y1
2093 stdbrx %1,%y0
2094 #"
2095 [(set_attr "length" "4,4,36")
2096 (set_attr "type" "load,store,*")])
2097
2098 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2099 (define_insn "*bswapdi2_64bit"
2100 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2101 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2102 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2103 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2104 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2105 "TARGET_POWERPC64 && !TARGET_LDBRX
2106 && (REG_P (operands[0]) || REG_P (operands[1]))"
2107 "#"
2108 [(set_attr "length" "16,12,36")])
2109
2110 (define_split
2111 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2112 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2113 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2114 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2115 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2116 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2117 [(const_int 0)]
2118 "
2119 {
2120 rtx dest = operands[0];
2121 rtx src = operands[1];
2122 rtx op2 = operands[2];
2123 rtx op3 = operands[3];
2124 rtx op4 = operands[4];
2125 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2126 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2127 rtx addr1;
2128 rtx addr2;
2129 rtx word_high;
2130 rtx word_low;
2131
2132 addr1 = XEXP (src, 0);
2133 if (GET_CODE (addr1) == PLUS)
2134 {
2135 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2136 if (TARGET_AVOID_XFORM)
2137 {
2138 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2139 addr2 = op2;
2140 }
2141 else
2142 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2143 }
2144 else if (TARGET_AVOID_XFORM)
2145 {
2146 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2147 addr2 = op2;
2148 }
2149 else
2150 {
2151 emit_move_insn (op2, GEN_INT (4));
2152 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2153 }
2154
2155 if (BYTES_BIG_ENDIAN)
2156 {
2157 word_high = change_address (src, SImode, addr1);
2158 word_low = change_address (src, SImode, addr2);
2159 }
2160 else
2161 {
2162 word_high = change_address (src, SImode, addr2);
2163 word_low = change_address (src, SImode, addr1);
2164 }
2165
2166 emit_insn (gen_bswapsi2 (op3_32, word_low));
2167 emit_insn (gen_bswapsi2 (op4_32, word_high));
2168 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2169 emit_insn (gen_iordi3 (dest, dest, op4));
2170 }")
2171
2172 (define_split
2173 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2174 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2175 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2176 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2177 (clobber (match_operand:DI 4 "" ""))]
2178 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2179 [(const_int 0)]
2180 "
2181 {
2182 rtx dest = operands[0];
2183 rtx src = operands[1];
2184 rtx op2 = operands[2];
2185 rtx op3 = operands[3];
2186 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2187 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2188 rtx addr1;
2189 rtx addr2;
2190 rtx word_high;
2191 rtx word_low;
2192
2193 addr1 = XEXP (dest, 0);
2194 if (GET_CODE (addr1) == PLUS)
2195 {
2196 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2197 if (TARGET_AVOID_XFORM)
2198 {
2199 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2200 addr2 = op2;
2201 }
2202 else
2203 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2204 }
2205 else if (TARGET_AVOID_XFORM)
2206 {
2207 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2208 addr2 = op2;
2209 }
2210 else
2211 {
2212 emit_move_insn (op2, GEN_INT (4));
2213 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2214 }
2215
2216 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2217 if (BYTES_BIG_ENDIAN)
2218 {
2219 word_high = change_address (dest, SImode, addr1);
2220 word_low = change_address (dest, SImode, addr2);
2221 emit_insn (gen_bswapsi2 (word_high, src_si));
2222 emit_insn (gen_bswapsi2 (word_low, op3_si));
2223 }
2224 else
2225 {
2226 word_high = change_address (dest, SImode, addr2);
2227 word_low = change_address (dest, SImode, addr1);
2228 emit_insn (gen_bswapsi2 (word_low, src_si));
2229 emit_insn (gen_bswapsi2 (word_high, op3_si));
2230 }
2231 }")
2232
2233 (define_split
2234 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2235 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2236 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2237 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2238 (clobber (match_operand:DI 4 "" ""))]
2239 "TARGET_POWERPC64 && reload_completed"
2240 [(const_int 0)]
2241 "
2242 {
2243 rtx dest = operands[0];
2244 rtx src = operands[1];
2245 rtx op2 = operands[2];
2246 rtx op3 = operands[3];
2247 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2248 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2249 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2250 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2251
2252 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2253 emit_insn (gen_bswapsi2 (dest_si, src_si));
2254 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2255 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2256 emit_insn (gen_iordi3 (dest, dest, op3));
2257 }")
2258
2259 (define_insn "bswapdi2_32bit"
2260 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2261 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2262 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2263 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2264 "#"
2265 [(set_attr "length" "16,12,36")])
2266
2267 (define_split
2268 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2269 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2270 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2271 "!TARGET_POWERPC64 && reload_completed"
2272 [(const_int 0)]
2273 "
2274 {
2275 rtx dest = operands[0];
2276 rtx src = operands[1];
2277 rtx op2 = operands[2];
2278 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2279 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2280 rtx addr1;
2281 rtx addr2;
2282 rtx word_high;
2283 rtx word_low;
2284
2285 addr1 = XEXP (src, 0);
2286 if (GET_CODE (addr1) == PLUS)
2287 {
2288 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2289 if (TARGET_AVOID_XFORM)
2290 {
2291 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2292 addr2 = op2;
2293 }
2294 else
2295 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2296 }
2297 else if (TARGET_AVOID_XFORM)
2298 {
2299 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2300 addr2 = op2;
2301 }
2302 else
2303 {
2304 emit_move_insn (op2, GEN_INT (4));
2305 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2306 }
2307
2308 if (BYTES_BIG_ENDIAN)
2309 {
2310 word_high = change_address (src, SImode, addr1);
2311 word_low = change_address (src, SImode, addr2);
2312 }
2313 else
2314 {
2315 word_high = change_address (src, SImode, addr2);
2316 word_low = change_address (src, SImode, addr1);
2317 }
2318
2319 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2320 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2321 }")
2322
2323 (define_split
2324 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2325 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2326 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2327 "!TARGET_POWERPC64 && reload_completed"
2328 [(const_int 0)]
2329 "
2330 {
2331 rtx dest = operands[0];
2332 rtx src = operands[1];
2333 rtx op2 = operands[2];
2334 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2335 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2336 rtx addr1;
2337 rtx addr2;
2338 rtx word_high;
2339 rtx word_low;
2340
2341 addr1 = XEXP (dest, 0);
2342 if (GET_CODE (addr1) == PLUS)
2343 {
2344 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2345 if (TARGET_AVOID_XFORM)
2346 {
2347 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2348 addr2 = op2;
2349 }
2350 else
2351 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2352 }
2353 else if (TARGET_AVOID_XFORM)
2354 {
2355 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2356 addr2 = op2;
2357 }
2358 else
2359 {
2360 emit_move_insn (op2, GEN_INT (4));
2361 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2362 }
2363
2364 if (BYTES_BIG_ENDIAN)
2365 {
2366 word_high = change_address (dest, SImode, addr1);
2367 word_low = change_address (dest, SImode, addr2);
2368 }
2369 else
2370 {
2371 word_high = change_address (dest, SImode, addr2);
2372 word_low = change_address (dest, SImode, addr1);
2373 }
2374
2375 emit_insn (gen_bswapsi2 (word_high, src_low));
2376 emit_insn (gen_bswapsi2 (word_low, src_high));
2377 }")
2378
2379 (define_split
2380 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2381 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2382 (clobber (match_operand:SI 2 "" ""))]
2383 "!TARGET_POWERPC64 && reload_completed"
2384 [(const_int 0)]
2385 "
2386 {
2387 rtx dest = operands[0];
2388 rtx src = operands[1];
2389 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2390 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2391 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2392 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2393
2394 emit_insn (gen_bswapsi2 (dest_high, src_low));
2395 emit_insn (gen_bswapsi2 (dest_low, src_high));
2396 }")
2397
2398 (define_insn "mulsi3"
2399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2400 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2401 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2402 ""
2403 "@
2404 mullw %0,%1,%2
2405 mulli %0,%1,%2"
2406 [(set (attr "type")
2407 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2408 (const_string "imul3")
2409 (match_operand:SI 2 "short_cint_operand" "")
2410 (const_string "imul2")]
2411 (const_string "imul")))])
2412
2413 (define_insn "*mulsi3_internal1"
2414 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2415 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2416 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2417 (const_int 0)))
2418 (clobber (match_scratch:SI 3 "=r,r"))]
2419 ""
2420 "@
2421 mullw. %3,%1,%2
2422 #"
2423 [(set_attr "type" "imul_compare")
2424 (set_attr "length" "4,8")])
2425
2426 (define_split
2427 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2428 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2429 (match_operand:SI 2 "gpc_reg_operand" ""))
2430 (const_int 0)))
2431 (clobber (match_scratch:SI 3 ""))]
2432 "reload_completed"
2433 [(set (match_dup 3)
2434 (mult:SI (match_dup 1) (match_dup 2)))
2435 (set (match_dup 0)
2436 (compare:CC (match_dup 3)
2437 (const_int 0)))]
2438 "")
2439
2440 (define_insn "*mulsi3_internal2"
2441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2442 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2443 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2444 (const_int 0)))
2445 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2446 (mult:SI (match_dup 1) (match_dup 2)))]
2447 ""
2448 "@
2449 mullw. %0,%1,%2
2450 #"
2451 [(set_attr "type" "imul_compare")
2452 (set_attr "length" "4,8")])
2453
2454 (define_split
2455 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2456 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2457 (match_operand:SI 2 "gpc_reg_operand" ""))
2458 (const_int 0)))
2459 (set (match_operand:SI 0 "gpc_reg_operand" "")
2460 (mult:SI (match_dup 1) (match_dup 2)))]
2461 "reload_completed"
2462 [(set (match_dup 0)
2463 (mult:SI (match_dup 1) (match_dup 2)))
2464 (set (match_dup 3)
2465 (compare:CC (match_dup 0)
2466 (const_int 0)))]
2467 "")
2468
2469
2470 (define_insn "udiv<mode>3"
2471 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2472 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2473 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2474 ""
2475 "div<wd>u %0,%1,%2"
2476 [(set (attr "type")
2477 (cond [(match_operand:SI 0 "" "")
2478 (const_string "idiv")]
2479 (const_string "ldiv")))])
2480
2481
2482 ;; For powers of two we can do srai/aze for divide and then adjust for
2483 ;; modulus. If it isn't a power of two, force operands into register and do
2484 ;; a normal divide.
2485 (define_expand "div<mode>3"
2486 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2487 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2488 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2489 ""
2490 {
2491 if (GET_CODE (operands[2]) != CONST_INT
2492 || INTVAL (operands[2]) <= 0
2493 || exact_log2 (INTVAL (operands[2])) < 0)
2494 operands[2] = force_reg (<MODE>mode, operands[2]);
2495 })
2496
2497 (define_insn "*div<mode>3"
2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2499 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2500 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2501 ""
2502 "div<wd> %0,%1,%2"
2503 [(set (attr "type")
2504 (cond [(match_operand:SI 0 "" "")
2505 (const_string "idiv")]
2506 (const_string "ldiv")))])
2507
2508 (define_expand "mod<mode>3"
2509 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2510 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2511 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2512 ""
2513 "
2514 {
2515 int i;
2516 rtx temp1;
2517 rtx temp2;
2518
2519 if (GET_CODE (operands[2]) != CONST_INT
2520 || INTVAL (operands[2]) <= 0
2521 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2522 FAIL;
2523
2524 temp1 = gen_reg_rtx (<MODE>mode);
2525 temp2 = gen_reg_rtx (<MODE>mode);
2526
2527 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2528 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2529 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2530 DONE;
2531 }")
2532
2533 (define_insn ""
2534 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2535 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2536 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2537 ""
2538 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2539 [(set_attr "type" "two")
2540 (set_attr "length" "8")])
2541
2542 (define_insn ""
2543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2544 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2545 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2546 (const_int 0)))
2547 (clobber (match_scratch:P 3 "=r,r"))]
2548 ""
2549 "@
2550 sra<wd>i %3,%1,%p2\;addze. %3,%3
2551 #"
2552 [(set_attr "type" "compare")
2553 (set_attr "length" "8,12")
2554 (set_attr "cell_micro" "not")])
2555
2556 (define_split
2557 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2558 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2559 (match_operand:GPR 2 "exact_log2_cint_operand"
2560 ""))
2561 (const_int 0)))
2562 (clobber (match_scratch:GPR 3 ""))]
2563 "reload_completed"
2564 [(set (match_dup 3)
2565 (div:<MODE> (match_dup 1) (match_dup 2)))
2566 (set (match_dup 0)
2567 (compare:CC (match_dup 3)
2568 (const_int 0)))]
2569 "")
2570
2571 (define_insn ""
2572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2573 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2574 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2575 (const_int 0)))
2576 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2577 (div:P (match_dup 1) (match_dup 2)))]
2578 ""
2579 "@
2580 sra<wd>i %0,%1,%p2\;addze. %0,%0
2581 #"
2582 [(set_attr "type" "compare")
2583 (set_attr "length" "8,12")
2584 (set_attr "cell_micro" "not")])
2585
2586 (define_split
2587 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2588 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2589 (match_operand:GPR 2 "exact_log2_cint_operand"
2590 ""))
2591 (const_int 0)))
2592 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2593 (div:GPR (match_dup 1) (match_dup 2)))]
2594 "reload_completed"
2595 [(set (match_dup 0)
2596 (div:<MODE> (match_dup 1) (match_dup 2)))
2597 (set (match_dup 3)
2598 (compare:CC (match_dup 0)
2599 (const_int 0)))]
2600 "")
2601 \f
2602 ;; Logical instructions
2603 ;; The logical instructions are mostly combined by using match_operator,
2604 ;; but the plain AND insns are somewhat different because there is no
2605 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2606 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2607
2608 (define_expand "andsi3"
2609 [(parallel
2610 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2611 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2612 (match_operand:SI 2 "and_operand" "")))
2613 (clobber (match_scratch:CC 3 ""))])]
2614 ""
2615 "")
2616
2617 (define_insn "andsi3_mc"
2618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2619 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2620 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2621 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2622 "rs6000_gen_cell_microcode"
2623 "@
2624 and %0,%1,%2
2625 rlwinm %0,%1,0,%m2,%M2
2626 andi. %0,%1,%b2
2627 andis. %0,%1,%u2"
2628 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2629
2630 (define_insn "andsi3_nomc"
2631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2632 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2633 (match_operand:SI 2 "and_operand" "?r,T")))
2634 (clobber (match_scratch:CC 3 "=X,X"))]
2635 "!rs6000_gen_cell_microcode"
2636 "@
2637 and %0,%1,%2
2638 rlwinm %0,%1,0,%m2,%M2")
2639
2640 (define_insn "andsi3_internal0_nomc"
2641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2642 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2643 (match_operand:SI 2 "and_operand" "?r,T")))]
2644 "!rs6000_gen_cell_microcode"
2645 "@
2646 and %0,%1,%2
2647 rlwinm %0,%1,0,%m2,%M2")
2648
2649
2650 ;; Note to set cr's other than cr0 we do the and immediate and then
2651 ;; the test again -- this avoids a mfcr which on the higher end
2652 ;; machines causes an execution serialization
2653
2654 (define_insn "*andsi3_internal2_mc"
2655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2656 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2657 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2658 (const_int 0)))
2659 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2660 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2661 "TARGET_32BIT && rs6000_gen_cell_microcode"
2662 "@
2663 and. %3,%1,%2
2664 andi. %3,%1,%b2
2665 andis. %3,%1,%u2
2666 rlwinm. %3,%1,0,%m2,%M2
2667 #
2668 #
2669 #
2670 #"
2671 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2672 compare,compare,compare,compare")
2673 (set_attr "length" "4,4,4,4,8,8,8,8")])
2674
2675 (define_insn "*andsi3_internal3_mc"
2676 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2677 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2678 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2679 (const_int 0)))
2680 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2681 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2682 "TARGET_64BIT && rs6000_gen_cell_microcode"
2683 "@
2684 #
2685 andi. %3,%1,%b2
2686 andis. %3,%1,%u2
2687 rlwinm. %3,%1,0,%m2,%M2
2688 #
2689 #
2690 #
2691 #"
2692 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2693 compare,compare,compare")
2694 (set_attr "length" "8,4,4,4,8,8,8,8")])
2695
2696 (define_split
2697 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2698 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2699 (match_operand:GPR 2 "and_operand" ""))
2700 (const_int 0)))
2701 (clobber (match_scratch:GPR 3 ""))
2702 (clobber (match_scratch:CC 4 ""))]
2703 "reload_completed"
2704 [(parallel [(set (match_dup 3)
2705 (and:<MODE> (match_dup 1)
2706 (match_dup 2)))
2707 (clobber (match_dup 4))])
2708 (set (match_dup 0)
2709 (compare:CC (match_dup 3)
2710 (const_int 0)))]
2711 "")
2712
2713 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2714 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2715
2716 (define_split
2717 [(set (match_operand:CC 0 "cc_reg_operand" "")
2718 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2719 (match_operand:SI 2 "gpc_reg_operand" ""))
2720 (const_int 0)))
2721 (clobber (match_scratch:SI 3 ""))
2722 (clobber (match_scratch:CC 4 ""))]
2723 "TARGET_POWERPC64 && reload_completed"
2724 [(parallel [(set (match_dup 3)
2725 (and:SI (match_dup 1)
2726 (match_dup 2)))
2727 (clobber (match_dup 4))])
2728 (set (match_dup 0)
2729 (compare:CC (match_dup 3)
2730 (const_int 0)))]
2731 "")
2732
2733 (define_insn "*andsi3_internal4"
2734 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2735 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2736 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2737 (const_int 0)))
2738 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2739 (and:SI (match_dup 1)
2740 (match_dup 2)))
2741 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2742 "TARGET_32BIT && rs6000_gen_cell_microcode"
2743 "@
2744 and. %0,%1,%2
2745 andi. %0,%1,%b2
2746 andis. %0,%1,%u2
2747 rlwinm. %0,%1,0,%m2,%M2
2748 #
2749 #
2750 #
2751 #"
2752 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2753 compare,compare,compare,compare")
2754 (set_attr "length" "4,4,4,4,8,8,8,8")])
2755
2756 (define_insn "*andsi3_internal5_mc"
2757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2758 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2759 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2760 (const_int 0)))
2761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2762 (and:SI (match_dup 1)
2763 (match_dup 2)))
2764 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2765 "TARGET_64BIT && rs6000_gen_cell_microcode"
2766 "@
2767 #
2768 andi. %0,%1,%b2
2769 andis. %0,%1,%u2
2770 rlwinm. %0,%1,0,%m2,%M2
2771 #
2772 #
2773 #
2774 #"
2775 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2776 compare,compare,compare")
2777 (set_attr "length" "8,4,4,4,8,8,8,8")])
2778
2779 (define_split
2780 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2781 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2782 (match_operand:SI 2 "and_operand" ""))
2783 (const_int 0)))
2784 (set (match_operand:SI 0 "gpc_reg_operand" "")
2785 (and:SI (match_dup 1)
2786 (match_dup 2)))
2787 (clobber (match_scratch:CC 4 ""))]
2788 "reload_completed"
2789 [(parallel [(set (match_dup 0)
2790 (and:SI (match_dup 1)
2791 (match_dup 2)))
2792 (clobber (match_dup 4))])
2793 (set (match_dup 3)
2794 (compare:CC (match_dup 0)
2795 (const_int 0)))]
2796 "")
2797
2798 (define_split
2799 [(set (match_operand:CC 3 "cc_reg_operand" "")
2800 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2801 (match_operand:SI 2 "gpc_reg_operand" ""))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "")
2804 (and:SI (match_dup 1)
2805 (match_dup 2)))
2806 (clobber (match_scratch:CC 4 ""))]
2807 "TARGET_POWERPC64 && reload_completed"
2808 [(parallel [(set (match_dup 0)
2809 (and:SI (match_dup 1)
2810 (match_dup 2)))
2811 (clobber (match_dup 4))])
2812 (set (match_dup 3)
2813 (compare:CC (match_dup 0)
2814 (const_int 0)))]
2815 "")
2816
2817 ;; Handle the PowerPC64 rlwinm corner case
2818
2819 (define_insn_and_split "*andsi3_internal6"
2820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2821 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2822 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2823 "TARGET_POWERPC64"
2824 "#"
2825 "TARGET_POWERPC64"
2826 [(set (match_dup 0)
2827 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2828 (match_dup 4)))
2829 (set (match_dup 0)
2830 (rotate:SI (match_dup 0) (match_dup 5)))]
2831 "
2832 {
2833 int mb = extract_MB (operands[2]);
2834 int me = extract_ME (operands[2]);
2835 operands[3] = GEN_INT (me + 1);
2836 operands[5] = GEN_INT (32 - (me + 1));
2837 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2838 }"
2839 [(set_attr "length" "8")])
2840
2841 (define_expand "iorsi3"
2842 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2843 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2844 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2845 ""
2846 "
2847 {
2848 if (GET_CODE (operands[2]) == CONST_INT
2849 && ! logical_operand (operands[2], SImode))
2850 {
2851 HOST_WIDE_INT value = INTVAL (operands[2]);
2852 rtx tmp = ((!can_create_pseudo_p ()
2853 || rtx_equal_p (operands[0], operands[1]))
2854 ? operands[0] : gen_reg_rtx (SImode));
2855
2856 emit_insn (gen_iorsi3 (tmp, operands[1],
2857 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2858 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2859 DONE;
2860 }
2861 }")
2862
2863 (define_expand "xorsi3"
2864 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2865 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2866 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2867 ""
2868 "
2869 {
2870 if (GET_CODE (operands[2]) == CONST_INT
2871 && ! logical_operand (operands[2], SImode))
2872 {
2873 HOST_WIDE_INT value = INTVAL (operands[2]);
2874 rtx tmp = ((!can_create_pseudo_p ()
2875 || rtx_equal_p (operands[0], operands[1]))
2876 ? operands[0] : gen_reg_rtx (SImode));
2877
2878 emit_insn (gen_xorsi3 (tmp, operands[1],
2879 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2880 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2881 DONE;
2882 }
2883 }")
2884
2885 (define_insn "*boolsi3_internal1"
2886 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2887 (match_operator:SI 3 "boolean_or_operator"
2888 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2889 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2890 ""
2891 "@
2892 %q3 %0,%1,%2
2893 %q3i %0,%1,%b2
2894 %q3is %0,%1,%u2")
2895
2896 (define_insn "*boolsi3_internal2"
2897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2898 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2899 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2900 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2901 (const_int 0)))
2902 (clobber (match_scratch:SI 3 "=r,r"))]
2903 "TARGET_32BIT"
2904 "@
2905 %q4. %3,%1,%2
2906 #"
2907 [(set_attr "type" "fast_compare,compare")
2908 (set_attr "length" "4,8")])
2909
2910 (define_split
2911 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2912 (compare:CC (match_operator:SI 4 "boolean_operator"
2913 [(match_operand:SI 1 "gpc_reg_operand" "")
2914 (match_operand:SI 2 "gpc_reg_operand" "")])
2915 (const_int 0)))
2916 (clobber (match_scratch:SI 3 ""))]
2917 "TARGET_32BIT && reload_completed"
2918 [(set (match_dup 3) (match_dup 4))
2919 (set (match_dup 0)
2920 (compare:CC (match_dup 3)
2921 (const_int 0)))]
2922 "")
2923
2924 (define_insn "*boolsi3_internal3"
2925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2926 (compare:CC (match_operator:SI 4 "boolean_operator"
2927 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2928 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2929 (const_int 0)))
2930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2931 (match_dup 4))]
2932 "TARGET_32BIT"
2933 "@
2934 %q4. %0,%1,%2
2935 #"
2936 [(set_attr "type" "fast_compare,compare")
2937 (set_attr "length" "4,8")])
2938
2939 (define_split
2940 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2941 (compare:CC (match_operator:SI 4 "boolean_operator"
2942 [(match_operand:SI 1 "gpc_reg_operand" "")
2943 (match_operand:SI 2 "gpc_reg_operand" "")])
2944 (const_int 0)))
2945 (set (match_operand:SI 0 "gpc_reg_operand" "")
2946 (match_dup 4))]
2947 "TARGET_32BIT && reload_completed"
2948 [(set (match_dup 0) (match_dup 4))
2949 (set (match_dup 3)
2950 (compare:CC (match_dup 0)
2951 (const_int 0)))]
2952 "")
2953
2954 ;; Split a logical operation that we can't do in one insn into two insns,
2955 ;; each of which does one 16-bit part. This is used by combine.
2956
2957 (define_split
2958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2959 (match_operator:SI 3 "boolean_or_operator"
2960 [(match_operand:SI 1 "gpc_reg_operand" "")
2961 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2962 ""
2963 [(set (match_dup 0) (match_dup 4))
2964 (set (match_dup 0) (match_dup 5))]
2965 "
2966 {
2967 rtx i;
2968 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2969 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2970 operands[1], i);
2971 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2972 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2973 operands[0], i);
2974 }")
2975
2976 (define_insn "*boolcsi3_internal1"
2977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2978 (match_operator:SI 3 "boolean_operator"
2979 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2980 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2981 ""
2982 "%q3 %0,%2,%1")
2983
2984 (define_insn "*boolcsi3_internal2"
2985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2986 (compare:CC (match_operator:SI 4 "boolean_operator"
2987 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2988 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2989 (const_int 0)))
2990 (clobber (match_scratch:SI 3 "=r,r"))]
2991 "TARGET_32BIT"
2992 "@
2993 %q4. %3,%2,%1
2994 #"
2995 [(set_attr "type" "compare")
2996 (set_attr "length" "4,8")])
2997
2998 (define_split
2999 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3000 (compare:CC (match_operator:SI 4 "boolean_operator"
3001 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3002 (match_operand:SI 2 "gpc_reg_operand" "")])
3003 (const_int 0)))
3004 (clobber (match_scratch:SI 3 ""))]
3005 "TARGET_32BIT && reload_completed"
3006 [(set (match_dup 3) (match_dup 4))
3007 (set (match_dup 0)
3008 (compare:CC (match_dup 3)
3009 (const_int 0)))]
3010 "")
3011
3012 (define_insn "*boolcsi3_internal3"
3013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3014 (compare:CC (match_operator:SI 4 "boolean_operator"
3015 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3016 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3017 (const_int 0)))
3018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3019 (match_dup 4))]
3020 "TARGET_32BIT"
3021 "@
3022 %q4. %0,%2,%1
3023 #"
3024 [(set_attr "type" "compare")
3025 (set_attr "length" "4,8")])
3026
3027 (define_split
3028 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3029 (compare:CC (match_operator:SI 4 "boolean_operator"
3030 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3031 (match_operand:SI 2 "gpc_reg_operand" "")])
3032 (const_int 0)))
3033 (set (match_operand:SI 0 "gpc_reg_operand" "")
3034 (match_dup 4))]
3035 "TARGET_32BIT && reload_completed"
3036 [(set (match_dup 0) (match_dup 4))
3037 (set (match_dup 3)
3038 (compare:CC (match_dup 0)
3039 (const_int 0)))]
3040 "")
3041
3042 (define_insn "*boolccsi3_internal1"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (match_operator:SI 3 "boolean_operator"
3045 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3046 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3047 ""
3048 "%q3 %0,%1,%2")
3049
3050 (define_insn "*boolccsi3_internal2"
3051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3052 (compare:CC (match_operator:SI 4 "boolean_operator"
3053 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3054 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3055 (const_int 0)))
3056 (clobber (match_scratch:SI 3 "=r,r"))]
3057 "TARGET_32BIT"
3058 "@
3059 %q4. %3,%1,%2
3060 #"
3061 [(set_attr "type" "fast_compare,compare")
3062 (set_attr "length" "4,8")])
3063
3064 (define_split
3065 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3066 (compare:CC (match_operator:SI 4 "boolean_operator"
3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3068 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3069 (const_int 0)))
3070 (clobber (match_scratch:SI 3 ""))]
3071 "TARGET_32BIT && reload_completed"
3072 [(set (match_dup 3) (match_dup 4))
3073 (set (match_dup 0)
3074 (compare:CC (match_dup 3)
3075 (const_int 0)))]
3076 "")
3077
3078 (define_insn "*boolccsi3_internal3"
3079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3082 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3083 (const_int 0)))
3084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3085 (match_dup 4))]
3086 "TARGET_32BIT"
3087 "@
3088 %q4. %0,%1,%2
3089 #"
3090 [(set_attr "type" "fast_compare,compare")
3091 (set_attr "length" "4,8")])
3092
3093 (define_split
3094 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3095 (compare:CC (match_operator:SI 4 "boolean_operator"
3096 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3097 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3098 (const_int 0)))
3099 (set (match_operand:SI 0 "gpc_reg_operand" "")
3100 (match_dup 4))]
3101 "TARGET_32BIT && reload_completed"
3102 [(set (match_dup 0) (match_dup 4))
3103 (set (match_dup 3)
3104 (compare:CC (match_dup 0)
3105 (const_int 0)))]
3106 "")
3107 \f
3108 ;; Rotate and shift insns, in all their variants. These support shifts,
3109 ;; field inserts and extracts, and various combinations thereof.
3110 (define_expand "insv"
3111 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3112 (match_operand:SI 1 "const_int_operand" "")
3113 (match_operand:SI 2 "const_int_operand" ""))
3114 (match_operand 3 "gpc_reg_operand" ""))]
3115 ""
3116 "
3117 {
3118 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3119 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3120 compiler if the address of the structure is taken later. Likewise, do
3121 not handle invalid E500 subregs. */
3122 if (GET_CODE (operands[0]) == SUBREG
3123 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3124 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3125 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3126 FAIL;
3127
3128 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3129 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3130 operands[3]));
3131 else
3132 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3133 operands[3]));
3134 DONE;
3135 }")
3136
3137 (define_insn "insvsi_internal"
3138 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3139 (match_operand:SI 1 "const_int_operand" "i")
3140 (match_operand:SI 2 "const_int_operand" "i"))
3141 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3142 ""
3143 "*
3144 {
3145 int start = INTVAL (operands[2]) & 31;
3146 int size = INTVAL (operands[1]) & 31;
3147
3148 operands[4] = GEN_INT (32 - start - size);
3149 operands[1] = GEN_INT (start + size - 1);
3150 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3151 }"
3152 [(set_attr "type" "insert_word")])
3153
3154 (define_insn "*insvsi_internal1"
3155 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3156 (match_operand:SI 1 "const_int_operand" "i")
3157 (match_operand:SI 2 "const_int_operand" "i"))
3158 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3159 (match_operand:SI 4 "const_int_operand" "i")))]
3160 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3161 "*
3162 {
3163 int shift = INTVAL (operands[4]) & 31;
3164 int start = INTVAL (operands[2]) & 31;
3165 int size = INTVAL (operands[1]) & 31;
3166
3167 operands[4] = GEN_INT (shift - start - size);
3168 operands[1] = GEN_INT (start + size - 1);
3169 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3170 }"
3171 [(set_attr "type" "insert_word")])
3172
3173 (define_insn "*insvsi_internal2"
3174 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3175 (match_operand:SI 1 "const_int_operand" "i")
3176 (match_operand:SI 2 "const_int_operand" "i"))
3177 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3178 (match_operand:SI 4 "const_int_operand" "i")))]
3179 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3180 "*
3181 {
3182 int shift = INTVAL (operands[4]) & 31;
3183 int start = INTVAL (operands[2]) & 31;
3184 int size = INTVAL (operands[1]) & 31;
3185
3186 operands[4] = GEN_INT (32 - shift - start - size);
3187 operands[1] = GEN_INT (start + size - 1);
3188 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3189 }"
3190 [(set_attr "type" "insert_word")])
3191
3192 (define_insn "*insvsi_internal3"
3193 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3194 (match_operand:SI 1 "const_int_operand" "i")
3195 (match_operand:SI 2 "const_int_operand" "i"))
3196 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3197 (match_operand:SI 4 "const_int_operand" "i")))]
3198 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3199 "*
3200 {
3201 int shift = INTVAL (operands[4]) & 31;
3202 int start = INTVAL (operands[2]) & 31;
3203 int size = INTVAL (operands[1]) & 31;
3204
3205 operands[4] = GEN_INT (32 - shift - start - size);
3206 operands[1] = GEN_INT (start + size - 1);
3207 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3208 }"
3209 [(set_attr "type" "insert_word")])
3210
3211 (define_insn "*insvsi_internal4"
3212 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3213 (match_operand:SI 1 "const_int_operand" "i")
3214 (match_operand:SI 2 "const_int_operand" "i"))
3215 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3216 (match_operand:SI 4 "const_int_operand" "i")
3217 (match_operand:SI 5 "const_int_operand" "i")))]
3218 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3219 "*
3220 {
3221 int extract_start = INTVAL (operands[5]) & 31;
3222 int extract_size = INTVAL (operands[4]) & 31;
3223 int insert_start = INTVAL (operands[2]) & 31;
3224 int insert_size = INTVAL (operands[1]) & 31;
3225
3226 /* Align extract field with insert field */
3227 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3228 operands[1] = GEN_INT (insert_start + insert_size - 1);
3229 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3230 }"
3231 [(set_attr "type" "insert_word")])
3232
3233 ;; combine patterns for rlwimi
3234 (define_insn "*insvsi_internal5"
3235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3236 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3237 (match_operand:SI 1 "mask_operand" "i"))
3238 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3239 (match_operand:SI 2 "const_int_operand" "i"))
3240 (match_operand:SI 5 "mask_operand" "i"))))]
3241 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3242 "*
3243 {
3244 int me = extract_ME(operands[5]);
3245 int mb = extract_MB(operands[5]);
3246 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3247 operands[2] = GEN_INT(mb);
3248 operands[1] = GEN_INT(me);
3249 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3250 }"
3251 [(set_attr "type" "insert_word")])
3252
3253 (define_insn "*insvsi_internal6"
3254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3255 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3256 (match_operand:SI 2 "const_int_operand" "i"))
3257 (match_operand:SI 5 "mask_operand" "i"))
3258 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3259 (match_operand:SI 1 "mask_operand" "i"))))]
3260 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3261 "*
3262 {
3263 int me = extract_ME(operands[5]);
3264 int mb = extract_MB(operands[5]);
3265 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3266 operands[2] = GEN_INT(mb);
3267 operands[1] = GEN_INT(me);
3268 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3269 }"
3270 [(set_attr "type" "insert_word")])
3271
3272 (define_insn "insvdi_internal"
3273 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3274 (match_operand:SI 1 "const_int_operand" "i")
3275 (match_operand:SI 2 "const_int_operand" "i"))
3276 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3277 "TARGET_POWERPC64"
3278 "*
3279 {
3280 int start = INTVAL (operands[2]) & 63;
3281 int size = INTVAL (operands[1]) & 63;
3282
3283 operands[1] = GEN_INT (64 - start - size);
3284 return \"rldimi %0,%3,%H1,%H2\";
3285 }"
3286 [(set_attr "type" "insert_dword")])
3287
3288 (define_insn "*insvdi_internal2"
3289 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3290 (match_operand:SI 1 "const_int_operand" "i")
3291 (match_operand:SI 2 "const_int_operand" "i"))
3292 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3293 (match_operand:SI 4 "const_int_operand" "i")))]
3294 "TARGET_POWERPC64
3295 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3296 "*
3297 {
3298 int shift = INTVAL (operands[4]) & 63;
3299 int start = (INTVAL (operands[2]) & 63) - 32;
3300 int size = INTVAL (operands[1]) & 63;
3301
3302 operands[4] = GEN_INT (64 - shift - start - size);
3303 operands[2] = GEN_INT (start);
3304 operands[1] = GEN_INT (start + size - 1);
3305 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3306 }")
3307
3308 (define_insn "*insvdi_internal3"
3309 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3310 (match_operand:SI 1 "const_int_operand" "i")
3311 (match_operand:SI 2 "const_int_operand" "i"))
3312 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3313 (match_operand:SI 4 "const_int_operand" "i")))]
3314 "TARGET_POWERPC64
3315 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3316 "*
3317 {
3318 int shift = INTVAL (operands[4]) & 63;
3319 int start = (INTVAL (operands[2]) & 63) - 32;
3320 int size = INTVAL (operands[1]) & 63;
3321
3322 operands[4] = GEN_INT (64 - shift - start - size);
3323 operands[2] = GEN_INT (start);
3324 operands[1] = GEN_INT (start + size - 1);
3325 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3326 }")
3327
3328 (define_expand "extzv"
3329 [(set (match_operand 0 "gpc_reg_operand" "")
3330 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3331 (match_operand:SI 2 "const_int_operand" "")
3332 (match_operand:SI 3 "const_int_operand" "")))]
3333 ""
3334 "
3335 {
3336 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3337 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3338 compiler if the address of the structure is taken later. */
3339 if (GET_CODE (operands[0]) == SUBREG
3340 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3341 FAIL;
3342
3343 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3344 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3345 operands[3]));
3346 else
3347 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3348 operands[3]));
3349 DONE;
3350 }")
3351
3352 (define_insn "extzvsi_internal"
3353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3354 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3355 (match_operand:SI 2 "const_int_operand" "i")
3356 (match_operand:SI 3 "const_int_operand" "i")))]
3357 ""
3358 "*
3359 {
3360 int start = INTVAL (operands[3]) & 31;
3361 int size = INTVAL (operands[2]) & 31;
3362
3363 if (start + size >= 32)
3364 operands[3] = const0_rtx;
3365 else
3366 operands[3] = GEN_INT (start + size);
3367 return \"rlwinm %0,%1,%3,%s2,31\";
3368 }")
3369
3370 (define_insn "*extzvsi_internal1"
3371 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3372 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3373 (match_operand:SI 2 "const_int_operand" "i,i")
3374 (match_operand:SI 3 "const_int_operand" "i,i"))
3375 (const_int 0)))
3376 (clobber (match_scratch:SI 4 "=r,r"))]
3377 ""
3378 "*
3379 {
3380 int start = INTVAL (operands[3]) & 31;
3381 int size = INTVAL (operands[2]) & 31;
3382
3383 /* Force split for non-cc0 compare. */
3384 if (which_alternative == 1)
3385 return \"#\";
3386
3387 /* If the bit-field being tested fits in the upper or lower half of a
3388 word, it is possible to use andiu. or andil. to test it. This is
3389 useful because the condition register set-use delay is smaller for
3390 andi[ul]. than for rlinm. This doesn't work when the starting bit
3391 position is 0 because the LT and GT bits may be set wrong. */
3392
3393 if ((start > 0 && start + size <= 16) || start >= 16)
3394 {
3395 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3396 - (1 << (16 - (start & 15) - size))));
3397 if (start < 16)
3398 return \"andis. %4,%1,%3\";
3399 else
3400 return \"andi. %4,%1,%3\";
3401 }
3402
3403 if (start + size >= 32)
3404 operands[3] = const0_rtx;
3405 else
3406 operands[3] = GEN_INT (start + size);
3407 return \"rlwinm. %4,%1,%3,%s2,31\";
3408 }"
3409 [(set_attr "type" "delayed_compare")
3410 (set_attr "length" "4,8")])
3411
3412 (define_split
3413 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3414 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3415 (match_operand:SI 2 "const_int_operand" "")
3416 (match_operand:SI 3 "const_int_operand" ""))
3417 (const_int 0)))
3418 (clobber (match_scratch:SI 4 ""))]
3419 "reload_completed"
3420 [(set (match_dup 4)
3421 (zero_extract:SI (match_dup 1) (match_dup 2)
3422 (match_dup 3)))
3423 (set (match_dup 0)
3424 (compare:CC (match_dup 4)
3425 (const_int 0)))]
3426 "")
3427
3428 (define_insn "*extzvsi_internal2"
3429 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3430 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3431 (match_operand:SI 2 "const_int_operand" "i,i")
3432 (match_operand:SI 3 "const_int_operand" "i,i"))
3433 (const_int 0)))
3434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3435 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3436 ""
3437 "*
3438 {
3439 int start = INTVAL (operands[3]) & 31;
3440 int size = INTVAL (operands[2]) & 31;
3441
3442 /* Force split for non-cc0 compare. */
3443 if (which_alternative == 1)
3444 return \"#\";
3445
3446 /* Since we are using the output value, we can't ignore any need for
3447 a shift. The bit-field must end at the LSB. */
3448 if (start >= 16 && start + size == 32)
3449 {
3450 operands[3] = GEN_INT ((1 << size) - 1);
3451 return \"andi. %0,%1,%3\";
3452 }
3453
3454 if (start + size >= 32)
3455 operands[3] = const0_rtx;
3456 else
3457 operands[3] = GEN_INT (start + size);
3458 return \"rlwinm. %0,%1,%3,%s2,31\";
3459 }"
3460 [(set_attr "type" "delayed_compare")
3461 (set_attr "length" "4,8")])
3462
3463 (define_split
3464 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3465 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3466 (match_operand:SI 2 "const_int_operand" "")
3467 (match_operand:SI 3 "const_int_operand" ""))
3468 (const_int 0)))
3469 (set (match_operand:SI 0 "gpc_reg_operand" "")
3470 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3471 "reload_completed"
3472 [(set (match_dup 0)
3473 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3474 (set (match_dup 4)
3475 (compare:CC (match_dup 0)
3476 (const_int 0)))]
3477 "")
3478
3479 (define_insn "extzvdi_internal"
3480 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3481 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3482 (match_operand:SI 2 "const_int_operand" "i")
3483 (match_operand:SI 3 "const_int_operand" "i")))]
3484 "TARGET_POWERPC64"
3485 "*
3486 {
3487 int start = INTVAL (operands[3]) & 63;
3488 int size = INTVAL (operands[2]) & 63;
3489
3490 if (start + size >= 64)
3491 operands[3] = const0_rtx;
3492 else
3493 operands[3] = GEN_INT (start + size);
3494 operands[2] = GEN_INT (64 - size);
3495 return \"rldicl %0,%1,%3,%2\";
3496 }")
3497
3498 (define_insn "*extzvdi_internal1"
3499 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3500 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3501 (match_operand:SI 2 "const_int_operand" "i")
3502 (match_operand:SI 3 "const_int_operand" "i"))
3503 (const_int 0)))
3504 (clobber (match_scratch:DI 4 "=r"))]
3505 "TARGET_64BIT && rs6000_gen_cell_microcode"
3506 "*
3507 {
3508 int start = INTVAL (operands[3]) & 63;
3509 int size = INTVAL (operands[2]) & 63;
3510
3511 if (start + size >= 64)
3512 operands[3] = const0_rtx;
3513 else
3514 operands[3] = GEN_INT (start + size);
3515 operands[2] = GEN_INT (64 - size);
3516 return \"rldicl. %4,%1,%3,%2\";
3517 }"
3518 [(set_attr "type" "compare")])
3519
3520 (define_insn "*extzvdi_internal2"
3521 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3522 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3523 (match_operand:SI 2 "const_int_operand" "i")
3524 (match_operand:SI 3 "const_int_operand" "i"))
3525 (const_int 0)))
3526 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3527 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3528 "TARGET_64BIT && rs6000_gen_cell_microcode"
3529 "*
3530 {
3531 int start = INTVAL (operands[3]) & 63;
3532 int size = INTVAL (operands[2]) & 63;
3533
3534 if (start + size >= 64)
3535 operands[3] = const0_rtx;
3536 else
3537 operands[3] = GEN_INT (start + size);
3538 operands[2] = GEN_INT (64 - size);
3539 return \"rldicl. %0,%1,%3,%2\";
3540 }"
3541 [(set_attr "type" "compare")])
3542
3543 (define_insn "rotlsi3"
3544 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3545 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3546 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3547 ""
3548 "@
3549 rlwnm %0,%1,%2,0xffffffff
3550 rlwinm %0,%1,%h2,0xffffffff"
3551 [(set_attr "type" "var_shift_rotate,integer")])
3552
3553 (define_insn "*rotlsi3_64"
3554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3555 (zero_extend:DI
3556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3557 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3558 "TARGET_64BIT"
3559 "@
3560 rlwnm %0,%1,%2,0xffffffff
3561 rlwinm %0,%1,%h2,0xffffffff"
3562 [(set_attr "type" "var_shift_rotate,integer")])
3563
3564 (define_insn "*rotlsi3_internal2"
3565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3566 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3567 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3568 (const_int 0)))
3569 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3570 ""
3571 "@
3572 rlwnm. %3,%1,%2,0xffffffff
3573 rlwinm. %3,%1,%h2,0xffffffff
3574 #
3575 #"
3576 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3577 (set_attr "length" "4,4,8,8")])
3578
3579 (define_split
3580 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3581 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3582 (match_operand:SI 2 "reg_or_cint_operand" ""))
3583 (const_int 0)))
3584 (clobber (match_scratch:SI 3 ""))]
3585 "reload_completed"
3586 [(set (match_dup 3)
3587 (rotate:SI (match_dup 1) (match_dup 2)))
3588 (set (match_dup 0)
3589 (compare:CC (match_dup 3)
3590 (const_int 0)))]
3591 "")
3592
3593 (define_insn "*rotlsi3_internal3"
3594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3595 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3596 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3597 (const_int 0)))
3598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3599 (rotate:SI (match_dup 1) (match_dup 2)))]
3600 ""
3601 "@
3602 rlwnm. %0,%1,%2,0xffffffff
3603 rlwinm. %0,%1,%h2,0xffffffff
3604 #
3605 #"
3606 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3607 (set_attr "length" "4,4,8,8")])
3608
3609 (define_split
3610 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3611 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3612 (match_operand:SI 2 "reg_or_cint_operand" ""))
3613 (const_int 0)))
3614 (set (match_operand:SI 0 "gpc_reg_operand" "")
3615 (rotate:SI (match_dup 1) (match_dup 2)))]
3616 "reload_completed"
3617 [(set (match_dup 0)
3618 (rotate:SI (match_dup 1) (match_dup 2)))
3619 (set (match_dup 3)
3620 (compare:CC (match_dup 0)
3621 (const_int 0)))]
3622 "")
3623
3624 (define_insn "*rotlsi3_internal4"
3625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3626 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3627 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3628 (match_operand:SI 3 "mask_operand" "n,n")))]
3629 ""
3630 "@
3631 rlwnm %0,%1,%2,%m3,%M3
3632 rlwinm %0,%1,%h2,%m3,%M3"
3633 [(set_attr "type" "var_shift_rotate,integer")])
3634
3635 (define_insn "*rotlsi3_internal5"
3636 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3637 (compare:CC (and:SI
3638 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3639 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3640 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3641 (const_int 0)))
3642 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3643 ""
3644 "@
3645 rlwnm. %4,%1,%2,%m3,%M3
3646 rlwinm. %4,%1,%h2,%m3,%M3
3647 #
3648 #"
3649 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3650 (set_attr "length" "4,4,8,8")])
3651
3652 (define_split
3653 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3654 (compare:CC (and:SI
3655 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3656 (match_operand:SI 2 "reg_or_cint_operand" ""))
3657 (match_operand:SI 3 "mask_operand" ""))
3658 (const_int 0)))
3659 (clobber (match_scratch:SI 4 ""))]
3660 "reload_completed"
3661 [(set (match_dup 4)
3662 (and:SI (rotate:SI (match_dup 1)
3663 (match_dup 2))
3664 (match_dup 3)))
3665 (set (match_dup 0)
3666 (compare:CC (match_dup 4)
3667 (const_int 0)))]
3668 "")
3669
3670 (define_insn "*rotlsi3_internal6"
3671 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3672 (compare:CC (and:SI
3673 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3674 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3675 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3676 (const_int 0)))
3677 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3678 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3679 ""
3680 "@
3681 rlwnm. %0,%1,%2,%m3,%M3
3682 rlwinm. %0,%1,%h2,%m3,%M3
3683 #
3684 #"
3685 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3686 (set_attr "length" "4,4,8,8")])
3687
3688 (define_split
3689 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3690 (compare:CC (and:SI
3691 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3692 (match_operand:SI 2 "reg_or_cint_operand" ""))
3693 (match_operand:SI 3 "mask_operand" ""))
3694 (const_int 0)))
3695 (set (match_operand:SI 0 "gpc_reg_operand" "")
3696 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3697 "reload_completed"
3698 [(set (match_dup 0)
3699 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3700 (set (match_dup 4)
3701 (compare:CC (match_dup 0)
3702 (const_int 0)))]
3703 "")
3704
3705 (define_insn "*rotlsi3_internal7"
3706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3707 (zero_extend:SI
3708 (subreg:QI
3709 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3710 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3711 ""
3712 "rlw%I2nm %0,%1,%h2,0xff"
3713 [(set (attr "cell_micro")
3714 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3715 (const_string "not")
3716 (const_string "always")))])
3717
3718 (define_insn "*rotlsi3_internal8"
3719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3720 (compare:CC (zero_extend:SI
3721 (subreg:QI
3722 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3723 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3724 (const_int 0)))
3725 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3726 ""
3727 "@
3728 rlwnm. %3,%1,%2,0xff
3729 rlwinm. %3,%1,%h2,0xff
3730 #
3731 #"
3732 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3733 (set_attr "length" "4,4,8,8")])
3734
3735 (define_split
3736 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3737 (compare:CC (zero_extend:SI
3738 (subreg:QI
3739 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3740 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3741 (const_int 0)))
3742 (clobber (match_scratch:SI 3 ""))]
3743 "reload_completed"
3744 [(set (match_dup 3)
3745 (zero_extend:SI (subreg:QI
3746 (rotate:SI (match_dup 1)
3747 (match_dup 2)) 0)))
3748 (set (match_dup 0)
3749 (compare:CC (match_dup 3)
3750 (const_int 0)))]
3751 "")
3752
3753 (define_insn "*rotlsi3_internal9"
3754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3755 (compare:CC (zero_extend:SI
3756 (subreg:QI
3757 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3758 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3759 (const_int 0)))
3760 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3761 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3762 ""
3763 "@
3764 rlwnm. %0,%1,%2,0xff
3765 rlwinm. %0,%1,%h2,0xff
3766 #
3767 #"
3768 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3769 (set_attr "length" "4,4,8,8")])
3770
3771 (define_split
3772 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3773 (compare:CC (zero_extend:SI
3774 (subreg:QI
3775 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3776 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3777 (const_int 0)))
3778 (set (match_operand:SI 0 "gpc_reg_operand" "")
3779 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3780 "reload_completed"
3781 [(set (match_dup 0)
3782 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3783 (set (match_dup 3)
3784 (compare:CC (match_dup 0)
3785 (const_int 0)))]
3786 "")
3787
3788 (define_insn "*rotlsi3_internal10"
3789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3790 (zero_extend:SI
3791 (subreg:HI
3792 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3793 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
3794 ""
3795 "@
3796 rlwnm %0,%1,%2,0xffff
3797 rlwinm %0,%1,%h2,0xffff"
3798 [(set_attr "type" "var_shift_rotate,integer")])
3799
3800
3801 (define_insn "*rotlsi3_internal11"
3802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3803 (compare:CC (zero_extend:SI
3804 (subreg:HI
3805 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3806 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3807 (const_int 0)))
3808 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3809 ""
3810 "@
3811 rlwnm. %3,%1,%2,0xffff
3812 rlwinm. %3,%1,%h2,0xffff
3813 #
3814 #"
3815 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3816 (set_attr "length" "4,4,8,8")])
3817
3818 (define_split
3819 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3820 (compare:CC (zero_extend:SI
3821 (subreg:HI
3822 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3823 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3824 (const_int 0)))
3825 (clobber (match_scratch:SI 3 ""))]
3826 "reload_completed"
3827 [(set (match_dup 3)
3828 (zero_extend:SI (subreg:HI
3829 (rotate:SI (match_dup 1)
3830 (match_dup 2)) 0)))
3831 (set (match_dup 0)
3832 (compare:CC (match_dup 3)
3833 (const_int 0)))]
3834 "")
3835
3836 (define_insn "*rotlsi3_internal12"
3837 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3838 (compare:CC (zero_extend:SI
3839 (subreg:HI
3840 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3841 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3842 (const_int 0)))
3843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3844 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3845 ""
3846 "@
3847 rlwnm. %0,%1,%2,0xffff
3848 rlwinm. %0,%1,%h2,0xffff
3849 #
3850 #"
3851 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3852 (set_attr "length" "4,4,8,8")])
3853
3854 (define_split
3855 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3856 (compare:CC (zero_extend:SI
3857 (subreg:HI
3858 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3859 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3860 (const_int 0)))
3861 (set (match_operand:SI 0 "gpc_reg_operand" "")
3862 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3863 "reload_completed"
3864 [(set (match_dup 0)
3865 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3866 (set (match_dup 3)
3867 (compare:CC (match_dup 0)
3868 (const_int 0)))]
3869 "")
3870
3871 (define_insn "ashlsi3"
3872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3873 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3874 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3875 ""
3876 "@
3877 slw %0,%1,%2
3878 slwi %0,%1,%h2"
3879 [(set_attr "type" "var_shift_rotate,shift")])
3880
3881 (define_insn "*ashlsi3_64"
3882 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3883 (zero_extend:DI
3884 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3885 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3886 "TARGET_POWERPC64"
3887 "@
3888 slw %0,%1,%2
3889 slwi %0,%1,%h2"
3890 [(set_attr "type" "var_shift_rotate,shift")])
3891
3892 (define_insn ""
3893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3894 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3895 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3896 (const_int 0)))
3897 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3898 "TARGET_32BIT"
3899 "@
3900 slw. %3,%1,%2
3901 slwi. %3,%1,%h2
3902 #
3903 #"
3904 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3905 (set_attr "length" "4,4,8,8")])
3906
3907 (define_split
3908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3909 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3910 (match_operand:SI 2 "reg_or_cint_operand" ""))
3911 (const_int 0)))
3912 (clobber (match_scratch:SI 3 ""))]
3913 "TARGET_32BIT && reload_completed"
3914 [(set (match_dup 3)
3915 (ashift:SI (match_dup 1) (match_dup 2)))
3916 (set (match_dup 0)
3917 (compare:CC (match_dup 3)
3918 (const_int 0)))]
3919 "")
3920
3921 (define_insn ""
3922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3923 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3924 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3925 (const_int 0)))
3926 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3927 (ashift:SI (match_dup 1) (match_dup 2)))]
3928 "TARGET_32BIT"
3929 "@
3930 slw. %0,%1,%2
3931 slwi. %0,%1,%h2
3932 #
3933 #"
3934 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3935 (set_attr "length" "4,4,8,8")])
3936
3937 (define_split
3938 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3939 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3940 (match_operand:SI 2 "reg_or_cint_operand" ""))
3941 (const_int 0)))
3942 (set (match_operand:SI 0 "gpc_reg_operand" "")
3943 (ashift:SI (match_dup 1) (match_dup 2)))]
3944 "TARGET_32BIT && reload_completed"
3945 [(set (match_dup 0)
3946 (ashift:SI (match_dup 1) (match_dup 2)))
3947 (set (match_dup 3)
3948 (compare:CC (match_dup 0)
3949 (const_int 0)))]
3950 "")
3951
3952 (define_insn "rlwinm"
3953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3954 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3955 (match_operand:SI 2 "const_int_operand" "i"))
3956 (match_operand:SI 3 "mask_operand" "n")))]
3957 "includes_lshift_p (operands[2], operands[3])"
3958 "rlwinm %0,%1,%h2,%m3,%M3")
3959
3960 (define_insn ""
3961 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3962 (compare:CC
3963 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3964 (match_operand:SI 2 "const_int_operand" "i,i"))
3965 (match_operand:SI 3 "mask_operand" "n,n"))
3966 (const_int 0)))
3967 (clobber (match_scratch:SI 4 "=r,r"))]
3968 "includes_lshift_p (operands[2], operands[3])"
3969 "@
3970 rlwinm. %4,%1,%h2,%m3,%M3
3971 #"
3972 [(set_attr "type" "delayed_compare")
3973 (set_attr "length" "4,8")])
3974
3975 (define_split
3976 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3977 (compare:CC
3978 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3979 (match_operand:SI 2 "const_int_operand" ""))
3980 (match_operand:SI 3 "mask_operand" ""))
3981 (const_int 0)))
3982 (clobber (match_scratch:SI 4 ""))]
3983 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3984 [(set (match_dup 4)
3985 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3986 (match_dup 3)))
3987 (set (match_dup 0)
3988 (compare:CC (match_dup 4)
3989 (const_int 0)))]
3990 "")
3991
3992 (define_insn ""
3993 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3994 (compare:CC
3995 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3996 (match_operand:SI 2 "const_int_operand" "i,i"))
3997 (match_operand:SI 3 "mask_operand" "n,n"))
3998 (const_int 0)))
3999 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4000 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4001 "includes_lshift_p (operands[2], operands[3])"
4002 "@
4003 rlwinm. %0,%1,%h2,%m3,%M3
4004 #"
4005 [(set_attr "type" "delayed_compare")
4006 (set_attr "length" "4,8")])
4007
4008 (define_split
4009 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4010 (compare:CC
4011 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "const_int_operand" ""))
4013 (match_operand:SI 3 "mask_operand" ""))
4014 (const_int 0)))
4015 (set (match_operand:SI 0 "gpc_reg_operand" "")
4016 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4017 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4018 [(set (match_dup 0)
4019 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4020 (set (match_dup 4)
4021 (compare:CC (match_dup 0)
4022 (const_int 0)))]
4023 "")
4024
4025 (define_insn "lshrsi3"
4026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4027 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4028 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4029 ""
4030 "@
4031 mr %0,%1
4032 srw %0,%1,%2
4033 srwi %0,%1,%h2"
4034 [(set_attr "type" "integer,var_shift_rotate,shift")])
4035
4036 (define_insn "*lshrsi3_64"
4037 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4038 (zero_extend:DI
4039 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4040 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4041 "TARGET_POWERPC64"
4042 "@
4043 srw %0,%1,%2
4044 srwi %0,%1,%h2"
4045 [(set_attr "type" "var_shift_rotate,shift")])
4046
4047 (define_insn ""
4048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4049 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4050 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4053 "TARGET_32BIT"
4054 "@
4055 mr. %1,%1
4056 srw. %3,%1,%2
4057 srwi. %3,%1,%h2
4058 #
4059 #
4060 #"
4061 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4062 (set_attr "length" "4,4,4,8,8,8")])
4063
4064 (define_split
4065 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4066 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4067 (match_operand:SI 2 "reg_or_cint_operand" ""))
4068 (const_int 0)))
4069 (clobber (match_scratch:SI 3 ""))]
4070 "TARGET_32BIT && reload_completed"
4071 [(set (match_dup 3)
4072 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4073 (set (match_dup 0)
4074 (compare:CC (match_dup 3)
4075 (const_int 0)))]
4076 "")
4077
4078 (define_insn ""
4079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4080 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4081 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4082 (const_int 0)))
4083 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4084 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4085 "TARGET_32BIT"
4086 "@
4087 mr. %0,%1
4088 srw. %0,%1,%2
4089 srwi. %0,%1,%h2
4090 #
4091 #
4092 #"
4093 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4094 (set_attr "length" "4,4,4,8,8,8")])
4095
4096 (define_split
4097 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4098 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4099 (match_operand:SI 2 "reg_or_cint_operand" ""))
4100 (const_int 0)))
4101 (set (match_operand:SI 0 "gpc_reg_operand" "")
4102 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4103 "TARGET_32BIT && reload_completed"
4104 [(set (match_dup 0)
4105 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4106 (set (match_dup 3)
4107 (compare:CC (match_dup 0)
4108 (const_int 0)))]
4109 "")
4110
4111 (define_insn ""
4112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4113 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4114 (match_operand:SI 2 "const_int_operand" "i"))
4115 (match_operand:SI 3 "mask_operand" "n")))]
4116 "includes_rshift_p (operands[2], operands[3])"
4117 "rlwinm %0,%1,%s2,%m3,%M3")
4118
4119 (define_insn ""
4120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4121 (compare:CC
4122 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4123 (match_operand:SI 2 "const_int_operand" "i,i"))
4124 (match_operand:SI 3 "mask_operand" "n,n"))
4125 (const_int 0)))
4126 (clobber (match_scratch:SI 4 "=r,r"))]
4127 "includes_rshift_p (operands[2], operands[3])"
4128 "@
4129 rlwinm. %4,%1,%s2,%m3,%M3
4130 #"
4131 [(set_attr "type" "delayed_compare")
4132 (set_attr "length" "4,8")])
4133
4134 (define_split
4135 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4136 (compare:CC
4137 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4138 (match_operand:SI 2 "const_int_operand" ""))
4139 (match_operand:SI 3 "mask_operand" ""))
4140 (const_int 0)))
4141 (clobber (match_scratch:SI 4 ""))]
4142 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4143 [(set (match_dup 4)
4144 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4145 (match_dup 3)))
4146 (set (match_dup 0)
4147 (compare:CC (match_dup 4)
4148 (const_int 0)))]
4149 "")
4150
4151 (define_insn ""
4152 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4153 (compare:CC
4154 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4155 (match_operand:SI 2 "const_int_operand" "i,i"))
4156 (match_operand:SI 3 "mask_operand" "n,n"))
4157 (const_int 0)))
4158 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4159 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4160 "includes_rshift_p (operands[2], operands[3])"
4161 "@
4162 rlwinm. %0,%1,%s2,%m3,%M3
4163 #"
4164 [(set_attr "type" "delayed_compare")
4165 (set_attr "length" "4,8")])
4166
4167 (define_split
4168 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4169 (compare:CC
4170 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4171 (match_operand:SI 2 "const_int_operand" ""))
4172 (match_operand:SI 3 "mask_operand" ""))
4173 (const_int 0)))
4174 (set (match_operand:SI 0 "gpc_reg_operand" "")
4175 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4176 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4177 [(set (match_dup 0)
4178 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4179 (set (match_dup 4)
4180 (compare:CC (match_dup 0)
4181 (const_int 0)))]
4182 "")
4183
4184 (define_insn ""
4185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4186 (zero_extend:SI
4187 (subreg:QI
4188 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4189 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4190 "includes_rshift_p (operands[2], GEN_INT (255))"
4191 "rlwinm %0,%1,%s2,0xff")
4192
4193 (define_insn ""
4194 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4195 (compare:CC
4196 (zero_extend:SI
4197 (subreg:QI
4198 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4199 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4200 (const_int 0)))
4201 (clobber (match_scratch:SI 3 "=r,r"))]
4202 "includes_rshift_p (operands[2], GEN_INT (255))"
4203 "@
4204 rlwinm. %3,%1,%s2,0xff
4205 #"
4206 [(set_attr "type" "delayed_compare")
4207 (set_attr "length" "4,8")])
4208
4209 (define_split
4210 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4211 (compare:CC
4212 (zero_extend:SI
4213 (subreg:QI
4214 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4215 (match_operand:SI 2 "const_int_operand" "")) 0))
4216 (const_int 0)))
4217 (clobber (match_scratch:SI 3 ""))]
4218 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4219 [(set (match_dup 3)
4220 (zero_extend:SI (subreg:QI
4221 (lshiftrt:SI (match_dup 1)
4222 (match_dup 2)) 0)))
4223 (set (match_dup 0)
4224 (compare:CC (match_dup 3)
4225 (const_int 0)))]
4226 "")
4227
4228 (define_insn ""
4229 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4230 (compare:CC
4231 (zero_extend:SI
4232 (subreg:QI
4233 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4234 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4235 (const_int 0)))
4236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4237 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4238 "includes_rshift_p (operands[2], GEN_INT (255))"
4239 "@
4240 rlwinm. %0,%1,%s2,0xff
4241 #"
4242 [(set_attr "type" "delayed_compare")
4243 (set_attr "length" "4,8")])
4244
4245 (define_split
4246 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4247 (compare:CC
4248 (zero_extend:SI
4249 (subreg:QI
4250 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4251 (match_operand:SI 2 "const_int_operand" "")) 0))
4252 (const_int 0)))
4253 (set (match_operand:SI 0 "gpc_reg_operand" "")
4254 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4255 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4256 [(set (match_dup 0)
4257 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4258 (set (match_dup 3)
4259 (compare:CC (match_dup 0)
4260 (const_int 0)))]
4261 "")
4262
4263 (define_insn ""
4264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4265 (zero_extend:SI
4266 (subreg:HI
4267 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4268 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4269 "includes_rshift_p (operands[2], GEN_INT (65535))"
4270 "rlwinm %0,%1,%s2,0xffff")
4271
4272 (define_insn ""
4273 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4274 (compare:CC
4275 (zero_extend:SI
4276 (subreg:HI
4277 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4278 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4279 (const_int 0)))
4280 (clobber (match_scratch:SI 3 "=r,r"))]
4281 "includes_rshift_p (operands[2], GEN_INT (65535))"
4282 "@
4283 rlwinm. %3,%1,%s2,0xffff
4284 #"
4285 [(set_attr "type" "delayed_compare")
4286 (set_attr "length" "4,8")])
4287
4288 (define_split
4289 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4290 (compare:CC
4291 (zero_extend:SI
4292 (subreg:HI
4293 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4294 (match_operand:SI 2 "const_int_operand" "")) 0))
4295 (const_int 0)))
4296 (clobber (match_scratch:SI 3 ""))]
4297 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4298 [(set (match_dup 3)
4299 (zero_extend:SI (subreg:HI
4300 (lshiftrt:SI (match_dup 1)
4301 (match_dup 2)) 0)))
4302 (set (match_dup 0)
4303 (compare:CC (match_dup 3)
4304 (const_int 0)))]
4305 "")
4306
4307 (define_insn ""
4308 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4309 (compare:CC
4310 (zero_extend:SI
4311 (subreg:HI
4312 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4313 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4314 (const_int 0)))
4315 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4316 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4317 "includes_rshift_p (operands[2], GEN_INT (65535))"
4318 "@
4319 rlwinm. %0,%1,%s2,0xffff
4320 #"
4321 [(set_attr "type" "delayed_compare")
4322 (set_attr "length" "4,8")])
4323
4324 (define_split
4325 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4326 (compare:CC
4327 (zero_extend:SI
4328 (subreg:HI
4329 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4330 (match_operand:SI 2 "const_int_operand" "")) 0))
4331 (const_int 0)))
4332 (set (match_operand:SI 0 "gpc_reg_operand" "")
4333 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4334 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4335 [(set (match_dup 0)
4336 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4337 (set (match_dup 3)
4338 (compare:CC (match_dup 0)
4339 (const_int 0)))]
4340 "")
4341
4342 (define_insn "ashrsi3"
4343 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4344 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4345 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4346 ""
4347 "@
4348 sraw %0,%1,%2
4349 srawi %0,%1,%h2"
4350 [(set_attr "type" "var_shift_rotate,shift")])
4351
4352 (define_insn "*ashrsi3_64"
4353 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4354 (sign_extend:DI
4355 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4357 "TARGET_POWERPC64"
4358 "@
4359 sraw %0,%1,%2
4360 srawi %0,%1,%h2"
4361 [(set_attr "type" "var_shift_rotate,shift")])
4362
4363 (define_insn ""
4364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4365 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4366 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4367 (const_int 0)))
4368 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4369 ""
4370 "@
4371 sraw. %3,%1,%2
4372 srawi. %3,%1,%h2
4373 #
4374 #"
4375 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4376 (set_attr "length" "4,4,8,8")])
4377
4378 (define_split
4379 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4380 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4381 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (const_int 0)))
4383 (clobber (match_scratch:SI 3 ""))]
4384 "reload_completed"
4385 [(set (match_dup 3)
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4387 (set (match_dup 0)
4388 (compare:CC (match_dup 3)
4389 (const_int 0)))]
4390 "")
4391
4392 (define_insn ""
4393 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4394 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4395 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4396 (const_int 0)))
4397 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4398 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4399 ""
4400 "@
4401 sraw. %0,%1,%2
4402 srawi. %0,%1,%h2
4403 #
4404 #"
4405 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4406 (set_attr "length" "4,4,8,8")])
4407 \f
4408 ;; Builtins to replace a division to generate FRE reciprocal estimate
4409 ;; instructions and the necessary fixup instructions
4410 (define_expand "recip<mode>3"
4411 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4412 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4413 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4414 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4415 {
4416 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4417 DONE;
4418 })
4419
4420 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4421 ;; hardware division. This is only done before register allocation and with
4422 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4423 (define_split
4424 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4425 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4426 (match_operand 2 "gpc_reg_operand" "")))]
4427 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4428 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4429 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4430 [(const_int 0)]
4431 {
4432 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4433 DONE;
4434 })
4435
4436 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4437 ;; appropriate fixup.
4438 (define_expand "rsqrt<mode>2"
4439 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4440 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4441 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4442 {
4443 rs6000_emit_swrsqrt (operands[0], operands[1]);
4444 DONE;
4445 })
4446 \f
4447 (define_split
4448 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4449 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4450 (match_operand:SI 2 "reg_or_cint_operand" ""))
4451 (const_int 0)))
4452 (set (match_operand:SI 0 "gpc_reg_operand" "")
4453 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4454 "reload_completed"
4455 [(set (match_dup 0)
4456 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4457 (set (match_dup 3)
4458 (compare:CC (match_dup 0)
4459 (const_int 0)))]
4460 "")
4461
4462 ;; Floating-point insns, excluding normal data motion.
4463 ;;
4464 ;; PowerPC has a full set of single-precision floating point instructions.
4465 ;;
4466 ;; For the POWER architecture, we pretend that we have both SFmode and
4467 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4468 ;; The only conversions we will do will be when storing to memory. In that
4469 ;; case, we will use the "frsp" instruction before storing.
4470 ;;
4471 ;; Note that when we store into a single-precision memory location, we need to
4472 ;; use the frsp insn first. If the register being stored isn't dead, we
4473 ;; need a scratch register for the frsp. But this is difficult when the store
4474 ;; is done by reload. It is not incorrect to do the frsp on the register in
4475 ;; this case, we just lose precision that we would have otherwise gotten but
4476 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4477
4478 (define_expand "extendsfdf2"
4479 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4480 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4481 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4482 "")
4483
4484 (define_insn_and_split "*extendsfdf2_fpr"
4485 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4486 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4487 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4488 "@
4489 #
4490 fmr %0,%1
4491 lfs%U1%X1 %0,%1"
4492 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4493 [(const_int 0)]
4494 {
4495 emit_note (NOTE_INSN_DELETED);
4496 DONE;
4497 }
4498 [(set_attr "type" "fp,fp,fpload")])
4499
4500 (define_expand "truncdfsf2"
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4502 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4503 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4504 "")
4505
4506 (define_insn "*truncdfsf2_fpr"
4507 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4508 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4509 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4510 "frsp %0,%1"
4511 [(set_attr "type" "fp")])
4512
4513 (define_expand "negsf2"
4514 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4515 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4516 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4517 "")
4518
4519 (define_insn "*negsf2"
4520 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4521 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4522 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4523 "fneg %0,%1"
4524 [(set_attr "type" "fp")])
4525
4526 (define_expand "abssf2"
4527 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4528 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4529 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4530 "")
4531
4532 (define_insn "*abssf2"
4533 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4534 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4535 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4536 "fabs %0,%1"
4537 [(set_attr "type" "fp")])
4538
4539 (define_insn ""
4540 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4541 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4543 "fnabs %0,%1"
4544 [(set_attr "type" "fp")])
4545
4546 (define_expand "addsf3"
4547 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4548 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4549 (match_operand:SF 2 "gpc_reg_operand" "")))]
4550 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4551 "")
4552
4553 (define_insn ""
4554 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4555 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4556 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4557 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4558 "fadds %0,%1,%2"
4559 [(set_attr "type" "fp")
4560 (set_attr "fp_type" "fp_addsub_s")])
4561
4562 (define_expand "subsf3"
4563 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4564 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4565 (match_operand:SF 2 "gpc_reg_operand" "")))]
4566 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4567 "")
4568
4569 (define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4573 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4574 "fsubs %0,%1,%2"
4575 [(set_attr "type" "fp")
4576 (set_attr "fp_type" "fp_addsub_s")])
4577
4578 (define_expand "mulsf3"
4579 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4580 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4581 (match_operand:SF 2 "gpc_reg_operand" "")))]
4582 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4583 "")
4584
4585 (define_insn ""
4586 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4587 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4588 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4589 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4590 "fmuls %0,%1,%2"
4591 [(set_attr "type" "fp")
4592 (set_attr "fp_type" "fp_mul_s")])
4593
4594 (define_expand "divsf3"
4595 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4596 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4597 (match_operand:SF 2 "gpc_reg_operand" "")))]
4598 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4599 "")
4600
4601 (define_insn ""
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4604 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4605 "TARGET_HARD_FLOAT && TARGET_FPRS
4606 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4607 "fdivs %0,%1,%2"
4608 [(set_attr "type" "sdiv")])
4609
4610 (define_insn "fres"
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4613 "TARGET_FRES"
4614 "fres %0,%1"
4615 [(set_attr "type" "fp")])
4616
4617 ; builtin fmaf support
4618 (define_insn "*fmasf4_fpr"
4619 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4620 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4621 (match_operand:SF 2 "gpc_reg_operand" "f")
4622 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4623 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4624 "fmadds %0,%1,%2,%3"
4625 [(set_attr "type" "fp")
4626 (set_attr "fp_type" "fp_maddsub_s")])
4627
4628 (define_insn "*fmssf4_fpr"
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4630 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4631 (match_operand:SF 2 "gpc_reg_operand" "f")
4632 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4633 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4634 "fmsubs %0,%1,%2,%3"
4635 [(set_attr "type" "fp")
4636 (set_attr "fp_type" "fp_maddsub_s")])
4637
4638 (define_insn "*nfmasf4_fpr"
4639 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4640 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4641 (match_operand:SF 2 "gpc_reg_operand" "f")
4642 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4644 "fnmadds %0,%1,%2,%3"
4645 [(set_attr "type" "fp")
4646 (set_attr "fp_type" "fp_maddsub_s")])
4647
4648 (define_insn "*nfmssf4_fpr"
4649 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4650 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4651 (match_operand:SF 2 "gpc_reg_operand" "f")
4652 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
4653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4654 "fnmsubs %0,%1,%2,%3"
4655 [(set_attr "type" "fp")
4656 (set_attr "fp_type" "fp_maddsub_s")])
4657
4658 (define_expand "sqrtsf2"
4659 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4660 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4661 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
4662 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
4663 && !TARGET_SIMPLE_FPU"
4664 "")
4665
4666 (define_insn ""
4667 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4668 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4669 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
4670 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4671 "fsqrts %0,%1"
4672 [(set_attr "type" "ssqrt")])
4673
4674 (define_insn "*rsqrtsf_internal1"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4676 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
4677 UNSPEC_RSQRT))]
4678 "TARGET_FRSQRTES"
4679 "frsqrtes %0,%1"
4680 [(set_attr "type" "fp")])
4681
4682 (define_expand "copysign<mode>3"
4683 [(set (match_dup 3)
4684 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
4685 (set (match_dup 4)
4686 (neg:SFDF (abs:SFDF (match_dup 1))))
4687 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
4688 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
4689 (match_dup 5))
4690 (match_dup 3)
4691 (match_dup 4)))]
4692 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
4693 && ((TARGET_PPC_GFXOPT
4694 && !HONOR_NANS (<MODE>mode)
4695 && !HONOR_SIGNED_ZEROS (<MODE>mode))
4696 || TARGET_CMPB
4697 || VECTOR_UNIT_VSX_P (<MODE>mode))"
4698 {
4699 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
4700 {
4701 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
4702 operands[2]));
4703 DONE;
4704 }
4705
4706 operands[3] = gen_reg_rtx (<MODE>mode);
4707 operands[4] = gen_reg_rtx (<MODE>mode);
4708 operands[5] = CONST0_RTX (<MODE>mode);
4709 })
4710
4711 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
4712 ;; compiler from optimizing -0.0
4713 (define_insn "copysign<mode>3_fcpsgn"
4714 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
4715 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
4716 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
4717 UNSPEC_COPYSIGN))]
4718 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
4719 "fcpsgn %0,%2,%1"
4720 [(set_attr "type" "fp")])
4721
4722 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4723 ;; fsel instruction and some auxiliary computations. Then we just have a
4724 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4725 ;; combine.
4726 (define_expand "smaxsf3"
4727 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4728 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4729 (match_operand:SF 2 "gpc_reg_operand" ""))
4730 (match_dup 1)
4731 (match_dup 2)))]
4732 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4733 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4734 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4735
4736 (define_expand "sminsf3"
4737 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4738 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4739 (match_operand:SF 2 "gpc_reg_operand" ""))
4740 (match_dup 2)
4741 (match_dup 1)))]
4742 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4743 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4744 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4745
4746 (define_split
4747 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4748 (match_operator:SF 3 "min_max_operator"
4749 [(match_operand:SF 1 "gpc_reg_operand" "")
4750 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4751 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4752 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4753 [(const_int 0)]
4754 "
4755 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4756 operands[1], operands[2]);
4757 DONE;
4758 }")
4759
4760 (define_expand "mov<mode>cc"
4761 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4762 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
4763 (match_operand:GPR 2 "gpc_reg_operand" "")
4764 (match_operand:GPR 3 "gpc_reg_operand" "")))]
4765 "TARGET_ISEL<sel>"
4766 "
4767 {
4768 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4769 DONE;
4770 else
4771 FAIL;
4772 }")
4773
4774 ;; We use the BASE_REGS for the isel input operands because, if rA is
4775 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4776 ;; because we may switch the operands and rB may end up being rA.
4777 ;;
4778 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4779 ;; leave out the mode in operand 4 and use one pattern, but reload can
4780 ;; change the mode underneath our feet and then gets confused trying
4781 ;; to reload the value.
4782 (define_insn "isel_signed_<mode>"
4783 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4784 (if_then_else:GPR
4785 (match_operator 1 "scc_comparison_operator"
4786 [(match_operand:CC 4 "cc_reg_operand" "y,y")
4787 (const_int 0)])
4788 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4789 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4790 "TARGET_ISEL<sel>"
4791 "*
4792 { return output_isel (operands); }"
4793 [(set_attr "type" "isel")
4794 (set_attr "length" "4")])
4795
4796 (define_insn "isel_unsigned_<mode>"
4797 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4798 (if_then_else:GPR
4799 (match_operator 1 "scc_comparison_operator"
4800 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
4801 (const_int 0)])
4802 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4803 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4804 "TARGET_ISEL<sel>"
4805 "*
4806 { return output_isel (operands); }"
4807 [(set_attr "type" "isel")
4808 (set_attr "length" "4")])
4809
4810 ;; These patterns can be useful for combine; they let combine know that
4811 ;; isel can handle reversed comparisons so long as the operands are
4812 ;; registers.
4813
4814 (define_insn "*isel_reversed_signed_<mode>"
4815 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4816 (if_then_else:GPR
4817 (match_operator 1 "scc_rev_comparison_operator"
4818 [(match_operand:CC 4 "cc_reg_operand" "y")
4819 (const_int 0)])
4820 (match_operand:GPR 2 "gpc_reg_operand" "b")
4821 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4822 "TARGET_ISEL<sel>"
4823 "*
4824 { return output_isel (operands); }"
4825 [(set_attr "type" "isel")
4826 (set_attr "length" "4")])
4827
4828 (define_insn "*isel_reversed_unsigned_<mode>"
4829 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4830 (if_then_else:GPR
4831 (match_operator 1 "scc_rev_comparison_operator"
4832 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4833 (const_int 0)])
4834 (match_operand:GPR 2 "gpc_reg_operand" "b")
4835 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4836 "TARGET_ISEL<sel>"
4837 "*
4838 { return output_isel (operands); }"
4839 [(set_attr "type" "isel")
4840 (set_attr "length" "4")])
4841
4842 (define_expand "movsfcc"
4843 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4844 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4845 (match_operand:SF 2 "gpc_reg_operand" "")
4846 (match_operand:SF 3 "gpc_reg_operand" "")))]
4847 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4848 "
4849 {
4850 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4851 DONE;
4852 else
4853 FAIL;
4854 }")
4855
4856 (define_insn "*fselsfsf4"
4857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4858 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4859 (match_operand:SF 4 "zero_fp_constant" "F"))
4860 (match_operand:SF 2 "gpc_reg_operand" "f")
4861 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4862 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4863 "fsel %0,%1,%2,%3"
4864 [(set_attr "type" "fp")])
4865
4866 (define_insn "*fseldfsf4"
4867 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4868 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
4869 (match_operand:DF 4 "zero_fp_constant" "F"))
4870 (match_operand:SF 2 "gpc_reg_operand" "f")
4871 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4872 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
4873 "fsel %0,%1,%2,%3"
4874 [(set_attr "type" "fp")])
4875
4876 (define_expand "negdf2"
4877 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4878 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4879 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4880 "")
4881
4882 (define_insn "*negdf2_fpr"
4883 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4884 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4885 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4886 && !VECTOR_UNIT_VSX_P (DFmode)"
4887 "fneg %0,%1"
4888 [(set_attr "type" "fp")])
4889
4890 (define_expand "absdf2"
4891 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4892 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4893 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4894 "")
4895
4896 (define_insn "*absdf2_fpr"
4897 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4898 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4899 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4900 && !VECTOR_UNIT_VSX_P (DFmode)"
4901 "fabs %0,%1"
4902 [(set_attr "type" "fp")])
4903
4904 (define_insn "*nabsdf2_fpr"
4905 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4906 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
4907 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4908 && !VECTOR_UNIT_VSX_P (DFmode)"
4909 "fnabs %0,%1"
4910 [(set_attr "type" "fp")])
4911
4912 (define_expand "adddf3"
4913 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4914 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4915 (match_operand:DF 2 "gpc_reg_operand" "")))]
4916 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4917 "")
4918
4919 (define_insn "*adddf3_fpr"
4920 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4921 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4922 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4923 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4924 && !VECTOR_UNIT_VSX_P (DFmode)"
4925 "fadd %0,%1,%2"
4926 [(set_attr "type" "fp")
4927 (set_attr "fp_type" "fp_addsub_d")])
4928
4929 (define_expand "subdf3"
4930 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4931 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4932 (match_operand:DF 2 "gpc_reg_operand" "")))]
4933 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4934 "")
4935
4936 (define_insn "*subdf3_fpr"
4937 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4938 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4939 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4940 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4941 && !VECTOR_UNIT_VSX_P (DFmode)"
4942 "fsub %0,%1,%2"
4943 [(set_attr "type" "fp")
4944 (set_attr "fp_type" "fp_addsub_d")])
4945
4946 (define_expand "muldf3"
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4948 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4949 (match_operand:DF 2 "gpc_reg_operand" "")))]
4950 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4951 "")
4952
4953 (define_insn "*muldf3_fpr"
4954 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4955 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4956 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4957 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4958 && !VECTOR_UNIT_VSX_P (DFmode)"
4959 "fmul %0,%1,%2"
4960 [(set_attr "type" "dmul")
4961 (set_attr "fp_type" "fp_mul_d")])
4962
4963 (define_expand "divdf3"
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4965 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4966 (match_operand:DF 2 "gpc_reg_operand" "")))]
4967 "TARGET_HARD_FLOAT
4968 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
4969 && !TARGET_SIMPLE_FPU"
4970 "")
4971
4972 (define_insn "*divdf3_fpr"
4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4974 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4975 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4976 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
4977 && !VECTOR_UNIT_VSX_P (DFmode)"
4978 "fdiv %0,%1,%2"
4979 [(set_attr "type" "ddiv")])
4980
4981 (define_insn "*fred_fpr"
4982 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4983 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4984 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
4985 "fre %0,%1"
4986 [(set_attr "type" "fp")])
4987
4988 (define_insn "*rsqrtdf_internal1"
4989 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4990 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
4991 UNSPEC_RSQRT))]
4992 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
4993 "frsqrte %0,%1"
4994 [(set_attr "type" "fp")])
4995
4996 ; builtin fma support
4997 (define_insn "*fmadf4_fpr"
4998 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4999 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5000 (match_operand:DF 2 "gpc_reg_operand" "f")
5001 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5002 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5003 && VECTOR_UNIT_NONE_P (DFmode)"
5004 "fmadd %0,%1,%2,%3"
5005 [(set_attr "type" "fp")
5006 (set_attr "fp_type" "fp_maddsub_d")])
5007
5008 (define_insn "*fmsdf4_fpr"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5010 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5011 (match_operand:DF 2 "gpc_reg_operand" "f")
5012 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5013 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5014 && VECTOR_UNIT_NONE_P (DFmode)"
5015 "fmsub %0,%1,%2,%3"
5016 [(set_attr "type" "fp")
5017 (set_attr "fp_type" "fp_maddsub_d")])
5018
5019 (define_insn "*nfmadf4_fpr"
5020 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5021 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5022 (match_operand:DF 2 "gpc_reg_operand" "f")
5023 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5024 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5025 && VECTOR_UNIT_NONE_P (DFmode)"
5026 "fnmadd %0,%1,%2,%3"
5027 [(set_attr "type" "fp")
5028 (set_attr "fp_type" "fp_maddsub_d")])
5029
5030 (define_insn "*nfmsdf4_fpr"
5031 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5032 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5033 (match_operand:DF 2 "gpc_reg_operand" "f")
5034 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5035 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5036 && VECTOR_UNIT_NONE_P (DFmode)"
5037 "fnmsub %0,%1,%2,%3"
5038 [(set_attr "type" "fp")
5039 (set_attr "fp_type" "fp_maddsub_d")])
5040
5041 (define_expand "sqrtdf2"
5042 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5043 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5044 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5045 "")
5046
5047 (define_insn "*sqrtdf2_fpr"
5048 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5049 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5050 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5051 && !VECTOR_UNIT_VSX_P (DFmode)"
5052 "fsqrt %0,%1"
5053 [(set_attr "type" "dsqrt")])
5054
5055 ;; The conditional move instructions allow us to perform max and min
5056 ;; operations even when
5057
5058 (define_expand "smaxdf3"
5059 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5060 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5061 (match_operand:DF 2 "gpc_reg_operand" ""))
5062 (match_dup 1)
5063 (match_dup 2)))]
5064 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5065 && !flag_trapping_math"
5066 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5067
5068 (define_expand "smindf3"
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5070 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5071 (match_operand:DF 2 "gpc_reg_operand" ""))
5072 (match_dup 2)
5073 (match_dup 1)))]
5074 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5075 && !flag_trapping_math"
5076 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5077
5078 (define_split
5079 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5080 (match_operator:DF 3 "min_max_operator"
5081 [(match_operand:DF 1 "gpc_reg_operand" "")
5082 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5083 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5084 && !flag_trapping_math"
5085 [(const_int 0)]
5086 "
5087 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5088 operands[1], operands[2]);
5089 DONE;
5090 }")
5091
5092 (define_expand "movdfcc"
5093 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5094 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5095 (match_operand:DF 2 "gpc_reg_operand" "")
5096 (match_operand:DF 3 "gpc_reg_operand" "")))]
5097 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5098 "
5099 {
5100 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5101 DONE;
5102 else
5103 FAIL;
5104 }")
5105
5106 (define_insn "*fseldfdf4"
5107 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5108 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5109 (match_operand:DF 4 "zero_fp_constant" "F"))
5110 (match_operand:DF 2 "gpc_reg_operand" "d")
5111 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5112 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5113 "fsel %0,%1,%2,%3"
5114 [(set_attr "type" "fp")])
5115
5116 (define_insn "*fselsfdf4"
5117 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5118 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5119 (match_operand:SF 4 "zero_fp_constant" "F"))
5120 (match_operand:DF 2 "gpc_reg_operand" "d")
5121 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5122 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5123 "fsel %0,%1,%2,%3"
5124 [(set_attr "type" "fp")])
5125 \f
5126 ;; Conversions to and from floating-point.
5127
5128 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5129 ; don't want to support putting SImode in FPR registers.
5130 (define_insn "lfiwax"
5131 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5132 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5133 UNSPEC_LFIWAX))]
5134 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5135 "lfiwax %0,%y1"
5136 [(set_attr "type" "fpload")])
5137
5138 ; This split must be run before register allocation because it allocates the
5139 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5140 ; it earlier to allow for the combiner to merge insns together where it might
5141 ; not be needed and also in case the insns are deleted as dead code.
5142
5143 (define_insn_and_split "floatsi<mode>2_lfiwax"
5144 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5145 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5146 (clobber (match_scratch:DI 2 "=d"))]
5147 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5148 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5149 "#"
5150 ""
5151 [(pc)]
5152 "
5153 {
5154 rtx dest = operands[0];
5155 rtx src = operands[1];
5156 rtx tmp;
5157
5158 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5159 tmp = convert_to_mode (DImode, src, false);
5160 else
5161 {
5162 tmp = operands[2];
5163 if (GET_CODE (tmp) == SCRATCH)
5164 tmp = gen_reg_rtx (DImode);
5165 if (MEM_P (src))
5166 {
5167 src = rs6000_address_for_fpconvert (src);
5168 emit_insn (gen_lfiwax (tmp, src));
5169 }
5170 else
5171 {
5172 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5173 emit_move_insn (stack, src);
5174 emit_insn (gen_lfiwax (tmp, stack));
5175 }
5176 }
5177 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5178 DONE;
5179 }"
5180 [(set_attr "length" "12")
5181 (set_attr "type" "fpload")])
5182
5183 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5184 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5185 (float:SFDF
5186 (sign_extend:DI
5187 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5188 (clobber (match_scratch:DI 2 "=0,d"))]
5189 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5190 && <SI_CONVERT_FP>"
5191 "#"
5192 ""
5193 [(pc)]
5194 "
5195 {
5196 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5197 if (GET_CODE (operands[2]) == SCRATCH)
5198 operands[2] = gen_reg_rtx (DImode);
5199 emit_insn (gen_lfiwax (operands[2], operands[1]));
5200 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5201 DONE;
5202 }"
5203 [(set_attr "length" "8")
5204 (set_attr "type" "fpload")])
5205
5206 (define_insn "lfiwzx"
5207 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5208 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5209 UNSPEC_LFIWZX))]
5210 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5211 "lfiwzx %0,%y1"
5212 [(set_attr "type" "fpload")])
5213
5214 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5215 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5216 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5217 (clobber (match_scratch:DI 2 "=d"))]
5218 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5219 && <SI_CONVERT_FP>"
5220 "#"
5221 ""
5222 [(pc)]
5223 "
5224 {
5225 rtx dest = operands[0];
5226 rtx src = operands[1];
5227 rtx tmp;
5228
5229 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5230 tmp = convert_to_mode (DImode, src, true);
5231 else
5232 {
5233 tmp = operands[2];
5234 if (GET_CODE (tmp) == SCRATCH)
5235 tmp = gen_reg_rtx (DImode);
5236 if (MEM_P (src))
5237 {
5238 src = rs6000_address_for_fpconvert (src);
5239 emit_insn (gen_lfiwzx (tmp, src));
5240 }
5241 else
5242 {
5243 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5244 emit_move_insn (stack, src);
5245 emit_insn (gen_lfiwzx (tmp, stack));
5246 }
5247 }
5248 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5249 DONE;
5250 }"
5251 [(set_attr "length" "12")
5252 (set_attr "type" "fpload")])
5253
5254 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5255 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5256 (unsigned_float:SFDF
5257 (zero_extend:DI
5258 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5259 (clobber (match_scratch:DI 2 "=0,d"))]
5260 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5261 && <SI_CONVERT_FP>"
5262 "#"
5263 ""
5264 [(pc)]
5265 "
5266 {
5267 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5268 if (GET_CODE (operands[2]) == SCRATCH)
5269 operands[2] = gen_reg_rtx (DImode);
5270 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5271 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5272 DONE;
5273 }"
5274 [(set_attr "length" "8")
5275 (set_attr "type" "fpload")])
5276
5277 ; For each of these conversions, there is a define_expand, a define_insn
5278 ; with a '#' template, and a define_split (with C code). The idea is
5279 ; to allow constant folding with the template of the define_insn,
5280 ; then to have the insns split later (between sched1 and final).
5281
5282 (define_expand "floatsidf2"
5283 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5284 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5285 (use (match_dup 2))
5286 (use (match_dup 3))
5287 (clobber (match_dup 4))
5288 (clobber (match_dup 5))
5289 (clobber (match_dup 6))])]
5290 "TARGET_HARD_FLOAT
5291 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5292 "
5293 {
5294 if (TARGET_E500_DOUBLE)
5295 {
5296 if (!REG_P (operands[1]))
5297 operands[1] = force_reg (SImode, operands[1]);
5298 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5299 DONE;
5300 }
5301 else if (TARGET_LFIWAX && TARGET_FCFID)
5302 {
5303 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5304 DONE;
5305 }
5306 else if (TARGET_FCFID)
5307 {
5308 rtx dreg = operands[1];
5309 if (!REG_P (dreg))
5310 dreg = force_reg (SImode, dreg);
5311 dreg = convert_to_mode (DImode, dreg, false);
5312 emit_insn (gen_floatdidf2 (operands[0], dreg));
5313 DONE;
5314 }
5315
5316 if (!REG_P (operands[1]))
5317 operands[1] = force_reg (SImode, operands[1]);
5318 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5319 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5320 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5321 operands[5] = gen_reg_rtx (DFmode);
5322 operands[6] = gen_reg_rtx (SImode);
5323 }")
5324
5325 (define_insn_and_split "*floatsidf2_internal"
5326 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5327 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5328 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5329 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5330 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5331 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5332 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5333 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5334 "#"
5335 ""
5336 [(pc)]
5337 "
5338 {
5339 rtx lowword, highword;
5340 gcc_assert (MEM_P (operands[4]));
5341 highword = adjust_address (operands[4], SImode, 0);
5342 lowword = adjust_address (operands[4], SImode, 4);
5343 if (! WORDS_BIG_ENDIAN)
5344 {
5345 rtx tmp;
5346 tmp = highword; highword = lowword; lowword = tmp;
5347 }
5348
5349 emit_insn (gen_xorsi3 (operands[6], operands[1],
5350 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5351 emit_move_insn (lowword, operands[6]);
5352 emit_move_insn (highword, operands[2]);
5353 emit_move_insn (operands[5], operands[4]);
5354 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5355 DONE;
5356 }"
5357 [(set_attr "length" "24")
5358 (set_attr "type" "fp")])
5359
5360 ;; If we don't have a direct conversion to single precision, don't enable this
5361 ;; conversion for 32-bit without fast math, because we don't have the insn to
5362 ;; generate the fixup swizzle to avoid double rounding problems.
5363 (define_expand "floatunssisf2"
5364 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5365 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5366 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5367 && (!TARGET_FPRS
5368 || (TARGET_FPRS
5369 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5370 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5371 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5372 "
5373 {
5374 if (!TARGET_FPRS)
5375 {
5376 if (!REG_P (operands[1]))
5377 operands[1] = force_reg (SImode, operands[1]);
5378 }
5379 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5380 {
5381 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5382 DONE;
5383 }
5384 else
5385 {
5386 rtx dreg = operands[1];
5387 if (!REG_P (dreg))
5388 dreg = force_reg (SImode, dreg);
5389 dreg = convert_to_mode (DImode, dreg, true);
5390 emit_insn (gen_floatdisf2 (operands[0], dreg));
5391 DONE;
5392 }
5393 }")
5394
5395 (define_expand "floatunssidf2"
5396 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5397 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5398 (use (match_dup 2))
5399 (use (match_dup 3))
5400 (clobber (match_dup 4))
5401 (clobber (match_dup 5))])]
5402 "TARGET_HARD_FLOAT
5403 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5404 "
5405 {
5406 if (TARGET_E500_DOUBLE)
5407 {
5408 if (!REG_P (operands[1]))
5409 operands[1] = force_reg (SImode, operands[1]);
5410 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5411 DONE;
5412 }
5413 else if (TARGET_LFIWZX && TARGET_FCFID)
5414 {
5415 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5416 DONE;
5417 }
5418 else if (TARGET_FCFID)
5419 {
5420 rtx dreg = operands[1];
5421 if (!REG_P (dreg))
5422 dreg = force_reg (SImode, dreg);
5423 dreg = convert_to_mode (DImode, dreg, true);
5424 emit_insn (gen_floatdidf2 (operands[0], dreg));
5425 DONE;
5426 }
5427
5428 if (!REG_P (operands[1]))
5429 operands[1] = force_reg (SImode, operands[1]);
5430 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5431 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5432 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5433 operands[5] = gen_reg_rtx (DFmode);
5434 }")
5435
5436 (define_insn_and_split "*floatunssidf2_internal"
5437 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5438 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5439 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5440 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5441 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5442 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5443 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5444 && !(TARGET_FCFID && TARGET_POWERPC64)"
5445 "#"
5446 ""
5447 [(pc)]
5448 "
5449 {
5450 rtx lowword, highword;
5451 gcc_assert (MEM_P (operands[4]));
5452 highword = adjust_address (operands[4], SImode, 0);
5453 lowword = adjust_address (operands[4], SImode, 4);
5454 if (! WORDS_BIG_ENDIAN)
5455 {
5456 rtx tmp;
5457 tmp = highword; highword = lowword; lowword = tmp;
5458 }
5459
5460 emit_move_insn (lowword, operands[1]);
5461 emit_move_insn (highword, operands[2]);
5462 emit_move_insn (operands[5], operands[4]);
5463 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5464 DONE;
5465 }"
5466 [(set_attr "length" "20")
5467 (set_attr "type" "fp")])
5468
5469 (define_expand "fix_trunc<mode>si2"
5470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5471 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5472 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5473 "
5474 {
5475 if (!<E500_CONVERT>)
5476 {
5477 rtx tmp, stack;
5478
5479 if (TARGET_STFIWX)
5480 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5481 else
5482 {
5483 tmp = gen_reg_rtx (DImode);
5484 stack = rs6000_allocate_stack_temp (DImode, true, false);
5485 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5486 tmp, stack));
5487 }
5488 DONE;
5489 }
5490 }")
5491
5492 ; Like the convert to float patterns, this insn must be split before
5493 ; register allocation so that it can allocate the memory slot if it
5494 ; needed
5495 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5496 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5497 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5498 (clobber (match_scratch:DI 2 "=d"))]
5499 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5500 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5501 && TARGET_STFIWX && can_create_pseudo_p ()"
5502 "#"
5503 ""
5504 [(pc)]
5505 {
5506 rtx dest = operands[0];
5507 rtx src = operands[1];
5508 rtx tmp = operands[2];
5509
5510 if (GET_CODE (tmp) == SCRATCH)
5511 tmp = gen_reg_rtx (DImode);
5512
5513 emit_insn (gen_fctiwz_<mode> (tmp, src));
5514 if (MEM_P (dest))
5515 {
5516 dest = rs6000_address_for_fpconvert (dest);
5517 emit_insn (gen_stfiwx (dest, tmp));
5518 DONE;
5519 }
5520 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5521 {
5522 dest = gen_lowpart (DImode, dest);
5523 emit_move_insn (dest, tmp);
5524 DONE;
5525 }
5526 else
5527 {
5528 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5529 emit_insn (gen_stfiwx (stack, tmp));
5530 emit_move_insn (dest, stack);
5531 DONE;
5532 }
5533 }
5534 [(set_attr "length" "12")
5535 (set_attr "type" "fp")])
5536
5537 (define_insn_and_split "fix_trunc<mode>si2_internal"
5538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5539 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5540 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5541 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5543 "#"
5544 ""
5545 [(pc)]
5546 "
5547 {
5548 rtx lowword;
5549 gcc_assert (MEM_P (operands[3]));
5550 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5551
5552 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5553 emit_move_insn (operands[3], operands[2]);
5554 emit_move_insn (operands[0], lowword);
5555 DONE;
5556 }"
5557 [(set_attr "length" "16")
5558 (set_attr "type" "fp")])
5559
5560 (define_expand "fix_trunc<mode>di2"
5561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5562 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5563 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5564 && TARGET_FCFID"
5565 "")
5566
5567 (define_insn "*fix_trunc<mode>di2_fctidz"
5568 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5569 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5570 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5571 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5572 "fctidz %0,%1"
5573 [(set_attr "type" "fp")])
5574
5575 (define_expand "fixuns_trunc<mode>si2"
5576 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5577 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5578 "TARGET_HARD_FLOAT
5579 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5580 || <E500_CONVERT>)"
5581 "
5582 {
5583 if (!<E500_CONVERT>)
5584 {
5585 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5586 DONE;
5587 }
5588 }")
5589
5590 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5591 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5592 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5593 (clobber (match_scratch:DI 2 "=d"))]
5594 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5595 && TARGET_STFIWX && can_create_pseudo_p ()"
5596 "#"
5597 ""
5598 [(pc)]
5599 {
5600 rtx dest = operands[0];
5601 rtx src = operands[1];
5602 rtx tmp = operands[2];
5603
5604 if (GET_CODE (tmp) == SCRATCH)
5605 tmp = gen_reg_rtx (DImode);
5606
5607 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5608 if (MEM_P (dest))
5609 {
5610 dest = rs6000_address_for_fpconvert (dest);
5611 emit_insn (gen_stfiwx (dest, tmp));
5612 DONE;
5613 }
5614 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5615 {
5616 dest = gen_lowpart (DImode, dest);
5617 emit_move_insn (dest, tmp);
5618 DONE;
5619 }
5620 else
5621 {
5622 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5623 emit_insn (gen_stfiwx (stack, tmp));
5624 emit_move_insn (dest, stack);
5625 DONE;
5626 }
5627 }
5628 [(set_attr "length" "12")
5629 (set_attr "type" "fp")])
5630
5631 (define_expand "fixuns_trunc<mode>di2"
5632 [(set (match_operand:DI 0 "register_operand" "")
5633 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5634 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5635 "")
5636
5637 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5638 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5639 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5640 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5641 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5642 "fctiduz %0,%1"
5643 [(set_attr "type" "fp")])
5644
5645 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5646 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5647 ; because the first makes it clear that operand 0 is not live
5648 ; before the instruction.
5649 (define_insn "fctiwz_<mode>"
5650 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5651 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5652 UNSPEC_FCTIWZ))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5654 "fctiwz %0,%1"
5655 [(set_attr "type" "fp")])
5656
5657 (define_insn "fctiwuz_<mode>"
5658 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5659 (unspec:DI [(unsigned_fix:SI
5660 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5661 UNSPEC_FCTIWUZ))]
5662 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5663 "fctiwuz %0,%1"
5664 [(set_attr "type" "fp")])
5665
5666 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5667 ;; since the friz instruction does not truncate the value if the floating
5668 ;; point value is < LONG_MIN or > LONG_MAX.
5669 (define_insn "*friz"
5670 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5671 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5672 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5673 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5674 && !flag_trapping_math && TARGET_FRIZ"
5675 "friz %0,%1"
5676 [(set_attr "type" "fp")])
5677
5678 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5679 ;; load to properly sign extend the value, but at least doing a store, load
5680 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5681 ;; if we have 32-bit memory ops
5682 (define_insn_and_split "*round32<mode>2_fprs"
5683 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5684 (float:SFDF
5685 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5686 (clobber (match_scratch:DI 2 "=d"))
5687 (clobber (match_scratch:DI 3 "=d"))]
5688 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5689 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5690 && can_create_pseudo_p ()"
5691 "#"
5692 ""
5693 [(pc)]
5694 {
5695 rtx dest = operands[0];
5696 rtx src = operands[1];
5697 rtx tmp1 = operands[2];
5698 rtx tmp2 = operands[3];
5699 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5700
5701 if (GET_CODE (tmp1) == SCRATCH)
5702 tmp1 = gen_reg_rtx (DImode);
5703 if (GET_CODE (tmp2) == SCRATCH)
5704 tmp2 = gen_reg_rtx (DImode);
5705
5706 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5707 emit_insn (gen_stfiwx (stack, tmp1));
5708 emit_insn (gen_lfiwax (tmp2, stack));
5709 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5710 DONE;
5711 }
5712 [(set_attr "type" "fpload")
5713 (set_attr "length" "16")])
5714
5715 (define_insn_and_split "*roundu32<mode>2_fprs"
5716 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5717 (unsigned_float:SFDF
5718 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5719 (clobber (match_scratch:DI 2 "=d"))
5720 (clobber (match_scratch:DI 3 "=d"))]
5721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5722 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5723 && can_create_pseudo_p ()"
5724 "#"
5725 ""
5726 [(pc)]
5727 {
5728 rtx dest = operands[0];
5729 rtx src = operands[1];
5730 rtx tmp1 = operands[2];
5731 rtx tmp2 = operands[3];
5732 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5733
5734 if (GET_CODE (tmp1) == SCRATCH)
5735 tmp1 = gen_reg_rtx (DImode);
5736 if (GET_CODE (tmp2) == SCRATCH)
5737 tmp2 = gen_reg_rtx (DImode);
5738
5739 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5740 emit_insn (gen_stfiwx (stack, tmp1));
5741 emit_insn (gen_lfiwzx (tmp2, stack));
5742 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5743 DONE;
5744 }
5745 [(set_attr "type" "fpload")
5746 (set_attr "length" "16")])
5747
5748 ;; No VSX equivalent to fctid
5749 (define_insn "lrint<mode>di2"
5750 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5751 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5752 UNSPEC_FCTID))]
5753 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5754 "fctid %0,%1"
5755 [(set_attr "type" "fp")])
5756
5757 (define_expand "btrunc<mode>2"
5758 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5759 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5760 UNSPEC_FRIZ))]
5761 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5762 "")
5763
5764 (define_insn "*btrunc<mode>2_fpr"
5765 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5766 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5767 UNSPEC_FRIZ))]
5768 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5769 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5770 "friz %0,%1"
5771 [(set_attr "type" "fp")])
5772
5773 (define_expand "ceil<mode>2"
5774 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5775 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5776 UNSPEC_FRIP))]
5777 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5778 "")
5779
5780 (define_insn "*ceil<mode>2_fpr"
5781 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5782 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5783 UNSPEC_FRIP))]
5784 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5785 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5786 "frip %0,%1"
5787 [(set_attr "type" "fp")])
5788
5789 (define_expand "floor<mode>2"
5790 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5791 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5792 UNSPEC_FRIM))]
5793 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5794 "")
5795
5796 (define_insn "*floor<mode>2_fpr"
5797 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5798 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5799 UNSPEC_FRIM))]
5800 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5801 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5802 "frim %0,%1"
5803 [(set_attr "type" "fp")])
5804
5805 ;; No VSX equivalent to frin
5806 (define_insn "round<mode>2"
5807 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5808 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5809 UNSPEC_FRIN))]
5810 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5811 "frin %0,%1"
5812 [(set_attr "type" "fp")])
5813
5814 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5815 (define_insn "stfiwx"
5816 [(set (match_operand:SI 0 "memory_operand" "=Z")
5817 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
5818 UNSPEC_STFIWX))]
5819 "TARGET_PPC_GFXOPT"
5820 "stfiwx %1,%y0"
5821 [(set_attr "type" "fpstore")])
5822
5823 ;; If we don't have a direct conversion to single precision, don't enable this
5824 ;; conversion for 32-bit without fast math, because we don't have the insn to
5825 ;; generate the fixup swizzle to avoid double rounding problems.
5826 (define_expand "floatsisf2"
5827 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5828 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5829 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5830 && (!TARGET_FPRS
5831 || (TARGET_FPRS
5832 && ((TARGET_FCFIDS && TARGET_LFIWAX)
5833 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5834 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5835 "
5836 {
5837 if (!TARGET_FPRS)
5838 {
5839 if (!REG_P (operands[1]))
5840 operands[1] = force_reg (SImode, operands[1]);
5841 }
5842 else if (TARGET_FCFIDS && TARGET_LFIWAX)
5843 {
5844 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
5845 DONE;
5846 }
5847 else if (TARGET_FCFID && TARGET_LFIWAX)
5848 {
5849 rtx dfreg = gen_reg_rtx (DFmode);
5850 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
5851 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
5852 DONE;
5853 }
5854 else
5855 {
5856 rtx dreg = operands[1];
5857 if (!REG_P (dreg))
5858 dreg = force_reg (SImode, dreg);
5859 dreg = convert_to_mode (DImode, dreg, false);
5860 emit_insn (gen_floatdisf2 (operands[0], dreg));
5861 DONE;
5862 }
5863 }")
5864
5865 (define_expand "floatdidf2"
5866 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5867 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
5868 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
5869 "")
5870
5871 (define_insn "*floatdidf2_fpr"
5872 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5873 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5874 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5875 && !VECTOR_UNIT_VSX_P (DFmode)"
5876 "fcfid %0,%1"
5877 [(set_attr "type" "fp")])
5878
5879 ; Allow the combiner to merge source memory operands to the conversion so that
5880 ; the optimizer/register allocator doesn't try to load the value too early in a
5881 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
5882 ; hit. We will split after reload to avoid the trip through the GPRs
5883
5884 (define_insn_and_split "*floatdidf2_mem"
5885 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5886 (float:DF (match_operand:DI 1 "memory_operand" "m")))
5887 (clobber (match_scratch:DI 2 "=d"))]
5888 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
5889 "#"
5890 "&& reload_completed"
5891 [(set (match_dup 2) (match_dup 1))
5892 (set (match_dup 0) (float:DF (match_dup 2)))]
5893 ""
5894 [(set_attr "length" "8")
5895 (set_attr "type" "fpload")])
5896
5897 (define_expand "floatunsdidf2"
5898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5899 (unsigned_float:DF
5900 (match_operand:DI 1 "gpc_reg_operand" "")))]
5901 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5902 "")
5903
5904 (define_insn "*floatunsdidf2_fcfidu"
5905 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5906 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5907 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
5908 "fcfidu %0,%1"
5909 [(set_attr "type" "fp")
5910 (set_attr "length" "4")])
5911
5912 (define_insn_and_split "*floatunsdidf2_mem"
5913 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5914 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
5915 (clobber (match_scratch:DI 2 "=d"))]
5916 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5917 "#"
5918 "&& reload_completed"
5919 [(set (match_dup 2) (match_dup 1))
5920 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
5921 ""
5922 [(set_attr "length" "8")
5923 (set_attr "type" "fpload")])
5924
5925 (define_expand "floatdisf2"
5926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5927 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5928 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5929 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
5930 "
5931 {
5932 if (!TARGET_FCFIDS)
5933 {
5934 rtx val = operands[1];
5935 if (!flag_unsafe_math_optimizations)
5936 {
5937 rtx label = gen_label_rtx ();
5938 val = gen_reg_rtx (DImode);
5939 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5940 emit_label (label);
5941 }
5942 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5943 DONE;
5944 }
5945 }")
5946
5947 (define_insn "floatdisf2_fcfids"
5948 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5949 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5950 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5951 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5952 "fcfids %0,%1"
5953 [(set_attr "type" "fp")])
5954
5955 (define_insn_and_split "*floatdisf2_mem"
5956 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5957 (float:SF (match_operand:DI 1 "memory_operand" "m")))
5958 (clobber (match_scratch:DI 2 "=f"))]
5959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5960 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5961 "#"
5962 "&& reload_completed"
5963 [(pc)]
5964 "
5965 {
5966 emit_move_insn (operands[2], operands[1]);
5967 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
5968 DONE;
5969 }"
5970 [(set_attr "length" "8")])
5971
5972 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5973 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5974 ;; from double rounding.
5975 ;; Instead of creating a new cpu type for two FP operations, just use fp
5976 (define_insn_and_split "floatdisf2_internal1"
5977 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5978 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
5979 (clobber (match_scratch:DF 2 "=d"))]
5980 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5981 "#"
5982 "&& reload_completed"
5983 [(set (match_dup 2)
5984 (float:DF (match_dup 1)))
5985 (set (match_dup 0)
5986 (float_truncate:SF (match_dup 2)))]
5987 ""
5988 [(set_attr "length" "8")
5989 (set_attr "type" "fp")])
5990
5991 ;; Twiddles bits to avoid double rounding.
5992 ;; Bits that might be truncated when converting to DFmode are replaced
5993 ;; by a bit that won't be lost at that stage, but is below the SFmode
5994 ;; rounding position.
5995 (define_expand "floatdisf2_internal2"
5996 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5997 (const_int 53)))
5998 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5999 (const_int 2047)))
6000 (clobber (scratch:CC))])
6001 (set (match_dup 3) (plus:DI (match_dup 3)
6002 (const_int 1)))
6003 (set (match_dup 0) (plus:DI (match_dup 0)
6004 (const_int 2047)))
6005 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6006 (const_int 2)))
6007 (set (match_dup 0) (ior:DI (match_dup 0)
6008 (match_dup 1)))
6009 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6010 (const_int -2048)))
6011 (clobber (scratch:CC))])
6012 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6013 (label_ref (match_operand:DI 2 "" ""))
6014 (pc)))
6015 (set (match_dup 0) (match_dup 1))]
6016 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6017 "
6018 {
6019 operands[3] = gen_reg_rtx (DImode);
6020 operands[4] = gen_reg_rtx (CCUNSmode);
6021 }")
6022
6023 (define_expand "floatunsdisf2"
6024 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6025 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6026 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6027 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6028 "")
6029
6030 (define_insn "floatunsdisf2_fcfidus"
6031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6032 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6033 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6034 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6035 "fcfidus %0,%1"
6036 [(set_attr "type" "fp")])
6037
6038 (define_insn_and_split "*floatunsdisf2_mem"
6039 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6040 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6041 (clobber (match_scratch:DI 2 "=f"))]
6042 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6043 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6044 "#"
6045 "&& reload_completed"
6046 [(pc)]
6047 "
6048 {
6049 emit_move_insn (operands[2], operands[1]);
6050 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6051 DONE;
6052 }"
6053 [(set_attr "length" "8")
6054 (set_attr "type" "fpload")])
6055 \f
6056 ;; Define the DImode operations that can be done in a small number
6057 ;; of instructions. The & constraints are to prevent the register
6058 ;; allocator from allocating registers that overlap with the inputs
6059 ;; (for example, having an input in 7,8 and an output in 6,7). We
6060 ;; also allow for the output being the same as one of the inputs.
6061
6062 (define_insn "*adddi3_noppc64"
6063 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6064 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6065 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6066 "! TARGET_POWERPC64"
6067 "*
6068 {
6069 if (WORDS_BIG_ENDIAN)
6070 return (GET_CODE (operands[2])) != CONST_INT
6071 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6072 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6073 else
6074 return (GET_CODE (operands[2])) != CONST_INT
6075 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6076 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6077 }"
6078 [(set_attr "type" "two")
6079 (set_attr "length" "8")])
6080
6081 (define_insn "*subdi3_noppc64"
6082 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6083 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6084 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6085 "! TARGET_POWERPC64"
6086 "*
6087 {
6088 if (WORDS_BIG_ENDIAN)
6089 return (GET_CODE (operands[1]) != CONST_INT)
6090 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6091 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6092 else
6093 return (GET_CODE (operands[1]) != CONST_INT)
6094 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6095 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6096 }"
6097 [(set_attr "type" "two")
6098 (set_attr "length" "8")])
6099
6100 (define_insn "*negdi2_noppc64"
6101 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6102 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6103 "! TARGET_POWERPC64"
6104 "*
6105 {
6106 return (WORDS_BIG_ENDIAN)
6107 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6108 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6109 }"
6110 [(set_attr "type" "two")
6111 (set_attr "length" "8")])
6112
6113 (define_insn "mulsidi3"
6114 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6115 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6116 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6117 "! TARGET_POWERPC64"
6118 {
6119 return (WORDS_BIG_ENDIAN)
6120 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6121 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6122 }
6123 [(set_attr "type" "imul")
6124 (set_attr "length" "8")])
6125
6126 (define_split
6127 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6128 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6129 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6130 "! TARGET_POWERPC64 && reload_completed"
6131 [(set (match_dup 3)
6132 (truncate:SI
6133 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6134 (sign_extend:DI (match_dup 2)))
6135 (const_int 32))))
6136 (set (match_dup 4)
6137 (mult:SI (match_dup 1)
6138 (match_dup 2)))]
6139 "
6140 {
6141 int endian = (WORDS_BIG_ENDIAN == 0);
6142 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6143 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6144 }")
6145
6146 (define_insn "umulsidi3"
6147 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6148 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6149 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6150 "! TARGET_POWERPC64"
6151 "*
6152 {
6153 return (WORDS_BIG_ENDIAN)
6154 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6155 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6156 }"
6157 [(set_attr "type" "imul")
6158 (set_attr "length" "8")])
6159
6160 (define_split
6161 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6162 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6163 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6164 "! TARGET_POWERPC64 && reload_completed"
6165 [(set (match_dup 3)
6166 (truncate:SI
6167 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6168 (zero_extend:DI (match_dup 2)))
6169 (const_int 32))))
6170 (set (match_dup 4)
6171 (mult:SI (match_dup 1)
6172 (match_dup 2)))]
6173 "
6174 {
6175 int endian = (WORDS_BIG_ENDIAN == 0);
6176 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6177 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6178 }")
6179
6180 (define_insn "smulsi3_highpart"
6181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6182 (truncate:SI
6183 (lshiftrt:DI (mult:DI (sign_extend:DI
6184 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6185 (sign_extend:DI
6186 (match_operand:SI 2 "gpc_reg_operand" "r")))
6187 (const_int 32))))]
6188 ""
6189 "mulhw %0,%1,%2"
6190 [(set_attr "type" "imul")])
6191
6192 (define_insn "umulsi3_highpart"
6193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6194 (truncate:SI
6195 (lshiftrt:DI (mult:DI (zero_extend:DI
6196 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6197 (zero_extend:DI
6198 (match_operand:SI 2 "gpc_reg_operand" "r")))
6199 (const_int 32))))]
6200 ""
6201 "mulhwu %0,%1,%2"
6202 [(set_attr "type" "imul")])
6203
6204 ;; Shift by a variable amount is too complex to be worth open-coding. We
6205 ;; just handle shifts by constants.
6206 (define_insn "ashrdi3_no_power"
6207 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6208 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6209 (match_operand:SI 2 "const_int_operand" "M,i")))]
6210 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6211 "@
6212 srawi %0,%1,31\;srawi %L0,%1,%h2
6213 srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2"
6214 [(set_attr "type" "two,three")
6215 (set_attr "length" "8,12")])
6216
6217 (define_insn "*ashrdisi3_noppc64"
6218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6219 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6220 (const_int 32)) 4))]
6221 "TARGET_32BIT && !TARGET_POWERPC64"
6222 "*
6223 {
6224 if (REGNO (operands[0]) == REGNO (operands[1]))
6225 return \"\";
6226 else
6227 return \"mr %0,%1\";
6228 }"
6229 [(set_attr "length" "4")])
6230
6231 \f
6232 ;; PowerPC64 DImode operations.
6233
6234 (define_insn "muldi3"
6235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6236 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6237 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6238 "TARGET_POWERPC64"
6239 "@
6240 mulld %0,%1,%2
6241 mulli %0,%1,%2"
6242 [(set (attr "type")
6243 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6244 (const_string "imul3")
6245 (match_operand:SI 2 "short_cint_operand" "")
6246 (const_string "imul2")]
6247 (const_string "lmul")))])
6248
6249 (define_insn "*muldi3_internal1"
6250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6251 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6252 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6253 (const_int 0)))
6254 (clobber (match_scratch:DI 3 "=r,r"))]
6255 "TARGET_POWERPC64"
6256 "@
6257 mulld. %3,%1,%2
6258 #"
6259 [(set_attr "type" "lmul_compare")
6260 (set_attr "length" "4,8")])
6261
6262 (define_split
6263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6264 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6265 (match_operand:DI 2 "gpc_reg_operand" ""))
6266 (const_int 0)))
6267 (clobber (match_scratch:DI 3 ""))]
6268 "TARGET_POWERPC64 && reload_completed"
6269 [(set (match_dup 3)
6270 (mult:DI (match_dup 1) (match_dup 2)))
6271 (set (match_dup 0)
6272 (compare:CC (match_dup 3)
6273 (const_int 0)))]
6274 "")
6275
6276 (define_insn "*muldi3_internal2"
6277 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6278 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6279 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6280 (const_int 0)))
6281 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6282 (mult:DI (match_dup 1) (match_dup 2)))]
6283 "TARGET_POWERPC64"
6284 "@
6285 mulld. %0,%1,%2
6286 #"
6287 [(set_attr "type" "lmul_compare")
6288 (set_attr "length" "4,8")])
6289
6290 (define_split
6291 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6292 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6293 (match_operand:DI 2 "gpc_reg_operand" ""))
6294 (const_int 0)))
6295 (set (match_operand:DI 0 "gpc_reg_operand" "")
6296 (mult:DI (match_dup 1) (match_dup 2)))]
6297 "TARGET_POWERPC64 && reload_completed"
6298 [(set (match_dup 0)
6299 (mult:DI (match_dup 1) (match_dup 2)))
6300 (set (match_dup 3)
6301 (compare:CC (match_dup 0)
6302 (const_int 0)))]
6303 "")
6304
6305 (define_insn "smuldi3_highpart"
6306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6307 (truncate:DI
6308 (lshiftrt:TI (mult:TI (sign_extend:TI
6309 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6310 (sign_extend:TI
6311 (match_operand:DI 2 "gpc_reg_operand" "r")))
6312 (const_int 64))))]
6313 "TARGET_POWERPC64"
6314 "mulhd %0,%1,%2"
6315 [(set_attr "type" "lmul")])
6316
6317 (define_insn "umuldi3_highpart"
6318 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6319 (truncate:DI
6320 (lshiftrt:TI (mult:TI (zero_extend:TI
6321 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6322 (zero_extend:TI
6323 (match_operand:DI 2 "gpc_reg_operand" "r")))
6324 (const_int 64))))]
6325 "TARGET_POWERPC64"
6326 "mulhdu %0,%1,%2"
6327 [(set_attr "type" "lmul")])
6328
6329 (define_insn "rotldi3"
6330 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6331 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6332 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6333 "TARGET_POWERPC64"
6334 "@
6335 rldcl %0,%1,%2,0
6336 rldicl %0,%1,%H2,0"
6337 [(set_attr "type" "var_shift_rotate,integer")])
6338
6339 (define_insn "*rotldi3_internal2"
6340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6341 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6342 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6343 (const_int 0)))
6344 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6345 "TARGET_64BIT"
6346 "@
6347 rldcl. %3,%1,%2,0
6348 rldicl. %3,%1,%H2,0
6349 #
6350 #"
6351 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6352 (set_attr "length" "4,4,8,8")])
6353
6354 (define_split
6355 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6356 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6357 (match_operand:DI 2 "reg_or_cint_operand" ""))
6358 (const_int 0)))
6359 (clobber (match_scratch:DI 3 ""))]
6360 "TARGET_POWERPC64 && reload_completed"
6361 [(set (match_dup 3)
6362 (rotate:DI (match_dup 1) (match_dup 2)))
6363 (set (match_dup 0)
6364 (compare:CC (match_dup 3)
6365 (const_int 0)))]
6366 "")
6367
6368 (define_insn "*rotldi3_internal3"
6369 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6370 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6371 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6372 (const_int 0)))
6373 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6374 (rotate:DI (match_dup 1) (match_dup 2)))]
6375 "TARGET_64BIT"
6376 "@
6377 rldcl. %0,%1,%2,0
6378 rldicl. %0,%1,%H2,0
6379 #
6380 #"
6381 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6382 (set_attr "length" "4,4,8,8")])
6383
6384 (define_split
6385 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6386 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6387 (match_operand:DI 2 "reg_or_cint_operand" ""))
6388 (const_int 0)))
6389 (set (match_operand:DI 0 "gpc_reg_operand" "")
6390 (rotate:DI (match_dup 1) (match_dup 2)))]
6391 "TARGET_POWERPC64 && reload_completed"
6392 [(set (match_dup 0)
6393 (rotate:DI (match_dup 1) (match_dup 2)))
6394 (set (match_dup 3)
6395 (compare:CC (match_dup 0)
6396 (const_int 0)))]
6397 "")
6398
6399 (define_insn "*rotldi3_internal4"
6400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6401 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6402 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6403 (match_operand:DI 3 "mask64_operand" "n,n")))]
6404 "TARGET_POWERPC64"
6405 "@
6406 rldc%B3 %0,%1,%2,%S3
6407 rldic%B3 %0,%1,%H2,%S3"
6408 [(set_attr "type" "var_shift_rotate,integer")])
6409
6410 (define_insn "*rotldi3_internal5"
6411 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6412 (compare:CC (and:DI
6413 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6414 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6415 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6416 (const_int 0)))
6417 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6418 "TARGET_64BIT"
6419 "@
6420 rldc%B3. %4,%1,%2,%S3
6421 rldic%B3. %4,%1,%H2,%S3
6422 #
6423 #"
6424 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6425 (set_attr "length" "4,4,8,8")])
6426
6427 (define_split
6428 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6429 (compare:CC (and:DI
6430 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6431 (match_operand:DI 2 "reg_or_cint_operand" ""))
6432 (match_operand:DI 3 "mask64_operand" ""))
6433 (const_int 0)))
6434 (clobber (match_scratch:DI 4 ""))]
6435 "TARGET_POWERPC64 && reload_completed"
6436 [(set (match_dup 4)
6437 (and:DI (rotate:DI (match_dup 1)
6438 (match_dup 2))
6439 (match_dup 3)))
6440 (set (match_dup 0)
6441 (compare:CC (match_dup 4)
6442 (const_int 0)))]
6443 "")
6444
6445 (define_insn "*rotldi3_internal6"
6446 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6447 (compare:CC (and:DI
6448 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6449 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6450 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6451 (const_int 0)))
6452 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6453 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6454 "TARGET_64BIT"
6455 "@
6456 rldc%B3. %0,%1,%2,%S3
6457 rldic%B3. %0,%1,%H2,%S3
6458 #
6459 #"
6460 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6461 (set_attr "length" "4,4,8,8")])
6462
6463 (define_split
6464 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6465 (compare:CC (and:DI
6466 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6467 (match_operand:DI 2 "reg_or_cint_operand" ""))
6468 (match_operand:DI 3 "mask64_operand" ""))
6469 (const_int 0)))
6470 (set (match_operand:DI 0 "gpc_reg_operand" "")
6471 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6472 "TARGET_POWERPC64 && reload_completed"
6473 [(set (match_dup 0)
6474 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6475 (set (match_dup 4)
6476 (compare:CC (match_dup 0)
6477 (const_int 0)))]
6478 "")
6479
6480 (define_insn "*rotldi3_internal7"
6481 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6482 (zero_extend:DI
6483 (subreg:QI
6484 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6485 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6486 "TARGET_POWERPC64"
6487 "@
6488 rldcl %0,%1,%2,56
6489 rldicl %0,%1,%H2,56"
6490 [(set_attr "type" "var_shift_rotate,integer")])
6491
6492 (define_insn "*rotldi3_internal8"
6493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6494 (compare:CC (zero_extend:DI
6495 (subreg:QI
6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6497 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6498 (const_int 0)))
6499 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6500 "TARGET_64BIT"
6501 "@
6502 rldcl. %3,%1,%2,56
6503 rldicl. %3,%1,%H2,56
6504 #
6505 #"
6506 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6507 (set_attr "length" "4,4,8,8")])
6508
6509 (define_split
6510 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6511 (compare:CC (zero_extend:DI
6512 (subreg:QI
6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6514 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6515 (const_int 0)))
6516 (clobber (match_scratch:DI 3 ""))]
6517 "TARGET_POWERPC64 && reload_completed"
6518 [(set (match_dup 3)
6519 (zero_extend:DI (subreg:QI
6520 (rotate:DI (match_dup 1)
6521 (match_dup 2)) 0)))
6522 (set (match_dup 0)
6523 (compare:CC (match_dup 3)
6524 (const_int 0)))]
6525 "")
6526
6527 (define_insn "*rotldi3_internal9"
6528 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6529 (compare:CC (zero_extend:DI
6530 (subreg:QI
6531 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6532 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6533 (const_int 0)))
6534 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6535 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6536 "TARGET_64BIT"
6537 "@
6538 rldcl. %0,%1,%2,56
6539 rldicl. %0,%1,%H2,56
6540 #
6541 #"
6542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6543 (set_attr "length" "4,4,8,8")])
6544
6545 (define_split
6546 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6547 (compare:CC (zero_extend:DI
6548 (subreg:QI
6549 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6550 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6551 (const_int 0)))
6552 (set (match_operand:DI 0 "gpc_reg_operand" "")
6553 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6554 "TARGET_POWERPC64 && reload_completed"
6555 [(set (match_dup 0)
6556 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6557 (set (match_dup 3)
6558 (compare:CC (match_dup 0)
6559 (const_int 0)))]
6560 "")
6561
6562 (define_insn "*rotldi3_internal10"
6563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6564 (zero_extend:DI
6565 (subreg:HI
6566 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6567 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6568 "TARGET_POWERPC64"
6569 "@
6570 rldcl %0,%1,%2,48
6571 rldicl %0,%1,%H2,48"
6572 [(set_attr "type" "var_shift_rotate,integer")])
6573
6574 (define_insn "*rotldi3_internal11"
6575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6576 (compare:CC (zero_extend:DI
6577 (subreg:HI
6578 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6579 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6580 (const_int 0)))
6581 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6582 "TARGET_64BIT"
6583 "@
6584 rldcl. %3,%1,%2,48
6585 rldicl. %3,%1,%H2,48
6586 #
6587 #"
6588 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6589 (set_attr "length" "4,4,8,8")])
6590
6591 (define_split
6592 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6593 (compare:CC (zero_extend:DI
6594 (subreg:HI
6595 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6596 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6597 (const_int 0)))
6598 (clobber (match_scratch:DI 3 ""))]
6599 "TARGET_POWERPC64 && reload_completed"
6600 [(set (match_dup 3)
6601 (zero_extend:DI (subreg:HI
6602 (rotate:DI (match_dup 1)
6603 (match_dup 2)) 0)))
6604 (set (match_dup 0)
6605 (compare:CC (match_dup 3)
6606 (const_int 0)))]
6607 "")
6608
6609 (define_insn "*rotldi3_internal12"
6610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6611 (compare:CC (zero_extend:DI
6612 (subreg:HI
6613 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6614 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6615 (const_int 0)))
6616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6617 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6618 "TARGET_64BIT"
6619 "@
6620 rldcl. %0,%1,%2,48
6621 rldicl. %0,%1,%H2,48
6622 #
6623 #"
6624 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6625 (set_attr "length" "4,4,8,8")])
6626
6627 (define_split
6628 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6629 (compare:CC (zero_extend:DI
6630 (subreg:HI
6631 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6632 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6633 (const_int 0)))
6634 (set (match_operand:DI 0 "gpc_reg_operand" "")
6635 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6636 "TARGET_POWERPC64 && reload_completed"
6637 [(set (match_dup 0)
6638 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6639 (set (match_dup 3)
6640 (compare:CC (match_dup 0)
6641 (const_int 0)))]
6642 "")
6643
6644 (define_insn "*rotldi3_internal13"
6645 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6646 (zero_extend:DI
6647 (subreg:SI
6648 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6649 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6650 "TARGET_POWERPC64"
6651 "@
6652 rldcl %0,%1,%2,32
6653 rldicl %0,%1,%H2,32"
6654 [(set_attr "type" "var_shift_rotate,integer")])
6655
6656 (define_insn "*rotldi3_internal14"
6657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6658 (compare:CC (zero_extend:DI
6659 (subreg:SI
6660 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6661 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6662 (const_int 0)))
6663 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6664 "TARGET_64BIT"
6665 "@
6666 rldcl. %3,%1,%2,32
6667 rldicl. %3,%1,%H2,32
6668 #
6669 #"
6670 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6671 (set_attr "length" "4,4,8,8")])
6672
6673 (define_split
6674 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6675 (compare:CC (zero_extend:DI
6676 (subreg:SI
6677 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6678 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6679 (const_int 0)))
6680 (clobber (match_scratch:DI 3 ""))]
6681 "TARGET_POWERPC64 && reload_completed"
6682 [(set (match_dup 3)
6683 (zero_extend:DI (subreg:SI
6684 (rotate:DI (match_dup 1)
6685 (match_dup 2)) 0)))
6686 (set (match_dup 0)
6687 (compare:CC (match_dup 3)
6688 (const_int 0)))]
6689 "")
6690
6691 (define_insn "*rotldi3_internal15"
6692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6693 (compare:CC (zero_extend:DI
6694 (subreg:SI
6695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6696 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6697 (const_int 0)))
6698 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6699 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6700 "TARGET_64BIT"
6701 "@
6702 rldcl. %0,%1,%2,32
6703 rldicl. %0,%1,%H2,32
6704 #
6705 #"
6706 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6707 (set_attr "length" "4,4,8,8")])
6708
6709 (define_split
6710 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6711 (compare:CC (zero_extend:DI
6712 (subreg:SI
6713 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6714 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6715 (const_int 0)))
6716 (set (match_operand:DI 0 "gpc_reg_operand" "")
6717 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6718 "TARGET_POWERPC64 && reload_completed"
6719 [(set (match_dup 0)
6720 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6721 (set (match_dup 3)
6722 (compare:CC (match_dup 0)
6723 (const_int 0)))]
6724 "")
6725
6726 (define_expand "ashldi3"
6727 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6728 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6729 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6730 "TARGET_POWERPC64"
6731 "")
6732
6733 (define_insn "*ashldi3_internal1"
6734 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6735 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6736 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6737 "TARGET_POWERPC64"
6738 "@
6739 sld %0,%1,%2
6740 sldi %0,%1,%H2"
6741 [(set_attr "type" "var_shift_rotate,shift")])
6742
6743 (define_insn "*ashldi3_internal2"
6744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6745 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6746 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6747 (const_int 0)))
6748 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6749 "TARGET_64BIT"
6750 "@
6751 sld. %3,%1,%2
6752 sldi. %3,%1,%H2
6753 #
6754 #"
6755 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6756 (set_attr "length" "4,4,8,8")])
6757
6758 (define_split
6759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6760 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6761 (match_operand:SI 2 "reg_or_cint_operand" ""))
6762 (const_int 0)))
6763 (clobber (match_scratch:DI 3 ""))]
6764 "TARGET_POWERPC64 && reload_completed"
6765 [(set (match_dup 3)
6766 (ashift:DI (match_dup 1) (match_dup 2)))
6767 (set (match_dup 0)
6768 (compare:CC (match_dup 3)
6769 (const_int 0)))]
6770 "")
6771
6772 (define_insn "*ashldi3_internal3"
6773 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6774 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6775 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6776 (const_int 0)))
6777 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6778 (ashift:DI (match_dup 1) (match_dup 2)))]
6779 "TARGET_64BIT"
6780 "@
6781 sld. %0,%1,%2
6782 sldi. %0,%1,%H2
6783 #
6784 #"
6785 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6786 (set_attr "length" "4,4,8,8")])
6787
6788 (define_split
6789 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6790 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6791 (match_operand:SI 2 "reg_or_cint_operand" ""))
6792 (const_int 0)))
6793 (set (match_operand:DI 0 "gpc_reg_operand" "")
6794 (ashift:DI (match_dup 1) (match_dup 2)))]
6795 "TARGET_POWERPC64 && reload_completed"
6796 [(set (match_dup 0)
6797 (ashift:DI (match_dup 1) (match_dup 2)))
6798 (set (match_dup 3)
6799 (compare:CC (match_dup 0)
6800 (const_int 0)))]
6801 "")
6802
6803 (define_insn "*ashldi3_internal4"
6804 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6805 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6806 (match_operand:SI 2 "const_int_operand" "i"))
6807 (match_operand:DI 3 "const_int_operand" "n")))]
6808 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6809 "rldic %0,%1,%H2,%W3")
6810
6811 (define_insn "ashldi3_internal5"
6812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6813 (compare:CC
6814 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6815 (match_operand:SI 2 "const_int_operand" "i,i"))
6816 (match_operand:DI 3 "const_int_operand" "n,n"))
6817 (const_int 0)))
6818 (clobber (match_scratch:DI 4 "=r,r"))]
6819 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6820 "@
6821 rldic. %4,%1,%H2,%W3
6822 #"
6823 [(set_attr "type" "compare")
6824 (set_attr "length" "4,8")])
6825
6826 (define_split
6827 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6828 (compare:CC
6829 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6830 (match_operand:SI 2 "const_int_operand" ""))
6831 (match_operand:DI 3 "const_int_operand" ""))
6832 (const_int 0)))
6833 (clobber (match_scratch:DI 4 ""))]
6834 "TARGET_POWERPC64 && reload_completed
6835 && includes_rldic_lshift_p (operands[2], operands[3])"
6836 [(set (match_dup 4)
6837 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6838 (match_dup 3)))
6839 (set (match_dup 0)
6840 (compare:CC (match_dup 4)
6841 (const_int 0)))]
6842 "")
6843
6844 (define_insn "*ashldi3_internal6"
6845 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6846 (compare:CC
6847 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6848 (match_operand:SI 2 "const_int_operand" "i,i"))
6849 (match_operand:DI 3 "const_int_operand" "n,n"))
6850 (const_int 0)))
6851 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6852 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6853 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6854 "@
6855 rldic. %0,%1,%H2,%W3
6856 #"
6857 [(set_attr "type" "compare")
6858 (set_attr "length" "4,8")])
6859
6860 (define_split
6861 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6862 (compare:CC
6863 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:SI 2 "const_int_operand" ""))
6865 (match_operand:DI 3 "const_int_operand" ""))
6866 (const_int 0)))
6867 (set (match_operand:DI 0 "gpc_reg_operand" "")
6868 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6869 "TARGET_POWERPC64 && reload_completed
6870 && includes_rldic_lshift_p (operands[2], operands[3])"
6871 [(set (match_dup 0)
6872 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6873 (match_dup 3)))
6874 (set (match_dup 4)
6875 (compare:CC (match_dup 0)
6876 (const_int 0)))]
6877 "")
6878
6879 (define_insn "*ashldi3_internal7"
6880 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6881 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6882 (match_operand:SI 2 "const_int_operand" "i"))
6883 (match_operand:DI 3 "mask64_operand" "n")))]
6884 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6885 "rldicr %0,%1,%H2,%S3")
6886
6887 (define_insn "ashldi3_internal8"
6888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6889 (compare:CC
6890 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6891 (match_operand:SI 2 "const_int_operand" "i,i"))
6892 (match_operand:DI 3 "mask64_operand" "n,n"))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 4 "=r,r"))]
6895 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6896 "@
6897 rldicr. %4,%1,%H2,%S3
6898 #"
6899 [(set_attr "type" "compare")
6900 (set_attr "length" "4,8")])
6901
6902 (define_split
6903 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6904 (compare:CC
6905 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6906 (match_operand:SI 2 "const_int_operand" ""))
6907 (match_operand:DI 3 "mask64_operand" ""))
6908 (const_int 0)))
6909 (clobber (match_scratch:DI 4 ""))]
6910 "TARGET_POWERPC64 && reload_completed
6911 && includes_rldicr_lshift_p (operands[2], operands[3])"
6912 [(set (match_dup 4)
6913 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6914 (match_dup 3)))
6915 (set (match_dup 0)
6916 (compare:CC (match_dup 4)
6917 (const_int 0)))]
6918 "")
6919
6920 (define_insn "*ashldi3_internal9"
6921 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6922 (compare:CC
6923 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6924 (match_operand:SI 2 "const_int_operand" "i,i"))
6925 (match_operand:DI 3 "mask64_operand" "n,n"))
6926 (const_int 0)))
6927 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6928 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6929 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6930 "@
6931 rldicr. %0,%1,%H2,%S3
6932 #"
6933 [(set_attr "type" "compare")
6934 (set_attr "length" "4,8")])
6935
6936 (define_split
6937 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6938 (compare:CC
6939 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6940 (match_operand:SI 2 "const_int_operand" ""))
6941 (match_operand:DI 3 "mask64_operand" ""))
6942 (const_int 0)))
6943 (set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6945 "TARGET_POWERPC64 && reload_completed
6946 && includes_rldicr_lshift_p (operands[2], operands[3])"
6947 [(set (match_dup 0)
6948 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6949 (match_dup 3)))
6950 (set (match_dup 4)
6951 (compare:CC (match_dup 0)
6952 (const_int 0)))]
6953 "")
6954
6955 (define_expand "lshrdi3"
6956 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6957 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6958 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6959 "TARGET_POWERPC64"
6960 "")
6961
6962 (define_insn "*lshrdi3_internal1"
6963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6964 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6965 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6966 "TARGET_POWERPC64"
6967 "@
6968 srd %0,%1,%2
6969 srdi %0,%1,%H2"
6970 [(set_attr "type" "var_shift_rotate,shift")])
6971
6972 (define_insn "*lshrdi3_internal2"
6973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6974 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6975 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6976 (const_int 0)))
6977 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6978 "TARGET_64BIT "
6979 "@
6980 srd. %3,%1,%2
6981 srdi. %3,%1,%H2
6982 #
6983 #"
6984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6985 (set_attr "length" "4,4,8,8")])
6986
6987 (define_split
6988 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6989 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6990 (match_operand:SI 2 "reg_or_cint_operand" ""))
6991 (const_int 0)))
6992 (clobber (match_scratch:DI 3 ""))]
6993 "TARGET_POWERPC64 && reload_completed"
6994 [(set (match_dup 3)
6995 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6996 (set (match_dup 0)
6997 (compare:CC (match_dup 3)
6998 (const_int 0)))]
6999 "")
7000
7001 (define_insn "*lshrdi3_internal3"
7002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7003 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7004 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7005 (const_int 0)))
7006 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7007 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7008 "TARGET_64BIT"
7009 "@
7010 srd. %0,%1,%2
7011 srdi. %0,%1,%H2
7012 #
7013 #"
7014 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7015 (set_attr "length" "4,4,8,8")])
7016
7017 (define_split
7018 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7019 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:SI 2 "reg_or_cint_operand" ""))
7021 (const_int 0)))
7022 (set (match_operand:DI 0 "gpc_reg_operand" "")
7023 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7024 "TARGET_POWERPC64 && reload_completed"
7025 [(set (match_dup 0)
7026 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7027 (set (match_dup 3)
7028 (compare:CC (match_dup 0)
7029 (const_int 0)))]
7030 "")
7031
7032 (define_expand "ashrdi3"
7033 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7034 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7035 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7036 "WORDS_BIG_ENDIAN"
7037 "
7038 {
7039 if (TARGET_POWERPC64)
7040 ;
7041 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7042 && WORDS_BIG_ENDIAN)
7043 {
7044 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7045 DONE;
7046 }
7047 else
7048 FAIL;
7049 }")
7050
7051 (define_insn "*ashrdi3_internal1"
7052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7053 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7054 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7055 "TARGET_POWERPC64"
7056 "@
7057 srad %0,%1,%2
7058 sradi %0,%1,%H2"
7059 [(set_attr "type" "var_shift_rotate,shift")])
7060
7061 (define_insn "*ashrdi3_internal2"
7062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7063 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7064 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7065 (const_int 0)))
7066 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7067 "TARGET_64BIT"
7068 "@
7069 srad. %3,%1,%2
7070 sradi. %3,%1,%H2
7071 #
7072 #"
7073 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7074 (set_attr "length" "4,4,8,8")])
7075
7076 (define_split
7077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7078 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7079 (match_operand:SI 2 "reg_or_cint_operand" ""))
7080 (const_int 0)))
7081 (clobber (match_scratch:DI 3 ""))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 3)
7084 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7085 (set (match_dup 0)
7086 (compare:CC (match_dup 3)
7087 (const_int 0)))]
7088 "")
7089
7090 (define_insn "*ashrdi3_internal3"
7091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7092 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7093 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7094 (const_int 0)))
7095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7096 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7097 "TARGET_64BIT"
7098 "@
7099 srad. %0,%1,%2
7100 sradi. %0,%1,%H2
7101 #
7102 #"
7103 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7104 (set_attr "length" "4,4,8,8")])
7105
7106 (define_split
7107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7108 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7109 (match_operand:SI 2 "reg_or_cint_operand" ""))
7110 (const_int 0)))
7111 (set (match_operand:DI 0 "gpc_reg_operand" "")
7112 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7113 "TARGET_POWERPC64 && reload_completed"
7114 [(set (match_dup 0)
7115 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7116 (set (match_dup 3)
7117 (compare:CC (match_dup 0)
7118 (const_int 0)))]
7119 "")
7120
7121 (define_expand "anddi3"
7122 [(parallel
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7124 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7125 (match_operand:DI 2 "and64_2_operand" "")))
7126 (clobber (match_scratch:CC 3 ""))])]
7127 "TARGET_POWERPC64"
7128 "")
7129
7130 (define_insn "anddi3_mc"
7131 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7132 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7133 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7134 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7135 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7136 "@
7137 and %0,%1,%2
7138 rldic%B2 %0,%1,0,%S2
7139 rlwinm %0,%1,0,%m2,%M2
7140 andi. %0,%1,%b2
7141 andis. %0,%1,%u2
7142 #"
7143 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7144 (set_attr "length" "4,4,4,4,4,8")])
7145
7146 (define_insn "anddi3_nomc"
7147 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7148 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7149 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7150 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7151 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7152 "@
7153 and %0,%1,%2
7154 rldic%B2 %0,%1,0,%S2
7155 rlwinm %0,%1,0,%m2,%M2
7156 #"
7157 [(set_attr "length" "4,4,4,8")])
7158
7159 (define_split
7160 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7161 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7162 (match_operand:DI 2 "mask64_2_operand" "")))
7163 (clobber (match_scratch:CC 3 ""))]
7164 "TARGET_POWERPC64
7165 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7166 && !mask_operand (operands[2], DImode)
7167 && !mask64_operand (operands[2], DImode)"
7168 [(set (match_dup 0)
7169 (and:DI (rotate:DI (match_dup 1)
7170 (match_dup 4))
7171 (match_dup 5)))
7172 (set (match_dup 0)
7173 (and:DI (rotate:DI (match_dup 0)
7174 (match_dup 6))
7175 (match_dup 7)))]
7176 {
7177 build_mask64_2_operands (operands[2], &operands[4]);
7178 })
7179
7180 (define_insn "*anddi3_internal2_mc"
7181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7182 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7183 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7184 (const_int 0)))
7185 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7186 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7187 "TARGET_64BIT && rs6000_gen_cell_microcode"
7188 "@
7189 and. %3,%1,%2
7190 rldic%B2. %3,%1,0,%S2
7191 rlwinm. %3,%1,0,%m2,%M2
7192 andi. %3,%1,%b2
7193 andis. %3,%1,%u2
7194 #
7195 #
7196 #
7197 #
7198 #
7199 #
7200 #"
7201 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7202 fast_compare,compare,compare,compare,compare,compare,\
7203 compare,compare")
7204 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7205
7206 (define_split
7207 [(set (match_operand:CC 0 "cc_reg_operand" "")
7208 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7209 (match_operand:DI 2 "mask64_2_operand" ""))
7210 (const_int 0)))
7211 (clobber (match_scratch:DI 3 ""))
7212 (clobber (match_scratch:CC 4 ""))]
7213 "TARGET_64BIT && reload_completed
7214 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7215 && !mask_operand (operands[2], DImode)
7216 && !mask64_operand (operands[2], DImode)"
7217 [(set (match_dup 3)
7218 (and:DI (rotate:DI (match_dup 1)
7219 (match_dup 5))
7220 (match_dup 6)))
7221 (parallel [(set (match_dup 0)
7222 (compare:CC (and:DI (rotate:DI (match_dup 3)
7223 (match_dup 7))
7224 (match_dup 8))
7225 (const_int 0)))
7226 (clobber (match_dup 3))])]
7227 "
7228 {
7229 build_mask64_2_operands (operands[2], &operands[5]);
7230 }")
7231
7232 (define_insn "*anddi3_internal3_mc"
7233 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7234 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7235 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7236 (const_int 0)))
7237 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7238 (and:DI (match_dup 1) (match_dup 2)))
7239 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7240 "TARGET_64BIT && rs6000_gen_cell_microcode"
7241 "@
7242 and. %0,%1,%2
7243 rldic%B2. %0,%1,0,%S2
7244 rlwinm. %0,%1,0,%m2,%M2
7245 andi. %0,%1,%b2
7246 andis. %0,%1,%u2
7247 #
7248 #
7249 #
7250 #
7251 #
7252 #
7253 #"
7254 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7255 fast_compare,compare,compare,compare,compare,compare,\
7256 compare,compare")
7257 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7258
7259 (define_split
7260 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7261 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7262 (match_operand:DI 2 "and64_2_operand" ""))
7263 (const_int 0)))
7264 (set (match_operand:DI 0 "gpc_reg_operand" "")
7265 (and:DI (match_dup 1) (match_dup 2)))
7266 (clobber (match_scratch:CC 4 ""))]
7267 "TARGET_64BIT && reload_completed"
7268 [(parallel [(set (match_dup 0)
7269 (and:DI (match_dup 1) (match_dup 2)))
7270 (clobber (match_dup 4))])
7271 (set (match_dup 3)
7272 (compare:CC (match_dup 0)
7273 (const_int 0)))]
7274 "")
7275
7276 (define_split
7277 [(set (match_operand:CC 3 "cc_reg_operand" "")
7278 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7279 (match_operand:DI 2 "mask64_2_operand" ""))
7280 (const_int 0)))
7281 (set (match_operand:DI 0 "gpc_reg_operand" "")
7282 (and:DI (match_dup 1) (match_dup 2)))
7283 (clobber (match_scratch:CC 4 ""))]
7284 "TARGET_64BIT && reload_completed
7285 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7286 && !mask_operand (operands[2], DImode)
7287 && !mask64_operand (operands[2], DImode)"
7288 [(set (match_dup 0)
7289 (and:DI (rotate:DI (match_dup 1)
7290 (match_dup 5))
7291 (match_dup 6)))
7292 (parallel [(set (match_dup 3)
7293 (compare:CC (and:DI (rotate:DI (match_dup 0)
7294 (match_dup 7))
7295 (match_dup 8))
7296 (const_int 0)))
7297 (set (match_dup 0)
7298 (and:DI (rotate:DI (match_dup 0)
7299 (match_dup 7))
7300 (match_dup 8)))])]
7301 "
7302 {
7303 build_mask64_2_operands (operands[2], &operands[5]);
7304 }")
7305
7306 (define_expand "iordi3"
7307 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7308 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7309 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7310 "TARGET_POWERPC64"
7311 "
7312 {
7313 if (non_logical_cint_operand (operands[2], DImode))
7314 {
7315 HOST_WIDE_INT value;
7316 rtx tmp = ((!can_create_pseudo_p ()
7317 || rtx_equal_p (operands[0], operands[1]))
7318 ? operands[0] : gen_reg_rtx (DImode));
7319
7320 if (GET_CODE (operands[2]) == CONST_INT)
7321 {
7322 value = INTVAL (operands[2]);
7323 emit_insn (gen_iordi3 (tmp, operands[1],
7324 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7325 }
7326 else
7327 {
7328 value = CONST_DOUBLE_LOW (operands[2]);
7329 emit_insn (gen_iordi3 (tmp, operands[1],
7330 immed_double_const (value
7331 & (~ (HOST_WIDE_INT) 0xffff),
7332 0, DImode)));
7333 }
7334
7335 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7336 DONE;
7337 }
7338 }")
7339
7340 (define_expand "xordi3"
7341 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7342 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7343 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7344 "TARGET_POWERPC64"
7345 "
7346 {
7347 if (non_logical_cint_operand (operands[2], DImode))
7348 {
7349 HOST_WIDE_INT value;
7350 rtx tmp = ((!can_create_pseudo_p ()
7351 || rtx_equal_p (operands[0], operands[1]))
7352 ? operands[0] : gen_reg_rtx (DImode));
7353
7354 if (GET_CODE (operands[2]) == CONST_INT)
7355 {
7356 value = INTVAL (operands[2]);
7357 emit_insn (gen_xordi3 (tmp, operands[1],
7358 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7359 }
7360 else
7361 {
7362 value = CONST_DOUBLE_LOW (operands[2]);
7363 emit_insn (gen_xordi3 (tmp, operands[1],
7364 immed_double_const (value
7365 & (~ (HOST_WIDE_INT) 0xffff),
7366 0, DImode)));
7367 }
7368
7369 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7370 DONE;
7371 }
7372 }")
7373
7374 (define_insn "*booldi3_internal1"
7375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7376 (match_operator:DI 3 "boolean_or_operator"
7377 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7378 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7379 "TARGET_POWERPC64"
7380 "@
7381 %q3 %0,%1,%2
7382 %q3i %0,%1,%b2
7383 %q3is %0,%1,%u2")
7384
7385 (define_insn "*booldi3_internal2"
7386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7387 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7388 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7389 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7390 (const_int 0)))
7391 (clobber (match_scratch:DI 3 "=r,r"))]
7392 "TARGET_64BIT"
7393 "@
7394 %q4. %3,%1,%2
7395 #"
7396 [(set_attr "type" "fast_compare,compare")
7397 (set_attr "length" "4,8")])
7398
7399 (define_split
7400 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7401 (compare:CC (match_operator:DI 4 "boolean_operator"
7402 [(match_operand:DI 1 "gpc_reg_operand" "")
7403 (match_operand:DI 2 "gpc_reg_operand" "")])
7404 (const_int 0)))
7405 (clobber (match_scratch:DI 3 ""))]
7406 "TARGET_POWERPC64 && reload_completed"
7407 [(set (match_dup 3) (match_dup 4))
7408 (set (match_dup 0)
7409 (compare:CC (match_dup 3)
7410 (const_int 0)))]
7411 "")
7412
7413 (define_insn "*booldi3_internal3"
7414 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7415 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7416 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7417 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7418 (const_int 0)))
7419 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7420 (match_dup 4))]
7421 "TARGET_64BIT"
7422 "@
7423 %q4. %0,%1,%2
7424 #"
7425 [(set_attr "type" "fast_compare,compare")
7426 (set_attr "length" "4,8")])
7427
7428 (define_split
7429 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7430 (compare:CC (match_operator:DI 4 "boolean_operator"
7431 [(match_operand:DI 1 "gpc_reg_operand" "")
7432 (match_operand:DI 2 "gpc_reg_operand" "")])
7433 (const_int 0)))
7434 (set (match_operand:DI 0 "gpc_reg_operand" "")
7435 (match_dup 4))]
7436 "TARGET_POWERPC64 && reload_completed"
7437 [(set (match_dup 0) (match_dup 4))
7438 (set (match_dup 3)
7439 (compare:CC (match_dup 0)
7440 (const_int 0)))]
7441 "")
7442
7443 ;; Split a logical operation that we can't do in one insn into two insns,
7444 ;; each of which does one 16-bit part. This is used by combine.
7445
7446 (define_split
7447 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7448 (match_operator:DI 3 "boolean_or_operator"
7449 [(match_operand:DI 1 "gpc_reg_operand" "")
7450 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7451 "TARGET_POWERPC64"
7452 [(set (match_dup 0) (match_dup 4))
7453 (set (match_dup 0) (match_dup 5))]
7454 "
7455 {
7456 rtx i3,i4;
7457
7458 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7459 {
7460 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7461 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7462 0, DImode);
7463 i4 = GEN_INT (value & 0xffff);
7464 }
7465 else
7466 {
7467 i3 = GEN_INT (INTVAL (operands[2])
7468 & (~ (HOST_WIDE_INT) 0xffff));
7469 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7470 }
7471 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7472 operands[1], i3);
7473 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7474 operands[0], i4);
7475 }")
7476
7477 (define_insn "*boolcdi3_internal1"
7478 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7479 (match_operator:DI 3 "boolean_operator"
7480 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7481 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7482 "TARGET_POWERPC64"
7483 "%q3 %0,%2,%1")
7484
7485 (define_insn "*boolcdi3_internal2"
7486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7487 (compare:CC (match_operator:DI 4 "boolean_operator"
7488 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7489 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7490 (const_int 0)))
7491 (clobber (match_scratch:DI 3 "=r,r"))]
7492 "TARGET_64BIT"
7493 "@
7494 %q4. %3,%2,%1
7495 #"
7496 [(set_attr "type" "fast_compare,compare")
7497 (set_attr "length" "4,8")])
7498
7499 (define_split
7500 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7501 (compare:CC (match_operator:DI 4 "boolean_operator"
7502 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7503 (match_operand:DI 2 "gpc_reg_operand" "")])
7504 (const_int 0)))
7505 (clobber (match_scratch:DI 3 ""))]
7506 "TARGET_POWERPC64 && reload_completed"
7507 [(set (match_dup 3) (match_dup 4))
7508 (set (match_dup 0)
7509 (compare:CC (match_dup 3)
7510 (const_int 0)))]
7511 "")
7512
7513 (define_insn "*boolcdi3_internal3"
7514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7515 (compare:CC (match_operator:DI 4 "boolean_operator"
7516 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7517 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7518 (const_int 0)))
7519 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7520 (match_dup 4))]
7521 "TARGET_64BIT"
7522 "@
7523 %q4. %0,%2,%1
7524 #"
7525 [(set_attr "type" "fast_compare,compare")
7526 (set_attr "length" "4,8")])
7527
7528 (define_split
7529 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7530 (compare:CC (match_operator:DI 4 "boolean_operator"
7531 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7532 (match_operand:DI 2 "gpc_reg_operand" "")])
7533 (const_int 0)))
7534 (set (match_operand:DI 0 "gpc_reg_operand" "")
7535 (match_dup 4))]
7536 "TARGET_POWERPC64 && reload_completed"
7537 [(set (match_dup 0) (match_dup 4))
7538 (set (match_dup 3)
7539 (compare:CC (match_dup 0)
7540 (const_int 0)))]
7541 "")
7542
7543 (define_insn "*boolccdi3_internal1"
7544 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7545 (match_operator:DI 3 "boolean_operator"
7546 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7547 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7548 "TARGET_POWERPC64"
7549 "%q3 %0,%1,%2")
7550
7551 (define_insn "*boolccdi3_internal2"
7552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7553 (compare:CC (match_operator:DI 4 "boolean_operator"
7554 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7555 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7556 (const_int 0)))
7557 (clobber (match_scratch:DI 3 "=r,r"))]
7558 "TARGET_64BIT"
7559 "@
7560 %q4. %3,%1,%2
7561 #"
7562 [(set_attr "type" "fast_compare,compare")
7563 (set_attr "length" "4,8")])
7564
7565 (define_split
7566 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7567 (compare:CC (match_operator:DI 4 "boolean_operator"
7568 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7569 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7570 (const_int 0)))
7571 (clobber (match_scratch:DI 3 ""))]
7572 "TARGET_POWERPC64 && reload_completed"
7573 [(set (match_dup 3) (match_dup 4))
7574 (set (match_dup 0)
7575 (compare:CC (match_dup 3)
7576 (const_int 0)))]
7577 "")
7578
7579 (define_insn "*boolccdi3_internal3"
7580 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7581 (compare:CC (match_operator:DI 4 "boolean_operator"
7582 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7583 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7584 (const_int 0)))
7585 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7586 (match_dup 4))]
7587 "TARGET_64BIT"
7588 "@
7589 %q4. %0,%1,%2
7590 #"
7591 [(set_attr "type" "fast_compare,compare")
7592 (set_attr "length" "4,8")])
7593
7594 (define_split
7595 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7596 (compare:CC (match_operator:DI 4 "boolean_operator"
7597 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7598 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7599 (const_int 0)))
7600 (set (match_operand:DI 0 "gpc_reg_operand" "")
7601 (match_dup 4))]
7602 "TARGET_POWERPC64 && reload_completed"
7603 [(set (match_dup 0) (match_dup 4))
7604 (set (match_dup 3)
7605 (compare:CC (match_dup 0)
7606 (const_int 0)))]
7607 "")
7608 \f
7609 ;; Now define ways of moving data around.
7610
7611 ;; Set up a register with a value from the GOT table
7612
7613 (define_expand "movsi_got"
7614 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7615 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7616 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7617 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7618 "
7619 {
7620 if (GET_CODE (operands[1]) == CONST)
7621 {
7622 rtx offset = const0_rtx;
7623 HOST_WIDE_INT value;
7624
7625 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7626 value = INTVAL (offset);
7627 if (value != 0)
7628 {
7629 rtx tmp = (!can_create_pseudo_p ()
7630 ? operands[0]
7631 : gen_reg_rtx (Pmode));
7632 emit_insn (gen_movsi_got (tmp, operands[1]));
7633 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7634 DONE;
7635 }
7636 }
7637
7638 operands[2] = rs6000_got_register (operands[1]);
7639 }")
7640
7641 (define_insn "*movsi_got_internal"
7642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7643 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7644 (match_operand:SI 2 "gpc_reg_operand" "b")]
7645 UNSPEC_MOVSI_GOT))]
7646 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7647 "lwz %0,%a1@got(%2)"
7648 [(set_attr "type" "load")])
7649
7650 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7651 ;; didn't get allocated to a hard register.
7652 (define_split
7653 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7654 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7655 (match_operand:SI 2 "memory_operand" "")]
7656 UNSPEC_MOVSI_GOT))]
7657 "DEFAULT_ABI == ABI_V4
7658 && flag_pic == 1
7659 && (reload_in_progress || reload_completed)"
7660 [(set (match_dup 0) (match_dup 2))
7661 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7662 UNSPEC_MOVSI_GOT))]
7663 "")
7664
7665 ;; For SI, we special-case integers that can't be loaded in one insn. We
7666 ;; do the load 16-bits at a time. We could do this by loading from memory,
7667 ;; and this is even supposed to be faster, but it is simpler not to get
7668 ;; integers in the TOC.
7669 (define_insn "movsi_low"
7670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7671 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7672 (match_operand 2 "" ""))))]
7673 "TARGET_MACHO && ! TARGET_64BIT"
7674 "lwz %0,lo16(%2)(%1)"
7675 [(set_attr "type" "load")
7676 (set_attr "length" "4")])
7677
7678 (define_insn "*movsi_internal1"
7679 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7680 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7681 "!TARGET_SINGLE_FPU &&
7682 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7683 "@
7684 mr %0,%1
7685 la %0,%a1
7686 lwz%U1%X1 %0,%1
7687 stw%U0%X0 %1,%0
7688 li %0,%1
7689 lis %0,%v1
7690 #
7691 mf%1 %0
7692 mt%0 %1
7693 mt%0 %1
7694 nop"
7695 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7696 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7697
7698 (define_insn "*movsi_internal1_single"
7699 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7700 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7701 "TARGET_SINGLE_FPU &&
7702 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7703 "@
7704 mr %0,%1
7705 la %0,%a1
7706 lwz%U1%X1 %0,%1
7707 stw%U0%X0 %1,%0
7708 li %0,%1
7709 lis %0,%v1
7710 #
7711 mf%1 %0
7712 mt%0 %1
7713 mt%0 %1
7714 nop
7715 stfs%U0%X0 %1,%0
7716 lfs%U1%X1 %0,%1"
7717 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
7718 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7719
7720 ;; Split a load of a large constant into the appropriate two-insn
7721 ;; sequence.
7722
7723 (define_split
7724 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7725 (match_operand:SI 1 "const_int_operand" ""))]
7726 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7727 && (INTVAL (operands[1]) & 0xffff) != 0"
7728 [(set (match_dup 0)
7729 (match_dup 2))
7730 (set (match_dup 0)
7731 (ior:SI (match_dup 0)
7732 (match_dup 3)))]
7733 "
7734 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7735
7736 if (tem == operands[0])
7737 DONE;
7738 else
7739 FAIL;
7740 }")
7741
7742 (define_insn "*mov<mode>_internal2"
7743 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7744 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7745 (const_int 0)))
7746 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7747 ""
7748 "@
7749 cmp<wd>i %2,%0,0
7750 mr. %0,%1
7751 #"
7752 [(set_attr "type" "cmp,compare,cmp")
7753 (set_attr "length" "4,4,8")])
7754
7755 (define_split
7756 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7757 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7758 (const_int 0)))
7759 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7760 "reload_completed"
7761 [(set (match_dup 0) (match_dup 1))
7762 (set (match_dup 2)
7763 (compare:CC (match_dup 0)
7764 (const_int 0)))]
7765 "")
7766 \f
7767 (define_insn "*movhi_internal"
7768 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7769 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7770 "gpc_reg_operand (operands[0], HImode)
7771 || gpc_reg_operand (operands[1], HImode)"
7772 "@
7773 mr %0,%1
7774 lhz%U1%X1 %0,%1
7775 sth%U0%X0 %1,%0
7776 li %0,%w1
7777 mf%1 %0
7778 mt%0 %1
7779 nop"
7780 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7781
7782 (define_expand "mov<mode>"
7783 [(set (match_operand:INT 0 "general_operand" "")
7784 (match_operand:INT 1 "any_operand" ""))]
7785 ""
7786 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7787
7788 (define_insn "*movqi_internal"
7789 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7790 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7791 "gpc_reg_operand (operands[0], QImode)
7792 || gpc_reg_operand (operands[1], QImode)"
7793 "@
7794 mr %0,%1
7795 lbz%U1%X1 %0,%1
7796 stb%U0%X0 %1,%0
7797 li %0,%1
7798 mf%1 %0
7799 mt%0 %1
7800 nop"
7801 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7802 \f
7803 ;; Here is how to move condition codes around. When we store CC data in
7804 ;; an integer register or memory, we store just the high-order 4 bits.
7805 ;; This lets us not shift in the most common case of CR0.
7806 (define_expand "movcc"
7807 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7808 (match_operand:CC 1 "nonimmediate_operand" ""))]
7809 ""
7810 "")
7811
7812 (define_insn "*movcc_internal1"
7813 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7814 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7815 "register_operand (operands[0], CCmode)
7816 || register_operand (operands[1], CCmode)"
7817 "@
7818 mcrf %0,%1
7819 mtcrf 128,%1
7820 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7821 crxor %0,%0,%0
7822 mfcr %0%Q1
7823 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7824 mr %0,%1
7825 li %0,%1
7826 mf%1 %0
7827 mt%0 %1
7828 lwz%U1%X1 %0,%1
7829 stw%U0%U1 %1,%0"
7830 [(set (attr "type")
7831 (cond [(eq_attr "alternative" "0,3")
7832 (const_string "cr_logical")
7833 (eq_attr "alternative" "1,2")
7834 (const_string "mtcr")
7835 (eq_attr "alternative" "6,7")
7836 (const_string "integer")
7837 (eq_attr "alternative" "8")
7838 (const_string "mfjmpr")
7839 (eq_attr "alternative" "9")
7840 (const_string "mtjmpr")
7841 (eq_attr "alternative" "10")
7842 (const_string "load")
7843 (eq_attr "alternative" "11")
7844 (const_string "store")
7845 (match_test "TARGET_MFCRF")
7846 (const_string "mfcrf")
7847 ]
7848 (const_string "mfcr")))
7849 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7850 \f
7851 ;; For floating-point, we normally deal with the floating-point registers
7852 ;; unless -msoft-float is used. The sole exception is that parameter passing
7853 ;; can produce floating-point values in fixed-point registers. Unless the
7854 ;; value is a simple constant or already in memory, we deal with this by
7855 ;; allocating memory and copying the value explicitly via that memory location.
7856 (define_expand "movsf"
7857 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7858 (match_operand:SF 1 "any_operand" ""))]
7859 ""
7860 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7861
7862 (define_split
7863 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7864 (match_operand:SF 1 "const_double_operand" ""))]
7865 "reload_completed
7866 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7867 || (GET_CODE (operands[0]) == SUBREG
7868 && GET_CODE (SUBREG_REG (operands[0])) == REG
7869 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7870 [(set (match_dup 2) (match_dup 3))]
7871 "
7872 {
7873 long l;
7874 REAL_VALUE_TYPE rv;
7875
7876 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7877 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7878
7879 if (! TARGET_POWERPC64)
7880 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7881 else
7882 operands[2] = gen_lowpart (SImode, operands[0]);
7883
7884 operands[3] = gen_int_mode (l, SImode);
7885 }")
7886
7887 (define_insn "*movsf_hardfloat"
7888 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")
7889 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]
7890 "(gpc_reg_operand (operands[0], SFmode)
7891 || gpc_reg_operand (operands[1], SFmode))
7892 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7893 "@
7894 mr %0,%1
7895 lwz%U1%X1 %0,%1
7896 stw%U0%X0 %1,%0
7897 fmr %0,%1
7898 lfs%U1%X1 %0,%1
7899 stfs%U0%X0 %1,%0
7900 mt%0 %1
7901 mf%1 %0
7902 nop
7903 #
7904 #"
7905 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")
7906 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7907
7908 (define_insn "*movsf_softfloat"
7909 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7910 (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7911 "(gpc_reg_operand (operands[0], SFmode)
7912 || gpc_reg_operand (operands[1], SFmode))
7913 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7914 "@
7915 mr %0,%1
7916 mt%0 %1
7917 mf%1 %0
7918 lwz%U1%X1 %0,%1
7919 stw%U0%X0 %1,%0
7920 li %0,%1
7921 lis %0,%v1
7922 #
7923 #
7924 nop"
7925 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7926 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7927
7928 \f
7929 (define_expand "movdf"
7930 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7931 (match_operand:DF 1 "any_operand" ""))]
7932 ""
7933 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7934
7935 (define_split
7936 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7937 (match_operand:DF 1 "const_int_operand" ""))]
7938 "! TARGET_POWERPC64 && reload_completed
7939 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7940 || (GET_CODE (operands[0]) == SUBREG
7941 && GET_CODE (SUBREG_REG (operands[0])) == REG
7942 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7943 [(set (match_dup 2) (match_dup 4))
7944 (set (match_dup 3) (match_dup 1))]
7945 "
7946 {
7947 int endian = (WORDS_BIG_ENDIAN == 0);
7948 HOST_WIDE_INT value = INTVAL (operands[1]);
7949
7950 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7951 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7952 #if HOST_BITS_PER_WIDE_INT == 32
7953 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7954 #else
7955 operands[4] = GEN_INT (value >> 32);
7956 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7957 #endif
7958 }")
7959
7960 (define_split
7961 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7962 (match_operand:DF 1 "const_double_operand" ""))]
7963 "! TARGET_POWERPC64 && reload_completed
7964 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7965 || (GET_CODE (operands[0]) == SUBREG
7966 && GET_CODE (SUBREG_REG (operands[0])) == REG
7967 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7968 [(set (match_dup 2) (match_dup 4))
7969 (set (match_dup 3) (match_dup 5))]
7970 "
7971 {
7972 int endian = (WORDS_BIG_ENDIAN == 0);
7973 long l[2];
7974 REAL_VALUE_TYPE rv;
7975
7976 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7977 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7978
7979 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7980 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7981 operands[4] = gen_int_mode (l[endian], SImode);
7982 operands[5] = gen_int_mode (l[1 - endian], SImode);
7983 }")
7984
7985 (define_split
7986 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7987 (match_operand:DF 1 "const_double_operand" ""))]
7988 "TARGET_POWERPC64 && reload_completed
7989 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7990 || (GET_CODE (operands[0]) == SUBREG
7991 && GET_CODE (SUBREG_REG (operands[0])) == REG
7992 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7993 [(set (match_dup 2) (match_dup 3))]
7994 "
7995 {
7996 int endian = (WORDS_BIG_ENDIAN == 0);
7997 long l[2];
7998 REAL_VALUE_TYPE rv;
7999 #if HOST_BITS_PER_WIDE_INT >= 64
8000 HOST_WIDE_INT val;
8001 #endif
8002
8003 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8004 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8005
8006 operands[2] = gen_lowpart (DImode, operands[0]);
8007 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8008 #if HOST_BITS_PER_WIDE_INT >= 64
8009 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8010 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8011
8012 operands[3] = gen_int_mode (val, DImode);
8013 #else
8014 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8015 #endif
8016 }")
8017
8018 ;; Don't have reload use general registers to load a constant. It is
8019 ;; less efficient than loading the constant into an FP register, since
8020 ;; it will probably be used there.
8021 (define_insn "*movdf_hardfloat32"
8022 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,!r,!r,!r")
8023 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
8024 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8025 && (gpc_reg_operand (operands[0], DFmode)
8026 || gpc_reg_operand (operands[1], DFmode))"
8027 "*
8028 {
8029 switch (which_alternative)
8030 {
8031 default:
8032 gcc_unreachable ();
8033 case 0:
8034 case 1:
8035 case 2:
8036 return \"#\";
8037 case 3:
8038 case 4:
8039 return \"xxlor %x0,%x1,%x1\";
8040 case 5:
8041 case 6:
8042 return \"lxsd%U1x %x0,%y1\";
8043 case 7:
8044 case 8:
8045 return \"stxsd%U0x %x1,%y0\";
8046 case 9:
8047 return \"stfd%U0%X0 %1,%0\";
8048 case 10:
8049 return \"lfd%U1%X1 %0,%1\";
8050 case 11:
8051 return \"fmr %0,%1\";
8052 case 12:
8053 return \"xxlxor %x0,%x0,%x0\";
8054 case 13:
8055 case 14:
8056 case 15:
8057 return \"#\";
8058 }
8059 }"
8060 [(set_attr "type" "store,load,two,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,*,*,*")
8061 (set_attr "length" "8,8,8,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8062
8063 (define_insn "*movdf_softfloat32"
8064 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8065 (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
8066 "! TARGET_POWERPC64
8067 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8068 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8069 && (gpc_reg_operand (operands[0], DFmode)
8070 || gpc_reg_operand (operands[1], DFmode))"
8071 "#"
8072 [(set_attr "type" "store,load,two,*,*,*")
8073 (set_attr "length" "8,8,8,8,12,16")])
8074
8075 ;; Reload patterns to support gpr load/store with misaligned mem.
8076 ;; and multiple gpr load/store at offset >= 0xfffc
8077 (define_expand "reload_<mode>_store"
8078 [(parallel [(match_operand 0 "memory_operand" "=m")
8079 (match_operand 1 "gpc_reg_operand" "r")
8080 (match_operand:GPR 2 "register_operand" "=&b")])]
8081 ""
8082 {
8083 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8084 DONE;
8085 })
8086
8087 (define_expand "reload_<mode>_load"
8088 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8089 (match_operand 1 "memory_operand" "m")
8090 (match_operand:GPR 2 "register_operand" "=b")])]
8091 ""
8092 {
8093 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8094 DONE;
8095 })
8096
8097 ; ld/std require word-aligned displacements -> 'Y' constraint.
8098 ; List Y->r and r->Y before r->r for reload.
8099 (define_insn "*movdf_hardfloat64_mfpgpr"
8100 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
8101 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
8102 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8103 && TARGET_DOUBLE_FLOAT
8104 && (gpc_reg_operand (operands[0], DFmode)
8105 || gpc_reg_operand (operands[1], DFmode))"
8106 "@
8107 std%U0%X0 %1,%0
8108 ld%U1%X1 %0,%1
8109 mr %0,%1
8110 xxlor %x0,%x1,%x1
8111 xxlor %x0,%x1,%x1
8112 lxsd%U1x %x0,%y1
8113 lxsd%U1x %x0,%y1
8114 stxsd%U0x %x1,%y0
8115 stxsd%U0x %x1,%y0
8116 stfd%U0%X0 %1,%0
8117 lfd%U1%X1 %0,%1
8118 fmr %0,%1
8119 xxlxor %x0,%x0,%x0
8120 mt%0 %1
8121 mf%1 %0
8122 nop
8123 #
8124 #
8125 #
8126 mftgpr %0,%1
8127 mffgpr %0,%1"
8128 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8129 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8130
8131 ; ld/std require word-aligned displacements -> 'Y' constraint.
8132 ; List Y->r and r->Y before r->r for reload.
8133 (define_insn "*movdf_hardfloat64"
8134 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r")
8135 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
8136 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8137 && TARGET_DOUBLE_FLOAT
8138 && (gpc_reg_operand (operands[0], DFmode)
8139 || gpc_reg_operand (operands[1], DFmode))"
8140 "@
8141 std%U0%X0 %1,%0
8142 ld%U1%X1 %0,%1
8143 mr %0,%1
8144 xxlor %x0,%x1,%x1
8145 xxlor %x0,%x1,%x1
8146 lxsd%U1x %x0,%y1
8147 lxsd%U1x %x0,%y1
8148 stxsd%U0x %x1,%y0
8149 stxsd%U0x %x1,%y0
8150 stfd%U0%X0 %1,%0
8151 lfd%U1%X1 %0,%1
8152 fmr %0,%1
8153 xxlxor %x0,%x0,%x0
8154 mt%0 %1
8155 mf%1 %0
8156 nop
8157 #
8158 #
8159 #"
8160 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
8161 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8162
8163 (define_insn "*movdf_softfloat64"
8164 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8165 (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8166 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8167 && (gpc_reg_operand (operands[0], DFmode)
8168 || gpc_reg_operand (operands[1], DFmode))"
8169 "@
8170 std%U0%X0 %1,%0
8171 ld%U1%X1 %0,%1
8172 mr %0,%1
8173 mt%0 %1
8174 mf%1 %0
8175 #
8176 #
8177 #
8178 nop"
8179 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8180 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8181 \f
8182 (define_expand "movtf"
8183 [(set (match_operand:TF 0 "general_operand" "")
8184 (match_operand:TF 1 "any_operand" ""))]
8185 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8186 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8187
8188 ;; It's important to list Y->r and r->Y before r->r because otherwise
8189 ;; reload, given m->r, will try to pick r->r and reload it, which
8190 ;; doesn't make progress.
8191 (define_insn_and_split "*movtf_internal"
8192 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8193 (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
8194 "!TARGET_IEEEQUAD
8195 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8196 && (gpc_reg_operand (operands[0], TFmode)
8197 || gpc_reg_operand (operands[1], TFmode))"
8198 "#"
8199 "&& reload_completed"
8200 [(pc)]
8201 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8202 [(set_attr "length" "8,8,8,20,20,16")])
8203
8204 (define_insn_and_split "*movtf_softfloat"
8205 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8206 (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
8207 "!TARGET_IEEEQUAD
8208 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8209 && (gpc_reg_operand (operands[0], TFmode)
8210 || gpc_reg_operand (operands[1], TFmode))"
8211 "#"
8212 "&& reload_completed"
8213 [(pc)]
8214 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8215 [(set_attr "length" "20,20,16")])
8216
8217 (define_expand "extenddftf2"
8218 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8219 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8220 "!TARGET_IEEEQUAD
8221 && TARGET_HARD_FLOAT
8222 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8223 && TARGET_LONG_DOUBLE_128"
8224 {
8225 if (TARGET_E500_DOUBLE)
8226 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8227 else
8228 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8229 DONE;
8230 })
8231
8232 (define_expand "extenddftf2_fprs"
8233 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8234 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8235 (use (match_dup 2))])]
8236 "!TARGET_IEEEQUAD
8237 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8238 && TARGET_LONG_DOUBLE_128"
8239 {
8240 operands[2] = CONST0_RTX (DFmode);
8241 /* Generate GOT reference early for SVR4 PIC. */
8242 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8243 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8244 })
8245
8246 (define_insn_and_split "*extenddftf2_internal"
8247 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8248 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8249 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8250 "!TARGET_IEEEQUAD
8251 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8252 && TARGET_LONG_DOUBLE_128"
8253 "#"
8254 "&& reload_completed"
8255 [(pc)]
8256 {
8257 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8258 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8259 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8260 operands[1]);
8261 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8262 operands[2]);
8263 DONE;
8264 })
8265
8266 (define_expand "extendsftf2"
8267 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8268 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8269 "!TARGET_IEEEQUAD
8270 && TARGET_HARD_FLOAT
8271 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8272 && TARGET_LONG_DOUBLE_128"
8273 {
8274 rtx tmp = gen_reg_rtx (DFmode);
8275 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8276 emit_insn (gen_extenddftf2 (operands[0], tmp));
8277 DONE;
8278 })
8279
8280 (define_expand "trunctfdf2"
8281 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8282 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8283 "!TARGET_IEEEQUAD
8284 && TARGET_HARD_FLOAT
8285 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8286 && TARGET_LONG_DOUBLE_128"
8287 "")
8288
8289 (define_insn_and_split "trunctfdf2_internal1"
8290 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8291 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8292 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8293 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8294 "@
8295 #
8296 fmr %0,%1"
8297 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8298 [(const_int 0)]
8299 {
8300 emit_note (NOTE_INSN_DELETED);
8301 DONE;
8302 }
8303 [(set_attr "type" "fp")])
8304
8305 (define_insn "trunctfdf2_internal2"
8306 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8307 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8308 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8309 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8310 && TARGET_LONG_DOUBLE_128"
8311 "fadd %0,%1,%L1"
8312 [(set_attr "type" "fp")
8313 (set_attr "fp_type" "fp_addsub_d")])
8314
8315 (define_expand "trunctfsf2"
8316 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8317 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8318 "!TARGET_IEEEQUAD
8319 && TARGET_HARD_FLOAT
8320 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8321 && TARGET_LONG_DOUBLE_128"
8322 {
8323 if (TARGET_E500_DOUBLE)
8324 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8325 else
8326 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8327 DONE;
8328 })
8329
8330 (define_insn_and_split "trunctfsf2_fprs"
8331 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8332 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8333 (clobber (match_scratch:DF 2 "=d"))]
8334 "!TARGET_IEEEQUAD
8335 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8336 && TARGET_LONG_DOUBLE_128"
8337 "#"
8338 "&& reload_completed"
8339 [(set (match_dup 2)
8340 (float_truncate:DF (match_dup 1)))
8341 (set (match_dup 0)
8342 (float_truncate:SF (match_dup 2)))]
8343 "")
8344
8345 (define_expand "floatsitf2"
8346 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8347 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8348 "!TARGET_IEEEQUAD
8349 && TARGET_HARD_FLOAT
8350 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8351 && TARGET_LONG_DOUBLE_128"
8352 {
8353 rtx tmp = gen_reg_rtx (DFmode);
8354 expand_float (tmp, operands[1], false);
8355 emit_insn (gen_extenddftf2 (operands[0], tmp));
8356 DONE;
8357 })
8358
8359 ; fadd, but rounding towards zero.
8360 ; This is probably not the optimal code sequence.
8361 (define_insn "fix_trunc_helper"
8362 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8363 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8364 UNSPEC_FIX_TRUNC_TF))
8365 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8366 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8367 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8368 [(set_attr "type" "fp")
8369 (set_attr "length" "20")])
8370
8371 (define_expand "fix_trunctfsi2"
8372 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8373 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8374 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8375 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8376 {
8377 if (TARGET_E500_DOUBLE)
8378 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8379 else
8380 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8381 DONE;
8382 })
8383
8384 (define_expand "fix_trunctfsi2_fprs"
8385 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8386 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8387 (clobber (match_dup 2))
8388 (clobber (match_dup 3))
8389 (clobber (match_dup 4))
8390 (clobber (match_dup 5))])]
8391 "!TARGET_IEEEQUAD
8392 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8393 {
8394 operands[2] = gen_reg_rtx (DFmode);
8395 operands[3] = gen_reg_rtx (DFmode);
8396 operands[4] = gen_reg_rtx (DImode);
8397 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8398 })
8399
8400 (define_insn_and_split "*fix_trunctfsi2_internal"
8401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8402 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8403 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8404 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8405 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8406 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8407 "!TARGET_IEEEQUAD
8408 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8409 "#"
8410 ""
8411 [(pc)]
8412 {
8413 rtx lowword;
8414 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8415
8416 gcc_assert (MEM_P (operands[5]));
8417 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8418
8419 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8420 emit_move_insn (operands[5], operands[4]);
8421 emit_move_insn (operands[0], lowword);
8422 DONE;
8423 })
8424
8425 (define_expand "negtf2"
8426 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8427 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8428 "!TARGET_IEEEQUAD
8429 && TARGET_HARD_FLOAT
8430 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8431 && TARGET_LONG_DOUBLE_128"
8432 "")
8433
8434 (define_insn "negtf2_internal"
8435 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8436 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8437 "!TARGET_IEEEQUAD
8438 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8439 "*
8440 {
8441 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8442 return \"fneg %L0,%L1\;fneg %0,%1\";
8443 else
8444 return \"fneg %0,%1\;fneg %L0,%L1\";
8445 }"
8446 [(set_attr "type" "fp")
8447 (set_attr "length" "8")])
8448
8449 (define_expand "abstf2"
8450 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8451 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8452 "!TARGET_IEEEQUAD
8453 && TARGET_HARD_FLOAT
8454 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8455 && TARGET_LONG_DOUBLE_128"
8456 "
8457 {
8458 rtx label = gen_label_rtx ();
8459 if (TARGET_E500_DOUBLE)
8460 {
8461 if (flag_finite_math_only && !flag_trapping_math)
8462 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8463 else
8464 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8465 }
8466 else
8467 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8468 emit_label (label);
8469 DONE;
8470 }")
8471
8472 (define_expand "abstf2_internal"
8473 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8474 (match_operand:TF 1 "gpc_reg_operand" ""))
8475 (set (match_dup 3) (match_dup 5))
8476 (set (match_dup 5) (abs:DF (match_dup 5)))
8477 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8478 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8479 (label_ref (match_operand 2 "" ""))
8480 (pc)))
8481 (set (match_dup 6) (neg:DF (match_dup 6)))]
8482 "!TARGET_IEEEQUAD
8483 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8484 && TARGET_LONG_DOUBLE_128"
8485 "
8486 {
8487 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8488 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8489 operands[3] = gen_reg_rtx (DFmode);
8490 operands[4] = gen_reg_rtx (CCFPmode);
8491 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8492 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8493 }")
8494 \f
8495 ;; Next come the multi-word integer load and store and the load and store
8496 ;; multiple insns.
8497
8498 ;; List r->r after r->Y, otherwise reload will try to reload a
8499 ;; non-offsettable address by using r->r which won't make progress.
8500 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8501 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8502 (define_insn "*movdi_internal32"
8503 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
8504 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
8505 "! TARGET_POWERPC64
8506 && (gpc_reg_operand (operands[0], DImode)
8507 || gpc_reg_operand (operands[1], DImode))"
8508 "@
8509 #
8510 #
8511 #
8512 stfd%U0%X0 %1,%0
8513 lfd%U1%X1 %0,%1
8514 fmr %0,%1
8515 #
8516 xxlxor %x0,%x0,%x0"
8517 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
8518
8519 (define_split
8520 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8521 (match_operand:DI 1 "const_int_operand" ""))]
8522 "! TARGET_POWERPC64 && reload_completed
8523 && gpr_or_gpr_p (operands[0], operands[1])"
8524 [(set (match_dup 2) (match_dup 4))
8525 (set (match_dup 3) (match_dup 1))]
8526 "
8527 {
8528 HOST_WIDE_INT value = INTVAL (operands[1]);
8529 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8530 DImode);
8531 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8532 DImode);
8533 #if HOST_BITS_PER_WIDE_INT == 32
8534 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8535 #else
8536 operands[4] = GEN_INT (value >> 32);
8537 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8538 #endif
8539 }")
8540
8541 (define_split
8542 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8543 (match_operand:DIFD 1 "input_operand" ""))]
8544 "reload_completed && !TARGET_POWERPC64
8545 && gpr_or_gpr_p (operands[0], operands[1])"
8546 [(pc)]
8547 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8548
8549 (define_insn "*movdi_mfpgpr"
8550 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
8551 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
8552 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8553 && (gpc_reg_operand (operands[0], DImode)
8554 || gpc_reg_operand (operands[1], DImode))"
8555 "@
8556 std%U0%X0 %1,%0
8557 ld%U1%X1 %0,%1
8558 mr %0,%1
8559 li %0,%1
8560 lis %0,%v1
8561 #
8562 stfd%U0%X0 %1,%0
8563 lfd%U1%X1 %0,%1
8564 fmr %0,%1
8565 mf%1 %0
8566 mt%0 %1
8567 nop
8568 mftgpr %0,%1
8569 mffgpr %0,%1"
8570 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8571 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
8572
8573 (define_insn "*movdi_internal64"
8574 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
8575 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
8576 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8577 && (gpc_reg_operand (operands[0], DImode)
8578 || gpc_reg_operand (operands[1], DImode))"
8579 "@
8580 std%U0%X0 %1,%0
8581 ld%U1%X1 %0,%1
8582 mr %0,%1
8583 li %0,%1
8584 lis %0,%v1
8585 #
8586 stfd%U0%X0 %1,%0
8587 lfd%U1%X1 %0,%1
8588 fmr %0,%1
8589 mf%1 %0
8590 mt%0 %1
8591 nop
8592 xxlxor %x0,%x0,%x0"
8593 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
8594 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8595
8596 ;; immediate value valid for a single instruction hiding in a const_double
8597 (define_insn ""
8598 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8599 (match_operand:DI 1 "const_double_operand" "F"))]
8600 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8601 && GET_CODE (operands[1]) == CONST_DOUBLE
8602 && num_insns_constant (operands[1], DImode) == 1"
8603 "*
8604 {
8605 return ((unsigned HOST_WIDE_INT)
8606 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8607 ? \"li %0,%1\" : \"lis %0,%v1\";
8608 }")
8609
8610 ;; Generate all one-bits and clear left or right.
8611 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8612 (define_split
8613 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8614 (match_operand:DI 1 "mask64_operand" ""))]
8615 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8616 [(set (match_dup 0) (const_int -1))
8617 (set (match_dup 0)
8618 (and:DI (rotate:DI (match_dup 0)
8619 (const_int 0))
8620 (match_dup 1)))]
8621 "")
8622
8623 ;; Split a load of a large constant into the appropriate five-instruction
8624 ;; sequence. Handle anything in a constant number of insns.
8625 ;; When non-easy constants can go in the TOC, this should use
8626 ;; easy_fp_constant predicate.
8627 (define_split
8628 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8629 (match_operand:DI 1 "const_int_operand" ""))]
8630 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8631 [(set (match_dup 0) (match_dup 2))
8632 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8633 "
8634 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8635
8636 if (tem == operands[0])
8637 DONE;
8638 else
8639 FAIL;
8640 }")
8641
8642 (define_split
8643 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8644 (match_operand:DI 1 "const_double_operand" ""))]
8645 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8646 [(set (match_dup 0) (match_dup 2))
8647 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8648 "
8649 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8650
8651 if (tem == operands[0])
8652 DONE;
8653 else
8654 FAIL;
8655 }")
8656 \f
8657 ;; TImode is similar, except that we usually want to compute the address into
8658 ;; a register and use lsi/stsi (the exception is during reload).
8659
8660 (define_insn "*movti_string"
8661 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8662 (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
8663 "! TARGET_POWERPC64
8664 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8665 "*
8666 {
8667 switch (which_alternative)
8668 {
8669 default:
8670 gcc_unreachable ();
8671 case 0:
8672 if (TARGET_STRING)
8673 return \"stswi %1,%P0,16\";
8674 case 1:
8675 return \"#\";
8676 case 2:
8677 /* If the address is not used in the output, we can use lsi. Otherwise,
8678 fall through to generating four loads. */
8679 if (TARGET_STRING
8680 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8681 return \"lswi %0,%P1,16\";
8682 /* ... fall through ... */
8683 case 3:
8684 case 4:
8685 case 5:
8686 return \"#\";
8687 }
8688 }"
8689 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
8690 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8691 (const_string "always")
8692 (const_string "conditional")))])
8693
8694 (define_insn "*movti_ppc64"
8695 [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
8696 (match_operand:TI 1 "input_operand" "r,Y,r"))]
8697 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8698 || gpc_reg_operand (operands[1], TImode)))
8699 && VECTOR_MEM_NONE_P (TImode)"
8700 "#"
8701 [(set_attr "type" "store,load,*")])
8702
8703 (define_split
8704 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8705 (match_operand:TI 1 "const_double_operand" ""))]
8706 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
8707 [(set (match_dup 2) (match_dup 4))
8708 (set (match_dup 3) (match_dup 5))]
8709 "
8710 {
8711 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8712 TImode);
8713 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8714 TImode);
8715 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8716 {
8717 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8718 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8719 }
8720 else if (GET_CODE (operands[1]) == CONST_INT)
8721 {
8722 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8723 operands[5] = operands[1];
8724 }
8725 else
8726 FAIL;
8727 }")
8728
8729 (define_split
8730 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8731 (match_operand:TI 1 "input_operand" ""))]
8732 "reload_completed && VECTOR_MEM_NONE_P (TImode)
8733 && gpr_or_gpr_p (operands[0], operands[1])"
8734 [(pc)]
8735 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8736 \f
8737 (define_expand "load_multiple"
8738 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8739 (match_operand:SI 1 "" ""))
8740 (use (match_operand:SI 2 "" ""))])]
8741 "TARGET_STRING && !TARGET_POWERPC64"
8742 "
8743 {
8744 int regno;
8745 int count;
8746 rtx op1;
8747 int i;
8748
8749 /* Support only loading a constant number of fixed-point registers from
8750 memory and only bother with this if more than two; the machine
8751 doesn't support more than eight. */
8752 if (GET_CODE (operands[2]) != CONST_INT
8753 || INTVAL (operands[2]) <= 2
8754 || INTVAL (operands[2]) > 8
8755 || GET_CODE (operands[1]) != MEM
8756 || GET_CODE (operands[0]) != REG
8757 || REGNO (operands[0]) >= 32)
8758 FAIL;
8759
8760 count = INTVAL (operands[2]);
8761 regno = REGNO (operands[0]);
8762
8763 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8764 op1 = replace_equiv_address (operands[1],
8765 force_reg (SImode, XEXP (operands[1], 0)));
8766
8767 for (i = 0; i < count; i++)
8768 XVECEXP (operands[3], 0, i)
8769 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8770 adjust_address_nv (op1, SImode, i * 4));
8771 }")
8772
8773 (define_insn "*ldmsi8"
8774 [(match_parallel 0 "load_multiple_operation"
8775 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8776 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8777 (set (match_operand:SI 3 "gpc_reg_operand" "")
8778 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8779 (set (match_operand:SI 4 "gpc_reg_operand" "")
8780 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8781 (set (match_operand:SI 5 "gpc_reg_operand" "")
8782 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8783 (set (match_operand:SI 6 "gpc_reg_operand" "")
8784 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8785 (set (match_operand:SI 7 "gpc_reg_operand" "")
8786 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8787 (set (match_operand:SI 8 "gpc_reg_operand" "")
8788 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8789 (set (match_operand:SI 9 "gpc_reg_operand" "")
8790 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8791 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8792 "*
8793 { return rs6000_output_load_multiple (operands); }"
8794 [(set_attr "type" "load_ux")
8795 (set_attr "length" "32")])
8796
8797 (define_insn "*ldmsi7"
8798 [(match_parallel 0 "load_multiple_operation"
8799 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8800 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8801 (set (match_operand:SI 3 "gpc_reg_operand" "")
8802 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8803 (set (match_operand:SI 4 "gpc_reg_operand" "")
8804 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8805 (set (match_operand:SI 5 "gpc_reg_operand" "")
8806 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8807 (set (match_operand:SI 6 "gpc_reg_operand" "")
8808 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8809 (set (match_operand:SI 7 "gpc_reg_operand" "")
8810 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8811 (set (match_operand:SI 8 "gpc_reg_operand" "")
8812 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8813 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8814 "*
8815 { return rs6000_output_load_multiple (operands); }"
8816 [(set_attr "type" "load_ux")
8817 (set_attr "length" "32")])
8818
8819 (define_insn "*ldmsi6"
8820 [(match_parallel 0 "load_multiple_operation"
8821 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8822 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8823 (set (match_operand:SI 3 "gpc_reg_operand" "")
8824 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8825 (set (match_operand:SI 4 "gpc_reg_operand" "")
8826 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8827 (set (match_operand:SI 5 "gpc_reg_operand" "")
8828 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8829 (set (match_operand:SI 6 "gpc_reg_operand" "")
8830 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8831 (set (match_operand:SI 7 "gpc_reg_operand" "")
8832 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8833 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8834 "*
8835 { return rs6000_output_load_multiple (operands); }"
8836 [(set_attr "type" "load_ux")
8837 (set_attr "length" "32")])
8838
8839 (define_insn "*ldmsi5"
8840 [(match_parallel 0 "load_multiple_operation"
8841 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8842 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8843 (set (match_operand:SI 3 "gpc_reg_operand" "")
8844 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8845 (set (match_operand:SI 4 "gpc_reg_operand" "")
8846 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8847 (set (match_operand:SI 5 "gpc_reg_operand" "")
8848 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8849 (set (match_operand:SI 6 "gpc_reg_operand" "")
8850 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8851 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8852 "*
8853 { return rs6000_output_load_multiple (operands); }"
8854 [(set_attr "type" "load_ux")
8855 (set_attr "length" "32")])
8856
8857 (define_insn "*ldmsi4"
8858 [(match_parallel 0 "load_multiple_operation"
8859 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8860 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8861 (set (match_operand:SI 3 "gpc_reg_operand" "")
8862 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8863 (set (match_operand:SI 4 "gpc_reg_operand" "")
8864 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8865 (set (match_operand:SI 5 "gpc_reg_operand" "")
8866 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8867 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8868 "*
8869 { return rs6000_output_load_multiple (operands); }"
8870 [(set_attr "type" "load_ux")
8871 (set_attr "length" "32")])
8872
8873 (define_insn "*ldmsi3"
8874 [(match_parallel 0 "load_multiple_operation"
8875 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8876 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8877 (set (match_operand:SI 3 "gpc_reg_operand" "")
8878 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8879 (set (match_operand:SI 4 "gpc_reg_operand" "")
8880 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8881 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8882 "*
8883 { return rs6000_output_load_multiple (operands); }"
8884 [(set_attr "type" "load_ux")
8885 (set_attr "length" "32")])
8886
8887 (define_expand "store_multiple"
8888 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8889 (match_operand:SI 1 "" ""))
8890 (clobber (scratch:SI))
8891 (use (match_operand:SI 2 "" ""))])]
8892 "TARGET_STRING && !TARGET_POWERPC64"
8893 "
8894 {
8895 int regno;
8896 int count;
8897 rtx to;
8898 rtx op0;
8899 int i;
8900
8901 /* Support only storing a constant number of fixed-point registers to
8902 memory and only bother with this if more than two; the machine
8903 doesn't support more than eight. */
8904 if (GET_CODE (operands[2]) != CONST_INT
8905 || INTVAL (operands[2]) <= 2
8906 || INTVAL (operands[2]) > 8
8907 || GET_CODE (operands[0]) != MEM
8908 || GET_CODE (operands[1]) != REG
8909 || REGNO (operands[1]) >= 32)
8910 FAIL;
8911
8912 count = INTVAL (operands[2]);
8913 regno = REGNO (operands[1]);
8914
8915 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8916 to = force_reg (SImode, XEXP (operands[0], 0));
8917 op0 = replace_equiv_address (operands[0], to);
8918
8919 XVECEXP (operands[3], 0, 0)
8920 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8921 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8922 gen_rtx_SCRATCH (SImode));
8923
8924 for (i = 1; i < count; i++)
8925 XVECEXP (operands[3], 0, i + 1)
8926 = gen_rtx_SET (VOIDmode,
8927 adjust_address_nv (op0, SImode, i * 4),
8928 gen_rtx_REG (SImode, regno + i));
8929 }")
8930
8931 (define_insn "*stmsi8"
8932 [(match_parallel 0 "store_multiple_operation"
8933 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8934 (match_operand:SI 2 "gpc_reg_operand" "r"))
8935 (clobber (match_scratch:SI 3 "=X"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8937 (match_operand:SI 4 "gpc_reg_operand" "r"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8939 (match_operand:SI 5 "gpc_reg_operand" "r"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8941 (match_operand:SI 6 "gpc_reg_operand" "r"))
8942 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8943 (match_operand:SI 7 "gpc_reg_operand" "r"))
8944 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8945 (match_operand:SI 8 "gpc_reg_operand" "r"))
8946 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8947 (match_operand:SI 9 "gpc_reg_operand" "r"))
8948 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8949 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8950 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
8951 "stswi %2,%1,%O0"
8952 [(set_attr "type" "store_ux")
8953 (set_attr "cell_micro" "always")])
8954
8955 (define_insn "*stmsi7"
8956 [(match_parallel 0 "store_multiple_operation"
8957 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8958 (match_operand:SI 2 "gpc_reg_operand" "r"))
8959 (clobber (match_scratch:SI 3 "=X"))
8960 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8961 (match_operand:SI 4 "gpc_reg_operand" "r"))
8962 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8963 (match_operand:SI 5 "gpc_reg_operand" "r"))
8964 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8965 (match_operand:SI 6 "gpc_reg_operand" "r"))
8966 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8967 (match_operand:SI 7 "gpc_reg_operand" "r"))
8968 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8969 (match_operand:SI 8 "gpc_reg_operand" "r"))
8970 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8971 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8972 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8973 "stswi %2,%1,%O0"
8974 [(set_attr "type" "store_ux")
8975 (set_attr "cell_micro" "always")])
8976
8977 (define_insn "*stmsi6"
8978 [(match_parallel 0 "store_multiple_operation"
8979 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8980 (match_operand:SI 2 "gpc_reg_operand" "r"))
8981 (clobber (match_scratch:SI 3 "=X"))
8982 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8983 (match_operand:SI 4 "gpc_reg_operand" "r"))
8984 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8985 (match_operand:SI 5 "gpc_reg_operand" "r"))
8986 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8987 (match_operand:SI 6 "gpc_reg_operand" "r"))
8988 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8989 (match_operand:SI 7 "gpc_reg_operand" "r"))
8990 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8991 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8992 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8993 "stswi %2,%1,%O0"
8994 [(set_attr "type" "store_ux")
8995 (set_attr "cell_micro" "always")])
8996
8997 (define_insn "*stmsi5"
8998 [(match_parallel 0 "store_multiple_operation"
8999 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9000 (match_operand:SI 2 "gpc_reg_operand" "r"))
9001 (clobber (match_scratch:SI 3 "=X"))
9002 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9003 (match_operand:SI 4 "gpc_reg_operand" "r"))
9004 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9005 (match_operand:SI 5 "gpc_reg_operand" "r"))
9006 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9007 (match_operand:SI 6 "gpc_reg_operand" "r"))
9008 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9009 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9010 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9011 "stswi %2,%1,%O0"
9012 [(set_attr "type" "store_ux")
9013 (set_attr "cell_micro" "always")])
9014
9015 (define_insn "*stmsi4"
9016 [(match_parallel 0 "store_multiple_operation"
9017 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9018 (match_operand:SI 2 "gpc_reg_operand" "r"))
9019 (clobber (match_scratch:SI 3 "=X"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9021 (match_operand:SI 4 "gpc_reg_operand" "r"))
9022 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9023 (match_operand:SI 5 "gpc_reg_operand" "r"))
9024 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9025 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9026 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9027 "stswi %2,%1,%O0"
9028 [(set_attr "type" "store_ux")
9029 (set_attr "cell_micro" "always")])
9030
9031 (define_insn "*stmsi3"
9032 [(match_parallel 0 "store_multiple_operation"
9033 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9034 (match_operand:SI 2 "gpc_reg_operand" "r"))
9035 (clobber (match_scratch:SI 3 "=X"))
9036 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9037 (match_operand:SI 4 "gpc_reg_operand" "r"))
9038 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9039 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9040 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9041 "stswi %2,%1,%O0"
9042 [(set_attr "type" "store_ux")
9043 (set_attr "cell_micro" "always")])
9044 \f
9045 (define_expand "setmemsi"
9046 [(parallel [(set (match_operand:BLK 0 "" "")
9047 (match_operand 2 "const_int_operand" ""))
9048 (use (match_operand:SI 1 "" ""))
9049 (use (match_operand:SI 3 "" ""))])]
9050 ""
9051 "
9052 {
9053 /* If value to set is not zero, use the library routine. */
9054 if (operands[2] != const0_rtx)
9055 FAIL;
9056
9057 if (expand_block_clear (operands))
9058 DONE;
9059 else
9060 FAIL;
9061 }")
9062
9063 ;; String/block move insn.
9064 ;; Argument 0 is the destination
9065 ;; Argument 1 is the source
9066 ;; Argument 2 is the length
9067 ;; Argument 3 is the alignment
9068
9069 (define_expand "movmemsi"
9070 [(parallel [(set (match_operand:BLK 0 "" "")
9071 (match_operand:BLK 1 "" ""))
9072 (use (match_operand:SI 2 "" ""))
9073 (use (match_operand:SI 3 "" ""))])]
9074 ""
9075 "
9076 {
9077 if (expand_block_move (operands))
9078 DONE;
9079 else
9080 FAIL;
9081 }")
9082
9083 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9084 ;; register allocator doesn't have a clue about allocating 8 word registers.
9085 ;; rD/rS = r5 is preferred, efficient form.
9086 (define_expand "movmemsi_8reg"
9087 [(parallel [(set (match_operand 0 "" "")
9088 (match_operand 1 "" ""))
9089 (use (match_operand 2 "" ""))
9090 (use (match_operand 3 "" ""))
9091 (clobber (reg:SI 5))
9092 (clobber (reg:SI 6))
9093 (clobber (reg:SI 7))
9094 (clobber (reg:SI 8))
9095 (clobber (reg:SI 9))
9096 (clobber (reg:SI 10))
9097 (clobber (reg:SI 11))
9098 (clobber (reg:SI 12))
9099 (clobber (match_scratch:SI 4 ""))])]
9100 "TARGET_STRING"
9101 "")
9102
9103 (define_insn ""
9104 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9105 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9106 (use (match_operand:SI 2 "immediate_operand" "i"))
9107 (use (match_operand:SI 3 "immediate_operand" "i"))
9108 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9109 (clobber (reg:SI 6))
9110 (clobber (reg:SI 7))
9111 (clobber (reg:SI 8))
9112 (clobber (reg:SI 9))
9113 (clobber (reg:SI 10))
9114 (clobber (reg:SI 11))
9115 (clobber (reg:SI 12))
9116 (clobber (match_scratch:SI 5 "=X"))]
9117 "TARGET_STRING
9118 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9119 || INTVAL (operands[2]) == 0)
9120 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9121 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9122 && REGNO (operands[4]) == 5"
9123 "lswi %4,%1,%2\;stswi %4,%0,%2"
9124 [(set_attr "type" "store_ux")
9125 (set_attr "cell_micro" "always")
9126 (set_attr "length" "8")])
9127
9128 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9129 ;; register allocator doesn't have a clue about allocating 6 word registers.
9130 ;; rD/rS = r5 is preferred, efficient form.
9131 (define_expand "movmemsi_6reg"
9132 [(parallel [(set (match_operand 0 "" "")
9133 (match_operand 1 "" ""))
9134 (use (match_operand 2 "" ""))
9135 (use (match_operand 3 "" ""))
9136 (clobber (reg:SI 5))
9137 (clobber (reg:SI 6))
9138 (clobber (reg:SI 7))
9139 (clobber (reg:SI 8))
9140 (clobber (reg:SI 9))
9141 (clobber (reg:SI 10))
9142 (clobber (match_scratch:SI 4 ""))])]
9143 "TARGET_STRING"
9144 "")
9145
9146 (define_insn ""
9147 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9148 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9149 (use (match_operand:SI 2 "immediate_operand" "i"))
9150 (use (match_operand:SI 3 "immediate_operand" "i"))
9151 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9152 (clobber (reg:SI 6))
9153 (clobber (reg:SI 7))
9154 (clobber (reg:SI 8))
9155 (clobber (reg:SI 9))
9156 (clobber (reg:SI 10))
9157 (clobber (match_scratch:SI 5 "=X"))]
9158 "TARGET_STRING
9159 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9160 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9161 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9162 && REGNO (operands[4]) == 5"
9163 "lswi %4,%1,%2\;stswi %4,%0,%2"
9164 [(set_attr "type" "store_ux")
9165 (set_attr "cell_micro" "always")
9166 (set_attr "length" "8")])
9167
9168 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9169 ;; problems with TImode.
9170 ;; rD/rS = r5 is preferred, efficient form.
9171 (define_expand "movmemsi_4reg"
9172 [(parallel [(set (match_operand 0 "" "")
9173 (match_operand 1 "" ""))
9174 (use (match_operand 2 "" ""))
9175 (use (match_operand 3 "" ""))
9176 (clobber (reg:SI 5))
9177 (clobber (reg:SI 6))
9178 (clobber (reg:SI 7))
9179 (clobber (reg:SI 8))
9180 (clobber (match_scratch:SI 4 ""))])]
9181 "TARGET_STRING"
9182 "")
9183
9184 (define_insn ""
9185 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9186 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9187 (use (match_operand:SI 2 "immediate_operand" "i"))
9188 (use (match_operand:SI 3 "immediate_operand" "i"))
9189 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9190 (clobber (reg:SI 6))
9191 (clobber (reg:SI 7))
9192 (clobber (reg:SI 8))
9193 (clobber (match_scratch:SI 5 "=X"))]
9194 "TARGET_STRING
9195 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9196 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9197 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9198 && REGNO (operands[4]) == 5"
9199 "lswi %4,%1,%2\;stswi %4,%0,%2"
9200 [(set_attr "type" "store_ux")
9201 (set_attr "cell_micro" "always")
9202 (set_attr "length" "8")])
9203
9204 ;; Move up to 8 bytes at a time.
9205 (define_expand "movmemsi_2reg"
9206 [(parallel [(set (match_operand 0 "" "")
9207 (match_operand 1 "" ""))
9208 (use (match_operand 2 "" ""))
9209 (use (match_operand 3 "" ""))
9210 (clobber (match_scratch:DI 4 ""))
9211 (clobber (match_scratch:SI 5 ""))])]
9212 "TARGET_STRING && ! TARGET_POWERPC64"
9213 "")
9214
9215 (define_insn ""
9216 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9217 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9218 (use (match_operand:SI 2 "immediate_operand" "i"))
9219 (use (match_operand:SI 3 "immediate_operand" "i"))
9220 (clobber (match_scratch:DI 4 "=&r"))
9221 (clobber (match_scratch:SI 5 "=X"))]
9222 "TARGET_STRING && ! TARGET_POWERPC64
9223 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9224 "lswi %4,%1,%2\;stswi %4,%0,%2"
9225 [(set_attr "type" "store_ux")
9226 (set_attr "cell_micro" "always")
9227 (set_attr "length" "8")])
9228
9229 ;; Move up to 4 bytes at a time.
9230 (define_expand "movmemsi_1reg"
9231 [(parallel [(set (match_operand 0 "" "")
9232 (match_operand 1 "" ""))
9233 (use (match_operand 2 "" ""))
9234 (use (match_operand 3 "" ""))
9235 (clobber (match_scratch:SI 4 ""))
9236 (clobber (match_scratch:SI 5 ""))])]
9237 "TARGET_STRING"
9238 "")
9239
9240 (define_insn ""
9241 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9242 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9243 (use (match_operand:SI 2 "immediate_operand" "i"))
9244 (use (match_operand:SI 3 "immediate_operand" "i"))
9245 (clobber (match_scratch:SI 4 "=&r"))
9246 (clobber (match_scratch:SI 5 "=X"))]
9247 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9248 "lswi %4,%1,%2\;stswi %4,%0,%2"
9249 [(set_attr "type" "store_ux")
9250 (set_attr "cell_micro" "always")
9251 (set_attr "length" "8")])
9252 \f
9253 ;; Define insns that do load or store with update. Some of these we can
9254 ;; get by using pre-decrement or pre-increment, but the hardware can also
9255 ;; do cases where the increment is not the size of the object.
9256 ;;
9257 ;; In all these cases, we use operands 0 and 1 for the register being
9258 ;; incremented because those are the operands that local-alloc will
9259 ;; tie and these are the pair most likely to be tieable (and the ones
9260 ;; that will benefit the most).
9261
9262 (define_insn "*movdi_update1"
9263 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9264 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9265 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9266 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9267 (plus:DI (match_dup 1) (match_dup 2)))]
9268 "TARGET_POWERPC64 && TARGET_UPDATE
9269 && (!avoiding_indexed_address_p (DImode)
9270 || !gpc_reg_operand (operands[2], DImode))"
9271 "@
9272 ldux %3,%0,%2
9273 ldu %3,%2(%0)"
9274 [(set_attr "type" "load_ux,load_u")])
9275
9276 (define_insn "movdi_<mode>_update"
9277 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9278 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9279 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9280 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9281 (plus:P (match_dup 1) (match_dup 2)))]
9282 "TARGET_POWERPC64 && TARGET_UPDATE
9283 && (!avoiding_indexed_address_p (Pmode)
9284 || !gpc_reg_operand (operands[2], Pmode)
9285 || (REG_P (operands[0])
9286 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9287 "@
9288 stdux %3,%0,%2
9289 stdu %3,%2(%0)"
9290 [(set_attr "type" "store_ux,store_u")])
9291
9292 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9293 ;; needed for stack allocation, even if the user passes -mno-update.
9294 (define_insn "movdi_<mode>_update_stack"
9295 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9296 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9297 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9298 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9299 (plus:P (match_dup 1) (match_dup 2)))]
9300 "TARGET_POWERPC64"
9301 "@
9302 stdux %3,%0,%2
9303 stdu %3,%2(%0)"
9304 [(set_attr "type" "store_ux,store_u")])
9305
9306 (define_insn "*movsi_update1"
9307 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9308 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9309 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9310 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9311 (plus:SI (match_dup 1) (match_dup 2)))]
9312 "TARGET_UPDATE
9313 && (!avoiding_indexed_address_p (SImode)
9314 || !gpc_reg_operand (operands[2], SImode))"
9315 "@
9316 lwzux %3,%0,%2
9317 lwzu %3,%2(%0)"
9318 [(set_attr "type" "load_ux,load_u")])
9319
9320 (define_insn "*movsi_update2"
9321 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9322 (sign_extend:DI
9323 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9324 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9325 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9326 (plus:DI (match_dup 1) (match_dup 2)))]
9327 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9328 && !avoiding_indexed_address_p (DImode)"
9329 "lwaux %3,%0,%2"
9330 [(set_attr "type" "load_ext_ux")])
9331
9332 (define_insn "movsi_update"
9333 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9334 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9335 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9336 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9337 (plus:SI (match_dup 1) (match_dup 2)))]
9338 "TARGET_UPDATE
9339 && (!avoiding_indexed_address_p (SImode)
9340 || !gpc_reg_operand (operands[2], SImode)
9341 || (REG_P (operands[0])
9342 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9343 "@
9344 stwux %3,%0,%2
9345 stwu %3,%2(%0)"
9346 [(set_attr "type" "store_ux,store_u")])
9347
9348 ;; This is an unconditional pattern; needed for stack allocation, even
9349 ;; if the user passes -mno-update.
9350 (define_insn "movsi_update_stack"
9351 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9352 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9353 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9354 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9355 (plus:SI (match_dup 1) (match_dup 2)))]
9356 ""
9357 "@
9358 stwux %3,%0,%2
9359 stwu %3,%2(%0)"
9360 [(set_attr "type" "store_ux,store_u")])
9361
9362 (define_insn "*movhi_update1"
9363 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9364 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9365 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9366 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9367 (plus:SI (match_dup 1) (match_dup 2)))]
9368 "TARGET_UPDATE
9369 && (!avoiding_indexed_address_p (SImode)
9370 || !gpc_reg_operand (operands[2], SImode))"
9371 "@
9372 lhzux %3,%0,%2
9373 lhzu %3,%2(%0)"
9374 [(set_attr "type" "load_ux,load_u")])
9375
9376 (define_insn "*movhi_update2"
9377 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9378 (zero_extend:SI
9379 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9380 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9381 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9382 (plus:SI (match_dup 1) (match_dup 2)))]
9383 "TARGET_UPDATE
9384 && (!avoiding_indexed_address_p (SImode)
9385 || !gpc_reg_operand (operands[2], SImode))"
9386 "@
9387 lhzux %3,%0,%2
9388 lhzu %3,%2(%0)"
9389 [(set_attr "type" "load_ux,load_u")])
9390
9391 (define_insn "*movhi_update3"
9392 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9393 (sign_extend:SI
9394 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9395 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9396 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9397 (plus:SI (match_dup 1) (match_dup 2)))]
9398 "TARGET_UPDATE && rs6000_gen_cell_microcode
9399 && (!avoiding_indexed_address_p (SImode)
9400 || !gpc_reg_operand (operands[2], SImode))"
9401 "@
9402 lhaux %3,%0,%2
9403 lhau %3,%2(%0)"
9404 [(set_attr "type" "load_ext_ux,load_ext_u")])
9405
9406 (define_insn "*movhi_update4"
9407 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9408 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9409 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9410 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9411 (plus:SI (match_dup 1) (match_dup 2)))]
9412 "TARGET_UPDATE
9413 && (!avoiding_indexed_address_p (SImode)
9414 || !gpc_reg_operand (operands[2], SImode))"
9415 "@
9416 sthux %3,%0,%2
9417 sthu %3,%2(%0)"
9418 [(set_attr "type" "store_ux,store_u")])
9419
9420 (define_insn "*movqi_update1"
9421 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9422 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9423 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9424 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9425 (plus:SI (match_dup 1) (match_dup 2)))]
9426 "TARGET_UPDATE
9427 && (!avoiding_indexed_address_p (SImode)
9428 || !gpc_reg_operand (operands[2], SImode))"
9429 "@
9430 lbzux %3,%0,%2
9431 lbzu %3,%2(%0)"
9432 [(set_attr "type" "load_ux,load_u")])
9433
9434 (define_insn "*movqi_update2"
9435 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9436 (zero_extend:SI
9437 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9438 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9439 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9440 (plus:SI (match_dup 1) (match_dup 2)))]
9441 "TARGET_UPDATE
9442 && (!avoiding_indexed_address_p (SImode)
9443 || !gpc_reg_operand (operands[2], SImode))"
9444 "@
9445 lbzux %3,%0,%2
9446 lbzu %3,%2(%0)"
9447 [(set_attr "type" "load_ux,load_u")])
9448
9449 (define_insn "*movqi_update3"
9450 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9451 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9452 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9453 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9454 (plus:SI (match_dup 1) (match_dup 2)))]
9455 "TARGET_UPDATE
9456 && (!avoiding_indexed_address_p (SImode)
9457 || !gpc_reg_operand (operands[2], SImode))"
9458 "@
9459 stbux %3,%0,%2
9460 stbu %3,%2(%0)"
9461 [(set_attr "type" "store_ux,store_u")])
9462
9463 (define_insn "*movsf_update1"
9464 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9465 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9466 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9467 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9468 (plus:SI (match_dup 1) (match_dup 2)))]
9469 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9470 && (!avoiding_indexed_address_p (SImode)
9471 || !gpc_reg_operand (operands[2], SImode))"
9472 "@
9473 lfsux %3,%0,%2
9474 lfsu %3,%2(%0)"
9475 [(set_attr "type" "fpload_ux,fpload_u")])
9476
9477 (define_insn "*movsf_update2"
9478 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9479 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9480 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9481 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9482 (plus:SI (match_dup 1) (match_dup 2)))]
9483 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9484 && (!avoiding_indexed_address_p (SImode)
9485 || !gpc_reg_operand (operands[2], SImode))"
9486 "@
9487 stfsux %3,%0,%2
9488 stfsu %3,%2(%0)"
9489 [(set_attr "type" "fpstore_ux,fpstore_u")])
9490
9491 (define_insn "*movsf_update3"
9492 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9493 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9494 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9495 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9496 (plus:SI (match_dup 1) (match_dup 2)))]
9497 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9498 && (!avoiding_indexed_address_p (SImode)
9499 || !gpc_reg_operand (operands[2], SImode))"
9500 "@
9501 lwzux %3,%0,%2
9502 lwzu %3,%2(%0)"
9503 [(set_attr "type" "load_ux,load_u")])
9504
9505 (define_insn "*movsf_update4"
9506 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9507 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9508 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9509 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9510 (plus:SI (match_dup 1) (match_dup 2)))]
9511 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9512 && (!avoiding_indexed_address_p (SImode)
9513 || !gpc_reg_operand (operands[2], SImode))"
9514 "@
9515 stwux %3,%0,%2
9516 stwu %3,%2(%0)"
9517 [(set_attr "type" "store_ux,store_u")])
9518
9519 (define_insn "*movdf_update1"
9520 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9521 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9522 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9523 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9524 (plus:SI (match_dup 1) (match_dup 2)))]
9525 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9526 && (!avoiding_indexed_address_p (SImode)
9527 || !gpc_reg_operand (operands[2], SImode))"
9528 "@
9529 lfdux %3,%0,%2
9530 lfdu %3,%2(%0)"
9531 [(set_attr "type" "fpload_ux,fpload_u")])
9532
9533 (define_insn "*movdf_update2"
9534 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9535 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9536 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9537 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9538 (plus:SI (match_dup 1) (match_dup 2)))]
9539 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9540 && (!avoiding_indexed_address_p (SImode)
9541 || !gpc_reg_operand (operands[2], SImode))"
9542 "@
9543 stfdux %3,%0,%2
9544 stfdu %3,%2(%0)"
9545 [(set_attr "type" "fpstore_ux,fpstore_u")])
9546
9547
9548 ;; After inserting conditional returns we can sometimes have
9549 ;; unnecessary register moves. Unfortunately we cannot have a
9550 ;; modeless peephole here, because some single SImode sets have early
9551 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9552 ;; sequences, using get_attr_length here will smash the operands
9553 ;; array. Neither is there an early_cobbler_p predicate.
9554 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9555 (define_peephole2
9556 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9557 (match_operand:DF 1 "any_operand" ""))
9558 (set (match_operand:DF 2 "gpc_reg_operand" "")
9559 (match_dup 0))]
9560 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9561 && peep2_reg_dead_p (2, operands[0])"
9562 [(set (match_dup 2) (match_dup 1))])
9563
9564 (define_peephole2
9565 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9566 (match_operand:SF 1 "any_operand" ""))
9567 (set (match_operand:SF 2 "gpc_reg_operand" "")
9568 (match_dup 0))]
9569 "peep2_reg_dead_p (2, operands[0])"
9570 [(set (match_dup 2) (match_dup 1))])
9571
9572 \f
9573 ;; TLS support.
9574
9575 ;; Mode attributes for different ABIs.
9576 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9577 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9578 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9579 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9580
9581 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9582 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9583 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9584 (match_operand 4 "" "g")))
9585 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9586 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9587 UNSPEC_TLSGD)
9588 (clobber (reg:SI LR_REGNO))]
9589 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9590 {
9591 if (TARGET_CMODEL != CMODEL_SMALL)
9592 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9593 "bl %z3\;nop";
9594 else
9595 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9596 }
9597 "&& TARGET_TLS_MARKERS"
9598 [(set (match_dup 0)
9599 (unspec:TLSmode [(match_dup 1)
9600 (match_dup 2)]
9601 UNSPEC_TLSGD))
9602 (parallel [(set (match_dup 0)
9603 (call (mem:TLSmode (match_dup 3))
9604 (match_dup 4)))
9605 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9606 (clobber (reg:SI LR_REGNO))])]
9607 ""
9608 [(set_attr "type" "two")
9609 (set (attr "length")
9610 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9611 (const_int 16)
9612 (const_int 12)))])
9613
9614 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9615 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9616 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9617 (match_operand 4 "" "g")))
9618 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9619 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9620 UNSPEC_TLSGD)
9621 (clobber (reg:SI LR_REGNO))]
9622 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9623 {
9624 if (flag_pic)
9625 {
9626 if (TARGET_SECURE_PLT && flag_pic == 2)
9627 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9628 else
9629 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9630 }
9631 else
9632 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9633 }
9634 "&& TARGET_TLS_MARKERS"
9635 [(set (match_dup 0)
9636 (unspec:TLSmode [(match_dup 1)
9637 (match_dup 2)]
9638 UNSPEC_TLSGD))
9639 (parallel [(set (match_dup 0)
9640 (call (mem:TLSmode (match_dup 3))
9641 (match_dup 4)))
9642 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9643 (clobber (reg:SI LR_REGNO))])]
9644 ""
9645 [(set_attr "type" "two")
9646 (set_attr "length" "8")])
9647
9648 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9649 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9650 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9651 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9652 UNSPEC_TLSGD))]
9653 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9654 "addi %0,%1,%2@got@tlsgd"
9655 "&& TARGET_CMODEL != CMODEL_SMALL"
9656 [(set (match_dup 3)
9657 (high:TLSmode
9658 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9659 (set (match_dup 0)
9660 (lo_sum:TLSmode (match_dup 3)
9661 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
9662 "
9663 {
9664 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9665 }"
9666 [(set (attr "length")
9667 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9668 (const_int 8)
9669 (const_int 4)))])
9670
9671 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9672 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9673 (high:TLSmode
9674 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9675 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9676 UNSPEC_TLSGD)))]
9677 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9678 "addis %0,%1,%2@got@tlsgd@ha"
9679 [(set_attr "length" "4")])
9680
9681 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9682 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9683 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9684 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9685 UNSPEC_TLSGD)))]
9686 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9687 "addi %0,%1,%2@got@tlsgd@l"
9688 [(set_attr "length" "4")])
9689
9690 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9691 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9692 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9693 (match_operand 2 "" "g")))
9694 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9695 UNSPEC_TLSGD)
9696 (clobber (reg:SI LR_REGNO))]
9697 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9698 "bl %z1(%3@tlsgd)\;nop"
9699 [(set_attr "type" "branch")
9700 (set_attr "length" "8")])
9701
9702 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9703 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9704 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9705 (match_operand 2 "" "g")))
9706 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9707 UNSPEC_TLSGD)
9708 (clobber (reg:SI LR_REGNO))]
9709 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9710 {
9711 if (flag_pic)
9712 {
9713 if (TARGET_SECURE_PLT && flag_pic == 2)
9714 return "bl %z1+32768(%3@tlsgd)@plt";
9715 return "bl %z1(%3@tlsgd)@plt";
9716 }
9717 return "bl %z1(%3@tlsgd)";
9718 }
9719 [(set_attr "type" "branch")
9720 (set_attr "length" "4")])
9721
9722 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9723 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9724 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9725 (match_operand 3 "" "g")))
9726 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9727 UNSPEC_TLSLD)
9728 (clobber (reg:SI LR_REGNO))]
9729 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9730 {
9731 if (TARGET_CMODEL != CMODEL_SMALL)
9732 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9733 "bl %z2\;nop";
9734 else
9735 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9736 }
9737 "&& TARGET_TLS_MARKERS"
9738 [(set (match_dup 0)
9739 (unspec:TLSmode [(match_dup 1)]
9740 UNSPEC_TLSLD))
9741 (parallel [(set (match_dup 0)
9742 (call (mem:TLSmode (match_dup 2))
9743 (match_dup 3)))
9744 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9745 (clobber (reg:SI LR_REGNO))])]
9746 ""
9747 [(set_attr "type" "two")
9748 (set (attr "length")
9749 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9750 (const_int 16)
9751 (const_int 12)))])
9752
9753 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
9754 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9755 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9756 (match_operand 3 "" "g")))
9757 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9758 UNSPEC_TLSLD)
9759 (clobber (reg:SI LR_REGNO))]
9760 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9761 {
9762 if (flag_pic)
9763 {
9764 if (TARGET_SECURE_PLT && flag_pic == 2)
9765 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
9766 else
9767 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
9768 }
9769 else
9770 return "addi %0,%1,%&@got@tlsld\;bl %z2";
9771 }
9772 "&& TARGET_TLS_MARKERS"
9773 [(set (match_dup 0)
9774 (unspec:TLSmode [(match_dup 1)]
9775 UNSPEC_TLSLD))
9776 (parallel [(set (match_dup 0)
9777 (call (mem:TLSmode (match_dup 2))
9778 (match_dup 3)))
9779 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9780 (clobber (reg:SI LR_REGNO))])]
9781 ""
9782 [(set_attr "length" "8")])
9783
9784 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
9785 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9786 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9787 UNSPEC_TLSLD))]
9788 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9789 "addi %0,%1,%&@got@tlsld"
9790 "&& TARGET_CMODEL != CMODEL_SMALL"
9791 [(set (match_dup 2)
9792 (high:TLSmode
9793 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
9794 (set (match_dup 0)
9795 (lo_sum:TLSmode (match_dup 2)
9796 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9797 "
9798 {
9799 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9800 }"
9801 [(set (attr "length")
9802 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9803 (const_int 8)
9804 (const_int 4)))])
9805
9806 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
9807 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9808 (high:TLSmode
9809 (unspec:TLSmode [(const_int 0)
9810 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9811 UNSPEC_TLSLD)))]
9812 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9813 "addis %0,%1,%&@got@tlsld@ha"
9814 [(set_attr "length" "4")])
9815
9816 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
9817 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9818 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9819 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9820 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9821 "addi %0,%1,%&@got@tlsld@l"
9822 [(set_attr "length" "4")])
9823
9824 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
9825 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9826 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9827 (match_operand 2 "" "g")))
9828 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9829 (clobber (reg:SI LR_REGNO))]
9830 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9831 "bl %z1(%&@tlsld)\;nop"
9832 [(set_attr "type" "branch")
9833 (set_attr "length" "8")])
9834
9835 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
9836 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9837 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9838 (match_operand 2 "" "g")))
9839 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9840 (clobber (reg:SI LR_REGNO))]
9841 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9842 {
9843 if (flag_pic)
9844 {
9845 if (TARGET_SECURE_PLT && flag_pic == 2)
9846 return "bl %z1+32768(%&@tlsld)@plt";
9847 return "bl %z1(%&@tlsld)@plt";
9848 }
9849 return "bl %z1(%&@tlsld)";
9850 }
9851 [(set_attr "type" "branch")
9852 (set_attr "length" "4")])
9853
9854 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
9855 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9856 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9857 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9858 UNSPEC_TLSDTPREL))]
9859 "HAVE_AS_TLS"
9860 "addi %0,%1,%2@dtprel")
9861
9862 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
9863 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9864 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9865 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9866 UNSPEC_TLSDTPRELHA))]
9867 "HAVE_AS_TLS"
9868 "addis %0,%1,%2@dtprel@ha")
9869
9870 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
9871 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9872 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9873 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9874 UNSPEC_TLSDTPRELLO))]
9875 "HAVE_AS_TLS"
9876 "addi %0,%1,%2@dtprel@l")
9877
9878 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
9879 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9880 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9881 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9882 UNSPEC_TLSGOTDTPREL))]
9883 "HAVE_AS_TLS"
9884 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
9885 "&& TARGET_CMODEL != CMODEL_SMALL"
9886 [(set (match_dup 3)
9887 (high:TLSmode
9888 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
9889 (set (match_dup 0)
9890 (lo_sum:TLSmode (match_dup 3)
9891 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
9892 "
9893 {
9894 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9895 }"
9896 [(set (attr "length")
9897 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9898 (const_int 8)
9899 (const_int 4)))])
9900
9901 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
9902 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9903 (high:TLSmode
9904 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9905 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9906 UNSPEC_TLSGOTDTPREL)))]
9907 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9908 "addis %0,%1,%2@got@dtprel@ha"
9909 [(set_attr "length" "4")])
9910
9911 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
9912 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9913 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9914 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9915 UNSPEC_TLSGOTDTPREL)))]
9916 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9917 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
9918 [(set_attr "length" "4")])
9919
9920 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
9921 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9922 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9923 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9924 UNSPEC_TLSTPREL))]
9925 "HAVE_AS_TLS"
9926 "addi %0,%1,%2@tprel")
9927
9928 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
9929 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9930 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9931 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9932 UNSPEC_TLSTPRELHA))]
9933 "HAVE_AS_TLS"
9934 "addis %0,%1,%2@tprel@ha")
9935
9936 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
9937 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9938 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9939 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9940 UNSPEC_TLSTPRELLO))]
9941 "HAVE_AS_TLS"
9942 "addi %0,%1,%2@tprel@l")
9943
9944 ;; "b" output constraint here and on tls_tls input to support linker tls
9945 ;; optimization. The linker may edit the instructions emitted by a
9946 ;; tls_got_tprel/tls_tls pair to addis,addi.
9947 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
9948 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9949 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9950 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9951 UNSPEC_TLSGOTTPREL))]
9952 "HAVE_AS_TLS"
9953 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
9954 "&& TARGET_CMODEL != CMODEL_SMALL"
9955 [(set (match_dup 3)
9956 (high:TLSmode
9957 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
9958 (set (match_dup 0)
9959 (lo_sum:TLSmode (match_dup 3)
9960 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
9961 "
9962 {
9963 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9964 }"
9965 [(set (attr "length")
9966 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9967 (const_int 8)
9968 (const_int 4)))])
9969
9970 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
9971 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9972 (high:TLSmode
9973 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9974 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9975 UNSPEC_TLSGOTTPREL)))]
9976 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9977 "addis %0,%1,%2@got@tprel@ha"
9978 [(set_attr "length" "4")])
9979
9980 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
9981 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9982 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9983 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9984 UNSPEC_TLSGOTTPREL)))]
9985 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9986 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
9987 [(set_attr "length" "4")])
9988
9989 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
9990 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9991 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9992 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9993 UNSPEC_TLSTLS))]
9994 "HAVE_AS_TLS"
9995 "add %0,%1,%2@tls")
9996 \f
9997 ;; Next come insns related to the calling sequence.
9998 ;;
9999 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10000 ;; We move the back-chain and decrement the stack pointer.
10001
10002 (define_expand "allocate_stack"
10003 [(set (match_operand 0 "gpc_reg_operand" "")
10004 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10005 (set (reg 1)
10006 (minus (reg 1) (match_dup 1)))]
10007 ""
10008 "
10009 { rtx chain = gen_reg_rtx (Pmode);
10010 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10011 rtx neg_op0;
10012 rtx insn, par, set, mem;
10013
10014 emit_move_insn (chain, stack_bot);
10015
10016 /* Check stack bounds if necessary. */
10017 if (crtl->limit_stack)
10018 {
10019 rtx available;
10020 available = expand_binop (Pmode, sub_optab,
10021 stack_pointer_rtx, stack_limit_rtx,
10022 NULL_RTX, 1, OPTAB_WIDEN);
10023 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10024 }
10025
10026 if (GET_CODE (operands[1]) != CONST_INT
10027 || INTVAL (operands[1]) < -32767
10028 || INTVAL (operands[1]) > 32768)
10029 {
10030 neg_op0 = gen_reg_rtx (Pmode);
10031 if (TARGET_32BIT)
10032 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10033 else
10034 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10035 }
10036 else
10037 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10038
10039 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10040 : gen_movdi_di_update_stack))
10041 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10042 chain));
10043 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10044 it now and set the alias set/attributes. The above gen_*_update
10045 calls will generate a PARALLEL with the MEM set being the first
10046 operation. */
10047 par = PATTERN (insn);
10048 gcc_assert (GET_CODE (par) == PARALLEL);
10049 set = XVECEXP (par, 0, 0);
10050 gcc_assert (GET_CODE (set) == SET);
10051 mem = SET_DEST (set);
10052 gcc_assert (MEM_P (mem));
10053 MEM_NOTRAP_P (mem) = 1;
10054 set_mem_alias_set (mem, get_frame_alias_set ());
10055
10056 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10057 DONE;
10058 }")
10059
10060 ;; These patterns say how to save and restore the stack pointer. We need not
10061 ;; save the stack pointer at function level since we are careful to
10062 ;; preserve the backchain. At block level, we have to restore the backchain
10063 ;; when we restore the stack pointer.
10064 ;;
10065 ;; For nonlocal gotos, we must save both the stack pointer and its
10066 ;; backchain and restore both. Note that in the nonlocal case, the
10067 ;; save area is a memory location.
10068
10069 (define_expand "save_stack_function"
10070 [(match_operand 0 "any_operand" "")
10071 (match_operand 1 "any_operand" "")]
10072 ""
10073 "DONE;")
10074
10075 (define_expand "restore_stack_function"
10076 [(match_operand 0 "any_operand" "")
10077 (match_operand 1 "any_operand" "")]
10078 ""
10079 "DONE;")
10080
10081 ;; Adjust stack pointer (op0) to a new value (op1).
10082 ;; First copy old stack backchain to new location, and ensure that the
10083 ;; scheduler won't reorder the sp assignment before the backchain write.
10084 (define_expand "restore_stack_block"
10085 [(set (match_dup 2) (match_dup 3))
10086 (set (match_dup 4) (match_dup 2))
10087 (match_dup 5)
10088 (set (match_operand 0 "register_operand" "")
10089 (match_operand 1 "register_operand" ""))]
10090 ""
10091 "
10092 {
10093 rtvec p;
10094
10095 operands[1] = force_reg (Pmode, operands[1]);
10096 operands[2] = gen_reg_rtx (Pmode);
10097 operands[3] = gen_frame_mem (Pmode, operands[0]);
10098 operands[4] = gen_frame_mem (Pmode, operands[1]);
10099 p = rtvec_alloc (1);
10100 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10101 gen_frame_mem (BLKmode, operands[0]),
10102 const0_rtx);
10103 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10104 }")
10105
10106 (define_expand "save_stack_nonlocal"
10107 [(set (match_dup 3) (match_dup 4))
10108 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10109 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10110 ""
10111 "
10112 {
10113 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10114
10115 /* Copy the backchain to the first word, sp to the second. */
10116 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10117 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10118 operands[3] = gen_reg_rtx (Pmode);
10119 operands[4] = gen_frame_mem (Pmode, operands[1]);
10120 }")
10121
10122 (define_expand "restore_stack_nonlocal"
10123 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10124 (set (match_dup 3) (match_dup 4))
10125 (set (match_dup 5) (match_dup 2))
10126 (match_dup 6)
10127 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10128 ""
10129 "
10130 {
10131 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10132 rtvec p;
10133
10134 /* Restore the backchain from the first word, sp from the second. */
10135 operands[2] = gen_reg_rtx (Pmode);
10136 operands[3] = gen_reg_rtx (Pmode);
10137 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10138 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10139 operands[5] = gen_frame_mem (Pmode, operands[3]);
10140 p = rtvec_alloc (1);
10141 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10142 gen_frame_mem (BLKmode, operands[0]),
10143 const0_rtx);
10144 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10145 }")
10146 \f
10147 ;; TOC register handling.
10148
10149 ;; Code to initialize the TOC register...
10150
10151 (define_insn "load_toc_aix_si"
10152 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10153 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10154 (use (reg:SI 2))])]
10155 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10156 "*
10157 {
10158 char buf[30];
10159 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10160 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10161 operands[2] = gen_rtx_REG (Pmode, 2);
10162 return \"lwz %0,%1(%2)\";
10163 }"
10164 [(set_attr "type" "load")])
10165
10166 (define_insn "load_toc_aix_di"
10167 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10168 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10169 (use (reg:DI 2))])]
10170 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10171 "*
10172 {
10173 char buf[30];
10174 #ifdef TARGET_RELOCATABLE
10175 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10176 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10177 #else
10178 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10179 #endif
10180 if (TARGET_ELF)
10181 strcat (buf, \"@toc\");
10182 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10183 operands[2] = gen_rtx_REG (Pmode, 2);
10184 return \"ld %0,%1(%2)\";
10185 }"
10186 [(set_attr "type" "load")])
10187
10188 (define_insn "load_toc_v4_pic_si"
10189 [(set (reg:SI LR_REGNO)
10190 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10191 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10192 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10193 [(set_attr "type" "branch")
10194 (set_attr "length" "4")])
10195
10196 (define_expand "load_toc_v4_PIC_1"
10197 [(parallel [(set (reg:SI LR_REGNO)
10198 (match_operand:SI 0 "immediate_operand" "s"))
10199 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10200 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10201 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10202 "")
10203
10204 (define_insn "load_toc_v4_PIC_1_normal"
10205 [(set (reg:SI LR_REGNO)
10206 (match_operand:SI 0 "immediate_operand" "s"))
10207 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10208 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10209 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10210 "bcl 20,31,%0\\n%0:"
10211 [(set_attr "type" "branch")
10212 (set_attr "length" "4")])
10213
10214 (define_insn "load_toc_v4_PIC_1_476"
10215 [(set (reg:SI LR_REGNO)
10216 (match_operand:SI 0 "immediate_operand" "s"))
10217 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10218 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10219 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10220 "*
10221 {
10222 char name[32];
10223 static char templ[32];
10224
10225 get_ppc476_thunk_name (name);
10226 sprintf (templ, \"bl %s\\n%%0:\", name);
10227 return templ;
10228 }"
10229 [(set_attr "type" "branch")
10230 (set_attr "length" "4")])
10231
10232 (define_expand "load_toc_v4_PIC_1b"
10233 [(parallel [(set (reg:SI LR_REGNO)
10234 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10235 (label_ref (match_operand 1 "" ""))]
10236 UNSPEC_TOCPTR))
10237 (match_dup 1)])]
10238 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10239 "")
10240
10241 (define_insn "load_toc_v4_PIC_1b_normal"
10242 [(set (reg:SI LR_REGNO)
10243 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10244 (label_ref (match_operand 1 "" ""))]
10245 UNSPEC_TOCPTR))
10246 (match_dup 1)]
10247 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10248 "bcl 20,31,$+8\;.long %0-$"
10249 [(set_attr "type" "branch")
10250 (set_attr "length" "8")])
10251
10252 (define_insn "load_toc_v4_PIC_1b_476"
10253 [(set (reg:SI LR_REGNO)
10254 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10255 (label_ref (match_operand 1 "" ""))]
10256 UNSPEC_TOCPTR))
10257 (match_dup 1)]
10258 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10259 "*
10260 {
10261 char name[32];
10262 static char templ[32];
10263
10264 get_ppc476_thunk_name (name);
10265 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10266 return templ;
10267 }"
10268 [(set_attr "type" "branch")
10269 (set_attr "length" "16")])
10270
10271 (define_insn "load_toc_v4_PIC_2"
10272 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10273 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10274 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10275 (match_operand:SI 3 "immediate_operand" "s")))))]
10276 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10277 "lwz %0,%2-%3(%1)"
10278 [(set_attr "type" "load")])
10279
10280 (define_insn "load_toc_v4_PIC_3b"
10281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10282 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10283 (high:SI
10284 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10285 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10286 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10287 "addis %0,%1,%2-%3@ha")
10288
10289 (define_insn "load_toc_v4_PIC_3c"
10290 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10291 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10292 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10293 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10294 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10295 "addi %0,%1,%2-%3@l")
10296
10297 ;; If the TOC is shared over a translation unit, as happens with all
10298 ;; the kinds of PIC that we support, we need to restore the TOC
10299 ;; pointer only when jumping over units of translation.
10300 ;; On Darwin, we need to reload the picbase.
10301
10302 (define_expand "builtin_setjmp_receiver"
10303 [(use (label_ref (match_operand 0 "" "")))]
10304 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10305 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10306 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10307 "
10308 {
10309 #if TARGET_MACHO
10310 if (DEFAULT_ABI == ABI_DARWIN)
10311 {
10312 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10313 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10314 rtx tmplabrtx;
10315 char tmplab[20];
10316
10317 crtl->uses_pic_offset_table = 1;
10318 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10319 CODE_LABEL_NUMBER (operands[0]));
10320 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10321
10322 emit_insn (gen_load_macho_picbase (tmplabrtx));
10323 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10324 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10325 }
10326 else
10327 #endif
10328 rs6000_emit_load_toc_table (FALSE);
10329 DONE;
10330 }")
10331
10332 ;; Largetoc support
10333 (define_insn "*largetoc_high"
10334 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10335 (high:DI
10336 (unspec [(match_operand:DI 1 "" "")
10337 (match_operand:DI 2 "gpc_reg_operand" "b")]
10338 UNSPEC_TOCREL)))]
10339 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10340 "addis %0,%2,%1@toc@ha")
10341
10342 (define_insn "*largetoc_high_plus"
10343 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10344 (high:DI
10345 (plus:DI
10346 (unspec [(match_operand:DI 1 "" "")
10347 (match_operand:DI 2 "gpc_reg_operand" "b")]
10348 UNSPEC_TOCREL)
10349 (match_operand 3 "const_int_operand" "n"))))]
10350 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10351 "addis %0,%2,%1+%3@toc@ha")
10352
10353 (define_insn "*largetoc_low"
10354 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10355 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10356 (match_operand:DI 2 "" "")))]
10357 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10358 "@
10359 addi %0,%1,%2@l
10360 addic %0,%1,%2@l")
10361
10362 (define_insn_and_split "*tocref<mode>"
10363 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10364 (match_operand:P 1 "small_toc_ref" "R"))]
10365 "TARGET_TOC"
10366 "la %0,%a1"
10367 "&& TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10368 [(set (match_dup 0) (high:P (match_dup 1)))
10369 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10370
10371 ;; Elf specific ways of loading addresses for non-PIC code.
10372 ;; The output of this could be r0, but we make a very strong
10373 ;; preference for a base register because it will usually
10374 ;; be needed there.
10375 (define_insn "elf_high"
10376 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10377 (high:SI (match_operand 1 "" "")))]
10378 "TARGET_ELF && ! TARGET_64BIT"
10379 "lis %0,%1@ha")
10380
10381 (define_insn "elf_low"
10382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10383 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10384 (match_operand 2 "" "")))]
10385 "TARGET_ELF && ! TARGET_64BIT"
10386 "@
10387 la %0,%2@l(%1)
10388 addic %0,%1,%K2")
10389 \f
10390 ;; Call and call_value insns
10391 (define_expand "call"
10392 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10393 (match_operand 1 "" ""))
10394 (use (match_operand 2 "" ""))
10395 (clobber (reg:SI LR_REGNO))])]
10396 ""
10397 "
10398 {
10399 #if TARGET_MACHO
10400 if (MACHOPIC_INDIRECT)
10401 operands[0] = machopic_indirect_call_target (operands[0]);
10402 #endif
10403
10404 gcc_assert (GET_CODE (operands[0]) == MEM);
10405 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10406
10407 operands[0] = XEXP (operands[0], 0);
10408
10409 if (GET_CODE (operands[0]) != SYMBOL_REF
10410 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10411 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10412 {
10413 if (INTVAL (operands[2]) & CALL_LONG)
10414 operands[0] = rs6000_longcall_ref (operands[0]);
10415
10416 switch (DEFAULT_ABI)
10417 {
10418 case ABI_V4:
10419 case ABI_DARWIN:
10420 operands[0] = force_reg (Pmode, operands[0]);
10421 break;
10422
10423 case ABI_AIX:
10424 /* AIX function pointers are really pointers to a three word
10425 area. */
10426 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
10427 DONE;
10428
10429 default:
10430 gcc_unreachable ();
10431 }
10432 }
10433 }")
10434
10435 (define_expand "call_value"
10436 [(parallel [(set (match_operand 0 "" "")
10437 (call (mem:SI (match_operand 1 "address_operand" ""))
10438 (match_operand 2 "" "")))
10439 (use (match_operand 3 "" ""))
10440 (clobber (reg:SI LR_REGNO))])]
10441 ""
10442 "
10443 {
10444 #if TARGET_MACHO
10445 if (MACHOPIC_INDIRECT)
10446 operands[1] = machopic_indirect_call_target (operands[1]);
10447 #endif
10448
10449 gcc_assert (GET_CODE (operands[1]) == MEM);
10450 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10451
10452 operands[1] = XEXP (operands[1], 0);
10453
10454 if (GET_CODE (operands[1]) != SYMBOL_REF
10455 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10456 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10457 {
10458 if (INTVAL (operands[3]) & CALL_LONG)
10459 operands[1] = rs6000_longcall_ref (operands[1]);
10460
10461 switch (DEFAULT_ABI)
10462 {
10463 case ABI_V4:
10464 case ABI_DARWIN:
10465 operands[1] = force_reg (Pmode, operands[1]);
10466 break;
10467
10468 case ABI_AIX:
10469 /* AIX function pointers are really pointers to a three word
10470 area. */
10471 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
10472 DONE;
10473
10474 default:
10475 gcc_unreachable ();
10476 }
10477 }
10478 }")
10479
10480 ;; Call to function in current module. No TOC pointer reload needed.
10481 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10482 ;; either the function was not prototyped, or it was prototyped as a
10483 ;; variable argument function. It is > 0 if FP registers were passed
10484 ;; and < 0 if they were not.
10485
10486 (define_insn "*call_local32"
10487 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10488 (match_operand 1 "" "g,g"))
10489 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10490 (clobber (reg:SI LR_REGNO))]
10491 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10492 "*
10493 {
10494 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10495 output_asm_insn (\"crxor 6,6,6\", operands);
10496
10497 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10498 output_asm_insn (\"creqv 6,6,6\", operands);
10499
10500 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10501 }"
10502 [(set_attr "type" "branch")
10503 (set_attr "length" "4,8")])
10504
10505 (define_insn "*call_local64"
10506 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10507 (match_operand 1 "" "g,g"))
10508 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10509 (clobber (reg:SI LR_REGNO))]
10510 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10511 "*
10512 {
10513 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10514 output_asm_insn (\"crxor 6,6,6\", operands);
10515
10516 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10517 output_asm_insn (\"creqv 6,6,6\", operands);
10518
10519 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10520 }"
10521 [(set_attr "type" "branch")
10522 (set_attr "length" "4,8")])
10523
10524 (define_insn "*call_value_local32"
10525 [(set (match_operand 0 "" "")
10526 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10527 (match_operand 2 "" "g,g")))
10528 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10529 (clobber (reg:SI LR_REGNO))]
10530 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10531 "*
10532 {
10533 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10534 output_asm_insn (\"crxor 6,6,6\", operands);
10535
10536 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10537 output_asm_insn (\"creqv 6,6,6\", operands);
10538
10539 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10540 }"
10541 [(set_attr "type" "branch")
10542 (set_attr "length" "4,8")])
10543
10544
10545 (define_insn "*call_value_local64"
10546 [(set (match_operand 0 "" "")
10547 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10548 (match_operand 2 "" "g,g")))
10549 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10550 (clobber (reg:SI LR_REGNO))]
10551 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10552 "*
10553 {
10554 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10555 output_asm_insn (\"crxor 6,6,6\", operands);
10556
10557 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10558 output_asm_insn (\"creqv 6,6,6\", operands);
10559
10560 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10561 }"
10562 [(set_attr "type" "branch")
10563 (set_attr "length" "4,8")])
10564
10565 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
10566 ;; Operand0 is the addresss of the function to call
10567 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10568 ;; Operand2 is the location in the function descriptor to load r2 from
10569 ;; Operand3 is the stack location to hold the current TOC pointer
10570
10571 (define_insn "call_indirect_aix<ptrsize>"
10572 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10573 (match_operand 1 "" "g,g"))
10574 (use (match_operand:P 2 "memory_operand" "m,m"))
10575 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10576 (use (reg:P STATIC_CHAIN_REGNUM))
10577 (clobber (reg:P LR_REGNO))]
10578 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10579 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10580 [(set_attr "type" "jmpreg")
10581 (set_attr "length" "12")])
10582
10583 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
10584 ;; Operand0 is the addresss of the function to call
10585 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10586 ;; Operand2 is the location in the function descriptor to load r2 from
10587 ;; Operand3 is the stack location to hold the current TOC pointer
10588
10589 (define_insn "call_indirect_aix<ptrsize>_nor11"
10590 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10591 (match_operand 1 "" "g,g"))
10592 (use (match_operand:P 2 "memory_operand" "m,m"))
10593 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10594 (clobber (reg:P LR_REGNO))]
10595 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10596 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10597 [(set_attr "type" "jmpreg")
10598 (set_attr "length" "12")])
10599
10600 ;; Operand0 is the return result of the function
10601 ;; Operand1 is the addresss of the function to call
10602 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10603 ;; Operand3 is the location in the function descriptor to load r2 from
10604 ;; Operand4 is the stack location to hold the current TOC pointer
10605
10606 (define_insn "call_value_indirect_aix<ptrsize>"
10607 [(set (match_operand 0 "" "")
10608 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10609 (match_operand 2 "" "g,g")))
10610 (use (match_operand:P 3 "memory_operand" "m,m"))
10611 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10612 (use (reg:P STATIC_CHAIN_REGNUM))
10613 (clobber (reg:P LR_REGNO))]
10614 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10615 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10616 [(set_attr "type" "jmpreg")
10617 (set_attr "length" "12")])
10618
10619 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
10620 ;; Operand0 is the return result of the function
10621 ;; Operand1 is the addresss of the function to call
10622 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10623 ;; Operand3 is the location in the function descriptor to load r2 from
10624 ;; Operand4 is the stack location to hold the current TOC pointer
10625
10626 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
10627 [(set (match_operand 0 "" "")
10628 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10629 (match_operand 2 "" "g,g")))
10630 (use (match_operand:P 3 "memory_operand" "m,m"))
10631 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10632 (clobber (reg:P LR_REGNO))]
10633 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10634 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10635 [(set_attr "type" "jmpreg")
10636 (set_attr "length" "12")])
10637
10638 ;; Call to function which may be in another module. Restore the TOC
10639 ;; pointer (r2) after the call unless this is System V.
10640 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10641 ;; either the function was not prototyped, or it was prototyped as a
10642 ;; variable argument function. It is > 0 if FP registers were passed
10643 ;; and < 0 if they were not.
10644
10645 (define_insn "*call_nonlocal_aix32"
10646 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10647 (match_operand 1 "" "g"))
10648 (use (match_operand:SI 2 "immediate_operand" "O"))
10649 (clobber (reg:SI LR_REGNO))]
10650 "TARGET_32BIT
10651 && DEFAULT_ABI == ABI_AIX
10652 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10653 "bl %z0\;nop"
10654 [(set_attr "type" "branch")
10655 (set_attr "length" "8")])
10656
10657 (define_insn "*call_nonlocal_aix64"
10658 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10659 (match_operand 1 "" "g"))
10660 (use (match_operand:SI 2 "immediate_operand" "O"))
10661 (clobber (reg:SI LR_REGNO))]
10662 "TARGET_64BIT
10663 && DEFAULT_ABI == ABI_AIX
10664 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10665 "bl %z0\;nop"
10666 [(set_attr "type" "branch")
10667 (set_attr "length" "8")])
10668
10669 (define_insn "*call_value_nonlocal_aix32"
10670 [(set (match_operand 0 "" "")
10671 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10672 (match_operand 2 "" "g")))
10673 (use (match_operand:SI 3 "immediate_operand" "O"))
10674 (clobber (reg:SI LR_REGNO))]
10675 "TARGET_32BIT
10676 && DEFAULT_ABI == ABI_AIX
10677 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10678 "bl %z1\;nop"
10679 [(set_attr "type" "branch")
10680 (set_attr "length" "8")])
10681
10682 (define_insn "*call_value_nonlocal_aix64"
10683 [(set (match_operand 0 "" "")
10684 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10685 (match_operand 2 "" "g")))
10686 (use (match_operand:SI 3 "immediate_operand" "O"))
10687 (clobber (reg:SI LR_REGNO))]
10688 "TARGET_64BIT
10689 && DEFAULT_ABI == ABI_AIX
10690 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10691 "bl %z1\;nop"
10692 [(set_attr "type" "branch")
10693 (set_attr "length" "8")])
10694
10695 ;; A function pointer under System V is just a normal pointer
10696 ;; operands[0] is the function pointer
10697 ;; operands[1] is the stack size to clean up
10698 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10699 ;; which indicates how to set cr1
10700
10701 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10702 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10703 (match_operand 1 "" "g,g,g,g"))
10704 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10705 (clobber (reg:SI LR_REGNO))]
10706 "DEFAULT_ABI == ABI_V4
10707 || DEFAULT_ABI == ABI_DARWIN"
10708 {
10709 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10710 output_asm_insn ("crxor 6,6,6", operands);
10711
10712 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10713 output_asm_insn ("creqv 6,6,6", operands);
10714
10715 return "b%T0l";
10716 }
10717 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10718 (set_attr "length" "4,4,8,8")])
10719
10720 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10721 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10722 (match_operand 1 "" "g,g"))
10723 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10724 (clobber (reg:SI LR_REGNO))]
10725 "(DEFAULT_ABI == ABI_DARWIN
10726 || (DEFAULT_ABI == ABI_V4
10727 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10728 {
10729 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10730 output_asm_insn ("crxor 6,6,6", operands);
10731
10732 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10733 output_asm_insn ("creqv 6,6,6", operands);
10734
10735 #if TARGET_MACHO
10736 return output_call(insn, operands, 0, 2);
10737 #else
10738 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10739 {
10740 gcc_assert (!TARGET_SECURE_PLT);
10741 return "bl %z0@plt";
10742 }
10743 else
10744 return "bl %z0";
10745 #endif
10746 }
10747 "DEFAULT_ABI == ABI_V4
10748 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10749 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10750 [(parallel [(call (mem:SI (match_dup 0))
10751 (match_dup 1))
10752 (use (match_dup 2))
10753 (use (match_dup 3))
10754 (clobber (reg:SI LR_REGNO))])]
10755 {
10756 operands[3] = pic_offset_table_rtx;
10757 }
10758 [(set_attr "type" "branch,branch")
10759 (set_attr "length" "4,8")])
10760
10761 (define_insn "*call_nonlocal_sysv_secure<mode>"
10762 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10763 (match_operand 1 "" "g,g"))
10764 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10765 (use (match_operand:SI 3 "register_operand" "r,r"))
10766 (clobber (reg:SI LR_REGNO))]
10767 "(DEFAULT_ABI == ABI_V4
10768 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10769 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10770 {
10771 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10772 output_asm_insn ("crxor 6,6,6", operands);
10773
10774 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10775 output_asm_insn ("creqv 6,6,6", operands);
10776
10777 if (flag_pic == 2)
10778 /* The magic 32768 offset here and in the other sysv call insns
10779 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10780 See sysv4.h:toc_section. */
10781 return "bl %z0+32768@plt";
10782 else
10783 return "bl %z0@plt";
10784 }
10785 [(set_attr "type" "branch,branch")
10786 (set_attr "length" "4,8")])
10787
10788 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10789 [(set (match_operand 0 "" "")
10790 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10791 (match_operand 2 "" "g,g,g,g")))
10792 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10793 (clobber (reg:SI LR_REGNO))]
10794 "DEFAULT_ABI == ABI_V4
10795 || DEFAULT_ABI == ABI_DARWIN"
10796 {
10797 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10798 output_asm_insn ("crxor 6,6,6", operands);
10799
10800 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10801 output_asm_insn ("creqv 6,6,6", operands);
10802
10803 return "b%T1l";
10804 }
10805 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10806 (set_attr "length" "4,4,8,8")])
10807
10808 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
10809 [(set (match_operand 0 "" "")
10810 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10811 (match_operand 2 "" "g,g")))
10812 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10813 (clobber (reg:SI LR_REGNO))]
10814 "(DEFAULT_ABI == ABI_DARWIN
10815 || (DEFAULT_ABI == ABI_V4
10816 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10817 {
10818 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10819 output_asm_insn ("crxor 6,6,6", operands);
10820
10821 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10822 output_asm_insn ("creqv 6,6,6", operands);
10823
10824 #if TARGET_MACHO
10825 return output_call(insn, operands, 1, 3);
10826 #else
10827 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10828 {
10829 gcc_assert (!TARGET_SECURE_PLT);
10830 return "bl %z1@plt";
10831 }
10832 else
10833 return "bl %z1";
10834 #endif
10835 }
10836 "DEFAULT_ABI == ABI_V4
10837 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10838 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10839 [(parallel [(set (match_dup 0)
10840 (call (mem:SI (match_dup 1))
10841 (match_dup 2)))
10842 (use (match_dup 3))
10843 (use (match_dup 4))
10844 (clobber (reg:SI LR_REGNO))])]
10845 {
10846 operands[4] = pic_offset_table_rtx;
10847 }
10848 [(set_attr "type" "branch,branch")
10849 (set_attr "length" "4,8")])
10850
10851 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
10852 [(set (match_operand 0 "" "")
10853 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10854 (match_operand 2 "" "g,g")))
10855 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10856 (use (match_operand:SI 4 "register_operand" "r,r"))
10857 (clobber (reg:SI LR_REGNO))]
10858 "(DEFAULT_ABI == ABI_V4
10859 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10860 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
10861 {
10862 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10863 output_asm_insn ("crxor 6,6,6", operands);
10864
10865 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10866 output_asm_insn ("creqv 6,6,6", operands);
10867
10868 if (flag_pic == 2)
10869 return "bl %z1+32768@plt";
10870 else
10871 return "bl %z1@plt";
10872 }
10873 [(set_attr "type" "branch,branch")
10874 (set_attr "length" "4,8")])
10875
10876 ;; Call subroutine returning any type.
10877 (define_expand "untyped_call"
10878 [(parallel [(call (match_operand 0 "" "")
10879 (const_int 0))
10880 (match_operand 1 "" "")
10881 (match_operand 2 "" "")])]
10882 ""
10883 "
10884 {
10885 int i;
10886
10887 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10888
10889 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10890 {
10891 rtx set = XVECEXP (operands[2], 0, i);
10892 emit_move_insn (SET_DEST (set), SET_SRC (set));
10893 }
10894
10895 /* The optimizer does not know that the call sets the function value
10896 registers we stored in the result block. We avoid problems by
10897 claiming that all hard registers are used and clobbered at this
10898 point. */
10899 emit_insn (gen_blockage ());
10900
10901 DONE;
10902 }")
10903
10904 ;; sibling call patterns
10905 (define_expand "sibcall"
10906 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10907 (match_operand 1 "" ""))
10908 (use (match_operand 2 "" ""))
10909 (use (reg:SI LR_REGNO))
10910 (simple_return)])]
10911 ""
10912 "
10913 {
10914 #if TARGET_MACHO
10915 if (MACHOPIC_INDIRECT)
10916 operands[0] = machopic_indirect_call_target (operands[0]);
10917 #endif
10918
10919 gcc_assert (GET_CODE (operands[0]) == MEM);
10920 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10921
10922 operands[0] = XEXP (operands[0], 0);
10923 }")
10924
10925 ;; this and similar patterns must be marked as using LR, otherwise
10926 ;; dataflow will try to delete the store into it. This is true
10927 ;; even when the actual reg to jump to is in CTR, when LR was
10928 ;; saved and restored around the PIC-setting BCL.
10929 (define_insn "*sibcall_local32"
10930 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10931 (match_operand 1 "" "g,g"))
10932 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10933 (use (reg:SI LR_REGNO))
10934 (simple_return)]
10935 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10936 "*
10937 {
10938 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10939 output_asm_insn (\"crxor 6,6,6\", operands);
10940
10941 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10942 output_asm_insn (\"creqv 6,6,6\", operands);
10943
10944 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10945 }"
10946 [(set_attr "type" "branch")
10947 (set_attr "length" "4,8")])
10948
10949 (define_insn "*sibcall_local64"
10950 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10951 (match_operand 1 "" "g,g"))
10952 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10953 (use (reg:SI LR_REGNO))
10954 (simple_return)]
10955 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10956 "*
10957 {
10958 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10959 output_asm_insn (\"crxor 6,6,6\", operands);
10960
10961 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10962 output_asm_insn (\"creqv 6,6,6\", operands);
10963
10964 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10965 }"
10966 [(set_attr "type" "branch")
10967 (set_attr "length" "4,8")])
10968
10969 (define_insn "*sibcall_value_local32"
10970 [(set (match_operand 0 "" "")
10971 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10972 (match_operand 2 "" "g,g")))
10973 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10974 (use (reg:SI LR_REGNO))
10975 (simple_return)]
10976 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10977 "*
10978 {
10979 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10980 output_asm_insn (\"crxor 6,6,6\", operands);
10981
10982 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10983 output_asm_insn (\"creqv 6,6,6\", operands);
10984
10985 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10986 }"
10987 [(set_attr "type" "branch")
10988 (set_attr "length" "4,8")])
10989
10990
10991 (define_insn "*sibcall_value_local64"
10992 [(set (match_operand 0 "" "")
10993 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10994 (match_operand 2 "" "g,g")))
10995 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10996 (use (reg:SI LR_REGNO))
10997 (simple_return)]
10998 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10999 "*
11000 {
11001 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11002 output_asm_insn (\"crxor 6,6,6\", operands);
11003
11004 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11005 output_asm_insn (\"creqv 6,6,6\", operands);
11006
11007 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11008 }"
11009 [(set_attr "type" "branch")
11010 (set_attr "length" "4,8")])
11011
11012 (define_insn "*sibcall_nonlocal_aix<mode>"
11013 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11014 (match_operand 1 "" "g,g"))
11015 (use (match_operand:SI 2 "immediate_operand" "O,O"))
11016 (use (reg:SI LR_REGNO))
11017 (simple_return)]
11018 "DEFAULT_ABI == ABI_AIX
11019 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11020 "@
11021 b %z0
11022 b%T0"
11023 [(set_attr "type" "branch")
11024 (set_attr "length" "4")])
11025
11026 (define_insn "*sibcall_value_nonlocal_aix<mode>"
11027 [(set (match_operand 0 "" "")
11028 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11029 (match_operand 2 "" "g,g")))
11030 (use (match_operand:SI 3 "immediate_operand" "O,O"))
11031 (use (reg:SI LR_REGNO))
11032 (simple_return)]
11033 "DEFAULT_ABI == ABI_AIX
11034 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11035 "@
11036 b %z1
11037 b%T1"
11038 [(set_attr "type" "branch")
11039 (set_attr "length" "4")])
11040
11041 (define_insn "*sibcall_nonlocal_sysv<mode>"
11042 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11043 (match_operand 1 "" ""))
11044 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11045 (use (reg:SI LR_REGNO))
11046 (simple_return)]
11047 "(DEFAULT_ABI == ABI_DARWIN
11048 || DEFAULT_ABI == ABI_V4)
11049 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11050 "*
11051 {
11052 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11053 output_asm_insn (\"crxor 6,6,6\", operands);
11054
11055 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11056 output_asm_insn (\"creqv 6,6,6\", operands);
11057
11058 if (which_alternative >= 2)
11059 return \"b%T0\";
11060 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11061 {
11062 gcc_assert (!TARGET_SECURE_PLT);
11063 return \"b %z0@plt\";
11064 }
11065 else
11066 return \"b %z0\";
11067 }"
11068 [(set_attr "type" "branch")
11069 (set_attr "length" "4,8,4,8")])
11070
11071 (define_expand "sibcall_value"
11072 [(parallel [(set (match_operand 0 "register_operand" "")
11073 (call (mem:SI (match_operand 1 "address_operand" ""))
11074 (match_operand 2 "" "")))
11075 (use (match_operand 3 "" ""))
11076 (use (reg:SI LR_REGNO))
11077 (simple_return)])]
11078 ""
11079 "
11080 {
11081 #if TARGET_MACHO
11082 if (MACHOPIC_INDIRECT)
11083 operands[1] = machopic_indirect_call_target (operands[1]);
11084 #endif
11085
11086 gcc_assert (GET_CODE (operands[1]) == MEM);
11087 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11088
11089 operands[1] = XEXP (operands[1], 0);
11090 }")
11091
11092 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11093 [(set (match_operand 0 "" "")
11094 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11095 (match_operand 2 "" "")))
11096 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11097 (use (reg:SI LR_REGNO))
11098 (simple_return)]
11099 "(DEFAULT_ABI == ABI_DARWIN
11100 || DEFAULT_ABI == ABI_V4)
11101 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11102 "*
11103 {
11104 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11105 output_asm_insn (\"crxor 6,6,6\", operands);
11106
11107 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11108 output_asm_insn (\"creqv 6,6,6\", operands);
11109
11110 if (which_alternative >= 2)
11111 return \"b%T1\";
11112 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11113 {
11114 gcc_assert (!TARGET_SECURE_PLT);
11115 return \"b %z1@plt\";
11116 }
11117 else
11118 return \"b %z1\";
11119 }"
11120 [(set_attr "type" "branch")
11121 (set_attr "length" "4,8,4,8")])
11122
11123 (define_expand "sibcall_epilogue"
11124 [(use (const_int 0))]
11125 ""
11126 {
11127 if (!TARGET_SCHED_PROLOG)
11128 emit_insn (gen_blockage ());
11129 rs6000_emit_epilogue (TRUE);
11130 DONE;
11131 })
11132
11133 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11134 ;; all of memory. This blocks insns from being moved across this point.
11135
11136 (define_insn "blockage"
11137 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11138 ""
11139 "")
11140
11141 (define_expand "probe_stack"
11142 [(set (match_operand 0 "memory_operand" "=m")
11143 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11144 ""
11145 {
11146 if (TARGET_64BIT)
11147 emit_insn (gen_probe_stack_di (operands[0]));
11148 else
11149 emit_insn (gen_probe_stack_si (operands[0]));
11150 DONE;
11151 })
11152
11153 (define_insn "probe_stack_<mode>"
11154 [(set (match_operand:P 0 "memory_operand" "=m")
11155 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11156 ""
11157 {
11158 operands[1] = gen_rtx_REG (Pmode, 0);
11159 return "st<wd>%U0%X0 %1,%0";
11160 }
11161 [(set_attr "type" "store")
11162 (set_attr "length" "4")])
11163
11164 (define_insn "probe_stack_range<P:mode>"
11165 [(set (match_operand:P 0 "register_operand" "=r")
11166 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11167 (match_operand:P 2 "register_operand" "r")]
11168 UNSPECV_PROBE_STACK_RANGE))]
11169 ""
11170 "* return output_probe_stack_range (operands[0], operands[2]);"
11171 [(set_attr "type" "three")])
11172 \f
11173 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11174 ;; signed & unsigned, and one type of branch.
11175 ;;
11176 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11177 ;; insns, and branches.
11178
11179 (define_expand "cbranch<mode>4"
11180 [(use (match_operator 0 "rs6000_cbranch_operator"
11181 [(match_operand:GPR 1 "gpc_reg_operand" "")
11182 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11183 (use (match_operand 3 ""))]
11184 ""
11185 "
11186 {
11187 /* Take care of the possibility that operands[2] might be negative but
11188 this might be a logical operation. That insn doesn't exist. */
11189 if (GET_CODE (operands[2]) == CONST_INT
11190 && INTVAL (operands[2]) < 0)
11191 {
11192 operands[2] = force_reg (<MODE>mode, operands[2]);
11193 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11194 GET_MODE (operands[0]),
11195 operands[1], operands[2]);
11196 }
11197
11198 rs6000_emit_cbranch (<MODE>mode, operands);
11199 DONE;
11200 }")
11201
11202 (define_expand "cbranch<mode>4"
11203 [(use (match_operator 0 "rs6000_cbranch_operator"
11204 [(match_operand:FP 1 "gpc_reg_operand" "")
11205 (match_operand:FP 2 "gpc_reg_operand" "")]))
11206 (use (match_operand 3 ""))]
11207 ""
11208 "
11209 {
11210 rs6000_emit_cbranch (<MODE>mode, operands);
11211 DONE;
11212 }")
11213
11214 (define_expand "cstore<mode>4"
11215 [(use (match_operator 1 "rs6000_cbranch_operator"
11216 [(match_operand:GPR 2 "gpc_reg_operand" "")
11217 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11218 (clobber (match_operand:SI 0 "register_operand"))]
11219 ""
11220 "
11221 {
11222 /* Take care of the possibility that operands[3] might be negative but
11223 this might be a logical operation. That insn doesn't exist. */
11224 if (GET_CODE (operands[3]) == CONST_INT
11225 && INTVAL (operands[3]) < 0)
11226 {
11227 operands[3] = force_reg (<MODE>mode, operands[3]);
11228 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11229 GET_MODE (operands[1]),
11230 operands[2], operands[3]);
11231 }
11232
11233 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11234 For SEQ, likewise, except that comparisons with zero should be done
11235 with an scc insns. However, due to the order that combine see the
11236 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11237 the cases we don't want to handle or are best handled by portable
11238 code. */
11239 if (GET_CODE (operands[1]) == NE)
11240 FAIL;
11241 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11242 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11243 && operands[3] == const0_rtx)
11244 FAIL;
11245 rs6000_emit_sCOND (<MODE>mode, operands);
11246 DONE;
11247 }")
11248
11249 (define_expand "cstore<mode>4"
11250 [(use (match_operator 1 "rs6000_cbranch_operator"
11251 [(match_operand:FP 2 "gpc_reg_operand" "")
11252 (match_operand:FP 3 "gpc_reg_operand" "")]))
11253 (clobber (match_operand:SI 0 "register_operand"))]
11254 ""
11255 "
11256 {
11257 rs6000_emit_sCOND (<MODE>mode, operands);
11258 DONE;
11259 }")
11260
11261
11262 (define_expand "stack_protect_set"
11263 [(match_operand 0 "memory_operand" "")
11264 (match_operand 1 "memory_operand" "")]
11265 ""
11266 {
11267 #ifdef TARGET_THREAD_SSP_OFFSET
11268 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11269 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11270 operands[1] = gen_rtx_MEM (Pmode, addr);
11271 #endif
11272 if (TARGET_64BIT)
11273 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11274 else
11275 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11276 DONE;
11277 })
11278
11279 (define_insn "stack_protect_setsi"
11280 [(set (match_operand:SI 0 "memory_operand" "=m")
11281 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11282 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11283 "TARGET_32BIT"
11284 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11285 [(set_attr "type" "three")
11286 (set_attr "length" "12")])
11287
11288 (define_insn "stack_protect_setdi"
11289 [(set (match_operand:DI 0 "memory_operand" "=Y")
11290 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11291 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11292 "TARGET_64BIT"
11293 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11294 [(set_attr "type" "three")
11295 (set_attr "length" "12")])
11296
11297 (define_expand "stack_protect_test"
11298 [(match_operand 0 "memory_operand" "")
11299 (match_operand 1 "memory_operand" "")
11300 (match_operand 2 "" "")]
11301 ""
11302 {
11303 rtx test, op0, op1;
11304 #ifdef TARGET_THREAD_SSP_OFFSET
11305 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11306 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11307 operands[1] = gen_rtx_MEM (Pmode, addr);
11308 #endif
11309 op0 = operands[0];
11310 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11311 test = gen_rtx_EQ (VOIDmode, op0, op1);
11312 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11313 DONE;
11314 })
11315
11316 (define_insn "stack_protect_testsi"
11317 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11318 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11319 (match_operand:SI 2 "memory_operand" "m,m")]
11320 UNSPEC_SP_TEST))
11321 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11322 (clobber (match_scratch:SI 3 "=&r,&r"))]
11323 "TARGET_32BIT"
11324 "@
11325 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11326 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11327 [(set_attr "length" "16,20")])
11328
11329 (define_insn "stack_protect_testdi"
11330 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11331 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11332 (match_operand:DI 2 "memory_operand" "Y,Y")]
11333 UNSPEC_SP_TEST))
11334 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11335 (clobber (match_scratch:DI 3 "=&r,&r"))]
11336 "TARGET_64BIT"
11337 "@
11338 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11339 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11340 [(set_attr "length" "16,20")])
11341
11342 \f
11343 ;; Here are the actual compare insns.
11344 (define_insn "*cmp<mode>_internal1"
11345 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11346 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11347 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11348 ""
11349 "cmp<wd>%I2 %0,%1,%2"
11350 [(set_attr "type" "cmp")])
11351
11352 ;; If we are comparing a register for equality with a large constant,
11353 ;; we can do this with an XOR followed by a compare. But this is profitable
11354 ;; only if the large constant is only used for the comparison (and in this
11355 ;; case we already have a register to reuse as scratch).
11356 ;;
11357 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11358 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11359
11360 (define_peephole2
11361 [(set (match_operand:SI 0 "register_operand")
11362 (match_operand:SI 1 "logical_const_operand" ""))
11363 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11364 [(match_dup 0)
11365 (match_operand:SI 2 "logical_const_operand" "")]))
11366 (set (match_operand:CC 4 "cc_reg_operand" "")
11367 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11368 (match_dup 0)))
11369 (set (pc)
11370 (if_then_else (match_operator 6 "equality_operator"
11371 [(match_dup 4) (const_int 0)])
11372 (match_operand 7 "" "")
11373 (match_operand 8 "" "")))]
11374 "peep2_reg_dead_p (3, operands[0])
11375 && peep2_reg_dead_p (4, operands[4])"
11376 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11377 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11378 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11379
11380 {
11381 /* Get the constant we are comparing against, and see what it looks like
11382 when sign-extended from 16 to 32 bits. Then see what constant we could
11383 XOR with SEXTC to get the sign-extended value. */
11384 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11385 SImode,
11386 operands[1], operands[2]);
11387 HOST_WIDE_INT c = INTVAL (cnst);
11388 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11389 HOST_WIDE_INT xorv = c ^ sextc;
11390
11391 operands[9] = GEN_INT (xorv);
11392 operands[10] = GEN_INT (sextc);
11393 })
11394
11395 (define_insn "*cmpsi_internal2"
11396 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11397 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11398 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11399 ""
11400 "cmplw%I2 %0,%1,%b2"
11401 [(set_attr "type" "cmp")])
11402
11403 (define_insn "*cmpdi_internal2"
11404 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11405 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11406 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11407 ""
11408 "cmpld%I2 %0,%1,%b2"
11409 [(set_attr "type" "cmp")])
11410
11411 ;; The following two insns don't exist as single insns, but if we provide
11412 ;; them, we can swap an add and compare, which will enable us to overlap more
11413 ;; of the required delay between a compare and branch. We generate code for
11414 ;; them by splitting.
11415
11416 (define_insn ""
11417 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11418 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11419 (match_operand:SI 2 "short_cint_operand" "i")))
11420 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11421 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11422 ""
11423 "#"
11424 [(set_attr "length" "8")])
11425
11426 (define_insn ""
11427 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11428 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11429 (match_operand:SI 2 "u_short_cint_operand" "i")))
11430 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11431 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11432 ""
11433 "#"
11434 [(set_attr "length" "8")])
11435
11436 (define_split
11437 [(set (match_operand:CC 3 "cc_reg_operand" "")
11438 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11439 (match_operand:SI 2 "short_cint_operand" "")))
11440 (set (match_operand:SI 0 "gpc_reg_operand" "")
11441 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11442 ""
11443 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11444 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11445
11446 (define_split
11447 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11448 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11449 (match_operand:SI 2 "u_short_cint_operand" "")))
11450 (set (match_operand:SI 0 "gpc_reg_operand" "")
11451 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11452 ""
11453 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11454 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11455
11456 (define_insn "*cmpsf_internal1"
11457 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11458 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11459 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11460 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
11461 "fcmpu %0,%1,%2"
11462 [(set_attr "type" "fpcompare")])
11463
11464 (define_insn "*cmpdf_internal1"
11465 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11466 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
11467 (match_operand:DF 2 "gpc_reg_operand" "d")))]
11468 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11469 && !VECTOR_UNIT_VSX_P (DFmode)"
11470 "fcmpu %0,%1,%2"
11471 [(set_attr "type" "fpcompare")])
11472
11473 ;; Only need to compare second words if first words equal
11474 (define_insn "*cmptf_internal1"
11475 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11476 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11477 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11478 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11479 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11480 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11481 [(set_attr "type" "fpcompare")
11482 (set_attr "length" "12")])
11483
11484 (define_insn_and_split "*cmptf_internal2"
11485 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11486 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11487 (match_operand:TF 2 "gpc_reg_operand" "d")))
11488 (clobber (match_scratch:DF 3 "=d"))
11489 (clobber (match_scratch:DF 4 "=d"))
11490 (clobber (match_scratch:DF 5 "=d"))
11491 (clobber (match_scratch:DF 6 "=d"))
11492 (clobber (match_scratch:DF 7 "=d"))
11493 (clobber (match_scratch:DF 8 "=d"))
11494 (clobber (match_scratch:DF 9 "=d"))
11495 (clobber (match_scratch:DF 10 "=d"))
11496 (clobber (match_scratch:GPR 11 "=b"))]
11497 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11498 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11499 "#"
11500 "&& reload_completed"
11501 [(set (match_dup 3) (match_dup 14))
11502 (set (match_dup 4) (match_dup 15))
11503 (set (match_dup 9) (abs:DF (match_dup 5)))
11504 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11505 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11506 (label_ref (match_dup 12))
11507 (pc)))
11508 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11509 (set (pc) (label_ref (match_dup 13)))
11510 (match_dup 12)
11511 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11512 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11513 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11514 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11515 (match_dup 13)]
11516 {
11517 REAL_VALUE_TYPE rv;
11518 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11519 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11520
11521 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11522 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11523 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11524 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11525 operands[12] = gen_label_rtx ();
11526 operands[13] = gen_label_rtx ();
11527 real_inf (&rv);
11528 operands[14] = force_const_mem (DFmode,
11529 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11530 operands[15] = force_const_mem (DFmode,
11531 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11532 DFmode));
11533 if (TARGET_TOC)
11534 {
11535 rtx tocref;
11536 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11537 operands[14] = gen_const_mem (DFmode, tocref);
11538 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11539 operands[15] = gen_const_mem (DFmode, tocref);
11540 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11541 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11542 }
11543 })
11544 \f
11545 ;; Now we have the scc insns. We can do some combinations because of the
11546 ;; way the machine works.
11547 ;;
11548 ;; Note that this is probably faster if we can put an insn between the
11549 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11550 ;; cases the insns below which don't use an intermediate CR field will
11551 ;; be used instead.
11552 (define_insn ""
11553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11554 (match_operator:SI 1 "scc_comparison_operator"
11555 [(match_operand 2 "cc_reg_operand" "y")
11556 (const_int 0)]))]
11557 ""
11558 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11559 [(set (attr "type")
11560 (cond [(match_test "TARGET_MFCRF")
11561 (const_string "mfcrf")
11562 ]
11563 (const_string "mfcr")))
11564 (set_attr "length" "8")])
11565
11566 ;; Same as above, but get the GT bit.
11567 (define_insn "move_from_CR_gt_bit"
11568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11569 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11570 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11571 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11572 [(set_attr "type" "mfcr")
11573 (set_attr "length" "8")])
11574
11575 ;; Same as above, but get the OV/ORDERED bit.
11576 (define_insn "move_from_CR_ov_bit"
11577 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11578 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11579 UNSPEC_MV_CR_OV))]
11580 "TARGET_ISEL"
11581 "mfcr %0\;rlwinm %0,%0,%t1,1"
11582 [(set_attr "type" "mfcr")
11583 (set_attr "length" "8")])
11584
11585 (define_insn ""
11586 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11587 (match_operator:DI 1 "scc_comparison_operator"
11588 [(match_operand 2 "cc_reg_operand" "y")
11589 (const_int 0)]))]
11590 "TARGET_POWERPC64"
11591 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11592 [(set (attr "type")
11593 (cond [(match_test "TARGET_MFCRF")
11594 (const_string "mfcrf")
11595 ]
11596 (const_string "mfcr")))
11597 (set_attr "length" "8")])
11598
11599 (define_insn ""
11600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11601 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11602 [(match_operand 2 "cc_reg_operand" "y,y")
11603 (const_int 0)])
11604 (const_int 0)))
11605 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11606 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11607 "TARGET_32BIT"
11608 "@
11609 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11610 #"
11611 [(set_attr "type" "delayed_compare")
11612 (set_attr "length" "8,16")])
11613
11614 (define_split
11615 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11616 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11617 [(match_operand 2 "cc_reg_operand" "")
11618 (const_int 0)])
11619 (const_int 0)))
11620 (set (match_operand:SI 3 "gpc_reg_operand" "")
11621 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11622 "TARGET_32BIT && reload_completed"
11623 [(set (match_dup 3)
11624 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11625 (set (match_dup 0)
11626 (compare:CC (match_dup 3)
11627 (const_int 0)))]
11628 "")
11629
11630 (define_insn ""
11631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11632 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11633 [(match_operand 2 "cc_reg_operand" "y")
11634 (const_int 0)])
11635 (match_operand:SI 3 "const_int_operand" "n")))]
11636 ""
11637 "*
11638 {
11639 int is_bit = ccr_bit (operands[1], 1);
11640 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11641 int count;
11642
11643 if (is_bit >= put_bit)
11644 count = is_bit - put_bit;
11645 else
11646 count = 32 - (put_bit - is_bit);
11647
11648 operands[4] = GEN_INT (count);
11649 operands[5] = GEN_INT (put_bit);
11650
11651 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11652 }"
11653 [(set (attr "type")
11654 (cond [(match_test "TARGET_MFCRF")
11655 (const_string "mfcrf")
11656 ]
11657 (const_string "mfcr")))
11658 (set_attr "length" "8")])
11659
11660 (define_insn ""
11661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11662 (compare:CC
11663 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11664 [(match_operand 2 "cc_reg_operand" "y,y")
11665 (const_int 0)])
11666 (match_operand:SI 3 "const_int_operand" "n,n"))
11667 (const_int 0)))
11668 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11669 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11670 (match_dup 3)))]
11671 ""
11672 "*
11673 {
11674 int is_bit = ccr_bit (operands[1], 1);
11675 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11676 int count;
11677
11678 /* Force split for non-cc0 compare. */
11679 if (which_alternative == 1)
11680 return \"#\";
11681
11682 if (is_bit >= put_bit)
11683 count = is_bit - put_bit;
11684 else
11685 count = 32 - (put_bit - is_bit);
11686
11687 operands[5] = GEN_INT (count);
11688 operands[6] = GEN_INT (put_bit);
11689
11690 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11691 }"
11692 [(set_attr "type" "delayed_compare")
11693 (set_attr "length" "8,16")])
11694
11695 (define_split
11696 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
11697 (compare:CC
11698 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11699 [(match_operand 2 "cc_reg_operand" "")
11700 (const_int 0)])
11701 (match_operand:SI 3 "const_int_operand" ""))
11702 (const_int 0)))
11703 (set (match_operand:SI 4 "gpc_reg_operand" "")
11704 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11705 (match_dup 3)))]
11706 "reload_completed"
11707 [(set (match_dup 4)
11708 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11709 (match_dup 3)))
11710 (set (match_dup 0)
11711 (compare:CC (match_dup 4)
11712 (const_int 0)))]
11713 "")
11714
11715 ;; There is a 3 cycle delay between consecutive mfcr instructions
11716 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11717
11718 (define_peephole
11719 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11720 (match_operator:SI 1 "scc_comparison_operator"
11721 [(match_operand 2 "cc_reg_operand" "y")
11722 (const_int 0)]))
11723 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11724 (match_operator:SI 4 "scc_comparison_operator"
11725 [(match_operand 5 "cc_reg_operand" "y")
11726 (const_int 0)]))]
11727 "REGNO (operands[2]) != REGNO (operands[5])"
11728 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11729 [(set_attr "type" "mfcr")
11730 (set_attr "length" "12")])
11731
11732 (define_peephole
11733 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11734 (match_operator:DI 1 "scc_comparison_operator"
11735 [(match_operand 2 "cc_reg_operand" "y")
11736 (const_int 0)]))
11737 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11738 (match_operator:DI 4 "scc_comparison_operator"
11739 [(match_operand 5 "cc_reg_operand" "y")
11740 (const_int 0)]))]
11741 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11742 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11743 [(set_attr "type" "mfcr")
11744 (set_attr "length" "12")])
11745
11746 ;; There are some scc insns that can be done directly, without a compare.
11747 ;; These are faster because they don't involve the communications between
11748 ;; the FXU and branch units. In fact, we will be replacing all of the
11749 ;; integer scc insns here or in the portable methods in emit_store_flag.
11750 ;;
11751 ;; Also support (neg (scc ..)) since that construct is used to replace
11752 ;; branches, (plus (scc ..) ..) since that construct is common and
11753 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11754 ;; cases where it is no more expensive than (neg (scc ..)).
11755
11756 ;; Have reload force a constant into a register for the simple insns that
11757 ;; otherwise won't accept constants. We do this because it is faster than
11758 ;; the cmp/mfcr sequence we would otherwise generate.
11759
11760 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11761 (DI "rKJI")])
11762
11763 (define_insn_and_split "*eq<mode>"
11764 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11765 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11766 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11767 ""
11768 "#"
11769 ""
11770 [(set (match_dup 0)
11771 (clz:GPR (match_dup 3)))
11772 (set (match_dup 0)
11773 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11774 {
11775 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11776 {
11777 /* Use output operand as intermediate. */
11778 operands[3] = operands[0];
11779
11780 if (logical_operand (operands[2], <MODE>mode))
11781 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11782 gen_rtx_XOR (<MODE>mode,
11783 operands[1], operands[2])));
11784 else
11785 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11786 gen_rtx_PLUS (<MODE>mode, operands[1],
11787 negate_rtx (<MODE>mode,
11788 operands[2]))));
11789 }
11790 else
11791 operands[3] = operands[1];
11792
11793 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11794 })
11795
11796 (define_insn_and_split "*eq<mode>_compare"
11797 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11798 (compare:CC
11799 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11800 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11801 (const_int 0)))
11802 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11803 (eq:P (match_dup 1) (match_dup 2)))]
11804 "optimize_size"
11805 "#"
11806 "optimize_size"
11807 [(set (match_dup 0)
11808 (clz:P (match_dup 4)))
11809 (parallel [(set (match_dup 3)
11810 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11811 (const_int 0)))
11812 (set (match_dup 0)
11813 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11814 {
11815 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11816 {
11817 /* Use output operand as intermediate. */
11818 operands[4] = operands[0];
11819
11820 if (logical_operand (operands[2], <MODE>mode))
11821 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11822 gen_rtx_XOR (<MODE>mode,
11823 operands[1], operands[2])));
11824 else
11825 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11826 gen_rtx_PLUS (<MODE>mode, operands[1],
11827 negate_rtx (<MODE>mode,
11828 operands[2]))));
11829 }
11830 else
11831 operands[4] = operands[1];
11832
11833 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11834 })
11835
11836 ;; We have insns of the form shown by the first define_insn below. If
11837 ;; there is something inside the comparison operation, we must split it.
11838 (define_split
11839 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11840 (plus:SI (match_operator 1 "comparison_operator"
11841 [(match_operand:SI 2 "" "")
11842 (match_operand:SI 3
11843 "reg_or_cint_operand" "")])
11844 (match_operand:SI 4 "gpc_reg_operand" "")))
11845 (clobber (match_operand:SI 5 "register_operand" ""))]
11846 "! gpc_reg_operand (operands[2], SImode)"
11847 [(set (match_dup 5) (match_dup 2))
11848 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
11849 (match_dup 4)))])
11850
11851 (define_insn "*plus_eqsi"
11852 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11853 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11854 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11855 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11856 "TARGET_32BIT"
11857 "@
11858 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
11859 subfic %0,%1,0\;addze %0,%3
11860 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
11861 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
11862 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
11863 [(set_attr "type" "three,two,three,three,three")
11864 (set_attr "length" "12,8,12,12,12")])
11865
11866 (define_insn "*compare_plus_eqsi"
11867 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11868 (compare:CC
11869 (plus:SI
11870 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11871 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11872 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11873 (const_int 0)))
11874 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11875 "TARGET_32BIT && optimize_size"
11876 "@
11877 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11878 subfic %4,%1,0\;addze. %4,%3
11879 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
11880 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
11881 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11882 #
11883 #
11884 #
11885 #
11886 #"
11887 [(set_attr "type" "compare")
11888 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11889
11890 (define_split
11891 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11892 (compare:CC
11893 (plus:SI
11894 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11895 (match_operand:SI 2 "scc_eq_operand" ""))
11896 (match_operand:SI 3 "gpc_reg_operand" ""))
11897 (const_int 0)))
11898 (clobber (match_scratch:SI 4 ""))]
11899 "TARGET_32BIT && optimize_size && reload_completed"
11900 [(set (match_dup 4)
11901 (plus:SI (eq:SI (match_dup 1)
11902 (match_dup 2))
11903 (match_dup 3)))
11904 (set (match_dup 0)
11905 (compare:CC (match_dup 4)
11906 (const_int 0)))]
11907 "")
11908
11909 (define_insn "*plus_eqsi_compare"
11910 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11911 (compare:CC
11912 (plus:SI
11913 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11914 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11915 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11916 (const_int 0)))
11917 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11918 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11919 "TARGET_32BIT && optimize_size"
11920 "@
11921 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11922 subfic %0,%1,0\;addze. %0,%3
11923 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
11924 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
11925 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11926 #
11927 #
11928 #
11929 #
11930 #"
11931 [(set_attr "type" "compare")
11932 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11933
11934 (define_split
11935 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11936 (compare:CC
11937 (plus:SI
11938 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11939 (match_operand:SI 2 "scc_eq_operand" ""))
11940 (match_operand:SI 3 "gpc_reg_operand" ""))
11941 (const_int 0)))
11942 (set (match_operand:SI 0 "gpc_reg_operand" "")
11943 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11944 "TARGET_32BIT && optimize_size && reload_completed"
11945 [(set (match_dup 0)
11946 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11947 (set (match_dup 4)
11948 (compare:CC (match_dup 0)
11949 (const_int 0)))]
11950 "")
11951
11952 (define_insn "*neg_eq0<mode>"
11953 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11954 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11955 (const_int 0))))]
11956 ""
11957 "addic %0,%1,-1\;subfe %0,%0,%0"
11958 [(set_attr "type" "two")
11959 (set_attr "length" "8")])
11960
11961 (define_insn_and_split "*neg_eq<mode>"
11962 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11963 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11964 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11965 ""
11966 "#"
11967 ""
11968 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11969 {
11970 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11971 {
11972 /* Use output operand as intermediate. */
11973 operands[3] = operands[0];
11974
11975 if (logical_operand (operands[2], <MODE>mode))
11976 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11977 gen_rtx_XOR (<MODE>mode,
11978 operands[1], operands[2])));
11979 else
11980 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11981 gen_rtx_PLUS (<MODE>mode, operands[1],
11982 negate_rtx (<MODE>mode,
11983 operands[2]))));
11984 }
11985 else
11986 operands[3] = operands[1];
11987 })
11988
11989 (define_insn "*ne0_<mode>"
11990 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11991 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
11992 (const_int 0)))
11993 (clobber (match_scratch:P 2 "=&r"))]
11994 "!(TARGET_32BIT && TARGET_ISEL)"
11995 "addic %2,%1,-1\;subfe %0,%2,%1"
11996 [(set_attr "type" "two")
11997 (set_attr "length" "8")])
11998
11999 (define_insn "*plus_ne0_<mode>"
12000 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12001 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12002 (const_int 0))
12003 (match_operand:P 2 "gpc_reg_operand" "r")))
12004 (clobber (match_scratch:P 3 "=&r"))]
12005 ""
12006 "addic %3,%1,-1\;addze %0,%2"
12007 [(set_attr "type" "two")
12008 (set_attr "length" "8")])
12009
12010 (define_insn "*compare_plus_ne0_<mode>"
12011 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12012 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12013 (const_int 0))
12014 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12015 (const_int 0)))
12016 (clobber (match_scratch:P 3 "=&r,&r"))
12017 (clobber (match_scratch:P 4 "=X,&r"))]
12018 ""
12019 "@
12020 addic %3,%1,-1\;addze. %3,%2
12021 #"
12022 [(set_attr "type" "compare")
12023 (set_attr "length" "8,12")])
12024
12025 (define_split
12026 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12027 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12028 (const_int 0))
12029 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12030 (clobber (match_scratch:P 3 ""))
12031 (clobber (match_scratch:P 4 ""))]
12032 "reload_completed"
12033 [(parallel [(set (match_dup 3)
12034 (plus:P (ne:P (match_dup 1)
12035 (const_int 0))
12036 (match_dup 2)))
12037 (clobber (match_dup 4))])
12038 (set (match_dup 0)
12039 (compare:CC (match_dup 3)
12040 (const_int 0)))]
12041 "")
12042
12043 ; For combine.
12044 (define_insn "*compare_plus_ne0_<mode>_1"
12045 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12046 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12047 (const_int 0))
12048 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12049 (clobber (match_scratch:P 3 "=&r,&r"))
12050 (clobber (match_scratch:P 4 "=X,&r"))]
12051 ""
12052 "@
12053 addic %3,%1,-1\;addze. %3,%2
12054 #"
12055 [(set_attr "type" "compare")
12056 (set_attr "length" "8,12")])
12057
12058 (define_split
12059 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12060 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12061 (const_int 0))
12062 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12063 (clobber (match_scratch:P 3 ""))
12064 (clobber (match_scratch:P 4 ""))]
12065 "reload_completed"
12066 [(parallel [(set (match_dup 3)
12067 (plus:P (ne:P (match_dup 1)
12068 (const_int 0))
12069 (match_dup 2)))
12070 (clobber (match_dup 4))])
12071 (set (match_dup 0)
12072 (compare:CC (match_dup 3)
12073 (const_int 0)))]
12074 "")
12075
12076 (define_insn "*plus_ne0_<mode>_compare"
12077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12078 (compare:CC
12079 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12080 (const_int 0))
12081 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12082 (const_int 0)))
12083 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12084 (plus:P (ne:P (match_dup 1)
12085 (const_int 0))
12086 (match_dup 2)))
12087 (clobber (match_scratch:P 3 "=&r,&r"))]
12088 ""
12089 "@
12090 addic %3,%1,-1\;addze. %0,%2
12091 #"
12092 [(set_attr "type" "compare")
12093 (set_attr "length" "8,12")])
12094
12095 (define_split
12096 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12097 (compare:CC
12098 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12099 (const_int 0))
12100 (match_operand:P 2 "gpc_reg_operand" ""))
12101 (const_int 0)))
12102 (set (match_operand:P 0 "gpc_reg_operand" "")
12103 (plus:P (ne:P (match_dup 1)
12104 (const_int 0))
12105 (match_dup 2)))
12106 (clobber (match_scratch:P 3 ""))]
12107 "reload_completed"
12108 [(parallel [(set (match_dup 0)
12109 (plus:P (ne:P (match_dup 1)
12110 (const_int 0))
12111 (match_dup 2)))
12112 (clobber (match_dup 3))])
12113 (set (match_dup 4)
12114 (compare:CC (match_dup 0)
12115 (const_int 0)))]
12116 "")
12117
12118 (define_insn "*leu<mode>"
12119 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12120 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12121 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12122 ""
12123 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12124 [(set_attr "type" "three")
12125 (set_attr "length" "12")])
12126
12127 (define_insn "*leu<mode>_compare"
12128 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12129 (compare:CC
12130 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12131 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12132 (const_int 0)))
12133 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12134 (leu:P (match_dup 1) (match_dup 2)))]
12135 ""
12136 "@
12137 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12138 #"
12139 [(set_attr "type" "compare")
12140 (set_attr "length" "12,16")])
12141
12142 (define_split
12143 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12144 (compare:CC
12145 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12146 (match_operand:P 2 "reg_or_short_operand" ""))
12147 (const_int 0)))
12148 (set (match_operand:P 0 "gpc_reg_operand" "")
12149 (leu:P (match_dup 1) (match_dup 2)))]
12150 "reload_completed"
12151 [(set (match_dup 0)
12152 (leu:P (match_dup 1) (match_dup 2)))
12153 (set (match_dup 3)
12154 (compare:CC (match_dup 0)
12155 (const_int 0)))]
12156 "")
12157
12158 (define_insn "*plus_leu<mode>"
12159 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12160 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12161 (match_operand:P 2 "reg_or_short_operand" "rI"))
12162 (match_operand:P 3 "gpc_reg_operand" "r")))]
12163 ""
12164 "subf%I2c %0,%1,%2\;addze %0,%3"
12165 [(set_attr "type" "two")
12166 (set_attr "length" "8")])
12167
12168 (define_insn ""
12169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12170 (compare:CC
12171 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12172 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12173 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12174 (const_int 0)))
12175 (clobber (match_scratch:SI 4 "=&r,&r"))]
12176 "TARGET_32BIT"
12177 "@
12178 subf%I2c %4,%1,%2\;addze. %4,%3
12179 #"
12180 [(set_attr "type" "compare")
12181 (set_attr "length" "8,12")])
12182
12183 (define_split
12184 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12185 (compare:CC
12186 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12187 (match_operand:SI 2 "reg_or_short_operand" ""))
12188 (match_operand:SI 3 "gpc_reg_operand" ""))
12189 (const_int 0)))
12190 (clobber (match_scratch:SI 4 ""))]
12191 "TARGET_32BIT && reload_completed"
12192 [(set (match_dup 4)
12193 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12194 (match_dup 3)))
12195 (set (match_dup 0)
12196 (compare:CC (match_dup 4)
12197 (const_int 0)))]
12198 "")
12199
12200 (define_insn ""
12201 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12202 (compare:CC
12203 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12204 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12205 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12206 (const_int 0)))
12207 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12208 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12209 "TARGET_32BIT"
12210 "@
12211 subf%I2c %0,%1,%2\;addze. %0,%3
12212 #"
12213 [(set_attr "type" "compare")
12214 (set_attr "length" "8,12")])
12215
12216 (define_split
12217 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12218 (compare:CC
12219 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12220 (match_operand:SI 2 "reg_or_short_operand" ""))
12221 (match_operand:SI 3 "gpc_reg_operand" ""))
12222 (const_int 0)))
12223 (set (match_operand:SI 0 "gpc_reg_operand" "")
12224 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12225 "TARGET_32BIT && reload_completed"
12226 [(set (match_dup 0)
12227 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12228 (set (match_dup 4)
12229 (compare:CC (match_dup 0)
12230 (const_int 0)))]
12231 "")
12232
12233 (define_insn "*neg_leu<mode>"
12234 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12235 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12236 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12237 ""
12238 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12239 [(set_attr "type" "three")
12240 (set_attr "length" "12")])
12241
12242 (define_insn "*and_neg_leu<mode>"
12243 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12244 (and:P (neg:P
12245 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12246 (match_operand:P 2 "reg_or_short_operand" "rI")))
12247 (match_operand:P 3 "gpc_reg_operand" "r")))]
12248 ""
12249 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12250 [(set_attr "type" "three")
12251 (set_attr "length" "12")])
12252
12253 (define_insn ""
12254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12255 (compare:CC
12256 (and:SI (neg:SI
12257 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12258 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12259 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12260 (const_int 0)))
12261 (clobber (match_scratch:SI 4 "=&r,&r"))]
12262 "TARGET_32BIT"
12263 "@
12264 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12265 #"
12266 [(set_attr "type" "compare")
12267 (set_attr "length" "12,16")])
12268
12269 (define_split
12270 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12271 (compare:CC
12272 (and:SI (neg:SI
12273 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12274 (match_operand:SI 2 "reg_or_short_operand" "")))
12275 (match_operand:SI 3 "gpc_reg_operand" ""))
12276 (const_int 0)))
12277 (clobber (match_scratch:SI 4 ""))]
12278 "TARGET_32BIT && reload_completed"
12279 [(set (match_dup 4)
12280 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12281 (match_dup 3)))
12282 (set (match_dup 0)
12283 (compare:CC (match_dup 4)
12284 (const_int 0)))]
12285 "")
12286
12287 (define_insn ""
12288 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12289 (compare:CC
12290 (and:SI (neg:SI
12291 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12292 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12293 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12294 (const_int 0)))
12295 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12296 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12297 "TARGET_32BIT"
12298 "@
12299 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12300 #"
12301 [(set_attr "type" "compare")
12302 (set_attr "length" "12,16")])
12303
12304 (define_split
12305 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12306 (compare:CC
12307 (and:SI (neg:SI
12308 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12309 (match_operand:SI 2 "reg_or_short_operand" "")))
12310 (match_operand:SI 3 "gpc_reg_operand" ""))
12311 (const_int 0)))
12312 (set (match_operand:SI 0 "gpc_reg_operand" "")
12313 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12314 "TARGET_32BIT && reload_completed"
12315 [(set (match_dup 0)
12316 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12317 (match_dup 3)))
12318 (set (match_dup 4)
12319 (compare:CC (match_dup 0)
12320 (const_int 0)))]
12321 "")
12322
12323 (define_insn_and_split "*ltu<mode>"
12324 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12325 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12326 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12327 ""
12328 "#"
12329 ""
12330 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12331 (set (match_dup 0) (neg:P (match_dup 0)))]
12332 "")
12333
12334 (define_insn_and_split "*ltu<mode>_compare"
12335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12336 (compare:CC
12337 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12338 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12339 (const_int 0)))
12340 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12341 (ltu:P (match_dup 1) (match_dup 2)))]
12342 ""
12343 "#"
12344 ""
12345 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12346 (parallel [(set (match_dup 3)
12347 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12348 (set (match_dup 0) (neg:P (match_dup 0)))])]
12349 "")
12350
12351 (define_insn_and_split "*plus_ltu<mode>"
12352 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12353 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12354 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12355 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12356 ""
12357 "#"
12358 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12359 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12360 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12361 "")
12362
12363 (define_insn_and_split "*plus_ltu<mode>_compare"
12364 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12365 (compare:CC
12366 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12367 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12368 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12369 (const_int 0)))
12370 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12371 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12372 ""
12373 "#"
12374 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12375 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12376 (parallel [(set (match_dup 4)
12377 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12378 (const_int 0)))
12379 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12380 "")
12381
12382 (define_insn "*neg_ltu<mode>"
12383 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12384 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12385 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12386 ""
12387 "@
12388 subfc %0,%2,%1\;subfe %0,%0,%0
12389 addic %0,%1,%n2\;subfe %0,%0,%0"
12390 [(set_attr "type" "two")
12391 (set_attr "length" "8")])
12392
12393 (define_insn "*geu<mode>"
12394 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12395 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12396 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12397 ""
12398 "@
12399 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12400 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12401 [(set_attr "type" "three")
12402 (set_attr "length" "12")])
12403
12404 (define_insn "*geu<mode>_compare"
12405 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12406 (compare:CC
12407 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12408 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12409 (const_int 0)))
12410 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12411 (geu:P (match_dup 1) (match_dup 2)))]
12412 ""
12413 "@
12414 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12415 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12416 #
12417 #"
12418 [(set_attr "type" "compare")
12419 (set_attr "length" "12,12,16,16")])
12420
12421 (define_split
12422 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12423 (compare:CC
12424 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12425 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12426 (const_int 0)))
12427 (set (match_operand:P 0 "gpc_reg_operand" "")
12428 (geu:P (match_dup 1) (match_dup 2)))]
12429 "reload_completed"
12430 [(set (match_dup 0)
12431 (geu:P (match_dup 1) (match_dup 2)))
12432 (set (match_dup 3)
12433 (compare:CC (match_dup 0)
12434 (const_int 0)))]
12435 "")
12436
12437 (define_insn "*plus_geu<mode>"
12438 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12439 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12440 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12441 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12442 ""
12443 "@
12444 subfc %0,%2,%1\;addze %0,%3
12445 addic %0,%1,%n2\;addze %0,%3"
12446 [(set_attr "type" "two")
12447 (set_attr "length" "8")])
12448
12449 (define_insn ""
12450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12451 (compare:CC
12452 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12453 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12454 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12455 (const_int 0)))
12456 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12457 "TARGET_32BIT"
12458 "@
12459 subfc %4,%2,%1\;addze. %4,%3
12460 addic %4,%1,%n2\;addze. %4,%3
12461 #
12462 #"
12463 [(set_attr "type" "compare")
12464 (set_attr "length" "8,8,12,12")])
12465
12466 (define_split
12467 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12468 (compare:CC
12469 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12470 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12471 (match_operand:SI 3 "gpc_reg_operand" ""))
12472 (const_int 0)))
12473 (clobber (match_scratch:SI 4 ""))]
12474 "TARGET_32BIT && reload_completed"
12475 [(set (match_dup 4)
12476 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12477 (match_dup 3)))
12478 (set (match_dup 0)
12479 (compare:CC (match_dup 4)
12480 (const_int 0)))]
12481 "")
12482
12483 (define_insn ""
12484 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12485 (compare:CC
12486 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12487 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12488 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12489 (const_int 0)))
12490 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12491 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12492 "TARGET_32BIT"
12493 "@
12494 subfc %0,%2,%1\;addze. %0,%3
12495 addic %0,%1,%n2\;addze. %0,%3
12496 #
12497 #"
12498 [(set_attr "type" "compare")
12499 (set_attr "length" "8,8,12,12")])
12500
12501 (define_split
12502 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12503 (compare:CC
12504 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12505 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12506 (match_operand:SI 3 "gpc_reg_operand" ""))
12507 (const_int 0)))
12508 (set (match_operand:SI 0 "gpc_reg_operand" "")
12509 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12510 "TARGET_32BIT && reload_completed"
12511 [(set (match_dup 0)
12512 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12513 (set (match_dup 4)
12514 (compare:CC (match_dup 0)
12515 (const_int 0)))]
12516 "")
12517
12518 (define_insn "*neg_geu<mode>"
12519 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12520 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12521 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12522 ""
12523 "@
12524 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12525 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12526 [(set_attr "type" "three")
12527 (set_attr "length" "12")])
12528
12529 (define_insn "*and_neg_geu<mode>"
12530 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12531 (and:P (neg:P
12532 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12533 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12534 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12535 ""
12536 "@
12537 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12538 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12539 [(set_attr "type" "three")
12540 (set_attr "length" "12")])
12541
12542 (define_insn ""
12543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12544 (compare:CC
12545 (and:SI (neg:SI
12546 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12547 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12548 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12549 (const_int 0)))
12550 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12551 "TARGET_32BIT"
12552 "@
12553 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12554 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12555 #
12556 #"
12557 [(set_attr "type" "compare")
12558 (set_attr "length" "12,12,16,16")])
12559
12560 (define_split
12561 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12562 (compare:CC
12563 (and:SI (neg:SI
12564 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12565 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12566 (match_operand:SI 3 "gpc_reg_operand" ""))
12567 (const_int 0)))
12568 (clobber (match_scratch:SI 4 ""))]
12569 "TARGET_32BIT && reload_completed"
12570 [(set (match_dup 4)
12571 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12572 (match_dup 3)))
12573 (set (match_dup 0)
12574 (compare:CC (match_dup 4)
12575 (const_int 0)))]
12576 "")
12577
12578 (define_insn ""
12579 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12580 (compare:CC
12581 (and:SI (neg:SI
12582 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12583 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12584 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12585 (const_int 0)))
12586 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12587 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12588 "TARGET_32BIT"
12589 "@
12590 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12591 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12592 #
12593 #"
12594 [(set_attr "type" "compare")
12595 (set_attr "length" "12,12,16,16")])
12596
12597 (define_split
12598 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12599 (compare:CC
12600 (and:SI (neg:SI
12601 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12602 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12603 (match_operand:SI 3 "gpc_reg_operand" ""))
12604 (const_int 0)))
12605 (set (match_operand:SI 0 "gpc_reg_operand" "")
12606 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12607 "TARGET_32BIT && reload_completed"
12608 [(set (match_dup 0)
12609 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12610 (set (match_dup 4)
12611 (compare:CC (match_dup 0)
12612 (const_int 0)))]
12613 "")
12614
12615 (define_insn "*plus_gt0<mode>"
12616 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12617 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12618 (const_int 0))
12619 (match_operand:P 2 "gpc_reg_operand" "r")))]
12620 ""
12621 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12622 [(set_attr "type" "three")
12623 (set_attr "length" "12")])
12624
12625 (define_insn ""
12626 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12627 (compare:CC
12628 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12629 (const_int 0))
12630 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12631 (const_int 0)))
12632 (clobber (match_scratch:SI 3 "=&r,&r"))]
12633 "TARGET_32BIT"
12634 "@
12635 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12636 #"
12637 [(set_attr "type" "compare")
12638 (set_attr "length" "12,16")])
12639
12640 (define_split
12641 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12642 (compare:CC
12643 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12644 (const_int 0))
12645 (match_operand:SI 2 "gpc_reg_operand" ""))
12646 (const_int 0)))
12647 (clobber (match_scratch:SI 3 ""))]
12648 "TARGET_32BIT && reload_completed"
12649 [(set (match_dup 3)
12650 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12651 (match_dup 2)))
12652 (set (match_dup 0)
12653 (compare:CC (match_dup 3)
12654 (const_int 0)))]
12655 "")
12656
12657 (define_insn ""
12658 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12659 (compare:CC
12660 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12661 (const_int 0))
12662 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12663 (const_int 0)))
12664 (clobber (match_scratch:DI 3 "=&r,&r"))]
12665 "TARGET_64BIT"
12666 "@
12667 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12668 #"
12669 [(set_attr "type" "compare")
12670 (set_attr "length" "12,16")])
12671
12672 (define_split
12673 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12674 (compare:CC
12675 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12676 (const_int 0))
12677 (match_operand:DI 2 "gpc_reg_operand" ""))
12678 (const_int 0)))
12679 (clobber (match_scratch:DI 3 ""))]
12680 "TARGET_64BIT && reload_completed"
12681 [(set (match_dup 3)
12682 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12683 (match_dup 2)))
12684 (set (match_dup 0)
12685 (compare:CC (match_dup 3)
12686 (const_int 0)))]
12687 "")
12688
12689 (define_insn ""
12690 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12691 (compare:CC
12692 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12693 (const_int 0))
12694 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12695 (const_int 0)))
12696 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12697 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12698 "TARGET_32BIT"
12699 "@
12700 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12701 #"
12702 [(set_attr "type" "compare")
12703 (set_attr "length" "12,16")])
12704
12705 (define_split
12706 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12707 (compare:CC
12708 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12709 (const_int 0))
12710 (match_operand:SI 2 "gpc_reg_operand" ""))
12711 (const_int 0)))
12712 (set (match_operand:SI 0 "gpc_reg_operand" "")
12713 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12714 "TARGET_32BIT && reload_completed"
12715 [(set (match_dup 0)
12716 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12717 (set (match_dup 3)
12718 (compare:CC (match_dup 0)
12719 (const_int 0)))]
12720 "")
12721
12722 (define_insn ""
12723 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12724 (compare:CC
12725 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12726 (const_int 0))
12727 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12728 (const_int 0)))
12729 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12730 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12731 "TARGET_64BIT"
12732 "@
12733 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12734 #"
12735 [(set_attr "type" "compare")
12736 (set_attr "length" "12,16")])
12737
12738 (define_split
12739 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12740 (compare:CC
12741 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12742 (const_int 0))
12743 (match_operand:DI 2 "gpc_reg_operand" ""))
12744 (const_int 0)))
12745 (set (match_operand:DI 0 "gpc_reg_operand" "")
12746 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12747 "TARGET_64BIT && reload_completed"
12748 [(set (match_dup 0)
12749 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12750 (set (match_dup 3)
12751 (compare:CC (match_dup 0)
12752 (const_int 0)))]
12753 "")
12754
12755 (define_insn_and_split "*gtu<mode>"
12756 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12757 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12758 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12759 ""
12760 "#"
12761 ""
12762 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12763 (set (match_dup 0) (neg:P (match_dup 0)))]
12764 "")
12765
12766 (define_insn_and_split "*gtu<mode>_compare"
12767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12768 (compare:CC
12769 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12770 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12771 (const_int 0)))
12772 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12773 (gtu:P (match_dup 1) (match_dup 2)))]
12774 ""
12775 "#"
12776 ""
12777 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12778 (parallel [(set (match_dup 3)
12779 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12780 (set (match_dup 0) (neg:P (match_dup 0)))])]
12781 "")
12782
12783 (define_insn_and_split "*plus_gtu<mode>"
12784 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12785 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12786 (match_operand:P 2 "reg_or_short_operand" "rI"))
12787 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12788 ""
12789 "#"
12790 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12791 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12792 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12793 "")
12794
12795 (define_insn_and_split "*plus_gtu<mode>_compare"
12796 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12797 (compare:CC
12798 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12799 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12800 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12801 (const_int 0)))
12802 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12803 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12804 ""
12805 "#"
12806 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12807 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12808 (parallel [(set (match_dup 4)
12809 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12810 (const_int 0)))
12811 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12812 "")
12813
12814 (define_insn "*neg_gtu<mode>"
12815 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12816 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12817 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12818 ""
12819 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12820 [(set_attr "type" "two")
12821 (set_attr "length" "8")])
12822
12823 \f
12824 ;; Define both directions of branch and return. If we need a reload
12825 ;; register, we'd rather use CR0 since it is much easier to copy a
12826 ;; register CC value to there.
12827
12828 (define_insn ""
12829 [(set (pc)
12830 (if_then_else (match_operator 1 "branch_comparison_operator"
12831 [(match_operand 2
12832 "cc_reg_operand" "y")
12833 (const_int 0)])
12834 (label_ref (match_operand 0 "" ""))
12835 (pc)))]
12836 ""
12837 "*
12838 {
12839 return output_cbranch (operands[1], \"%l0\", 0, insn);
12840 }"
12841 [(set_attr "type" "branch")])
12842
12843 (define_insn ""
12844 [(set (pc)
12845 (if_then_else (match_operator 0 "branch_comparison_operator"
12846 [(match_operand 1
12847 "cc_reg_operand" "y")
12848 (const_int 0)])
12849 (any_return)
12850 (pc)))]
12851 "<return_pred>"
12852 "*
12853 {
12854 return output_cbranch (operands[0], NULL, 0, insn);
12855 }"
12856 [(set_attr "type" "jmpreg")
12857 (set_attr "length" "4")])
12858
12859 (define_insn ""
12860 [(set (pc)
12861 (if_then_else (match_operator 1 "branch_comparison_operator"
12862 [(match_operand 2
12863 "cc_reg_operand" "y")
12864 (const_int 0)])
12865 (pc)
12866 (label_ref (match_operand 0 "" ""))))]
12867 ""
12868 "*
12869 {
12870 return output_cbranch (operands[1], \"%l0\", 1, insn);
12871 }"
12872 [(set_attr "type" "branch")])
12873
12874 (define_insn ""
12875 [(set (pc)
12876 (if_then_else (match_operator 0 "branch_comparison_operator"
12877 [(match_operand 1
12878 "cc_reg_operand" "y")
12879 (const_int 0)])
12880 (pc)
12881 (any_return)))]
12882 "<return_pred>"
12883 "*
12884 {
12885 return output_cbranch (operands[0], NULL, 1, insn);
12886 }"
12887 [(set_attr "type" "jmpreg")
12888 (set_attr "length" "4")])
12889
12890 ;; Logic on condition register values.
12891
12892 ; This pattern matches things like
12893 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12894 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12895 ; (const_int 1)))
12896 ; which are generated by the branch logic.
12897 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12898
12899 (define_insn "*cceq_ior_compare"
12900 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12901 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12902 [(match_operator:SI 2
12903 "branch_positive_comparison_operator"
12904 [(match_operand 3
12905 "cc_reg_operand" "y,y")
12906 (const_int 0)])
12907 (match_operator:SI 4
12908 "branch_positive_comparison_operator"
12909 [(match_operand 5
12910 "cc_reg_operand" "0,y")
12911 (const_int 0)])])
12912 (const_int 1)))]
12913 ""
12914 "cr%q1 %E0,%j2,%j4"
12915 [(set_attr "type" "cr_logical,delayed_cr")])
12916
12917 ; Why is the constant -1 here, but 1 in the previous pattern?
12918 ; Because ~1 has all but the low bit set.
12919 (define_insn ""
12920 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12921 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12922 [(not:SI (match_operator:SI 2
12923 "branch_positive_comparison_operator"
12924 [(match_operand 3
12925 "cc_reg_operand" "y,y")
12926 (const_int 0)]))
12927 (match_operator:SI 4
12928 "branch_positive_comparison_operator"
12929 [(match_operand 5
12930 "cc_reg_operand" "0,y")
12931 (const_int 0)])])
12932 (const_int -1)))]
12933 ""
12934 "cr%q1 %E0,%j2,%j4"
12935 [(set_attr "type" "cr_logical,delayed_cr")])
12936
12937 (define_insn "*cceq_rev_compare"
12938 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12939 (compare:CCEQ (match_operator:SI 1
12940 "branch_positive_comparison_operator"
12941 [(match_operand 2
12942 "cc_reg_operand" "0,y")
12943 (const_int 0)])
12944 (const_int 0)))]
12945 ""
12946 "crnot %E0,%j1"
12947 [(set_attr "type" "cr_logical,delayed_cr")])
12948
12949 ;; If we are comparing the result of two comparisons, this can be done
12950 ;; using creqv or crxor.
12951
12952 (define_insn_and_split ""
12953 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12954 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12955 [(match_operand 2 "cc_reg_operand" "y")
12956 (const_int 0)])
12957 (match_operator 3 "branch_comparison_operator"
12958 [(match_operand 4 "cc_reg_operand" "y")
12959 (const_int 0)])))]
12960 ""
12961 "#"
12962 ""
12963 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12964 (match_dup 5)))]
12965 "
12966 {
12967 int positive_1, positive_2;
12968
12969 positive_1 = branch_positive_comparison_operator (operands[1],
12970 GET_MODE (operands[1]));
12971 positive_2 = branch_positive_comparison_operator (operands[3],
12972 GET_MODE (operands[3]));
12973
12974 if (! positive_1)
12975 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
12976 GET_CODE (operands[1])),
12977 SImode,
12978 operands[2], const0_rtx);
12979 else if (GET_MODE (operands[1]) != SImode)
12980 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12981 operands[2], const0_rtx);
12982
12983 if (! positive_2)
12984 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
12985 GET_CODE (operands[3])),
12986 SImode,
12987 operands[4], const0_rtx);
12988 else if (GET_MODE (operands[3]) != SImode)
12989 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12990 operands[4], const0_rtx);
12991
12992 if (positive_1 == positive_2)
12993 {
12994 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12995 operands[5] = constm1_rtx;
12996 }
12997 else
12998 {
12999 operands[5] = const1_rtx;
13000 }
13001 }")
13002
13003 ;; Unconditional branch and return.
13004
13005 (define_insn "jump"
13006 [(set (pc)
13007 (label_ref (match_operand 0 "" "")))]
13008 ""
13009 "b %l0"
13010 [(set_attr "type" "branch")])
13011
13012 (define_insn "<return_str>return"
13013 [(any_return)]
13014 "<return_pred>"
13015 "blr"
13016 [(set_attr "type" "jmpreg")])
13017
13018 (define_expand "indirect_jump"
13019 [(set (pc) (match_operand 0 "register_operand" ""))])
13020
13021 (define_insn "*indirect_jump<mode>"
13022 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13023 ""
13024 "@
13025 bctr
13026 blr"
13027 [(set_attr "type" "jmpreg")])
13028
13029 ;; Table jump for switch statements:
13030 (define_expand "tablejump"
13031 [(use (match_operand 0 "" ""))
13032 (use (label_ref (match_operand 1 "" "")))]
13033 ""
13034 "
13035 {
13036 if (TARGET_32BIT)
13037 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13038 else
13039 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13040 DONE;
13041 }")
13042
13043 (define_expand "tablejumpsi"
13044 [(set (match_dup 3)
13045 (plus:SI (match_operand:SI 0 "" "")
13046 (match_dup 2)))
13047 (parallel [(set (pc) (match_dup 3))
13048 (use (label_ref (match_operand 1 "" "")))])]
13049 "TARGET_32BIT"
13050 "
13051 { operands[0] = force_reg (SImode, operands[0]);
13052 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13053 operands[3] = gen_reg_rtx (SImode);
13054 }")
13055
13056 (define_expand "tablejumpdi"
13057 [(set (match_dup 4)
13058 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13059 (set (match_dup 3)
13060 (plus:DI (match_dup 4)
13061 (match_dup 2)))
13062 (parallel [(set (pc) (match_dup 3))
13063 (use (label_ref (match_operand 1 "" "")))])]
13064 "TARGET_64BIT"
13065 "
13066 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13067 operands[3] = gen_reg_rtx (DImode);
13068 operands[4] = gen_reg_rtx (DImode);
13069 }")
13070
13071 (define_insn "*tablejump<mode>_internal1"
13072 [(set (pc)
13073 (match_operand:P 0 "register_operand" "c,*l"))
13074 (use (label_ref (match_operand 1 "" "")))]
13075 ""
13076 "@
13077 bctr
13078 blr"
13079 [(set_attr "type" "jmpreg")])
13080
13081 (define_insn "nop"
13082 [(const_int 0)]
13083 ""
13084 "nop")
13085
13086 (define_insn "group_ending_nop"
13087 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13088 ""
13089 "*
13090 {
13091 if (rs6000_cpu_attr == CPU_POWER6)
13092 return \"ori 1,1,0\";
13093 return \"ori 2,2,0\";
13094 }")
13095 \f
13096 ;; Define the subtract-one-and-jump insns, starting with the template
13097 ;; so loop.c knows what to generate.
13098
13099 (define_expand "doloop_end"
13100 [(use (match_operand 0 "" "")) ; loop pseudo
13101 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13102 (use (match_operand 2 "" "")) ; max iterations
13103 (use (match_operand 3 "" "")) ; loop level
13104 (use (match_operand 4 "" "")) ; label
13105 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
13106 ""
13107 "
13108 {
13109 /* Only use this on innermost loops. */
13110 if (INTVAL (operands[3]) > 1)
13111 FAIL;
13112 if (TARGET_64BIT)
13113 {
13114 if (GET_MODE (operands[0]) != DImode)
13115 FAIL;
13116 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13117 }
13118 else
13119 {
13120 if (GET_MODE (operands[0]) != SImode)
13121 FAIL;
13122 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13123 }
13124 DONE;
13125 }")
13126
13127 (define_expand "ctr<mode>"
13128 [(parallel [(set (pc)
13129 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13130 (const_int 1))
13131 (label_ref (match_operand 1 "" ""))
13132 (pc)))
13133 (set (match_dup 0)
13134 (plus:P (match_dup 0)
13135 (const_int -1)))
13136 (clobber (match_scratch:CC 2 ""))
13137 (clobber (match_scratch:P 3 ""))])]
13138 ""
13139 "")
13140
13141 ;; We need to be able to do this for any operand, including MEM, or we
13142 ;; will cause reload to blow up since we don't allow output reloads on
13143 ;; JUMP_INSNs.
13144 ;; For the length attribute to be calculated correctly, the
13145 ;; label MUST be operand 0.
13146
13147 (define_insn "*ctr<mode>_internal1"
13148 [(set (pc)
13149 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13150 (const_int 1))
13151 (label_ref (match_operand 0 "" ""))
13152 (pc)))
13153 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13154 (plus:P (match_dup 1)
13155 (const_int -1)))
13156 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13157 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13158 ""
13159 "*
13160 {
13161 if (which_alternative != 0)
13162 return \"#\";
13163 else if (get_attr_length (insn) == 4)
13164 return \"bdnz %l0\";
13165 else
13166 return \"bdz $+8\;b %l0\";
13167 }"
13168 [(set_attr "type" "branch")
13169 (set_attr "length" "*,12,16,16")])
13170
13171 (define_insn "*ctr<mode>_internal2"
13172 [(set (pc)
13173 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13174 (const_int 1))
13175 (pc)
13176 (label_ref (match_operand 0 "" ""))))
13177 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13178 (plus:P (match_dup 1)
13179 (const_int -1)))
13180 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13181 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13182 ""
13183 "*
13184 {
13185 if (which_alternative != 0)
13186 return \"#\";
13187 else if (get_attr_length (insn) == 4)
13188 return \"bdz %l0\";
13189 else
13190 return \"bdnz $+8\;b %l0\";
13191 }"
13192 [(set_attr "type" "branch")
13193 (set_attr "length" "*,12,16,16")])
13194
13195 ;; Similar but use EQ
13196
13197 (define_insn "*ctr<mode>_internal5"
13198 [(set (pc)
13199 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13200 (const_int 1))
13201 (label_ref (match_operand 0 "" ""))
13202 (pc)))
13203 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13204 (plus:P (match_dup 1)
13205 (const_int -1)))
13206 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13207 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13208 ""
13209 "*
13210 {
13211 if (which_alternative != 0)
13212 return \"#\";
13213 else if (get_attr_length (insn) == 4)
13214 return \"bdz %l0\";
13215 else
13216 return \"bdnz $+8\;b %l0\";
13217 }"
13218 [(set_attr "type" "branch")
13219 (set_attr "length" "*,12,16,16")])
13220
13221 (define_insn "*ctr<mode>_internal6"
13222 [(set (pc)
13223 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13224 (const_int 1))
13225 (pc)
13226 (label_ref (match_operand 0 "" ""))))
13227 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13228 (plus:P (match_dup 1)
13229 (const_int -1)))
13230 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13231 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13232 ""
13233 "*
13234 {
13235 if (which_alternative != 0)
13236 return \"#\";
13237 else if (get_attr_length (insn) == 4)
13238 return \"bdnz %l0\";
13239 else
13240 return \"bdz $+8\;b %l0\";
13241 }"
13242 [(set_attr "type" "branch")
13243 (set_attr "length" "*,12,16,16")])
13244
13245 ;; Now the splitters if we could not allocate the CTR register
13246
13247 (define_split
13248 [(set (pc)
13249 (if_then_else (match_operator 2 "comparison_operator"
13250 [(match_operand:P 1 "gpc_reg_operand" "")
13251 (const_int 1)])
13252 (match_operand 5 "" "")
13253 (match_operand 6 "" "")))
13254 (set (match_operand:P 0 "gpc_reg_operand" "")
13255 (plus:P (match_dup 1) (const_int -1)))
13256 (clobber (match_scratch:CC 3 ""))
13257 (clobber (match_scratch:P 4 ""))]
13258 "reload_completed"
13259 [(parallel [(set (match_dup 3)
13260 (compare:CC (plus:P (match_dup 1)
13261 (const_int -1))
13262 (const_int 0)))
13263 (set (match_dup 0)
13264 (plus:P (match_dup 1)
13265 (const_int -1)))])
13266 (set (pc) (if_then_else (match_dup 7)
13267 (match_dup 5)
13268 (match_dup 6)))]
13269 "
13270 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13271 operands[3], const0_rtx); }")
13272
13273 (define_split
13274 [(set (pc)
13275 (if_then_else (match_operator 2 "comparison_operator"
13276 [(match_operand:P 1 "gpc_reg_operand" "")
13277 (const_int 1)])
13278 (match_operand 5 "" "")
13279 (match_operand 6 "" "")))
13280 (set (match_operand:P 0 "nonimmediate_operand" "")
13281 (plus:P (match_dup 1) (const_int -1)))
13282 (clobber (match_scratch:CC 3 ""))
13283 (clobber (match_scratch:P 4 ""))]
13284 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13285 [(parallel [(set (match_dup 3)
13286 (compare:CC (plus:P (match_dup 1)
13287 (const_int -1))
13288 (const_int 0)))
13289 (set (match_dup 4)
13290 (plus:P (match_dup 1)
13291 (const_int -1)))])
13292 (set (match_dup 0)
13293 (match_dup 4))
13294 (set (pc) (if_then_else (match_dup 7)
13295 (match_dup 5)
13296 (match_dup 6)))]
13297 "
13298 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13299 operands[3], const0_rtx); }")
13300 \f
13301 (define_insn "trap"
13302 [(trap_if (const_int 1) (const_int 0))]
13303 ""
13304 "trap"
13305 [(set_attr "type" "trap")])
13306
13307 (define_expand "ctrap<mode>4"
13308 [(trap_if (match_operator 0 "ordered_comparison_operator"
13309 [(match_operand:GPR 1 "register_operand")
13310 (match_operand:GPR 2 "reg_or_short_operand")])
13311 (match_operand 3 "zero_constant" ""))]
13312 ""
13313 "")
13314
13315 (define_insn ""
13316 [(trap_if (match_operator 0 "ordered_comparison_operator"
13317 [(match_operand:GPR 1 "register_operand" "r")
13318 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13319 (const_int 0))]
13320 ""
13321 "t<wd>%V0%I2 %1,%2"
13322 [(set_attr "type" "trap")])
13323 \f
13324 ;; Insns related to generating the function prologue and epilogue.
13325
13326 (define_expand "prologue"
13327 [(use (const_int 0))]
13328 ""
13329 {
13330 rs6000_emit_prologue ();
13331 if (!TARGET_SCHED_PROLOG)
13332 emit_insn (gen_blockage ());
13333 DONE;
13334 })
13335
13336 (define_insn "*movesi_from_cr_one"
13337 [(match_parallel 0 "mfcr_operation"
13338 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13339 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13340 (match_operand 3 "immediate_operand" "n")]
13341 UNSPEC_MOVESI_FROM_CR))])]
13342 "TARGET_MFCRF"
13343 "*
13344 {
13345 int mask = 0;
13346 int i;
13347 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13348 {
13349 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13350 operands[4] = GEN_INT (mask);
13351 output_asm_insn (\"mfcr %1,%4\", operands);
13352 }
13353 return \"\";
13354 }"
13355 [(set_attr "type" "mfcrf")])
13356
13357 (define_insn "movesi_from_cr"
13358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13359 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13360 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13361 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13362 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13363 UNSPEC_MOVESI_FROM_CR))]
13364 ""
13365 "mfcr %0"
13366 [(set_attr "type" "mfcr")])
13367
13368 (define_insn "*stmw"
13369 [(match_parallel 0 "stmw_operation"
13370 [(set (match_operand:SI 1 "memory_operand" "=m")
13371 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13372 "TARGET_MULTIPLE"
13373 "stmw %2,%1"
13374 [(set_attr "type" "store_ux")])
13375
13376 ; The following comment applies to:
13377 ; save_gpregs_*
13378 ; save_fpregs_*
13379 ; restore_gpregs*
13380 ; return_and_restore_gpregs*
13381 ; return_and_restore_fpregs*
13382 ; return_and_restore_fpregs_aix*
13383 ;
13384 ; The out-of-line save / restore functions expects one input argument.
13385 ; Since those are not standard call_insn's, we must avoid using
13386 ; MATCH_OPERAND for that argument. That way the register rename
13387 ; optimization will not try to rename this register.
13388 ; Each pattern is repeated for each possible register number used in
13389 ; various ABIs (r11, r1, and for some functions r12)
13390
13391 (define_insn "*save_gpregs_<mode>_r11"
13392 [(match_parallel 0 "any_parallel_operand"
13393 [(clobber (reg:P 65))
13394 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13395 (use (reg:P 11))
13396 (set (match_operand:P 2 "memory_operand" "=m")
13397 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13398 ""
13399 "bl %1"
13400 [(set_attr "type" "branch")
13401 (set_attr "length" "4")])
13402
13403 (define_insn "*save_gpregs_<mode>_r12"
13404 [(match_parallel 0 "any_parallel_operand"
13405 [(clobber (reg:P 65))
13406 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13407 (use (reg:P 12))
13408 (set (match_operand:P 2 "memory_operand" "=m")
13409 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13410 ""
13411 "bl %1"
13412 [(set_attr "type" "branch")
13413 (set_attr "length" "4")])
13414
13415 (define_insn "*save_gpregs_<mode>_r1"
13416 [(match_parallel 0 "any_parallel_operand"
13417 [(clobber (reg:P 65))
13418 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13419 (use (reg:P 1))
13420 (set (match_operand:P 2 "memory_operand" "=m")
13421 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13422 ""
13423 "bl %1"
13424 [(set_attr "type" "branch")
13425 (set_attr "length" "4")])
13426
13427 (define_insn "*save_fpregs_<mode>_r11"
13428 [(match_parallel 0 "any_parallel_operand"
13429 [(clobber (reg:P 65))
13430 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13431 (use (reg:P 11))
13432 (set (match_operand:DF 2 "memory_operand" "=m")
13433 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13434 ""
13435 "bl %1"
13436 [(set_attr "type" "branch")
13437 (set_attr "length" "4")])
13438
13439 (define_insn "*save_fpregs_<mode>_r12"
13440 [(match_parallel 0 "any_parallel_operand"
13441 [(clobber (reg:P 65))
13442 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13443 (use (reg:P 12))
13444 (set (match_operand:DF 2 "memory_operand" "=m")
13445 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13446 ""
13447 "bl %1"
13448 [(set_attr "type" "branch")
13449 (set_attr "length" "4")])
13450
13451 (define_insn "*save_fpregs_<mode>_r1"
13452 [(match_parallel 0 "any_parallel_operand"
13453 [(clobber (reg:P 65))
13454 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13455 (use (reg:P 1))
13456 (set (match_operand:DF 2 "memory_operand" "=m")
13457 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13458 ""
13459 "bl %1"
13460 [(set_attr "type" "branch")
13461 (set_attr "length" "4")])
13462
13463 ; This is to explain that changes to the stack pointer should
13464 ; not be moved over loads from or stores to stack memory.
13465 (define_insn "stack_tie"
13466 [(match_parallel 0 "tie_operand"
13467 [(set (mem:BLK (reg 1)) (const_int 0))])]
13468 ""
13469 ""
13470 [(set_attr "length" "0")])
13471
13472 (define_expand "epilogue"
13473 [(use (const_int 0))]
13474 ""
13475 {
13476 if (!TARGET_SCHED_PROLOG)
13477 emit_insn (gen_blockage ());
13478 rs6000_emit_epilogue (FALSE);
13479 DONE;
13480 })
13481
13482 ; On some processors, doing the mtcrf one CC register at a time is
13483 ; faster (like on the 604e). On others, doing them all at once is
13484 ; faster; for instance, on the 601 and 750.
13485
13486 (define_expand "movsi_to_cr_one"
13487 [(set (match_operand:CC 0 "cc_reg_operand" "")
13488 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13489 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13490 ""
13491 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13492
13493 (define_insn "*movsi_to_cr"
13494 [(match_parallel 0 "mtcrf_operation"
13495 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13496 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13497 (match_operand 3 "immediate_operand" "n")]
13498 UNSPEC_MOVESI_TO_CR))])]
13499 ""
13500 "*
13501 {
13502 int mask = 0;
13503 int i;
13504 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13505 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13506 operands[4] = GEN_INT (mask);
13507 return \"mtcrf %4,%2\";
13508 }"
13509 [(set_attr "type" "mtcr")])
13510
13511 (define_insn "*mtcrfsi"
13512 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13513 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13514 (match_operand 2 "immediate_operand" "n")]
13515 UNSPEC_MOVESI_TO_CR))]
13516 "GET_CODE (operands[0]) == REG
13517 && CR_REGNO_P (REGNO (operands[0]))
13518 && GET_CODE (operands[2]) == CONST_INT
13519 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13520 "mtcrf %R0,%1"
13521 [(set_attr "type" "mtcr")])
13522
13523 ; The load-multiple instructions have similar properties.
13524 ; Note that "load_multiple" is a name known to the machine-independent
13525 ; code that actually corresponds to the PowerPC load-string.
13526
13527 (define_insn "*lmw"
13528 [(match_parallel 0 "lmw_operation"
13529 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13530 (match_operand:SI 2 "memory_operand" "m"))])]
13531 "TARGET_MULTIPLE"
13532 "lmw %1,%2"
13533 [(set_attr "type" "load_ux")
13534 (set_attr "cell_micro" "always")])
13535
13536 (define_insn "*return_internal_<mode>"
13537 [(simple_return)
13538 (use (match_operand:P 0 "register_operand" "lc"))]
13539 ""
13540 "b%T0"
13541 [(set_attr "type" "jmpreg")])
13542
13543 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13544 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13545
13546 ; The following comment applies to:
13547 ; save_gpregs_*
13548 ; save_fpregs_*
13549 ; restore_gpregs*
13550 ; return_and_restore_gpregs*
13551 ; return_and_restore_fpregs*
13552 ; return_and_restore_fpregs_aix*
13553 ;
13554 ; The out-of-line save / restore functions expects one input argument.
13555 ; Since those are not standard call_insn's, we must avoid using
13556 ; MATCH_OPERAND for that argument. That way the register rename
13557 ; optimization will not try to rename this register.
13558 ; Each pattern is repeated for each possible register number used in
13559 ; various ABIs (r11, r1, and for some functions r12)
13560
13561 (define_insn "*restore_gpregs_<mode>_r11"
13562 [(match_parallel 0 "any_parallel_operand"
13563 [(clobber (match_operand:P 1 "register_operand" "=l"))
13564 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13565 (use (reg:P 11))
13566 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13567 (match_operand:P 4 "memory_operand" "m"))])]
13568 ""
13569 "bl %2"
13570 [(set_attr "type" "branch")
13571 (set_attr "length" "4")])
13572
13573 (define_insn "*restore_gpregs_<mode>_r12"
13574 [(match_parallel 0 "any_parallel_operand"
13575 [(clobber (match_operand:P 1 "register_operand" "=l"))
13576 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13577 (use (reg:P 12))
13578 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13579 (match_operand:P 4 "memory_operand" "m"))])]
13580 ""
13581 "bl %2"
13582 [(set_attr "type" "branch")
13583 (set_attr "length" "4")])
13584
13585 (define_insn "*restore_gpregs_<mode>_r1"
13586 [(match_parallel 0 "any_parallel_operand"
13587 [(clobber (match_operand:P 1 "register_operand" "=l"))
13588 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13589 (use (reg:P 1))
13590 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13591 (match_operand:P 4 "memory_operand" "m"))])]
13592 ""
13593 "bl %2"
13594 [(set_attr "type" "branch")
13595 (set_attr "length" "4")])
13596
13597 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13598 [(match_parallel 0 "any_parallel_operand"
13599 [(return)
13600 (clobber (match_operand:P 1 "register_operand" "=l"))
13601 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13602 (use (reg:P 11))
13603 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13604 (match_operand:P 4 "memory_operand" "m"))])]
13605 ""
13606 "b %2"
13607 [(set_attr "type" "branch")
13608 (set_attr "length" "4")])
13609
13610 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13611 [(match_parallel 0 "any_parallel_operand"
13612 [(return)
13613 (clobber (match_operand:P 1 "register_operand" "=l"))
13614 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13615 (use (reg:P 12))
13616 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13617 (match_operand:P 4 "memory_operand" "m"))])]
13618 ""
13619 "b %2"
13620 [(set_attr "type" "branch")
13621 (set_attr "length" "4")])
13622
13623 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13624 [(match_parallel 0 "any_parallel_operand"
13625 [(return)
13626 (clobber (match_operand:P 1 "register_operand" "=l"))
13627 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13628 (use (reg:P 1))
13629 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13630 (match_operand:P 4 "memory_operand" "m"))])]
13631 ""
13632 "b %2"
13633 [(set_attr "type" "branch")
13634 (set_attr "length" "4")])
13635
13636 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13637 [(match_parallel 0 "any_parallel_operand"
13638 [(return)
13639 (clobber (match_operand:P 1 "register_operand" "=l"))
13640 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13641 (use (reg:P 11))
13642 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13643 (match_operand:DF 4 "memory_operand" "m"))])]
13644 ""
13645 "b %2"
13646 [(set_attr "type" "branch")
13647 (set_attr "length" "4")])
13648
13649 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13650 [(match_parallel 0 "any_parallel_operand"
13651 [(return)
13652 (clobber (match_operand:P 1 "register_operand" "=l"))
13653 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13654 (use (reg:P 12))
13655 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13656 (match_operand:DF 4 "memory_operand" "m"))])]
13657 ""
13658 "b %2"
13659 [(set_attr "type" "branch")
13660 (set_attr "length" "4")])
13661
13662 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13663 [(match_parallel 0 "any_parallel_operand"
13664 [(return)
13665 (clobber (match_operand:P 1 "register_operand" "=l"))
13666 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13667 (use (reg:P 1))
13668 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13669 (match_operand:DF 4 "memory_operand" "m"))])]
13670 ""
13671 "b %2"
13672 [(set_attr "type" "branch")
13673 (set_attr "length" "4")])
13674
13675 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13676 [(match_parallel 0 "any_parallel_operand"
13677 [(return)
13678 (use (match_operand:P 1 "register_operand" "l"))
13679 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13680 (use (reg:P 11))
13681 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13682 (match_operand:DF 4 "memory_operand" "m"))])]
13683 ""
13684 "b %2"
13685 [(set_attr "type" "branch")
13686 (set_attr "length" "4")])
13687
13688 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
13689 [(match_parallel 0 "any_parallel_operand"
13690 [(return)
13691 (use (match_operand:P 1 "register_operand" "l"))
13692 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13693 (use (reg:P 1))
13694 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13695 (match_operand:DF 4 "memory_operand" "m"))])]
13696 ""
13697 "b %2"
13698 [(set_attr "type" "branch")
13699 (set_attr "length" "4")])
13700
13701 ; This is used in compiling the unwind routines.
13702 (define_expand "eh_return"
13703 [(use (match_operand 0 "general_operand" ""))]
13704 ""
13705 "
13706 {
13707 if (TARGET_32BIT)
13708 emit_insn (gen_eh_set_lr_si (operands[0]));
13709 else
13710 emit_insn (gen_eh_set_lr_di (operands[0]));
13711 DONE;
13712 }")
13713
13714 ; We can't expand this before we know where the link register is stored.
13715 (define_insn "eh_set_lr_<mode>"
13716 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13717 UNSPECV_EH_RR)
13718 (clobber (match_scratch:P 1 "=&b"))]
13719 ""
13720 "#")
13721
13722 (define_split
13723 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13724 (clobber (match_scratch 1 ""))]
13725 "reload_completed"
13726 [(const_int 0)]
13727 "
13728 {
13729 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13730 DONE;
13731 }")
13732
13733 (define_insn "prefetch"
13734 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13735 (match_operand:SI 1 "const_int_operand" "n")
13736 (match_operand:SI 2 "const_int_operand" "n"))]
13737 ""
13738 "*
13739 {
13740 if (GET_CODE (operands[0]) == REG)
13741 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13742 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13743 }"
13744 [(set_attr "type" "load")])
13745 \f
13746 (define_insn "bpermd_<mode>"
13747 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13748 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
13749 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
13750 "TARGET_POPCNTD"
13751 "bpermd %0,%1,%2"
13752 [(set_attr "type" "integer")])
13753
13754 \f
13755 ;; Builtin fma support. Handle
13756 ;; Note that the conditions for expansion are in the FMA_F iterator.
13757
13758 (define_expand "fma<mode>4"
13759 [(set (match_operand:FMA_F 0 "register_operand" "")
13760 (fma:FMA_F
13761 (match_operand:FMA_F 1 "register_operand" "")
13762 (match_operand:FMA_F 2 "register_operand" "")
13763 (match_operand:FMA_F 3 "register_operand" "")))]
13764 ""
13765 "")
13766
13767 ; Altivec only has fma and nfms.
13768 (define_expand "fms<mode>4"
13769 [(set (match_operand:FMA_F 0 "register_operand" "")
13770 (fma:FMA_F
13771 (match_operand:FMA_F 1 "register_operand" "")
13772 (match_operand:FMA_F 2 "register_operand" "")
13773 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
13774 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13775 "")
13776
13777 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
13778 (define_expand "fnma<mode>4"
13779 [(set (match_operand:FMA_F 0 "register_operand" "")
13780 (neg:FMA_F
13781 (fma:FMA_F
13782 (match_operand:FMA_F 1 "register_operand" "")
13783 (match_operand:FMA_F 2 "register_operand" "")
13784 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13785 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
13786 "")
13787
13788 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
13789 (define_expand "fnms<mode>4"
13790 [(set (match_operand:FMA_F 0 "register_operand" "")
13791 (neg:FMA_F
13792 (fma:FMA_F
13793 (match_operand:FMA_F 1 "register_operand" "")
13794 (match_operand:FMA_F 2 "register_operand" "")
13795 (match_operand:FMA_F 3 "register_operand" ""))))]
13796 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13797 "")
13798
13799 ; Not an official optab name, but used from builtins.
13800 (define_expand "nfma<mode>4"
13801 [(set (match_operand:FMA_F 0 "register_operand" "")
13802 (neg:FMA_F
13803 (fma:FMA_F
13804 (match_operand:FMA_F 1 "register_operand" "")
13805 (match_operand:FMA_F 2 "register_operand" "")
13806 (match_operand:FMA_F 3 "register_operand" ""))))]
13807 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13808 "")
13809
13810 ; Not an official optab name, but used from builtins.
13811 (define_expand "nfms<mode>4"
13812 [(set (match_operand:FMA_F 0 "register_operand" "")
13813 (neg:FMA_F
13814 (fma:FMA_F
13815 (match_operand:FMA_F 1 "register_operand" "")
13816 (match_operand:FMA_F 2 "register_operand" "")
13817 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13818 ""
13819 "")
13820
13821 (define_expand "rs6000_get_timebase"
13822 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
13823 ""
13824 {
13825 if (TARGET_POWERPC64)
13826 emit_insn (gen_rs6000_mftb_di (operands[0]));
13827 else
13828 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
13829 DONE;
13830 })
13831
13832 (define_insn "rs6000_get_timebase_ppc32"
13833 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13834 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
13835 (clobber (match_scratch:SI 1 "=r"))
13836 (clobber (match_scratch:CC 2 "=y"))]
13837 "!TARGET_POWERPC64"
13838 {
13839 if (WORDS_BIG_ENDIAN)
13840 if (TARGET_MFCRF)
13841 {
13842 return "mfspr %0,269\;"
13843 "mfspr %L0,268\;"
13844 "mfspr %1,269\;"
13845 "cmpw %2,%0,%1\;"
13846 "bne- %2,$-16";
13847 }
13848 else
13849 {
13850 return "mftbu %0\;"
13851 "mftb %L0\;"
13852 "mftbu %1\;"
13853 "cmpw %2,%0,%1\;"
13854 "bne- %2,$-16";
13855 }
13856 else
13857 if (TARGET_MFCRF)
13858 {
13859 return "mfspr %L0,269\;"
13860 "mfspr %0,268\;"
13861 "mfspr %1,269\;"
13862 "cmpw %2,%L0,%1\;"
13863 "bne- %2,$-16";
13864 }
13865 else
13866 {
13867 return "mftbu %L0\;"
13868 "mftb %0\;"
13869 "mftbu %1\;"
13870 "cmpw %2,%L0,%1\;"
13871 "bne- %2,$-16";
13872 }
13873 })
13874
13875 (define_insn "rs6000_mftb_<mode>"
13876 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13877 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
13878 ""
13879 {
13880 if (TARGET_MFCRF)
13881 return "mfspr %0,268";
13882 else
13883 return "mftb %0";
13884 })
13885
13886 \f
13887
13888 (include "sync.md")
13889 (include "vector.md")
13890 (include "vsx.md")
13891 (include "altivec.md")
13892 (include "spe.md")
13893 (include "dfp.md")
13894 (include "paired.md")