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[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5
6 ;; This file is part of GCC.
7
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
12
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 ;; MA 02110-1301, USA.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; UNSPEC usage
27 ;;
28
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
54 (UNSPEC_STFIWX 32)
55 (UNSPEC_POPCNTB 33)
56 (UNSPEC_FRES 34)
57 (UNSPEC_SP_SET 35)
58 (UNSPEC_SP_TEST 36)
59 (UNSPEC_SYNC 37)
60 (UNSPEC_LWSYNC 38)
61 (UNSPEC_ISYNC 39)
62 (UNSPEC_SYNC_OP 40)
63 (UNSPEC_ATOMIC 41)
64 (UNSPEC_CMPXCHG 42)
65 (UNSPEC_XCHG 43)
66 (UNSPEC_AND 44)
67 ])
68
69 ;;
70 ;; UNSPEC_VOLATILE usage
71 ;;
72
73 (define_constants
74 [(UNSPECV_BLOCK 0)
75 (UNSPECV_LL 1) ; load-locked
76 (UNSPECV_SC 2) ; store-conditional
77 (UNSPECV_EH_RR 9) ; eh_reg_restore
78 ])
79 \f
80 ;; Define an insn type attribute. This is used in function unit delay
81 ;; computations.
82 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
83 (const_string "integer"))
84
85 ;; Length (in bytes).
86 ; '(pc)' in the following doesn't include the instruction itself; it is
87 ; calculated as if the instruction had zero size.
88 (define_attr "length" ""
89 (if_then_else (eq_attr "type" "branch")
90 (if_then_else (and (ge (minus (match_dup 0) (pc))
91 (const_int -32768))
92 (lt (minus (match_dup 0) (pc))
93 (const_int 32764)))
94 (const_int 4)
95 (const_int 8))
96 (const_int 4)))
97
98 ;; Processor type -- this attribute must exactly match the processor_type
99 ;; enumeration in rs6000.h.
100
101 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
102 (const (symbol_ref "rs6000_cpu_attr")))
103
104 (automata_option "ndfa")
105
106 (include "rios1.md")
107 (include "rios2.md")
108 (include "rs64.md")
109 (include "mpc.md")
110 (include "40x.md")
111 (include "440.md")
112 (include "603.md")
113 (include "6xx.md")
114 (include "7xx.md")
115 (include "7450.md")
116 (include "8540.md")
117 (include "power4.md")
118 (include "power5.md")
119
120 (include "predicates.md")
121
122 (include "darwin.md")
123
124 \f
125 ;; Mode macros
126
127 ; This mode macro allows :GPR to be used to indicate the allowable size
128 ; of whole values in GPRs.
129 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
130
131 ; Any supported integer mode.
132 (define_mode_macro INT [QI HI SI DI TI])
133
134 ; Any supported integer mode that fits in one register.
135 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
136
137 ; SImode or DImode, even if DImode doesn't fit in GPRs.
138 (define_mode_macro SDI [SI DI])
139
140 ; The size of a pointer. Also, the size of the value that a record-condition
141 ; (one with a '.') will compare.
142 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
143
144 ; Any hardware-supported floating-point mode
145 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
146 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
147 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
148 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
149
150 ; Various instructions that come in SI and DI forms.
151 ; A generic w/d attribute, for things like cmpw/cmpd.
152 (define_mode_attr wd [(SI "w") (DI "d")])
153
154 \f
155 ;; Start with fixed-point load and store insns. Here we put only the more
156 ;; complex forms. Basic data transfer is done later.
157
158 (define_expand "zero_extendqidi2"
159 [(set (match_operand:DI 0 "gpc_reg_operand" "")
160 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
161 "TARGET_POWERPC64"
162 "")
163
164 (define_insn ""
165 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
166 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
167 "TARGET_POWERPC64"
168 "@
169 lbz%U1%X1 %0,%1
170 rldicl %0,%1,0,56"
171 [(set_attr "type" "load,*")])
172
173 (define_insn ""
174 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
175 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
176 (const_int 0)))
177 (clobber (match_scratch:DI 2 "=r,r"))]
178 "TARGET_64BIT"
179 "@
180 rldicl. %2,%1,0,56
181 #"
182 [(set_attr "type" "compare")
183 (set_attr "length" "4,8")])
184
185 (define_split
186 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
187 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
188 (const_int 0)))
189 (clobber (match_scratch:DI 2 ""))]
190 "TARGET_POWERPC64 && reload_completed"
191 [(set (match_dup 2)
192 (zero_extend:DI (match_dup 1)))
193 (set (match_dup 0)
194 (compare:CC (match_dup 2)
195 (const_int 0)))]
196 "")
197
198 (define_insn ""
199 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
200 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
201 (const_int 0)))
202 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
203 (zero_extend:DI (match_dup 1)))]
204 "TARGET_64BIT"
205 "@
206 rldicl. %0,%1,0,56
207 #"
208 [(set_attr "type" "compare")
209 (set_attr "length" "4,8")])
210
211 (define_split
212 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
213 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
214 (const_int 0)))
215 (set (match_operand:DI 0 "gpc_reg_operand" "")
216 (zero_extend:DI (match_dup 1)))]
217 "TARGET_POWERPC64 && reload_completed"
218 [(set (match_dup 0)
219 (zero_extend:DI (match_dup 1)))
220 (set (match_dup 2)
221 (compare:CC (match_dup 0)
222 (const_int 0)))]
223 "")
224
225 (define_insn "extendqidi2"
226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
227 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
228 "TARGET_POWERPC64"
229 "extsb %0,%1")
230
231 (define_insn ""
232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
233 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
234 (const_int 0)))
235 (clobber (match_scratch:DI 2 "=r,r"))]
236 "TARGET_64BIT"
237 "@
238 extsb. %2,%1
239 #"
240 [(set_attr "type" "compare")
241 (set_attr "length" "4,8")])
242
243 (define_split
244 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
245 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
246 (const_int 0)))
247 (clobber (match_scratch:DI 2 ""))]
248 "TARGET_POWERPC64 && reload_completed"
249 [(set (match_dup 2)
250 (sign_extend:DI (match_dup 1)))
251 (set (match_dup 0)
252 (compare:CC (match_dup 2)
253 (const_int 0)))]
254 "")
255
256 (define_insn ""
257 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
258 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
259 (const_int 0)))
260 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
261 (sign_extend:DI (match_dup 1)))]
262 "TARGET_64BIT"
263 "@
264 extsb. %0,%1
265 #"
266 [(set_attr "type" "compare")
267 (set_attr "length" "4,8")])
268
269 (define_split
270 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
271 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
272 (const_int 0)))
273 (set (match_operand:DI 0 "gpc_reg_operand" "")
274 (sign_extend:DI (match_dup 1)))]
275 "TARGET_POWERPC64 && reload_completed"
276 [(set (match_dup 0)
277 (sign_extend:DI (match_dup 1)))
278 (set (match_dup 2)
279 (compare:CC (match_dup 0)
280 (const_int 0)))]
281 "")
282
283 (define_expand "zero_extendhidi2"
284 [(set (match_operand:DI 0 "gpc_reg_operand" "")
285 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
286 "TARGET_POWERPC64"
287 "")
288
289 (define_insn ""
290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
291 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
292 "TARGET_POWERPC64"
293 "@
294 lhz%U1%X1 %0,%1
295 rldicl %0,%1,0,48"
296 [(set_attr "type" "load,*")])
297
298 (define_insn ""
299 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
300 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
301 (const_int 0)))
302 (clobber (match_scratch:DI 2 "=r,r"))]
303 "TARGET_64BIT"
304 "@
305 rldicl. %2,%1,0,48
306 #"
307 [(set_attr "type" "compare")
308 (set_attr "length" "4,8")])
309
310 (define_split
311 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
312 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
313 (const_int 0)))
314 (clobber (match_scratch:DI 2 ""))]
315 "TARGET_POWERPC64 && reload_completed"
316 [(set (match_dup 2)
317 (zero_extend:DI (match_dup 1)))
318 (set (match_dup 0)
319 (compare:CC (match_dup 2)
320 (const_int 0)))]
321 "")
322
323 (define_insn ""
324 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
325 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
326 (const_int 0)))
327 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
328 (zero_extend:DI (match_dup 1)))]
329 "TARGET_64BIT"
330 "@
331 rldicl. %0,%1,0,48
332 #"
333 [(set_attr "type" "compare")
334 (set_attr "length" "4,8")])
335
336 (define_split
337 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
338 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
339 (const_int 0)))
340 (set (match_operand:DI 0 "gpc_reg_operand" "")
341 (zero_extend:DI (match_dup 1)))]
342 "TARGET_POWERPC64 && reload_completed"
343 [(set (match_dup 0)
344 (zero_extend:DI (match_dup 1)))
345 (set (match_dup 2)
346 (compare:CC (match_dup 0)
347 (const_int 0)))]
348 "")
349
350 (define_expand "extendhidi2"
351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
352 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
353 "TARGET_POWERPC64"
354 "")
355
356 (define_insn ""
357 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
358 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
359 "TARGET_POWERPC64"
360 "@
361 lha%U1%X1 %0,%1
362 extsh %0,%1"
363 [(set_attr "type" "load_ext,*")])
364
365 (define_insn ""
366 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
367 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
368 (const_int 0)))
369 (clobber (match_scratch:DI 2 "=r,r"))]
370 "TARGET_64BIT"
371 "@
372 extsh. %2,%1
373 #"
374 [(set_attr "type" "compare")
375 (set_attr "length" "4,8")])
376
377 (define_split
378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
379 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
380 (const_int 0)))
381 (clobber (match_scratch:DI 2 ""))]
382 "TARGET_POWERPC64 && reload_completed"
383 [(set (match_dup 2)
384 (sign_extend:DI (match_dup 1)))
385 (set (match_dup 0)
386 (compare:CC (match_dup 2)
387 (const_int 0)))]
388 "")
389
390 (define_insn ""
391 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
392 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
393 (const_int 0)))
394 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
395 (sign_extend:DI (match_dup 1)))]
396 "TARGET_64BIT"
397 "@
398 extsh. %0,%1
399 #"
400 [(set_attr "type" "compare")
401 (set_attr "length" "4,8")])
402
403 (define_split
404 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
405 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
406 (const_int 0)))
407 (set (match_operand:DI 0 "gpc_reg_operand" "")
408 (sign_extend:DI (match_dup 1)))]
409 "TARGET_POWERPC64 && reload_completed"
410 [(set (match_dup 0)
411 (sign_extend:DI (match_dup 1)))
412 (set (match_dup 2)
413 (compare:CC (match_dup 0)
414 (const_int 0)))]
415 "")
416
417 (define_expand "zero_extendsidi2"
418 [(set (match_operand:DI 0 "gpc_reg_operand" "")
419 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
420 "TARGET_POWERPC64"
421 "")
422
423 (define_insn ""
424 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
425 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
426 "TARGET_POWERPC64"
427 "@
428 lwz%U1%X1 %0,%1
429 rldicl %0,%1,0,32"
430 [(set_attr "type" "load,*")])
431
432 (define_insn ""
433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
434 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
435 (const_int 0)))
436 (clobber (match_scratch:DI 2 "=r,r"))]
437 "TARGET_64BIT"
438 "@
439 rldicl. %2,%1,0,32
440 #"
441 [(set_attr "type" "compare")
442 (set_attr "length" "4,8")])
443
444 (define_split
445 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
446 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
447 (const_int 0)))
448 (clobber (match_scratch:DI 2 ""))]
449 "TARGET_POWERPC64 && reload_completed"
450 [(set (match_dup 2)
451 (zero_extend:DI (match_dup 1)))
452 (set (match_dup 0)
453 (compare:CC (match_dup 2)
454 (const_int 0)))]
455 "")
456
457 (define_insn ""
458 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
459 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
460 (const_int 0)))
461 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
462 (zero_extend:DI (match_dup 1)))]
463 "TARGET_64BIT"
464 "@
465 rldicl. %0,%1,0,32
466 #"
467 [(set_attr "type" "compare")
468 (set_attr "length" "4,8")])
469
470 (define_split
471 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
472 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
473 (const_int 0)))
474 (set (match_operand:DI 0 "gpc_reg_operand" "")
475 (zero_extend:DI (match_dup 1)))]
476 "TARGET_POWERPC64 && reload_completed"
477 [(set (match_dup 0)
478 (zero_extend:DI (match_dup 1)))
479 (set (match_dup 2)
480 (compare:CC (match_dup 0)
481 (const_int 0)))]
482 "")
483
484 (define_expand "extendsidi2"
485 [(set (match_operand:DI 0 "gpc_reg_operand" "")
486 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
487 "TARGET_POWERPC64"
488 "")
489
490 (define_insn ""
491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
492 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
493 "TARGET_POWERPC64"
494 "@
495 lwa%U1%X1 %0,%1
496 extsw %0,%1"
497 [(set_attr "type" "load_ext,*")])
498
499 (define_insn ""
500 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
501 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
502 (const_int 0)))
503 (clobber (match_scratch:DI 2 "=r,r"))]
504 "TARGET_64BIT"
505 "@
506 extsw. %2,%1
507 #"
508 [(set_attr "type" "compare")
509 (set_attr "length" "4,8")])
510
511 (define_split
512 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
513 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
514 (const_int 0)))
515 (clobber (match_scratch:DI 2 ""))]
516 "TARGET_POWERPC64 && reload_completed"
517 [(set (match_dup 2)
518 (sign_extend:DI (match_dup 1)))
519 (set (match_dup 0)
520 (compare:CC (match_dup 2)
521 (const_int 0)))]
522 "")
523
524 (define_insn ""
525 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
526 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
527 (const_int 0)))
528 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
529 (sign_extend:DI (match_dup 1)))]
530 "TARGET_64BIT"
531 "@
532 extsw. %0,%1
533 #"
534 [(set_attr "type" "compare")
535 (set_attr "length" "4,8")])
536
537 (define_split
538 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
540 (const_int 0)))
541 (set (match_operand:DI 0 "gpc_reg_operand" "")
542 (sign_extend:DI (match_dup 1)))]
543 "TARGET_POWERPC64 && reload_completed"
544 [(set (match_dup 0)
545 (sign_extend:DI (match_dup 1)))
546 (set (match_dup 2)
547 (compare:CC (match_dup 0)
548 (const_int 0)))]
549 "")
550
551 (define_expand "zero_extendqisi2"
552 [(set (match_operand:SI 0 "gpc_reg_operand" "")
553 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
554 ""
555 "")
556
557 (define_insn ""
558 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
559 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
560 ""
561 "@
562 lbz%U1%X1 %0,%1
563 {rlinm|rlwinm} %0,%1,0,0xff"
564 [(set_attr "type" "load,*")])
565
566 (define_insn ""
567 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
568 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
569 (const_int 0)))
570 (clobber (match_scratch:SI 2 "=r,r"))]
571 ""
572 "@
573 {andil.|andi.} %2,%1,0xff
574 #"
575 [(set_attr "type" "compare")
576 (set_attr "length" "4,8")])
577
578 (define_split
579 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
580 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
581 (const_int 0)))
582 (clobber (match_scratch:SI 2 ""))]
583 "reload_completed"
584 [(set (match_dup 2)
585 (zero_extend:SI (match_dup 1)))
586 (set (match_dup 0)
587 (compare:CC (match_dup 2)
588 (const_int 0)))]
589 "")
590
591 (define_insn ""
592 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
593 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
594 (const_int 0)))
595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
596 (zero_extend:SI (match_dup 1)))]
597 ""
598 "@
599 {andil.|andi.} %0,%1,0xff
600 #"
601 [(set_attr "type" "compare")
602 (set_attr "length" "4,8")])
603
604 (define_split
605 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
607 (const_int 0)))
608 (set (match_operand:SI 0 "gpc_reg_operand" "")
609 (zero_extend:SI (match_dup 1)))]
610 "reload_completed"
611 [(set (match_dup 0)
612 (zero_extend:SI (match_dup 1)))
613 (set (match_dup 2)
614 (compare:CC (match_dup 0)
615 (const_int 0)))]
616 "")
617
618 (define_expand "extendqisi2"
619 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
620 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
621 ""
622 "
623 {
624 if (TARGET_POWERPC)
625 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
626 else if (TARGET_POWER)
627 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
628 else
629 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
630 DONE;
631 }")
632
633 (define_insn "extendqisi2_ppc"
634 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
635 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
636 "TARGET_POWERPC"
637 "extsb %0,%1")
638
639 (define_insn ""
640 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
641 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
642 (const_int 0)))
643 (clobber (match_scratch:SI 2 "=r,r"))]
644 "TARGET_POWERPC"
645 "@
646 extsb. %2,%1
647 #"
648 [(set_attr "type" "compare")
649 (set_attr "length" "4,8")])
650
651 (define_split
652 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
653 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
654 (const_int 0)))
655 (clobber (match_scratch:SI 2 ""))]
656 "TARGET_POWERPC && reload_completed"
657 [(set (match_dup 2)
658 (sign_extend:SI (match_dup 1)))
659 (set (match_dup 0)
660 (compare:CC (match_dup 2)
661 (const_int 0)))]
662 "")
663
664 (define_insn ""
665 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
666 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
667 (const_int 0)))
668 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
669 (sign_extend:SI (match_dup 1)))]
670 "TARGET_POWERPC"
671 "@
672 extsb. %0,%1
673 #"
674 [(set_attr "type" "compare")
675 (set_attr "length" "4,8")])
676
677 (define_split
678 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
679 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
680 (const_int 0)))
681 (set (match_operand:SI 0 "gpc_reg_operand" "")
682 (sign_extend:SI (match_dup 1)))]
683 "TARGET_POWERPC && reload_completed"
684 [(set (match_dup 0)
685 (sign_extend:SI (match_dup 1)))
686 (set (match_dup 2)
687 (compare:CC (match_dup 0)
688 (const_int 0)))]
689 "")
690
691 (define_expand "extendqisi2_power"
692 [(parallel [(set (match_dup 2)
693 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
694 (const_int 24)))
695 (clobber (scratch:SI))])
696 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
697 (ashiftrt:SI (match_dup 2)
698 (const_int 24)))
699 (clobber (scratch:SI))])]
700 "TARGET_POWER"
701 "
702 { operands[1] = gen_lowpart (SImode, operands[1]);
703 operands[2] = gen_reg_rtx (SImode); }")
704
705 (define_expand "extendqisi2_no_power"
706 [(set (match_dup 2)
707 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
708 (const_int 24)))
709 (set (match_operand:SI 0 "gpc_reg_operand" "")
710 (ashiftrt:SI (match_dup 2)
711 (const_int 24)))]
712 "! TARGET_POWER && ! TARGET_POWERPC"
713 "
714 { operands[1] = gen_lowpart (SImode, operands[1]);
715 operands[2] = gen_reg_rtx (SImode); }")
716
717 (define_expand "zero_extendqihi2"
718 [(set (match_operand:HI 0 "gpc_reg_operand" "")
719 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
720 ""
721 "")
722
723 (define_insn ""
724 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
725 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
726 ""
727 "@
728 lbz%U1%X1 %0,%1
729 {rlinm|rlwinm} %0,%1,0,0xff"
730 [(set_attr "type" "load,*")])
731
732 (define_insn ""
733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
734 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
735 (const_int 0)))
736 (clobber (match_scratch:HI 2 "=r,r"))]
737 ""
738 "@
739 {andil.|andi.} %2,%1,0xff
740 #"
741 [(set_attr "type" "compare")
742 (set_attr "length" "4,8")])
743
744 (define_split
745 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
746 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
747 (const_int 0)))
748 (clobber (match_scratch:HI 2 ""))]
749 "reload_completed"
750 [(set (match_dup 2)
751 (zero_extend:HI (match_dup 1)))
752 (set (match_dup 0)
753 (compare:CC (match_dup 2)
754 (const_int 0)))]
755 "")
756
757 (define_insn ""
758 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
759 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
760 (const_int 0)))
761 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
762 (zero_extend:HI (match_dup 1)))]
763 ""
764 "@
765 {andil.|andi.} %0,%1,0xff
766 #"
767 [(set_attr "type" "compare")
768 (set_attr "length" "4,8")])
769
770 (define_split
771 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
772 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
773 (const_int 0)))
774 (set (match_operand:HI 0 "gpc_reg_operand" "")
775 (zero_extend:HI (match_dup 1)))]
776 "reload_completed"
777 [(set (match_dup 0)
778 (zero_extend:HI (match_dup 1)))
779 (set (match_dup 2)
780 (compare:CC (match_dup 0)
781 (const_int 0)))]
782 "")
783
784 (define_expand "extendqihi2"
785 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
786 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
787 ""
788 "
789 {
790 if (TARGET_POWERPC)
791 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
792 else if (TARGET_POWER)
793 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
794 else
795 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
796 DONE;
797 }")
798
799 (define_insn "extendqihi2_ppc"
800 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
801 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
802 "TARGET_POWERPC"
803 "extsb %0,%1")
804
805 (define_insn ""
806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
807 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
808 (const_int 0)))
809 (clobber (match_scratch:HI 2 "=r,r"))]
810 "TARGET_POWERPC"
811 "@
812 extsb. %2,%1
813 #"
814 [(set_attr "type" "compare")
815 (set_attr "length" "4,8")])
816
817 (define_split
818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
819 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
820 (const_int 0)))
821 (clobber (match_scratch:HI 2 ""))]
822 "TARGET_POWERPC && reload_completed"
823 [(set (match_dup 2)
824 (sign_extend:HI (match_dup 1)))
825 (set (match_dup 0)
826 (compare:CC (match_dup 2)
827 (const_int 0)))]
828 "")
829
830 (define_insn ""
831 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
832 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
833 (const_int 0)))
834 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
835 (sign_extend:HI (match_dup 1)))]
836 "TARGET_POWERPC"
837 "@
838 extsb. %0,%1
839 #"
840 [(set_attr "type" "compare")
841 (set_attr "length" "4,8")])
842
843 (define_split
844 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
845 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
846 (const_int 0)))
847 (set (match_operand:HI 0 "gpc_reg_operand" "")
848 (sign_extend:HI (match_dup 1)))]
849 "TARGET_POWERPC && reload_completed"
850 [(set (match_dup 0)
851 (sign_extend:HI (match_dup 1)))
852 (set (match_dup 2)
853 (compare:CC (match_dup 0)
854 (const_int 0)))]
855 "")
856
857 (define_expand "extendqihi2_power"
858 [(parallel [(set (match_dup 2)
859 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
860 (const_int 24)))
861 (clobber (scratch:SI))])
862 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
863 (ashiftrt:SI (match_dup 2)
864 (const_int 24)))
865 (clobber (scratch:SI))])]
866 "TARGET_POWER"
867 "
868 { operands[0] = gen_lowpart (SImode, operands[0]);
869 operands[1] = gen_lowpart (SImode, operands[1]);
870 operands[2] = gen_reg_rtx (SImode); }")
871
872 (define_expand "extendqihi2_no_power"
873 [(set (match_dup 2)
874 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
875 (const_int 24)))
876 (set (match_operand:HI 0 "gpc_reg_operand" "")
877 (ashiftrt:SI (match_dup 2)
878 (const_int 24)))]
879 "! TARGET_POWER && ! TARGET_POWERPC"
880 "
881 { operands[0] = gen_lowpart (SImode, operands[0]);
882 operands[1] = gen_lowpart (SImode, operands[1]);
883 operands[2] = gen_reg_rtx (SImode); }")
884
885 (define_expand "zero_extendhisi2"
886 [(set (match_operand:SI 0 "gpc_reg_operand" "")
887 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
888 ""
889 "")
890
891 (define_insn ""
892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
893 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
894 ""
895 "@
896 lhz%U1%X1 %0,%1
897 {rlinm|rlwinm} %0,%1,0,0xffff"
898 [(set_attr "type" "load,*")])
899
900 (define_insn ""
901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
902 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
903 (const_int 0)))
904 (clobber (match_scratch:SI 2 "=r,r"))]
905 ""
906 "@
907 {andil.|andi.} %2,%1,0xffff
908 #"
909 [(set_attr "type" "compare")
910 (set_attr "length" "4,8")])
911
912 (define_split
913 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
914 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
915 (const_int 0)))
916 (clobber (match_scratch:SI 2 ""))]
917 "reload_completed"
918 [(set (match_dup 2)
919 (zero_extend:SI (match_dup 1)))
920 (set (match_dup 0)
921 (compare:CC (match_dup 2)
922 (const_int 0)))]
923 "")
924
925 (define_insn ""
926 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
927 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
928 (const_int 0)))
929 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
930 (zero_extend:SI (match_dup 1)))]
931 ""
932 "@
933 {andil.|andi.} %0,%1,0xffff
934 #"
935 [(set_attr "type" "compare")
936 (set_attr "length" "4,8")])
937
938 (define_split
939 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
940 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
941 (const_int 0)))
942 (set (match_operand:SI 0 "gpc_reg_operand" "")
943 (zero_extend:SI (match_dup 1)))]
944 "reload_completed"
945 [(set (match_dup 0)
946 (zero_extend:SI (match_dup 1)))
947 (set (match_dup 2)
948 (compare:CC (match_dup 0)
949 (const_int 0)))]
950 "")
951
952 (define_expand "extendhisi2"
953 [(set (match_operand:SI 0 "gpc_reg_operand" "")
954 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
955 ""
956 "")
957
958 (define_insn ""
959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
960 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
961 ""
962 "@
963 lha%U1%X1 %0,%1
964 {exts|extsh} %0,%1"
965 [(set_attr "type" "load_ext,*")])
966
967 (define_insn ""
968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
969 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
970 (const_int 0)))
971 (clobber (match_scratch:SI 2 "=r,r"))]
972 ""
973 "@
974 {exts.|extsh.} %2,%1
975 #"
976 [(set_attr "type" "compare")
977 (set_attr "length" "4,8")])
978
979 (define_split
980 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
981 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
982 (const_int 0)))
983 (clobber (match_scratch:SI 2 ""))]
984 "reload_completed"
985 [(set (match_dup 2)
986 (sign_extend:SI (match_dup 1)))
987 (set (match_dup 0)
988 (compare:CC (match_dup 2)
989 (const_int 0)))]
990 "")
991
992 (define_insn ""
993 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
994 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
995 (const_int 0)))
996 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
997 (sign_extend:SI (match_dup 1)))]
998 ""
999 "@
1000 {exts.|extsh.} %0,%1
1001 #"
1002 [(set_attr "type" "compare")
1003 (set_attr "length" "4,8")])
1004 \f
1005 (define_split
1006 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1007 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1008 (const_int 0)))
1009 (set (match_operand:SI 0 "gpc_reg_operand" "")
1010 (sign_extend:SI (match_dup 1)))]
1011 "reload_completed"
1012 [(set (match_dup 0)
1013 (sign_extend:SI (match_dup 1)))
1014 (set (match_dup 2)
1015 (compare:CC (match_dup 0)
1016 (const_int 0)))]
1017 "")
1018
1019 ;; Fixed-point arithmetic insns.
1020
1021 (define_expand "add<mode>3"
1022 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1023 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1024 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1025 ""
1026 "
1027 {
1028 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1029 {
1030 if (non_short_cint_operand (operands[2], DImode))
1031 FAIL;
1032 }
1033 else if (GET_CODE (operands[2]) == CONST_INT
1034 && ! add_operand (operands[2], <MODE>mode))
1035 {
1036 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1037 ? operands[0] : gen_reg_rtx (<MODE>mode));
1038
1039 HOST_WIDE_INT val = INTVAL (operands[2]);
1040 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1041 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1042
1043 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1044 FAIL;
1045
1046 /* The ordering here is important for the prolog expander.
1047 When space is allocated from the stack, adding 'low' first may
1048 produce a temporary deallocation (which would be bad). */
1049 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1050 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1051 DONE;
1052 }
1053 }")
1054
1055 ;; Discourage ai/addic because of carry but provide it in an alternative
1056 ;; allowing register zero as source.
1057 (define_insn "*add<mode>3_internal1"
1058 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1059 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1060 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1061 ""
1062 "@
1063 {cax|add} %0,%1,%2
1064 {cal %0,%2(%1)|addi %0,%1,%2}
1065 {ai|addic} %0,%1,%2
1066 {cau|addis} %0,%1,%v2"
1067 [(set_attr "length" "4,4,4,4")])
1068
1069 (define_insn "addsi3_high"
1070 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1071 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1072 (high:SI (match_operand 2 "" ""))))]
1073 "TARGET_MACHO && !TARGET_64BIT"
1074 "{cau|addis} %0,%1,ha16(%2)"
1075 [(set_attr "length" "4")])
1076
1077 (define_insn "*add<mode>3_internal2"
1078 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1079 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1080 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1081 (const_int 0)))
1082 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1083 ""
1084 "@
1085 {cax.|add.} %3,%1,%2
1086 {ai.|addic.} %3,%1,%2
1087 #
1088 #"
1089 [(set_attr "type" "fast_compare,compare,compare,compare")
1090 (set_attr "length" "4,4,8,8")])
1091
1092 (define_split
1093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1094 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1095 (match_operand:GPR 2 "reg_or_short_operand" ""))
1096 (const_int 0)))
1097 (clobber (match_scratch:GPR 3 ""))]
1098 "reload_completed"
1099 [(set (match_dup 3)
1100 (plus:GPR (match_dup 1)
1101 (match_dup 2)))
1102 (set (match_dup 0)
1103 (compare:CC (match_dup 3)
1104 (const_int 0)))]
1105 "")
1106
1107 (define_insn "*add<mode>3_internal3"
1108 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1109 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1110 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1111 (const_int 0)))
1112 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1113 (plus:P (match_dup 1)
1114 (match_dup 2)))]
1115 ""
1116 "@
1117 {cax.|add.} %0,%1,%2
1118 {ai.|addic.} %0,%1,%2
1119 #
1120 #"
1121 [(set_attr "type" "fast_compare,compare,compare,compare")
1122 (set_attr "length" "4,4,8,8")])
1123
1124 (define_split
1125 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1126 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1127 (match_operand:P 2 "reg_or_short_operand" ""))
1128 (const_int 0)))
1129 (set (match_operand:P 0 "gpc_reg_operand" "")
1130 (plus:P (match_dup 1) (match_dup 2)))]
1131 "reload_completed"
1132 [(set (match_dup 0)
1133 (plus:P (match_dup 1)
1134 (match_dup 2)))
1135 (set (match_dup 3)
1136 (compare:CC (match_dup 0)
1137 (const_int 0)))]
1138 "")
1139
1140 ;; Split an add that we can't do in one insn into two insns, each of which
1141 ;; does one 16-bit part. This is used by combine. Note that the low-order
1142 ;; add should be last in case the result gets used in an address.
1143
1144 (define_split
1145 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1146 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1147 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1148 ""
1149 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1150 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1151 "
1152 {
1153 HOST_WIDE_INT val = INTVAL (operands[2]);
1154 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1155 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1156
1157 operands[4] = GEN_INT (low);
1158 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1159 operands[3] = GEN_INT (rest);
1160 else if (! no_new_pseudos)
1161 {
1162 operands[3] = gen_reg_rtx (DImode);
1163 emit_move_insn (operands[3], operands[2]);
1164 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1165 DONE;
1166 }
1167 else
1168 FAIL;
1169 }")
1170
1171 (define_insn "one_cmpl<mode>2"
1172 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1173 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1174 ""
1175 "nor %0,%1,%1")
1176
1177 (define_insn ""
1178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1179 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1180 (const_int 0)))
1181 (clobber (match_scratch:P 2 "=r,r"))]
1182 ""
1183 "@
1184 nor. %2,%1,%1
1185 #"
1186 [(set_attr "type" "compare")
1187 (set_attr "length" "4,8")])
1188
1189 (define_split
1190 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1191 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1192 (const_int 0)))
1193 (clobber (match_scratch:P 2 ""))]
1194 "reload_completed"
1195 [(set (match_dup 2)
1196 (not:P (match_dup 1)))
1197 (set (match_dup 0)
1198 (compare:CC (match_dup 2)
1199 (const_int 0)))]
1200 "")
1201
1202 (define_insn ""
1203 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1204 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1205 (const_int 0)))
1206 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1207 (not:P (match_dup 1)))]
1208 ""
1209 "@
1210 nor. %0,%1,%1
1211 #"
1212 [(set_attr "type" "compare")
1213 (set_attr "length" "4,8")])
1214
1215 (define_split
1216 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1217 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1218 (const_int 0)))
1219 (set (match_operand:P 0 "gpc_reg_operand" "")
1220 (not:P (match_dup 1)))]
1221 "reload_completed"
1222 [(set (match_dup 0)
1223 (not:P (match_dup 1)))
1224 (set (match_dup 2)
1225 (compare:CC (match_dup 0)
1226 (const_int 0)))]
1227 "")
1228
1229 (define_insn ""
1230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1231 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1232 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1233 "! TARGET_POWERPC"
1234 "{sf%I1|subf%I1c} %0,%2,%1")
1235
1236 (define_insn ""
1237 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1238 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1239 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1240 "TARGET_POWERPC"
1241 "@
1242 subf %0,%2,%1
1243 subfic %0,%2,%1")
1244
1245 (define_insn ""
1246 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1247 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1248 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1249 (const_int 0)))
1250 (clobber (match_scratch:SI 3 "=r,r"))]
1251 "! TARGET_POWERPC"
1252 "@
1253 {sf.|subfc.} %3,%2,%1
1254 #"
1255 [(set_attr "type" "compare")
1256 (set_attr "length" "4,8")])
1257
1258 (define_insn ""
1259 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1260 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1261 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1262 (const_int 0)))
1263 (clobber (match_scratch:P 3 "=r,r"))]
1264 "TARGET_POWERPC"
1265 "@
1266 subf. %3,%2,%1
1267 #"
1268 [(set_attr "type" "fast_compare")
1269 (set_attr "length" "4,8")])
1270
1271 (define_split
1272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1273 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1274 (match_operand:P 2 "gpc_reg_operand" ""))
1275 (const_int 0)))
1276 (clobber (match_scratch:P 3 ""))]
1277 "reload_completed"
1278 [(set (match_dup 3)
1279 (minus:P (match_dup 1)
1280 (match_dup 2)))
1281 (set (match_dup 0)
1282 (compare:CC (match_dup 3)
1283 (const_int 0)))]
1284 "")
1285
1286 (define_insn ""
1287 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1288 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1289 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1290 (const_int 0)))
1291 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1292 (minus:SI (match_dup 1) (match_dup 2)))]
1293 "! TARGET_POWERPC"
1294 "@
1295 {sf.|subfc.} %0,%2,%1
1296 #"
1297 [(set_attr "type" "compare")
1298 (set_attr "length" "4,8")])
1299
1300 (define_insn ""
1301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1302 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1303 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1304 (const_int 0)))
1305 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1306 (minus:P (match_dup 1)
1307 (match_dup 2)))]
1308 "TARGET_POWERPC"
1309 "@
1310 subf. %0,%2,%1
1311 #"
1312 [(set_attr "type" "fast_compare")
1313 (set_attr "length" "4,8")])
1314
1315 (define_split
1316 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1317 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1318 (match_operand:P 2 "gpc_reg_operand" ""))
1319 (const_int 0)))
1320 (set (match_operand:P 0 "gpc_reg_operand" "")
1321 (minus:P (match_dup 1)
1322 (match_dup 2)))]
1323 "reload_completed"
1324 [(set (match_dup 0)
1325 (minus:P (match_dup 1)
1326 (match_dup 2)))
1327 (set (match_dup 3)
1328 (compare:CC (match_dup 0)
1329 (const_int 0)))]
1330 "")
1331
1332 (define_expand "sub<mode>3"
1333 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1334 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1335 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1336 ""
1337 "
1338 {
1339 if (GET_CODE (operands[2]) == CONST_INT)
1340 {
1341 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1342 negate_rtx (<MODE>mode, operands[2])));
1343 DONE;
1344 }
1345 }")
1346
1347 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1348 ;; instruction and some auxiliary computations. Then we just have a single
1349 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1350 ;; combine.
1351
1352 (define_expand "sminsi3"
1353 [(set (match_dup 3)
1354 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1355 (match_operand:SI 2 "reg_or_short_operand" ""))
1356 (const_int 0)
1357 (minus:SI (match_dup 2) (match_dup 1))))
1358 (set (match_operand:SI 0 "gpc_reg_operand" "")
1359 (minus:SI (match_dup 2) (match_dup 3)))]
1360 "TARGET_POWER || TARGET_ISEL"
1361 "
1362 {
1363 if (TARGET_ISEL)
1364 {
1365 operands[2] = force_reg (SImode, operands[2]);
1366 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1367 DONE;
1368 }
1369
1370 operands[3] = gen_reg_rtx (SImode);
1371 }")
1372
1373 (define_split
1374 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1375 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1376 (match_operand:SI 2 "reg_or_short_operand" "")))
1377 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1378 "TARGET_POWER"
1379 [(set (match_dup 3)
1380 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1381 (const_int 0)
1382 (minus:SI (match_dup 2) (match_dup 1))))
1383 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1384 "")
1385
1386 (define_expand "smaxsi3"
1387 [(set (match_dup 3)
1388 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1389 (match_operand:SI 2 "reg_or_short_operand" ""))
1390 (const_int 0)
1391 (minus:SI (match_dup 2) (match_dup 1))))
1392 (set (match_operand:SI 0 "gpc_reg_operand" "")
1393 (plus:SI (match_dup 3) (match_dup 1)))]
1394 "TARGET_POWER || TARGET_ISEL"
1395 "
1396 {
1397 if (TARGET_ISEL)
1398 {
1399 operands[2] = force_reg (SImode, operands[2]);
1400 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1401 DONE;
1402 }
1403 operands[3] = gen_reg_rtx (SImode);
1404 }")
1405
1406 (define_split
1407 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1408 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1409 (match_operand:SI 2 "reg_or_short_operand" "")))
1410 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1411 "TARGET_POWER"
1412 [(set (match_dup 3)
1413 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1414 (const_int 0)
1415 (minus:SI (match_dup 2) (match_dup 1))))
1416 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1417 "")
1418
1419 (define_expand "uminsi3"
1420 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1421 (match_dup 5)))
1422 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1423 (match_dup 5)))
1424 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1425 (const_int 0)
1426 (minus:SI (match_dup 4) (match_dup 3))))
1427 (set (match_operand:SI 0 "gpc_reg_operand" "")
1428 (minus:SI (match_dup 2) (match_dup 3)))]
1429 "TARGET_POWER || TARGET_ISEL"
1430 "
1431 {
1432 if (TARGET_ISEL)
1433 {
1434 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1435 DONE;
1436 }
1437 operands[3] = gen_reg_rtx (SImode);
1438 operands[4] = gen_reg_rtx (SImode);
1439 operands[5] = GEN_INT (-2147483647 - 1);
1440 }")
1441
1442 (define_expand "umaxsi3"
1443 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1444 (match_dup 5)))
1445 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1446 (match_dup 5)))
1447 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1448 (const_int 0)
1449 (minus:SI (match_dup 4) (match_dup 3))))
1450 (set (match_operand:SI 0 "gpc_reg_operand" "")
1451 (plus:SI (match_dup 3) (match_dup 1)))]
1452 "TARGET_POWER || TARGET_ISEL"
1453 "
1454 {
1455 if (TARGET_ISEL)
1456 {
1457 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1458 DONE;
1459 }
1460 operands[3] = gen_reg_rtx (SImode);
1461 operands[4] = gen_reg_rtx (SImode);
1462 operands[5] = GEN_INT (-2147483647 - 1);
1463 }")
1464
1465 (define_insn ""
1466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1467 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1468 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1469 (const_int 0)
1470 (minus:SI (match_dup 2) (match_dup 1))))]
1471 "TARGET_POWER"
1472 "doz%I2 %0,%1,%2")
1473
1474 (define_insn ""
1475 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1476 (compare:CC
1477 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1478 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1479 (const_int 0)
1480 (minus:SI (match_dup 2) (match_dup 1)))
1481 (const_int 0)))
1482 (clobber (match_scratch:SI 3 "=r,r"))]
1483 "TARGET_POWER"
1484 "@
1485 doz%I2. %3,%1,%2
1486 #"
1487 [(set_attr "type" "delayed_compare")
1488 (set_attr "length" "4,8")])
1489
1490 (define_split
1491 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1492 (compare:CC
1493 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1494 (match_operand:SI 2 "reg_or_short_operand" ""))
1495 (const_int 0)
1496 (minus:SI (match_dup 2) (match_dup 1)))
1497 (const_int 0)))
1498 (clobber (match_scratch:SI 3 ""))]
1499 "TARGET_POWER && reload_completed"
1500 [(set (match_dup 3)
1501 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1502 (const_int 0)
1503 (minus:SI (match_dup 2) (match_dup 1))))
1504 (set (match_dup 0)
1505 (compare:CC (match_dup 3)
1506 (const_int 0)))]
1507 "")
1508
1509 (define_insn ""
1510 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1511 (compare:CC
1512 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1513 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1514 (const_int 0)
1515 (minus:SI (match_dup 2) (match_dup 1)))
1516 (const_int 0)))
1517 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1518 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1519 (const_int 0)
1520 (minus:SI (match_dup 2) (match_dup 1))))]
1521 "TARGET_POWER"
1522 "@
1523 doz%I2. %0,%1,%2
1524 #"
1525 [(set_attr "type" "delayed_compare")
1526 (set_attr "length" "4,8")])
1527
1528 (define_split
1529 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1530 (compare:CC
1531 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1532 (match_operand:SI 2 "reg_or_short_operand" ""))
1533 (const_int 0)
1534 (minus:SI (match_dup 2) (match_dup 1)))
1535 (const_int 0)))
1536 (set (match_operand:SI 0 "gpc_reg_operand" "")
1537 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1538 (const_int 0)
1539 (minus:SI (match_dup 2) (match_dup 1))))]
1540 "TARGET_POWER && reload_completed"
1541 [(set (match_dup 0)
1542 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1543 (const_int 0)
1544 (minus:SI (match_dup 2) (match_dup 1))))
1545 (set (match_dup 3)
1546 (compare:CC (match_dup 0)
1547 (const_int 0)))]
1548 "")
1549
1550 ;; We don't need abs with condition code because such comparisons should
1551 ;; never be done.
1552 (define_expand "abssi2"
1553 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1554 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1555 ""
1556 "
1557 {
1558 if (TARGET_ISEL)
1559 {
1560 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1561 DONE;
1562 }
1563 else if (! TARGET_POWER)
1564 {
1565 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1566 DONE;
1567 }
1568 }")
1569
1570 (define_insn "*abssi2_power"
1571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1572 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1573 "TARGET_POWER"
1574 "abs %0,%1")
1575
1576 (define_insn_and_split "abssi2_isel"
1577 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1578 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1579 (clobber (match_scratch:SI 2 "=&b"))
1580 (clobber (match_scratch:CC 3 "=y"))]
1581 "TARGET_ISEL"
1582 "#"
1583 "&& reload_completed"
1584 [(set (match_dup 2) (neg:SI (match_dup 1)))
1585 (set (match_dup 3)
1586 (compare:CC (match_dup 1)
1587 (const_int 0)))
1588 (set (match_dup 0)
1589 (if_then_else:SI (ge (match_dup 3)
1590 (const_int 0))
1591 (match_dup 1)
1592 (match_dup 2)))]
1593 "")
1594
1595 (define_insn_and_split "abssi2_nopower"
1596 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1597 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1598 (clobber (match_scratch:SI 2 "=&r,&r"))]
1599 "! TARGET_POWER && ! TARGET_ISEL"
1600 "#"
1601 "&& reload_completed"
1602 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1603 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1604 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1605 "")
1606
1607 (define_insn "*nabs_power"
1608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1609 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1610 "TARGET_POWER"
1611 "nabs %0,%1")
1612
1613 (define_insn_and_split "*nabs_nopower"
1614 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1615 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1616 (clobber (match_scratch:SI 2 "=&r,&r"))]
1617 "! TARGET_POWER"
1618 "#"
1619 "&& reload_completed"
1620 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1621 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1622 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1623 "")
1624
1625 (define_expand "neg<mode>2"
1626 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1627 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1628 ""
1629 "")
1630
1631 (define_insn "*neg<mode>2_internal"
1632 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1633 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1634 ""
1635 "neg %0,%1")
1636
1637 (define_insn ""
1638 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1639 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1640 (const_int 0)))
1641 (clobber (match_scratch:P 2 "=r,r"))]
1642 ""
1643 "@
1644 neg. %2,%1
1645 #"
1646 [(set_attr "type" "fast_compare")
1647 (set_attr "length" "4,8")])
1648
1649 (define_split
1650 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1651 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1652 (const_int 0)))
1653 (clobber (match_scratch:P 2 ""))]
1654 "reload_completed"
1655 [(set (match_dup 2)
1656 (neg:P (match_dup 1)))
1657 (set (match_dup 0)
1658 (compare:CC (match_dup 2)
1659 (const_int 0)))]
1660 "")
1661
1662 (define_insn ""
1663 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1664 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1665 (const_int 0)))
1666 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1667 (neg:P (match_dup 1)))]
1668 ""
1669 "@
1670 neg. %0,%1
1671 #"
1672 [(set_attr "type" "fast_compare")
1673 (set_attr "length" "4,8")])
1674
1675 (define_split
1676 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1677 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1678 (const_int 0)))
1679 (set (match_operand:P 0 "gpc_reg_operand" "")
1680 (neg:P (match_dup 1)))]
1681 "reload_completed"
1682 [(set (match_dup 0)
1683 (neg:P (match_dup 1)))
1684 (set (match_dup 2)
1685 (compare:CC (match_dup 0)
1686 (const_int 0)))]
1687 "")
1688
1689 (define_insn "clz<mode>2"
1690 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1691 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1692 ""
1693 "{cntlz|cntlz<wd>} %0,%1")
1694
1695 (define_expand "ctz<mode>2"
1696 [(set (match_dup 2)
1697 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1698 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1699 (match_dup 2)))
1700 (clobber (scratch:CC))])
1701 (set (match_dup 4) (clz:GPR (match_dup 3)))
1702 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1703 (minus:GPR (match_dup 5) (match_dup 4)))]
1704 ""
1705 {
1706 operands[2] = gen_reg_rtx (<MODE>mode);
1707 operands[3] = gen_reg_rtx (<MODE>mode);
1708 operands[4] = gen_reg_rtx (<MODE>mode);
1709 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1710 })
1711
1712 (define_expand "ffs<mode>2"
1713 [(set (match_dup 2)
1714 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1715 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1716 (match_dup 2)))
1717 (clobber (scratch:CC))])
1718 (set (match_dup 4) (clz:GPR (match_dup 3)))
1719 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1720 (minus:GPR (match_dup 5) (match_dup 4)))]
1721 ""
1722 {
1723 operands[2] = gen_reg_rtx (<MODE>mode);
1724 operands[3] = gen_reg_rtx (<MODE>mode);
1725 operands[4] = gen_reg_rtx (<MODE>mode);
1726 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1727 })
1728
1729 (define_expand "popcount<mode>2"
1730 [(set (match_dup 2)
1731 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1732 UNSPEC_POPCNTB))
1733 (set (match_dup 3)
1734 (mult:GPR (match_dup 2) (match_dup 4)))
1735 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1736 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1737 "TARGET_POPCNTB"
1738 {
1739 operands[2] = gen_reg_rtx (<MODE>mode);
1740 operands[3] = gen_reg_rtx (<MODE>mode);
1741 operands[4] = force_reg (<MODE>mode,
1742 <MODE>mode == SImode
1743 ? GEN_INT (0x01010101)
1744 : GEN_INT ((HOST_WIDE_INT)
1745 0x01010101 << 32 | 0x01010101));
1746 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1747 })
1748
1749 (define_insn "popcntb<mode>2"
1750 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1751 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1752 UNSPEC_POPCNTB))]
1753 "TARGET_POPCNTB"
1754 "popcntb %0,%1")
1755
1756 (define_expand "mulsi3"
1757 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1758 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1759 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1760 ""
1761 "
1762 {
1763 if (TARGET_POWER)
1764 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1765 else
1766 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1767 DONE;
1768 }")
1769
1770 (define_insn "mulsi3_mq"
1771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1772 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1773 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1774 (clobber (match_scratch:SI 3 "=q,q"))]
1775 "TARGET_POWER"
1776 "@
1777 {muls|mullw} %0,%1,%2
1778 {muli|mulli} %0,%1,%2"
1779 [(set (attr "type")
1780 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1781 (const_string "imul3")
1782 (match_operand:SI 2 "short_cint_operand" "")
1783 (const_string "imul2")]
1784 (const_string "imul")))])
1785
1786 (define_insn "mulsi3_no_mq"
1787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1788 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1789 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1790 "! TARGET_POWER"
1791 "@
1792 {muls|mullw} %0,%1,%2
1793 {muli|mulli} %0,%1,%2"
1794 [(set (attr "type")
1795 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1796 (const_string "imul3")
1797 (match_operand:SI 2 "short_cint_operand" "")
1798 (const_string "imul2")]
1799 (const_string "imul")))])
1800
1801 (define_insn "*mulsi3_mq_internal1"
1802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1803 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1804 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1805 (const_int 0)))
1806 (clobber (match_scratch:SI 3 "=r,r"))
1807 (clobber (match_scratch:SI 4 "=q,q"))]
1808 "TARGET_POWER"
1809 "@
1810 {muls.|mullw.} %3,%1,%2
1811 #"
1812 [(set_attr "type" "imul_compare")
1813 (set_attr "length" "4,8")])
1814
1815 (define_split
1816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1817 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1818 (match_operand:SI 2 "gpc_reg_operand" ""))
1819 (const_int 0)))
1820 (clobber (match_scratch:SI 3 ""))
1821 (clobber (match_scratch:SI 4 ""))]
1822 "TARGET_POWER && reload_completed"
1823 [(parallel [(set (match_dup 3)
1824 (mult:SI (match_dup 1) (match_dup 2)))
1825 (clobber (match_dup 4))])
1826 (set (match_dup 0)
1827 (compare:CC (match_dup 3)
1828 (const_int 0)))]
1829 "")
1830
1831 (define_insn "*mulsi3_no_mq_internal1"
1832 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1833 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1834 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1835 (const_int 0)))
1836 (clobber (match_scratch:SI 3 "=r,r"))]
1837 "! TARGET_POWER"
1838 "@
1839 {muls.|mullw.} %3,%1,%2
1840 #"
1841 [(set_attr "type" "imul_compare")
1842 (set_attr "length" "4,8")])
1843
1844 (define_split
1845 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1846 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1847 (match_operand:SI 2 "gpc_reg_operand" ""))
1848 (const_int 0)))
1849 (clobber (match_scratch:SI 3 ""))]
1850 "! TARGET_POWER && reload_completed"
1851 [(set (match_dup 3)
1852 (mult:SI (match_dup 1) (match_dup 2)))
1853 (set (match_dup 0)
1854 (compare:CC (match_dup 3)
1855 (const_int 0)))]
1856 "")
1857
1858 (define_insn "*mulsi3_mq_internal2"
1859 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1860 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1861 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1862 (const_int 0)))
1863 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1864 (mult:SI (match_dup 1) (match_dup 2)))
1865 (clobber (match_scratch:SI 4 "=q,q"))]
1866 "TARGET_POWER"
1867 "@
1868 {muls.|mullw.} %0,%1,%2
1869 #"
1870 [(set_attr "type" "imul_compare")
1871 (set_attr "length" "4,8")])
1872
1873 (define_split
1874 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1875 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_operand:SI 2 "gpc_reg_operand" ""))
1877 (const_int 0)))
1878 (set (match_operand:SI 0 "gpc_reg_operand" "")
1879 (mult:SI (match_dup 1) (match_dup 2)))
1880 (clobber (match_scratch:SI 4 ""))]
1881 "TARGET_POWER && reload_completed"
1882 [(parallel [(set (match_dup 0)
1883 (mult:SI (match_dup 1) (match_dup 2)))
1884 (clobber (match_dup 4))])
1885 (set (match_dup 3)
1886 (compare:CC (match_dup 0)
1887 (const_int 0)))]
1888 "")
1889
1890 (define_insn "*mulsi3_no_mq_internal2"
1891 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1892 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1893 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1894 (const_int 0)))
1895 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1896 (mult:SI (match_dup 1) (match_dup 2)))]
1897 "! TARGET_POWER"
1898 "@
1899 {muls.|mullw.} %0,%1,%2
1900 #"
1901 [(set_attr "type" "imul_compare")
1902 (set_attr "length" "4,8")])
1903
1904 (define_split
1905 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1906 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1907 (match_operand:SI 2 "gpc_reg_operand" ""))
1908 (const_int 0)))
1909 (set (match_operand:SI 0 "gpc_reg_operand" "")
1910 (mult:SI (match_dup 1) (match_dup 2)))]
1911 "! TARGET_POWER && reload_completed"
1912 [(set (match_dup 0)
1913 (mult:SI (match_dup 1) (match_dup 2)))
1914 (set (match_dup 3)
1915 (compare:CC (match_dup 0)
1916 (const_int 0)))]
1917 "")
1918
1919 ;; Operand 1 is divided by operand 2; quotient goes to operand
1920 ;; 0 and remainder to operand 3.
1921 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1922
1923 (define_expand "divmodsi4"
1924 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1925 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1926 (match_operand:SI 2 "gpc_reg_operand" "")))
1927 (set (match_operand:SI 3 "register_operand" "")
1928 (mod:SI (match_dup 1) (match_dup 2)))])]
1929 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1930 "
1931 {
1932 if (! TARGET_POWER && ! TARGET_POWERPC)
1933 {
1934 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1935 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1936 emit_insn (gen_divss_call ());
1937 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1938 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1939 DONE;
1940 }
1941 }")
1942
1943 (define_insn "*divmodsi4_internal"
1944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1945 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1946 (match_operand:SI 2 "gpc_reg_operand" "r")))
1947 (set (match_operand:SI 3 "register_operand" "=q")
1948 (mod:SI (match_dup 1) (match_dup 2)))]
1949 "TARGET_POWER"
1950 "divs %0,%1,%2"
1951 [(set_attr "type" "idiv")])
1952
1953 (define_expand "udiv<mode>3"
1954 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1955 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1956 (match_operand:GPR 2 "gpc_reg_operand" "")))]
1957 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1958 "
1959 {
1960 if (! TARGET_POWER && ! TARGET_POWERPC)
1961 {
1962 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1963 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1964 emit_insn (gen_quous_call ());
1965 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1966 DONE;
1967 }
1968 else if (TARGET_POWER)
1969 {
1970 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1971 DONE;
1972 }
1973 }")
1974
1975 (define_insn "udivsi3_mq"
1976 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1977 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1978 (match_operand:SI 2 "gpc_reg_operand" "r")))
1979 (clobber (match_scratch:SI 3 "=q"))]
1980 "TARGET_POWERPC && TARGET_POWER"
1981 "divwu %0,%1,%2"
1982 [(set_attr "type" "idiv")])
1983
1984 (define_insn "*udivsi3_no_mq"
1985 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1986 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1987 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1988 "TARGET_POWERPC && ! TARGET_POWER"
1989 "div<wd>u %0,%1,%2"
1990 [(set_attr "type" "idiv")])
1991
1992 ;; For powers of two we can do srai/aze for divide and then adjust for
1993 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1994 ;; used; for PowerPC, force operands into register and do a normal divide;
1995 ;; for AIX common-mode, use quoss call on register operands.
1996 (define_expand "div<mode>3"
1997 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1998 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1999 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2000 ""
2001 "
2002 {
2003 if (GET_CODE (operands[2]) == CONST_INT
2004 && INTVAL (operands[2]) > 0
2005 && exact_log2 (INTVAL (operands[2])) >= 0)
2006 ;
2007 else if (TARGET_POWERPC)
2008 {
2009 operands[2] = force_reg (SImode, operands[2]);
2010 if (TARGET_POWER)
2011 {
2012 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2013 DONE;
2014 }
2015 }
2016 else if (TARGET_POWER)
2017 FAIL;
2018 else
2019 {
2020 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2021 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2022 emit_insn (gen_quoss_call ());
2023 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2024 DONE;
2025 }
2026 }")
2027
2028 (define_insn "divsi3_mq"
2029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2030 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2031 (match_operand:SI 2 "gpc_reg_operand" "r")))
2032 (clobber (match_scratch:SI 3 "=q"))]
2033 "TARGET_POWERPC && TARGET_POWER"
2034 "divw %0,%1,%2"
2035 [(set_attr "type" "idiv")])
2036
2037 (define_insn "*div<mode>3_no_mq"
2038 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2039 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2040 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2041 "TARGET_POWERPC && ! TARGET_POWER"
2042 "div<wd> %0,%1,%2"
2043 [(set_attr "type" "idiv")])
2044
2045 (define_expand "mod<mode>3"
2046 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2047 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2048 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2049 ""
2050 "
2051 {
2052 int i;
2053 rtx temp1;
2054 rtx temp2;
2055
2056 if (GET_CODE (operands[2]) != CONST_INT
2057 || INTVAL (operands[2]) <= 0
2058 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2059 FAIL;
2060
2061 temp1 = gen_reg_rtx (<MODE>mode);
2062 temp2 = gen_reg_rtx (<MODE>mode);
2063
2064 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2065 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2066 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2067 DONE;
2068 }")
2069
2070 (define_insn ""
2071 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2072 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2073 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2074 ""
2075 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2076 [(set_attr "type" "two")
2077 (set_attr "length" "8")])
2078
2079 (define_insn ""
2080 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2081 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2082 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2083 (const_int 0)))
2084 (clobber (match_scratch:P 3 "=r,r"))]
2085 ""
2086 "@
2087 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2088 #"
2089 [(set_attr "type" "compare")
2090 (set_attr "length" "8,12")])
2091
2092 (define_split
2093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2094 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2095 (match_operand:GPR 2 "exact_log2_cint_operand"
2096 ""))
2097 (const_int 0)))
2098 (clobber (match_scratch:GPR 3 ""))]
2099 "reload_completed"
2100 [(set (match_dup 3)
2101 (div:<MODE> (match_dup 1) (match_dup 2)))
2102 (set (match_dup 0)
2103 (compare:CC (match_dup 3)
2104 (const_int 0)))]
2105 "")
2106
2107 (define_insn ""
2108 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2109 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2110 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2111 (const_int 0)))
2112 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2113 (div:P (match_dup 1) (match_dup 2)))]
2114 ""
2115 "@
2116 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2117 #"
2118 [(set_attr "type" "compare")
2119 (set_attr "length" "8,12")])
2120
2121 (define_split
2122 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2123 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2124 (match_operand:GPR 2 "exact_log2_cint_operand"
2125 ""))
2126 (const_int 0)))
2127 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2128 (div:GPR (match_dup 1) (match_dup 2)))]
2129 "reload_completed"
2130 [(set (match_dup 0)
2131 (div:<MODE> (match_dup 1) (match_dup 2)))
2132 (set (match_dup 3)
2133 (compare:CC (match_dup 0)
2134 (const_int 0)))]
2135 "")
2136
2137 (define_insn ""
2138 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2139 (udiv:SI
2140 (plus:DI (ashift:DI
2141 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2142 (const_int 32))
2143 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2144 (match_operand:SI 3 "gpc_reg_operand" "r")))
2145 (set (match_operand:SI 2 "register_operand" "=*q")
2146 (umod:SI
2147 (plus:DI (ashift:DI
2148 (zero_extend:DI (match_dup 1)) (const_int 32))
2149 (zero_extend:DI (match_dup 4)))
2150 (match_dup 3)))]
2151 "TARGET_POWER"
2152 "div %0,%1,%3"
2153 [(set_attr "type" "idiv")])
2154
2155 ;; To do unsigned divide we handle the cases of the divisor looking like a
2156 ;; negative number. If it is a constant that is less than 2**31, we don't
2157 ;; have to worry about the branches. So make a few subroutines here.
2158 ;;
2159 ;; First comes the normal case.
2160 (define_expand "udivmodsi4_normal"
2161 [(set (match_dup 4) (const_int 0))
2162 (parallel [(set (match_operand:SI 0 "" "")
2163 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2164 (const_int 32))
2165 (zero_extend:DI (match_operand:SI 1 "" "")))
2166 (match_operand:SI 2 "" "")))
2167 (set (match_operand:SI 3 "" "")
2168 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2169 (const_int 32))
2170 (zero_extend:DI (match_dup 1)))
2171 (match_dup 2)))])]
2172 "TARGET_POWER"
2173 "
2174 { operands[4] = gen_reg_rtx (SImode); }")
2175
2176 ;; This handles the branches.
2177 (define_expand "udivmodsi4_tests"
2178 [(set (match_operand:SI 0 "" "") (const_int 0))
2179 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2180 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2181 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2182 (label_ref (match_operand:SI 4 "" "")) (pc)))
2183 (set (match_dup 0) (const_int 1))
2184 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2185 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2186 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2187 (label_ref (match_dup 4)) (pc)))]
2188 "TARGET_POWER"
2189 "
2190 { operands[5] = gen_reg_rtx (CCUNSmode);
2191 operands[6] = gen_reg_rtx (CCmode);
2192 }")
2193
2194 (define_expand "udivmodsi4"
2195 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2196 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2197 (match_operand:SI 2 "reg_or_cint_operand" "")))
2198 (set (match_operand:SI 3 "gpc_reg_operand" "")
2199 (umod:SI (match_dup 1) (match_dup 2)))])]
2200 ""
2201 "
2202 {
2203 rtx label = 0;
2204
2205 if (! TARGET_POWER)
2206 {
2207 if (! TARGET_POWERPC)
2208 {
2209 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2210 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2211 emit_insn (gen_divus_call ());
2212 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2213 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2214 DONE;
2215 }
2216 else
2217 FAIL;
2218 }
2219
2220 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2221 {
2222 operands[2] = force_reg (SImode, operands[2]);
2223 label = gen_label_rtx ();
2224 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2225 operands[3], label));
2226 }
2227 else
2228 operands[2] = force_reg (SImode, operands[2]);
2229
2230 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2231 operands[3]));
2232 if (label)
2233 emit_label (label);
2234
2235 DONE;
2236 }")
2237
2238 ;; AIX architecture-independent common-mode multiply (DImode),
2239 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2240 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2241 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2242 ;; assumed unused if generating common-mode, so ignore.
2243 (define_insn "mulh_call"
2244 [(set (reg:SI 3)
2245 (truncate:SI
2246 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2247 (sign_extend:DI (reg:SI 4)))
2248 (const_int 32))))
2249 (clobber (match_scratch:SI 0 "=l"))]
2250 "! TARGET_POWER && ! TARGET_POWERPC"
2251 "bla __mulh"
2252 [(set_attr "type" "imul")])
2253
2254 (define_insn "mull_call"
2255 [(set (reg:DI 3)
2256 (mult:DI (sign_extend:DI (reg:SI 3))
2257 (sign_extend:DI (reg:SI 4))))
2258 (clobber (match_scratch:SI 0 "=l"))
2259 (clobber (reg:SI 0))]
2260 "! TARGET_POWER && ! TARGET_POWERPC"
2261 "bla __mull"
2262 [(set_attr "type" "imul")])
2263
2264 (define_insn "divss_call"
2265 [(set (reg:SI 3)
2266 (div:SI (reg:SI 3) (reg:SI 4)))
2267 (set (reg:SI 4)
2268 (mod:SI (reg:SI 3) (reg:SI 4)))
2269 (clobber (match_scratch:SI 0 "=l"))
2270 (clobber (reg:SI 0))]
2271 "! TARGET_POWER && ! TARGET_POWERPC"
2272 "bla __divss"
2273 [(set_attr "type" "idiv")])
2274
2275 (define_insn "divus_call"
2276 [(set (reg:SI 3)
2277 (udiv:SI (reg:SI 3) (reg:SI 4)))
2278 (set (reg:SI 4)
2279 (umod:SI (reg:SI 3) (reg:SI 4)))
2280 (clobber (match_scratch:SI 0 "=l"))
2281 (clobber (reg:SI 0))
2282 (clobber (match_scratch:CC 1 "=x"))
2283 (clobber (reg:CC 69))]
2284 "! TARGET_POWER && ! TARGET_POWERPC"
2285 "bla __divus"
2286 [(set_attr "type" "idiv")])
2287
2288 (define_insn "quoss_call"
2289 [(set (reg:SI 3)
2290 (div:SI (reg:SI 3) (reg:SI 4)))
2291 (clobber (match_scratch:SI 0 "=l"))]
2292 "! TARGET_POWER && ! TARGET_POWERPC"
2293 "bla __quoss"
2294 [(set_attr "type" "idiv")])
2295
2296 (define_insn "quous_call"
2297 [(set (reg:SI 3)
2298 (udiv:SI (reg:SI 3) (reg:SI 4)))
2299 (clobber (match_scratch:SI 0 "=l"))
2300 (clobber (reg:SI 0))
2301 (clobber (match_scratch:CC 1 "=x"))
2302 (clobber (reg:CC 69))]
2303 "! TARGET_POWER && ! TARGET_POWERPC"
2304 "bla __quous"
2305 [(set_attr "type" "idiv")])
2306 \f
2307 ;; Logical instructions
2308 ;; The logical instructions are mostly combined by using match_operator,
2309 ;; but the plain AND insns are somewhat different because there is no
2310 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2311 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2312
2313 (define_insn "andsi3"
2314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2315 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2316 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2317 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2318 ""
2319 "@
2320 and %0,%1,%2
2321 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2322 {andil.|andi.} %0,%1,%b2
2323 {andiu.|andis.} %0,%1,%u2"
2324 [(set_attr "type" "*,*,compare,compare")])
2325
2326 ;; Note to set cr's other than cr0 we do the and immediate and then
2327 ;; the test again -- this avoids a mfcr which on the higher end
2328 ;; machines causes an execution serialization
2329
2330 (define_insn "*andsi3_internal2"
2331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2332 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2333 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2334 (const_int 0)))
2335 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2336 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2337 "TARGET_32BIT"
2338 "@
2339 and. %3,%1,%2
2340 {andil.|andi.} %3,%1,%b2
2341 {andiu.|andis.} %3,%1,%u2
2342 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2343 #
2344 #
2345 #
2346 #"
2347 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2348 (set_attr "length" "4,4,4,4,8,8,8,8")])
2349
2350 (define_insn "*andsi3_internal3"
2351 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2352 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2353 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2354 (const_int 0)))
2355 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2356 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2357 "TARGET_64BIT"
2358 "@
2359 #
2360 {andil.|andi.} %3,%1,%b2
2361 {andiu.|andis.} %3,%1,%u2
2362 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2363 #
2364 #
2365 #
2366 #"
2367 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2368 (set_attr "length" "8,4,4,4,8,8,8,8")])
2369
2370 (define_split
2371 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2372 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2373 (match_operand:GPR 2 "and_operand" ""))
2374 (const_int 0)))
2375 (clobber (match_scratch:GPR 3 ""))
2376 (clobber (match_scratch:CC 4 ""))]
2377 "reload_completed"
2378 [(parallel [(set (match_dup 3)
2379 (and:<MODE> (match_dup 1)
2380 (match_dup 2)))
2381 (clobber (match_dup 4))])
2382 (set (match_dup 0)
2383 (compare:CC (match_dup 3)
2384 (const_int 0)))]
2385 "")
2386
2387 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2388 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2389
2390 (define_split
2391 [(set (match_operand:CC 0 "cc_reg_operand" "")
2392 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2393 (match_operand:SI 2 "gpc_reg_operand" ""))
2394 (const_int 0)))
2395 (clobber (match_scratch:SI 3 ""))
2396 (clobber (match_scratch:CC 4 ""))]
2397 "TARGET_POWERPC64 && reload_completed"
2398 [(parallel [(set (match_dup 3)
2399 (and:SI (match_dup 1)
2400 (match_dup 2)))
2401 (clobber (match_dup 4))])
2402 (set (match_dup 0)
2403 (compare:CC (match_dup 3)
2404 (const_int 0)))]
2405 "")
2406
2407 (define_insn "*andsi3_internal4"
2408 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2409 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2410 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2411 (const_int 0)))
2412 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2413 (and:SI (match_dup 1)
2414 (match_dup 2)))
2415 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2416 "TARGET_32BIT"
2417 "@
2418 and. %0,%1,%2
2419 {andil.|andi.} %0,%1,%b2
2420 {andiu.|andis.} %0,%1,%u2
2421 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2422 #
2423 #
2424 #
2425 #"
2426 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2427 (set_attr "length" "4,4,4,4,8,8,8,8")])
2428
2429 (define_insn "*andsi3_internal5"
2430 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2431 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2432 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2433 (const_int 0)))
2434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2435 (and:SI (match_dup 1)
2436 (match_dup 2)))
2437 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2438 "TARGET_64BIT"
2439 "@
2440 #
2441 {andil.|andi.} %0,%1,%b2
2442 {andiu.|andis.} %0,%1,%u2
2443 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2444 #
2445 #
2446 #
2447 #"
2448 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2449 (set_attr "length" "8,4,4,4,8,8,8,8")])
2450
2451 (define_split
2452 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2453 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2454 (match_operand:SI 2 "and_operand" ""))
2455 (const_int 0)))
2456 (set (match_operand:SI 0 "gpc_reg_operand" "")
2457 (and:SI (match_dup 1)
2458 (match_dup 2)))
2459 (clobber (match_scratch:CC 4 ""))]
2460 "reload_completed"
2461 [(parallel [(set (match_dup 0)
2462 (and:SI (match_dup 1)
2463 (match_dup 2)))
2464 (clobber (match_dup 4))])
2465 (set (match_dup 3)
2466 (compare:CC (match_dup 0)
2467 (const_int 0)))]
2468 "")
2469
2470 (define_split
2471 [(set (match_operand:CC 3 "cc_reg_operand" "")
2472 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2473 (match_operand:SI 2 "gpc_reg_operand" ""))
2474 (const_int 0)))
2475 (set (match_operand:SI 0 "gpc_reg_operand" "")
2476 (and:SI (match_dup 1)
2477 (match_dup 2)))
2478 (clobber (match_scratch:CC 4 ""))]
2479 "TARGET_POWERPC64 && reload_completed"
2480 [(parallel [(set (match_dup 0)
2481 (and:SI (match_dup 1)
2482 (match_dup 2)))
2483 (clobber (match_dup 4))])
2484 (set (match_dup 3)
2485 (compare:CC (match_dup 0)
2486 (const_int 0)))]
2487 "")
2488
2489 ;; Handle the PowerPC64 rlwinm corner case
2490
2491 (define_insn_and_split "*andsi3_internal6"
2492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2493 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2494 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2495 "TARGET_POWERPC64"
2496 "#"
2497 "TARGET_POWERPC64"
2498 [(set (match_dup 0)
2499 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2500 (match_dup 4)))
2501 (set (match_dup 0)
2502 (rotate:SI (match_dup 0) (match_dup 5)))]
2503 "
2504 {
2505 int mb = extract_MB (operands[2]);
2506 int me = extract_ME (operands[2]);
2507 operands[3] = GEN_INT (me + 1);
2508 operands[5] = GEN_INT (32 - (me + 1));
2509 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2510 }"
2511 [(set_attr "length" "8")])
2512
2513 (define_expand "iorsi3"
2514 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2515 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2516 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2517 ""
2518 "
2519 {
2520 if (GET_CODE (operands[2]) == CONST_INT
2521 && ! logical_operand (operands[2], SImode))
2522 {
2523 HOST_WIDE_INT value = INTVAL (operands[2]);
2524 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2525 ? operands[0] : gen_reg_rtx (SImode));
2526
2527 emit_insn (gen_iorsi3 (tmp, operands[1],
2528 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2529 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2530 DONE;
2531 }
2532 }")
2533
2534 (define_expand "xorsi3"
2535 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2536 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2537 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2538 ""
2539 "
2540 {
2541 if (GET_CODE (operands[2]) == CONST_INT
2542 && ! logical_operand (operands[2], SImode))
2543 {
2544 HOST_WIDE_INT value = INTVAL (operands[2]);
2545 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2546 ? operands[0] : gen_reg_rtx (SImode));
2547
2548 emit_insn (gen_xorsi3 (tmp, operands[1],
2549 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2550 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2551 DONE;
2552 }
2553 }")
2554
2555 (define_insn "*boolsi3_internal1"
2556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2557 (match_operator:SI 3 "boolean_or_operator"
2558 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2559 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2560 ""
2561 "@
2562 %q3 %0,%1,%2
2563 {%q3il|%q3i} %0,%1,%b2
2564 {%q3iu|%q3is} %0,%1,%u2")
2565
2566 (define_insn "*boolsi3_internal2"
2567 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2568 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2569 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2570 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2571 (const_int 0)))
2572 (clobber (match_scratch:SI 3 "=r,r"))]
2573 "TARGET_32BIT"
2574 "@
2575 %q4. %3,%1,%2
2576 #"
2577 [(set_attr "type" "compare")
2578 (set_attr "length" "4,8")])
2579
2580 (define_split
2581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2582 (compare:CC (match_operator:SI 4 "boolean_operator"
2583 [(match_operand:SI 1 "gpc_reg_operand" "")
2584 (match_operand:SI 2 "gpc_reg_operand" "")])
2585 (const_int 0)))
2586 (clobber (match_scratch:SI 3 ""))]
2587 "TARGET_32BIT && reload_completed"
2588 [(set (match_dup 3) (match_dup 4))
2589 (set (match_dup 0)
2590 (compare:CC (match_dup 3)
2591 (const_int 0)))]
2592 "")
2593
2594 (define_insn "*boolsi3_internal3"
2595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2596 (compare:CC (match_operator:SI 4 "boolean_operator"
2597 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2598 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2599 (const_int 0)))
2600 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2601 (match_dup 4))]
2602 "TARGET_32BIT"
2603 "@
2604 %q4. %0,%1,%2
2605 #"
2606 [(set_attr "type" "compare")
2607 (set_attr "length" "4,8")])
2608
2609 (define_split
2610 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2611 (compare:CC (match_operator:SI 4 "boolean_operator"
2612 [(match_operand:SI 1 "gpc_reg_operand" "")
2613 (match_operand:SI 2 "gpc_reg_operand" "")])
2614 (const_int 0)))
2615 (set (match_operand:SI 0 "gpc_reg_operand" "")
2616 (match_dup 4))]
2617 "TARGET_32BIT && reload_completed"
2618 [(set (match_dup 0) (match_dup 4))
2619 (set (match_dup 3)
2620 (compare:CC (match_dup 0)
2621 (const_int 0)))]
2622 "")
2623
2624 ;; Split a logical operation that we can't do in one insn into two insns,
2625 ;; each of which does one 16-bit part. This is used by combine.
2626
2627 (define_split
2628 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2629 (match_operator:SI 3 "boolean_or_operator"
2630 [(match_operand:SI 1 "gpc_reg_operand" "")
2631 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2632 ""
2633 [(set (match_dup 0) (match_dup 4))
2634 (set (match_dup 0) (match_dup 5))]
2635 "
2636 {
2637 rtx i;
2638 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2639 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2640 operands[1], i);
2641 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2642 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2643 operands[0], i);
2644 }")
2645
2646 (define_insn "*boolcsi3_internal1"
2647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2648 (match_operator:SI 3 "boolean_operator"
2649 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2650 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2651 ""
2652 "%q3 %0,%2,%1")
2653
2654 (define_insn "*boolcsi3_internal2"
2655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2656 (compare:CC (match_operator:SI 4 "boolean_operator"
2657 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2658 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2659 (const_int 0)))
2660 (clobber (match_scratch:SI 3 "=r,r"))]
2661 "TARGET_32BIT"
2662 "@
2663 %q4. %3,%2,%1
2664 #"
2665 [(set_attr "type" "compare")
2666 (set_attr "length" "4,8")])
2667
2668 (define_split
2669 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2670 (compare:CC (match_operator:SI 4 "boolean_operator"
2671 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2672 (match_operand:SI 2 "gpc_reg_operand" "")])
2673 (const_int 0)))
2674 (clobber (match_scratch:SI 3 ""))]
2675 "TARGET_32BIT && reload_completed"
2676 [(set (match_dup 3) (match_dup 4))
2677 (set (match_dup 0)
2678 (compare:CC (match_dup 3)
2679 (const_int 0)))]
2680 "")
2681
2682 (define_insn "*boolcsi3_internal3"
2683 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2684 (compare:CC (match_operator:SI 4 "boolean_operator"
2685 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2686 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2687 (const_int 0)))
2688 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2689 (match_dup 4))]
2690 "TARGET_32BIT"
2691 "@
2692 %q4. %0,%2,%1
2693 #"
2694 [(set_attr "type" "compare")
2695 (set_attr "length" "4,8")])
2696
2697 (define_split
2698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2699 (compare:CC (match_operator:SI 4 "boolean_operator"
2700 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2701 (match_operand:SI 2 "gpc_reg_operand" "")])
2702 (const_int 0)))
2703 (set (match_operand:SI 0 "gpc_reg_operand" "")
2704 (match_dup 4))]
2705 "TARGET_32BIT && reload_completed"
2706 [(set (match_dup 0) (match_dup 4))
2707 (set (match_dup 3)
2708 (compare:CC (match_dup 0)
2709 (const_int 0)))]
2710 "")
2711
2712 (define_insn "*boolccsi3_internal1"
2713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2714 (match_operator:SI 3 "boolean_operator"
2715 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2716 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2717 ""
2718 "%q3 %0,%1,%2")
2719
2720 (define_insn "*boolccsi3_internal2"
2721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2722 (compare:CC (match_operator:SI 4 "boolean_operator"
2723 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2724 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2725 (const_int 0)))
2726 (clobber (match_scratch:SI 3 "=r,r"))]
2727 "TARGET_32BIT"
2728 "@
2729 %q4. %3,%1,%2
2730 #"
2731 [(set_attr "type" "compare")
2732 (set_attr "length" "4,8")])
2733
2734 (define_split
2735 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2736 (compare:CC (match_operator:SI 4 "boolean_operator"
2737 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2738 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2739 (const_int 0)))
2740 (clobber (match_scratch:SI 3 ""))]
2741 "TARGET_32BIT && reload_completed"
2742 [(set (match_dup 3) (match_dup 4))
2743 (set (match_dup 0)
2744 (compare:CC (match_dup 3)
2745 (const_int 0)))]
2746 "")
2747
2748 (define_insn "*boolccsi3_internal3"
2749 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2750 (compare:CC (match_operator:SI 4 "boolean_operator"
2751 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2752 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2753 (const_int 0)))
2754 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2755 (match_dup 4))]
2756 "TARGET_32BIT"
2757 "@
2758 %q4. %0,%1,%2
2759 #"
2760 [(set_attr "type" "compare")
2761 (set_attr "length" "4,8")])
2762
2763 (define_split
2764 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2765 (compare:CC (match_operator:SI 4 "boolean_operator"
2766 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2767 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2768 (const_int 0)))
2769 (set (match_operand:SI 0 "gpc_reg_operand" "")
2770 (match_dup 4))]
2771 "TARGET_32BIT && reload_completed"
2772 [(set (match_dup 0) (match_dup 4))
2773 (set (match_dup 3)
2774 (compare:CC (match_dup 0)
2775 (const_int 0)))]
2776 "")
2777
2778 ;; maskir insn. We need four forms because things might be in arbitrary
2779 ;; orders. Don't define forms that only set CR fields because these
2780 ;; would modify an input register.
2781
2782 (define_insn "*maskir_internal1"
2783 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2784 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2785 (match_operand:SI 1 "gpc_reg_operand" "0"))
2786 (and:SI (match_dup 2)
2787 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2788 "TARGET_POWER"
2789 "maskir %0,%3,%2")
2790
2791 (define_insn "*maskir_internal2"
2792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2793 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2794 (match_operand:SI 1 "gpc_reg_operand" "0"))
2795 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2796 (match_dup 2))))]
2797 "TARGET_POWER"
2798 "maskir %0,%3,%2")
2799
2800 (define_insn "*maskir_internal3"
2801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2802 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2803 (match_operand:SI 3 "gpc_reg_operand" "r"))
2804 (and:SI (not:SI (match_dup 2))
2805 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2806 "TARGET_POWER"
2807 "maskir %0,%3,%2")
2808
2809 (define_insn "*maskir_internal4"
2810 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2811 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2812 (match_operand:SI 2 "gpc_reg_operand" "r"))
2813 (and:SI (not:SI (match_dup 2))
2814 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2815 "TARGET_POWER"
2816 "maskir %0,%3,%2")
2817
2818 (define_insn "*maskir_internal5"
2819 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2820 (compare:CC
2821 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2822 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2823 (and:SI (match_dup 2)
2824 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2825 (const_int 0)))
2826 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2827 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2828 (and:SI (match_dup 2) (match_dup 3))))]
2829 "TARGET_POWER"
2830 "@
2831 maskir. %0,%3,%2
2832 #"
2833 [(set_attr "type" "compare")
2834 (set_attr "length" "4,8")])
2835
2836 (define_split
2837 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2838 (compare:CC
2839 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2840 (match_operand:SI 1 "gpc_reg_operand" ""))
2841 (and:SI (match_dup 2)
2842 (match_operand:SI 3 "gpc_reg_operand" "")))
2843 (const_int 0)))
2844 (set (match_operand:SI 0 "gpc_reg_operand" "")
2845 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2846 (and:SI (match_dup 2) (match_dup 3))))]
2847 "TARGET_POWER && reload_completed"
2848 [(set (match_dup 0)
2849 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2850 (and:SI (match_dup 2) (match_dup 3))))
2851 (set (match_dup 4)
2852 (compare:CC (match_dup 0)
2853 (const_int 0)))]
2854 "")
2855
2856 (define_insn "*maskir_internal6"
2857 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2858 (compare:CC
2859 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2860 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2861 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2862 (match_dup 2)))
2863 (const_int 0)))
2864 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2865 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2866 (and:SI (match_dup 3) (match_dup 2))))]
2867 "TARGET_POWER"
2868 "@
2869 maskir. %0,%3,%2
2870 #"
2871 [(set_attr "type" "compare")
2872 (set_attr "length" "4,8")])
2873
2874 (define_split
2875 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2876 (compare:CC
2877 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2878 (match_operand:SI 1 "gpc_reg_operand" ""))
2879 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2880 (match_dup 2)))
2881 (const_int 0)))
2882 (set (match_operand:SI 0 "gpc_reg_operand" "")
2883 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2884 (and:SI (match_dup 3) (match_dup 2))))]
2885 "TARGET_POWER && reload_completed"
2886 [(set (match_dup 0)
2887 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2888 (and:SI (match_dup 3) (match_dup 2))))
2889 (set (match_dup 4)
2890 (compare:CC (match_dup 0)
2891 (const_int 0)))]
2892 "")
2893
2894 (define_insn "*maskir_internal7"
2895 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2896 (compare:CC
2897 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2898 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2899 (and:SI (not:SI (match_dup 2))
2900 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2901 (const_int 0)))
2902 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2903 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2904 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2905 "TARGET_POWER"
2906 "@
2907 maskir. %0,%3,%2
2908 #"
2909 [(set_attr "type" "compare")
2910 (set_attr "length" "4,8")])
2911
2912 (define_split
2913 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2914 (compare:CC
2915 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2916 (match_operand:SI 3 "gpc_reg_operand" ""))
2917 (and:SI (not:SI (match_dup 2))
2918 (match_operand:SI 1 "gpc_reg_operand" "")))
2919 (const_int 0)))
2920 (set (match_operand:SI 0 "gpc_reg_operand" "")
2921 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2922 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2923 "TARGET_POWER && reload_completed"
2924 [(set (match_dup 0)
2925 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2926 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2927 (set (match_dup 4)
2928 (compare:CC (match_dup 0)
2929 (const_int 0)))]
2930 "")
2931
2932 (define_insn "*maskir_internal8"
2933 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2934 (compare:CC
2935 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2936 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2937 (and:SI (not:SI (match_dup 2))
2938 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2939 (const_int 0)))
2940 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2941 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2942 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2943 "TARGET_POWER"
2944 "@
2945 maskir. %0,%3,%2
2946 #"
2947 [(set_attr "type" "compare")
2948 (set_attr "length" "4,8")])
2949
2950 (define_split
2951 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2952 (compare:CC
2953 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2954 (match_operand:SI 2 "gpc_reg_operand" ""))
2955 (and:SI (not:SI (match_dup 2))
2956 (match_operand:SI 1 "gpc_reg_operand" "")))
2957 (const_int 0)))
2958 (set (match_operand:SI 0 "gpc_reg_operand" "")
2959 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2960 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2961 "TARGET_POWER && reload_completed"
2962 [(set (match_dup 0)
2963 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2964 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2965 (set (match_dup 4)
2966 (compare:CC (match_dup 0)
2967 (const_int 0)))]
2968 "")
2969 \f
2970 ;; Rotate and shift insns, in all their variants. These support shifts,
2971 ;; field inserts and extracts, and various combinations thereof.
2972 (define_expand "insv"
2973 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2974 (match_operand:SI 1 "const_int_operand" "")
2975 (match_operand:SI 2 "const_int_operand" ""))
2976 (match_operand 3 "gpc_reg_operand" ""))]
2977 ""
2978 "
2979 {
2980 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2981 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2982 compiler if the address of the structure is taken later. */
2983 if (GET_CODE (operands[0]) == SUBREG
2984 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2985 FAIL;
2986
2987 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2988 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2989 else
2990 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2991 DONE;
2992 }")
2993
2994 (define_insn "insvsi"
2995 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2996 (match_operand:SI 1 "const_int_operand" "i")
2997 (match_operand:SI 2 "const_int_operand" "i"))
2998 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2999 ""
3000 "*
3001 {
3002 int start = INTVAL (operands[2]) & 31;
3003 int size = INTVAL (operands[1]) & 31;
3004
3005 operands[4] = GEN_INT (32 - start - size);
3006 operands[1] = GEN_INT (start + size - 1);
3007 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3008 }"
3009 [(set_attr "type" "insert_word")])
3010
3011 (define_insn "*insvsi_internal1"
3012 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3013 (match_operand:SI 1 "const_int_operand" "i")
3014 (match_operand:SI 2 "const_int_operand" "i"))
3015 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3016 (match_operand:SI 4 "const_int_operand" "i")))]
3017 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3018 "*
3019 {
3020 int shift = INTVAL (operands[4]) & 31;
3021 int start = INTVAL (operands[2]) & 31;
3022 int size = INTVAL (operands[1]) & 31;
3023
3024 operands[4] = GEN_INT (shift - start - size);
3025 operands[1] = GEN_INT (start + size - 1);
3026 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3027 }"
3028 [(set_attr "type" "insert_word")])
3029
3030 (define_insn "*insvsi_internal2"
3031 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3032 (match_operand:SI 1 "const_int_operand" "i")
3033 (match_operand:SI 2 "const_int_operand" "i"))
3034 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3035 (match_operand:SI 4 "const_int_operand" "i")))]
3036 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3037 "*
3038 {
3039 int shift = INTVAL (operands[4]) & 31;
3040 int start = INTVAL (operands[2]) & 31;
3041 int size = INTVAL (operands[1]) & 31;
3042
3043 operands[4] = GEN_INT (32 - shift - start - size);
3044 operands[1] = GEN_INT (start + size - 1);
3045 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3046 }"
3047 [(set_attr "type" "insert_word")])
3048
3049 (define_insn "*insvsi_internal3"
3050 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3051 (match_operand:SI 1 "const_int_operand" "i")
3052 (match_operand:SI 2 "const_int_operand" "i"))
3053 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3054 (match_operand:SI 4 "const_int_operand" "i")))]
3055 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3056 "*
3057 {
3058 int shift = INTVAL (operands[4]) & 31;
3059 int start = INTVAL (operands[2]) & 31;
3060 int size = INTVAL (operands[1]) & 31;
3061
3062 operands[4] = GEN_INT (32 - shift - start - size);
3063 operands[1] = GEN_INT (start + size - 1);
3064 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3065 }"
3066 [(set_attr "type" "insert_word")])
3067
3068 (define_insn "*insvsi_internal4"
3069 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3070 (match_operand:SI 1 "const_int_operand" "i")
3071 (match_operand:SI 2 "const_int_operand" "i"))
3072 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3073 (match_operand:SI 4 "const_int_operand" "i")
3074 (match_operand:SI 5 "const_int_operand" "i")))]
3075 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3076 "*
3077 {
3078 int extract_start = INTVAL (operands[5]) & 31;
3079 int extract_size = INTVAL (operands[4]) & 31;
3080 int insert_start = INTVAL (operands[2]) & 31;
3081 int insert_size = INTVAL (operands[1]) & 31;
3082
3083 /* Align extract field with insert field */
3084 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3085 operands[1] = GEN_INT (insert_start + insert_size - 1);
3086 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3087 }"
3088 [(set_attr "type" "insert_word")])
3089
3090 ;; combine patterns for rlwimi
3091 (define_insn "*insvsi_internal5"
3092 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3093 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3094 (match_operand:SI 1 "mask_operand" "i"))
3095 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3096 (match_operand:SI 2 "const_int_operand" "i"))
3097 (match_operand:SI 5 "mask_operand" "i"))))]
3098 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3099 "*
3100 {
3101 int me = extract_ME(operands[5]);
3102 int mb = extract_MB(operands[5]);
3103 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3104 operands[2] = GEN_INT(mb);
3105 operands[1] = GEN_INT(me);
3106 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3107 }"
3108 [(set_attr "type" "insert_word")])
3109
3110 (define_insn "*insvsi_internal6"
3111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3112 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3113 (match_operand:SI 2 "const_int_operand" "i"))
3114 (match_operand:SI 5 "mask_operand" "i"))
3115 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3116 (match_operand:SI 1 "mask_operand" "i"))))]
3117 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3118 "*
3119 {
3120 int me = extract_ME(operands[5]);
3121 int mb = extract_MB(operands[5]);
3122 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3123 operands[2] = GEN_INT(mb);
3124 operands[1] = GEN_INT(me);
3125 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3126 }"
3127 [(set_attr "type" "insert_word")])
3128
3129 (define_insn "insvdi"
3130 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3131 (match_operand:SI 1 "const_int_operand" "i")
3132 (match_operand:SI 2 "const_int_operand" "i"))
3133 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3134 "TARGET_POWERPC64"
3135 "*
3136 {
3137 int start = INTVAL (operands[2]) & 63;
3138 int size = INTVAL (operands[1]) & 63;
3139
3140 operands[1] = GEN_INT (64 - start - size);
3141 return \"rldimi %0,%3,%H1,%H2\";
3142 }")
3143
3144 (define_insn "*insvdi_internal2"
3145 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3146 (match_operand:SI 1 "const_int_operand" "i")
3147 (match_operand:SI 2 "const_int_operand" "i"))
3148 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3149 (match_operand:SI 4 "const_int_operand" "i")))]
3150 "TARGET_POWERPC64
3151 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3152 "*
3153 {
3154 int shift = INTVAL (operands[4]) & 63;
3155 int start = (INTVAL (operands[2]) & 63) - 32;
3156 int size = INTVAL (operands[1]) & 63;
3157
3158 operands[4] = GEN_INT (64 - shift - start - size);
3159 operands[2] = GEN_INT (start);
3160 operands[1] = GEN_INT (start + size - 1);
3161 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3162 }")
3163
3164 (define_insn "*insvdi_internal3"
3165 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3166 (match_operand:SI 1 "const_int_operand" "i")
3167 (match_operand:SI 2 "const_int_operand" "i"))
3168 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3169 (match_operand:SI 4 "const_int_operand" "i")))]
3170 "TARGET_POWERPC64
3171 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3172 "*
3173 {
3174 int shift = INTVAL (operands[4]) & 63;
3175 int start = (INTVAL (operands[2]) & 63) - 32;
3176 int size = INTVAL (operands[1]) & 63;
3177
3178 operands[4] = GEN_INT (64 - shift - start - size);
3179 operands[2] = GEN_INT (start);
3180 operands[1] = GEN_INT (start + size - 1);
3181 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3182 }")
3183
3184 (define_expand "extzv"
3185 [(set (match_operand 0 "gpc_reg_operand" "")
3186 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3187 (match_operand:SI 2 "const_int_operand" "")
3188 (match_operand:SI 3 "const_int_operand" "")))]
3189 ""
3190 "
3191 {
3192 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3193 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3194 compiler if the address of the structure is taken later. */
3195 if (GET_CODE (operands[0]) == SUBREG
3196 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3197 FAIL;
3198
3199 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3200 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3201 else
3202 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3203 DONE;
3204 }")
3205
3206 (define_insn "extzvsi"
3207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3208 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3209 (match_operand:SI 2 "const_int_operand" "i")
3210 (match_operand:SI 3 "const_int_operand" "i")))]
3211 ""
3212 "*
3213 {
3214 int start = INTVAL (operands[3]) & 31;
3215 int size = INTVAL (operands[2]) & 31;
3216
3217 if (start + size >= 32)
3218 operands[3] = const0_rtx;
3219 else
3220 operands[3] = GEN_INT (start + size);
3221 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3222 }")
3223
3224 (define_insn "*extzvsi_internal1"
3225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3226 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3227 (match_operand:SI 2 "const_int_operand" "i,i")
3228 (match_operand:SI 3 "const_int_operand" "i,i"))
3229 (const_int 0)))
3230 (clobber (match_scratch:SI 4 "=r,r"))]
3231 ""
3232 "*
3233 {
3234 int start = INTVAL (operands[3]) & 31;
3235 int size = INTVAL (operands[2]) & 31;
3236
3237 /* Force split for non-cc0 compare. */
3238 if (which_alternative == 1)
3239 return \"#\";
3240
3241 /* If the bit-field being tested fits in the upper or lower half of a
3242 word, it is possible to use andiu. or andil. to test it. This is
3243 useful because the condition register set-use delay is smaller for
3244 andi[ul]. than for rlinm. This doesn't work when the starting bit
3245 position is 0 because the LT and GT bits may be set wrong. */
3246
3247 if ((start > 0 && start + size <= 16) || start >= 16)
3248 {
3249 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3250 - (1 << (16 - (start & 15) - size))));
3251 if (start < 16)
3252 return \"{andiu.|andis.} %4,%1,%3\";
3253 else
3254 return \"{andil.|andi.} %4,%1,%3\";
3255 }
3256
3257 if (start + size >= 32)
3258 operands[3] = const0_rtx;
3259 else
3260 operands[3] = GEN_INT (start + size);
3261 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3262 }"
3263 [(set_attr "type" "compare")
3264 (set_attr "length" "4,8")])
3265
3266 (define_split
3267 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3268 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3269 (match_operand:SI 2 "const_int_operand" "")
3270 (match_operand:SI 3 "const_int_operand" ""))
3271 (const_int 0)))
3272 (clobber (match_scratch:SI 4 ""))]
3273 "reload_completed"
3274 [(set (match_dup 4)
3275 (zero_extract:SI (match_dup 1) (match_dup 2)
3276 (match_dup 3)))
3277 (set (match_dup 0)
3278 (compare:CC (match_dup 4)
3279 (const_int 0)))]
3280 "")
3281
3282 (define_insn "*extzvsi_internal2"
3283 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3284 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3285 (match_operand:SI 2 "const_int_operand" "i,i")
3286 (match_operand:SI 3 "const_int_operand" "i,i"))
3287 (const_int 0)))
3288 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3289 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3290 ""
3291 "*
3292 {
3293 int start = INTVAL (operands[3]) & 31;
3294 int size = INTVAL (operands[2]) & 31;
3295
3296 /* Force split for non-cc0 compare. */
3297 if (which_alternative == 1)
3298 return \"#\";
3299
3300 /* Since we are using the output value, we can't ignore any need for
3301 a shift. The bit-field must end at the LSB. */
3302 if (start >= 16 && start + size == 32)
3303 {
3304 operands[3] = GEN_INT ((1 << size) - 1);
3305 return \"{andil.|andi.} %0,%1,%3\";
3306 }
3307
3308 if (start + size >= 32)
3309 operands[3] = const0_rtx;
3310 else
3311 operands[3] = GEN_INT (start + size);
3312 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3313 }"
3314 [(set_attr "type" "compare")
3315 (set_attr "length" "4,8")])
3316
3317 (define_split
3318 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3319 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3320 (match_operand:SI 2 "const_int_operand" "")
3321 (match_operand:SI 3 "const_int_operand" ""))
3322 (const_int 0)))
3323 (set (match_operand:SI 0 "gpc_reg_operand" "")
3324 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3325 "reload_completed"
3326 [(set (match_dup 0)
3327 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3328 (set (match_dup 4)
3329 (compare:CC (match_dup 0)
3330 (const_int 0)))]
3331 "")
3332
3333 (define_insn "extzvdi"
3334 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3335 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3336 (match_operand:SI 2 "const_int_operand" "i")
3337 (match_operand:SI 3 "const_int_operand" "i")))]
3338 "TARGET_POWERPC64"
3339 "*
3340 {
3341 int start = INTVAL (operands[3]) & 63;
3342 int size = INTVAL (operands[2]) & 63;
3343
3344 if (start + size >= 64)
3345 operands[3] = const0_rtx;
3346 else
3347 operands[3] = GEN_INT (start + size);
3348 operands[2] = GEN_INT (64 - size);
3349 return \"rldicl %0,%1,%3,%2\";
3350 }")
3351
3352 (define_insn "*extzvdi_internal1"
3353 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3354 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3355 (match_operand:SI 2 "const_int_operand" "i")
3356 (match_operand:SI 3 "const_int_operand" "i"))
3357 (const_int 0)))
3358 (clobber (match_scratch:DI 4 "=r"))]
3359 "TARGET_64BIT"
3360 "*
3361 {
3362 int start = INTVAL (operands[3]) & 63;
3363 int size = INTVAL (operands[2]) & 63;
3364
3365 if (start + size >= 64)
3366 operands[3] = const0_rtx;
3367 else
3368 operands[3] = GEN_INT (start + size);
3369 operands[2] = GEN_INT (64 - size);
3370 return \"rldicl. %4,%1,%3,%2\";
3371 }"
3372 [(set_attr "type" "compare")])
3373
3374 (define_insn "*extzvdi_internal2"
3375 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3376 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3377 (match_operand:SI 2 "const_int_operand" "i")
3378 (match_operand:SI 3 "const_int_operand" "i"))
3379 (const_int 0)))
3380 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3381 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3382 "TARGET_64BIT"
3383 "*
3384 {
3385 int start = INTVAL (operands[3]) & 63;
3386 int size = INTVAL (operands[2]) & 63;
3387
3388 if (start + size >= 64)
3389 operands[3] = const0_rtx;
3390 else
3391 operands[3] = GEN_INT (start + size);
3392 operands[2] = GEN_INT (64 - size);
3393 return \"rldicl. %0,%1,%3,%2\";
3394 }"
3395 [(set_attr "type" "compare")])
3396
3397 (define_insn "rotlsi3"
3398 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3399 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3400 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3401 ""
3402 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3403
3404 (define_insn "*rotlsi3_internal2"
3405 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3406 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3407 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3408 (const_int 0)))
3409 (clobber (match_scratch:SI 3 "=r,r"))]
3410 ""
3411 "@
3412 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3413 #"
3414 [(set_attr "type" "delayed_compare")
3415 (set_attr "length" "4,8")])
3416
3417 (define_split
3418 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3419 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3420 (match_operand:SI 2 "reg_or_cint_operand" ""))
3421 (const_int 0)))
3422 (clobber (match_scratch:SI 3 ""))]
3423 "reload_completed"
3424 [(set (match_dup 3)
3425 (rotate:SI (match_dup 1) (match_dup 2)))
3426 (set (match_dup 0)
3427 (compare:CC (match_dup 3)
3428 (const_int 0)))]
3429 "")
3430
3431 (define_insn "*rotlsi3_internal3"
3432 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3433 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3434 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3435 (const_int 0)))
3436 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3437 (rotate:SI (match_dup 1) (match_dup 2)))]
3438 ""
3439 "@
3440 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3441 #"
3442 [(set_attr "type" "delayed_compare")
3443 (set_attr "length" "4,8")])
3444
3445 (define_split
3446 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3447 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3448 (match_operand:SI 2 "reg_or_cint_operand" ""))
3449 (const_int 0)))
3450 (set (match_operand:SI 0 "gpc_reg_operand" "")
3451 (rotate:SI (match_dup 1) (match_dup 2)))]
3452 "reload_completed"
3453 [(set (match_dup 0)
3454 (rotate:SI (match_dup 1) (match_dup 2)))
3455 (set (match_dup 3)
3456 (compare:CC (match_dup 0)
3457 (const_int 0)))]
3458 "")
3459
3460 (define_insn "*rotlsi3_internal4"
3461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3462 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3463 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3464 (match_operand:SI 3 "mask_operand" "n")))]
3465 ""
3466 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3467
3468 (define_insn "*rotlsi3_internal5"
3469 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3470 (compare:CC (and:SI
3471 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3472 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3473 (match_operand:SI 3 "mask_operand" "n,n"))
3474 (const_int 0)))
3475 (clobber (match_scratch:SI 4 "=r,r"))]
3476 ""
3477 "@
3478 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3479 #"
3480 [(set_attr "type" "delayed_compare")
3481 (set_attr "length" "4,8")])
3482
3483 (define_split
3484 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3485 (compare:CC (and:SI
3486 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3487 (match_operand:SI 2 "reg_or_cint_operand" ""))
3488 (match_operand:SI 3 "mask_operand" ""))
3489 (const_int 0)))
3490 (clobber (match_scratch:SI 4 ""))]
3491 "reload_completed"
3492 [(set (match_dup 4)
3493 (and:SI (rotate:SI (match_dup 1)
3494 (match_dup 2))
3495 (match_dup 3)))
3496 (set (match_dup 0)
3497 (compare:CC (match_dup 4)
3498 (const_int 0)))]
3499 "")
3500
3501 (define_insn "*rotlsi3_internal6"
3502 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3503 (compare:CC (and:SI
3504 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3505 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3506 (match_operand:SI 3 "mask_operand" "n,n"))
3507 (const_int 0)))
3508 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3509 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3510 ""
3511 "@
3512 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3513 #"
3514 [(set_attr "type" "delayed_compare")
3515 (set_attr "length" "4,8")])
3516
3517 (define_split
3518 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3519 (compare:CC (and:SI
3520 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3521 (match_operand:SI 2 "reg_or_cint_operand" ""))
3522 (match_operand:SI 3 "mask_operand" ""))
3523 (const_int 0)))
3524 (set (match_operand:SI 0 "gpc_reg_operand" "")
3525 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3526 "reload_completed"
3527 [(set (match_dup 0)
3528 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3529 (set (match_dup 4)
3530 (compare:CC (match_dup 0)
3531 (const_int 0)))]
3532 "")
3533
3534 (define_insn "*rotlsi3_internal7"
3535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3536 (zero_extend:SI
3537 (subreg:QI
3538 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3539 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3540 ""
3541 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3542
3543 (define_insn "*rotlsi3_internal8"
3544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3545 (compare:CC (zero_extend:SI
3546 (subreg:QI
3547 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3548 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3549 (const_int 0)))
3550 (clobber (match_scratch:SI 3 "=r,r"))]
3551 ""
3552 "@
3553 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3554 #"
3555 [(set_attr "type" "delayed_compare")
3556 (set_attr "length" "4,8")])
3557
3558 (define_split
3559 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3560 (compare:CC (zero_extend:SI
3561 (subreg:QI
3562 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3563 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3564 (const_int 0)))
3565 (clobber (match_scratch:SI 3 ""))]
3566 "reload_completed"
3567 [(set (match_dup 3)
3568 (zero_extend:SI (subreg:QI
3569 (rotate:SI (match_dup 1)
3570 (match_dup 2)) 0)))
3571 (set (match_dup 0)
3572 (compare:CC (match_dup 3)
3573 (const_int 0)))]
3574 "")
3575
3576 (define_insn "*rotlsi3_internal9"
3577 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3578 (compare:CC (zero_extend:SI
3579 (subreg:QI
3580 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3581 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3582 (const_int 0)))
3583 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3584 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3585 ""
3586 "@
3587 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3588 #"
3589 [(set_attr "type" "delayed_compare")
3590 (set_attr "length" "4,8")])
3591
3592 (define_split
3593 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3594 (compare:CC (zero_extend:SI
3595 (subreg:QI
3596 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3597 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3598 (const_int 0)))
3599 (set (match_operand:SI 0 "gpc_reg_operand" "")
3600 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3601 "reload_completed"
3602 [(set (match_dup 0)
3603 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3604 (set (match_dup 3)
3605 (compare:CC (match_dup 0)
3606 (const_int 0)))]
3607 "")
3608
3609 (define_insn "*rotlsi3_internal10"
3610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3611 (zero_extend:SI
3612 (subreg:HI
3613 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3614 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3615 ""
3616 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3617
3618 (define_insn "*rotlsi3_internal11"
3619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3620 (compare:CC (zero_extend:SI
3621 (subreg:HI
3622 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3623 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3624 (const_int 0)))
3625 (clobber (match_scratch:SI 3 "=r,r"))]
3626 ""
3627 "@
3628 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3629 #"
3630 [(set_attr "type" "delayed_compare")
3631 (set_attr "length" "4,8")])
3632
3633 (define_split
3634 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3635 (compare:CC (zero_extend:SI
3636 (subreg:HI
3637 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 3 ""))]
3641 "reload_completed"
3642 [(set (match_dup 3)
3643 (zero_extend:SI (subreg:HI
3644 (rotate:SI (match_dup 1)
3645 (match_dup 2)) 0)))
3646 (set (match_dup 0)
3647 (compare:CC (match_dup 3)
3648 (const_int 0)))]
3649 "")
3650
3651 (define_insn "*rotlsi3_internal12"
3652 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3653 (compare:CC (zero_extend:SI
3654 (subreg:HI
3655 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3656 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3657 (const_int 0)))
3658 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3659 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3660 ""
3661 "@
3662 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3663 #"
3664 [(set_attr "type" "delayed_compare")
3665 (set_attr "length" "4,8")])
3666
3667 (define_split
3668 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3669 (compare:CC (zero_extend:SI
3670 (subreg:HI
3671 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3672 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3673 (const_int 0)))
3674 (set (match_operand:SI 0 "gpc_reg_operand" "")
3675 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3676 "reload_completed"
3677 [(set (match_dup 0)
3678 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3679 (set (match_dup 3)
3680 (compare:CC (match_dup 0)
3681 (const_int 0)))]
3682 "")
3683
3684 ;; Note that we use "sle." instead of "sl." so that we can set
3685 ;; SHIFT_COUNT_TRUNCATED.
3686
3687 (define_expand "ashlsi3"
3688 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3689 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3690 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3691 ""
3692 "
3693 {
3694 if (TARGET_POWER)
3695 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3696 else
3697 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3698 DONE;
3699 }")
3700
3701 (define_insn "ashlsi3_power"
3702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3703 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3704 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3705 (clobber (match_scratch:SI 3 "=q,X"))]
3706 "TARGET_POWER"
3707 "@
3708 sle %0,%1,%2
3709 {sli|slwi} %0,%1,%h2")
3710
3711 (define_insn "ashlsi3_no_power"
3712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3713 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3714 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3715 "! TARGET_POWER"
3716 "{sl|slw}%I2 %0,%1,%h2")
3717
3718 (define_insn ""
3719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3720 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3721 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3722 (const_int 0)))
3723 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3724 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3725 "TARGET_POWER"
3726 "@
3727 sle. %3,%1,%2
3728 {sli.|slwi.} %3,%1,%h2
3729 #
3730 #"
3731 [(set_attr "type" "delayed_compare")
3732 (set_attr "length" "4,4,8,8")])
3733
3734 (define_split
3735 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3736 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3737 (match_operand:SI 2 "reg_or_cint_operand" ""))
3738 (const_int 0)))
3739 (clobber (match_scratch:SI 3 ""))
3740 (clobber (match_scratch:SI 4 ""))]
3741 "TARGET_POWER && reload_completed"
3742 [(parallel [(set (match_dup 3)
3743 (ashift:SI (match_dup 1) (match_dup 2)))
3744 (clobber (match_dup 4))])
3745 (set (match_dup 0)
3746 (compare:CC (match_dup 3)
3747 (const_int 0)))]
3748 "")
3749
3750 (define_insn ""
3751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3752 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3753 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3754 (const_int 0)))
3755 (clobber (match_scratch:SI 3 "=r,r"))]
3756 "! TARGET_POWER && TARGET_32BIT"
3757 "@
3758 {sl|slw}%I2. %3,%1,%h2
3759 #"
3760 [(set_attr "type" "delayed_compare")
3761 (set_attr "length" "4,8")])
3762
3763 (define_split
3764 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3765 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3766 (match_operand:SI 2 "reg_or_cint_operand" ""))
3767 (const_int 0)))
3768 (clobber (match_scratch:SI 3 ""))]
3769 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3770 [(set (match_dup 3)
3771 (ashift:SI (match_dup 1) (match_dup 2)))
3772 (set (match_dup 0)
3773 (compare:CC (match_dup 3)
3774 (const_int 0)))]
3775 "")
3776
3777 (define_insn ""
3778 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3779 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3780 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3781 (const_int 0)))
3782 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3783 (ashift:SI (match_dup 1) (match_dup 2)))
3784 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3785 "TARGET_POWER"
3786 "@
3787 sle. %0,%1,%2
3788 {sli.|slwi.} %0,%1,%h2
3789 #
3790 #"
3791 [(set_attr "type" "delayed_compare")
3792 (set_attr "length" "4,4,8,8")])
3793
3794 (define_split
3795 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3796 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3797 (match_operand:SI 2 "reg_or_cint_operand" ""))
3798 (const_int 0)))
3799 (set (match_operand:SI 0 "gpc_reg_operand" "")
3800 (ashift:SI (match_dup 1) (match_dup 2)))
3801 (clobber (match_scratch:SI 4 ""))]
3802 "TARGET_POWER && reload_completed"
3803 [(parallel [(set (match_dup 0)
3804 (ashift:SI (match_dup 1) (match_dup 2)))
3805 (clobber (match_dup 4))])
3806 (set (match_dup 3)
3807 (compare:CC (match_dup 0)
3808 (const_int 0)))]
3809 "")
3810
3811 (define_insn ""
3812 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3813 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3814 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3815 (const_int 0)))
3816 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3817 (ashift:SI (match_dup 1) (match_dup 2)))]
3818 "! TARGET_POWER && TARGET_32BIT"
3819 "@
3820 {sl|slw}%I2. %0,%1,%h2
3821 #"
3822 [(set_attr "type" "delayed_compare")
3823 (set_attr "length" "4,8")])
3824
3825 (define_split
3826 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3827 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3828 (match_operand:SI 2 "reg_or_cint_operand" ""))
3829 (const_int 0)))
3830 (set (match_operand:SI 0 "gpc_reg_operand" "")
3831 (ashift:SI (match_dup 1) (match_dup 2)))]
3832 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3833 [(set (match_dup 0)
3834 (ashift:SI (match_dup 1) (match_dup 2)))
3835 (set (match_dup 3)
3836 (compare:CC (match_dup 0)
3837 (const_int 0)))]
3838 "")
3839
3840 (define_insn "rlwinm"
3841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3842 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3843 (match_operand:SI 2 "const_int_operand" "i"))
3844 (match_operand:SI 3 "mask_operand" "n")))]
3845 "includes_lshift_p (operands[2], operands[3])"
3846 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3847
3848 (define_insn ""
3849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3850 (compare:CC
3851 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3852 (match_operand:SI 2 "const_int_operand" "i,i"))
3853 (match_operand:SI 3 "mask_operand" "n,n"))
3854 (const_int 0)))
3855 (clobber (match_scratch:SI 4 "=r,r"))]
3856 "includes_lshift_p (operands[2], operands[3])"
3857 "@
3858 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3859 #"
3860 [(set_attr "type" "delayed_compare")
3861 (set_attr "length" "4,8")])
3862
3863 (define_split
3864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3865 (compare:CC
3866 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3867 (match_operand:SI 2 "const_int_operand" ""))
3868 (match_operand:SI 3 "mask_operand" ""))
3869 (const_int 0)))
3870 (clobber (match_scratch:SI 4 ""))]
3871 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3872 [(set (match_dup 4)
3873 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3874 (match_dup 3)))
3875 (set (match_dup 0)
3876 (compare:CC (match_dup 4)
3877 (const_int 0)))]
3878 "")
3879
3880 (define_insn ""
3881 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3882 (compare:CC
3883 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3884 (match_operand:SI 2 "const_int_operand" "i,i"))
3885 (match_operand:SI 3 "mask_operand" "n,n"))
3886 (const_int 0)))
3887 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3888 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3889 "includes_lshift_p (operands[2], operands[3])"
3890 "@
3891 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3892 #"
3893 [(set_attr "type" "delayed_compare")
3894 (set_attr "length" "4,8")])
3895
3896 (define_split
3897 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3898 (compare:CC
3899 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3900 (match_operand:SI 2 "const_int_operand" ""))
3901 (match_operand:SI 3 "mask_operand" ""))
3902 (const_int 0)))
3903 (set (match_operand:SI 0 "gpc_reg_operand" "")
3904 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3905 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3906 [(set (match_dup 0)
3907 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3908 (set (match_dup 4)
3909 (compare:CC (match_dup 0)
3910 (const_int 0)))]
3911 "")
3912
3913 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3914 ;; "sli x,x,0".
3915 (define_expand "lshrsi3"
3916 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3917 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3918 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3919 ""
3920 "
3921 {
3922 if (TARGET_POWER)
3923 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3924 else
3925 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3926 DONE;
3927 }")
3928
3929 (define_insn "lshrsi3_power"
3930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3931 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3932 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3933 (clobber (match_scratch:SI 3 "=q,X,X"))]
3934 "TARGET_POWER"
3935 "@
3936 sre %0,%1,%2
3937 mr %0,%1
3938 {s%A2i|s%A2wi} %0,%1,%h2")
3939
3940 (define_insn "lshrsi3_no_power"
3941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3942 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3943 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3944 "! TARGET_POWER"
3945 "@
3946 mr %0,%1
3947 {sr|srw}%I2 %0,%1,%h2")
3948
3949 (define_insn ""
3950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3951 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3952 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3953 (const_int 0)))
3954 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3955 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3956 "TARGET_POWER"
3957 "@
3958 sre. %3,%1,%2
3959 mr. %1,%1
3960 {s%A2i.|s%A2wi.} %3,%1,%h2
3961 #
3962 #
3963 #"
3964 [(set_attr "type" "delayed_compare")
3965 (set_attr "length" "4,4,4,8,8,8")])
3966
3967 (define_split
3968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3969 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3970 (match_operand:SI 2 "reg_or_cint_operand" ""))
3971 (const_int 0)))
3972 (clobber (match_scratch:SI 3 ""))
3973 (clobber (match_scratch:SI 4 ""))]
3974 "TARGET_POWER && reload_completed"
3975 [(parallel [(set (match_dup 3)
3976 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3977 (clobber (match_dup 4))])
3978 (set (match_dup 0)
3979 (compare:CC (match_dup 3)
3980 (const_int 0)))]
3981 "")
3982
3983 (define_insn ""
3984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3985 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3986 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3987 (const_int 0)))
3988 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3989 "! TARGET_POWER && TARGET_32BIT"
3990 "@
3991 mr. %1,%1
3992 {sr|srw}%I2. %3,%1,%h2
3993 #
3994 #"
3995 [(set_attr "type" "delayed_compare")
3996 (set_attr "length" "4,4,8,8")])
3997
3998 (define_split
3999 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4000 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4001 (match_operand:SI 2 "reg_or_cint_operand" ""))
4002 (const_int 0)))
4003 (clobber (match_scratch:SI 3 ""))]
4004 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4005 [(set (match_dup 3)
4006 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4007 (set (match_dup 0)
4008 (compare:CC (match_dup 3)
4009 (const_int 0)))]
4010 "")
4011
4012 (define_insn ""
4013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4014 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4015 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4016 (const_int 0)))
4017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4018 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4019 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4020 "TARGET_POWER"
4021 "@
4022 sre. %0,%1,%2
4023 mr. %0,%1
4024 {s%A2i.|s%A2wi.} %0,%1,%h2
4025 #
4026 #
4027 #"
4028 [(set_attr "type" "delayed_compare")
4029 (set_attr "length" "4,4,4,8,8,8")])
4030
4031 (define_split
4032 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4033 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4034 (match_operand:SI 2 "reg_or_cint_operand" ""))
4035 (const_int 0)))
4036 (set (match_operand:SI 0 "gpc_reg_operand" "")
4037 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4038 (clobber (match_scratch:SI 4 ""))]
4039 "TARGET_POWER && reload_completed"
4040 [(parallel [(set (match_dup 0)
4041 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4042 (clobber (match_dup 4))])
4043 (set (match_dup 3)
4044 (compare:CC (match_dup 0)
4045 (const_int 0)))]
4046 "")
4047
4048 (define_insn ""
4049 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4050 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4051 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4052 (const_int 0)))
4053 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4054 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4055 "! TARGET_POWER && TARGET_32BIT"
4056 "@
4057 mr. %0,%1
4058 {sr|srw}%I2. %0,%1,%h2
4059 #
4060 #"
4061 [(set_attr "type" "delayed_compare")
4062 (set_attr "length" "4,4,8,8")])
4063
4064 (define_split
4065 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4066 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4067 (match_operand:SI 2 "reg_or_cint_operand" ""))
4068 (const_int 0)))
4069 (set (match_operand:SI 0 "gpc_reg_operand" "")
4070 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4071 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4072 [(set (match_dup 0)
4073 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4074 (set (match_dup 3)
4075 (compare:CC (match_dup 0)
4076 (const_int 0)))]
4077 "")
4078
4079 (define_insn ""
4080 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4081 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4082 (match_operand:SI 2 "const_int_operand" "i"))
4083 (match_operand:SI 3 "mask_operand" "n")))]
4084 "includes_rshift_p (operands[2], operands[3])"
4085 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4086
4087 (define_insn ""
4088 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4089 (compare:CC
4090 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4091 (match_operand:SI 2 "const_int_operand" "i,i"))
4092 (match_operand:SI 3 "mask_operand" "n,n"))
4093 (const_int 0)))
4094 (clobber (match_scratch:SI 4 "=r,r"))]
4095 "includes_rshift_p (operands[2], operands[3])"
4096 "@
4097 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4098 #"
4099 [(set_attr "type" "delayed_compare")
4100 (set_attr "length" "4,8")])
4101
4102 (define_split
4103 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4104 (compare:CC
4105 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4106 (match_operand:SI 2 "const_int_operand" ""))
4107 (match_operand:SI 3 "mask_operand" ""))
4108 (const_int 0)))
4109 (clobber (match_scratch:SI 4 ""))]
4110 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4111 [(set (match_dup 4)
4112 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4113 (match_dup 3)))
4114 (set (match_dup 0)
4115 (compare:CC (match_dup 4)
4116 (const_int 0)))]
4117 "")
4118
4119 (define_insn ""
4120 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4121 (compare:CC
4122 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4123 (match_operand:SI 2 "const_int_operand" "i,i"))
4124 (match_operand:SI 3 "mask_operand" "n,n"))
4125 (const_int 0)))
4126 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4127 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4128 "includes_rshift_p (operands[2], operands[3])"
4129 "@
4130 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4131 #"
4132 [(set_attr "type" "delayed_compare")
4133 (set_attr "length" "4,8")])
4134
4135 (define_split
4136 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4137 (compare:CC
4138 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4139 (match_operand:SI 2 "const_int_operand" ""))
4140 (match_operand:SI 3 "mask_operand" ""))
4141 (const_int 0)))
4142 (set (match_operand:SI 0 "gpc_reg_operand" "")
4143 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4144 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4145 [(set (match_dup 0)
4146 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4147 (set (match_dup 4)
4148 (compare:CC (match_dup 0)
4149 (const_int 0)))]
4150 "")
4151
4152 (define_insn ""
4153 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4154 (zero_extend:SI
4155 (subreg:QI
4156 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4157 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4158 "includes_rshift_p (operands[2], GEN_INT (255))"
4159 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4160
4161 (define_insn ""
4162 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4163 (compare:CC
4164 (zero_extend:SI
4165 (subreg:QI
4166 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4167 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4168 (const_int 0)))
4169 (clobber (match_scratch:SI 3 "=r,r"))]
4170 "includes_rshift_p (operands[2], GEN_INT (255))"
4171 "@
4172 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4173 #"
4174 [(set_attr "type" "delayed_compare")
4175 (set_attr "length" "4,8")])
4176
4177 (define_split
4178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4179 (compare:CC
4180 (zero_extend:SI
4181 (subreg:QI
4182 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4183 (match_operand:SI 2 "const_int_operand" "")) 0))
4184 (const_int 0)))
4185 (clobber (match_scratch:SI 3 ""))]
4186 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4187 [(set (match_dup 3)
4188 (zero_extend:SI (subreg:QI
4189 (lshiftrt:SI (match_dup 1)
4190 (match_dup 2)) 0)))
4191 (set (match_dup 0)
4192 (compare:CC (match_dup 3)
4193 (const_int 0)))]
4194 "")
4195
4196 (define_insn ""
4197 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4198 (compare:CC
4199 (zero_extend:SI
4200 (subreg:QI
4201 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4202 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4203 (const_int 0)))
4204 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4205 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4206 "includes_rshift_p (operands[2], GEN_INT (255))"
4207 "@
4208 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4209 #"
4210 [(set_attr "type" "delayed_compare")
4211 (set_attr "length" "4,8")])
4212
4213 (define_split
4214 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4215 (compare:CC
4216 (zero_extend:SI
4217 (subreg:QI
4218 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4219 (match_operand:SI 2 "const_int_operand" "")) 0))
4220 (const_int 0)))
4221 (set (match_operand:SI 0 "gpc_reg_operand" "")
4222 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4223 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4224 [(set (match_dup 0)
4225 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4226 (set (match_dup 3)
4227 (compare:CC (match_dup 0)
4228 (const_int 0)))]
4229 "")
4230
4231 (define_insn ""
4232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4233 (zero_extend:SI
4234 (subreg:HI
4235 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4236 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4237 "includes_rshift_p (operands[2], GEN_INT (65535))"
4238 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4239
4240 (define_insn ""
4241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4242 (compare:CC
4243 (zero_extend:SI
4244 (subreg:HI
4245 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4246 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4247 (const_int 0)))
4248 (clobber (match_scratch:SI 3 "=r,r"))]
4249 "includes_rshift_p (operands[2], GEN_INT (65535))"
4250 "@
4251 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4252 #"
4253 [(set_attr "type" "delayed_compare")
4254 (set_attr "length" "4,8")])
4255
4256 (define_split
4257 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4258 (compare:CC
4259 (zero_extend:SI
4260 (subreg:HI
4261 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4262 (match_operand:SI 2 "const_int_operand" "")) 0))
4263 (const_int 0)))
4264 (clobber (match_scratch:SI 3 ""))]
4265 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4266 [(set (match_dup 3)
4267 (zero_extend:SI (subreg:HI
4268 (lshiftrt:SI (match_dup 1)
4269 (match_dup 2)) 0)))
4270 (set (match_dup 0)
4271 (compare:CC (match_dup 3)
4272 (const_int 0)))]
4273 "")
4274
4275 (define_insn ""
4276 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4277 (compare:CC
4278 (zero_extend:SI
4279 (subreg:HI
4280 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4281 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4282 (const_int 0)))
4283 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4284 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4285 "includes_rshift_p (operands[2], GEN_INT (65535))"
4286 "@
4287 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4288 #"
4289 [(set_attr "type" "delayed_compare")
4290 (set_attr "length" "4,8")])
4291
4292 (define_split
4293 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4294 (compare:CC
4295 (zero_extend:SI
4296 (subreg:HI
4297 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4298 (match_operand:SI 2 "const_int_operand" "")) 0))
4299 (const_int 0)))
4300 (set (match_operand:SI 0 "gpc_reg_operand" "")
4301 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4302 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4303 [(set (match_dup 0)
4304 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4305 (set (match_dup 3)
4306 (compare:CC (match_dup 0)
4307 (const_int 0)))]
4308 "")
4309
4310 (define_insn ""
4311 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4312 (const_int 1)
4313 (match_operand:SI 1 "gpc_reg_operand" "r"))
4314 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4315 (const_int 31)))]
4316 "TARGET_POWER"
4317 "rrib %0,%1,%2")
4318
4319 (define_insn ""
4320 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4321 (const_int 1)
4322 (match_operand:SI 1 "gpc_reg_operand" "r"))
4323 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4324 (const_int 31)))]
4325 "TARGET_POWER"
4326 "rrib %0,%1,%2")
4327
4328 (define_insn ""
4329 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4330 (const_int 1)
4331 (match_operand:SI 1 "gpc_reg_operand" "r"))
4332 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4333 (const_int 1)
4334 (const_int 0)))]
4335 "TARGET_POWER"
4336 "rrib %0,%1,%2")
4337
4338 (define_expand "ashrsi3"
4339 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4340 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4341 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4342 ""
4343 "
4344 {
4345 if (TARGET_POWER)
4346 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4347 else
4348 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4349 DONE;
4350 }")
4351
4352 (define_insn "ashrsi3_power"
4353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4354 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4355 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4356 (clobber (match_scratch:SI 3 "=q,X"))]
4357 "TARGET_POWER"
4358 "@
4359 srea %0,%1,%2
4360 {srai|srawi} %0,%1,%h2")
4361
4362 (define_insn "ashrsi3_no_power"
4363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4364 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4365 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4366 "! TARGET_POWER"
4367 "{sra|sraw}%I2 %0,%1,%h2")
4368
4369 (define_insn ""
4370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4371 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4372 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4373 (const_int 0)))
4374 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4375 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4376 "TARGET_POWER"
4377 "@
4378 srea. %3,%1,%2
4379 {srai.|srawi.} %3,%1,%h2
4380 #
4381 #"
4382 [(set_attr "type" "delayed_compare")
4383 (set_attr "length" "4,4,8,8")])
4384
4385 (define_split
4386 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4387 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4388 (match_operand:SI 2 "reg_or_cint_operand" ""))
4389 (const_int 0)))
4390 (clobber (match_scratch:SI 3 ""))
4391 (clobber (match_scratch:SI 4 ""))]
4392 "TARGET_POWER && reload_completed"
4393 [(parallel [(set (match_dup 3)
4394 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4395 (clobber (match_dup 4))])
4396 (set (match_dup 0)
4397 (compare:CC (match_dup 3)
4398 (const_int 0)))]
4399 "")
4400
4401 (define_insn ""
4402 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4403 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4404 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4405 (const_int 0)))
4406 (clobber (match_scratch:SI 3 "=r,r"))]
4407 "! TARGET_POWER"
4408 "@
4409 {sra|sraw}%I2. %3,%1,%h2
4410 #"
4411 [(set_attr "type" "delayed_compare")
4412 (set_attr "length" "4,8")])
4413
4414 (define_split
4415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4416 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4417 (match_operand:SI 2 "reg_or_cint_operand" ""))
4418 (const_int 0)))
4419 (clobber (match_scratch:SI 3 ""))]
4420 "! TARGET_POWER && reload_completed"
4421 [(set (match_dup 3)
4422 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4423 (set (match_dup 0)
4424 (compare:CC (match_dup 3)
4425 (const_int 0)))]
4426 "")
4427
4428 (define_insn ""
4429 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4430 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4431 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4432 (const_int 0)))
4433 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4434 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4435 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4436 "TARGET_POWER"
4437 "@
4438 srea. %0,%1,%2
4439 {srai.|srawi.} %0,%1,%h2
4440 #
4441 #"
4442 [(set_attr "type" "delayed_compare")
4443 (set_attr "length" "4,4,8,8")])
4444
4445 (define_split
4446 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4447 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4448 (match_operand:SI 2 "reg_or_cint_operand" ""))
4449 (const_int 0)))
4450 (set (match_operand:SI 0 "gpc_reg_operand" "")
4451 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4452 (clobber (match_scratch:SI 4 ""))]
4453 "TARGET_POWER && reload_completed"
4454 [(parallel [(set (match_dup 0)
4455 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4456 (clobber (match_dup 4))])
4457 (set (match_dup 3)
4458 (compare:CC (match_dup 0)
4459 (const_int 0)))]
4460 "")
4461
4462 (define_insn ""
4463 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4464 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4465 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4466 (const_int 0)))
4467 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4468 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4469 "! TARGET_POWER"
4470 "@
4471 {sra|sraw}%I2. %0,%1,%h2
4472 #"
4473 [(set_attr "type" "delayed_compare")
4474 (set_attr "length" "4,8")])
4475 \f
4476 (define_split
4477 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4478 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4479 (match_operand:SI 2 "reg_or_cint_operand" ""))
4480 (const_int 0)))
4481 (set (match_operand:SI 0 "gpc_reg_operand" "")
4482 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4483 "! TARGET_POWER && reload_completed"
4484 [(set (match_dup 0)
4485 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4486 (set (match_dup 3)
4487 (compare:CC (match_dup 0)
4488 (const_int 0)))]
4489 "")
4490
4491 ;; Floating-point insns, excluding normal data motion.
4492 ;;
4493 ;; PowerPC has a full set of single-precision floating point instructions.
4494 ;;
4495 ;; For the POWER architecture, we pretend that we have both SFmode and
4496 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4497 ;; The only conversions we will do will be when storing to memory. In that
4498 ;; case, we will use the "frsp" instruction before storing.
4499 ;;
4500 ;; Note that when we store into a single-precision memory location, we need to
4501 ;; use the frsp insn first. If the register being stored isn't dead, we
4502 ;; need a scratch register for the frsp. But this is difficult when the store
4503 ;; is done by reload. It is not incorrect to do the frsp on the register in
4504 ;; this case, we just lose precision that we would have otherwise gotten but
4505 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4506
4507 (define_expand "extendsfdf2"
4508 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4509 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4510 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4511 "")
4512
4513 (define_insn_and_split "*extendsfdf2_fpr"
4514 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4515 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4516 "TARGET_HARD_FLOAT && TARGET_FPRS"
4517 "@
4518 #
4519 fmr %0,%1
4520 lfs%U1%X1 %0,%1"
4521 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4522 [(const_int 0)]
4523 {
4524 emit_note (NOTE_INSN_DELETED);
4525 DONE;
4526 }
4527 [(set_attr "type" "fp,fp,fpload")])
4528
4529 (define_expand "truncdfsf2"
4530 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4531 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4532 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4533 "")
4534
4535 (define_insn "*truncdfsf2_fpr"
4536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4537 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4538 "TARGET_HARD_FLOAT && TARGET_FPRS"
4539 "frsp %0,%1"
4540 [(set_attr "type" "fp")])
4541
4542 (define_insn "aux_truncdfsf2"
4543 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4544 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4545 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4546 "frsp %0,%1"
4547 [(set_attr "type" "fp")])
4548
4549 (define_expand "negsf2"
4550 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4551 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4552 "TARGET_HARD_FLOAT"
4553 "")
4554
4555 (define_insn "*negsf2"
4556 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4557 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4558 "TARGET_HARD_FLOAT && TARGET_FPRS"
4559 "fneg %0,%1"
4560 [(set_attr "type" "fp")])
4561
4562 (define_expand "abssf2"
4563 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4564 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4565 "TARGET_HARD_FLOAT"
4566 "")
4567
4568 (define_insn "*abssf2"
4569 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4570 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4571 "TARGET_HARD_FLOAT && TARGET_FPRS"
4572 "fabs %0,%1"
4573 [(set_attr "type" "fp")])
4574
4575 (define_insn ""
4576 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4577 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4578 "TARGET_HARD_FLOAT && TARGET_FPRS"
4579 "fnabs %0,%1"
4580 [(set_attr "type" "fp")])
4581
4582 (define_expand "addsf3"
4583 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4584 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4585 (match_operand:SF 2 "gpc_reg_operand" "")))]
4586 "TARGET_HARD_FLOAT"
4587 "")
4588
4589 (define_insn ""
4590 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4591 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4592 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4593 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4594 "fadds %0,%1,%2"
4595 [(set_attr "type" "fp")])
4596
4597 (define_insn ""
4598 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4599 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4600 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4601 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4602 "{fa|fadd} %0,%1,%2"
4603 [(set_attr "type" "fp")])
4604
4605 (define_expand "subsf3"
4606 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4607 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4608 (match_operand:SF 2 "gpc_reg_operand" "")))]
4609 "TARGET_HARD_FLOAT"
4610 "")
4611
4612 (define_insn ""
4613 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4614 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4615 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4616 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4617 "fsubs %0,%1,%2"
4618 [(set_attr "type" "fp")])
4619
4620 (define_insn ""
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4622 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4623 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4624 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4625 "{fs|fsub} %0,%1,%2"
4626 [(set_attr "type" "fp")])
4627
4628 (define_expand "mulsf3"
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4630 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4631 (match_operand:SF 2 "gpc_reg_operand" "")))]
4632 "TARGET_HARD_FLOAT"
4633 "")
4634
4635 (define_insn ""
4636 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4637 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4638 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4639 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4640 "fmuls %0,%1,%2"
4641 [(set_attr "type" "fp")])
4642
4643 (define_insn ""
4644 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4645 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4646 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4647 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4648 "{fm|fmul} %0,%1,%2"
4649 [(set_attr "type" "dmul")])
4650
4651 (define_insn "fres"
4652 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4653 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4654 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4655 "fres %0,%1"
4656 [(set_attr "type" "fp")])
4657
4658 (define_expand "divsf3"
4659 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4660 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4661 (match_operand:SF 2 "gpc_reg_operand" "")))]
4662 "TARGET_HARD_FLOAT"
4663 {
4664 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4665 && flag_finite_math_only && !flag_trapping_math)
4666 {
4667 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4668 DONE;
4669 }
4670 })
4671
4672 (define_insn ""
4673 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4674 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4675 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4676 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4677 "fdivs %0,%1,%2"
4678 [(set_attr "type" "sdiv")])
4679
4680 (define_insn ""
4681 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4682 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4683 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4684 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4685 "{fd|fdiv} %0,%1,%2"
4686 [(set_attr "type" "ddiv")])
4687
4688 (define_insn ""
4689 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4690 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4691 (match_operand:SF 2 "gpc_reg_operand" "f"))
4692 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4693 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4694 "fmadds %0,%1,%2,%3"
4695 [(set_attr "type" "fp")])
4696
4697 (define_insn ""
4698 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4699 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4700 (match_operand:SF 2 "gpc_reg_operand" "f"))
4701 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4702 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4703 "{fma|fmadd} %0,%1,%2,%3"
4704 [(set_attr "type" "dmul")])
4705
4706 (define_insn ""
4707 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4708 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4709 (match_operand:SF 2 "gpc_reg_operand" "f"))
4710 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4711 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4712 "fmsubs %0,%1,%2,%3"
4713 [(set_attr "type" "fp")])
4714
4715 (define_insn ""
4716 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4717 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4718 (match_operand:SF 2 "gpc_reg_operand" "f"))
4719 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4720 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4721 "{fms|fmsub} %0,%1,%2,%3"
4722 [(set_attr "type" "dmul")])
4723
4724 (define_insn ""
4725 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4726 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4727 (match_operand:SF 2 "gpc_reg_operand" "f"))
4728 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4729 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4730 && HONOR_SIGNED_ZEROS (SFmode)"
4731 "fnmadds %0,%1,%2,%3"
4732 [(set_attr "type" "fp")])
4733
4734 (define_insn ""
4735 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4736 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4737 (match_operand:SF 2 "gpc_reg_operand" "f"))
4738 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4739 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4740 && ! HONOR_SIGNED_ZEROS (SFmode)"
4741 "fnmadds %0,%1,%2,%3"
4742 [(set_attr "type" "fp")])
4743
4744 (define_insn ""
4745 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4746 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4747 (match_operand:SF 2 "gpc_reg_operand" "f"))
4748 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4749 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4750 "{fnma|fnmadd} %0,%1,%2,%3"
4751 [(set_attr "type" "dmul")])
4752
4753 (define_insn ""
4754 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4755 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4756 (match_operand:SF 2 "gpc_reg_operand" "f"))
4757 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4758 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4759 && ! HONOR_SIGNED_ZEROS (SFmode)"
4760 "{fnma|fnmadd} %0,%1,%2,%3"
4761 [(set_attr "type" "dmul")])
4762
4763 (define_insn ""
4764 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4765 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4766 (match_operand:SF 2 "gpc_reg_operand" "f"))
4767 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4768 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4769 && HONOR_SIGNED_ZEROS (SFmode)"
4770 "fnmsubs %0,%1,%2,%3"
4771 [(set_attr "type" "fp")])
4772
4773 (define_insn ""
4774 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4775 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4776 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4777 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4778 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4779 && ! HONOR_SIGNED_ZEROS (SFmode)"
4780 "fnmsubs %0,%1,%2,%3"
4781 [(set_attr "type" "fp")])
4782
4783 (define_insn ""
4784 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4785 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4786 (match_operand:SF 2 "gpc_reg_operand" "f"))
4787 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4788 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4789 "{fnms|fnmsub} %0,%1,%2,%3"
4790 [(set_attr "type" "dmul")])
4791
4792 (define_insn ""
4793 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4794 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4795 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4796 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4797 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4798 && ! HONOR_SIGNED_ZEROS (SFmode)"
4799 "{fnms|fnmsub} %0,%1,%2,%3"
4800 [(set_attr "type" "fp")])
4801
4802 (define_expand "sqrtsf2"
4803 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4804 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4805 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4806 "")
4807
4808 (define_insn ""
4809 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4810 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4811 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4812 "fsqrts %0,%1"
4813 [(set_attr "type" "ssqrt")])
4814
4815 (define_insn ""
4816 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4817 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4818 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4819 "fsqrt %0,%1"
4820 [(set_attr "type" "dsqrt")])
4821
4822 (define_expand "copysignsf3"
4823 [(set (match_dup 3)
4824 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4825 (set (match_dup 4)
4826 (neg:SF (abs:SF (match_dup 1))))
4827 (set (match_operand:SF 0 "gpc_reg_operand" "")
4828 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4829 (match_dup 5))
4830 (match_dup 3)
4831 (match_dup 4)))]
4832 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4833 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4834 {
4835 operands[3] = gen_reg_rtx (SFmode);
4836 operands[4] = gen_reg_rtx (SFmode);
4837 operands[5] = CONST0_RTX (SFmode);
4838 })
4839
4840 (define_expand "copysigndf3"
4841 [(set (match_dup 3)
4842 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4843 (set (match_dup 4)
4844 (neg:DF (abs:DF (match_dup 1))))
4845 (set (match_operand:DF 0 "gpc_reg_operand" "")
4846 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4847 (match_dup 5))
4848 (match_dup 3)
4849 (match_dup 4)))]
4850 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4851 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4852 {
4853 operands[3] = gen_reg_rtx (DFmode);
4854 operands[4] = gen_reg_rtx (DFmode);
4855 operands[5] = CONST0_RTX (DFmode);
4856 })
4857
4858 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4859 ;; fsel instruction and some auxiliary computations. Then we just have a
4860 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4861 ;; combine.
4862 (define_expand "smaxsf3"
4863 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4864 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4865 (match_operand:SF 2 "gpc_reg_operand" ""))
4866 (match_dup 1)
4867 (match_dup 2)))]
4868 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4869 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4870
4871 (define_expand "sminsf3"
4872 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4873 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4874 (match_operand:SF 2 "gpc_reg_operand" ""))
4875 (match_dup 2)
4876 (match_dup 1)))]
4877 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4878 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4879
4880 (define_split
4881 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4882 (match_operator:SF 3 "min_max_operator"
4883 [(match_operand:SF 1 "gpc_reg_operand" "")
4884 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4885 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4886 [(const_int 0)]
4887 "
4888 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4889 operands[1], operands[2]);
4890 DONE;
4891 }")
4892
4893 (define_expand "movsicc"
4894 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4895 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4896 (match_operand:SI 2 "gpc_reg_operand" "")
4897 (match_operand:SI 3 "gpc_reg_operand" "")))]
4898 "TARGET_ISEL"
4899 "
4900 {
4901 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4902 DONE;
4903 else
4904 FAIL;
4905 }")
4906
4907 ;; We use the BASE_REGS for the isel input operands because, if rA is
4908 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4909 ;; because we may switch the operands and rB may end up being rA.
4910 ;;
4911 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4912 ;; leave out the mode in operand 4 and use one pattern, but reload can
4913 ;; change the mode underneath our feet and then gets confused trying
4914 ;; to reload the value.
4915 (define_insn "isel_signed"
4916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4917 (if_then_else:SI
4918 (match_operator 1 "comparison_operator"
4919 [(match_operand:CC 4 "cc_reg_operand" "y")
4920 (const_int 0)])
4921 (match_operand:SI 2 "gpc_reg_operand" "b")
4922 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4923 "TARGET_ISEL"
4924 "*
4925 { return output_isel (operands); }"
4926 [(set_attr "length" "4")])
4927
4928 (define_insn "isel_unsigned"
4929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4930 (if_then_else:SI
4931 (match_operator 1 "comparison_operator"
4932 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4933 (const_int 0)])
4934 (match_operand:SI 2 "gpc_reg_operand" "b")
4935 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4936 "TARGET_ISEL"
4937 "*
4938 { return output_isel (operands); }"
4939 [(set_attr "length" "4")])
4940
4941 (define_expand "movsfcc"
4942 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4943 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4944 (match_operand:SF 2 "gpc_reg_operand" "")
4945 (match_operand:SF 3 "gpc_reg_operand" "")))]
4946 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4947 "
4948 {
4949 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4950 DONE;
4951 else
4952 FAIL;
4953 }")
4954
4955 (define_insn "*fselsfsf4"
4956 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4957 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4958 (match_operand:SF 4 "zero_fp_constant" "F"))
4959 (match_operand:SF 2 "gpc_reg_operand" "f")
4960 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4961 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4962 "fsel %0,%1,%2,%3"
4963 [(set_attr "type" "fp")])
4964
4965 (define_insn "*fseldfsf4"
4966 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4967 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4968 (match_operand:DF 4 "zero_fp_constant" "F"))
4969 (match_operand:SF 2 "gpc_reg_operand" "f")
4970 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4971 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4972 "fsel %0,%1,%2,%3"
4973 [(set_attr "type" "fp")])
4974
4975 (define_expand "negdf2"
4976 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4977 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4978 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4979 "")
4980
4981 (define_insn "*negdf2_fpr"
4982 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4983 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4984 "TARGET_HARD_FLOAT && TARGET_FPRS"
4985 "fneg %0,%1"
4986 [(set_attr "type" "fp")])
4987
4988 (define_expand "absdf2"
4989 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4990 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4991 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4992 "")
4993
4994 (define_insn "*absdf2_fpr"
4995 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4996 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4997 "TARGET_HARD_FLOAT && TARGET_FPRS"
4998 "fabs %0,%1"
4999 [(set_attr "type" "fp")])
5000
5001 (define_insn "*nabsdf2_fpr"
5002 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5003 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5004 "TARGET_HARD_FLOAT && TARGET_FPRS"
5005 "fnabs %0,%1"
5006 [(set_attr "type" "fp")])
5007
5008 (define_expand "adddf3"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5010 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5011 (match_operand:DF 2 "gpc_reg_operand" "")))]
5012 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5013 "")
5014
5015 (define_insn "*adddf3_fpr"
5016 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5017 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5018 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5019 "TARGET_HARD_FLOAT && TARGET_FPRS"
5020 "{fa|fadd} %0,%1,%2"
5021 [(set_attr "type" "fp")])
5022
5023 (define_expand "subdf3"
5024 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5025 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5026 (match_operand:DF 2 "gpc_reg_operand" "")))]
5027 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5028 "")
5029
5030 (define_insn "*subdf3_fpr"
5031 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5032 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5033 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5034 "TARGET_HARD_FLOAT && TARGET_FPRS"
5035 "{fs|fsub} %0,%1,%2"
5036 [(set_attr "type" "fp")])
5037
5038 (define_expand "muldf3"
5039 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5040 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5041 (match_operand:DF 2 "gpc_reg_operand" "")))]
5042 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5043 "")
5044
5045 (define_insn "*muldf3_fpr"
5046 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5047 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5048 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5049 "TARGET_HARD_FLOAT && TARGET_FPRS"
5050 "{fm|fmul} %0,%1,%2"
5051 [(set_attr "type" "dmul")])
5052
5053 (define_insn "fred"
5054 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5055 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5056 "TARGET_POPCNTB && flag_finite_math_only"
5057 "fre %0,%1"
5058 [(set_attr "type" "fp")])
5059
5060 (define_expand "divdf3"
5061 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5062 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5063 (match_operand:DF 2 "gpc_reg_operand" "")))]
5064 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5065 {
5066 if (swdiv && !optimize_size && TARGET_POPCNTB
5067 && flag_finite_math_only && !flag_trapping_math)
5068 {
5069 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5070 DONE;
5071 }
5072 })
5073
5074 (define_insn "*divdf3_fpr"
5075 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5076 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5077 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5078 "TARGET_HARD_FLOAT && TARGET_FPRS"
5079 "{fd|fdiv} %0,%1,%2"
5080 [(set_attr "type" "ddiv")])
5081
5082 (define_insn ""
5083 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5084 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5085 (match_operand:DF 2 "gpc_reg_operand" "f"))
5086 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5087 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5088 "{fma|fmadd} %0,%1,%2,%3"
5089 [(set_attr "type" "dmul")])
5090
5091 (define_insn ""
5092 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5093 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5094 (match_operand:DF 2 "gpc_reg_operand" "f"))
5095 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5096 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5097 "{fms|fmsub} %0,%1,%2,%3"
5098 [(set_attr "type" "dmul")])
5099
5100 (define_insn ""
5101 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5102 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5103 (match_operand:DF 2 "gpc_reg_operand" "f"))
5104 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5105 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5106 && HONOR_SIGNED_ZEROS (DFmode)"
5107 "{fnma|fnmadd} %0,%1,%2,%3"
5108 [(set_attr "type" "dmul")])
5109
5110 (define_insn ""
5111 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5112 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5113 (match_operand:DF 2 "gpc_reg_operand" "f"))
5114 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5115 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5116 && ! HONOR_SIGNED_ZEROS (DFmode)"
5117 "{fnma|fnmadd} %0,%1,%2,%3"
5118 [(set_attr "type" "dmul")])
5119
5120 (define_insn ""
5121 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5122 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5123 (match_operand:DF 2 "gpc_reg_operand" "f"))
5124 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5125 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5126 && HONOR_SIGNED_ZEROS (DFmode)"
5127 "{fnms|fnmsub} %0,%1,%2,%3"
5128 [(set_attr "type" "dmul")])
5129
5130 (define_insn ""
5131 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5132 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5133 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5134 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5135 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5136 && ! HONOR_SIGNED_ZEROS (DFmode)"
5137 "{fnms|fnmsub} %0,%1,%2,%3"
5138 [(set_attr "type" "dmul")])
5139
5140 (define_insn "sqrtdf2"
5141 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5142 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5143 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5144 "fsqrt %0,%1"
5145 [(set_attr "type" "dsqrt")])
5146
5147 ;; The conditional move instructions allow us to perform max and min
5148 ;; operations even when
5149
5150 (define_expand "smaxdf3"
5151 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5152 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5153 (match_operand:DF 2 "gpc_reg_operand" ""))
5154 (match_dup 1)
5155 (match_dup 2)))]
5156 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5157 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5158
5159 (define_expand "smindf3"
5160 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5161 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5162 (match_operand:DF 2 "gpc_reg_operand" ""))
5163 (match_dup 2)
5164 (match_dup 1)))]
5165 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5166 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5167
5168 (define_split
5169 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5170 (match_operator:DF 3 "min_max_operator"
5171 [(match_operand:DF 1 "gpc_reg_operand" "")
5172 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5173 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5174 [(const_int 0)]
5175 "
5176 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5177 operands[1], operands[2]);
5178 DONE;
5179 }")
5180
5181 (define_expand "movdfcc"
5182 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5183 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5184 (match_operand:DF 2 "gpc_reg_operand" "")
5185 (match_operand:DF 3 "gpc_reg_operand" "")))]
5186 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5187 "
5188 {
5189 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5190 DONE;
5191 else
5192 FAIL;
5193 }")
5194
5195 (define_insn "*fseldfdf4"
5196 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5197 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5198 (match_operand:DF 4 "zero_fp_constant" "F"))
5199 (match_operand:DF 2 "gpc_reg_operand" "f")
5200 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5201 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5202 "fsel %0,%1,%2,%3"
5203 [(set_attr "type" "fp")])
5204
5205 (define_insn "*fselsfdf4"
5206 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5207 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5208 (match_operand:SF 4 "zero_fp_constant" "F"))
5209 (match_operand:DF 2 "gpc_reg_operand" "f")
5210 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5211 "TARGET_PPC_GFXOPT"
5212 "fsel %0,%1,%2,%3"
5213 [(set_attr "type" "fp")])
5214 \f
5215 ;; Conversions to and from floating-point.
5216
5217 (define_expand "fixuns_truncsfsi2"
5218 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5219 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5220 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5221 "")
5222
5223 (define_expand "fix_truncsfsi2"
5224 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5225 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5226 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5227 "")
5228
5229 ; For each of these conversions, there is a define_expand, a define_insn
5230 ; with a '#' template, and a define_split (with C code). The idea is
5231 ; to allow constant folding with the template of the define_insn,
5232 ; then to have the insns split later (between sched1 and final).
5233
5234 (define_expand "floatsidf2"
5235 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5236 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5237 (use (match_dup 2))
5238 (use (match_dup 3))
5239 (clobber (match_dup 4))
5240 (clobber (match_dup 5))
5241 (clobber (match_dup 6))])]
5242 "TARGET_HARD_FLOAT && TARGET_FPRS"
5243 "
5244 {
5245 if (TARGET_E500_DOUBLE)
5246 {
5247 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5248 DONE;
5249 }
5250 if (TARGET_POWERPC64)
5251 {
5252 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5253 rtx t1 = gen_reg_rtx (DImode);
5254 rtx t2 = gen_reg_rtx (DImode);
5255 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5256 DONE;
5257 }
5258
5259 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5260 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5261 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5262 operands[5] = gen_reg_rtx (DFmode);
5263 operands[6] = gen_reg_rtx (SImode);
5264 }")
5265
5266 (define_insn_and_split "*floatsidf2_internal"
5267 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5268 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5269 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5270 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5271 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5272 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5273 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5274 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5275 "#"
5276 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5277 [(pc)]
5278 "
5279 {
5280 rtx lowword, highword;
5281 gcc_assert (MEM_P (operands[4]));
5282 highword = adjust_address (operands[4], SImode, 0);
5283 lowword = adjust_address (operands[4], SImode, 4);
5284 if (! WORDS_BIG_ENDIAN)
5285 {
5286 rtx tmp;
5287 tmp = highword; highword = lowword; lowword = tmp;
5288 }
5289
5290 emit_insn (gen_xorsi3 (operands[6], operands[1],
5291 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5292 emit_move_insn (lowword, operands[6]);
5293 emit_move_insn (highword, operands[2]);
5294 emit_move_insn (operands[5], operands[4]);
5295 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5296 DONE;
5297 }"
5298 [(set_attr "length" "24")])
5299
5300 (define_expand "floatunssisf2"
5301 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5302 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5303 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5304 "")
5305
5306 (define_expand "floatunssidf2"
5307 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5308 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5309 (use (match_dup 2))
5310 (use (match_dup 3))
5311 (clobber (match_dup 4))
5312 (clobber (match_dup 5))])]
5313 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5314 "
5315 {
5316 if (TARGET_E500_DOUBLE)
5317 {
5318 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5319 DONE;
5320 }
5321 if (TARGET_POWERPC64)
5322 {
5323 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5324 rtx t1 = gen_reg_rtx (DImode);
5325 rtx t2 = gen_reg_rtx (DImode);
5326 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5327 t1, t2));
5328 DONE;
5329 }
5330
5331 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5332 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5333 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5334 operands[5] = gen_reg_rtx (DFmode);
5335 }")
5336
5337 (define_insn_and_split "*floatunssidf2_internal"
5338 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5339 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5340 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5341 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5342 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5343 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5344 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5345 "#"
5346 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5347 [(pc)]
5348 "
5349 {
5350 rtx lowword, highword;
5351 gcc_assert (MEM_P (operands[4]));
5352 highword = adjust_address (operands[4], SImode, 0);
5353 lowword = adjust_address (operands[4], SImode, 4);
5354 if (! WORDS_BIG_ENDIAN)
5355 {
5356 rtx tmp;
5357 tmp = highword; highword = lowword; lowword = tmp;
5358 }
5359
5360 emit_move_insn (lowword, operands[1]);
5361 emit_move_insn (highword, operands[2]);
5362 emit_move_insn (operands[5], operands[4]);
5363 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5364 DONE;
5365 }"
5366 [(set_attr "length" "20")])
5367
5368 (define_expand "fix_truncdfsi2"
5369 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5370 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5371 (clobber (match_dup 2))
5372 (clobber (match_dup 3))])]
5373 "(TARGET_POWER2 || TARGET_POWERPC)
5374 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5375 "
5376 {
5377 if (TARGET_E500_DOUBLE)
5378 {
5379 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5380 DONE;
5381 }
5382 operands[2] = gen_reg_rtx (DImode);
5383 if (TARGET_PPC_GFXOPT)
5384 {
5385 rtx orig_dest = operands[0];
5386 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5387 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5388 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5389 operands[2]));
5390 if (operands[0] != orig_dest)
5391 emit_move_insn (orig_dest, operands[0]);
5392 DONE;
5393 }
5394 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5395 }")
5396
5397 (define_insn_and_split "*fix_truncdfsi2_internal"
5398 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5399 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5400 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5401 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5402 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5403 "#"
5404 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5405 [(pc)]
5406 "
5407 {
5408 rtx lowword;
5409 gcc_assert (MEM_P (operands[3]));
5410 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5411
5412 emit_insn (gen_fctiwz (operands[2], operands[1]));
5413 emit_move_insn (operands[3], operands[2]);
5414 emit_move_insn (operands[0], lowword);
5415 DONE;
5416 }"
5417 [(set_attr "length" "16")])
5418
5419 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5420 [(set (match_operand:SI 0 "memory_operand" "=Z")
5421 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5422 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5423 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5424 && TARGET_PPC_GFXOPT"
5425 "#"
5426 "&& 1"
5427 [(pc)]
5428 "
5429 {
5430 emit_insn (gen_fctiwz (operands[2], operands[1]));
5431 emit_insn (gen_stfiwx (operands[0], operands[2]));
5432 DONE;
5433 }"
5434 [(set_attr "length" "16")])
5435
5436 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5437 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5438 ; because the first makes it clear that operand 0 is not live
5439 ; before the instruction.
5440 (define_insn "fctiwz"
5441 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5442 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5443 UNSPEC_FCTIWZ))]
5444 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5445 "{fcirz|fctiwz} %0,%1"
5446 [(set_attr "type" "fp")])
5447
5448 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5449 (define_insn "stfiwx"
5450 [(set (match_operand:SI 0 "memory_operand" "=Z")
5451 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5452 UNSPEC_STFIWX))]
5453 "TARGET_PPC_GFXOPT"
5454 "stfiwx %1,%y0"
5455 [(set_attr "type" "fpstore")])
5456
5457 (define_expand "floatsisf2"
5458 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5459 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5460 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5461 "")
5462
5463 (define_insn "floatdidf2"
5464 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5465 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5466 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5467 "fcfid %0,%1"
5468 [(set_attr "type" "fp")])
5469
5470 (define_insn_and_split "floatsidf_ppc64"
5471 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5472 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5473 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5474 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5475 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5476 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5477 "#"
5478 "&& 1"
5479 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5480 (set (match_dup 2) (match_dup 3))
5481 (set (match_dup 4) (match_dup 2))
5482 (set (match_dup 0) (float:DF (match_dup 4)))]
5483 "")
5484
5485 (define_insn_and_split "floatunssidf_ppc64"
5486 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5487 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5488 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5489 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5490 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5491 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5492 "#"
5493 "&& 1"
5494 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5495 (set (match_dup 2) (match_dup 3))
5496 (set (match_dup 4) (match_dup 2))
5497 (set (match_dup 0) (float:DF (match_dup 4)))]
5498 "")
5499
5500 (define_insn "fix_truncdfdi2"
5501 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5502 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5503 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5504 "fctidz %0,%1"
5505 [(set_attr "type" "fp")])
5506
5507 (define_expand "floatdisf2"
5508 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5509 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5510 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5511 "
5512 {
5513 rtx val = operands[1];
5514 if (!flag_unsafe_math_optimizations)
5515 {
5516 rtx label = gen_label_rtx ();
5517 val = gen_reg_rtx (DImode);
5518 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5519 emit_label (label);
5520 }
5521 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5522 DONE;
5523 }")
5524
5525 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5526 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5527 ;; from double rounding.
5528 (define_insn_and_split "floatdisf2_internal1"
5529 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5530 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5531 (clobber (match_scratch:DF 2 "=f"))]
5532 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5533 "#"
5534 "&& reload_completed"
5535 [(set (match_dup 2)
5536 (float:DF (match_dup 1)))
5537 (set (match_dup 0)
5538 (float_truncate:SF (match_dup 2)))]
5539 "")
5540
5541 ;; Twiddles bits to avoid double rounding.
5542 ;; Bits that might be truncated when converting to DFmode are replaced
5543 ;; by a bit that won't be lost at that stage, but is below the SFmode
5544 ;; rounding position.
5545 (define_expand "floatdisf2_internal2"
5546 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5547 (const_int 53)))
5548 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5549 (const_int 2047)))
5550 (clobber (scratch:CC))])
5551 (set (match_dup 3) (plus:DI (match_dup 3)
5552 (const_int 1)))
5553 (set (match_dup 0) (plus:DI (match_dup 0)
5554 (const_int 2047)))
5555 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5556 (const_int 3)))
5557 (set (match_dup 0) (ior:DI (match_dup 0)
5558 (match_dup 1)))
5559 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5560 (const_int -2048)))
5561 (clobber (scratch:CC))])
5562 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5563 (label_ref (match_operand:DI 2 "" ""))
5564 (pc)))
5565 (set (match_dup 0) (match_dup 1))]
5566 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5567 "
5568 {
5569 operands[3] = gen_reg_rtx (DImode);
5570 operands[4] = gen_reg_rtx (CCUNSmode);
5571 }")
5572 \f
5573 ;; Define the DImode operations that can be done in a small number
5574 ;; of instructions. The & constraints are to prevent the register
5575 ;; allocator from allocating registers that overlap with the inputs
5576 ;; (for example, having an input in 7,8 and an output in 6,7). We
5577 ;; also allow for the output being the same as one of the inputs.
5578
5579 (define_insn "*adddi3_noppc64"
5580 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5581 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5582 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5583 "! TARGET_POWERPC64"
5584 "*
5585 {
5586 if (WORDS_BIG_ENDIAN)
5587 return (GET_CODE (operands[2])) != CONST_INT
5588 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5589 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5590 else
5591 return (GET_CODE (operands[2])) != CONST_INT
5592 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5593 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5594 }"
5595 [(set_attr "type" "two")
5596 (set_attr "length" "8")])
5597
5598 (define_insn "*subdi3_noppc64"
5599 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5600 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5601 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5602 "! TARGET_POWERPC64"
5603 "*
5604 {
5605 if (WORDS_BIG_ENDIAN)
5606 return (GET_CODE (operands[1]) != CONST_INT)
5607 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5608 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5609 else
5610 return (GET_CODE (operands[1]) != CONST_INT)
5611 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5612 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5613 }"
5614 [(set_attr "type" "two")
5615 (set_attr "length" "8")])
5616
5617 (define_insn "*negdi2_noppc64"
5618 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5619 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5620 "! TARGET_POWERPC64"
5621 "*
5622 {
5623 return (WORDS_BIG_ENDIAN)
5624 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5625 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5626 }"
5627 [(set_attr "type" "two")
5628 (set_attr "length" "8")])
5629
5630 (define_expand "mulsidi3"
5631 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5632 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5633 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5634 "! TARGET_POWERPC64"
5635 "
5636 {
5637 if (! TARGET_POWER && ! TARGET_POWERPC)
5638 {
5639 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5640 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5641 emit_insn (gen_mull_call ());
5642 if (WORDS_BIG_ENDIAN)
5643 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5644 else
5645 {
5646 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5647 gen_rtx_REG (SImode, 3));
5648 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5649 gen_rtx_REG (SImode, 4));
5650 }
5651 DONE;
5652 }
5653 else if (TARGET_POWER)
5654 {
5655 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5656 DONE;
5657 }
5658 }")
5659
5660 (define_insn "mulsidi3_mq"
5661 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5662 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5663 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5664 (clobber (match_scratch:SI 3 "=q"))]
5665 "TARGET_POWER"
5666 "mul %0,%1,%2\;mfmq %L0"
5667 [(set_attr "type" "imul")
5668 (set_attr "length" "8")])
5669
5670 (define_insn "*mulsidi3_no_mq"
5671 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5672 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5673 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5674 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5675 "*
5676 {
5677 return (WORDS_BIG_ENDIAN)
5678 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5679 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5680 }"
5681 [(set_attr "type" "imul")
5682 (set_attr "length" "8")])
5683
5684 (define_split
5685 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5686 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5687 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5688 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5689 [(set (match_dup 3)
5690 (truncate:SI
5691 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5692 (sign_extend:DI (match_dup 2)))
5693 (const_int 32))))
5694 (set (match_dup 4)
5695 (mult:SI (match_dup 1)
5696 (match_dup 2)))]
5697 "
5698 {
5699 int endian = (WORDS_BIG_ENDIAN == 0);
5700 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5701 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5702 }")
5703
5704 (define_expand "umulsidi3"
5705 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5706 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5707 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5708 "TARGET_POWERPC && ! TARGET_POWERPC64"
5709 "
5710 {
5711 if (TARGET_POWER)
5712 {
5713 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5714 DONE;
5715 }
5716 }")
5717
5718 (define_insn "umulsidi3_mq"
5719 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5720 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5721 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5722 (clobber (match_scratch:SI 3 "=q"))]
5723 "TARGET_POWERPC && TARGET_POWER"
5724 "*
5725 {
5726 return (WORDS_BIG_ENDIAN)
5727 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5728 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5729 }"
5730 [(set_attr "type" "imul")
5731 (set_attr "length" "8")])
5732
5733 (define_insn "*umulsidi3_no_mq"
5734 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5735 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5736 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5737 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5738 "*
5739 {
5740 return (WORDS_BIG_ENDIAN)
5741 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5742 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5743 }"
5744 [(set_attr "type" "imul")
5745 (set_attr "length" "8")])
5746
5747 (define_split
5748 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5749 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5750 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5751 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5752 [(set (match_dup 3)
5753 (truncate:SI
5754 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5755 (zero_extend:DI (match_dup 2)))
5756 (const_int 32))))
5757 (set (match_dup 4)
5758 (mult:SI (match_dup 1)
5759 (match_dup 2)))]
5760 "
5761 {
5762 int endian = (WORDS_BIG_ENDIAN == 0);
5763 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5764 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5765 }")
5766
5767 (define_expand "smulsi3_highpart"
5768 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5769 (truncate:SI
5770 (lshiftrt:DI (mult:DI (sign_extend:DI
5771 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5772 (sign_extend:DI
5773 (match_operand:SI 2 "gpc_reg_operand" "r")))
5774 (const_int 32))))]
5775 ""
5776 "
5777 {
5778 if (! TARGET_POWER && ! TARGET_POWERPC)
5779 {
5780 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5781 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5782 emit_insn (gen_mulh_call ());
5783 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5784 DONE;
5785 }
5786 else if (TARGET_POWER)
5787 {
5788 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5789 DONE;
5790 }
5791 }")
5792
5793 (define_insn "smulsi3_highpart_mq"
5794 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5795 (truncate:SI
5796 (lshiftrt:DI (mult:DI (sign_extend:DI
5797 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5798 (sign_extend:DI
5799 (match_operand:SI 2 "gpc_reg_operand" "r")))
5800 (const_int 32))))
5801 (clobber (match_scratch:SI 3 "=q"))]
5802 "TARGET_POWER"
5803 "mul %0,%1,%2"
5804 [(set_attr "type" "imul")])
5805
5806 (define_insn "*smulsi3_highpart_no_mq"
5807 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5808 (truncate:SI
5809 (lshiftrt:DI (mult:DI (sign_extend:DI
5810 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5811 (sign_extend:DI
5812 (match_operand:SI 2 "gpc_reg_operand" "r")))
5813 (const_int 32))))]
5814 "TARGET_POWERPC && ! TARGET_POWER"
5815 "mulhw %0,%1,%2"
5816 [(set_attr "type" "imul")])
5817
5818 (define_expand "umulsi3_highpart"
5819 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5820 (truncate:SI
5821 (lshiftrt:DI (mult:DI (zero_extend:DI
5822 (match_operand:SI 1 "gpc_reg_operand" ""))
5823 (zero_extend:DI
5824 (match_operand:SI 2 "gpc_reg_operand" "")))
5825 (const_int 32))))]
5826 "TARGET_POWERPC"
5827 "
5828 {
5829 if (TARGET_POWER)
5830 {
5831 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5832 DONE;
5833 }
5834 }")
5835
5836 (define_insn "umulsi3_highpart_mq"
5837 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5838 (truncate:SI
5839 (lshiftrt:DI (mult:DI (zero_extend:DI
5840 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5841 (zero_extend:DI
5842 (match_operand:SI 2 "gpc_reg_operand" "r")))
5843 (const_int 32))))
5844 (clobber (match_scratch:SI 3 "=q"))]
5845 "TARGET_POWERPC && TARGET_POWER"
5846 "mulhwu %0,%1,%2"
5847 [(set_attr "type" "imul")])
5848
5849 (define_insn "*umulsi3_highpart_no_mq"
5850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5851 (truncate:SI
5852 (lshiftrt:DI (mult:DI (zero_extend:DI
5853 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5854 (zero_extend:DI
5855 (match_operand:SI 2 "gpc_reg_operand" "r")))
5856 (const_int 32))))]
5857 "TARGET_POWERPC && ! TARGET_POWER"
5858 "mulhwu %0,%1,%2"
5859 [(set_attr "type" "imul")])
5860
5861 ;; If operands 0 and 2 are in the same register, we have a problem. But
5862 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5863 ;; why we have the strange constraints below.
5864 (define_insn "ashldi3_power"
5865 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5866 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5867 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5868 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5869 "TARGET_POWER"
5870 "@
5871 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5872 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5873 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5874 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5875 [(set_attr "length" "8")])
5876
5877 (define_insn "lshrdi3_power"
5878 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5879 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5880 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5881 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5882 "TARGET_POWER"
5883 "@
5884 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5885 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5886 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5887 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5888 [(set_attr "length" "8")])
5889
5890 ;; Shift by a variable amount is too complex to be worth open-coding. We
5891 ;; just handle shifts by constants.
5892 (define_insn "ashrdi3_power"
5893 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5894 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5895 (match_operand:SI 2 "const_int_operand" "M,i")))
5896 (clobber (match_scratch:SI 3 "=X,q"))]
5897 "TARGET_POWER"
5898 "@
5899 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5900 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5901 [(set_attr "length" "8")])
5902
5903 (define_insn "ashrdi3_no_power"
5904 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5905 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5906 (match_operand:SI 2 "const_int_operand" "M,i")))]
5907 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5908 "@
5909 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5910 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5911 [(set_attr "type" "two,three")
5912 (set_attr "length" "8,12")])
5913
5914 (define_insn "*ashrdisi3_noppc64"
5915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5916 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5917 (const_int 32)) 4))]
5918 "TARGET_32BIT && !TARGET_POWERPC64"
5919 "*
5920 {
5921 if (REGNO (operands[0]) == REGNO (operands[1]))
5922 return \"\";
5923 else
5924 return \"mr %0,%1\";
5925 }"
5926 [(set_attr "length" "4")])
5927
5928 \f
5929 ;; PowerPC64 DImode operations.
5930
5931 (define_insn_and_split "absdi2"
5932 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5933 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5934 (clobber (match_scratch:DI 2 "=&r,&r"))]
5935 "TARGET_POWERPC64"
5936 "#"
5937 "&& reload_completed"
5938 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5939 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5940 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5941 "")
5942
5943 (define_insn_and_split "*nabsdi2"
5944 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5945 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5946 (clobber (match_scratch:DI 2 "=&r,&r"))]
5947 "TARGET_POWERPC64"
5948 "#"
5949 "&& reload_completed"
5950 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5951 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5952 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5953 "")
5954
5955 (define_insn "muldi3"
5956 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5957 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5958 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5959 "TARGET_POWERPC64"
5960 "mulld %0,%1,%2"
5961 [(set_attr "type" "lmul")])
5962
5963 (define_insn "*muldi3_internal1"
5964 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5965 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5966 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5967 (const_int 0)))
5968 (clobber (match_scratch:DI 3 "=r,r"))]
5969 "TARGET_POWERPC64"
5970 "@
5971 mulld. %3,%1,%2
5972 #"
5973 [(set_attr "type" "lmul_compare")
5974 (set_attr "length" "4,8")])
5975
5976 (define_split
5977 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5978 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5979 (match_operand:DI 2 "gpc_reg_operand" ""))
5980 (const_int 0)))
5981 (clobber (match_scratch:DI 3 ""))]
5982 "TARGET_POWERPC64 && reload_completed"
5983 [(set (match_dup 3)
5984 (mult:DI (match_dup 1) (match_dup 2)))
5985 (set (match_dup 0)
5986 (compare:CC (match_dup 3)
5987 (const_int 0)))]
5988 "")
5989
5990 (define_insn "*muldi3_internal2"
5991 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5992 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5993 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5994 (const_int 0)))
5995 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5996 (mult:DI (match_dup 1) (match_dup 2)))]
5997 "TARGET_POWERPC64"
5998 "@
5999 mulld. %0,%1,%2
6000 #"
6001 [(set_attr "type" "lmul_compare")
6002 (set_attr "length" "4,8")])
6003
6004 (define_split
6005 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6006 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6007 (match_operand:DI 2 "gpc_reg_operand" ""))
6008 (const_int 0)))
6009 (set (match_operand:DI 0 "gpc_reg_operand" "")
6010 (mult:DI (match_dup 1) (match_dup 2)))]
6011 "TARGET_POWERPC64 && reload_completed"
6012 [(set (match_dup 0)
6013 (mult:DI (match_dup 1) (match_dup 2)))
6014 (set (match_dup 3)
6015 (compare:CC (match_dup 0)
6016 (const_int 0)))]
6017 "")
6018
6019 (define_insn "smuldi3_highpart"
6020 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6021 (truncate:DI
6022 (lshiftrt:TI (mult:TI (sign_extend:TI
6023 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6024 (sign_extend:TI
6025 (match_operand:DI 2 "gpc_reg_operand" "r")))
6026 (const_int 64))))]
6027 "TARGET_POWERPC64"
6028 "mulhd %0,%1,%2"
6029 [(set_attr "type" "lmul")])
6030
6031 (define_insn "umuldi3_highpart"
6032 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6033 (truncate:DI
6034 (lshiftrt:TI (mult:TI (zero_extend:TI
6035 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6036 (zero_extend:TI
6037 (match_operand:DI 2 "gpc_reg_operand" "r")))
6038 (const_int 64))))]
6039 "TARGET_POWERPC64"
6040 "mulhdu %0,%1,%2"
6041 [(set_attr "type" "lmul")])
6042
6043 (define_insn "rotldi3"
6044 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6045 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6046 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6047 "TARGET_POWERPC64"
6048 "rld%I2cl %0,%1,%H2,0")
6049
6050 (define_insn "*rotldi3_internal2"
6051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6052 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6053 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6054 (const_int 0)))
6055 (clobber (match_scratch:DI 3 "=r,r"))]
6056 "TARGET_64BIT"
6057 "@
6058 rld%I2cl. %3,%1,%H2,0
6059 #"
6060 [(set_attr "type" "delayed_compare")
6061 (set_attr "length" "4,8")])
6062
6063 (define_split
6064 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6065 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6066 (match_operand:DI 2 "reg_or_cint_operand" ""))
6067 (const_int 0)))
6068 (clobber (match_scratch:DI 3 ""))]
6069 "TARGET_POWERPC64 && reload_completed"
6070 [(set (match_dup 3)
6071 (rotate:DI (match_dup 1) (match_dup 2)))
6072 (set (match_dup 0)
6073 (compare:CC (match_dup 3)
6074 (const_int 0)))]
6075 "")
6076
6077 (define_insn "*rotldi3_internal3"
6078 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6079 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6080 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6081 (const_int 0)))
6082 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6083 (rotate:DI (match_dup 1) (match_dup 2)))]
6084 "TARGET_64BIT"
6085 "@
6086 rld%I2cl. %0,%1,%H2,0
6087 #"
6088 [(set_attr "type" "delayed_compare")
6089 (set_attr "length" "4,8")])
6090
6091 (define_split
6092 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6093 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6094 (match_operand:DI 2 "reg_or_cint_operand" ""))
6095 (const_int 0)))
6096 (set (match_operand:DI 0 "gpc_reg_operand" "")
6097 (rotate:DI (match_dup 1) (match_dup 2)))]
6098 "TARGET_POWERPC64 && reload_completed"
6099 [(set (match_dup 0)
6100 (rotate:DI (match_dup 1) (match_dup 2)))
6101 (set (match_dup 3)
6102 (compare:CC (match_dup 0)
6103 (const_int 0)))]
6104 "")
6105
6106 (define_insn "*rotldi3_internal4"
6107 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6108 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6109 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6110 (match_operand:DI 3 "mask_operand" "n")))]
6111 "TARGET_POWERPC64"
6112 "rld%I2c%B3 %0,%1,%H2,%S3")
6113
6114 (define_insn "*rotldi3_internal5"
6115 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6116 (compare:CC (and:DI
6117 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6118 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6119 (match_operand:DI 3 "mask_operand" "n,n"))
6120 (const_int 0)))
6121 (clobber (match_scratch:DI 4 "=r,r"))]
6122 "TARGET_64BIT"
6123 "@
6124 rld%I2c%B3. %4,%1,%H2,%S3
6125 #"
6126 [(set_attr "type" "delayed_compare")
6127 (set_attr "length" "4,8")])
6128
6129 (define_split
6130 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6131 (compare:CC (and:DI
6132 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6133 (match_operand:DI 2 "reg_or_cint_operand" ""))
6134 (match_operand:DI 3 "mask_operand" ""))
6135 (const_int 0)))
6136 (clobber (match_scratch:DI 4 ""))]
6137 "TARGET_POWERPC64 && reload_completed"
6138 [(set (match_dup 4)
6139 (and:DI (rotate:DI (match_dup 1)
6140 (match_dup 2))
6141 (match_dup 3)))
6142 (set (match_dup 0)
6143 (compare:CC (match_dup 4)
6144 (const_int 0)))]
6145 "")
6146
6147 (define_insn "*rotldi3_internal6"
6148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6149 (compare:CC (and:DI
6150 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6151 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6152 (match_operand:DI 3 "mask_operand" "n,n"))
6153 (const_int 0)))
6154 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6155 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6156 "TARGET_64BIT"
6157 "@
6158 rld%I2c%B3. %0,%1,%H2,%S3
6159 #"
6160 [(set_attr "type" "delayed_compare")
6161 (set_attr "length" "4,8")])
6162
6163 (define_split
6164 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6165 (compare:CC (and:DI
6166 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6167 (match_operand:DI 2 "reg_or_cint_operand" ""))
6168 (match_operand:DI 3 "mask_operand" ""))
6169 (const_int 0)))
6170 (set (match_operand:DI 0 "gpc_reg_operand" "")
6171 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6172 "TARGET_POWERPC64 && reload_completed"
6173 [(set (match_dup 0)
6174 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6175 (set (match_dup 4)
6176 (compare:CC (match_dup 0)
6177 (const_int 0)))]
6178 "")
6179
6180 (define_insn "*rotldi3_internal7"
6181 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6182 (zero_extend:DI
6183 (subreg:QI
6184 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6185 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6186 "TARGET_POWERPC64"
6187 "rld%I2cl %0,%1,%H2,56")
6188
6189 (define_insn "*rotldi3_internal8"
6190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6191 (compare:CC (zero_extend:DI
6192 (subreg:QI
6193 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6194 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6195 (const_int 0)))
6196 (clobber (match_scratch:DI 3 "=r,r"))]
6197 "TARGET_64BIT"
6198 "@
6199 rld%I2cl. %3,%1,%H2,56
6200 #"
6201 [(set_attr "type" "delayed_compare")
6202 (set_attr "length" "4,8")])
6203
6204 (define_split
6205 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6206 (compare:CC (zero_extend:DI
6207 (subreg:QI
6208 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6209 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6210 (const_int 0)))
6211 (clobber (match_scratch:DI 3 ""))]
6212 "TARGET_POWERPC64 && reload_completed"
6213 [(set (match_dup 3)
6214 (zero_extend:DI (subreg:QI
6215 (rotate:DI (match_dup 1)
6216 (match_dup 2)) 0)))
6217 (set (match_dup 0)
6218 (compare:CC (match_dup 3)
6219 (const_int 0)))]
6220 "")
6221
6222 (define_insn "*rotldi3_internal9"
6223 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6224 (compare:CC (zero_extend:DI
6225 (subreg:QI
6226 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6227 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6228 (const_int 0)))
6229 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6230 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6231 "TARGET_64BIT"
6232 "@
6233 rld%I2cl. %0,%1,%H2,56
6234 #"
6235 [(set_attr "type" "delayed_compare")
6236 (set_attr "length" "4,8")])
6237
6238 (define_split
6239 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6240 (compare:CC (zero_extend:DI
6241 (subreg:QI
6242 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6243 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6244 (const_int 0)))
6245 (set (match_operand:DI 0 "gpc_reg_operand" "")
6246 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6247 "TARGET_POWERPC64 && reload_completed"
6248 [(set (match_dup 0)
6249 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6250 (set (match_dup 3)
6251 (compare:CC (match_dup 0)
6252 (const_int 0)))]
6253 "")
6254
6255 (define_insn "*rotldi3_internal10"
6256 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6257 (zero_extend:DI
6258 (subreg:HI
6259 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6260 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6261 "TARGET_POWERPC64"
6262 "rld%I2cl %0,%1,%H2,48")
6263
6264 (define_insn "*rotldi3_internal11"
6265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6266 (compare:CC (zero_extend:DI
6267 (subreg:HI
6268 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6269 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6270 (const_int 0)))
6271 (clobber (match_scratch:DI 3 "=r,r"))]
6272 "TARGET_64BIT"
6273 "@
6274 rld%I2cl. %3,%1,%H2,48
6275 #"
6276 [(set_attr "type" "delayed_compare")
6277 (set_attr "length" "4,8")])
6278
6279 (define_split
6280 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6281 (compare:CC (zero_extend:DI
6282 (subreg:HI
6283 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6284 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6285 (const_int 0)))
6286 (clobber (match_scratch:DI 3 ""))]
6287 "TARGET_POWERPC64 && reload_completed"
6288 [(set (match_dup 3)
6289 (zero_extend:DI (subreg:HI
6290 (rotate:DI (match_dup 1)
6291 (match_dup 2)) 0)))
6292 (set (match_dup 0)
6293 (compare:CC (match_dup 3)
6294 (const_int 0)))]
6295 "")
6296
6297 (define_insn "*rotldi3_internal12"
6298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6299 (compare:CC (zero_extend:DI
6300 (subreg:HI
6301 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6302 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6303 (const_int 0)))
6304 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6305 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6306 "TARGET_64BIT"
6307 "@
6308 rld%I2cl. %0,%1,%H2,48
6309 #"
6310 [(set_attr "type" "delayed_compare")
6311 (set_attr "length" "4,8")])
6312
6313 (define_split
6314 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6315 (compare:CC (zero_extend:DI
6316 (subreg:HI
6317 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6318 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6319 (const_int 0)))
6320 (set (match_operand:DI 0 "gpc_reg_operand" "")
6321 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6322 "TARGET_POWERPC64 && reload_completed"
6323 [(set (match_dup 0)
6324 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6325 (set (match_dup 3)
6326 (compare:CC (match_dup 0)
6327 (const_int 0)))]
6328 "")
6329
6330 (define_insn "*rotldi3_internal13"
6331 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6332 (zero_extend:DI
6333 (subreg:SI
6334 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6335 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6336 "TARGET_POWERPC64"
6337 "rld%I2cl %0,%1,%H2,32")
6338
6339 (define_insn "*rotldi3_internal14"
6340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6341 (compare:CC (zero_extend:DI
6342 (subreg:SI
6343 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6344 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6345 (const_int 0)))
6346 (clobber (match_scratch:DI 3 "=r,r"))]
6347 "TARGET_64BIT"
6348 "@
6349 rld%I2cl. %3,%1,%H2,32
6350 #"
6351 [(set_attr "type" "delayed_compare")
6352 (set_attr "length" "4,8")])
6353
6354 (define_split
6355 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6356 (compare:CC (zero_extend:DI
6357 (subreg:SI
6358 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6359 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6360 (const_int 0)))
6361 (clobber (match_scratch:DI 3 ""))]
6362 "TARGET_POWERPC64 && reload_completed"
6363 [(set (match_dup 3)
6364 (zero_extend:DI (subreg:SI
6365 (rotate:DI (match_dup 1)
6366 (match_dup 2)) 0)))
6367 (set (match_dup 0)
6368 (compare:CC (match_dup 3)
6369 (const_int 0)))]
6370 "")
6371
6372 (define_insn "*rotldi3_internal15"
6373 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6374 (compare:CC (zero_extend:DI
6375 (subreg:SI
6376 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6377 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6378 (const_int 0)))
6379 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6380 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6381 "TARGET_64BIT"
6382 "@
6383 rld%I2cl. %0,%1,%H2,32
6384 #"
6385 [(set_attr "type" "delayed_compare")
6386 (set_attr "length" "4,8")])
6387
6388 (define_split
6389 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6390 (compare:CC (zero_extend:DI
6391 (subreg:SI
6392 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6393 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6394 (const_int 0)))
6395 (set (match_operand:DI 0 "gpc_reg_operand" "")
6396 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6397 "TARGET_POWERPC64 && reload_completed"
6398 [(set (match_dup 0)
6399 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6400 (set (match_dup 3)
6401 (compare:CC (match_dup 0)
6402 (const_int 0)))]
6403 "")
6404
6405 (define_expand "ashldi3"
6406 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6407 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6408 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6409 "TARGET_POWERPC64 || TARGET_POWER"
6410 "
6411 {
6412 if (TARGET_POWERPC64)
6413 ;
6414 else if (TARGET_POWER)
6415 {
6416 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6417 DONE;
6418 }
6419 else
6420 FAIL;
6421 }")
6422
6423 (define_insn "*ashldi3_internal1"
6424 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6425 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6426 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6427 "TARGET_POWERPC64"
6428 "sld%I2 %0,%1,%H2")
6429
6430 (define_insn "*ashldi3_internal2"
6431 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6432 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6433 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6434 (const_int 0)))
6435 (clobber (match_scratch:DI 3 "=r,r"))]
6436 "TARGET_64BIT"
6437 "@
6438 sld%I2. %3,%1,%H2
6439 #"
6440 [(set_attr "type" "delayed_compare")
6441 (set_attr "length" "4,8")])
6442
6443 (define_split
6444 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6445 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6446 (match_operand:SI 2 "reg_or_cint_operand" ""))
6447 (const_int 0)))
6448 (clobber (match_scratch:DI 3 ""))]
6449 "TARGET_POWERPC64 && reload_completed"
6450 [(set (match_dup 3)
6451 (ashift:DI (match_dup 1) (match_dup 2)))
6452 (set (match_dup 0)
6453 (compare:CC (match_dup 3)
6454 (const_int 0)))]
6455 "")
6456
6457 (define_insn "*ashldi3_internal3"
6458 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6459 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6460 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6461 (const_int 0)))
6462 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6463 (ashift:DI (match_dup 1) (match_dup 2)))]
6464 "TARGET_64BIT"
6465 "@
6466 sld%I2. %0,%1,%H2
6467 #"
6468 [(set_attr "type" "delayed_compare")
6469 (set_attr "length" "4,8")])
6470
6471 (define_split
6472 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6473 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6474 (match_operand:SI 2 "reg_or_cint_operand" ""))
6475 (const_int 0)))
6476 (set (match_operand:DI 0 "gpc_reg_operand" "")
6477 (ashift:DI (match_dup 1) (match_dup 2)))]
6478 "TARGET_POWERPC64 && reload_completed"
6479 [(set (match_dup 0)
6480 (ashift:DI (match_dup 1) (match_dup 2)))
6481 (set (match_dup 3)
6482 (compare:CC (match_dup 0)
6483 (const_int 0)))]
6484 "")
6485
6486 (define_insn "*ashldi3_internal4"
6487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6488 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6489 (match_operand:SI 2 "const_int_operand" "i"))
6490 (match_operand:DI 3 "const_int_operand" "n")))]
6491 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6492 "rldic %0,%1,%H2,%W3")
6493
6494 (define_insn "ashldi3_internal5"
6495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6496 (compare:CC
6497 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6498 (match_operand:SI 2 "const_int_operand" "i,i"))
6499 (match_operand:DI 3 "const_int_operand" "n,n"))
6500 (const_int 0)))
6501 (clobber (match_scratch:DI 4 "=r,r"))]
6502 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6503 "@
6504 rldic. %4,%1,%H2,%W3
6505 #"
6506 [(set_attr "type" "delayed_compare")
6507 (set_attr "length" "4,8")])
6508
6509 (define_split
6510 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6511 (compare:CC
6512 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6513 (match_operand:SI 2 "const_int_operand" ""))
6514 (match_operand:DI 3 "const_int_operand" ""))
6515 (const_int 0)))
6516 (clobber (match_scratch:DI 4 ""))]
6517 "TARGET_POWERPC64 && reload_completed
6518 && includes_rldic_lshift_p (operands[2], operands[3])"
6519 [(set (match_dup 4)
6520 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6521 (match_dup 3)))
6522 (set (match_dup 0)
6523 (compare:CC (match_dup 4)
6524 (const_int 0)))]
6525 "")
6526
6527 (define_insn "*ashldi3_internal6"
6528 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6529 (compare:CC
6530 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6531 (match_operand:SI 2 "const_int_operand" "i,i"))
6532 (match_operand:DI 3 "const_int_operand" "n,n"))
6533 (const_int 0)))
6534 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6535 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6536 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6537 "@
6538 rldic. %0,%1,%H2,%W3
6539 #"
6540 [(set_attr "type" "delayed_compare")
6541 (set_attr "length" "4,8")])
6542
6543 (define_split
6544 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6545 (compare:CC
6546 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6547 (match_operand:SI 2 "const_int_operand" ""))
6548 (match_operand:DI 3 "const_int_operand" ""))
6549 (const_int 0)))
6550 (set (match_operand:DI 0 "gpc_reg_operand" "")
6551 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6552 "TARGET_POWERPC64 && reload_completed
6553 && includes_rldic_lshift_p (operands[2], operands[3])"
6554 [(set (match_dup 0)
6555 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6556 (match_dup 3)))
6557 (set (match_dup 4)
6558 (compare:CC (match_dup 0)
6559 (const_int 0)))]
6560 "")
6561
6562 (define_insn "*ashldi3_internal7"
6563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6564 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6565 (match_operand:SI 2 "const_int_operand" "i"))
6566 (match_operand:DI 3 "mask_operand" "n")))]
6567 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6568 "rldicr %0,%1,%H2,%S3")
6569
6570 (define_insn "ashldi3_internal8"
6571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6572 (compare:CC
6573 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6574 (match_operand:SI 2 "const_int_operand" "i,i"))
6575 (match_operand:DI 3 "mask_operand" "n,n"))
6576 (const_int 0)))
6577 (clobber (match_scratch:DI 4 "=r,r"))]
6578 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6579 "@
6580 rldicr. %4,%1,%H2,%S3
6581 #"
6582 [(set_attr "type" "delayed_compare")
6583 (set_attr "length" "4,8")])
6584
6585 (define_split
6586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6587 (compare:CC
6588 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6589 (match_operand:SI 2 "const_int_operand" ""))
6590 (match_operand:DI 3 "mask_operand" ""))
6591 (const_int 0)))
6592 (clobber (match_scratch:DI 4 ""))]
6593 "TARGET_POWERPC64 && reload_completed
6594 && includes_rldicr_lshift_p (operands[2], operands[3])"
6595 [(set (match_dup 4)
6596 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6597 (match_dup 3)))
6598 (set (match_dup 0)
6599 (compare:CC (match_dup 4)
6600 (const_int 0)))]
6601 "")
6602
6603 (define_insn "*ashldi3_internal9"
6604 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6605 (compare:CC
6606 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6607 (match_operand:SI 2 "const_int_operand" "i,i"))
6608 (match_operand:DI 3 "mask_operand" "n,n"))
6609 (const_int 0)))
6610 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6611 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6612 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6613 "@
6614 rldicr. %0,%1,%H2,%S3
6615 #"
6616 [(set_attr "type" "delayed_compare")
6617 (set_attr "length" "4,8")])
6618
6619 (define_split
6620 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6621 (compare:CC
6622 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6623 (match_operand:SI 2 "const_int_operand" ""))
6624 (match_operand:DI 3 "mask_operand" ""))
6625 (const_int 0)))
6626 (set (match_operand:DI 0 "gpc_reg_operand" "")
6627 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6628 "TARGET_POWERPC64 && reload_completed
6629 && includes_rldicr_lshift_p (operands[2], operands[3])"
6630 [(set (match_dup 0)
6631 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6632 (match_dup 3)))
6633 (set (match_dup 4)
6634 (compare:CC (match_dup 0)
6635 (const_int 0)))]
6636 "")
6637
6638 (define_expand "lshrdi3"
6639 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6640 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6641 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6642 "TARGET_POWERPC64 || TARGET_POWER"
6643 "
6644 {
6645 if (TARGET_POWERPC64)
6646 ;
6647 else if (TARGET_POWER)
6648 {
6649 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6650 DONE;
6651 }
6652 else
6653 FAIL;
6654 }")
6655
6656 (define_insn "*lshrdi3_internal1"
6657 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6658 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6659 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6660 "TARGET_POWERPC64"
6661 "srd%I2 %0,%1,%H2")
6662
6663 (define_insn "*lshrdi3_internal2"
6664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6665 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6666 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6667 (const_int 0)))
6668 (clobber (match_scratch:DI 3 "=r,r"))]
6669 "TARGET_64BIT "
6670 "@
6671 srd%I2. %3,%1,%H2
6672 #"
6673 [(set_attr "type" "delayed_compare")
6674 (set_attr "length" "4,8")])
6675
6676 (define_split
6677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6678 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6679 (match_operand:SI 2 "reg_or_cint_operand" ""))
6680 (const_int 0)))
6681 (clobber (match_scratch:DI 3 ""))]
6682 "TARGET_POWERPC64 && reload_completed"
6683 [(set (match_dup 3)
6684 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6685 (set (match_dup 0)
6686 (compare:CC (match_dup 3)
6687 (const_int 0)))]
6688 "")
6689
6690 (define_insn "*lshrdi3_internal3"
6691 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6692 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6693 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6694 (const_int 0)))
6695 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6696 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6697 "TARGET_64BIT"
6698 "@
6699 srd%I2. %0,%1,%H2
6700 #"
6701 [(set_attr "type" "delayed_compare")
6702 (set_attr "length" "4,8")])
6703
6704 (define_split
6705 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6706 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6707 (match_operand:SI 2 "reg_or_cint_operand" ""))
6708 (const_int 0)))
6709 (set (match_operand:DI 0 "gpc_reg_operand" "")
6710 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6711 "TARGET_POWERPC64 && reload_completed"
6712 [(set (match_dup 0)
6713 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6714 (set (match_dup 3)
6715 (compare:CC (match_dup 0)
6716 (const_int 0)))]
6717 "")
6718
6719 (define_expand "ashrdi3"
6720 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6721 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6722 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6723 "WORDS_BIG_ENDIAN"
6724 "
6725 {
6726 if (TARGET_POWERPC64)
6727 ;
6728 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6729 {
6730 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6731 DONE;
6732 }
6733 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6734 && WORDS_BIG_ENDIAN)
6735 {
6736 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6737 DONE;
6738 }
6739 else
6740 FAIL;
6741 }")
6742
6743 (define_insn "*ashrdi3_internal1"
6744 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6745 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6746 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6747 "TARGET_POWERPC64"
6748 "srad%I2 %0,%1,%H2")
6749
6750 (define_insn "*ashrdi3_internal2"
6751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6752 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6753 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6754 (const_int 0)))
6755 (clobber (match_scratch:DI 3 "=r,r"))]
6756 "TARGET_64BIT"
6757 "@
6758 srad%I2. %3,%1,%H2
6759 #"
6760 [(set_attr "type" "delayed_compare")
6761 (set_attr "length" "4,8")])
6762
6763 (define_split
6764 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6765 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6766 (match_operand:SI 2 "reg_or_cint_operand" ""))
6767 (const_int 0)))
6768 (clobber (match_scratch:DI 3 ""))]
6769 "TARGET_POWERPC64 && reload_completed"
6770 [(set (match_dup 3)
6771 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6772 (set (match_dup 0)
6773 (compare:CC (match_dup 3)
6774 (const_int 0)))]
6775 "")
6776
6777 (define_insn "*ashrdi3_internal3"
6778 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6779 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6780 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6781 (const_int 0)))
6782 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6783 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6784 "TARGET_64BIT"
6785 "@
6786 srad%I2. %0,%1,%H2
6787 #"
6788 [(set_attr "type" "delayed_compare")
6789 (set_attr "length" "4,8")])
6790
6791 (define_split
6792 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6793 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6794 (match_operand:SI 2 "reg_or_cint_operand" ""))
6795 (const_int 0)))
6796 (set (match_operand:DI 0 "gpc_reg_operand" "")
6797 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6798 "TARGET_POWERPC64 && reload_completed"
6799 [(set (match_dup 0)
6800 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6801 (set (match_dup 3)
6802 (compare:CC (match_dup 0)
6803 (const_int 0)))]
6804 "")
6805
6806 (define_insn "anddi3"
6807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6808 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6809 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6810 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6811 "TARGET_POWERPC64"
6812 "@
6813 and %0,%1,%2
6814 rldic%B2 %0,%1,0,%S2
6815 rlwinm %0,%1,0,%m2,%M2
6816 andi. %0,%1,%b2
6817 andis. %0,%1,%u2
6818 #"
6819 [(set_attr "type" "*,*,*,compare,compare,*")
6820 (set_attr "length" "4,4,4,4,4,8")])
6821
6822 (define_split
6823 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6824 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6825 (match_operand:DI 2 "mask64_2_operand" "")))
6826 (clobber (match_scratch:CC 3 ""))]
6827 "TARGET_POWERPC64
6828 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6829 && !mask_operand (operands[2], DImode)"
6830 [(set (match_dup 0)
6831 (and:DI (rotate:DI (match_dup 1)
6832 (match_dup 4))
6833 (match_dup 5)))
6834 (set (match_dup 0)
6835 (and:DI (rotate:DI (match_dup 0)
6836 (match_dup 6))
6837 (match_dup 7)))]
6838 {
6839 build_mask64_2_operands (operands[2], &operands[4]);
6840 })
6841
6842 (define_insn "*anddi3_internal2"
6843 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6844 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6845 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6846 (const_int 0)))
6847 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6848 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6849 "TARGET_64BIT"
6850 "@
6851 and. %3,%1,%2
6852 rldic%B2. %3,%1,0,%S2
6853 andi. %3,%1,%b2
6854 andis. %3,%1,%u2
6855 #
6856 #
6857 #
6858 #
6859 #
6860 #"
6861 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6862 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6863
6864 (define_split
6865 [(set (match_operand:CC 0 "cc_reg_operand" "")
6866 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6867 (match_operand:DI 2 "mask64_2_operand" ""))
6868 (const_int 0)))
6869 (clobber (match_scratch:DI 3 ""))
6870 (clobber (match_scratch:CC 4 ""))]
6871 "TARGET_POWERPC64 && reload_completed
6872 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6873 && !mask_operand (operands[2], DImode)"
6874 [(set (match_dup 3)
6875 (and:DI (rotate:DI (match_dup 1)
6876 (match_dup 5))
6877 (match_dup 6)))
6878 (parallel [(set (match_dup 0)
6879 (compare:CC (and:DI (rotate:DI (match_dup 3)
6880 (match_dup 7))
6881 (match_dup 8))
6882 (const_int 0)))
6883 (clobber (match_dup 3))])]
6884 "
6885 {
6886 build_mask64_2_operands (operands[2], &operands[5]);
6887 }")
6888
6889 (define_insn "*anddi3_internal3"
6890 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6891 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6892 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6893 (const_int 0)))
6894 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
6895 (and:DI (match_dup 1) (match_dup 2)))
6896 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6897 "TARGET_64BIT"
6898 "@
6899 and. %0,%1,%2
6900 rldic%B2. %0,%1,0,%S2
6901 andi. %0,%1,%b2
6902 andis. %0,%1,%u2
6903 #
6904 #
6905 #
6906 #
6907 #
6908 #"
6909 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6910 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6911
6912 (define_split
6913 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6914 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6915 (match_operand:DI 2 "and_operand" ""))
6916 (const_int 0)))
6917 (set (match_operand:DI 0 "gpc_reg_operand" "")
6918 (and:DI (match_dup 1) (match_dup 2)))
6919 (clobber (match_scratch:CC 4 ""))]
6920 "TARGET_POWERPC64 && reload_completed"
6921 [(parallel [(set (match_dup 0)
6922 (and:DI (match_dup 1) (match_dup 2)))
6923 (clobber (match_dup 4))])
6924 (set (match_dup 3)
6925 (compare:CC (match_dup 0)
6926 (const_int 0)))]
6927 "")
6928
6929 (define_split
6930 [(set (match_operand:CC 3 "cc_reg_operand" "")
6931 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6932 (match_operand:DI 2 "mask64_2_operand" ""))
6933 (const_int 0)))
6934 (set (match_operand:DI 0 "gpc_reg_operand" "")
6935 (and:DI (match_dup 1) (match_dup 2)))
6936 (clobber (match_scratch:CC 4 ""))]
6937 "TARGET_POWERPC64 && reload_completed
6938 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6939 && !mask_operand (operands[2], DImode)"
6940 [(set (match_dup 0)
6941 (and:DI (rotate:DI (match_dup 1)
6942 (match_dup 5))
6943 (match_dup 6)))
6944 (parallel [(set (match_dup 3)
6945 (compare:CC (and:DI (rotate:DI (match_dup 0)
6946 (match_dup 7))
6947 (match_dup 8))
6948 (const_int 0)))
6949 (set (match_dup 0)
6950 (and:DI (rotate:DI (match_dup 0)
6951 (match_dup 7))
6952 (match_dup 8)))])]
6953 "
6954 {
6955 build_mask64_2_operands (operands[2], &operands[5]);
6956 }")
6957
6958 (define_expand "iordi3"
6959 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6960 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6961 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6962 "TARGET_POWERPC64"
6963 "
6964 {
6965 if (non_logical_cint_operand (operands[2], DImode))
6966 {
6967 HOST_WIDE_INT value;
6968 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6969 ? operands[0] : gen_reg_rtx (DImode));
6970
6971 if (GET_CODE (operands[2]) == CONST_INT)
6972 {
6973 value = INTVAL (operands[2]);
6974 emit_insn (gen_iordi3 (tmp, operands[1],
6975 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6976 }
6977 else
6978 {
6979 value = CONST_DOUBLE_LOW (operands[2]);
6980 emit_insn (gen_iordi3 (tmp, operands[1],
6981 immed_double_const (value
6982 & (~ (HOST_WIDE_INT) 0xffff),
6983 0, DImode)));
6984 }
6985
6986 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6987 DONE;
6988 }
6989 }")
6990
6991 (define_expand "xordi3"
6992 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6993 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6994 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6995 "TARGET_POWERPC64"
6996 "
6997 {
6998 if (non_logical_cint_operand (operands[2], DImode))
6999 {
7000 HOST_WIDE_INT value;
7001 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7002 ? operands[0] : gen_reg_rtx (DImode));
7003
7004 if (GET_CODE (operands[2]) == CONST_INT)
7005 {
7006 value = INTVAL (operands[2]);
7007 emit_insn (gen_xordi3 (tmp, operands[1],
7008 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7009 }
7010 else
7011 {
7012 value = CONST_DOUBLE_LOW (operands[2]);
7013 emit_insn (gen_xordi3 (tmp, operands[1],
7014 immed_double_const (value
7015 & (~ (HOST_WIDE_INT) 0xffff),
7016 0, DImode)));
7017 }
7018
7019 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7020 DONE;
7021 }
7022 }")
7023
7024 (define_insn "*booldi3_internal1"
7025 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7026 (match_operator:DI 3 "boolean_or_operator"
7027 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7028 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7029 "TARGET_POWERPC64"
7030 "@
7031 %q3 %0,%1,%2
7032 %q3i %0,%1,%b2
7033 %q3is %0,%1,%u2")
7034
7035 (define_insn "*booldi3_internal2"
7036 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7037 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7038 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7039 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7040 (const_int 0)))
7041 (clobber (match_scratch:DI 3 "=r,r"))]
7042 "TARGET_64BIT"
7043 "@
7044 %q4. %3,%1,%2
7045 #"
7046 [(set_attr "type" "compare")
7047 (set_attr "length" "4,8")])
7048
7049 (define_split
7050 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7051 (compare:CC (match_operator:DI 4 "boolean_operator"
7052 [(match_operand:DI 1 "gpc_reg_operand" "")
7053 (match_operand:DI 2 "gpc_reg_operand" "")])
7054 (const_int 0)))
7055 (clobber (match_scratch:DI 3 ""))]
7056 "TARGET_POWERPC64 && reload_completed"
7057 [(set (match_dup 3) (match_dup 4))
7058 (set (match_dup 0)
7059 (compare:CC (match_dup 3)
7060 (const_int 0)))]
7061 "")
7062
7063 (define_insn "*booldi3_internal3"
7064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7065 (compare:CC (match_operator:DI 4 "boolean_operator"
7066 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7067 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7068 (const_int 0)))
7069 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7070 (match_dup 4))]
7071 "TARGET_64BIT"
7072 "@
7073 %q4. %0,%1,%2
7074 #"
7075 [(set_attr "type" "compare")
7076 (set_attr "length" "4,8")])
7077
7078 (define_split
7079 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7080 (compare:CC (match_operator:DI 4 "boolean_operator"
7081 [(match_operand:DI 1 "gpc_reg_operand" "")
7082 (match_operand:DI 2 "gpc_reg_operand" "")])
7083 (const_int 0)))
7084 (set (match_operand:DI 0 "gpc_reg_operand" "")
7085 (match_dup 4))]
7086 "TARGET_POWERPC64 && reload_completed"
7087 [(set (match_dup 0) (match_dup 4))
7088 (set (match_dup 3)
7089 (compare:CC (match_dup 0)
7090 (const_int 0)))]
7091 "")
7092
7093 ;; Split a logical operation that we can't do in one insn into two insns,
7094 ;; each of which does one 16-bit part. This is used by combine.
7095
7096 (define_split
7097 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7098 (match_operator:DI 3 "boolean_or_operator"
7099 [(match_operand:DI 1 "gpc_reg_operand" "")
7100 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7101 "TARGET_POWERPC64"
7102 [(set (match_dup 0) (match_dup 4))
7103 (set (match_dup 0) (match_dup 5))]
7104 "
7105 {
7106 rtx i3,i4;
7107
7108 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7109 {
7110 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7111 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7112 0, DImode);
7113 i4 = GEN_INT (value & 0xffff);
7114 }
7115 else
7116 {
7117 i3 = GEN_INT (INTVAL (operands[2])
7118 & (~ (HOST_WIDE_INT) 0xffff));
7119 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7120 }
7121 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7122 operands[1], i3);
7123 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7124 operands[0], i4);
7125 }")
7126
7127 (define_insn "*boolcdi3_internal1"
7128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7129 (match_operator:DI 3 "boolean_operator"
7130 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7131 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7132 "TARGET_POWERPC64"
7133 "%q3 %0,%2,%1")
7134
7135 (define_insn "*boolcdi3_internal2"
7136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7137 (compare:CC (match_operator:DI 4 "boolean_operator"
7138 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7139 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7140 (const_int 0)))
7141 (clobber (match_scratch:DI 3 "=r,r"))]
7142 "TARGET_64BIT"
7143 "@
7144 %q4. %3,%2,%1
7145 #"
7146 [(set_attr "type" "compare")
7147 (set_attr "length" "4,8")])
7148
7149 (define_split
7150 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7151 (compare:CC (match_operator:DI 4 "boolean_operator"
7152 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7153 (match_operand:DI 2 "gpc_reg_operand" "")])
7154 (const_int 0)))
7155 (clobber (match_scratch:DI 3 ""))]
7156 "TARGET_POWERPC64 && reload_completed"
7157 [(set (match_dup 3) (match_dup 4))
7158 (set (match_dup 0)
7159 (compare:CC (match_dup 3)
7160 (const_int 0)))]
7161 "")
7162
7163 (define_insn "*boolcdi3_internal3"
7164 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7165 (compare:CC (match_operator:DI 4 "boolean_operator"
7166 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7167 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7168 (const_int 0)))
7169 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7170 (match_dup 4))]
7171 "TARGET_64BIT"
7172 "@
7173 %q4. %0,%2,%1
7174 #"
7175 [(set_attr "type" "compare")
7176 (set_attr "length" "4,8")])
7177
7178 (define_split
7179 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7180 (compare:CC (match_operator:DI 4 "boolean_operator"
7181 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7182 (match_operand:DI 2 "gpc_reg_operand" "")])
7183 (const_int 0)))
7184 (set (match_operand:DI 0 "gpc_reg_operand" "")
7185 (match_dup 4))]
7186 "TARGET_POWERPC64 && reload_completed"
7187 [(set (match_dup 0) (match_dup 4))
7188 (set (match_dup 3)
7189 (compare:CC (match_dup 0)
7190 (const_int 0)))]
7191 "")
7192
7193 (define_insn "*boolccdi3_internal1"
7194 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7195 (match_operator:DI 3 "boolean_operator"
7196 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7197 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7198 "TARGET_POWERPC64"
7199 "%q3 %0,%1,%2")
7200
7201 (define_insn "*boolccdi3_internal2"
7202 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7203 (compare:CC (match_operator:DI 4 "boolean_operator"
7204 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7205 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7206 (const_int 0)))
7207 (clobber (match_scratch:DI 3 "=r,r"))]
7208 "TARGET_64BIT"
7209 "@
7210 %q4. %3,%1,%2
7211 #"
7212 [(set_attr "type" "compare")
7213 (set_attr "length" "4,8")])
7214
7215 (define_split
7216 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7217 (compare:CC (match_operator:DI 4 "boolean_operator"
7218 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7219 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7220 (const_int 0)))
7221 (clobber (match_scratch:DI 3 ""))]
7222 "TARGET_POWERPC64 && reload_completed"
7223 [(set (match_dup 3) (match_dup 4))
7224 (set (match_dup 0)
7225 (compare:CC (match_dup 3)
7226 (const_int 0)))]
7227 "")
7228
7229 (define_insn "*boolccdi3_internal3"
7230 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7231 (compare:CC (match_operator:DI 4 "boolean_operator"
7232 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7233 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7234 (const_int 0)))
7235 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7236 (match_dup 4))]
7237 "TARGET_64BIT"
7238 "@
7239 %q4. %0,%1,%2
7240 #"
7241 [(set_attr "type" "compare")
7242 (set_attr "length" "4,8")])
7243
7244 (define_split
7245 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7246 (compare:CC (match_operator:DI 4 "boolean_operator"
7247 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7248 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7249 (const_int 0)))
7250 (set (match_operand:DI 0 "gpc_reg_operand" "")
7251 (match_dup 4))]
7252 "TARGET_POWERPC64 && reload_completed"
7253 [(set (match_dup 0) (match_dup 4))
7254 (set (match_dup 3)
7255 (compare:CC (match_dup 0)
7256 (const_int 0)))]
7257 "")
7258 \f
7259 ;; Now define ways of moving data around.
7260
7261 ;; Set up a register with a value from the GOT table
7262
7263 (define_expand "movsi_got"
7264 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7265 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7266 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7267 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7268 "
7269 {
7270 if (GET_CODE (operands[1]) == CONST)
7271 {
7272 rtx offset = const0_rtx;
7273 HOST_WIDE_INT value;
7274
7275 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7276 value = INTVAL (offset);
7277 if (value != 0)
7278 {
7279 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7280 emit_insn (gen_movsi_got (tmp, operands[1]));
7281 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7282 DONE;
7283 }
7284 }
7285
7286 operands[2] = rs6000_got_register (operands[1]);
7287 }")
7288
7289 (define_insn "*movsi_got_internal"
7290 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7291 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7292 (match_operand:SI 2 "gpc_reg_operand" "b")]
7293 UNSPEC_MOVSI_GOT))]
7294 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7295 "{l|lwz} %0,%a1@got(%2)"
7296 [(set_attr "type" "load")])
7297
7298 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7299 ;; didn't get allocated to a hard register.
7300 (define_split
7301 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7302 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7303 (match_operand:SI 2 "memory_operand" "")]
7304 UNSPEC_MOVSI_GOT))]
7305 "DEFAULT_ABI == ABI_V4
7306 && flag_pic == 1
7307 && (reload_in_progress || reload_completed)"
7308 [(set (match_dup 0) (match_dup 2))
7309 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7310 UNSPEC_MOVSI_GOT))]
7311 "")
7312
7313 ;; For SI, we special-case integers that can't be loaded in one insn. We
7314 ;; do the load 16-bits at a time. We could do this by loading from memory,
7315 ;; and this is even supposed to be faster, but it is simpler not to get
7316 ;; integers in the TOC.
7317 (define_insn "movsi_low"
7318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7319 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7320 (match_operand 2 "" ""))))]
7321 "TARGET_MACHO && ! TARGET_64BIT"
7322 "{l|lwz} %0,lo16(%2)(%1)"
7323 [(set_attr "type" "load")
7324 (set_attr "length" "4")])
7325
7326 (define_insn "*movsi_internal1"
7327 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7328 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7329 "gpc_reg_operand (operands[0], SImode)
7330 || gpc_reg_operand (operands[1], SImode)"
7331 "@
7332 mr %0,%1
7333 {cal|la} %0,%a1
7334 {l%U1%X1|lwz%U1%X1} %0,%1
7335 {st%U0%X0|stw%U0%X0} %1,%0
7336 {lil|li} %0,%1
7337 {liu|lis} %0,%v1
7338 #
7339 {cal|la} %0,%a1
7340 mf%1 %0
7341 mt%0 %1
7342 mt%0 %1
7343 mt%0 %1
7344 {cror 0,0,0|nop}"
7345 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7346 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7347
7348 ;; Split a load of a large constant into the appropriate two-insn
7349 ;; sequence.
7350
7351 (define_split
7352 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7353 (match_operand:SI 1 "const_int_operand" ""))]
7354 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7355 && (INTVAL (operands[1]) & 0xffff) != 0"
7356 [(set (match_dup 0)
7357 (match_dup 2))
7358 (set (match_dup 0)
7359 (ior:SI (match_dup 0)
7360 (match_dup 3)))]
7361 "
7362 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7363
7364 if (tem == operands[0])
7365 DONE;
7366 else
7367 FAIL;
7368 }")
7369
7370 (define_insn "*mov<mode>_internal2"
7371 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7372 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7373 (const_int 0)))
7374 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7375 ""
7376 "@
7377 {cmpi|cmp<wd>i} %2,%0,0
7378 mr. %0,%1
7379 #"
7380 [(set_attr "type" "cmp,compare,cmp")
7381 (set_attr "length" "4,4,8")])
7382
7383 (define_split
7384 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7385 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7386 (const_int 0)))
7387 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7388 "reload_completed"
7389 [(set (match_dup 0) (match_dup 1))
7390 (set (match_dup 2)
7391 (compare:CC (match_dup 0)
7392 (const_int 0)))]
7393 "")
7394 \f
7395 (define_insn "*movhi_internal"
7396 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7397 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7398 "gpc_reg_operand (operands[0], HImode)
7399 || gpc_reg_operand (operands[1], HImode)"
7400 "@
7401 mr %0,%1
7402 lhz%U1%X1 %0,%1
7403 sth%U0%X0 %1,%0
7404 {lil|li} %0,%w1
7405 mf%1 %0
7406 mt%0 %1
7407 mt%0 %1
7408 {cror 0,0,0|nop}"
7409 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7410
7411 (define_expand "mov<mode>"
7412 [(set (match_operand:INT 0 "general_operand" "")
7413 (match_operand:INT 1 "any_operand" ""))]
7414 ""
7415 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7416
7417 (define_insn "*movqi_internal"
7418 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7419 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7420 "gpc_reg_operand (operands[0], QImode)
7421 || gpc_reg_operand (operands[1], QImode)"
7422 "@
7423 mr %0,%1
7424 lbz%U1%X1 %0,%1
7425 stb%U0%X0 %1,%0
7426 {lil|li} %0,%1
7427 mf%1 %0
7428 mt%0 %1
7429 mt%0 %1
7430 {cror 0,0,0|nop}"
7431 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7432 \f
7433 ;; Here is how to move condition codes around. When we store CC data in
7434 ;; an integer register or memory, we store just the high-order 4 bits.
7435 ;; This lets us not shift in the most common case of CR0.
7436 (define_expand "movcc"
7437 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7438 (match_operand:CC 1 "nonimmediate_operand" ""))]
7439 ""
7440 "")
7441
7442 (define_insn "*movcc_internal1"
7443 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7444 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7445 "register_operand (operands[0], CCmode)
7446 || register_operand (operands[1], CCmode)"
7447 "@
7448 mcrf %0,%1
7449 mtcrf 128,%1
7450 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7451 mfcr %0%Q1
7452 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7453 mr %0,%1
7454 mf%1 %0
7455 mt%0 %1
7456 mt%0 %1
7457 {l%U1%X1|lwz%U1%X1} %0,%1
7458 {st%U0%U1|stw%U0%U1} %1,%0"
7459 [(set (attr "type")
7460 (cond [(eq_attr "alternative" "0")
7461 (const_string "cr_logical")
7462 (eq_attr "alternative" "1,2")
7463 (const_string "mtcr")
7464 (eq_attr "alternative" "5,7")
7465 (const_string "integer")
7466 (eq_attr "alternative" "6")
7467 (const_string "mfjmpr")
7468 (eq_attr "alternative" "8")
7469 (const_string "mtjmpr")
7470 (eq_attr "alternative" "9")
7471 (const_string "load")
7472 (eq_attr "alternative" "10")
7473 (const_string "store")
7474 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7475 (const_string "mfcrf")
7476 ]
7477 (const_string "mfcr")))
7478 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7479 \f
7480 ;; For floating-point, we normally deal with the floating-point registers
7481 ;; unless -msoft-float is used. The sole exception is that parameter passing
7482 ;; can produce floating-point values in fixed-point registers. Unless the
7483 ;; value is a simple constant or already in memory, we deal with this by
7484 ;; allocating memory and copying the value explicitly via that memory location.
7485 (define_expand "movsf"
7486 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7487 (match_operand:SF 1 "any_operand" ""))]
7488 ""
7489 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7490
7491 (define_split
7492 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7493 (match_operand:SF 1 "const_double_operand" ""))]
7494 "reload_completed
7495 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7496 || (GET_CODE (operands[0]) == SUBREG
7497 && GET_CODE (SUBREG_REG (operands[0])) == REG
7498 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7499 [(set (match_dup 2) (match_dup 3))]
7500 "
7501 {
7502 long l;
7503 REAL_VALUE_TYPE rv;
7504
7505 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7506 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7507
7508 if (! TARGET_POWERPC64)
7509 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7510 else
7511 operands[2] = gen_lowpart (SImode, operands[0]);
7512
7513 operands[3] = gen_int_mode (l, SImode);
7514 }")
7515
7516 (define_insn "*movsf_hardfloat"
7517 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7518 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7519 "(gpc_reg_operand (operands[0], SFmode)
7520 || gpc_reg_operand (operands[1], SFmode))
7521 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7522 "@
7523 mr %0,%1
7524 {l%U1%X1|lwz%U1%X1} %0,%1
7525 {st%U0%X0|stw%U0%X0} %1,%0
7526 fmr %0,%1
7527 lfs%U1%X1 %0,%1
7528 stfs%U0%X0 %1,%0
7529 mt%0 %1
7530 mt%0 %1
7531 mf%1 %0
7532 {cror 0,0,0|nop}
7533 #
7534 #"
7535 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7536 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7537
7538 (define_insn "*movsf_softfloat"
7539 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7540 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7541 "(gpc_reg_operand (operands[0], SFmode)
7542 || gpc_reg_operand (operands[1], SFmode))
7543 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7544 "@
7545 mr %0,%1
7546 mt%0 %1
7547 mt%0 %1
7548 mf%1 %0
7549 {l%U1%X1|lwz%U1%X1} %0,%1
7550 {st%U0%X0|stw%U0%X0} %1,%0
7551 {lil|li} %0,%1
7552 {liu|lis} %0,%v1
7553 {cal|la} %0,%a1
7554 #
7555 #
7556 {cror 0,0,0|nop}"
7557 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7558 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7559
7560 \f
7561 (define_expand "movdf"
7562 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7563 (match_operand:DF 1 "any_operand" ""))]
7564 ""
7565 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7566
7567 (define_split
7568 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7569 (match_operand:DF 1 "const_int_operand" ""))]
7570 "! TARGET_POWERPC64 && reload_completed
7571 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7572 || (GET_CODE (operands[0]) == SUBREG
7573 && GET_CODE (SUBREG_REG (operands[0])) == REG
7574 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7575 [(set (match_dup 2) (match_dup 4))
7576 (set (match_dup 3) (match_dup 1))]
7577 "
7578 {
7579 int endian = (WORDS_BIG_ENDIAN == 0);
7580 HOST_WIDE_INT value = INTVAL (operands[1]);
7581
7582 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7583 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7584 #if HOST_BITS_PER_WIDE_INT == 32
7585 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7586 #else
7587 operands[4] = GEN_INT (value >> 32);
7588 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7589 #endif
7590 }")
7591
7592 (define_split
7593 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7594 (match_operand:DF 1 "const_double_operand" ""))]
7595 "! TARGET_POWERPC64 && reload_completed
7596 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7597 || (GET_CODE (operands[0]) == SUBREG
7598 && GET_CODE (SUBREG_REG (operands[0])) == REG
7599 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7600 [(set (match_dup 2) (match_dup 4))
7601 (set (match_dup 3) (match_dup 5))]
7602 "
7603 {
7604 int endian = (WORDS_BIG_ENDIAN == 0);
7605 long l[2];
7606 REAL_VALUE_TYPE rv;
7607
7608 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7609 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7610
7611 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7612 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7613 operands[4] = gen_int_mode (l[endian], SImode);
7614 operands[5] = gen_int_mode (l[1 - endian], SImode);
7615 }")
7616
7617 (define_split
7618 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7619 (match_operand:DF 1 "easy_fp_constant" ""))]
7620 "TARGET_POWERPC64 && reload_completed
7621 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7622 || (GET_CODE (operands[0]) == SUBREG
7623 && GET_CODE (SUBREG_REG (operands[0])) == REG
7624 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7625 [(set (match_dup 2) (match_dup 3))]
7626 "
7627 {
7628 int endian = (WORDS_BIG_ENDIAN == 0);
7629 long l[2];
7630 REAL_VALUE_TYPE rv;
7631 #if HOST_BITS_PER_WIDE_INT >= 64
7632 HOST_WIDE_INT val;
7633 #endif
7634
7635 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7636 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7637
7638 operands[2] = gen_lowpart (DImode, operands[0]);
7639 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7640 #if HOST_BITS_PER_WIDE_INT >= 64
7641 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7642 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7643
7644 operands[3] = gen_int_mode (val, DImode);
7645 #else
7646 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7647 #endif
7648 }")
7649
7650 ;; Don't have reload use general registers to load a constant. First,
7651 ;; it might not work if the output operand is the equivalent of
7652 ;; a non-offsettable memref, but also it is less efficient than loading
7653 ;; the constant into an FP register, since it will probably be used there.
7654 ;; The "??" is a kludge until we can figure out a more reasonable way
7655 ;; of handling these non-offsettable values.
7656 (define_insn "*movdf_hardfloat32"
7657 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7658 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7659 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7660 && (gpc_reg_operand (operands[0], DFmode)
7661 || gpc_reg_operand (operands[1], DFmode))"
7662 "*
7663 {
7664 switch (which_alternative)
7665 {
7666 default:
7667 gcc_unreachable ();
7668 case 0:
7669 /* We normally copy the low-numbered register first. However, if
7670 the first register operand 0 is the same as the second register
7671 of operand 1, we must copy in the opposite order. */
7672 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7673 return \"mr %L0,%L1\;mr %0,%1\";
7674 else
7675 return \"mr %0,%1\;mr %L0,%L1\";
7676 case 1:
7677 if (GET_CODE (operands[1]) == MEM
7678 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7679 reload_completed || reload_in_progress)
7680 || GET_CODE (XEXP (operands[1], 0)) == REG
7681 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7682 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7683 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7684 {
7685 /* If the low-address word is used in the address, we must load
7686 it last. Otherwise, load it first. Note that we cannot have
7687 auto-increment in that case since the address register is
7688 known to be dead. */
7689 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7690 operands[1], 0))
7691 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7692 else
7693 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7694 }
7695 else
7696 {
7697 rtx addreg;
7698
7699 addreg = find_addr_reg (XEXP (operands[1], 0));
7700 if (refers_to_regno_p (REGNO (operands[0]),
7701 REGNO (operands[0]) + 1,
7702 operands[1], 0))
7703 {
7704 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7705 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7706 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7707 return \"{lx|lwzx} %0,%1\";
7708 }
7709 else
7710 {
7711 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7712 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7713 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7714 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7715 return \"\";
7716 }
7717 }
7718 case 2:
7719 if (GET_CODE (operands[0]) == MEM
7720 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7721 reload_completed || reload_in_progress)
7722 || GET_CODE (XEXP (operands[0], 0)) == REG
7723 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7724 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7725 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7726 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7727 else
7728 {
7729 rtx addreg;
7730
7731 addreg = find_addr_reg (XEXP (operands[0], 0));
7732 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7733 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7734 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7735 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7736 return \"\";
7737 }
7738 case 3:
7739 return \"fmr %0,%1\";
7740 case 4:
7741 return \"lfd%U1%X1 %0,%1\";
7742 case 5:
7743 return \"stfd%U0%X0 %1,%0\";
7744 case 6:
7745 case 7:
7746 case 8:
7747 return \"#\";
7748 }
7749 }"
7750 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7751 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7752
7753 (define_insn "*movdf_softfloat32"
7754 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7755 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7756 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7757 && (gpc_reg_operand (operands[0], DFmode)
7758 || gpc_reg_operand (operands[1], DFmode))"
7759 "*
7760 {
7761 switch (which_alternative)
7762 {
7763 default:
7764 gcc_unreachable ();
7765 case 0:
7766 /* We normally copy the low-numbered register first. However, if
7767 the first register operand 0 is the same as the second register of
7768 operand 1, we must copy in the opposite order. */
7769 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7770 return \"mr %L0,%L1\;mr %0,%1\";
7771 else
7772 return \"mr %0,%1\;mr %L0,%L1\";
7773 case 1:
7774 /* If the low-address word is used in the address, we must load
7775 it last. Otherwise, load it first. Note that we cannot have
7776 auto-increment in that case since the address register is
7777 known to be dead. */
7778 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7779 operands[1], 0))
7780 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7781 else
7782 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7783 case 2:
7784 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7785 case 3:
7786 case 4:
7787 case 5:
7788 return \"#\";
7789 }
7790 }"
7791 [(set_attr "type" "two,load,store,*,*,*")
7792 (set_attr "length" "8,8,8,8,12,16")])
7793
7794 ; ld/std require word-aligned displacements -> 'Y' constraint.
7795 ; List Y->r and r->Y before r->r for reload.
7796 (define_insn "*movdf_hardfloat64"
7797 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7798 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7799 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7800 && (gpc_reg_operand (operands[0], DFmode)
7801 || gpc_reg_operand (operands[1], DFmode))"
7802 "@
7803 std%U0%X0 %1,%0
7804 ld%U1%X1 %0,%1
7805 mr %0,%1
7806 fmr %0,%1
7807 lfd%U1%X1 %0,%1
7808 stfd%U0%X0 %1,%0
7809 mt%0 %1
7810 mf%1 %0
7811 {cror 0,0,0|nop}
7812 #
7813 #
7814 #"
7815 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7816 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7817
7818 (define_insn "*movdf_softfloat64"
7819 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7820 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7821 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7822 && (gpc_reg_operand (operands[0], DFmode)
7823 || gpc_reg_operand (operands[1], DFmode))"
7824 "@
7825 ld%U1%X1 %0,%1
7826 std%U0%X0 %1,%0
7827 mr %0,%1
7828 mt%0 %1
7829 mf%1 %0
7830 #
7831 #
7832 #
7833 {cror 0,0,0|nop}"
7834 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7835 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7836 \f
7837 (define_expand "movtf"
7838 [(set (match_operand:TF 0 "general_operand" "")
7839 (match_operand:TF 1 "any_operand" ""))]
7840 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7841 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7842 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7843
7844 ; It's important to list the o->f and f->o moves before f->f because
7845 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7846 ; which doesn't make progress. Likewise r->Y must be before r->r.
7847 (define_insn_and_split "*movtf_internal"
7848 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7849 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7850 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7851 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7852 && (gpc_reg_operand (operands[0], TFmode)
7853 || gpc_reg_operand (operands[1], TFmode))"
7854 "#"
7855 "&& reload_completed"
7856 [(pc)]
7857 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7858 [(set_attr "length" "8,8,8,20,20,16")])
7859
7860 (define_expand "extenddftf2"
7861 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7862 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7863 (use (match_dup 2))])]
7864 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7865 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7866 {
7867 operands[2] = CONST0_RTX (DFmode);
7868 })
7869
7870 (define_insn_and_split "*extenddftf2_internal"
7871 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7872 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7873 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7874 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7875 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7876 "#"
7877 "&& reload_completed"
7878 [(pc)]
7879 {
7880 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7881 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7882 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7883 operands[1]);
7884 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7885 operands[2]);
7886 DONE;
7887 })
7888
7889 (define_expand "extendsftf2"
7890 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7891 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7892 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7893 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7894 {
7895 rtx tmp = gen_reg_rtx (DFmode);
7896 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7897 emit_insn (gen_extenddftf2 (operands[0], tmp));
7898 DONE;
7899 })
7900
7901 (define_expand "trunctfdf2"
7902 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7903 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
7904 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7905 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7906 "")
7907
7908 (define_insn_and_split "trunctfdf2_internal1"
7909 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7910 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7911 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
7912 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7913 "@
7914 #
7915 fmr %0,%1"
7916 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7917 [(const_int 0)]
7918 {
7919 emit_note (NOTE_INSN_DELETED);
7920 DONE;
7921 }
7922 [(set_attr "type" "fp")])
7923
7924 (define_insn "trunctfdf2_internal2"
7925 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7926 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7927 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
7928 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7929 "fadd %0,%1,%L1"
7930 [(set_attr "type" "fp")])
7931
7932 (define_insn_and_split "trunctfsf2"
7933 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7934 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7935 (clobber (match_scratch:DF 2 "=f"))]
7936 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7937 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7938 "#"
7939 "&& reload_completed"
7940 [(set (match_dup 2)
7941 (float_truncate:DF (match_dup 1)))
7942 (set (match_dup 0)
7943 (float_truncate:SF (match_dup 2)))]
7944 "")
7945
7946 (define_expand "floatsitf2"
7947 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7948 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
7949 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7950 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7951 {
7952 rtx tmp = gen_reg_rtx (DFmode);
7953 expand_float (tmp, operands[1], false);
7954 emit_insn (gen_extenddftf2 (operands[0], tmp));
7955 DONE;
7956 })
7957
7958 ; fadd, but rounding towards zero.
7959 ; This is probably not the optimal code sequence.
7960 (define_insn "fix_trunc_helper"
7961 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7962 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7963 UNSPEC_FIX_TRUNC_TF))
7964 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7965 "TARGET_HARD_FLOAT && TARGET_FPRS"
7966 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7967 [(set_attr "type" "fp")
7968 (set_attr "length" "20")])
7969
7970 (define_expand "fix_trunctfsi2"
7971 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7972 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7973 (clobber (match_dup 2))
7974 (clobber (match_dup 3))
7975 (clobber (match_dup 4))
7976 (clobber (match_dup 5))])]
7977 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7978 && (TARGET_POWER2 || TARGET_POWERPC)
7979 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7980 {
7981 operands[2] = gen_reg_rtx (DFmode);
7982 operands[3] = gen_reg_rtx (DFmode);
7983 operands[4] = gen_reg_rtx (DImode);
7984 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7985 })
7986
7987 (define_insn_and_split "*fix_trunctfsi2_internal"
7988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7989 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7990 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7991 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7992 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7993 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
7994 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7995 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7996 "#"
7997 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
7998 [(pc)]
7999 {
8000 rtx lowword;
8001 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8002
8003 gcc_assert (MEM_P (operands[5]));
8004 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8005
8006 emit_insn (gen_fctiwz (operands[4], operands[2]));
8007 emit_move_insn (operands[5], operands[4]);
8008 emit_move_insn (operands[0], lowword);
8009 DONE;
8010 })
8011
8012 (define_insn "negtf2"
8013 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8014 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8015 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8016 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8017 "*
8018 {
8019 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8020 return \"fneg %L0,%L1\;fneg %0,%1\";
8021 else
8022 return \"fneg %0,%1\;fneg %L0,%L1\";
8023 }"
8024 [(set_attr "type" "fp")
8025 (set_attr "length" "8")])
8026
8027 (define_expand "abstf2"
8028 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8029 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8030 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8031 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8032 "
8033 {
8034 rtx label = gen_label_rtx ();
8035 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8036 emit_label (label);
8037 DONE;
8038 }")
8039
8040 (define_expand "abstf2_internal"
8041 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8042 (match_operand:TF 1 "gpc_reg_operand" "f"))
8043 (set (match_dup 3) (match_dup 5))
8044 (set (match_dup 5) (abs:DF (match_dup 5)))
8045 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8046 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8047 (label_ref (match_operand 2 "" ""))
8048 (pc)))
8049 (set (match_dup 6) (neg:DF (match_dup 6)))]
8050 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8051 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8052 "
8053 {
8054 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8055 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8056 operands[3] = gen_reg_rtx (DFmode);
8057 operands[4] = gen_reg_rtx (CCFPmode);
8058 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8059 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8060 }")
8061 \f
8062 ;; Next come the multi-word integer load and store and the load and store
8063 ;; multiple insns.
8064
8065 ; List r->r after r->"o<>", otherwise reload will try to reload a
8066 ; non-offsettable address by using r->r which won't make progress.
8067 (define_insn "*movdi_internal32"
8068 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8069 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8070 "! TARGET_POWERPC64
8071 && (gpc_reg_operand (operands[0], DImode)
8072 || gpc_reg_operand (operands[1], DImode))"
8073 "@
8074 #
8075 #
8076 #
8077 fmr %0,%1
8078 lfd%U1%X1 %0,%1
8079 stfd%U0%X0 %1,%0
8080 #"
8081 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8082
8083 (define_split
8084 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8085 (match_operand:DI 1 "const_int_operand" ""))]
8086 "! TARGET_POWERPC64 && reload_completed"
8087 [(set (match_dup 2) (match_dup 4))
8088 (set (match_dup 3) (match_dup 1))]
8089 "
8090 {
8091 HOST_WIDE_INT value = INTVAL (operands[1]);
8092 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8093 DImode);
8094 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8095 DImode);
8096 #if HOST_BITS_PER_WIDE_INT == 32
8097 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8098 #else
8099 operands[4] = GEN_INT (value >> 32);
8100 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8101 #endif
8102 }")
8103
8104 (define_split
8105 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8106 (match_operand:DI 1 "input_operand" ""))]
8107 "reload_completed && !TARGET_POWERPC64
8108 && gpr_or_gpr_p (operands[0], operands[1])"
8109 [(pc)]
8110 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8111
8112 (define_insn "*movdi_internal64"
8113 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8114 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8115 "TARGET_POWERPC64
8116 && (gpc_reg_operand (operands[0], DImode)
8117 || gpc_reg_operand (operands[1], DImode))"
8118 "@
8119 mr %0,%1
8120 ld%U1%X1 %0,%1
8121 std%U0%X0 %1,%0
8122 li %0,%1
8123 lis %0,%v1
8124 #
8125 {cal|la} %0,%a1
8126 fmr %0,%1
8127 lfd%U1%X1 %0,%1
8128 stfd%U0%X0 %1,%0
8129 mf%1 %0
8130 mt%0 %1
8131 {cror 0,0,0|nop}"
8132 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8133 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8134
8135 ;; immediate value valid for a single instruction hiding in a const_double
8136 (define_insn ""
8137 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8138 (match_operand:DI 1 "const_double_operand" "F"))]
8139 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8140 && GET_CODE (operands[1]) == CONST_DOUBLE
8141 && num_insns_constant (operands[1], DImode) == 1"
8142 "*
8143 {
8144 return ((unsigned HOST_WIDE_INT)
8145 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8146 ? \"li %0,%1\" : \"lis %0,%v1\";
8147 }")
8148
8149 ;; Generate all one-bits and clear left or right.
8150 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8151 (define_split
8152 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8153 (match_operand:DI 1 "mask_operand" ""))]
8154 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8155 [(set (match_dup 0) (const_int -1))
8156 (set (match_dup 0)
8157 (and:DI (rotate:DI (match_dup 0)
8158 (const_int 0))
8159 (match_dup 1)))]
8160 "")
8161
8162 ;; Split a load of a large constant into the appropriate five-instruction
8163 ;; sequence. Handle anything in a constant number of insns.
8164 ;; When non-easy constants can go in the TOC, this should use
8165 ;; easy_fp_constant predicate.
8166 (define_split
8167 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8168 (match_operand:DI 1 "const_int_operand" ""))]
8169 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8170 [(set (match_dup 0) (match_dup 2))
8171 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8172 "
8173 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8174
8175 if (tem == operands[0])
8176 DONE;
8177 else
8178 FAIL;
8179 }")
8180
8181 (define_split
8182 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8183 (match_operand:DI 1 "const_double_operand" ""))]
8184 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8185 [(set (match_dup 0) (match_dup 2))
8186 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8187 "
8188 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8189
8190 if (tem == operands[0])
8191 DONE;
8192 else
8193 FAIL;
8194 }")
8195 \f
8196 ;; TImode is similar, except that we usually want to compute the address into
8197 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8198 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8199
8200 ;; We say that MQ is clobbered in the last alternative because the first
8201 ;; alternative would never get used otherwise since it would need a reload
8202 ;; while the 2nd alternative would not. We put memory cases first so they
8203 ;; are preferred. Otherwise, we'd try to reload the output instead of
8204 ;; giving the SCRATCH mq.
8205
8206 (define_insn "*movti_power"
8207 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8208 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8209 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8210 "TARGET_POWER && ! TARGET_POWERPC64
8211 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8212 "*
8213 {
8214 switch (which_alternative)
8215 {
8216 default:
8217 gcc_unreachable ();
8218
8219 case 0:
8220 if (TARGET_STRING)
8221 return \"{stsi|stswi} %1,%P0,16\";
8222 case 1:
8223 case 2:
8224 return \"#\";
8225 case 3:
8226 /* If the address is not used in the output, we can use lsi. Otherwise,
8227 fall through to generating four loads. */
8228 if (TARGET_STRING
8229 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8230 return \"{lsi|lswi} %0,%P1,16\";
8231 /* ... fall through ... */
8232 case 4:
8233 case 5:
8234 return \"#\";
8235 }
8236 }"
8237 [(set_attr "type" "store,store,*,load,load,*")])
8238
8239 (define_insn "*movti_string"
8240 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8241 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8242 "! TARGET_POWER && ! TARGET_POWERPC64
8243 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8244 "*
8245 {
8246 switch (which_alternative)
8247 {
8248 default:
8249 gcc_unreachable ();
8250 case 0:
8251 if (TARGET_STRING)
8252 return \"{stsi|stswi} %1,%P0,16\";
8253 case 1:
8254 case 2:
8255 return \"#\";
8256 case 3:
8257 /* If the address is not used in the output, we can use lsi. Otherwise,
8258 fall through to generating four loads. */
8259 if (TARGET_STRING
8260 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8261 return \"{lsi|lswi} %0,%P1,16\";
8262 /* ... fall through ... */
8263 case 4:
8264 case 5:
8265 return \"#\";
8266 }
8267 }"
8268 [(set_attr "type" "store,store,*,load,load,*")])
8269
8270 (define_insn "*movti_ppc64"
8271 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8272 (match_operand:TI 1 "input_operand" "r,r,m"))]
8273 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8274 || gpc_reg_operand (operands[1], TImode))"
8275 "#"
8276 [(set_attr "type" "*,load,store")])
8277
8278 (define_split
8279 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8280 (match_operand:TI 1 "const_double_operand" ""))]
8281 "TARGET_POWERPC64"
8282 [(set (match_dup 2) (match_dup 4))
8283 (set (match_dup 3) (match_dup 5))]
8284 "
8285 {
8286 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8287 TImode);
8288 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8289 TImode);
8290 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8291 {
8292 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8293 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8294 }
8295 else if (GET_CODE (operands[1]) == CONST_INT)
8296 {
8297 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8298 operands[5] = operands[1];
8299 }
8300 else
8301 FAIL;
8302 }")
8303
8304 (define_split
8305 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8306 (match_operand:TI 1 "input_operand" ""))]
8307 "reload_completed
8308 && gpr_or_gpr_p (operands[0], operands[1])"
8309 [(pc)]
8310 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8311 \f
8312 (define_expand "load_multiple"
8313 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8314 (match_operand:SI 1 "" ""))
8315 (use (match_operand:SI 2 "" ""))])]
8316 "TARGET_STRING && !TARGET_POWERPC64"
8317 "
8318 {
8319 int regno;
8320 int count;
8321 rtx op1;
8322 int i;
8323
8324 /* Support only loading a constant number of fixed-point registers from
8325 memory and only bother with this if more than two; the machine
8326 doesn't support more than eight. */
8327 if (GET_CODE (operands[2]) != CONST_INT
8328 || INTVAL (operands[2]) <= 2
8329 || INTVAL (operands[2]) > 8
8330 || GET_CODE (operands[1]) != MEM
8331 || GET_CODE (operands[0]) != REG
8332 || REGNO (operands[0]) >= 32)
8333 FAIL;
8334
8335 count = INTVAL (operands[2]);
8336 regno = REGNO (operands[0]);
8337
8338 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8339 op1 = replace_equiv_address (operands[1],
8340 force_reg (SImode, XEXP (operands[1], 0)));
8341
8342 for (i = 0; i < count; i++)
8343 XVECEXP (operands[3], 0, i)
8344 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8345 adjust_address_nv (op1, SImode, i * 4));
8346 }")
8347
8348 (define_insn "*ldmsi8"
8349 [(match_parallel 0 "load_multiple_operation"
8350 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8351 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8352 (set (match_operand:SI 3 "gpc_reg_operand" "")
8353 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8354 (set (match_operand:SI 4 "gpc_reg_operand" "")
8355 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8356 (set (match_operand:SI 5 "gpc_reg_operand" "")
8357 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8358 (set (match_operand:SI 6 "gpc_reg_operand" "")
8359 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8360 (set (match_operand:SI 7 "gpc_reg_operand" "")
8361 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8362 (set (match_operand:SI 8 "gpc_reg_operand" "")
8363 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8364 (set (match_operand:SI 9 "gpc_reg_operand" "")
8365 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8366 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8367 "*
8368 { return rs6000_output_load_multiple (operands); }"
8369 [(set_attr "type" "load")
8370 (set_attr "length" "32")])
8371
8372 (define_insn "*ldmsi7"
8373 [(match_parallel 0 "load_multiple_operation"
8374 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8375 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8376 (set (match_operand:SI 3 "gpc_reg_operand" "")
8377 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8378 (set (match_operand:SI 4 "gpc_reg_operand" "")
8379 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8380 (set (match_operand:SI 5 "gpc_reg_operand" "")
8381 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8382 (set (match_operand:SI 6 "gpc_reg_operand" "")
8383 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8384 (set (match_operand:SI 7 "gpc_reg_operand" "")
8385 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8386 (set (match_operand:SI 8 "gpc_reg_operand" "")
8387 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8388 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8389 "*
8390 { return rs6000_output_load_multiple (operands); }"
8391 [(set_attr "type" "load")
8392 (set_attr "length" "32")])
8393
8394 (define_insn "*ldmsi6"
8395 [(match_parallel 0 "load_multiple_operation"
8396 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8397 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8398 (set (match_operand:SI 3 "gpc_reg_operand" "")
8399 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8400 (set (match_operand:SI 4 "gpc_reg_operand" "")
8401 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8402 (set (match_operand:SI 5 "gpc_reg_operand" "")
8403 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8404 (set (match_operand:SI 6 "gpc_reg_operand" "")
8405 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8406 (set (match_operand:SI 7 "gpc_reg_operand" "")
8407 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8408 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8409 "*
8410 { return rs6000_output_load_multiple (operands); }"
8411 [(set_attr "type" "load")
8412 (set_attr "length" "32")])
8413
8414 (define_insn "*ldmsi5"
8415 [(match_parallel 0 "load_multiple_operation"
8416 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8417 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8418 (set (match_operand:SI 3 "gpc_reg_operand" "")
8419 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8420 (set (match_operand:SI 4 "gpc_reg_operand" "")
8421 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8422 (set (match_operand:SI 5 "gpc_reg_operand" "")
8423 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8424 (set (match_operand:SI 6 "gpc_reg_operand" "")
8425 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8426 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8427 "*
8428 { return rs6000_output_load_multiple (operands); }"
8429 [(set_attr "type" "load")
8430 (set_attr "length" "32")])
8431
8432 (define_insn "*ldmsi4"
8433 [(match_parallel 0 "load_multiple_operation"
8434 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8435 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8436 (set (match_operand:SI 3 "gpc_reg_operand" "")
8437 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8438 (set (match_operand:SI 4 "gpc_reg_operand" "")
8439 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8440 (set (match_operand:SI 5 "gpc_reg_operand" "")
8441 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8442 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8443 "*
8444 { return rs6000_output_load_multiple (operands); }"
8445 [(set_attr "type" "load")
8446 (set_attr "length" "32")])
8447
8448 (define_insn "*ldmsi3"
8449 [(match_parallel 0 "load_multiple_operation"
8450 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8451 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8452 (set (match_operand:SI 3 "gpc_reg_operand" "")
8453 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8454 (set (match_operand:SI 4 "gpc_reg_operand" "")
8455 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8456 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8457 "*
8458 { return rs6000_output_load_multiple (operands); }"
8459 [(set_attr "type" "load")
8460 (set_attr "length" "32")])
8461
8462 (define_expand "store_multiple"
8463 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8464 (match_operand:SI 1 "" ""))
8465 (clobber (scratch:SI))
8466 (use (match_operand:SI 2 "" ""))])]
8467 "TARGET_STRING && !TARGET_POWERPC64"
8468 "
8469 {
8470 int regno;
8471 int count;
8472 rtx to;
8473 rtx op0;
8474 int i;
8475
8476 /* Support only storing a constant number of fixed-point registers to
8477 memory and only bother with this if more than two; the machine
8478 doesn't support more than eight. */
8479 if (GET_CODE (operands[2]) != CONST_INT
8480 || INTVAL (operands[2]) <= 2
8481 || INTVAL (operands[2]) > 8
8482 || GET_CODE (operands[0]) != MEM
8483 || GET_CODE (operands[1]) != REG
8484 || REGNO (operands[1]) >= 32)
8485 FAIL;
8486
8487 count = INTVAL (operands[2]);
8488 regno = REGNO (operands[1]);
8489
8490 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8491 to = force_reg (SImode, XEXP (operands[0], 0));
8492 op0 = replace_equiv_address (operands[0], to);
8493
8494 XVECEXP (operands[3], 0, 0)
8495 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8496 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8497 gen_rtx_SCRATCH (SImode));
8498
8499 for (i = 1; i < count; i++)
8500 XVECEXP (operands[3], 0, i + 1)
8501 = gen_rtx_SET (VOIDmode,
8502 adjust_address_nv (op0, SImode, i * 4),
8503 gen_rtx_REG (SImode, regno + i));
8504 }")
8505
8506 (define_insn "*store_multiple_power"
8507 [(match_parallel 0 "store_multiple_operation"
8508 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8509 (match_operand:SI 2 "gpc_reg_operand" "r"))
8510 (clobber (match_scratch:SI 3 "=q"))])]
8511 "TARGET_STRING && TARGET_POWER"
8512 "{stsi|stswi} %2,%P1,%O0"
8513 [(set_attr "type" "store")])
8514
8515 (define_insn "*stmsi8"
8516 [(match_parallel 0 "store_multiple_operation"
8517 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8518 (match_operand:SI 2 "gpc_reg_operand" "r"))
8519 (clobber (match_scratch:SI 3 "X"))
8520 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8521 (match_operand:SI 4 "gpc_reg_operand" "r"))
8522 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8523 (match_operand:SI 5 "gpc_reg_operand" "r"))
8524 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8525 (match_operand:SI 6 "gpc_reg_operand" "r"))
8526 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8527 (match_operand:SI 7 "gpc_reg_operand" "r"))
8528 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8529 (match_operand:SI 8 "gpc_reg_operand" "r"))
8530 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8531 (match_operand:SI 9 "gpc_reg_operand" "r"))
8532 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8533 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8534 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8535 "{stsi|stswi} %2,%1,%O0"
8536 [(set_attr "type" "store")])
8537
8538 (define_insn "*stmsi7"
8539 [(match_parallel 0 "store_multiple_operation"
8540 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8541 (match_operand:SI 2 "gpc_reg_operand" "r"))
8542 (clobber (match_scratch:SI 3 "X"))
8543 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8544 (match_operand:SI 4 "gpc_reg_operand" "r"))
8545 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8546 (match_operand:SI 5 "gpc_reg_operand" "r"))
8547 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8548 (match_operand:SI 6 "gpc_reg_operand" "r"))
8549 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8550 (match_operand:SI 7 "gpc_reg_operand" "r"))
8551 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8552 (match_operand:SI 8 "gpc_reg_operand" "r"))
8553 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8554 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8555 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8556 "{stsi|stswi} %2,%1,%O0"
8557 [(set_attr "type" "store")])
8558
8559 (define_insn "*stmsi6"
8560 [(match_parallel 0 "store_multiple_operation"
8561 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8562 (match_operand:SI 2 "gpc_reg_operand" "r"))
8563 (clobber (match_scratch:SI 3 "X"))
8564 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8565 (match_operand:SI 4 "gpc_reg_operand" "r"))
8566 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8567 (match_operand:SI 5 "gpc_reg_operand" "r"))
8568 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8569 (match_operand:SI 6 "gpc_reg_operand" "r"))
8570 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8571 (match_operand:SI 7 "gpc_reg_operand" "r"))
8572 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8573 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8574 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8575 "{stsi|stswi} %2,%1,%O0"
8576 [(set_attr "type" "store")])
8577
8578 (define_insn "*stmsi5"
8579 [(match_parallel 0 "store_multiple_operation"
8580 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8581 (match_operand:SI 2 "gpc_reg_operand" "r"))
8582 (clobber (match_scratch:SI 3 "X"))
8583 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8584 (match_operand:SI 4 "gpc_reg_operand" "r"))
8585 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8586 (match_operand:SI 5 "gpc_reg_operand" "r"))
8587 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8588 (match_operand:SI 6 "gpc_reg_operand" "r"))
8589 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8590 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8591 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8592 "{stsi|stswi} %2,%1,%O0"
8593 [(set_attr "type" "store")])
8594
8595 (define_insn "*stmsi4"
8596 [(match_parallel 0 "store_multiple_operation"
8597 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8598 (match_operand:SI 2 "gpc_reg_operand" "r"))
8599 (clobber (match_scratch:SI 3 "X"))
8600 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8601 (match_operand:SI 4 "gpc_reg_operand" "r"))
8602 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8603 (match_operand:SI 5 "gpc_reg_operand" "r"))
8604 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8605 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8606 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8607 "{stsi|stswi} %2,%1,%O0"
8608 [(set_attr "type" "store")])
8609
8610 (define_insn "*stmsi3"
8611 [(match_parallel 0 "store_multiple_operation"
8612 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8613 (match_operand:SI 2 "gpc_reg_operand" "r"))
8614 (clobber (match_scratch:SI 3 "X"))
8615 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8616 (match_operand:SI 4 "gpc_reg_operand" "r"))
8617 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8618 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8619 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8620 "{stsi|stswi} %2,%1,%O0"
8621 [(set_attr "type" "store")])
8622 \f
8623 (define_expand "setmemsi"
8624 [(parallel [(set (match_operand:BLK 0 "" "")
8625 (match_operand 2 "const_int_operand" ""))
8626 (use (match_operand:SI 1 "" ""))
8627 (use (match_operand:SI 3 "" ""))])]
8628 ""
8629 "
8630 {
8631 /* If value to set is not zero, use the library routine. */
8632 if (operands[2] != const0_rtx)
8633 FAIL;
8634
8635 if (expand_block_clear (operands))
8636 DONE;
8637 else
8638 FAIL;
8639 }")
8640
8641 ;; String/block move insn.
8642 ;; Argument 0 is the destination
8643 ;; Argument 1 is the source
8644 ;; Argument 2 is the length
8645 ;; Argument 3 is the alignment
8646
8647 (define_expand "movmemsi"
8648 [(parallel [(set (match_operand:BLK 0 "" "")
8649 (match_operand:BLK 1 "" ""))
8650 (use (match_operand:SI 2 "" ""))
8651 (use (match_operand:SI 3 "" ""))])]
8652 ""
8653 "
8654 {
8655 if (expand_block_move (operands))
8656 DONE;
8657 else
8658 FAIL;
8659 }")
8660
8661 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8662 ;; register allocator doesn't have a clue about allocating 8 word registers.
8663 ;; rD/rS = r5 is preferred, efficient form.
8664 (define_expand "movmemsi_8reg"
8665 [(parallel [(set (match_operand 0 "" "")
8666 (match_operand 1 "" ""))
8667 (use (match_operand 2 "" ""))
8668 (use (match_operand 3 "" ""))
8669 (clobber (reg:SI 5))
8670 (clobber (reg:SI 6))
8671 (clobber (reg:SI 7))
8672 (clobber (reg:SI 8))
8673 (clobber (reg:SI 9))
8674 (clobber (reg:SI 10))
8675 (clobber (reg:SI 11))
8676 (clobber (reg:SI 12))
8677 (clobber (match_scratch:SI 4 ""))])]
8678 "TARGET_STRING"
8679 "")
8680
8681 (define_insn ""
8682 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8683 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8684 (use (match_operand:SI 2 "immediate_operand" "i"))
8685 (use (match_operand:SI 3 "immediate_operand" "i"))
8686 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8687 (clobber (reg:SI 6))
8688 (clobber (reg:SI 7))
8689 (clobber (reg:SI 8))
8690 (clobber (reg:SI 9))
8691 (clobber (reg:SI 10))
8692 (clobber (reg:SI 11))
8693 (clobber (reg:SI 12))
8694 (clobber (match_scratch:SI 5 "=q"))]
8695 "TARGET_STRING && TARGET_POWER
8696 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8697 || INTVAL (operands[2]) == 0)
8698 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8699 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8700 && REGNO (operands[4]) == 5"
8701 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8702 [(set_attr "type" "load")
8703 (set_attr "length" "8")])
8704
8705 (define_insn ""
8706 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8707 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8708 (use (match_operand:SI 2 "immediate_operand" "i"))
8709 (use (match_operand:SI 3 "immediate_operand" "i"))
8710 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8711 (clobber (reg:SI 6))
8712 (clobber (reg:SI 7))
8713 (clobber (reg:SI 8))
8714 (clobber (reg:SI 9))
8715 (clobber (reg:SI 10))
8716 (clobber (reg:SI 11))
8717 (clobber (reg:SI 12))
8718 (clobber (match_scratch:SI 5 "X"))]
8719 "TARGET_STRING && ! TARGET_POWER
8720 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8721 || INTVAL (operands[2]) == 0)
8722 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8723 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8724 && REGNO (operands[4]) == 5"
8725 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8726 [(set_attr "type" "load")
8727 (set_attr "length" "8")])
8728
8729 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8730 ;; register allocator doesn't have a clue about allocating 6 word registers.
8731 ;; rD/rS = r5 is preferred, efficient form.
8732 (define_expand "movmemsi_6reg"
8733 [(parallel [(set (match_operand 0 "" "")
8734 (match_operand 1 "" ""))
8735 (use (match_operand 2 "" ""))
8736 (use (match_operand 3 "" ""))
8737 (clobber (reg:SI 5))
8738 (clobber (reg:SI 6))
8739 (clobber (reg:SI 7))
8740 (clobber (reg:SI 8))
8741 (clobber (reg:SI 9))
8742 (clobber (reg:SI 10))
8743 (clobber (match_scratch:SI 4 ""))])]
8744 "TARGET_STRING"
8745 "")
8746
8747 (define_insn ""
8748 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8749 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8750 (use (match_operand:SI 2 "immediate_operand" "i"))
8751 (use (match_operand:SI 3 "immediate_operand" "i"))
8752 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8753 (clobber (reg:SI 6))
8754 (clobber (reg:SI 7))
8755 (clobber (reg:SI 8))
8756 (clobber (reg:SI 9))
8757 (clobber (reg:SI 10))
8758 (clobber (match_scratch:SI 5 "=q"))]
8759 "TARGET_STRING && TARGET_POWER
8760 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8761 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8762 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8763 && REGNO (operands[4]) == 5"
8764 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8765 [(set_attr "type" "load")
8766 (set_attr "length" "8")])
8767
8768 (define_insn ""
8769 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8770 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8771 (use (match_operand:SI 2 "immediate_operand" "i"))
8772 (use (match_operand:SI 3 "immediate_operand" "i"))
8773 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8774 (clobber (reg:SI 6))
8775 (clobber (reg:SI 7))
8776 (clobber (reg:SI 8))
8777 (clobber (reg:SI 9))
8778 (clobber (reg:SI 10))
8779 (clobber (match_scratch:SI 5 "X"))]
8780 "TARGET_STRING && ! TARGET_POWER
8781 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8782 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8783 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8784 && REGNO (operands[4]) == 5"
8785 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8786 [(set_attr "type" "load")
8787 (set_attr "length" "8")])
8788
8789 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8790 ;; problems with TImode.
8791 ;; rD/rS = r5 is preferred, efficient form.
8792 (define_expand "movmemsi_4reg"
8793 [(parallel [(set (match_operand 0 "" "")
8794 (match_operand 1 "" ""))
8795 (use (match_operand 2 "" ""))
8796 (use (match_operand 3 "" ""))
8797 (clobber (reg:SI 5))
8798 (clobber (reg:SI 6))
8799 (clobber (reg:SI 7))
8800 (clobber (reg:SI 8))
8801 (clobber (match_scratch:SI 4 ""))])]
8802 "TARGET_STRING"
8803 "")
8804
8805 (define_insn ""
8806 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8807 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8808 (use (match_operand:SI 2 "immediate_operand" "i"))
8809 (use (match_operand:SI 3 "immediate_operand" "i"))
8810 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8811 (clobber (reg:SI 6))
8812 (clobber (reg:SI 7))
8813 (clobber (reg:SI 8))
8814 (clobber (match_scratch:SI 5 "=q"))]
8815 "TARGET_STRING && TARGET_POWER
8816 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8817 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8818 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8819 && REGNO (operands[4]) == 5"
8820 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8821 [(set_attr "type" "load")
8822 (set_attr "length" "8")])
8823
8824 (define_insn ""
8825 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8826 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8827 (use (match_operand:SI 2 "immediate_operand" "i"))
8828 (use (match_operand:SI 3 "immediate_operand" "i"))
8829 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8830 (clobber (reg:SI 6))
8831 (clobber (reg:SI 7))
8832 (clobber (reg:SI 8))
8833 (clobber (match_scratch:SI 5 "X"))]
8834 "TARGET_STRING && ! TARGET_POWER
8835 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8836 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8837 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8838 && REGNO (operands[4]) == 5"
8839 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8840 [(set_attr "type" "load")
8841 (set_attr "length" "8")])
8842
8843 ;; Move up to 8 bytes at a time.
8844 (define_expand "movmemsi_2reg"
8845 [(parallel [(set (match_operand 0 "" "")
8846 (match_operand 1 "" ""))
8847 (use (match_operand 2 "" ""))
8848 (use (match_operand 3 "" ""))
8849 (clobber (match_scratch:DI 4 ""))
8850 (clobber (match_scratch:SI 5 ""))])]
8851 "TARGET_STRING && ! TARGET_POWERPC64"
8852 "")
8853
8854 (define_insn ""
8855 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8856 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8857 (use (match_operand:SI 2 "immediate_operand" "i"))
8858 (use (match_operand:SI 3 "immediate_operand" "i"))
8859 (clobber (match_scratch:DI 4 "=&r"))
8860 (clobber (match_scratch:SI 5 "=q"))]
8861 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8862 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8863 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8864 [(set_attr "type" "load")
8865 (set_attr "length" "8")])
8866
8867 (define_insn ""
8868 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8869 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8870 (use (match_operand:SI 2 "immediate_operand" "i"))
8871 (use (match_operand:SI 3 "immediate_operand" "i"))
8872 (clobber (match_scratch:DI 4 "=&r"))
8873 (clobber (match_scratch:SI 5 "X"))]
8874 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8875 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8876 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8877 [(set_attr "type" "load")
8878 (set_attr "length" "8")])
8879
8880 ;; Move up to 4 bytes at a time.
8881 (define_expand "movmemsi_1reg"
8882 [(parallel [(set (match_operand 0 "" "")
8883 (match_operand 1 "" ""))
8884 (use (match_operand 2 "" ""))
8885 (use (match_operand 3 "" ""))
8886 (clobber (match_scratch:SI 4 ""))
8887 (clobber (match_scratch:SI 5 ""))])]
8888 "TARGET_STRING"
8889 "")
8890
8891 (define_insn ""
8892 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8893 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8894 (use (match_operand:SI 2 "immediate_operand" "i"))
8895 (use (match_operand:SI 3 "immediate_operand" "i"))
8896 (clobber (match_scratch:SI 4 "=&r"))
8897 (clobber (match_scratch:SI 5 "=q"))]
8898 "TARGET_STRING && TARGET_POWER
8899 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8900 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8901 [(set_attr "type" "load")
8902 (set_attr "length" "8")])
8903
8904 (define_insn ""
8905 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8906 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8907 (use (match_operand:SI 2 "immediate_operand" "i"))
8908 (use (match_operand:SI 3 "immediate_operand" "i"))
8909 (clobber (match_scratch:SI 4 "=&r"))
8910 (clobber (match_scratch:SI 5 "X"))]
8911 "TARGET_STRING && ! TARGET_POWER
8912 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8913 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8914 [(set_attr "type" "load")
8915 (set_attr "length" "8")])
8916 \f
8917 ;; Define insns that do load or store with update. Some of these we can
8918 ;; get by using pre-decrement or pre-increment, but the hardware can also
8919 ;; do cases where the increment is not the size of the object.
8920 ;;
8921 ;; In all these cases, we use operands 0 and 1 for the register being
8922 ;; incremented because those are the operands that local-alloc will
8923 ;; tie and these are the pair most likely to be tieable (and the ones
8924 ;; that will benefit the most).
8925
8926 (define_insn "*movdi_update1"
8927 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8928 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8929 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8930 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8931 (plus:DI (match_dup 1) (match_dup 2)))]
8932 "TARGET_POWERPC64 && TARGET_UPDATE"
8933 "@
8934 ldux %3,%0,%2
8935 ldu %3,%2(%0)"
8936 [(set_attr "type" "load_ux,load_u")])
8937
8938 (define_insn "movdi_<mode>_update"
8939 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8940 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8941 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8942 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8943 (plus:P (match_dup 1) (match_dup 2)))]
8944 "TARGET_POWERPC64 && TARGET_UPDATE"
8945 "@
8946 stdux %3,%0,%2
8947 stdu %3,%2(%0)"
8948 [(set_attr "type" "store_ux,store_u")])
8949
8950 (define_insn "*movsi_update1"
8951 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8952 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8953 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8954 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8955 (plus:SI (match_dup 1) (match_dup 2)))]
8956 "TARGET_UPDATE"
8957 "@
8958 {lux|lwzux} %3,%0,%2
8959 {lu|lwzu} %3,%2(%0)"
8960 [(set_attr "type" "load_ux,load_u")])
8961
8962 (define_insn "*movsi_update2"
8963 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8964 (sign_extend:DI
8965 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8966 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8967 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8968 (plus:DI (match_dup 1) (match_dup 2)))]
8969 "TARGET_POWERPC64"
8970 "lwaux %3,%0,%2"
8971 [(set_attr "type" "load_ext_ux")])
8972
8973 (define_insn "movsi_update"
8974 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8975 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8976 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8977 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8978 (plus:SI (match_dup 1) (match_dup 2)))]
8979 "TARGET_UPDATE"
8980 "@
8981 {stux|stwux} %3,%0,%2
8982 {stu|stwu} %3,%2(%0)"
8983 [(set_attr "type" "store_ux,store_u")])
8984
8985 (define_insn "*movhi_update1"
8986 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8987 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8988 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8989 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8990 (plus:SI (match_dup 1) (match_dup 2)))]
8991 "TARGET_UPDATE"
8992 "@
8993 lhzux %3,%0,%2
8994 lhzu %3,%2(%0)"
8995 [(set_attr "type" "load_ux,load_u")])
8996
8997 (define_insn "*movhi_update2"
8998 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8999 (zero_extend:SI
9000 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9001 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9002 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9003 (plus:SI (match_dup 1) (match_dup 2)))]
9004 "TARGET_UPDATE"
9005 "@
9006 lhzux %3,%0,%2
9007 lhzu %3,%2(%0)"
9008 [(set_attr "type" "load_ux,load_u")])
9009
9010 (define_insn "*movhi_update3"
9011 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9012 (sign_extend:SI
9013 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9014 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9015 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9016 (plus:SI (match_dup 1) (match_dup 2)))]
9017 "TARGET_UPDATE"
9018 "@
9019 lhaux %3,%0,%2
9020 lhau %3,%2(%0)"
9021 [(set_attr "type" "load_ext_ux,load_ext_u")])
9022
9023 (define_insn "*movhi_update4"
9024 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9025 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9026 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9027 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9028 (plus:SI (match_dup 1) (match_dup 2)))]
9029 "TARGET_UPDATE"
9030 "@
9031 sthux %3,%0,%2
9032 sthu %3,%2(%0)"
9033 [(set_attr "type" "store_ux,store_u")])
9034
9035 (define_insn "*movqi_update1"
9036 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9037 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9038 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9039 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9040 (plus:SI (match_dup 1) (match_dup 2)))]
9041 "TARGET_UPDATE"
9042 "@
9043 lbzux %3,%0,%2
9044 lbzu %3,%2(%0)"
9045 [(set_attr "type" "load_ux,load_u")])
9046
9047 (define_insn "*movqi_update2"
9048 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9049 (zero_extend:SI
9050 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9051 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9052 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9053 (plus:SI (match_dup 1) (match_dup 2)))]
9054 "TARGET_UPDATE"
9055 "@
9056 lbzux %3,%0,%2
9057 lbzu %3,%2(%0)"
9058 [(set_attr "type" "load_ux,load_u")])
9059
9060 (define_insn "*movqi_update3"
9061 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9062 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9063 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9064 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9065 (plus:SI (match_dup 1) (match_dup 2)))]
9066 "TARGET_UPDATE"
9067 "@
9068 stbux %3,%0,%2
9069 stbu %3,%2(%0)"
9070 [(set_attr "type" "store_ux,store_u")])
9071
9072 (define_insn "*movsf_update1"
9073 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9074 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9075 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9076 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9077 (plus:SI (match_dup 1) (match_dup 2)))]
9078 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9079 "@
9080 lfsux %3,%0,%2
9081 lfsu %3,%2(%0)"
9082 [(set_attr "type" "fpload_ux,fpload_u")])
9083
9084 (define_insn "*movsf_update2"
9085 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9086 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9087 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9088 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9089 (plus:SI (match_dup 1) (match_dup 2)))]
9090 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9091 "@
9092 stfsux %3,%0,%2
9093 stfsu %3,%2(%0)"
9094 [(set_attr "type" "fpstore_ux,fpstore_u")])
9095
9096 (define_insn "*movsf_update3"
9097 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9098 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9099 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9100 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9101 (plus:SI (match_dup 1) (match_dup 2)))]
9102 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9103 "@
9104 {lux|lwzux} %3,%0,%2
9105 {lu|lwzu} %3,%2(%0)"
9106 [(set_attr "type" "load_ux,load_u")])
9107
9108 (define_insn "*movsf_update4"
9109 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9110 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9111 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9112 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9113 (plus:SI (match_dup 1) (match_dup 2)))]
9114 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9115 "@
9116 {stux|stwux} %3,%0,%2
9117 {stu|stwu} %3,%2(%0)"
9118 [(set_attr "type" "store_ux,store_u")])
9119
9120 (define_insn "*movdf_update1"
9121 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9122 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9123 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9124 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9125 (plus:SI (match_dup 1) (match_dup 2)))]
9126 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9127 "@
9128 lfdux %3,%0,%2
9129 lfdu %3,%2(%0)"
9130 [(set_attr "type" "fpload_ux,fpload_u")])
9131
9132 (define_insn "*movdf_update2"
9133 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9134 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9135 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9136 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9137 (plus:SI (match_dup 1) (match_dup 2)))]
9138 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9139 "@
9140 stfdux %3,%0,%2
9141 stfdu %3,%2(%0)"
9142 [(set_attr "type" "fpstore_ux,fpstore_u")])
9143
9144 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9145
9146 (define_insn "*lfq_power2"
9147 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9148 (match_operand:V2DF 1 "memory_operand" ""))]
9149 "TARGET_POWER2
9150 && TARGET_HARD_FLOAT && TARGET_FPRS"
9151 "lfq%U1%X1 %0,%1")
9152
9153 (define_peephole2
9154 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9155 (match_operand:DF 1 "memory_operand" ""))
9156 (set (match_operand:DF 2 "gpc_reg_operand" "")
9157 (match_operand:DF 3 "memory_operand" ""))]
9158 "TARGET_POWER2
9159 && TARGET_HARD_FLOAT && TARGET_FPRS
9160 && registers_ok_for_quad_peep (operands[0], operands[2])
9161 && mems_ok_for_quad_peep (operands[1], operands[3])"
9162 [(set (match_dup 0)
9163 (match_dup 1))]
9164 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9165 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9166
9167 (define_insn "*stfq_power2"
9168 [(set (match_operand:V2DF 0 "memory_operand" "")
9169 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9170 "TARGET_POWER2
9171 && TARGET_HARD_FLOAT && TARGET_FPRS"
9172 "stfq%U0%X0 %1,%0")
9173
9174
9175 (define_peephole2
9176 [(set (match_operand:DF 0 "memory_operand" "")
9177 (match_operand:DF 1 "gpc_reg_operand" ""))
9178 (set (match_operand:DF 2 "memory_operand" "")
9179 (match_operand:DF 3 "gpc_reg_operand" ""))]
9180 "TARGET_POWER2
9181 && TARGET_HARD_FLOAT && TARGET_FPRS
9182 && registers_ok_for_quad_peep (operands[1], operands[3])
9183 && mems_ok_for_quad_peep (operands[0], operands[2])"
9184 [(set (match_dup 0)
9185 (match_dup 1))]
9186 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9187 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9188
9189 ;; after inserting conditional returns we can sometimes have
9190 ;; unnecessary register moves. Unfortunately we cannot have a
9191 ;; modeless peephole here, because some single SImode sets have early
9192 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9193 ;; sequences, using get_attr_length here will smash the operands
9194 ;; array. Neither is there an early_cobbler_p predicate.
9195 (define_peephole2
9196 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9197 (match_operand:DF 1 "any_operand" ""))
9198 (set (match_operand:DF 2 "gpc_reg_operand" "")
9199 (match_dup 0))]
9200 "peep2_reg_dead_p (2, operands[0])"
9201 [(set (match_dup 2) (match_dup 1))])
9202
9203 (define_peephole2
9204 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9205 (match_operand:SF 1 "any_operand" ""))
9206 (set (match_operand:SF 2 "gpc_reg_operand" "")
9207 (match_dup 0))]
9208 "peep2_reg_dead_p (2, operands[0])"
9209 [(set (match_dup 2) (match_dup 1))])
9210
9211 \f
9212 ;; TLS support.
9213
9214 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9215 (define_insn "tls_gd_32"
9216 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9217 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9218 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9219 UNSPEC_TLSGD))]
9220 "HAVE_AS_TLS && !TARGET_64BIT"
9221 "addi %0,%1,%2@got@tlsgd")
9222
9223 (define_insn "tls_gd_64"
9224 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9225 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9226 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9227 UNSPEC_TLSGD))]
9228 "HAVE_AS_TLS && TARGET_64BIT"
9229 "addi %0,%1,%2@got@tlsgd")
9230
9231 (define_insn "tls_ld_32"
9232 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9233 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9234 UNSPEC_TLSLD))]
9235 "HAVE_AS_TLS && !TARGET_64BIT"
9236 "addi %0,%1,%&@got@tlsld")
9237
9238 (define_insn "tls_ld_64"
9239 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9240 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9241 UNSPEC_TLSLD))]
9242 "HAVE_AS_TLS && TARGET_64BIT"
9243 "addi %0,%1,%&@got@tlsld")
9244
9245 (define_insn "tls_dtprel_32"
9246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9247 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9248 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9249 UNSPEC_TLSDTPREL))]
9250 "HAVE_AS_TLS && !TARGET_64BIT"
9251 "addi %0,%1,%2@dtprel")
9252
9253 (define_insn "tls_dtprel_64"
9254 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9255 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9256 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9257 UNSPEC_TLSDTPREL))]
9258 "HAVE_AS_TLS && TARGET_64BIT"
9259 "addi %0,%1,%2@dtprel")
9260
9261 (define_insn "tls_dtprel_ha_32"
9262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9263 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9264 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9265 UNSPEC_TLSDTPRELHA))]
9266 "HAVE_AS_TLS && !TARGET_64BIT"
9267 "addis %0,%1,%2@dtprel@ha")
9268
9269 (define_insn "tls_dtprel_ha_64"
9270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9271 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9272 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9273 UNSPEC_TLSDTPRELHA))]
9274 "HAVE_AS_TLS && TARGET_64BIT"
9275 "addis %0,%1,%2@dtprel@ha")
9276
9277 (define_insn "tls_dtprel_lo_32"
9278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9279 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9280 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9281 UNSPEC_TLSDTPRELLO))]
9282 "HAVE_AS_TLS && !TARGET_64BIT"
9283 "addi %0,%1,%2@dtprel@l")
9284
9285 (define_insn "tls_dtprel_lo_64"
9286 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9287 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9288 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9289 UNSPEC_TLSDTPRELLO))]
9290 "HAVE_AS_TLS && TARGET_64BIT"
9291 "addi %0,%1,%2@dtprel@l")
9292
9293 (define_insn "tls_got_dtprel_32"
9294 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9295 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9296 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9297 UNSPEC_TLSGOTDTPREL))]
9298 "HAVE_AS_TLS && !TARGET_64BIT"
9299 "lwz %0,%2@got@dtprel(%1)")
9300
9301 (define_insn "tls_got_dtprel_64"
9302 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9303 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9304 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9305 UNSPEC_TLSGOTDTPREL))]
9306 "HAVE_AS_TLS && TARGET_64BIT"
9307 "ld %0,%2@got@dtprel(%1)")
9308
9309 (define_insn "tls_tprel_32"
9310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9311 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9312 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9313 UNSPEC_TLSTPREL))]
9314 "HAVE_AS_TLS && !TARGET_64BIT"
9315 "addi %0,%1,%2@tprel")
9316
9317 (define_insn "tls_tprel_64"
9318 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9319 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9320 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9321 UNSPEC_TLSTPREL))]
9322 "HAVE_AS_TLS && TARGET_64BIT"
9323 "addi %0,%1,%2@tprel")
9324
9325 (define_insn "tls_tprel_ha_32"
9326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9327 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9328 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9329 UNSPEC_TLSTPRELHA))]
9330 "HAVE_AS_TLS && !TARGET_64BIT"
9331 "addis %0,%1,%2@tprel@ha")
9332
9333 (define_insn "tls_tprel_ha_64"
9334 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9335 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9336 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9337 UNSPEC_TLSTPRELHA))]
9338 "HAVE_AS_TLS && TARGET_64BIT"
9339 "addis %0,%1,%2@tprel@ha")
9340
9341 (define_insn "tls_tprel_lo_32"
9342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9343 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9344 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9345 UNSPEC_TLSTPRELLO))]
9346 "HAVE_AS_TLS && !TARGET_64BIT"
9347 "addi %0,%1,%2@tprel@l")
9348
9349 (define_insn "tls_tprel_lo_64"
9350 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9351 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9352 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9353 UNSPEC_TLSTPRELLO))]
9354 "HAVE_AS_TLS && TARGET_64BIT"
9355 "addi %0,%1,%2@tprel@l")
9356
9357 ;; "b" output constraint here and on tls_tls input to support linker tls
9358 ;; optimization. The linker may edit the instructions emitted by a
9359 ;; tls_got_tprel/tls_tls pair to addis,addi.
9360 (define_insn "tls_got_tprel_32"
9361 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9362 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9363 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9364 UNSPEC_TLSGOTTPREL))]
9365 "HAVE_AS_TLS && !TARGET_64BIT"
9366 "lwz %0,%2@got@tprel(%1)")
9367
9368 (define_insn "tls_got_tprel_64"
9369 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9370 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9371 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9372 UNSPEC_TLSGOTTPREL))]
9373 "HAVE_AS_TLS && TARGET_64BIT"
9374 "ld %0,%2@got@tprel(%1)")
9375
9376 (define_insn "tls_tls_32"
9377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9378 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9379 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9380 UNSPEC_TLSTLS))]
9381 "HAVE_AS_TLS && !TARGET_64BIT"
9382 "add %0,%1,%2@tls")
9383
9384 (define_insn "tls_tls_64"
9385 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9386 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9387 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9388 UNSPEC_TLSTLS))]
9389 "HAVE_AS_TLS && TARGET_64BIT"
9390 "add %0,%1,%2@tls")
9391 \f
9392 ;; Next come insns related to the calling sequence.
9393 ;;
9394 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9395 ;; We move the back-chain and decrement the stack pointer.
9396
9397 (define_expand "allocate_stack"
9398 [(set (match_operand 0 "gpc_reg_operand" "=r")
9399 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9400 (set (reg 1)
9401 (minus (reg 1) (match_dup 1)))]
9402 ""
9403 "
9404 { rtx chain = gen_reg_rtx (Pmode);
9405 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9406 rtx neg_op0;
9407
9408 emit_move_insn (chain, stack_bot);
9409
9410 /* Check stack bounds if necessary. */
9411 if (current_function_limit_stack)
9412 {
9413 rtx available;
9414 available = expand_binop (Pmode, sub_optab,
9415 stack_pointer_rtx, stack_limit_rtx,
9416 NULL_RTX, 1, OPTAB_WIDEN);
9417 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9418 }
9419
9420 if (GET_CODE (operands[1]) != CONST_INT
9421 || INTVAL (operands[1]) < -32767
9422 || INTVAL (operands[1]) > 32768)
9423 {
9424 neg_op0 = gen_reg_rtx (Pmode);
9425 if (TARGET_32BIT)
9426 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9427 else
9428 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9429 }
9430 else
9431 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9432
9433 if (TARGET_UPDATE)
9434 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9435 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9436
9437 else
9438 {
9439 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9440 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9441 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9442 }
9443
9444 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9445 DONE;
9446 }")
9447
9448 ;; These patterns say how to save and restore the stack pointer. We need not
9449 ;; save the stack pointer at function level since we are careful to
9450 ;; preserve the backchain. At block level, we have to restore the backchain
9451 ;; when we restore the stack pointer.
9452 ;;
9453 ;; For nonlocal gotos, we must save both the stack pointer and its
9454 ;; backchain and restore both. Note that in the nonlocal case, the
9455 ;; save area is a memory location.
9456
9457 (define_expand "save_stack_function"
9458 [(match_operand 0 "any_operand" "")
9459 (match_operand 1 "any_operand" "")]
9460 ""
9461 "DONE;")
9462
9463 (define_expand "restore_stack_function"
9464 [(match_operand 0 "any_operand" "")
9465 (match_operand 1 "any_operand" "")]
9466 ""
9467 "DONE;")
9468
9469 (define_expand "restore_stack_block"
9470 [(use (match_operand 0 "register_operand" ""))
9471 (set (match_dup 2) (match_dup 3))
9472 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9473 (set (match_dup 3) (match_dup 2))]
9474 ""
9475 "
9476 {
9477 operands[2] = gen_reg_rtx (Pmode);
9478 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9479 }")
9480
9481 (define_expand "save_stack_nonlocal"
9482 [(match_operand 0 "memory_operand" "")
9483 (match_operand 1 "register_operand" "")]
9484 ""
9485 "
9486 {
9487 rtx temp = gen_reg_rtx (Pmode);
9488 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9489
9490 /* Copy the backchain to the first word, sp to the second. */
9491 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9492 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9493 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9494 operands[1]);
9495 DONE;
9496 }")
9497
9498 (define_expand "restore_stack_nonlocal"
9499 [(match_operand 0 "register_operand" "")
9500 (match_operand 1 "memory_operand" "")]
9501 ""
9502 "
9503 {
9504 rtx temp = gen_reg_rtx (Pmode);
9505 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9506
9507 /* Restore the backchain from the first word, sp from the second. */
9508 emit_move_insn (temp,
9509 adjust_address_nv (operands[1], Pmode, 0));
9510 emit_move_insn (operands[0],
9511 adjust_address_nv (operands[1], Pmode, units_per_word));
9512 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9513 DONE;
9514 }")
9515 \f
9516 ;; TOC register handling.
9517
9518 ;; Code to initialize the TOC register...
9519
9520 (define_insn "load_toc_aix_si"
9521 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9522 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9523 (use (reg:SI 2))])]
9524 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9525 "*
9526 {
9527 char buf[30];
9528 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9529 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9530 operands[2] = gen_rtx_REG (Pmode, 2);
9531 return \"{l|lwz} %0,%1(%2)\";
9532 }"
9533 [(set_attr "type" "load")])
9534
9535 (define_insn "load_toc_aix_di"
9536 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9537 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9538 (use (reg:DI 2))])]
9539 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9540 "*
9541 {
9542 char buf[30];
9543 #ifdef TARGET_RELOCATABLE
9544 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9545 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9546 #else
9547 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9548 #endif
9549 if (TARGET_ELF)
9550 strcat (buf, \"@toc\");
9551 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9552 operands[2] = gen_rtx_REG (Pmode, 2);
9553 return \"ld %0,%1(%2)\";
9554 }"
9555 [(set_attr "type" "load")])
9556
9557 (define_insn "load_toc_v4_pic_si"
9558 [(set (match_operand:SI 0 "register_operand" "=l")
9559 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9560 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9561 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9562 [(set_attr "type" "branch")
9563 (set_attr "length" "4")])
9564
9565 (define_insn "load_toc_v4_PIC_1"
9566 [(set (match_operand:SI 0 "register_operand" "=l")
9567 (match_operand:SI 1 "immediate_operand" "s"))
9568 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9569 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9570 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9571 "bcl 20,31,%1\\n%1:"
9572 [(set_attr "type" "branch")
9573 (set_attr "length" "4")])
9574
9575 (define_insn "load_toc_v4_PIC_1b"
9576 [(set (match_operand:SI 0 "register_operand" "=l")
9577 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9578 UNSPEC_TOCPTR))]
9579 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9580 "bcl 20,31,$+8\\n\\t.long %1-$"
9581 [(set_attr "type" "branch")
9582 (set_attr "length" "8")])
9583
9584 (define_insn "load_toc_v4_PIC_2"
9585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9586 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9587 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9588 (match_operand:SI 3 "immediate_operand" "s")))))]
9589 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9590 "{l|lwz} %0,%2-%3(%1)"
9591 [(set_attr "type" "load")])
9592
9593 (define_insn "load_toc_v4_PIC_3b"
9594 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9595 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9596 (high:SI
9597 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9598 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9599 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9600 "{cau|addis} %0,%1,%2-%3@ha")
9601
9602 (define_insn "load_toc_v4_PIC_3c"
9603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9604 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9605 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9606 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9607 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9608 "{cal|addi} %0,%1,%2-%3@l")
9609
9610 ;; If the TOC is shared over a translation unit, as happens with all
9611 ;; the kinds of PIC that we support, we need to restore the TOC
9612 ;; pointer only when jumping over units of translation.
9613 ;; On Darwin, we need to reload the picbase.
9614
9615 (define_expand "builtin_setjmp_receiver"
9616 [(use (label_ref (match_operand 0 "" "")))]
9617 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9618 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9619 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9620 "
9621 {
9622 #if TARGET_MACHO
9623 if (DEFAULT_ABI == ABI_DARWIN)
9624 {
9625 const char *picbase = machopic_function_base_name ();
9626 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9627 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9628 rtx tmplabrtx;
9629 char tmplab[20];
9630
9631 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9632 CODE_LABEL_NUMBER (operands[0]));
9633 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9634
9635 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9636 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9637 }
9638 else
9639 #endif
9640 rs6000_emit_load_toc_table (FALSE);
9641 DONE;
9642 }")
9643
9644 ;; Elf specific ways of loading addresses for non-PIC code.
9645 ;; The output of this could be r0, but we make a very strong
9646 ;; preference for a base register because it will usually
9647 ;; be needed there.
9648 (define_insn "elf_high"
9649 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9650 (high:SI (match_operand 1 "" "")))]
9651 "TARGET_ELF && ! TARGET_64BIT"
9652 "{liu|lis} %0,%1@ha")
9653
9654 (define_insn "elf_low"
9655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9656 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9657 (match_operand 2 "" "")))]
9658 "TARGET_ELF && ! TARGET_64BIT"
9659 "@
9660 {cal|la} %0,%2@l(%1)
9661 {ai|addic} %0,%1,%K2")
9662 \f
9663 ;; A function pointer under AIX is a pointer to a data area whose first word
9664 ;; contains the actual address of the function, whose second word contains a
9665 ;; pointer to its TOC, and whose third word contains a value to place in the
9666 ;; static chain register (r11). Note that if we load the static chain, our
9667 ;; "trampoline" need not have any executable code.
9668
9669 (define_expand "call_indirect_aix32"
9670 [(set (match_dup 2)
9671 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9672 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9673 (reg:SI 2))
9674 (set (reg:SI 2)
9675 (mem:SI (plus:SI (match_dup 0)
9676 (const_int 4))))
9677 (set (reg:SI 11)
9678 (mem:SI (plus:SI (match_dup 0)
9679 (const_int 8))))
9680 (parallel [(call (mem:SI (match_dup 2))
9681 (match_operand 1 "" ""))
9682 (use (reg:SI 2))
9683 (use (reg:SI 11))
9684 (set (reg:SI 2)
9685 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9686 (clobber (scratch:SI))])]
9687 "TARGET_32BIT"
9688 "
9689 { operands[2] = gen_reg_rtx (SImode); }")
9690
9691 (define_expand "call_indirect_aix64"
9692 [(set (match_dup 2)
9693 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9694 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9695 (reg:DI 2))
9696 (set (reg:DI 2)
9697 (mem:DI (plus:DI (match_dup 0)
9698 (const_int 8))))
9699 (set (reg:DI 11)
9700 (mem:DI (plus:DI (match_dup 0)
9701 (const_int 16))))
9702 (parallel [(call (mem:SI (match_dup 2))
9703 (match_operand 1 "" ""))
9704 (use (reg:DI 2))
9705 (use (reg:DI 11))
9706 (set (reg:DI 2)
9707 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9708 (clobber (scratch:SI))])]
9709 "TARGET_64BIT"
9710 "
9711 { operands[2] = gen_reg_rtx (DImode); }")
9712
9713 (define_expand "call_value_indirect_aix32"
9714 [(set (match_dup 3)
9715 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9716 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9717 (reg:SI 2))
9718 (set (reg:SI 2)
9719 (mem:SI (plus:SI (match_dup 1)
9720 (const_int 4))))
9721 (set (reg:SI 11)
9722 (mem:SI (plus:SI (match_dup 1)
9723 (const_int 8))))
9724 (parallel [(set (match_operand 0 "" "")
9725 (call (mem:SI (match_dup 3))
9726 (match_operand 2 "" "")))
9727 (use (reg:SI 2))
9728 (use (reg:SI 11))
9729 (set (reg:SI 2)
9730 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9731 (clobber (scratch:SI))])]
9732 "TARGET_32BIT"
9733 "
9734 { operands[3] = gen_reg_rtx (SImode); }")
9735
9736 (define_expand "call_value_indirect_aix64"
9737 [(set (match_dup 3)
9738 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9739 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9740 (reg:DI 2))
9741 (set (reg:DI 2)
9742 (mem:DI (plus:DI (match_dup 1)
9743 (const_int 8))))
9744 (set (reg:DI 11)
9745 (mem:DI (plus:DI (match_dup 1)
9746 (const_int 16))))
9747 (parallel [(set (match_operand 0 "" "")
9748 (call (mem:SI (match_dup 3))
9749 (match_operand 2 "" "")))
9750 (use (reg:DI 2))
9751 (use (reg:DI 11))
9752 (set (reg:DI 2)
9753 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9754 (clobber (scratch:SI))])]
9755 "TARGET_64BIT"
9756 "
9757 { operands[3] = gen_reg_rtx (DImode); }")
9758
9759 ;; Now the definitions for the call and call_value insns
9760 (define_expand "call"
9761 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9762 (match_operand 1 "" ""))
9763 (use (match_operand 2 "" ""))
9764 (clobber (scratch:SI))])]
9765 ""
9766 "
9767 {
9768 #if TARGET_MACHO
9769 if (MACHOPIC_INDIRECT)
9770 operands[0] = machopic_indirect_call_target (operands[0]);
9771 #endif
9772
9773 gcc_assert (GET_CODE (operands[0]) == MEM);
9774 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9775
9776 operands[0] = XEXP (operands[0], 0);
9777
9778 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9779 && flag_pic
9780 && GET_CODE (operands[0]) == SYMBOL_REF
9781 && !SYMBOL_REF_LOCAL_P (operands[0]))
9782 {
9783 rtx call;
9784 rtvec tmp;
9785
9786 tmp = gen_rtvec (3,
9787 gen_rtx_CALL (VOIDmode,
9788 gen_rtx_MEM (SImode, operands[0]),
9789 operands[1]),
9790 gen_rtx_USE (VOIDmode, operands[2]),
9791 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9792 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9793 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9794 DONE;
9795 }
9796
9797 if (GET_CODE (operands[0]) != SYMBOL_REF
9798 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9799 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9800 {
9801 if (INTVAL (operands[2]) & CALL_LONG)
9802 operands[0] = rs6000_longcall_ref (operands[0]);
9803
9804 switch (DEFAULT_ABI)
9805 {
9806 case ABI_V4:
9807 case ABI_DARWIN:
9808 operands[0] = force_reg (Pmode, operands[0]);
9809 break;
9810
9811 case ABI_AIX:
9812 /* AIX function pointers are really pointers to a three word
9813 area. */
9814 emit_call_insn (TARGET_32BIT
9815 ? gen_call_indirect_aix32 (force_reg (SImode,
9816 operands[0]),
9817 operands[1])
9818 : gen_call_indirect_aix64 (force_reg (DImode,
9819 operands[0]),
9820 operands[1]));
9821 DONE;
9822
9823 default:
9824 gcc_unreachable ();
9825 }
9826 }
9827 }")
9828
9829 (define_expand "call_value"
9830 [(parallel [(set (match_operand 0 "" "")
9831 (call (mem:SI (match_operand 1 "address_operand" ""))
9832 (match_operand 2 "" "")))
9833 (use (match_operand 3 "" ""))
9834 (clobber (scratch:SI))])]
9835 ""
9836 "
9837 {
9838 #if TARGET_MACHO
9839 if (MACHOPIC_INDIRECT)
9840 operands[1] = machopic_indirect_call_target (operands[1]);
9841 #endif
9842
9843 gcc_assert (GET_CODE (operands[1]) == MEM);
9844 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
9845
9846 operands[1] = XEXP (operands[1], 0);
9847
9848 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9849 && flag_pic
9850 && GET_CODE (operands[1]) == SYMBOL_REF
9851 && !SYMBOL_REF_LOCAL_P (operands[1]))
9852 {
9853 rtx call;
9854 rtvec tmp;
9855
9856 tmp = gen_rtvec (3,
9857 gen_rtx_SET (VOIDmode,
9858 operands[0],
9859 gen_rtx_CALL (VOIDmode,
9860 gen_rtx_MEM (SImode,
9861 operands[1]),
9862 operands[2])),
9863 gen_rtx_USE (VOIDmode, operands[3]),
9864 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9865 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9866 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9867 DONE;
9868 }
9869
9870 if (GET_CODE (operands[1]) != SYMBOL_REF
9871 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
9872 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
9873 {
9874 if (INTVAL (operands[3]) & CALL_LONG)
9875 operands[1] = rs6000_longcall_ref (operands[1]);
9876
9877 switch (DEFAULT_ABI)
9878 {
9879 case ABI_V4:
9880 case ABI_DARWIN:
9881 operands[1] = force_reg (Pmode, operands[1]);
9882 break;
9883
9884 case ABI_AIX:
9885 /* AIX function pointers are really pointers to a three word
9886 area. */
9887 emit_call_insn (TARGET_32BIT
9888 ? gen_call_value_indirect_aix32 (operands[0],
9889 force_reg (SImode,
9890 operands[1]),
9891 operands[2])
9892 : gen_call_value_indirect_aix64 (operands[0],
9893 force_reg (DImode,
9894 operands[1]),
9895 operands[2]));
9896 DONE;
9897
9898 default:
9899 gcc_unreachable ();
9900 }
9901 }
9902 }")
9903
9904 ;; Call to function in current module. No TOC pointer reload needed.
9905 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9906 ;; either the function was not prototyped, or it was prototyped as a
9907 ;; variable argument function. It is > 0 if FP registers were passed
9908 ;; and < 0 if they were not.
9909
9910 (define_insn "*call_local32"
9911 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9912 (match_operand 1 "" "g,g"))
9913 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9914 (clobber (match_scratch:SI 3 "=l,l"))]
9915 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9916 "*
9917 {
9918 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9919 output_asm_insn (\"crxor 6,6,6\", operands);
9920
9921 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9922 output_asm_insn (\"creqv 6,6,6\", operands);
9923
9924 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9925 }"
9926 [(set_attr "type" "branch")
9927 (set_attr "length" "4,8")])
9928
9929 (define_insn "*call_local64"
9930 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9931 (match_operand 1 "" "g,g"))
9932 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9933 (clobber (match_scratch:SI 3 "=l,l"))]
9934 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9935 "*
9936 {
9937 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9938 output_asm_insn (\"crxor 6,6,6\", operands);
9939
9940 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9941 output_asm_insn (\"creqv 6,6,6\", operands);
9942
9943 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9944 }"
9945 [(set_attr "type" "branch")
9946 (set_attr "length" "4,8")])
9947
9948 (define_insn "*call_value_local32"
9949 [(set (match_operand 0 "" "")
9950 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9951 (match_operand 2 "" "g,g")))
9952 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9953 (clobber (match_scratch:SI 4 "=l,l"))]
9954 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9955 "*
9956 {
9957 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9958 output_asm_insn (\"crxor 6,6,6\", operands);
9959
9960 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9961 output_asm_insn (\"creqv 6,6,6\", operands);
9962
9963 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9964 }"
9965 [(set_attr "type" "branch")
9966 (set_attr "length" "4,8")])
9967
9968
9969 (define_insn "*call_value_local64"
9970 [(set (match_operand 0 "" "")
9971 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9972 (match_operand 2 "" "g,g")))
9973 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9974 (clobber (match_scratch:SI 4 "=l,l"))]
9975 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9976 "*
9977 {
9978 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9979 output_asm_insn (\"crxor 6,6,6\", operands);
9980
9981 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9982 output_asm_insn (\"creqv 6,6,6\", operands);
9983
9984 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9985 }"
9986 [(set_attr "type" "branch")
9987 (set_attr "length" "4,8")])
9988
9989 ;; Call to function which may be in another module. Restore the TOC
9990 ;; pointer (r2) after the call unless this is System V.
9991 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9992 ;; either the function was not prototyped, or it was prototyped as a
9993 ;; variable argument function. It is > 0 if FP registers were passed
9994 ;; and < 0 if they were not.
9995
9996 (define_insn "*call_indirect_nonlocal_aix32"
9997 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
9998 (match_operand 1 "" "g,g"))
9999 (use (reg:SI 2))
10000 (use (reg:SI 11))
10001 (set (reg:SI 2)
10002 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10003 (clobber (match_scratch:SI 2 "=l,l"))]
10004 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10005 "b%T0l\;{l|lwz} 2,20(1)"
10006 [(set_attr "type" "jmpreg")
10007 (set_attr "length" "8")])
10008
10009 (define_insn "*call_nonlocal_aix32"
10010 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10011 (match_operand 1 "" "g"))
10012 (use (match_operand:SI 2 "immediate_operand" "O"))
10013 (clobber (match_scratch:SI 3 "=l"))]
10014 "TARGET_32BIT
10015 && DEFAULT_ABI == ABI_AIX
10016 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10017 "bl %z0\;%."
10018 [(set_attr "type" "branch")
10019 (set_attr "length" "8")])
10020
10021 (define_insn "*call_indirect_nonlocal_aix64"
10022 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10023 (match_operand 1 "" "g,g"))
10024 (use (reg:DI 2))
10025 (use (reg:DI 11))
10026 (set (reg:DI 2)
10027 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10028 (clobber (match_scratch:SI 2 "=l,l"))]
10029 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10030 "b%T0l\;ld 2,40(1)"
10031 [(set_attr "type" "jmpreg")
10032 (set_attr "length" "8")])
10033
10034 (define_insn "*call_nonlocal_aix64"
10035 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10036 (match_operand 1 "" "g"))
10037 (use (match_operand:SI 2 "immediate_operand" "O"))
10038 (clobber (match_scratch:SI 3 "=l"))]
10039 "TARGET_64BIT
10040 && DEFAULT_ABI == ABI_AIX
10041 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10042 "bl %z0\;%."
10043 [(set_attr "type" "branch")
10044 (set_attr "length" "8")])
10045
10046 (define_insn "*call_value_indirect_nonlocal_aix32"
10047 [(set (match_operand 0 "" "")
10048 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10049 (match_operand 2 "" "g,g")))
10050 (use (reg:SI 2))
10051 (use (reg:SI 11))
10052 (set (reg:SI 2)
10053 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10054 (clobber (match_scratch:SI 3 "=l,l"))]
10055 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10056 "b%T1l\;{l|lwz} 2,20(1)"
10057 [(set_attr "type" "jmpreg")
10058 (set_attr "length" "8")])
10059
10060 (define_insn "*call_value_nonlocal_aix32"
10061 [(set (match_operand 0 "" "")
10062 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10063 (match_operand 2 "" "g")))
10064 (use (match_operand:SI 3 "immediate_operand" "O"))
10065 (clobber (match_scratch:SI 4 "=l"))]
10066 "TARGET_32BIT
10067 && DEFAULT_ABI == ABI_AIX
10068 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10069 "bl %z1\;%."
10070 [(set_attr "type" "branch")
10071 (set_attr "length" "8")])
10072
10073 (define_insn "*call_value_indirect_nonlocal_aix64"
10074 [(set (match_operand 0 "" "")
10075 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10076 (match_operand 2 "" "g,g")))
10077 (use (reg:DI 2))
10078 (use (reg:DI 11))
10079 (set (reg:DI 2)
10080 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10081 (clobber (match_scratch:SI 3 "=l,l"))]
10082 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10083 "b%T1l\;ld 2,40(1)"
10084 [(set_attr "type" "jmpreg")
10085 (set_attr "length" "8")])
10086
10087 (define_insn "*call_value_nonlocal_aix64"
10088 [(set (match_operand 0 "" "")
10089 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10090 (match_operand 2 "" "g")))
10091 (use (match_operand:SI 3 "immediate_operand" "O"))
10092 (clobber (match_scratch:SI 4 "=l"))]
10093 "TARGET_64BIT
10094 && DEFAULT_ABI == ABI_AIX
10095 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10096 "bl %z1\;%."
10097 [(set_attr "type" "branch")
10098 (set_attr "length" "8")])
10099
10100 ;; A function pointer under System V is just a normal pointer
10101 ;; operands[0] is the function pointer
10102 ;; operands[1] is the stack size to clean up
10103 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10104 ;; which indicates how to set cr1
10105
10106 (define_insn "*call_indirect_nonlocal_sysv"
10107 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10108 (match_operand 1 "" "g,g,g,g"))
10109 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10110 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10111 "DEFAULT_ABI == ABI_V4
10112 || DEFAULT_ABI == ABI_DARWIN"
10113 {
10114 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10115 output_asm_insn ("crxor 6,6,6", operands);
10116
10117 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10118 output_asm_insn ("creqv 6,6,6", operands);
10119
10120 return "b%T0l";
10121 }
10122 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10123 (set_attr "length" "4,4,8,8")])
10124
10125 (define_insn "*call_nonlocal_sysv"
10126 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10127 (match_operand 1 "" "g,g"))
10128 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10129 (clobber (match_scratch:SI 3 "=l,l"))]
10130 "(DEFAULT_ABI == ABI_DARWIN
10131 || (DEFAULT_ABI == ABI_V4
10132 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10133 {
10134 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10135 output_asm_insn ("crxor 6,6,6", operands);
10136
10137 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10138 output_asm_insn ("creqv 6,6,6", operands);
10139
10140 #if TARGET_MACHO
10141 return output_call(insn, operands, 0, 2);
10142 #else
10143 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10144 {
10145 if (TARGET_SECURE_PLT && flag_pic == 2)
10146 /* The magic 32768 offset here and in the other sysv call insns
10147 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10148 See sysv4.h:toc_section. */
10149 return "bl %z0+32768@plt";
10150 else
10151 return "bl %z0@plt";
10152 }
10153 else
10154 return "bl %z0";
10155 #endif
10156 }
10157 [(set_attr "type" "branch,branch")
10158 (set_attr "length" "4,8")])
10159
10160 (define_insn "*call_value_indirect_nonlocal_sysv"
10161 [(set (match_operand 0 "" "")
10162 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10163 (match_operand 2 "" "g,g,g,g")))
10164 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10165 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10166 "DEFAULT_ABI == ABI_V4
10167 || DEFAULT_ABI == ABI_DARWIN"
10168 {
10169 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10170 output_asm_insn ("crxor 6,6,6", operands);
10171
10172 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10173 output_asm_insn ("creqv 6,6,6", operands);
10174
10175 return "b%T1l";
10176 }
10177 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10178 (set_attr "length" "4,4,8,8")])
10179
10180 (define_insn "*call_value_nonlocal_sysv"
10181 [(set (match_operand 0 "" "")
10182 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10183 (match_operand 2 "" "g,g")))
10184 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10185 (clobber (match_scratch:SI 4 "=l,l"))]
10186 "(DEFAULT_ABI == ABI_DARWIN
10187 || (DEFAULT_ABI == ABI_V4
10188 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10189 {
10190 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10191 output_asm_insn ("crxor 6,6,6", operands);
10192
10193 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10194 output_asm_insn ("creqv 6,6,6", operands);
10195
10196 #if TARGET_MACHO
10197 return output_call(insn, operands, 1, 3);
10198 #else
10199 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10200 {
10201 if (TARGET_SECURE_PLT && flag_pic == 2)
10202 return "bl %z1+32768@plt";
10203 else
10204 return "bl %z1@plt";
10205 }
10206 else
10207 return "bl %z1";
10208 #endif
10209 }
10210 [(set_attr "type" "branch,branch")
10211 (set_attr "length" "4,8")])
10212
10213 ;; Call subroutine returning any type.
10214 (define_expand "untyped_call"
10215 [(parallel [(call (match_operand 0 "" "")
10216 (const_int 0))
10217 (match_operand 1 "" "")
10218 (match_operand 2 "" "")])]
10219 ""
10220 "
10221 {
10222 int i;
10223
10224 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10225
10226 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10227 {
10228 rtx set = XVECEXP (operands[2], 0, i);
10229 emit_move_insn (SET_DEST (set), SET_SRC (set));
10230 }
10231
10232 /* The optimizer does not know that the call sets the function value
10233 registers we stored in the result block. We avoid problems by
10234 claiming that all hard registers are used and clobbered at this
10235 point. */
10236 emit_insn (gen_blockage ());
10237
10238 DONE;
10239 }")
10240
10241 ;; sibling call patterns
10242 (define_expand "sibcall"
10243 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10244 (match_operand 1 "" ""))
10245 (use (match_operand 2 "" ""))
10246 (use (match_operand 3 "" ""))
10247 (return)])]
10248 ""
10249 "
10250 {
10251 #if TARGET_MACHO
10252 if (MACHOPIC_INDIRECT)
10253 operands[0] = machopic_indirect_call_target (operands[0]);
10254 #endif
10255
10256 gcc_assert (GET_CODE (operands[0]) == MEM);
10257 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10258
10259 operands[0] = XEXP (operands[0], 0);
10260 operands[3] = gen_reg_rtx (SImode);
10261
10262 }")
10263
10264 ;; this and similar patterns must be marked as using LR, otherwise
10265 ;; dataflow will try to delete the store into it. This is true
10266 ;; even when the actual reg to jump to is in CTR, when LR was
10267 ;; saved and restored around the PIC-setting BCL.
10268 (define_insn "*sibcall_local32"
10269 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10270 (match_operand 1 "" "g,g"))
10271 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10272 (use (match_operand:SI 3 "register_operand" "l,l"))
10273 (return)]
10274 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10275 "*
10276 {
10277 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10278 output_asm_insn (\"crxor 6,6,6\", operands);
10279
10280 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10281 output_asm_insn (\"creqv 6,6,6\", operands);
10282
10283 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10284 }"
10285 [(set_attr "type" "branch")
10286 (set_attr "length" "4,8")])
10287
10288 (define_insn "*sibcall_local64"
10289 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10290 (match_operand 1 "" "g,g"))
10291 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10292 (use (match_operand:SI 3 "register_operand" "l,l"))
10293 (return)]
10294 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10295 "*
10296 {
10297 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10298 output_asm_insn (\"crxor 6,6,6\", operands);
10299
10300 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10301 output_asm_insn (\"creqv 6,6,6\", operands);
10302
10303 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10304 }"
10305 [(set_attr "type" "branch")
10306 (set_attr "length" "4,8")])
10307
10308 (define_insn "*sibcall_value_local32"
10309 [(set (match_operand 0 "" "")
10310 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10311 (match_operand 2 "" "g,g")))
10312 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10313 (use (match_operand:SI 4 "register_operand" "l,l"))
10314 (return)]
10315 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10316 "*
10317 {
10318 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10319 output_asm_insn (\"crxor 6,6,6\", operands);
10320
10321 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10322 output_asm_insn (\"creqv 6,6,6\", operands);
10323
10324 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10325 }"
10326 [(set_attr "type" "branch")
10327 (set_attr "length" "4,8")])
10328
10329
10330 (define_insn "*sibcall_value_local64"
10331 [(set (match_operand 0 "" "")
10332 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10333 (match_operand 2 "" "g,g")))
10334 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10335 (use (match_operand:SI 4 "register_operand" "l,l"))
10336 (return)]
10337 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10338 "*
10339 {
10340 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10341 output_asm_insn (\"crxor 6,6,6\", operands);
10342
10343 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10344 output_asm_insn (\"creqv 6,6,6\", operands);
10345
10346 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10347 }"
10348 [(set_attr "type" "branch")
10349 (set_attr "length" "4,8")])
10350
10351 (define_insn "*sibcall_nonlocal_aix32"
10352 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10353 (match_operand 1 "" "g"))
10354 (use (match_operand:SI 2 "immediate_operand" "O"))
10355 (use (match_operand:SI 3 "register_operand" "l"))
10356 (return)]
10357 "TARGET_32BIT
10358 && DEFAULT_ABI == ABI_AIX
10359 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10360 "b %z0"
10361 [(set_attr "type" "branch")
10362 (set_attr "length" "4")])
10363
10364 (define_insn "*sibcall_nonlocal_aix64"
10365 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10366 (match_operand 1 "" "g"))
10367 (use (match_operand:SI 2 "immediate_operand" "O"))
10368 (use (match_operand:SI 3 "register_operand" "l"))
10369 (return)]
10370 "TARGET_64BIT
10371 && DEFAULT_ABI == ABI_AIX
10372 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10373 "b %z0"
10374 [(set_attr "type" "branch")
10375 (set_attr "length" "4")])
10376
10377 (define_insn "*sibcall_value_nonlocal_aix32"
10378 [(set (match_operand 0 "" "")
10379 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10380 (match_operand 2 "" "g")))
10381 (use (match_operand:SI 3 "immediate_operand" "O"))
10382 (use (match_operand:SI 4 "register_operand" "l"))
10383 (return)]
10384 "TARGET_32BIT
10385 && DEFAULT_ABI == ABI_AIX
10386 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10387 "b %z1"
10388 [(set_attr "type" "branch")
10389 (set_attr "length" "4")])
10390
10391 (define_insn "*sibcall_value_nonlocal_aix64"
10392 [(set (match_operand 0 "" "")
10393 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10394 (match_operand 2 "" "g")))
10395 (use (match_operand:SI 3 "immediate_operand" "O"))
10396 (use (match_operand:SI 4 "register_operand" "l"))
10397 (return)]
10398 "TARGET_64BIT
10399 && DEFAULT_ABI == ABI_AIX
10400 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10401 "b %z1"
10402 [(set_attr "type" "branch")
10403 (set_attr "length" "4")])
10404
10405 (define_insn "*sibcall_nonlocal_sysv"
10406 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10407 (match_operand 1 "" ""))
10408 (use (match_operand 2 "immediate_operand" "O,n"))
10409 (use (match_operand:SI 3 "register_operand" "l,l"))
10410 (return)]
10411 "(DEFAULT_ABI == ABI_DARWIN
10412 || DEFAULT_ABI == ABI_V4)
10413 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10414 "*
10415 {
10416 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10417 output_asm_insn (\"crxor 6,6,6\", operands);
10418
10419 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10420 output_asm_insn (\"creqv 6,6,6\", operands);
10421
10422 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10423 {
10424 if (TARGET_SECURE_PLT && flag_pic == 2)
10425 return \"b %z0+32768@plt\";
10426 else
10427 return \"b %z0@plt\";
10428 }
10429 else
10430 return \"b %z0\";
10431 }"
10432 [(set_attr "type" "branch,branch")
10433 (set_attr "length" "4,8")])
10434
10435 (define_expand "sibcall_value"
10436 [(parallel [(set (match_operand 0 "register_operand" "")
10437 (call (mem:SI (match_operand 1 "address_operand" ""))
10438 (match_operand 2 "" "")))
10439 (use (match_operand 3 "" ""))
10440 (use (match_operand 4 "" ""))
10441 (return)])]
10442 ""
10443 "
10444 {
10445 #if TARGET_MACHO
10446 if (MACHOPIC_INDIRECT)
10447 operands[1] = machopic_indirect_call_target (operands[1]);
10448 #endif
10449
10450 gcc_assert (GET_CODE (operands[1]) == MEM);
10451 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10452
10453 operands[1] = XEXP (operands[1], 0);
10454 operands[4] = gen_reg_rtx (SImode);
10455
10456 }")
10457
10458 (define_insn "*sibcall_value_nonlocal_sysv"
10459 [(set (match_operand 0 "" "")
10460 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10461 (match_operand 2 "" "")))
10462 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10463 (use (match_operand:SI 4 "register_operand" "l,l"))
10464 (return)]
10465 "(DEFAULT_ABI == ABI_DARWIN
10466 || DEFAULT_ABI == ABI_V4)
10467 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10468 "*
10469 {
10470 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10471 output_asm_insn (\"crxor 6,6,6\", operands);
10472
10473 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10474 output_asm_insn (\"creqv 6,6,6\", operands);
10475
10476 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10477 {
10478 if (TARGET_SECURE_PLT && flag_pic == 2)
10479 return \"b %z1+32768@plt\";
10480 else
10481 return \"b %z1@plt\";
10482 }
10483 else
10484 return \"b %z1\";
10485 }"
10486 [(set_attr "type" "branch,branch")
10487 (set_attr "length" "4,8")])
10488
10489 (define_expand "sibcall_epilogue"
10490 [(use (const_int 0))]
10491 "TARGET_SCHED_PROLOG"
10492 "
10493 {
10494 rs6000_emit_epilogue (TRUE);
10495 DONE;
10496 }")
10497
10498 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10499 ;; all of memory. This blocks insns from being moved across this point.
10500
10501 (define_insn "blockage"
10502 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10503 ""
10504 "")
10505 \f
10506 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10507 ;; signed & unsigned, and one type of branch.
10508 ;;
10509 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10510 ;; insns, and branches. We store the operands of compares until we see
10511 ;; how it is used.
10512 (define_expand "cmp<mode>"
10513 [(set (cc0)
10514 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10515 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10516 ""
10517 "
10518 {
10519 /* Take care of the possibility that operands[1] might be negative but
10520 this might be a logical operation. That insn doesn't exist. */
10521 if (GET_CODE (operands[1]) == CONST_INT
10522 && INTVAL (operands[1]) < 0)
10523 operands[1] = force_reg (<MODE>mode, operands[1]);
10524
10525 rs6000_compare_op0 = operands[0];
10526 rs6000_compare_op1 = operands[1];
10527 rs6000_compare_fp_p = 0;
10528 DONE;
10529 }")
10530
10531 (define_expand "cmp<mode>"
10532 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10533 (match_operand:FP 1 "gpc_reg_operand" "")))]
10534 ""
10535 "
10536 {
10537 rs6000_compare_op0 = operands[0];
10538 rs6000_compare_op1 = operands[1];
10539 rs6000_compare_fp_p = 1;
10540 DONE;
10541 }")
10542
10543 (define_expand "beq"
10544 [(use (match_operand 0 "" ""))]
10545 ""
10546 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10547
10548 (define_expand "bne"
10549 [(use (match_operand 0 "" ""))]
10550 ""
10551 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10552
10553 (define_expand "bge"
10554 [(use (match_operand 0 "" ""))]
10555 ""
10556 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10557
10558 (define_expand "bgt"
10559 [(use (match_operand 0 "" ""))]
10560 ""
10561 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10562
10563 (define_expand "ble"
10564 [(use (match_operand 0 "" ""))]
10565 ""
10566 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10567
10568 (define_expand "blt"
10569 [(use (match_operand 0 "" ""))]
10570 ""
10571 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10572
10573 (define_expand "bgeu"
10574 [(use (match_operand 0 "" ""))]
10575 ""
10576 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10577
10578 (define_expand "bgtu"
10579 [(use (match_operand 0 "" ""))]
10580 ""
10581 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10582
10583 (define_expand "bleu"
10584 [(use (match_operand 0 "" ""))]
10585 ""
10586 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10587
10588 (define_expand "bltu"
10589 [(use (match_operand 0 "" ""))]
10590 ""
10591 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10592
10593 (define_expand "bunordered"
10594 [(use (match_operand 0 "" ""))]
10595 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10596 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10597
10598 (define_expand "bordered"
10599 [(use (match_operand 0 "" ""))]
10600 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10601 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10602
10603 (define_expand "buneq"
10604 [(use (match_operand 0 "" ""))]
10605 ""
10606 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10607
10608 (define_expand "bunge"
10609 [(use (match_operand 0 "" ""))]
10610 ""
10611 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10612
10613 (define_expand "bungt"
10614 [(use (match_operand 0 "" ""))]
10615 ""
10616 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10617
10618 (define_expand "bunle"
10619 [(use (match_operand 0 "" ""))]
10620 ""
10621 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10622
10623 (define_expand "bunlt"
10624 [(use (match_operand 0 "" ""))]
10625 ""
10626 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10627
10628 (define_expand "bltgt"
10629 [(use (match_operand 0 "" ""))]
10630 ""
10631 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10632
10633 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10634 ;; For SEQ, likewise, except that comparisons with zero should be done
10635 ;; with an scc insns. However, due to the order that combine see the
10636 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10637 ;; the cases we don't want to handle.
10638 (define_expand "seq"
10639 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10640 ""
10641 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10642
10643 (define_expand "sne"
10644 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10645 ""
10646 "
10647 {
10648 if (! rs6000_compare_fp_p)
10649 FAIL;
10650
10651 rs6000_emit_sCOND (NE, operands[0]);
10652 DONE;
10653 }")
10654
10655 ;; A >= 0 is best done the portable way for A an integer.
10656 (define_expand "sge"
10657 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10658 ""
10659 "
10660 {
10661 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10662 FAIL;
10663
10664 rs6000_emit_sCOND (GE, operands[0]);
10665 DONE;
10666 }")
10667
10668 ;; A > 0 is best done using the portable sequence, so fail in that case.
10669 (define_expand "sgt"
10670 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10671 ""
10672 "
10673 {
10674 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10675 FAIL;
10676
10677 rs6000_emit_sCOND (GT, operands[0]);
10678 DONE;
10679 }")
10680
10681 ;; A <= 0 is best done the portable way for A an integer.
10682 (define_expand "sle"
10683 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10684 ""
10685 "
10686 {
10687 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10688 FAIL;
10689
10690 rs6000_emit_sCOND (LE, operands[0]);
10691 DONE;
10692 }")
10693
10694 ;; A < 0 is best done in the portable way for A an integer.
10695 (define_expand "slt"
10696 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10697 ""
10698 "
10699 {
10700 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10701 FAIL;
10702
10703 rs6000_emit_sCOND (LT, operands[0]);
10704 DONE;
10705 }")
10706
10707 (define_expand "sgeu"
10708 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10709 ""
10710 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10711
10712 (define_expand "sgtu"
10713 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10714 ""
10715 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10716
10717 (define_expand "sleu"
10718 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10719 ""
10720 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10721
10722 (define_expand "sltu"
10723 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10724 ""
10725 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10726
10727 (define_expand "sunordered"
10728 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10729 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10730 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10731
10732 (define_expand "sordered"
10733 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10734 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10735 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10736
10737 (define_expand "suneq"
10738 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10739 ""
10740 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10741
10742 (define_expand "sunge"
10743 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10744 ""
10745 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10746
10747 (define_expand "sungt"
10748 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10749 ""
10750 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10751
10752 (define_expand "sunle"
10753 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10754 ""
10755 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10756
10757 (define_expand "sunlt"
10758 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10759 ""
10760 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10761
10762 (define_expand "sltgt"
10763 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10764 ""
10765 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10766
10767 (define_expand "stack_protect_set"
10768 [(match_operand 0 "memory_operand" "")
10769 (match_operand 1 "memory_operand" "")]
10770 ""
10771 {
10772 #ifdef TARGET_THREAD_SSP_OFFSET
10773 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10774 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10775 operands[1] = gen_rtx_MEM (Pmode, addr);
10776 #endif
10777 if (TARGET_64BIT)
10778 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10779 else
10780 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10781 DONE;
10782 })
10783
10784 (define_insn "stack_protect_setsi"
10785 [(set (match_operand:SI 0 "memory_operand" "=m")
10786 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10787 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10788 "TARGET_32BIT"
10789 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
10790 [(set_attr "type" "three")
10791 (set_attr "length" "12")])
10792
10793 (define_insn "stack_protect_setdi"
10794 [(set (match_operand:DI 0 "memory_operand" "=m")
10795 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10796 (set (match_scratch:DI 2 "=&r") (const_int 0))]
10797 "TARGET_64BIT"
10798 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
10799 [(set_attr "type" "three")
10800 (set_attr "length" "12")])
10801
10802 (define_expand "stack_protect_test"
10803 [(match_operand 0 "memory_operand" "")
10804 (match_operand 1 "memory_operand" "")
10805 (match_operand 2 "" "")]
10806 ""
10807 {
10808 #ifdef TARGET_THREAD_SSP_OFFSET
10809 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10810 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10811 operands[1] = gen_rtx_MEM (Pmode, addr);
10812 #endif
10813 rs6000_compare_op0 = operands[0];
10814 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
10815 UNSPEC_SP_TEST);
10816 rs6000_compare_fp_p = 0;
10817 emit_jump_insn (gen_beq (operands[2]));
10818 DONE;
10819 })
10820
10821 (define_insn "stack_protect_testsi"
10822 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10823 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
10824 (match_operand:SI 2 "memory_operand" "m,m")]
10825 UNSPEC_SP_TEST))
10826 (set (match_scratch:SI 4 "=r,r") (const_int 0))
10827 (clobber (match_scratch:SI 3 "=&r,&r"))]
10828 "TARGET_32BIT"
10829 "@
10830 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10831 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10832 [(set_attr "length" "16,20")])
10833
10834 (define_insn "stack_protect_testdi"
10835 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10836 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
10837 (match_operand:DI 2 "memory_operand" "m,m")]
10838 UNSPEC_SP_TEST))
10839 (set (match_scratch:DI 4 "=r,r") (const_int 0))
10840 (clobber (match_scratch:DI 3 "=&r,&r"))]
10841 "TARGET_64BIT"
10842 "@
10843 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10844 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10845 [(set_attr "length" "16,20")])
10846
10847 \f
10848 ;; Here are the actual compare insns.
10849 (define_insn "*cmp<mode>_internal1"
10850 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10851 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10852 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
10853 ""
10854 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
10855 [(set_attr "type" "cmp")])
10856
10857 ;; If we are comparing a register for equality with a large constant,
10858 ;; we can do this with an XOR followed by a compare. But we need a scratch
10859 ;; register for the result of the XOR.
10860
10861 (define_split
10862 [(set (match_operand:CC 0 "cc_reg_operand" "")
10863 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10864 (match_operand:SI 2 "non_short_cint_operand" "")))
10865 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10866 "find_single_use (operands[0], insn, 0)
10867 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10868 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10869 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10870 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10871 "
10872 {
10873 /* Get the constant we are comparing against, C, and see what it looks like
10874 sign-extended to 16 bits. Then see what constant could be XOR'ed
10875 with C to get the sign-extended value. */
10876
10877 HOST_WIDE_INT c = INTVAL (operands[2]);
10878 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10879 HOST_WIDE_INT xorv = c ^ sextc;
10880
10881 operands[4] = GEN_INT (xorv);
10882 operands[5] = GEN_INT (sextc);
10883 }")
10884
10885 (define_insn "*cmpsi_internal2"
10886 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10887 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10888 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10889 ""
10890 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10891 [(set_attr "type" "cmp")])
10892
10893 (define_insn "*cmpdi_internal2"
10894 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10895 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10896 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10897 ""
10898 "cmpld%I2 %0,%1,%b2"
10899 [(set_attr "type" "cmp")])
10900
10901 ;; The following two insns don't exist as single insns, but if we provide
10902 ;; them, we can swap an add and compare, which will enable us to overlap more
10903 ;; of the required delay between a compare and branch. We generate code for
10904 ;; them by splitting.
10905
10906 (define_insn ""
10907 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10908 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10909 (match_operand:SI 2 "short_cint_operand" "i")))
10910 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10911 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10912 ""
10913 "#"
10914 [(set_attr "length" "8")])
10915
10916 (define_insn ""
10917 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10918 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10919 (match_operand:SI 2 "u_short_cint_operand" "i")))
10920 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10921 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10922 ""
10923 "#"
10924 [(set_attr "length" "8")])
10925
10926 (define_split
10927 [(set (match_operand:CC 3 "cc_reg_operand" "")
10928 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10929 (match_operand:SI 2 "short_cint_operand" "")))
10930 (set (match_operand:SI 0 "gpc_reg_operand" "")
10931 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10932 ""
10933 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10934 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10935
10936 (define_split
10937 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10938 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10939 (match_operand:SI 2 "u_short_cint_operand" "")))
10940 (set (match_operand:SI 0 "gpc_reg_operand" "")
10941 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10942 ""
10943 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10944 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10945
10946 (define_insn "*cmpsf_internal1"
10947 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10948 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10949 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10950 "TARGET_HARD_FLOAT && TARGET_FPRS"
10951 "fcmpu %0,%1,%2"
10952 [(set_attr "type" "fpcompare")])
10953
10954 (define_insn "*cmpdf_internal1"
10955 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10956 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10957 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10958 "TARGET_HARD_FLOAT && TARGET_FPRS"
10959 "fcmpu %0,%1,%2"
10960 [(set_attr "type" "fpcompare")])
10961
10962 ;; Only need to compare second words if first words equal
10963 (define_insn "*cmptf_internal1"
10964 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10965 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10966 (match_operand:TF 2 "gpc_reg_operand" "f")))]
10967 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
10968 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10969 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
10970 [(set_attr "type" "fpcompare")
10971 (set_attr "length" "12")])
10972
10973 (define_insn_and_split "*cmptf_internal2"
10974 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10975 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10976 (match_operand:TF 2 "gpc_reg_operand" "f")))
10977 (clobber (match_scratch:DF 3 "=f"))
10978 (clobber (match_scratch:DF 4 "=f"))
10979 (clobber (match_scratch:DF 5 "=f"))
10980 (clobber (match_scratch:DF 6 "=f"))
10981 (clobber (match_scratch:DF 7 "=f"))
10982 (clobber (match_scratch:DF 8 "=f"))
10983 (clobber (match_scratch:DF 9 "=f"))
10984 (clobber (match_scratch:DF 10 "=f"))]
10985 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
10986 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10987 "#"
10988 "&& reload_completed"
10989 [(set (match_dup 3) (match_dup 13))
10990 (set (match_dup 4) (match_dup 14))
10991 (set (match_dup 9) (abs:DF (match_dup 5)))
10992 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
10993 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
10994 (label_ref (match_dup 11))
10995 (pc)))
10996 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
10997 (set (pc) (label_ref (match_dup 12)))
10998 (match_dup 11)
10999 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11000 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11001 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11002 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11003 (match_dup 12)]
11004 {
11005 REAL_VALUE_TYPE rv;
11006 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11007 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11008
11009 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11010 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11011 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11012 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11013 operands[11] = gen_label_rtx ();
11014 operands[12] = gen_label_rtx ();
11015 real_inf (&rv);
11016 operands[13] = force_const_mem (DFmode,
11017 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11018 operands[14] = force_const_mem (DFmode,
11019 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11020 DFmode));
11021 if (TARGET_TOC)
11022 {
11023 operands[13] = gen_const_mem (DFmode,
11024 create_TOC_reference (XEXP (operands[13], 0)));
11025 operands[14] = gen_const_mem (DFmode,
11026 create_TOC_reference (XEXP (operands[14], 0)));
11027 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11028 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11029 }
11030 })
11031 \f
11032 ;; Now we have the scc insns. We can do some combinations because of the
11033 ;; way the machine works.
11034 ;;
11035 ;; Note that this is probably faster if we can put an insn between the
11036 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11037 ;; cases the insns below which don't use an intermediate CR field will
11038 ;; be used instead.
11039 (define_insn ""
11040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11041 (match_operator:SI 1 "scc_comparison_operator"
11042 [(match_operand 2 "cc_reg_operand" "y")
11043 (const_int 0)]))]
11044 ""
11045 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11046 [(set (attr "type")
11047 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11048 (const_string "mfcrf")
11049 ]
11050 (const_string "mfcr")))
11051 (set_attr "length" "8")])
11052
11053 ;; Same as above, but get the GT bit.
11054 (define_insn "move_from_CR_gt_bit"
11055 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11056 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11057 "TARGET_E500"
11058 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11059 [(set_attr "type" "mfcr")
11060 (set_attr "length" "8")])
11061
11062 ;; Same as above, but get the OV/ORDERED bit.
11063 (define_insn "move_from_CR_ov_bit"
11064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11065 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11066 "TARGET_ISEL"
11067 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11068 [(set_attr "type" "mfcr")
11069 (set_attr "length" "8")])
11070
11071 (define_insn ""
11072 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11073 (match_operator:DI 1 "scc_comparison_operator"
11074 [(match_operand 2 "cc_reg_operand" "y")
11075 (const_int 0)]))]
11076 "TARGET_POWERPC64"
11077 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11078 [(set (attr "type")
11079 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11080 (const_string "mfcrf")
11081 ]
11082 (const_string "mfcr")))
11083 (set_attr "length" "8")])
11084
11085 (define_insn ""
11086 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11087 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11088 [(match_operand 2 "cc_reg_operand" "y,y")
11089 (const_int 0)])
11090 (const_int 0)))
11091 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11092 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11093 "TARGET_32BIT"
11094 "@
11095 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11096 #"
11097 [(set_attr "type" "delayed_compare")
11098 (set_attr "length" "8,16")])
11099
11100 (define_split
11101 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11102 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11103 [(match_operand 2 "cc_reg_operand" "")
11104 (const_int 0)])
11105 (const_int 0)))
11106 (set (match_operand:SI 3 "gpc_reg_operand" "")
11107 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11108 "TARGET_32BIT && reload_completed"
11109 [(set (match_dup 3)
11110 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11111 (set (match_dup 0)
11112 (compare:CC (match_dup 3)
11113 (const_int 0)))]
11114 "")
11115
11116 (define_insn ""
11117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11118 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11119 [(match_operand 2 "cc_reg_operand" "y")
11120 (const_int 0)])
11121 (match_operand:SI 3 "const_int_operand" "n")))]
11122 ""
11123 "*
11124 {
11125 int is_bit = ccr_bit (operands[1], 1);
11126 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11127 int count;
11128
11129 if (is_bit >= put_bit)
11130 count = is_bit - put_bit;
11131 else
11132 count = 32 - (put_bit - is_bit);
11133
11134 operands[4] = GEN_INT (count);
11135 operands[5] = GEN_INT (put_bit);
11136
11137 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11138 }"
11139 [(set (attr "type")
11140 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11141 (const_string "mfcrf")
11142 ]
11143 (const_string "mfcr")))
11144 (set_attr "length" "8")])
11145
11146 (define_insn ""
11147 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11148 (compare:CC
11149 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11150 [(match_operand 2 "cc_reg_operand" "y,y")
11151 (const_int 0)])
11152 (match_operand:SI 3 "const_int_operand" "n,n"))
11153 (const_int 0)))
11154 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11155 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11156 (match_dup 3)))]
11157 ""
11158 "*
11159 {
11160 int is_bit = ccr_bit (operands[1], 1);
11161 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11162 int count;
11163
11164 /* Force split for non-cc0 compare. */
11165 if (which_alternative == 1)
11166 return \"#\";
11167
11168 if (is_bit >= put_bit)
11169 count = is_bit - put_bit;
11170 else
11171 count = 32 - (put_bit - is_bit);
11172
11173 operands[5] = GEN_INT (count);
11174 operands[6] = GEN_INT (put_bit);
11175
11176 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11177 }"
11178 [(set_attr "type" "delayed_compare")
11179 (set_attr "length" "8,16")])
11180
11181 (define_split
11182 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11183 (compare:CC
11184 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11185 [(match_operand 2 "cc_reg_operand" "")
11186 (const_int 0)])
11187 (match_operand:SI 3 "const_int_operand" ""))
11188 (const_int 0)))
11189 (set (match_operand:SI 4 "gpc_reg_operand" "")
11190 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11191 (match_dup 3)))]
11192 "reload_completed"
11193 [(set (match_dup 4)
11194 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11195 (match_dup 3)))
11196 (set (match_dup 0)
11197 (compare:CC (match_dup 4)
11198 (const_int 0)))]
11199 "")
11200
11201 ;; There is a 3 cycle delay between consecutive mfcr instructions
11202 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11203
11204 (define_peephole
11205 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11206 (match_operator:SI 1 "scc_comparison_operator"
11207 [(match_operand 2 "cc_reg_operand" "y")
11208 (const_int 0)]))
11209 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11210 (match_operator:SI 4 "scc_comparison_operator"
11211 [(match_operand 5 "cc_reg_operand" "y")
11212 (const_int 0)]))]
11213 "REGNO (operands[2]) != REGNO (operands[5])"
11214 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11215 [(set_attr "type" "mfcr")
11216 (set_attr "length" "12")])
11217
11218 (define_peephole
11219 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11220 (match_operator:DI 1 "scc_comparison_operator"
11221 [(match_operand 2 "cc_reg_operand" "y")
11222 (const_int 0)]))
11223 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11224 (match_operator:DI 4 "scc_comparison_operator"
11225 [(match_operand 5 "cc_reg_operand" "y")
11226 (const_int 0)]))]
11227 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11228 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11229 [(set_attr "type" "mfcr")
11230 (set_attr "length" "12")])
11231
11232 ;; There are some scc insns that can be done directly, without a compare.
11233 ;; These are faster because they don't involve the communications between
11234 ;; the FXU and branch units. In fact, we will be replacing all of the
11235 ;; integer scc insns here or in the portable methods in emit_store_flag.
11236 ;;
11237 ;; Also support (neg (scc ..)) since that construct is used to replace
11238 ;; branches, (plus (scc ..) ..) since that construct is common and
11239 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11240 ;; cases where it is no more expensive than (neg (scc ..)).
11241
11242 ;; Have reload force a constant into a register for the simple insns that
11243 ;; otherwise won't accept constants. We do this because it is faster than
11244 ;; the cmp/mfcr sequence we would otherwise generate.
11245
11246 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11247 (DI "rKJI")])
11248
11249 (define_insn_and_split "*eq<mode>"
11250 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11251 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11252 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
11253 (clobber (match_scratch:GPR 3 "=r"))
11254 (clobber (match_scratch:GPR 4 "=r"))]
11255 ""
11256 "#"
11257 "reload_completed"
11258 [(set (match_dup 3)
11259 (clz:GPR (match_dup 4)))
11260 (set (match_dup 0)
11261 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
11262 {
11263 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11264 {
11265 if (logical_operand (operands[2], <MODE>mode))
11266 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11267 gen_rtx_XOR (<MODE>mode,
11268 operands[1], operands[2])));
11269 else
11270 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11271 gen_rtx_PLUS (<MODE>mode, operands[1],
11272 negate_rtx (<MODE>mode,
11273 operands[2]))));
11274 }
11275 else
11276 operands[4] = operands[1];
11277
11278 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11279 })
11280
11281 (define_insn_and_split "*eq<mode>_compare"
11282 [(set (match_operand:CC 5 "cc_reg_operand" "=y")
11283 (compare:CC
11284 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11285 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11286 (const_int 0)))
11287 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11288 (eq:P (match_dup 1) (match_dup 2)))
11289 (clobber (match_scratch:P 3 "=r"))
11290 (clobber (match_scratch:P 4 "=r"))]
11291 ""
11292 "#"
11293 "reload_completed"
11294 [(set (match_dup 3)
11295 (clz:P (match_dup 4)))
11296 (parallel [(set (match_dup 5)
11297 (compare:CC (lshiftrt:P (match_dup 3) (match_dup 6))
11298 (const_int 0)))
11299 (set (match_dup 0)
11300 (lshiftrt:P (match_dup 3) (match_dup 6)))])]
11301 {
11302 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11303 {
11304 if (logical_operand (operands[2], <MODE>mode))
11305 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11306 gen_rtx_XOR (<MODE>mode,
11307 operands[1], operands[2])));
11308 else
11309 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11310 gen_rtx_PLUS (<MODE>mode, operands[1],
11311 negate_rtx (<MODE>mode,
11312 operands[2]))));
11313 }
11314 else
11315 operands[4] = operands[1];
11316
11317 operands[6] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11318 })
11319
11320 ;; We have insns of the form shown by the first define_insn below. If
11321 ;; there is something inside the comparison operation, we must split it.
11322 (define_split
11323 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11324 (plus:SI (match_operator 1 "comparison_operator"
11325 [(match_operand:SI 2 "" "")
11326 (match_operand:SI 3
11327 "reg_or_cint_operand" "")])
11328 (match_operand:SI 4 "gpc_reg_operand" "")))
11329 (clobber (match_operand:SI 5 "register_operand" ""))]
11330 "! gpc_reg_operand (operands[2], SImode)"
11331 [(set (match_dup 5) (match_dup 2))
11332 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11333 (match_dup 4)))])
11334
11335 (define_insn ""
11336 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11337 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11338 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11339 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11340 "TARGET_32BIT"
11341 "@
11342 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11343 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11344 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11345 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11346 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11347 [(set_attr "type" "three,two,three,three,three")
11348 (set_attr "length" "12,8,12,12,12")])
11349
11350 (define_insn ""
11351 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11352 (compare:CC
11353 (plus:SI
11354 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11355 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11356 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11357 (const_int 0)))
11358 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11359 "TARGET_32BIT"
11360 "@
11361 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11362 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11363 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11364 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11365 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11366 #
11367 #
11368 #
11369 #
11370 #"
11371 [(set_attr "type" "compare")
11372 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11373
11374 (define_split
11375 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11376 (compare:CC
11377 (plus:SI
11378 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11379 (match_operand:SI 2 "scc_eq_operand" ""))
11380 (match_operand:SI 3 "gpc_reg_operand" ""))
11381 (const_int 0)))
11382 (clobber (match_scratch:SI 4 ""))]
11383 "TARGET_32BIT && reload_completed"
11384 [(set (match_dup 4)
11385 (plus:SI (eq:SI (match_dup 1)
11386 (match_dup 2))
11387 (match_dup 3)))
11388 (set (match_dup 0)
11389 (compare:CC (match_dup 4)
11390 (const_int 0)))]
11391 "")
11392
11393 (define_insn ""
11394 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11395 (compare:CC
11396 (plus:SI
11397 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11398 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11399 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11400 (const_int 0)))
11401 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11402 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11403 "TARGET_32BIT"
11404 "@
11405 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11406 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11407 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11408 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11409 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11410 #
11411 #
11412 #
11413 #
11414 #"
11415 [(set_attr "type" "compare")
11416 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11417
11418 (define_split
11419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11420 (compare:CC
11421 (plus:SI
11422 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11423 (match_operand:SI 2 "scc_eq_operand" ""))
11424 (match_operand:SI 3 "gpc_reg_operand" ""))
11425 (const_int 0)))
11426 (set (match_operand:SI 0 "gpc_reg_operand" "")
11427 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11428 "TARGET_32BIT && reload_completed"
11429 [(set (match_dup 0)
11430 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11431 (set (match_dup 4)
11432 (compare:CC (match_dup 0)
11433 (const_int 0)))]
11434 "")
11435
11436 (define_insn ""
11437 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11438 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11439 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))]
11440 "TARGET_32BIT"
11441 "@
11442 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11443 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11444 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11445 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11446 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11447 [(set_attr "type" "three,two,three,three,three")
11448 (set_attr "length" "12,8,12,12,12")])
11449
11450 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11451 ;; since it nabs/sr is just as fast.
11452 (define_insn "*ne0"
11453 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11454 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11455 (const_int 31)))
11456 (clobber (match_scratch:SI 2 "=&r"))]
11457 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11458 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11459 [(set_attr "type" "two")
11460 (set_attr "length" "8")])
11461
11462 (define_insn ""
11463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11464 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11465 (const_int 63)))
11466 (clobber (match_scratch:DI 2 "=&r"))]
11467 "TARGET_64BIT"
11468 "addic %2,%1,-1\;subfe %0,%2,%1"
11469 [(set_attr "type" "two")
11470 (set_attr "length" "8")])
11471
11472 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11473 (define_insn ""
11474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11475 (plus:SI (lshiftrt:SI
11476 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11477 (const_int 31))
11478 (match_operand:SI 2 "gpc_reg_operand" "r")))
11479 (clobber (match_scratch:SI 3 "=&r"))]
11480 "TARGET_32BIT"
11481 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11482 [(set_attr "type" "two")
11483 (set_attr "length" "8")])
11484
11485 (define_insn ""
11486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11487 (plus:DI (lshiftrt:DI
11488 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11489 (const_int 63))
11490 (match_operand:DI 2 "gpc_reg_operand" "r")))
11491 (clobber (match_scratch:DI 3 "=&r"))]
11492 "TARGET_64BIT"
11493 "addic %3,%1,-1\;addze %0,%2"
11494 [(set_attr "type" "two")
11495 (set_attr "length" "8")])
11496
11497 (define_insn ""
11498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11499 (compare:CC
11500 (plus:SI (lshiftrt:SI
11501 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11502 (const_int 31))
11503 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11504 (const_int 0)))
11505 (clobber (match_scratch:SI 3 "=&r,&r"))
11506 (clobber (match_scratch:SI 4 "=X,&r"))]
11507 "TARGET_32BIT"
11508 "@
11509 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11510 #"
11511 [(set_attr "type" "compare")
11512 (set_attr "length" "8,12")])
11513
11514 (define_split
11515 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11516 (compare:CC
11517 (plus:SI (lshiftrt:SI
11518 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11519 (const_int 31))
11520 (match_operand:SI 2 "gpc_reg_operand" ""))
11521 (const_int 0)))
11522 (clobber (match_scratch:SI 3 ""))
11523 (clobber (match_scratch:SI 4 ""))]
11524 "TARGET_32BIT && reload_completed"
11525 [(parallel [(set (match_dup 3)
11526 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11527 (const_int 31))
11528 (match_dup 2)))
11529 (clobber (match_dup 4))])
11530 (set (match_dup 0)
11531 (compare:CC (match_dup 3)
11532 (const_int 0)))]
11533 "")
11534
11535 (define_insn ""
11536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11537 (compare:CC
11538 (plus:DI (lshiftrt:DI
11539 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11540 (const_int 63))
11541 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11542 (const_int 0)))
11543 (clobber (match_scratch:DI 3 "=&r,&r"))]
11544 "TARGET_64BIT"
11545 "@
11546 addic %3,%1,-1\;addze. %3,%2
11547 #"
11548 [(set_attr "type" "compare")
11549 (set_attr "length" "8,12")])
11550
11551 (define_split
11552 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11553 (compare:CC
11554 (plus:DI (lshiftrt:DI
11555 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11556 (const_int 63))
11557 (match_operand:DI 2 "gpc_reg_operand" ""))
11558 (const_int 0)))
11559 (clobber (match_scratch:DI 3 ""))]
11560 "TARGET_64BIT && reload_completed"
11561 [(set (match_dup 3)
11562 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11563 (const_int 63))
11564 (match_dup 2)))
11565 (set (match_dup 0)
11566 (compare:CC (match_dup 3)
11567 (const_int 0)))]
11568 "")
11569
11570 (define_insn ""
11571 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11572 (compare:CC
11573 (plus:SI (lshiftrt:SI
11574 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11575 (const_int 31))
11576 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11577 (const_int 0)))
11578 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11579 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11580 (match_dup 2)))
11581 (clobber (match_scratch:SI 3 "=&r,&r"))]
11582 "TARGET_32BIT"
11583 "@
11584 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11585 #"
11586 [(set_attr "type" "compare")
11587 (set_attr "length" "8,12")])
11588
11589 (define_split
11590 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11591 (compare:CC
11592 (plus:SI (lshiftrt:SI
11593 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11594 (const_int 31))
11595 (match_operand:SI 2 "gpc_reg_operand" ""))
11596 (const_int 0)))
11597 (set (match_operand:SI 0 "gpc_reg_operand" "")
11598 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11599 (match_dup 2)))
11600 (clobber (match_scratch:SI 3 ""))]
11601 "TARGET_32BIT && reload_completed"
11602 [(parallel [(set (match_dup 0)
11603 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11604 (match_dup 2)))
11605 (clobber (match_dup 3))])
11606 (set (match_dup 4)
11607 (compare:CC (match_dup 0)
11608 (const_int 0)))]
11609 "")
11610
11611 (define_insn ""
11612 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11613 (compare:CC
11614 (plus:DI (lshiftrt:DI
11615 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11616 (const_int 63))
11617 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11618 (const_int 0)))
11619 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11620 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11621 (match_dup 2)))
11622 (clobber (match_scratch:DI 3 "=&r,&r"))]
11623 "TARGET_64BIT"
11624 "@
11625 addic %3,%1,-1\;addze. %0,%2
11626 #"
11627 [(set_attr "type" "compare")
11628 (set_attr "length" "8,12")])
11629
11630 (define_split
11631 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11632 (compare:CC
11633 (plus:DI (lshiftrt:DI
11634 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11635 (const_int 63))
11636 (match_operand:DI 2 "gpc_reg_operand" ""))
11637 (const_int 0)))
11638 (set (match_operand:DI 0 "gpc_reg_operand" "")
11639 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11640 (match_dup 2)))
11641 (clobber (match_scratch:DI 3 ""))]
11642 "TARGET_64BIT && reload_completed"
11643 [(parallel [(set (match_dup 0)
11644 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11645 (match_dup 2)))
11646 (clobber (match_dup 3))])
11647 (set (match_dup 4)
11648 (compare:CC (match_dup 0)
11649 (const_int 0)))]
11650 "")
11651
11652 (define_insn ""
11653 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11654 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11655 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11656 (clobber (match_scratch:SI 3 "=r,X"))]
11657 "TARGET_POWER"
11658 "@
11659 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11660 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11661 [(set_attr "length" "12")])
11662
11663 (define_insn ""
11664 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11665 (compare:CC
11666 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11667 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11668 (const_int 0)))
11669 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11670 (le:SI (match_dup 1) (match_dup 2)))
11671 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11672 "TARGET_POWER"
11673 "@
11674 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11675 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11676 #
11677 #"
11678 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11679 (set_attr "length" "12,12,16,16")])
11680
11681 (define_split
11682 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11683 (compare:CC
11684 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11685 (match_operand:SI 2 "reg_or_short_operand" ""))
11686 (const_int 0)))
11687 (set (match_operand:SI 0 "gpc_reg_operand" "")
11688 (le:SI (match_dup 1) (match_dup 2)))
11689 (clobber (match_scratch:SI 3 ""))]
11690 "TARGET_POWER && reload_completed"
11691 [(parallel [(set (match_dup 0)
11692 (le:SI (match_dup 1) (match_dup 2)))
11693 (clobber (match_dup 3))])
11694 (set (match_dup 4)
11695 (compare:CC (match_dup 0)
11696 (const_int 0)))]
11697 "")
11698
11699 (define_insn ""
11700 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11701 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11702 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11703 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11704 "TARGET_POWER"
11705 "@
11706 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11707 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11708 [(set_attr "length" "12")])
11709
11710 (define_insn ""
11711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11712 (compare:CC
11713 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11714 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11715 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11716 (const_int 0)))
11717 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11718 "TARGET_POWER"
11719 "@
11720 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11721 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11722 #
11723 #"
11724 [(set_attr "type" "compare")
11725 (set_attr "length" "12,12,16,16")])
11726
11727 (define_split
11728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11729 (compare:CC
11730 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11731 (match_operand:SI 2 "reg_or_short_operand" ""))
11732 (match_operand:SI 3 "gpc_reg_operand" ""))
11733 (const_int 0)))
11734 (clobber (match_scratch:SI 4 ""))]
11735 "TARGET_POWER && reload_completed"
11736 [(set (match_dup 4)
11737 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11738 (match_dup 3)))
11739 (set (match_dup 0)
11740 (compare:CC (match_dup 4)
11741 (const_int 0)))]
11742 "")
11743
11744 (define_insn ""
11745 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11746 (compare:CC
11747 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11748 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11749 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11750 (const_int 0)))
11751 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11752 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11753 "TARGET_POWER"
11754 "@
11755 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11756 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11757 #
11758 #"
11759 [(set_attr "type" "compare")
11760 (set_attr "length" "12,12,16,16")])
11761
11762 (define_split
11763 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11764 (compare:CC
11765 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11766 (match_operand:SI 2 "reg_or_short_operand" ""))
11767 (match_operand:SI 3 "gpc_reg_operand" ""))
11768 (const_int 0)))
11769 (set (match_operand:SI 0 "gpc_reg_operand" "")
11770 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11771 "TARGET_POWER && reload_completed"
11772 [(set (match_dup 0)
11773 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11774 (set (match_dup 4)
11775 (compare:CC (match_dup 0)
11776 (const_int 0)))]
11777 "")
11778
11779 (define_insn ""
11780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11781 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11782 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11783 "TARGET_POWER"
11784 "@
11785 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11786 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11787 [(set_attr "length" "12")])
11788
11789 (define_insn ""
11790 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11791 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11792 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11793 "TARGET_32BIT"
11794 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11795 [(set_attr "type" "three")
11796 (set_attr "length" "12")])
11797
11798 (define_insn ""
11799 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11800 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11801 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11802 "TARGET_64BIT"
11803 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11804 [(set_attr "type" "three")
11805 (set_attr "length" "12")])
11806
11807 (define_insn ""
11808 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11809 (compare:CC
11810 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11811 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11812 (const_int 0)))
11813 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11814 (leu:DI (match_dup 1) (match_dup 2)))]
11815 "TARGET_64BIT"
11816 "@
11817 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11818 #"
11819 [(set_attr "type" "compare")
11820 (set_attr "length" "12,16")])
11821
11822 (define_split
11823 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11824 (compare:CC
11825 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11826 (match_operand:DI 2 "reg_or_short_operand" ""))
11827 (const_int 0)))
11828 (set (match_operand:DI 0 "gpc_reg_operand" "")
11829 (leu:DI (match_dup 1) (match_dup 2)))]
11830 "TARGET_64BIT && reload_completed"
11831 [(set (match_dup 0)
11832 (leu:DI (match_dup 1) (match_dup 2)))
11833 (set (match_dup 3)
11834 (compare:CC (match_dup 0)
11835 (const_int 0)))]
11836 "")
11837
11838 (define_insn ""
11839 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11840 (compare:CC
11841 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11842 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11843 (const_int 0)))
11844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11845 (leu:SI (match_dup 1) (match_dup 2)))]
11846 "TARGET_32BIT"
11847 "@
11848 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11849 #"
11850 [(set_attr "type" "compare")
11851 (set_attr "length" "12,16")])
11852
11853 (define_split
11854 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11855 (compare:CC
11856 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11857 (match_operand:SI 2 "reg_or_short_operand" ""))
11858 (const_int 0)))
11859 (set (match_operand:SI 0 "gpc_reg_operand" "")
11860 (leu:SI (match_dup 1) (match_dup 2)))]
11861 "TARGET_32BIT && reload_completed"
11862 [(set (match_dup 0)
11863 (leu:SI (match_dup 1) (match_dup 2)))
11864 (set (match_dup 3)
11865 (compare:CC (match_dup 0)
11866 (const_int 0)))]
11867 "")
11868
11869 (define_insn ""
11870 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11871 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11872 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11873 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11874 "TARGET_32BIT"
11875 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11876 [(set_attr "type" "two")
11877 (set_attr "length" "8")])
11878
11879 (define_insn ""
11880 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11881 (compare:CC
11882 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11883 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11884 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11885 (const_int 0)))
11886 (clobber (match_scratch:SI 4 "=&r,&r"))]
11887 "TARGET_32BIT"
11888 "@
11889 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11890 #"
11891 [(set_attr "type" "compare")
11892 (set_attr "length" "8,12")])
11893
11894 (define_split
11895 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11896 (compare:CC
11897 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11898 (match_operand:SI 2 "reg_or_short_operand" ""))
11899 (match_operand:SI 3 "gpc_reg_operand" ""))
11900 (const_int 0)))
11901 (clobber (match_scratch:SI 4 ""))]
11902 "TARGET_32BIT && reload_completed"
11903 [(set (match_dup 4)
11904 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11905 (match_dup 3)))
11906 (set (match_dup 0)
11907 (compare:CC (match_dup 4)
11908 (const_int 0)))]
11909 "")
11910
11911 (define_insn ""
11912 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11913 (compare:CC
11914 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11915 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11916 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11917 (const_int 0)))
11918 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11919 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11920 "TARGET_32BIT"
11921 "@
11922 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11923 #"
11924 [(set_attr "type" "compare")
11925 (set_attr "length" "8,12")])
11926
11927 (define_split
11928 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11929 (compare:CC
11930 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11931 (match_operand:SI 2 "reg_or_short_operand" ""))
11932 (match_operand:SI 3 "gpc_reg_operand" ""))
11933 (const_int 0)))
11934 (set (match_operand:SI 0 "gpc_reg_operand" "")
11935 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11936 "TARGET_32BIT && reload_completed"
11937 [(set (match_dup 0)
11938 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11939 (set (match_dup 4)
11940 (compare:CC (match_dup 0)
11941 (const_int 0)))]
11942 "")
11943
11944 (define_insn ""
11945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11946 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11947 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11948 "TARGET_32BIT"
11949 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11950 [(set_attr "type" "three")
11951 (set_attr "length" "12")])
11952
11953 (define_insn ""
11954 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11955 (and:SI (neg:SI
11956 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11957 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11958 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11959 "TARGET_32BIT"
11960 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
11961 [(set_attr "type" "three")
11962 (set_attr "length" "12")])
11963
11964 (define_insn ""
11965 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11966 (compare:CC
11967 (and:SI (neg:SI
11968 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11969 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11970 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11971 (const_int 0)))
11972 (clobber (match_scratch:SI 4 "=&r,&r"))]
11973 "TARGET_32BIT"
11974 "@
11975 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11976 #"
11977 [(set_attr "type" "compare")
11978 (set_attr "length" "12,16")])
11979
11980 (define_split
11981 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11982 (compare:CC
11983 (and:SI (neg:SI
11984 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11985 (match_operand:SI 2 "reg_or_short_operand" "")))
11986 (match_operand:SI 3 "gpc_reg_operand" ""))
11987 (const_int 0)))
11988 (clobber (match_scratch:SI 4 ""))]
11989 "TARGET_32BIT && reload_completed"
11990 [(set (match_dup 4)
11991 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11992 (match_dup 3)))
11993 (set (match_dup 0)
11994 (compare:CC (match_dup 4)
11995 (const_int 0)))]
11996 "")
11997
11998 (define_insn ""
11999 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12000 (compare:CC
12001 (and:SI (neg:SI
12002 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12003 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12004 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12005 (const_int 0)))
12006 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12007 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12008 "TARGET_32BIT"
12009 "@
12010 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12011 #"
12012 [(set_attr "type" "compare")
12013 (set_attr "length" "12,16")])
12014
12015 (define_split
12016 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12017 (compare:CC
12018 (and:SI (neg:SI
12019 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12020 (match_operand:SI 2 "reg_or_short_operand" "")))
12021 (match_operand:SI 3 "gpc_reg_operand" ""))
12022 (const_int 0)))
12023 (set (match_operand:SI 0 "gpc_reg_operand" "")
12024 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12025 "TARGET_32BIT && reload_completed"
12026 [(set (match_dup 0)
12027 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12028 (match_dup 3)))
12029 (set (match_dup 4)
12030 (compare:CC (match_dup 0)
12031 (const_int 0)))]
12032 "")
12033
12034 (define_insn ""
12035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12036 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12037 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12038 "TARGET_POWER"
12039 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12040 [(set_attr "length" "12")])
12041
12042 (define_insn ""
12043 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12044 (compare:CC
12045 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12046 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12047 (const_int 0)))
12048 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12049 (lt:SI (match_dup 1) (match_dup 2)))]
12050 "TARGET_POWER"
12051 "@
12052 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12053 #"
12054 [(set_attr "type" "delayed_compare")
12055 (set_attr "length" "12,16")])
12056
12057 (define_split
12058 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12059 (compare:CC
12060 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12061 (match_operand:SI 2 "reg_or_short_operand" ""))
12062 (const_int 0)))
12063 (set (match_operand:SI 0 "gpc_reg_operand" "")
12064 (lt:SI (match_dup 1) (match_dup 2)))]
12065 "TARGET_POWER && reload_completed"
12066 [(set (match_dup 0)
12067 (lt:SI (match_dup 1) (match_dup 2)))
12068 (set (match_dup 3)
12069 (compare:CC (match_dup 0)
12070 (const_int 0)))]
12071 "")
12072
12073 (define_insn ""
12074 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12075 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12076 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12077 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12078 "TARGET_POWER"
12079 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12080 [(set_attr "length" "12")])
12081
12082 (define_insn ""
12083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12084 (compare:CC
12085 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12086 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12087 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12088 (const_int 0)))
12089 (clobber (match_scratch:SI 4 "=&r,&r"))]
12090 "TARGET_POWER"
12091 "@
12092 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12093 #"
12094 [(set_attr "type" "compare")
12095 (set_attr "length" "12,16")])
12096
12097 (define_split
12098 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12099 (compare:CC
12100 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12101 (match_operand:SI 2 "reg_or_short_operand" ""))
12102 (match_operand:SI 3 "gpc_reg_operand" ""))
12103 (const_int 0)))
12104 (clobber (match_scratch:SI 4 ""))]
12105 "TARGET_POWER && reload_completed"
12106 [(set (match_dup 4)
12107 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12108 (match_dup 3)))
12109 (set (match_dup 0)
12110 (compare:CC (match_dup 4)
12111 (const_int 0)))]
12112 "")
12113
12114 (define_insn ""
12115 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12116 (compare:CC
12117 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12118 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12119 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12120 (const_int 0)))
12121 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12122 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12123 "TARGET_POWER"
12124 "@
12125 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12126 #"
12127 [(set_attr "type" "compare")
12128 (set_attr "length" "12,16")])
12129
12130 (define_split
12131 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12132 (compare:CC
12133 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12134 (match_operand:SI 2 "reg_or_short_operand" ""))
12135 (match_operand:SI 3 "gpc_reg_operand" ""))
12136 (const_int 0)))
12137 (set (match_operand:SI 0 "gpc_reg_operand" "")
12138 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12139 "TARGET_POWER && reload_completed"
12140 [(set (match_dup 0)
12141 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12142 (set (match_dup 4)
12143 (compare:CC (match_dup 0)
12144 (const_int 0)))]
12145 "")
12146
12147 (define_insn ""
12148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12149 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12150 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12151 "TARGET_POWER"
12152 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12153 [(set_attr "length" "12")])
12154
12155 (define_insn_and_split ""
12156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12157 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12158 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12159 "TARGET_32BIT"
12160 "#"
12161 "TARGET_32BIT"
12162 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12163 (set (match_dup 0) (neg:SI (match_dup 0)))]
12164 "")
12165
12166 (define_insn_and_split ""
12167 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12168 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12169 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12170 "TARGET_64BIT"
12171 "#"
12172 "TARGET_64BIT"
12173 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12174 (set (match_dup 0) (neg:DI (match_dup 0)))]
12175 "")
12176
12177 (define_insn ""
12178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12179 (compare:CC
12180 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12181 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12182 (const_int 0)))
12183 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12184 (ltu:SI (match_dup 1) (match_dup 2)))]
12185 "TARGET_32BIT"
12186 "@
12187 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12188 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12189 #
12190 #"
12191 [(set_attr "type" "compare")
12192 (set_attr "length" "12,12,16,16")])
12193
12194 (define_split
12195 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12196 (compare:CC
12197 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12198 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12199 (const_int 0)))
12200 (set (match_operand:SI 0 "gpc_reg_operand" "")
12201 (ltu:SI (match_dup 1) (match_dup 2)))]
12202 "TARGET_32BIT && reload_completed"
12203 [(set (match_dup 0)
12204 (ltu:SI (match_dup 1) (match_dup 2)))
12205 (set (match_dup 3)
12206 (compare:CC (match_dup 0)
12207 (const_int 0)))]
12208 "")
12209
12210 (define_insn_and_split ""
12211 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12212 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12213 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12214 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12215 "TARGET_32BIT"
12216 "#"
12217 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12218 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12219 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12220 "")
12221
12222 (define_insn_and_split ""
12223 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12224 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12225 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12226 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12227 "TARGET_64BIT"
12228 "#"
12229 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12230 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12231 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12232 "")
12233
12234 (define_insn ""
12235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12236 (compare:CC
12237 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12238 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12239 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12240 (const_int 0)))
12241 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12242 "TARGET_32BIT"
12243 "@
12244 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12245 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12246 #
12247 #"
12248 [(set_attr "type" "compare")
12249 (set_attr "length" "12,12,16,16")])
12250
12251 (define_split
12252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12253 (compare:CC
12254 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12255 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12256 (match_operand:SI 3 "gpc_reg_operand" ""))
12257 (const_int 0)))
12258 (clobber (match_scratch:SI 4 ""))]
12259 "TARGET_32BIT && reload_completed"
12260 [(set (match_dup 4)
12261 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12262 (match_dup 3)))
12263 (set (match_dup 0)
12264 (compare:CC (match_dup 4)
12265 (const_int 0)))]
12266 "")
12267
12268 (define_insn ""
12269 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12270 (compare:CC
12271 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12272 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12273 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12274 (const_int 0)))
12275 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12276 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12277 "TARGET_32BIT"
12278 "@
12279 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12280 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12281 #
12282 #"
12283 [(set_attr "type" "compare")
12284 (set_attr "length" "12,12,16,16")])
12285
12286 (define_split
12287 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12288 (compare:CC
12289 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12290 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12291 (match_operand:SI 3 "gpc_reg_operand" ""))
12292 (const_int 0)))
12293 (set (match_operand:SI 0 "gpc_reg_operand" "")
12294 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12295 "TARGET_32BIT && reload_completed"
12296 [(set (match_dup 0)
12297 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12298 (set (match_dup 4)
12299 (compare:CC (match_dup 0)
12300 (const_int 0)))]
12301 "")
12302
12303 (define_insn ""
12304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12305 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12306 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12307 "TARGET_32BIT"
12308 "@
12309 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12310 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12311 [(set_attr "type" "two")
12312 (set_attr "length" "8")])
12313
12314 (define_insn ""
12315 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12316 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12317 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12318 "TARGET_64BIT"
12319 "@
12320 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12321 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12322 [(set_attr "type" "two")
12323 (set_attr "length" "8")])
12324
12325 (define_insn ""
12326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12327 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12328 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12329 (clobber (match_scratch:SI 3 "=r"))]
12330 "TARGET_POWER"
12331 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12332 [(set_attr "length" "12")])
12333
12334 (define_insn ""
12335 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12336 (compare:CC
12337 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12338 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12339 (const_int 0)))
12340 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12341 (ge:SI (match_dup 1) (match_dup 2)))
12342 (clobber (match_scratch:SI 3 "=r,r"))]
12343 "TARGET_POWER"
12344 "@
12345 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12346 #"
12347 [(set_attr "type" "compare")
12348 (set_attr "length" "12,16")])
12349
12350 (define_split
12351 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12352 (compare:CC
12353 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12354 (match_operand:SI 2 "reg_or_short_operand" ""))
12355 (const_int 0)))
12356 (set (match_operand:SI 0 "gpc_reg_operand" "")
12357 (ge:SI (match_dup 1) (match_dup 2)))
12358 (clobber (match_scratch:SI 3 ""))]
12359 "TARGET_POWER && reload_completed"
12360 [(parallel [(set (match_dup 0)
12361 (ge:SI (match_dup 1) (match_dup 2)))
12362 (clobber (match_dup 3))])
12363 (set (match_dup 4)
12364 (compare:CC (match_dup 0)
12365 (const_int 0)))]
12366 "")
12367
12368 (define_insn ""
12369 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12370 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12371 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12372 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12373 "TARGET_POWER"
12374 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12375 [(set_attr "length" "12")])
12376
12377 (define_insn ""
12378 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12379 (compare:CC
12380 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12381 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12382 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12383 (const_int 0)))
12384 (clobber (match_scratch:SI 4 "=&r,&r"))]
12385 "TARGET_POWER"
12386 "@
12387 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12388 #"
12389 [(set_attr "type" "compare")
12390 (set_attr "length" "12,16")])
12391
12392 (define_split
12393 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12394 (compare:CC
12395 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12396 (match_operand:SI 2 "reg_or_short_operand" ""))
12397 (match_operand:SI 3 "gpc_reg_operand" ""))
12398 (const_int 0)))
12399 (clobber (match_scratch:SI 4 ""))]
12400 "TARGET_POWER && reload_completed"
12401 [(set (match_dup 4)
12402 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12403 (match_dup 3)))
12404 (set (match_dup 0)
12405 (compare:CC (match_dup 4)
12406 (const_int 0)))]
12407 "")
12408
12409 (define_insn ""
12410 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12411 (compare:CC
12412 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12413 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12414 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12415 (const_int 0)))
12416 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12417 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12418 "TARGET_POWER"
12419 "@
12420 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12421 #"
12422 [(set_attr "type" "compare")
12423 (set_attr "length" "12,16")])
12424
12425 (define_split
12426 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12427 (compare:CC
12428 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12429 (match_operand:SI 2 "reg_or_short_operand" ""))
12430 (match_operand:SI 3 "gpc_reg_operand" ""))
12431 (const_int 0)))
12432 (set (match_operand:SI 0 "gpc_reg_operand" "")
12433 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12434 "TARGET_POWER && reload_completed"
12435 [(set (match_dup 0)
12436 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12437 (set (match_dup 4)
12438 (compare:CC (match_dup 0)
12439 (const_int 0)))]
12440 "")
12441
12442 (define_insn ""
12443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12444 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12445 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12446 "TARGET_POWER"
12447 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12448 [(set_attr "length" "12")])
12449
12450 (define_insn ""
12451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12452 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12453 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12454 "TARGET_32BIT"
12455 "@
12456 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12457 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12458 [(set_attr "type" "three")
12459 (set_attr "length" "12")])
12460
12461 (define_insn ""
12462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12463 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12464 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12465 "TARGET_64BIT"
12466 "@
12467 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12468 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12469 [(set_attr "type" "three")
12470 (set_attr "length" "12")])
12471
12472 (define_insn ""
12473 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12474 (compare:CC
12475 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12476 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12477 (const_int 0)))
12478 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12479 (geu:SI (match_dup 1) (match_dup 2)))]
12480 "TARGET_32BIT"
12481 "@
12482 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12483 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12484 #
12485 #"
12486 [(set_attr "type" "compare")
12487 (set_attr "length" "12,12,16,16")])
12488
12489 (define_split
12490 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12491 (compare:CC
12492 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12493 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12494 (const_int 0)))
12495 (set (match_operand:SI 0 "gpc_reg_operand" "")
12496 (geu:SI (match_dup 1) (match_dup 2)))]
12497 "TARGET_32BIT && reload_completed"
12498 [(set (match_dup 0)
12499 (geu:SI (match_dup 1) (match_dup 2)))
12500 (set (match_dup 3)
12501 (compare:CC (match_dup 0)
12502 (const_int 0)))]
12503 "")
12504
12505 (define_insn ""
12506 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12507 (compare:CC
12508 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12509 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12510 (const_int 0)))
12511 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12512 (geu:DI (match_dup 1) (match_dup 2)))]
12513 "TARGET_64BIT"
12514 "@
12515 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12516 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12517 #
12518 #"
12519 [(set_attr "type" "compare")
12520 (set_attr "length" "12,12,16,16")])
12521
12522 (define_split
12523 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12524 (compare:CC
12525 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12526 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12527 (const_int 0)))
12528 (set (match_operand:DI 0 "gpc_reg_operand" "")
12529 (geu:DI (match_dup 1) (match_dup 2)))]
12530 "TARGET_64BIT && reload_completed"
12531 [(set (match_dup 0)
12532 (geu:DI (match_dup 1) (match_dup 2)))
12533 (set (match_dup 3)
12534 (compare:CC (match_dup 0)
12535 (const_int 0)))]
12536 "")
12537
12538 (define_insn ""
12539 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12540 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12541 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12542 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12543 "TARGET_32BIT"
12544 "@
12545 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12546 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12547 [(set_attr "type" "two")
12548 (set_attr "length" "8")])
12549
12550 (define_insn ""
12551 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12552 (compare:CC
12553 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12554 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12555 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12556 (const_int 0)))
12557 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12558 "TARGET_32BIT"
12559 "@
12560 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12561 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12562 #
12563 #"
12564 [(set_attr "type" "compare")
12565 (set_attr "length" "8,8,12,12")])
12566
12567 (define_split
12568 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12569 (compare:CC
12570 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12571 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12572 (match_operand:SI 3 "gpc_reg_operand" ""))
12573 (const_int 0)))
12574 (clobber (match_scratch:SI 4 ""))]
12575 "TARGET_32BIT && reload_completed"
12576 [(set (match_dup 4)
12577 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12578 (match_dup 3)))
12579 (set (match_dup 0)
12580 (compare:CC (match_dup 4)
12581 (const_int 0)))]
12582 "")
12583
12584 (define_insn ""
12585 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12586 (compare:CC
12587 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12588 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12589 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12590 (const_int 0)))
12591 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12592 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12593 "TARGET_32BIT"
12594 "@
12595 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12596 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12597 #
12598 #"
12599 [(set_attr "type" "compare")
12600 (set_attr "length" "8,8,12,12")])
12601
12602 (define_split
12603 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12604 (compare:CC
12605 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12606 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12607 (match_operand:SI 3 "gpc_reg_operand" ""))
12608 (const_int 0)))
12609 (set (match_operand:SI 0 "gpc_reg_operand" "")
12610 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12611 "TARGET_32BIT && reload_completed"
12612 [(set (match_dup 0)
12613 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12614 (set (match_dup 4)
12615 (compare:CC (match_dup 0)
12616 (const_int 0)))]
12617 "")
12618
12619 (define_insn ""
12620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12621 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12622 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12623 "TARGET_32BIT"
12624 "@
12625 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12626 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12627 [(set_attr "type" "three")
12628 (set_attr "length" "12")])
12629
12630 (define_insn ""
12631 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12632 (and:SI (neg:SI
12633 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12634 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12635 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12636 "TARGET_32BIT"
12637 "@
12638 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12639 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12640 [(set_attr "type" "three")
12641 (set_attr "length" "12")])
12642
12643 (define_insn ""
12644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12645 (compare:CC
12646 (and:SI (neg:SI
12647 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12648 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12649 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12650 (const_int 0)))
12651 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12652 "TARGET_32BIT"
12653 "@
12654 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12655 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12656 #
12657 #"
12658 [(set_attr "type" "compare")
12659 (set_attr "length" "12,12,16,16")])
12660
12661 (define_split
12662 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12663 (compare:CC
12664 (and:SI (neg:SI
12665 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12666 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12667 (match_operand:SI 3 "gpc_reg_operand" ""))
12668 (const_int 0)))
12669 (clobber (match_scratch:SI 4 ""))]
12670 "TARGET_32BIT && reload_completed"
12671 [(set (match_dup 4)
12672 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12673 (match_dup 3)))
12674 (set (match_dup 0)
12675 (compare:CC (match_dup 4)
12676 (const_int 0)))]
12677 "")
12678
12679 (define_insn ""
12680 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12681 (compare:CC
12682 (and:SI (neg:SI
12683 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12684 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12685 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12686 (const_int 0)))
12687 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12688 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12689 "TARGET_32BIT"
12690 "@
12691 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12692 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12693 #
12694 #"
12695 [(set_attr "type" "compare")
12696 (set_attr "length" "12,12,16,16")])
12697
12698 (define_split
12699 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12700 (compare:CC
12701 (and:SI (neg:SI
12702 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12703 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12704 (match_operand:SI 3 "gpc_reg_operand" ""))
12705 (const_int 0)))
12706 (set (match_operand:SI 0 "gpc_reg_operand" "")
12707 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12708 "TARGET_32BIT && reload_completed"
12709 [(set (match_dup 0)
12710 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12711 (set (match_dup 4)
12712 (compare:CC (match_dup 0)
12713 (const_int 0)))]
12714 "")
12715
12716 (define_insn ""
12717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12718 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12719 (const_int 0)))]
12720 "TARGET_32BIT"
12721 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12722 [(set_attr "type" "three")
12723 (set_attr "length" "12")])
12724
12725 (define_insn ""
12726 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12727 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12728 (const_int 0)))]
12729 "TARGET_64BIT"
12730 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12731 [(set_attr "type" "three")
12732 (set_attr "length" "12")])
12733
12734 (define_insn ""
12735 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12736 (compare:CC
12737 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12738 (const_int 0))
12739 (const_int 0)))
12740 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12741 (gt:SI (match_dup 1) (const_int 0)))]
12742 "TARGET_32BIT"
12743 "@
12744 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12745 #"
12746 [(set_attr "type" "delayed_compare")
12747 (set_attr "length" "12,16")])
12748
12749 (define_split
12750 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12751 (compare:CC
12752 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12753 (const_int 0))
12754 (const_int 0)))
12755 (set (match_operand:SI 0 "gpc_reg_operand" "")
12756 (gt:SI (match_dup 1) (const_int 0)))]
12757 "TARGET_32BIT && reload_completed"
12758 [(set (match_dup 0)
12759 (gt:SI (match_dup 1) (const_int 0)))
12760 (set (match_dup 2)
12761 (compare:CC (match_dup 0)
12762 (const_int 0)))]
12763 "")
12764
12765 (define_insn ""
12766 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12767 (compare:CC
12768 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12769 (const_int 0))
12770 (const_int 0)))
12771 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12772 (gt:DI (match_dup 1) (const_int 0)))]
12773 "TARGET_64BIT"
12774 "@
12775 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12776 #"
12777 [(set_attr "type" "delayed_compare")
12778 (set_attr "length" "12,16")])
12779
12780 (define_split
12781 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12782 (compare:CC
12783 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12784 (const_int 0))
12785 (const_int 0)))
12786 (set (match_operand:DI 0 "gpc_reg_operand" "")
12787 (gt:DI (match_dup 1) (const_int 0)))]
12788 "TARGET_64BIT && reload_completed"
12789 [(set (match_dup 0)
12790 (gt:DI (match_dup 1) (const_int 0)))
12791 (set (match_dup 2)
12792 (compare:CC (match_dup 0)
12793 (const_int 0)))]
12794 "")
12795
12796 (define_insn ""
12797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12798 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12799 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12800 "TARGET_POWER"
12801 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12802 [(set_attr "length" "12")])
12803
12804 (define_insn ""
12805 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12806 (compare:CC
12807 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12808 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12809 (const_int 0)))
12810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12811 (gt:SI (match_dup 1) (match_dup 2)))]
12812 "TARGET_POWER"
12813 "@
12814 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12815 #"
12816 [(set_attr "type" "delayed_compare")
12817 (set_attr "length" "12,16")])
12818
12819 (define_split
12820 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12821 (compare:CC
12822 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12823 (match_operand:SI 2 "reg_or_short_operand" ""))
12824 (const_int 0)))
12825 (set (match_operand:SI 0 "gpc_reg_operand" "")
12826 (gt:SI (match_dup 1) (match_dup 2)))]
12827 "TARGET_POWER && reload_completed"
12828 [(set (match_dup 0)
12829 (gt:SI (match_dup 1) (match_dup 2)))
12830 (set (match_dup 3)
12831 (compare:CC (match_dup 0)
12832 (const_int 0)))]
12833 "")
12834
12835 (define_insn ""
12836 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12837 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12838 (const_int 0))
12839 (match_operand:SI 2 "gpc_reg_operand" "r")))]
12840 "TARGET_32BIT"
12841 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12842 [(set_attr "type" "three")
12843 (set_attr "length" "12")])
12844
12845 (define_insn ""
12846 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
12847 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12848 (const_int 0))
12849 (match_operand:DI 2 "gpc_reg_operand" "r")))]
12850 "TARGET_64BIT"
12851 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12852 [(set_attr "type" "three")
12853 (set_attr "length" "12")])
12854
12855 (define_insn ""
12856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12857 (compare:CC
12858 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12859 (const_int 0))
12860 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12861 (const_int 0)))
12862 (clobber (match_scratch:SI 3 "=&r,&r"))]
12863 "TARGET_32BIT"
12864 "@
12865 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12866 #"
12867 [(set_attr "type" "compare")
12868 (set_attr "length" "12,16")])
12869
12870 (define_split
12871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12872 (compare:CC
12873 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12874 (const_int 0))
12875 (match_operand:SI 2 "gpc_reg_operand" ""))
12876 (const_int 0)))
12877 (clobber (match_scratch:SI 3 ""))]
12878 "TARGET_32BIT && reload_completed"
12879 [(set (match_dup 3)
12880 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12881 (match_dup 2)))
12882 (set (match_dup 0)
12883 (compare:CC (match_dup 3)
12884 (const_int 0)))]
12885 "")
12886
12887 (define_insn ""
12888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12889 (compare:CC
12890 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12891 (const_int 0))
12892 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12893 (const_int 0)))
12894 (clobber (match_scratch:DI 3 "=&r,&r"))]
12895 "TARGET_64BIT"
12896 "@
12897 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12898 #"
12899 [(set_attr "type" "compare")
12900 (set_attr "length" "12,16")])
12901
12902 (define_split
12903 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12904 (compare:CC
12905 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12906 (const_int 0))
12907 (match_operand:DI 2 "gpc_reg_operand" ""))
12908 (const_int 0)))
12909 (clobber (match_scratch:DI 3 ""))]
12910 "TARGET_64BIT && reload_completed"
12911 [(set (match_dup 3)
12912 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12913 (match_dup 2)))
12914 (set (match_dup 0)
12915 (compare:CC (match_dup 3)
12916 (const_int 0)))]
12917 "")
12918
12919 (define_insn ""
12920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12921 (compare:CC
12922 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12923 (const_int 0))
12924 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12925 (const_int 0)))
12926 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12927 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12928 "TARGET_32BIT"
12929 "@
12930 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12931 #"
12932 [(set_attr "type" "compare")
12933 (set_attr "length" "12,16")])
12934
12935 (define_split
12936 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12937 (compare:CC
12938 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12939 (const_int 0))
12940 (match_operand:SI 2 "gpc_reg_operand" ""))
12941 (const_int 0)))
12942 (set (match_operand:SI 0 "gpc_reg_operand" "")
12943 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12944 "TARGET_32BIT && reload_completed"
12945 [(set (match_dup 0)
12946 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12947 (set (match_dup 3)
12948 (compare:CC (match_dup 0)
12949 (const_int 0)))]
12950 "")
12951
12952 (define_insn ""
12953 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12954 (compare:CC
12955 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12956 (const_int 0))
12957 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12958 (const_int 0)))
12959 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12960 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12961 "TARGET_64BIT"
12962 "@
12963 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12964 #"
12965 [(set_attr "type" "compare")
12966 (set_attr "length" "12,16")])
12967
12968 (define_split
12969 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12970 (compare:CC
12971 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12972 (const_int 0))
12973 (match_operand:DI 2 "gpc_reg_operand" ""))
12974 (const_int 0)))
12975 (set (match_operand:DI 0 "gpc_reg_operand" "")
12976 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12977 "TARGET_64BIT && reload_completed"
12978 [(set (match_dup 0)
12979 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12980 (set (match_dup 3)
12981 (compare:CC (match_dup 0)
12982 (const_int 0)))]
12983 "")
12984
12985 (define_insn ""
12986 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12987 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12988 (match_operand:SI 2 "reg_or_short_operand" "r"))
12989 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12990 "TARGET_POWER"
12991 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12992 [(set_attr "length" "12")])
12993
12994 (define_insn ""
12995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12996 (compare:CC
12997 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12998 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12999 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13000 (const_int 0)))
13001 (clobber (match_scratch:SI 4 "=&r,&r"))]
13002 "TARGET_POWER"
13003 "@
13004 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13005 #"
13006 [(set_attr "type" "compare")
13007 (set_attr "length" "12,16")])
13008
13009 (define_split
13010 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13011 (compare:CC
13012 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13013 (match_operand:SI 2 "reg_or_short_operand" ""))
13014 (match_operand:SI 3 "gpc_reg_operand" ""))
13015 (const_int 0)))
13016 (clobber (match_scratch:SI 4 ""))]
13017 "TARGET_POWER && reload_completed"
13018 [(set (match_dup 4)
13019 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13020 (set (match_dup 0)
13021 (compare:CC (match_dup 4)
13022 (const_int 0)))]
13023 "")
13024
13025 (define_insn ""
13026 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13027 (compare:CC
13028 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13029 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13030 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13031 (const_int 0)))
13032 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13033 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13034 "TARGET_POWER"
13035 "@
13036 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13037 #"
13038 [(set_attr "type" "compare")
13039 (set_attr "length" "12,16")])
13040
13041 (define_split
13042 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13043 (compare:CC
13044 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13045 (match_operand:SI 2 "reg_or_short_operand" ""))
13046 (match_operand:SI 3 "gpc_reg_operand" ""))
13047 (const_int 0)))
13048 (set (match_operand:SI 0 "gpc_reg_operand" "")
13049 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13050 "TARGET_POWER && reload_completed"
13051 [(set (match_dup 0)
13052 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13053 (set (match_dup 4)
13054 (compare:CC (match_dup 0)
13055 (const_int 0)))]
13056 "")
13057
13058 (define_insn ""
13059 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13060 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13061 (const_int 0))))]
13062 "TARGET_32BIT"
13063 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13064 [(set_attr "type" "three")
13065 (set_attr "length" "12")])
13066
13067 (define_insn ""
13068 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13069 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13070 (const_int 0))))]
13071 "TARGET_64BIT"
13072 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13073 [(set_attr "type" "three")
13074 (set_attr "length" "12")])
13075
13076 (define_insn ""
13077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13078 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13079 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13080 "TARGET_POWER"
13081 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13082 [(set_attr "length" "12")])
13083
13084 (define_insn_and_split ""
13085 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13086 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13087 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13088 "TARGET_32BIT"
13089 "#"
13090 "TARGET_32BIT"
13091 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13092 (set (match_dup 0) (neg:SI (match_dup 0)))]
13093 "")
13094
13095 (define_insn_and_split ""
13096 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13097 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13098 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13099 "TARGET_64BIT"
13100 "#"
13101 "TARGET_64BIT"
13102 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13103 (set (match_dup 0) (neg:DI (match_dup 0)))]
13104 "")
13105
13106 (define_insn ""
13107 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13108 (compare:CC
13109 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13110 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13111 (const_int 0)))
13112 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13113 (gtu:SI (match_dup 1) (match_dup 2)))]
13114 "TARGET_32BIT"
13115 "@
13116 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13117 #"
13118 [(set_attr "type" "compare")
13119 (set_attr "length" "12,16")])
13120
13121 (define_split
13122 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13123 (compare:CC
13124 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13125 (match_operand:SI 2 "reg_or_short_operand" ""))
13126 (const_int 0)))
13127 (set (match_operand:SI 0 "gpc_reg_operand" "")
13128 (gtu:SI (match_dup 1) (match_dup 2)))]
13129 "TARGET_32BIT && reload_completed"
13130 [(set (match_dup 0)
13131 (gtu:SI (match_dup 1) (match_dup 2)))
13132 (set (match_dup 3)
13133 (compare:CC (match_dup 0)
13134 (const_int 0)))]
13135 "")
13136
13137 (define_insn ""
13138 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13139 (compare:CC
13140 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13141 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13142 (const_int 0)))
13143 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13144 (gtu:DI (match_dup 1) (match_dup 2)))]
13145 "TARGET_64BIT"
13146 "@
13147 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13148 #"
13149 [(set_attr "type" "compare")
13150 (set_attr "length" "12,16")])
13151
13152 (define_split
13153 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13154 (compare:CC
13155 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13156 (match_operand:DI 2 "reg_or_short_operand" ""))
13157 (const_int 0)))
13158 (set (match_operand:DI 0 "gpc_reg_operand" "")
13159 (gtu:DI (match_dup 1) (match_dup 2)))]
13160 "TARGET_64BIT && reload_completed"
13161 [(set (match_dup 0)
13162 (gtu:DI (match_dup 1) (match_dup 2)))
13163 (set (match_dup 3)
13164 (compare:CC (match_dup 0)
13165 (const_int 0)))]
13166 "")
13167
13168 (define_insn_and_split ""
13169 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13170 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13171 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13172 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13173 "TARGET_32BIT"
13174 "#"
13175 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13176 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13177 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13178 "")
13179
13180 (define_insn_and_split ""
13181 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13182 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13183 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13184 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13185 "TARGET_64BIT"
13186 "#"
13187 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13188 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13189 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13190 "")
13191
13192 (define_insn ""
13193 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13194 (compare:CC
13195 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13196 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13197 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13198 (const_int 0)))
13199 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13200 "TARGET_32BIT"
13201 "@
13202 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13203 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13204 #
13205 #"
13206 [(set_attr "type" "compare")
13207 (set_attr "length" "8,12,12,16")])
13208
13209 (define_split
13210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13211 (compare:CC
13212 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13213 (match_operand:SI 2 "reg_or_short_operand" ""))
13214 (match_operand:SI 3 "gpc_reg_operand" ""))
13215 (const_int 0)))
13216 (clobber (match_scratch:SI 4 ""))]
13217 "TARGET_32BIT && reload_completed"
13218 [(set (match_dup 4)
13219 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13220 (match_dup 3)))
13221 (set (match_dup 0)
13222 (compare:CC (match_dup 4)
13223 (const_int 0)))]
13224 "")
13225
13226 (define_insn ""
13227 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13228 (compare:CC
13229 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13230 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13231 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13232 (const_int 0)))
13233 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13234 "TARGET_64BIT"
13235 "@
13236 addic %4,%1,%k2\;addze. %4,%3
13237 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13238 #
13239 #"
13240 [(set_attr "type" "compare")
13241 (set_attr "length" "8,12,12,16")])
13242
13243 (define_split
13244 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13245 (compare:CC
13246 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13247 (match_operand:DI 2 "reg_or_short_operand" ""))
13248 (match_operand:DI 3 "gpc_reg_operand" ""))
13249 (const_int 0)))
13250 (clobber (match_scratch:DI 4 ""))]
13251 "TARGET_64BIT && reload_completed"
13252 [(set (match_dup 4)
13253 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13254 (match_dup 3)))
13255 (set (match_dup 0)
13256 (compare:CC (match_dup 4)
13257 (const_int 0)))]
13258 "")
13259
13260 (define_insn ""
13261 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13262 (compare:CC
13263 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13264 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13265 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13266 (const_int 0)))
13267 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13268 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13269 "TARGET_32BIT"
13270 "@
13271 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13272 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13273 #
13274 #"
13275 [(set_attr "type" "compare")
13276 (set_attr "length" "8,12,12,16")])
13277
13278 (define_split
13279 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13280 (compare:CC
13281 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13282 (match_operand:SI 2 "reg_or_short_operand" ""))
13283 (match_operand:SI 3 "gpc_reg_operand" ""))
13284 (const_int 0)))
13285 (set (match_operand:SI 0 "gpc_reg_operand" "")
13286 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13287 "TARGET_32BIT && reload_completed"
13288 [(set (match_dup 0)
13289 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13290 (set (match_dup 4)
13291 (compare:CC (match_dup 0)
13292 (const_int 0)))]
13293 "")
13294
13295 (define_insn ""
13296 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13297 (compare:CC
13298 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13299 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13300 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13301 (const_int 0)))
13302 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13303 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13304 "TARGET_64BIT"
13305 "@
13306 addic %0,%1,%k2\;addze. %0,%3
13307 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13308 #
13309 #"
13310 [(set_attr "type" "compare")
13311 (set_attr "length" "8,12,12,16")])
13312
13313 (define_split
13314 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13315 (compare:CC
13316 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13317 (match_operand:DI 2 "reg_or_short_operand" ""))
13318 (match_operand:DI 3 "gpc_reg_operand" ""))
13319 (const_int 0)))
13320 (set (match_operand:DI 0 "gpc_reg_operand" "")
13321 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13322 "TARGET_64BIT && reload_completed"
13323 [(set (match_dup 0)
13324 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13325 (set (match_dup 4)
13326 (compare:CC (match_dup 0)
13327 (const_int 0)))]
13328 "")
13329
13330 (define_insn ""
13331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13332 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13333 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13334 "TARGET_32BIT"
13335 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13336 [(set_attr "type" "two")
13337 (set_attr "length" "8")])
13338
13339 (define_insn ""
13340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13341 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13342 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13343 "TARGET_64BIT"
13344 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13345 [(set_attr "type" "two")
13346 (set_attr "length" "8")])
13347 \f
13348 ;; Define both directions of branch and return. If we need a reload
13349 ;; register, we'd rather use CR0 since it is much easier to copy a
13350 ;; register CC value to there.
13351
13352 (define_insn ""
13353 [(set (pc)
13354 (if_then_else (match_operator 1 "branch_comparison_operator"
13355 [(match_operand 2
13356 "cc_reg_operand" "y")
13357 (const_int 0)])
13358 (label_ref (match_operand 0 "" ""))
13359 (pc)))]
13360 ""
13361 "*
13362 {
13363 return output_cbranch (operands[1], \"%l0\", 0, insn);
13364 }"
13365 [(set_attr "type" "branch")])
13366
13367 (define_insn ""
13368 [(set (pc)
13369 (if_then_else (match_operator 0 "branch_comparison_operator"
13370 [(match_operand 1
13371 "cc_reg_operand" "y")
13372 (const_int 0)])
13373 (return)
13374 (pc)))]
13375 "direct_return ()"
13376 "*
13377 {
13378 return output_cbranch (operands[0], NULL, 0, insn);
13379 }"
13380 [(set_attr "type" "branch")
13381 (set_attr "length" "4")])
13382
13383 (define_insn ""
13384 [(set (pc)
13385 (if_then_else (match_operator 1 "branch_comparison_operator"
13386 [(match_operand 2
13387 "cc_reg_operand" "y")
13388 (const_int 0)])
13389 (pc)
13390 (label_ref (match_operand 0 "" ""))))]
13391 ""
13392 "*
13393 {
13394 return output_cbranch (operands[1], \"%l0\", 1, insn);
13395 }"
13396 [(set_attr "type" "branch")])
13397
13398 (define_insn ""
13399 [(set (pc)
13400 (if_then_else (match_operator 0 "branch_comparison_operator"
13401 [(match_operand 1
13402 "cc_reg_operand" "y")
13403 (const_int 0)])
13404 (pc)
13405 (return)))]
13406 "direct_return ()"
13407 "*
13408 {
13409 return output_cbranch (operands[0], NULL, 1, insn);
13410 }"
13411 [(set_attr "type" "branch")
13412 (set_attr "length" "4")])
13413
13414 ;; Logic on condition register values.
13415
13416 ; This pattern matches things like
13417 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13418 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13419 ; (const_int 1)))
13420 ; which are generated by the branch logic.
13421 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13422
13423 (define_insn "*cceq_ior_compare"
13424 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13425 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13426 [(match_operator:SI 2
13427 "branch_positive_comparison_operator"
13428 [(match_operand 3
13429 "cc_reg_operand" "y,y")
13430 (const_int 0)])
13431 (match_operator:SI 4
13432 "branch_positive_comparison_operator"
13433 [(match_operand 5
13434 "cc_reg_operand" "0,y")
13435 (const_int 0)])])
13436 (const_int 1)))]
13437 ""
13438 "cr%q1 %E0,%j2,%j4"
13439 [(set_attr "type" "cr_logical,delayed_cr")])
13440
13441 ; Why is the constant -1 here, but 1 in the previous pattern?
13442 ; Because ~1 has all but the low bit set.
13443 (define_insn ""
13444 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13445 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13446 [(not:SI (match_operator:SI 2
13447 "branch_positive_comparison_operator"
13448 [(match_operand 3
13449 "cc_reg_operand" "y,y")
13450 (const_int 0)]))
13451 (match_operator:SI 4
13452 "branch_positive_comparison_operator"
13453 [(match_operand 5
13454 "cc_reg_operand" "0,y")
13455 (const_int 0)])])
13456 (const_int -1)))]
13457 ""
13458 "cr%q1 %E0,%j2,%j4"
13459 [(set_attr "type" "cr_logical,delayed_cr")])
13460
13461 (define_insn "*cceq_rev_compare"
13462 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13463 (compare:CCEQ (match_operator:SI 1
13464 "branch_positive_comparison_operator"
13465 [(match_operand 2
13466 "cc_reg_operand" "0,y")
13467 (const_int 0)])
13468 (const_int 0)))]
13469 ""
13470 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13471 [(set_attr "type" "cr_logical,delayed_cr")])
13472
13473 ;; If we are comparing the result of two comparisons, this can be done
13474 ;; using creqv or crxor.
13475
13476 (define_insn_and_split ""
13477 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13478 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13479 [(match_operand 2 "cc_reg_operand" "y")
13480 (const_int 0)])
13481 (match_operator 3 "branch_comparison_operator"
13482 [(match_operand 4 "cc_reg_operand" "y")
13483 (const_int 0)])))]
13484 ""
13485 "#"
13486 ""
13487 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13488 (match_dup 5)))]
13489 "
13490 {
13491 int positive_1, positive_2;
13492
13493 positive_1 = branch_positive_comparison_operator (operands[1],
13494 GET_MODE (operands[1]));
13495 positive_2 = branch_positive_comparison_operator (operands[3],
13496 GET_MODE (operands[3]));
13497
13498 if (! positive_1)
13499 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13500 GET_CODE (operands[1])),
13501 SImode,
13502 operands[2], const0_rtx);
13503 else if (GET_MODE (operands[1]) != SImode)
13504 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13505 operands[2], const0_rtx);
13506
13507 if (! positive_2)
13508 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13509 GET_CODE (operands[3])),
13510 SImode,
13511 operands[4], const0_rtx);
13512 else if (GET_MODE (operands[3]) != SImode)
13513 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13514 operands[4], const0_rtx);
13515
13516 if (positive_1 == positive_2)
13517 {
13518 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13519 operands[5] = constm1_rtx;
13520 }
13521 else
13522 {
13523 operands[5] = const1_rtx;
13524 }
13525 }")
13526
13527 ;; Unconditional branch and return.
13528
13529 (define_insn "jump"
13530 [(set (pc)
13531 (label_ref (match_operand 0 "" "")))]
13532 ""
13533 "b %l0"
13534 [(set_attr "type" "branch")])
13535
13536 (define_insn "return"
13537 [(return)]
13538 "direct_return ()"
13539 "{br|blr}"
13540 [(set_attr "type" "jmpreg")])
13541
13542 (define_expand "indirect_jump"
13543 [(set (pc) (match_operand 0 "register_operand" ""))])
13544
13545 (define_insn "*indirect_jump<mode>"
13546 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13547 ""
13548 "@
13549 bctr
13550 {br|blr}"
13551 [(set_attr "type" "jmpreg")])
13552
13553 ;; Table jump for switch statements:
13554 (define_expand "tablejump"
13555 [(use (match_operand 0 "" ""))
13556 (use (label_ref (match_operand 1 "" "")))]
13557 ""
13558 "
13559 {
13560 if (TARGET_32BIT)
13561 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13562 else
13563 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13564 DONE;
13565 }")
13566
13567 (define_expand "tablejumpsi"
13568 [(set (match_dup 3)
13569 (plus:SI (match_operand:SI 0 "" "")
13570 (match_dup 2)))
13571 (parallel [(set (pc) (match_dup 3))
13572 (use (label_ref (match_operand 1 "" "")))])]
13573 "TARGET_32BIT"
13574 "
13575 { operands[0] = force_reg (SImode, operands[0]);
13576 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13577 operands[3] = gen_reg_rtx (SImode);
13578 }")
13579
13580 (define_expand "tablejumpdi"
13581 [(set (match_dup 4)
13582 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13583 (set (match_dup 3)
13584 (plus:DI (match_dup 4)
13585 (match_dup 2)))
13586 (parallel [(set (pc) (match_dup 3))
13587 (use (label_ref (match_operand 1 "" "")))])]
13588 "TARGET_64BIT"
13589 "
13590 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13591 operands[3] = gen_reg_rtx (DImode);
13592 operands[4] = gen_reg_rtx (DImode);
13593 }")
13594
13595 (define_insn ""
13596 [(set (pc)
13597 (match_operand:P 0 "register_operand" "c,*l"))
13598 (use (label_ref (match_operand 1 "" "")))]
13599 ""
13600 "@
13601 bctr
13602 {br|blr}"
13603 [(set_attr "type" "jmpreg")])
13604
13605 (define_insn "nop"
13606 [(const_int 0)]
13607 ""
13608 "{cror 0,0,0|nop}")
13609 \f
13610 ;; Define the subtract-one-and-jump insns, starting with the template
13611 ;; so loop.c knows what to generate.
13612
13613 (define_expand "doloop_end"
13614 [(use (match_operand 0 "" "")) ; loop pseudo
13615 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13616 (use (match_operand 2 "" "")) ; max iterations
13617 (use (match_operand 3 "" "")) ; loop level
13618 (use (match_operand 4 "" ""))] ; label
13619 ""
13620 "
13621 {
13622 /* Only use this on innermost loops. */
13623 if (INTVAL (operands[3]) > 1)
13624 FAIL;
13625 if (TARGET_64BIT)
13626 {
13627 if (GET_MODE (operands[0]) != DImode)
13628 FAIL;
13629 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13630 }
13631 else
13632 {
13633 if (GET_MODE (operands[0]) != SImode)
13634 FAIL;
13635 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13636 }
13637 DONE;
13638 }")
13639
13640 (define_expand "ctr<mode>"
13641 [(parallel [(set (pc)
13642 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13643 (const_int 1))
13644 (label_ref (match_operand 1 "" ""))
13645 (pc)))
13646 (set (match_dup 0)
13647 (plus:P (match_dup 0)
13648 (const_int -1)))
13649 (clobber (match_scratch:CC 2 ""))
13650 (clobber (match_scratch:P 3 ""))])]
13651 ""
13652 "")
13653
13654 ;; We need to be able to do this for any operand, including MEM, or we
13655 ;; will cause reload to blow up since we don't allow output reloads on
13656 ;; JUMP_INSNs.
13657 ;; For the length attribute to be calculated correctly, the
13658 ;; label MUST be operand 0.
13659
13660 (define_insn "*ctr<mode>_internal1"
13661 [(set (pc)
13662 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13663 (const_int 1))
13664 (label_ref (match_operand 0 "" ""))
13665 (pc)))
13666 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13667 (plus:P (match_dup 1)
13668 (const_int -1)))
13669 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13670 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13671 ""
13672 "*
13673 {
13674 if (which_alternative != 0)
13675 return \"#\";
13676 else if (get_attr_length (insn) == 4)
13677 return \"{bdn|bdnz} %l0\";
13678 else
13679 return \"bdz $+8\;b %l0\";
13680 }"
13681 [(set_attr "type" "branch")
13682 (set_attr "length" "*,12,16,16")])
13683
13684 (define_insn "*ctr<mode>_internal2"
13685 [(set (pc)
13686 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13687 (const_int 1))
13688 (pc)
13689 (label_ref (match_operand 0 "" ""))))
13690 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13691 (plus:P (match_dup 1)
13692 (const_int -1)))
13693 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13694 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13695 ""
13696 "*
13697 {
13698 if (which_alternative != 0)
13699 return \"#\";
13700 else if (get_attr_length (insn) == 4)
13701 return \"bdz %l0\";
13702 else
13703 return \"{bdn|bdnz} $+8\;b %l0\";
13704 }"
13705 [(set_attr "type" "branch")
13706 (set_attr "length" "*,12,16,16")])
13707
13708 ;; Similar but use EQ
13709
13710 (define_insn "*ctr<mode>_internal5"
13711 [(set (pc)
13712 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13713 (const_int 1))
13714 (label_ref (match_operand 0 "" ""))
13715 (pc)))
13716 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13717 (plus:P (match_dup 1)
13718 (const_int -1)))
13719 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13720 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13721 ""
13722 "*
13723 {
13724 if (which_alternative != 0)
13725 return \"#\";
13726 else if (get_attr_length (insn) == 4)
13727 return \"bdz %l0\";
13728 else
13729 return \"{bdn|bdnz} $+8\;b %l0\";
13730 }"
13731 [(set_attr "type" "branch")
13732 (set_attr "length" "*,12,16,16")])
13733
13734 (define_insn "*ctr<mode>_internal6"
13735 [(set (pc)
13736 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13737 (const_int 1))
13738 (pc)
13739 (label_ref (match_operand 0 "" ""))))
13740 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13741 (plus:P (match_dup 1)
13742 (const_int -1)))
13743 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13744 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13745 ""
13746 "*
13747 {
13748 if (which_alternative != 0)
13749 return \"#\";
13750 else if (get_attr_length (insn) == 4)
13751 return \"{bdn|bdnz} %l0\";
13752 else
13753 return \"bdz $+8\;b %l0\";
13754 }"
13755 [(set_attr "type" "branch")
13756 (set_attr "length" "*,12,16,16")])
13757
13758 ;; Now the splitters if we could not allocate the CTR register
13759
13760 (define_split
13761 [(set (pc)
13762 (if_then_else (match_operator 2 "comparison_operator"
13763 [(match_operand:P 1 "gpc_reg_operand" "")
13764 (const_int 1)])
13765 (match_operand 5 "" "")
13766 (match_operand 6 "" "")))
13767 (set (match_operand:P 0 "gpc_reg_operand" "")
13768 (plus:P (match_dup 1) (const_int -1)))
13769 (clobber (match_scratch:CC 3 ""))
13770 (clobber (match_scratch:P 4 ""))]
13771 "reload_completed"
13772 [(parallel [(set (match_dup 3)
13773 (compare:CC (plus:P (match_dup 1)
13774 (const_int -1))
13775 (const_int 0)))
13776 (set (match_dup 0)
13777 (plus:P (match_dup 1)
13778 (const_int -1)))])
13779 (set (pc) (if_then_else (match_dup 7)
13780 (match_dup 5)
13781 (match_dup 6)))]
13782 "
13783 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13784 operands[3], const0_rtx); }")
13785
13786 (define_split
13787 [(set (pc)
13788 (if_then_else (match_operator 2 "comparison_operator"
13789 [(match_operand:P 1 "gpc_reg_operand" "")
13790 (const_int 1)])
13791 (match_operand 5 "" "")
13792 (match_operand 6 "" "")))
13793 (set (match_operand:P 0 "nonimmediate_operand" "")
13794 (plus:P (match_dup 1) (const_int -1)))
13795 (clobber (match_scratch:CC 3 ""))
13796 (clobber (match_scratch:P 4 ""))]
13797 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13798 [(parallel [(set (match_dup 3)
13799 (compare:CC (plus:P (match_dup 1)
13800 (const_int -1))
13801 (const_int 0)))
13802 (set (match_dup 4)
13803 (plus:P (match_dup 1)
13804 (const_int -1)))])
13805 (set (match_dup 0)
13806 (match_dup 4))
13807 (set (pc) (if_then_else (match_dup 7)
13808 (match_dup 5)
13809 (match_dup 6)))]
13810 "
13811 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13812 operands[3], const0_rtx); }")
13813 \f
13814 (define_insn "trap"
13815 [(trap_if (const_int 1) (const_int 0))]
13816 ""
13817 "{t 31,0,0|trap}")
13818
13819 (define_expand "conditional_trap"
13820 [(trap_if (match_operator 0 "trap_comparison_operator"
13821 [(match_dup 2) (match_dup 3)])
13822 (match_operand 1 "const_int_operand" ""))]
13823 ""
13824 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13825 operands[2] = rs6000_compare_op0;
13826 operands[3] = rs6000_compare_op1;")
13827
13828 (define_insn ""
13829 [(trap_if (match_operator 0 "trap_comparison_operator"
13830 [(match_operand:GPR 1 "register_operand" "r")
13831 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13832 (const_int 0))]
13833 ""
13834 "{t|t<wd>}%V0%I2 %1,%2")
13835 \f
13836 ;; Insns related to generating the function prologue and epilogue.
13837
13838 (define_expand "prologue"
13839 [(use (const_int 0))]
13840 "TARGET_SCHED_PROLOG"
13841 "
13842 {
13843 rs6000_emit_prologue ();
13844 DONE;
13845 }")
13846
13847 (define_insn "*movesi_from_cr_one"
13848 [(match_parallel 0 "mfcr_operation"
13849 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13850 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13851 (match_operand 3 "immediate_operand" "n")]
13852 UNSPEC_MOVESI_FROM_CR))])]
13853 "TARGET_MFCRF"
13854 "*
13855 {
13856 int mask = 0;
13857 int i;
13858 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13859 {
13860 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13861 operands[4] = GEN_INT (mask);
13862 output_asm_insn (\"mfcr %1,%4\", operands);
13863 }
13864 return \"\";
13865 }"
13866 [(set_attr "type" "mfcrf")])
13867
13868 (define_insn "movesi_from_cr"
13869 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13870 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13871 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13872 UNSPEC_MOVESI_FROM_CR))]
13873 ""
13874 "mfcr %0"
13875 [(set_attr "type" "mfcr")])
13876
13877 (define_insn "*stmw"
13878 [(match_parallel 0 "stmw_operation"
13879 [(set (match_operand:SI 1 "memory_operand" "=m")
13880 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13881 "TARGET_MULTIPLE"
13882 "{stm|stmw} %2,%1")
13883
13884 (define_insn "*save_fpregs_<mode>"
13885 [(match_parallel 0 "any_parallel_operand"
13886 [(clobber (match_operand:P 1 "register_operand" "=l"))
13887 (use (match_operand:P 2 "call_operand" "s"))
13888 (set (match_operand:DF 3 "memory_operand" "=m")
13889 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13890 ""
13891 "bl %z2"
13892 [(set_attr "type" "branch")
13893 (set_attr "length" "4")])
13894
13895 ; These are to explain that changes to the stack pointer should
13896 ; not be moved over stores to stack memory.
13897 (define_insn "stack_tie"
13898 [(set (match_operand:BLK 0 "memory_operand" "+m")
13899 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13900 ""
13901 ""
13902 [(set_attr "length" "0")])
13903
13904
13905 (define_expand "epilogue"
13906 [(use (const_int 0))]
13907 "TARGET_SCHED_PROLOG"
13908 "
13909 {
13910 rs6000_emit_epilogue (FALSE);
13911 DONE;
13912 }")
13913
13914 ; On some processors, doing the mtcrf one CC register at a time is
13915 ; faster (like on the 604e). On others, doing them all at once is
13916 ; faster; for instance, on the 601 and 750.
13917
13918 (define_expand "movsi_to_cr_one"
13919 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13920 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13921 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13922 ""
13923 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13924
13925 (define_insn "*movsi_to_cr"
13926 [(match_parallel 0 "mtcrf_operation"
13927 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13928 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13929 (match_operand 3 "immediate_operand" "n")]
13930 UNSPEC_MOVESI_TO_CR))])]
13931 ""
13932 "*
13933 {
13934 int mask = 0;
13935 int i;
13936 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13937 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13938 operands[4] = GEN_INT (mask);
13939 return \"mtcrf %4,%2\";
13940 }"
13941 [(set_attr "type" "mtcr")])
13942
13943 (define_insn "*mtcrfsi"
13944 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13945 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13946 (match_operand 2 "immediate_operand" "n")]
13947 UNSPEC_MOVESI_TO_CR))]
13948 "GET_CODE (operands[0]) == REG
13949 && CR_REGNO_P (REGNO (operands[0]))
13950 && GET_CODE (operands[2]) == CONST_INT
13951 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13952 "mtcrf %R0,%1"
13953 [(set_attr "type" "mtcr")])
13954
13955 ; The load-multiple instructions have similar properties.
13956 ; Note that "load_multiple" is a name known to the machine-independent
13957 ; code that actually corresponds to the powerpc load-string.
13958
13959 (define_insn "*lmw"
13960 [(match_parallel 0 "lmw_operation"
13961 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13962 (match_operand:SI 2 "memory_operand" "m"))])]
13963 "TARGET_MULTIPLE"
13964 "{lm|lmw} %1,%2")
13965
13966 (define_insn "*return_internal_<mode>"
13967 [(return)
13968 (use (match_operand:P 0 "register_operand" "lc"))]
13969 ""
13970 "b%T0"
13971 [(set_attr "type" "jmpreg")])
13972
13973 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13974 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13975
13976 (define_insn "*return_and_restore_fpregs_<mode>"
13977 [(match_parallel 0 "any_parallel_operand"
13978 [(return)
13979 (use (match_operand:P 1 "register_operand" "l"))
13980 (use (match_operand:P 2 "call_operand" "s"))
13981 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13982 (match_operand:DF 4 "memory_operand" "m"))])]
13983 ""
13984 "b %z2")
13985
13986 ; This is used in compiling the unwind routines.
13987 (define_expand "eh_return"
13988 [(use (match_operand 0 "general_operand" ""))]
13989 ""
13990 "
13991 {
13992 if (TARGET_32BIT)
13993 emit_insn (gen_eh_set_lr_si (operands[0]));
13994 else
13995 emit_insn (gen_eh_set_lr_di (operands[0]));
13996 DONE;
13997 }")
13998
13999 ; We can't expand this before we know where the link register is stored.
14000 (define_insn "eh_set_lr_<mode>"
14001 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14002 UNSPECV_EH_RR)
14003 (clobber (match_scratch:P 1 "=&b"))]
14004 ""
14005 "#")
14006
14007 (define_split
14008 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14009 (clobber (match_scratch 1 ""))]
14010 "reload_completed"
14011 [(const_int 0)]
14012 "
14013 {
14014 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14015 DONE;
14016 }")
14017
14018 (define_insn "prefetch"
14019 [(prefetch (match_operand 0 "indexed_or_indirect_address" "p")
14020 (match_operand:SI 1 "const_int_operand" "n")
14021 (match_operand:SI 2 "const_int_operand" "n"))]
14022 "TARGET_POWERPC"
14023 "*
14024 {
14025 if (GET_CODE (operands[0]) == REG)
14026 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14027 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14028 }"
14029 [(set_attr "type" "load")])
14030 \f
14031
14032 (include "sync.md")
14033 (include "altivec.md")
14034 (include "spe.md")