projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
re PR target/19147 (invalid rlwinm patterns)
[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5
6 ;; This file is part of GCC.
7
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
12
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; UNSPEC usage
27 ;;
28
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit
54 ])
55
56 ;;
57 ;; UNSPEC_VOLATILE usage
58 ;;
59
60 (define_constants
61 [(UNSPECV_BLOCK 0)
62 (UNSPECV_EH_RR 9) ; eh_reg_restore
63 ])
64 \f
65 ;; Define an insn type attribute. This is used in function unit delay
66 ;; computations.
67 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
68 (const_string "integer"))
69
70 ;; Length (in bytes).
71 ; '(pc)' in the following doesn't include the instruction itself; it is
72 ; calculated as if the instruction had zero size.
73 (define_attr "length" ""
74 (if_then_else (eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
76 (const_int -32768))
77 (lt (minus (match_dup 0) (pc))
78 (const_int 32764)))
79 (const_int 4)
80 (const_int 8))
81 (const_int 4)))
82
83 ;; Processor type -- this attribute must exactly match the processor_type
84 ;; enumeration in rs6000.h.
85
86 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
87 (const (symbol_ref "rs6000_cpu_attr")))
88
89 (automata_option "ndfa")
90
91 (include "rios1.md")
92 (include "rios2.md")
93 (include "rs64.md")
94 (include "mpc.md")
95 (include "40x.md")
96 (include "440.md")
97 (include "603.md")
98 (include "6xx.md")
99 (include "7xx.md")
100 (include "7450.md")
101 (include "8540.md")
102 (include "power4.md")
103 (include "power5.md")
104 (include "darwin.md")
105
106 \f
107 ;; This mode macro allows :P to be used for patterns that operate on
108 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
109 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
110
111 ;; Start with fixed-point load and store insns. Here we put only the more
112 ;; complex forms. Basic data transfer is done later.
113
114 (define_expand "zero_extendqidi2"
115 [(set (match_operand:DI 0 "gpc_reg_operand" "")
116 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
117 "TARGET_POWERPC64"
118 "")
119
120 (define_insn ""
121 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
122 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
123 "TARGET_POWERPC64"
124 "@
125 lbz%U1%X1 %0,%1
126 rldicl %0,%1,0,56"
127 [(set_attr "type" "load,*")])
128
129 (define_insn ""
130 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
131 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
132 (const_int 0)))
133 (clobber (match_scratch:DI 2 "=r,r"))]
134 "TARGET_64BIT"
135 "@
136 rldicl. %2,%1,0,56
137 #"
138 [(set_attr "type" "compare")
139 (set_attr "length" "4,8")])
140
141 (define_split
142 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
143 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
144 (const_int 0)))
145 (clobber (match_scratch:DI 2 ""))]
146 "TARGET_POWERPC64 && reload_completed"
147 [(set (match_dup 2)
148 (zero_extend:DI (match_dup 1)))
149 (set (match_dup 0)
150 (compare:CC (match_dup 2)
151 (const_int 0)))]
152 "")
153
154 (define_insn ""
155 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
156 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
157 (const_int 0)))
158 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
159 (zero_extend:DI (match_dup 1)))]
160 "TARGET_64BIT"
161 "@
162 rldicl. %0,%1,0,56
163 #"
164 [(set_attr "type" "compare")
165 (set_attr "length" "4,8")])
166
167 (define_split
168 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
169 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
170 (const_int 0)))
171 (set (match_operand:DI 0 "gpc_reg_operand" "")
172 (zero_extend:DI (match_dup 1)))]
173 "TARGET_POWERPC64 && reload_completed"
174 [(set (match_dup 0)
175 (zero_extend:DI (match_dup 1)))
176 (set (match_dup 2)
177 (compare:CC (match_dup 0)
178 (const_int 0)))]
179 "")
180
181 (define_insn "extendqidi2"
182 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
183 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
184 "TARGET_POWERPC64"
185 "extsb %0,%1")
186
187 (define_insn ""
188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
189 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
190 (const_int 0)))
191 (clobber (match_scratch:DI 2 "=r,r"))]
192 "TARGET_64BIT"
193 "@
194 extsb. %2,%1
195 #"
196 [(set_attr "type" "compare")
197 (set_attr "length" "4,8")])
198
199 (define_split
200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
201 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
202 (const_int 0)))
203 (clobber (match_scratch:DI 2 ""))]
204 "TARGET_POWERPC64 && reload_completed"
205 [(set (match_dup 2)
206 (sign_extend:DI (match_dup 1)))
207 (set (match_dup 0)
208 (compare:CC (match_dup 2)
209 (const_int 0)))]
210 "")
211
212 (define_insn ""
213 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
214 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
215 (const_int 0)))
216 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
217 (sign_extend:DI (match_dup 1)))]
218 "TARGET_64BIT"
219 "@
220 extsb. %0,%1
221 #"
222 [(set_attr "type" "compare")
223 (set_attr "length" "4,8")])
224
225 (define_split
226 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
227 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
228 (const_int 0)))
229 (set (match_operand:DI 0 "gpc_reg_operand" "")
230 (sign_extend:DI (match_dup 1)))]
231 "TARGET_POWERPC64 && reload_completed"
232 [(set (match_dup 0)
233 (sign_extend:DI (match_dup 1)))
234 (set (match_dup 2)
235 (compare:CC (match_dup 0)
236 (const_int 0)))]
237 "")
238
239 (define_expand "zero_extendhidi2"
240 [(set (match_operand:DI 0 "gpc_reg_operand" "")
241 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
242 "TARGET_POWERPC64"
243 "")
244
245 (define_insn ""
246 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
247 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
248 "TARGET_POWERPC64"
249 "@
250 lhz%U1%X1 %0,%1
251 rldicl %0,%1,0,48"
252 [(set_attr "type" "load,*")])
253
254 (define_insn ""
255 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
256 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
257 (const_int 0)))
258 (clobber (match_scratch:DI 2 "=r,r"))]
259 "TARGET_64BIT"
260 "@
261 rldicl. %2,%1,0,48
262 #"
263 [(set_attr "type" "compare")
264 (set_attr "length" "4,8")])
265
266 (define_split
267 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
268 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
269 (const_int 0)))
270 (clobber (match_scratch:DI 2 ""))]
271 "TARGET_POWERPC64 && reload_completed"
272 [(set (match_dup 2)
273 (zero_extend:DI (match_dup 1)))
274 (set (match_dup 0)
275 (compare:CC (match_dup 2)
276 (const_int 0)))]
277 "")
278
279 (define_insn ""
280 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
281 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
282 (const_int 0)))
283 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
284 (zero_extend:DI (match_dup 1)))]
285 "TARGET_64BIT"
286 "@
287 rldicl. %0,%1,0,48
288 #"
289 [(set_attr "type" "compare")
290 (set_attr "length" "4,8")])
291
292 (define_split
293 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
294 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
295 (const_int 0)))
296 (set (match_operand:DI 0 "gpc_reg_operand" "")
297 (zero_extend:DI (match_dup 1)))]
298 "TARGET_POWERPC64 && reload_completed"
299 [(set (match_dup 0)
300 (zero_extend:DI (match_dup 1)))
301 (set (match_dup 2)
302 (compare:CC (match_dup 0)
303 (const_int 0)))]
304 "")
305
306 (define_expand "extendhidi2"
307 [(set (match_operand:DI 0 "gpc_reg_operand" "")
308 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
309 "TARGET_POWERPC64"
310 "")
311
312 (define_insn ""
313 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
314 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
315 "TARGET_POWERPC64"
316 "@
317 lha%U1%X1 %0,%1
318 extsh %0,%1"
319 [(set_attr "type" "load_ext,*")])
320
321 (define_insn ""
322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
323 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
324 (const_int 0)))
325 (clobber (match_scratch:DI 2 "=r,r"))]
326 "TARGET_64BIT"
327 "@
328 extsh. %2,%1
329 #"
330 [(set_attr "type" "compare")
331 (set_attr "length" "4,8")])
332
333 (define_split
334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
335 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
336 (const_int 0)))
337 (clobber (match_scratch:DI 2 ""))]
338 "TARGET_POWERPC64 && reload_completed"
339 [(set (match_dup 2)
340 (sign_extend:DI (match_dup 1)))
341 (set (match_dup 0)
342 (compare:CC (match_dup 2)
343 (const_int 0)))]
344 "")
345
346 (define_insn ""
347 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
348 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
349 (const_int 0)))
350 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
351 (sign_extend:DI (match_dup 1)))]
352 "TARGET_64BIT"
353 "@
354 extsh. %0,%1
355 #"
356 [(set_attr "type" "compare")
357 (set_attr "length" "4,8")])
358
359 (define_split
360 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
361 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
362 (const_int 0)))
363 (set (match_operand:DI 0 "gpc_reg_operand" "")
364 (sign_extend:DI (match_dup 1)))]
365 "TARGET_POWERPC64 && reload_completed"
366 [(set (match_dup 0)
367 (sign_extend:DI (match_dup 1)))
368 (set (match_dup 2)
369 (compare:CC (match_dup 0)
370 (const_int 0)))]
371 "")
372
373 (define_expand "zero_extendsidi2"
374 [(set (match_operand:DI 0 "gpc_reg_operand" "")
375 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
376 "TARGET_POWERPC64"
377 "")
378
379 (define_insn ""
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
381 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
382 "TARGET_POWERPC64"
383 "@
384 lwz%U1%X1 %0,%1
385 rldicl %0,%1,0,32"
386 [(set_attr "type" "load,*")])
387
388 (define_insn ""
389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
390 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
391 (const_int 0)))
392 (clobber (match_scratch:DI 2 "=r,r"))]
393 "TARGET_64BIT"
394 "@
395 rldicl. %2,%1,0,32
396 #"
397 [(set_attr "type" "compare")
398 (set_attr "length" "4,8")])
399
400 (define_split
401 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
402 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
403 (const_int 0)))
404 (clobber (match_scratch:DI 2 ""))]
405 "TARGET_POWERPC64 && reload_completed"
406 [(set (match_dup 2)
407 (zero_extend:DI (match_dup 1)))
408 (set (match_dup 0)
409 (compare:CC (match_dup 2)
410 (const_int 0)))]
411 "")
412
413 (define_insn ""
414 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
415 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
416 (const_int 0)))
417 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
418 (zero_extend:DI (match_dup 1)))]
419 "TARGET_64BIT"
420 "@
421 rldicl. %0,%1,0,32
422 #"
423 [(set_attr "type" "compare")
424 (set_attr "length" "4,8")])
425
426 (define_split
427 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
428 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
429 (const_int 0)))
430 (set (match_operand:DI 0 "gpc_reg_operand" "")
431 (zero_extend:DI (match_dup 1)))]
432 "TARGET_POWERPC64 && reload_completed"
433 [(set (match_dup 0)
434 (zero_extend:DI (match_dup 1)))
435 (set (match_dup 2)
436 (compare:CC (match_dup 0)
437 (const_int 0)))]
438 "")
439
440 (define_expand "extendsidi2"
441 [(set (match_operand:DI 0 "gpc_reg_operand" "")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
443 "TARGET_POWERPC64"
444 "")
445
446 (define_insn ""
447 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
448 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
449 "TARGET_POWERPC64"
450 "@
451 lwa%U1%X1 %0,%1
452 extsw %0,%1"
453 [(set_attr "type" "load_ext,*")])
454
455 (define_insn ""
456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
457 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
458 (const_int 0)))
459 (clobber (match_scratch:DI 2 "=r,r"))]
460 "TARGET_64BIT"
461 "@
462 extsw. %2,%1
463 #"
464 [(set_attr "type" "compare")
465 (set_attr "length" "4,8")])
466
467 (define_split
468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
469 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
470 (const_int 0)))
471 (clobber (match_scratch:DI 2 ""))]
472 "TARGET_POWERPC64 && reload_completed"
473 [(set (match_dup 2)
474 (sign_extend:DI (match_dup 1)))
475 (set (match_dup 0)
476 (compare:CC (match_dup 2)
477 (const_int 0)))]
478 "")
479
480 (define_insn ""
481 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
482 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
483 (const_int 0)))
484 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
485 (sign_extend:DI (match_dup 1)))]
486 "TARGET_64BIT"
487 "@
488 extsw. %0,%1
489 #"
490 [(set_attr "type" "compare")
491 (set_attr "length" "4,8")])
492
493 (define_split
494 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
495 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
496 (const_int 0)))
497 (set (match_operand:DI 0 "gpc_reg_operand" "")
498 (sign_extend:DI (match_dup 1)))]
499 "TARGET_POWERPC64 && reload_completed"
500 [(set (match_dup 0)
501 (sign_extend:DI (match_dup 1)))
502 (set (match_dup 2)
503 (compare:CC (match_dup 0)
504 (const_int 0)))]
505 "")
506
507 (define_expand "zero_extendqisi2"
508 [(set (match_operand:SI 0 "gpc_reg_operand" "")
509 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
510 ""
511 "")
512
513 (define_insn ""
514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
515 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
516 ""
517 "@
518 lbz%U1%X1 %0,%1
519 {rlinm|rlwinm} %0,%1,0,0xff"
520 [(set_attr "type" "load,*")])
521
522 (define_insn ""
523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
524 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
525 (const_int 0)))
526 (clobber (match_scratch:SI 2 "=r,r"))]
527 ""
528 "@
529 {andil.|andi.} %2,%1,0xff
530 #"
531 [(set_attr "type" "compare")
532 (set_attr "length" "4,8")])
533
534 (define_split
535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
536 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
537 (const_int 0)))
538 (clobber (match_scratch:SI 2 ""))]
539 "reload_completed"
540 [(set (match_dup 2)
541 (zero_extend:SI (match_dup 1)))
542 (set (match_dup 0)
543 (compare:CC (match_dup 2)
544 (const_int 0)))]
545 "")
546
547 (define_insn ""
548 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
549 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
550 (const_int 0)))
551 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
552 (zero_extend:SI (match_dup 1)))]
553 ""
554 "@
555 {andil.|andi.} %0,%1,0xff
556 #"
557 [(set_attr "type" "compare")
558 (set_attr "length" "4,8")])
559
560 (define_split
561 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
562 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
563 (const_int 0)))
564 (set (match_operand:SI 0 "gpc_reg_operand" "")
565 (zero_extend:SI (match_dup 1)))]
566 "reload_completed"
567 [(set (match_dup 0)
568 (zero_extend:SI (match_dup 1)))
569 (set (match_dup 2)
570 (compare:CC (match_dup 0)
571 (const_int 0)))]
572 "")
573
574 (define_expand "extendqisi2"
575 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
576 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
577 ""
578 "
579 {
580 if (TARGET_POWERPC)
581 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
582 else if (TARGET_POWER)
583 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
584 else
585 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
586 DONE;
587 }")
588
589 (define_insn "extendqisi2_ppc"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
591 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
592 "TARGET_POWERPC"
593 "extsb %0,%1")
594
595 (define_insn ""
596 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
597 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
598 (const_int 0)))
599 (clobber (match_scratch:SI 2 "=r,r"))]
600 "TARGET_POWERPC"
601 "@
602 extsb. %2,%1
603 #"
604 [(set_attr "type" "compare")
605 (set_attr "length" "4,8")])
606
607 (define_split
608 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
609 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
610 (const_int 0)))
611 (clobber (match_scratch:SI 2 ""))]
612 "TARGET_POWERPC && reload_completed"
613 [(set (match_dup 2)
614 (sign_extend:SI (match_dup 1)))
615 (set (match_dup 0)
616 (compare:CC (match_dup 2)
617 (const_int 0)))]
618 "")
619
620 (define_insn ""
621 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
622 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
623 (const_int 0)))
624 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
625 (sign_extend:SI (match_dup 1)))]
626 "TARGET_POWERPC"
627 "@
628 extsb. %0,%1
629 #"
630 [(set_attr "type" "compare")
631 (set_attr "length" "4,8")])
632
633 (define_split
634 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
635 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
636 (const_int 0)))
637 (set (match_operand:SI 0 "gpc_reg_operand" "")
638 (sign_extend:SI (match_dup 1)))]
639 "TARGET_POWERPC && reload_completed"
640 [(set (match_dup 0)
641 (sign_extend:SI (match_dup 1)))
642 (set (match_dup 2)
643 (compare:CC (match_dup 0)
644 (const_int 0)))]
645 "")
646
647 (define_expand "extendqisi2_power"
648 [(parallel [(set (match_dup 2)
649 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
650 (const_int 24)))
651 (clobber (scratch:SI))])
652 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
653 (ashiftrt:SI (match_dup 2)
654 (const_int 24)))
655 (clobber (scratch:SI))])]
656 "TARGET_POWER"
657 "
658 { operands[1] = gen_lowpart (SImode, operands[1]);
659 operands[2] = gen_reg_rtx (SImode); }")
660
661 (define_expand "extendqisi2_no_power"
662 [(set (match_dup 2)
663 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
664 (const_int 24)))
665 (set (match_operand:SI 0 "gpc_reg_operand" "")
666 (ashiftrt:SI (match_dup 2)
667 (const_int 24)))]
668 "! TARGET_POWER && ! TARGET_POWERPC"
669 "
670 { operands[1] = gen_lowpart (SImode, operands[1]);
671 operands[2] = gen_reg_rtx (SImode); }")
672
673 (define_expand "zero_extendqihi2"
674 [(set (match_operand:HI 0 "gpc_reg_operand" "")
675 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
676 ""
677 "")
678
679 (define_insn ""
680 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
681 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
682 ""
683 "@
684 lbz%U1%X1 %0,%1
685 {rlinm|rlwinm} %0,%1,0,0xff"
686 [(set_attr "type" "load,*")])
687
688 (define_insn ""
689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
690 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (clobber (match_scratch:HI 2 "=r,r"))]
693 ""
694 "@
695 {andil.|andi.} %2,%1,0xff
696 #"
697 [(set_attr "type" "compare")
698 (set_attr "length" "4,8")])
699
700 (define_split
701 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
702 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
703 (const_int 0)))
704 (clobber (match_scratch:HI 2 ""))]
705 "reload_completed"
706 [(set (match_dup 2)
707 (zero_extend:HI (match_dup 1)))
708 (set (match_dup 0)
709 (compare:CC (match_dup 2)
710 (const_int 0)))]
711 "")
712
713 (define_insn ""
714 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
715 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
716 (const_int 0)))
717 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
718 (zero_extend:HI (match_dup 1)))]
719 ""
720 "@
721 {andil.|andi.} %0,%1,0xff
722 #"
723 [(set_attr "type" "compare")
724 (set_attr "length" "4,8")])
725
726 (define_split
727 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
728 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
729 (const_int 0)))
730 (set (match_operand:HI 0 "gpc_reg_operand" "")
731 (zero_extend:HI (match_dup 1)))]
732 "reload_completed"
733 [(set (match_dup 0)
734 (zero_extend:HI (match_dup 1)))
735 (set (match_dup 2)
736 (compare:CC (match_dup 0)
737 (const_int 0)))]
738 "")
739
740 (define_expand "extendqihi2"
741 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
742 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
743 ""
744 "
745 {
746 if (TARGET_POWERPC)
747 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
748 else if (TARGET_POWER)
749 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
750 else
751 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
752 DONE;
753 }")
754
755 (define_insn "extendqihi2_ppc"
756 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
757 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
758 "TARGET_POWERPC"
759 "extsb %0,%1")
760
761 (define_insn ""
762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
763 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
764 (const_int 0)))
765 (clobber (match_scratch:HI 2 "=r,r"))]
766 "TARGET_POWERPC"
767 "@
768 extsb. %2,%1
769 #"
770 [(set_attr "type" "compare")
771 (set_attr "length" "4,8")])
772
773 (define_split
774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
775 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
776 (const_int 0)))
777 (clobber (match_scratch:HI 2 ""))]
778 "TARGET_POWERPC && reload_completed"
779 [(set (match_dup 2)
780 (sign_extend:HI (match_dup 1)))
781 (set (match_dup 0)
782 (compare:CC (match_dup 2)
783 (const_int 0)))]
784 "")
785
786 (define_insn ""
787 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
788 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
789 (const_int 0)))
790 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
791 (sign_extend:HI (match_dup 1)))]
792 "TARGET_POWERPC"
793 "@
794 extsb. %0,%1
795 #"
796 [(set_attr "type" "compare")
797 (set_attr "length" "4,8")])
798
799 (define_split
800 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
801 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
802 (const_int 0)))
803 (set (match_operand:HI 0 "gpc_reg_operand" "")
804 (sign_extend:HI (match_dup 1)))]
805 "TARGET_POWERPC && reload_completed"
806 [(set (match_dup 0)
807 (sign_extend:HI (match_dup 1)))
808 (set (match_dup 2)
809 (compare:CC (match_dup 0)
810 (const_int 0)))]
811 "")
812
813 (define_expand "extendqihi2_power"
814 [(parallel [(set (match_dup 2)
815 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
816 (const_int 24)))
817 (clobber (scratch:SI))])
818 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
819 (ashiftrt:SI (match_dup 2)
820 (const_int 24)))
821 (clobber (scratch:SI))])]
822 "TARGET_POWER"
823 "
824 { operands[0] = gen_lowpart (SImode, operands[0]);
825 operands[1] = gen_lowpart (SImode, operands[1]);
826 operands[2] = gen_reg_rtx (SImode); }")
827
828 (define_expand "extendqihi2_no_power"
829 [(set (match_dup 2)
830 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
831 (const_int 24)))
832 (set (match_operand:HI 0 "gpc_reg_operand" "")
833 (ashiftrt:SI (match_dup 2)
834 (const_int 24)))]
835 "! TARGET_POWER && ! TARGET_POWERPC"
836 "
837 { operands[0] = gen_lowpart (SImode, operands[0]);
838 operands[1] = gen_lowpart (SImode, operands[1]);
839 operands[2] = gen_reg_rtx (SImode); }")
840
841 (define_expand "zero_extendhisi2"
842 [(set (match_operand:SI 0 "gpc_reg_operand" "")
843 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
844 ""
845 "")
846
847 (define_insn ""
848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
849 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
850 ""
851 "@
852 lhz%U1%X1 %0,%1
853 {rlinm|rlwinm} %0,%1,0,0xffff"
854 [(set_attr "type" "load,*")])
855
856 (define_insn ""
857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
858 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
859 (const_int 0)))
860 (clobber (match_scratch:SI 2 "=r,r"))]
861 ""
862 "@
863 {andil.|andi.} %2,%1,0xffff
864 #"
865 [(set_attr "type" "compare")
866 (set_attr "length" "4,8")])
867
868 (define_split
869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
870 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
871 (const_int 0)))
872 (clobber (match_scratch:SI 2 ""))]
873 "reload_completed"
874 [(set (match_dup 2)
875 (zero_extend:SI (match_dup 1)))
876 (set (match_dup 0)
877 (compare:CC (match_dup 2)
878 (const_int 0)))]
879 "")
880
881 (define_insn ""
882 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
883 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
884 (const_int 0)))
885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
886 (zero_extend:SI (match_dup 1)))]
887 ""
888 "@
889 {andil.|andi.} %0,%1,0xffff
890 #"
891 [(set_attr "type" "compare")
892 (set_attr "length" "4,8")])
893
894 (define_split
895 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
896 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
897 (const_int 0)))
898 (set (match_operand:SI 0 "gpc_reg_operand" "")
899 (zero_extend:SI (match_dup 1)))]
900 "reload_completed"
901 [(set (match_dup 0)
902 (zero_extend:SI (match_dup 1)))
903 (set (match_dup 2)
904 (compare:CC (match_dup 0)
905 (const_int 0)))]
906 "")
907
908 (define_expand "extendhisi2"
909 [(set (match_operand:SI 0 "gpc_reg_operand" "")
910 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
911 ""
912 "")
913
914 (define_insn ""
915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
916 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
917 ""
918 "@
919 lha%U1%X1 %0,%1
920 {exts|extsh} %0,%1"
921 [(set_attr "type" "load_ext,*")])
922
923 (define_insn ""
924 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
925 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
926 (const_int 0)))
927 (clobber (match_scratch:SI 2 "=r,r"))]
928 ""
929 "@
930 {exts.|extsh.} %2,%1
931 #"
932 [(set_attr "type" "compare")
933 (set_attr "length" "4,8")])
934
935 (define_split
936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
937 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
938 (const_int 0)))
939 (clobber (match_scratch:SI 2 ""))]
940 "reload_completed"
941 [(set (match_dup 2)
942 (sign_extend:SI (match_dup 1)))
943 (set (match_dup 0)
944 (compare:CC (match_dup 2)
945 (const_int 0)))]
946 "")
947
948 (define_insn ""
949 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
950 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
951 (const_int 0)))
952 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
953 (sign_extend:SI (match_dup 1)))]
954 ""
955 "@
956 {exts.|extsh.} %0,%1
957 #"
958 [(set_attr "type" "compare")
959 (set_attr "length" "4,8")])
960 \f
961 (define_split
962 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
963 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
964 (const_int 0)))
965 (set (match_operand:SI 0 "gpc_reg_operand" "")
966 (sign_extend:SI (match_dup 1)))]
967 "reload_completed"
968 [(set (match_dup 0)
969 (sign_extend:SI (match_dup 1)))
970 (set (match_dup 2)
971 (compare:CC (match_dup 0)
972 (const_int 0)))]
973 "")
974
975 ;; Fixed-point arithmetic insns.
976
977 ;; Discourage ai/addic because of carry but provide it in an alternative
978 ;; allowing register zero as source.
979 (define_expand "addsi3"
980 [(set (match_operand:SI 0 "gpc_reg_operand" "")
981 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
982 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
983 ""
984 "
985 {
986 if (GET_CODE (operands[2]) == CONST_INT
987 && ! add_operand (operands[2], SImode))
988 {
989 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
990 ? operands[0] : gen_reg_rtx (SImode));
991
992 HOST_WIDE_INT val = INTVAL (operands[2]);
993 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
994 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
995
996 /* The ordering here is important for the prolog expander.
997 When space is allocated from the stack, adding 'low' first may
998 produce a temporary deallocation (which would be bad). */
999 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1000 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1001 DONE;
1002 }
1003 }")
1004
1005 (define_insn "*addsi3_internal1"
1006 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1007 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1008 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1009 ""
1010 "@
1011 {cax|add} %0,%1,%2
1012 {cal %0,%2(%1)|addi %0,%1,%2}
1013 {ai|addic} %0,%1,%2
1014 {cau|addis} %0,%1,%v2"
1015 [(set_attr "length" "4,4,4,4")])
1016
1017 (define_insn "addsi3_high"
1018 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1019 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1020 (high:SI (match_operand 2 "" ""))))]
1021 "TARGET_MACHO && !TARGET_64BIT"
1022 "{cau|addis} %0,%1,ha16(%2)"
1023 [(set_attr "length" "4")])
1024
1025 (define_insn "*addsi3_internal2"
1026 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1027 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1028 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1029 (const_int 0)))
1030 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1031 "TARGET_32BIT"
1032 "@
1033 {cax.|add.} %3,%1,%2
1034 {ai.|addic.} %3,%1,%2
1035 #
1036 #"
1037 [(set_attr "type" "fast_compare,compare,compare,compare")
1038 (set_attr "length" "4,4,8,8")])
1039
1040 (define_split
1041 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1042 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1043 (match_operand:SI 2 "reg_or_short_operand" ""))
1044 (const_int 0)))
1045 (clobber (match_scratch:SI 3 ""))]
1046 "TARGET_32BIT && reload_completed"
1047 [(set (match_dup 3)
1048 (plus:SI (match_dup 1)
1049 (match_dup 2)))
1050 (set (match_dup 0)
1051 (compare:CC (match_dup 3)
1052 (const_int 0)))]
1053 "")
1054
1055 (define_insn "*addsi3_internal3"
1056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1057 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1058 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1059 (const_int 0)))
1060 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1061 (plus:SI (match_dup 1)
1062 (match_dup 2)))]
1063 "TARGET_32BIT"
1064 "@
1065 {cax.|add.} %0,%1,%2
1066 {ai.|addic.} %0,%1,%2
1067 #
1068 #"
1069 [(set_attr "type" "fast_compare,compare,compare,compare")
1070 (set_attr "length" "4,4,8,8")])
1071
1072 (define_split
1073 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1074 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1075 (match_operand:SI 2 "reg_or_short_operand" ""))
1076 (const_int 0)))
1077 (set (match_operand:SI 0 "gpc_reg_operand" "")
1078 (plus:SI (match_dup 1) (match_dup 2)))]
1079 "TARGET_32BIT && reload_completed"
1080 [(set (match_dup 0)
1081 (plus:SI (match_dup 1)
1082 (match_dup 2)))
1083 (set (match_dup 3)
1084 (compare:CC (match_dup 0)
1085 (const_int 0)))]
1086 "")
1087
1088 ;; Split an add that we can't do in one insn into two insns, each of which
1089 ;; does one 16-bit part. This is used by combine. Note that the low-order
1090 ;; add should be last in case the result gets used in an address.
1091
1092 (define_split
1093 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1094 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1095 (match_operand:SI 2 "non_add_cint_operand" "")))]
1096 ""
1097 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1098 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1099 "
1100 {
1101 HOST_WIDE_INT val = INTVAL (operands[2]);
1102 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1103 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1104
1105 operands[3] = GEN_INT (rest);
1106 operands[4] = GEN_INT (low);
1107 }")
1108
1109 (define_insn "one_cmplsi2"
1110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1111 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1112 ""
1113 "nor %0,%1,%1")
1114
1115 (define_insn ""
1116 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1117 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1118 (const_int 0)))
1119 (clobber (match_scratch:SI 2 "=r,r"))]
1120 "TARGET_32BIT"
1121 "@
1122 nor. %2,%1,%1
1123 #"
1124 [(set_attr "type" "compare")
1125 (set_attr "length" "4,8")])
1126
1127 (define_split
1128 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1129 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1130 (const_int 0)))
1131 (clobber (match_scratch:SI 2 ""))]
1132 "TARGET_32BIT && reload_completed"
1133 [(set (match_dup 2)
1134 (not:SI (match_dup 1)))
1135 (set (match_dup 0)
1136 (compare:CC (match_dup 2)
1137 (const_int 0)))]
1138 "")
1139
1140 (define_insn ""
1141 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1142 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1143 (const_int 0)))
1144 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1145 (not:SI (match_dup 1)))]
1146 "TARGET_32BIT"
1147 "@
1148 nor. %0,%1,%1
1149 #"
1150 [(set_attr "type" "compare")
1151 (set_attr "length" "4,8")])
1152
1153 (define_split
1154 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1155 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1156 (const_int 0)))
1157 (set (match_operand:SI 0 "gpc_reg_operand" "")
1158 (not:SI (match_dup 1)))]
1159 "TARGET_32BIT && reload_completed"
1160 [(set (match_dup 0)
1161 (not:SI (match_dup 1)))
1162 (set (match_dup 2)
1163 (compare:CC (match_dup 0)
1164 (const_int 0)))]
1165 "")
1166
1167 (define_insn ""
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1169 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1170 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1171 "! TARGET_POWERPC"
1172 "{sf%I1|subf%I1c} %0,%2,%1")
1173
1174 (define_insn ""
1175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1176 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1177 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1178 "TARGET_POWERPC"
1179 "@
1180 subf %0,%2,%1
1181 subfic %0,%2,%1")
1182
1183 (define_insn ""
1184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1185 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1186 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1187 (const_int 0)))
1188 (clobber (match_scratch:SI 3 "=r,r"))]
1189 "! TARGET_POWERPC"
1190 "@
1191 {sf.|subfc.} %3,%2,%1
1192 #"
1193 [(set_attr "type" "compare")
1194 (set_attr "length" "4,8")])
1195
1196 (define_insn ""
1197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1198 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1199 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1200 (const_int 0)))
1201 (clobber (match_scratch:SI 3 "=r,r"))]
1202 "TARGET_POWERPC && TARGET_32BIT"
1203 "@
1204 subf. %3,%2,%1
1205 #"
1206 [(set_attr "type" "fast_compare")
1207 (set_attr "length" "4,8")])
1208
1209 (define_split
1210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1211 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1212 (match_operand:SI 2 "gpc_reg_operand" ""))
1213 (const_int 0)))
1214 (clobber (match_scratch:SI 3 ""))]
1215 "TARGET_32BIT && reload_completed"
1216 [(set (match_dup 3)
1217 (minus:SI (match_dup 1)
1218 (match_dup 2)))
1219 (set (match_dup 0)
1220 (compare:CC (match_dup 3)
1221 (const_int 0)))]
1222 "")
1223
1224 (define_insn ""
1225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1226 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1227 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1228 (const_int 0)))
1229 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1230 (minus:SI (match_dup 1) (match_dup 2)))]
1231 "! TARGET_POWERPC"
1232 "@
1233 {sf.|subfc.} %0,%2,%1
1234 #"
1235 [(set_attr "type" "compare")
1236 (set_attr "length" "4,8")])
1237
1238 (define_insn ""
1239 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1240 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1241 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1242 (const_int 0)))
1243 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1244 (minus:SI (match_dup 1)
1245 (match_dup 2)))]
1246 "TARGET_POWERPC && TARGET_32BIT"
1247 "@
1248 subf. %0,%2,%1
1249 #"
1250 [(set_attr "type" "fast_compare")
1251 (set_attr "length" "4,8")])
1252
1253 (define_split
1254 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1255 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1256 (match_operand:SI 2 "gpc_reg_operand" ""))
1257 (const_int 0)))
1258 (set (match_operand:SI 0 "gpc_reg_operand" "")
1259 (minus:SI (match_dup 1)
1260 (match_dup 2)))]
1261 "TARGET_32BIT && reload_completed"
1262 [(set (match_dup 0)
1263 (minus:SI (match_dup 1)
1264 (match_dup 2)))
1265 (set (match_dup 3)
1266 (compare:CC (match_dup 0)
1267 (const_int 0)))]
1268 "")
1269
1270 (define_expand "subsi3"
1271 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1272 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1273 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1274 ""
1275 "
1276 {
1277 if (GET_CODE (operands[2]) == CONST_INT)
1278 {
1279 emit_insn (gen_addsi3 (operands[0], operands[1],
1280 negate_rtx (SImode, operands[2])));
1281 DONE;
1282 }
1283 }")
1284
1285 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1286 ;; instruction and some auxiliary computations. Then we just have a single
1287 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1288 ;; combine.
1289
1290 (define_expand "sminsi3"
1291 [(set (match_dup 3)
1292 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1293 (match_operand:SI 2 "reg_or_short_operand" ""))
1294 (const_int 0)
1295 (minus:SI (match_dup 2) (match_dup 1))))
1296 (set (match_operand:SI 0 "gpc_reg_operand" "")
1297 (minus:SI (match_dup 2) (match_dup 3)))]
1298 "TARGET_POWER || TARGET_ISEL"
1299 "
1300 {
1301 if (TARGET_ISEL)
1302 {
1303 operands[2] = force_reg (SImode, operands[2]);
1304 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1305 DONE;
1306 }
1307
1308 operands[3] = gen_reg_rtx (SImode);
1309 }")
1310
1311 (define_split
1312 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1313 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1314 (match_operand:SI 2 "reg_or_short_operand" "")))
1315 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1316 "TARGET_POWER"
1317 [(set (match_dup 3)
1318 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1319 (const_int 0)
1320 (minus:SI (match_dup 2) (match_dup 1))))
1321 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1322 "")
1323
1324 (define_expand "smaxsi3"
1325 [(set (match_dup 3)
1326 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1327 (match_operand:SI 2 "reg_or_short_operand" ""))
1328 (const_int 0)
1329 (minus:SI (match_dup 2) (match_dup 1))))
1330 (set (match_operand:SI 0 "gpc_reg_operand" "")
1331 (plus:SI (match_dup 3) (match_dup 1)))]
1332 "TARGET_POWER || TARGET_ISEL"
1333 "
1334 {
1335 if (TARGET_ISEL)
1336 {
1337 operands[2] = force_reg (SImode, operands[2]);
1338 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1339 DONE;
1340 }
1341 operands[3] = gen_reg_rtx (SImode);
1342 }")
1343
1344 (define_split
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1346 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1347 (match_operand:SI 2 "reg_or_short_operand" "")))
1348 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1349 "TARGET_POWER"
1350 [(set (match_dup 3)
1351 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1352 (const_int 0)
1353 (minus:SI (match_dup 2) (match_dup 1))))
1354 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1355 "")
1356
1357 (define_expand "uminsi3"
1358 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1359 (match_dup 5)))
1360 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1361 (match_dup 5)))
1362 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1363 (const_int 0)
1364 (minus:SI (match_dup 4) (match_dup 3))))
1365 (set (match_operand:SI 0 "gpc_reg_operand" "")
1366 (minus:SI (match_dup 2) (match_dup 3)))]
1367 "TARGET_POWER || TARGET_ISEL"
1368 "
1369 {
1370 if (TARGET_ISEL)
1371 {
1372 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1373 DONE;
1374 }
1375 operands[3] = gen_reg_rtx (SImode);
1376 operands[4] = gen_reg_rtx (SImode);
1377 operands[5] = GEN_INT (-2147483647 - 1);
1378 }")
1379
1380 (define_expand "umaxsi3"
1381 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1382 (match_dup 5)))
1383 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1384 (match_dup 5)))
1385 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1386 (const_int 0)
1387 (minus:SI (match_dup 4) (match_dup 3))))
1388 (set (match_operand:SI 0 "gpc_reg_operand" "")
1389 (plus:SI (match_dup 3) (match_dup 1)))]
1390 "TARGET_POWER || TARGET_ISEL"
1391 "
1392 {
1393 if (TARGET_ISEL)
1394 {
1395 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1396 DONE;
1397 }
1398 operands[3] = gen_reg_rtx (SImode);
1399 operands[4] = gen_reg_rtx (SImode);
1400 operands[5] = GEN_INT (-2147483647 - 1);
1401 }")
1402
1403 (define_insn ""
1404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1406 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1407 (const_int 0)
1408 (minus:SI (match_dup 2) (match_dup 1))))]
1409 "TARGET_POWER"
1410 "doz%I2 %0,%1,%2")
1411
1412 (define_insn ""
1413 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1414 (compare:CC
1415 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1416 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1417 (const_int 0)
1418 (minus:SI (match_dup 2) (match_dup 1)))
1419 (const_int 0)))
1420 (clobber (match_scratch:SI 3 "=r,r"))]
1421 "TARGET_POWER"
1422 "@
1423 doz%I2. %3,%1,%2
1424 #"
1425 [(set_attr "type" "delayed_compare")
1426 (set_attr "length" "4,8")])
1427
1428 (define_split
1429 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1430 (compare:CC
1431 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1432 (match_operand:SI 2 "reg_or_short_operand" ""))
1433 (const_int 0)
1434 (minus:SI (match_dup 2) (match_dup 1)))
1435 (const_int 0)))
1436 (clobber (match_scratch:SI 3 ""))]
1437 "TARGET_POWER && reload_completed"
1438 [(set (match_dup 3)
1439 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1440 (const_int 0)
1441 (minus:SI (match_dup 2) (match_dup 1))))
1442 (set (match_dup 0)
1443 (compare:CC (match_dup 3)
1444 (const_int 0)))]
1445 "")
1446
1447 (define_insn ""
1448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1449 (compare:CC
1450 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1451 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1452 (const_int 0)
1453 (minus:SI (match_dup 2) (match_dup 1)))
1454 (const_int 0)))
1455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1456 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1457 (const_int 0)
1458 (minus:SI (match_dup 2) (match_dup 1))))]
1459 "TARGET_POWER"
1460 "@
1461 doz%I2. %0,%1,%2
1462 #"
1463 [(set_attr "type" "delayed_compare")
1464 (set_attr "length" "4,8")])
1465
1466 (define_split
1467 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1468 (compare:CC
1469 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1470 (match_operand:SI 2 "reg_or_short_operand" ""))
1471 (const_int 0)
1472 (minus:SI (match_dup 2) (match_dup 1)))
1473 (const_int 0)))
1474 (set (match_operand:SI 0 "gpc_reg_operand" "")
1475 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1476 (const_int 0)
1477 (minus:SI (match_dup 2) (match_dup 1))))]
1478 "TARGET_POWER && reload_completed"
1479 [(set (match_dup 0)
1480 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1481 (const_int 0)
1482 (minus:SI (match_dup 2) (match_dup 1))))
1483 (set (match_dup 3)
1484 (compare:CC (match_dup 0)
1485 (const_int 0)))]
1486 "")
1487
1488 ;; We don't need abs with condition code because such comparisons should
1489 ;; never be done.
1490 (define_expand "abssi2"
1491 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1492 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1493 ""
1494 "
1495 {
1496 if (TARGET_ISEL)
1497 {
1498 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1499 DONE;
1500 }
1501 else if (! TARGET_POWER)
1502 {
1503 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1504 DONE;
1505 }
1506 }")
1507
1508 (define_insn "*abssi2_power"
1509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1510 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1511 "TARGET_POWER"
1512 "abs %0,%1")
1513
1514 (define_insn_and_split "abssi2_isel"
1515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1516 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1517 (clobber (match_scratch:SI 2 "=&b"))
1518 (clobber (match_scratch:CC 3 "=y"))]
1519 "TARGET_ISEL"
1520 "#"
1521 "&& reload_completed"
1522 [(set (match_dup 2) (neg:SI (match_dup 1)))
1523 (set (match_dup 3)
1524 (compare:CC (match_dup 1)
1525 (const_int 0)))
1526 (set (match_dup 0)
1527 (if_then_else:SI (ge (match_dup 3)
1528 (const_int 0))
1529 (match_dup 1)
1530 (match_dup 2)))]
1531 "")
1532
1533 (define_insn_and_split "abssi2_nopower"
1534 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1535 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1536 (clobber (match_scratch:SI 2 "=&r,&r"))]
1537 "! TARGET_POWER && ! TARGET_ISEL"
1538 "#"
1539 "&& reload_completed"
1540 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1541 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1542 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1543 "")
1544
1545 (define_insn "*nabs_power"
1546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1547 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1548 "TARGET_POWER"
1549 "nabs %0,%1")
1550
1551 (define_insn_and_split "*nabs_nopower"
1552 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1553 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1554 (clobber (match_scratch:SI 2 "=&r,&r"))]
1555 "! TARGET_POWER"
1556 "#"
1557 "&& reload_completed"
1558 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1559 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1560 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1561 "")
1562
1563 (define_insn "negsi2"
1564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1565 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1566 ""
1567 "neg %0,%1")
1568
1569 (define_insn ""
1570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1571 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1572 (const_int 0)))
1573 (clobber (match_scratch:SI 2 "=r,r"))]
1574 "TARGET_32BIT"
1575 "@
1576 neg. %2,%1
1577 #"
1578 [(set_attr "type" "fast_compare")
1579 (set_attr "length" "4,8")])
1580
1581 (define_split
1582 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1583 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1584 (const_int 0)))
1585 (clobber (match_scratch:SI 2 ""))]
1586 "TARGET_32BIT && reload_completed"
1587 [(set (match_dup 2)
1588 (neg:SI (match_dup 1)))
1589 (set (match_dup 0)
1590 (compare:CC (match_dup 2)
1591 (const_int 0)))]
1592 "")
1593
1594 (define_insn ""
1595 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1596 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1597 (const_int 0)))
1598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1599 (neg:SI (match_dup 1)))]
1600 "TARGET_32BIT"
1601 "@
1602 neg. %0,%1
1603 #"
1604 [(set_attr "type" "fast_compare")
1605 (set_attr "length" "4,8")])
1606
1607 (define_split
1608 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1609 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1610 (const_int 0)))
1611 (set (match_operand:SI 0 "gpc_reg_operand" "")
1612 (neg:SI (match_dup 1)))]
1613 "TARGET_32BIT && reload_completed"
1614 [(set (match_dup 0)
1615 (neg:SI (match_dup 1)))
1616 (set (match_dup 2)
1617 (compare:CC (match_dup 0)
1618 (const_int 0)))]
1619 "")
1620
1621 (define_insn "clzsi2"
1622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1623 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1624 ""
1625 "{cntlz|cntlzw} %0,%1")
1626
1627 (define_expand "ctzsi2"
1628 [(set (match_dup 2)
1629 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1630 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1631 (match_dup 2)))
1632 (clobber (scratch:CC))])
1633 (set (match_dup 4) (clz:SI (match_dup 3)))
1634 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1635 (minus:SI (const_int 31) (match_dup 4)))]
1636 ""
1637 {
1638 operands[2] = gen_reg_rtx (SImode);
1639 operands[3] = gen_reg_rtx (SImode);
1640 operands[4] = gen_reg_rtx (SImode);
1641 })
1642
1643 (define_expand "ffssi2"
1644 [(set (match_dup 2)
1645 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1646 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1647 (match_dup 2)))
1648 (clobber (scratch:CC))])
1649 (set (match_dup 4) (clz:SI (match_dup 3)))
1650 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1651 (minus:SI (const_int 32) (match_dup 4)))]
1652 ""
1653 {
1654 operands[2] = gen_reg_rtx (SImode);
1655 operands[3] = gen_reg_rtx (SImode);
1656 operands[4] = gen_reg_rtx (SImode);
1657 })
1658
1659 (define_expand "mulsi3"
1660 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1661 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1662 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1663 ""
1664 "
1665 {
1666 if (TARGET_POWER)
1667 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1668 else
1669 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1670 DONE;
1671 }")
1672
1673 (define_insn "mulsi3_mq"
1674 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1675 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1676 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1677 (clobber (match_scratch:SI 3 "=q,q"))]
1678 "TARGET_POWER"
1679 "@
1680 {muls|mullw} %0,%1,%2
1681 {muli|mulli} %0,%1,%2"
1682 [(set (attr "type")
1683 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1684 (const_string "imul3")
1685 (match_operand:SI 2 "short_cint_operand" "")
1686 (const_string "imul2")]
1687 (const_string "imul")))])
1688
1689 (define_insn "mulsi3_no_mq"
1690 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1691 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1692 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1693 "! TARGET_POWER"
1694 "@
1695 {muls|mullw} %0,%1,%2
1696 {muli|mulli} %0,%1,%2"
1697 [(set (attr "type")
1698 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1699 (const_string "imul3")
1700 (match_operand:SI 2 "short_cint_operand" "")
1701 (const_string "imul2")]
1702 (const_string "imul")))])
1703
1704 (define_insn "*mulsi3_mq_internal1"
1705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1706 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1707 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1708 (const_int 0)))
1709 (clobber (match_scratch:SI 3 "=r,r"))
1710 (clobber (match_scratch:SI 4 "=q,q"))]
1711 "TARGET_POWER"
1712 "@
1713 {muls.|mullw.} %3,%1,%2
1714 #"
1715 [(set_attr "type" "imul_compare")
1716 (set_attr "length" "4,8")])
1717
1718 (define_split
1719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1720 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1721 (match_operand:SI 2 "gpc_reg_operand" ""))
1722 (const_int 0)))
1723 (clobber (match_scratch:SI 3 ""))
1724 (clobber (match_scratch:SI 4 ""))]
1725 "TARGET_POWER && reload_completed"
1726 [(parallel [(set (match_dup 3)
1727 (mult:SI (match_dup 1) (match_dup 2)))
1728 (clobber (match_dup 4))])
1729 (set (match_dup 0)
1730 (compare:CC (match_dup 3)
1731 (const_int 0)))]
1732 "")
1733
1734 (define_insn "*mulsi3_no_mq_internal1"
1735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1736 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1737 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1738 (const_int 0)))
1739 (clobber (match_scratch:SI 3 "=r,r"))]
1740 "! TARGET_POWER"
1741 "@
1742 {muls.|mullw.} %3,%1,%2
1743 #"
1744 [(set_attr "type" "imul_compare")
1745 (set_attr "length" "4,8")])
1746
1747 (define_split
1748 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1749 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1750 (match_operand:SI 2 "gpc_reg_operand" ""))
1751 (const_int 0)))
1752 (clobber (match_scratch:SI 3 ""))]
1753 "! TARGET_POWER && reload_completed"
1754 [(set (match_dup 3)
1755 (mult:SI (match_dup 1) (match_dup 2)))
1756 (set (match_dup 0)
1757 (compare:CC (match_dup 3)
1758 (const_int 0)))]
1759 "")
1760
1761 (define_insn "*mulsi3_mq_internal2"
1762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1763 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1764 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1765 (const_int 0)))
1766 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1767 (mult:SI (match_dup 1) (match_dup 2)))
1768 (clobber (match_scratch:SI 4 "=q,q"))]
1769 "TARGET_POWER"
1770 "@
1771 {muls.|mullw.} %0,%1,%2
1772 #"
1773 [(set_attr "type" "imul_compare")
1774 (set_attr "length" "4,8")])
1775
1776 (define_split
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1779 (match_operand:SI 2 "gpc_reg_operand" ""))
1780 (const_int 0)))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (mult:SI (match_dup 1) (match_dup 2)))
1783 (clobber (match_scratch:SI 4 ""))]
1784 "TARGET_POWER && reload_completed"
1785 [(parallel [(set (match_dup 0)
1786 (mult:SI (match_dup 1) (match_dup 2)))
1787 (clobber (match_dup 4))])
1788 (set (match_dup 3)
1789 (compare:CC (match_dup 0)
1790 (const_int 0)))]
1791 "")
1792
1793 (define_insn "*mulsi3_no_mq_internal2"
1794 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1795 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1796 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1797 (const_int 0)))
1798 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1799 (mult:SI (match_dup 1) (match_dup 2)))]
1800 "! TARGET_POWER"
1801 "@
1802 {muls.|mullw.} %0,%1,%2
1803 #"
1804 [(set_attr "type" "imul_compare")
1805 (set_attr "length" "4,8")])
1806
1807 (define_split
1808 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1809 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1810 (match_operand:SI 2 "gpc_reg_operand" ""))
1811 (const_int 0)))
1812 (set (match_operand:SI 0 "gpc_reg_operand" "")
1813 (mult:SI (match_dup 1) (match_dup 2)))]
1814 "! TARGET_POWER && reload_completed"
1815 [(set (match_dup 0)
1816 (mult:SI (match_dup 1) (match_dup 2)))
1817 (set (match_dup 3)
1818 (compare:CC (match_dup 0)
1819 (const_int 0)))]
1820 "")
1821
1822 ;; Operand 1 is divided by operand 2; quotient goes to operand
1823 ;; 0 and remainder to operand 3.
1824 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1825
1826 (define_expand "divmodsi4"
1827 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1828 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1829 (match_operand:SI 2 "gpc_reg_operand" "")))
1830 (set (match_operand:SI 3 "register_operand" "")
1831 (mod:SI (match_dup 1) (match_dup 2)))])]
1832 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1833 "
1834 {
1835 if (! TARGET_POWER && ! TARGET_POWERPC)
1836 {
1837 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1838 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1839 emit_insn (gen_divss_call ());
1840 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1841 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1842 DONE;
1843 }
1844 }")
1845
1846 (define_insn "*divmodsi4_internal"
1847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1848 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1849 (match_operand:SI 2 "gpc_reg_operand" "r")))
1850 (set (match_operand:SI 3 "register_operand" "=q")
1851 (mod:SI (match_dup 1) (match_dup 2)))]
1852 "TARGET_POWER"
1853 "divs %0,%1,%2"
1854 [(set_attr "type" "idiv")])
1855
1856 (define_expand "udivsi3"
1857 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1858 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1859 (match_operand:SI 2 "gpc_reg_operand" "")))]
1860 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1861 "
1862 {
1863 if (! TARGET_POWER && ! TARGET_POWERPC)
1864 {
1865 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1866 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1867 emit_insn (gen_quous_call ());
1868 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1869 DONE;
1870 }
1871 else if (TARGET_POWER)
1872 {
1873 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1874 DONE;
1875 }
1876 }")
1877
1878 (define_insn "udivsi3_mq"
1879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1880 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1881 (match_operand:SI 2 "gpc_reg_operand" "r")))
1882 (clobber (match_scratch:SI 3 "=q"))]
1883 "TARGET_POWERPC && TARGET_POWER"
1884 "divwu %0,%1,%2"
1885 [(set_attr "type" "idiv")])
1886
1887 (define_insn "*udivsi3_no_mq"
1888 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1889 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1890 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1891 "TARGET_POWERPC && ! TARGET_POWER"
1892 "divwu %0,%1,%2"
1893 [(set_attr "type" "idiv")])
1894
1895 ;; For powers of two we can do srai/aze for divide and then adjust for
1896 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1897 ;; used; for PowerPC, force operands into register and do a normal divide;
1898 ;; for AIX common-mode, use quoss call on register operands.
1899 (define_expand "divsi3"
1900 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1901 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1902 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1903 ""
1904 "
1905 {
1906 if (GET_CODE (operands[2]) == CONST_INT
1907 && INTVAL (operands[2]) > 0
1908 && exact_log2 (INTVAL (operands[2])) >= 0)
1909 ;
1910 else if (TARGET_POWERPC)
1911 {
1912 operands[2] = force_reg (SImode, operands[2]);
1913 if (TARGET_POWER)
1914 {
1915 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1916 DONE;
1917 }
1918 }
1919 else if (TARGET_POWER)
1920 FAIL;
1921 else
1922 {
1923 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1924 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1925 emit_insn (gen_quoss_call ());
1926 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1927 DONE;
1928 }
1929 }")
1930
1931 (define_insn "divsi3_mq"
1932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1933 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1934 (match_operand:SI 2 "gpc_reg_operand" "r")))
1935 (clobber (match_scratch:SI 3 "=q"))]
1936 "TARGET_POWERPC && TARGET_POWER"
1937 "divw %0,%1,%2"
1938 [(set_attr "type" "idiv")])
1939
1940 (define_insn "*divsi3_no_mq"
1941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1942 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1943 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1944 "TARGET_POWERPC && ! TARGET_POWER"
1945 "divw %0,%1,%2"
1946 [(set_attr "type" "idiv")])
1947
1948 (define_expand "modsi3"
1949 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1950 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1951 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1952 ""
1953 "
1954 {
1955 int i;
1956 rtx temp1;
1957 rtx temp2;
1958
1959 if (GET_CODE (operands[2]) != CONST_INT
1960 || INTVAL (operands[2]) <= 0
1961 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1962 FAIL;
1963
1964 temp1 = gen_reg_rtx (SImode);
1965 temp2 = gen_reg_rtx (SImode);
1966
1967 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1968 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1969 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1970 DONE;
1971 }")
1972
1973 (define_insn ""
1974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1975 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1976 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1977 ""
1978 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1979 [(set_attr "type" "two")
1980 (set_attr "length" "8")])
1981
1982 (define_insn ""
1983 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1984 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1985 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1986 (const_int 0)))
1987 (clobber (match_scratch:SI 3 "=r,r"))]
1988 ""
1989 "@
1990 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1991 #"
1992 [(set_attr "type" "compare")
1993 (set_attr "length" "8,12")])
1994
1995 (define_split
1996 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1997 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1998 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1999 (const_int 0)))
2000 (clobber (match_scratch:SI 3 ""))]
2001 "reload_completed"
2002 [(set (match_dup 3)
2003 (div:SI (match_dup 1) (match_dup 2)))
2004 (set (match_dup 0)
2005 (compare:CC (match_dup 3)
2006 (const_int 0)))]
2007 "")
2008
2009 (define_insn ""
2010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2011 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2012 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2013 (const_int 0)))
2014 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2015 (div:SI (match_dup 1) (match_dup 2)))]
2016 ""
2017 "@
2018 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2019 #"
2020 [(set_attr "type" "compare")
2021 (set_attr "length" "8,12")])
2022
2023 (define_split
2024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2025 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2026 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2027 (const_int 0)))
2028 (set (match_operand:SI 0 "gpc_reg_operand" "")
2029 (div:SI (match_dup 1) (match_dup 2)))]
2030 "reload_completed"
2031 [(set (match_dup 0)
2032 (div:SI (match_dup 1) (match_dup 2)))
2033 (set (match_dup 3)
2034 (compare:CC (match_dup 0)
2035 (const_int 0)))]
2036 "")
2037
2038 (define_insn ""
2039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2040 (udiv:SI
2041 (plus:DI (ashift:DI
2042 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2043 (const_int 32))
2044 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2045 (match_operand:SI 3 "gpc_reg_operand" "r")))
2046 (set (match_operand:SI 2 "register_operand" "=*q")
2047 (umod:SI
2048 (plus:DI (ashift:DI
2049 (zero_extend:DI (match_dup 1)) (const_int 32))
2050 (zero_extend:DI (match_dup 4)))
2051 (match_dup 3)))]
2052 "TARGET_POWER"
2053 "div %0,%1,%3"
2054 [(set_attr "type" "idiv")])
2055
2056 ;; To do unsigned divide we handle the cases of the divisor looking like a
2057 ;; negative number. If it is a constant that is less than 2**31, we don't
2058 ;; have to worry about the branches. So make a few subroutines here.
2059 ;;
2060 ;; First comes the normal case.
2061 (define_expand "udivmodsi4_normal"
2062 [(set (match_dup 4) (const_int 0))
2063 (parallel [(set (match_operand:SI 0 "" "")
2064 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2065 (const_int 32))
2066 (zero_extend:DI (match_operand:SI 1 "" "")))
2067 (match_operand:SI 2 "" "")))
2068 (set (match_operand:SI 3 "" "")
2069 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2070 (const_int 32))
2071 (zero_extend:DI (match_dup 1)))
2072 (match_dup 2)))])]
2073 "TARGET_POWER"
2074 "
2075 { operands[4] = gen_reg_rtx (SImode); }")
2076
2077 ;; This handles the branches.
2078 (define_expand "udivmodsi4_tests"
2079 [(set (match_operand:SI 0 "" "") (const_int 0))
2080 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2081 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2082 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2083 (label_ref (match_operand:SI 4 "" "")) (pc)))
2084 (set (match_dup 0) (const_int 1))
2085 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2086 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2087 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2088 (label_ref (match_dup 4)) (pc)))]
2089 "TARGET_POWER"
2090 "
2091 { operands[5] = gen_reg_rtx (CCUNSmode);
2092 operands[6] = gen_reg_rtx (CCmode);
2093 }")
2094
2095 (define_expand "udivmodsi4"
2096 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2097 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2098 (match_operand:SI 2 "reg_or_cint_operand" "")))
2099 (set (match_operand:SI 3 "gpc_reg_operand" "")
2100 (umod:SI (match_dup 1) (match_dup 2)))])]
2101 ""
2102 "
2103 {
2104 rtx label = 0;
2105
2106 if (! TARGET_POWER)
2107 {
2108 if (! TARGET_POWERPC)
2109 {
2110 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2111 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2112 emit_insn (gen_divus_call ());
2113 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2114 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2115 DONE;
2116 }
2117 else
2118 FAIL;
2119 }
2120
2121 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2122 {
2123 operands[2] = force_reg (SImode, operands[2]);
2124 label = gen_label_rtx ();
2125 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2126 operands[3], label));
2127 }
2128 else
2129 operands[2] = force_reg (SImode, operands[2]);
2130
2131 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2132 operands[3]));
2133 if (label)
2134 emit_label (label);
2135
2136 DONE;
2137 }")
2138
2139 ;; AIX architecture-independent common-mode multiply (DImode),
2140 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2141 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2142 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2143 ;; assumed unused if generating common-mode, so ignore.
2144 (define_insn "mulh_call"
2145 [(set (reg:SI 3)
2146 (truncate:SI
2147 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2148 (sign_extend:DI (reg:SI 4)))
2149 (const_int 32))))
2150 (clobber (match_scratch:SI 0 "=l"))]
2151 "! TARGET_POWER && ! TARGET_POWERPC"
2152 "bla __mulh"
2153 [(set_attr "type" "imul")])
2154
2155 (define_insn "mull_call"
2156 [(set (reg:DI 3)
2157 (mult:DI (sign_extend:DI (reg:SI 3))
2158 (sign_extend:DI (reg:SI 4))))
2159 (clobber (match_scratch:SI 0 "=l"))
2160 (clobber (reg:SI 0))]
2161 "! TARGET_POWER && ! TARGET_POWERPC"
2162 "bla __mull"
2163 [(set_attr "type" "imul")])
2164
2165 (define_insn "divss_call"
2166 [(set (reg:SI 3)
2167 (div:SI (reg:SI 3) (reg:SI 4)))
2168 (set (reg:SI 4)
2169 (mod:SI (reg:SI 3) (reg:SI 4)))
2170 (clobber (match_scratch:SI 0 "=l"))
2171 (clobber (reg:SI 0))]
2172 "! TARGET_POWER && ! TARGET_POWERPC"
2173 "bla __divss"
2174 [(set_attr "type" "idiv")])
2175
2176 (define_insn "divus_call"
2177 [(set (reg:SI 3)
2178 (udiv:SI (reg:SI 3) (reg:SI 4)))
2179 (set (reg:SI 4)
2180 (umod:SI (reg:SI 3) (reg:SI 4)))
2181 (clobber (match_scratch:SI 0 "=l"))
2182 (clobber (reg:SI 0))
2183 (clobber (match_scratch:CC 1 "=x"))
2184 (clobber (reg:CC 69))]
2185 "! TARGET_POWER && ! TARGET_POWERPC"
2186 "bla __divus"
2187 [(set_attr "type" "idiv")])
2188
2189 (define_insn "quoss_call"
2190 [(set (reg:SI 3)
2191 (div:SI (reg:SI 3) (reg:SI 4)))
2192 (clobber (match_scratch:SI 0 "=l"))]
2193 "! TARGET_POWER && ! TARGET_POWERPC"
2194 "bla __quoss"
2195 [(set_attr "type" "idiv")])
2196
2197 (define_insn "quous_call"
2198 [(set (reg:SI 3)
2199 (udiv:SI (reg:SI 3) (reg:SI 4)))
2200 (clobber (match_scratch:SI 0 "=l"))
2201 (clobber (reg:SI 0))
2202 (clobber (match_scratch:CC 1 "=x"))
2203 (clobber (reg:CC 69))]
2204 "! TARGET_POWER && ! TARGET_POWERPC"
2205 "bla __quous"
2206 [(set_attr "type" "idiv")])
2207 \f
2208 ;; Logical instructions
2209 ;; The logical instructions are mostly combined by using match_operator,
2210 ;; but the plain AND insns are somewhat different because there is no
2211 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2212 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2213
2214 (define_insn "andsi3"
2215 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2216 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2217 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2218 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2219 ""
2220 "@
2221 and %0,%1,%2
2222 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2223 {andil.|andi.} %0,%1,%b2
2224 {andiu.|andis.} %0,%1,%u2"
2225 [(set_attr "type" "*,*,compare,compare")])
2226
2227 ;; Note to set cr's other than cr0 we do the and immediate and then
2228 ;; the test again -- this avoids a mfcr which on the higher end
2229 ;; machines causes an execution serialization
2230
2231 (define_insn "*andsi3_internal2"
2232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2233 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2234 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2235 (const_int 0)))
2236 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2237 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2238 "TARGET_32BIT"
2239 "@
2240 and. %3,%1,%2
2241 {andil.|andi.} %3,%1,%b2
2242 {andiu.|andis.} %3,%1,%u2
2243 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2244 #
2245 #
2246 #
2247 #"
2248 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2249 (set_attr "length" "4,4,4,4,8,8,8,8")])
2250
2251 (define_insn "*andsi3_internal3"
2252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2253 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2254 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2255 (const_int 0)))
2256 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2257 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2258 "TARGET_64BIT"
2259 "@
2260 #
2261 {andil.|andi.} %3,%1,%b2
2262 {andiu.|andis.} %3,%1,%u2
2263 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2264 #
2265 #
2266 #
2267 #"
2268 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2269 (set_attr "length" "8,4,4,4,8,8,8,8")])
2270
2271 (define_split
2272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2273 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2274 (match_operand:SI 2 "and_operand" ""))
2275 (const_int 0)))
2276 (clobber (match_scratch:SI 3 ""))
2277 (clobber (match_scratch:CC 4 ""))]
2278 "reload_completed"
2279 [(parallel [(set (match_dup 3)
2280 (and:SI (match_dup 1)
2281 (match_dup 2)))
2282 (clobber (match_dup 4))])
2283 (set (match_dup 0)
2284 (compare:CC (match_dup 3)
2285 (const_int 0)))]
2286 "")
2287
2288 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2289 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2290
2291 (define_split
2292 [(set (match_operand:CC 0 "cc_reg_operand" "")
2293 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2294 (match_operand:SI 2 "gpc_reg_operand" ""))
2295 (const_int 0)))
2296 (clobber (match_scratch:SI 3 ""))
2297 (clobber (match_scratch:CC 4 ""))]
2298 "TARGET_POWERPC64 && reload_completed"
2299 [(parallel [(set (match_dup 3)
2300 (and:SI (match_dup 1)
2301 (match_dup 2)))
2302 (clobber (match_dup 4))])
2303 (set (match_dup 0)
2304 (compare:CC (match_dup 3)
2305 (const_int 0)))]
2306 "")
2307
2308 (define_insn "*andsi3_internal4"
2309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2310 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2311 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2312 (const_int 0)))
2313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2314 (and:SI (match_dup 1)
2315 (match_dup 2)))
2316 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2317 "TARGET_32BIT"
2318 "@
2319 and. %0,%1,%2
2320 {andil.|andi.} %0,%1,%b2
2321 {andiu.|andis.} %0,%1,%u2
2322 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2323 #
2324 #
2325 #
2326 #"
2327 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2328 (set_attr "length" "4,4,4,4,8,8,8,8")])
2329
2330 (define_insn "*andsi3_internal5"
2331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2332 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2333 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2334 (const_int 0)))
2335 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2336 (and:SI (match_dup 1)
2337 (match_dup 2)))
2338 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2339 "TARGET_64BIT"
2340 "@
2341 #
2342 {andil.|andi.} %0,%1,%b2
2343 {andiu.|andis.} %0,%1,%u2
2344 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2345 #
2346 #
2347 #
2348 #"
2349 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2350 (set_attr "length" "8,4,4,4,8,8,8,8")])
2351
2352 (define_split
2353 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2354 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2355 (match_operand:SI 2 "and_operand" ""))
2356 (const_int 0)))
2357 (set (match_operand:SI 0 "gpc_reg_operand" "")
2358 (and:SI (match_dup 1)
2359 (match_dup 2)))
2360 (clobber (match_scratch:CC 4 ""))]
2361 "reload_completed"
2362 [(parallel [(set (match_dup 0)
2363 (and:SI (match_dup 1)
2364 (match_dup 2)))
2365 (clobber (match_dup 4))])
2366 (set (match_dup 3)
2367 (compare:CC (match_dup 0)
2368 (const_int 0)))]
2369 "")
2370
2371 (define_split
2372 [(set (match_operand:CC 3 "cc_reg_operand" "")
2373 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2374 (match_operand:SI 2 "gpc_reg_operand" ""))
2375 (const_int 0)))
2376 (set (match_operand:SI 0 "gpc_reg_operand" "")
2377 (and:SI (match_dup 1)
2378 (match_dup 2)))
2379 (clobber (match_scratch:CC 4 ""))]
2380 "TARGET_POWERPC64 && reload_completed"
2381 [(parallel [(set (match_dup 0)
2382 (and:SI (match_dup 1)
2383 (match_dup 2)))
2384 (clobber (match_dup 4))])
2385 (set (match_dup 3)
2386 (compare:CC (match_dup 0)
2387 (const_int 0)))]
2388 "")
2389
2390 ;; Handle the PowerPC64 rlwinm corner case
2391
2392 (define_insn_and_split "*andsi3_internal6"
2393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2394 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2395 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2396 "TARGET_POWERPC64"
2397 "#"
2398 "TARGET_POWERPC64"
2399 [(set (match_dup 0)
2400 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2401 (match_dup 4)))
2402 (set (match_dup 0)
2403 (rotate:SI (match_dup 0) (match_dup 5)))]
2404 "
2405 {
2406 int mb = extract_MB (operands[2]);
2407 int me = extract_ME (operands[2]);
2408 operands[3] = GEN_INT (me + 1);
2409 operands[5] = GEN_INT (32 - (me + 1));
2410 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2411 }"
2412 [(set_attr "length" "8")])
2413
2414 (define_expand "iorsi3"
2415 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2416 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2417 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2418 ""
2419 "
2420 {
2421 if (GET_CODE (operands[2]) == CONST_INT
2422 && ! logical_operand (operands[2], SImode))
2423 {
2424 HOST_WIDE_INT value = INTVAL (operands[2]);
2425 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2426 ? operands[0] : gen_reg_rtx (SImode));
2427
2428 emit_insn (gen_iorsi3 (tmp, operands[1],
2429 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2430 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2431 DONE;
2432 }
2433 }")
2434
2435 (define_expand "xorsi3"
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2437 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2438 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2439 ""
2440 "
2441 {
2442 if (GET_CODE (operands[2]) == CONST_INT
2443 && ! logical_operand (operands[2], SImode))
2444 {
2445 HOST_WIDE_INT value = INTVAL (operands[2]);
2446 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2447 ? operands[0] : gen_reg_rtx (SImode));
2448
2449 emit_insn (gen_xorsi3 (tmp, operands[1],
2450 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2451 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2452 DONE;
2453 }
2454 }")
2455
2456 (define_insn "*boolsi3_internal1"
2457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2458 (match_operator:SI 3 "boolean_or_operator"
2459 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2460 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2461 ""
2462 "@
2463 %q3 %0,%1,%2
2464 {%q3il|%q3i} %0,%1,%b2
2465 {%q3iu|%q3is} %0,%1,%u2")
2466
2467 (define_insn "*boolsi3_internal2"
2468 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2469 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2470 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2471 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2472 (const_int 0)))
2473 (clobber (match_scratch:SI 3 "=r,r"))]
2474 "TARGET_32BIT"
2475 "@
2476 %q4. %3,%1,%2
2477 #"
2478 [(set_attr "type" "compare")
2479 (set_attr "length" "4,8")])
2480
2481 (define_split
2482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2483 (compare:CC (match_operator:SI 4 "boolean_operator"
2484 [(match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "gpc_reg_operand" "")])
2486 (const_int 0)))
2487 (clobber (match_scratch:SI 3 ""))]
2488 "TARGET_32BIT && reload_completed"
2489 [(set (match_dup 3) (match_dup 4))
2490 (set (match_dup 0)
2491 (compare:CC (match_dup 3)
2492 (const_int 0)))]
2493 "")
2494
2495 (define_insn "*boolsi3_internal3"
2496 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2497 (compare:CC (match_operator:SI 4 "boolean_operator"
2498 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2499 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2500 (const_int 0)))
2501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2502 (match_dup 4))]
2503 "TARGET_32BIT"
2504 "@
2505 %q4. %0,%1,%2
2506 #"
2507 [(set_attr "type" "compare")
2508 (set_attr "length" "4,8")])
2509
2510 (define_split
2511 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2512 (compare:CC (match_operator:SI 4 "boolean_operator"
2513 [(match_operand:SI 1 "gpc_reg_operand" "")
2514 (match_operand:SI 2 "gpc_reg_operand" "")])
2515 (const_int 0)))
2516 (set (match_operand:SI 0 "gpc_reg_operand" "")
2517 (match_dup 4))]
2518 "TARGET_32BIT && reload_completed"
2519 [(set (match_dup 0) (match_dup 4))
2520 (set (match_dup 3)
2521 (compare:CC (match_dup 0)
2522 (const_int 0)))]
2523 "")
2524
2525 ;; Split a logical operation that we can't do in one insn into two insns,
2526 ;; each of which does one 16-bit part. This is used by combine.
2527
2528 (define_split
2529 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2530 (match_operator:SI 3 "boolean_or_operator"
2531 [(match_operand:SI 1 "gpc_reg_operand" "")
2532 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2533 ""
2534 [(set (match_dup 0) (match_dup 4))
2535 (set (match_dup 0) (match_dup 5))]
2536 "
2537 {
2538 rtx i;
2539 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2540 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2541 operands[1], i);
2542 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2543 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2544 operands[0], i);
2545 }")
2546
2547 (define_insn "*boolcsi3_internal1"
2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2549 (match_operator:SI 3 "boolean_operator"
2550 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2551 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2552 ""
2553 "%q3 %0,%2,%1")
2554
2555 (define_insn "*boolcsi3_internal2"
2556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2557 (compare:CC (match_operator:SI 4 "boolean_operator"
2558 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2559 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2560 (const_int 0)))
2561 (clobber (match_scratch:SI 3 "=r,r"))]
2562 "TARGET_32BIT"
2563 "@
2564 %q4. %3,%2,%1
2565 #"
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2568
2569 (define_split
2570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2571 (compare:CC (match_operator:SI 4 "boolean_operator"
2572 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
2574 (const_int 0)))
2575 (clobber (match_scratch:SI 3 ""))]
2576 "TARGET_32BIT && reload_completed"
2577 [(set (match_dup 3) (match_dup 4))
2578 (set (match_dup 0)
2579 (compare:CC (match_dup 3)
2580 (const_int 0)))]
2581 "")
2582
2583 (define_insn "*boolcsi3_internal3"
2584 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2585 (compare:CC (match_operator:SI 4 "boolean_operator"
2586 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2587 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2588 (const_int 0)))
2589 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2590 (match_dup 4))]
2591 "TARGET_32BIT"
2592 "@
2593 %q4. %0,%2,%1
2594 #"
2595 [(set_attr "type" "compare")
2596 (set_attr "length" "4,8")])
2597
2598 (define_split
2599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2600 (compare:CC (match_operator:SI 4 "boolean_operator"
2601 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2602 (match_operand:SI 2 "gpc_reg_operand" "")])
2603 (const_int 0)))
2604 (set (match_operand:SI 0 "gpc_reg_operand" "")
2605 (match_dup 4))]
2606 "TARGET_32BIT && reload_completed"
2607 [(set (match_dup 0) (match_dup 4))
2608 (set (match_dup 3)
2609 (compare:CC (match_dup 0)
2610 (const_int 0)))]
2611 "")
2612
2613 (define_insn "*boolccsi3_internal1"
2614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2615 (match_operator:SI 3 "boolean_operator"
2616 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2617 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2618 ""
2619 "%q3 %0,%1,%2")
2620
2621 (define_insn "*boolccsi3_internal2"
2622 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2623 (compare:CC (match_operator:SI 4 "boolean_operator"
2624 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2625 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2626 (const_int 0)))
2627 (clobber (match_scratch:SI 3 "=r,r"))]
2628 "TARGET_32BIT"
2629 "@
2630 %q4. %3,%1,%2
2631 #"
2632 [(set_attr "type" "compare")
2633 (set_attr "length" "4,8")])
2634
2635 (define_split
2636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2637 (compare:CC (match_operator:SI 4 "boolean_operator"
2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2639 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2640 (const_int 0)))
2641 (clobber (match_scratch:SI 3 ""))]
2642 "TARGET_32BIT && reload_completed"
2643 [(set (match_dup 3) (match_dup 4))
2644 (set (match_dup 0)
2645 (compare:CC (match_dup 3)
2646 (const_int 0)))]
2647 "")
2648
2649 (define_insn "*boolccsi3_internal3"
2650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2651 (compare:CC (match_operator:SI 4 "boolean_operator"
2652 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2653 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2654 (const_int 0)))
2655 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2656 (match_dup 4))]
2657 "TARGET_32BIT"
2658 "@
2659 %q4. %0,%1,%2
2660 #"
2661 [(set_attr "type" "compare")
2662 (set_attr "length" "4,8")])
2663
2664 (define_split
2665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2666 (compare:CC (match_operator:SI 4 "boolean_operator"
2667 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2668 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2669 (const_int 0)))
2670 (set (match_operand:SI 0 "gpc_reg_operand" "")
2671 (match_dup 4))]
2672 "TARGET_32BIT && reload_completed"
2673 [(set (match_dup 0) (match_dup 4))
2674 (set (match_dup 3)
2675 (compare:CC (match_dup 0)
2676 (const_int 0)))]
2677 "")
2678
2679 ;; maskir insn. We need four forms because things might be in arbitrary
2680 ;; orders. Don't define forms that only set CR fields because these
2681 ;; would modify an input register.
2682
2683 (define_insn "*maskir_internal1"
2684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2685 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2686 (match_operand:SI 1 "gpc_reg_operand" "0"))
2687 (and:SI (match_dup 2)
2688 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2689 "TARGET_POWER"
2690 "maskir %0,%3,%2")
2691
2692 (define_insn "*maskir_internal2"
2693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2694 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2695 (match_operand:SI 1 "gpc_reg_operand" "0"))
2696 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2697 (match_dup 2))))]
2698 "TARGET_POWER"
2699 "maskir %0,%3,%2")
2700
2701 (define_insn "*maskir_internal3"
2702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2703 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2704 (match_operand:SI 3 "gpc_reg_operand" "r"))
2705 (and:SI (not:SI (match_dup 2))
2706 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2707 "TARGET_POWER"
2708 "maskir %0,%3,%2")
2709
2710 (define_insn "*maskir_internal4"
2711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2712 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2713 (match_operand:SI 2 "gpc_reg_operand" "r"))
2714 (and:SI (not:SI (match_dup 2))
2715 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2716 "TARGET_POWER"
2717 "maskir %0,%3,%2")
2718
2719 (define_insn "*maskir_internal5"
2720 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2721 (compare:CC
2722 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2723 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2724 (and:SI (match_dup 2)
2725 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2726 (const_int 0)))
2727 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2728 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2729 (and:SI (match_dup 2) (match_dup 3))))]
2730 "TARGET_POWER"
2731 "@
2732 maskir. %0,%3,%2
2733 #"
2734 [(set_attr "type" "compare")
2735 (set_attr "length" "4,8")])
2736
2737 (define_split
2738 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2739 (compare:CC
2740 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2741 (match_operand:SI 1 "gpc_reg_operand" ""))
2742 (and:SI (match_dup 2)
2743 (match_operand:SI 3 "gpc_reg_operand" "")))
2744 (const_int 0)))
2745 (set (match_operand:SI 0 "gpc_reg_operand" "")
2746 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2747 (and:SI (match_dup 2) (match_dup 3))))]
2748 "TARGET_POWER && reload_completed"
2749 [(set (match_dup 0)
2750 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2751 (and:SI (match_dup 2) (match_dup 3))))
2752 (set (match_dup 4)
2753 (compare:CC (match_dup 0)
2754 (const_int 0)))]
2755 "")
2756
2757 (define_insn "*maskir_internal6"
2758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2759 (compare:CC
2760 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2761 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2762 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2763 (match_dup 2)))
2764 (const_int 0)))
2765 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2766 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2767 (and:SI (match_dup 3) (match_dup 2))))]
2768 "TARGET_POWER"
2769 "@
2770 maskir. %0,%3,%2
2771 #"
2772 [(set_attr "type" "compare")
2773 (set_attr "length" "4,8")])
2774
2775 (define_split
2776 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2777 (compare:CC
2778 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2779 (match_operand:SI 1 "gpc_reg_operand" ""))
2780 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2781 (match_dup 2)))
2782 (const_int 0)))
2783 (set (match_operand:SI 0 "gpc_reg_operand" "")
2784 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2785 (and:SI (match_dup 3) (match_dup 2))))]
2786 "TARGET_POWER && reload_completed"
2787 [(set (match_dup 0)
2788 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2789 (and:SI (match_dup 3) (match_dup 2))))
2790 (set (match_dup 4)
2791 (compare:CC (match_dup 0)
2792 (const_int 0)))]
2793 "")
2794
2795 (define_insn "*maskir_internal7"
2796 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2797 (compare:CC
2798 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2799 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2800 (and:SI (not:SI (match_dup 2))
2801 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2804 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2805 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2806 "TARGET_POWER"
2807 "@
2808 maskir. %0,%3,%2
2809 #"
2810 [(set_attr "type" "compare")
2811 (set_attr "length" "4,8")])
2812
2813 (define_split
2814 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2815 (compare:CC
2816 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2817 (match_operand:SI 3 "gpc_reg_operand" ""))
2818 (and:SI (not:SI (match_dup 2))
2819 (match_operand:SI 1 "gpc_reg_operand" "")))
2820 (const_int 0)))
2821 (set (match_operand:SI 0 "gpc_reg_operand" "")
2822 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2823 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2824 "TARGET_POWER && reload_completed"
2825 [(set (match_dup 0)
2826 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2827 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2828 (set (match_dup 4)
2829 (compare:CC (match_dup 0)
2830 (const_int 0)))]
2831 "")
2832
2833 (define_insn "*maskir_internal8"
2834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2835 (compare:CC
2836 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2837 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2838 (and:SI (not:SI (match_dup 2))
2839 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2840 (const_int 0)))
2841 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2842 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2843 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2844 "TARGET_POWER"
2845 "@
2846 maskir. %0,%3,%2
2847 #"
2848 [(set_attr "type" "compare")
2849 (set_attr "length" "4,8")])
2850
2851 (define_split
2852 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2853 (compare:CC
2854 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2855 (match_operand:SI 2 "gpc_reg_operand" ""))
2856 (and:SI (not:SI (match_dup 2))
2857 (match_operand:SI 1 "gpc_reg_operand" "")))
2858 (const_int 0)))
2859 (set (match_operand:SI 0 "gpc_reg_operand" "")
2860 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2861 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2862 "TARGET_POWER && reload_completed"
2863 [(set (match_dup 0)
2864 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2865 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2866 (set (match_dup 4)
2867 (compare:CC (match_dup 0)
2868 (const_int 0)))]
2869 "")
2870 \f
2871 ;; Rotate and shift insns, in all their variants. These support shifts,
2872 ;; field inserts and extracts, and various combinations thereof.
2873 (define_expand "insv"
2874 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2875 (match_operand:SI 1 "const_int_operand" "")
2876 (match_operand:SI 2 "const_int_operand" ""))
2877 (match_operand 3 "gpc_reg_operand" ""))]
2878 ""
2879 "
2880 {
2881 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2882 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2883 compiler if the address of the structure is taken later. */
2884 if (GET_CODE (operands[0]) == SUBREG
2885 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2886 FAIL;
2887
2888 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2889 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2890 else
2891 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2892 DONE;
2893 }")
2894
2895 (define_insn "insvsi"
2896 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2897 (match_operand:SI 1 "const_int_operand" "i")
2898 (match_operand:SI 2 "const_int_operand" "i"))
2899 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2900 ""
2901 "*
2902 {
2903 int start = INTVAL (operands[2]) & 31;
2904 int size = INTVAL (operands[1]) & 31;
2905
2906 operands[4] = GEN_INT (32 - start - size);
2907 operands[1] = GEN_INT (start + size - 1);
2908 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2909 }"
2910 [(set_attr "type" "insert_word")])
2911
2912 (define_insn "*insvsi_internal1"
2913 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2914 (match_operand:SI 1 "const_int_operand" "i")
2915 (match_operand:SI 2 "const_int_operand" "i"))
2916 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2917 (match_operand:SI 4 "const_int_operand" "i")))]
2918 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2919 "*
2920 {
2921 int shift = INTVAL (operands[4]) & 31;
2922 int start = INTVAL (operands[2]) & 31;
2923 int size = INTVAL (operands[1]) & 31;
2924
2925 operands[4] = GEN_INT (shift - start - size);
2926 operands[1] = GEN_INT (start + size - 1);
2927 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2928 }"
2929 [(set_attr "type" "insert_word")])
2930
2931 (define_insn "*insvsi_internal2"
2932 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2933 (match_operand:SI 1 "const_int_operand" "i")
2934 (match_operand:SI 2 "const_int_operand" "i"))
2935 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2936 (match_operand:SI 4 "const_int_operand" "i")))]
2937 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2938 "*
2939 {
2940 int shift = INTVAL (operands[4]) & 31;
2941 int start = INTVAL (operands[2]) & 31;
2942 int size = INTVAL (operands[1]) & 31;
2943
2944 operands[4] = GEN_INT (32 - shift - start - size);
2945 operands[1] = GEN_INT (start + size - 1);
2946 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2947 }"
2948 [(set_attr "type" "insert_word")])
2949
2950 (define_insn "*insvsi_internal3"
2951 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2952 (match_operand:SI 1 "const_int_operand" "i")
2953 (match_operand:SI 2 "const_int_operand" "i"))
2954 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2955 (match_operand:SI 4 "const_int_operand" "i")))]
2956 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2957 "*
2958 {
2959 int shift = INTVAL (operands[4]) & 31;
2960 int start = INTVAL (operands[2]) & 31;
2961 int size = INTVAL (operands[1]) & 31;
2962
2963 operands[4] = GEN_INT (32 - shift - start - size);
2964 operands[1] = GEN_INT (start + size - 1);
2965 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2966 }"
2967 [(set_attr "type" "insert_word")])
2968
2969 (define_insn "*insvsi_internal4"
2970 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2971 (match_operand:SI 1 "const_int_operand" "i")
2972 (match_operand:SI 2 "const_int_operand" "i"))
2973 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2974 (match_operand:SI 4 "const_int_operand" "i")
2975 (match_operand:SI 5 "const_int_operand" "i")))]
2976 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2977 "*
2978 {
2979 int extract_start = INTVAL (operands[5]) & 31;
2980 int extract_size = INTVAL (operands[4]) & 31;
2981 int insert_start = INTVAL (operands[2]) & 31;
2982 int insert_size = INTVAL (operands[1]) & 31;
2983
2984 /* Align extract field with insert field */
2985 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2986 operands[1] = GEN_INT (insert_start + insert_size - 1);
2987 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2988 }"
2989 [(set_attr "type" "insert_word")])
2990
2991 ;; combine patterns for rlwimi
2992 (define_insn "*insvsi_internal5"
2993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2994 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2995 (match_operand:SI 1 "mask_operand" "i"))
2996 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2997 (match_operand:SI 2 "const_int_operand" "i"))
2998 (match_operand:SI 5 "mask_operand" "i"))))]
2999 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3000 "*
3001 {
3002 int me = extract_ME(operands[5]);
3003 int mb = extract_MB(operands[5]);
3004 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3005 operands[2] = GEN_INT(mb);
3006 operands[1] = GEN_INT(me);
3007 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3008 }"
3009 [(set_attr "type" "insert_word")])
3010
3011 (define_insn "*insvsi_internal6"
3012 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3013 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3014 (match_operand:SI 2 "const_int_operand" "i"))
3015 (match_operand:SI 5 "mask_operand" "i"))
3016 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3017 (match_operand:SI 1 "mask_operand" "i"))))]
3018 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3019 "*
3020 {
3021 int me = extract_ME(operands[5]);
3022 int mb = extract_MB(operands[5]);
3023 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3024 operands[2] = GEN_INT(mb);
3025 operands[1] = GEN_INT(me);
3026 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3027 }"
3028 [(set_attr "type" "insert_word")])
3029
3030 (define_insn "insvdi"
3031 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3032 (match_operand:SI 1 "const_int_operand" "i")
3033 (match_operand:SI 2 "const_int_operand" "i"))
3034 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3035 "TARGET_POWERPC64"
3036 "*
3037 {
3038 int start = INTVAL (operands[2]) & 63;
3039 int size = INTVAL (operands[1]) & 63;
3040
3041 operands[1] = GEN_INT (64 - start - size);
3042 return \"rldimi %0,%3,%H1,%H2\";
3043 }")
3044
3045 (define_insn "*insvdi_internal2"
3046 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3047 (match_operand:SI 1 "const_int_operand" "i")
3048 (match_operand:SI 2 "const_int_operand" "i"))
3049 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3050 (match_operand:SI 4 "const_int_operand" "i")))]
3051 "TARGET_POWERPC64
3052 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3053 "*
3054 {
3055 int shift = INTVAL (operands[4]) & 63;
3056 int start = (INTVAL (operands[2]) & 63) - 32;
3057 int size = INTVAL (operands[1]) & 63;
3058
3059 operands[4] = GEN_INT (64 - shift - start - size);
3060 operands[2] = GEN_INT (start);
3061 operands[1] = GEN_INT (start + size - 1);
3062 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3063 }")
3064
3065 (define_insn "*insvdi_internal3"
3066 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3067 (match_operand:SI 1 "const_int_operand" "i")
3068 (match_operand:SI 2 "const_int_operand" "i"))
3069 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3070 (match_operand:SI 4 "const_int_operand" "i")))]
3071 "TARGET_POWERPC64
3072 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3073 "*
3074 {
3075 int shift = INTVAL (operands[4]) & 63;
3076 int start = (INTVAL (operands[2]) & 63) - 32;
3077 int size = INTVAL (operands[1]) & 63;
3078
3079 operands[4] = GEN_INT (64 - shift - start - size);
3080 operands[2] = GEN_INT (start);
3081 operands[1] = GEN_INT (start + size - 1);
3082 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3083 }")
3084
3085 (define_expand "extzv"
3086 [(set (match_operand 0 "gpc_reg_operand" "")
3087 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3088 (match_operand:SI 2 "const_int_operand" "")
3089 (match_operand:SI 3 "const_int_operand" "")))]
3090 ""
3091 "
3092 {
3093 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3094 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3095 compiler if the address of the structure is taken later. */
3096 if (GET_CODE (operands[0]) == SUBREG
3097 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3098 FAIL;
3099
3100 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3101 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3102 else
3103 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3104 DONE;
3105 }")
3106
3107 (define_insn "extzvsi"
3108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3109 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3110 (match_operand:SI 2 "const_int_operand" "i")
3111 (match_operand:SI 3 "const_int_operand" "i")))]
3112 ""
3113 "*
3114 {
3115 int start = INTVAL (operands[3]) & 31;
3116 int size = INTVAL (operands[2]) & 31;
3117
3118 if (start + size >= 32)
3119 operands[3] = const0_rtx;
3120 else
3121 operands[3] = GEN_INT (start + size);
3122 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3123 }")
3124
3125 (define_insn "*extzvsi_internal1"
3126 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3127 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3128 (match_operand:SI 2 "const_int_operand" "i,i")
3129 (match_operand:SI 3 "const_int_operand" "i,i"))
3130 (const_int 0)))
3131 (clobber (match_scratch:SI 4 "=r,r"))]
3132 ""
3133 "*
3134 {
3135 int start = INTVAL (operands[3]) & 31;
3136 int size = INTVAL (operands[2]) & 31;
3137
3138 /* Force split for non-cc0 compare. */
3139 if (which_alternative == 1)
3140 return \"#\";
3141
3142 /* If the bit-field being tested fits in the upper or lower half of a
3143 word, it is possible to use andiu. or andil. to test it. This is
3144 useful because the condition register set-use delay is smaller for
3145 andi[ul]. than for rlinm. This doesn't work when the starting bit
3146 position is 0 because the LT and GT bits may be set wrong. */
3147
3148 if ((start > 0 && start + size <= 16) || start >= 16)
3149 {
3150 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3151 - (1 << (16 - (start & 15) - size))));
3152 if (start < 16)
3153 return \"{andiu.|andis.} %4,%1,%3\";
3154 else
3155 return \"{andil.|andi.} %4,%1,%3\";
3156 }
3157
3158 if (start + size >= 32)
3159 operands[3] = const0_rtx;
3160 else
3161 operands[3] = GEN_INT (start + size);
3162 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3163 }"
3164 [(set_attr "type" "compare")
3165 (set_attr "length" "4,8")])
3166
3167 (define_split
3168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3169 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3170 (match_operand:SI 2 "const_int_operand" "")
3171 (match_operand:SI 3 "const_int_operand" ""))
3172 (const_int 0)))
3173 (clobber (match_scratch:SI 4 ""))]
3174 "reload_completed"
3175 [(set (match_dup 4)
3176 (zero_extract:SI (match_dup 1) (match_dup 2)
3177 (match_dup 3)))
3178 (set (match_dup 0)
3179 (compare:CC (match_dup 4)
3180 (const_int 0)))]
3181 "")
3182
3183 (define_insn "*extzvsi_internal2"
3184 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3185 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3186 (match_operand:SI 2 "const_int_operand" "i,i")
3187 (match_operand:SI 3 "const_int_operand" "i,i"))
3188 (const_int 0)))
3189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3190 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3191 ""
3192 "*
3193 {
3194 int start = INTVAL (operands[3]) & 31;
3195 int size = INTVAL (operands[2]) & 31;
3196
3197 /* Force split for non-cc0 compare. */
3198 if (which_alternative == 1)
3199 return \"#\";
3200
3201 /* Since we are using the output value, we can't ignore any need for
3202 a shift. The bit-field must end at the LSB. */
3203 if (start >= 16 && start + size == 32)
3204 {
3205 operands[3] = GEN_INT ((1 << size) - 1);
3206 return \"{andil.|andi.} %0,%1,%3\";
3207 }
3208
3209 if (start + size >= 32)
3210 operands[3] = const0_rtx;
3211 else
3212 operands[3] = GEN_INT (start + size);
3213 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3214 }"
3215 [(set_attr "type" "compare")
3216 (set_attr "length" "4,8")])
3217
3218 (define_split
3219 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3220 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3221 (match_operand:SI 2 "const_int_operand" "")
3222 (match_operand:SI 3 "const_int_operand" ""))
3223 (const_int 0)))
3224 (set (match_operand:SI 0 "gpc_reg_operand" "")
3225 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3226 "reload_completed"
3227 [(set (match_dup 0)
3228 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3229 (set (match_dup 4)
3230 (compare:CC (match_dup 0)
3231 (const_int 0)))]
3232 "")
3233
3234 (define_insn "extzvdi"
3235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3236 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3237 (match_operand:SI 2 "const_int_operand" "i")
3238 (match_operand:SI 3 "const_int_operand" "i")))]
3239 "TARGET_POWERPC64"
3240 "*
3241 {
3242 int start = INTVAL (operands[3]) & 63;
3243 int size = INTVAL (operands[2]) & 63;
3244
3245 if (start + size >= 64)
3246 operands[3] = const0_rtx;
3247 else
3248 operands[3] = GEN_INT (start + size);
3249 operands[2] = GEN_INT (64 - size);
3250 return \"rldicl %0,%1,%3,%2\";
3251 }")
3252
3253 (define_insn "*extzvdi_internal1"
3254 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3255 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3256 (match_operand:SI 2 "const_int_operand" "i")
3257 (match_operand:SI 3 "const_int_operand" "i"))
3258 (const_int 0)))
3259 (clobber (match_scratch:DI 4 "=r"))]
3260 "TARGET_64BIT"
3261 "*
3262 {
3263 int start = INTVAL (operands[3]) & 63;
3264 int size = INTVAL (operands[2]) & 63;
3265
3266 if (start + size >= 64)
3267 operands[3] = const0_rtx;
3268 else
3269 operands[3] = GEN_INT (start + size);
3270 operands[2] = GEN_INT (64 - size);
3271 return \"rldicl. %4,%1,%3,%2\";
3272 }"
3273 [(set_attr "type" "compare")])
3274
3275 (define_insn "*extzvdi_internal2"
3276 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3277 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3278 (match_operand:SI 2 "const_int_operand" "i")
3279 (match_operand:SI 3 "const_int_operand" "i"))
3280 (const_int 0)))
3281 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3282 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3283 "TARGET_64BIT"
3284 "*
3285 {
3286 int start = INTVAL (operands[3]) & 63;
3287 int size = INTVAL (operands[2]) & 63;
3288
3289 if (start + size >= 64)
3290 operands[3] = const0_rtx;
3291 else
3292 operands[3] = GEN_INT (start + size);
3293 operands[2] = GEN_INT (64 - size);
3294 return \"rldicl. %0,%1,%3,%2\";
3295 }"
3296 [(set_attr "type" "compare")])
3297
3298 (define_insn "rotlsi3"
3299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3300 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3301 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3302 ""
3303 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3304
3305 (define_insn "*rotlsi3_internal2"
3306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3307 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3309 (const_int 0)))
3310 (clobber (match_scratch:SI 3 "=r,r"))]
3311 ""
3312 "@
3313 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3314 #"
3315 [(set_attr "type" "delayed_compare")
3316 (set_attr "length" "4,8")])
3317
3318 (define_split
3319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3320 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3321 (match_operand:SI 2 "reg_or_cint_operand" ""))
3322 (const_int 0)))
3323 (clobber (match_scratch:SI 3 ""))]
3324 "reload_completed"
3325 [(set (match_dup 3)
3326 (rotate:SI (match_dup 1) (match_dup 2)))
3327 (set (match_dup 0)
3328 (compare:CC (match_dup 3)
3329 (const_int 0)))]
3330 "")
3331
3332 (define_insn "*rotlsi3_internal3"
3333 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3334 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3335 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3336 (const_int 0)))
3337 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3338 (rotate:SI (match_dup 1) (match_dup 2)))]
3339 ""
3340 "@
3341 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3342 #"
3343 [(set_attr "type" "delayed_compare")
3344 (set_attr "length" "4,8")])
3345
3346 (define_split
3347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3348 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3349 (match_operand:SI 2 "reg_or_cint_operand" ""))
3350 (const_int 0)))
3351 (set (match_operand:SI 0 "gpc_reg_operand" "")
3352 (rotate:SI (match_dup 1) (match_dup 2)))]
3353 "reload_completed"
3354 [(set (match_dup 0)
3355 (rotate:SI (match_dup 1) (match_dup 2)))
3356 (set (match_dup 3)
3357 (compare:CC (match_dup 0)
3358 (const_int 0)))]
3359 "")
3360
3361 (define_insn "*rotlsi3_internal4"
3362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3363 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3364 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3365 (match_operand:SI 3 "mask_operand" "n")))]
3366 ""
3367 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3368
3369 (define_insn "*rotlsi3_internal5"
3370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3371 (compare:CC (and:SI
3372 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3373 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3374 (match_operand:SI 3 "mask_operand" "n,n"))
3375 (const_int 0)))
3376 (clobber (match_scratch:SI 4 "=r,r"))]
3377 ""
3378 "@
3379 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3380 #"
3381 [(set_attr "type" "delayed_compare")
3382 (set_attr "length" "4,8")])
3383
3384 (define_split
3385 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3386 (compare:CC (and:SI
3387 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3388 (match_operand:SI 2 "reg_or_cint_operand" ""))
3389 (match_operand:SI 3 "mask_operand" ""))
3390 (const_int 0)))
3391 (clobber (match_scratch:SI 4 ""))]
3392 "reload_completed"
3393 [(set (match_dup 4)
3394 (and:SI (rotate:SI (match_dup 1)
3395 (match_dup 2))
3396 (match_dup 3)))
3397 (set (match_dup 0)
3398 (compare:CC (match_dup 4)
3399 (const_int 0)))]
3400 "")
3401
3402 (define_insn "*rotlsi3_internal6"
3403 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3404 (compare:CC (and:SI
3405 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3406 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3407 (match_operand:SI 3 "mask_operand" "n,n"))
3408 (const_int 0)))
3409 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3410 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3411 ""
3412 "@
3413 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3414 #"
3415 [(set_attr "type" "delayed_compare")
3416 (set_attr "length" "4,8")])
3417
3418 (define_split
3419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3420 (compare:CC (and:SI
3421 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3422 (match_operand:SI 2 "reg_or_cint_operand" ""))
3423 (match_operand:SI 3 "mask_operand" ""))
3424 (const_int 0)))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3427 "reload_completed"
3428 [(set (match_dup 0)
3429 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3430 (set (match_dup 4)
3431 (compare:CC (match_dup 0)
3432 (const_int 0)))]
3433 "")
3434
3435 (define_insn "*rotlsi3_internal7"
3436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3437 (zero_extend:SI
3438 (subreg:QI
3439 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3440 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3441 ""
3442 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3443
3444 (define_insn "*rotlsi3_internal8"
3445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3446 (compare:CC (zero_extend:SI
3447 (subreg:QI
3448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3449 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3450 (const_int 0)))
3451 (clobber (match_scratch:SI 3 "=r,r"))]
3452 ""
3453 "@
3454 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3455 #"
3456 [(set_attr "type" "delayed_compare")
3457 (set_attr "length" "4,8")])
3458
3459 (define_split
3460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3461 (compare:CC (zero_extend:SI
3462 (subreg:QI
3463 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3464 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3465 (const_int 0)))
3466 (clobber (match_scratch:SI 3 ""))]
3467 "reload_completed"
3468 [(set (match_dup 3)
3469 (zero_extend:SI (subreg:QI
3470 (rotate:SI (match_dup 1)
3471 (match_dup 2)) 0)))
3472 (set (match_dup 0)
3473 (compare:CC (match_dup 3)
3474 (const_int 0)))]
3475 "")
3476
3477 (define_insn "*rotlsi3_internal9"
3478 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3479 (compare:CC (zero_extend:SI
3480 (subreg:QI
3481 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3482 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3483 (const_int 0)))
3484 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3485 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3486 ""
3487 "@
3488 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3489 #"
3490 [(set_attr "type" "delayed_compare")
3491 (set_attr "length" "4,8")])
3492
3493 (define_split
3494 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3495 (compare:CC (zero_extend:SI
3496 (subreg:QI
3497 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3498 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3499 (const_int 0)))
3500 (set (match_operand:SI 0 "gpc_reg_operand" "")
3501 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3502 "reload_completed"
3503 [(set (match_dup 0)
3504 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3505 (set (match_dup 3)
3506 (compare:CC (match_dup 0)
3507 (const_int 0)))]
3508 "")
3509
3510 (define_insn "*rotlsi3_internal10"
3511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3512 (zero_extend:SI
3513 (subreg:HI
3514 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3515 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3516 ""
3517 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3518
3519 (define_insn "*rotlsi3_internal11"
3520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3521 (compare:CC (zero_extend:SI
3522 (subreg:HI
3523 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3524 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3525 (const_int 0)))
3526 (clobber (match_scratch:SI 3 "=r,r"))]
3527 ""
3528 "@
3529 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3530 #"
3531 [(set_attr "type" "delayed_compare")
3532 (set_attr "length" "4,8")])
3533
3534 (define_split
3535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3536 (compare:CC (zero_extend:SI
3537 (subreg:HI
3538 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3539 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3540 (const_int 0)))
3541 (clobber (match_scratch:SI 3 ""))]
3542 "reload_completed"
3543 [(set (match_dup 3)
3544 (zero_extend:SI (subreg:HI
3545 (rotate:SI (match_dup 1)
3546 (match_dup 2)) 0)))
3547 (set (match_dup 0)
3548 (compare:CC (match_dup 3)
3549 (const_int 0)))]
3550 "")
3551
3552 (define_insn "*rotlsi3_internal12"
3553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3554 (compare:CC (zero_extend:SI
3555 (subreg:HI
3556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3557 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3558 (const_int 0)))
3559 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3560 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3561 ""
3562 "@
3563 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3564 #"
3565 [(set_attr "type" "delayed_compare")
3566 (set_attr "length" "4,8")])
3567
3568 (define_split
3569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3570 (compare:CC (zero_extend:SI
3571 (subreg:HI
3572 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3573 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3574 (const_int 0)))
3575 (set (match_operand:SI 0 "gpc_reg_operand" "")
3576 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3577 "reload_completed"
3578 [(set (match_dup 0)
3579 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3580 (set (match_dup 3)
3581 (compare:CC (match_dup 0)
3582 (const_int 0)))]
3583 "")
3584
3585 ;; Note that we use "sle." instead of "sl." so that we can set
3586 ;; SHIFT_COUNT_TRUNCATED.
3587
3588 (define_expand "ashlsi3"
3589 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3590 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3591 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3592 ""
3593 "
3594 {
3595 if (TARGET_POWER)
3596 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3597 else
3598 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3599 DONE;
3600 }")
3601
3602 (define_insn "ashlsi3_power"
3603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3604 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3605 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3606 (clobber (match_scratch:SI 3 "=q,X"))]
3607 "TARGET_POWER"
3608 "@
3609 sle %0,%1,%2
3610 {sli|slwi} %0,%1,%h2")
3611
3612 (define_insn "ashlsi3_no_power"
3613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3614 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3615 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3616 "! TARGET_POWER"
3617 "{sl|slw}%I2 %0,%1,%h2")
3618
3619 (define_insn ""
3620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3621 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3622 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3623 (const_int 0)))
3624 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3625 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3626 "TARGET_POWER"
3627 "@
3628 sle. %3,%1,%2
3629 {sli.|slwi.} %3,%1,%h2
3630 #
3631 #"
3632 [(set_attr "type" "delayed_compare")
3633 (set_attr "length" "4,4,8,8")])
3634
3635 (define_split
3636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3637 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 3 ""))
3641 (clobber (match_scratch:SI 4 ""))]
3642 "TARGET_POWER && reload_completed"
3643 [(parallel [(set (match_dup 3)
3644 (ashift:SI (match_dup 1) (match_dup 2)))
3645 (clobber (match_dup 4))])
3646 (set (match_dup 0)
3647 (compare:CC (match_dup 3)
3648 (const_int 0)))]
3649 "")
3650
3651 (define_insn ""
3652 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3653 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3654 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3655 (const_int 0)))
3656 (clobber (match_scratch:SI 3 "=r,r"))]
3657 "! TARGET_POWER && TARGET_32BIT"
3658 "@
3659 {sl|slw}%I2. %3,%1,%h2
3660 #"
3661 [(set_attr "type" "delayed_compare")
3662 (set_attr "length" "4,8")])
3663
3664 (define_split
3665 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3666 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3667 (match_operand:SI 2 "reg_or_cint_operand" ""))
3668 (const_int 0)))
3669 (clobber (match_scratch:SI 3 ""))]
3670 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3671 [(set (match_dup 3)
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3673 (set (match_dup 0)
3674 (compare:CC (match_dup 3)
3675 (const_int 0)))]
3676 "")
3677
3678 (define_insn ""
3679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3680 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3681 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3682 (const_int 0)))
3683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3684 (ashift:SI (match_dup 1) (match_dup 2)))
3685 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3686 "TARGET_POWER"
3687 "@
3688 sle. %0,%1,%2
3689 {sli.|slwi.} %0,%1,%h2
3690 #
3691 #"
3692 [(set_attr "type" "delayed_compare")
3693 (set_attr "length" "4,4,8,8")])
3694
3695 (define_split
3696 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3697 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3698 (match_operand:SI 2 "reg_or_cint_operand" ""))
3699 (const_int 0)))
3700 (set (match_operand:SI 0 "gpc_reg_operand" "")
3701 (ashift:SI (match_dup 1) (match_dup 2)))
3702 (clobber (match_scratch:SI 4 ""))]
3703 "TARGET_POWER && reload_completed"
3704 [(parallel [(set (match_dup 0)
3705 (ashift:SI (match_dup 1) (match_dup 2)))
3706 (clobber (match_dup 4))])
3707 (set (match_dup 3)
3708 (compare:CC (match_dup 0)
3709 (const_int 0)))]
3710 "")
3711
3712 (define_insn ""
3713 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3714 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3715 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3716 (const_int 0)))
3717 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3718 (ashift:SI (match_dup 1) (match_dup 2)))]
3719 "! TARGET_POWER && TARGET_32BIT"
3720 "@
3721 {sl|slw}%I2. %0,%1,%h2
3722 #"
3723 [(set_attr "type" "delayed_compare")
3724 (set_attr "length" "4,8")])
3725
3726 (define_split
3727 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3728 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3729 (match_operand:SI 2 "reg_or_cint_operand" ""))
3730 (const_int 0)))
3731 (set (match_operand:SI 0 "gpc_reg_operand" "")
3732 (ashift:SI (match_dup 1) (match_dup 2)))]
3733 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3734 [(set (match_dup 0)
3735 (ashift:SI (match_dup 1) (match_dup 2)))
3736 (set (match_dup 3)
3737 (compare:CC (match_dup 0)
3738 (const_int 0)))]
3739 "")
3740
3741 (define_insn ""
3742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3743 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3744 (match_operand:SI 2 "const_int_operand" "i"))
3745 (match_operand:SI 3 "mask_operand" "n")))]
3746 "includes_lshift_p (operands[2], operands[3])"
3747 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3748
3749 (define_insn ""
3750 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3751 (compare:CC
3752 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3753 (match_operand:SI 2 "const_int_operand" "i,i"))
3754 (match_operand:SI 3 "mask_operand" "n,n"))
3755 (const_int 0)))
3756 (clobber (match_scratch:SI 4 "=r,r"))]
3757 "includes_lshift_p (operands[2], operands[3])"
3758 "@
3759 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3760 #"
3761 [(set_attr "type" "delayed_compare")
3762 (set_attr "length" "4,8")])
3763
3764 (define_split
3765 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3766 (compare:CC
3767 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3768 (match_operand:SI 2 "const_int_operand" ""))
3769 (match_operand:SI 3 "mask_operand" ""))
3770 (const_int 0)))
3771 (clobber (match_scratch:SI 4 ""))]
3772 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3773 [(set (match_dup 4)
3774 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3775 (match_dup 3)))
3776 (set (match_dup 0)
3777 (compare:CC (match_dup 4)
3778 (const_int 0)))]
3779 "")
3780
3781 (define_insn ""
3782 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3783 (compare:CC
3784 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3785 (match_operand:SI 2 "const_int_operand" "i,i"))
3786 (match_operand:SI 3 "mask_operand" "n,n"))
3787 (const_int 0)))
3788 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3789 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3790 "includes_lshift_p (operands[2], operands[3])"
3791 "@
3792 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3793 #"
3794 [(set_attr "type" "delayed_compare")
3795 (set_attr "length" "4,8")])
3796
3797 (define_split
3798 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3799 (compare:CC
3800 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3801 (match_operand:SI 2 "const_int_operand" ""))
3802 (match_operand:SI 3 "mask_operand" ""))
3803 (const_int 0)))
3804 (set (match_operand:SI 0 "gpc_reg_operand" "")
3805 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3806 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3807 [(set (match_dup 0)
3808 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3809 (set (match_dup 4)
3810 (compare:CC (match_dup 0)
3811 (const_int 0)))]
3812 "")
3813
3814 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3815 ;; "sli x,x,0".
3816 (define_expand "lshrsi3"
3817 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3818 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3819 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3820 ""
3821 "
3822 {
3823 if (TARGET_POWER)
3824 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3825 else
3826 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3827 DONE;
3828 }")
3829
3830 (define_insn "lshrsi3_power"
3831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3832 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3833 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3834 (clobber (match_scratch:SI 3 "=q,X,X"))]
3835 "TARGET_POWER"
3836 "@
3837 sre %0,%1,%2
3838 mr %0,%1
3839 {s%A2i|s%A2wi} %0,%1,%h2")
3840
3841 (define_insn "lshrsi3_no_power"
3842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3843 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3845 "! TARGET_POWER"
3846 "@
3847 mr %0,%1
3848 {sr|srw}%I2 %0,%1,%h2")
3849
3850 (define_insn ""
3851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3852 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3853 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3854 (const_int 0)))
3855 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3856 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3857 "TARGET_POWER"
3858 "@
3859 sre. %3,%1,%2
3860 mr. %1,%1
3861 {s%A2i.|s%A2wi.} %3,%1,%h2
3862 #
3863 #
3864 #"
3865 [(set_attr "type" "delayed_compare")
3866 (set_attr "length" "4,4,4,8,8,8")])
3867
3868 (define_split
3869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3870 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3871 (match_operand:SI 2 "reg_or_cint_operand" ""))
3872 (const_int 0)))
3873 (clobber (match_scratch:SI 3 ""))
3874 (clobber (match_scratch:SI 4 ""))]
3875 "TARGET_POWER && reload_completed"
3876 [(parallel [(set (match_dup 3)
3877 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3878 (clobber (match_dup 4))])
3879 (set (match_dup 0)
3880 (compare:CC (match_dup 3)
3881 (const_int 0)))]
3882 "")
3883
3884 (define_insn ""
3885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3888 (const_int 0)))
3889 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3890 "! TARGET_POWER && TARGET_32BIT"
3891 "@
3892 mr. %1,%1
3893 {sr|srw}%I2. %3,%1,%h2
3894 #
3895 #"
3896 [(set_attr "type" "delayed_compare")
3897 (set_attr "length" "4,4,8,8")])
3898
3899 (define_split
3900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3901 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3902 (match_operand:SI 2 "reg_or_cint_operand" ""))
3903 (const_int 0)))
3904 (clobber (match_scratch:SI 3 ""))]
3905 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3906 [(set (match_dup 3)
3907 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3908 (set (match_dup 0)
3909 (compare:CC (match_dup 3)
3910 (const_int 0)))]
3911 "")
3912
3913 (define_insn ""
3914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3915 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3916 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3917 (const_int 0)))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3919 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3920 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3921 "TARGET_POWER"
3922 "@
3923 sre. %0,%1,%2
3924 mr. %0,%1
3925 {s%A2i.|s%A2wi.} %0,%1,%h2
3926 #
3927 #
3928 #"
3929 [(set_attr "type" "delayed_compare")
3930 (set_attr "length" "4,4,4,8,8,8")])
3931
3932 (define_split
3933 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3934 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3935 (match_operand:SI 2 "reg_or_cint_operand" ""))
3936 (const_int 0)))
3937 (set (match_operand:SI 0 "gpc_reg_operand" "")
3938 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3939 (clobber (match_scratch:SI 4 ""))]
3940 "TARGET_POWER && reload_completed"
3941 [(parallel [(set (match_dup 0)
3942 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3943 (clobber (match_dup 4))])
3944 (set (match_dup 3)
3945 (compare:CC (match_dup 0)
3946 (const_int 0)))]
3947 "")
3948
3949 (define_insn ""
3950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3951 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3952 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3953 (const_int 0)))
3954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3955 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3956 "! TARGET_POWER && TARGET_32BIT"
3957 "@
3958 mr. %0,%1
3959 {sr|srw}%I2. %0,%1,%h2
3960 #
3961 #"
3962 [(set_attr "type" "delayed_compare")
3963 (set_attr "length" "4,4,8,8")])
3964
3965 (define_split
3966 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3967 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3968 (match_operand:SI 2 "reg_or_cint_operand" ""))
3969 (const_int 0)))
3970 (set (match_operand:SI 0 "gpc_reg_operand" "")
3971 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3972 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3973 [(set (match_dup 0)
3974 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3975 (set (match_dup 3)
3976 (compare:CC (match_dup 0)
3977 (const_int 0)))]
3978 "")
3979
3980 (define_insn ""
3981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3982 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3983 (match_operand:SI 2 "const_int_operand" "i"))
3984 (match_operand:SI 3 "mask_operand" "n")))]
3985 "includes_rshift_p (operands[2], operands[3])"
3986 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3987
3988 (define_insn ""
3989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3990 (compare:CC
3991 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3992 (match_operand:SI 2 "const_int_operand" "i,i"))
3993 (match_operand:SI 3 "mask_operand" "n,n"))
3994 (const_int 0)))
3995 (clobber (match_scratch:SI 4 "=r,r"))]
3996 "includes_rshift_p (operands[2], operands[3])"
3997 "@
3998 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3999 #"
4000 [(set_attr "type" "delayed_compare")
4001 (set_attr "length" "4,8")])
4002
4003 (define_split
4004 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4005 (compare:CC
4006 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "const_int_operand" ""))
4008 (match_operand:SI 3 "mask_operand" ""))
4009 (const_int 0)))
4010 (clobber (match_scratch:SI 4 ""))]
4011 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4012 [(set (match_dup 4)
4013 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4014 (match_dup 3)))
4015 (set (match_dup 0)
4016 (compare:CC (match_dup 4)
4017 (const_int 0)))]
4018 "")
4019
4020 (define_insn ""
4021 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4022 (compare:CC
4023 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4024 (match_operand:SI 2 "const_int_operand" "i,i"))
4025 (match_operand:SI 3 "mask_operand" "n,n"))
4026 (const_int 0)))
4027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4028 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4029 "includes_rshift_p (operands[2], operands[3])"
4030 "@
4031 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4032 #"
4033 [(set_attr "type" "delayed_compare")
4034 (set_attr "length" "4,8")])
4035
4036 (define_split
4037 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4038 (compare:CC
4039 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4040 (match_operand:SI 2 "const_int_operand" ""))
4041 (match_operand:SI 3 "mask_operand" ""))
4042 (const_int 0)))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "")
4044 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4045 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4046 [(set (match_dup 0)
4047 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4048 (set (match_dup 4)
4049 (compare:CC (match_dup 0)
4050 (const_int 0)))]
4051 "")
4052
4053 (define_insn ""
4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4055 (zero_extend:SI
4056 (subreg:QI
4057 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4058 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4059 "includes_rshift_p (operands[2], GEN_INT (255))"
4060 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4061
4062 (define_insn ""
4063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4064 (compare:CC
4065 (zero_extend:SI
4066 (subreg:QI
4067 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4068 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4069 (const_int 0)))
4070 (clobber (match_scratch:SI 3 "=r,r"))]
4071 "includes_rshift_p (operands[2], GEN_INT (255))"
4072 "@
4073 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4074 #"
4075 [(set_attr "type" "delayed_compare")
4076 (set_attr "length" "4,8")])
4077
4078 (define_split
4079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4080 (compare:CC
4081 (zero_extend:SI
4082 (subreg:QI
4083 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4084 (match_operand:SI 2 "const_int_operand" "")) 0))
4085 (const_int 0)))
4086 (clobber (match_scratch:SI 3 ""))]
4087 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4088 [(set (match_dup 3)
4089 (zero_extend:SI (subreg:QI
4090 (lshiftrt:SI (match_dup 1)
4091 (match_dup 2)) 0)))
4092 (set (match_dup 0)
4093 (compare:CC (match_dup 3)
4094 (const_int 0)))]
4095 "")
4096
4097 (define_insn ""
4098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4099 (compare:CC
4100 (zero_extend:SI
4101 (subreg:QI
4102 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4103 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4104 (const_int 0)))
4105 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4106 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4107 "includes_rshift_p (operands[2], GEN_INT (255))"
4108 "@
4109 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4110 #"
4111 [(set_attr "type" "delayed_compare")
4112 (set_attr "length" "4,8")])
4113
4114 (define_split
4115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4116 (compare:CC
4117 (zero_extend:SI
4118 (subreg:QI
4119 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4120 (match_operand:SI 2 "const_int_operand" "")) 0))
4121 (const_int 0)))
4122 (set (match_operand:SI 0 "gpc_reg_operand" "")
4123 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4124 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4125 [(set (match_dup 0)
4126 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4127 (set (match_dup 3)
4128 (compare:CC (match_dup 0)
4129 (const_int 0)))]
4130 "")
4131
4132 (define_insn ""
4133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4134 (zero_extend:SI
4135 (subreg:HI
4136 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4137 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4138 "includes_rshift_p (operands[2], GEN_INT (65535))"
4139 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4140
4141 (define_insn ""
4142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4143 (compare:CC
4144 (zero_extend:SI
4145 (subreg:HI
4146 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4148 (const_int 0)))
4149 (clobber (match_scratch:SI 3 "=r,r"))]
4150 "includes_rshift_p (operands[2], GEN_INT (65535))"
4151 "@
4152 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4153 #"
4154 [(set_attr "type" "delayed_compare")
4155 (set_attr "length" "4,8")])
4156
4157 (define_split
4158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4159 (compare:CC
4160 (zero_extend:SI
4161 (subreg:HI
4162 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4163 (match_operand:SI 2 "const_int_operand" "")) 0))
4164 (const_int 0)))
4165 (clobber (match_scratch:SI 3 ""))]
4166 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4167 [(set (match_dup 3)
4168 (zero_extend:SI (subreg:HI
4169 (lshiftrt:SI (match_dup 1)
4170 (match_dup 2)) 0)))
4171 (set (match_dup 0)
4172 (compare:CC (match_dup 3)
4173 (const_int 0)))]
4174 "")
4175
4176 (define_insn ""
4177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4178 (compare:CC
4179 (zero_extend:SI
4180 (subreg:HI
4181 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4182 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4183 (const_int 0)))
4184 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4185 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4186 "includes_rshift_p (operands[2], GEN_INT (65535))"
4187 "@
4188 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4189 #"
4190 [(set_attr "type" "delayed_compare")
4191 (set_attr "length" "4,8")])
4192
4193 (define_split
4194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4195 (compare:CC
4196 (zero_extend:SI
4197 (subreg:HI
4198 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4199 (match_operand:SI 2 "const_int_operand" "")) 0))
4200 (const_int 0)))
4201 (set (match_operand:SI 0 "gpc_reg_operand" "")
4202 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4203 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4204 [(set (match_dup 0)
4205 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4206 (set (match_dup 3)
4207 (compare:CC (match_dup 0)
4208 (const_int 0)))]
4209 "")
4210
4211 (define_insn ""
4212 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4213 (const_int 1)
4214 (match_operand:SI 1 "gpc_reg_operand" "r"))
4215 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4216 (const_int 31)))]
4217 "TARGET_POWER"
4218 "rrib %0,%1,%2")
4219
4220 (define_insn ""
4221 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4222 (const_int 1)
4223 (match_operand:SI 1 "gpc_reg_operand" "r"))
4224 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4225 (const_int 31)))]
4226 "TARGET_POWER"
4227 "rrib %0,%1,%2")
4228
4229 (define_insn ""
4230 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4231 (const_int 1)
4232 (match_operand:SI 1 "gpc_reg_operand" "r"))
4233 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4234 (const_int 1)
4235 (const_int 0)))]
4236 "TARGET_POWER"
4237 "rrib %0,%1,%2")
4238
4239 (define_expand "ashrsi3"
4240 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4241 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4242 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4243 ""
4244 "
4245 {
4246 if (TARGET_POWER)
4247 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4248 else
4249 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4250 DONE;
4251 }")
4252
4253 (define_insn "ashrsi3_power"
4254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4255 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4256 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4257 (clobber (match_scratch:SI 3 "=q,X"))]
4258 "TARGET_POWER"
4259 "@
4260 srea %0,%1,%2
4261 {srai|srawi} %0,%1,%h2")
4262
4263 (define_insn "ashrsi3_no_power"
4264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4265 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4266 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4267 "! TARGET_POWER"
4268 "{sra|sraw}%I2 %0,%1,%h2")
4269
4270 (define_insn ""
4271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4272 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4273 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4274 (const_int 0)))
4275 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4276 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4277 "TARGET_POWER"
4278 "@
4279 srea. %3,%1,%2
4280 {srai.|srawi.} %3,%1,%h2
4281 #
4282 #"
4283 [(set_attr "type" "delayed_compare")
4284 (set_attr "length" "4,4,8,8")])
4285
4286 (define_split
4287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4288 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4289 (match_operand:SI 2 "reg_or_cint_operand" ""))
4290 (const_int 0)))
4291 (clobber (match_scratch:SI 3 ""))
4292 (clobber (match_scratch:SI 4 ""))]
4293 "TARGET_POWER && reload_completed"
4294 [(parallel [(set (match_dup 3)
4295 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4296 (clobber (match_dup 4))])
4297 (set (match_dup 0)
4298 (compare:CC (match_dup 3)
4299 (const_int 0)))]
4300 "")
4301
4302 (define_insn ""
4303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4304 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4305 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4306 (const_int 0)))
4307 (clobber (match_scratch:SI 3 "=r,r"))]
4308 "! TARGET_POWER"
4309 "@
4310 {sra|sraw}%I2. %3,%1,%h2
4311 #"
4312 [(set_attr "type" "delayed_compare")
4313 (set_attr "length" "4,8")])
4314
4315 (define_split
4316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4317 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4318 (match_operand:SI 2 "reg_or_cint_operand" ""))
4319 (const_int 0)))
4320 (clobber (match_scratch:SI 3 ""))]
4321 "! TARGET_POWER && reload_completed"
4322 [(set (match_dup 3)
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4324 (set (match_dup 0)
4325 (compare:CC (match_dup 3)
4326 (const_int 0)))]
4327 "")
4328
4329 (define_insn ""
4330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4331 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4332 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4333 (const_int 0)))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4335 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4337 "TARGET_POWER"
4338 "@
4339 srea. %0,%1,%2
4340 {srai.|srawi.} %0,%1,%h2
4341 #
4342 #"
4343 [(set_attr "type" "delayed_compare")
4344 (set_attr "length" "4,4,8,8")])
4345
4346 (define_split
4347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4348 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4349 (match_operand:SI 2 "reg_or_cint_operand" ""))
4350 (const_int 0)))
4351 (set (match_operand:SI 0 "gpc_reg_operand" "")
4352 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4353 (clobber (match_scratch:SI 4 ""))]
4354 "TARGET_POWER && reload_completed"
4355 [(parallel [(set (match_dup 0)
4356 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4357 (clobber (match_dup 4))])
4358 (set (match_dup 3)
4359 (compare:CC (match_dup 0)
4360 (const_int 0)))]
4361 "")
4362
4363 (define_insn ""
4364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4365 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4366 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4367 (const_int 0)))
4368 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4369 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4370 "! TARGET_POWER"
4371 "@
4372 {sra|sraw}%I2. %0,%1,%h2
4373 #"
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,8")])
4376 \f
4377 (define_split
4378 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4379 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "reg_or_cint_operand" ""))
4381 (const_int 0)))
4382 (set (match_operand:SI 0 "gpc_reg_operand" "")
4383 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4384 "! TARGET_POWER && reload_completed"
4385 [(set (match_dup 0)
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4387 (set (match_dup 3)
4388 (compare:CC (match_dup 0)
4389 (const_int 0)))]
4390 "")
4391
4392 ;; Floating-point insns, excluding normal data motion.
4393 ;;
4394 ;; PowerPC has a full set of single-precision floating point instructions.
4395 ;;
4396 ;; For the POWER architecture, we pretend that we have both SFmode and
4397 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4398 ;; The only conversions we will do will be when storing to memory. In that
4399 ;; case, we will use the "frsp" instruction before storing.
4400 ;;
4401 ;; Note that when we store into a single-precision memory location, we need to
4402 ;; use the frsp insn first. If the register being stored isn't dead, we
4403 ;; need a scratch register for the frsp. But this is difficult when the store
4404 ;; is done by reload. It is not incorrect to do the frsp on the register in
4405 ;; this case, we just lose precision that we would have otherwise gotten but
4406 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4407
4408 (define_expand "extendsfdf2"
4409 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4410 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
4411 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4412 "")
4413
4414 (define_insn_and_split "*extendsfdf2_fpr"
4415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
4416 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
4417 "TARGET_HARD_FLOAT && TARGET_FPRS"
4418 "@
4419 #
4420 fmr %0,%1"
4421 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
4422 [(const_int 0)]
4423 {
4424 emit_note (NOTE_INSN_DELETED);
4425 DONE;
4426 }
4427 [(set_attr "type" "fp")])
4428
4429 (define_expand "truncdfsf2"
4430 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4431 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4432 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4433 "")
4434
4435 (define_insn "*truncdfsf2_fpr"
4436 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4437 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4438 "TARGET_HARD_FLOAT && TARGET_FPRS"
4439 "frsp %0,%1"
4440 [(set_attr "type" "fp")])
4441
4442 (define_insn "aux_truncdfsf2"
4443 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4444 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4445 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4446 "frsp %0,%1"
4447 [(set_attr "type" "fp")])
4448
4449 (define_expand "negsf2"
4450 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4451 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4452 "TARGET_HARD_FLOAT"
4453 "")
4454
4455 (define_insn "*negsf2"
4456 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4457 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4458 "TARGET_HARD_FLOAT && TARGET_FPRS"
4459 "fneg %0,%1"
4460 [(set_attr "type" "fp")])
4461
4462 (define_expand "abssf2"
4463 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4464 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4465 "TARGET_HARD_FLOAT"
4466 "")
4467
4468 (define_insn "*abssf2"
4469 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4470 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4471 "TARGET_HARD_FLOAT && TARGET_FPRS"
4472 "fabs %0,%1"
4473 [(set_attr "type" "fp")])
4474
4475 (define_insn ""
4476 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4477 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4478 "TARGET_HARD_FLOAT && TARGET_FPRS"
4479 "fnabs %0,%1"
4480 [(set_attr "type" "fp")])
4481
4482 (define_expand "addsf3"
4483 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4484 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4485 (match_operand:SF 2 "gpc_reg_operand" "")))]
4486 "TARGET_HARD_FLOAT"
4487 "")
4488
4489 (define_insn ""
4490 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4491 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4492 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4493 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4494 "fadds %0,%1,%2"
4495 [(set_attr "type" "fp")])
4496
4497 (define_insn ""
4498 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4499 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4500 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4501 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4502 "{fa|fadd} %0,%1,%2"
4503 [(set_attr "type" "fp")])
4504
4505 (define_expand "subsf3"
4506 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4507 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4508 (match_operand:SF 2 "gpc_reg_operand" "")))]
4509 "TARGET_HARD_FLOAT"
4510 "")
4511
4512 (define_insn ""
4513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4514 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4515 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4516 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4517 "fsubs %0,%1,%2"
4518 [(set_attr "type" "fp")])
4519
4520 (define_insn ""
4521 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4522 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4523 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4524 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4525 "{fs|fsub} %0,%1,%2"
4526 [(set_attr "type" "fp")])
4527
4528 (define_expand "mulsf3"
4529 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4530 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4531 (match_operand:SF 2 "gpc_reg_operand" "")))]
4532 "TARGET_HARD_FLOAT"
4533 "")
4534
4535 (define_insn ""
4536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4537 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4538 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4539 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4540 "fmuls %0,%1,%2"
4541 [(set_attr "type" "fp")])
4542
4543 (define_insn ""
4544 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4545 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4546 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4547 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4548 "{fm|fmul} %0,%1,%2"
4549 [(set_attr "type" "dmul")])
4550
4551 (define_expand "divsf3"
4552 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4553 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4554 (match_operand:SF 2 "gpc_reg_operand" "")))]
4555 "TARGET_HARD_FLOAT"
4556 "")
4557
4558 (define_insn ""
4559 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4560 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4561 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4562 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4563 "fdivs %0,%1,%2"
4564 [(set_attr "type" "sdiv")])
4565
4566 (define_insn ""
4567 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4568 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4569 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4570 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4571 "{fd|fdiv} %0,%1,%2"
4572 [(set_attr "type" "ddiv")])
4573
4574 (define_insn ""
4575 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4576 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4577 (match_operand:SF 2 "gpc_reg_operand" "f"))
4578 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4579 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4580 "fmadds %0,%1,%2,%3"
4581 [(set_attr "type" "fp")])
4582
4583 (define_insn ""
4584 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4585 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4586 (match_operand:SF 2 "gpc_reg_operand" "f"))
4587 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4588 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4589 "{fma|fmadd} %0,%1,%2,%3"
4590 [(set_attr "type" "dmul")])
4591
4592 (define_insn ""
4593 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4594 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4595 (match_operand:SF 2 "gpc_reg_operand" "f"))
4596 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4597 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4598 "fmsubs %0,%1,%2,%3"
4599 [(set_attr "type" "fp")])
4600
4601 (define_insn ""
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4604 (match_operand:SF 2 "gpc_reg_operand" "f"))
4605 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4606 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4607 "{fms|fmsub} %0,%1,%2,%3"
4608 [(set_attr "type" "dmul")])
4609
4610 (define_insn ""
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4613 (match_operand:SF 2 "gpc_reg_operand" "f"))
4614 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4615 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4616 && HONOR_SIGNED_ZEROS (SFmode)"
4617 "fnmadds %0,%1,%2,%3"
4618 [(set_attr "type" "fp")])
4619
4620 (define_insn ""
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4622 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4623 (match_operand:SF 2 "gpc_reg_operand" "f"))
4624 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4625 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4626 && ! HONOR_SIGNED_ZEROS (SFmode)"
4627 "fnmadds %0,%1,%2,%3"
4628 [(set_attr "type" "fp")])
4629
4630 (define_insn ""
4631 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4632 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4633 (match_operand:SF 2 "gpc_reg_operand" "f"))
4634 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4635 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4636 "{fnma|fnmadd} %0,%1,%2,%3"
4637 [(set_attr "type" "dmul")])
4638
4639 (define_insn ""
4640 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4641 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4642 (match_operand:SF 2 "gpc_reg_operand" "f"))
4643 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4644 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4645 && ! HONOR_SIGNED_ZEROS (SFmode)"
4646 "{fnma|fnmadd} %0,%1,%2,%3"
4647 [(set_attr "type" "dmul")])
4648
4649 (define_insn ""
4650 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4651 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4652 (match_operand:SF 2 "gpc_reg_operand" "f"))
4653 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4654 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4655 && HONOR_SIGNED_ZEROS (SFmode)"
4656 "fnmsubs %0,%1,%2,%3"
4657 [(set_attr "type" "fp")])
4658
4659 (define_insn ""
4660 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4661 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4662 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4663 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4664 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4665 && ! HONOR_SIGNED_ZEROS (SFmode)"
4666 "fnmsubs %0,%1,%2,%3"
4667 [(set_attr "type" "fp")])
4668
4669 (define_insn ""
4670 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4671 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4672 (match_operand:SF 2 "gpc_reg_operand" "f"))
4673 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4674 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4675 "{fnms|fnmsub} %0,%1,%2,%3"
4676 [(set_attr "type" "dmul")])
4677
4678 (define_insn ""
4679 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4680 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4681 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4682 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4683 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4684 && ! HONOR_SIGNED_ZEROS (SFmode)"
4685 "{fnms|fnmsub} %0,%1,%2,%3"
4686 [(set_attr "type" "fp")])
4687
4688 (define_expand "sqrtsf2"
4689 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4690 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4691 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4692 "")
4693
4694 (define_insn ""
4695 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4696 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4697 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4698 "fsqrts %0,%1"
4699 [(set_attr "type" "ssqrt")])
4700
4701 (define_insn ""
4702 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4703 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4704 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4705 "fsqrt %0,%1"
4706 [(set_attr "type" "dsqrt")])
4707
4708 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4709 ;; fsel instruction and some auxiliary computations. Then we just have a
4710 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4711 ;; combine.
4712 (define_expand "maxsf3"
4713 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4714 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4715 (match_operand:SF 2 "gpc_reg_operand" ""))
4716 (match_dup 1)
4717 (match_dup 2)))]
4718 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4719 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4720
4721 (define_expand "minsf3"
4722 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4723 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4724 (match_operand:SF 2 "gpc_reg_operand" ""))
4725 (match_dup 2)
4726 (match_dup 1)))]
4727 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4728 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4729
4730 (define_split
4731 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4732 (match_operator:SF 3 "min_max_operator"
4733 [(match_operand:SF 1 "gpc_reg_operand" "")
4734 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4735 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4736 [(const_int 0)]
4737 "
4738 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4739 operands[1], operands[2]);
4740 DONE;
4741 }")
4742
4743 (define_expand "movsicc"
4744 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4745 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4746 (match_operand:SI 2 "gpc_reg_operand" "")
4747 (match_operand:SI 3 "gpc_reg_operand" "")))]
4748 "TARGET_ISEL"
4749 "
4750 {
4751 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4752 DONE;
4753 else
4754 FAIL;
4755 }")
4756
4757 ;; We use the BASE_REGS for the isel input operands because, if rA is
4758 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4759 ;; because we may switch the operands and rB may end up being rA.
4760 ;;
4761 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4762 ;; leave out the mode in operand 4 and use one pattern, but reload can
4763 ;; change the mode underneath our feet and then gets confused trying
4764 ;; to reload the value.
4765 (define_insn "isel_signed"
4766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4767 (if_then_else:SI
4768 (match_operator 1 "comparison_operator"
4769 [(match_operand:CC 4 "cc_reg_operand" "y")
4770 (const_int 0)])
4771 (match_operand:SI 2 "gpc_reg_operand" "b")
4772 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4773 "TARGET_ISEL"
4774 "*
4775 { return output_isel (operands); }"
4776 [(set_attr "length" "4")])
4777
4778 (define_insn "isel_unsigned"
4779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4780 (if_then_else:SI
4781 (match_operator 1 "comparison_operator"
4782 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4783 (const_int 0)])
4784 (match_operand:SI 2 "gpc_reg_operand" "b")
4785 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4786 "TARGET_ISEL"
4787 "*
4788 { return output_isel (operands); }"
4789 [(set_attr "length" "4")])
4790
4791 (define_expand "movsfcc"
4792 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4793 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4794 (match_operand:SF 2 "gpc_reg_operand" "")
4795 (match_operand:SF 3 "gpc_reg_operand" "")))]
4796 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4797 "
4798 {
4799 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4800 DONE;
4801 else
4802 FAIL;
4803 }")
4804
4805 (define_insn "*fselsfsf4"
4806 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4807 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4808 (match_operand:SF 4 "zero_fp_constant" "F"))
4809 (match_operand:SF 2 "gpc_reg_operand" "f")
4810 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4811 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4812 "fsel %0,%1,%2,%3"
4813 [(set_attr "type" "fp")])
4814
4815 (define_insn "*fseldfsf4"
4816 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4817 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4818 (match_operand:DF 4 "zero_fp_constant" "F"))
4819 (match_operand:SF 2 "gpc_reg_operand" "f")
4820 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4821 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4822 "fsel %0,%1,%2,%3"
4823 [(set_attr "type" "fp")])
4824
4825 (define_expand "negdf2"
4826 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4827 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4828 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4829 "")
4830
4831 (define_insn "*negdf2_fpr"
4832 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4833 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4834 "TARGET_HARD_FLOAT && TARGET_FPRS"
4835 "fneg %0,%1"
4836 [(set_attr "type" "fp")])
4837
4838 (define_expand "absdf2"
4839 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4840 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4841 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4842 "")
4843
4844 (define_insn "*absdf2_fpr"
4845 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4846 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4847 "TARGET_HARD_FLOAT && TARGET_FPRS"
4848 "fabs %0,%1"
4849 [(set_attr "type" "fp")])
4850
4851 (define_insn "*nabsdf2_fpr"
4852 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4853 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4854 "TARGET_HARD_FLOAT && TARGET_FPRS"
4855 "fnabs %0,%1"
4856 [(set_attr "type" "fp")])
4857
4858 (define_expand "adddf3"
4859 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4860 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4861 (match_operand:DF 2 "gpc_reg_operand" "")))]
4862 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4863 "")
4864
4865 (define_insn "*adddf3_fpr"
4866 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4867 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4868 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4869 "TARGET_HARD_FLOAT && TARGET_FPRS"
4870 "{fa|fadd} %0,%1,%2"
4871 [(set_attr "type" "fp")])
4872
4873 (define_expand "subdf3"
4874 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4875 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4876 (match_operand:DF 2 "gpc_reg_operand" "")))]
4877 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4878 "")
4879
4880 (define_insn "*subdf3_fpr"
4881 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4882 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4883 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4884 "TARGET_HARD_FLOAT && TARGET_FPRS"
4885 "{fs|fsub} %0,%1,%2"
4886 [(set_attr "type" "fp")])
4887
4888 (define_expand "muldf3"
4889 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4890 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4891 (match_operand:DF 2 "gpc_reg_operand" "")))]
4892 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4893 "")
4894
4895 (define_insn "*muldf3_fpr"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4897 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4898 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4899 "TARGET_HARD_FLOAT && TARGET_FPRS"
4900 "{fm|fmul} %0,%1,%2"
4901 [(set_attr "type" "dmul")])
4902
4903 (define_expand "divdf3"
4904 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4905 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4906 (match_operand:DF 2 "gpc_reg_operand" "")))]
4907 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4908 "")
4909
4910 (define_insn "*divdf3_fpr"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4912 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4913 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4914 "TARGET_HARD_FLOAT && TARGET_FPRS"
4915 "{fd|fdiv} %0,%1,%2"
4916 [(set_attr "type" "ddiv")])
4917
4918 (define_insn ""
4919 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4920 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4921 (match_operand:DF 2 "gpc_reg_operand" "f"))
4922 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4923 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4924 "{fma|fmadd} %0,%1,%2,%3"
4925 [(set_attr "type" "dmul")])
4926
4927 (define_insn ""
4928 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4929 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4930 (match_operand:DF 2 "gpc_reg_operand" "f"))
4931 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4932 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4933 "{fms|fmsub} %0,%1,%2,%3"
4934 [(set_attr "type" "dmul")])
4935
4936 (define_insn ""
4937 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4938 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4939 (match_operand:DF 2 "gpc_reg_operand" "f"))
4940 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4941 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4942 && HONOR_SIGNED_ZEROS (DFmode)"
4943 "{fnma|fnmadd} %0,%1,%2,%3"
4944 [(set_attr "type" "dmul")])
4945
4946 (define_insn ""
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4948 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4949 (match_operand:DF 2 "gpc_reg_operand" "f"))
4950 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4951 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4952 && ! HONOR_SIGNED_ZEROS (DFmode)"
4953 "{fnma|fnmadd} %0,%1,%2,%3"
4954 [(set_attr "type" "dmul")])
4955
4956 (define_insn ""
4957 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4958 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4959 (match_operand:DF 2 "gpc_reg_operand" "f"))
4960 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4961 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4962 && HONOR_SIGNED_ZEROS (DFmode)"
4963 "{fnms|fnmsub} %0,%1,%2,%3"
4964 [(set_attr "type" "dmul")])
4965
4966 (define_insn ""
4967 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4968 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4969 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4970 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4971 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4972 && ! HONOR_SIGNED_ZEROS (DFmode)"
4973 "{fnms|fnmsub} %0,%1,%2,%3"
4974 [(set_attr "type" "dmul")])
4975
4976 (define_insn "sqrtdf2"
4977 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4978 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4979 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4980 "fsqrt %0,%1"
4981 [(set_attr "type" "dsqrt")])
4982
4983 ;; The conditional move instructions allow us to perform max and min
4984 ;; operations even when
4985
4986 (define_expand "maxdf3"
4987 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4988 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4989 (match_operand:DF 2 "gpc_reg_operand" ""))
4990 (match_dup 1)
4991 (match_dup 2)))]
4992 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4993 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4994
4995 (define_expand "mindf3"
4996 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4997 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4998 (match_operand:DF 2 "gpc_reg_operand" ""))
4999 (match_dup 2)
5000 (match_dup 1)))]
5001 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5002 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5003
5004 (define_split
5005 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5006 (match_operator:DF 3 "min_max_operator"
5007 [(match_operand:DF 1 "gpc_reg_operand" "")
5008 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5009 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5010 [(const_int 0)]
5011 "
5012 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5013 operands[1], operands[2]);
5014 DONE;
5015 }")
5016
5017 (define_expand "movdfcc"
5018 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5019 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5020 (match_operand:DF 2 "gpc_reg_operand" "")
5021 (match_operand:DF 3 "gpc_reg_operand" "")))]
5022 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5023 "
5024 {
5025 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5026 DONE;
5027 else
5028 FAIL;
5029 }")
5030
5031 (define_insn "*fseldfdf4"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5033 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5034 (match_operand:DF 4 "zero_fp_constant" "F"))
5035 (match_operand:DF 2 "gpc_reg_operand" "f")
5036 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5037 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5038 "fsel %0,%1,%2,%3"
5039 [(set_attr "type" "fp")])
5040
5041 (define_insn "*fselsfdf4"
5042 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5043 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5044 (match_operand:SF 4 "zero_fp_constant" "F"))
5045 (match_operand:DF 2 "gpc_reg_operand" "f")
5046 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5047 "TARGET_PPC_GFXOPT"
5048 "fsel %0,%1,%2,%3"
5049 [(set_attr "type" "fp")])
5050 \f
5051 ;; Conversions to and from floating-point.
5052
5053 (define_expand "fixuns_truncsfsi2"
5054 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5055 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5056 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5057 "")
5058
5059 (define_expand "fix_truncsfsi2"
5060 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5061 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5062 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5063 "")
5064
5065 ; For each of these conversions, there is a define_expand, a define_insn
5066 ; with a '#' template, and a define_split (with C code). The idea is
5067 ; to allow constant folding with the template of the define_insn,
5068 ; then to have the insns split later (between sched1 and final).
5069
5070 (define_expand "floatsidf2"
5071 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5072 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5073 (use (match_dup 2))
5074 (use (match_dup 3))
5075 (clobber (match_dup 4))
5076 (clobber (match_dup 5))
5077 (clobber (match_dup 6))])]
5078 "TARGET_HARD_FLOAT && TARGET_FPRS"
5079 "
5080 {
5081 if (TARGET_E500_DOUBLE)
5082 {
5083 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5084 DONE;
5085 }
5086 if (TARGET_POWERPC64)
5087 {
5088 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5089 rtx t1 = gen_reg_rtx (DImode);
5090 rtx t2 = gen_reg_rtx (DImode);
5091 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5092 DONE;
5093 }
5094
5095 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5096 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5097 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5098 operands[5] = gen_reg_rtx (DFmode);
5099 operands[6] = gen_reg_rtx (SImode);
5100 }")
5101
5102 (define_insn "*floatsidf2_internal"
5103 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5104 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5105 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5106 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5107 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5108 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5109 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5110 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5111 "#"
5112 [(set_attr "length" "24")])
5113
5114 (define_split
5115 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5116 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5117 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5118 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5119 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5120 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5121 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5122 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5123 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5124 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5125 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5126 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5127 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5128 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5129 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5130 "
5131 {
5132 rtx lowword, highword;
5133 if (GET_CODE (operands[4]) != MEM)
5134 abort();
5135 highword = XEXP (operands[4], 0);
5136 lowword = plus_constant (highword, 4);
5137 if (! WORDS_BIG_ENDIAN)
5138 {
5139 rtx tmp;
5140 tmp = highword; highword = lowword; lowword = tmp;
5141 }
5142
5143 emit_insn (gen_xorsi3 (operands[6], operands[1],
5144 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5145 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5146 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5147 emit_move_insn (operands[5], operands[4]);
5148 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5149 DONE;
5150 }")
5151
5152 (define_expand "floatunssisf2"
5153 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5154 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5155 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5156 "")
5157
5158 (define_expand "floatunssidf2"
5159 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5160 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5161 (use (match_dup 2))
5162 (use (match_dup 3))
5163 (clobber (match_dup 4))
5164 (clobber (match_dup 5))])]
5165 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5166 "
5167 {
5168 if (TARGET_E500_DOUBLE)
5169 {
5170 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5171 DONE;
5172 }
5173 if (TARGET_POWERPC64)
5174 {
5175 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5176 rtx t1 = gen_reg_rtx (DImode);
5177 rtx t2 = gen_reg_rtx (DImode);
5178 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5179 t1, t2));
5180 DONE;
5181 }
5182
5183 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5184 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5185 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5186 operands[5] = gen_reg_rtx (DFmode);
5187 }")
5188
5189 (define_insn "*floatunssidf2_internal"
5190 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5191 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5192 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5193 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5194 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5195 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5196 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5197 "#"
5198 [(set_attr "length" "20")])
5199
5200 (define_split
5201 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5202 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5203 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5204 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5205 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5206 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5207 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5208 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5209 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5210 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5211 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5212 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5213 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5214 "
5215 {
5216 rtx lowword, highword;
5217 if (GET_CODE (operands[4]) != MEM)
5218 abort();
5219 highword = XEXP (operands[4], 0);
5220 lowword = plus_constant (highword, 4);
5221 if (! WORDS_BIG_ENDIAN)
5222 {
5223 rtx tmp;
5224 tmp = highword; highword = lowword; lowword = tmp;
5225 }
5226
5227 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5228 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5229 emit_move_insn (operands[5], operands[4]);
5230 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5231 DONE;
5232 }")
5233
5234 (define_expand "fix_truncdfsi2"
5235 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5236 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5237 (clobber (match_dup 2))
5238 (clobber (match_dup 3))])]
5239 "(TARGET_POWER2 || TARGET_POWERPC)
5240 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5241 "
5242 {
5243 if (TARGET_E500_DOUBLE)
5244 {
5245 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5246 DONE;
5247 }
5248 operands[2] = gen_reg_rtx (DImode);
5249 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5250 }")
5251
5252 (define_insn "*fix_truncdfsi2_internal"
5253 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5254 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5255 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5256 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5257 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5258 "#"
5259 [(set_attr "length" "16")])
5260
5261 (define_split
5262 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5263 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5264 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5265 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5266 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5267 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5268 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5269 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5270 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5271 "
5272 {
5273 rtx lowword;
5274 if (GET_CODE (operands[3]) != MEM)
5275 abort();
5276 lowword = XEXP (operands[3], 0);
5277 if (WORDS_BIG_ENDIAN)
5278 lowword = plus_constant (lowword, 4);
5279
5280 emit_insn (gen_fctiwz (operands[2], operands[1]));
5281 emit_move_insn (operands[3], operands[2]);
5282 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5283 DONE;
5284 }")
5285
5286 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5287 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5288 ; because the first makes it clear that operand 0 is not live
5289 ; before the instruction.
5290 (define_insn "fctiwz"
5291 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5292 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5293 UNSPEC_FCTIWZ))]
5294 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5295 "{fcirz|fctiwz} %0,%1"
5296 [(set_attr "type" "fp")])
5297
5298 (define_expand "floatsisf2"
5299 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5300 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5301 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5302 "")
5303
5304 (define_insn "floatdidf2"
5305 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5306 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5307 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5308 "fcfid %0,%1"
5309 [(set_attr "type" "fp")])
5310
5311 (define_insn_and_split "floatsidf_ppc64"
5312 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5313 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5314 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5315 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5316 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5317 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5318 "#"
5319 "&& 1"
5320 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5321 (set (match_dup 2) (match_dup 3))
5322 (set (match_dup 4) (match_dup 2))
5323 (set (match_dup 0) (float:DF (match_dup 4)))]
5324 "")
5325
5326 (define_insn_and_split "floatunssidf_ppc64"
5327 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5328 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5329 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5330 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5331 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5332 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5333 "#"
5334 "&& 1"
5335 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5336 (set (match_dup 2) (match_dup 3))
5337 (set (match_dup 4) (match_dup 2))
5338 (set (match_dup 0) (float:DF (match_dup 4)))]
5339 "")
5340
5341 (define_insn "fix_truncdfdi2"
5342 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5343 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5344 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5345 "fctidz %0,%1"
5346 [(set_attr "type" "fp")])
5347
5348 (define_expand "floatdisf2"
5349 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5350 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5351 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5352 "
5353 {
5354 rtx val = operands[1];
5355 if (!flag_unsafe_math_optimizations)
5356 {
5357 rtx label = gen_label_rtx ();
5358 val = gen_reg_rtx (DImode);
5359 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5360 emit_label (label);
5361 }
5362 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5363 DONE;
5364 }")
5365
5366 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5367 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5368 ;; from double rounding.
5369 (define_insn_and_split "floatdisf2_internal1"
5370 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5371 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5372 (clobber (match_scratch:DF 2 "=f"))]
5373 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5374 "#"
5375 "&& reload_completed"
5376 [(set (match_dup 2)
5377 (float:DF (match_dup 1)))
5378 (set (match_dup 0)
5379 (float_truncate:SF (match_dup 2)))]
5380 "")
5381
5382 ;; Twiddles bits to avoid double rounding.
5383 ;; Bits that might be truncated when converting to DFmode are replaced
5384 ;; by a bit that won't be lost at that stage, but is below the SFmode
5385 ;; rounding position.
5386 (define_expand "floatdisf2_internal2"
5387 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5388 (const_int 53)))
5389 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5390 (const_int 2047)))
5391 (clobber (scratch:CC))])
5392 (set (match_dup 3) (plus:DI (match_dup 3)
5393 (const_int 1)))
5394 (set (match_dup 0) (plus:DI (match_dup 0)
5395 (const_int 2047)))
5396 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5397 (const_int 3)))
5398 (set (match_dup 0) (ior:DI (match_dup 0)
5399 (match_dup 1)))
5400 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5401 (const_int -2048)))
5402 (clobber (scratch:CC))])
5403 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5404 (label_ref (match_operand:DI 2 "" ""))
5405 (pc)))
5406 (set (match_dup 0) (match_dup 1))]
5407 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5408 "
5409 {
5410 operands[3] = gen_reg_rtx (DImode);
5411 operands[4] = gen_reg_rtx (CCUNSmode);
5412 }")
5413 \f
5414 ;; Define the DImode operations that can be done in a small number
5415 ;; of instructions. The & constraints are to prevent the register
5416 ;; allocator from allocating registers that overlap with the inputs
5417 ;; (for example, having an input in 7,8 and an output in 6,7). We
5418 ;; also allow for the output being the same as one of the inputs.
5419
5420 (define_insn "*adddi3_noppc64"
5421 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5422 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5423 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5424 "! TARGET_POWERPC64"
5425 "*
5426 {
5427 if (WORDS_BIG_ENDIAN)
5428 return (GET_CODE (operands[2])) != CONST_INT
5429 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5430 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5431 else
5432 return (GET_CODE (operands[2])) != CONST_INT
5433 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5434 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5435 }"
5436 [(set_attr "type" "two")
5437 (set_attr "length" "8")])
5438
5439 (define_insn "*subdi3_noppc64"
5440 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5441 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5442 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5443 "! TARGET_POWERPC64"
5444 "*
5445 {
5446 if (WORDS_BIG_ENDIAN)
5447 return (GET_CODE (operands[1]) != CONST_INT)
5448 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5449 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5450 else
5451 return (GET_CODE (operands[1]) != CONST_INT)
5452 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5453 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5454 }"
5455 [(set_attr "type" "two")
5456 (set_attr "length" "8")])
5457
5458 (define_insn "*negdi2_noppc64"
5459 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5460 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5461 "! TARGET_POWERPC64"
5462 "*
5463 {
5464 return (WORDS_BIG_ENDIAN)
5465 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5466 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5467 }"
5468 [(set_attr "type" "two")
5469 (set_attr "length" "8")])
5470
5471 (define_expand "mulsidi3"
5472 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5473 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5474 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5475 "! TARGET_POWERPC64"
5476 "
5477 {
5478 if (! TARGET_POWER && ! TARGET_POWERPC)
5479 {
5480 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5481 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5482 emit_insn (gen_mull_call ());
5483 if (WORDS_BIG_ENDIAN)
5484 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5485 else
5486 {
5487 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5488 gen_rtx_REG (SImode, 3));
5489 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5490 gen_rtx_REG (SImode, 4));
5491 }
5492 DONE;
5493 }
5494 else if (TARGET_POWER)
5495 {
5496 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5497 DONE;
5498 }
5499 }")
5500
5501 (define_insn "mulsidi3_mq"
5502 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5503 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5504 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5505 (clobber (match_scratch:SI 3 "=q"))]
5506 "TARGET_POWER"
5507 "mul %0,%1,%2\;mfmq %L0"
5508 [(set_attr "type" "imul")
5509 (set_attr "length" "8")])
5510
5511 (define_insn "*mulsidi3_no_mq"
5512 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5513 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5514 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5515 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5516 "*
5517 {
5518 return (WORDS_BIG_ENDIAN)
5519 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5520 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5521 }"
5522 [(set_attr "type" "imul")
5523 (set_attr "length" "8")])
5524
5525 (define_split
5526 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5527 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5528 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5529 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5530 [(set (match_dup 3)
5531 (truncate:SI
5532 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5533 (sign_extend:DI (match_dup 2)))
5534 (const_int 32))))
5535 (set (match_dup 4)
5536 (mult:SI (match_dup 1)
5537 (match_dup 2)))]
5538 "
5539 {
5540 int endian = (WORDS_BIG_ENDIAN == 0);
5541 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5542 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5543 }")
5544
5545 (define_expand "umulsidi3"
5546 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5547 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5548 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5549 "TARGET_POWERPC && ! TARGET_POWERPC64"
5550 "
5551 {
5552 if (TARGET_POWER)
5553 {
5554 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5555 DONE;
5556 }
5557 }")
5558
5559 (define_insn "umulsidi3_mq"
5560 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5561 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5562 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5563 (clobber (match_scratch:SI 3 "=q"))]
5564 "TARGET_POWERPC && TARGET_POWER"
5565 "*
5566 {
5567 return (WORDS_BIG_ENDIAN)
5568 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5569 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5570 }"
5571 [(set_attr "type" "imul")
5572 (set_attr "length" "8")])
5573
5574 (define_insn "*umulsidi3_no_mq"
5575 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5576 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5577 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5578 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5579 "*
5580 {
5581 return (WORDS_BIG_ENDIAN)
5582 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5583 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5584 }"
5585 [(set_attr "type" "imul")
5586 (set_attr "length" "8")])
5587
5588 (define_split
5589 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5590 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5591 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5592 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5593 [(set (match_dup 3)
5594 (truncate:SI
5595 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5596 (zero_extend:DI (match_dup 2)))
5597 (const_int 32))))
5598 (set (match_dup 4)
5599 (mult:SI (match_dup 1)
5600 (match_dup 2)))]
5601 "
5602 {
5603 int endian = (WORDS_BIG_ENDIAN == 0);
5604 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5605 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5606 }")
5607
5608 (define_expand "smulsi3_highpart"
5609 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5610 (truncate:SI
5611 (lshiftrt:DI (mult:DI (sign_extend:DI
5612 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5613 (sign_extend:DI
5614 (match_operand:SI 2 "gpc_reg_operand" "r")))
5615 (const_int 32))))]
5616 ""
5617 "
5618 {
5619 if (! TARGET_POWER && ! TARGET_POWERPC)
5620 {
5621 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5622 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5623 emit_insn (gen_mulh_call ());
5624 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5625 DONE;
5626 }
5627 else if (TARGET_POWER)
5628 {
5629 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5630 DONE;
5631 }
5632 }")
5633
5634 (define_insn "smulsi3_highpart_mq"
5635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5636 (truncate:SI
5637 (lshiftrt:DI (mult:DI (sign_extend:DI
5638 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5639 (sign_extend:DI
5640 (match_operand:SI 2 "gpc_reg_operand" "r")))
5641 (const_int 32))))
5642 (clobber (match_scratch:SI 3 "=q"))]
5643 "TARGET_POWER"
5644 "mul %0,%1,%2"
5645 [(set_attr "type" "imul")])
5646
5647 (define_insn "*smulsi3_highpart_no_mq"
5648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5649 (truncate:SI
5650 (lshiftrt:DI (mult:DI (sign_extend:DI
5651 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5652 (sign_extend:DI
5653 (match_operand:SI 2 "gpc_reg_operand" "r")))
5654 (const_int 32))))]
5655 "TARGET_POWERPC && ! TARGET_POWER"
5656 "mulhw %0,%1,%2"
5657 [(set_attr "type" "imul")])
5658
5659 (define_expand "umulsi3_highpart"
5660 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5661 (truncate:SI
5662 (lshiftrt:DI (mult:DI (zero_extend:DI
5663 (match_operand:SI 1 "gpc_reg_operand" ""))
5664 (zero_extend:DI
5665 (match_operand:SI 2 "gpc_reg_operand" "")))
5666 (const_int 32))))]
5667 "TARGET_POWERPC"
5668 "
5669 {
5670 if (TARGET_POWER)
5671 {
5672 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5673 DONE;
5674 }
5675 }")
5676
5677 (define_insn "umulsi3_highpart_mq"
5678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5679 (truncate:SI
5680 (lshiftrt:DI (mult:DI (zero_extend:DI
5681 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5682 (zero_extend:DI
5683 (match_operand:SI 2 "gpc_reg_operand" "r")))
5684 (const_int 32))))
5685 (clobber (match_scratch:SI 3 "=q"))]
5686 "TARGET_POWERPC && TARGET_POWER"
5687 "mulhwu %0,%1,%2"
5688 [(set_attr "type" "imul")])
5689
5690 (define_insn "*umulsi3_highpart_no_mq"
5691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5692 (truncate:SI
5693 (lshiftrt:DI (mult:DI (zero_extend:DI
5694 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5695 (zero_extend:DI
5696 (match_operand:SI 2 "gpc_reg_operand" "r")))
5697 (const_int 32))))]
5698 "TARGET_POWERPC && ! TARGET_POWER"
5699 "mulhwu %0,%1,%2"
5700 [(set_attr "type" "imul")])
5701
5702 ;; If operands 0 and 2 are in the same register, we have a problem. But
5703 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5704 ;; why we have the strange constraints below.
5705 (define_insn "ashldi3_power"
5706 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5707 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5708 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5709 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5710 "TARGET_POWER"
5711 "@
5712 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5713 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5714 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5715 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5716 [(set_attr "length" "8")])
5717
5718 (define_insn "lshrdi3_power"
5719 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5720 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5721 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5722 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5723 "TARGET_POWER"
5724 "@
5725 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5726 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5727 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5728 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5729 [(set_attr "length" "8")])
5730
5731 ;; Shift by a variable amount is too complex to be worth open-coding. We
5732 ;; just handle shifts by constants.
5733 (define_insn "ashrdi3_power"
5734 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5735 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5736 (match_operand:SI 2 "const_int_operand" "M,i")))
5737 (clobber (match_scratch:SI 3 "=X,q"))]
5738 "TARGET_POWER"
5739 "@
5740 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5741 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5742 [(set_attr "length" "8")])
5743
5744 (define_insn "ashrdi3_no_power"
5745 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5746 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5747 (match_operand:SI 2 "const_int_operand" "M,i")))]
5748 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5749 "@
5750 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5751 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5752 [(set_attr "type" "two,three")
5753 (set_attr "length" "8,12")])
5754
5755 (define_insn "*ashrdisi3_noppc64"
5756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5757 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5758 (const_int 32)) 4))]
5759 "TARGET_32BIT && !TARGET_POWERPC64"
5760 "*
5761 {
5762 if (REGNO (operands[0]) == REGNO (operands[1]))
5763 return \"\";
5764 else
5765 return \"mr %0,%1\";
5766 }"
5767 [(set_attr "length" "4")])
5768
5769 \f
5770 ;; PowerPC64 DImode operations.
5771
5772 (define_expand "adddi3"
5773 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5774 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5775 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5776 ""
5777 "
5778 {
5779 if (! TARGET_POWERPC64)
5780 {
5781 if (non_short_cint_operand (operands[2], DImode))
5782 FAIL;
5783 }
5784 else
5785 if (GET_CODE (operands[2]) == CONST_INT
5786 && ! add_operand (operands[2], DImode))
5787 {
5788 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5789 ? operands[0] : gen_reg_rtx (DImode));
5790
5791 HOST_WIDE_INT val = INTVAL (operands[2]);
5792 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5793 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5794
5795 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5796 FAIL;
5797
5798 /* The ordering here is important for the prolog expander.
5799 When space is allocated from the stack, adding 'low' first may
5800 produce a temporary deallocation (which would be bad). */
5801 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5802 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5803 DONE;
5804 }
5805 }")
5806
5807 ;; Discourage ai/addic because of carry but provide it in an alternative
5808 ;; allowing register zero as source.
5809
5810 (define_insn "*adddi3_internal1"
5811 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5812 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5813 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5814 "TARGET_POWERPC64"
5815 "@
5816 add %0,%1,%2
5817 addi %0,%1,%2
5818 addic %0,%1,%2
5819 addis %0,%1,%v2")
5820
5821 (define_insn "*adddi3_internal2"
5822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5823 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5824 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5825 (const_int 0)))
5826 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5827 "TARGET_64BIT"
5828 "@
5829 add. %3,%1,%2
5830 addic. %3,%1,%2
5831 #
5832 #"
5833 [(set_attr "type" "fast_compare,compare,compare,compare")
5834 (set_attr "length" "4,4,8,8")])
5835
5836 (define_split
5837 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5838 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5839 (match_operand:DI 2 "reg_or_short_operand" ""))
5840 (const_int 0)))
5841 (clobber (match_scratch:DI 3 ""))]
5842 "TARGET_POWERPC64 && reload_completed"
5843 [(set (match_dup 3)
5844 (plus:DI (match_dup 1) (match_dup 2)))
5845 (set (match_dup 0)
5846 (compare:CC (match_dup 3)
5847 (const_int 0)))]
5848 "")
5849
5850 (define_insn "*adddi3_internal3"
5851 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5852 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5853 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5854 (const_int 0)))
5855 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5856 (plus:DI (match_dup 1) (match_dup 2)))]
5857 "TARGET_64BIT"
5858 "@
5859 add. %0,%1,%2
5860 addic. %0,%1,%2
5861 #
5862 #"
5863 [(set_attr "type" "fast_compare,compare,compare,compare")
5864 (set_attr "length" "4,4,8,8")])
5865
5866 (define_split
5867 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5868 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5869 (match_operand:DI 2 "reg_or_short_operand" ""))
5870 (const_int 0)))
5871 (set (match_operand:DI 0 "gpc_reg_operand" "")
5872 (plus:DI (match_dup 1) (match_dup 2)))]
5873 "TARGET_POWERPC64 && reload_completed"
5874 [(set (match_dup 0)
5875 (plus:DI (match_dup 1) (match_dup 2)))
5876 (set (match_dup 3)
5877 (compare:CC (match_dup 0)
5878 (const_int 0)))]
5879 "")
5880
5881 ;; Split an add that we can't do in one insn into two insns, each of which
5882 ;; does one 16-bit part. This is used by combine. Note that the low-order
5883 ;; add should be last in case the result gets used in an address.
5884
5885 (define_split
5886 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5887 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5888 (match_operand:DI 2 "non_add_cint_operand" "")))]
5889 "TARGET_POWERPC64"
5890 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5891 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5892 "
5893 {
5894 HOST_WIDE_INT val = INTVAL (operands[2]);
5895 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5896 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5897
5898 operands[4] = GEN_INT (low);
5899 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5900 operands[3] = GEN_INT (rest);
5901 else if (! no_new_pseudos)
5902 {
5903 operands[3] = gen_reg_rtx (DImode);
5904 emit_move_insn (operands[3], operands[2]);
5905 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5906 DONE;
5907 }
5908 else
5909 FAIL;
5910 }")
5911
5912 (define_insn "one_cmpldi2"
5913 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5914 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5915 "TARGET_POWERPC64"
5916 "nor %0,%1,%1")
5917
5918 (define_insn ""
5919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5920 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5921 (const_int 0)))
5922 (clobber (match_scratch:DI 2 "=r,r"))]
5923 "TARGET_64BIT"
5924 "@
5925 nor. %2,%1,%1
5926 #"
5927 [(set_attr "type" "compare")
5928 (set_attr "length" "4,8")])
5929
5930 (define_split
5931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5932 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5933 (const_int 0)))
5934 (clobber (match_scratch:DI 2 ""))]
5935 "TARGET_POWERPC64 && reload_completed"
5936 [(set (match_dup 2)
5937 (not:DI (match_dup 1)))
5938 (set (match_dup 0)
5939 (compare:CC (match_dup 2)
5940 (const_int 0)))]
5941 "")
5942
5943 (define_insn ""
5944 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5945 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5946 (const_int 0)))
5947 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5948 (not:DI (match_dup 1)))]
5949 "TARGET_64BIT"
5950 "@
5951 nor. %0,%1,%1
5952 #"
5953 [(set_attr "type" "compare")
5954 (set_attr "length" "4,8")])
5955
5956 (define_split
5957 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5958 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5959 (const_int 0)))
5960 (set (match_operand:DI 0 "gpc_reg_operand" "")
5961 (not:DI (match_dup 1)))]
5962 "TARGET_POWERPC64 && reload_completed"
5963 [(set (match_dup 0)
5964 (not:DI (match_dup 1)))
5965 (set (match_dup 2)
5966 (compare:CC (match_dup 0)
5967 (const_int 0)))]
5968 "")
5969
5970 (define_insn ""
5971 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5972 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5973 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5974 "TARGET_POWERPC64"
5975 "@
5976 subf %0,%2,%1
5977 subfic %0,%2,%1")
5978
5979 (define_insn ""
5980 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5981 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5982 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5983 (const_int 0)))
5984 (clobber (match_scratch:DI 3 "=r,r"))]
5985 "TARGET_64BIT"
5986 "@
5987 subf. %3,%2,%1
5988 #"
5989 [(set_attr "type" "fast_compare")
5990 (set_attr "length" "4,8")])
5991
5992 (define_split
5993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5994 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5995 (match_operand:DI 2 "gpc_reg_operand" ""))
5996 (const_int 0)))
5997 (clobber (match_scratch:DI 3 ""))]
5998 "TARGET_POWERPC64 && reload_completed"
5999 [(set (match_dup 3)
6000 (minus:DI (match_dup 1) (match_dup 2)))
6001 (set (match_dup 0)
6002 (compare:CC (match_dup 3)
6003 (const_int 0)))]
6004 "")
6005
6006 (define_insn ""
6007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6008 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6009 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6010 (const_int 0)))
6011 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6012 (minus:DI (match_dup 1) (match_dup 2)))]
6013 "TARGET_64BIT"
6014 "@
6015 subf. %0,%2,%1
6016 #"
6017 [(set_attr "type" "fast_compare")
6018 (set_attr "length" "4,8")])
6019
6020 (define_split
6021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6022 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6023 (match_operand:DI 2 "gpc_reg_operand" ""))
6024 (const_int 0)))
6025 (set (match_operand:DI 0 "gpc_reg_operand" "")
6026 (minus:DI (match_dup 1) (match_dup 2)))]
6027 "TARGET_POWERPC64 && reload_completed"
6028 [(set (match_dup 0)
6029 (minus:DI (match_dup 1) (match_dup 2)))
6030 (set (match_dup 3)
6031 (compare:CC (match_dup 0)
6032 (const_int 0)))]
6033 "")
6034
6035 (define_expand "subdi3"
6036 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6037 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6038 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6039 ""
6040 "
6041 {
6042 if (GET_CODE (operands[2]) == CONST_INT)
6043 {
6044 emit_insn (gen_adddi3 (operands[0], operands[1],
6045 negate_rtx (DImode, operands[2])));
6046 DONE;
6047 }
6048 }")
6049
6050 (define_insn_and_split "absdi2"
6051 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6052 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6053 (clobber (match_scratch:DI 2 "=&r,&r"))]
6054 "TARGET_POWERPC64"
6055 "#"
6056 "&& reload_completed"
6057 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6058 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6059 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6060 "")
6061
6062 (define_insn_and_split "*nabsdi2"
6063 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6064 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6065 (clobber (match_scratch:DI 2 "=&r,&r"))]
6066 "TARGET_POWERPC64"
6067 "#"
6068 "&& reload_completed"
6069 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6070 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6071 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6072 "")
6073
6074 (define_expand "negdi2"
6075 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6076 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6077 ""
6078 "")
6079
6080 (define_insn ""
6081 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6082 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6083 "TARGET_POWERPC64"
6084 "neg %0,%1")
6085
6086 (define_insn ""
6087 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6088 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6089 (const_int 0)))
6090 (clobber (match_scratch:DI 2 "=r,r"))]
6091 "TARGET_64BIT"
6092 "@
6093 neg. %2,%1
6094 #"
6095 [(set_attr "type" "fast_compare")
6096 (set_attr "length" "4,8")])
6097
6098 (define_split
6099 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6100 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6101 (const_int 0)))
6102 (clobber (match_scratch:DI 2 ""))]
6103 "TARGET_POWERPC64 && reload_completed"
6104 [(set (match_dup 2)
6105 (neg:DI (match_dup 1)))
6106 (set (match_dup 0)
6107 (compare:CC (match_dup 2)
6108 (const_int 0)))]
6109 "")
6110
6111 (define_insn ""
6112 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6113 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6114 (const_int 0)))
6115 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6116 (neg:DI (match_dup 1)))]
6117 "TARGET_64BIT"
6118 "@
6119 neg. %0,%1
6120 #"
6121 [(set_attr "type" "fast_compare")
6122 (set_attr "length" "4,8")])
6123
6124 (define_split
6125 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6126 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6127 (const_int 0)))
6128 (set (match_operand:DI 0 "gpc_reg_operand" "")
6129 (neg:DI (match_dup 1)))]
6130 "TARGET_POWERPC64 && reload_completed"
6131 [(set (match_dup 0)
6132 (neg:DI (match_dup 1)))
6133 (set (match_dup 2)
6134 (compare:CC (match_dup 0)
6135 (const_int 0)))]
6136 "")
6137
6138 (define_insn "clzdi2"
6139 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6140 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6141 "TARGET_POWERPC64"
6142 "cntlzd %0,%1")
6143
6144 (define_expand "ctzdi2"
6145 [(set (match_dup 2)
6146 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6147 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6148 (match_dup 2)))
6149 (clobber (scratch:CC))])
6150 (set (match_dup 4) (clz:DI (match_dup 3)))
6151 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6152 (minus:DI (const_int 63) (match_dup 4)))]
6153 "TARGET_POWERPC64"
6154 {
6155 operands[2] = gen_reg_rtx (DImode);
6156 operands[3] = gen_reg_rtx (DImode);
6157 operands[4] = gen_reg_rtx (DImode);
6158 })
6159
6160 (define_expand "ffsdi2"
6161 [(set (match_dup 2)
6162 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6163 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6164 (match_dup 2)))
6165 (clobber (scratch:CC))])
6166 (set (match_dup 4) (clz:DI (match_dup 3)))
6167 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6168 (minus:DI (const_int 64) (match_dup 4)))]
6169 "TARGET_POWERPC64"
6170 {
6171 operands[2] = gen_reg_rtx (DImode);
6172 operands[3] = gen_reg_rtx (DImode);
6173 operands[4] = gen_reg_rtx (DImode);
6174 })
6175
6176 (define_insn "muldi3"
6177 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6178 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6179 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6180 "TARGET_POWERPC64"
6181 "mulld %0,%1,%2"
6182 [(set_attr "type" "lmul")])
6183
6184 (define_insn "*muldi3_internal1"
6185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6186 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6187 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6188 (const_int 0)))
6189 (clobber (match_scratch:DI 3 "=r,r"))]
6190 "TARGET_POWERPC64"
6191 "@
6192 mulld. %3,%1,%2
6193 #"
6194 [(set_attr "type" "lmul_compare")
6195 (set_attr "length" "4,8")])
6196
6197 (define_split
6198 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6199 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6200 (match_operand:DI 2 "gpc_reg_operand" ""))
6201 (const_int 0)))
6202 (clobber (match_scratch:DI 3 ""))]
6203 "TARGET_POWERPC64 && reload_completed"
6204 [(set (match_dup 3)
6205 (mult:DI (match_dup 1) (match_dup 2)))
6206 (set (match_dup 0)
6207 (compare:CC (match_dup 3)
6208 (const_int 0)))]
6209 "")
6210
6211 (define_insn "*muldi3_internal2"
6212 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6213 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6214 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6215 (const_int 0)))
6216 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6217 (mult:DI (match_dup 1) (match_dup 2)))]
6218 "TARGET_POWERPC64"
6219 "@
6220 mulld. %0,%1,%2
6221 #"
6222 [(set_attr "type" "lmul_compare")
6223 (set_attr "length" "4,8")])
6224
6225 (define_split
6226 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6227 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6228 (match_operand:DI 2 "gpc_reg_operand" ""))
6229 (const_int 0)))
6230 (set (match_operand:DI 0 "gpc_reg_operand" "")
6231 (mult:DI (match_dup 1) (match_dup 2)))]
6232 "TARGET_POWERPC64 && reload_completed"
6233 [(set (match_dup 0)
6234 (mult:DI (match_dup 1) (match_dup 2)))
6235 (set (match_dup 3)
6236 (compare:CC (match_dup 0)
6237 (const_int 0)))]
6238 "")
6239
6240 (define_insn "smuldi3_highpart"
6241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6242 (truncate:DI
6243 (lshiftrt:TI (mult:TI (sign_extend:TI
6244 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6245 (sign_extend:TI
6246 (match_operand:DI 2 "gpc_reg_operand" "r")))
6247 (const_int 64))))]
6248 "TARGET_POWERPC64"
6249 "mulhd %0,%1,%2"
6250 [(set_attr "type" "lmul")])
6251
6252 (define_insn "umuldi3_highpart"
6253 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6254 (truncate:DI
6255 (lshiftrt:TI (mult:TI (zero_extend:TI
6256 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6257 (zero_extend:TI
6258 (match_operand:DI 2 "gpc_reg_operand" "r")))
6259 (const_int 64))))]
6260 "TARGET_POWERPC64"
6261 "mulhdu %0,%1,%2"
6262 [(set_attr "type" "lmul")])
6263
6264 (define_expand "divdi3"
6265 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6266 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6267 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6268 "TARGET_POWERPC64"
6269 "
6270 {
6271 if (GET_CODE (operands[2]) == CONST_INT
6272 && INTVAL (operands[2]) > 0
6273 && exact_log2 (INTVAL (operands[2])) >= 0)
6274 ;
6275 else
6276 operands[2] = force_reg (DImode, operands[2]);
6277 }")
6278
6279 (define_expand "moddi3"
6280 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6281 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6282 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6283 "TARGET_POWERPC64"
6284 "
6285 {
6286 int i;
6287 rtx temp1;
6288 rtx temp2;
6289
6290 if (GET_CODE (operands[2]) != CONST_INT
6291 || INTVAL (operands[2]) <= 0
6292 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6293 FAIL;
6294
6295 temp1 = gen_reg_rtx (DImode);
6296 temp2 = gen_reg_rtx (DImode);
6297
6298 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6299 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6300 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6301 DONE;
6302 }")
6303
6304 (define_insn ""
6305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6306 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6307 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6308 "TARGET_POWERPC64"
6309 "sradi %0,%1,%p2\;addze %0,%0"
6310 [(set_attr "type" "two")
6311 (set_attr "length" "8")])
6312
6313 (define_insn ""
6314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6315 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6316 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6317 (const_int 0)))
6318 (clobber (match_scratch:DI 3 "=r,r"))]
6319 "TARGET_64BIT"
6320 "@
6321 sradi %3,%1,%p2\;addze. %3,%3
6322 #"
6323 [(set_attr "type" "compare")
6324 (set_attr "length" "8,12")])
6325
6326 (define_split
6327 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6328 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6329 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6330 (const_int 0)))
6331 (clobber (match_scratch:DI 3 ""))]
6332 "TARGET_POWERPC64 && reload_completed"
6333 [(set (match_dup 3)
6334 (div:DI (match_dup 1) (match_dup 2)))
6335 (set (match_dup 0)
6336 (compare:CC (match_dup 3)
6337 (const_int 0)))]
6338 "")
6339
6340 (define_insn ""
6341 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6342 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6343 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6344 (const_int 0)))
6345 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6346 (div:DI (match_dup 1) (match_dup 2)))]
6347 "TARGET_64BIT"
6348 "@
6349 sradi %0,%1,%p2\;addze. %0,%0
6350 #"
6351 [(set_attr "type" "compare")
6352 (set_attr "length" "8,12")])
6353
6354 (define_split
6355 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6356 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6357 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6358 (const_int 0)))
6359 (set (match_operand:DI 0 "gpc_reg_operand" "")
6360 (div:DI (match_dup 1) (match_dup 2)))]
6361 "TARGET_POWERPC64 && reload_completed"
6362 [(set (match_dup 0)
6363 (div:DI (match_dup 1) (match_dup 2)))
6364 (set (match_dup 3)
6365 (compare:CC (match_dup 0)
6366 (const_int 0)))]
6367 "")
6368
6369 (define_insn ""
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6371 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6372 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6373 "TARGET_POWERPC64"
6374 "divd %0,%1,%2"
6375 [(set_attr "type" "ldiv")])
6376
6377 (define_insn "udivdi3"
6378 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6379 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6380 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6381 "TARGET_POWERPC64"
6382 "divdu %0,%1,%2"
6383 [(set_attr "type" "ldiv")])
6384
6385 (define_insn "rotldi3"
6386 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6387 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6388 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6389 "TARGET_POWERPC64"
6390 "rld%I2cl %0,%1,%H2,0")
6391
6392 (define_insn "*rotldi3_internal2"
6393 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6394 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6395 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6396 (const_int 0)))
6397 (clobber (match_scratch:DI 3 "=r,r"))]
6398 "TARGET_64BIT"
6399 "@
6400 rld%I2cl. %3,%1,%H2,0
6401 #"
6402 [(set_attr "type" "delayed_compare")
6403 (set_attr "length" "4,8")])
6404
6405 (define_split
6406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6407 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6408 (match_operand:DI 2 "reg_or_cint_operand" ""))
6409 (const_int 0)))
6410 (clobber (match_scratch:DI 3 ""))]
6411 "TARGET_POWERPC64 && reload_completed"
6412 [(set (match_dup 3)
6413 (rotate:DI (match_dup 1) (match_dup 2)))
6414 (set (match_dup 0)
6415 (compare:CC (match_dup 3)
6416 (const_int 0)))]
6417 "")
6418
6419 (define_insn "*rotldi3_internal3"
6420 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6421 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6422 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6423 (const_int 0)))
6424 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6425 (rotate:DI (match_dup 1) (match_dup 2)))]
6426 "TARGET_64BIT"
6427 "@
6428 rld%I2cl. %0,%1,%H2,0
6429 #"
6430 [(set_attr "type" "delayed_compare")
6431 (set_attr "length" "4,8")])
6432
6433 (define_split
6434 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6435 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6436 (match_operand:DI 2 "reg_or_cint_operand" ""))
6437 (const_int 0)))
6438 (set (match_operand:DI 0 "gpc_reg_operand" "")
6439 (rotate:DI (match_dup 1) (match_dup 2)))]
6440 "TARGET_POWERPC64 && reload_completed"
6441 [(set (match_dup 0)
6442 (rotate:DI (match_dup 1) (match_dup 2)))
6443 (set (match_dup 3)
6444 (compare:CC (match_dup 0)
6445 (const_int 0)))]
6446 "")
6447
6448 (define_insn "*rotldi3_internal4"
6449 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6450 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6451 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6452 (match_operand:DI 3 "mask64_operand" "n")))]
6453 "TARGET_POWERPC64"
6454 "rld%I2c%B3 %0,%1,%H2,%S3")
6455
6456 (define_insn "*rotldi3_internal5"
6457 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6458 (compare:CC (and:DI
6459 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6460 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6461 (match_operand:DI 3 "mask64_operand" "n,n"))
6462 (const_int 0)))
6463 (clobber (match_scratch:DI 4 "=r,r"))]
6464 "TARGET_64BIT"
6465 "@
6466 rld%I2c%B3. %4,%1,%H2,%S3
6467 #"
6468 [(set_attr "type" "delayed_compare")
6469 (set_attr "length" "4,8")])
6470
6471 (define_split
6472 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6473 (compare:CC (and:DI
6474 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6475 (match_operand:DI 2 "reg_or_cint_operand" ""))
6476 (match_operand:DI 3 "mask64_operand" ""))
6477 (const_int 0)))
6478 (clobber (match_scratch:DI 4 ""))]
6479 "TARGET_POWERPC64 && reload_completed"
6480 [(set (match_dup 4)
6481 (and:DI (rotate:DI (match_dup 1)
6482 (match_dup 2))
6483 (match_dup 3)))
6484 (set (match_dup 0)
6485 (compare:CC (match_dup 4)
6486 (const_int 0)))]
6487 "")
6488
6489 (define_insn "*rotldi3_internal6"
6490 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6491 (compare:CC (and:DI
6492 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6493 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6494 (match_operand:DI 3 "mask64_operand" "n,n"))
6495 (const_int 0)))
6496 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6497 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6498 "TARGET_64BIT"
6499 "@
6500 rld%I2c%B3. %0,%1,%H2,%S3
6501 #"
6502 [(set_attr "type" "delayed_compare")
6503 (set_attr "length" "4,8")])
6504
6505 (define_split
6506 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6507 (compare:CC (and:DI
6508 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6509 (match_operand:DI 2 "reg_or_cint_operand" ""))
6510 (match_operand:DI 3 "mask64_operand" ""))
6511 (const_int 0)))
6512 (set (match_operand:DI 0 "gpc_reg_operand" "")
6513 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6514 "TARGET_POWERPC64 && reload_completed"
6515 [(set (match_dup 0)
6516 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6517 (set (match_dup 4)
6518 (compare:CC (match_dup 0)
6519 (const_int 0)))]
6520 "")
6521
6522 (define_insn "*rotldi3_internal7"
6523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6524 (zero_extend:DI
6525 (subreg:QI
6526 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6527 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6528 "TARGET_POWERPC64"
6529 "rld%I2cl %0,%1,%H2,56")
6530
6531 (define_insn "*rotldi3_internal8"
6532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6533 (compare:CC (zero_extend:DI
6534 (subreg:QI
6535 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6536 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6537 (const_int 0)))
6538 (clobber (match_scratch:DI 3 "=r,r"))]
6539 "TARGET_64BIT"
6540 "@
6541 rld%I2cl. %3,%1,%H2,56
6542 #"
6543 [(set_attr "type" "delayed_compare")
6544 (set_attr "length" "4,8")])
6545
6546 (define_split
6547 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6548 (compare:CC (zero_extend:DI
6549 (subreg:QI
6550 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6551 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6552 (const_int 0)))
6553 (clobber (match_scratch:DI 3 ""))]
6554 "TARGET_POWERPC64 && reload_completed"
6555 [(set (match_dup 3)
6556 (zero_extend:DI (subreg:QI
6557 (rotate:DI (match_dup 1)
6558 (match_dup 2)) 0)))
6559 (set (match_dup 0)
6560 (compare:CC (match_dup 3)
6561 (const_int 0)))]
6562 "")
6563
6564 (define_insn "*rotldi3_internal9"
6565 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6566 (compare:CC (zero_extend:DI
6567 (subreg:QI
6568 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6569 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6570 (const_int 0)))
6571 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6572 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6573 "TARGET_64BIT"
6574 "@
6575 rld%I2cl. %0,%1,%H2,56
6576 #"
6577 [(set_attr "type" "delayed_compare")
6578 (set_attr "length" "4,8")])
6579
6580 (define_split
6581 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6582 (compare:CC (zero_extend:DI
6583 (subreg:QI
6584 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6585 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6586 (const_int 0)))
6587 (set (match_operand:DI 0 "gpc_reg_operand" "")
6588 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6589 "TARGET_POWERPC64 && reload_completed"
6590 [(set (match_dup 0)
6591 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6592 (set (match_dup 3)
6593 (compare:CC (match_dup 0)
6594 (const_int 0)))]
6595 "")
6596
6597 (define_insn "*rotldi3_internal10"
6598 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6599 (zero_extend:DI
6600 (subreg:HI
6601 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6602 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6603 "TARGET_POWERPC64"
6604 "rld%I2cl %0,%1,%H2,48")
6605
6606 (define_insn "*rotldi3_internal11"
6607 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6608 (compare:CC (zero_extend:DI
6609 (subreg:HI
6610 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6611 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6612 (const_int 0)))
6613 (clobber (match_scratch:DI 3 "=r,r"))]
6614 "TARGET_64BIT"
6615 "@
6616 rld%I2cl. %3,%1,%H2,48
6617 #"
6618 [(set_attr "type" "delayed_compare")
6619 (set_attr "length" "4,8")])
6620
6621 (define_split
6622 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6623 (compare:CC (zero_extend:DI
6624 (subreg:HI
6625 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6626 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6627 (const_int 0)))
6628 (clobber (match_scratch:DI 3 ""))]
6629 "TARGET_POWERPC64 && reload_completed"
6630 [(set (match_dup 3)
6631 (zero_extend:DI (subreg:HI
6632 (rotate:DI (match_dup 1)
6633 (match_dup 2)) 0)))
6634 (set (match_dup 0)
6635 (compare:CC (match_dup 3)
6636 (const_int 0)))]
6637 "")
6638
6639 (define_insn "*rotldi3_internal12"
6640 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6641 (compare:CC (zero_extend:DI
6642 (subreg:HI
6643 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6644 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6645 (const_int 0)))
6646 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6647 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6648 "TARGET_64BIT"
6649 "@
6650 rld%I2cl. %0,%1,%H2,48
6651 #"
6652 [(set_attr "type" "delayed_compare")
6653 (set_attr "length" "4,8")])
6654
6655 (define_split
6656 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6657 (compare:CC (zero_extend:DI
6658 (subreg:HI
6659 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6660 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6661 (const_int 0)))
6662 (set (match_operand:DI 0 "gpc_reg_operand" "")
6663 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6664 "TARGET_POWERPC64 && reload_completed"
6665 [(set (match_dup 0)
6666 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6667 (set (match_dup 3)
6668 (compare:CC (match_dup 0)
6669 (const_int 0)))]
6670 "")
6671
6672 (define_insn "*rotldi3_internal13"
6673 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6674 (zero_extend:DI
6675 (subreg:SI
6676 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6677 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6678 "TARGET_POWERPC64"
6679 "rld%I2cl %0,%1,%H2,32")
6680
6681 (define_insn "*rotldi3_internal14"
6682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6683 (compare:CC (zero_extend:DI
6684 (subreg:SI
6685 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6686 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6687 (const_int 0)))
6688 (clobber (match_scratch:DI 3 "=r,r"))]
6689 "TARGET_64BIT"
6690 "@
6691 rld%I2cl. %3,%1,%H2,32
6692 #"
6693 [(set_attr "type" "delayed_compare")
6694 (set_attr "length" "4,8")])
6695
6696 (define_split
6697 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6698 (compare:CC (zero_extend:DI
6699 (subreg:SI
6700 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6701 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6702 (const_int 0)))
6703 (clobber (match_scratch:DI 3 ""))]
6704 "TARGET_POWERPC64 && reload_completed"
6705 [(set (match_dup 3)
6706 (zero_extend:DI (subreg:SI
6707 (rotate:DI (match_dup 1)
6708 (match_dup 2)) 0)))
6709 (set (match_dup 0)
6710 (compare:CC (match_dup 3)
6711 (const_int 0)))]
6712 "")
6713
6714 (define_insn "*rotldi3_internal15"
6715 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6716 (compare:CC (zero_extend:DI
6717 (subreg:SI
6718 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6719 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6720 (const_int 0)))
6721 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6722 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6723 "TARGET_64BIT"
6724 "@
6725 rld%I2cl. %0,%1,%H2,32
6726 #"
6727 [(set_attr "type" "delayed_compare")
6728 (set_attr "length" "4,8")])
6729
6730 (define_split
6731 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6732 (compare:CC (zero_extend:DI
6733 (subreg:SI
6734 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6735 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6736 (const_int 0)))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "")
6738 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6739 "TARGET_POWERPC64 && reload_completed"
6740 [(set (match_dup 0)
6741 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6742 (set (match_dup 3)
6743 (compare:CC (match_dup 0)
6744 (const_int 0)))]
6745 "")
6746
6747 (define_expand "ashldi3"
6748 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6749 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6750 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6751 "TARGET_POWERPC64 || TARGET_POWER"
6752 "
6753 {
6754 if (TARGET_POWERPC64)
6755 ;
6756 else if (TARGET_POWER)
6757 {
6758 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6759 DONE;
6760 }
6761 else
6762 FAIL;
6763 }")
6764
6765 (define_insn "*ashldi3_internal1"
6766 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6767 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6768 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6769 "TARGET_POWERPC64"
6770 "sld%I2 %0,%1,%H2")
6771
6772 (define_insn "*ashldi3_internal2"
6773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6774 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6775 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6776 (const_int 0)))
6777 (clobber (match_scratch:DI 3 "=r,r"))]
6778 "TARGET_64BIT"
6779 "@
6780 sld%I2. %3,%1,%H2
6781 #"
6782 [(set_attr "type" "delayed_compare")
6783 (set_attr "length" "4,8")])
6784
6785 (define_split
6786 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6787 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6788 (match_operand:SI 2 "reg_or_cint_operand" ""))
6789 (const_int 0)))
6790 (clobber (match_scratch:DI 3 ""))]
6791 "TARGET_POWERPC64 && reload_completed"
6792 [(set (match_dup 3)
6793 (ashift:DI (match_dup 1) (match_dup 2)))
6794 (set (match_dup 0)
6795 (compare:CC (match_dup 3)
6796 (const_int 0)))]
6797 "")
6798
6799 (define_insn "*ashldi3_internal3"
6800 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6801 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6802 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6803 (const_int 0)))
6804 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6805 (ashift:DI (match_dup 1) (match_dup 2)))]
6806 "TARGET_64BIT"
6807 "@
6808 sld%I2. %0,%1,%H2
6809 #"
6810 [(set_attr "type" "delayed_compare")
6811 (set_attr "length" "4,8")])
6812
6813 (define_split
6814 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6815 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6816 (match_operand:SI 2 "reg_or_cint_operand" ""))
6817 (const_int 0)))
6818 (set (match_operand:DI 0 "gpc_reg_operand" "")
6819 (ashift:DI (match_dup 1) (match_dup 2)))]
6820 "TARGET_POWERPC64 && reload_completed"
6821 [(set (match_dup 0)
6822 (ashift:DI (match_dup 1) (match_dup 2)))
6823 (set (match_dup 3)
6824 (compare:CC (match_dup 0)
6825 (const_int 0)))]
6826 "")
6827
6828 (define_insn "*ashldi3_internal4"
6829 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6830 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6831 (match_operand:SI 2 "const_int_operand" "i"))
6832 (match_operand:DI 3 "const_int_operand" "n")))]
6833 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6834 "rldic %0,%1,%H2,%W3")
6835
6836 (define_insn "ashldi3_internal5"
6837 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6838 (compare:CC
6839 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6840 (match_operand:SI 2 "const_int_operand" "i,i"))
6841 (match_operand:DI 3 "const_int_operand" "n,n"))
6842 (const_int 0)))
6843 (clobber (match_scratch:DI 4 "=r,r"))]
6844 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6845 "@
6846 rldic. %4,%1,%H2,%W3
6847 #"
6848 [(set_attr "type" "delayed_compare")
6849 (set_attr "length" "4,8")])
6850
6851 (define_split
6852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6853 (compare:CC
6854 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6855 (match_operand:SI 2 "const_int_operand" ""))
6856 (match_operand:DI 3 "const_int_operand" ""))
6857 (const_int 0)))
6858 (clobber (match_scratch:DI 4 ""))]
6859 "TARGET_POWERPC64 && reload_completed
6860 && includes_rldic_lshift_p (operands[2], operands[3])"
6861 [(set (match_dup 4)
6862 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6863 (match_dup 3)))
6864 (set (match_dup 0)
6865 (compare:CC (match_dup 4)
6866 (const_int 0)))]
6867 "")
6868
6869 (define_insn "*ashldi3_internal6"
6870 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6871 (compare:CC
6872 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6873 (match_operand:SI 2 "const_int_operand" "i,i"))
6874 (match_operand:DI 3 "const_int_operand" "n,n"))
6875 (const_int 0)))
6876 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6877 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6878 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6879 "@
6880 rldic. %0,%1,%H2,%W3
6881 #"
6882 [(set_attr "type" "delayed_compare")
6883 (set_attr "length" "4,8")])
6884
6885 (define_split
6886 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6887 (compare:CC
6888 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6889 (match_operand:SI 2 "const_int_operand" ""))
6890 (match_operand:DI 3 "const_int_operand" ""))
6891 (const_int 0)))
6892 (set (match_operand:DI 0 "gpc_reg_operand" "")
6893 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6894 "TARGET_POWERPC64 && reload_completed
6895 && includes_rldic_lshift_p (operands[2], operands[3])"
6896 [(set (match_dup 0)
6897 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6898 (match_dup 3)))
6899 (set (match_dup 4)
6900 (compare:CC (match_dup 0)
6901 (const_int 0)))]
6902 "")
6903
6904 (define_insn "*ashldi3_internal7"
6905 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6906 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6907 (match_operand:SI 2 "const_int_operand" "i"))
6908 (match_operand:DI 3 "mask64_operand" "n")))]
6909 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6910 "rldicr %0,%1,%H2,%S3")
6911
6912 (define_insn "ashldi3_internal8"
6913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6914 (compare:CC
6915 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6916 (match_operand:SI 2 "const_int_operand" "i,i"))
6917 (match_operand:DI 3 "mask64_operand" "n,n"))
6918 (const_int 0)))
6919 (clobber (match_scratch:DI 4 "=r,r"))]
6920 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6921 "@
6922 rldicr. %4,%1,%H2,%S3
6923 #"
6924 [(set_attr "type" "delayed_compare")
6925 (set_attr "length" "4,8")])
6926
6927 (define_split
6928 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6929 (compare:CC
6930 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6931 (match_operand:SI 2 "const_int_operand" ""))
6932 (match_operand:DI 3 "mask64_operand" ""))
6933 (const_int 0)))
6934 (clobber (match_scratch:DI 4 ""))]
6935 "TARGET_POWERPC64 && reload_completed
6936 && includes_rldicr_lshift_p (operands[2], operands[3])"
6937 [(set (match_dup 4)
6938 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6939 (match_dup 3)))
6940 (set (match_dup 0)
6941 (compare:CC (match_dup 4)
6942 (const_int 0)))]
6943 "")
6944
6945 (define_insn "*ashldi3_internal9"
6946 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6947 (compare:CC
6948 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6949 (match_operand:SI 2 "const_int_operand" "i,i"))
6950 (match_operand:DI 3 "mask64_operand" "n,n"))
6951 (const_int 0)))
6952 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6953 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6954 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6955 "@
6956 rldicr. %0,%1,%H2,%S3
6957 #"
6958 [(set_attr "type" "delayed_compare")
6959 (set_attr "length" "4,8")])
6960
6961 (define_split
6962 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6963 (compare:CC
6964 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6965 (match_operand:SI 2 "const_int_operand" ""))
6966 (match_operand:DI 3 "mask64_operand" ""))
6967 (const_int 0)))
6968 (set (match_operand:DI 0 "gpc_reg_operand" "")
6969 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6970 "TARGET_POWERPC64 && reload_completed
6971 && includes_rldicr_lshift_p (operands[2], operands[3])"
6972 [(set (match_dup 0)
6973 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6974 (match_dup 3)))
6975 (set (match_dup 4)
6976 (compare:CC (match_dup 0)
6977 (const_int 0)))]
6978 "")
6979
6980 (define_expand "lshrdi3"
6981 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6982 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6983 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6984 "TARGET_POWERPC64 || TARGET_POWER"
6985 "
6986 {
6987 if (TARGET_POWERPC64)
6988 ;
6989 else if (TARGET_POWER)
6990 {
6991 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6992 DONE;
6993 }
6994 else
6995 FAIL;
6996 }")
6997
6998 (define_insn "*lshrdi3_internal1"
6999 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7000 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7001 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7002 "TARGET_POWERPC64"
7003 "srd%I2 %0,%1,%H2")
7004
7005 (define_insn "*lshrdi3_internal2"
7006 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7007 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7008 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7009 (const_int 0)))
7010 (clobber (match_scratch:DI 3 "=r,r"))]
7011 "TARGET_64BIT "
7012 "@
7013 srd%I2. %3,%1,%H2
7014 #"
7015 [(set_attr "type" "delayed_compare")
7016 (set_attr "length" "4,8")])
7017
7018 (define_split
7019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7020 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7021 (match_operand:SI 2 "reg_or_cint_operand" ""))
7022 (const_int 0)))
7023 (clobber (match_scratch:DI 3 ""))]
7024 "TARGET_POWERPC64 && reload_completed"
7025 [(set (match_dup 3)
7026 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7027 (set (match_dup 0)
7028 (compare:CC (match_dup 3)
7029 (const_int 0)))]
7030 "")
7031
7032 (define_insn "*lshrdi3_internal3"
7033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7034 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7035 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7036 (const_int 0)))
7037 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7038 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7039 "TARGET_64BIT"
7040 "@
7041 srd%I2. %0,%1,%H2
7042 #"
7043 [(set_attr "type" "delayed_compare")
7044 (set_attr "length" "4,8")])
7045
7046 (define_split
7047 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7048 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7049 (match_operand:SI 2 "reg_or_cint_operand" ""))
7050 (const_int 0)))
7051 (set (match_operand:DI 0 "gpc_reg_operand" "")
7052 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7053 "TARGET_POWERPC64 && reload_completed"
7054 [(set (match_dup 0)
7055 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7056 (set (match_dup 3)
7057 (compare:CC (match_dup 0)
7058 (const_int 0)))]
7059 "")
7060
7061 (define_expand "ashrdi3"
7062 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7063 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7064 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7065 "WORDS_BIG_ENDIAN"
7066 "
7067 {
7068 if (TARGET_POWERPC64)
7069 ;
7070 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7071 {
7072 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7073 DONE;
7074 }
7075 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7076 && WORDS_BIG_ENDIAN)
7077 {
7078 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7079 DONE;
7080 }
7081 else
7082 FAIL;
7083 }")
7084
7085 (define_insn "*ashrdi3_internal1"
7086 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7087 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7088 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7089 "TARGET_POWERPC64"
7090 "srad%I2 %0,%1,%H2")
7091
7092 (define_insn "*ashrdi3_internal2"
7093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7094 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7095 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7096 (const_int 0)))
7097 (clobber (match_scratch:DI 3 "=r,r"))]
7098 "TARGET_64BIT"
7099 "@
7100 srad%I2. %3,%1,%H2
7101 #"
7102 [(set_attr "type" "delayed_compare")
7103 (set_attr "length" "4,8")])
7104
7105 (define_split
7106 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7107 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7108 (match_operand:SI 2 "reg_or_cint_operand" ""))
7109 (const_int 0)))
7110 (clobber (match_scratch:DI 3 ""))]
7111 "TARGET_POWERPC64 && reload_completed"
7112 [(set (match_dup 3)
7113 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7114 (set (match_dup 0)
7115 (compare:CC (match_dup 3)
7116 (const_int 0)))]
7117 "")
7118
7119 (define_insn "*ashrdi3_internal3"
7120 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7121 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7122 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7123 (const_int 0)))
7124 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7125 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7126 "TARGET_64BIT"
7127 "@
7128 srad%I2. %0,%1,%H2
7129 #"
7130 [(set_attr "type" "delayed_compare")
7131 (set_attr "length" "4,8")])
7132
7133 (define_split
7134 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7135 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7136 (match_operand:SI 2 "reg_or_cint_operand" ""))
7137 (const_int 0)))
7138 (set (match_operand:DI 0 "gpc_reg_operand" "")
7139 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7140 "TARGET_POWERPC64 && reload_completed"
7141 [(set (match_dup 0)
7142 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7143 (set (match_dup 3)
7144 (compare:CC (match_dup 0)
7145 (const_int 0)))]
7146 "")
7147
7148 (define_insn "anddi3"
7149 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7150 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7151 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7152 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7153 "TARGET_POWERPC64"
7154 "@
7155 and %0,%1,%2
7156 rldic%B2 %0,%1,0,%S2
7157 rlwinm %0,%1,0,%m2,%M2
7158 andi. %0,%1,%b2
7159 andis. %0,%1,%u2
7160 #"
7161 [(set_attr "type" "*,*,*,compare,compare,*")
7162 (set_attr "length" "4,4,4,4,4,8")])
7163
7164 (define_split
7165 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7166 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7167 (match_operand:DI 2 "mask64_2_operand" "")))
7168 (clobber (match_scratch:CC 3 ""))]
7169 "TARGET_POWERPC64
7170 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7171 && !mask64_operand (operands[2], DImode)"
7172 [(set (match_dup 0)
7173 (and:DI (rotate:DI (match_dup 1)
7174 (match_dup 4))
7175 (match_dup 5)))
7176 (set (match_dup 0)
7177 (and:DI (rotate:DI (match_dup 0)
7178 (match_dup 6))
7179 (match_dup 7)))]
7180 {
7181 build_mask64_2_operands (operands[2], &operands[4]);
7182 })
7183
7184 (define_insn "*anddi3_internal2"
7185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7186 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7187 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7188 (const_int 0)))
7189 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7190 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7191 "TARGET_64BIT"
7192 "@
7193 and. %3,%1,%2
7194 rldic%B2. %3,%1,0,%S2
7195 andi. %3,%1,%b2
7196 andis. %3,%1,%u2
7197 #
7198 #
7199 #
7200 #
7201 #
7202 #"
7203 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7204 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7205
7206 (define_split
7207 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7208 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7209 (match_operand:DI 2 "and64_operand" ""))
7210 (const_int 0)))
7211 (clobber (match_scratch:DI 3 ""))
7212 (clobber (match_scratch:CC 4 ""))]
7213 "TARGET_POWERPC64 && reload_completed"
7214 [(parallel [(set (match_dup 3)
7215 (and:DI (match_dup 1)
7216 (match_dup 2)))
7217 (clobber (match_dup 4))])
7218 (set (match_dup 0)
7219 (compare:CC (match_dup 3)
7220 (const_int 0)))]
7221 "")
7222
7223 (define_split
7224 [(set (match_operand:CC 0 "cc_reg_operand" "")
7225 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7226 (match_operand:DI 2 "mask64_2_operand" ""))
7227 (const_int 0)))
7228 (clobber (match_scratch:DI 3 ""))
7229 (clobber (match_scratch:CC 4 ""))]
7230 "TARGET_POWERPC64 && reload_completed
7231 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7232 && !mask64_operand (operands[2], DImode)"
7233 [(set (match_dup 3)
7234 (and:DI (rotate:DI (match_dup 1)
7235 (match_dup 5))
7236 (match_dup 6)))
7237 (parallel [(set (match_dup 0)
7238 (compare:CC (and:DI (rotate:DI (match_dup 3)
7239 (match_dup 7))
7240 (match_dup 8))
7241 (const_int 0)))
7242 (clobber (match_dup 3))])]
7243 "
7244 {
7245 build_mask64_2_operands (operands[2], &operands[5]);
7246 }")
7247
7248 (define_insn "*anddi3_internal3"
7249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7250 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7251 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7252 (const_int 0)))
7253 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7254 (and:DI (match_dup 1) (match_dup 2)))
7255 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7256 "TARGET_64BIT"
7257 "@
7258 and. %0,%1,%2
7259 rldic%B2. %0,%1,0,%S2
7260 andi. %0,%1,%b2
7261 andis. %0,%1,%u2
7262 #
7263 #
7264 #
7265 #
7266 #
7267 #"
7268 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7269 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7270
7271 (define_split
7272 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7273 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7274 (match_operand:DI 2 "and64_operand" ""))
7275 (const_int 0)))
7276 (set (match_operand:DI 0 "gpc_reg_operand" "")
7277 (and:DI (match_dup 1) (match_dup 2)))
7278 (clobber (match_scratch:CC 4 ""))]
7279 "TARGET_POWERPC64 && reload_completed"
7280 [(parallel [(set (match_dup 0)
7281 (and:DI (match_dup 1) (match_dup 2)))
7282 (clobber (match_dup 4))])
7283 (set (match_dup 3)
7284 (compare:CC (match_dup 0)
7285 (const_int 0)))]
7286 "")
7287
7288 (define_split
7289 [(set (match_operand:CC 3 "cc_reg_operand" "")
7290 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7291 (match_operand:DI 2 "mask64_2_operand" ""))
7292 (const_int 0)))
7293 (set (match_operand:DI 0 "gpc_reg_operand" "")
7294 (and:DI (match_dup 1) (match_dup 2)))
7295 (clobber (match_scratch:CC 4 ""))]
7296 "TARGET_POWERPC64 && reload_completed
7297 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7298 && !mask64_operand (operands[2], DImode)"
7299 [(set (match_dup 0)
7300 (and:DI (rotate:DI (match_dup 1)
7301 (match_dup 5))
7302 (match_dup 6)))
7303 (parallel [(set (match_dup 3)
7304 (compare:CC (and:DI (rotate:DI (match_dup 0)
7305 (match_dup 7))
7306 (match_dup 8))
7307 (const_int 0)))
7308 (set (match_dup 0)
7309 (and:DI (rotate:DI (match_dup 0)
7310 (match_dup 7))
7311 (match_dup 8)))])]
7312 "
7313 {
7314 build_mask64_2_operands (operands[2], &operands[5]);
7315 }")
7316
7317 (define_expand "iordi3"
7318 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7319 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7320 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7321 "TARGET_POWERPC64"
7322 "
7323 {
7324 if (non_logical_cint_operand (operands[2], DImode))
7325 {
7326 HOST_WIDE_INT value;
7327 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7328 ? operands[0] : gen_reg_rtx (DImode));
7329
7330 if (GET_CODE (operands[2]) == CONST_INT)
7331 {
7332 value = INTVAL (operands[2]);
7333 emit_insn (gen_iordi3 (tmp, operands[1],
7334 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7335 }
7336 else
7337 {
7338 value = CONST_DOUBLE_LOW (operands[2]);
7339 emit_insn (gen_iordi3 (tmp, operands[1],
7340 immed_double_const (value
7341 & (~ (HOST_WIDE_INT) 0xffff),
7342 0, DImode)));
7343 }
7344
7345 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7346 DONE;
7347 }
7348 }")
7349
7350 (define_expand "xordi3"
7351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7352 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7353 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7354 "TARGET_POWERPC64"
7355 "
7356 {
7357 if (non_logical_cint_operand (operands[2], DImode))
7358 {
7359 HOST_WIDE_INT value;
7360 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7361 ? operands[0] : gen_reg_rtx (DImode));
7362
7363 if (GET_CODE (operands[2]) == CONST_INT)
7364 {
7365 value = INTVAL (operands[2]);
7366 emit_insn (gen_xordi3 (tmp, operands[1],
7367 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7368 }
7369 else
7370 {
7371 value = CONST_DOUBLE_LOW (operands[2]);
7372 emit_insn (gen_xordi3 (tmp, operands[1],
7373 immed_double_const (value
7374 & (~ (HOST_WIDE_INT) 0xffff),
7375 0, DImode)));
7376 }
7377
7378 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7379 DONE;
7380 }
7381 }")
7382
7383 (define_insn "*booldi3_internal1"
7384 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7385 (match_operator:DI 3 "boolean_or_operator"
7386 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7387 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7388 "TARGET_POWERPC64"
7389 "@
7390 %q3 %0,%1,%2
7391 %q3i %0,%1,%b2
7392 %q3is %0,%1,%u2")
7393
7394 (define_insn "*booldi3_internal2"
7395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7396 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7397 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7398 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7399 (const_int 0)))
7400 (clobber (match_scratch:DI 3 "=r,r"))]
7401 "TARGET_64BIT"
7402 "@
7403 %q4. %3,%1,%2
7404 #"
7405 [(set_attr "type" "compare")
7406 (set_attr "length" "4,8")])
7407
7408 (define_split
7409 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7410 (compare:CC (match_operator:DI 4 "boolean_operator"
7411 [(match_operand:DI 1 "gpc_reg_operand" "")
7412 (match_operand:DI 2 "gpc_reg_operand" "")])
7413 (const_int 0)))
7414 (clobber (match_scratch:DI 3 ""))]
7415 "TARGET_POWERPC64 && reload_completed"
7416 [(set (match_dup 3) (match_dup 4))
7417 (set (match_dup 0)
7418 (compare:CC (match_dup 3)
7419 (const_int 0)))]
7420 "")
7421
7422 (define_insn "*booldi3_internal3"
7423 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7424 (compare:CC (match_operator:DI 4 "boolean_operator"
7425 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7426 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7427 (const_int 0)))
7428 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7429 (match_dup 4))]
7430 "TARGET_64BIT"
7431 "@
7432 %q4. %0,%1,%2
7433 #"
7434 [(set_attr "type" "compare")
7435 (set_attr "length" "4,8")])
7436
7437 (define_split
7438 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7439 (compare:CC (match_operator:DI 4 "boolean_operator"
7440 [(match_operand:DI 1 "gpc_reg_operand" "")
7441 (match_operand:DI 2 "gpc_reg_operand" "")])
7442 (const_int 0)))
7443 (set (match_operand:DI 0 "gpc_reg_operand" "")
7444 (match_dup 4))]
7445 "TARGET_POWERPC64 && reload_completed"
7446 [(set (match_dup 0) (match_dup 4))
7447 (set (match_dup 3)
7448 (compare:CC (match_dup 0)
7449 (const_int 0)))]
7450 "")
7451
7452 ;; Split a logical operation that we can't do in one insn into two insns,
7453 ;; each of which does one 16-bit part. This is used by combine.
7454
7455 (define_split
7456 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7457 (match_operator:DI 3 "boolean_or_operator"
7458 [(match_operand:DI 1 "gpc_reg_operand" "")
7459 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7460 "TARGET_POWERPC64"
7461 [(set (match_dup 0) (match_dup 4))
7462 (set (match_dup 0) (match_dup 5))]
7463 "
7464 {
7465 rtx i3,i4;
7466
7467 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7468 {
7469 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7470 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7471 0, DImode);
7472 i4 = GEN_INT (value & 0xffff);
7473 }
7474 else
7475 {
7476 i3 = GEN_INT (INTVAL (operands[2])
7477 & (~ (HOST_WIDE_INT) 0xffff));
7478 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7479 }
7480 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7481 operands[1], i3);
7482 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7483 operands[0], i4);
7484 }")
7485
7486 (define_insn "*boolcdi3_internal1"
7487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7488 (match_operator:DI 3 "boolean_operator"
7489 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7490 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7491 "TARGET_POWERPC64"
7492 "%q3 %0,%2,%1")
7493
7494 (define_insn "*boolcdi3_internal2"
7495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7496 (compare:CC (match_operator:DI 4 "boolean_operator"
7497 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7498 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7499 (const_int 0)))
7500 (clobber (match_scratch:DI 3 "=r,r"))]
7501 "TARGET_64BIT"
7502 "@
7503 %q4. %3,%2,%1
7504 #"
7505 [(set_attr "type" "compare")
7506 (set_attr "length" "4,8")])
7507
7508 (define_split
7509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7510 (compare:CC (match_operator:DI 4 "boolean_operator"
7511 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7512 (match_operand:DI 2 "gpc_reg_operand" "")])
7513 (const_int 0)))
7514 (clobber (match_scratch:DI 3 ""))]
7515 "TARGET_POWERPC64 && reload_completed"
7516 [(set (match_dup 3) (match_dup 4))
7517 (set (match_dup 0)
7518 (compare:CC (match_dup 3)
7519 (const_int 0)))]
7520 "")
7521
7522 (define_insn "*boolcdi3_internal3"
7523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7524 (compare:CC (match_operator:DI 4 "boolean_operator"
7525 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7526 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7527 (const_int 0)))
7528 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7529 (match_dup 4))]
7530 "TARGET_64BIT"
7531 "@
7532 %q4. %0,%2,%1
7533 #"
7534 [(set_attr "type" "compare")
7535 (set_attr "length" "4,8")])
7536
7537 (define_split
7538 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7539 (compare:CC (match_operator:DI 4 "boolean_operator"
7540 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7541 (match_operand:DI 2 "gpc_reg_operand" "")])
7542 (const_int 0)))
7543 (set (match_operand:DI 0 "gpc_reg_operand" "")
7544 (match_dup 4))]
7545 "TARGET_POWERPC64 && reload_completed"
7546 [(set (match_dup 0) (match_dup 4))
7547 (set (match_dup 3)
7548 (compare:CC (match_dup 0)
7549 (const_int 0)))]
7550 "")
7551
7552 (define_insn "*boolccdi3_internal1"
7553 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7554 (match_operator:DI 3 "boolean_operator"
7555 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7556 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7557 "TARGET_POWERPC64"
7558 "%q3 %0,%1,%2")
7559
7560 (define_insn "*boolccdi3_internal2"
7561 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7562 (compare:CC (match_operator:DI 4 "boolean_operator"
7563 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7564 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7565 (const_int 0)))
7566 (clobber (match_scratch:DI 3 "=r,r"))]
7567 "TARGET_64BIT"
7568 "@
7569 %q4. %3,%1,%2
7570 #"
7571 [(set_attr "type" "compare")
7572 (set_attr "length" "4,8")])
7573
7574 (define_split
7575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7576 (compare:CC (match_operator:DI 4 "boolean_operator"
7577 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7578 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7579 (const_int 0)))
7580 (clobber (match_scratch:DI 3 ""))]
7581 "TARGET_POWERPC64 && reload_completed"
7582 [(set (match_dup 3) (match_dup 4))
7583 (set (match_dup 0)
7584 (compare:CC (match_dup 3)
7585 (const_int 0)))]
7586 "")
7587
7588 (define_insn "*boolccdi3_internal3"
7589 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7590 (compare:CC (match_operator:DI 4 "boolean_operator"
7591 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7592 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7593 (const_int 0)))
7594 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7595 (match_dup 4))]
7596 "TARGET_64BIT"
7597 "@
7598 %q4. %0,%1,%2
7599 #"
7600 [(set_attr "type" "compare")
7601 (set_attr "length" "4,8")])
7602
7603 (define_split
7604 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7605 (compare:CC (match_operator:DI 4 "boolean_operator"
7606 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7607 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7608 (const_int 0)))
7609 (set (match_operand:DI 0 "gpc_reg_operand" "")
7610 (match_dup 4))]
7611 "TARGET_POWERPC64 && reload_completed"
7612 [(set (match_dup 0) (match_dup 4))
7613 (set (match_dup 3)
7614 (compare:CC (match_dup 0)
7615 (const_int 0)))]
7616 "")
7617 \f
7618 ;; Now define ways of moving data around.
7619
7620 ;; Elf specific ways of loading addresses for non-PIC code.
7621 ;; The output of this could be r0, but we make a very strong
7622 ;; preference for a base register because it will usually
7623 ;; be needed there.
7624 (define_insn "elf_high"
7625 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7626 (high:SI (match_operand 1 "" "")))]
7627 "TARGET_ELF && ! TARGET_64BIT"
7628 "{liu|lis} %0,%1@ha")
7629
7630 (define_insn "elf_low"
7631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7632 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7633 (match_operand 2 "" "")))]
7634 "TARGET_ELF && ! TARGET_64BIT"
7635 "@
7636 {cal|la} %0,%2@l(%1)
7637 {ai|addic} %0,%1,%K2")
7638
7639
7640 ;; Set up a register with a value from the GOT table
7641
7642 (define_expand "movsi_got"
7643 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7644 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7645 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7646 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7647 "
7648 {
7649 if (GET_CODE (operands[1]) == CONST)
7650 {
7651 rtx offset = const0_rtx;
7652 HOST_WIDE_INT value;
7653
7654 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7655 value = INTVAL (offset);
7656 if (value != 0)
7657 {
7658 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7659 emit_insn (gen_movsi_got (tmp, operands[1]));
7660 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7661 DONE;
7662 }
7663 }
7664
7665 operands[2] = rs6000_got_register (operands[1]);
7666 }")
7667
7668 (define_insn "*movsi_got_internal"
7669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7670 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7671 (match_operand:SI 2 "gpc_reg_operand" "b")]
7672 UNSPEC_MOVSI_GOT))]
7673 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7674 "{l|lwz} %0,%a1@got(%2)"
7675 [(set_attr "type" "load")])
7676
7677 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7678 ;; didn't get allocated to a hard register.
7679 (define_split
7680 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7681 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7682 (match_operand:SI 2 "memory_operand" "")]
7683 UNSPEC_MOVSI_GOT))]
7684 "DEFAULT_ABI == ABI_V4
7685 && flag_pic == 1
7686 && (reload_in_progress || reload_completed)"
7687 [(set (match_dup 0) (match_dup 2))
7688 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7689 UNSPEC_MOVSI_GOT))]
7690 "")
7691
7692 ;; For SI, we special-case integers that can't be loaded in one insn. We
7693 ;; do the load 16-bits at a time. We could do this by loading from memory,
7694 ;; and this is even supposed to be faster, but it is simpler not to get
7695 ;; integers in the TOC.
7696 (define_expand "movsi"
7697 [(set (match_operand:SI 0 "general_operand" "")
7698 (match_operand:SI 1 "any_operand" ""))]
7699 ""
7700 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7701
7702 (define_insn "movsi_low"
7703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7704 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7705 (match_operand 2 "" ""))))]
7706 "TARGET_MACHO && ! TARGET_64BIT"
7707 "{l|lwz} %0,lo16(%2)(%1)"
7708 [(set_attr "type" "load")
7709 (set_attr "length" "4")])
7710
7711 (define_insn "*movsi_internal1"
7712 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7713 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7714 "gpc_reg_operand (operands[0], SImode)
7715 || gpc_reg_operand (operands[1], SImode)"
7716 "@
7717 mr %0,%1
7718 {cal|la} %0,%a1
7719 {l%U1%X1|lwz%U1%X1} %0,%1
7720 {st%U0%X0|stw%U0%X0} %1,%0
7721 {lil|li} %0,%1
7722 {liu|lis} %0,%v1
7723 #
7724 {cal|la} %0,%a1
7725 mf%1 %0
7726 mt%0 %1
7727 mt%0 %1
7728 mt%0 %1
7729 {cror 0,0,0|nop}"
7730 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7731 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7732
7733 ;; Split a load of a large constant into the appropriate two-insn
7734 ;; sequence.
7735
7736 (define_split
7737 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7738 (match_operand:SI 1 "const_int_operand" ""))]
7739 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7740 && (INTVAL (operands[1]) & 0xffff) != 0"
7741 [(set (match_dup 0)
7742 (match_dup 2))
7743 (set (match_dup 0)
7744 (ior:SI (match_dup 0)
7745 (match_dup 3)))]
7746 "
7747 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7748
7749 if (tem == operands[0])
7750 DONE;
7751 else
7752 FAIL;
7753 }")
7754
7755 (define_insn "*movsi_internal2"
7756 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7757 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7758 (const_int 0)))
7759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7760 "TARGET_32BIT"
7761 "@
7762 {cmpi|cmpwi} %2,%0,0
7763 mr. %0,%1
7764 #"
7765 [(set_attr "type" "cmp,compare,cmp")
7766 (set_attr "length" "4,4,8")])
7767
7768 (define_split
7769 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7770 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7771 (const_int 0)))
7772 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7773 "TARGET_32BIT && reload_completed"
7774 [(set (match_dup 0) (match_dup 1))
7775 (set (match_dup 2)
7776 (compare:CC (match_dup 0)
7777 (const_int 0)))]
7778 "")
7779 \f
7780 (define_expand "movhi"
7781 [(set (match_operand:HI 0 "general_operand" "")
7782 (match_operand:HI 1 "any_operand" ""))]
7783 ""
7784 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7785
7786 (define_insn "*movhi_internal"
7787 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7788 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7789 "gpc_reg_operand (operands[0], HImode)
7790 || gpc_reg_operand (operands[1], HImode)"
7791 "@
7792 mr %0,%1
7793 lhz%U1%X1 %0,%1
7794 sth%U0%X0 %1,%0
7795 {lil|li} %0,%w1
7796 mf%1 %0
7797 mt%0 %1
7798 mt%0 %1
7799 {cror 0,0,0|nop}"
7800 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7801
7802 (define_expand "movqi"
7803 [(set (match_operand:QI 0 "general_operand" "")
7804 (match_operand:QI 1 "any_operand" ""))]
7805 ""
7806 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7807
7808 (define_insn "*movqi_internal"
7809 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7810 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7811 "gpc_reg_operand (operands[0], QImode)
7812 || gpc_reg_operand (operands[1], QImode)"
7813 "@
7814 mr %0,%1
7815 lbz%U1%X1 %0,%1
7816 stb%U0%X0 %1,%0
7817 {lil|li} %0,%1
7818 mf%1 %0
7819 mt%0 %1
7820 mt%0 %1
7821 {cror 0,0,0|nop}"
7822 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7823 \f
7824 ;; Here is how to move condition codes around. When we store CC data in
7825 ;; an integer register or memory, we store just the high-order 4 bits.
7826 ;; This lets us not shift in the most common case of CR0.
7827 (define_expand "movcc"
7828 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7829 (match_operand:CC 1 "nonimmediate_operand" ""))]
7830 ""
7831 "")
7832
7833 (define_insn "*movcc_internal1"
7834 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7835 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7836 "register_operand (operands[0], CCmode)
7837 || register_operand (operands[1], CCmode)"
7838 "@
7839 mcrf %0,%1
7840 mtcrf 128,%1
7841 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7842 mfcr %0%Q1
7843 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7844 mr %0,%1
7845 mf%1 %0
7846 mt%0 %1
7847 mt%0 %1
7848 {l%U1%X1|lwz%U1%X1} %0,%1
7849 {st%U0%U1|stw%U0%U1} %1,%0"
7850 [(set (attr "type")
7851 (cond [(eq_attr "alternative" "0")
7852 (const_string "cr_logical")
7853 (eq_attr "alternative" "1,2")
7854 (const_string "mtcr")
7855 (eq_attr "alternative" "5,7")
7856 (const_string "integer")
7857 (eq_attr "alternative" "6")
7858 (const_string "mfjmpr")
7859 (eq_attr "alternative" "8")
7860 (const_string "mtjmpr")
7861 (eq_attr "alternative" "9")
7862 (const_string "load")
7863 (eq_attr "alternative" "10")
7864 (const_string "store")
7865 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7866 (const_string "mfcrf")
7867 ]
7868 (const_string "mfcr")))
7869 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7870 \f
7871 ;; For floating-point, we normally deal with the floating-point registers
7872 ;; unless -msoft-float is used. The sole exception is that parameter passing
7873 ;; can produce floating-point values in fixed-point registers. Unless the
7874 ;; value is a simple constant or already in memory, we deal with this by
7875 ;; allocating memory and copying the value explicitly via that memory location.
7876 (define_expand "movsf"
7877 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7878 (match_operand:SF 1 "any_operand" ""))]
7879 ""
7880 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7881
7882 (define_split
7883 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7884 (match_operand:SF 1 "const_double_operand" ""))]
7885 "reload_completed
7886 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7887 || (GET_CODE (operands[0]) == SUBREG
7888 && GET_CODE (SUBREG_REG (operands[0])) == REG
7889 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7890 [(set (match_dup 2) (match_dup 3))]
7891 "
7892 {
7893 long l;
7894 REAL_VALUE_TYPE rv;
7895
7896 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7897 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7898
7899 if (! TARGET_POWERPC64)
7900 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7901 else
7902 operands[2] = gen_lowpart (SImode, operands[0]);
7903
7904 operands[3] = gen_int_mode (l, SImode);
7905 }")
7906
7907 (define_insn "*movsf_hardfloat"
7908 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7909 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7910 "(gpc_reg_operand (operands[0], SFmode)
7911 || gpc_reg_operand (operands[1], SFmode))
7912 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7913 "@
7914 mr %0,%1
7915 {l%U1%X1|lwz%U1%X1} %0,%1
7916 {st%U0%X0|stw%U0%X0} %1,%0
7917 fmr %0,%1
7918 lfs%U1%X1 %0,%1
7919 stfs%U0%X0 %1,%0
7920 mt%0 %1
7921 mt%0 %1
7922 mf%1 %0
7923 {cror 0,0,0|nop}
7924 #
7925 #"
7926 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7927 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7928
7929 (define_insn "*movsf_softfloat"
7930 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7931 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7932 "(gpc_reg_operand (operands[0], SFmode)
7933 || gpc_reg_operand (operands[1], SFmode))
7934 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7935 "@
7936 mr %0,%1
7937 mt%0 %1
7938 mt%0 %1
7939 mf%1 %0
7940 {l%U1%X1|lwz%U1%X1} %0,%1
7941 {st%U0%X0|stw%U0%X0} %1,%0
7942 {lil|li} %0,%1
7943 {liu|lis} %0,%v1
7944 {cal|la} %0,%a1
7945 #
7946 #
7947 {cror 0,0,0|nop}"
7948 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7949 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7950
7951 \f
7952 (define_expand "movdf"
7953 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7954 (match_operand:DF 1 "any_operand" ""))]
7955 ""
7956 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7957
7958 (define_split
7959 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7960 (match_operand:DF 1 "const_int_operand" ""))]
7961 "! TARGET_POWERPC64 && reload_completed
7962 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7963 || (GET_CODE (operands[0]) == SUBREG
7964 && GET_CODE (SUBREG_REG (operands[0])) == REG
7965 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7966 [(set (match_dup 2) (match_dup 4))
7967 (set (match_dup 3) (match_dup 1))]
7968 "
7969 {
7970 int endian = (WORDS_BIG_ENDIAN == 0);
7971 HOST_WIDE_INT value = INTVAL (operands[1]);
7972
7973 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7974 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7975 #if HOST_BITS_PER_WIDE_INT == 32
7976 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7977 #else
7978 operands[4] = GEN_INT (value >> 32);
7979 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7980 #endif
7981 }")
7982
7983 (define_split
7984 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7985 (match_operand:DF 1 "const_double_operand" ""))]
7986 "! TARGET_POWERPC64 && reload_completed
7987 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7988 || (GET_CODE (operands[0]) == SUBREG
7989 && GET_CODE (SUBREG_REG (operands[0])) == REG
7990 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7991 [(set (match_dup 2) (match_dup 4))
7992 (set (match_dup 3) (match_dup 5))]
7993 "
7994 {
7995 int endian = (WORDS_BIG_ENDIAN == 0);
7996 long l[2];
7997 REAL_VALUE_TYPE rv;
7998
7999 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8000 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8001
8002 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8003 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8004 operands[4] = gen_int_mode (l[endian], SImode);
8005 operands[5] = gen_int_mode (l[1 - endian], SImode);
8006 }")
8007
8008 (define_split
8009 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8010 (match_operand:DF 1 "easy_fp_constant" ""))]
8011 "TARGET_POWERPC64 && reload_completed
8012 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8013 || (GET_CODE (operands[0]) == SUBREG
8014 && GET_CODE (SUBREG_REG (operands[0])) == REG
8015 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8016 [(set (match_dup 2) (match_dup 3))]
8017 "
8018 {
8019 int endian = (WORDS_BIG_ENDIAN == 0);
8020 long l[2];
8021 REAL_VALUE_TYPE rv;
8022 #if HOST_BITS_PER_WIDE_INT >= 64
8023 HOST_WIDE_INT val;
8024 #endif
8025
8026 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8027 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8028
8029 operands[2] = gen_lowpart (DImode, operands[0]);
8030 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8031 #if HOST_BITS_PER_WIDE_INT >= 64
8032 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8033 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8034
8035 operands[3] = gen_int_mode (val, DImode);
8036 #else
8037 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8038 #endif
8039 }")
8040
8041 ;; Don't have reload use general registers to load a constant. First,
8042 ;; it might not work if the output operand is the equivalent of
8043 ;; a non-offsettable memref, but also it is less efficient than loading
8044 ;; the constant into an FP register, since it will probably be used there.
8045 ;; The "??" is a kludge until we can figure out a more reasonable way
8046 ;; of handling these non-offsettable values.
8047 (define_insn "*movdf_hardfloat32"
8048 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8049 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8050 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8051 && (gpc_reg_operand (operands[0], DFmode)
8052 || gpc_reg_operand (operands[1], DFmode))"
8053 "*
8054 {
8055 switch (which_alternative)
8056 {
8057 default:
8058 abort ();
8059 case 0:
8060 /* We normally copy the low-numbered register first. However, if
8061 the first register operand 0 is the same as the second register
8062 of operand 1, we must copy in the opposite order. */
8063 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8064 return \"mr %L0,%L1\;mr %0,%1\";
8065 else
8066 return \"mr %0,%1\;mr %L0,%L1\";
8067 case 1:
8068 if (GET_CODE (operands[1]) == MEM
8069 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8070 reload_completed || reload_in_progress)
8071 || GET_CODE (XEXP (operands[1], 0)) == REG
8072 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8073 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8074 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8075 {
8076 /* If the low-address word is used in the address, we must load
8077 it last. Otherwise, load it first. Note that we cannot have
8078 auto-increment in that case since the address register is
8079 known to be dead. */
8080 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8081 operands[1], 0))
8082 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8083 else
8084 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8085 }
8086 else
8087 {
8088 rtx addreg;
8089
8090 addreg = find_addr_reg (XEXP (operands[1], 0));
8091 if (refers_to_regno_p (REGNO (operands[0]),
8092 REGNO (operands[0]) + 1,
8093 operands[1], 0))
8094 {
8095 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8096 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8097 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8098 return \"{lx|lwzx} %0,%1\";
8099 }
8100 else
8101 {
8102 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8103 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8104 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8105 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8106 return \"\";
8107 }
8108 }
8109 case 2:
8110 if (GET_CODE (operands[0]) == MEM
8111 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8112 reload_completed || reload_in_progress)
8113 || GET_CODE (XEXP (operands[0], 0)) == REG
8114 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8115 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8116 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8117 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8118 else
8119 {
8120 rtx addreg;
8121
8122 addreg = find_addr_reg (XEXP (operands[0], 0));
8123 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8124 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8125 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8126 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8127 return \"\";
8128 }
8129 case 3:
8130 return \"fmr %0,%1\";
8131 case 4:
8132 return \"lfd%U1%X1 %0,%1\";
8133 case 5:
8134 return \"stfd%U0%X0 %1,%0\";
8135 case 6:
8136 case 7:
8137 case 8:
8138 return \"#\";
8139 }
8140 }"
8141 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8142 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8143
8144 (define_insn "*movdf_softfloat32"
8145 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8146 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8147 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8148 && (gpc_reg_operand (operands[0], DFmode)
8149 || gpc_reg_operand (operands[1], DFmode))"
8150 "*
8151 {
8152 switch (which_alternative)
8153 {
8154 default:
8155 abort ();
8156 case 0:
8157 /* We normally copy the low-numbered register first. However, if
8158 the first register operand 0 is the same as the second register of
8159 operand 1, we must copy in the opposite order. */
8160 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8161 return \"mr %L0,%L1\;mr %0,%1\";
8162 else
8163 return \"mr %0,%1\;mr %L0,%L1\";
8164 case 1:
8165 /* If the low-address word is used in the address, we must load
8166 it last. Otherwise, load it first. Note that we cannot have
8167 auto-increment in that case since the address register is
8168 known to be dead. */
8169 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8170 operands[1], 0))
8171 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8172 else
8173 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8174 case 2:
8175 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8176 case 3:
8177 case 4:
8178 case 5:
8179 return \"#\";
8180 }
8181 }"
8182 [(set_attr "type" "two,load,store,*,*,*")
8183 (set_attr "length" "8,8,8,8,12,16")])
8184
8185 ; ld/std require word-aligned displacements -> 'Y' constraint.
8186 ; List Y->r and r->Y before r->r for reload.
8187 (define_insn "*movdf_hardfloat64"
8188 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8189 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8190 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8191 && (gpc_reg_operand (operands[0], DFmode)
8192 || gpc_reg_operand (operands[1], DFmode))"
8193 "@
8194 std%U0%X0 %1,%0
8195 ld%U1%X1 %0,%1
8196 mr %0,%1
8197 fmr %0,%1
8198 lfd%U1%X1 %0,%1
8199 stfd%U0%X0 %1,%0
8200 mt%0 %1
8201 mf%1 %0
8202 {cror 0,0,0|nop}
8203 #
8204 #
8205 #"
8206 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8207 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8208
8209 (define_insn "*movdf_softfloat64"
8210 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8211 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8212 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8213 && (gpc_reg_operand (operands[0], DFmode)
8214 || gpc_reg_operand (operands[1], DFmode))"
8215 "@
8216 ld%U1%X1 %0,%1
8217 std%U0%X0 %1,%0
8218 mr %0,%1
8219 mt%0 %1
8220 mf%1 %0
8221 #
8222 #
8223 #
8224 {cror 0,0,0|nop}"
8225 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8226 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8227 \f
8228 (define_expand "movtf"
8229 [(set (match_operand:TF 0 "general_operand" "")
8230 (match_operand:TF 1 "any_operand" ""))]
8231 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8232 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8233 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8234
8235 ; It's important to list the o->f and f->o moves before f->f because
8236 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8237 ; which doesn't make progress. Likewise r->o<> must be before r->r.
8238 (define_insn_and_split "*movtf_internal"
8239 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,o<>,r")
8240 (match_operand:TF 1 "input_operand" "f,o,f,mGHF,r,r"))]
8241 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8242 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8243 && (gpc_reg_operand (operands[0], TFmode)
8244 || gpc_reg_operand (operands[1], TFmode))"
8245 "#"
8246 "&& reload_completed"
8247 [(pc)]
8248 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8249 [(set_attr "length" "8,8,8,20,20,16")])
8250
8251 (define_expand "extenddftf2"
8252 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8253 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8254 (use (match_dup 2))])]
8255 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8256 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8257 {
8258 operands[2] = CONST0_RTX (DFmode);
8259 })
8260
8261 (define_insn_and_split "*extenddftf2_internal"
8262 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8263 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8264 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8265 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8266 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8267 "#"
8268 "&& reload_completed"
8269 [(pc)]
8270 {
8271 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8272 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8273 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8274 operands[1]);
8275 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8276 operands[2]);
8277 DONE;
8278 })
8279
8280 (define_expand "extendsftf2"
8281 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8282 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8283 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8284 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8285 {
8286 rtx tmp = gen_reg_rtx (DFmode);
8287 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8288 emit_insn (gen_extenddftf2 (operands[0], tmp));
8289 DONE;
8290 })
8291
8292 (define_insn "trunctfdf2"
8293 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8294 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8295 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8296 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8297 "fadd %0,%1,%L1"
8298 [(set_attr "type" "fp")
8299 (set_attr "length" "4")])
8300
8301 (define_insn_and_split "trunctfsf2"
8302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8303 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8304 (clobber (match_scratch:DF 2 "=f"))]
8305 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8306 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8307 "#"
8308 "&& reload_completed"
8309 [(set (match_dup 2)
8310 (float_truncate:DF (match_dup 1)))
8311 (set (match_dup 0)
8312 (float_truncate:SF (match_dup 2)))]
8313 "")
8314
8315 (define_expand "floatsitf2"
8316 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8317 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8318 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8319 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8320 {
8321 rtx tmp = gen_reg_rtx (DFmode);
8322 expand_float (tmp, operands[1], false);
8323 emit_insn (gen_extenddftf2 (operands[0], tmp));
8324 DONE;
8325 })
8326
8327 ; fadd, but rounding towards zero.
8328 ; This is probably not the optimal code sequence.
8329 (define_insn "fix_trunc_helper"
8330 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8331 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8332 UNSPEC_FIX_TRUNC_TF))
8333 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8334 "TARGET_HARD_FLOAT && TARGET_FPRS"
8335 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8336 [(set_attr "type" "fp")
8337 (set_attr "length" "20")])
8338
8339 (define_expand "fix_trunctfsi2"
8340 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8341 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8342 (clobber (match_dup 2))
8343 (clobber (match_dup 3))
8344 (clobber (match_dup 4))
8345 (clobber (match_dup 5))])]
8346 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8347 && (TARGET_POWER2 || TARGET_POWERPC)
8348 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8349 {
8350 operands[2] = gen_reg_rtx (DFmode);
8351 operands[3] = gen_reg_rtx (DFmode);
8352 operands[4] = gen_reg_rtx (DImode);
8353 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8354 })
8355
8356 (define_insn_and_split "*fix_trunctfsi2_internal"
8357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8358 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8359 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8360 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8361 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8362 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8363 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8364 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8365 "#"
8366 "&& reload_completed"
8367 [(pc)]
8368 {
8369 rtx lowword;
8370 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8371
8372 if (GET_CODE (operands[5]) != MEM)
8373 abort();
8374 lowword = XEXP (operands[5], 0);
8375 if (WORDS_BIG_ENDIAN)
8376 lowword = plus_constant (lowword, 4);
8377
8378 emit_insn (gen_fctiwz (operands[4], operands[2]));
8379 emit_move_insn (operands[5], operands[4]);
8380 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8381 DONE;
8382 })
8383
8384 (define_insn "negtf2"
8385 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8386 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8387 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8388 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8389 "*
8390 {
8391 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8392 return \"fneg %L0,%L1\;fneg %0,%1\";
8393 else
8394 return \"fneg %0,%1\;fneg %L0,%L1\";
8395 }"
8396 [(set_attr "type" "fp")
8397 (set_attr "length" "8")])
8398
8399 (define_expand "abstf2"
8400 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8401 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8402 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8403 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8404 "
8405 {
8406 rtx label = gen_label_rtx ();
8407 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8408 emit_label (label);
8409 DONE;
8410 }")
8411
8412 (define_expand "abstf2_internal"
8413 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8414 (match_operand:TF 1 "gpc_reg_operand" "f"))
8415 (set (match_dup 3) (match_dup 5))
8416 (set (match_dup 5) (abs:DF (match_dup 5)))
8417 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8418 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8419 (label_ref (match_operand 2 "" ""))
8420 (pc)))
8421 (set (match_dup 6) (neg:DF (match_dup 6)))]
8422 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8423 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8424 "
8425 {
8426 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8427 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8428 operands[3] = gen_reg_rtx (DFmode);
8429 operands[4] = gen_reg_rtx (CCFPmode);
8430 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8431 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8432 }")
8433 \f
8434 ;; Next come the multi-word integer load and store and the load and store
8435 ;; multiple insns.
8436 (define_expand "movdi"
8437 [(set (match_operand:DI 0 "general_operand" "")
8438 (match_operand:DI 1 "any_operand" ""))]
8439 ""
8440 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8441
8442 ; List r->r after r->"o<>", otherwise reload will try to reload a
8443 ; non-offsettable address by using r->r which won't make progress.
8444 (define_insn "*movdi_internal32"
8445 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8446 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8447 "! TARGET_POWERPC64
8448 && (gpc_reg_operand (operands[0], DImode)
8449 || gpc_reg_operand (operands[1], DImode))"
8450 "@
8451 #
8452 #
8453 #
8454 fmr %0,%1
8455 lfd%U1%X1 %0,%1
8456 stfd%U0%X0 %1,%0
8457 #"
8458 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8459
8460 (define_split
8461 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8462 (match_operand:DI 1 "const_int_operand" ""))]
8463 "! TARGET_POWERPC64 && reload_completed"
8464 [(set (match_dup 2) (match_dup 4))
8465 (set (match_dup 3) (match_dup 1))]
8466 "
8467 {
8468 HOST_WIDE_INT value = INTVAL (operands[1]);
8469 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8470 DImode);
8471 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8472 DImode);
8473 #if HOST_BITS_PER_WIDE_INT == 32
8474 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8475 #else
8476 operands[4] = GEN_INT (value >> 32);
8477 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8478 #endif
8479 }")
8480
8481 (define_split
8482 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8483 (match_operand:DI 1 "input_operand" ""))]
8484 "reload_completed && !TARGET_POWERPC64
8485 && gpr_or_gpr_p (operands[0], operands[1])"
8486 [(pc)]
8487 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8488
8489 (define_split
8490 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8491 (match_operand:TI 1 "const_double_operand" ""))]
8492 "TARGET_POWERPC64"
8493 [(set (match_dup 2) (match_dup 4))
8494 (set (match_dup 3) (match_dup 5))]
8495 "
8496 {
8497 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8498 TImode);
8499 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8500 TImode);
8501 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8502 {
8503 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8504 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8505 }
8506 else if (GET_CODE (operands[1]) == CONST_INT)
8507 {
8508 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8509 operands[5] = operands[1];
8510 }
8511 else
8512 FAIL;
8513 }")
8514
8515 (define_insn "*movdi_internal64"
8516 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8517 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8518 "TARGET_POWERPC64
8519 && (gpc_reg_operand (operands[0], DImode)
8520 || gpc_reg_operand (operands[1], DImode))"
8521 "@
8522 mr %0,%1
8523 ld%U1%X1 %0,%1
8524 std%U0%X0 %1,%0
8525 li %0,%1
8526 lis %0,%v1
8527 #
8528 {cal|la} %0,%a1
8529 fmr %0,%1
8530 lfd%U1%X1 %0,%1
8531 stfd%U0%X0 %1,%0
8532 mf%1 %0
8533 mt%0 %1
8534 {cror 0,0,0|nop}"
8535 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8536 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8537
8538 ;; immediate value valid for a single instruction hiding in a const_double
8539 (define_insn ""
8540 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8541 (match_operand:DI 1 "const_double_operand" "F"))]
8542 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8543 && GET_CODE (operands[1]) == CONST_DOUBLE
8544 && num_insns_constant (operands[1], DImode) == 1"
8545 "*
8546 {
8547 return ((unsigned HOST_WIDE_INT)
8548 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8549 ? \"li %0,%1\" : \"lis %0,%v1\";
8550 }")
8551
8552 ;; Generate all one-bits and clear left or right.
8553 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8554 (define_split
8555 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8556 (match_operand:DI 1 "mask64_operand" ""))]
8557 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8558 [(set (match_dup 0) (const_int -1))
8559 (set (match_dup 0)
8560 (and:DI (rotate:DI (match_dup 0)
8561 (const_int 0))
8562 (match_dup 1)))]
8563 "")
8564
8565 ;; Split a load of a large constant into the appropriate five-instruction
8566 ;; sequence. Handle anything in a constant number of insns.
8567 ;; When non-easy constants can go in the TOC, this should use
8568 ;; easy_fp_constant predicate.
8569 (define_split
8570 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8571 (match_operand:DI 1 "const_int_operand" ""))]
8572 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8573 [(set (match_dup 0) (match_dup 2))
8574 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8575 "
8576 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8577
8578 if (tem == operands[0])
8579 DONE;
8580 else
8581 FAIL;
8582 }")
8583
8584 (define_split
8585 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8586 (match_operand:DI 1 "const_double_operand" ""))]
8587 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8588 [(set (match_dup 0) (match_dup 2))
8589 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8590 "
8591 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8592
8593 if (tem == operands[0])
8594 DONE;
8595 else
8596 FAIL;
8597 }")
8598
8599 (define_insn "*movdi_internal2"
8600 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8601 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8602 (const_int 0)))
8603 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8604 "TARGET_64BIT"
8605 "@
8606 cmpdi %2,%0,0
8607 mr. %0,%1
8608 #"
8609 [(set_attr "type" "cmp,compare,cmp")
8610 (set_attr "length" "4,4,8")])
8611
8612 (define_split
8613 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8614 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8615 (const_int 0)))
8616 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8617 "TARGET_POWERPC64 && reload_completed"
8618 [(set (match_dup 0) (match_dup 1))
8619 (set (match_dup 2)
8620 (compare:CC (match_dup 0)
8621 (const_int 0)))]
8622 "")
8623 \f
8624 ;; TImode is similar, except that we usually want to compute the address into
8625 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8626 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8627 (define_expand "movti"
8628 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8629 (match_operand:TI 1 "general_operand" ""))
8630 (clobber (scratch:SI))])]
8631 ""
8632 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8633
8634 ;; We say that MQ is clobbered in the last alternative because the first
8635 ;; alternative would never get used otherwise since it would need a reload
8636 ;; while the 2nd alternative would not. We put memory cases first so they
8637 ;; are preferred. Otherwise, we'd try to reload the output instead of
8638 ;; giving the SCRATCH mq.
8639
8640 (define_insn "*movti_power"
8641 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8642 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8643 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8644 "TARGET_POWER && ! TARGET_POWERPC64
8645 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8646 "*
8647 {
8648 switch (which_alternative)
8649 {
8650 default:
8651 abort ();
8652
8653 case 0:
8654 if (TARGET_STRING)
8655 return \"{stsi|stswi} %1,%P0,16\";
8656 case 1:
8657 case 2:
8658 return \"#\";
8659 case 3:
8660 /* If the address is not used in the output, we can use lsi. Otherwise,
8661 fall through to generating four loads. */
8662 if (TARGET_STRING
8663 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8664 return \"{lsi|lswi} %0,%P1,16\";
8665 /* ... fall through ... */
8666 case 4:
8667 return \"#\";
8668 }
8669 }"
8670 [(set_attr "type" "store,store,*,load,load")])
8671
8672 (define_insn "*movti_string"
8673 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r")
8674 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8675 "! TARGET_POWER && ! TARGET_POWERPC64
8676 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8677 "*
8678 {
8679 switch (which_alternative)
8680 {
8681 default:
8682 abort ();
8683 case 0:
8684 if (TARGET_STRING)
8685 return \"{stsi|stswi} %1,%P0,16\";
8686 case 1:
8687 case 2:
8688 return \"#\";
8689 case 3:
8690 /* If the address is not used in the output, we can use lsi. Otherwise,
8691 fall through to generating four loads. */
8692 if (TARGET_STRING
8693 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8694 return \"{lsi|lswi} %0,%P1,16\";
8695 /* ... fall through ... */
8696 case 4:
8697 return \"#\";
8698 }
8699 }"
8700 [(set_attr "type" "store,store,*,load,load")])
8701
8702 (define_insn "*movti_ppc64"
8703 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8704 (match_operand:TI 1 "input_operand" "r,r,m"))]
8705 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8706 || gpc_reg_operand (operands[1], TImode))"
8707 "#"
8708 [(set_attr "type" "*,load,store")])
8709
8710 (define_split
8711 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8712 (match_operand:TI 1 "input_operand" ""))]
8713 "reload_completed
8714 && gpr_or_gpr_p (operands[0], operands[1])"
8715 [(pc)]
8716 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8717 \f
8718 (define_expand "load_multiple"
8719 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8720 (match_operand:SI 1 "" ""))
8721 (use (match_operand:SI 2 "" ""))])]
8722 "TARGET_STRING && !TARGET_POWERPC64"
8723 "
8724 {
8725 int regno;
8726 int count;
8727 rtx op1;
8728 int i;
8729
8730 /* Support only loading a constant number of fixed-point registers from
8731 memory and only bother with this if more than two; the machine
8732 doesn't support more than eight. */
8733 if (GET_CODE (operands[2]) != CONST_INT
8734 || INTVAL (operands[2]) <= 2
8735 || INTVAL (operands[2]) > 8
8736 || GET_CODE (operands[1]) != MEM
8737 || GET_CODE (operands[0]) != REG
8738 || REGNO (operands[0]) >= 32)
8739 FAIL;
8740
8741 count = INTVAL (operands[2]);
8742 regno = REGNO (operands[0]);
8743
8744 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8745 op1 = replace_equiv_address (operands[1],
8746 force_reg (SImode, XEXP (operands[1], 0)));
8747
8748 for (i = 0; i < count; i++)
8749 XVECEXP (operands[3], 0, i)
8750 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8751 adjust_address_nv (op1, SImode, i * 4));
8752 }")
8753
8754 (define_insn "*ldmsi8"
8755 [(match_parallel 0 "load_multiple_operation"
8756 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8757 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8758 (set (match_operand:SI 3 "gpc_reg_operand" "")
8759 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8760 (set (match_operand:SI 4 "gpc_reg_operand" "")
8761 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8762 (set (match_operand:SI 5 "gpc_reg_operand" "")
8763 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8764 (set (match_operand:SI 6 "gpc_reg_operand" "")
8765 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8766 (set (match_operand:SI 7 "gpc_reg_operand" "")
8767 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8768 (set (match_operand:SI 8 "gpc_reg_operand" "")
8769 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8770 (set (match_operand:SI 9 "gpc_reg_operand" "")
8771 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8772 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8773 "*
8774 { return rs6000_output_load_multiple (operands); }"
8775 [(set_attr "type" "load")
8776 (set_attr "length" "32")])
8777
8778 (define_insn "*ldmsi7"
8779 [(match_parallel 0 "load_multiple_operation"
8780 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8781 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8782 (set (match_operand:SI 3 "gpc_reg_operand" "")
8783 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8784 (set (match_operand:SI 4 "gpc_reg_operand" "")
8785 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8786 (set (match_operand:SI 5 "gpc_reg_operand" "")
8787 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8788 (set (match_operand:SI 6 "gpc_reg_operand" "")
8789 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8790 (set (match_operand:SI 7 "gpc_reg_operand" "")
8791 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8792 (set (match_operand:SI 8 "gpc_reg_operand" "")
8793 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8794 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8795 "*
8796 { return rs6000_output_load_multiple (operands); }"
8797 [(set_attr "type" "load")
8798 (set_attr "length" "32")])
8799
8800 (define_insn "*ldmsi6"
8801 [(match_parallel 0 "load_multiple_operation"
8802 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8803 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8804 (set (match_operand:SI 3 "gpc_reg_operand" "")
8805 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8806 (set (match_operand:SI 4 "gpc_reg_operand" "")
8807 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8808 (set (match_operand:SI 5 "gpc_reg_operand" "")
8809 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8810 (set (match_operand:SI 6 "gpc_reg_operand" "")
8811 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8812 (set (match_operand:SI 7 "gpc_reg_operand" "")
8813 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8814 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8815 "*
8816 { return rs6000_output_load_multiple (operands); }"
8817 [(set_attr "type" "load")
8818 (set_attr "length" "32")])
8819
8820 (define_insn "*ldmsi5"
8821 [(match_parallel 0 "load_multiple_operation"
8822 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8823 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8824 (set (match_operand:SI 3 "gpc_reg_operand" "")
8825 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8826 (set (match_operand:SI 4 "gpc_reg_operand" "")
8827 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8828 (set (match_operand:SI 5 "gpc_reg_operand" "")
8829 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8830 (set (match_operand:SI 6 "gpc_reg_operand" "")
8831 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8832 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8833 "*
8834 { return rs6000_output_load_multiple (operands); }"
8835 [(set_attr "type" "load")
8836 (set_attr "length" "32")])
8837
8838 (define_insn "*ldmsi4"
8839 [(match_parallel 0 "load_multiple_operation"
8840 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8841 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8842 (set (match_operand:SI 3 "gpc_reg_operand" "")
8843 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8844 (set (match_operand:SI 4 "gpc_reg_operand" "")
8845 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8846 (set (match_operand:SI 5 "gpc_reg_operand" "")
8847 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8848 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8849 "*
8850 { return rs6000_output_load_multiple (operands); }"
8851 [(set_attr "type" "load")
8852 (set_attr "length" "32")])
8853
8854 (define_insn "*ldmsi3"
8855 [(match_parallel 0 "load_multiple_operation"
8856 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8857 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8858 (set (match_operand:SI 3 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8860 (set (match_operand:SI 4 "gpc_reg_operand" "")
8861 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8862 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8863 "*
8864 { return rs6000_output_load_multiple (operands); }"
8865 [(set_attr "type" "load")
8866 (set_attr "length" "32")])
8867
8868 (define_expand "store_multiple"
8869 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8870 (match_operand:SI 1 "" ""))
8871 (clobber (scratch:SI))
8872 (use (match_operand:SI 2 "" ""))])]
8873 "TARGET_STRING && !TARGET_POWERPC64"
8874 "
8875 {
8876 int regno;
8877 int count;
8878 rtx to;
8879 rtx op0;
8880 int i;
8881
8882 /* Support only storing a constant number of fixed-point registers to
8883 memory and only bother with this if more than two; the machine
8884 doesn't support more than eight. */
8885 if (GET_CODE (operands[2]) != CONST_INT
8886 || INTVAL (operands[2]) <= 2
8887 || INTVAL (operands[2]) > 8
8888 || GET_CODE (operands[0]) != MEM
8889 || GET_CODE (operands[1]) != REG
8890 || REGNO (operands[1]) >= 32)
8891 FAIL;
8892
8893 count = INTVAL (operands[2]);
8894 regno = REGNO (operands[1]);
8895
8896 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8897 to = force_reg (SImode, XEXP (operands[0], 0));
8898 op0 = replace_equiv_address (operands[0], to);
8899
8900 XVECEXP (operands[3], 0, 0)
8901 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8902 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8903 gen_rtx_SCRATCH (SImode));
8904
8905 for (i = 1; i < count; i++)
8906 XVECEXP (operands[3], 0, i + 1)
8907 = gen_rtx_SET (VOIDmode,
8908 adjust_address_nv (op0, SImode, i * 4),
8909 gen_rtx_REG (SImode, regno + i));
8910 }")
8911
8912 (define_insn "*store_multiple_power"
8913 [(match_parallel 0 "store_multiple_operation"
8914 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8915 (match_operand:SI 2 "gpc_reg_operand" "r"))
8916 (clobber (match_scratch:SI 3 "=q"))])]
8917 "TARGET_STRING && TARGET_POWER"
8918 "{stsi|stswi} %2,%P1,%O0"
8919 [(set_attr "type" "store")])
8920
8921 (define_insn "*stmsi8"
8922 [(match_parallel 0 "store_multiple_operation"
8923 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8924 (match_operand:SI 2 "gpc_reg_operand" "r"))
8925 (clobber (match_scratch:SI 3 "X"))
8926 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8927 (match_operand:SI 4 "gpc_reg_operand" "r"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8929 (match_operand:SI 5 "gpc_reg_operand" "r"))
8930 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8931 (match_operand:SI 6 "gpc_reg_operand" "r"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8933 (match_operand:SI 7 "gpc_reg_operand" "r"))
8934 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8935 (match_operand:SI 8 "gpc_reg_operand" "r"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8937 (match_operand:SI 9 "gpc_reg_operand" "r"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8939 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8940 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8941 "{stsi|stswi} %2,%1,%O0"
8942 [(set_attr "type" "store")])
8943
8944 (define_insn "*stmsi7"
8945 [(match_parallel 0 "store_multiple_operation"
8946 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8947 (match_operand:SI 2 "gpc_reg_operand" "r"))
8948 (clobber (match_scratch:SI 3 "X"))
8949 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8950 (match_operand:SI 4 "gpc_reg_operand" "r"))
8951 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8952 (match_operand:SI 5 "gpc_reg_operand" "r"))
8953 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8954 (match_operand:SI 6 "gpc_reg_operand" "r"))
8955 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8956 (match_operand:SI 7 "gpc_reg_operand" "r"))
8957 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8958 (match_operand:SI 8 "gpc_reg_operand" "r"))
8959 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8960 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8961 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8962 "{stsi|stswi} %2,%1,%O0"
8963 [(set_attr "type" "store")])
8964
8965 (define_insn "*stmsi6"
8966 [(match_parallel 0 "store_multiple_operation"
8967 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8968 (match_operand:SI 2 "gpc_reg_operand" "r"))
8969 (clobber (match_scratch:SI 3 "X"))
8970 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8971 (match_operand:SI 4 "gpc_reg_operand" "r"))
8972 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8973 (match_operand:SI 5 "gpc_reg_operand" "r"))
8974 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8975 (match_operand:SI 6 "gpc_reg_operand" "r"))
8976 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8977 (match_operand:SI 7 "gpc_reg_operand" "r"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8979 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8980 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8981 "{stsi|stswi} %2,%1,%O0"
8982 [(set_attr "type" "store")])
8983
8984 (define_insn "*stmsi5"
8985 [(match_parallel 0 "store_multiple_operation"
8986 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8987 (match_operand:SI 2 "gpc_reg_operand" "r"))
8988 (clobber (match_scratch:SI 3 "X"))
8989 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8990 (match_operand:SI 4 "gpc_reg_operand" "r"))
8991 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8992 (match_operand:SI 5 "gpc_reg_operand" "r"))
8993 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8994 (match_operand:SI 6 "gpc_reg_operand" "r"))
8995 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8996 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8997 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8998 "{stsi|stswi} %2,%1,%O0"
8999 [(set_attr "type" "store")])
9000
9001 (define_insn "*stmsi4"
9002 [(match_parallel 0 "store_multiple_operation"
9003 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9004 (match_operand:SI 2 "gpc_reg_operand" "r"))
9005 (clobber (match_scratch:SI 3 "X"))
9006 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9007 (match_operand:SI 4 "gpc_reg_operand" "r"))
9008 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9009 (match_operand:SI 5 "gpc_reg_operand" "r"))
9010 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9011 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9012 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9013 "{stsi|stswi} %2,%1,%O0"
9014 [(set_attr "type" "store")])
9015
9016 (define_insn "*stmsi3"
9017 [(match_parallel 0 "store_multiple_operation"
9018 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9019 (match_operand:SI 2 "gpc_reg_operand" "r"))
9020 (clobber (match_scratch:SI 3 "X"))
9021 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9022 (match_operand:SI 4 "gpc_reg_operand" "r"))
9023 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9024 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9025 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9026 "{stsi|stswi} %2,%1,%O0"
9027 [(set_attr "type" "store")])
9028 \f
9029 (define_expand "clrmemsi"
9030 [(parallel [(set (match_operand:BLK 0 "" "")
9031 (const_int 0))
9032 (use (match_operand:SI 1 "" ""))
9033 (use (match_operand:SI 2 "" ""))])]
9034 ""
9035 "
9036 {
9037 if (expand_block_clear (operands))
9038 DONE;
9039 else
9040 FAIL;
9041 }")
9042
9043 ;; String/block move insn.
9044 ;; Argument 0 is the destination
9045 ;; Argument 1 is the source
9046 ;; Argument 2 is the length
9047 ;; Argument 3 is the alignment
9048
9049 (define_expand "movmemsi"
9050 [(parallel [(set (match_operand:BLK 0 "" "")
9051 (match_operand:BLK 1 "" ""))
9052 (use (match_operand:SI 2 "" ""))
9053 (use (match_operand:SI 3 "" ""))])]
9054 ""
9055 "
9056 {
9057 if (expand_block_move (operands))
9058 DONE;
9059 else
9060 FAIL;
9061 }")
9062
9063 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9064 ;; register allocator doesn't have a clue about allocating 8 word registers.
9065 ;; rD/rS = r5 is preferred, efficient form.
9066 (define_expand "movmemsi_8reg"
9067 [(parallel [(set (match_operand 0 "" "")
9068 (match_operand 1 "" ""))
9069 (use (match_operand 2 "" ""))
9070 (use (match_operand 3 "" ""))
9071 (clobber (reg:SI 5))
9072 (clobber (reg:SI 6))
9073 (clobber (reg:SI 7))
9074 (clobber (reg:SI 8))
9075 (clobber (reg:SI 9))
9076 (clobber (reg:SI 10))
9077 (clobber (reg:SI 11))
9078 (clobber (reg:SI 12))
9079 (clobber (match_scratch:SI 4 ""))])]
9080 "TARGET_STRING"
9081 "")
9082
9083 (define_insn ""
9084 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9085 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9086 (use (match_operand:SI 2 "immediate_operand" "i"))
9087 (use (match_operand:SI 3 "immediate_operand" "i"))
9088 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9089 (clobber (reg:SI 6))
9090 (clobber (reg:SI 7))
9091 (clobber (reg:SI 8))
9092 (clobber (reg:SI 9))
9093 (clobber (reg:SI 10))
9094 (clobber (reg:SI 11))
9095 (clobber (reg:SI 12))
9096 (clobber (match_scratch:SI 5 "=q"))]
9097 "TARGET_STRING && TARGET_POWER
9098 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9099 || INTVAL (operands[2]) == 0)
9100 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9101 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9102 && REGNO (operands[4]) == 5"
9103 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9104 [(set_attr "type" "load")
9105 (set_attr "length" "8")])
9106
9107 (define_insn ""
9108 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9109 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9110 (use (match_operand:SI 2 "immediate_operand" "i"))
9111 (use (match_operand:SI 3 "immediate_operand" "i"))
9112 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9113 (clobber (reg:SI 6))
9114 (clobber (reg:SI 7))
9115 (clobber (reg:SI 8))
9116 (clobber (reg:SI 9))
9117 (clobber (reg:SI 10))
9118 (clobber (reg:SI 11))
9119 (clobber (reg:SI 12))
9120 (clobber (match_scratch:SI 5 "X"))]
9121 "TARGET_STRING && ! TARGET_POWER
9122 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9123 || INTVAL (operands[2]) == 0)
9124 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9125 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9126 && REGNO (operands[4]) == 5"
9127 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9128 [(set_attr "type" "load")
9129 (set_attr "length" "8")])
9130
9131 (define_insn ""
9132 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9133 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9134 (use (match_operand:SI 2 "immediate_operand" "i"))
9135 (use (match_operand:SI 3 "immediate_operand" "i"))
9136 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9137 (clobber (reg:SI 6))
9138 (clobber (reg:SI 7))
9139 (clobber (reg:SI 8))
9140 (clobber (reg:SI 9))
9141 (clobber (reg:SI 10))
9142 (clobber (reg:SI 11))
9143 (clobber (reg:SI 12))
9144 (clobber (match_scratch:SI 5 "X"))]
9145 "TARGET_STRING && TARGET_POWERPC64
9146 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9147 || INTVAL (operands[2]) == 0)
9148 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9149 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9150 && REGNO (operands[4]) == 5"
9151 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9152 [(set_attr "type" "load")
9153 (set_attr "length" "8")])
9154
9155 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9156 ;; register allocator doesn't have a clue about allocating 6 word registers.
9157 ;; rD/rS = r5 is preferred, efficient form.
9158 (define_expand "movmemsi_6reg"
9159 [(parallel [(set (match_operand 0 "" "")
9160 (match_operand 1 "" ""))
9161 (use (match_operand 2 "" ""))
9162 (use (match_operand 3 "" ""))
9163 (clobber (reg:SI 5))
9164 (clobber (reg:SI 6))
9165 (clobber (reg:SI 7))
9166 (clobber (reg:SI 8))
9167 (clobber (reg:SI 9))
9168 (clobber (reg:SI 10))
9169 (clobber (match_scratch:SI 4 ""))])]
9170 "TARGET_STRING"
9171 "")
9172
9173 (define_insn ""
9174 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9175 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9176 (use (match_operand:SI 2 "immediate_operand" "i"))
9177 (use (match_operand:SI 3 "immediate_operand" "i"))
9178 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9179 (clobber (reg:SI 6))
9180 (clobber (reg:SI 7))
9181 (clobber (reg:SI 8))
9182 (clobber (reg:SI 9))
9183 (clobber (reg:SI 10))
9184 (clobber (match_scratch:SI 5 "=q"))]
9185 "TARGET_STRING && TARGET_POWER
9186 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9187 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9188 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9189 && REGNO (operands[4]) == 5"
9190 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9191 [(set_attr "type" "load")
9192 (set_attr "length" "8")])
9193
9194 (define_insn ""
9195 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9196 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9197 (use (match_operand:SI 2 "immediate_operand" "i"))
9198 (use (match_operand:SI 3 "immediate_operand" "i"))
9199 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9200 (clobber (reg:SI 6))
9201 (clobber (reg:SI 7))
9202 (clobber (reg:SI 8))
9203 (clobber (reg:SI 9))
9204 (clobber (reg:SI 10))
9205 (clobber (match_scratch:SI 5 "X"))]
9206 "TARGET_STRING && ! TARGET_POWER
9207 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9208 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9209 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9210 && REGNO (operands[4]) == 5"
9211 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9212 [(set_attr "type" "load")
9213 (set_attr "length" "8")])
9214
9215 (define_insn ""
9216 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9217 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9218 (use (match_operand:SI 2 "immediate_operand" "i"))
9219 (use (match_operand:SI 3 "immediate_operand" "i"))
9220 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9221 (clobber (reg:SI 6))
9222 (clobber (reg:SI 7))
9223 (clobber (reg:SI 8))
9224 (clobber (reg:SI 9))
9225 (clobber (reg:SI 10))
9226 (clobber (match_scratch:SI 5 "X"))]
9227 "TARGET_STRING && TARGET_POWERPC64
9228 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9229 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9230 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9231 && REGNO (operands[4]) == 5"
9232 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9233 [(set_attr "type" "load")
9234 (set_attr "length" "8")])
9235
9236 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9237 ;; problems with TImode.
9238 ;; rD/rS = r5 is preferred, efficient form.
9239 (define_expand "movmemsi_4reg"
9240 [(parallel [(set (match_operand 0 "" "")
9241 (match_operand 1 "" ""))
9242 (use (match_operand 2 "" ""))
9243 (use (match_operand 3 "" ""))
9244 (clobber (reg:SI 5))
9245 (clobber (reg:SI 6))
9246 (clobber (reg:SI 7))
9247 (clobber (reg:SI 8))
9248 (clobber (match_scratch:SI 4 ""))])]
9249 "TARGET_STRING"
9250 "")
9251
9252 (define_insn ""
9253 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9254 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9255 (use (match_operand:SI 2 "immediate_operand" "i"))
9256 (use (match_operand:SI 3 "immediate_operand" "i"))
9257 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9258 (clobber (reg:SI 6))
9259 (clobber (reg:SI 7))
9260 (clobber (reg:SI 8))
9261 (clobber (match_scratch:SI 5 "=q"))]
9262 "TARGET_STRING && TARGET_POWER
9263 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9264 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9265 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9266 && REGNO (operands[4]) == 5"
9267 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9268 [(set_attr "type" "load")
9269 (set_attr "length" "8")])
9270
9271 (define_insn ""
9272 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9273 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9274 (use (match_operand:SI 2 "immediate_operand" "i"))
9275 (use (match_operand:SI 3 "immediate_operand" "i"))
9276 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9277 (clobber (reg:SI 6))
9278 (clobber (reg:SI 7))
9279 (clobber (reg:SI 8))
9280 (clobber (match_scratch:SI 5 "X"))]
9281 "TARGET_STRING && ! TARGET_POWER
9282 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9283 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9284 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9285 && REGNO (operands[4]) == 5"
9286 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9287 [(set_attr "type" "load")
9288 (set_attr "length" "8")])
9289
9290 (define_insn ""
9291 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9292 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9293 (use (match_operand:SI 2 "immediate_operand" "i"))
9294 (use (match_operand:SI 3 "immediate_operand" "i"))
9295 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9296 (clobber (reg:SI 6))
9297 (clobber (reg:SI 7))
9298 (clobber (reg:SI 8))
9299 (clobber (match_scratch:SI 5 "X"))]
9300 "TARGET_STRING && TARGET_POWERPC64
9301 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9302 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9303 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9304 && REGNO (operands[4]) == 5"
9305 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9306 [(set_attr "type" "load")
9307 (set_attr "length" "8")])
9308
9309 ;; Move up to 8 bytes at a time.
9310 (define_expand "movmemsi_2reg"
9311 [(parallel [(set (match_operand 0 "" "")
9312 (match_operand 1 "" ""))
9313 (use (match_operand 2 "" ""))
9314 (use (match_operand 3 "" ""))
9315 (clobber (match_scratch:DI 4 ""))
9316 (clobber (match_scratch:SI 5 ""))])]
9317 "TARGET_STRING && ! TARGET_POWERPC64"
9318 "")
9319
9320 (define_insn ""
9321 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9322 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9323 (use (match_operand:SI 2 "immediate_operand" "i"))
9324 (use (match_operand:SI 3 "immediate_operand" "i"))
9325 (clobber (match_scratch:DI 4 "=&r"))
9326 (clobber (match_scratch:SI 5 "=q"))]
9327 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9328 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9329 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9330 [(set_attr "type" "load")
9331 (set_attr "length" "8")])
9332
9333 (define_insn ""
9334 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9335 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9336 (use (match_operand:SI 2 "immediate_operand" "i"))
9337 (use (match_operand:SI 3 "immediate_operand" "i"))
9338 (clobber (match_scratch:DI 4 "=&r"))
9339 (clobber (match_scratch:SI 5 "X"))]
9340 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9341 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9342 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9343 [(set_attr "type" "load")
9344 (set_attr "length" "8")])
9345
9346 ;; Move up to 4 bytes at a time.
9347 (define_expand "movmemsi_1reg"
9348 [(parallel [(set (match_operand 0 "" "")
9349 (match_operand 1 "" ""))
9350 (use (match_operand 2 "" ""))
9351 (use (match_operand 3 "" ""))
9352 (clobber (match_scratch:SI 4 ""))
9353 (clobber (match_scratch:SI 5 ""))])]
9354 "TARGET_STRING"
9355 "")
9356
9357 (define_insn ""
9358 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9359 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9360 (use (match_operand:SI 2 "immediate_operand" "i"))
9361 (use (match_operand:SI 3 "immediate_operand" "i"))
9362 (clobber (match_scratch:SI 4 "=&r"))
9363 (clobber (match_scratch:SI 5 "=q"))]
9364 "TARGET_STRING && TARGET_POWER
9365 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9366 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9367 [(set_attr "type" "load")
9368 (set_attr "length" "8")])
9369
9370 (define_insn ""
9371 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9372 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9373 (use (match_operand:SI 2 "immediate_operand" "i"))
9374 (use (match_operand:SI 3 "immediate_operand" "i"))
9375 (clobber (match_scratch:SI 4 "=&r"))
9376 (clobber (match_scratch:SI 5 "X"))]
9377 "TARGET_STRING && ! TARGET_POWER
9378 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9379 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9380 [(set_attr "type" "load")
9381 (set_attr "length" "8")])
9382
9383 (define_insn ""
9384 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9385 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9386 (use (match_operand:SI 2 "immediate_operand" "i"))
9387 (use (match_operand:SI 3 "immediate_operand" "i"))
9388 (clobber (match_scratch:SI 4 "=&r"))
9389 (clobber (match_scratch:SI 5 "X"))]
9390 "TARGET_STRING && TARGET_POWERPC64
9391 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9392 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9393 [(set_attr "type" "load")
9394 (set_attr "length" "8")])
9395
9396 \f
9397 ;; Define insns that do load or store with update. Some of these we can
9398 ;; get by using pre-decrement or pre-increment, but the hardware can also
9399 ;; do cases where the increment is not the size of the object.
9400 ;;
9401 ;; In all these cases, we use operands 0 and 1 for the register being
9402 ;; incremented because those are the operands that local-alloc will
9403 ;; tie and these are the pair most likely to be tieable (and the ones
9404 ;; that will benefit the most).
9405
9406 (define_insn "*movdi_update1"
9407 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9408 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9409 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9410 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9411 (plus:DI (match_dup 1) (match_dup 2)))]
9412 "TARGET_POWERPC64 && TARGET_UPDATE"
9413 "@
9414 ldux %3,%0,%2
9415 ldu %3,%2(%0)"
9416 [(set_attr "type" "load_ux,load_u")])
9417
9418 (define_insn "movdi_<mode>_update"
9419 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9420 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9421 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9422 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9423 (plus:P (match_dup 1) (match_dup 2)))]
9424 "TARGET_POWERPC64 && TARGET_UPDATE"
9425 "@
9426 stdux %3,%0,%2
9427 stdu %3,%2(%0)"
9428 [(set_attr "type" "store_ux,store_u")])
9429
9430 (define_insn "*movsi_update1"
9431 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9432 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9433 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9434 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9435 (plus:SI (match_dup 1) (match_dup 2)))]
9436 "TARGET_UPDATE"
9437 "@
9438 {lux|lwzux} %3,%0,%2
9439 {lu|lwzu} %3,%2(%0)"
9440 [(set_attr "type" "load_ux,load_u")])
9441
9442 (define_insn "*movsi_update2"
9443 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9444 (sign_extend:DI
9445 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9446 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9447 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9448 (plus:DI (match_dup 1) (match_dup 2)))]
9449 "TARGET_POWERPC64"
9450 "lwaux %3,%0,%2"
9451 [(set_attr "type" "load_ext_ux")])
9452
9453 (define_insn "movsi_update"
9454 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9455 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9456 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9457 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9458 (plus:SI (match_dup 1) (match_dup 2)))]
9459 "TARGET_UPDATE"
9460 "@
9461 {stux|stwux} %3,%0,%2
9462 {stu|stwu} %3,%2(%0)"
9463 [(set_attr "type" "store_ux,store_u")])
9464
9465 (define_insn "*movhi_update1"
9466 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9467 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9468 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9469 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9470 (plus:SI (match_dup 1) (match_dup 2)))]
9471 "TARGET_UPDATE"
9472 "@
9473 lhzux %3,%0,%2
9474 lhzu %3,%2(%0)"
9475 [(set_attr "type" "load_ux,load_u")])
9476
9477 (define_insn "*movhi_update2"
9478 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9479 (zero_extend:SI
9480 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9481 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9482 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9483 (plus:SI (match_dup 1) (match_dup 2)))]
9484 "TARGET_UPDATE"
9485 "@
9486 lhzux %3,%0,%2
9487 lhzu %3,%2(%0)"
9488 [(set_attr "type" "load_ux,load_u")])
9489
9490 (define_insn "*movhi_update3"
9491 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9492 (sign_extend:SI
9493 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9494 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9495 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9496 (plus:SI (match_dup 1) (match_dup 2)))]
9497 "TARGET_UPDATE"
9498 "@
9499 lhaux %3,%0,%2
9500 lhau %3,%2(%0)"
9501 [(set_attr "type" "load_ext_ux,load_ext_u")])
9502
9503 (define_insn "*movhi_update4"
9504 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9505 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9506 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9507 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9508 (plus:SI (match_dup 1) (match_dup 2)))]
9509 "TARGET_UPDATE"
9510 "@
9511 sthux %3,%0,%2
9512 sthu %3,%2(%0)"
9513 [(set_attr "type" "store_ux,store_u")])
9514
9515 (define_insn "*movqi_update1"
9516 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9517 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9518 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9519 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9520 (plus:SI (match_dup 1) (match_dup 2)))]
9521 "TARGET_UPDATE"
9522 "@
9523 lbzux %3,%0,%2
9524 lbzu %3,%2(%0)"
9525 [(set_attr "type" "load_ux,load_u")])
9526
9527 (define_insn "*movqi_update2"
9528 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9529 (zero_extend:SI
9530 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9531 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9532 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9533 (plus:SI (match_dup 1) (match_dup 2)))]
9534 "TARGET_UPDATE"
9535 "@
9536 lbzux %3,%0,%2
9537 lbzu %3,%2(%0)"
9538 [(set_attr "type" "load_ux,load_u")])
9539
9540 (define_insn "*movqi_update3"
9541 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9542 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9543 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9544 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9545 (plus:SI (match_dup 1) (match_dup 2)))]
9546 "TARGET_UPDATE"
9547 "@
9548 stbux %3,%0,%2
9549 stbu %3,%2(%0)"
9550 [(set_attr "type" "store_ux,store_u")])
9551
9552 (define_insn "*movsf_update1"
9553 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9554 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9555 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9556 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9557 (plus:SI (match_dup 1) (match_dup 2)))]
9558 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9559 "@
9560 lfsux %3,%0,%2
9561 lfsu %3,%2(%0)"
9562 [(set_attr "type" "fpload_ux,fpload_u")])
9563
9564 (define_insn "*movsf_update2"
9565 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9566 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9567 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9568 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9569 (plus:SI (match_dup 1) (match_dup 2)))]
9570 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9571 "@
9572 stfsux %3,%0,%2
9573 stfsu %3,%2(%0)"
9574 [(set_attr "type" "fpstore_ux,fpstore_u")])
9575
9576 (define_insn "*movsf_update3"
9577 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9578 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9579 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9580 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9581 (plus:SI (match_dup 1) (match_dup 2)))]
9582 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9583 "@
9584 {lux|lwzux} %3,%0,%2
9585 {lu|lwzu} %3,%2(%0)"
9586 [(set_attr "type" "load_ux,load_u")])
9587
9588 (define_insn "*movsf_update4"
9589 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9590 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9591 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9592 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9593 (plus:SI (match_dup 1) (match_dup 2)))]
9594 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9595 "@
9596 {stux|stwux} %3,%0,%2
9597 {stu|stwu} %3,%2(%0)"
9598 [(set_attr "type" "store_ux,store_u")])
9599
9600 (define_insn "*movdf_update1"
9601 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9602 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9603 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9604 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9605 (plus:SI (match_dup 1) (match_dup 2)))]
9606 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9607 "@
9608 lfdux %3,%0,%2
9609 lfdu %3,%2(%0)"
9610 [(set_attr "type" "fpload_ux,fpload_u")])
9611
9612 (define_insn "*movdf_update2"
9613 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9614 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9615 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9616 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9617 (plus:SI (match_dup 1) (match_dup 2)))]
9618 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9619 "@
9620 stfdux %3,%0,%2
9621 stfdu %3,%2(%0)"
9622 [(set_attr "type" "fpstore_ux,fpstore_u")])
9623
9624 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9625
9626 (define_insn "*lfq_power2"
9627 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9628 (match_operand:TF 1 "memory_operand" ""))]
9629 "TARGET_POWER2
9630 && TARGET_HARD_FLOAT && TARGET_FPRS"
9631 "lfq%U1%X1 %0,%1")
9632
9633 (define_peephole2
9634 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9635 (match_operand:DF 1 "memory_operand" ""))
9636 (set (match_operand:DF 2 "gpc_reg_operand" "")
9637 (match_operand:DF 3 "memory_operand" ""))]
9638 "TARGET_POWER2
9639 && TARGET_HARD_FLOAT && TARGET_FPRS
9640 && registers_ok_for_quad_peep (operands[0], operands[2])
9641 && mems_ok_for_quad_peep (operands[1], operands[3])"
9642 [(set (match_dup 0)
9643 (match_dup 1))]
9644 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9645 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9646
9647 (define_insn "*stfq_power2"
9648 [(set (match_operand:TF 0 "memory_operand" "")
9649 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9650 "TARGET_POWER2
9651 && TARGET_HARD_FLOAT && TARGET_FPRS"
9652 "stfq%U0%X0 %1,%0")
9653
9654
9655 (define_peephole2
9656 [(set (match_operand:DF 0 "memory_operand" "")
9657 (match_operand:DF 1 "gpc_reg_operand" ""))
9658 (set (match_operand:DF 2 "memory_operand" "")
9659 (match_operand:DF 3 "gpc_reg_operand" ""))]
9660 "TARGET_POWER2
9661 && TARGET_HARD_FLOAT && TARGET_FPRS
9662 && registers_ok_for_quad_peep (operands[1], operands[3])
9663 && mems_ok_for_quad_peep (operands[0], operands[2])"
9664 [(set (match_dup 0)
9665 (match_dup 1))]
9666 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9667 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9668
9669 ;; after inserting conditional returns we can sometimes have
9670 ;; unnecessary register moves. Unfortunately we cannot have a
9671 ;; modeless peephole here, because some single SImode sets have early
9672 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9673 ;; sequences, using get_attr_length here will smash the operands
9674 ;; array. Neither is there an early_cobbler_p predicate.
9675 (define_peephole2
9676 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9677 (match_operand:DF 1 "any_operand" ""))
9678 (set (match_operand:DF 2 "gpc_reg_operand" "")
9679 (match_dup 0))]
9680 "peep2_reg_dead_p (2, operands[0])"
9681 [(set (match_dup 2) (match_dup 1))])
9682
9683 (define_peephole2
9684 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9685 (match_operand:SF 1 "any_operand" ""))
9686 (set (match_operand:SF 2 "gpc_reg_operand" "")
9687 (match_dup 0))]
9688 "peep2_reg_dead_p (2, operands[0])"
9689 [(set (match_dup 2) (match_dup 1))])
9690
9691 \f
9692 ;; TLS support.
9693
9694 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9695 (define_insn "tls_gd_32"
9696 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9697 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9698 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9699 UNSPEC_TLSGD))]
9700 "HAVE_AS_TLS && !TARGET_64BIT"
9701 "addi %0,%1,%2@got@tlsgd")
9702
9703 (define_insn "tls_gd_64"
9704 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9705 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9706 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9707 UNSPEC_TLSGD))]
9708 "HAVE_AS_TLS && TARGET_64BIT"
9709 "addi %0,%1,%2@got@tlsgd")
9710
9711 (define_insn "tls_ld_32"
9712 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9713 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9714 UNSPEC_TLSLD))]
9715 "HAVE_AS_TLS && !TARGET_64BIT"
9716 "addi %0,%1,%&@got@tlsld")
9717
9718 (define_insn "tls_ld_64"
9719 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9720 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9721 UNSPEC_TLSLD))]
9722 "HAVE_AS_TLS && TARGET_64BIT"
9723 "addi %0,%1,%&@got@tlsld")
9724
9725 (define_insn "tls_dtprel_32"
9726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9727 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9728 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9729 UNSPEC_TLSDTPREL))]
9730 "HAVE_AS_TLS && !TARGET_64BIT"
9731 "addi %0,%1,%2@dtprel")
9732
9733 (define_insn "tls_dtprel_64"
9734 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9735 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9736 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9737 UNSPEC_TLSDTPREL))]
9738 "HAVE_AS_TLS && TARGET_64BIT"
9739 "addi %0,%1,%2@dtprel")
9740
9741 (define_insn "tls_dtprel_ha_32"
9742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9743 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9744 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9745 UNSPEC_TLSDTPRELHA))]
9746 "HAVE_AS_TLS && !TARGET_64BIT"
9747 "addis %0,%1,%2@dtprel@ha")
9748
9749 (define_insn "tls_dtprel_ha_64"
9750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9751 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9752 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9753 UNSPEC_TLSDTPRELHA))]
9754 "HAVE_AS_TLS && TARGET_64BIT"
9755 "addis %0,%1,%2@dtprel@ha")
9756
9757 (define_insn "tls_dtprel_lo_32"
9758 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9759 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9760 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9761 UNSPEC_TLSDTPRELLO))]
9762 "HAVE_AS_TLS && !TARGET_64BIT"
9763 "addi %0,%1,%2@dtprel@l")
9764
9765 (define_insn "tls_dtprel_lo_64"
9766 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9767 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9768 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9769 UNSPEC_TLSDTPRELLO))]
9770 "HAVE_AS_TLS && TARGET_64BIT"
9771 "addi %0,%1,%2@dtprel@l")
9772
9773 (define_insn "tls_got_dtprel_32"
9774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9775 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9776 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9777 UNSPEC_TLSGOTDTPREL))]
9778 "HAVE_AS_TLS && !TARGET_64BIT"
9779 "lwz %0,%2@got@dtprel(%1)")
9780
9781 (define_insn "tls_got_dtprel_64"
9782 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9783 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9784 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9785 UNSPEC_TLSGOTDTPREL))]
9786 "HAVE_AS_TLS && TARGET_64BIT"
9787 "ld %0,%2@got@dtprel(%1)")
9788
9789 (define_insn "tls_tprel_32"
9790 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9791 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9792 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9793 UNSPEC_TLSTPREL))]
9794 "HAVE_AS_TLS && !TARGET_64BIT"
9795 "addi %0,%1,%2@tprel")
9796
9797 (define_insn "tls_tprel_64"
9798 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9799 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9800 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9801 UNSPEC_TLSTPREL))]
9802 "HAVE_AS_TLS && TARGET_64BIT"
9803 "addi %0,%1,%2@tprel")
9804
9805 (define_insn "tls_tprel_ha_32"
9806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9807 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9808 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9809 UNSPEC_TLSTPRELHA))]
9810 "HAVE_AS_TLS && !TARGET_64BIT"
9811 "addis %0,%1,%2@tprel@ha")
9812
9813 (define_insn "tls_tprel_ha_64"
9814 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9815 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9816 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9817 UNSPEC_TLSTPRELHA))]
9818 "HAVE_AS_TLS && TARGET_64BIT"
9819 "addis %0,%1,%2@tprel@ha")
9820
9821 (define_insn "tls_tprel_lo_32"
9822 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9823 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9824 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9825 UNSPEC_TLSTPRELLO))]
9826 "HAVE_AS_TLS && !TARGET_64BIT"
9827 "addi %0,%1,%2@tprel@l")
9828
9829 (define_insn "tls_tprel_lo_64"
9830 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9831 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9832 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9833 UNSPEC_TLSTPRELLO))]
9834 "HAVE_AS_TLS && TARGET_64BIT"
9835 "addi %0,%1,%2@tprel@l")
9836
9837 ;; "b" output constraint here and on tls_tls input to support linker tls
9838 ;; optimization. The linker may edit the instructions emitted by a
9839 ;; tls_got_tprel/tls_tls pair to addis,addi.
9840 (define_insn "tls_got_tprel_32"
9841 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9842 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9843 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9844 UNSPEC_TLSGOTTPREL))]
9845 "HAVE_AS_TLS && !TARGET_64BIT"
9846 "lwz %0,%2@got@tprel(%1)")
9847
9848 (define_insn "tls_got_tprel_64"
9849 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9850 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9851 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9852 UNSPEC_TLSGOTTPREL))]
9853 "HAVE_AS_TLS && TARGET_64BIT"
9854 "ld %0,%2@got@tprel(%1)")
9855
9856 (define_insn "tls_tls_32"
9857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9858 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9859 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9860 UNSPEC_TLSTLS))]
9861 "HAVE_AS_TLS && !TARGET_64BIT"
9862 "add %0,%1,%2@tls")
9863
9864 (define_insn "tls_tls_64"
9865 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9866 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9867 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9868 UNSPEC_TLSTLS))]
9869 "HAVE_AS_TLS && TARGET_64BIT"
9870 "add %0,%1,%2@tls")
9871 \f
9872 ;; Next come insns related to the calling sequence.
9873 ;;
9874 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9875 ;; We move the back-chain and decrement the stack pointer.
9876
9877 (define_expand "allocate_stack"
9878 [(set (match_operand 0 "gpc_reg_operand" "=r")
9879 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9880 (set (reg 1)
9881 (minus (reg 1) (match_dup 1)))]
9882 ""
9883 "
9884 { rtx chain = gen_reg_rtx (Pmode);
9885 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9886 rtx neg_op0;
9887
9888 emit_move_insn (chain, stack_bot);
9889
9890 /* Check stack bounds if necessary. */
9891 if (current_function_limit_stack)
9892 {
9893 rtx available;
9894 available = expand_binop (Pmode, sub_optab,
9895 stack_pointer_rtx, stack_limit_rtx,
9896 NULL_RTX, 1, OPTAB_WIDEN);
9897 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9898 }
9899
9900 if (GET_CODE (operands[1]) != CONST_INT
9901 || INTVAL (operands[1]) < -32767
9902 || INTVAL (operands[1]) > 32768)
9903 {
9904 neg_op0 = gen_reg_rtx (Pmode);
9905 if (TARGET_32BIT)
9906 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9907 else
9908 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9909 }
9910 else
9911 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9912
9913 if (TARGET_UPDATE)
9914 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9915 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9916
9917 else
9918 {
9919 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9920 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9921 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9922 }
9923
9924 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9925 DONE;
9926 }")
9927
9928 ;; These patterns say how to save and restore the stack pointer. We need not
9929 ;; save the stack pointer at function level since we are careful to
9930 ;; preserve the backchain. At block level, we have to restore the backchain
9931 ;; when we restore the stack pointer.
9932 ;;
9933 ;; For nonlocal gotos, we must save both the stack pointer and its
9934 ;; backchain and restore both. Note that in the nonlocal case, the
9935 ;; save area is a memory location.
9936
9937 (define_expand "save_stack_function"
9938 [(match_operand 0 "any_operand" "")
9939 (match_operand 1 "any_operand" "")]
9940 ""
9941 "DONE;")
9942
9943 (define_expand "restore_stack_function"
9944 [(match_operand 0 "any_operand" "")
9945 (match_operand 1 "any_operand" "")]
9946 ""
9947 "DONE;")
9948
9949 (define_expand "restore_stack_block"
9950 [(use (match_operand 0 "register_operand" ""))
9951 (set (match_dup 2) (match_dup 3))
9952 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9953 (set (match_dup 3) (match_dup 2))]
9954 ""
9955 "
9956 {
9957 operands[2] = gen_reg_rtx (Pmode);
9958 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9959 }")
9960
9961 (define_expand "save_stack_nonlocal"
9962 [(match_operand 0 "memory_operand" "")
9963 (match_operand 1 "register_operand" "")]
9964 ""
9965 "
9966 {
9967 rtx temp = gen_reg_rtx (Pmode);
9968 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9969
9970 /* Copy the backchain to the first word, sp to the second. */
9971 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9972 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9973 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9974 operands[1]);
9975 DONE;
9976 }")
9977
9978 (define_expand "restore_stack_nonlocal"
9979 [(match_operand 0 "register_operand" "")
9980 (match_operand 1 "memory_operand" "")]
9981 ""
9982 "
9983 {
9984 rtx temp = gen_reg_rtx (Pmode);
9985 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9986
9987 /* Restore the backchain from the first word, sp from the second. */
9988 emit_move_insn (temp,
9989 adjust_address_nv (operands[1], Pmode, 0));
9990 emit_move_insn (operands[0],
9991 adjust_address_nv (operands[1], Pmode, units_per_word));
9992 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9993 DONE;
9994 }")
9995 \f
9996 ;; TOC register handling.
9997
9998 ;; Code to initialize the TOC register...
9999
10000 (define_insn "load_toc_aix_si"
10001 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10002 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10003 (use (reg:SI 2))])]
10004 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10005 "*
10006 {
10007 char buf[30];
10008 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10009 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10010 operands[2] = gen_rtx_REG (Pmode, 2);
10011 return \"{l|lwz} %0,%1(%2)\";
10012 }"
10013 [(set_attr "type" "load")])
10014
10015 (define_insn "load_toc_aix_di"
10016 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10017 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10018 (use (reg:DI 2))])]
10019 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10020 "*
10021 {
10022 char buf[30];
10023 #ifdef TARGET_RELOCATABLE
10024 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10025 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10026 #else
10027 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10028 #endif
10029 if (TARGET_ELF)
10030 strcat (buf, \"@toc\");
10031 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10032 operands[2] = gen_rtx_REG (Pmode, 2);
10033 return \"ld %0,%1(%2)\";
10034 }"
10035 [(set_attr "type" "load")])
10036
10037 (define_insn "load_toc_v4_pic_si"
10038 [(set (match_operand:SI 0 "register_operand" "=l")
10039 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10040 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10041 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10042 [(set_attr "type" "branch")
10043 (set_attr "length" "4")])
10044
10045 (define_insn "load_toc_v4_PIC_1"
10046 [(set (match_operand:SI 0 "register_operand" "=l")
10047 (match_operand:SI 1 "immediate_operand" "s"))
10048 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10049 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10050 "bcl 20,31,%1\\n%1:"
10051 [(set_attr "type" "branch")
10052 (set_attr "length" "4")])
10053
10054 (define_insn "load_toc_v4_PIC_1b"
10055 [(set (match_operand:SI 0 "register_operand" "=l")
10056 (match_operand:SI 1 "immediate_operand" "s"))
10057 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10058 UNSPEC_TOCPTR))]
10059 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10060 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
10061 [(set_attr "type" "branch")
10062 (set_attr "length" "8")])
10063
10064 (define_insn "load_toc_v4_PIC_2"
10065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10066 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10067 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10068 (match_operand:SI 3 "immediate_operand" "s")))))]
10069 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10070 "{l|lwz} %0,%2-%3(%1)"
10071 [(set_attr "type" "load")])
10072
10073
10074 ;; If the TOC is shared over a translation unit, as happens with all
10075 ;; the kinds of PIC that we support, we need to restore the TOC
10076 ;; pointer only when jumping over units of translation.
10077 ;; On Darwin, we need to reload the picbase.
10078
10079 (define_expand "builtin_setjmp_receiver"
10080 [(use (label_ref (match_operand 0 "" "")))]
10081 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10082 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10083 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10084 "
10085 {
10086 #if TARGET_MACHO
10087 if (DEFAULT_ABI == ABI_DARWIN)
10088 {
10089 const char *picbase = machopic_function_base_name ();
10090 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10091 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10092 rtx tmplabrtx;
10093 char tmplab[20];
10094
10095 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10096 CODE_LABEL_NUMBER (operands[0]));
10097 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10098
10099 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10100 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10101 }
10102 else
10103 #endif
10104 rs6000_emit_load_toc_table (FALSE);
10105 DONE;
10106 }")
10107 \f
10108 ;; A function pointer under AIX is a pointer to a data area whose first word
10109 ;; contains the actual address of the function, whose second word contains a
10110 ;; pointer to its TOC, and whose third word contains a value to place in the
10111 ;; static chain register (r11). Note that if we load the static chain, our
10112 ;; "trampoline" need not have any executable code.
10113
10114 (define_expand "call_indirect_aix32"
10115 [(set (match_dup 2)
10116 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10117 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10118 (reg:SI 2))
10119 (set (reg:SI 2)
10120 (mem:SI (plus:SI (match_dup 0)
10121 (const_int 4))))
10122 (set (reg:SI 11)
10123 (mem:SI (plus:SI (match_dup 0)
10124 (const_int 8))))
10125 (parallel [(call (mem:SI (match_dup 2))
10126 (match_operand 1 "" ""))
10127 (use (reg:SI 2))
10128 (use (reg:SI 11))
10129 (set (reg:SI 2)
10130 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10131 (clobber (scratch:SI))])]
10132 "TARGET_32BIT"
10133 "
10134 { operands[2] = gen_reg_rtx (SImode); }")
10135
10136 (define_expand "call_indirect_aix64"
10137 [(set (match_dup 2)
10138 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10139 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10140 (reg:DI 2))
10141 (set (reg:DI 2)
10142 (mem:DI (plus:DI (match_dup 0)
10143 (const_int 8))))
10144 (set (reg:DI 11)
10145 (mem:DI (plus:DI (match_dup 0)
10146 (const_int 16))))
10147 (parallel [(call (mem:SI (match_dup 2))
10148 (match_operand 1 "" ""))
10149 (use (reg:DI 2))
10150 (use (reg:DI 11))
10151 (set (reg:DI 2)
10152 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10153 (clobber (scratch:SI))])]
10154 "TARGET_64BIT"
10155 "
10156 { operands[2] = gen_reg_rtx (DImode); }")
10157
10158 (define_expand "call_value_indirect_aix32"
10159 [(set (match_dup 3)
10160 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10161 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10162 (reg:SI 2))
10163 (set (reg:SI 2)
10164 (mem:SI (plus:SI (match_dup 1)
10165 (const_int 4))))
10166 (set (reg:SI 11)
10167 (mem:SI (plus:SI (match_dup 1)
10168 (const_int 8))))
10169 (parallel [(set (match_operand 0 "" "")
10170 (call (mem:SI (match_dup 3))
10171 (match_operand 2 "" "")))
10172 (use (reg:SI 2))
10173 (use (reg:SI 11))
10174 (set (reg:SI 2)
10175 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10176 (clobber (scratch:SI))])]
10177 "TARGET_32BIT"
10178 "
10179 { operands[3] = gen_reg_rtx (SImode); }")
10180
10181 (define_expand "call_value_indirect_aix64"
10182 [(set (match_dup 3)
10183 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10184 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10185 (reg:DI 2))
10186 (set (reg:DI 2)
10187 (mem:DI (plus:DI (match_dup 1)
10188 (const_int 8))))
10189 (set (reg:DI 11)
10190 (mem:DI (plus:DI (match_dup 1)
10191 (const_int 16))))
10192 (parallel [(set (match_operand 0 "" "")
10193 (call (mem:SI (match_dup 3))
10194 (match_operand 2 "" "")))
10195 (use (reg:DI 2))
10196 (use (reg:DI 11))
10197 (set (reg:DI 2)
10198 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10199 (clobber (scratch:SI))])]
10200 "TARGET_64BIT"
10201 "
10202 { operands[3] = gen_reg_rtx (DImode); }")
10203
10204 ;; Now the definitions for the call and call_value insns
10205 (define_expand "call"
10206 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10207 (match_operand 1 "" ""))
10208 (use (match_operand 2 "" ""))
10209 (clobber (scratch:SI))])]
10210 ""
10211 "
10212 {
10213 #if TARGET_MACHO
10214 if (MACHOPIC_INDIRECT)
10215 operands[0] = machopic_indirect_call_target (operands[0]);
10216 #endif
10217
10218 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10219 abort ();
10220
10221 operands[0] = XEXP (operands[0], 0);
10222
10223 if (GET_CODE (operands[0]) != SYMBOL_REF
10224 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10225 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10226 {
10227 if (INTVAL (operands[2]) & CALL_LONG)
10228 operands[0] = rs6000_longcall_ref (operands[0]);
10229
10230 if (DEFAULT_ABI == ABI_V4
10231 || DEFAULT_ABI == ABI_DARWIN)
10232 operands[0] = force_reg (Pmode, operands[0]);
10233
10234 else if (DEFAULT_ABI == ABI_AIX)
10235 {
10236 /* AIX function pointers are really pointers to a three word
10237 area. */
10238 emit_call_insn (TARGET_32BIT
10239 ? gen_call_indirect_aix32 (force_reg (SImode,
10240 operands[0]),
10241 operands[1])
10242 : gen_call_indirect_aix64 (force_reg (DImode,
10243 operands[0]),
10244 operands[1]));
10245 DONE;
10246 }
10247 else
10248 abort ();
10249 }
10250 }")
10251
10252 (define_expand "call_value"
10253 [(parallel [(set (match_operand 0 "" "")
10254 (call (mem:SI (match_operand 1 "address_operand" ""))
10255 (match_operand 2 "" "")))
10256 (use (match_operand 3 "" ""))
10257 (clobber (scratch:SI))])]
10258 ""
10259 "
10260 {
10261 #if TARGET_MACHO
10262 if (MACHOPIC_INDIRECT)
10263 operands[1] = machopic_indirect_call_target (operands[1]);
10264 #endif
10265
10266 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10267 abort ();
10268
10269 operands[1] = XEXP (operands[1], 0);
10270
10271 if (GET_CODE (operands[1]) != SYMBOL_REF
10272 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10273 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10274 {
10275 if (INTVAL (operands[3]) & CALL_LONG)
10276 operands[1] = rs6000_longcall_ref (operands[1]);
10277
10278 if (DEFAULT_ABI == ABI_V4
10279 || DEFAULT_ABI == ABI_DARWIN)
10280 operands[1] = force_reg (Pmode, operands[1]);
10281
10282 else if (DEFAULT_ABI == ABI_AIX)
10283 {
10284 /* AIX function pointers are really pointers to a three word
10285 area. */
10286 emit_call_insn (TARGET_32BIT
10287 ? gen_call_value_indirect_aix32 (operands[0],
10288 force_reg (SImode,
10289 operands[1]),
10290 operands[2])
10291 : gen_call_value_indirect_aix64 (operands[0],
10292 force_reg (DImode,
10293 operands[1]),
10294 operands[2]));
10295 DONE;
10296 }
10297 else
10298 abort ();
10299 }
10300 }")
10301
10302 ;; Call to function in current module. No TOC pointer reload needed.
10303 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10304 ;; either the function was not prototyped, or it was prototyped as a
10305 ;; variable argument function. It is > 0 if FP registers were passed
10306 ;; and < 0 if they were not.
10307
10308 (define_insn "*call_local32"
10309 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10310 (match_operand 1 "" "g,g"))
10311 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10312 (clobber (match_scratch:SI 3 "=l,l"))]
10313 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10314 "*
10315 {
10316 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10317 output_asm_insn (\"crxor 6,6,6\", operands);
10318
10319 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10320 output_asm_insn (\"creqv 6,6,6\", operands);
10321
10322 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10323 }"
10324 [(set_attr "type" "branch")
10325 (set_attr "length" "4,8")])
10326
10327 (define_insn "*call_local64"
10328 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10329 (match_operand 1 "" "g,g"))
10330 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10331 (clobber (match_scratch:SI 3 "=l,l"))]
10332 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10333 "*
10334 {
10335 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10336 output_asm_insn (\"crxor 6,6,6\", operands);
10337
10338 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10339 output_asm_insn (\"creqv 6,6,6\", operands);
10340
10341 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10342 }"
10343 [(set_attr "type" "branch")
10344 (set_attr "length" "4,8")])
10345
10346 (define_insn "*call_value_local32"
10347 [(set (match_operand 0 "" "")
10348 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10349 (match_operand 2 "" "g,g")))
10350 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10351 (clobber (match_scratch:SI 4 "=l,l"))]
10352 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10353 "*
10354 {
10355 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10356 output_asm_insn (\"crxor 6,6,6\", operands);
10357
10358 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10359 output_asm_insn (\"creqv 6,6,6\", operands);
10360
10361 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10362 }"
10363 [(set_attr "type" "branch")
10364 (set_attr "length" "4,8")])
10365
10366
10367 (define_insn "*call_value_local64"
10368 [(set (match_operand 0 "" "")
10369 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10370 (match_operand 2 "" "g,g")))
10371 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10372 (clobber (match_scratch:SI 4 "=l,l"))]
10373 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10374 "*
10375 {
10376 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10377 output_asm_insn (\"crxor 6,6,6\", operands);
10378
10379 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10380 output_asm_insn (\"creqv 6,6,6\", operands);
10381
10382 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10383 }"
10384 [(set_attr "type" "branch")
10385 (set_attr "length" "4,8")])
10386
10387 ;; Call to function which may be in another module. Restore the TOC
10388 ;; pointer (r2) after the call unless this is System V.
10389 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10390 ;; either the function was not prototyped, or it was prototyped as a
10391 ;; variable argument function. It is > 0 if FP registers were passed
10392 ;; and < 0 if they were not.
10393
10394 (define_insn "*call_indirect_nonlocal_aix32"
10395 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10396 (match_operand 1 "" "g"))
10397 (use (reg:SI 2))
10398 (use (reg:SI 11))
10399 (set (reg:SI 2)
10400 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10401 (clobber (match_scratch:SI 2 "=l"))]
10402 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10403 "b%T0l\;{l|lwz} 2,20(1)"
10404 [(set_attr "type" "jmpreg")
10405 (set_attr "length" "8")])
10406
10407 (define_insn "*call_nonlocal_aix32"
10408 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10409 (match_operand 1 "" "g"))
10410 (use (match_operand:SI 2 "immediate_operand" "O"))
10411 (clobber (match_scratch:SI 3 "=l"))]
10412 "TARGET_32BIT
10413 && DEFAULT_ABI == ABI_AIX
10414 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10415 "bl %z0\;%."
10416 [(set_attr "type" "branch")
10417 (set_attr "length" "8")])
10418
10419 (define_insn "*call_indirect_nonlocal_aix64"
10420 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10421 (match_operand 1 "" "g"))
10422 (use (reg:DI 2))
10423 (use (reg:DI 11))
10424 (set (reg:DI 2)
10425 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10426 (clobber (match_scratch:SI 2 "=l"))]
10427 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10428 "b%T0l\;ld 2,40(1)"
10429 [(set_attr "type" "jmpreg")
10430 (set_attr "length" "8")])
10431
10432 (define_insn "*call_nonlocal_aix64"
10433 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10434 (match_operand 1 "" "g"))
10435 (use (match_operand:SI 2 "immediate_operand" "O"))
10436 (clobber (match_scratch:SI 3 "=l"))]
10437 "TARGET_64BIT
10438 && DEFAULT_ABI == ABI_AIX
10439 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10440 "bl %z0\;%."
10441 [(set_attr "type" "branch")
10442 (set_attr "length" "8")])
10443
10444 (define_insn "*call_value_indirect_nonlocal_aix32"
10445 [(set (match_operand 0 "" "")
10446 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10447 (match_operand 2 "" "g")))
10448 (use (reg:SI 2))
10449 (use (reg:SI 11))
10450 (set (reg:SI 2)
10451 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10452 (clobber (match_scratch:SI 3 "=l"))]
10453 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10454 "b%T1l\;{l|lwz} 2,20(1)"
10455 [(set_attr "type" "jmpreg")
10456 (set_attr "length" "8")])
10457
10458 (define_insn "*call_value_nonlocal_aix32"
10459 [(set (match_operand 0 "" "")
10460 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10461 (match_operand 2 "" "g")))
10462 (use (match_operand:SI 3 "immediate_operand" "O"))
10463 (clobber (match_scratch:SI 4 "=l"))]
10464 "TARGET_32BIT
10465 && DEFAULT_ABI == ABI_AIX
10466 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10467 "bl %z1\;%."
10468 [(set_attr "type" "branch")
10469 (set_attr "length" "8")])
10470
10471 (define_insn "*call_value_indirect_nonlocal_aix64"
10472 [(set (match_operand 0 "" "")
10473 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10474 (match_operand 2 "" "g")))
10475 (use (reg:DI 2))
10476 (use (reg:DI 11))
10477 (set (reg:DI 2)
10478 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10479 (clobber (match_scratch:SI 3 "=l"))]
10480 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10481 "b%T1l\;ld 2,40(1)"
10482 [(set_attr "type" "jmpreg")
10483 (set_attr "length" "8")])
10484
10485 (define_insn "*call_value_nonlocal_aix64"
10486 [(set (match_operand 0 "" "")
10487 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10488 (match_operand 2 "" "g")))
10489 (use (match_operand:SI 3 "immediate_operand" "O"))
10490 (clobber (match_scratch:SI 4 "=l"))]
10491 "TARGET_64BIT
10492 && DEFAULT_ABI == ABI_AIX
10493 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10494 "bl %z1\;%."
10495 [(set_attr "type" "branch")
10496 (set_attr "length" "8")])
10497
10498 ;; A function pointer under System V is just a normal pointer
10499 ;; operands[0] is the function pointer
10500 ;; operands[1] is the stack size to clean up
10501 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10502 ;; which indicates how to set cr1
10503
10504 (define_insn "*call_indirect_nonlocal_sysv"
10505 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10506 (match_operand 1 "" "g,g"))
10507 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10508 (clobber (match_scratch:SI 3 "=l,l"))]
10509 "DEFAULT_ABI == ABI_V4
10510 || DEFAULT_ABI == ABI_DARWIN"
10511 {
10512 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10513 output_asm_insn ("crxor 6,6,6", operands);
10514
10515 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10516 output_asm_insn ("creqv 6,6,6", operands);
10517
10518 return "b%T0l";
10519 }
10520 [(set_attr "type" "jmpreg,jmpreg")
10521 (set_attr "length" "4,8")])
10522
10523 (define_insn "*call_nonlocal_sysv"
10524 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10525 (match_operand 1 "" "g,g"))
10526 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10527 (clobber (match_scratch:SI 3 "=l,l"))]
10528 "(DEFAULT_ABI == ABI_DARWIN
10529 || (DEFAULT_ABI == ABI_V4
10530 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10531 {
10532 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10533 output_asm_insn ("crxor 6,6,6", operands);
10534
10535 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10536 output_asm_insn ("creqv 6,6,6", operands);
10537
10538 #if TARGET_MACHO
10539 return output_call(insn, operands, 0, 2);
10540 #else
10541 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10542 #endif
10543 }
10544 [(set_attr "type" "branch,branch")
10545 (set_attr "length" "4,8")])
10546
10547 (define_insn "*call_value_indirect_nonlocal_sysv"
10548 [(set (match_operand 0 "" "")
10549 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10550 (match_operand 2 "" "g,g")))
10551 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10552 (clobber (match_scratch:SI 4 "=l,l"))]
10553 "DEFAULT_ABI == ABI_V4
10554 || DEFAULT_ABI == ABI_DARWIN"
10555 {
10556 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10557 output_asm_insn ("crxor 6,6,6", operands);
10558
10559 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10560 output_asm_insn ("creqv 6,6,6", operands);
10561
10562 return "b%T1l";
10563 }
10564 [(set_attr "type" "jmpreg,jmpreg")
10565 (set_attr "length" "4,8")])
10566
10567 (define_insn "*call_value_nonlocal_sysv"
10568 [(set (match_operand 0 "" "")
10569 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10570 (match_operand 2 "" "g,g")))
10571 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10572 (clobber (match_scratch:SI 4 "=l,l"))]
10573 "(DEFAULT_ABI == ABI_DARWIN
10574 || (DEFAULT_ABI == ABI_V4
10575 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10576 {
10577 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10578 output_asm_insn ("crxor 6,6,6", operands);
10579
10580 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10581 output_asm_insn ("creqv 6,6,6", operands);
10582
10583 #if TARGET_MACHO
10584 return output_call(insn, operands, 1, 3);
10585 #else
10586 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10587 #endif
10588 }
10589 [(set_attr "type" "branch,branch")
10590 (set_attr "length" "4,8")])
10591
10592 ;; Call subroutine returning any type.
10593 (define_expand "untyped_call"
10594 [(parallel [(call (match_operand 0 "" "")
10595 (const_int 0))
10596 (match_operand 1 "" "")
10597 (match_operand 2 "" "")])]
10598 ""
10599 "
10600 {
10601 int i;
10602
10603 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10604
10605 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10606 {
10607 rtx set = XVECEXP (operands[2], 0, i);
10608 emit_move_insn (SET_DEST (set), SET_SRC (set));
10609 }
10610
10611 /* The optimizer does not know that the call sets the function value
10612 registers we stored in the result block. We avoid problems by
10613 claiming that all hard registers are used and clobbered at this
10614 point. */
10615 emit_insn (gen_blockage ());
10616
10617 DONE;
10618 }")
10619
10620 ;; sibling call patterns
10621 (define_expand "sibcall"
10622 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10623 (match_operand 1 "" ""))
10624 (use (match_operand 2 "" ""))
10625 (use (match_operand 3 "" ""))
10626 (return)])]
10627 ""
10628 "
10629 {
10630 #if TARGET_MACHO
10631 if (MACHOPIC_INDIRECT)
10632 operands[0] = machopic_indirect_call_target (operands[0]);
10633 #endif
10634
10635 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10636 abort ();
10637
10638 operands[0] = XEXP (operands[0], 0);
10639 operands[3] = gen_reg_rtx (SImode);
10640
10641 }")
10642
10643 ;; this and similar patterns must be marked as using LR, otherwise
10644 ;; dataflow will try to delete the store into it. This is true
10645 ;; even when the actual reg to jump to is in CTR, when LR was
10646 ;; saved and restored around the PIC-setting BCL.
10647 (define_insn "*sibcall_local32"
10648 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10649 (match_operand 1 "" "g,g"))
10650 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10651 (use (match_operand:SI 3 "register_operand" "l,l"))
10652 (return)]
10653 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10654 "*
10655 {
10656 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10657 output_asm_insn (\"crxor 6,6,6\", operands);
10658
10659 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10660 output_asm_insn (\"creqv 6,6,6\", operands);
10661
10662 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10663 }"
10664 [(set_attr "type" "branch")
10665 (set_attr "length" "4,8")])
10666
10667 (define_insn "*sibcall_local64"
10668 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10669 (match_operand 1 "" "g,g"))
10670 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10671 (use (match_operand:SI 3 "register_operand" "l,l"))
10672 (return)]
10673 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10674 "*
10675 {
10676 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10677 output_asm_insn (\"crxor 6,6,6\", operands);
10678
10679 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10680 output_asm_insn (\"creqv 6,6,6\", operands);
10681
10682 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10683 }"
10684 [(set_attr "type" "branch")
10685 (set_attr "length" "4,8")])
10686
10687 (define_insn "*sibcall_value_local32"
10688 [(set (match_operand 0 "" "")
10689 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10690 (match_operand 2 "" "g,g")))
10691 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10692 (use (match_operand:SI 4 "register_operand" "l,l"))
10693 (return)]
10694 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10695 "*
10696 {
10697 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10698 output_asm_insn (\"crxor 6,6,6\", operands);
10699
10700 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10701 output_asm_insn (\"creqv 6,6,6\", operands);
10702
10703 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10704 }"
10705 [(set_attr "type" "branch")
10706 (set_attr "length" "4,8")])
10707
10708
10709 (define_insn "*sibcall_value_local64"
10710 [(set (match_operand 0 "" "")
10711 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10712 (match_operand 2 "" "g,g")))
10713 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10714 (use (match_operand:SI 4 "register_operand" "l,l"))
10715 (return)]
10716 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10717 "*
10718 {
10719 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10720 output_asm_insn (\"crxor 6,6,6\", operands);
10721
10722 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10723 output_asm_insn (\"creqv 6,6,6\", operands);
10724
10725 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10726 }"
10727 [(set_attr "type" "branch")
10728 (set_attr "length" "4,8")])
10729
10730 (define_insn "*sibcall_nonlocal_aix32"
10731 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10732 (match_operand 1 "" "g"))
10733 (use (match_operand:SI 2 "immediate_operand" "O"))
10734 (use (match_operand:SI 3 "register_operand" "l"))
10735 (return)]
10736 "TARGET_32BIT
10737 && DEFAULT_ABI == ABI_AIX
10738 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10739 "b %z0"
10740 [(set_attr "type" "branch")
10741 (set_attr "length" "4")])
10742
10743 (define_insn "*sibcall_nonlocal_aix64"
10744 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10745 (match_operand 1 "" "g"))
10746 (use (match_operand:SI 2 "immediate_operand" "O"))
10747 (use (match_operand:SI 3 "register_operand" "l"))
10748 (return)]
10749 "TARGET_64BIT
10750 && DEFAULT_ABI == ABI_AIX
10751 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10752 "b %z0"
10753 [(set_attr "type" "branch")
10754 (set_attr "length" "4")])
10755
10756 (define_insn "*sibcall_value_nonlocal_aix32"
10757 [(set (match_operand 0 "" "")
10758 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10759 (match_operand 2 "" "g")))
10760 (use (match_operand:SI 3 "immediate_operand" "O"))
10761 (use (match_operand:SI 4 "register_operand" "l"))
10762 (return)]
10763 "TARGET_32BIT
10764 && DEFAULT_ABI == ABI_AIX
10765 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10766 "b %z1"
10767 [(set_attr "type" "branch")
10768 (set_attr "length" "4")])
10769
10770 (define_insn "*sibcall_value_nonlocal_aix64"
10771 [(set (match_operand 0 "" "")
10772 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10773 (match_operand 2 "" "g")))
10774 (use (match_operand:SI 3 "immediate_operand" "O"))
10775 (use (match_operand:SI 4 "register_operand" "l"))
10776 (return)]
10777 "TARGET_64BIT
10778 && DEFAULT_ABI == ABI_AIX
10779 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10780 "b %z1"
10781 [(set_attr "type" "branch")
10782 (set_attr "length" "4")])
10783
10784 (define_insn "*sibcall_nonlocal_sysv"
10785 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10786 (match_operand 1 "" ""))
10787 (use (match_operand 2 "immediate_operand" "O,n"))
10788 (use (match_operand:SI 3 "register_operand" "l,l"))
10789 (return)]
10790 "(DEFAULT_ABI == ABI_DARWIN
10791 || DEFAULT_ABI == ABI_V4)
10792 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10793 "*
10794 {
10795 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10796 output_asm_insn (\"crxor 6,6,6\", operands);
10797
10798 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10799 output_asm_insn (\"creqv 6,6,6\", operands);
10800
10801 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10802 }"
10803 [(set_attr "type" "branch,branch")
10804 (set_attr "length" "4,8")])
10805
10806 (define_expand "sibcall_value"
10807 [(parallel [(set (match_operand 0 "register_operand" "")
10808 (call (mem:SI (match_operand 1 "address_operand" ""))
10809 (match_operand 2 "" "")))
10810 (use (match_operand 3 "" ""))
10811 (use (match_operand 4 "" ""))
10812 (return)])]
10813 ""
10814 "
10815 {
10816 #if TARGET_MACHO
10817 if (MACHOPIC_INDIRECT)
10818 operands[1] = machopic_indirect_call_target (operands[1]);
10819 #endif
10820
10821 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10822 abort ();
10823
10824 operands[1] = XEXP (operands[1], 0);
10825 operands[4] = gen_reg_rtx (SImode);
10826
10827 }")
10828
10829 (define_insn "*sibcall_value_nonlocal_sysv"
10830 [(set (match_operand 0 "" "")
10831 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10832 (match_operand 2 "" "")))
10833 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10834 (use (match_operand:SI 4 "register_operand" "l,l"))
10835 (return)]
10836 "(DEFAULT_ABI == ABI_DARWIN
10837 || DEFAULT_ABI == ABI_V4)
10838 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10839 "*
10840 {
10841 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10842 output_asm_insn (\"crxor 6,6,6\", operands);
10843
10844 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10845 output_asm_insn (\"creqv 6,6,6\", operands);
10846
10847 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10848 }"
10849 [(set_attr "type" "branch,branch")
10850 (set_attr "length" "4,8")])
10851
10852 (define_expand "sibcall_epilogue"
10853 [(use (const_int 0))]
10854 "TARGET_SCHED_PROLOG"
10855 "
10856 {
10857 rs6000_emit_epilogue (TRUE);
10858 DONE;
10859 }")
10860
10861 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10862 ;; all of memory. This blocks insns from being moved across this point.
10863
10864 (define_insn "blockage"
10865 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10866 ""
10867 "")
10868 \f
10869 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10870 ;; signed & unsigned, and one type of branch.
10871 ;;
10872 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10873 ;; insns, and branches. We store the operands of compares until we see
10874 ;; how it is used.
10875 (define_expand "cmpsi"
10876 [(set (cc0)
10877 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10878 (match_operand:SI 1 "reg_or_short_operand" "")))]
10879 ""
10880 "
10881 {
10882 /* Take care of the possibility that operands[1] might be negative but
10883 this might be a logical operation. That insn doesn't exist. */
10884 if (GET_CODE (operands[1]) == CONST_INT
10885 && INTVAL (operands[1]) < 0)
10886 operands[1] = force_reg (SImode, operands[1]);
10887
10888 rs6000_compare_op0 = operands[0];
10889 rs6000_compare_op1 = operands[1];
10890 rs6000_compare_fp_p = 0;
10891 DONE;
10892 }")
10893
10894 (define_expand "cmpdi"
10895 [(set (cc0)
10896 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10897 (match_operand:DI 1 "reg_or_short_operand" "")))]
10898 "TARGET_POWERPC64"
10899 "
10900 {
10901 /* Take care of the possibility that operands[1] might be negative but
10902 this might be a logical operation. That insn doesn't exist. */
10903 if (GET_CODE (operands[1]) == CONST_INT
10904 && INTVAL (operands[1]) < 0)
10905 operands[1] = force_reg (DImode, operands[1]);
10906
10907 rs6000_compare_op0 = operands[0];
10908 rs6000_compare_op1 = operands[1];
10909 rs6000_compare_fp_p = 0;
10910 DONE;
10911 }")
10912
10913 (define_expand "cmpsf"
10914 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10915 (match_operand:SF 1 "gpc_reg_operand" "")))]
10916 "TARGET_HARD_FLOAT"
10917 "
10918 {
10919 rs6000_compare_op0 = operands[0];
10920 rs6000_compare_op1 = operands[1];
10921 rs6000_compare_fp_p = 1;
10922 DONE;
10923 }")
10924
10925 (define_expand "cmpdf"
10926 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10927 (match_operand:DF 1 "gpc_reg_operand" "")))]
10928 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
10929 "
10930 {
10931 rs6000_compare_op0 = operands[0];
10932 rs6000_compare_op1 = operands[1];
10933 rs6000_compare_fp_p = 1;
10934 DONE;
10935 }")
10936
10937 (define_expand "cmptf"
10938 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10939 (match_operand:TF 1 "gpc_reg_operand" "")))]
10940 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10941 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10942 "
10943 {
10944 rs6000_compare_op0 = operands[0];
10945 rs6000_compare_op1 = operands[1];
10946 rs6000_compare_fp_p = 1;
10947 DONE;
10948 }")
10949
10950 (define_expand "beq"
10951 [(use (match_operand 0 "" ""))]
10952 ""
10953 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10954
10955 (define_expand "bne"
10956 [(use (match_operand 0 "" ""))]
10957 ""
10958 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10959
10960 (define_expand "bge"
10961 [(use (match_operand 0 "" ""))]
10962 ""
10963 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10964
10965 (define_expand "bgt"
10966 [(use (match_operand 0 "" ""))]
10967 ""
10968 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10969
10970 (define_expand "ble"
10971 [(use (match_operand 0 "" ""))]
10972 ""
10973 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10974
10975 (define_expand "blt"
10976 [(use (match_operand 0 "" ""))]
10977 ""
10978 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10979
10980 (define_expand "bgeu"
10981 [(use (match_operand 0 "" ""))]
10982 ""
10983 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10984
10985 (define_expand "bgtu"
10986 [(use (match_operand 0 "" ""))]
10987 ""
10988 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10989
10990 (define_expand "bleu"
10991 [(use (match_operand 0 "" ""))]
10992 ""
10993 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10994
10995 (define_expand "bltu"
10996 [(use (match_operand 0 "" ""))]
10997 ""
10998 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10999
11000 (define_expand "bunordered"
11001 [(use (match_operand 0 "" ""))]
11002 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11003 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11004
11005 (define_expand "bordered"
11006 [(use (match_operand 0 "" ""))]
11007 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11008 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11009
11010 (define_expand "buneq"
11011 [(use (match_operand 0 "" ""))]
11012 ""
11013 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11014
11015 (define_expand "bunge"
11016 [(use (match_operand 0 "" ""))]
11017 ""
11018 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11019
11020 (define_expand "bungt"
11021 [(use (match_operand 0 "" ""))]
11022 ""
11023 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11024
11025 (define_expand "bunle"
11026 [(use (match_operand 0 "" ""))]
11027 ""
11028 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11029
11030 (define_expand "bunlt"
11031 [(use (match_operand 0 "" ""))]
11032 ""
11033 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11034
11035 (define_expand "bltgt"
11036 [(use (match_operand 0 "" ""))]
11037 ""
11038 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11039
11040 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11041 ;; For SEQ, likewise, except that comparisons with zero should be done
11042 ;; with an scc insns. However, due to the order that combine see the
11043 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11044 ;; the cases we don't want to handle.
11045 (define_expand "seq"
11046 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11047 ""
11048 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11049
11050 (define_expand "sne"
11051 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11052 ""
11053 "
11054 {
11055 if (! rs6000_compare_fp_p)
11056 FAIL;
11057
11058 rs6000_emit_sCOND (NE, operands[0]);
11059 DONE;
11060 }")
11061
11062 ;; A >= 0 is best done the portable way for A an integer.
11063 (define_expand "sge"
11064 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11065 ""
11066 "
11067 {
11068 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11069 FAIL;
11070
11071 rs6000_emit_sCOND (GE, operands[0]);
11072 DONE;
11073 }")
11074
11075 ;; A > 0 is best done using the portable sequence, so fail in that case.
11076 (define_expand "sgt"
11077 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11078 ""
11079 "
11080 {
11081 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11082 FAIL;
11083
11084 rs6000_emit_sCOND (GT, operands[0]);
11085 DONE;
11086 }")
11087
11088 ;; A <= 0 is best done the portable way for A an integer.
11089 (define_expand "sle"
11090 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11091 ""
11092 "
11093 {
11094 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11095 FAIL;
11096
11097 rs6000_emit_sCOND (LE, operands[0]);
11098 DONE;
11099 }")
11100
11101 ;; A < 0 is best done in the portable way for A an integer.
11102 (define_expand "slt"
11103 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11104 ""
11105 "
11106 {
11107 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11108 FAIL;
11109
11110 rs6000_emit_sCOND (LT, operands[0]);
11111 DONE;
11112 }")
11113
11114 (define_expand "sgeu"
11115 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11116 ""
11117 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11118
11119 (define_expand "sgtu"
11120 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11121 ""
11122 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11123
11124 (define_expand "sleu"
11125 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11126 ""
11127 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11128
11129 (define_expand "sltu"
11130 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11131 ""
11132 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11133
11134 (define_expand "sunordered"
11135 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11136 ""
11137 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11138
11139 (define_expand "sordered"
11140 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11141 ""
11142 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11143
11144 (define_expand "suneq"
11145 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11146 ""
11147 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11148
11149 (define_expand "sunge"
11150 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11151 ""
11152 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11153
11154 (define_expand "sungt"
11155 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11156 ""
11157 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11158
11159 (define_expand "sunle"
11160 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11161 ""
11162 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11163
11164 (define_expand "sunlt"
11165 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11166 ""
11167 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11168
11169 (define_expand "sltgt"
11170 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11171 ""
11172 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11173
11174 \f
11175 ;; Here are the actual compare insns.
11176 (define_insn "*cmpsi_internal1"
11177 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11178 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11179 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11180 ""
11181 "{cmp%I2|cmpw%I2} %0,%1,%2"
11182 [(set_attr "type" "cmp")])
11183
11184 (define_insn "*cmpdi_internal1"
11185 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11186 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11187 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11188 "TARGET_POWERPC64"
11189 "cmpd%I2 %0,%1,%2"
11190 [(set_attr "type" "cmp")])
11191
11192 ;; If we are comparing a register for equality with a large constant,
11193 ;; we can do this with an XOR followed by a compare. But we need a scratch
11194 ;; register for the result of the XOR.
11195
11196 (define_split
11197 [(set (match_operand:CC 0 "cc_reg_operand" "")
11198 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11199 (match_operand:SI 2 "non_short_cint_operand" "")))
11200 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11201 "find_single_use (operands[0], insn, 0)
11202 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11203 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11204 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11205 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11206 "
11207 {
11208 /* Get the constant we are comparing against, C, and see what it looks like
11209 sign-extended to 16 bits. Then see what constant could be XOR'ed
11210 with C to get the sign-extended value. */
11211
11212 HOST_WIDE_INT c = INTVAL (operands[2]);
11213 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11214 HOST_WIDE_INT xorv = c ^ sextc;
11215
11216 operands[4] = GEN_INT (xorv);
11217 operands[5] = GEN_INT (sextc);
11218 }")
11219
11220 (define_insn "*cmpsi_internal2"
11221 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11222 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11223 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11224 ""
11225 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11226 [(set_attr "type" "cmp")])
11227
11228 (define_insn "*cmpdi_internal2"
11229 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11230 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11231 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11232 ""
11233 "cmpld%I2 %0,%1,%b2"
11234 [(set_attr "type" "cmp")])
11235
11236 ;; The following two insns don't exist as single insns, but if we provide
11237 ;; them, we can swap an add and compare, which will enable us to overlap more
11238 ;; of the required delay between a compare and branch. We generate code for
11239 ;; them by splitting.
11240
11241 (define_insn ""
11242 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11243 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11244 (match_operand:SI 2 "short_cint_operand" "i")))
11245 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11246 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11247 ""
11248 "#"
11249 [(set_attr "length" "8")])
11250
11251 (define_insn ""
11252 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11253 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11254 (match_operand:SI 2 "u_short_cint_operand" "i")))
11255 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11256 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11257 ""
11258 "#"
11259 [(set_attr "length" "8")])
11260
11261 (define_split
11262 [(set (match_operand:CC 3 "cc_reg_operand" "")
11263 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11264 (match_operand:SI 2 "short_cint_operand" "")))
11265 (set (match_operand:SI 0 "gpc_reg_operand" "")
11266 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11267 ""
11268 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11269 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11270
11271 (define_split
11272 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11273 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11274 (match_operand:SI 2 "u_short_cint_operand" "")))
11275 (set (match_operand:SI 0 "gpc_reg_operand" "")
11276 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11277 ""
11278 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11279 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11280
11281 (define_insn "*cmpsf_internal1"
11282 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11283 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11284 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11285 "TARGET_HARD_FLOAT && TARGET_FPRS"
11286 "fcmpu %0,%1,%2"
11287 [(set_attr "type" "fpcompare")])
11288
11289 (define_insn "*cmpdf_internal1"
11290 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11291 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11292 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11293 "TARGET_HARD_FLOAT && TARGET_FPRS"
11294 "fcmpu %0,%1,%2"
11295 [(set_attr "type" "fpcompare")])
11296
11297 ;; Only need to compare second words if first words equal
11298 (define_insn "*cmptf_internal1"
11299 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11300 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11301 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11302 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11303 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11304 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11305 [(set_attr "type" "fpcompare")
11306 (set_attr "length" "12")])
11307 \f
11308 ;; Now we have the scc insns. We can do some combinations because of the
11309 ;; way the machine works.
11310 ;;
11311 ;; Note that this is probably faster if we can put an insn between the
11312 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11313 ;; cases the insns below which don't use an intermediate CR field will
11314 ;; be used instead.
11315 (define_insn ""
11316 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11317 (match_operator:SI 1 "scc_comparison_operator"
11318 [(match_operand 2 "cc_reg_operand" "y")
11319 (const_int 0)]))]
11320 ""
11321 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11322 [(set (attr "type")
11323 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11324 (const_string "mfcrf")
11325 ]
11326 (const_string "mfcr")))
11327 (set_attr "length" "8")])
11328
11329 ;; Same as above, but get the GT bit.
11330 (define_insn "move_from_CR_eq_bit"
11331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11332 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
11333 "TARGET_E500"
11334 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
11335 [(set_attr "type" "mfcr")
11336 (set_attr "length" "8")])
11337
11338 ;; Same as above, but get the OV/ORDERED bit.
11339 (define_insn "move_from_CR_ov_bit"
11340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11341 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11342 "TARGET_ISEL"
11343 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11344 [(set_attr "type" "mfcr")
11345 (set_attr "length" "8")])
11346
11347 (define_insn ""
11348 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11349 (match_operator:DI 1 "scc_comparison_operator"
11350 [(match_operand 2 "cc_reg_operand" "y")
11351 (const_int 0)]))]
11352 "TARGET_POWERPC64"
11353 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11354 [(set (attr "type")
11355 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11356 (const_string "mfcrf")
11357 ]
11358 (const_string "mfcr")))
11359 (set_attr "length" "8")])
11360
11361 (define_insn ""
11362 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11363 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11364 [(match_operand 2 "cc_reg_operand" "y,y")
11365 (const_int 0)])
11366 (const_int 0)))
11367 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11368 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11369 "TARGET_32BIT"
11370 "@
11371 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11372 #"
11373 [(set_attr "type" "delayed_compare")
11374 (set_attr "length" "8,16")])
11375
11376 (define_split
11377 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11378 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11379 [(match_operand 2 "cc_reg_operand" "")
11380 (const_int 0)])
11381 (const_int 0)))
11382 (set (match_operand:SI 3 "gpc_reg_operand" "")
11383 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11384 "TARGET_32BIT && reload_completed"
11385 [(set (match_dup 3)
11386 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11387 (set (match_dup 0)
11388 (compare:CC (match_dup 3)
11389 (const_int 0)))]
11390 "")
11391
11392 (define_insn ""
11393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11394 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11395 [(match_operand 2 "cc_reg_operand" "y")
11396 (const_int 0)])
11397 (match_operand:SI 3 "const_int_operand" "n")))]
11398 ""
11399 "*
11400 {
11401 int is_bit = ccr_bit (operands[1], 1);
11402 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11403 int count;
11404
11405 if (is_bit >= put_bit)
11406 count = is_bit - put_bit;
11407 else
11408 count = 32 - (put_bit - is_bit);
11409
11410 operands[4] = GEN_INT (count);
11411 operands[5] = GEN_INT (put_bit);
11412
11413 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11414 }"
11415 [(set (attr "type")
11416 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11417 (const_string "mfcrf")
11418 ]
11419 (const_string "mfcr")))
11420 (set_attr "length" "8")])
11421
11422 (define_insn ""
11423 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11424 (compare:CC
11425 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11426 [(match_operand 2 "cc_reg_operand" "y,y")
11427 (const_int 0)])
11428 (match_operand:SI 3 "const_int_operand" "n,n"))
11429 (const_int 0)))
11430 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11431 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11432 (match_dup 3)))]
11433 ""
11434 "*
11435 {
11436 int is_bit = ccr_bit (operands[1], 1);
11437 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11438 int count;
11439
11440 /* Force split for non-cc0 compare. */
11441 if (which_alternative == 1)
11442 return \"#\";
11443
11444 if (is_bit >= put_bit)
11445 count = is_bit - put_bit;
11446 else
11447 count = 32 - (put_bit - is_bit);
11448
11449 operands[5] = GEN_INT (count);
11450 operands[6] = GEN_INT (put_bit);
11451
11452 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11453 }"
11454 [(set_attr "type" "delayed_compare")
11455 (set_attr "length" "8,16")])
11456
11457 (define_split
11458 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11459 (compare:CC
11460 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11461 [(match_operand 2 "cc_reg_operand" "")
11462 (const_int 0)])
11463 (match_operand:SI 3 "const_int_operand" ""))
11464 (const_int 0)))
11465 (set (match_operand:SI 4 "gpc_reg_operand" "")
11466 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11467 (match_dup 3)))]
11468 "reload_completed"
11469 [(set (match_dup 4)
11470 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11471 (match_dup 3)))
11472 (set (match_dup 0)
11473 (compare:CC (match_dup 4)
11474 (const_int 0)))]
11475 "")
11476
11477 ;; There is a 3 cycle delay between consecutive mfcr instructions
11478 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11479
11480 (define_peephole
11481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11482 (match_operator:SI 1 "scc_comparison_operator"
11483 [(match_operand 2 "cc_reg_operand" "y")
11484 (const_int 0)]))
11485 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11486 (match_operator:SI 4 "scc_comparison_operator"
11487 [(match_operand 5 "cc_reg_operand" "y")
11488 (const_int 0)]))]
11489 "REGNO (operands[2]) != REGNO (operands[5])"
11490 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11491 [(set_attr "type" "mfcr")
11492 (set_attr "length" "12")])
11493
11494 (define_peephole
11495 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11496 (match_operator:DI 1 "scc_comparison_operator"
11497 [(match_operand 2 "cc_reg_operand" "y")
11498 (const_int 0)]))
11499 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11500 (match_operator:DI 4 "scc_comparison_operator"
11501 [(match_operand 5 "cc_reg_operand" "y")
11502 (const_int 0)]))]
11503 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11504 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11505 [(set_attr "type" "mfcr")
11506 (set_attr "length" "12")])
11507
11508 ;; There are some scc insns that can be done directly, without a compare.
11509 ;; These are faster because they don't involve the communications between
11510 ;; the FXU and branch units. In fact, we will be replacing all of the
11511 ;; integer scc insns here or in the portable methods in emit_store_flag.
11512 ;;
11513 ;; Also support (neg (scc ..)) since that construct is used to replace
11514 ;; branches, (plus (scc ..) ..) since that construct is common and
11515 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11516 ;; cases where it is no more expensive than (neg (scc ..)).
11517
11518 ;; Have reload force a constant into a register for the simple insns that
11519 ;; otherwise won't accept constants. We do this because it is faster than
11520 ;; the cmp/mfcr sequence we would otherwise generate.
11521
11522 (define_insn ""
11523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11524 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11525 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11526 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11527 "TARGET_32BIT"
11528 "@
11529 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11530 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11531 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11532 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11533 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11534 [(set_attr "type" "three,two,three,three,three")
11535 (set_attr "length" "12,8,12,12,12")])
11536
11537 (define_insn ""
11538 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11539 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11540 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11541 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11542 "TARGET_64BIT"
11543 "@
11544 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11545 subfic %3,%1,0\;adde %0,%3,%1
11546 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11547 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11548 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11549 [(set_attr "type" "three,two,three,three,three")
11550 (set_attr "length" "12,8,12,12,12")])
11551
11552 (define_insn ""
11553 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11554 (compare:CC
11555 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11556 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11557 (const_int 0)))
11558 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11559 (eq:SI (match_dup 1) (match_dup 2)))
11560 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11561 "TARGET_32BIT"
11562 "@
11563 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11564 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11565 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11566 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11567 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11568 #
11569 #
11570 #
11571 #
11572 #"
11573 [(set_attr "type" "compare")
11574 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11575
11576 (define_split
11577 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11578 (compare:CC
11579 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11580 (match_operand:SI 2 "reg_or_cint_operand" ""))
11581 (const_int 0)))
11582 (set (match_operand:SI 0 "gpc_reg_operand" "")
11583 (eq:SI (match_dup 1) (match_dup 2)))
11584 (clobber (match_scratch:SI 3 ""))]
11585 "TARGET_32BIT && reload_completed"
11586 [(parallel [(set (match_dup 0)
11587 (eq:SI (match_dup 1) (match_dup 2)))
11588 (clobber (match_dup 3))])
11589 (set (match_dup 4)
11590 (compare:CC (match_dup 0)
11591 (const_int 0)))]
11592 "")
11593
11594 (define_insn ""
11595 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11596 (compare:CC
11597 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11598 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11599 (const_int 0)))
11600 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11601 (eq:DI (match_dup 1) (match_dup 2)))
11602 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11603 "TARGET_64BIT"
11604 "@
11605 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11606 subfic %3,%1,0\;adde. %0,%3,%1
11607 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11608 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11609 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11610 #
11611 #
11612 #
11613 #
11614 #"
11615 [(set_attr "type" "compare")
11616 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11617
11618 (define_split
11619 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11620 (compare:CC
11621 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11622 (match_operand:DI 2 "reg_or_cint_operand" ""))
11623 (const_int 0)))
11624 (set (match_operand:DI 0 "gpc_reg_operand" "")
11625 (eq:DI (match_dup 1) (match_dup 2)))
11626 (clobber (match_scratch:DI 3 ""))]
11627 "TARGET_64BIT && reload_completed"
11628 [(parallel [(set (match_dup 0)
11629 (eq:DI (match_dup 1) (match_dup 2)))
11630 (clobber (match_dup 3))])
11631 (set (match_dup 4)
11632 (compare:CC (match_dup 0)
11633 (const_int 0)))]
11634 "")
11635
11636 ;; We have insns of the form shown by the first define_insn below. If
11637 ;; there is something inside the comparison operation, we must split it.
11638 (define_split
11639 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11640 (plus:SI (match_operator 1 "comparison_operator"
11641 [(match_operand:SI 2 "" "")
11642 (match_operand:SI 3
11643 "reg_or_cint_operand" "")])
11644 (match_operand:SI 4 "gpc_reg_operand" "")))
11645 (clobber (match_operand:SI 5 "register_operand" ""))]
11646 "! gpc_reg_operand (operands[2], SImode)"
11647 [(set (match_dup 5) (match_dup 2))
11648 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11649 (match_dup 4)))])
11650
11651 (define_insn ""
11652 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11653 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11654 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11655 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11656 "TARGET_32BIT"
11657 "@
11658 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11659 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11660 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11661 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11662 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11663 [(set_attr "type" "three,two,three,three,three")
11664 (set_attr "length" "12,8,12,12,12")])
11665
11666 (define_insn ""
11667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11668 (compare:CC
11669 (plus:SI
11670 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11671 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11672 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11673 (const_int 0)))
11674 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11675 "TARGET_32BIT"
11676 "@
11677 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11678 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11679 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11680 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11681 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11682 #
11683 #
11684 #
11685 #
11686 #"
11687 [(set_attr "type" "compare")
11688 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11689
11690 (define_split
11691 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11692 (compare:CC
11693 (plus:SI
11694 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11695 (match_operand:SI 2 "reg_or_cint_operand" ""))
11696 (match_operand:SI 3 "gpc_reg_operand" ""))
11697 (const_int 0)))
11698 (clobber (match_scratch:SI 4 ""))]
11699 "TARGET_32BIT && reload_completed"
11700 [(set (match_dup 4)
11701 (plus:SI (eq:SI (match_dup 1)
11702 (match_dup 2))
11703 (match_dup 3)))
11704 (set (match_dup 0)
11705 (compare:CC (match_dup 4)
11706 (const_int 0)))]
11707 "")
11708
11709 (define_insn ""
11710 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11711 (compare:CC
11712 (plus:SI
11713 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11714 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11715 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11716 (const_int 0)))
11717 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11718 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11719 "TARGET_32BIT"
11720 "@
11721 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11722 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11723 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11724 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11725 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11726 #
11727 #
11728 #
11729 #
11730 #"
11731 [(set_attr "type" "compare")
11732 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11733
11734 (define_split
11735 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11736 (compare:CC
11737 (plus:SI
11738 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11739 (match_operand:SI 2 "reg_or_cint_operand" ""))
11740 (match_operand:SI 3 "gpc_reg_operand" ""))
11741 (const_int 0)))
11742 (set (match_operand:SI 0 "gpc_reg_operand" "")
11743 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11744 "TARGET_32BIT && reload_completed"
11745 [(set (match_dup 0)
11746 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11747 (set (match_dup 4)
11748 (compare:CC (match_dup 0)
11749 (const_int 0)))]
11750 "")
11751
11752 (define_insn ""
11753 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11754 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11755 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11756 "TARGET_32BIT"
11757 "@
11758 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11759 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11760 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11761 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11762 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11763 [(set_attr "type" "three,two,three,three,three")
11764 (set_attr "length" "12,8,12,12,12")])
11765
11766 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11767 ;; since it nabs/sr is just as fast.
11768 (define_insn "*ne0"
11769 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11770 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11771 (const_int 31)))
11772 (clobber (match_scratch:SI 2 "=&r"))]
11773 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11774 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11775 [(set_attr "type" "two")
11776 (set_attr "length" "8")])
11777
11778 (define_insn ""
11779 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11780 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11781 (const_int 63)))
11782 (clobber (match_scratch:DI 2 "=&r"))]
11783 "TARGET_64BIT"
11784 "addic %2,%1,-1\;subfe %0,%2,%1"
11785 [(set_attr "type" "two")
11786 (set_attr "length" "8")])
11787
11788 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11789 (define_insn ""
11790 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11791 (plus:SI (lshiftrt:SI
11792 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11793 (const_int 31))
11794 (match_operand:SI 2 "gpc_reg_operand" "r")))
11795 (clobber (match_scratch:SI 3 "=&r"))]
11796 "TARGET_32BIT"
11797 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11798 [(set_attr "type" "two")
11799 (set_attr "length" "8")])
11800
11801 (define_insn ""
11802 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11803 (plus:DI (lshiftrt:DI
11804 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11805 (const_int 63))
11806 (match_operand:DI 2 "gpc_reg_operand" "r")))
11807 (clobber (match_scratch:DI 3 "=&r"))]
11808 "TARGET_64BIT"
11809 "addic %3,%1,-1\;addze %0,%2"
11810 [(set_attr "type" "two")
11811 (set_attr "length" "8")])
11812
11813 (define_insn ""
11814 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11815 (compare:CC
11816 (plus:SI (lshiftrt:SI
11817 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11818 (const_int 31))
11819 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11820 (const_int 0)))
11821 (clobber (match_scratch:SI 3 "=&r,&r"))
11822 (clobber (match_scratch:SI 4 "=X,&r"))]
11823 "TARGET_32BIT"
11824 "@
11825 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11826 #"
11827 [(set_attr "type" "compare")
11828 (set_attr "length" "8,12")])
11829
11830 (define_split
11831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11832 (compare:CC
11833 (plus:SI (lshiftrt:SI
11834 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11835 (const_int 31))
11836 (match_operand:SI 2 "gpc_reg_operand" ""))
11837 (const_int 0)))
11838 (clobber (match_scratch:SI 3 ""))
11839 (clobber (match_scratch:SI 4 ""))]
11840 "TARGET_32BIT && reload_completed"
11841 [(parallel [(set (match_dup 3)
11842 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11843 (const_int 31))
11844 (match_dup 2)))
11845 (clobber (match_dup 4))])
11846 (set (match_dup 0)
11847 (compare:CC (match_dup 3)
11848 (const_int 0)))]
11849 "")
11850
11851 (define_insn ""
11852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11853 (compare:CC
11854 (plus:DI (lshiftrt:DI
11855 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11856 (const_int 63))
11857 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11858 (const_int 0)))
11859 (clobber (match_scratch:DI 3 "=&r,&r"))]
11860 "TARGET_64BIT"
11861 "@
11862 addic %3,%1,-1\;addze. %3,%2
11863 #"
11864 [(set_attr "type" "compare")
11865 (set_attr "length" "8,12")])
11866
11867 (define_split
11868 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11869 (compare:CC
11870 (plus:DI (lshiftrt:DI
11871 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11872 (const_int 63))
11873 (match_operand:DI 2 "gpc_reg_operand" ""))
11874 (const_int 0)))
11875 (clobber (match_scratch:DI 3 ""))]
11876 "TARGET_64BIT && reload_completed"
11877 [(set (match_dup 3)
11878 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11879 (const_int 63))
11880 (match_dup 2)))
11881 (set (match_dup 0)
11882 (compare:CC (match_dup 3)
11883 (const_int 0)))]
11884 "")
11885
11886 (define_insn ""
11887 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11888 (compare:CC
11889 (plus:SI (lshiftrt:SI
11890 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11891 (const_int 31))
11892 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11893 (const_int 0)))
11894 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11895 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11896 (match_dup 2)))
11897 (clobber (match_scratch:SI 3 "=&r,&r"))]
11898 "TARGET_32BIT"
11899 "@
11900 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11901 #"
11902 [(set_attr "type" "compare")
11903 (set_attr "length" "8,12")])
11904
11905 (define_split
11906 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11907 (compare:CC
11908 (plus:SI (lshiftrt:SI
11909 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11910 (const_int 31))
11911 (match_operand:SI 2 "gpc_reg_operand" ""))
11912 (const_int 0)))
11913 (set (match_operand:SI 0 "gpc_reg_operand" "")
11914 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11915 (match_dup 2)))
11916 (clobber (match_scratch:SI 3 ""))]
11917 "TARGET_32BIT && reload_completed"
11918 [(parallel [(set (match_dup 0)
11919 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11920 (match_dup 2)))
11921 (clobber (match_dup 3))])
11922 (set (match_dup 4)
11923 (compare:CC (match_dup 0)
11924 (const_int 0)))]
11925 "")
11926
11927 (define_insn ""
11928 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11929 (compare:CC
11930 (plus:DI (lshiftrt:DI
11931 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11932 (const_int 63))
11933 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11934 (const_int 0)))
11935 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11936 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11937 (match_dup 2)))
11938 (clobber (match_scratch:DI 3 "=&r,&r"))]
11939 "TARGET_64BIT"
11940 "@
11941 addic %3,%1,-1\;addze. %0,%2
11942 #"
11943 [(set_attr "type" "compare")
11944 (set_attr "length" "8,12")])
11945
11946 (define_split
11947 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11948 (compare:CC
11949 (plus:DI (lshiftrt:DI
11950 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11951 (const_int 63))
11952 (match_operand:DI 2 "gpc_reg_operand" ""))
11953 (const_int 0)))
11954 (set (match_operand:DI 0 "gpc_reg_operand" "")
11955 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11956 (match_dup 2)))
11957 (clobber (match_scratch:DI 3 ""))]
11958 "TARGET_64BIT && reload_completed"
11959 [(parallel [(set (match_dup 0)
11960 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11961 (match_dup 2)))
11962 (clobber (match_dup 3))])
11963 (set (match_dup 4)
11964 (compare:CC (match_dup 0)
11965 (const_int 0)))]
11966 "")
11967
11968 (define_insn ""
11969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11970 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11971 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11972 (clobber (match_scratch:SI 3 "=r,X"))]
11973 "TARGET_POWER"
11974 "@
11975 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11976 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11977 [(set_attr "length" "12")])
11978
11979 (define_insn ""
11980 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11981 (compare:CC
11982 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11983 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11984 (const_int 0)))
11985 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11986 (le:SI (match_dup 1) (match_dup 2)))
11987 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11988 "TARGET_POWER"
11989 "@
11990 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11991 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11992 #
11993 #"
11994 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11995 (set_attr "length" "12,12,16,16")])
11996
11997 (define_split
11998 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11999 (compare:CC
12000 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12001 (match_operand:SI 2 "reg_or_short_operand" ""))
12002 (const_int 0)))
12003 (set (match_operand:SI 0 "gpc_reg_operand" "")
12004 (le:SI (match_dup 1) (match_dup 2)))
12005 (clobber (match_scratch:SI 3 ""))]
12006 "TARGET_POWER && reload_completed"
12007 [(parallel [(set (match_dup 0)
12008 (le:SI (match_dup 1) (match_dup 2)))
12009 (clobber (match_dup 3))])
12010 (set (match_dup 4)
12011 (compare:CC (match_dup 0)
12012 (const_int 0)))]
12013 "")
12014
12015 (define_insn ""
12016 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12017 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12018 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12019 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12020 "TARGET_POWER"
12021 "@
12022 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12023 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12024 [(set_attr "length" "12")])
12025
12026 (define_insn ""
12027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12028 (compare:CC
12029 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12030 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12031 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12032 (const_int 0)))
12033 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12034 "TARGET_POWER"
12035 "@
12036 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12037 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12038 #
12039 #"
12040 [(set_attr "type" "compare")
12041 (set_attr "length" "12,12,16,16")])
12042
12043 (define_split
12044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12045 (compare:CC
12046 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12047 (match_operand:SI 2 "reg_or_short_operand" ""))
12048 (match_operand:SI 3 "gpc_reg_operand" ""))
12049 (const_int 0)))
12050 (clobber (match_scratch:SI 4 ""))]
12051 "TARGET_POWER && reload_completed"
12052 [(set (match_dup 4)
12053 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12054 (match_dup 3)))
12055 (set (match_dup 0)
12056 (compare:CC (match_dup 4)
12057 (const_int 0)))]
12058 "")
12059
12060 (define_insn ""
12061 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12062 (compare:CC
12063 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12064 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12065 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12066 (const_int 0)))
12067 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12068 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12069 "TARGET_POWER"
12070 "@
12071 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12072 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12073 #
12074 #"
12075 [(set_attr "type" "compare")
12076 (set_attr "length" "12,12,16,16")])
12077
12078 (define_split
12079 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12080 (compare:CC
12081 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12082 (match_operand:SI 2 "reg_or_short_operand" ""))
12083 (match_operand:SI 3 "gpc_reg_operand" ""))
12084 (const_int 0)))
12085 (set (match_operand:SI 0 "gpc_reg_operand" "")
12086 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12087 "TARGET_POWER && reload_completed"
12088 [(set (match_dup 0)
12089 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12090 (set (match_dup 4)
12091 (compare:CC (match_dup 0)
12092 (const_int 0)))]
12093 "")
12094
12095 (define_insn ""
12096 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12097 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12098 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12099 "TARGET_POWER"
12100 "@
12101 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12102 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12103 [(set_attr "length" "12")])
12104
12105 (define_insn ""
12106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12107 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12108 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12109 "TARGET_32BIT"
12110 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12111 [(set_attr "type" "three")
12112 (set_attr "length" "12")])
12113
12114 (define_insn ""
12115 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12116 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12117 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12118 "TARGET_64BIT"
12119 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12120 [(set_attr "type" "three")
12121 (set_attr "length" "12")])
12122
12123 (define_insn ""
12124 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12125 (compare:CC
12126 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12127 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12128 (const_int 0)))
12129 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12130 (leu:DI (match_dup 1) (match_dup 2)))]
12131 "TARGET_64BIT"
12132 "@
12133 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12134 #"
12135 [(set_attr "type" "compare")
12136 (set_attr "length" "12,16")])
12137
12138 (define_split
12139 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12140 (compare:CC
12141 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12142 (match_operand:DI 2 "reg_or_short_operand" ""))
12143 (const_int 0)))
12144 (set (match_operand:DI 0 "gpc_reg_operand" "")
12145 (leu:DI (match_dup 1) (match_dup 2)))]
12146 "TARGET_64BIT && reload_completed"
12147 [(set (match_dup 0)
12148 (leu:DI (match_dup 1) (match_dup 2)))
12149 (set (match_dup 3)
12150 (compare:CC (match_dup 0)
12151 (const_int 0)))]
12152 "")
12153
12154 (define_insn ""
12155 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12156 (compare:CC
12157 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12158 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12159 (const_int 0)))
12160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12161 (leu:SI (match_dup 1) (match_dup 2)))]
12162 "TARGET_32BIT"
12163 "@
12164 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12165 #"
12166 [(set_attr "type" "compare")
12167 (set_attr "length" "12,16")])
12168
12169 (define_split
12170 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12171 (compare:CC
12172 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12173 (match_operand:SI 2 "reg_or_short_operand" ""))
12174 (const_int 0)))
12175 (set (match_operand:SI 0 "gpc_reg_operand" "")
12176 (leu:SI (match_dup 1) (match_dup 2)))]
12177 "TARGET_32BIT && reload_completed"
12178 [(set (match_dup 0)
12179 (leu:SI (match_dup 1) (match_dup 2)))
12180 (set (match_dup 3)
12181 (compare:CC (match_dup 0)
12182 (const_int 0)))]
12183 "")
12184
12185 (define_insn ""
12186 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12187 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12188 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12189 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12190 "TARGET_32BIT"
12191 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12192 [(set_attr "type" "two")
12193 (set_attr "length" "8")])
12194
12195 (define_insn ""
12196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12197 (compare:CC
12198 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12199 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12200 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12201 (const_int 0)))
12202 (clobber (match_scratch:SI 4 "=&r,&r"))]
12203 "TARGET_32BIT"
12204 "@
12205 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12206 #"
12207 [(set_attr "type" "compare")
12208 (set_attr "length" "8,12")])
12209
12210 (define_split
12211 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12212 (compare:CC
12213 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12214 (match_operand:SI 2 "reg_or_short_operand" ""))
12215 (match_operand:SI 3 "gpc_reg_operand" ""))
12216 (const_int 0)))
12217 (clobber (match_scratch:SI 4 ""))]
12218 "TARGET_32BIT && reload_completed"
12219 [(set (match_dup 4)
12220 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12221 (match_dup 3)))
12222 (set (match_dup 0)
12223 (compare:CC (match_dup 4)
12224 (const_int 0)))]
12225 "")
12226
12227 (define_insn ""
12228 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12229 (compare:CC
12230 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12231 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12232 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12233 (const_int 0)))
12234 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12235 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12236 "TARGET_32BIT"
12237 "@
12238 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12239 #"
12240 [(set_attr "type" "compare")
12241 (set_attr "length" "8,12")])
12242
12243 (define_split
12244 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12245 (compare:CC
12246 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12247 (match_operand:SI 2 "reg_or_short_operand" ""))
12248 (match_operand:SI 3 "gpc_reg_operand" ""))
12249 (const_int 0)))
12250 (set (match_operand:SI 0 "gpc_reg_operand" "")
12251 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12252 "TARGET_32BIT && reload_completed"
12253 [(set (match_dup 0)
12254 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12255 (set (match_dup 4)
12256 (compare:CC (match_dup 0)
12257 (const_int 0)))]
12258 "")
12259
12260 (define_insn ""
12261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12262 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12263 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12264 "TARGET_32BIT"
12265 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12266 [(set_attr "type" "three")
12267 (set_attr "length" "12")])
12268
12269 (define_insn ""
12270 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12271 (and:SI (neg:SI
12272 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12273 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12274 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12275 "TARGET_32BIT"
12276 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12277 [(set_attr "type" "three")
12278 (set_attr "length" "12")])
12279
12280 (define_insn ""
12281 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12282 (compare:CC
12283 (and:SI (neg:SI
12284 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12285 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12286 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12287 (const_int 0)))
12288 (clobber (match_scratch:SI 4 "=&r,&r"))]
12289 "TARGET_32BIT"
12290 "@
12291 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12292 #"
12293 [(set_attr "type" "compare")
12294 (set_attr "length" "12,16")])
12295
12296 (define_split
12297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12298 (compare:CC
12299 (and:SI (neg:SI
12300 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12301 (match_operand:SI 2 "reg_or_short_operand" "")))
12302 (match_operand:SI 3 "gpc_reg_operand" ""))
12303 (const_int 0)))
12304 (clobber (match_scratch:SI 4 ""))]
12305 "TARGET_32BIT && reload_completed"
12306 [(set (match_dup 4)
12307 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12308 (match_dup 3)))
12309 (set (match_dup 0)
12310 (compare:CC (match_dup 4)
12311 (const_int 0)))]
12312 "")
12313
12314 (define_insn ""
12315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12316 (compare:CC
12317 (and:SI (neg:SI
12318 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12319 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12320 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12321 (const_int 0)))
12322 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12323 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12324 "TARGET_32BIT"
12325 "@
12326 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12327 #"
12328 [(set_attr "type" "compare")
12329 (set_attr "length" "12,16")])
12330
12331 (define_split
12332 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12333 (compare:CC
12334 (and:SI (neg:SI
12335 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12336 (match_operand:SI 2 "reg_or_short_operand" "")))
12337 (match_operand:SI 3 "gpc_reg_operand" ""))
12338 (const_int 0)))
12339 (set (match_operand:SI 0 "gpc_reg_operand" "")
12340 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12341 "TARGET_32BIT && reload_completed"
12342 [(set (match_dup 0)
12343 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12344 (match_dup 3)))
12345 (set (match_dup 4)
12346 (compare:CC (match_dup 0)
12347 (const_int 0)))]
12348 "")
12349
12350 (define_insn ""
12351 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12352 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12353 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12354 "TARGET_POWER"
12355 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12356 [(set_attr "length" "12")])
12357
12358 (define_insn ""
12359 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12360 (compare:CC
12361 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12362 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12363 (const_int 0)))
12364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12365 (lt:SI (match_dup 1) (match_dup 2)))]
12366 "TARGET_POWER"
12367 "@
12368 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12369 #"
12370 [(set_attr "type" "delayed_compare")
12371 (set_attr "length" "12,16")])
12372
12373 (define_split
12374 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12375 (compare:CC
12376 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12377 (match_operand:SI 2 "reg_or_short_operand" ""))
12378 (const_int 0)))
12379 (set (match_operand:SI 0 "gpc_reg_operand" "")
12380 (lt:SI (match_dup 1) (match_dup 2)))]
12381 "TARGET_POWER && reload_completed"
12382 [(set (match_dup 0)
12383 (lt:SI (match_dup 1) (match_dup 2)))
12384 (set (match_dup 3)
12385 (compare:CC (match_dup 0)
12386 (const_int 0)))]
12387 "")
12388
12389 (define_insn ""
12390 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12391 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12392 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12393 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12394 "TARGET_POWER"
12395 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12396 [(set_attr "length" "12")])
12397
12398 (define_insn ""
12399 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12400 (compare:CC
12401 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12402 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12403 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12404 (const_int 0)))
12405 (clobber (match_scratch:SI 4 "=&r,&r"))]
12406 "TARGET_POWER"
12407 "@
12408 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12409 #"
12410 [(set_attr "type" "compare")
12411 (set_attr "length" "12,16")])
12412
12413 (define_split
12414 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12415 (compare:CC
12416 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12417 (match_operand:SI 2 "reg_or_short_operand" ""))
12418 (match_operand:SI 3 "gpc_reg_operand" ""))
12419 (const_int 0)))
12420 (clobber (match_scratch:SI 4 ""))]
12421 "TARGET_POWER && reload_completed"
12422 [(set (match_dup 4)
12423 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12424 (match_dup 3)))
12425 (set (match_dup 0)
12426 (compare:CC (match_dup 4)
12427 (const_int 0)))]
12428 "")
12429
12430 (define_insn ""
12431 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12432 (compare:CC
12433 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12434 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12435 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12436 (const_int 0)))
12437 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12438 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12439 "TARGET_POWER"
12440 "@
12441 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12442 #"
12443 [(set_attr "type" "compare")
12444 (set_attr "length" "12,16")])
12445
12446 (define_split
12447 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12448 (compare:CC
12449 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12450 (match_operand:SI 2 "reg_or_short_operand" ""))
12451 (match_operand:SI 3 "gpc_reg_operand" ""))
12452 (const_int 0)))
12453 (set (match_operand:SI 0 "gpc_reg_operand" "")
12454 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12455 "TARGET_POWER && reload_completed"
12456 [(set (match_dup 0)
12457 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12458 (set (match_dup 4)
12459 (compare:CC (match_dup 0)
12460 (const_int 0)))]
12461 "")
12462
12463 (define_insn ""
12464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12465 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12466 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12467 "TARGET_POWER"
12468 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12469 [(set_attr "length" "12")])
12470
12471 (define_insn_and_split ""
12472 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12473 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12474 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12475 "TARGET_32BIT"
12476 "#"
12477 "TARGET_32BIT"
12478 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12479 (set (match_dup 0) (neg:SI (match_dup 0)))]
12480 "")
12481
12482 (define_insn_and_split ""
12483 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12484 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12485 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12486 "TARGET_64BIT"
12487 "#"
12488 "TARGET_64BIT"
12489 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12490 (set (match_dup 0) (neg:DI (match_dup 0)))]
12491 "")
12492
12493 (define_insn ""
12494 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12495 (compare:CC
12496 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12497 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12498 (const_int 0)))
12499 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12500 (ltu:SI (match_dup 1) (match_dup 2)))]
12501 "TARGET_32BIT"
12502 "@
12503 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12504 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12505 #
12506 #"
12507 [(set_attr "type" "compare")
12508 (set_attr "length" "12,12,16,16")])
12509
12510 (define_split
12511 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12512 (compare:CC
12513 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12514 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12515 (const_int 0)))
12516 (set (match_operand:SI 0 "gpc_reg_operand" "")
12517 (ltu:SI (match_dup 1) (match_dup 2)))]
12518 "TARGET_32BIT && reload_completed"
12519 [(set (match_dup 0)
12520 (ltu:SI (match_dup 1) (match_dup 2)))
12521 (set (match_dup 3)
12522 (compare:CC (match_dup 0)
12523 (const_int 0)))]
12524 "")
12525
12526 (define_insn_and_split ""
12527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12528 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12529 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12530 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12531 "TARGET_32BIT"
12532 "#"
12533 "TARGET_32BIT"
12534 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12535 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12536 "")
12537
12538 (define_insn_and_split ""
12539 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12540 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12541 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12542 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12543 "TARGET_64BIT"
12544 "#"
12545 "TARGET_64BIT"
12546 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12547 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12548 "")
12549
12550 (define_insn ""
12551 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12552 (compare:CC
12553 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12554 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12555 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12556 (const_int 0)))
12557 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12558 "TARGET_32BIT"
12559 "@
12560 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12561 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12562 #
12563 #"
12564 [(set_attr "type" "compare")
12565 (set_attr "length" "12,12,16,16")])
12566
12567 (define_split
12568 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12569 (compare:CC
12570 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12571 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12572 (match_operand:SI 3 "gpc_reg_operand" ""))
12573 (const_int 0)))
12574 (clobber (match_scratch:SI 4 ""))]
12575 "TARGET_32BIT && reload_completed"
12576 [(set (match_dup 4)
12577 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12578 (match_dup 3)))
12579 (set (match_dup 0)
12580 (compare:CC (match_dup 4)
12581 (const_int 0)))]
12582 "")
12583
12584 (define_insn ""
12585 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12586 (compare:CC
12587 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12588 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12589 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12590 (const_int 0)))
12591 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12592 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12593 "TARGET_32BIT"
12594 "@
12595 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12596 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12597 #
12598 #"
12599 [(set_attr "type" "compare")
12600 (set_attr "length" "12,12,16,16")])
12601
12602 (define_split
12603 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12604 (compare:CC
12605 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12606 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12607 (match_operand:SI 3 "gpc_reg_operand" ""))
12608 (const_int 0)))
12609 (set (match_operand:SI 0 "gpc_reg_operand" "")
12610 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12611 "TARGET_32BIT && reload_completed"
12612 [(set (match_dup 0)
12613 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12614 (set (match_dup 4)
12615 (compare:CC (match_dup 0)
12616 (const_int 0)))]
12617 "")
12618
12619 (define_insn ""
12620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12621 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12622 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12623 "TARGET_32BIT"
12624 "@
12625 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12626 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12627 [(set_attr "type" "two")
12628 (set_attr "length" "8")])
12629
12630 (define_insn ""
12631 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12632 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12633 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12634 "TARGET_64BIT"
12635 "@
12636 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12637 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12638 [(set_attr "type" "two")
12639 (set_attr "length" "8")])
12640
12641 (define_insn ""
12642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12643 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12644 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12645 (clobber (match_scratch:SI 3 "=r"))]
12646 "TARGET_POWER"
12647 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12648 [(set_attr "length" "12")])
12649
12650 (define_insn ""
12651 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12652 (compare:CC
12653 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12654 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12655 (const_int 0)))
12656 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12657 (ge:SI (match_dup 1) (match_dup 2)))
12658 (clobber (match_scratch:SI 3 "=r,r"))]
12659 "TARGET_POWER"
12660 "@
12661 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12662 #"
12663 [(set_attr "type" "compare")
12664 (set_attr "length" "12,16")])
12665
12666 (define_split
12667 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12668 (compare:CC
12669 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12670 (match_operand:SI 2 "reg_or_short_operand" ""))
12671 (const_int 0)))
12672 (set (match_operand:SI 0 "gpc_reg_operand" "")
12673 (ge:SI (match_dup 1) (match_dup 2)))
12674 (clobber (match_scratch:SI 3 ""))]
12675 "TARGET_POWER && reload_completed"
12676 [(parallel [(set (match_dup 0)
12677 (ge:SI (match_dup 1) (match_dup 2)))
12678 (clobber (match_dup 3))])
12679 (set (match_dup 4)
12680 (compare:CC (match_dup 0)
12681 (const_int 0)))]
12682 "")
12683
12684 (define_insn ""
12685 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12686 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12687 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12688 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12689 "TARGET_POWER"
12690 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12691 [(set_attr "length" "12")])
12692
12693 (define_insn ""
12694 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12695 (compare:CC
12696 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12697 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12698 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12699 (const_int 0)))
12700 (clobber (match_scratch:SI 4 "=&r,&r"))]
12701 "TARGET_POWER"
12702 "@
12703 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12704 #"
12705 [(set_attr "type" "compare")
12706 (set_attr "length" "12,16")])
12707
12708 (define_split
12709 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12710 (compare:CC
12711 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12712 (match_operand:SI 2 "reg_or_short_operand" ""))
12713 (match_operand:SI 3 "gpc_reg_operand" ""))
12714 (const_int 0)))
12715 (clobber (match_scratch:SI 4 ""))]
12716 "TARGET_POWER && reload_completed"
12717 [(set (match_dup 4)
12718 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12719 (match_dup 3)))
12720 (set (match_dup 0)
12721 (compare:CC (match_dup 4)
12722 (const_int 0)))]
12723 "")
12724
12725 (define_insn ""
12726 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12727 (compare:CC
12728 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12729 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12730 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12731 (const_int 0)))
12732 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12733 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12734 "TARGET_POWER"
12735 "@
12736 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12737 #"
12738 [(set_attr "type" "compare")
12739 (set_attr "length" "12,16")])
12740
12741 (define_split
12742 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12743 (compare:CC
12744 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12745 (match_operand:SI 2 "reg_or_short_operand" ""))
12746 (match_operand:SI 3 "gpc_reg_operand" ""))
12747 (const_int 0)))
12748 (set (match_operand:SI 0 "gpc_reg_operand" "")
12749 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12750 "TARGET_POWER && reload_completed"
12751 [(set (match_dup 0)
12752 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12753 (set (match_dup 4)
12754 (compare:CC (match_dup 0)
12755 (const_int 0)))]
12756 "")
12757
12758 (define_insn ""
12759 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12760 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12761 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12762 "TARGET_POWER"
12763 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12764 [(set_attr "length" "12")])
12765
12766 (define_insn ""
12767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12768 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12769 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12770 "TARGET_32BIT"
12771 "@
12772 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12773 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12774 [(set_attr "type" "three")
12775 (set_attr "length" "12")])
12776
12777 (define_insn ""
12778 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12779 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12780 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12781 "TARGET_64BIT"
12782 "@
12783 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12784 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12785 [(set_attr "type" "three")
12786 (set_attr "length" "12")])
12787
12788 (define_insn ""
12789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12790 (compare:CC
12791 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12792 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12793 (const_int 0)))
12794 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12795 (geu:SI (match_dup 1) (match_dup 2)))]
12796 "TARGET_32BIT"
12797 "@
12798 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12799 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12800 #
12801 #"
12802 [(set_attr "type" "compare")
12803 (set_attr "length" "12,12,16,16")])
12804
12805 (define_split
12806 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12807 (compare:CC
12808 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12809 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12810 (const_int 0)))
12811 (set (match_operand:SI 0 "gpc_reg_operand" "")
12812 (geu:SI (match_dup 1) (match_dup 2)))]
12813 "TARGET_32BIT && reload_completed"
12814 [(set (match_dup 0)
12815 (geu:SI (match_dup 1) (match_dup 2)))
12816 (set (match_dup 3)
12817 (compare:CC (match_dup 0)
12818 (const_int 0)))]
12819 "")
12820
12821 (define_insn ""
12822 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12823 (compare:CC
12824 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12825 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12826 (const_int 0)))
12827 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12828 (geu:DI (match_dup 1) (match_dup 2)))]
12829 "TARGET_64BIT"
12830 "@
12831 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12832 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12833 #
12834 #"
12835 [(set_attr "type" "compare")
12836 (set_attr "length" "12,12,16,16")])
12837
12838 (define_split
12839 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12840 (compare:CC
12841 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12842 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12843 (const_int 0)))
12844 (set (match_operand:DI 0 "gpc_reg_operand" "")
12845 (geu:DI (match_dup 1) (match_dup 2)))]
12846 "TARGET_64BIT && reload_completed"
12847 [(set (match_dup 0)
12848 (geu:DI (match_dup 1) (match_dup 2)))
12849 (set (match_dup 3)
12850 (compare:CC (match_dup 0)
12851 (const_int 0)))]
12852 "")
12853
12854 (define_insn ""
12855 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12856 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12857 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12858 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12859 "TARGET_32BIT"
12860 "@
12861 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12862 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12863 [(set_attr "type" "two")
12864 (set_attr "length" "8")])
12865
12866 (define_insn ""
12867 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12868 (compare:CC
12869 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12870 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12871 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12872 (const_int 0)))
12873 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12874 "TARGET_32BIT"
12875 "@
12876 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12877 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12878 #
12879 #"
12880 [(set_attr "type" "compare")
12881 (set_attr "length" "8,8,12,12")])
12882
12883 (define_split
12884 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12885 (compare:CC
12886 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12887 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12888 (match_operand:SI 3 "gpc_reg_operand" ""))
12889 (const_int 0)))
12890 (clobber (match_scratch:SI 4 ""))]
12891 "TARGET_32BIT && reload_completed"
12892 [(set (match_dup 4)
12893 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12894 (match_dup 3)))
12895 (set (match_dup 0)
12896 (compare:CC (match_dup 4)
12897 (const_int 0)))]
12898 "")
12899
12900 (define_insn ""
12901 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12902 (compare:CC
12903 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12904 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12905 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12906 (const_int 0)))
12907 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12908 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12909 "TARGET_32BIT"
12910 "@
12911 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12912 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12913 #
12914 #"
12915 [(set_attr "type" "compare")
12916 (set_attr "length" "8,8,12,12")])
12917
12918 (define_split
12919 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12920 (compare:CC
12921 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12922 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12923 (match_operand:SI 3 "gpc_reg_operand" ""))
12924 (const_int 0)))
12925 (set (match_operand:SI 0 "gpc_reg_operand" "")
12926 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12927 "TARGET_32BIT && reload_completed"
12928 [(set (match_dup 0)
12929 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12930 (set (match_dup 4)
12931 (compare:CC (match_dup 0)
12932 (const_int 0)))]
12933 "")
12934
12935 (define_insn ""
12936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12937 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12938 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12939 "TARGET_32BIT"
12940 "@
12941 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12942 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12943 [(set_attr "type" "three")
12944 (set_attr "length" "12")])
12945
12946 (define_insn ""
12947 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12948 (and:SI (neg:SI
12949 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12950 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12951 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12952 "TARGET_32BIT"
12953 "@
12954 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12955 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12956 [(set_attr "type" "three")
12957 (set_attr "length" "12")])
12958
12959 (define_insn ""
12960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12961 (compare:CC
12962 (and:SI (neg:SI
12963 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12964 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12965 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12966 (const_int 0)))
12967 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12968 "TARGET_32BIT"
12969 "@
12970 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12971 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12972 #
12973 #"
12974 [(set_attr "type" "compare")
12975 (set_attr "length" "12,12,16,16")])
12976
12977 (define_split
12978 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12979 (compare:CC
12980 (and:SI (neg:SI
12981 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12982 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12983 (match_operand:SI 3 "gpc_reg_operand" ""))
12984 (const_int 0)))
12985 (clobber (match_scratch:SI 4 ""))]
12986 "TARGET_32BIT && reload_completed"
12987 [(set (match_dup 4)
12988 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12989 (match_dup 3)))
12990 (set (match_dup 0)
12991 (compare:CC (match_dup 4)
12992 (const_int 0)))]
12993 "")
12994
12995 (define_insn ""
12996 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12997 (compare:CC
12998 (and:SI (neg:SI
12999 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13000 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13001 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13002 (const_int 0)))
13003 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13004 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13005 "TARGET_32BIT"
13006 "@
13007 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13008 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13009 #
13010 #"
13011 [(set_attr "type" "compare")
13012 (set_attr "length" "12,12,16,16")])
13013
13014 (define_split
13015 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13016 (compare:CC
13017 (and:SI (neg:SI
13018 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13019 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13020 (match_operand:SI 3 "gpc_reg_operand" ""))
13021 (const_int 0)))
13022 (set (match_operand:SI 0 "gpc_reg_operand" "")
13023 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13024 "TARGET_32BIT && reload_completed"
13025 [(set (match_dup 0)
13026 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13027 (set (match_dup 4)
13028 (compare:CC (match_dup 0)
13029 (const_int 0)))]
13030 "")
13031
13032 (define_insn ""
13033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13034 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13035 (const_int 0)))]
13036 "TARGET_32BIT"
13037 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13038 [(set_attr "type" "three")
13039 (set_attr "length" "12")])
13040
13041 (define_insn ""
13042 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13043 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13044 (const_int 0)))]
13045 "TARGET_64BIT"
13046 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13047 [(set_attr "type" "three")
13048 (set_attr "length" "12")])
13049
13050 (define_insn ""
13051 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13052 (compare:CC
13053 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13054 (const_int 0))
13055 (const_int 0)))
13056 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13057 (gt:SI (match_dup 1) (const_int 0)))]
13058 "TARGET_32BIT"
13059 "@
13060 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13061 #"
13062 [(set_attr "type" "delayed_compare")
13063 (set_attr "length" "12,16")])
13064
13065 (define_split
13066 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13067 (compare:CC
13068 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13069 (const_int 0))
13070 (const_int 0)))
13071 (set (match_operand:SI 0 "gpc_reg_operand" "")
13072 (gt:SI (match_dup 1) (const_int 0)))]
13073 "TARGET_32BIT && reload_completed"
13074 [(set (match_dup 0)
13075 (gt:SI (match_dup 1) (const_int 0)))
13076 (set (match_dup 2)
13077 (compare:CC (match_dup 0)
13078 (const_int 0)))]
13079 "")
13080
13081 (define_insn ""
13082 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13083 (compare:CC
13084 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13085 (const_int 0))
13086 (const_int 0)))
13087 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13088 (gt:DI (match_dup 1) (const_int 0)))]
13089 "TARGET_64BIT"
13090 "@
13091 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13092 #"
13093 [(set_attr "type" "delayed_compare")
13094 (set_attr "length" "12,16")])
13095
13096 (define_split
13097 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13098 (compare:CC
13099 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13100 (const_int 0))
13101 (const_int 0)))
13102 (set (match_operand:DI 0 "gpc_reg_operand" "")
13103 (gt:DI (match_dup 1) (const_int 0)))]
13104 "TARGET_64BIT && reload_completed"
13105 [(set (match_dup 0)
13106 (gt:DI (match_dup 1) (const_int 0)))
13107 (set (match_dup 2)
13108 (compare:CC (match_dup 0)
13109 (const_int 0)))]
13110 "")
13111
13112 (define_insn ""
13113 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13114 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13115 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13116 "TARGET_POWER"
13117 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13118 [(set_attr "length" "12")])
13119
13120 (define_insn ""
13121 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13122 (compare:CC
13123 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13124 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13125 (const_int 0)))
13126 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13127 (gt:SI (match_dup 1) (match_dup 2)))]
13128 "TARGET_POWER"
13129 "@
13130 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13131 #"
13132 [(set_attr "type" "delayed_compare")
13133 (set_attr "length" "12,16")])
13134
13135 (define_split
13136 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13137 (compare:CC
13138 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13139 (match_operand:SI 2 "reg_or_short_operand" ""))
13140 (const_int 0)))
13141 (set (match_operand:SI 0 "gpc_reg_operand" "")
13142 (gt:SI (match_dup 1) (match_dup 2)))]
13143 "TARGET_POWER && reload_completed"
13144 [(set (match_dup 0)
13145 (gt:SI (match_dup 1) (match_dup 2)))
13146 (set (match_dup 3)
13147 (compare:CC (match_dup 0)
13148 (const_int 0)))]
13149 "")
13150
13151 (define_insn ""
13152 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13153 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13154 (const_int 0))
13155 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13156 "TARGET_32BIT"
13157 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13158 [(set_attr "type" "three")
13159 (set_attr "length" "12")])
13160
13161 (define_insn ""
13162 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13163 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13164 (const_int 0))
13165 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13166 "TARGET_64BIT"
13167 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13168 [(set_attr "type" "three")
13169 (set_attr "length" "12")])
13170
13171 (define_insn ""
13172 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13173 (compare:CC
13174 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13175 (const_int 0))
13176 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13177 (const_int 0)))
13178 (clobber (match_scratch:SI 3 "=&r,&r"))]
13179 "TARGET_32BIT"
13180 "@
13181 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13182 #"
13183 [(set_attr "type" "compare")
13184 (set_attr "length" "12,16")])
13185
13186 (define_split
13187 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13188 (compare:CC
13189 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13190 (const_int 0))
13191 (match_operand:SI 2 "gpc_reg_operand" ""))
13192 (const_int 0)))
13193 (clobber (match_scratch:SI 3 ""))]
13194 "TARGET_32BIT && reload_completed"
13195 [(set (match_dup 3)
13196 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13197 (match_dup 2)))
13198 (set (match_dup 0)
13199 (compare:CC (match_dup 3)
13200 (const_int 0)))]
13201 "")
13202
13203 (define_insn ""
13204 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13205 (compare:CC
13206 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13207 (const_int 0))
13208 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13209 (const_int 0)))
13210 (clobber (match_scratch:DI 3 "=&r,&r"))]
13211 "TARGET_64BIT"
13212 "@
13213 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13214 #"
13215 [(set_attr "type" "compare")
13216 (set_attr "length" "12,16")])
13217
13218 (define_split
13219 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13220 (compare:CC
13221 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13222 (const_int 0))
13223 (match_operand:DI 2 "gpc_reg_operand" ""))
13224 (const_int 0)))
13225 (clobber (match_scratch:DI 3 ""))]
13226 "TARGET_64BIT && reload_completed"
13227 [(set (match_dup 3)
13228 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13229 (match_dup 2)))
13230 (set (match_dup 0)
13231 (compare:CC (match_dup 3)
13232 (const_int 0)))]
13233 "")
13234
13235 (define_insn ""
13236 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13237 (compare:CC
13238 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13239 (const_int 0))
13240 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13241 (const_int 0)))
13242 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13243 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13244 "TARGET_32BIT"
13245 "@
13246 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13247 #"
13248 [(set_attr "type" "compare")
13249 (set_attr "length" "12,16")])
13250
13251 (define_split
13252 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13253 (compare:CC
13254 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13255 (const_int 0))
13256 (match_operand:SI 2 "gpc_reg_operand" ""))
13257 (const_int 0)))
13258 (set (match_operand:SI 0 "gpc_reg_operand" "")
13259 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13260 "TARGET_32BIT && reload_completed"
13261 [(set (match_dup 0)
13262 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13263 (set (match_dup 3)
13264 (compare:CC (match_dup 0)
13265 (const_int 0)))]
13266 "")
13267
13268 (define_insn ""
13269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13270 (compare:CC
13271 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13272 (const_int 0))
13273 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13274 (const_int 0)))
13275 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13276 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13277 "TARGET_64BIT"
13278 "@
13279 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13280 #"
13281 [(set_attr "type" "compare")
13282 (set_attr "length" "12,16")])
13283
13284 (define_split
13285 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13286 (compare:CC
13287 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13288 (const_int 0))
13289 (match_operand:DI 2 "gpc_reg_operand" ""))
13290 (const_int 0)))
13291 (set (match_operand:DI 0 "gpc_reg_operand" "")
13292 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13293 "TARGET_64BIT && reload_completed"
13294 [(set (match_dup 0)
13295 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13296 (set (match_dup 3)
13297 (compare:CC (match_dup 0)
13298 (const_int 0)))]
13299 "")
13300
13301 (define_insn ""
13302 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13303 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13304 (match_operand:SI 2 "reg_or_short_operand" "r"))
13305 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13306 "TARGET_POWER"
13307 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13308 [(set_attr "length" "12")])
13309
13310 (define_insn ""
13311 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13312 (compare:CC
13313 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13314 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13315 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13316 (const_int 0)))
13317 (clobber (match_scratch:SI 4 "=&r,&r"))]
13318 "TARGET_POWER"
13319 "@
13320 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13321 #"
13322 [(set_attr "type" "compare")
13323 (set_attr "length" "12,16")])
13324
13325 (define_split
13326 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13327 (compare:CC
13328 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13329 (match_operand:SI 2 "reg_or_short_operand" ""))
13330 (match_operand:SI 3 "gpc_reg_operand" ""))
13331 (const_int 0)))
13332 (clobber (match_scratch:SI 4 ""))]
13333 "TARGET_POWER && reload_completed"
13334 [(set (match_dup 4)
13335 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13336 (set (match_dup 0)
13337 (compare:CC (match_dup 4)
13338 (const_int 0)))]
13339 "")
13340
13341 (define_insn ""
13342 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13343 (compare:CC
13344 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13345 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13346 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13347 (const_int 0)))
13348 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13349 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13350 "TARGET_POWER"
13351 "@
13352 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13353 #"
13354 [(set_attr "type" "compare")
13355 (set_attr "length" "12,16")])
13356
13357 (define_split
13358 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13359 (compare:CC
13360 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13361 (match_operand:SI 2 "reg_or_short_operand" ""))
13362 (match_operand:SI 3 "gpc_reg_operand" ""))
13363 (const_int 0)))
13364 (set (match_operand:SI 0 "gpc_reg_operand" "")
13365 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13366 "TARGET_POWER && reload_completed"
13367 [(set (match_dup 0)
13368 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13369 (set (match_dup 4)
13370 (compare:CC (match_dup 0)
13371 (const_int 0)))]
13372 "")
13373
13374 (define_insn ""
13375 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13376 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13377 (const_int 0))))]
13378 "TARGET_32BIT"
13379 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13380 [(set_attr "type" "three")
13381 (set_attr "length" "12")])
13382
13383 (define_insn ""
13384 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13385 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13386 (const_int 0))))]
13387 "TARGET_64BIT"
13388 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13389 [(set_attr "type" "three")
13390 (set_attr "length" "12")])
13391
13392 (define_insn ""
13393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13394 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13395 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13396 "TARGET_POWER"
13397 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13398 [(set_attr "length" "12")])
13399
13400 (define_insn_and_split ""
13401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13402 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13403 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13404 "TARGET_32BIT"
13405 "#"
13406 "TARGET_32BIT"
13407 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13408 (set (match_dup 0) (neg:SI (match_dup 0)))]
13409 "")
13410
13411 (define_insn_and_split ""
13412 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13413 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13414 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13415 "TARGET_64BIT"
13416 "#"
13417 "TARGET_64BIT"
13418 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13419 (set (match_dup 0) (neg:DI (match_dup 0)))]
13420 "")
13421
13422 (define_insn ""
13423 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13424 (compare:CC
13425 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13426 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13427 (const_int 0)))
13428 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13429 (gtu:SI (match_dup 1) (match_dup 2)))]
13430 "TARGET_32BIT"
13431 "@
13432 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13433 #"
13434 [(set_attr "type" "compare")
13435 (set_attr "length" "12,16")])
13436
13437 (define_split
13438 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13439 (compare:CC
13440 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13441 (match_operand:SI 2 "reg_or_short_operand" ""))
13442 (const_int 0)))
13443 (set (match_operand:SI 0 "gpc_reg_operand" "")
13444 (gtu:SI (match_dup 1) (match_dup 2)))]
13445 "TARGET_32BIT && reload_completed"
13446 [(set (match_dup 0)
13447 (gtu:SI (match_dup 1) (match_dup 2)))
13448 (set (match_dup 3)
13449 (compare:CC (match_dup 0)
13450 (const_int 0)))]
13451 "")
13452
13453 (define_insn ""
13454 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13455 (compare:CC
13456 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13457 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13458 (const_int 0)))
13459 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13460 (gtu:DI (match_dup 1) (match_dup 2)))]
13461 "TARGET_64BIT"
13462 "@
13463 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13464 #"
13465 [(set_attr "type" "compare")
13466 (set_attr "length" "12,16")])
13467
13468 (define_split
13469 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13470 (compare:CC
13471 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13472 (match_operand:DI 2 "reg_or_short_operand" ""))
13473 (const_int 0)))
13474 (set (match_operand:DI 0 "gpc_reg_operand" "")
13475 (gtu:DI (match_dup 1) (match_dup 2)))]
13476 "TARGET_64BIT && reload_completed"
13477 [(set (match_dup 0)
13478 (gtu:DI (match_dup 1) (match_dup 2)))
13479 (set (match_dup 3)
13480 (compare:CC (match_dup 0)
13481 (const_int 0)))]
13482 "")
13483
13484 (define_insn_and_split ""
13485 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13486 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13487 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13488 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13489 "TARGET_32BIT"
13490 "#"
13491 "TARGET_32BIT"
13492 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13493 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13494 "")
13495
13496 (define_insn_and_split ""
13497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13498 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13499 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13500 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13501 "TARGET_64BIT"
13502 "#"
13503 "TARGET_64BIT"
13504 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13505 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13506 "")
13507
13508 (define_insn ""
13509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13510 (compare:CC
13511 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13512 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13513 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13514 (const_int 0)))
13515 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13516 "TARGET_32BIT"
13517 "@
13518 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13519 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13520 #
13521 #"
13522 [(set_attr "type" "compare")
13523 (set_attr "length" "8,12,12,16")])
13524
13525 (define_split
13526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13527 (compare:CC
13528 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13529 (match_operand:SI 2 "reg_or_short_operand" ""))
13530 (match_operand:SI 3 "gpc_reg_operand" ""))
13531 (const_int 0)))
13532 (clobber (match_scratch:SI 4 ""))]
13533 "TARGET_32BIT && reload_completed"
13534 [(set (match_dup 4)
13535 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13536 (match_dup 3)))
13537 (set (match_dup 0)
13538 (compare:CC (match_dup 4)
13539 (const_int 0)))]
13540 "")
13541
13542 (define_insn ""
13543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13544 (compare:CC
13545 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13546 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13547 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13548 (const_int 0)))
13549 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13550 "TARGET_64BIT"
13551 "@
13552 addic %4,%1,%k2\;addze. %4,%3
13553 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13554 #
13555 #"
13556 [(set_attr "type" "compare")
13557 (set_attr "length" "8,12,12,16")])
13558
13559 (define_split
13560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13561 (compare:CC
13562 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13563 (match_operand:DI 2 "reg_or_short_operand" ""))
13564 (match_operand:DI 3 "gpc_reg_operand" ""))
13565 (const_int 0)))
13566 (clobber (match_scratch:DI 4 ""))]
13567 "TARGET_64BIT && reload_completed"
13568 [(set (match_dup 4)
13569 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13570 (match_dup 3)))
13571 (set (match_dup 0)
13572 (compare:CC (match_dup 4)
13573 (const_int 0)))]
13574 "")
13575
13576 (define_insn ""
13577 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13578 (compare:CC
13579 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13580 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13581 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13582 (const_int 0)))
13583 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13584 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13585 "TARGET_32BIT"
13586 "@
13587 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13588 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13589 #
13590 #"
13591 [(set_attr "type" "compare")
13592 (set_attr "length" "8,12,12,16")])
13593
13594 (define_split
13595 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13596 (compare:CC
13597 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13598 (match_operand:SI 2 "reg_or_short_operand" ""))
13599 (match_operand:SI 3 "gpc_reg_operand" ""))
13600 (const_int 0)))
13601 (set (match_operand:SI 0 "gpc_reg_operand" "")
13602 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13603 "TARGET_32BIT && reload_completed"
13604 [(set (match_dup 0)
13605 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13606 (set (match_dup 4)
13607 (compare:CC (match_dup 0)
13608 (const_int 0)))]
13609 "")
13610
13611 (define_insn ""
13612 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13613 (compare:CC
13614 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13615 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13616 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13617 (const_int 0)))
13618 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13619 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13620 "TARGET_64BIT"
13621 "@
13622 addic %0,%1,%k2\;addze. %0,%3
13623 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13624 #
13625 #"
13626 [(set_attr "type" "compare")
13627 (set_attr "length" "8,12,12,16")])
13628
13629 (define_split
13630 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13631 (compare:CC
13632 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13633 (match_operand:DI 2 "reg_or_short_operand" ""))
13634 (match_operand:DI 3 "gpc_reg_operand" ""))
13635 (const_int 0)))
13636 (set (match_operand:DI 0 "gpc_reg_operand" "")
13637 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13638 "TARGET_64BIT && reload_completed"
13639 [(set (match_dup 0)
13640 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13641 (set (match_dup 4)
13642 (compare:CC (match_dup 0)
13643 (const_int 0)))]
13644 "")
13645
13646 (define_insn ""
13647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13648 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13649 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13650 "TARGET_32BIT"
13651 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13652 [(set_attr "type" "two")
13653 (set_attr "length" "8")])
13654
13655 (define_insn ""
13656 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13657 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13658 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13659 "TARGET_64BIT"
13660 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13661 [(set_attr "type" "two")
13662 (set_attr "length" "8")])
13663 \f
13664 ;; Define both directions of branch and return. If we need a reload
13665 ;; register, we'd rather use CR0 since it is much easier to copy a
13666 ;; register CC value to there.
13667
13668 (define_insn ""
13669 [(set (pc)
13670 (if_then_else (match_operator 1 "branch_comparison_operator"
13671 [(match_operand 2
13672 "cc_reg_operand" "y")
13673 (const_int 0)])
13674 (label_ref (match_operand 0 "" ""))
13675 (pc)))]
13676 ""
13677 "*
13678 {
13679 return output_cbranch (operands[1], \"%l0\", 0, insn);
13680 }"
13681 [(set_attr "type" "branch")])
13682
13683 (define_insn ""
13684 [(set (pc)
13685 (if_then_else (match_operator 0 "branch_comparison_operator"
13686 [(match_operand 1
13687 "cc_reg_operand" "y")
13688 (const_int 0)])
13689 (return)
13690 (pc)))]
13691 "direct_return ()"
13692 "*
13693 {
13694 return output_cbranch (operands[0], NULL, 0, insn);
13695 }"
13696 [(set_attr "type" "branch")
13697 (set_attr "length" "4")])
13698
13699 (define_insn ""
13700 [(set (pc)
13701 (if_then_else (match_operator 1 "branch_comparison_operator"
13702 [(match_operand 2
13703 "cc_reg_operand" "y")
13704 (const_int 0)])
13705 (pc)
13706 (label_ref (match_operand 0 "" ""))))]
13707 ""
13708 "*
13709 {
13710 return output_cbranch (operands[1], \"%l0\", 1, insn);
13711 }"
13712 [(set_attr "type" "branch")])
13713
13714 (define_insn ""
13715 [(set (pc)
13716 (if_then_else (match_operator 0 "branch_comparison_operator"
13717 [(match_operand 1
13718 "cc_reg_operand" "y")
13719 (const_int 0)])
13720 (pc)
13721 (return)))]
13722 "direct_return ()"
13723 "*
13724 {
13725 return output_cbranch (operands[0], NULL, 1, insn);
13726 }"
13727 [(set_attr "type" "branch")
13728 (set_attr "length" "4")])
13729
13730 ;; Logic on condition register values.
13731
13732 ; This pattern matches things like
13733 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13734 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13735 ; (const_int 1)))
13736 ; which are generated by the branch logic.
13737 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13738
13739 (define_insn "*cceq_ior_compare"
13740 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13741 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13742 [(match_operator:SI 2
13743 "branch_positive_comparison_operator"
13744 [(match_operand 3
13745 "cc_reg_operand" "y,y")
13746 (const_int 0)])
13747 (match_operator:SI 4
13748 "branch_positive_comparison_operator"
13749 [(match_operand 5
13750 "cc_reg_operand" "0,y")
13751 (const_int 0)])])
13752 (const_int 1)))]
13753 ""
13754 "cr%q1 %E0,%j2,%j4"
13755 [(set_attr "type" "cr_logical,delayed_cr")])
13756
13757 ; Why is the constant -1 here, but 1 in the previous pattern?
13758 ; Because ~1 has all but the low bit set.
13759 (define_insn ""
13760 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13761 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13762 [(not:SI (match_operator:SI 2
13763 "branch_positive_comparison_operator"
13764 [(match_operand 3
13765 "cc_reg_operand" "y,y")
13766 (const_int 0)]))
13767 (match_operator:SI 4
13768 "branch_positive_comparison_operator"
13769 [(match_operand 5
13770 "cc_reg_operand" "0,y")
13771 (const_int 0)])])
13772 (const_int -1)))]
13773 ""
13774 "cr%q1 %E0,%j2,%j4"
13775 [(set_attr "type" "cr_logical,delayed_cr")])
13776
13777 (define_insn "*cceq_rev_compare"
13778 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13779 (compare:CCEQ (match_operator:SI 1
13780 "branch_positive_comparison_operator"
13781 [(match_operand 2
13782 "cc_reg_operand" "0,y")
13783 (const_int 0)])
13784 (const_int 0)))]
13785 ""
13786 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13787 [(set_attr "type" "cr_logical,delayed_cr")])
13788
13789 ;; If we are comparing the result of two comparisons, this can be done
13790 ;; using creqv or crxor.
13791
13792 (define_insn_and_split ""
13793 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13794 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13795 [(match_operand 2 "cc_reg_operand" "y")
13796 (const_int 0)])
13797 (match_operator 3 "branch_comparison_operator"
13798 [(match_operand 4 "cc_reg_operand" "y")
13799 (const_int 0)])))]
13800 ""
13801 "#"
13802 ""
13803 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13804 (match_dup 5)))]
13805 "
13806 {
13807 int positive_1, positive_2;
13808
13809 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13810 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13811
13812 if (! positive_1)
13813 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13814 GET_CODE (operands[1])),
13815 SImode,
13816 operands[2], const0_rtx);
13817 else if (GET_MODE (operands[1]) != SImode)
13818 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13819 operands[2], const0_rtx);
13820
13821 if (! positive_2)
13822 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13823 GET_CODE (operands[3])),
13824 SImode,
13825 operands[4], const0_rtx);
13826 else if (GET_MODE (operands[3]) != SImode)
13827 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13828 operands[4], const0_rtx);
13829
13830 if (positive_1 == positive_2)
13831 {
13832 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13833 operands[5] = constm1_rtx;
13834 }
13835 else
13836 {
13837 operands[5] = const1_rtx;
13838 }
13839 }")
13840
13841 ;; Unconditional branch and return.
13842
13843 (define_insn "jump"
13844 [(set (pc)
13845 (label_ref (match_operand 0 "" "")))]
13846 ""
13847 "b %l0"
13848 [(set_attr "type" "branch")])
13849
13850 (define_insn "return"
13851 [(return)]
13852 "direct_return ()"
13853 "{br|blr}"
13854 [(set_attr "type" "jmpreg")])
13855
13856 (define_expand "indirect_jump"
13857 [(set (pc) (match_operand 0 "register_operand" ""))]
13858 ""
13859 "
13860 {
13861 if (TARGET_32BIT)
13862 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13863 else
13864 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13865 DONE;
13866 }")
13867
13868 (define_insn "indirect_jumpsi"
13869 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13870 "TARGET_32BIT"
13871 "@
13872 bctr
13873 {br|blr}"
13874 [(set_attr "type" "jmpreg")])
13875
13876 (define_insn "indirect_jumpdi"
13877 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13878 "TARGET_64BIT"
13879 "@
13880 bctr
13881 blr"
13882 [(set_attr "type" "jmpreg")])
13883
13884 ;; Table jump for switch statements:
13885 (define_expand "tablejump"
13886 [(use (match_operand 0 "" ""))
13887 (use (label_ref (match_operand 1 "" "")))]
13888 ""
13889 "
13890 {
13891 if (TARGET_32BIT)
13892 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13893 else
13894 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13895 DONE;
13896 }")
13897
13898 (define_expand "tablejumpsi"
13899 [(set (match_dup 3)
13900 (plus:SI (match_operand:SI 0 "" "")
13901 (match_dup 2)))
13902 (parallel [(set (pc) (match_dup 3))
13903 (use (label_ref (match_operand 1 "" "")))])]
13904 "TARGET_32BIT"
13905 "
13906 { operands[0] = force_reg (SImode, operands[0]);
13907 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13908 operands[3] = gen_reg_rtx (SImode);
13909 }")
13910
13911 (define_expand "tablejumpdi"
13912 [(set (match_dup 4)
13913 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13914 (set (match_dup 3)
13915 (plus:DI (match_dup 4)
13916 (match_dup 2)))
13917 (parallel [(set (pc) (match_dup 3))
13918 (use (label_ref (match_operand 1 "" "")))])]
13919 "TARGET_64BIT"
13920 "
13921 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13922 operands[3] = gen_reg_rtx (DImode);
13923 operands[4] = gen_reg_rtx (DImode);
13924 }")
13925
13926 (define_insn ""
13927 [(set (pc)
13928 (match_operand:SI 0 "register_operand" "c,*l"))
13929 (use (label_ref (match_operand 1 "" "")))]
13930 "TARGET_32BIT"
13931 "@
13932 bctr
13933 {br|blr}"
13934 [(set_attr "type" "jmpreg")])
13935
13936 (define_insn ""
13937 [(set (pc)
13938 (match_operand:DI 0 "register_operand" "c,*l"))
13939 (use (label_ref (match_operand 1 "" "")))]
13940 "TARGET_64BIT"
13941 "@
13942 bctr
13943 blr"
13944 [(set_attr "type" "jmpreg")])
13945
13946 (define_insn "nop"
13947 [(const_int 0)]
13948 ""
13949 "{cror 0,0,0|nop}")
13950 \f
13951 ;; Define the subtract-one-and-jump insns, starting with the template
13952 ;; so loop.c knows what to generate.
13953
13954 (define_expand "doloop_end"
13955 [(use (match_operand 0 "" "")) ; loop pseudo
13956 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13957 (use (match_operand 2 "" "")) ; max iterations
13958 (use (match_operand 3 "" "")) ; loop level
13959 (use (match_operand 4 "" ""))] ; label
13960 ""
13961 "
13962 {
13963 /* Only use this on innermost loops. */
13964 if (INTVAL (operands[3]) > 1)
13965 FAIL;
13966 if (TARGET_64BIT)
13967 {
13968 if (GET_MODE (operands[0]) != DImode)
13969 FAIL;
13970 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13971 }
13972 else
13973 {
13974 if (GET_MODE (operands[0]) != SImode)
13975 FAIL;
13976 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13977 }
13978 DONE;
13979 }")
13980
13981 (define_expand "ctrsi"
13982 [(parallel [(set (pc)
13983 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13984 (const_int 1))
13985 (label_ref (match_operand 1 "" ""))
13986 (pc)))
13987 (set (match_dup 0)
13988 (plus:SI (match_dup 0)
13989 (const_int -1)))
13990 (clobber (match_scratch:CC 2 ""))
13991 (clobber (match_scratch:SI 3 ""))])]
13992 "TARGET_32BIT"
13993 "")
13994
13995 (define_expand "ctrdi"
13996 [(parallel [(set (pc)
13997 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13998 (const_int 1))
13999 (label_ref (match_operand 1 "" ""))
14000 (pc)))
14001 (set (match_dup 0)
14002 (plus:DI (match_dup 0)
14003 (const_int -1)))
14004 (clobber (match_scratch:CC 2 ""))
14005 (clobber (match_scratch:DI 3 ""))])]
14006 "TARGET_64BIT"
14007 "")
14008
14009 ;; We need to be able to do this for any operand, including MEM, or we
14010 ;; will cause reload to blow up since we don't allow output reloads on
14011 ;; JUMP_INSNs.
14012 ;; For the length attribute to be calculated correctly, the
14013 ;; label MUST be operand 0.
14014
14015 (define_insn "*ctrsi_internal1"
14016 [(set (pc)
14017 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14018 (const_int 1))
14019 (label_ref (match_operand 0 "" ""))
14020 (pc)))
14021 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14022 (plus:SI (match_dup 1)
14023 (const_int -1)))
14024 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14025 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14026 "TARGET_32BIT"
14027 "*
14028 {
14029 if (which_alternative != 0)
14030 return \"#\";
14031 else if (get_attr_length (insn) == 4)
14032 return \"{bdn|bdnz} %l0\";
14033 else
14034 return \"bdz $+8\;b %l0\";
14035 }"
14036 [(set_attr "type" "branch")
14037 (set_attr "length" "*,12,16,16")])
14038
14039 (define_insn "*ctrsi_internal2"
14040 [(set (pc)
14041 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14042 (const_int 1))
14043 (pc)
14044 (label_ref (match_operand 0 "" ""))))
14045 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14046 (plus:SI (match_dup 1)
14047 (const_int -1)))
14048 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14049 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14050 "TARGET_32BIT"
14051 "*
14052 {
14053 if (which_alternative != 0)
14054 return \"#\";
14055 else if (get_attr_length (insn) == 4)
14056 return \"bdz %l0\";
14057 else
14058 return \"{bdn|bdnz} $+8\;b %l0\";
14059 }"
14060 [(set_attr "type" "branch")
14061 (set_attr "length" "*,12,16,16")])
14062
14063 (define_insn "*ctrdi_internal1"
14064 [(set (pc)
14065 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14066 (const_int 1))
14067 (label_ref (match_operand 0 "" ""))
14068 (pc)))
14069 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14070 (plus:DI (match_dup 1)
14071 (const_int -1)))
14072 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14073 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14074 "TARGET_64BIT"
14075 "*
14076 {
14077 if (which_alternative != 0)
14078 return \"#\";
14079 else if (get_attr_length (insn) == 4)
14080 return \"{bdn|bdnz} %l0\";
14081 else
14082 return \"bdz $+8\;b %l0\";
14083 }"
14084 [(set_attr "type" "branch")
14085 (set_attr "length" "*,12,16,16")])
14086
14087 (define_insn "*ctrdi_internal2"
14088 [(set (pc)
14089 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14090 (const_int 1))
14091 (pc)
14092 (label_ref (match_operand 0 "" ""))))
14093 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14094 (plus:DI (match_dup 1)
14095 (const_int -1)))
14096 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14097 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14098 "TARGET_64BIT"
14099 "*
14100 {
14101 if (which_alternative != 0)
14102 return \"#\";
14103 else if (get_attr_length (insn) == 4)
14104 return \"bdz %l0\";
14105 else
14106 return \"{bdn|bdnz} $+8\;b %l0\";
14107 }"
14108 [(set_attr "type" "branch")
14109 (set_attr "length" "*,12,16,16")])
14110
14111 ;; Similar but use EQ
14112
14113 (define_insn "*ctrsi_internal5"
14114 [(set (pc)
14115 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14116 (const_int 1))
14117 (label_ref (match_operand 0 "" ""))
14118 (pc)))
14119 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14120 (plus:SI (match_dup 1)
14121 (const_int -1)))
14122 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14123 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14124 "TARGET_32BIT"
14125 "*
14126 {
14127 if (which_alternative != 0)
14128 return \"#\";
14129 else if (get_attr_length (insn) == 4)
14130 return \"bdz %l0\";
14131 else
14132 return \"{bdn|bdnz} $+8\;b %l0\";
14133 }"
14134 [(set_attr "type" "branch")
14135 (set_attr "length" "*,12,16,16")])
14136
14137 (define_insn "*ctrsi_internal6"
14138 [(set (pc)
14139 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14140 (const_int 1))
14141 (pc)
14142 (label_ref (match_operand 0 "" ""))))
14143 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14144 (plus:SI (match_dup 1)
14145 (const_int -1)))
14146 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14147 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14148 "TARGET_32BIT"
14149 "*
14150 {
14151 if (which_alternative != 0)
14152 return \"#\";
14153 else if (get_attr_length (insn) == 4)
14154 return \"{bdn|bdnz} %l0\";
14155 else
14156 return \"bdz $+8\;b %l0\";
14157 }"
14158 [(set_attr "type" "branch")
14159 (set_attr "length" "*,12,16,16")])
14160
14161 (define_insn "*ctrdi_internal5"
14162 [(set (pc)
14163 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14164 (const_int 1))
14165 (label_ref (match_operand 0 "" ""))
14166 (pc)))
14167 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14168 (plus:DI (match_dup 1)
14169 (const_int -1)))
14170 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14171 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14172 "TARGET_64BIT"
14173 "*
14174 {
14175 if (which_alternative != 0)
14176 return \"#\";
14177 else if (get_attr_length (insn) == 4)
14178 return \"bdz %l0\";
14179 else
14180 return \"{bdn|bdnz} $+8\;b %l0\";
14181 }"
14182 [(set_attr "type" "branch")
14183 (set_attr "length" "*,12,16,16")])
14184
14185 (define_insn "*ctrdi_internal6"
14186 [(set (pc)
14187 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14188 (const_int 1))
14189 (pc)
14190 (label_ref (match_operand 0 "" ""))))
14191 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14192 (plus:DI (match_dup 1)
14193 (const_int -1)))
14194 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14195 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14196 "TARGET_64BIT"
14197 "*
14198 {
14199 if (which_alternative != 0)
14200 return \"#\";
14201 else if (get_attr_length (insn) == 4)
14202 return \"{bdn|bdnz} %l0\";
14203 else
14204 return \"bdz $+8\;b %l0\";
14205 }"
14206 [(set_attr "type" "branch")
14207 (set_attr "length" "*,12,16,16")])
14208
14209 ;; Now the splitters if we could not allocate the CTR register
14210
14211 (define_split
14212 [(set (pc)
14213 (if_then_else (match_operator 2 "comparison_operator"
14214 [(match_operand:SI 1 "gpc_reg_operand" "")
14215 (const_int 1)])
14216 (match_operand 5 "" "")
14217 (match_operand 6 "" "")))
14218 (set (match_operand:SI 0 "gpc_reg_operand" "")
14219 (plus:SI (match_dup 1)
14220 (const_int -1)))
14221 (clobber (match_scratch:CC 3 ""))
14222 (clobber (match_scratch:SI 4 ""))]
14223 "TARGET_32BIT && reload_completed"
14224 [(parallel [(set (match_dup 3)
14225 (compare:CC (plus:SI (match_dup 1)
14226 (const_int -1))
14227 (const_int 0)))
14228 (set (match_dup 0)
14229 (plus:SI (match_dup 1)
14230 (const_int -1)))])
14231 (set (pc) (if_then_else (match_dup 7)
14232 (match_dup 5)
14233 (match_dup 6)))]
14234 "
14235 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14236 operands[3], const0_rtx); }")
14237
14238 (define_split
14239 [(set (pc)
14240 (if_then_else (match_operator 2 "comparison_operator"
14241 [(match_operand:SI 1 "gpc_reg_operand" "")
14242 (const_int 1)])
14243 (match_operand 5 "" "")
14244 (match_operand 6 "" "")))
14245 (set (match_operand:SI 0 "nonimmediate_operand" "")
14246 (plus:SI (match_dup 1) (const_int -1)))
14247 (clobber (match_scratch:CC 3 ""))
14248 (clobber (match_scratch:SI 4 ""))]
14249 "TARGET_32BIT && reload_completed
14250 && ! gpc_reg_operand (operands[0], SImode)"
14251 [(parallel [(set (match_dup 3)
14252 (compare:CC (plus:SI (match_dup 1)
14253 (const_int -1))
14254 (const_int 0)))
14255 (set (match_dup 4)
14256 (plus:SI (match_dup 1)
14257 (const_int -1)))])
14258 (set (match_dup 0)
14259 (match_dup 4))
14260 (set (pc) (if_then_else (match_dup 7)
14261 (match_dup 5)
14262 (match_dup 6)))]
14263 "
14264 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14265 operands[3], const0_rtx); }")
14266 (define_split
14267 [(set (pc)
14268 (if_then_else (match_operator 2 "comparison_operator"
14269 [(match_operand:DI 1 "gpc_reg_operand" "")
14270 (const_int 1)])
14271 (match_operand 5 "" "")
14272 (match_operand 6 "" "")))
14273 (set (match_operand:DI 0 "gpc_reg_operand" "")
14274 (plus:DI (match_dup 1)
14275 (const_int -1)))
14276 (clobber (match_scratch:CC 3 ""))
14277 (clobber (match_scratch:DI 4 ""))]
14278 "TARGET_64BIT && reload_completed"
14279 [(parallel [(set (match_dup 3)
14280 (compare:CC (plus:DI (match_dup 1)
14281 (const_int -1))
14282 (const_int 0)))
14283 (set (match_dup 0)
14284 (plus:DI (match_dup 1)
14285 (const_int -1)))])
14286 (set (pc) (if_then_else (match_dup 7)
14287 (match_dup 5)
14288 (match_dup 6)))]
14289 "
14290 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14291 operands[3], const0_rtx); }")
14292
14293 (define_split
14294 [(set (pc)
14295 (if_then_else (match_operator 2 "comparison_operator"
14296 [(match_operand:DI 1 "gpc_reg_operand" "")
14297 (const_int 1)])
14298 (match_operand 5 "" "")
14299 (match_operand 6 "" "")))
14300 (set (match_operand:DI 0 "nonimmediate_operand" "")
14301 (plus:DI (match_dup 1) (const_int -1)))
14302 (clobber (match_scratch:CC 3 ""))
14303 (clobber (match_scratch:DI 4 ""))]
14304 "TARGET_64BIT && reload_completed
14305 && ! gpc_reg_operand (operands[0], DImode)"
14306 [(parallel [(set (match_dup 3)
14307 (compare:CC (plus:DI (match_dup 1)
14308 (const_int -1))
14309 (const_int 0)))
14310 (set (match_dup 4)
14311 (plus:DI (match_dup 1)
14312 (const_int -1)))])
14313 (set (match_dup 0)
14314 (match_dup 4))
14315 (set (pc) (if_then_else (match_dup 7)
14316 (match_dup 5)
14317 (match_dup 6)))]
14318 "
14319 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14320 operands[3], const0_rtx); }")
14321 \f
14322 (define_insn "trap"
14323 [(trap_if (const_int 1) (const_int 0))]
14324 ""
14325 "{t 31,0,0|trap}")
14326
14327 (define_expand "conditional_trap"
14328 [(trap_if (match_operator 0 "trap_comparison_operator"
14329 [(match_dup 2) (match_dup 3)])
14330 (match_operand 1 "const_int_operand" ""))]
14331 ""
14332 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14333 operands[2] = rs6000_compare_op0;
14334 operands[3] = rs6000_compare_op1;")
14335
14336 (define_insn ""
14337 [(trap_if (match_operator 0 "trap_comparison_operator"
14338 [(match_operand:SI 1 "register_operand" "r")
14339 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14340 (const_int 0))]
14341 ""
14342 "{t|tw}%V0%I2 %1,%2")
14343
14344 (define_insn ""
14345 [(trap_if (match_operator 0 "trap_comparison_operator"
14346 [(match_operand:DI 1 "register_operand" "r")
14347 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14348 (const_int 0))]
14349 "TARGET_POWERPC64"
14350 "td%V0%I2 %1,%2")
14351 \f
14352 ;; Insns related to generating the function prologue and epilogue.
14353
14354 (define_expand "prologue"
14355 [(use (const_int 0))]
14356 "TARGET_SCHED_PROLOG"
14357 "
14358 {
14359 rs6000_emit_prologue ();
14360 DONE;
14361 }")
14362
14363 (define_insn "*movesi_from_cr_one"
14364 [(match_parallel 0 "mfcr_operation"
14365 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14366 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14367 (match_operand 3 "immediate_operand" "n")]
14368 UNSPEC_MOVESI_FROM_CR))])]
14369 "TARGET_MFCRF"
14370 "*
14371 {
14372 int mask = 0;
14373 int i;
14374 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14375 {
14376 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14377 operands[4] = GEN_INT (mask);
14378 output_asm_insn (\"mfcr %1,%4\", operands);
14379 }
14380 return \"\";
14381 }"
14382 [(set_attr "type" "mfcrf")])
14383
14384 (define_insn "movesi_from_cr"
14385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14386 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14387 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14388 UNSPEC_MOVESI_FROM_CR))]
14389 ""
14390 "mfcr %0"
14391 [(set_attr "type" "mfcr")])
14392
14393 (define_insn "*stmw"
14394 [(match_parallel 0 "stmw_operation"
14395 [(set (match_operand:SI 1 "memory_operand" "=m")
14396 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14397 "TARGET_MULTIPLE"
14398 "{stm|stmw} %2,%1")
14399
14400 (define_insn "*save_fpregs_si"
14401 [(match_parallel 0 "any_parallel_operand"
14402 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14403 (use (match_operand:SI 2 "call_operand" "s"))
14404 (set (match_operand:DF 3 "memory_operand" "=m")
14405 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14406 "TARGET_32BIT"
14407 "bl %z2"
14408 [(set_attr "type" "branch")
14409 (set_attr "length" "4")])
14410
14411 (define_insn "*save_fpregs_di"
14412 [(match_parallel 0 "any_parallel_operand"
14413 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14414 (use (match_operand:DI 2 "call_operand" "s"))
14415 (set (match_operand:DF 3 "memory_operand" "=m")
14416 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14417 "TARGET_64BIT"
14418 "bl %z2"
14419 [(set_attr "type" "branch")
14420 (set_attr "length" "4")])
14421
14422 ; These are to explain that changes to the stack pointer should
14423 ; not be moved over stores to stack memory.
14424 (define_insn "stack_tie"
14425 [(set (match_operand:BLK 0 "memory_operand" "+m")
14426 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14427 ""
14428 ""
14429 [(set_attr "length" "0")])
14430
14431
14432 (define_expand "epilogue"
14433 [(use (const_int 0))]
14434 "TARGET_SCHED_PROLOG"
14435 "
14436 {
14437 rs6000_emit_epilogue (FALSE);
14438 DONE;
14439 }")
14440
14441 ; On some processors, doing the mtcrf one CC register at a time is
14442 ; faster (like on the 604e). On others, doing them all at once is
14443 ; faster; for instance, on the 601 and 750.
14444
14445 (define_expand "movsi_to_cr_one"
14446 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14447 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14448 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14449 ""
14450 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14451
14452 (define_insn "*movsi_to_cr"
14453 [(match_parallel 0 "mtcrf_operation"
14454 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14455 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14456 (match_operand 3 "immediate_operand" "n")]
14457 UNSPEC_MOVESI_TO_CR))])]
14458 ""
14459 "*
14460 {
14461 int mask = 0;
14462 int i;
14463 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14464 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14465 operands[4] = GEN_INT (mask);
14466 return \"mtcrf %4,%2\";
14467 }"
14468 [(set_attr "type" "mtcr")])
14469
14470 (define_insn "*mtcrfsi"
14471 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14472 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14473 (match_operand 2 "immediate_operand" "n")]
14474 UNSPEC_MOVESI_TO_CR))]
14475 "GET_CODE (operands[0]) == REG
14476 && CR_REGNO_P (REGNO (operands[0]))
14477 && GET_CODE (operands[2]) == CONST_INT
14478 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14479 "mtcrf %R0,%1"
14480 [(set_attr "type" "mtcr")])
14481
14482 ; The load-multiple instructions have similar properties.
14483 ; Note that "load_multiple" is a name known to the machine-independent
14484 ; code that actually corresponds to the powerpc load-string.
14485
14486 (define_insn "*lmw"
14487 [(match_parallel 0 "lmw_operation"
14488 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14489 (match_operand:SI 2 "memory_operand" "m"))])]
14490 "TARGET_MULTIPLE"
14491 "{lm|lmw} %1,%2")
14492
14493 (define_insn "*return_internal_si"
14494 [(return)
14495 (use (match_operand:SI 0 "register_operand" "lc"))]
14496 "TARGET_32BIT"
14497 "b%T0"
14498 [(set_attr "type" "jmpreg")])
14499
14500 (define_insn "*return_internal_di"
14501 [(return)
14502 (use (match_operand:DI 0 "register_operand" "lc"))]
14503 "TARGET_64BIT"
14504 "b%T0"
14505 [(set_attr "type" "jmpreg")])
14506
14507 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14508 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14509
14510 (define_insn "*return_and_restore_fpregs_si"
14511 [(match_parallel 0 "any_parallel_operand"
14512 [(return)
14513 (use (match_operand:SI 1 "register_operand" "l"))
14514 (use (match_operand:SI 2 "call_operand" "s"))
14515 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14516 (match_operand:DF 4 "memory_operand" "m"))])]
14517 "TARGET_32BIT"
14518 "b %z2")
14519
14520 (define_insn "*return_and_restore_fpregs_di"
14521 [(match_parallel 0 "any_parallel_operand"
14522 [(return)
14523 (use (match_operand:DI 1 "register_operand" "l"))
14524 (use (match_operand:DI 2 "call_operand" "s"))
14525 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14526 (match_operand:DF 4 "memory_operand" "m"))])]
14527 "TARGET_64BIT"
14528 "b %z2")
14529
14530 ; This is used in compiling the unwind routines.
14531 (define_expand "eh_return"
14532 [(use (match_operand 0 "general_operand" ""))]
14533 ""
14534 "
14535 {
14536 if (TARGET_32BIT)
14537 emit_insn (gen_eh_set_lr_si (operands[0]));
14538 else
14539 emit_insn (gen_eh_set_lr_di (operands[0]));
14540 DONE;
14541 }")
14542
14543 ; We can't expand this before we know where the link register is stored.
14544 (define_insn "eh_set_lr_si"
14545 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14546 UNSPECV_EH_RR)
14547 (clobber (match_scratch:SI 1 "=&b"))]
14548 "TARGET_32BIT"
14549 "#")
14550
14551 (define_insn "eh_set_lr_di"
14552 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14553 UNSPECV_EH_RR)
14554 (clobber (match_scratch:DI 1 "=&b"))]
14555 "TARGET_64BIT"
14556 "#")
14557
14558 (define_split
14559 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14560 (clobber (match_scratch 1 ""))]
14561 "reload_completed"
14562 [(const_int 0)]
14563 "
14564 {
14565 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14566 DONE;
14567 }")
14568
14569 (define_insn "prefetch"
14570 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14571 (match_operand:SI 1 "const_int_operand" "n")
14572 (match_operand:SI 2 "const_int_operand" "n"))]
14573 "TARGET_POWERPC"
14574 "*
14575 {
14576 if (GET_CODE (operands[0]) == REG)
14577 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14578 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14579 }"
14580 [(set_attr "type" "load")])
14581
14582 (include "altivec.md")
14583 (include "spe.md")