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[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5
6 ;; This file is part of GCC.
7
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
12
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; UNSPEC usage
27 ;;
28
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
54 ])
55
56 ;;
57 ;; UNSPEC_VOLATILE usage
58 ;;
59
60 (define_constants
61 [(UNSPECV_BLOCK 0)
62 (UNSPECV_EH_RR 9) ; eh_reg_restore
63 ])
64 \f
65 ;; Define an insn type attribute. This is used in function unit delay
66 ;; computations.
67 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
68 (const_string "integer"))
69
70 ;; Length (in bytes).
71 ; '(pc)' in the following doesn't include the instruction itself; it is
72 ; calculated as if the instruction had zero size.
73 (define_attr "length" ""
74 (if_then_else (eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
76 (const_int -32768))
77 (lt (minus (match_dup 0) (pc))
78 (const_int 32764)))
79 (const_int 4)
80 (const_int 8))
81 (const_int 4)))
82
83 ;; Processor type -- this attribute must exactly match the processor_type
84 ;; enumeration in rs6000.h.
85
86 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
87 (const (symbol_ref "rs6000_cpu_attr")))
88
89 (automata_option "ndfa")
90
91 (include "rios1.md")
92 (include "rios2.md")
93 (include "rs64.md")
94 (include "mpc.md")
95 (include "40x.md")
96 (include "440.md")
97 (include "603.md")
98 (include "6xx.md")
99 (include "7xx.md")
100 (include "7450.md")
101 (include "8540.md")
102 (include "power4.md")
103 (include "power5.md")
104
105 \f
106 ;; Start with fixed-point load and store insns. Here we put only the more
107 ;; complex forms. Basic data transfer is done later.
108
109 (define_expand "zero_extendqidi2"
110 [(set (match_operand:DI 0 "gpc_reg_operand" "")
111 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
112 "TARGET_POWERPC64"
113 "")
114
115 (define_insn ""
116 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
117 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
118 "TARGET_POWERPC64"
119 "@
120 lbz%U1%X1 %0,%1
121 rldicl %0,%1,0,56"
122 [(set_attr "type" "load,*")])
123
124 (define_insn ""
125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
126 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
127 (const_int 0)))
128 (clobber (match_scratch:DI 2 "=r,r"))]
129 "TARGET_64BIT"
130 "@
131 rldicl. %2,%1,0,56
132 #"
133 [(set_attr "type" "compare")
134 (set_attr "length" "4,8")])
135
136 (define_split
137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
138 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
139 (const_int 0)))
140 (clobber (match_scratch:DI 2 ""))]
141 "TARGET_POWERPC64 && reload_completed"
142 [(set (match_dup 2)
143 (zero_extend:DI (match_dup 1)))
144 (set (match_dup 0)
145 (compare:CC (match_dup 2)
146 (const_int 0)))]
147 "")
148
149 (define_insn ""
150 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
151 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
152 (const_int 0)))
153 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
154 (zero_extend:DI (match_dup 1)))]
155 "TARGET_64BIT"
156 "@
157 rldicl. %0,%1,0,56
158 #"
159 [(set_attr "type" "compare")
160 (set_attr "length" "4,8")])
161
162 (define_split
163 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
164 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
165 (const_int 0)))
166 (set (match_operand:DI 0 "gpc_reg_operand" "")
167 (zero_extend:DI (match_dup 1)))]
168 "TARGET_POWERPC64 && reload_completed"
169 [(set (match_dup 0)
170 (zero_extend:DI (match_dup 1)))
171 (set (match_dup 2)
172 (compare:CC (match_dup 0)
173 (const_int 0)))]
174 "")
175
176 (define_insn "extendqidi2"
177 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
178 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
179 "TARGET_POWERPC64"
180 "extsb %0,%1")
181
182 (define_insn ""
183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
184 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
185 (const_int 0)))
186 (clobber (match_scratch:DI 2 "=r,r"))]
187 "TARGET_64BIT"
188 "@
189 extsb. %2,%1
190 #"
191 [(set_attr "type" "compare")
192 (set_attr "length" "4,8")])
193
194 (define_split
195 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
196 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
197 (const_int 0)))
198 (clobber (match_scratch:DI 2 ""))]
199 "TARGET_POWERPC64 && reload_completed"
200 [(set (match_dup 2)
201 (sign_extend:DI (match_dup 1)))
202 (set (match_dup 0)
203 (compare:CC (match_dup 2)
204 (const_int 0)))]
205 "")
206
207 (define_insn ""
208 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
209 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
210 (const_int 0)))
211 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
212 (sign_extend:DI (match_dup 1)))]
213 "TARGET_64BIT"
214 "@
215 extsb. %0,%1
216 #"
217 [(set_attr "type" "compare")
218 (set_attr "length" "4,8")])
219
220 (define_split
221 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
222 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
223 (const_int 0)))
224 (set (match_operand:DI 0 "gpc_reg_operand" "")
225 (sign_extend:DI (match_dup 1)))]
226 "TARGET_POWERPC64 && reload_completed"
227 [(set (match_dup 0)
228 (sign_extend:DI (match_dup 1)))
229 (set (match_dup 2)
230 (compare:CC (match_dup 0)
231 (const_int 0)))]
232 "")
233
234 (define_expand "zero_extendhidi2"
235 [(set (match_operand:DI 0 "gpc_reg_operand" "")
236 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
237 "TARGET_POWERPC64"
238 "")
239
240 (define_insn ""
241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
242 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
243 "TARGET_POWERPC64"
244 "@
245 lhz%U1%X1 %0,%1
246 rldicl %0,%1,0,48"
247 [(set_attr "type" "load,*")])
248
249 (define_insn ""
250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
251 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
252 (const_int 0)))
253 (clobber (match_scratch:DI 2 "=r,r"))]
254 "TARGET_64BIT"
255 "@
256 rldicl. %2,%1,0,48
257 #"
258 [(set_attr "type" "compare")
259 (set_attr "length" "4,8")])
260
261 (define_split
262 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
263 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
264 (const_int 0)))
265 (clobber (match_scratch:DI 2 ""))]
266 "TARGET_POWERPC64 && reload_completed"
267 [(set (match_dup 2)
268 (zero_extend:DI (match_dup 1)))
269 (set (match_dup 0)
270 (compare:CC (match_dup 2)
271 (const_int 0)))]
272 "")
273
274 (define_insn ""
275 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
276 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
277 (const_int 0)))
278 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
279 (zero_extend:DI (match_dup 1)))]
280 "TARGET_64BIT"
281 "@
282 rldicl. %0,%1,0,48
283 #"
284 [(set_attr "type" "compare")
285 (set_attr "length" "4,8")])
286
287 (define_split
288 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
289 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
290 (const_int 0)))
291 (set (match_operand:DI 0 "gpc_reg_operand" "")
292 (zero_extend:DI (match_dup 1)))]
293 "TARGET_POWERPC64 && reload_completed"
294 [(set (match_dup 0)
295 (zero_extend:DI (match_dup 1)))
296 (set (match_dup 2)
297 (compare:CC (match_dup 0)
298 (const_int 0)))]
299 "")
300
301 (define_expand "extendhidi2"
302 [(set (match_operand:DI 0 "gpc_reg_operand" "")
303 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
304 "TARGET_POWERPC64"
305 "")
306
307 (define_insn ""
308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
309 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
310 "TARGET_POWERPC64"
311 "@
312 lha%U1%X1 %0,%1
313 extsh %0,%1"
314 [(set_attr "type" "load_ext,*")])
315
316 (define_insn ""
317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
319 (const_int 0)))
320 (clobber (match_scratch:DI 2 "=r,r"))]
321 "TARGET_64BIT"
322 "@
323 extsh. %2,%1
324 #"
325 [(set_attr "type" "compare")
326 (set_attr "length" "4,8")])
327
328 (define_split
329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
330 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
331 (const_int 0)))
332 (clobber (match_scratch:DI 2 ""))]
333 "TARGET_POWERPC64 && reload_completed"
334 [(set (match_dup 2)
335 (sign_extend:DI (match_dup 1)))
336 (set (match_dup 0)
337 (compare:CC (match_dup 2)
338 (const_int 0)))]
339 "")
340
341 (define_insn ""
342 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
343 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
344 (const_int 0)))
345 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
346 (sign_extend:DI (match_dup 1)))]
347 "TARGET_64BIT"
348 "@
349 extsh. %0,%1
350 #"
351 [(set_attr "type" "compare")
352 (set_attr "length" "4,8")])
353
354 (define_split
355 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
356 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
357 (const_int 0)))
358 (set (match_operand:DI 0 "gpc_reg_operand" "")
359 (sign_extend:DI (match_dup 1)))]
360 "TARGET_POWERPC64 && reload_completed"
361 [(set (match_dup 0)
362 (sign_extend:DI (match_dup 1)))
363 (set (match_dup 2)
364 (compare:CC (match_dup 0)
365 (const_int 0)))]
366 "")
367
368 (define_expand "zero_extendsidi2"
369 [(set (match_operand:DI 0 "gpc_reg_operand" "")
370 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
371 "TARGET_POWERPC64"
372 "")
373
374 (define_insn ""
375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
376 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
377 "TARGET_POWERPC64"
378 "@
379 lwz%U1%X1 %0,%1
380 rldicl %0,%1,0,32"
381 [(set_attr "type" "load,*")])
382
383 (define_insn ""
384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
385 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
386 (const_int 0)))
387 (clobber (match_scratch:DI 2 "=r,r"))]
388 "TARGET_64BIT"
389 "@
390 rldicl. %2,%1,0,32
391 #"
392 [(set_attr "type" "compare")
393 (set_attr "length" "4,8")])
394
395 (define_split
396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
397 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
398 (const_int 0)))
399 (clobber (match_scratch:DI 2 ""))]
400 "TARGET_POWERPC64 && reload_completed"
401 [(set (match_dup 2)
402 (zero_extend:DI (match_dup 1)))
403 (set (match_dup 0)
404 (compare:CC (match_dup 2)
405 (const_int 0)))]
406 "")
407
408 (define_insn ""
409 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
410 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
411 (const_int 0)))
412 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
413 (zero_extend:DI (match_dup 1)))]
414 "TARGET_64BIT"
415 "@
416 rldicl. %0,%1,0,32
417 #"
418 [(set_attr "type" "compare")
419 (set_attr "length" "4,8")])
420
421 (define_split
422 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
423 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
424 (const_int 0)))
425 (set (match_operand:DI 0 "gpc_reg_operand" "")
426 (zero_extend:DI (match_dup 1)))]
427 "TARGET_POWERPC64 && reload_completed"
428 [(set (match_dup 0)
429 (zero_extend:DI (match_dup 1)))
430 (set (match_dup 2)
431 (compare:CC (match_dup 0)
432 (const_int 0)))]
433 "")
434
435 (define_expand "extendsidi2"
436 [(set (match_operand:DI 0 "gpc_reg_operand" "")
437 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
438 "TARGET_POWERPC64"
439 "")
440
441 (define_insn ""
442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
443 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
444 "TARGET_POWERPC64"
445 "@
446 lwa%U1%X1 %0,%1
447 extsw %0,%1"
448 [(set_attr "type" "load_ext,*")])
449
450 (define_insn ""
451 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
452 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
453 (const_int 0)))
454 (clobber (match_scratch:DI 2 "=r,r"))]
455 "TARGET_64BIT"
456 "@
457 extsw. %2,%1
458 #"
459 [(set_attr "type" "compare")
460 (set_attr "length" "4,8")])
461
462 (define_split
463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
464 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
465 (const_int 0)))
466 (clobber (match_scratch:DI 2 ""))]
467 "TARGET_POWERPC64 && reload_completed"
468 [(set (match_dup 2)
469 (sign_extend:DI (match_dup 1)))
470 (set (match_dup 0)
471 (compare:CC (match_dup 2)
472 (const_int 0)))]
473 "")
474
475 (define_insn ""
476 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
477 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
478 (const_int 0)))
479 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
480 (sign_extend:DI (match_dup 1)))]
481 "TARGET_64BIT"
482 "@
483 extsw. %0,%1
484 #"
485 [(set_attr "type" "compare")
486 (set_attr "length" "4,8")])
487
488 (define_split
489 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
490 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
491 (const_int 0)))
492 (set (match_operand:DI 0 "gpc_reg_operand" "")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_POWERPC64 && reload_completed"
495 [(set (match_dup 0)
496 (sign_extend:DI (match_dup 1)))
497 (set (match_dup 2)
498 (compare:CC (match_dup 0)
499 (const_int 0)))]
500 "")
501
502 (define_expand "zero_extendqisi2"
503 [(set (match_operand:SI 0 "gpc_reg_operand" "")
504 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
505 ""
506 "")
507
508 (define_insn ""
509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
510 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
511 ""
512 "@
513 lbz%U1%X1 %0,%1
514 {rlinm|rlwinm} %0,%1,0,0xff"
515 [(set_attr "type" "load,*")])
516
517 (define_insn ""
518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
519 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
520 (const_int 0)))
521 (clobber (match_scratch:SI 2 "=r,r"))]
522 ""
523 "@
524 {andil.|andi.} %2,%1,0xff
525 #"
526 [(set_attr "type" "compare")
527 (set_attr "length" "4,8")])
528
529 (define_split
530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
531 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
532 (const_int 0)))
533 (clobber (match_scratch:SI 2 ""))]
534 "reload_completed"
535 [(set (match_dup 2)
536 (zero_extend:SI (match_dup 1)))
537 (set (match_dup 0)
538 (compare:CC (match_dup 2)
539 (const_int 0)))]
540 "")
541
542 (define_insn ""
543 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
544 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
545 (const_int 0)))
546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
547 (zero_extend:SI (match_dup 1)))]
548 ""
549 "@
550 {andil.|andi.} %0,%1,0xff
551 #"
552 [(set_attr "type" "compare")
553 (set_attr "length" "4,8")])
554
555 (define_split
556 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
557 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
558 (const_int 0)))
559 (set (match_operand:SI 0 "gpc_reg_operand" "")
560 (zero_extend:SI (match_dup 1)))]
561 "reload_completed"
562 [(set (match_dup 0)
563 (zero_extend:SI (match_dup 1)))
564 (set (match_dup 2)
565 (compare:CC (match_dup 0)
566 (const_int 0)))]
567 "")
568
569 (define_expand "extendqisi2"
570 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
571 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
572 ""
573 "
574 {
575 if (TARGET_POWERPC)
576 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
577 else if (TARGET_POWER)
578 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
579 else
580 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
581 DONE;
582 }")
583
584 (define_insn "extendqisi2_ppc"
585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
586 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
587 "TARGET_POWERPC"
588 "extsb %0,%1")
589
590 (define_insn ""
591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
592 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
593 (const_int 0)))
594 (clobber (match_scratch:SI 2 "=r,r"))]
595 "TARGET_POWERPC"
596 "@
597 extsb. %2,%1
598 #"
599 [(set_attr "type" "compare")
600 (set_attr "length" "4,8")])
601
602 (define_split
603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
604 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
605 (const_int 0)))
606 (clobber (match_scratch:SI 2 ""))]
607 "TARGET_POWERPC && reload_completed"
608 [(set (match_dup 2)
609 (sign_extend:SI (match_dup 1)))
610 (set (match_dup 0)
611 (compare:CC (match_dup 2)
612 (const_int 0)))]
613 "")
614
615 (define_insn ""
616 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
618 (const_int 0)))
619 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
620 (sign_extend:SI (match_dup 1)))]
621 "TARGET_POWERPC"
622 "@
623 extsb. %0,%1
624 #"
625 [(set_attr "type" "compare")
626 (set_attr "length" "4,8")])
627
628 (define_split
629 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
630 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
631 (const_int 0)))
632 (set (match_operand:SI 0 "gpc_reg_operand" "")
633 (sign_extend:SI (match_dup 1)))]
634 "TARGET_POWERPC && reload_completed"
635 [(set (match_dup 0)
636 (sign_extend:SI (match_dup 1)))
637 (set (match_dup 2)
638 (compare:CC (match_dup 0)
639 (const_int 0)))]
640 "")
641
642 (define_expand "extendqisi2_power"
643 [(parallel [(set (match_dup 2)
644 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
645 (const_int 24)))
646 (clobber (scratch:SI))])
647 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
648 (ashiftrt:SI (match_dup 2)
649 (const_int 24)))
650 (clobber (scratch:SI))])]
651 "TARGET_POWER"
652 "
653 { operands[1] = gen_lowpart (SImode, operands[1]);
654 operands[2] = gen_reg_rtx (SImode); }")
655
656 (define_expand "extendqisi2_no_power"
657 [(set (match_dup 2)
658 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
659 (const_int 24)))
660 (set (match_operand:SI 0 "gpc_reg_operand" "")
661 (ashiftrt:SI (match_dup 2)
662 (const_int 24)))]
663 "! TARGET_POWER && ! TARGET_POWERPC"
664 "
665 { operands[1] = gen_lowpart (SImode, operands[1]);
666 operands[2] = gen_reg_rtx (SImode); }")
667
668 (define_expand "zero_extendqihi2"
669 [(set (match_operand:HI 0 "gpc_reg_operand" "")
670 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
671 ""
672 "")
673
674 (define_insn ""
675 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
676 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
677 ""
678 "@
679 lbz%U1%X1 %0,%1
680 {rlinm|rlwinm} %0,%1,0,0xff"
681 [(set_attr "type" "load,*")])
682
683 (define_insn ""
684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
685 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
686 (const_int 0)))
687 (clobber (match_scratch:HI 2 "=r,r"))]
688 ""
689 "@
690 {andil.|andi.} %2,%1,0xff
691 #"
692 [(set_attr "type" "compare")
693 (set_attr "length" "4,8")])
694
695 (define_split
696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
697 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
698 (const_int 0)))
699 (clobber (match_scratch:HI 2 ""))]
700 "reload_completed"
701 [(set (match_dup 2)
702 (zero_extend:HI (match_dup 1)))
703 (set (match_dup 0)
704 (compare:CC (match_dup 2)
705 (const_int 0)))]
706 "")
707
708 (define_insn ""
709 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
711 (const_int 0)))
712 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
713 (zero_extend:HI (match_dup 1)))]
714 ""
715 "@
716 {andil.|andi.} %0,%1,0xff
717 #"
718 [(set_attr "type" "compare")
719 (set_attr "length" "4,8")])
720
721 (define_split
722 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
723 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
724 (const_int 0)))
725 (set (match_operand:HI 0 "gpc_reg_operand" "")
726 (zero_extend:HI (match_dup 1)))]
727 "reload_completed"
728 [(set (match_dup 0)
729 (zero_extend:HI (match_dup 1)))
730 (set (match_dup 2)
731 (compare:CC (match_dup 0)
732 (const_int 0)))]
733 "")
734
735 (define_expand "extendqihi2"
736 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
737 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
738 ""
739 "
740 {
741 if (TARGET_POWERPC)
742 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
743 else if (TARGET_POWER)
744 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
745 else
746 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
747 DONE;
748 }")
749
750 (define_insn "extendqihi2_ppc"
751 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
752 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
753 "TARGET_POWERPC"
754 "extsb %0,%1")
755
756 (define_insn ""
757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
758 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
759 (const_int 0)))
760 (clobber (match_scratch:HI 2 "=r,r"))]
761 "TARGET_POWERPC"
762 "@
763 extsb. %2,%1
764 #"
765 [(set_attr "type" "compare")
766 (set_attr "length" "4,8")])
767
768 (define_split
769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
770 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
771 (const_int 0)))
772 (clobber (match_scratch:HI 2 ""))]
773 "TARGET_POWERPC && reload_completed"
774 [(set (match_dup 2)
775 (sign_extend:HI (match_dup 1)))
776 (set (match_dup 0)
777 (compare:CC (match_dup 2)
778 (const_int 0)))]
779 "")
780
781 (define_insn ""
782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
783 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
784 (const_int 0)))
785 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
786 (sign_extend:HI (match_dup 1)))]
787 "TARGET_POWERPC"
788 "@
789 extsb. %0,%1
790 #"
791 [(set_attr "type" "compare")
792 (set_attr "length" "4,8")])
793
794 (define_split
795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
796 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
797 (const_int 0)))
798 (set (match_operand:HI 0 "gpc_reg_operand" "")
799 (sign_extend:HI (match_dup 1)))]
800 "TARGET_POWERPC && reload_completed"
801 [(set (match_dup 0)
802 (sign_extend:HI (match_dup 1)))
803 (set (match_dup 2)
804 (compare:CC (match_dup 0)
805 (const_int 0)))]
806 "")
807
808 (define_expand "extendqihi2_power"
809 [(parallel [(set (match_dup 2)
810 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
811 (const_int 24)))
812 (clobber (scratch:SI))])
813 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
814 (ashiftrt:SI (match_dup 2)
815 (const_int 24)))
816 (clobber (scratch:SI))])]
817 "TARGET_POWER"
818 "
819 { operands[0] = gen_lowpart (SImode, operands[0]);
820 operands[1] = gen_lowpart (SImode, operands[1]);
821 operands[2] = gen_reg_rtx (SImode); }")
822
823 (define_expand "extendqihi2_no_power"
824 [(set (match_dup 2)
825 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
826 (const_int 24)))
827 (set (match_operand:HI 0 "gpc_reg_operand" "")
828 (ashiftrt:SI (match_dup 2)
829 (const_int 24)))]
830 "! TARGET_POWER && ! TARGET_POWERPC"
831 "
832 { operands[0] = gen_lowpart (SImode, operands[0]);
833 operands[1] = gen_lowpart (SImode, operands[1]);
834 operands[2] = gen_reg_rtx (SImode); }")
835
836 (define_expand "zero_extendhisi2"
837 [(set (match_operand:SI 0 "gpc_reg_operand" "")
838 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
839 ""
840 "")
841
842 (define_insn ""
843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
844 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
845 ""
846 "@
847 lhz%U1%X1 %0,%1
848 {rlinm|rlwinm} %0,%1,0,0xffff"
849 [(set_attr "type" "load,*")])
850
851 (define_insn ""
852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
853 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
854 (const_int 0)))
855 (clobber (match_scratch:SI 2 "=r,r"))]
856 ""
857 "@
858 {andil.|andi.} %2,%1,0xffff
859 #"
860 [(set_attr "type" "compare")
861 (set_attr "length" "4,8")])
862
863 (define_split
864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
865 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
866 (const_int 0)))
867 (clobber (match_scratch:SI 2 ""))]
868 "reload_completed"
869 [(set (match_dup 2)
870 (zero_extend:SI (match_dup 1)))
871 (set (match_dup 0)
872 (compare:CC (match_dup 2)
873 (const_int 0)))]
874 "")
875
876 (define_insn ""
877 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
878 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
879 (const_int 0)))
880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
881 (zero_extend:SI (match_dup 1)))]
882 ""
883 "@
884 {andil.|andi.} %0,%1,0xffff
885 #"
886 [(set_attr "type" "compare")
887 (set_attr "length" "4,8")])
888
889 (define_split
890 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
891 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
892 (const_int 0)))
893 (set (match_operand:SI 0 "gpc_reg_operand" "")
894 (zero_extend:SI (match_dup 1)))]
895 "reload_completed"
896 [(set (match_dup 0)
897 (zero_extend:SI (match_dup 1)))
898 (set (match_dup 2)
899 (compare:CC (match_dup 0)
900 (const_int 0)))]
901 "")
902
903 (define_expand "extendhisi2"
904 [(set (match_operand:SI 0 "gpc_reg_operand" "")
905 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
906 ""
907 "")
908
909 (define_insn ""
910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
911 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
912 ""
913 "@
914 lha%U1%X1 %0,%1
915 {exts|extsh} %0,%1"
916 [(set_attr "type" "load_ext,*")])
917
918 (define_insn ""
919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
920 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
921 (const_int 0)))
922 (clobber (match_scratch:SI 2 "=r,r"))]
923 ""
924 "@
925 {exts.|extsh.} %2,%1
926 #"
927 [(set_attr "type" "compare")
928 (set_attr "length" "4,8")])
929
930 (define_split
931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
932 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
933 (const_int 0)))
934 (clobber (match_scratch:SI 2 ""))]
935 "reload_completed"
936 [(set (match_dup 2)
937 (sign_extend:SI (match_dup 1)))
938 (set (match_dup 0)
939 (compare:CC (match_dup 2)
940 (const_int 0)))]
941 "")
942
943 (define_insn ""
944 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
945 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
946 (const_int 0)))
947 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
948 (sign_extend:SI (match_dup 1)))]
949 ""
950 "@
951 {exts.|extsh.} %0,%1
952 #"
953 [(set_attr "type" "compare")
954 (set_attr "length" "4,8")])
955 \f
956 (define_split
957 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
958 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
959 (const_int 0)))
960 (set (match_operand:SI 0 "gpc_reg_operand" "")
961 (sign_extend:SI (match_dup 1)))]
962 "reload_completed"
963 [(set (match_dup 0)
964 (sign_extend:SI (match_dup 1)))
965 (set (match_dup 2)
966 (compare:CC (match_dup 0)
967 (const_int 0)))]
968 "")
969
970 ;; Fixed-point arithmetic insns.
971
972 ;; Discourage ai/addic because of carry but provide it in an alternative
973 ;; allowing register zero as source.
974 (define_expand "addsi3"
975 [(set (match_operand:SI 0 "gpc_reg_operand" "")
976 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
977 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
978 ""
979 "
980 {
981 if (GET_CODE (operands[2]) == CONST_INT
982 && ! add_operand (operands[2], SImode))
983 {
984 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
985 ? operands[0] : gen_reg_rtx (SImode));
986
987 HOST_WIDE_INT val = INTVAL (operands[2]);
988 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
989 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
990
991 /* The ordering here is important for the prolog expander.
992 When space is allocated from the stack, adding 'low' first may
993 produce a temporary deallocation (which would be bad). */
994 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
995 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
996 DONE;
997 }
998 }")
999
1000 (define_insn "*addsi3_internal1"
1001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1002 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1003 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1004 ""
1005 "@
1006 {cax|add} %0,%1,%2
1007 {cal %0,%2(%1)|addi %0,%1,%2}
1008 {ai|addic} %0,%1,%2
1009 {cau|addis} %0,%1,%v2"
1010 [(set_attr "length" "4,4,4,4")])
1011
1012 (define_insn "addsi3_high"
1013 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1014 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1015 (high:SI (match_operand 2 "" ""))))]
1016 "TARGET_MACHO && !TARGET_64BIT"
1017 "{cau|addis} %0,%1,ha16(%2)"
1018 [(set_attr "length" "4")])
1019
1020 (define_insn "*addsi3_internal2"
1021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1022 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1023 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1024 (const_int 0)))
1025 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1026 "TARGET_32BIT"
1027 "@
1028 {cax.|add.} %3,%1,%2
1029 {ai.|addic.} %3,%1,%2
1030 #
1031 #"
1032 [(set_attr "type" "fast_compare,compare,compare,compare")
1033 (set_attr "length" "4,4,8,8")])
1034
1035 (define_split
1036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1037 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1038 (match_operand:SI 2 "reg_or_short_operand" ""))
1039 (const_int 0)))
1040 (clobber (match_scratch:SI 3 ""))]
1041 "TARGET_32BIT && reload_completed"
1042 [(set (match_dup 3)
1043 (plus:SI (match_dup 1)
1044 (match_dup 2)))
1045 (set (match_dup 0)
1046 (compare:CC (match_dup 3)
1047 (const_int 0)))]
1048 "")
1049
1050 (define_insn "*addsi3_internal3"
1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1052 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1053 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1054 (const_int 0)))
1055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1056 (plus:SI (match_dup 1)
1057 (match_dup 2)))]
1058 "TARGET_32BIT"
1059 "@
1060 {cax.|add.} %0,%1,%2
1061 {ai.|addic.} %0,%1,%2
1062 #
1063 #"
1064 [(set_attr "type" "fast_compare,compare,compare,compare")
1065 (set_attr "length" "4,4,8,8")])
1066
1067 (define_split
1068 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1069 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1070 (match_operand:SI 2 "reg_or_short_operand" ""))
1071 (const_int 0)))
1072 (set (match_operand:SI 0 "gpc_reg_operand" "")
1073 (plus:SI (match_dup 1) (match_dup 2)))]
1074 "TARGET_32BIT && reload_completed"
1075 [(set (match_dup 0)
1076 (plus:SI (match_dup 1)
1077 (match_dup 2)))
1078 (set (match_dup 3)
1079 (compare:CC (match_dup 0)
1080 (const_int 0)))]
1081 "")
1082
1083 ;; Split an add that we can't do in one insn into two insns, each of which
1084 ;; does one 16-bit part. This is used by combine. Note that the low-order
1085 ;; add should be last in case the result gets used in an address.
1086
1087 (define_split
1088 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1089 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1090 (match_operand:SI 2 "non_add_cint_operand" "")))]
1091 ""
1092 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1093 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1094 "
1095 {
1096 HOST_WIDE_INT val = INTVAL (operands[2]);
1097 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1098 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1099
1100 operands[3] = GEN_INT (rest);
1101 operands[4] = GEN_INT (low);
1102 }")
1103
1104 (define_insn "one_cmplsi2"
1105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1106 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1107 ""
1108 "nor %0,%1,%1")
1109
1110 (define_insn ""
1111 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1112 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1113 (const_int 0)))
1114 (clobber (match_scratch:SI 2 "=r,r"))]
1115 "TARGET_32BIT"
1116 "@
1117 nor. %2,%1,%1
1118 #"
1119 [(set_attr "type" "compare")
1120 (set_attr "length" "4,8")])
1121
1122 (define_split
1123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1124 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1125 (const_int 0)))
1126 (clobber (match_scratch:SI 2 ""))]
1127 "TARGET_32BIT && reload_completed"
1128 [(set (match_dup 2)
1129 (not:SI (match_dup 1)))
1130 (set (match_dup 0)
1131 (compare:CC (match_dup 2)
1132 (const_int 0)))]
1133 "")
1134
1135 (define_insn ""
1136 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1137 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1138 (const_int 0)))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1140 (not:SI (match_dup 1)))]
1141 "TARGET_32BIT"
1142 "@
1143 nor. %0,%1,%1
1144 #"
1145 [(set_attr "type" "compare")
1146 (set_attr "length" "4,8")])
1147
1148 (define_split
1149 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1150 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1151 (const_int 0)))
1152 (set (match_operand:SI 0 "gpc_reg_operand" "")
1153 (not:SI (match_dup 1)))]
1154 "TARGET_32BIT && reload_completed"
1155 [(set (match_dup 0)
1156 (not:SI (match_dup 1)))
1157 (set (match_dup 2)
1158 (compare:CC (match_dup 0)
1159 (const_int 0)))]
1160 "")
1161
1162 (define_insn ""
1163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1165 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1166 "! TARGET_POWERPC"
1167 "{sf%I1|subf%I1c} %0,%2,%1")
1168
1169 (define_insn ""
1170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1171 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1172 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1173 "TARGET_POWERPC"
1174 "@
1175 subf %0,%2,%1
1176 subfic %0,%2,%1")
1177
1178 (define_insn ""
1179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1180 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1181 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1182 (const_int 0)))
1183 (clobber (match_scratch:SI 3 "=r,r"))]
1184 "! TARGET_POWERPC"
1185 "@
1186 {sf.|subfc.} %3,%2,%1
1187 #"
1188 [(set_attr "type" "compare")
1189 (set_attr "length" "4,8")])
1190
1191 (define_insn ""
1192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1193 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1194 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1195 (const_int 0)))
1196 (clobber (match_scratch:SI 3 "=r,r"))]
1197 "TARGET_POWERPC && TARGET_32BIT"
1198 "@
1199 subf. %3,%2,%1
1200 #"
1201 [(set_attr "type" "fast_compare")
1202 (set_attr "length" "4,8")])
1203
1204 (define_split
1205 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1206 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1207 (match_operand:SI 2 "gpc_reg_operand" ""))
1208 (const_int 0)))
1209 (clobber (match_scratch:SI 3 ""))]
1210 "TARGET_32BIT && reload_completed"
1211 [(set (match_dup 3)
1212 (minus:SI (match_dup 1)
1213 (match_dup 2)))
1214 (set (match_dup 0)
1215 (compare:CC (match_dup 3)
1216 (const_int 0)))]
1217 "")
1218
1219 (define_insn ""
1220 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1221 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1222 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1223 (const_int 0)))
1224 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1225 (minus:SI (match_dup 1) (match_dup 2)))]
1226 "! TARGET_POWERPC"
1227 "@
1228 {sf.|subfc.} %0,%2,%1
1229 #"
1230 [(set_attr "type" "compare")
1231 (set_attr "length" "4,8")])
1232
1233 (define_insn ""
1234 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1235 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1236 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1237 (const_int 0)))
1238 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1239 (minus:SI (match_dup 1)
1240 (match_dup 2)))]
1241 "TARGET_POWERPC && TARGET_32BIT"
1242 "@
1243 subf. %0,%2,%1
1244 #"
1245 [(set_attr "type" "fast_compare")
1246 (set_attr "length" "4,8")])
1247
1248 (define_split
1249 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1250 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1251 (match_operand:SI 2 "gpc_reg_operand" ""))
1252 (const_int 0)))
1253 (set (match_operand:SI 0 "gpc_reg_operand" "")
1254 (minus:SI (match_dup 1)
1255 (match_dup 2)))]
1256 "TARGET_32BIT && reload_completed"
1257 [(set (match_dup 0)
1258 (minus:SI (match_dup 1)
1259 (match_dup 2)))
1260 (set (match_dup 3)
1261 (compare:CC (match_dup 0)
1262 (const_int 0)))]
1263 "")
1264
1265 (define_expand "subsi3"
1266 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1267 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1268 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1269 ""
1270 "
1271 {
1272 if (GET_CODE (operands[2]) == CONST_INT)
1273 {
1274 emit_insn (gen_addsi3 (operands[0], operands[1],
1275 negate_rtx (SImode, operands[2])));
1276 DONE;
1277 }
1278 }")
1279
1280 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1281 ;; instruction and some auxiliary computations. Then we just have a single
1282 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1283 ;; combine.
1284
1285 (define_expand "sminsi3"
1286 [(set (match_dup 3)
1287 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1288 (match_operand:SI 2 "reg_or_short_operand" ""))
1289 (const_int 0)
1290 (minus:SI (match_dup 2) (match_dup 1))))
1291 (set (match_operand:SI 0 "gpc_reg_operand" "")
1292 (minus:SI (match_dup 2) (match_dup 3)))]
1293 "TARGET_POWER || TARGET_ISEL"
1294 "
1295 {
1296 if (TARGET_ISEL)
1297 {
1298 operands[2] = force_reg (SImode, operands[2]);
1299 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1300 DONE;
1301 }
1302
1303 operands[3] = gen_reg_rtx (SImode);
1304 }")
1305
1306 (define_split
1307 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1308 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1309 (match_operand:SI 2 "reg_or_short_operand" "")))
1310 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1311 "TARGET_POWER"
1312 [(set (match_dup 3)
1313 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1314 (const_int 0)
1315 (minus:SI (match_dup 2) (match_dup 1))))
1316 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1317 "")
1318
1319 (define_expand "smaxsi3"
1320 [(set (match_dup 3)
1321 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1322 (match_operand:SI 2 "reg_or_short_operand" ""))
1323 (const_int 0)
1324 (minus:SI (match_dup 2) (match_dup 1))))
1325 (set (match_operand:SI 0 "gpc_reg_operand" "")
1326 (plus:SI (match_dup 3) (match_dup 1)))]
1327 "TARGET_POWER || TARGET_ISEL"
1328 "
1329 {
1330 if (TARGET_ISEL)
1331 {
1332 operands[2] = force_reg (SImode, operands[2]);
1333 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1334 DONE;
1335 }
1336 operands[3] = gen_reg_rtx (SImode);
1337 }")
1338
1339 (define_split
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1341 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1342 (match_operand:SI 2 "reg_or_short_operand" "")))
1343 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1344 "TARGET_POWER"
1345 [(set (match_dup 3)
1346 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1347 (const_int 0)
1348 (minus:SI (match_dup 2) (match_dup 1))))
1349 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1350 "")
1351
1352 (define_expand "uminsi3"
1353 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1354 (match_dup 5)))
1355 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1356 (match_dup 5)))
1357 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1358 (const_int 0)
1359 (minus:SI (match_dup 4) (match_dup 3))))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "")
1361 (minus:SI (match_dup 2) (match_dup 3)))]
1362 "TARGET_POWER || TARGET_ISEL"
1363 "
1364 {
1365 if (TARGET_ISEL)
1366 {
1367 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1368 DONE;
1369 }
1370 operands[3] = gen_reg_rtx (SImode);
1371 operands[4] = gen_reg_rtx (SImode);
1372 operands[5] = GEN_INT (-2147483647 - 1);
1373 }")
1374
1375 (define_expand "umaxsi3"
1376 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1377 (match_dup 5)))
1378 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1379 (match_dup 5)))
1380 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1381 (const_int 0)
1382 (minus:SI (match_dup 4) (match_dup 3))))
1383 (set (match_operand:SI 0 "gpc_reg_operand" "")
1384 (plus:SI (match_dup 3) (match_dup 1)))]
1385 "TARGET_POWER || TARGET_ISEL"
1386 "
1387 {
1388 if (TARGET_ISEL)
1389 {
1390 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1391 DONE;
1392 }
1393 operands[3] = gen_reg_rtx (SImode);
1394 operands[4] = gen_reg_rtx (SImode);
1395 operands[5] = GEN_INT (-2147483647 - 1);
1396 }")
1397
1398 (define_insn ""
1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1400 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1401 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1402 (const_int 0)
1403 (minus:SI (match_dup 2) (match_dup 1))))]
1404 "TARGET_POWER"
1405 "doz%I2 %0,%1,%2")
1406
1407 (define_insn ""
1408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1409 (compare:CC
1410 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1411 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1412 (const_int 0)
1413 (minus:SI (match_dup 2) (match_dup 1)))
1414 (const_int 0)))
1415 (clobber (match_scratch:SI 3 "=r,r"))]
1416 "TARGET_POWER"
1417 "@
1418 doz%I2. %3,%1,%2
1419 #"
1420 [(set_attr "type" "delayed_compare")
1421 (set_attr "length" "4,8")])
1422
1423 (define_split
1424 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1425 (compare:CC
1426 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1427 (match_operand:SI 2 "reg_or_short_operand" ""))
1428 (const_int 0)
1429 (minus:SI (match_dup 2) (match_dup 1)))
1430 (const_int 0)))
1431 (clobber (match_scratch:SI 3 ""))]
1432 "TARGET_POWER && reload_completed"
1433 [(set (match_dup 3)
1434 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1435 (const_int 0)
1436 (minus:SI (match_dup 2) (match_dup 1))))
1437 (set (match_dup 0)
1438 (compare:CC (match_dup 3)
1439 (const_int 0)))]
1440 "")
1441
1442 (define_insn ""
1443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1444 (compare:CC
1445 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1446 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1447 (const_int 0)
1448 (minus:SI (match_dup 2) (match_dup 1)))
1449 (const_int 0)))
1450 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1451 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1452 (const_int 0)
1453 (minus:SI (match_dup 2) (match_dup 1))))]
1454 "TARGET_POWER"
1455 "@
1456 doz%I2. %0,%1,%2
1457 #"
1458 [(set_attr "type" "delayed_compare")
1459 (set_attr "length" "4,8")])
1460
1461 (define_split
1462 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1463 (compare:CC
1464 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1465 (match_operand:SI 2 "reg_or_short_operand" ""))
1466 (const_int 0)
1467 (minus:SI (match_dup 2) (match_dup 1)))
1468 (const_int 0)))
1469 (set (match_operand:SI 0 "gpc_reg_operand" "")
1470 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1471 (const_int 0)
1472 (minus:SI (match_dup 2) (match_dup 1))))]
1473 "TARGET_POWER && reload_completed"
1474 [(set (match_dup 0)
1475 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1476 (const_int 0)
1477 (minus:SI (match_dup 2) (match_dup 1))))
1478 (set (match_dup 3)
1479 (compare:CC (match_dup 0)
1480 (const_int 0)))]
1481 "")
1482
1483 ;; We don't need abs with condition code because such comparisons should
1484 ;; never be done.
1485 (define_expand "abssi2"
1486 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1487 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1488 ""
1489 "
1490 {
1491 if (TARGET_ISEL)
1492 {
1493 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1494 DONE;
1495 }
1496 else if (! TARGET_POWER)
1497 {
1498 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1499 DONE;
1500 }
1501 }")
1502
1503 (define_insn "*abssi2_power"
1504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1505 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1506 "TARGET_POWER"
1507 "abs %0,%1")
1508
1509 (define_insn_and_split "abssi2_isel"
1510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1511 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1512 (clobber (match_scratch:SI 2 "=&b"))
1513 (clobber (match_scratch:CC 3 "=y"))]
1514 "TARGET_ISEL"
1515 "#"
1516 "&& reload_completed"
1517 [(set (match_dup 2) (neg:SI (match_dup 1)))
1518 (set (match_dup 3)
1519 (compare:CC (match_dup 1)
1520 (const_int 0)))
1521 (set (match_dup 0)
1522 (if_then_else:SI (ge (match_dup 3)
1523 (const_int 0))
1524 (match_dup 1)
1525 (match_dup 2)))]
1526 "")
1527
1528 (define_insn_and_split "abssi2_nopower"
1529 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1530 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1531 (clobber (match_scratch:SI 2 "=&r,&r"))]
1532 "! TARGET_POWER && ! TARGET_ISEL"
1533 "#"
1534 "&& reload_completed"
1535 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1536 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1537 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1538 "")
1539
1540 (define_insn "*nabs_power"
1541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1542 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1543 "TARGET_POWER"
1544 "nabs %0,%1")
1545
1546 (define_insn_and_split "*nabs_nopower"
1547 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1548 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1549 (clobber (match_scratch:SI 2 "=&r,&r"))]
1550 "! TARGET_POWER"
1551 "#"
1552 "&& reload_completed"
1553 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1554 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1555 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1556 "")
1557
1558 (define_insn "negsi2"
1559 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1560 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1561 ""
1562 "neg %0,%1")
1563
1564 (define_insn ""
1565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1566 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1567 (const_int 0)))
1568 (clobber (match_scratch:SI 2 "=r,r"))]
1569 "TARGET_32BIT"
1570 "@
1571 neg. %2,%1
1572 #"
1573 [(set_attr "type" "fast_compare")
1574 (set_attr "length" "4,8")])
1575
1576 (define_split
1577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1578 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1579 (const_int 0)))
1580 (clobber (match_scratch:SI 2 ""))]
1581 "TARGET_32BIT && reload_completed"
1582 [(set (match_dup 2)
1583 (neg:SI (match_dup 1)))
1584 (set (match_dup 0)
1585 (compare:CC (match_dup 2)
1586 (const_int 0)))]
1587 "")
1588
1589 (define_insn ""
1590 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1591 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1592 (const_int 0)))
1593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1594 (neg:SI (match_dup 1)))]
1595 "TARGET_32BIT"
1596 "@
1597 neg. %0,%1
1598 #"
1599 [(set_attr "type" "fast_compare")
1600 (set_attr "length" "4,8")])
1601
1602 (define_split
1603 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1604 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1605 (const_int 0)))
1606 (set (match_operand:SI 0 "gpc_reg_operand" "")
1607 (neg:SI (match_dup 1)))]
1608 "TARGET_32BIT && reload_completed"
1609 [(set (match_dup 0)
1610 (neg:SI (match_dup 1)))
1611 (set (match_dup 2)
1612 (compare:CC (match_dup 0)
1613 (const_int 0)))]
1614 "")
1615
1616 (define_insn "clzsi2"
1617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1618 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1619 ""
1620 "{cntlz|cntlzw} %0,%1")
1621
1622 (define_expand "ctzsi2"
1623 [(set (match_dup 2)
1624 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1625 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1626 (match_dup 2)))
1627 (clobber (scratch:CC))])
1628 (set (match_dup 4) (clz:SI (match_dup 3)))
1629 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1630 (minus:SI (const_int 31) (match_dup 4)))]
1631 ""
1632 {
1633 operands[2] = gen_reg_rtx (SImode);
1634 operands[3] = gen_reg_rtx (SImode);
1635 operands[4] = gen_reg_rtx (SImode);
1636 })
1637
1638 (define_expand "ffssi2"
1639 [(set (match_dup 2)
1640 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1641 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1642 (match_dup 2)))
1643 (clobber (scratch:CC))])
1644 (set (match_dup 4) (clz:SI (match_dup 3)))
1645 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1646 (minus:SI (const_int 32) (match_dup 4)))]
1647 ""
1648 {
1649 operands[2] = gen_reg_rtx (SImode);
1650 operands[3] = gen_reg_rtx (SImode);
1651 operands[4] = gen_reg_rtx (SImode);
1652 })
1653
1654 (define_expand "mulsi3"
1655 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1656 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1657 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1658 ""
1659 "
1660 {
1661 if (TARGET_POWER)
1662 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1663 else
1664 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1665 DONE;
1666 }")
1667
1668 (define_insn "mulsi3_mq"
1669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1670 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1671 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1672 (clobber (match_scratch:SI 3 "=q,q"))]
1673 "TARGET_POWER"
1674 "@
1675 {muls|mullw} %0,%1,%2
1676 {muli|mulli} %0,%1,%2"
1677 [(set (attr "type")
1678 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1679 (const_string "imul3")
1680 (match_operand:SI 2 "short_cint_operand" "")
1681 (const_string "imul2")]
1682 (const_string "imul")))])
1683
1684 (define_insn "mulsi3_no_mq"
1685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1686 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1687 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1688 "! TARGET_POWER"
1689 "@
1690 {muls|mullw} %0,%1,%2
1691 {muli|mulli} %0,%1,%2"
1692 [(set (attr "type")
1693 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1694 (const_string "imul3")
1695 (match_operand:SI 2 "short_cint_operand" "")
1696 (const_string "imul2")]
1697 (const_string "imul")))])
1698
1699 (define_insn "*mulsi3_mq_internal1"
1700 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1701 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1702 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1703 (const_int 0)))
1704 (clobber (match_scratch:SI 3 "=r,r"))
1705 (clobber (match_scratch:SI 4 "=q,q"))]
1706 "TARGET_POWER"
1707 "@
1708 {muls.|mullw.} %3,%1,%2
1709 #"
1710 [(set_attr "type" "imul_compare")
1711 (set_attr "length" "4,8")])
1712
1713 (define_split
1714 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1715 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1716 (match_operand:SI 2 "gpc_reg_operand" ""))
1717 (const_int 0)))
1718 (clobber (match_scratch:SI 3 ""))
1719 (clobber (match_scratch:SI 4 ""))]
1720 "TARGET_POWER && reload_completed"
1721 [(parallel [(set (match_dup 3)
1722 (mult:SI (match_dup 1) (match_dup 2)))
1723 (clobber (match_dup 4))])
1724 (set (match_dup 0)
1725 (compare:CC (match_dup 3)
1726 (const_int 0)))]
1727 "")
1728
1729 (define_insn "*mulsi3_no_mq_internal1"
1730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1732 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1733 (const_int 0)))
1734 (clobber (match_scratch:SI 3 "=r,r"))]
1735 "! TARGET_POWER"
1736 "@
1737 {muls.|mullw.} %3,%1,%2
1738 #"
1739 [(set_attr "type" "imul_compare")
1740 (set_attr "length" "4,8")])
1741
1742 (define_split
1743 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1744 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1745 (match_operand:SI 2 "gpc_reg_operand" ""))
1746 (const_int 0)))
1747 (clobber (match_scratch:SI 3 ""))]
1748 "! TARGET_POWER && reload_completed"
1749 [(set (match_dup 3)
1750 (mult:SI (match_dup 1) (match_dup 2)))
1751 (set (match_dup 0)
1752 (compare:CC (match_dup 3)
1753 (const_int 0)))]
1754 "")
1755
1756 (define_insn "*mulsi3_mq_internal2"
1757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1758 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1759 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1760 (const_int 0)))
1761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1762 (mult:SI (match_dup 1) (match_dup 2)))
1763 (clobber (match_scratch:SI 4 "=q,q"))]
1764 "TARGET_POWER"
1765 "@
1766 {muls.|mullw.} %0,%1,%2
1767 #"
1768 [(set_attr "type" "imul_compare")
1769 (set_attr "length" "4,8")])
1770
1771 (define_split
1772 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1773 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1774 (match_operand:SI 2 "gpc_reg_operand" ""))
1775 (const_int 0)))
1776 (set (match_operand:SI 0 "gpc_reg_operand" "")
1777 (mult:SI (match_dup 1) (match_dup 2)))
1778 (clobber (match_scratch:SI 4 ""))]
1779 "TARGET_POWER && reload_completed"
1780 [(parallel [(set (match_dup 0)
1781 (mult:SI (match_dup 1) (match_dup 2)))
1782 (clobber (match_dup 4))])
1783 (set (match_dup 3)
1784 (compare:CC (match_dup 0)
1785 (const_int 0)))]
1786 "")
1787
1788 (define_insn "*mulsi3_no_mq_internal2"
1789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1792 (const_int 0)))
1793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1794 (mult:SI (match_dup 1) (match_dup 2)))]
1795 "! TARGET_POWER"
1796 "@
1797 {muls.|mullw.} %0,%1,%2
1798 #"
1799 [(set_attr "type" "imul_compare")
1800 (set_attr "length" "4,8")])
1801
1802 (define_split
1803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1804 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1805 (match_operand:SI 2 "gpc_reg_operand" ""))
1806 (const_int 0)))
1807 (set (match_operand:SI 0 "gpc_reg_operand" "")
1808 (mult:SI (match_dup 1) (match_dup 2)))]
1809 "! TARGET_POWER && reload_completed"
1810 [(set (match_dup 0)
1811 (mult:SI (match_dup 1) (match_dup 2)))
1812 (set (match_dup 3)
1813 (compare:CC (match_dup 0)
1814 (const_int 0)))]
1815 "")
1816
1817 ;; Operand 1 is divided by operand 2; quotient goes to operand
1818 ;; 0 and remainder to operand 3.
1819 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1820
1821 (define_expand "divmodsi4"
1822 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1823 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1824 (match_operand:SI 2 "gpc_reg_operand" "")))
1825 (set (match_operand:SI 3 "register_operand" "")
1826 (mod:SI (match_dup 1) (match_dup 2)))])]
1827 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1828 "
1829 {
1830 if (! TARGET_POWER && ! TARGET_POWERPC)
1831 {
1832 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1833 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1834 emit_insn (gen_divss_call ());
1835 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1836 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1837 DONE;
1838 }
1839 }")
1840
1841 (define_insn "*divmodsi4_internal"
1842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1843 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1844 (match_operand:SI 2 "gpc_reg_operand" "r")))
1845 (set (match_operand:SI 3 "register_operand" "=q")
1846 (mod:SI (match_dup 1) (match_dup 2)))]
1847 "TARGET_POWER"
1848 "divs %0,%1,%2"
1849 [(set_attr "type" "idiv")])
1850
1851 (define_expand "udivsi3"
1852 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1853 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1854 (match_operand:SI 2 "gpc_reg_operand" "")))]
1855 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1856 "
1857 {
1858 if (! TARGET_POWER && ! TARGET_POWERPC)
1859 {
1860 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1861 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1862 emit_insn (gen_quous_call ());
1863 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1864 DONE;
1865 }
1866 else if (TARGET_POWER)
1867 {
1868 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1869 DONE;
1870 }
1871 }")
1872
1873 (define_insn "udivsi3_mq"
1874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1875 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1876 (match_operand:SI 2 "gpc_reg_operand" "r")))
1877 (clobber (match_scratch:SI 3 "=q"))]
1878 "TARGET_POWERPC && TARGET_POWER"
1879 "divwu %0,%1,%2"
1880 [(set_attr "type" "idiv")])
1881
1882 (define_insn "*udivsi3_no_mq"
1883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1884 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1885 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1886 "TARGET_POWERPC && ! TARGET_POWER"
1887 "divwu %0,%1,%2"
1888 [(set_attr "type" "idiv")])
1889
1890 ;; For powers of two we can do srai/aze for divide and then adjust for
1891 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1892 ;; used; for PowerPC, force operands into register and do a normal divide;
1893 ;; for AIX common-mode, use quoss call on register operands.
1894 (define_expand "divsi3"
1895 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1896 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1897 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1898 ""
1899 "
1900 {
1901 if (GET_CODE (operands[2]) == CONST_INT
1902 && INTVAL (operands[2]) > 0
1903 && exact_log2 (INTVAL (operands[2])) >= 0)
1904 ;
1905 else if (TARGET_POWERPC)
1906 {
1907 operands[2] = force_reg (SImode, operands[2]);
1908 if (TARGET_POWER)
1909 {
1910 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1911 DONE;
1912 }
1913 }
1914 else if (TARGET_POWER)
1915 FAIL;
1916 else
1917 {
1918 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1919 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1920 emit_insn (gen_quoss_call ());
1921 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1922 DONE;
1923 }
1924 }")
1925
1926 (define_insn "divsi3_mq"
1927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1928 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1929 (match_operand:SI 2 "gpc_reg_operand" "r")))
1930 (clobber (match_scratch:SI 3 "=q"))]
1931 "TARGET_POWERPC && TARGET_POWER"
1932 "divw %0,%1,%2"
1933 [(set_attr "type" "idiv")])
1934
1935 (define_insn "*divsi3_no_mq"
1936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1937 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1938 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1939 "TARGET_POWERPC && ! TARGET_POWER"
1940 "divw %0,%1,%2"
1941 [(set_attr "type" "idiv")])
1942
1943 (define_expand "modsi3"
1944 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1945 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1946 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1947 ""
1948 "
1949 {
1950 int i;
1951 rtx temp1;
1952 rtx temp2;
1953
1954 if (GET_CODE (operands[2]) != CONST_INT
1955 || INTVAL (operands[2]) <= 0
1956 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1957 FAIL;
1958
1959 temp1 = gen_reg_rtx (SImode);
1960 temp2 = gen_reg_rtx (SImode);
1961
1962 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1963 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1964 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1965 DONE;
1966 }")
1967
1968 (define_insn ""
1969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1970 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1971 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1972 ""
1973 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1974 [(set_attr "length" "8")])
1975
1976 (define_insn ""
1977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1978 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1979 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1980 (const_int 0)))
1981 (clobber (match_scratch:SI 3 "=r,r"))]
1982 ""
1983 "@
1984 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1985 #"
1986 [(set_attr "type" "compare")
1987 (set_attr "length" "8,12")])
1988
1989 (define_split
1990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1991 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1992 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1993 (const_int 0)))
1994 (clobber (match_scratch:SI 3 ""))]
1995 "reload_completed"
1996 [(set (match_dup 3)
1997 (div:SI (match_dup 1) (match_dup 2)))
1998 (set (match_dup 0)
1999 (compare:CC (match_dup 3)
2000 (const_int 0)))]
2001 "")
2002
2003 (define_insn ""
2004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2005 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2006 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2007 (const_int 0)))
2008 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2009 (div:SI (match_dup 1) (match_dup 2)))]
2010 ""
2011 "@
2012 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2013 #"
2014 [(set_attr "type" "compare")
2015 (set_attr "length" "8,12")])
2016
2017 (define_split
2018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2019 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2020 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2021 (const_int 0)))
2022 (set (match_operand:SI 0 "gpc_reg_operand" "")
2023 (div:SI (match_dup 1) (match_dup 2)))]
2024 "reload_completed"
2025 [(set (match_dup 0)
2026 (div:SI (match_dup 1) (match_dup 2)))
2027 (set (match_dup 3)
2028 (compare:CC (match_dup 0)
2029 (const_int 0)))]
2030 "")
2031
2032 (define_insn ""
2033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2034 (udiv:SI
2035 (plus:DI (ashift:DI
2036 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2037 (const_int 32))
2038 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2039 (match_operand:SI 3 "gpc_reg_operand" "r")))
2040 (set (match_operand:SI 2 "register_operand" "=*q")
2041 (umod:SI
2042 (plus:DI (ashift:DI
2043 (zero_extend:DI (match_dup 1)) (const_int 32))
2044 (zero_extend:DI (match_dup 4)))
2045 (match_dup 3)))]
2046 "TARGET_POWER"
2047 "div %0,%1,%3"
2048 [(set_attr "type" "idiv")])
2049
2050 ;; To do unsigned divide we handle the cases of the divisor looking like a
2051 ;; negative number. If it is a constant that is less than 2**31, we don't
2052 ;; have to worry about the branches. So make a few subroutines here.
2053 ;;
2054 ;; First comes the normal case.
2055 (define_expand "udivmodsi4_normal"
2056 [(set (match_dup 4) (const_int 0))
2057 (parallel [(set (match_operand:SI 0 "" "")
2058 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2059 (const_int 32))
2060 (zero_extend:DI (match_operand:SI 1 "" "")))
2061 (match_operand:SI 2 "" "")))
2062 (set (match_operand:SI 3 "" "")
2063 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2064 (const_int 32))
2065 (zero_extend:DI (match_dup 1)))
2066 (match_dup 2)))])]
2067 "TARGET_POWER"
2068 "
2069 { operands[4] = gen_reg_rtx (SImode); }")
2070
2071 ;; This handles the branches.
2072 (define_expand "udivmodsi4_tests"
2073 [(set (match_operand:SI 0 "" "") (const_int 0))
2074 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2075 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2076 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2077 (label_ref (match_operand:SI 4 "" "")) (pc)))
2078 (set (match_dup 0) (const_int 1))
2079 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2080 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2081 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2082 (label_ref (match_dup 4)) (pc)))]
2083 "TARGET_POWER"
2084 "
2085 { operands[5] = gen_reg_rtx (CCUNSmode);
2086 operands[6] = gen_reg_rtx (CCmode);
2087 }")
2088
2089 (define_expand "udivmodsi4"
2090 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2091 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2092 (match_operand:SI 2 "reg_or_cint_operand" "")))
2093 (set (match_operand:SI 3 "gpc_reg_operand" "")
2094 (umod:SI (match_dup 1) (match_dup 2)))])]
2095 ""
2096 "
2097 {
2098 rtx label = 0;
2099
2100 if (! TARGET_POWER)
2101 {
2102 if (! TARGET_POWERPC)
2103 {
2104 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2105 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2106 emit_insn (gen_divus_call ());
2107 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2108 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2109 DONE;
2110 }
2111 else
2112 FAIL;
2113 }
2114
2115 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2116 {
2117 operands[2] = force_reg (SImode, operands[2]);
2118 label = gen_label_rtx ();
2119 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2120 operands[3], label));
2121 }
2122 else
2123 operands[2] = force_reg (SImode, operands[2]);
2124
2125 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2126 operands[3]));
2127 if (label)
2128 emit_label (label);
2129
2130 DONE;
2131 }")
2132
2133 ;; AIX architecture-independent common-mode multiply (DImode),
2134 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2135 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2136 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2137 ;; assumed unused if generating common-mode, so ignore.
2138 (define_insn "mulh_call"
2139 [(set (reg:SI 3)
2140 (truncate:SI
2141 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2142 (sign_extend:DI (reg:SI 4)))
2143 (const_int 32))))
2144 (clobber (match_scratch:SI 0 "=l"))]
2145 "! TARGET_POWER && ! TARGET_POWERPC"
2146 "bla __mulh"
2147 [(set_attr "type" "imul")])
2148
2149 (define_insn "mull_call"
2150 [(set (reg:DI 3)
2151 (mult:DI (sign_extend:DI (reg:SI 3))
2152 (sign_extend:DI (reg:SI 4))))
2153 (clobber (match_scratch:SI 0 "=l"))
2154 (clobber (reg:SI 0))]
2155 "! TARGET_POWER && ! TARGET_POWERPC"
2156 "bla __mull"
2157 [(set_attr "type" "imul")])
2158
2159 (define_insn "divss_call"
2160 [(set (reg:SI 3)
2161 (div:SI (reg:SI 3) (reg:SI 4)))
2162 (set (reg:SI 4)
2163 (mod:SI (reg:SI 3) (reg:SI 4)))
2164 (clobber (match_scratch:SI 0 "=l"))
2165 (clobber (reg:SI 0))]
2166 "! TARGET_POWER && ! TARGET_POWERPC"
2167 "bla __divss"
2168 [(set_attr "type" "idiv")])
2169
2170 (define_insn "divus_call"
2171 [(set (reg:SI 3)
2172 (udiv:SI (reg:SI 3) (reg:SI 4)))
2173 (set (reg:SI 4)
2174 (umod:SI (reg:SI 3) (reg:SI 4)))
2175 (clobber (match_scratch:SI 0 "=l"))
2176 (clobber (reg:SI 0))
2177 (clobber (match_scratch:CC 1 "=x"))
2178 (clobber (reg:CC 69))]
2179 "! TARGET_POWER && ! TARGET_POWERPC"
2180 "bla __divus"
2181 [(set_attr "type" "idiv")])
2182
2183 (define_insn "quoss_call"
2184 [(set (reg:SI 3)
2185 (div:SI (reg:SI 3) (reg:SI 4)))
2186 (clobber (match_scratch:SI 0 "=l"))]
2187 "! TARGET_POWER && ! TARGET_POWERPC"
2188 "bla __quoss"
2189 [(set_attr "type" "idiv")])
2190
2191 (define_insn "quous_call"
2192 [(set (reg:SI 3)
2193 (udiv:SI (reg:SI 3) (reg:SI 4)))
2194 (clobber (match_scratch:SI 0 "=l"))
2195 (clobber (reg:SI 0))
2196 (clobber (match_scratch:CC 1 "=x"))
2197 (clobber (reg:CC 69))]
2198 "! TARGET_POWER && ! TARGET_POWERPC"
2199 "bla __quous"
2200 [(set_attr "type" "idiv")])
2201 \f
2202 ;; Logical instructions
2203 ;; The logical instructions are mostly combined by using match_operator,
2204 ;; but the plain AND insns are somewhat different because there is no
2205 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2206 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2207
2208 (define_insn "andsi3"
2209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2210 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2211 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2212 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2213 ""
2214 "@
2215 and %0,%1,%2
2216 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2217 {andil.|andi.} %0,%1,%b2
2218 {andiu.|andis.} %0,%1,%u2")
2219
2220 ;; Note to set cr's other than cr0 we do the and immediate and then
2221 ;; the test again -- this avoids a mfcr which on the higher end
2222 ;; machines causes an execution serialization
2223
2224 (define_insn "*andsi3_internal2"
2225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2226 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2227 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2228 (const_int 0)))
2229 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2230 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2231 "TARGET_32BIT"
2232 "@
2233 and. %3,%1,%2
2234 {andil.|andi.} %3,%1,%b2
2235 {andiu.|andis.} %3,%1,%u2
2236 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2237 #
2238 #
2239 #
2240 #"
2241 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2242 (set_attr "length" "4,4,4,4,8,8,8,8")])
2243
2244 (define_insn "*andsi3_internal3"
2245 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2246 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2247 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2248 (const_int 0)))
2249 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2250 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2251 "TARGET_64BIT"
2252 "@
2253 #
2254 {andil.|andi.} %3,%1,%b2
2255 {andiu.|andis.} %3,%1,%u2
2256 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2257 #
2258 #
2259 #
2260 #"
2261 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2262 (set_attr "length" "8,4,4,4,8,8,8,8")])
2263
2264 (define_split
2265 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2266 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2267 (match_operand:SI 2 "and_operand" ""))
2268 (const_int 0)))
2269 (clobber (match_scratch:SI 3 ""))
2270 (clobber (match_scratch:CC 4 ""))]
2271 "reload_completed"
2272 [(parallel [(set (match_dup 3)
2273 (and:SI (match_dup 1)
2274 (match_dup 2)))
2275 (clobber (match_dup 4))])
2276 (set (match_dup 0)
2277 (compare:CC (match_dup 3)
2278 (const_int 0)))]
2279 "")
2280
2281 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2282 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2283
2284 (define_split
2285 [(set (match_operand:CC 0 "cc_reg_operand" "")
2286 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2287 (match_operand:SI 2 "gpc_reg_operand" ""))
2288 (const_int 0)))
2289 (clobber (match_scratch:SI 3 ""))
2290 (clobber (match_scratch:CC 4 ""))]
2291 "TARGET_POWERPC64 && reload_completed"
2292 [(parallel [(set (match_dup 3)
2293 (and:SI (match_dup 1)
2294 (match_dup 2)))
2295 (clobber (match_dup 4))])
2296 (set (match_dup 0)
2297 (compare:CC (match_dup 3)
2298 (const_int 0)))]
2299 "")
2300
2301 (define_insn "*andsi3_internal4"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2305 (const_int 0)))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2307 (and:SI (match_dup 1)
2308 (match_dup 2)))
2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2310 "TARGET_32BIT"
2311 "@
2312 and. %0,%1,%2
2313 {andil.|andi.} %0,%1,%b2
2314 {andiu.|andis.} %0,%1,%u2
2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2316 #
2317 #
2318 #
2319 #"
2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2321 (set_attr "length" "4,4,4,4,8,8,8,8")])
2322
2323 (define_insn "*andsi3_internal5"
2324 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2326 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2327 (const_int 0)))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2329 (and:SI (match_dup 1)
2330 (match_dup 2)))
2331 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2332 "TARGET_64BIT"
2333 "@
2334 #
2335 {andil.|andi.} %0,%1,%b2
2336 {andiu.|andis.} %0,%1,%u2
2337 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2338 #
2339 #
2340 #
2341 #"
2342 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2343 (set_attr "length" "8,4,4,4,8,8,8,8")])
2344
2345 (define_split
2346 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2347 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2348 (match_operand:SI 2 "and_operand" ""))
2349 (const_int 0)))
2350 (set (match_operand:SI 0 "gpc_reg_operand" "")
2351 (and:SI (match_dup 1)
2352 (match_dup 2)))
2353 (clobber (match_scratch:CC 4 ""))]
2354 "reload_completed"
2355 [(parallel [(set (match_dup 0)
2356 (and:SI (match_dup 1)
2357 (match_dup 2)))
2358 (clobber (match_dup 4))])
2359 (set (match_dup 3)
2360 (compare:CC (match_dup 0)
2361 (const_int 0)))]
2362 "")
2363
2364 (define_split
2365 [(set (match_operand:CC 3 "cc_reg_operand" "")
2366 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2367 (match_operand:SI 2 "gpc_reg_operand" ""))
2368 (const_int 0)))
2369 (set (match_operand:SI 0 "gpc_reg_operand" "")
2370 (and:SI (match_dup 1)
2371 (match_dup 2)))
2372 (clobber (match_scratch:CC 4 ""))]
2373 "TARGET_POWERPC64 && reload_completed"
2374 [(parallel [(set (match_dup 0)
2375 (and:SI (match_dup 1)
2376 (match_dup 2)))
2377 (clobber (match_dup 4))])
2378 (set (match_dup 3)
2379 (compare:CC (match_dup 0)
2380 (const_int 0)))]
2381 "")
2382
2383 ;; Handle the PowerPC64 rlwinm corner case
2384
2385 (define_insn_and_split "*andsi3_internal6"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2387 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2388 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2389 "TARGET_POWERPC64"
2390 "#"
2391 "TARGET_POWERPC64"
2392 [(set (match_dup 0)
2393 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2394 (match_dup 4)))
2395 (set (match_dup 0)
2396 (rotate:SI (match_dup 0) (match_dup 5)))]
2397 "
2398 {
2399 int mb = extract_MB (operands[2]);
2400 int me = extract_ME (operands[2]);
2401 operands[3] = GEN_INT (me + 1);
2402 operands[5] = GEN_INT (32 - (me + 1));
2403 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2404 }"
2405 [(set_attr "length" "8")])
2406
2407 (define_insn_and_split "*andsi3_internal7"
2408 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2409 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2410 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2411 (const_int 0)))
2412 (clobber (match_scratch:SI 3 "=r,r"))]
2413 "TARGET_POWERPC64"
2414 "#"
2415 "TARGET_POWERPC64"
2416 [(parallel [(set (match_dup 2)
2417 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2418 (match_dup 5))
2419 (const_int 0)))
2420 (clobber (match_dup 3))])]
2421 "
2422 {
2423 int mb = extract_MB (operands[1]);
2424 int me = extract_ME (operands[1]);
2425 operands[4] = GEN_INT (me + 1);
2426 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2427 }"
2428 [(set_attr "type" "delayed_compare,compare")
2429 (set_attr "length" "4,8")])
2430
2431 (define_insn_and_split "*andsi3_internal8"
2432 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2433 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2434 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2435 (const_int 0)))
2436 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2437 (and:SI (match_dup 1)
2438 (match_dup 2)))]
2439 "TARGET_POWERPC64"
2440 "#"
2441 "TARGET_POWERPC64"
2442 [(parallel [(set (match_dup 3)
2443 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2444 (match_dup 5))
2445 (const_int 0)))
2446 (set (match_dup 0)
2447 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2448 (match_dup 5)))])
2449 (set (match_dup 0)
2450 (rotate:SI (match_dup 0) (match_dup 6)))]
2451 "
2452 {
2453 int mb = extract_MB (operands[2]);
2454 int me = extract_ME (operands[2]);
2455 operands[4] = GEN_INT (me + 1);
2456 operands[6] = GEN_INT (32 - (me + 1));
2457 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2458 }"
2459 [(set_attr "type" "delayed_compare,compare")
2460 (set_attr "length" "8,12")])
2461
2462 (define_expand "iorsi3"
2463 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2464 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2465 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2466 ""
2467 "
2468 {
2469 if (GET_CODE (operands[2]) == CONST_INT
2470 && ! logical_operand (operands[2], SImode))
2471 {
2472 HOST_WIDE_INT value = INTVAL (operands[2]);
2473 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2474 ? operands[0] : gen_reg_rtx (SImode));
2475
2476 emit_insn (gen_iorsi3 (tmp, operands[1],
2477 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2478 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2479 DONE;
2480 }
2481 }")
2482
2483 (define_expand "xorsi3"
2484 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2485 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2486 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2487 ""
2488 "
2489 {
2490 if (GET_CODE (operands[2]) == CONST_INT
2491 && ! logical_operand (operands[2], SImode))
2492 {
2493 HOST_WIDE_INT value = INTVAL (operands[2]);
2494 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2495 ? operands[0] : gen_reg_rtx (SImode));
2496
2497 emit_insn (gen_xorsi3 (tmp, operands[1],
2498 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2499 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2500 DONE;
2501 }
2502 }")
2503
2504 (define_insn "*boolsi3_internal1"
2505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2506 (match_operator:SI 3 "boolean_or_operator"
2507 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2508 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2509 ""
2510 "@
2511 %q3 %0,%1,%2
2512 {%q3il|%q3i} %0,%1,%b2
2513 {%q3iu|%q3is} %0,%1,%u2")
2514
2515 (define_insn "*boolsi3_internal2"
2516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2517 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2518 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2519 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2520 (const_int 0)))
2521 (clobber (match_scratch:SI 3 "=r,r"))]
2522 "TARGET_32BIT"
2523 "@
2524 %q4. %3,%1,%2
2525 #"
2526 [(set_attr "type" "compare")
2527 (set_attr "length" "4,8")])
2528
2529 (define_split
2530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2531 (compare:CC (match_operator:SI 4 "boolean_operator"
2532 [(match_operand:SI 1 "gpc_reg_operand" "")
2533 (match_operand:SI 2 "gpc_reg_operand" "")])
2534 (const_int 0)))
2535 (clobber (match_scratch:SI 3 ""))]
2536 "TARGET_32BIT && reload_completed"
2537 [(set (match_dup 3) (match_dup 4))
2538 (set (match_dup 0)
2539 (compare:CC (match_dup 3)
2540 (const_int 0)))]
2541 "")
2542
2543 (define_insn "*boolsi3_internal3"
2544 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2545 (compare:CC (match_operator:SI 4 "boolean_operator"
2546 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2547 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2548 (const_int 0)))
2549 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2550 (match_dup 4))]
2551 "TARGET_32BIT"
2552 "@
2553 %q4. %0,%1,%2
2554 #"
2555 [(set_attr "type" "compare")
2556 (set_attr "length" "4,8")])
2557
2558 (define_split
2559 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2560 (compare:CC (match_operator:SI 4 "boolean_operator"
2561 [(match_operand:SI 1 "gpc_reg_operand" "")
2562 (match_operand:SI 2 "gpc_reg_operand" "")])
2563 (const_int 0)))
2564 (set (match_operand:SI 0 "gpc_reg_operand" "")
2565 (match_dup 4))]
2566 "TARGET_32BIT && reload_completed"
2567 [(set (match_dup 0) (match_dup 4))
2568 (set (match_dup 3)
2569 (compare:CC (match_dup 0)
2570 (const_int 0)))]
2571 "")
2572
2573 ;; Split a logical operation that we can't do in one insn into two insns,
2574 ;; each of which does one 16-bit part. This is used by combine.
2575
2576 (define_split
2577 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2578 (match_operator:SI 3 "boolean_or_operator"
2579 [(match_operand:SI 1 "gpc_reg_operand" "")
2580 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2581 ""
2582 [(set (match_dup 0) (match_dup 4))
2583 (set (match_dup 0) (match_dup 5))]
2584 "
2585 {
2586 rtx i;
2587 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2588 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2589 operands[1], i);
2590 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2591 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2592 operands[0], i);
2593 }")
2594
2595 (define_insn "*boolcsi3_internal1"
2596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2597 (match_operator:SI 3 "boolean_operator"
2598 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2599 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2600 ""
2601 "%q3 %0,%2,%1")
2602
2603 (define_insn "*boolcsi3_internal2"
2604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2605 (compare:CC (match_operator:SI 4 "boolean_operator"
2606 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2607 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2608 (const_int 0)))
2609 (clobber (match_scratch:SI 3 "=r,r"))]
2610 "TARGET_32BIT"
2611 "@
2612 %q4. %3,%2,%1
2613 #"
2614 [(set_attr "type" "compare")
2615 (set_attr "length" "4,8")])
2616
2617 (define_split
2618 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2619 (compare:CC (match_operator:SI 4 "boolean_operator"
2620 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2621 (match_operand:SI 2 "gpc_reg_operand" "")])
2622 (const_int 0)))
2623 (clobber (match_scratch:SI 3 ""))]
2624 "TARGET_32BIT && reload_completed"
2625 [(set (match_dup 3) (match_dup 4))
2626 (set (match_dup 0)
2627 (compare:CC (match_dup 3)
2628 (const_int 0)))]
2629 "")
2630
2631 (define_insn "*boolcsi3_internal3"
2632 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2633 (compare:CC (match_operator:SI 4 "boolean_operator"
2634 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2635 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2636 (const_int 0)))
2637 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2638 (match_dup 4))]
2639 "TARGET_32BIT"
2640 "@
2641 %q4. %0,%2,%1
2642 #"
2643 [(set_attr "type" "compare")
2644 (set_attr "length" "4,8")])
2645
2646 (define_split
2647 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2648 (compare:CC (match_operator:SI 4 "boolean_operator"
2649 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2650 (match_operand:SI 2 "gpc_reg_operand" "")])
2651 (const_int 0)))
2652 (set (match_operand:SI 0 "gpc_reg_operand" "")
2653 (match_dup 4))]
2654 "TARGET_32BIT && reload_completed"
2655 [(set (match_dup 0) (match_dup 4))
2656 (set (match_dup 3)
2657 (compare:CC (match_dup 0)
2658 (const_int 0)))]
2659 "")
2660
2661 (define_insn "*boolccsi3_internal1"
2662 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2663 (match_operator:SI 3 "boolean_operator"
2664 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2665 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2666 ""
2667 "%q3 %0,%1,%2")
2668
2669 (define_insn "*boolccsi3_internal2"
2670 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2671 (compare:CC (match_operator:SI 4 "boolean_operator"
2672 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2673 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2674 (const_int 0)))
2675 (clobber (match_scratch:SI 3 "=r,r"))]
2676 "TARGET_32BIT"
2677 "@
2678 %q4. %3,%1,%2
2679 #"
2680 [(set_attr "type" "compare")
2681 (set_attr "length" "4,8")])
2682
2683 (define_split
2684 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2685 (compare:CC (match_operator:SI 4 "boolean_operator"
2686 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2687 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2688 (const_int 0)))
2689 (clobber (match_scratch:SI 3 ""))]
2690 "TARGET_32BIT && reload_completed"
2691 [(set (match_dup 3) (match_dup 4))
2692 (set (match_dup 0)
2693 (compare:CC (match_dup 3)
2694 (const_int 0)))]
2695 "")
2696
2697 (define_insn "*boolccsi3_internal3"
2698 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2699 (compare:CC (match_operator:SI 4 "boolean_operator"
2700 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2701 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2702 (const_int 0)))
2703 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2704 (match_dup 4))]
2705 "TARGET_32BIT"
2706 "@
2707 %q4. %0,%1,%2
2708 #"
2709 [(set_attr "type" "compare")
2710 (set_attr "length" "4,8")])
2711
2712 (define_split
2713 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2714 (compare:CC (match_operator:SI 4 "boolean_operator"
2715 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2716 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2717 (const_int 0)))
2718 (set (match_operand:SI 0 "gpc_reg_operand" "")
2719 (match_dup 4))]
2720 "TARGET_32BIT && reload_completed"
2721 [(set (match_dup 0) (match_dup 4))
2722 (set (match_dup 3)
2723 (compare:CC (match_dup 0)
2724 (const_int 0)))]
2725 "")
2726
2727 ;; maskir insn. We need four forms because things might be in arbitrary
2728 ;; orders. Don't define forms that only set CR fields because these
2729 ;; would modify an input register.
2730
2731 (define_insn "*maskir_internal1"
2732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2733 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2734 (match_operand:SI 1 "gpc_reg_operand" "0"))
2735 (and:SI (match_dup 2)
2736 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2737 "TARGET_POWER"
2738 "maskir %0,%3,%2")
2739
2740 (define_insn "*maskir_internal2"
2741 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2742 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2743 (match_operand:SI 1 "gpc_reg_operand" "0"))
2744 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2745 (match_dup 2))))]
2746 "TARGET_POWER"
2747 "maskir %0,%3,%2")
2748
2749 (define_insn "*maskir_internal3"
2750 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2751 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2752 (match_operand:SI 3 "gpc_reg_operand" "r"))
2753 (and:SI (not:SI (match_dup 2))
2754 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2755 "TARGET_POWER"
2756 "maskir %0,%3,%2")
2757
2758 (define_insn "*maskir_internal4"
2759 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2760 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2761 (match_operand:SI 2 "gpc_reg_operand" "r"))
2762 (and:SI (not:SI (match_dup 2))
2763 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2764 "TARGET_POWER"
2765 "maskir %0,%3,%2")
2766
2767 (define_insn "*maskir_internal5"
2768 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2769 (compare:CC
2770 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2771 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2772 (and:SI (match_dup 2)
2773 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2774 (const_int 0)))
2775 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2776 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2777 (and:SI (match_dup 2) (match_dup 3))))]
2778 "TARGET_POWER"
2779 "@
2780 maskir. %0,%3,%2
2781 #"
2782 [(set_attr "type" "compare")
2783 (set_attr "length" "4,8")])
2784
2785 (define_split
2786 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2787 (compare:CC
2788 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2789 (match_operand:SI 1 "gpc_reg_operand" ""))
2790 (and:SI (match_dup 2)
2791 (match_operand:SI 3 "gpc_reg_operand" "")))
2792 (const_int 0)))
2793 (set (match_operand:SI 0 "gpc_reg_operand" "")
2794 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2795 (and:SI (match_dup 2) (match_dup 3))))]
2796 "TARGET_POWER && reload_completed"
2797 [(set (match_dup 0)
2798 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2799 (and:SI (match_dup 2) (match_dup 3))))
2800 (set (match_dup 4)
2801 (compare:CC (match_dup 0)
2802 (const_int 0)))]
2803 "")
2804
2805 (define_insn "*maskir_internal6"
2806 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2807 (compare:CC
2808 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2809 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2810 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2811 (match_dup 2)))
2812 (const_int 0)))
2813 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2814 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2815 (and:SI (match_dup 3) (match_dup 2))))]
2816 "TARGET_POWER"
2817 "@
2818 maskir. %0,%3,%2
2819 #"
2820 [(set_attr "type" "compare")
2821 (set_attr "length" "4,8")])
2822
2823 (define_split
2824 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2825 (compare:CC
2826 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (match_operand:SI 1 "gpc_reg_operand" ""))
2828 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2829 (match_dup 2)))
2830 (const_int 0)))
2831 (set (match_operand:SI 0 "gpc_reg_operand" "")
2832 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2833 (and:SI (match_dup 3) (match_dup 2))))]
2834 "TARGET_POWER && reload_completed"
2835 [(set (match_dup 0)
2836 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2837 (and:SI (match_dup 3) (match_dup 2))))
2838 (set (match_dup 4)
2839 (compare:CC (match_dup 0)
2840 (const_int 0)))]
2841 "")
2842
2843 (define_insn "*maskir_internal7"
2844 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2845 (compare:CC
2846 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2847 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2848 (and:SI (not:SI (match_dup 2))
2849 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2850 (const_int 0)))
2851 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2852 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2853 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2854 "TARGET_POWER"
2855 "@
2856 maskir. %0,%3,%2
2857 #"
2858 [(set_attr "type" "compare")
2859 (set_attr "length" "4,8")])
2860
2861 (define_split
2862 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2863 (compare:CC
2864 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2865 (match_operand:SI 3 "gpc_reg_operand" ""))
2866 (and:SI (not:SI (match_dup 2))
2867 (match_operand:SI 1 "gpc_reg_operand" "")))
2868 (const_int 0)))
2869 (set (match_operand:SI 0 "gpc_reg_operand" "")
2870 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2871 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2872 "TARGET_POWER && reload_completed"
2873 [(set (match_dup 0)
2874 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2875 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2876 (set (match_dup 4)
2877 (compare:CC (match_dup 0)
2878 (const_int 0)))]
2879 "")
2880
2881 (define_insn "*maskir_internal8"
2882 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2883 (compare:CC
2884 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2885 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2886 (and:SI (not:SI (match_dup 2))
2887 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2888 (const_int 0)))
2889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2890 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2891 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2892 "TARGET_POWER"
2893 "@
2894 maskir. %0,%3,%2
2895 #"
2896 [(set_attr "type" "compare")
2897 (set_attr "length" "4,8")])
2898
2899 (define_split
2900 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2901 (compare:CC
2902 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2903 (match_operand:SI 2 "gpc_reg_operand" ""))
2904 (and:SI (not:SI (match_dup 2))
2905 (match_operand:SI 1 "gpc_reg_operand" "")))
2906 (const_int 0)))
2907 (set (match_operand:SI 0 "gpc_reg_operand" "")
2908 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2909 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2910 "TARGET_POWER && reload_completed"
2911 [(set (match_dup 0)
2912 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2913 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2914 (set (match_dup 4)
2915 (compare:CC (match_dup 0)
2916 (const_int 0)))]
2917 "")
2918 \f
2919 ;; Rotate and shift insns, in all their variants. These support shifts,
2920 ;; field inserts and extracts, and various combinations thereof.
2921 (define_expand "insv"
2922 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2923 (match_operand:SI 1 "const_int_operand" "")
2924 (match_operand:SI 2 "const_int_operand" ""))
2925 (match_operand 3 "gpc_reg_operand" ""))]
2926 ""
2927 "
2928 {
2929 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2930 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2931 compiler if the address of the structure is taken later. */
2932 if (GET_CODE (operands[0]) == SUBREG
2933 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2934 FAIL;
2935
2936 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2937 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2938 else
2939 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2940 DONE;
2941 }")
2942
2943 (define_insn "insvsi"
2944 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2945 (match_operand:SI 1 "const_int_operand" "i")
2946 (match_operand:SI 2 "const_int_operand" "i"))
2947 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2948 ""
2949 "*
2950 {
2951 int start = INTVAL (operands[2]) & 31;
2952 int size = INTVAL (operands[1]) & 31;
2953
2954 operands[4] = GEN_INT (32 - start - size);
2955 operands[1] = GEN_INT (start + size - 1);
2956 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2957 }"
2958 [(set_attr "type" "insert_word")])
2959
2960 (define_insn "*insvsi_internal1"
2961 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2962 (match_operand:SI 1 "const_int_operand" "i")
2963 (match_operand:SI 2 "const_int_operand" "i"))
2964 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2965 (match_operand:SI 4 "const_int_operand" "i")))]
2966 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2967 "*
2968 {
2969 int shift = INTVAL (operands[4]) & 31;
2970 int start = INTVAL (operands[2]) & 31;
2971 int size = INTVAL (operands[1]) & 31;
2972
2973 operands[4] = GEN_INT (shift - start - size);
2974 operands[1] = GEN_INT (start + size - 1);
2975 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2976 }"
2977 [(set_attr "type" "insert_word")])
2978
2979 (define_insn "*insvsi_internal2"
2980 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2981 (match_operand:SI 1 "const_int_operand" "i")
2982 (match_operand:SI 2 "const_int_operand" "i"))
2983 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2984 (match_operand:SI 4 "const_int_operand" "i")))]
2985 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2986 "*
2987 {
2988 int shift = INTVAL (operands[4]) & 31;
2989 int start = INTVAL (operands[2]) & 31;
2990 int size = INTVAL (operands[1]) & 31;
2991
2992 operands[4] = GEN_INT (32 - shift - start - size);
2993 operands[1] = GEN_INT (start + size - 1);
2994 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2995 }"
2996 [(set_attr "type" "insert_word")])
2997
2998 (define_insn "*insvsi_internal3"
2999 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3000 (match_operand:SI 1 "const_int_operand" "i")
3001 (match_operand:SI 2 "const_int_operand" "i"))
3002 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3003 (match_operand:SI 4 "const_int_operand" "i")))]
3004 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3005 "*
3006 {
3007 int shift = INTVAL (operands[4]) & 31;
3008 int start = INTVAL (operands[2]) & 31;
3009 int size = INTVAL (operands[1]) & 31;
3010
3011 operands[4] = GEN_INT (32 - shift - start - size);
3012 operands[1] = GEN_INT (start + size - 1);
3013 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3014 }"
3015 [(set_attr "type" "insert_word")])
3016
3017 (define_insn "*insvsi_internal4"
3018 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3019 (match_operand:SI 1 "const_int_operand" "i")
3020 (match_operand:SI 2 "const_int_operand" "i"))
3021 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3022 (match_operand:SI 4 "const_int_operand" "i")
3023 (match_operand:SI 5 "const_int_operand" "i")))]
3024 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3025 "*
3026 {
3027 int extract_start = INTVAL (operands[5]) & 31;
3028 int extract_size = INTVAL (operands[4]) & 31;
3029 int insert_start = INTVAL (operands[2]) & 31;
3030 int insert_size = INTVAL (operands[1]) & 31;
3031
3032 /* Align extract field with insert field */
3033 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3034 operands[1] = GEN_INT (insert_start + insert_size - 1);
3035 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3036 }"
3037 [(set_attr "type" "insert_word")])
3038
3039 ;; combine patterns for rlwimi
3040 (define_insn "*insvsi_internal5"
3041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3042 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3043 (match_operand:SI 1 "mask_operand" "i"))
3044 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3045 (match_operand:SI 2 "const_int_operand" "i"))
3046 (match_operand:SI 5 "mask_operand" "i"))))]
3047 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3048 "*
3049 {
3050 int me = extract_ME(operands[5]);
3051 int mb = extract_MB(operands[5]);
3052 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3053 operands[2] = GEN_INT(mb);
3054 operands[1] = GEN_INT(me);
3055 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3056 }"
3057 [(set_attr "type" "insert_word")])
3058
3059 (define_insn "*insvsi_internal6"
3060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3061 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3062 (match_operand:SI 2 "const_int_operand" "i"))
3063 (match_operand:SI 5 "mask_operand" "i"))
3064 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3065 (match_operand:SI 1 "mask_operand" "i"))))]
3066 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3067 "*
3068 {
3069 int me = extract_ME(operands[5]);
3070 int mb = extract_MB(operands[5]);
3071 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3072 operands[2] = GEN_INT(mb);
3073 operands[1] = GEN_INT(me);
3074 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3075 }"
3076 [(set_attr "type" "insert_word")])
3077
3078 (define_insn "insvdi"
3079 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3080 (match_operand:SI 1 "const_int_operand" "i")
3081 (match_operand:SI 2 "const_int_operand" "i"))
3082 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3083 "TARGET_POWERPC64"
3084 "*
3085 {
3086 int start = INTVAL (operands[2]) & 63;
3087 int size = INTVAL (operands[1]) & 63;
3088
3089 operands[1] = GEN_INT (64 - start - size);
3090 return \"rldimi %0,%3,%H1,%H2\";
3091 }")
3092
3093 (define_insn "*insvdi_internal2"
3094 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3095 (match_operand:SI 1 "const_int_operand" "i")
3096 (match_operand:SI 2 "const_int_operand" "i"))
3097 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3098 (match_operand:SI 4 "const_int_operand" "i")))]
3099 "TARGET_POWERPC64
3100 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3101 "*
3102 {
3103 int shift = INTVAL (operands[4]) & 63;
3104 int start = (INTVAL (operands[2]) & 63) - 32;
3105 int size = INTVAL (operands[1]) & 63;
3106
3107 operands[4] = GEN_INT (64 - shift - start - size);
3108 operands[2] = GEN_INT (start);
3109 operands[1] = GEN_INT (start + size - 1);
3110 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3111 }")
3112
3113 (define_insn "*insvdi_internal3"
3114 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3115 (match_operand:SI 1 "const_int_operand" "i")
3116 (match_operand:SI 2 "const_int_operand" "i"))
3117 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3118 (match_operand:SI 4 "const_int_operand" "i")))]
3119 "TARGET_POWERPC64
3120 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3121 "*
3122 {
3123 int shift = INTVAL (operands[4]) & 63;
3124 int start = (INTVAL (operands[2]) & 63) - 32;
3125 int size = INTVAL (operands[1]) & 63;
3126
3127 operands[4] = GEN_INT (64 - shift - start - size);
3128 operands[2] = GEN_INT (start);
3129 operands[1] = GEN_INT (start + size - 1);
3130 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3131 }")
3132
3133 (define_expand "extzv"
3134 [(set (match_operand 0 "gpc_reg_operand" "")
3135 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3136 (match_operand:SI 2 "const_int_operand" "")
3137 (match_operand:SI 3 "const_int_operand" "")))]
3138 ""
3139 "
3140 {
3141 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3142 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3143 compiler if the address of the structure is taken later. */
3144 if (GET_CODE (operands[0]) == SUBREG
3145 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3146 FAIL;
3147
3148 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3149 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3150 else
3151 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3152 DONE;
3153 }")
3154
3155 (define_insn "extzvsi"
3156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3157 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3158 (match_operand:SI 2 "const_int_operand" "i")
3159 (match_operand:SI 3 "const_int_operand" "i")))]
3160 ""
3161 "*
3162 {
3163 int start = INTVAL (operands[3]) & 31;
3164 int size = INTVAL (operands[2]) & 31;
3165
3166 if (start + size >= 32)
3167 operands[3] = const0_rtx;
3168 else
3169 operands[3] = GEN_INT (start + size);
3170 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3171 }")
3172
3173 (define_insn "*extzvsi_internal1"
3174 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3175 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3176 (match_operand:SI 2 "const_int_operand" "i,i")
3177 (match_operand:SI 3 "const_int_operand" "i,i"))
3178 (const_int 0)))
3179 (clobber (match_scratch:SI 4 "=r,r"))]
3180 ""
3181 "*
3182 {
3183 int start = INTVAL (operands[3]) & 31;
3184 int size = INTVAL (operands[2]) & 31;
3185
3186 /* Force split for non-cc0 compare. */
3187 if (which_alternative == 1)
3188 return \"#\";
3189
3190 /* If the bit-field being tested fits in the upper or lower half of a
3191 word, it is possible to use andiu. or andil. to test it. This is
3192 useful because the condition register set-use delay is smaller for
3193 andi[ul]. than for rlinm. This doesn't work when the starting bit
3194 position is 0 because the LT and GT bits may be set wrong. */
3195
3196 if ((start > 0 && start + size <= 16) || start >= 16)
3197 {
3198 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3199 - (1 << (16 - (start & 15) - size))));
3200 if (start < 16)
3201 return \"{andiu.|andis.} %4,%1,%3\";
3202 else
3203 return \"{andil.|andi.} %4,%1,%3\";
3204 }
3205
3206 if (start + size >= 32)
3207 operands[3] = const0_rtx;
3208 else
3209 operands[3] = GEN_INT (start + size);
3210 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3211 }"
3212 [(set_attr "type" "compare")
3213 (set_attr "length" "4,8")])
3214
3215 (define_split
3216 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3217 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3218 (match_operand:SI 2 "const_int_operand" "")
3219 (match_operand:SI 3 "const_int_operand" ""))
3220 (const_int 0)))
3221 (clobber (match_scratch:SI 4 ""))]
3222 "reload_completed"
3223 [(set (match_dup 4)
3224 (zero_extract:SI (match_dup 1) (match_dup 2)
3225 (match_dup 3)))
3226 (set (match_dup 0)
3227 (compare:CC (match_dup 4)
3228 (const_int 0)))]
3229 "")
3230
3231 (define_insn "*extzvsi_internal2"
3232 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3233 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3234 (match_operand:SI 2 "const_int_operand" "i,i")
3235 (match_operand:SI 3 "const_int_operand" "i,i"))
3236 (const_int 0)))
3237 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3238 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3239 ""
3240 "*
3241 {
3242 int start = INTVAL (operands[3]) & 31;
3243 int size = INTVAL (operands[2]) & 31;
3244
3245 /* Force split for non-cc0 compare. */
3246 if (which_alternative == 1)
3247 return \"#\";
3248
3249 /* Since we are using the output value, we can't ignore any need for
3250 a shift. The bit-field must end at the LSB. */
3251 if (start >= 16 && start + size == 32)
3252 {
3253 operands[3] = GEN_INT ((1 << size) - 1);
3254 return \"{andil.|andi.} %0,%1,%3\";
3255 }
3256
3257 if (start + size >= 32)
3258 operands[3] = const0_rtx;
3259 else
3260 operands[3] = GEN_INT (start + size);
3261 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3262 }"
3263 [(set_attr "type" "compare")
3264 (set_attr "length" "4,8")])
3265
3266 (define_split
3267 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3268 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3269 (match_operand:SI 2 "const_int_operand" "")
3270 (match_operand:SI 3 "const_int_operand" ""))
3271 (const_int 0)))
3272 (set (match_operand:SI 0 "gpc_reg_operand" "")
3273 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3274 "reload_completed"
3275 [(set (match_dup 0)
3276 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3277 (set (match_dup 4)
3278 (compare:CC (match_dup 0)
3279 (const_int 0)))]
3280 "")
3281
3282 (define_insn "extzvdi"
3283 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3284 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3285 (match_operand:SI 2 "const_int_operand" "i")
3286 (match_operand:SI 3 "const_int_operand" "i")))]
3287 "TARGET_POWERPC64"
3288 "*
3289 {
3290 int start = INTVAL (operands[3]) & 63;
3291 int size = INTVAL (operands[2]) & 63;
3292
3293 if (start + size >= 64)
3294 operands[3] = const0_rtx;
3295 else
3296 operands[3] = GEN_INT (start + size);
3297 operands[2] = GEN_INT (64 - size);
3298 return \"rldicl %0,%1,%3,%2\";
3299 }")
3300
3301 (define_insn "*extzvdi_internal1"
3302 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3303 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3304 (match_operand:SI 2 "const_int_operand" "i")
3305 (match_operand:SI 3 "const_int_operand" "i"))
3306 (const_int 0)))
3307 (clobber (match_scratch:DI 4 "=r"))]
3308 "TARGET_64BIT"
3309 "*
3310 {
3311 int start = INTVAL (operands[3]) & 63;
3312 int size = INTVAL (operands[2]) & 63;
3313
3314 if (start + size >= 64)
3315 operands[3] = const0_rtx;
3316 else
3317 operands[3] = GEN_INT (start + size);
3318 operands[2] = GEN_INT (64 - size);
3319 return \"rldicl. %4,%1,%3,%2\";
3320 }")
3321
3322 (define_insn "*extzvdi_internal2"
3323 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3324 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3325 (match_operand:SI 2 "const_int_operand" "i")
3326 (match_operand:SI 3 "const_int_operand" "i"))
3327 (const_int 0)))
3328 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3329 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3330 "TARGET_64BIT"
3331 "*
3332 {
3333 int start = INTVAL (operands[3]) & 63;
3334 int size = INTVAL (operands[2]) & 63;
3335
3336 if (start + size >= 64)
3337 operands[3] = const0_rtx;
3338 else
3339 operands[3] = GEN_INT (start + size);
3340 operands[2] = GEN_INT (64 - size);
3341 return \"rldicl. %0,%1,%3,%2\";
3342 }")
3343
3344 (define_insn "rotlsi3"
3345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3346 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3347 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3348 ""
3349 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3350
3351 (define_insn "*rotlsi3_internal2"
3352 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3353 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3354 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3355 (const_int 0)))
3356 (clobber (match_scratch:SI 3 "=r,r"))]
3357 ""
3358 "@
3359 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3360 #"
3361 [(set_attr "type" "delayed_compare")
3362 (set_attr "length" "4,8")])
3363
3364 (define_split
3365 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3366 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3367 (match_operand:SI 2 "reg_or_cint_operand" ""))
3368 (const_int 0)))
3369 (clobber (match_scratch:SI 3 ""))]
3370 "reload_completed"
3371 [(set (match_dup 3)
3372 (rotate:SI (match_dup 1) (match_dup 2)))
3373 (set (match_dup 0)
3374 (compare:CC (match_dup 3)
3375 (const_int 0)))]
3376 "")
3377
3378 (define_insn "*rotlsi3_internal3"
3379 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3380 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3381 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3382 (const_int 0)))
3383 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3384 (rotate:SI (match_dup 1) (match_dup 2)))]
3385 ""
3386 "@
3387 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3388 #"
3389 [(set_attr "type" "delayed_compare")
3390 (set_attr "length" "4,8")])
3391
3392 (define_split
3393 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3394 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3395 (match_operand:SI 2 "reg_or_cint_operand" ""))
3396 (const_int 0)))
3397 (set (match_operand:SI 0 "gpc_reg_operand" "")
3398 (rotate:SI (match_dup 1) (match_dup 2)))]
3399 "reload_completed"
3400 [(set (match_dup 0)
3401 (rotate:SI (match_dup 1) (match_dup 2)))
3402 (set (match_dup 3)
3403 (compare:CC (match_dup 0)
3404 (const_int 0)))]
3405 "")
3406
3407 (define_insn "*rotlsi3_internal4"
3408 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3409 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3410 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3411 (match_operand:SI 3 "mask_operand" "n")))]
3412 ""
3413 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3414
3415 (define_insn "*rotlsi3_internal5"
3416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3417 (compare:CC (and:SI
3418 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3419 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3420 (match_operand:SI 3 "mask_operand" "n,n"))
3421 (const_int 0)))
3422 (clobber (match_scratch:SI 4 "=r,r"))]
3423 ""
3424 "@
3425 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3426 #"
3427 [(set_attr "type" "delayed_compare")
3428 (set_attr "length" "4,8")])
3429
3430 (define_split
3431 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3432 (compare:CC (and:SI
3433 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3434 (match_operand:SI 2 "reg_or_cint_operand" ""))
3435 (match_operand:SI 3 "mask_operand" ""))
3436 (const_int 0)))
3437 (clobber (match_scratch:SI 4 ""))]
3438 "reload_completed"
3439 [(set (match_dup 4)
3440 (and:SI (rotate:SI (match_dup 1)
3441 (match_dup 2))
3442 (match_dup 3)))
3443 (set (match_dup 0)
3444 (compare:CC (match_dup 4)
3445 (const_int 0)))]
3446 "")
3447
3448 (define_insn "*rotlsi3_internal6"
3449 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3450 (compare:CC (and:SI
3451 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3452 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3453 (match_operand:SI 3 "mask_operand" "n,n"))
3454 (const_int 0)))
3455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3456 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3457 ""
3458 "@
3459 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3460 #"
3461 [(set_attr "type" "delayed_compare")
3462 (set_attr "length" "4,8")])
3463
3464 (define_split
3465 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3466 (compare:CC (and:SI
3467 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3468 (match_operand:SI 2 "reg_or_cint_operand" ""))
3469 (match_operand:SI 3 "mask_operand" ""))
3470 (const_int 0)))
3471 (set (match_operand:SI 0 "gpc_reg_operand" "")
3472 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3473 "reload_completed"
3474 [(set (match_dup 0)
3475 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3476 (set (match_dup 4)
3477 (compare:CC (match_dup 0)
3478 (const_int 0)))]
3479 "")
3480
3481 (define_insn "*rotlsi3_internal7"
3482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3483 (zero_extend:SI
3484 (subreg:QI
3485 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3486 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3487 ""
3488 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3489
3490 (define_insn "*rotlsi3_internal8"
3491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3492 (compare:CC (zero_extend:SI
3493 (subreg:QI
3494 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3495 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3496 (const_int 0)))
3497 (clobber (match_scratch:SI 3 "=r,r"))]
3498 ""
3499 "@
3500 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3501 #"
3502 [(set_attr "type" "delayed_compare")
3503 (set_attr "length" "4,8")])
3504
3505 (define_split
3506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3507 (compare:CC (zero_extend:SI
3508 (subreg:QI
3509 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3510 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3511 (const_int 0)))
3512 (clobber (match_scratch:SI 3 ""))]
3513 "reload_completed"
3514 [(set (match_dup 3)
3515 (zero_extend:SI (subreg:QI
3516 (rotate:SI (match_dup 1)
3517 (match_dup 2)) 0)))
3518 (set (match_dup 0)
3519 (compare:CC (match_dup 3)
3520 (const_int 0)))]
3521 "")
3522
3523 (define_insn "*rotlsi3_internal9"
3524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3525 (compare:CC (zero_extend:SI
3526 (subreg:QI
3527 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3528 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3529 (const_int 0)))
3530 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3531 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3532 ""
3533 "@
3534 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3535 #"
3536 [(set_attr "type" "delayed_compare")
3537 (set_attr "length" "4,8")])
3538
3539 (define_split
3540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3541 (compare:CC (zero_extend:SI
3542 (subreg:QI
3543 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3544 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3545 (const_int 0)))
3546 (set (match_operand:SI 0 "gpc_reg_operand" "")
3547 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3548 "reload_completed"
3549 [(set (match_dup 0)
3550 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3551 (set (match_dup 3)
3552 (compare:CC (match_dup 0)
3553 (const_int 0)))]
3554 "")
3555
3556 (define_insn "*rotlsi3_internal10"
3557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3558 (zero_extend:SI
3559 (subreg:HI
3560 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3561 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3562 ""
3563 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3564
3565 (define_insn "*rotlsi3_internal11"
3566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3567 (compare:CC (zero_extend:SI
3568 (subreg:HI
3569 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3570 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3571 (const_int 0)))
3572 (clobber (match_scratch:SI 3 "=r,r"))]
3573 ""
3574 "@
3575 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3576 #"
3577 [(set_attr "type" "delayed_compare")
3578 (set_attr "length" "4,8")])
3579
3580 (define_split
3581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3582 (compare:CC (zero_extend:SI
3583 (subreg:HI
3584 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3585 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3586 (const_int 0)))
3587 (clobber (match_scratch:SI 3 ""))]
3588 "reload_completed"
3589 [(set (match_dup 3)
3590 (zero_extend:SI (subreg:HI
3591 (rotate:SI (match_dup 1)
3592 (match_dup 2)) 0)))
3593 (set (match_dup 0)
3594 (compare:CC (match_dup 3)
3595 (const_int 0)))]
3596 "")
3597
3598 (define_insn "*rotlsi3_internal12"
3599 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3600 (compare:CC (zero_extend:SI
3601 (subreg:HI
3602 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3603 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3604 (const_int 0)))
3605 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3606 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3607 ""
3608 "@
3609 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3610 #"
3611 [(set_attr "type" "delayed_compare")
3612 (set_attr "length" "4,8")])
3613
3614 (define_split
3615 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3616 (compare:CC (zero_extend:SI
3617 (subreg:HI
3618 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3619 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3620 (const_int 0)))
3621 (set (match_operand:SI 0 "gpc_reg_operand" "")
3622 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3623 "reload_completed"
3624 [(set (match_dup 0)
3625 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3626 (set (match_dup 3)
3627 (compare:CC (match_dup 0)
3628 (const_int 0)))]
3629 "")
3630
3631 ;; Note that we use "sle." instead of "sl." so that we can set
3632 ;; SHIFT_COUNT_TRUNCATED.
3633
3634 (define_expand "ashlsi3"
3635 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3636 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3637 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3638 ""
3639 "
3640 {
3641 if (TARGET_POWER)
3642 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3643 else
3644 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3645 DONE;
3646 }")
3647
3648 (define_insn "ashlsi3_power"
3649 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3650 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3651 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3652 (clobber (match_scratch:SI 3 "=q,X"))]
3653 "TARGET_POWER"
3654 "@
3655 sle %0,%1,%2
3656 {sli|slwi} %0,%1,%h2")
3657
3658 (define_insn "ashlsi3_no_power"
3659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3660 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3661 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3662 "! TARGET_POWER"
3663 "{sl|slw}%I2 %0,%1,%h2")
3664
3665 (define_insn ""
3666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3667 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3668 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3669 (const_int 0)))
3670 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3671 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3672 "TARGET_POWER"
3673 "@
3674 sle. %3,%1,%2
3675 {sli.|slwi.} %3,%1,%h2
3676 #
3677 #"
3678 [(set_attr "type" "delayed_compare")
3679 (set_attr "length" "4,4,8,8")])
3680
3681 (define_split
3682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3683 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3684 (match_operand:SI 2 "reg_or_cint_operand" ""))
3685 (const_int 0)))
3686 (clobber (match_scratch:SI 3 ""))
3687 (clobber (match_scratch:SI 4 ""))]
3688 "TARGET_POWER && reload_completed"
3689 [(parallel [(set (match_dup 3)
3690 (ashift:SI (match_dup 1) (match_dup 2)))
3691 (clobber (match_dup 4))])
3692 (set (match_dup 0)
3693 (compare:CC (match_dup 3)
3694 (const_int 0)))]
3695 "")
3696
3697 (define_insn ""
3698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3699 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3700 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3701 (const_int 0)))
3702 (clobber (match_scratch:SI 3 "=r,r"))]
3703 "! TARGET_POWER && TARGET_32BIT"
3704 "@
3705 {sl|slw}%I2. %3,%1,%h2
3706 #"
3707 [(set_attr "type" "delayed_compare")
3708 (set_attr "length" "4,8")])
3709
3710 (define_split
3711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3712 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3713 (match_operand:SI 2 "reg_or_cint_operand" ""))
3714 (const_int 0)))
3715 (clobber (match_scratch:SI 3 ""))]
3716 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3717 [(set (match_dup 3)
3718 (ashift:SI (match_dup 1) (match_dup 2)))
3719 (set (match_dup 0)
3720 (compare:CC (match_dup 3)
3721 (const_int 0)))]
3722 "")
3723
3724 (define_insn ""
3725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3726 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3727 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3728 (const_int 0)))
3729 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3730 (ashift:SI (match_dup 1) (match_dup 2)))
3731 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3732 "TARGET_POWER"
3733 "@
3734 sle. %0,%1,%2
3735 {sli.|slwi.} %0,%1,%h2
3736 #
3737 #"
3738 [(set_attr "type" "delayed_compare")
3739 (set_attr "length" "4,4,8,8")])
3740
3741 (define_split
3742 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3743 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3744 (match_operand:SI 2 "reg_or_cint_operand" ""))
3745 (const_int 0)))
3746 (set (match_operand:SI 0 "gpc_reg_operand" "")
3747 (ashift:SI (match_dup 1) (match_dup 2)))
3748 (clobber (match_scratch:SI 4 ""))]
3749 "TARGET_POWER && reload_completed"
3750 [(parallel [(set (match_dup 0)
3751 (ashift:SI (match_dup 1) (match_dup 2)))
3752 (clobber (match_dup 4))])
3753 (set (match_dup 3)
3754 (compare:CC (match_dup 0)
3755 (const_int 0)))]
3756 "")
3757
3758 (define_insn ""
3759 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3760 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3761 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3762 (const_int 0)))
3763 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3764 (ashift:SI (match_dup 1) (match_dup 2)))]
3765 "! TARGET_POWER && TARGET_32BIT"
3766 "@
3767 {sl|slw}%I2. %0,%1,%h2
3768 #"
3769 [(set_attr "type" "delayed_compare")
3770 (set_attr "length" "4,8")])
3771
3772 (define_split
3773 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3774 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3775 (match_operand:SI 2 "reg_or_cint_operand" ""))
3776 (const_int 0)))
3777 (set (match_operand:SI 0 "gpc_reg_operand" "")
3778 (ashift:SI (match_dup 1) (match_dup 2)))]
3779 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3780 [(set (match_dup 0)
3781 (ashift:SI (match_dup 1) (match_dup 2)))
3782 (set (match_dup 3)
3783 (compare:CC (match_dup 0)
3784 (const_int 0)))]
3785 "")
3786
3787 (define_insn ""
3788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3789 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3790 (match_operand:SI 2 "const_int_operand" "i"))
3791 (match_operand:SI 3 "mask_operand" "n")))]
3792 "includes_lshift_p (operands[2], operands[3])"
3793 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3794
3795 (define_insn ""
3796 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3797 (compare:CC
3798 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3799 (match_operand:SI 2 "const_int_operand" "i,i"))
3800 (match_operand:SI 3 "mask_operand" "n,n"))
3801 (const_int 0)))
3802 (clobber (match_scratch:SI 4 "=r,r"))]
3803 "includes_lshift_p (operands[2], operands[3])"
3804 "@
3805 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3806 #"
3807 [(set_attr "type" "delayed_compare")
3808 (set_attr "length" "4,8")])
3809
3810 (define_split
3811 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3812 (compare:CC
3813 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3814 (match_operand:SI 2 "const_int_operand" ""))
3815 (match_operand:SI 3 "mask_operand" ""))
3816 (const_int 0)))
3817 (clobber (match_scratch:SI 4 ""))]
3818 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3819 [(set (match_dup 4)
3820 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3821 (match_dup 3)))
3822 (set (match_dup 0)
3823 (compare:CC (match_dup 4)
3824 (const_int 0)))]
3825 "")
3826
3827 (define_insn ""
3828 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3829 (compare:CC
3830 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3831 (match_operand:SI 2 "const_int_operand" "i,i"))
3832 (match_operand:SI 3 "mask_operand" "n,n"))
3833 (const_int 0)))
3834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3835 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3836 "includes_lshift_p (operands[2], operands[3])"
3837 "@
3838 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3839 #"
3840 [(set_attr "type" "delayed_compare")
3841 (set_attr "length" "4,8")])
3842
3843 (define_split
3844 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3845 (compare:CC
3846 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3847 (match_operand:SI 2 "const_int_operand" ""))
3848 (match_operand:SI 3 "mask_operand" ""))
3849 (const_int 0)))
3850 (set (match_operand:SI 0 "gpc_reg_operand" "")
3851 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3852 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3853 [(set (match_dup 0)
3854 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3855 (set (match_dup 4)
3856 (compare:CC (match_dup 0)
3857 (const_int 0)))]
3858 "")
3859
3860 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3861 ;; "sli x,x,0".
3862 (define_expand "lshrsi3"
3863 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3864 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3865 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3866 ""
3867 "
3868 {
3869 if (TARGET_POWER)
3870 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3871 else
3872 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3873 DONE;
3874 }")
3875
3876 (define_insn "lshrsi3_power"
3877 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3878 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3879 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3880 (clobber (match_scratch:SI 3 "=q,X,X"))]
3881 "TARGET_POWER"
3882 "@
3883 sre %0,%1,%2
3884 mr %0,%1
3885 {s%A2i|s%A2wi} %0,%1,%h2")
3886
3887 (define_insn "lshrsi3_no_power"
3888 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3889 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3890 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3891 "! TARGET_POWER"
3892 "@
3893 mr %0,%1
3894 {sr|srw}%I2 %0,%1,%h2")
3895
3896 (define_insn ""
3897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3898 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3899 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3900 (const_int 0)))
3901 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3902 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3903 "TARGET_POWER"
3904 "@
3905 sre. %3,%1,%2
3906 mr. %1,%1
3907 {s%A2i.|s%A2wi.} %3,%1,%h2
3908 #
3909 #
3910 #"
3911 [(set_attr "type" "delayed_compare")
3912 (set_attr "length" "4,4,4,8,8,8")])
3913
3914 (define_split
3915 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3916 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3917 (match_operand:SI 2 "reg_or_cint_operand" ""))
3918 (const_int 0)))
3919 (clobber (match_scratch:SI 3 ""))
3920 (clobber (match_scratch:SI 4 ""))]
3921 "TARGET_POWER && reload_completed"
3922 [(parallel [(set (match_dup 3)
3923 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3924 (clobber (match_dup 4))])
3925 (set (match_dup 0)
3926 (compare:CC (match_dup 3)
3927 (const_int 0)))]
3928 "")
3929
3930 (define_insn ""
3931 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3932 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3933 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3934 (const_int 0)))
3935 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3936 "! TARGET_POWER && TARGET_32BIT"
3937 "@
3938 mr. %1,%1
3939 {sr|srw}%I2. %3,%1,%h2
3940 #
3941 #"
3942 [(set_attr "type" "delayed_compare")
3943 (set_attr "length" "4,4,8,8")])
3944
3945 (define_split
3946 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3947 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3948 (match_operand:SI 2 "reg_or_cint_operand" ""))
3949 (const_int 0)))
3950 (clobber (match_scratch:SI 3 ""))]
3951 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3952 [(set (match_dup 3)
3953 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3954 (set (match_dup 0)
3955 (compare:CC (match_dup 3)
3956 (const_int 0)))]
3957 "")
3958
3959 (define_insn ""
3960 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3961 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3962 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3963 (const_int 0)))
3964 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3965 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3966 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3967 "TARGET_POWER"
3968 "@
3969 sre. %0,%1,%2
3970 mr. %0,%1
3971 {s%A2i.|s%A2wi.} %0,%1,%h2
3972 #
3973 #
3974 #"
3975 [(set_attr "type" "delayed_compare")
3976 (set_attr "length" "4,4,4,8,8,8")])
3977
3978 (define_split
3979 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3980 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3981 (match_operand:SI 2 "reg_or_cint_operand" ""))
3982 (const_int 0)))
3983 (set (match_operand:SI 0 "gpc_reg_operand" "")
3984 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3985 (clobber (match_scratch:SI 4 ""))]
3986 "TARGET_POWER && reload_completed"
3987 [(parallel [(set (match_dup 0)
3988 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3989 (clobber (match_dup 4))])
3990 (set (match_dup 3)
3991 (compare:CC (match_dup 0)
3992 (const_int 0)))]
3993 "")
3994
3995 (define_insn ""
3996 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3997 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3998 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3999 (const_int 0)))
4000 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4001 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4002 "! TARGET_POWER && TARGET_32BIT"
4003 "@
4004 mr. %0,%1
4005 {sr|srw}%I2. %0,%1,%h2
4006 #
4007 #"
4008 [(set_attr "type" "delayed_compare")
4009 (set_attr "length" "4,4,8,8")])
4010
4011 (define_split
4012 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4013 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4014 (match_operand:SI 2 "reg_or_cint_operand" ""))
4015 (const_int 0)))
4016 (set (match_operand:SI 0 "gpc_reg_operand" "")
4017 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4018 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4019 [(set (match_dup 0)
4020 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4021 (set (match_dup 3)
4022 (compare:CC (match_dup 0)
4023 (const_int 0)))]
4024 "")
4025
4026 (define_insn ""
4027 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4028 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4029 (match_operand:SI 2 "const_int_operand" "i"))
4030 (match_operand:SI 3 "mask_operand" "n")))]
4031 "includes_rshift_p (operands[2], operands[3])"
4032 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4033
4034 (define_insn ""
4035 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4036 (compare:CC
4037 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4038 (match_operand:SI 2 "const_int_operand" "i,i"))
4039 (match_operand:SI 3 "mask_operand" "n,n"))
4040 (const_int 0)))
4041 (clobber (match_scratch:SI 4 "=r,r"))]
4042 "includes_rshift_p (operands[2], operands[3])"
4043 "@
4044 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4045 #"
4046 [(set_attr "type" "delayed_compare")
4047 (set_attr "length" "4,8")])
4048
4049 (define_split
4050 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4051 (compare:CC
4052 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4053 (match_operand:SI 2 "const_int_operand" ""))
4054 (match_operand:SI 3 "mask_operand" ""))
4055 (const_int 0)))
4056 (clobber (match_scratch:SI 4 ""))]
4057 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4058 [(set (match_dup 4)
4059 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4060 (match_dup 3)))
4061 (set (match_dup 0)
4062 (compare:CC (match_dup 4)
4063 (const_int 0)))]
4064 "")
4065
4066 (define_insn ""
4067 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4068 (compare:CC
4069 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4070 (match_operand:SI 2 "const_int_operand" "i,i"))
4071 (match_operand:SI 3 "mask_operand" "n,n"))
4072 (const_int 0)))
4073 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4074 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4075 "includes_rshift_p (operands[2], operands[3])"
4076 "@
4077 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4078 #"
4079 [(set_attr "type" "delayed_compare")
4080 (set_attr "length" "4,8")])
4081
4082 (define_split
4083 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4084 (compare:CC
4085 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4086 (match_operand:SI 2 "const_int_operand" ""))
4087 (match_operand:SI 3 "mask_operand" ""))
4088 (const_int 0)))
4089 (set (match_operand:SI 0 "gpc_reg_operand" "")
4090 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4091 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4092 [(set (match_dup 0)
4093 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4094 (set (match_dup 4)
4095 (compare:CC (match_dup 0)
4096 (const_int 0)))]
4097 "")
4098
4099 (define_insn ""
4100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4101 (zero_extend:SI
4102 (subreg:QI
4103 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4104 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4105 "includes_rshift_p (operands[2], GEN_INT (255))"
4106 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4107
4108 (define_insn ""
4109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4110 (compare:CC
4111 (zero_extend:SI
4112 (subreg:QI
4113 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4114 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4115 (const_int 0)))
4116 (clobber (match_scratch:SI 3 "=r,r"))]
4117 "includes_rshift_p (operands[2], GEN_INT (255))"
4118 "@
4119 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4120 #"
4121 [(set_attr "type" "delayed_compare")
4122 (set_attr "length" "4,8")])
4123
4124 (define_split
4125 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4126 (compare:CC
4127 (zero_extend:SI
4128 (subreg:QI
4129 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4130 (match_operand:SI 2 "const_int_operand" "")) 0))
4131 (const_int 0)))
4132 (clobber (match_scratch:SI 3 ""))]
4133 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4134 [(set (match_dup 3)
4135 (zero_extend:SI (subreg:QI
4136 (lshiftrt:SI (match_dup 1)
4137 (match_dup 2)) 0)))
4138 (set (match_dup 0)
4139 (compare:CC (match_dup 3)
4140 (const_int 0)))]
4141 "")
4142
4143 (define_insn ""
4144 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4145 (compare:CC
4146 (zero_extend:SI
4147 (subreg:QI
4148 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4149 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4150 (const_int 0)))
4151 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4152 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4153 "includes_rshift_p (operands[2], GEN_INT (255))"
4154 "@
4155 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4156 #"
4157 [(set_attr "type" "delayed_compare")
4158 (set_attr "length" "4,8")])
4159
4160 (define_split
4161 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4162 (compare:CC
4163 (zero_extend:SI
4164 (subreg:QI
4165 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4166 (match_operand:SI 2 "const_int_operand" "")) 0))
4167 (const_int 0)))
4168 (set (match_operand:SI 0 "gpc_reg_operand" "")
4169 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4170 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4171 [(set (match_dup 0)
4172 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4173 (set (match_dup 3)
4174 (compare:CC (match_dup 0)
4175 (const_int 0)))]
4176 "")
4177
4178 (define_insn ""
4179 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4180 (zero_extend:SI
4181 (subreg:HI
4182 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4183 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4184 "includes_rshift_p (operands[2], GEN_INT (65535))"
4185 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4186
4187 (define_insn ""
4188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4189 (compare:CC
4190 (zero_extend:SI
4191 (subreg:HI
4192 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4193 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4194 (const_int 0)))
4195 (clobber (match_scratch:SI 3 "=r,r"))]
4196 "includes_rshift_p (operands[2], GEN_INT (65535))"
4197 "@
4198 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4199 #"
4200 [(set_attr "type" "delayed_compare")
4201 (set_attr "length" "4,8")])
4202
4203 (define_split
4204 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4205 (compare:CC
4206 (zero_extend:SI
4207 (subreg:HI
4208 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4209 (match_operand:SI 2 "const_int_operand" "")) 0))
4210 (const_int 0)))
4211 (clobber (match_scratch:SI 3 ""))]
4212 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4213 [(set (match_dup 3)
4214 (zero_extend:SI (subreg:HI
4215 (lshiftrt:SI (match_dup 1)
4216 (match_dup 2)) 0)))
4217 (set (match_dup 0)
4218 (compare:CC (match_dup 3)
4219 (const_int 0)))]
4220 "")
4221
4222 (define_insn ""
4223 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4224 (compare:CC
4225 (zero_extend:SI
4226 (subreg:HI
4227 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4228 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4229 (const_int 0)))
4230 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4231 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4232 "includes_rshift_p (operands[2], GEN_INT (65535))"
4233 "@
4234 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4235 #"
4236 [(set_attr "type" "delayed_compare")
4237 (set_attr "length" "4,8")])
4238
4239 (define_split
4240 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4241 (compare:CC
4242 (zero_extend:SI
4243 (subreg:HI
4244 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4245 (match_operand:SI 2 "const_int_operand" "")) 0))
4246 (const_int 0)))
4247 (set (match_operand:SI 0 "gpc_reg_operand" "")
4248 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4249 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4250 [(set (match_dup 0)
4251 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4252 (set (match_dup 3)
4253 (compare:CC (match_dup 0)
4254 (const_int 0)))]
4255 "")
4256
4257 (define_insn ""
4258 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4259 (const_int 1)
4260 (match_operand:SI 1 "gpc_reg_operand" "r"))
4261 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4262 (const_int 31)))]
4263 "TARGET_POWER"
4264 "rrib %0,%1,%2")
4265
4266 (define_insn ""
4267 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4268 (const_int 1)
4269 (match_operand:SI 1 "gpc_reg_operand" "r"))
4270 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4271 (const_int 31)))]
4272 "TARGET_POWER"
4273 "rrib %0,%1,%2")
4274
4275 (define_insn ""
4276 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4277 (const_int 1)
4278 (match_operand:SI 1 "gpc_reg_operand" "r"))
4279 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4280 (const_int 1)
4281 (const_int 0)))]
4282 "TARGET_POWER"
4283 "rrib %0,%1,%2")
4284
4285 (define_expand "ashrsi3"
4286 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4287 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4288 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4289 ""
4290 "
4291 {
4292 if (TARGET_POWER)
4293 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4294 else
4295 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4296 DONE;
4297 }")
4298
4299 (define_insn "ashrsi3_power"
4300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4301 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4302 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4303 (clobber (match_scratch:SI 3 "=q,X"))]
4304 "TARGET_POWER"
4305 "@
4306 srea %0,%1,%2
4307 {srai|srawi} %0,%1,%h2")
4308
4309 (define_insn "ashrsi3_no_power"
4310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4311 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4312 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4313 "! TARGET_POWER"
4314 "{sra|sraw}%I2 %0,%1,%h2")
4315
4316 (define_insn ""
4317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4318 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4319 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4320 (const_int 0)))
4321 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4322 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4323 "TARGET_POWER"
4324 "@
4325 srea. %3,%1,%2
4326 {srai.|srawi.} %3,%1,%h2
4327 #
4328 #"
4329 [(set_attr "type" "delayed_compare")
4330 (set_attr "length" "4,4,8,8")])
4331
4332 (define_split
4333 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4334 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4335 (match_operand:SI 2 "reg_or_cint_operand" ""))
4336 (const_int 0)))
4337 (clobber (match_scratch:SI 3 ""))
4338 (clobber (match_scratch:SI 4 ""))]
4339 "TARGET_POWER && reload_completed"
4340 [(parallel [(set (match_dup 3)
4341 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4342 (clobber (match_dup 4))])
4343 (set (match_dup 0)
4344 (compare:CC (match_dup 3)
4345 (const_int 0)))]
4346 "")
4347
4348 (define_insn ""
4349 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4350 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4351 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4352 (const_int 0)))
4353 (clobber (match_scratch:SI 3 "=r,r"))]
4354 "! TARGET_POWER"
4355 "@
4356 {sra|sraw}%I2. %3,%1,%h2
4357 #"
4358 [(set_attr "type" "delayed_compare")
4359 (set_attr "length" "4,8")])
4360
4361 (define_split
4362 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4363 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4364 (match_operand:SI 2 "reg_or_cint_operand" ""))
4365 (const_int 0)))
4366 (clobber (match_scratch:SI 3 ""))]
4367 "! TARGET_POWER && reload_completed"
4368 [(set (match_dup 3)
4369 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4370 (set (match_dup 0)
4371 (compare:CC (match_dup 3)
4372 (const_int 0)))]
4373 "")
4374
4375 (define_insn ""
4376 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4377 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4378 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4379 (const_int 0)))
4380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4381 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4382 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4383 "TARGET_POWER"
4384 "@
4385 srea. %0,%1,%2
4386 {srai.|srawi.} %0,%1,%h2
4387 #
4388 #"
4389 [(set_attr "type" "delayed_compare")
4390 (set_attr "length" "4,4,8,8")])
4391
4392 (define_split
4393 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4394 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4395 (match_operand:SI 2 "reg_or_cint_operand" ""))
4396 (const_int 0)))
4397 (set (match_operand:SI 0 "gpc_reg_operand" "")
4398 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4399 (clobber (match_scratch:SI 4 ""))]
4400 "TARGET_POWER && reload_completed"
4401 [(parallel [(set (match_dup 0)
4402 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4403 (clobber (match_dup 4))])
4404 (set (match_dup 3)
4405 (compare:CC (match_dup 0)
4406 (const_int 0)))]
4407 "")
4408
4409 (define_insn ""
4410 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4411 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4412 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4413 (const_int 0)))
4414 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4415 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4416 "! TARGET_POWER"
4417 "@
4418 {sra|sraw}%I2. %0,%1,%h2
4419 #"
4420 [(set_attr "type" "delayed_compare")
4421 (set_attr "length" "4,8")])
4422 \f
4423 (define_split
4424 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4425 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4426 (match_operand:SI 2 "reg_or_cint_operand" ""))
4427 (const_int 0)))
4428 (set (match_operand:SI 0 "gpc_reg_operand" "")
4429 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4430 "! TARGET_POWER && reload_completed"
4431 [(set (match_dup 0)
4432 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4433 (set (match_dup 3)
4434 (compare:CC (match_dup 0)
4435 (const_int 0)))]
4436 "")
4437
4438 ;; Floating-point insns, excluding normal data motion.
4439 ;;
4440 ;; PowerPC has a full set of single-precision floating point instructions.
4441 ;;
4442 ;; For the POWER architecture, we pretend that we have both SFmode and
4443 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4444 ;; The only conversions we will do will be when storing to memory. In that
4445 ;; case, we will use the "frsp" instruction before storing.
4446 ;;
4447 ;; Note that when we store into a single-precision memory location, we need to
4448 ;; use the frsp insn first. If the register being stored isn't dead, we
4449 ;; need a scratch register for the frsp. But this is difficult when the store
4450 ;; is done by reload. It is not incorrect to do the frsp on the register in
4451 ;; this case, we just lose precision that we would have otherwise gotten but
4452 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4453
4454 (define_insn_and_split "extendsfdf2"
4455 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
4456 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
4457 "TARGET_HARD_FLOAT && TARGET_FPRS"
4458 "@
4459 #
4460 fmr %0,%1"
4461 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
4462 [(const_int 0)]
4463 {
4464 emit_note (NOTE_INSN_DELETED);
4465 DONE;
4466 }
4467 [(set_attr "type" "fp")])
4468
4469 (define_insn "truncdfsf2"
4470 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4471 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4472 "TARGET_HARD_FLOAT && TARGET_FPRS"
4473 "frsp %0,%1"
4474 [(set_attr "type" "fp")])
4475
4476 (define_insn "aux_truncdfsf2"
4477 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4478 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4479 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4480 "frsp %0,%1"
4481 [(set_attr "type" "fp")])
4482
4483 (define_expand "negsf2"
4484 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4485 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4486 "TARGET_HARD_FLOAT"
4487 "")
4488
4489 (define_insn "*negsf2"
4490 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4491 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4492 "TARGET_HARD_FLOAT && TARGET_FPRS"
4493 "fneg %0,%1"
4494 [(set_attr "type" "fp")])
4495
4496 (define_expand "abssf2"
4497 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4498 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4499 "TARGET_HARD_FLOAT"
4500 "")
4501
4502 (define_insn "*abssf2"
4503 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4504 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4505 "TARGET_HARD_FLOAT && TARGET_FPRS"
4506 "fabs %0,%1"
4507 [(set_attr "type" "fp")])
4508
4509 (define_insn ""
4510 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4511 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4512 "TARGET_HARD_FLOAT && TARGET_FPRS"
4513 "fnabs %0,%1"
4514 [(set_attr "type" "fp")])
4515
4516 (define_expand "addsf3"
4517 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4518 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4519 (match_operand:SF 2 "gpc_reg_operand" "")))]
4520 "TARGET_HARD_FLOAT"
4521 "")
4522
4523 (define_insn ""
4524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4525 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4526 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4527 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4528 "fadds %0,%1,%2"
4529 [(set_attr "type" "fp")])
4530
4531 (define_insn ""
4532 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4533 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4534 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4535 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4536 "{fa|fadd} %0,%1,%2"
4537 [(set_attr "type" "fp")])
4538
4539 (define_expand "subsf3"
4540 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4541 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4542 (match_operand:SF 2 "gpc_reg_operand" "")))]
4543 "TARGET_HARD_FLOAT"
4544 "")
4545
4546 (define_insn ""
4547 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4548 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4549 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4550 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4551 "fsubs %0,%1,%2"
4552 [(set_attr "type" "fp")])
4553
4554 (define_insn ""
4555 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4556 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4557 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4558 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4559 "{fs|fsub} %0,%1,%2"
4560 [(set_attr "type" "fp")])
4561
4562 (define_expand "mulsf3"
4563 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4564 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4565 (match_operand:SF 2 "gpc_reg_operand" "")))]
4566 "TARGET_HARD_FLOAT"
4567 "")
4568
4569 (define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4573 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4574 "fmuls %0,%1,%2"
4575 [(set_attr "type" "fp")])
4576
4577 (define_insn ""
4578 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4579 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4580 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4581 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4582 "{fm|fmul} %0,%1,%2"
4583 [(set_attr "type" "dmul")])
4584
4585 (define_expand "divsf3"
4586 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4587 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4588 (match_operand:SF 2 "gpc_reg_operand" "")))]
4589 "TARGET_HARD_FLOAT"
4590 "")
4591
4592 (define_insn ""
4593 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4594 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4595 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4596 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4597 "fdivs %0,%1,%2"
4598 [(set_attr "type" "sdiv")])
4599
4600 (define_insn ""
4601 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4602 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4603 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4604 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4605 "{fd|fdiv} %0,%1,%2"
4606 [(set_attr "type" "ddiv")])
4607
4608 (define_insn ""
4609 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4610 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4611 (match_operand:SF 2 "gpc_reg_operand" "f"))
4612 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4613 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4614 "fmadds %0,%1,%2,%3"
4615 [(set_attr "type" "fp")])
4616
4617 (define_insn ""
4618 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4619 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4620 (match_operand:SF 2 "gpc_reg_operand" "f"))
4621 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4622 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4623 "{fma|fmadd} %0,%1,%2,%3"
4624 [(set_attr "type" "dmul")])
4625
4626 (define_insn ""
4627 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4628 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4629 (match_operand:SF 2 "gpc_reg_operand" "f"))
4630 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4631 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4632 "fmsubs %0,%1,%2,%3"
4633 [(set_attr "type" "fp")])
4634
4635 (define_insn ""
4636 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4637 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4638 (match_operand:SF 2 "gpc_reg_operand" "f"))
4639 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4640 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4641 "{fms|fmsub} %0,%1,%2,%3"
4642 [(set_attr "type" "dmul")])
4643
4644 (define_insn ""
4645 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4646 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4647 (match_operand:SF 2 "gpc_reg_operand" "f"))
4648 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4649 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4650 && HONOR_SIGNED_ZEROS (SFmode)"
4651 "fnmadds %0,%1,%2,%3"
4652 [(set_attr "type" "fp")])
4653
4654 (define_insn ""
4655 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4656 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4657 (match_operand:SF 2 "gpc_reg_operand" "f"))
4658 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4659 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4660 && ! HONOR_SIGNED_ZEROS (SFmode)"
4661 "fnmadds %0,%1,%2,%3"
4662 [(set_attr "type" "fp")])
4663
4664 (define_insn ""
4665 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4666 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4667 (match_operand:SF 2 "gpc_reg_operand" "f"))
4668 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4669 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4670 "{fnma|fnmadd} %0,%1,%2,%3"
4671 [(set_attr "type" "dmul")])
4672
4673 (define_insn ""
4674 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4675 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4676 (match_operand:SF 2 "gpc_reg_operand" "f"))
4677 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4678 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4679 && ! HONOR_SIGNED_ZEROS (SFmode)"
4680 "{fnma|fnmadd} %0,%1,%2,%3"
4681 [(set_attr "type" "dmul")])
4682
4683 (define_insn ""
4684 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4685 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4686 (match_operand:SF 2 "gpc_reg_operand" "f"))
4687 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4688 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4689 && HONOR_SIGNED_ZEROS (SFmode)"
4690 "fnmsubs %0,%1,%2,%3"
4691 [(set_attr "type" "fp")])
4692
4693 (define_insn ""
4694 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4695 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4696 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4697 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4698 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4699 && ! HONOR_SIGNED_ZEROS (SFmode)"
4700 "fnmsubs %0,%1,%2,%3"
4701 [(set_attr "type" "fp")])
4702
4703 (define_insn ""
4704 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4705 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4706 (match_operand:SF 2 "gpc_reg_operand" "f"))
4707 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4708 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4709 "{fnms|fnmsub} %0,%1,%2,%3"
4710 [(set_attr "type" "dmul")])
4711
4712 (define_insn ""
4713 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4714 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4715 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4716 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4717 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4718 && ! HONOR_SIGNED_ZEROS (SFmode)"
4719 "{fnms|fnmsub} %0,%1,%2,%3"
4720 [(set_attr "type" "fp")])
4721
4722 (define_expand "sqrtsf2"
4723 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4724 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4725 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4726 "")
4727
4728 (define_insn ""
4729 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4730 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4731 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4732 "fsqrts %0,%1"
4733 [(set_attr "type" "ssqrt")])
4734
4735 (define_insn ""
4736 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4737 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4738 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4739 "fsqrt %0,%1"
4740 [(set_attr "type" "dsqrt")])
4741
4742 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4743 ;; fsel instruction and some auxiliary computations. Then we just have a
4744 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4745 ;; combine.
4746 (define_expand "maxsf3"
4747 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4748 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4749 (match_operand:SF 2 "gpc_reg_operand" ""))
4750 (match_dup 1)
4751 (match_dup 2)))]
4752 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4753 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4754
4755 (define_expand "minsf3"
4756 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4757 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4758 (match_operand:SF 2 "gpc_reg_operand" ""))
4759 (match_dup 2)
4760 (match_dup 1)))]
4761 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4762 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4763
4764 (define_split
4765 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4766 (match_operator:SF 3 "min_max_operator"
4767 [(match_operand:SF 1 "gpc_reg_operand" "")
4768 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4769 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4770 [(const_int 0)]
4771 "
4772 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4773 operands[1], operands[2]);
4774 DONE;
4775 }")
4776
4777 (define_expand "movsicc"
4778 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4779 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4780 (match_operand:SI 2 "gpc_reg_operand" "")
4781 (match_operand:SI 3 "gpc_reg_operand" "")))]
4782 "TARGET_ISEL"
4783 "
4784 {
4785 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4786 DONE;
4787 else
4788 FAIL;
4789 }")
4790
4791 ;; We use the BASE_REGS for the isel input operands because, if rA is
4792 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4793 ;; because we may switch the operands and rB may end up being rA.
4794 ;;
4795 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4796 ;; leave out the mode in operand 4 and use one pattern, but reload can
4797 ;; change the mode underneath our feet and then gets confused trying
4798 ;; to reload the value.
4799 (define_insn "isel_signed"
4800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4801 (if_then_else:SI
4802 (match_operator 1 "comparison_operator"
4803 [(match_operand:CC 4 "cc_reg_operand" "y")
4804 (const_int 0)])
4805 (match_operand:SI 2 "gpc_reg_operand" "b")
4806 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4807 "TARGET_ISEL"
4808 "*
4809 { return output_isel (operands); }"
4810 [(set_attr "length" "4")])
4811
4812 (define_insn "isel_unsigned"
4813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4814 (if_then_else:SI
4815 (match_operator 1 "comparison_operator"
4816 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4817 (const_int 0)])
4818 (match_operand:SI 2 "gpc_reg_operand" "b")
4819 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4820 "TARGET_ISEL"
4821 "*
4822 { return output_isel (operands); }"
4823 [(set_attr "length" "4")])
4824
4825 (define_expand "movsfcc"
4826 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4827 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4828 (match_operand:SF 2 "gpc_reg_operand" "")
4829 (match_operand:SF 3 "gpc_reg_operand" "")))]
4830 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4831 "
4832 {
4833 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4834 DONE;
4835 else
4836 FAIL;
4837 }")
4838
4839 (define_insn "*fselsfsf4"
4840 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4841 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4842 (match_operand:SF 4 "zero_fp_constant" "F"))
4843 (match_operand:SF 2 "gpc_reg_operand" "f")
4844 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4845 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4846 "fsel %0,%1,%2,%3"
4847 [(set_attr "type" "fp")])
4848
4849 (define_insn "*fseldfsf4"
4850 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4851 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4852 (match_operand:DF 4 "zero_fp_constant" "F"))
4853 (match_operand:SF 2 "gpc_reg_operand" "f")
4854 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4855 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4856 "fsel %0,%1,%2,%3"
4857 [(set_attr "type" "fp")])
4858
4859 (define_insn "negdf2"
4860 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4861 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4862 "TARGET_HARD_FLOAT && TARGET_FPRS"
4863 "fneg %0,%1"
4864 [(set_attr "type" "fp")])
4865
4866 (define_insn "absdf2"
4867 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4868 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4869 "TARGET_HARD_FLOAT && TARGET_FPRS"
4870 "fabs %0,%1"
4871 [(set_attr "type" "fp")])
4872
4873 (define_insn ""
4874 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4875 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4876 "TARGET_HARD_FLOAT && TARGET_FPRS"
4877 "fnabs %0,%1"
4878 [(set_attr "type" "fp")])
4879
4880 (define_insn "adddf3"
4881 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4882 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4883 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4884 "TARGET_HARD_FLOAT && TARGET_FPRS"
4885 "{fa|fadd} %0,%1,%2"
4886 [(set_attr "type" "fp")])
4887
4888 (define_insn "subdf3"
4889 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4890 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4891 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4892 "TARGET_HARD_FLOAT && TARGET_FPRS"
4893 "{fs|fsub} %0,%1,%2"
4894 [(set_attr "type" "fp")])
4895
4896 (define_insn "muldf3"
4897 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4898 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4899 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4900 "TARGET_HARD_FLOAT && TARGET_FPRS"
4901 "{fm|fmul} %0,%1,%2"
4902 [(set_attr "type" "dmul")])
4903
4904 (define_insn "divdf3"
4905 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4906 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4907 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4908 "TARGET_HARD_FLOAT && TARGET_FPRS"
4909 "{fd|fdiv} %0,%1,%2"
4910 [(set_attr "type" "ddiv")])
4911
4912 (define_insn ""
4913 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4914 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4915 (match_operand:DF 2 "gpc_reg_operand" "f"))
4916 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4917 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4918 "{fma|fmadd} %0,%1,%2,%3"
4919 [(set_attr "type" "dmul")])
4920
4921 (define_insn ""
4922 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4923 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4924 (match_operand:DF 2 "gpc_reg_operand" "f"))
4925 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4926 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4927 "{fms|fmsub} %0,%1,%2,%3"
4928 [(set_attr "type" "dmul")])
4929
4930 (define_insn ""
4931 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4932 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4933 (match_operand:DF 2 "gpc_reg_operand" "f"))
4934 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4935 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4936 && HONOR_SIGNED_ZEROS (DFmode)"
4937 "{fnma|fnmadd} %0,%1,%2,%3"
4938 [(set_attr "type" "dmul")])
4939
4940 (define_insn ""
4941 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4942 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4943 (match_operand:DF 2 "gpc_reg_operand" "f"))
4944 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4945 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4946 && ! HONOR_SIGNED_ZEROS (DFmode)"
4947 "{fnma|fnmadd} %0,%1,%2,%3"
4948 [(set_attr "type" "dmul")])
4949
4950 (define_insn ""
4951 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4952 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4953 (match_operand:DF 2 "gpc_reg_operand" "f"))
4954 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4955 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4956 && HONOR_SIGNED_ZEROS (DFmode)"
4957 "{fnms|fnmsub} %0,%1,%2,%3"
4958 [(set_attr "type" "dmul")])
4959
4960 (define_insn ""
4961 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4962 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4963 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4964 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4965 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4966 && ! HONOR_SIGNED_ZEROS (DFmode)"
4967 "{fnms|fnmsub} %0,%1,%2,%3"
4968 [(set_attr "type" "dmul")])
4969
4970 (define_insn "sqrtdf2"
4971 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4972 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4973 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4974 "fsqrt %0,%1"
4975 [(set_attr "type" "dsqrt")])
4976
4977 ;; The conditional move instructions allow us to perform max and min
4978 ;; operations even when
4979
4980 (define_expand "maxdf3"
4981 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4982 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4983 (match_operand:DF 2 "gpc_reg_operand" ""))
4984 (match_dup 1)
4985 (match_dup 2)))]
4986 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4987 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4988
4989 (define_expand "mindf3"
4990 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4991 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4992 (match_operand:DF 2 "gpc_reg_operand" ""))
4993 (match_dup 2)
4994 (match_dup 1)))]
4995 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4996 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4997
4998 (define_split
4999 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5000 (match_operator:DF 3 "min_max_operator"
5001 [(match_operand:DF 1 "gpc_reg_operand" "")
5002 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5003 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5004 [(const_int 0)]
5005 "
5006 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5007 operands[1], operands[2]);
5008 DONE;
5009 }")
5010
5011 (define_expand "movdfcc"
5012 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5013 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5014 (match_operand:DF 2 "gpc_reg_operand" "")
5015 (match_operand:DF 3 "gpc_reg_operand" "")))]
5016 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5017 "
5018 {
5019 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5020 DONE;
5021 else
5022 FAIL;
5023 }")
5024
5025 (define_insn "*fseldfdf4"
5026 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5027 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5028 (match_operand:DF 4 "zero_fp_constant" "F"))
5029 (match_operand:DF 2 "gpc_reg_operand" "f")
5030 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5031 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5032 "fsel %0,%1,%2,%3"
5033 [(set_attr "type" "fp")])
5034
5035 (define_insn "*fselsfdf4"
5036 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5037 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5038 (match_operand:SF 4 "zero_fp_constant" "F"))
5039 (match_operand:DF 2 "gpc_reg_operand" "f")
5040 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5041 "TARGET_PPC_GFXOPT"
5042 "fsel %0,%1,%2,%3"
5043 [(set_attr "type" "fp")])
5044 \f
5045 ;; Conversions to and from floating-point.
5046
5047 (define_expand "fixuns_truncsfsi2"
5048 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5049 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5050 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5051 "")
5052
5053 (define_expand "fix_truncsfsi2"
5054 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5055 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5056 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5057 "")
5058
5059 ; For each of these conversions, there is a define_expand, a define_insn
5060 ; with a '#' template, and a define_split (with C code). The idea is
5061 ; to allow constant folding with the template of the define_insn,
5062 ; then to have the insns split later (between sched1 and final).
5063
5064 (define_expand "floatsidf2"
5065 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5066 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5067 (use (match_dup 2))
5068 (use (match_dup 3))
5069 (clobber (match_dup 4))
5070 (clobber (match_dup 5))
5071 (clobber (match_dup 6))])]
5072 "TARGET_HARD_FLOAT && TARGET_FPRS"
5073 "
5074 {
5075 if (TARGET_POWERPC64)
5076 {
5077 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5078 rtx t1 = gen_reg_rtx (DImode);
5079 rtx t2 = gen_reg_rtx (DImode);
5080 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5081 DONE;
5082 }
5083
5084 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5085 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5086 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5087 operands[5] = gen_reg_rtx (DFmode);
5088 operands[6] = gen_reg_rtx (SImode);
5089 }")
5090
5091 (define_insn "*floatsidf2_internal"
5092 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5093 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5094 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5095 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5096 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5097 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5098 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5099 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5100 "#"
5101 [(set_attr "length" "24")])
5102
5103 (define_split
5104 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5105 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5106 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5107 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5108 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5109 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5110 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5111 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5112 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5113 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5114 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5115 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5116 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5117 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5118 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5119 "
5120 {
5121 rtx lowword, highword;
5122 if (GET_CODE (operands[4]) != MEM)
5123 abort();
5124 highword = XEXP (operands[4], 0);
5125 lowword = plus_constant (highword, 4);
5126 if (! WORDS_BIG_ENDIAN)
5127 {
5128 rtx tmp;
5129 tmp = highword; highword = lowword; lowword = tmp;
5130 }
5131
5132 emit_insn (gen_xorsi3 (operands[6], operands[1],
5133 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5134 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5135 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5136 emit_move_insn (operands[5], operands[4]);
5137 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5138 DONE;
5139 }")
5140
5141 (define_expand "floatunssisf2"
5142 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5143 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5144 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5145 "")
5146
5147 (define_expand "floatunssidf2"
5148 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5149 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5150 (use (match_dup 2))
5151 (use (match_dup 3))
5152 (clobber (match_dup 4))
5153 (clobber (match_dup 5))])]
5154 "TARGET_HARD_FLOAT && TARGET_FPRS"
5155 "
5156 {
5157 if (TARGET_POWERPC64)
5158 {
5159 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5160 rtx t1 = gen_reg_rtx (DImode);
5161 rtx t2 = gen_reg_rtx (DImode);
5162 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5163 t1, t2));
5164 DONE;
5165 }
5166
5167 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5168 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5169 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5170 operands[5] = gen_reg_rtx (DFmode);
5171 }")
5172
5173 (define_insn "*floatunssidf2_internal"
5174 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5175 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5176 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5177 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5178 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5179 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5180 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5181 "#"
5182 [(set_attr "length" "20")])
5183
5184 (define_split
5185 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5186 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5187 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5188 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5189 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5190 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5191 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5192 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5193 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5194 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5195 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5196 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5197 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5198 "
5199 {
5200 rtx lowword, highword;
5201 if (GET_CODE (operands[4]) != MEM)
5202 abort();
5203 highword = XEXP (operands[4], 0);
5204 lowword = plus_constant (highword, 4);
5205 if (! WORDS_BIG_ENDIAN)
5206 {
5207 rtx tmp;
5208 tmp = highword; highword = lowword; lowword = tmp;
5209 }
5210
5211 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5212 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5213 emit_move_insn (operands[5], operands[4]);
5214 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5215 DONE;
5216 }")
5217
5218 (define_expand "fix_truncdfsi2"
5219 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5220 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5221 (clobber (match_dup 2))
5222 (clobber (match_dup 3))])]
5223 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5224 "
5225 {
5226 operands[2] = gen_reg_rtx (DImode);
5227 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5228 }")
5229
5230 (define_insn "*fix_truncdfsi2_internal"
5231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5232 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5233 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5234 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5235 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5236 "#"
5237 [(set_attr "length" "16")])
5238
5239 (define_split
5240 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5241 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5242 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5243 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5244 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5245 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5246 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5247 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5248 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5249 "
5250 {
5251 rtx lowword;
5252 if (GET_CODE (operands[3]) != MEM)
5253 abort();
5254 lowword = XEXP (operands[3], 0);
5255 if (WORDS_BIG_ENDIAN)
5256 lowword = plus_constant (lowword, 4);
5257
5258 emit_insn (gen_fctiwz (operands[2], operands[1]));
5259 emit_move_insn (operands[3], operands[2]);
5260 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5261 DONE;
5262 }")
5263
5264 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5265 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5266 ; because the first makes it clear that operand 0 is not live
5267 ; before the instruction.
5268 (define_insn "fctiwz"
5269 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5270 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5271 UNSPEC_FCTIWZ))]
5272 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5273 "{fcirz|fctiwz} %0,%1"
5274 [(set_attr "type" "fp")])
5275
5276 (define_expand "floatsisf2"
5277 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5278 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5279 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5280 "")
5281
5282 (define_insn "floatdidf2"
5283 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5284 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5285 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5286 "fcfid %0,%1"
5287 [(set_attr "type" "fp")])
5288
5289 (define_insn_and_split "floatsidf_ppc64"
5290 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5291 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5292 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5293 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5294 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5295 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5296 "#"
5297 "&& 1"
5298 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5299 (set (match_dup 2) (match_dup 3))
5300 (set (match_dup 4) (match_dup 2))
5301 (set (match_dup 0) (float:DF (match_dup 4)))]
5302 "")
5303
5304 (define_insn_and_split "floatunssidf_ppc64"
5305 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5306 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5307 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5308 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5309 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5310 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5311 "#"
5312 "&& 1"
5313 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5314 (set (match_dup 2) (match_dup 3))
5315 (set (match_dup 4) (match_dup 2))
5316 (set (match_dup 0) (float:DF (match_dup 4)))]
5317 "")
5318
5319 (define_insn "fix_truncdfdi2"
5320 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5321 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5322 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5323 "fctidz %0,%1"
5324 [(set_attr "type" "fp")])
5325
5326 (define_expand "floatdisf2"
5327 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5328 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5329 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5330 "
5331 {
5332 if (!flag_unsafe_math_optimizations)
5333 {
5334 rtx label = gen_label_rtx ();
5335 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5336 emit_label (label);
5337 }
5338 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5339 DONE;
5340 }")
5341
5342 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5343 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5344 ;; from double rounding.
5345 (define_insn_and_split "floatdisf2_internal1"
5346 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5347 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5348 (clobber (match_scratch:DF 2 "=f"))]
5349 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5350 "#"
5351 "&& reload_completed"
5352 [(set (match_dup 2)
5353 (float:DF (match_dup 1)))
5354 (set (match_dup 0)
5355 (float_truncate:SF (match_dup 2)))]
5356 "")
5357
5358 ;; Twiddles bits to avoid double rounding.
5359 ;; Bits that might be truncated when converting to DFmode are replaced
5360 ;; by a bit that won't be lost at that stage, but is below the SFmode
5361 ;; rounding position.
5362 (define_expand "floatdisf2_internal2"
5363 [(parallel [(set (match_dup 4)
5364 (compare:CC (and:DI (match_operand:DI 0 "" "")
5365 (const_int 2047))
5366 (const_int 0)))
5367 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5368 (clobber (match_scratch:CC 7 ""))])
5369 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5370 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5371 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5372 (label_ref (match_operand:DI 1 "" ""))
5373 (pc)))
5374 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5375 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5376 (label_ref (match_dup 1))
5377 (pc)))
5378 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5379 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5380 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5381 "
5382 {
5383 operands[2] = gen_reg_rtx (DImode);
5384 operands[3] = gen_reg_rtx (DImode);
5385 operands[4] = gen_reg_rtx (CCmode);
5386 operands[5] = gen_reg_rtx (CCUNSmode);
5387 }")
5388 \f
5389 ;; Define the DImode operations that can be done in a small number
5390 ;; of instructions. The & constraints are to prevent the register
5391 ;; allocator from allocating registers that overlap with the inputs
5392 ;; (for example, having an input in 7,8 and an output in 6,7). We
5393 ;; also allow for the output being the same as one of the inputs.
5394
5395 (define_insn "*adddi3_noppc64"
5396 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5397 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5398 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5399 "! TARGET_POWERPC64"
5400 "*
5401 {
5402 if (WORDS_BIG_ENDIAN)
5403 return (GET_CODE (operands[2])) != CONST_INT
5404 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5405 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5406 else
5407 return (GET_CODE (operands[2])) != CONST_INT
5408 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5409 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5410 }"
5411 [(set_attr "length" "8")])
5412
5413 (define_insn "*subdi3_noppc64"
5414 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5415 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5416 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5417 "! TARGET_POWERPC64"
5418 "*
5419 {
5420 if (WORDS_BIG_ENDIAN)
5421 return (GET_CODE (operands[1]) != CONST_INT)
5422 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5423 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5424 else
5425 return (GET_CODE (operands[1]) != CONST_INT)
5426 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5427 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5428 }"
5429 [(set_attr "length" "8")])
5430
5431 (define_insn "*negdi2_noppc64"
5432 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5433 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5434 "! TARGET_POWERPC64"
5435 "*
5436 {
5437 return (WORDS_BIG_ENDIAN)
5438 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5439 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5440 }"
5441 [(set_attr "length" "8")])
5442
5443 (define_expand "mulsidi3"
5444 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5445 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5446 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5447 "! TARGET_POWERPC64"
5448 "
5449 {
5450 if (! TARGET_POWER && ! TARGET_POWERPC)
5451 {
5452 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5453 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5454 emit_insn (gen_mull_call ());
5455 if (WORDS_BIG_ENDIAN)
5456 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5457 else
5458 {
5459 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5460 gen_rtx_REG (SImode, 3));
5461 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5462 gen_rtx_REG (SImode, 4));
5463 }
5464 DONE;
5465 }
5466 else if (TARGET_POWER)
5467 {
5468 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5469 DONE;
5470 }
5471 }")
5472
5473 (define_insn "mulsidi3_mq"
5474 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5475 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5476 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5477 (clobber (match_scratch:SI 3 "=q"))]
5478 "TARGET_POWER"
5479 "mul %0,%1,%2\;mfmq %L0"
5480 [(set_attr "type" "imul")
5481 (set_attr "length" "8")])
5482
5483 (define_insn "*mulsidi3_no_mq"
5484 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5485 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5486 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5487 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5488 "*
5489 {
5490 return (WORDS_BIG_ENDIAN)
5491 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5492 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5493 }"
5494 [(set_attr "type" "imul")
5495 (set_attr "length" "8")])
5496
5497 (define_split
5498 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5499 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5500 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5501 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5502 [(set (match_dup 3)
5503 (truncate:SI
5504 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5505 (sign_extend:DI (match_dup 2)))
5506 (const_int 32))))
5507 (set (match_dup 4)
5508 (mult:SI (match_dup 1)
5509 (match_dup 2)))]
5510 "
5511 {
5512 int endian = (WORDS_BIG_ENDIAN == 0);
5513 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5514 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5515 }")
5516
5517 (define_expand "umulsidi3"
5518 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5519 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5520 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5521 "TARGET_POWERPC && ! TARGET_POWERPC64"
5522 "
5523 {
5524 if (TARGET_POWER)
5525 {
5526 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5527 DONE;
5528 }
5529 }")
5530
5531 (define_insn "umulsidi3_mq"
5532 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5533 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5534 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5535 (clobber (match_scratch:SI 3 "=q"))]
5536 "TARGET_POWERPC && TARGET_POWER"
5537 "*
5538 {
5539 return (WORDS_BIG_ENDIAN)
5540 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5541 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5542 }"
5543 [(set_attr "type" "imul")
5544 (set_attr "length" "8")])
5545
5546 (define_insn "*umulsidi3_no_mq"
5547 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5548 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5549 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5550 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5551 "*
5552 {
5553 return (WORDS_BIG_ENDIAN)
5554 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5555 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5556 }"
5557 [(set_attr "type" "imul")
5558 (set_attr "length" "8")])
5559
5560 (define_split
5561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5562 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5563 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5564 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5565 [(set (match_dup 3)
5566 (truncate:SI
5567 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5568 (zero_extend:DI (match_dup 2)))
5569 (const_int 32))))
5570 (set (match_dup 4)
5571 (mult:SI (match_dup 1)
5572 (match_dup 2)))]
5573 "
5574 {
5575 int endian = (WORDS_BIG_ENDIAN == 0);
5576 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5577 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5578 }")
5579
5580 (define_expand "smulsi3_highpart"
5581 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5582 (truncate:SI
5583 (lshiftrt:DI (mult:DI (sign_extend:DI
5584 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5585 (sign_extend:DI
5586 (match_operand:SI 2 "gpc_reg_operand" "r")))
5587 (const_int 32))))]
5588 ""
5589 "
5590 {
5591 if (! TARGET_POWER && ! TARGET_POWERPC)
5592 {
5593 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5594 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5595 emit_insn (gen_mulh_call ());
5596 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5597 DONE;
5598 }
5599 else if (TARGET_POWER)
5600 {
5601 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5602 DONE;
5603 }
5604 }")
5605
5606 (define_insn "smulsi3_highpart_mq"
5607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5608 (truncate:SI
5609 (lshiftrt:DI (mult:DI (sign_extend:DI
5610 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5611 (sign_extend:DI
5612 (match_operand:SI 2 "gpc_reg_operand" "r")))
5613 (const_int 32))))
5614 (clobber (match_scratch:SI 3 "=q"))]
5615 "TARGET_POWER"
5616 "mul %0,%1,%2"
5617 [(set_attr "type" "imul")])
5618
5619 (define_insn "*smulsi3_highpart_no_mq"
5620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5621 (truncate:SI
5622 (lshiftrt:DI (mult:DI (sign_extend:DI
5623 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5624 (sign_extend:DI
5625 (match_operand:SI 2 "gpc_reg_operand" "r")))
5626 (const_int 32))))]
5627 "TARGET_POWERPC && ! TARGET_POWER"
5628 "mulhw %0,%1,%2"
5629 [(set_attr "type" "imul")])
5630
5631 (define_expand "umulsi3_highpart"
5632 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5633 (truncate:SI
5634 (lshiftrt:DI (mult:DI (zero_extend:DI
5635 (match_operand:SI 1 "gpc_reg_operand" ""))
5636 (zero_extend:DI
5637 (match_operand:SI 2 "gpc_reg_operand" "")))
5638 (const_int 32))))]
5639 "TARGET_POWERPC"
5640 "
5641 {
5642 if (TARGET_POWER)
5643 {
5644 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5645 DONE;
5646 }
5647 }")
5648
5649 (define_insn "umulsi3_highpart_mq"
5650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5651 (truncate:SI
5652 (lshiftrt:DI (mult:DI (zero_extend:DI
5653 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5654 (zero_extend:DI
5655 (match_operand:SI 2 "gpc_reg_operand" "r")))
5656 (const_int 32))))
5657 (clobber (match_scratch:SI 3 "=q"))]
5658 "TARGET_POWERPC && TARGET_POWER"
5659 "mulhwu %0,%1,%2"
5660 [(set_attr "type" "imul")])
5661
5662 (define_insn "*umulsi3_highpart_no_mq"
5663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5664 (truncate:SI
5665 (lshiftrt:DI (mult:DI (zero_extend:DI
5666 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5667 (zero_extend:DI
5668 (match_operand:SI 2 "gpc_reg_operand" "r")))
5669 (const_int 32))))]
5670 "TARGET_POWERPC && ! TARGET_POWER"
5671 "mulhwu %0,%1,%2"
5672 [(set_attr "type" "imul")])
5673
5674 ;; If operands 0 and 2 are in the same register, we have a problem. But
5675 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5676 ;; why we have the strange constraints below.
5677 (define_insn "ashldi3_power"
5678 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5679 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5680 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5681 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5682 "TARGET_POWER"
5683 "@
5684 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5685 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5686 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5687 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5688 [(set_attr "length" "8")])
5689
5690 (define_insn "lshrdi3_power"
5691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5692 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5693 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5694 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5695 "TARGET_POWER"
5696 "@
5697 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5698 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5699 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5700 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5701 [(set_attr "length" "8")])
5702
5703 ;; Shift by a variable amount is too complex to be worth open-coding. We
5704 ;; just handle shifts by constants.
5705 (define_insn "ashrdi3_power"
5706 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5707 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5708 (match_operand:SI 2 "const_int_operand" "M,i")))
5709 (clobber (match_scratch:SI 3 "=X,q"))]
5710 "TARGET_POWER"
5711 "@
5712 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5713 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5714 [(set_attr "length" "8")])
5715
5716 (define_insn "ashrdi3_no_power"
5717 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5718 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5719 (match_operand:SI 2 "const_int_operand" "M,i")))]
5720 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5721 "@
5722 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5723 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5724 [(set_attr "length" "8,12")])
5725
5726 (define_insn "*ashrdisi3_noppc64"
5727 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5728 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5729 (const_int 32)) 4))]
5730 "TARGET_32BIT && !TARGET_POWERPC64"
5731 "*
5732 {
5733 if (REGNO (operands[0]) == REGNO (operands[1]))
5734 return \"\";
5735 else
5736 return \"mr %0,%1\";
5737 }"
5738 [(set_attr "length" "4")])
5739
5740 \f
5741 ;; PowerPC64 DImode operations.
5742
5743 (define_expand "adddi3"
5744 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5745 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5746 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5747 ""
5748 "
5749 {
5750 if (! TARGET_POWERPC64)
5751 {
5752 if (non_short_cint_operand (operands[2], DImode))
5753 FAIL;
5754 }
5755 else
5756 if (GET_CODE (operands[2]) == CONST_INT
5757 && ! add_operand (operands[2], DImode))
5758 {
5759 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5760 ? operands[0] : gen_reg_rtx (DImode));
5761
5762 HOST_WIDE_INT val = INTVAL (operands[2]);
5763 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5764 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5765
5766 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5767 FAIL;
5768
5769 /* The ordering here is important for the prolog expander.
5770 When space is allocated from the stack, adding 'low' first may
5771 produce a temporary deallocation (which would be bad). */
5772 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5773 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5774 DONE;
5775 }
5776 }")
5777
5778 ;; Discourage ai/addic because of carry but provide it in an alternative
5779 ;; allowing register zero as source.
5780
5781 (define_insn "*adddi3_internal1"
5782 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5783 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5784 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5785 "TARGET_POWERPC64"
5786 "@
5787 add %0,%1,%2
5788 addi %0,%1,%2
5789 addic %0,%1,%2
5790 addis %0,%1,%v2")
5791
5792 (define_insn "*adddi3_internal2"
5793 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5794 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5795 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5796 (const_int 0)))
5797 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5798 "TARGET_64BIT"
5799 "@
5800 add. %3,%1,%2
5801 addic. %3,%1,%2
5802 #
5803 #"
5804 [(set_attr "type" "fast_compare,compare,compare,compare")
5805 (set_attr "length" "4,4,8,8")])
5806
5807 (define_split
5808 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5809 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5810 (match_operand:DI 2 "reg_or_short_operand" ""))
5811 (const_int 0)))
5812 (clobber (match_scratch:DI 3 ""))]
5813 "TARGET_POWERPC64 && reload_completed"
5814 [(set (match_dup 3)
5815 (plus:DI (match_dup 1) (match_dup 2)))
5816 (set (match_dup 0)
5817 (compare:CC (match_dup 3)
5818 (const_int 0)))]
5819 "")
5820
5821 (define_insn "*adddi3_internal3"
5822 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5823 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5824 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5825 (const_int 0)))
5826 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5827 (plus:DI (match_dup 1) (match_dup 2)))]
5828 "TARGET_64BIT"
5829 "@
5830 add. %0,%1,%2
5831 addic. %0,%1,%2
5832 #
5833 #"
5834 [(set_attr "type" "fast_compare,compare,compare,compare")
5835 (set_attr "length" "4,4,8,8")])
5836
5837 (define_split
5838 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5839 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5840 (match_operand:DI 2 "reg_or_short_operand" ""))
5841 (const_int 0)))
5842 (set (match_operand:DI 0 "gpc_reg_operand" "")
5843 (plus:DI (match_dup 1) (match_dup 2)))]
5844 "TARGET_POWERPC64 && reload_completed"
5845 [(set (match_dup 0)
5846 (plus:DI (match_dup 1) (match_dup 2)))
5847 (set (match_dup 3)
5848 (compare:CC (match_dup 0)
5849 (const_int 0)))]
5850 "")
5851
5852 ;; Split an add that we can't do in one insn into two insns, each of which
5853 ;; does one 16-bit part. This is used by combine. Note that the low-order
5854 ;; add should be last in case the result gets used in an address.
5855
5856 (define_split
5857 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5858 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5859 (match_operand:DI 2 "non_add_cint_operand" "")))]
5860 "TARGET_POWERPC64"
5861 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5862 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5863 "
5864 {
5865 HOST_WIDE_INT val = INTVAL (operands[2]);
5866 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5867 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5868
5869 operands[4] = GEN_INT (low);
5870 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5871 operands[3] = GEN_INT (rest);
5872 else if (! no_new_pseudos)
5873 {
5874 operands[3] = gen_reg_rtx (DImode);
5875 emit_move_insn (operands[3], operands[2]);
5876 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5877 DONE;
5878 }
5879 else
5880 FAIL;
5881 }")
5882
5883 (define_insn "one_cmpldi2"
5884 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5885 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5886 "TARGET_POWERPC64"
5887 "nor %0,%1,%1")
5888
5889 (define_insn ""
5890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5891 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5892 (const_int 0)))
5893 (clobber (match_scratch:DI 2 "=r,r"))]
5894 "TARGET_64BIT"
5895 "@
5896 nor. %2,%1,%1
5897 #"
5898 [(set_attr "type" "compare")
5899 (set_attr "length" "4,8")])
5900
5901 (define_split
5902 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5903 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5904 (const_int 0)))
5905 (clobber (match_scratch:DI 2 ""))]
5906 "TARGET_POWERPC64 && reload_completed"
5907 [(set (match_dup 2)
5908 (not:DI (match_dup 1)))
5909 (set (match_dup 0)
5910 (compare:CC (match_dup 2)
5911 (const_int 0)))]
5912 "")
5913
5914 (define_insn ""
5915 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5916 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5917 (const_int 0)))
5918 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5919 (not:DI (match_dup 1)))]
5920 "TARGET_64BIT"
5921 "@
5922 nor. %0,%1,%1
5923 #"
5924 [(set_attr "type" "compare")
5925 (set_attr "length" "4,8")])
5926
5927 (define_split
5928 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5929 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5930 (const_int 0)))
5931 (set (match_operand:DI 0 "gpc_reg_operand" "")
5932 (not:DI (match_dup 1)))]
5933 "TARGET_POWERPC64 && reload_completed"
5934 [(set (match_dup 0)
5935 (not:DI (match_dup 1)))
5936 (set (match_dup 2)
5937 (compare:CC (match_dup 0)
5938 (const_int 0)))]
5939 "")
5940
5941 (define_insn ""
5942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5943 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5944 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5945 "TARGET_POWERPC64"
5946 "@
5947 subf %0,%2,%1
5948 subfic %0,%2,%1")
5949
5950 (define_insn ""
5951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5952 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5953 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5954 (const_int 0)))
5955 (clobber (match_scratch:DI 3 "=r,r"))]
5956 "TARGET_64BIT"
5957 "@
5958 subf. %3,%2,%1
5959 #"
5960 [(set_attr "type" "fast_compare")
5961 (set_attr "length" "4,8")])
5962
5963 (define_split
5964 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5965 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5966 (match_operand:DI 2 "gpc_reg_operand" ""))
5967 (const_int 0)))
5968 (clobber (match_scratch:DI 3 ""))]
5969 "TARGET_POWERPC64 && reload_completed"
5970 [(set (match_dup 3)
5971 (minus:DI (match_dup 1) (match_dup 2)))
5972 (set (match_dup 0)
5973 (compare:CC (match_dup 3)
5974 (const_int 0)))]
5975 "")
5976
5977 (define_insn ""
5978 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5979 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5980 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5981 (const_int 0)))
5982 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5983 (minus:DI (match_dup 1) (match_dup 2)))]
5984 "TARGET_64BIT"
5985 "@
5986 subf. %0,%2,%1
5987 #"
5988 [(set_attr "type" "fast_compare")
5989 (set_attr "length" "4,8")])
5990
5991 (define_split
5992 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5993 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5994 (match_operand:DI 2 "gpc_reg_operand" ""))
5995 (const_int 0)))
5996 (set (match_operand:DI 0 "gpc_reg_operand" "")
5997 (minus:DI (match_dup 1) (match_dup 2)))]
5998 "TARGET_POWERPC64 && reload_completed"
5999 [(set (match_dup 0)
6000 (minus:DI (match_dup 1) (match_dup 2)))
6001 (set (match_dup 3)
6002 (compare:CC (match_dup 0)
6003 (const_int 0)))]
6004 "")
6005
6006 (define_expand "subdi3"
6007 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6008 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6009 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6010 ""
6011 "
6012 {
6013 if (GET_CODE (operands[2]) == CONST_INT)
6014 {
6015 emit_insn (gen_adddi3 (operands[0], operands[1],
6016 negate_rtx (DImode, operands[2])));
6017 DONE;
6018 }
6019 }")
6020
6021 (define_insn_and_split "absdi2"
6022 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6023 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6024 (clobber (match_scratch:DI 2 "=&r,&r"))]
6025 "TARGET_POWERPC64"
6026 "#"
6027 "&& reload_completed"
6028 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6029 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6030 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6031 "")
6032
6033 (define_insn_and_split "*nabsdi2"
6034 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6035 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6036 (clobber (match_scratch:DI 2 "=&r,&r"))]
6037 "TARGET_POWERPC64"
6038 "#"
6039 "&& reload_completed"
6040 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6041 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6042 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6043 "")
6044
6045 (define_expand "negdi2"
6046 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6047 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6048 ""
6049 "")
6050
6051 (define_insn ""
6052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6053 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6054 "TARGET_POWERPC64"
6055 "neg %0,%1")
6056
6057 (define_insn ""
6058 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6059 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6060 (const_int 0)))
6061 (clobber (match_scratch:DI 2 "=r,r"))]
6062 "TARGET_64BIT"
6063 "@
6064 neg. %2,%1
6065 #"
6066 [(set_attr "type" "fast_compare")
6067 (set_attr "length" "4,8")])
6068
6069 (define_split
6070 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6071 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6072 (const_int 0)))
6073 (clobber (match_scratch:DI 2 ""))]
6074 "TARGET_POWERPC64 && reload_completed"
6075 [(set (match_dup 2)
6076 (neg:DI (match_dup 1)))
6077 (set (match_dup 0)
6078 (compare:CC (match_dup 2)
6079 (const_int 0)))]
6080 "")
6081
6082 (define_insn ""
6083 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6084 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6085 (const_int 0)))
6086 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6087 (neg:DI (match_dup 1)))]
6088 "TARGET_64BIT"
6089 "@
6090 neg. %0,%1
6091 #"
6092 [(set_attr "type" "fast_compare")
6093 (set_attr "length" "4,8")])
6094
6095 (define_split
6096 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6097 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6098 (const_int 0)))
6099 (set (match_operand:DI 0 "gpc_reg_operand" "")
6100 (neg:DI (match_dup 1)))]
6101 "TARGET_POWERPC64 && reload_completed"
6102 [(set (match_dup 0)
6103 (neg:DI (match_dup 1)))
6104 (set (match_dup 2)
6105 (compare:CC (match_dup 0)
6106 (const_int 0)))]
6107 "")
6108
6109 (define_insn "clzdi2"
6110 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6111 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6112 "TARGET_POWERPC64"
6113 "cntlzd %0,%1")
6114
6115 (define_expand "ctzdi2"
6116 [(set (match_dup 2)
6117 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6118 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6119 (match_dup 2)))
6120 (clobber (scratch:CC))])
6121 (set (match_dup 4) (clz:DI (match_dup 3)))
6122 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6123 (minus:DI (const_int 63) (match_dup 4)))]
6124 "TARGET_POWERPC64"
6125 {
6126 operands[2] = gen_reg_rtx (DImode);
6127 operands[3] = gen_reg_rtx (DImode);
6128 operands[4] = gen_reg_rtx (DImode);
6129 })
6130
6131 (define_expand "ffsdi2"
6132 [(set (match_dup 2)
6133 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6134 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6135 (match_dup 2)))
6136 (clobber (scratch:CC))])
6137 (set (match_dup 4) (clz:DI (match_dup 3)))
6138 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6139 (minus:DI (const_int 64) (match_dup 4)))]
6140 "TARGET_POWERPC64"
6141 {
6142 operands[2] = gen_reg_rtx (DImode);
6143 operands[3] = gen_reg_rtx (DImode);
6144 operands[4] = gen_reg_rtx (DImode);
6145 })
6146
6147 (define_insn "muldi3"
6148 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6149 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6150 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6151 "TARGET_POWERPC64"
6152 "mulld %0,%1,%2"
6153 [(set_attr "type" "lmul")])
6154
6155 (define_insn "*muldi3_internal1"
6156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6157 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6158 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6159 (const_int 0)))
6160 (clobber (match_scratch:DI 3 "=r,r"))]
6161 "TARGET_POWERPC64"
6162 "@
6163 mulld. %3,%1,%2
6164 #"
6165 [(set_attr "type" "lmul_compare")
6166 (set_attr "length" "4,8")])
6167
6168 (define_split
6169 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6170 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6171 (match_operand:DI 2 "gpc_reg_operand" ""))
6172 (const_int 0)))
6173 (clobber (match_scratch:DI 3 ""))]
6174 "TARGET_POWERPC64 && reload_completed"
6175 [(set (match_dup 3)
6176 (mult:DI (match_dup 1) (match_dup 2)))
6177 (set (match_dup 0)
6178 (compare:CC (match_dup 3)
6179 (const_int 0)))]
6180 "")
6181
6182 (define_insn "*muldi3_internal2"
6183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6184 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6185 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6186 (const_int 0)))
6187 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6188 (mult:DI (match_dup 1) (match_dup 2)))]
6189 "TARGET_POWERPC64"
6190 "@
6191 mulld. %0,%1,%2
6192 #"
6193 [(set_attr "type" "lmul_compare")
6194 (set_attr "length" "4,8")])
6195
6196 (define_split
6197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6198 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6199 (match_operand:DI 2 "gpc_reg_operand" ""))
6200 (const_int 0)))
6201 (set (match_operand:DI 0 "gpc_reg_operand" "")
6202 (mult:DI (match_dup 1) (match_dup 2)))]
6203 "TARGET_POWERPC64 && reload_completed"
6204 [(set (match_dup 0)
6205 (mult:DI (match_dup 1) (match_dup 2)))
6206 (set (match_dup 3)
6207 (compare:CC (match_dup 0)
6208 (const_int 0)))]
6209 "")
6210
6211 (define_insn "smuldi3_highpart"
6212 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6213 (truncate:DI
6214 (lshiftrt:TI (mult:TI (sign_extend:TI
6215 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6216 (sign_extend:TI
6217 (match_operand:DI 2 "gpc_reg_operand" "r")))
6218 (const_int 64))))]
6219 "TARGET_POWERPC64"
6220 "mulhd %0,%1,%2"
6221 [(set_attr "type" "lmul")])
6222
6223 (define_insn "umuldi3_highpart"
6224 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6225 (truncate:DI
6226 (lshiftrt:TI (mult:TI (zero_extend:TI
6227 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6228 (zero_extend:TI
6229 (match_operand:DI 2 "gpc_reg_operand" "r")))
6230 (const_int 64))))]
6231 "TARGET_POWERPC64"
6232 "mulhdu %0,%1,%2"
6233 [(set_attr "type" "lmul")])
6234
6235 (define_expand "divdi3"
6236 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6237 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6238 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6239 "TARGET_POWERPC64"
6240 "
6241 {
6242 if (GET_CODE (operands[2]) == CONST_INT
6243 && INTVAL (operands[2]) > 0
6244 && exact_log2 (INTVAL (operands[2])) >= 0)
6245 ;
6246 else
6247 operands[2] = force_reg (DImode, operands[2]);
6248 }")
6249
6250 (define_expand "moddi3"
6251 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6252 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6253 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6254 "TARGET_POWERPC64"
6255 "
6256 {
6257 int i;
6258 rtx temp1;
6259 rtx temp2;
6260
6261 if (GET_CODE (operands[2]) != CONST_INT
6262 || INTVAL (operands[2]) <= 0
6263 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6264 FAIL;
6265
6266 temp1 = gen_reg_rtx (DImode);
6267 temp2 = gen_reg_rtx (DImode);
6268
6269 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6270 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6271 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6272 DONE;
6273 }")
6274
6275 (define_insn ""
6276 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6277 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6278 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6279 "TARGET_POWERPC64"
6280 "sradi %0,%1,%p2\;addze %0,%0"
6281 [(set_attr "length" "8")])
6282
6283 (define_insn ""
6284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6285 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6286 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6287 (const_int 0)))
6288 (clobber (match_scratch:DI 3 "=r,r"))]
6289 "TARGET_64BIT"
6290 "@
6291 sradi %3,%1,%p2\;addze. %3,%3
6292 #"
6293 [(set_attr "type" "compare")
6294 (set_attr "length" "8,12")])
6295
6296 (define_split
6297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6298 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6299 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6300 (const_int 0)))
6301 (clobber (match_scratch:DI 3 ""))]
6302 "TARGET_POWERPC64 && reload_completed"
6303 [(set (match_dup 3)
6304 (div:DI (match_dup 1) (match_dup 2)))
6305 (set (match_dup 0)
6306 (compare:CC (match_dup 3)
6307 (const_int 0)))]
6308 "")
6309
6310 (define_insn ""
6311 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6312 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6313 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6314 (const_int 0)))
6315 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6316 (div:DI (match_dup 1) (match_dup 2)))]
6317 "TARGET_64BIT"
6318 "@
6319 sradi %0,%1,%p2\;addze. %0,%0
6320 #"
6321 [(set_attr "type" "compare")
6322 (set_attr "length" "8,12")])
6323
6324 (define_split
6325 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6326 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6327 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6328 (const_int 0)))
6329 (set (match_operand:DI 0 "gpc_reg_operand" "")
6330 (div:DI (match_dup 1) (match_dup 2)))]
6331 "TARGET_POWERPC64 && reload_completed"
6332 [(set (match_dup 0)
6333 (div:DI (match_dup 1) (match_dup 2)))
6334 (set (match_dup 3)
6335 (compare:CC (match_dup 0)
6336 (const_int 0)))]
6337 "")
6338
6339 (define_insn ""
6340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6341 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6342 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6343 "TARGET_POWERPC64"
6344 "divd %0,%1,%2"
6345 [(set_attr "type" "ldiv")])
6346
6347 (define_insn "udivdi3"
6348 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6349 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6350 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6351 "TARGET_POWERPC64"
6352 "divdu %0,%1,%2"
6353 [(set_attr "type" "ldiv")])
6354
6355 (define_insn "rotldi3"
6356 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6357 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6358 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6359 "TARGET_POWERPC64"
6360 "rld%I2cl %0,%1,%H2,0")
6361
6362 (define_insn "*rotldi3_internal2"
6363 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6364 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6365 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6366 (const_int 0)))
6367 (clobber (match_scratch:DI 3 "=r,r"))]
6368 "TARGET_64BIT"
6369 "@
6370 rld%I2cl. %3,%1,%H2,0
6371 #"
6372 [(set_attr "type" "delayed_compare")
6373 (set_attr "length" "4,8")])
6374
6375 (define_split
6376 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6377 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6378 (match_operand:DI 2 "reg_or_cint_operand" ""))
6379 (const_int 0)))
6380 (clobber (match_scratch:DI 3 ""))]
6381 "TARGET_POWERPC64 && reload_completed"
6382 [(set (match_dup 3)
6383 (rotate:DI (match_dup 1) (match_dup 2)))
6384 (set (match_dup 0)
6385 (compare:CC (match_dup 3)
6386 (const_int 0)))]
6387 "")
6388
6389 (define_insn "*rotldi3_internal3"
6390 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6391 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6392 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6393 (const_int 0)))
6394 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6395 (rotate:DI (match_dup 1) (match_dup 2)))]
6396 "TARGET_64BIT"
6397 "@
6398 rld%I2cl. %0,%1,%H2,0
6399 #"
6400 [(set_attr "type" "delayed_compare")
6401 (set_attr "length" "4,8")])
6402
6403 (define_split
6404 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6405 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6406 (match_operand:DI 2 "reg_or_cint_operand" ""))
6407 (const_int 0)))
6408 (set (match_operand:DI 0 "gpc_reg_operand" "")
6409 (rotate:DI (match_dup 1) (match_dup 2)))]
6410 "TARGET_POWERPC64 && reload_completed"
6411 [(set (match_dup 0)
6412 (rotate:DI (match_dup 1) (match_dup 2)))
6413 (set (match_dup 3)
6414 (compare:CC (match_dup 0)
6415 (const_int 0)))]
6416 "")
6417
6418 (define_insn "*rotldi3_internal4"
6419 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6420 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6421 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6422 (match_operand:DI 3 "mask64_operand" "n")))]
6423 "TARGET_POWERPC64"
6424 "rld%I2c%B3 %0,%1,%H2,%S3")
6425
6426 (define_insn "*rotldi3_internal5"
6427 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6428 (compare:CC (and:DI
6429 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6430 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6431 (match_operand:DI 3 "mask64_operand" "n,n"))
6432 (const_int 0)))
6433 (clobber (match_scratch:DI 4 "=r,r"))]
6434 "TARGET_64BIT"
6435 "@
6436 rld%I2c%B3. %4,%1,%H2,%S3
6437 #"
6438 [(set_attr "type" "delayed_compare")
6439 (set_attr "length" "4,8")])
6440
6441 (define_split
6442 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6443 (compare:CC (and:DI
6444 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6445 (match_operand:DI 2 "reg_or_cint_operand" ""))
6446 (match_operand:DI 3 "mask64_operand" ""))
6447 (const_int 0)))
6448 (clobber (match_scratch:DI 4 ""))]
6449 "TARGET_POWERPC64 && reload_completed"
6450 [(set (match_dup 4)
6451 (and:DI (rotate:DI (match_dup 1)
6452 (match_dup 2))
6453 (match_dup 3)))
6454 (set (match_dup 0)
6455 (compare:CC (match_dup 4)
6456 (const_int 0)))]
6457 "")
6458
6459 (define_insn "*rotldi3_internal6"
6460 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6461 (compare:CC (and:DI
6462 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6463 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6464 (match_operand:DI 3 "mask64_operand" "n,n"))
6465 (const_int 0)))
6466 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6467 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6468 "TARGET_64BIT"
6469 "@
6470 rld%I2c%B3. %0,%1,%H2,%S3
6471 #"
6472 [(set_attr "type" "delayed_compare")
6473 (set_attr "length" "4,8")])
6474
6475 (define_split
6476 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6477 (compare:CC (and:DI
6478 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6479 (match_operand:DI 2 "reg_or_cint_operand" ""))
6480 (match_operand:DI 3 "mask64_operand" ""))
6481 (const_int 0)))
6482 (set (match_operand:DI 0 "gpc_reg_operand" "")
6483 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6484 "TARGET_POWERPC64 && reload_completed"
6485 [(set (match_dup 0)
6486 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6487 (set (match_dup 4)
6488 (compare:CC (match_dup 0)
6489 (const_int 0)))]
6490 "")
6491
6492 (define_insn "*rotldi3_internal7"
6493 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6494 (zero_extend:DI
6495 (subreg:QI
6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6497 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6498 "TARGET_POWERPC64"
6499 "rld%I2cl %0,%1,%H2,56")
6500
6501 (define_insn "*rotldi3_internal8"
6502 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6503 (compare:CC (zero_extend:DI
6504 (subreg:QI
6505 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6506 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6507 (const_int 0)))
6508 (clobber (match_scratch:DI 3 "=r,r"))]
6509 "TARGET_64BIT"
6510 "@
6511 rld%I2cl. %3,%1,%H2,56
6512 #"
6513 [(set_attr "type" "delayed_compare")
6514 (set_attr "length" "4,8")])
6515
6516 (define_split
6517 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6518 (compare:CC (zero_extend:DI
6519 (subreg:QI
6520 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6521 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6522 (const_int 0)))
6523 (clobber (match_scratch:DI 3 ""))]
6524 "TARGET_POWERPC64 && reload_completed"
6525 [(set (match_dup 3)
6526 (zero_extend:DI (subreg:QI
6527 (rotate:DI (match_dup 1)
6528 (match_dup 2)) 0)))
6529 (set (match_dup 0)
6530 (compare:CC (match_dup 3)
6531 (const_int 0)))]
6532 "")
6533
6534 (define_insn "*rotldi3_internal9"
6535 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6536 (compare:CC (zero_extend:DI
6537 (subreg:QI
6538 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6539 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6540 (const_int 0)))
6541 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6542 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6543 "TARGET_64BIT"
6544 "@
6545 rld%I2cl. %0,%1,%H2,56
6546 #"
6547 [(set_attr "type" "delayed_compare")
6548 (set_attr "length" "4,8")])
6549
6550 (define_split
6551 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6552 (compare:CC (zero_extend:DI
6553 (subreg:QI
6554 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6555 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6556 (const_int 0)))
6557 (set (match_operand:DI 0 "gpc_reg_operand" "")
6558 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6559 "TARGET_POWERPC64 && reload_completed"
6560 [(set (match_dup 0)
6561 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6562 (set (match_dup 3)
6563 (compare:CC (match_dup 0)
6564 (const_int 0)))]
6565 "")
6566
6567 (define_insn "*rotldi3_internal10"
6568 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6569 (zero_extend:DI
6570 (subreg:HI
6571 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6572 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6573 "TARGET_POWERPC64"
6574 "rld%I2cl %0,%1,%H2,48")
6575
6576 (define_insn "*rotldi3_internal11"
6577 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6578 (compare:CC (zero_extend:DI
6579 (subreg:HI
6580 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6581 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6582 (const_int 0)))
6583 (clobber (match_scratch:DI 3 "=r,r"))]
6584 "TARGET_64BIT"
6585 "@
6586 rld%I2cl. %3,%1,%H2,48
6587 #"
6588 [(set_attr "type" "delayed_compare")
6589 (set_attr "length" "4,8")])
6590
6591 (define_split
6592 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6593 (compare:CC (zero_extend:DI
6594 (subreg:HI
6595 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6596 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6597 (const_int 0)))
6598 (clobber (match_scratch:DI 3 ""))]
6599 "TARGET_POWERPC64 && reload_completed"
6600 [(set (match_dup 3)
6601 (zero_extend:DI (subreg:HI
6602 (rotate:DI (match_dup 1)
6603 (match_dup 2)) 0)))
6604 (set (match_dup 0)
6605 (compare:CC (match_dup 3)
6606 (const_int 0)))]
6607 "")
6608
6609 (define_insn "*rotldi3_internal12"
6610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6611 (compare:CC (zero_extend:DI
6612 (subreg:HI
6613 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6614 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6615 (const_int 0)))
6616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6617 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6618 "TARGET_64BIT"
6619 "@
6620 rld%I2cl. %0,%1,%H2,48
6621 #"
6622 [(set_attr "type" "delayed_compare")
6623 (set_attr "length" "4,8")])
6624
6625 (define_split
6626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6627 (compare:CC (zero_extend:DI
6628 (subreg:HI
6629 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6630 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6631 (const_int 0)))
6632 (set (match_operand:DI 0 "gpc_reg_operand" "")
6633 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6634 "TARGET_POWERPC64 && reload_completed"
6635 [(set (match_dup 0)
6636 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6637 (set (match_dup 3)
6638 (compare:CC (match_dup 0)
6639 (const_int 0)))]
6640 "")
6641
6642 (define_insn "*rotldi3_internal13"
6643 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6644 (zero_extend:DI
6645 (subreg:SI
6646 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6647 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6648 "TARGET_POWERPC64"
6649 "rld%I2cl %0,%1,%H2,32")
6650
6651 (define_insn "*rotldi3_internal14"
6652 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6653 (compare:CC (zero_extend:DI
6654 (subreg:SI
6655 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6656 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6657 (const_int 0)))
6658 (clobber (match_scratch:DI 3 "=r,r"))]
6659 "TARGET_64BIT"
6660 "@
6661 rld%I2cl. %3,%1,%H2,32
6662 #"
6663 [(set_attr "type" "delayed_compare")
6664 (set_attr "length" "4,8")])
6665
6666 (define_split
6667 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6668 (compare:CC (zero_extend:DI
6669 (subreg:SI
6670 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6671 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6672 (const_int 0)))
6673 (clobber (match_scratch:DI 3 ""))]
6674 "TARGET_POWERPC64 && reload_completed"
6675 [(set (match_dup 3)
6676 (zero_extend:DI (subreg:SI
6677 (rotate:DI (match_dup 1)
6678 (match_dup 2)) 0)))
6679 (set (match_dup 0)
6680 (compare:CC (match_dup 3)
6681 (const_int 0)))]
6682 "")
6683
6684 (define_insn "*rotldi3_internal15"
6685 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6686 (compare:CC (zero_extend:DI
6687 (subreg:SI
6688 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6689 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6690 (const_int 0)))
6691 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6692 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6693 "TARGET_64BIT"
6694 "@
6695 rld%I2cl. %0,%1,%H2,32
6696 #"
6697 [(set_attr "type" "delayed_compare")
6698 (set_attr "length" "4,8")])
6699
6700 (define_split
6701 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6702 (compare:CC (zero_extend:DI
6703 (subreg:SI
6704 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6705 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6706 (const_int 0)))
6707 (set (match_operand:DI 0 "gpc_reg_operand" "")
6708 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6709 "TARGET_POWERPC64 && reload_completed"
6710 [(set (match_dup 0)
6711 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6712 (set (match_dup 3)
6713 (compare:CC (match_dup 0)
6714 (const_int 0)))]
6715 "")
6716
6717 (define_expand "ashldi3"
6718 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6719 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6720 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6721 "TARGET_POWERPC64 || TARGET_POWER"
6722 "
6723 {
6724 if (TARGET_POWERPC64)
6725 ;
6726 else if (TARGET_POWER)
6727 {
6728 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6729 DONE;
6730 }
6731 else
6732 FAIL;
6733 }")
6734
6735 (define_insn "*ashldi3_internal1"
6736 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6737 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6738 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6739 "TARGET_POWERPC64"
6740 "sld%I2 %0,%1,%H2"
6741 [(set_attr "length" "8")])
6742
6743 (define_insn "*ashldi3_internal2"
6744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6745 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6746 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6747 (const_int 0)))
6748 (clobber (match_scratch:DI 3 "=r,r"))]
6749 "TARGET_64BIT"
6750 "@
6751 sld%I2. %3,%1,%H2
6752 #"
6753 [(set_attr "type" "delayed_compare")
6754 (set_attr "length" "4,8")])
6755
6756 (define_split
6757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6758 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6759 (match_operand:SI 2 "reg_or_cint_operand" ""))
6760 (const_int 0)))
6761 (clobber (match_scratch:DI 3 ""))]
6762 "TARGET_POWERPC64 && reload_completed"
6763 [(set (match_dup 3)
6764 (ashift:DI (match_dup 1) (match_dup 2)))
6765 (set (match_dup 0)
6766 (compare:CC (match_dup 3)
6767 (const_int 0)))]
6768 "")
6769
6770 (define_insn "*ashldi3_internal3"
6771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6772 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6773 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6774 (const_int 0)))
6775 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6776 (ashift:DI (match_dup 1) (match_dup 2)))]
6777 "TARGET_64BIT"
6778 "@
6779 sld%I2. %0,%1,%H2
6780 #"
6781 [(set_attr "type" "delayed_compare")
6782 (set_attr "length" "4,8")])
6783
6784 (define_split
6785 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6786 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6787 (match_operand:SI 2 "reg_or_cint_operand" ""))
6788 (const_int 0)))
6789 (set (match_operand:DI 0 "gpc_reg_operand" "")
6790 (ashift:DI (match_dup 1) (match_dup 2)))]
6791 "TARGET_POWERPC64 && reload_completed"
6792 [(set (match_dup 0)
6793 (ashift:DI (match_dup 1) (match_dup 2)))
6794 (set (match_dup 3)
6795 (compare:CC (match_dup 0)
6796 (const_int 0)))]
6797 "")
6798
6799 (define_insn "*ashldi3_internal4"
6800 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6801 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6802 (match_operand:SI 2 "const_int_operand" "i"))
6803 (match_operand:DI 3 "const_int_operand" "n")))]
6804 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6805 "rldic %0,%1,%H2,%W3")
6806
6807 (define_insn "ashldi3_internal5"
6808 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6809 (compare:CC
6810 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6811 (match_operand:SI 2 "const_int_operand" "i,i"))
6812 (match_operand:DI 3 "const_int_operand" "n,n"))
6813 (const_int 0)))
6814 (clobber (match_scratch:DI 4 "=r,r"))]
6815 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6816 "@
6817 rldic. %4,%1,%H2,%W3
6818 #"
6819 [(set_attr "type" "delayed_compare")
6820 (set_attr "length" "4,8")])
6821
6822 (define_split
6823 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6824 (compare:CC
6825 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6826 (match_operand:SI 2 "const_int_operand" ""))
6827 (match_operand:DI 3 "const_int_operand" ""))
6828 (const_int 0)))
6829 (clobber (match_scratch:DI 4 ""))]
6830 "TARGET_POWERPC64 && reload_completed
6831 && includes_rldic_lshift_p (operands[2], operands[3])"
6832 [(set (match_dup 4)
6833 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6834 (match_dup 3)))
6835 (set (match_dup 0)
6836 (compare:CC (match_dup 4)
6837 (const_int 0)))]
6838 "")
6839
6840 (define_insn "*ashldi3_internal6"
6841 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6842 (compare:CC
6843 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6844 (match_operand:SI 2 "const_int_operand" "i,i"))
6845 (match_operand:DI 3 "const_int_operand" "n,n"))
6846 (const_int 0)))
6847 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6848 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6849 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6850 "@
6851 rldic. %0,%1,%H2,%W3
6852 #"
6853 [(set_attr "type" "delayed_compare")
6854 (set_attr "length" "4,8")])
6855
6856 (define_split
6857 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6858 (compare:CC
6859 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6860 (match_operand:SI 2 "const_int_operand" ""))
6861 (match_operand:DI 3 "const_int_operand" ""))
6862 (const_int 0)))
6863 (set (match_operand:DI 0 "gpc_reg_operand" "")
6864 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6865 "TARGET_POWERPC64 && reload_completed
6866 && includes_rldic_lshift_p (operands[2], operands[3])"
6867 [(set (match_dup 0)
6868 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6869 (match_dup 3)))
6870 (set (match_dup 4)
6871 (compare:CC (match_dup 0)
6872 (const_int 0)))]
6873 "")
6874
6875 (define_insn "*ashldi3_internal7"
6876 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6877 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6878 (match_operand:SI 2 "const_int_operand" "i"))
6879 (match_operand:DI 3 "mask64_operand" "n")))]
6880 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6881 "rldicr %0,%1,%H2,%S3")
6882
6883 (define_insn "ashldi3_internal8"
6884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6885 (compare:CC
6886 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6887 (match_operand:SI 2 "const_int_operand" "i,i"))
6888 (match_operand:DI 3 "mask64_operand" "n,n"))
6889 (const_int 0)))
6890 (clobber (match_scratch:DI 4 "=r,r"))]
6891 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6892 "@
6893 rldicr. %4,%1,%H2,%S3
6894 #"
6895 [(set_attr "type" "delayed_compare")
6896 (set_attr "length" "4,8")])
6897
6898 (define_split
6899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6900 (compare:CC
6901 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6902 (match_operand:SI 2 "const_int_operand" ""))
6903 (match_operand:DI 3 "mask64_operand" ""))
6904 (const_int 0)))
6905 (clobber (match_scratch:DI 4 ""))]
6906 "TARGET_POWERPC64 && reload_completed
6907 && includes_rldicr_lshift_p (operands[2], operands[3])"
6908 [(set (match_dup 4)
6909 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6910 (match_dup 3)))
6911 (set (match_dup 0)
6912 (compare:CC (match_dup 4)
6913 (const_int 0)))]
6914 "")
6915
6916 (define_insn "*ashldi3_internal9"
6917 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6918 (compare:CC
6919 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6920 (match_operand:SI 2 "const_int_operand" "i,i"))
6921 (match_operand:DI 3 "mask64_operand" "n,n"))
6922 (const_int 0)))
6923 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6924 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6925 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6926 "@
6927 rldicr. %0,%1,%H2,%S3
6928 #"
6929 [(set_attr "type" "delayed_compare")
6930 (set_attr "length" "4,8")])
6931
6932 (define_split
6933 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6934 (compare:CC
6935 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6936 (match_operand:SI 2 "const_int_operand" ""))
6937 (match_operand:DI 3 "mask64_operand" ""))
6938 (const_int 0)))
6939 (set (match_operand:DI 0 "gpc_reg_operand" "")
6940 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6941 "TARGET_POWERPC64 && reload_completed
6942 && includes_rldicr_lshift_p (operands[2], operands[3])"
6943 [(set (match_dup 0)
6944 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6945 (match_dup 3)))
6946 (set (match_dup 4)
6947 (compare:CC (match_dup 0)
6948 (const_int 0)))]
6949 "")
6950
6951 (define_expand "lshrdi3"
6952 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6953 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6954 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6955 "TARGET_POWERPC64 || TARGET_POWER"
6956 "
6957 {
6958 if (TARGET_POWERPC64)
6959 ;
6960 else if (TARGET_POWER)
6961 {
6962 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6963 DONE;
6964 }
6965 else
6966 FAIL;
6967 }")
6968
6969 (define_insn "*lshrdi3_internal1"
6970 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6971 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6972 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6973 "TARGET_POWERPC64"
6974 "srd%I2 %0,%1,%H2")
6975
6976 (define_insn "*lshrdi3_internal2"
6977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6978 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6979 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6980 (const_int 0)))
6981 (clobber (match_scratch:DI 3 "=r,r"))]
6982 "TARGET_64BIT "
6983 "@
6984 srd%I2. %3,%1,%H2
6985 #"
6986 [(set_attr "type" "delayed_compare")
6987 (set_attr "length" "4,8")])
6988
6989 (define_split
6990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6991 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:SI 2 "reg_or_cint_operand" ""))
6993 (const_int 0)))
6994 (clobber (match_scratch:DI 3 ""))]
6995 "TARGET_POWERPC64 && reload_completed"
6996 [(set (match_dup 3)
6997 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6998 (set (match_dup 0)
6999 (compare:CC (match_dup 3)
7000 (const_int 0)))]
7001 "")
7002
7003 (define_insn "*lshrdi3_internal3"
7004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7005 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7006 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7007 (const_int 0)))
7008 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7009 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7010 "TARGET_64BIT"
7011 "@
7012 srd%I2. %0,%1,%H2
7013 #"
7014 [(set_attr "type" "delayed_compare")
7015 (set_attr "length" "4,8")])
7016
7017 (define_split
7018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7019 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:SI 2 "reg_or_cint_operand" ""))
7021 (const_int 0)))
7022 (set (match_operand:DI 0 "gpc_reg_operand" "")
7023 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7024 "TARGET_POWERPC64 && reload_completed"
7025 [(set (match_dup 0)
7026 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7027 (set (match_dup 3)
7028 (compare:CC (match_dup 0)
7029 (const_int 0)))]
7030 "")
7031
7032 (define_expand "ashrdi3"
7033 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7034 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7035 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7036 "WORDS_BIG_ENDIAN"
7037 "
7038 {
7039 if (TARGET_POWERPC64)
7040 ;
7041 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7042 {
7043 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7044 DONE;
7045 }
7046 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7047 && WORDS_BIG_ENDIAN)
7048 {
7049 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7050 DONE;
7051 }
7052 else
7053 FAIL;
7054 }")
7055
7056 (define_insn "*ashrdi3_internal1"
7057 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7058 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7059 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7060 "TARGET_POWERPC64"
7061 "srad%I2 %0,%1,%H2")
7062
7063 (define_insn "*ashrdi3_internal2"
7064 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7065 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7066 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7067 (const_int 0)))
7068 (clobber (match_scratch:DI 3 "=r,r"))]
7069 "TARGET_64BIT"
7070 "@
7071 srad%I2. %3,%1,%H2
7072 #"
7073 [(set_attr "type" "delayed_compare")
7074 (set_attr "length" "4,8")])
7075
7076 (define_split
7077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7078 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7079 (match_operand:SI 2 "reg_or_cint_operand" ""))
7080 (const_int 0)))
7081 (clobber (match_scratch:DI 3 ""))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 3)
7084 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7085 (set (match_dup 0)
7086 (compare:CC (match_dup 3)
7087 (const_int 0)))]
7088 "")
7089
7090 (define_insn "*ashrdi3_internal3"
7091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7092 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7093 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7094 (const_int 0)))
7095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7096 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7097 "TARGET_64BIT"
7098 "@
7099 srad%I2. %0,%1,%H2
7100 #"
7101 [(set_attr "type" "delayed_compare")
7102 (set_attr "length" "4,8")])
7103
7104 (define_split
7105 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7106 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7107 (match_operand:SI 2 "reg_or_cint_operand" ""))
7108 (const_int 0)))
7109 (set (match_operand:DI 0 "gpc_reg_operand" "")
7110 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7111 "TARGET_POWERPC64 && reload_completed"
7112 [(set (match_dup 0)
7113 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7114 (set (match_dup 3)
7115 (compare:CC (match_dup 0)
7116 (const_int 0)))]
7117 "")
7118
7119 (define_insn "anddi3"
7120 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7121 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7122 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7123 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
7124 "TARGET_POWERPC64"
7125 "@
7126 and %0,%1,%2
7127 rldic%B2 %0,%1,0,%S2
7128 andi. %0,%1,%b2
7129 andis. %0,%1,%u2
7130 #"
7131 [(set_attr "length" "4,4,4,4,8")])
7132
7133 (define_split
7134 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7135 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7136 (match_operand:DI 2 "mask64_2_operand" "")))
7137 (clobber (match_scratch:CC 3 ""))]
7138 "TARGET_POWERPC64
7139 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7140 && !mask64_operand (operands[2], DImode)"
7141 [(set (match_dup 0)
7142 (and:DI (rotate:DI (match_dup 1)
7143 (match_dup 4))
7144 (match_dup 5)))
7145 (set (match_dup 0)
7146 (and:DI (rotate:DI (match_dup 0)
7147 (match_dup 6))
7148 (match_dup 7)))]
7149 "
7150 {
7151 build_mask64_2_operands (operands[2], &operands[4]);
7152 }")
7153
7154 (define_insn "*anddi3_internal2"
7155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7156 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7157 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7158 (const_int 0)))
7159 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7160 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7161 "TARGET_64BIT"
7162 "@
7163 and. %3,%1,%2
7164 rldic%B2. %3,%1,0,%S2
7165 andi. %3,%1,%b2
7166 andis. %3,%1,%u2
7167 #
7168 #
7169 #
7170 #
7171 #
7172 #"
7173 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7174 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7175
7176 (define_split
7177 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7178 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7179 (match_operand:DI 2 "and64_operand" ""))
7180 (const_int 0)))
7181 (clobber (match_scratch:DI 3 ""))
7182 (clobber (match_scratch:CC 4 ""))]
7183 "TARGET_POWERPC64 && reload_completed"
7184 [(parallel [(set (match_dup 3)
7185 (and:DI (match_dup 1)
7186 (match_dup 2)))
7187 (clobber (match_dup 4))])
7188 (set (match_dup 0)
7189 (compare:CC (match_dup 3)
7190 (const_int 0)))]
7191 "")
7192
7193 (define_split
7194 [(set (match_operand:CC 0 "cc_reg_operand" "")
7195 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7196 (match_operand:DI 2 "mask64_2_operand" ""))
7197 (const_int 0)))
7198 (clobber (match_scratch:DI 3 ""))
7199 (clobber (match_scratch:CC 4 ""))]
7200 "TARGET_POWERPC64 && reload_completed
7201 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7202 && !mask64_operand (operands[2], DImode)"
7203 [(set (match_dup 3)
7204 (and:DI (rotate:DI (match_dup 1)
7205 (match_dup 5))
7206 (match_dup 6)))
7207 (parallel [(set (match_dup 0)
7208 (compare:CC (and:DI (rotate:DI (match_dup 3)
7209 (match_dup 7))
7210 (match_dup 8))
7211 (const_int 0)))
7212 (clobber (match_dup 3))])]
7213 "
7214 {
7215 build_mask64_2_operands (operands[2], &operands[5]);
7216 }")
7217
7218 (define_insn "*anddi3_internal3"
7219 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7220 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7221 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7222 (const_int 0)))
7223 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7224 (and:DI (match_dup 1) (match_dup 2)))
7225 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7226 "TARGET_64BIT"
7227 "@
7228 and. %0,%1,%2
7229 rldic%B2. %0,%1,0,%S2
7230 andi. %0,%1,%b2
7231 andis. %0,%1,%u2
7232 #
7233 #
7234 #
7235 #
7236 #
7237 #"
7238 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7239 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7240
7241 (define_split
7242 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7243 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7244 (match_operand:DI 2 "and64_operand" ""))
7245 (const_int 0)))
7246 (set (match_operand:DI 0 "gpc_reg_operand" "")
7247 (and:DI (match_dup 1) (match_dup 2)))
7248 (clobber (match_scratch:CC 4 ""))]
7249 "TARGET_POWERPC64 && reload_completed"
7250 [(parallel [(set (match_dup 0)
7251 (and:DI (match_dup 1) (match_dup 2)))
7252 (clobber (match_dup 4))])
7253 (set (match_dup 3)
7254 (compare:CC (match_dup 0)
7255 (const_int 0)))]
7256 "")
7257
7258 (define_split
7259 [(set (match_operand:CC 3 "cc_reg_operand" "")
7260 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7261 (match_operand:DI 2 "mask64_2_operand" ""))
7262 (const_int 0)))
7263 (set (match_operand:DI 0 "gpc_reg_operand" "")
7264 (and:DI (match_dup 1) (match_dup 2)))
7265 (clobber (match_scratch:CC 4 ""))]
7266 "TARGET_POWERPC64 && reload_completed
7267 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7268 && !mask64_operand (operands[2], DImode)"
7269 [(set (match_dup 0)
7270 (and:DI (rotate:DI (match_dup 1)
7271 (match_dup 5))
7272 (match_dup 6)))
7273 (parallel [(set (match_dup 3)
7274 (compare:CC (and:DI (rotate:DI (match_dup 0)
7275 (match_dup 7))
7276 (match_dup 8))
7277 (const_int 0)))
7278 (set (match_dup 0)
7279 (and:DI (rotate:DI (match_dup 0)
7280 (match_dup 7))
7281 (match_dup 8)))])]
7282 "
7283 {
7284 build_mask64_2_operands (operands[2], &operands[5]);
7285 }")
7286
7287 (define_expand "iordi3"
7288 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7289 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7290 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7291 "TARGET_POWERPC64"
7292 "
7293 {
7294 if (non_logical_cint_operand (operands[2], DImode))
7295 {
7296 HOST_WIDE_INT value;
7297 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7298 ? operands[0] : gen_reg_rtx (DImode));
7299
7300 if (GET_CODE (operands[2]) == CONST_INT)
7301 {
7302 value = INTVAL (operands[2]);
7303 emit_insn (gen_iordi3 (tmp, operands[1],
7304 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7305 }
7306 else
7307 {
7308 value = CONST_DOUBLE_LOW (operands[2]);
7309 emit_insn (gen_iordi3 (tmp, operands[1],
7310 immed_double_const (value
7311 & (~ (HOST_WIDE_INT) 0xffff),
7312 0, DImode)));
7313 }
7314
7315 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7316 DONE;
7317 }
7318 }")
7319
7320 (define_expand "xordi3"
7321 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7322 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7323 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7324 "TARGET_POWERPC64"
7325 "
7326 {
7327 if (non_logical_cint_operand (operands[2], DImode))
7328 {
7329 HOST_WIDE_INT value;
7330 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7331 ? operands[0] : gen_reg_rtx (DImode));
7332
7333 if (GET_CODE (operands[2]) == CONST_INT)
7334 {
7335 value = INTVAL (operands[2]);
7336 emit_insn (gen_xordi3 (tmp, operands[1],
7337 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7338 }
7339 else
7340 {
7341 value = CONST_DOUBLE_LOW (operands[2]);
7342 emit_insn (gen_xordi3 (tmp, operands[1],
7343 immed_double_const (value
7344 & (~ (HOST_WIDE_INT) 0xffff),
7345 0, DImode)));
7346 }
7347
7348 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7349 DONE;
7350 }
7351 }")
7352
7353 (define_insn "*booldi3_internal1"
7354 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7355 (match_operator:DI 3 "boolean_or_operator"
7356 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7357 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7358 "TARGET_POWERPC64"
7359 "@
7360 %q3 %0,%1,%2
7361 %q3i %0,%1,%b2
7362 %q3is %0,%1,%u2")
7363
7364 (define_insn "*booldi3_internal2"
7365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7366 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7367 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7368 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7369 (const_int 0)))
7370 (clobber (match_scratch:DI 3 "=r,r"))]
7371 "TARGET_64BIT"
7372 "@
7373 %q4. %3,%1,%2
7374 #"
7375 [(set_attr "type" "compare")
7376 (set_attr "length" "4,8")])
7377
7378 (define_split
7379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7380 (compare:CC (match_operator:DI 4 "boolean_operator"
7381 [(match_operand:DI 1 "gpc_reg_operand" "")
7382 (match_operand:DI 2 "gpc_reg_operand" "")])
7383 (const_int 0)))
7384 (clobber (match_scratch:DI 3 ""))]
7385 "TARGET_POWERPC64 && reload_completed"
7386 [(set (match_dup 3) (match_dup 4))
7387 (set (match_dup 0)
7388 (compare:CC (match_dup 3)
7389 (const_int 0)))]
7390 "")
7391
7392 (define_insn "*booldi3_internal3"
7393 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7394 (compare:CC (match_operator:DI 4 "boolean_operator"
7395 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7396 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7397 (const_int 0)))
7398 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7399 (match_dup 4))]
7400 "TARGET_64BIT"
7401 "@
7402 %q4. %0,%1,%2
7403 #"
7404 [(set_attr "type" "compare")
7405 (set_attr "length" "4,8")])
7406
7407 (define_split
7408 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7409 (compare:CC (match_operator:DI 4 "boolean_operator"
7410 [(match_operand:DI 1 "gpc_reg_operand" "")
7411 (match_operand:DI 2 "gpc_reg_operand" "")])
7412 (const_int 0)))
7413 (set (match_operand:DI 0 "gpc_reg_operand" "")
7414 (match_dup 4))]
7415 "TARGET_POWERPC64 && reload_completed"
7416 [(set (match_dup 0) (match_dup 4))
7417 (set (match_dup 3)
7418 (compare:CC (match_dup 0)
7419 (const_int 0)))]
7420 "")
7421
7422 ;; Split a logical operation that we can't do in one insn into two insns,
7423 ;; each of which does one 16-bit part. This is used by combine.
7424
7425 (define_split
7426 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7427 (match_operator:DI 3 "boolean_or_operator"
7428 [(match_operand:DI 1 "gpc_reg_operand" "")
7429 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7430 "TARGET_POWERPC64"
7431 [(set (match_dup 0) (match_dup 4))
7432 (set (match_dup 0) (match_dup 5))]
7433 "
7434 {
7435 rtx i3,i4;
7436
7437 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7438 {
7439 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7440 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7441 0, DImode);
7442 i4 = GEN_INT (value & 0xffff);
7443 }
7444 else
7445 {
7446 i3 = GEN_INT (INTVAL (operands[2])
7447 & (~ (HOST_WIDE_INT) 0xffff));
7448 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7449 }
7450 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7451 operands[1], i3);
7452 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7453 operands[0], i4);
7454 }")
7455
7456 (define_insn "*boolcdi3_internal1"
7457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7458 (match_operator:DI 3 "boolean_operator"
7459 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7460 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7461 "TARGET_POWERPC64"
7462 "%q3 %0,%2,%1")
7463
7464 (define_insn "*boolcdi3_internal2"
7465 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7466 (compare:CC (match_operator:DI 4 "boolean_operator"
7467 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7468 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7469 (const_int 0)))
7470 (clobber (match_scratch:DI 3 "=r,r"))]
7471 "TARGET_64BIT"
7472 "@
7473 %q4. %3,%2,%1
7474 #"
7475 [(set_attr "type" "compare")
7476 (set_attr "length" "4,8")])
7477
7478 (define_split
7479 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7480 (compare:CC (match_operator:DI 4 "boolean_operator"
7481 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7482 (match_operand:DI 2 "gpc_reg_operand" "")])
7483 (const_int 0)))
7484 (clobber (match_scratch:DI 3 ""))]
7485 "TARGET_POWERPC64 && reload_completed"
7486 [(set (match_dup 3) (match_dup 4))
7487 (set (match_dup 0)
7488 (compare:CC (match_dup 3)
7489 (const_int 0)))]
7490 "")
7491
7492 (define_insn "*boolcdi3_internal3"
7493 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7494 (compare:CC (match_operator:DI 4 "boolean_operator"
7495 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7496 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7497 (const_int 0)))
7498 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7499 (match_dup 4))]
7500 "TARGET_64BIT"
7501 "@
7502 %q4. %0,%2,%1
7503 #"
7504 [(set_attr "type" "compare")
7505 (set_attr "length" "4,8")])
7506
7507 (define_split
7508 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7509 (compare:CC (match_operator:DI 4 "boolean_operator"
7510 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7511 (match_operand:DI 2 "gpc_reg_operand" "")])
7512 (const_int 0)))
7513 (set (match_operand:DI 0 "gpc_reg_operand" "")
7514 (match_dup 4))]
7515 "TARGET_POWERPC64 && reload_completed"
7516 [(set (match_dup 0) (match_dup 4))
7517 (set (match_dup 3)
7518 (compare:CC (match_dup 0)
7519 (const_int 0)))]
7520 "")
7521
7522 (define_insn "*boolccdi3_internal1"
7523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7524 (match_operator:DI 3 "boolean_operator"
7525 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7526 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7527 "TARGET_POWERPC64"
7528 "%q3 %0,%1,%2")
7529
7530 (define_insn "*boolccdi3_internal2"
7531 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7532 (compare:CC (match_operator:DI 4 "boolean_operator"
7533 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7534 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7535 (const_int 0)))
7536 (clobber (match_scratch:DI 3 "=r,r"))]
7537 "TARGET_64BIT"
7538 "@
7539 %q4. %3,%1,%2
7540 #"
7541 [(set_attr "type" "compare")
7542 (set_attr "length" "4,8")])
7543
7544 (define_split
7545 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7546 (compare:CC (match_operator:DI 4 "boolean_operator"
7547 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7548 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7549 (const_int 0)))
7550 (clobber (match_scratch:DI 3 ""))]
7551 "TARGET_POWERPC64 && reload_completed"
7552 [(set (match_dup 3) (match_dup 4))
7553 (set (match_dup 0)
7554 (compare:CC (match_dup 3)
7555 (const_int 0)))]
7556 "")
7557
7558 (define_insn "*boolccdi3_internal3"
7559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7560 (compare:CC (match_operator:DI 4 "boolean_operator"
7561 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7562 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7563 (const_int 0)))
7564 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7565 (match_dup 4))]
7566 "TARGET_64BIT"
7567 "@
7568 %q4. %0,%1,%2
7569 #"
7570 [(set_attr "type" "compare")
7571 (set_attr "length" "4,8")])
7572
7573 (define_split
7574 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7575 (compare:CC (match_operator:DI 4 "boolean_operator"
7576 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7577 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7578 (const_int 0)))
7579 (set (match_operand:DI 0 "gpc_reg_operand" "")
7580 (match_dup 4))]
7581 "TARGET_POWERPC64 && reload_completed"
7582 [(set (match_dup 0) (match_dup 4))
7583 (set (match_dup 3)
7584 (compare:CC (match_dup 0)
7585 (const_int 0)))]
7586 "")
7587 \f
7588 ;; Now define ways of moving data around.
7589
7590 ;; Elf specific ways of loading addresses for non-PIC code.
7591 ;; The output of this could be r0, but we make a very strong
7592 ;; preference for a base register because it will usually
7593 ;; be needed there.
7594 (define_insn "elf_high"
7595 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7596 (high:SI (match_operand 1 "" "")))]
7597 "TARGET_ELF && ! TARGET_64BIT"
7598 "{liu|lis} %0,%1@ha")
7599
7600 (define_insn "elf_low"
7601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7602 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7603 (match_operand 2 "" "")))]
7604 "TARGET_ELF && ! TARGET_64BIT"
7605 "@
7606 {cal|la} %0,%2@l(%1)
7607 {ai|addic} %0,%1,%K2")
7608
7609 ;; Mach-O PIC trickery.
7610 (define_insn "macho_high"
7611 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7612 (high:SI (match_operand 1 "" "")))]
7613 "TARGET_MACHO && ! TARGET_64BIT"
7614 "{liu|lis} %0,ha16(%1)")
7615
7616 (define_insn "macho_low"
7617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7618 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7619 (match_operand 2 "" "")))]
7620 "TARGET_MACHO && ! TARGET_64BIT"
7621 "@
7622 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7623 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7624
7625 ;; Set up a register with a value from the GOT table
7626
7627 (define_expand "movsi_got"
7628 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7629 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7630 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7631 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7632 "
7633 {
7634 if (GET_CODE (operands[1]) == CONST)
7635 {
7636 rtx offset = const0_rtx;
7637 HOST_WIDE_INT value;
7638
7639 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7640 value = INTVAL (offset);
7641 if (value != 0)
7642 {
7643 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7644 emit_insn (gen_movsi_got (tmp, operands[1]));
7645 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7646 DONE;
7647 }
7648 }
7649
7650 operands[2] = rs6000_got_register (operands[1]);
7651 }")
7652
7653 (define_insn "*movsi_got_internal"
7654 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7655 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7656 (match_operand:SI 2 "gpc_reg_operand" "b")]
7657 UNSPEC_MOVSI_GOT))]
7658 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7659 "{l|lwz} %0,%a1@got(%2)"
7660 [(set_attr "type" "load")])
7661
7662 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7663 ;; didn't get allocated to a hard register.
7664 (define_split
7665 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7666 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7667 (match_operand:SI 2 "memory_operand" "")]
7668 UNSPEC_MOVSI_GOT))]
7669 "DEFAULT_ABI == ABI_V4
7670 && flag_pic == 1
7671 && (reload_in_progress || reload_completed)"
7672 [(set (match_dup 0) (match_dup 2))
7673 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7674 UNSPEC_MOVSI_GOT))]
7675 "")
7676
7677 ;; For SI, we special-case integers that can't be loaded in one insn. We
7678 ;; do the load 16-bits at a time. We could do this by loading from memory,
7679 ;; and this is even supposed to be faster, but it is simpler not to get
7680 ;; integers in the TOC.
7681 (define_expand "movsi"
7682 [(set (match_operand:SI 0 "general_operand" "")
7683 (match_operand:SI 1 "any_operand" ""))]
7684 ""
7685 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7686
7687 (define_insn "movsi_low"
7688 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7689 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7690 (match_operand 2 "" ""))))]
7691 "TARGET_MACHO && ! TARGET_64BIT"
7692 "{l|lwz} %0,lo16(%2)(%1)"
7693 [(set_attr "type" "load")
7694 (set_attr "length" "4")])
7695
7696 (define_insn "movsi_low_st"
7697 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7698 (match_operand 2 "" "")))
7699 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7700 "TARGET_MACHO && ! TARGET_64BIT"
7701 "{st|stw} %0,lo16(%2)(%1)"
7702 [(set_attr "type" "store")
7703 (set_attr "length" "4")])
7704
7705 (define_insn "movdf_low"
7706 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7707 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7708 (match_operand 2 "" ""))))]
7709 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7710 "*
7711 {
7712 switch (which_alternative)
7713 {
7714 case 0:
7715 return \"lfd %0,lo16(%2)(%1)\";
7716 case 1:
7717 {
7718 rtx operands2[4];
7719 operands2[0] = operands[0];
7720 operands2[1] = operands[1];
7721 operands2[2] = operands[2];
7722 if (TARGET_POWERPC64 && TARGET_32BIT)
7723 /* Note, old assemblers didn't support relocation here. */
7724 return \"ld %0,lo16(%2)(%1)\";
7725 else
7726 {
7727 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7728 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7729 #if TARGET_MACHO
7730 if (MACHO_DYNAMIC_NO_PIC_P)
7731 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7732 else
7733 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7734 although in practice it almost always is. */
7735 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7736 #endif
7737 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7738 }
7739 }
7740 default:
7741 abort();
7742 }
7743 }"
7744 [(set_attr "type" "load")
7745 (set_attr "length" "4,12")])
7746
7747 (define_insn "movdf_low_st"
7748 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7749 (match_operand 2 "" "")))
7750 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7751 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7752 "stfd %0,lo16(%2)(%1)"
7753 [(set_attr "type" "store")
7754 (set_attr "length" "4")])
7755
7756 (define_insn "movsf_low"
7757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7758 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7759 (match_operand 2 "" ""))))]
7760 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7761 "@
7762 lfs %0,lo16(%2)(%1)
7763 {l|lwz} %0,lo16(%2)(%1)"
7764 [(set_attr "type" "load")
7765 (set_attr "length" "4")])
7766
7767 (define_insn "movsf_low_st"
7768 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7769 (match_operand 2 "" "")))
7770 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7771 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7772 "@
7773 stfs %0,lo16(%2)(%1)
7774 {st|stw} %0,lo16(%2)(%1)"
7775 [(set_attr "type" "store")
7776 (set_attr "length" "4")])
7777
7778 (define_insn "*movsi_internal1"
7779 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7780 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7781 "gpc_reg_operand (operands[0], SImode)
7782 || gpc_reg_operand (operands[1], SImode)"
7783 "@
7784 mr %0,%1
7785 {cal|la} %0,%a1
7786 {l%U1%X1|lwz%U1%X1} %0,%1
7787 {st%U0%X0|stw%U0%X0} %1,%0
7788 {lil|li} %0,%1
7789 {liu|lis} %0,%v1
7790 #
7791 {cal|la} %0,%a1
7792 mf%1 %0
7793 mt%0 %1
7794 mt%0 %1
7795 mt%0 %1
7796 {cror 0,0,0|nop}"
7797 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7798 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7799
7800 ;; Split a load of a large constant into the appropriate two-insn
7801 ;; sequence.
7802
7803 (define_split
7804 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7805 (match_operand:SI 1 "const_int_operand" ""))]
7806 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7807 && (INTVAL (operands[1]) & 0xffff) != 0"
7808 [(set (match_dup 0)
7809 (match_dup 2))
7810 (set (match_dup 0)
7811 (ior:SI (match_dup 0)
7812 (match_dup 3)))]
7813 "
7814 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7815
7816 if (tem == operands[0])
7817 DONE;
7818 else
7819 FAIL;
7820 }")
7821
7822 (define_insn "*movsi_internal2"
7823 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7824 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7825 (const_int 0)))
7826 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7827 "TARGET_32BIT"
7828 "@
7829 {cmpi|cmpwi} %2,%0,0
7830 mr. %0,%1
7831 #"
7832 [(set_attr "type" "cmp,compare,cmp")
7833 (set_attr "length" "4,4,8")])
7834
7835 (define_split
7836 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7837 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7838 (const_int 0)))
7839 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7840 "TARGET_32BIT && reload_completed"
7841 [(set (match_dup 0) (match_dup 1))
7842 (set (match_dup 2)
7843 (compare:CC (match_dup 0)
7844 (const_int 0)))]
7845 "")
7846 \f
7847 (define_expand "movhi"
7848 [(set (match_operand:HI 0 "general_operand" "")
7849 (match_operand:HI 1 "any_operand" ""))]
7850 ""
7851 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7852
7853 (define_insn "*movhi_internal"
7854 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7855 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7856 "gpc_reg_operand (operands[0], HImode)
7857 || gpc_reg_operand (operands[1], HImode)"
7858 "@
7859 mr %0,%1
7860 lhz%U1%X1 %0,%1
7861 sth%U0%X0 %1,%0
7862 {lil|li} %0,%w1
7863 mf%1 %0
7864 mt%0 %1
7865 mt%0 %1
7866 {cror 0,0,0|nop}"
7867 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7868
7869 (define_expand "movqi"
7870 [(set (match_operand:QI 0 "general_operand" "")
7871 (match_operand:QI 1 "any_operand" ""))]
7872 ""
7873 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7874
7875 (define_insn "*movqi_internal"
7876 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7877 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7878 "gpc_reg_operand (operands[0], QImode)
7879 || gpc_reg_operand (operands[1], QImode)"
7880 "@
7881 mr %0,%1
7882 lbz%U1%X1 %0,%1
7883 stb%U0%X0 %1,%0
7884 {lil|li} %0,%1
7885 mf%1 %0
7886 mt%0 %1
7887 mt%0 %1
7888 {cror 0,0,0|nop}"
7889 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7890 \f
7891 ;; Here is how to move condition codes around. When we store CC data in
7892 ;; an integer register or memory, we store just the high-order 4 bits.
7893 ;; This lets us not shift in the most common case of CR0.
7894 (define_expand "movcc"
7895 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7896 (match_operand:CC 1 "nonimmediate_operand" ""))]
7897 ""
7898 "")
7899
7900 (define_insn "*movcc_internal1"
7901 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7902 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7903 "register_operand (operands[0], CCmode)
7904 || register_operand (operands[1], CCmode)"
7905 "@
7906 mcrf %0,%1
7907 mtcrf 128,%1
7908 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7909 mfcr %0%Q1
7910 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7911 mr %0,%1
7912 mf%1 %0
7913 mt%0 %1
7914 mt%0 %1
7915 {l%U1%X1|lwz%U1%X1} %0,%1
7916 {st%U0%U1|stw%U0%U1} %1,%0"
7917 [(set (attr "type")
7918 (cond [(eq_attr "alternative" "0")
7919 (const_string "cr_logical")
7920 (eq_attr "alternative" "1,2")
7921 (const_string "mtcr")
7922 (eq_attr "alternative" "5,7")
7923 (const_string "integer")
7924 (eq_attr "alternative" "6")
7925 (const_string "mfjmpr")
7926 (eq_attr "alternative" "8")
7927 (const_string "mtjmpr")
7928 (eq_attr "alternative" "9")
7929 (const_string "load")
7930 (eq_attr "alternative" "10")
7931 (const_string "store")
7932 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7933 (const_string "mfcrf")
7934 ]
7935 (const_string "mfcr")))
7936 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7937 \f
7938 ;; For floating-point, we normally deal with the floating-point registers
7939 ;; unless -msoft-float is used. The sole exception is that parameter passing
7940 ;; can produce floating-point values in fixed-point registers. Unless the
7941 ;; value is a simple constant or already in memory, we deal with this by
7942 ;; allocating memory and copying the value explicitly via that memory location.
7943 (define_expand "movsf"
7944 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7945 (match_operand:SF 1 "any_operand" ""))]
7946 ""
7947 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7948
7949 (define_split
7950 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7951 (match_operand:SF 1 "const_double_operand" ""))]
7952 "reload_completed
7953 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7954 || (GET_CODE (operands[0]) == SUBREG
7955 && GET_CODE (SUBREG_REG (operands[0])) == REG
7956 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7957 [(set (match_dup 2) (match_dup 3))]
7958 "
7959 {
7960 long l;
7961 REAL_VALUE_TYPE rv;
7962
7963 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7964 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7965
7966 if (! TARGET_POWERPC64)
7967 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7968 else
7969 operands[2] = gen_lowpart (SImode, operands[0]);
7970
7971 operands[3] = gen_int_mode (l, SImode);
7972 }")
7973
7974 (define_insn "*movsf_hardfloat"
7975 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7976 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7977 "(gpc_reg_operand (operands[0], SFmode)
7978 || gpc_reg_operand (operands[1], SFmode))
7979 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7980 "@
7981 mr %0,%1
7982 {l%U1%X1|lwz%U1%X1} %0,%1
7983 {st%U0%X0|stw%U0%X0} %1,%0
7984 fmr %0,%1
7985 lfs%U1%X1 %0,%1
7986 stfs%U0%X0 %1,%0
7987 mt%0 %1
7988 mt%0 %1
7989 mf%1 %0
7990 {cror 0,0,0|nop}
7991 #
7992 #"
7993 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7994 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7995
7996 (define_insn "*movsf_softfloat"
7997 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7998 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7999 "(gpc_reg_operand (operands[0], SFmode)
8000 || gpc_reg_operand (operands[1], SFmode))
8001 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8002 "@
8003 mr %0,%1
8004 mt%0 %1
8005 mt%0 %1
8006 mf%1 %0
8007 {l%U1%X1|lwz%U1%X1} %0,%1
8008 {st%U0%X0|stw%U0%X0} %1,%0
8009 {lil|li} %0,%1
8010 {liu|lis} %0,%v1
8011 {cal|la} %0,%a1
8012 #
8013 #
8014 {cror 0,0,0|nop}"
8015 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
8016 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8017
8018 \f
8019 (define_expand "movdf"
8020 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8021 (match_operand:DF 1 "any_operand" ""))]
8022 ""
8023 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8024
8025 (define_split
8026 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8027 (match_operand:DF 1 "const_int_operand" ""))]
8028 "! TARGET_POWERPC64 && reload_completed
8029 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8030 || (GET_CODE (operands[0]) == SUBREG
8031 && GET_CODE (SUBREG_REG (operands[0])) == REG
8032 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8033 [(set (match_dup 2) (match_dup 4))
8034 (set (match_dup 3) (match_dup 1))]
8035 "
8036 {
8037 int endian = (WORDS_BIG_ENDIAN == 0);
8038 HOST_WIDE_INT value = INTVAL (operands[1]);
8039
8040 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8041 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8042 #if HOST_BITS_PER_WIDE_INT == 32
8043 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8044 #else
8045 operands[4] = GEN_INT (value >> 32);
8046 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8047 #endif
8048 }")
8049
8050 (define_split
8051 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8052 (match_operand:DF 1 "const_double_operand" ""))]
8053 "! TARGET_POWERPC64 && reload_completed
8054 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8055 || (GET_CODE (operands[0]) == SUBREG
8056 && GET_CODE (SUBREG_REG (operands[0])) == REG
8057 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8058 [(set (match_dup 2) (match_dup 4))
8059 (set (match_dup 3) (match_dup 5))]
8060 "
8061 {
8062 int endian = (WORDS_BIG_ENDIAN == 0);
8063 long l[2];
8064 REAL_VALUE_TYPE rv;
8065
8066 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8067 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8068
8069 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8070 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8071 operands[4] = gen_int_mode (l[endian], SImode);
8072 operands[5] = gen_int_mode (l[1 - endian], SImode);
8073 }")
8074
8075 (define_split
8076 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8077 (match_operand:DF 1 "easy_fp_constant" ""))]
8078 "TARGET_POWERPC64 && reload_completed
8079 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8080 || (GET_CODE (operands[0]) == SUBREG
8081 && GET_CODE (SUBREG_REG (operands[0])) == REG
8082 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8083 [(set (match_dup 2) (match_dup 3))]
8084 "
8085 {
8086 int endian = (WORDS_BIG_ENDIAN == 0);
8087 long l[2];
8088 REAL_VALUE_TYPE rv;
8089 #if HOST_BITS_PER_WIDE_INT >= 64
8090 HOST_WIDE_INT val;
8091 #endif
8092
8093 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8094 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8095
8096 operands[2] = gen_lowpart (DImode, operands[0]);
8097 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8098 #if HOST_BITS_PER_WIDE_INT >= 64
8099 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8100 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8101
8102 operands[3] = gen_int_mode (val, DImode);
8103 #else
8104 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8105 #endif
8106 }")
8107
8108 ;; Don't have reload use general registers to load a constant. First,
8109 ;; it might not work if the output operand is the equivalent of
8110 ;; a non-offsettable memref, but also it is less efficient than loading
8111 ;; the constant into an FP register, since it will probably be used there.
8112 ;; The "??" is a kludge until we can figure out a more reasonable way
8113 ;; of handling these non-offsettable values.
8114 (define_insn "*movdf_hardfloat32"
8115 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8116 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8117 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8118 && (gpc_reg_operand (operands[0], DFmode)
8119 || gpc_reg_operand (operands[1], DFmode))"
8120 "*
8121 {
8122 switch (which_alternative)
8123 {
8124 default:
8125 abort ();
8126 case 0:
8127 /* We normally copy the low-numbered register first. However, if
8128 the first register operand 0 is the same as the second register
8129 of operand 1, we must copy in the opposite order. */
8130 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8131 return \"mr %L0,%L1\;mr %0,%1\";
8132 else
8133 return \"mr %0,%1\;mr %L0,%L1\";
8134 case 1:
8135 if (GET_CODE (operands[1]) == MEM
8136 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8137 reload_completed || reload_in_progress)
8138 || GET_CODE (XEXP (operands[1], 0)) == REG
8139 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8140 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8141 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8142 {
8143 /* If the low-address word is used in the address, we must load
8144 it last. Otherwise, load it first. Note that we cannot have
8145 auto-increment in that case since the address register is
8146 known to be dead. */
8147 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8148 operands[1], 0))
8149 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8150 else
8151 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8152 }
8153 else
8154 {
8155 rtx addreg;
8156
8157 addreg = find_addr_reg (XEXP (operands[1], 0));
8158 if (refers_to_regno_p (REGNO (operands[0]),
8159 REGNO (operands[0]) + 1,
8160 operands[1], 0))
8161 {
8162 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8163 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8164 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8165 return \"{lx|lwzx} %0,%1\";
8166 }
8167 else
8168 {
8169 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8170 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8171 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8172 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8173 return \"\";
8174 }
8175 }
8176 case 2:
8177 if (GET_CODE (operands[0]) == MEM
8178 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8179 reload_completed || reload_in_progress)
8180 || GET_CODE (XEXP (operands[0], 0)) == REG
8181 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8182 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8183 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8184 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8185 else
8186 {
8187 rtx addreg;
8188
8189 addreg = find_addr_reg (XEXP (operands[0], 0));
8190 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8191 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8192 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8193 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8194 return \"\";
8195 }
8196 case 3:
8197 return \"fmr %0,%1\";
8198 case 4:
8199 return \"lfd%U1%X1 %0,%1\";
8200 case 5:
8201 return \"stfd%U0%X0 %1,%0\";
8202 case 6:
8203 case 7:
8204 case 8:
8205 return \"#\";
8206 }
8207 }"
8208 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8209 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8210
8211 (define_insn "*movdf_softfloat32"
8212 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8213 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8214 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8215 && (gpc_reg_operand (operands[0], DFmode)
8216 || gpc_reg_operand (operands[1], DFmode))"
8217 "*
8218 {
8219 switch (which_alternative)
8220 {
8221 default:
8222 abort ();
8223 case 0:
8224 /* We normally copy the low-numbered register first. However, if
8225 the first register operand 0 is the same as the second register of
8226 operand 1, we must copy in the opposite order. */
8227 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8228 return \"mr %L0,%L1\;mr %0,%1\";
8229 else
8230 return \"mr %0,%1\;mr %L0,%L1\";
8231 case 1:
8232 /* If the low-address word is used in the address, we must load
8233 it last. Otherwise, load it first. Note that we cannot have
8234 auto-increment in that case since the address register is
8235 known to be dead. */
8236 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8237 operands[1], 0))
8238 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8239 else
8240 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8241 case 2:
8242 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8243 case 3:
8244 case 4:
8245 case 5:
8246 return \"#\";
8247 }
8248 }"
8249 [(set_attr "type" "*,load,store,*,*,*")
8250 (set_attr "length" "8,8,8,8,12,16")])
8251
8252 ; ld/std require word-aligned displacements -> 'Y' constraint.
8253 ; List Y->r and r->Y before r->r for reload.
8254 (define_insn "*movdf_hardfloat64"
8255 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8256 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8257 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8258 && (gpc_reg_operand (operands[0], DFmode)
8259 || gpc_reg_operand (operands[1], DFmode))"
8260 "@
8261 std%U0%X0 %1,%0
8262 ld%U1%X1 %0,%1
8263 mr %0,%1
8264 fmr %0,%1
8265 lfd%U1%X1 %0,%1
8266 stfd%U0%X0 %1,%0
8267 mt%0 %1
8268 mf%1 %0
8269 {cror 0,0,0|nop}
8270 #
8271 #
8272 #"
8273 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8274 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8275
8276 (define_insn "*movdf_softfloat64"
8277 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8278 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8279 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8280 && (gpc_reg_operand (operands[0], DFmode)
8281 || gpc_reg_operand (operands[1], DFmode))"
8282 "@
8283 ld%U1%X1 %0,%1
8284 std%U0%X0 %1,%0
8285 mr %0,%1
8286 mt%0 %1
8287 mf%1 %0
8288 #
8289 #
8290 #
8291 {cror 0,0,0|nop}"
8292 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8293 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8294 \f
8295 (define_expand "movtf"
8296 [(set (match_operand:TF 0 "general_operand" "")
8297 (match_operand:TF 1 "any_operand" ""))]
8298 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8299 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8300 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8301
8302 ; It's important to list the o->f and f->o moves before f->f because
8303 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8304 ; which doesn't make progress.
8305 (define_insn_and_split "*movtf_internal"
8306 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
8307 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
8308 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8309 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8310 && (gpc_reg_operand (operands[0], TFmode)
8311 || gpc_reg_operand (operands[1], TFmode))"
8312 "#"
8313 "&& reload_completed"
8314 [(pc)]
8315 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8316 [(set_attr "length" "8,8,8,20,20")])
8317
8318 (define_expand "extenddftf2"
8319 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8320 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8321 (use (match_dup 2))])]
8322 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8323 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8324 {
8325 operands[2] = CONST0_RTX (DFmode);
8326 })
8327
8328 (define_insn_and_split "*extenddftf2_internal"
8329 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8330 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8331 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8332 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8333 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8334 "#"
8335 "&& reload_completed"
8336 [(pc)]
8337 {
8338 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8339 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8340 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8341 operands[1]);
8342 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8343 operands[2]);
8344 DONE;
8345 })
8346
8347 (define_expand "extendsftf2"
8348 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8349 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8350 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8351 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8352 {
8353 rtx tmp = gen_reg_rtx (DFmode);
8354 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8355 emit_insn (gen_extenddftf2 (operands[0], tmp));
8356 DONE;
8357 })
8358
8359 (define_insn "trunctfdf2"
8360 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8361 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8362 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8363 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8364 "fadd %0,%1,%L1"
8365 [(set_attr "type" "fp")
8366 (set_attr "length" "4")])
8367
8368 (define_insn_and_split "trunctfsf2"
8369 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8370 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8371 (clobber (match_scratch:DF 2 "=f"))]
8372 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8373 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8374 "#"
8375 "&& reload_completed"
8376 [(set (match_dup 2)
8377 (float_truncate:DF (match_dup 1)))
8378 (set (match_dup 0)
8379 (float_truncate:SF (match_dup 2)))]
8380 "")
8381
8382 (define_expand "floatsitf2"
8383 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8384 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8385 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8386 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8387 {
8388 rtx tmp = gen_reg_rtx (DFmode);
8389 expand_float (tmp, operands[1], false);
8390 emit_insn (gen_extenddftf2 (operands[0], tmp));
8391 DONE;
8392 })
8393
8394 ; fadd, but rounding towards zero.
8395 ; This is probably not the optimal code sequence.
8396 (define_insn "fix_trunc_helper"
8397 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8398 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8399 UNSPEC_FIX_TRUNC_TF))
8400 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8401 "TARGET_HARD_FLOAT && TARGET_FPRS"
8402 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8403 [(set_attr "type" "fp")
8404 (set_attr "length" "20")])
8405
8406 (define_expand "fix_trunctfsi2"
8407 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8408 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8409 (clobber (match_dup 2))
8410 (clobber (match_dup 3))
8411 (clobber (match_dup 4))
8412 (clobber (match_dup 5))])]
8413 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8414 && (TARGET_POWER2 || TARGET_POWERPC)
8415 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8416 {
8417 operands[2] = gen_reg_rtx (DFmode);
8418 operands[3] = gen_reg_rtx (DFmode);
8419 operands[4] = gen_reg_rtx (DImode);
8420 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8421 })
8422
8423 (define_insn_and_split "*fix_trunctfsi2_internal"
8424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8425 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8426 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8427 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8428 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8429 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8430 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8431 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8432 "#"
8433 "&& reload_completed"
8434 [(pc)]
8435 {
8436 rtx lowword;
8437 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8438
8439 if (GET_CODE (operands[5]) != MEM)
8440 abort();
8441 lowword = XEXP (operands[5], 0);
8442 if (WORDS_BIG_ENDIAN)
8443 lowword = plus_constant (lowword, 4);
8444
8445 emit_insn (gen_fctiwz (operands[4], operands[2]));
8446 emit_move_insn (operands[5], operands[4]);
8447 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8448 DONE;
8449 })
8450
8451 (define_insn "negtf2"
8452 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8453 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8454 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8455 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8456 "*
8457 {
8458 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8459 return \"fneg %L0,%L1\;fneg %0,%1\";
8460 else
8461 return \"fneg %0,%1\;fneg %L0,%L1\";
8462 }"
8463 [(set_attr "type" "fp")
8464 (set_attr "length" "8")])
8465
8466 (define_expand "abstf2"
8467 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8468 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8469 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8470 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8471 "
8472 {
8473 rtx label = gen_label_rtx ();
8474 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8475 emit_label (label);
8476 DONE;
8477 }")
8478
8479 (define_expand "abstf2_internal"
8480 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8481 (match_operand:TF 1 "gpc_reg_operand" "f"))
8482 (set (match_dup 3) (match_dup 5))
8483 (set (match_dup 5) (abs:DF (match_dup 5)))
8484 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8485 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8486 (label_ref (match_operand 2 "" ""))
8487 (pc)))
8488 (set (match_dup 6) (neg:DF (match_dup 6)))]
8489 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8490 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8491 "
8492 {
8493 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8494 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8495 operands[3] = gen_reg_rtx (DFmode);
8496 operands[4] = gen_reg_rtx (CCFPmode);
8497 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8498 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8499 }")
8500 \f
8501 ;; Next come the multi-word integer load and store and the load and store
8502 ;; multiple insns.
8503 (define_expand "movdi"
8504 [(set (match_operand:DI 0 "general_operand" "")
8505 (match_operand:DI 1 "any_operand" ""))]
8506 ""
8507 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8508
8509 (define_insn "*movdi_internal32"
8510 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8511 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8512 "! TARGET_POWERPC64
8513 && (gpc_reg_operand (operands[0], DImode)
8514 || gpc_reg_operand (operands[1], DImode))"
8515 "*
8516 {
8517 switch (which_alternative)
8518 {
8519 default:
8520 abort ();
8521 case 0:
8522 case 1:
8523 case 2:
8524 return \"#\";
8525 case 3:
8526 return \"fmr %0,%1\";
8527 case 4:
8528 return \"lfd%U1%X1 %0,%1\";
8529 case 5:
8530 return \"stfd%U0%X0 %1,%0\";
8531 case 6:
8532 case 7:
8533 case 8:
8534 case 9:
8535 case 10:
8536 return \"#\";
8537 }
8538 }"
8539 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
8540
8541 (define_split
8542 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8543 (match_operand:DI 1 "const_int_operand" ""))]
8544 "! TARGET_POWERPC64 && reload_completed"
8545 [(set (match_dup 2) (match_dup 4))
8546 (set (match_dup 3) (match_dup 1))]
8547 "
8548 {
8549 HOST_WIDE_INT value = INTVAL (operands[1]);
8550 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8551 DImode);
8552 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8553 DImode);
8554 #if HOST_BITS_PER_WIDE_INT == 32
8555 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8556 #else
8557 operands[4] = GEN_INT (value >> 32);
8558 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8559 #endif
8560 }")
8561
8562 (define_split
8563 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8564 (match_operand:DI 1 "input_operand" ""))]
8565 "reload_completed && !TARGET_POWERPC64
8566 && gpr_or_gpr_p (operands[0], operands[1])"
8567 [(pc)]
8568 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8569
8570 (define_split
8571 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8572 (match_operand:TI 1 "const_double_operand" ""))]
8573 "TARGET_POWERPC64"
8574 [(set (match_dup 2) (match_dup 4))
8575 (set (match_dup 3) (match_dup 5))]
8576 "
8577 {
8578 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8579 TImode);
8580 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8581 TImode);
8582 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8583 {
8584 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8585 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8586 }
8587 else if (GET_CODE (operands[1]) == CONST_INT)
8588 {
8589 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8590 operands[5] = operands[1];
8591 }
8592 else
8593 FAIL;
8594 }")
8595
8596 (define_insn "*movdi_internal64"
8597 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
8598 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8599 "TARGET_POWERPC64
8600 && (gpc_reg_operand (operands[0], DImode)
8601 || gpc_reg_operand (operands[1], DImode))"
8602 "@
8603 mr %0,%1
8604 ld%U1%X1 %0,%1
8605 std%U0%X0 %1,%0
8606 li %0,%1
8607 lis %0,%v1
8608 #
8609 {cal|la} %0,%a1
8610 fmr %0,%1
8611 lfd%U1%X1 %0,%1
8612 stfd%U0%X0 %1,%0
8613 mf%1 %0
8614 mt%0 %1
8615 {cror 0,0,0|nop}"
8616 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8617 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8618
8619 ;; immediate value valid for a single instruction hiding in a const_double
8620 (define_insn ""
8621 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8622 (match_operand:DI 1 "const_double_operand" "F"))]
8623 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8624 && GET_CODE (operands[1]) == CONST_DOUBLE
8625 && num_insns_constant (operands[1], DImode) == 1"
8626 "*
8627 {
8628 return ((unsigned HOST_WIDE_INT)
8629 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8630 ? \"li %0,%1\" : \"lis %0,%v1\";
8631 }")
8632
8633 ;; Generate all one-bits and clear left or right.
8634 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8635 (define_split
8636 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8637 (match_operand:DI 1 "mask64_operand" ""))]
8638 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8639 [(set (match_dup 0) (const_int -1))
8640 (set (match_dup 0)
8641 (and:DI (rotate:DI (match_dup 0)
8642 (const_int 0))
8643 (match_dup 1)))]
8644 "")
8645
8646 ;; Split a load of a large constant into the appropriate five-instruction
8647 ;; sequence. Handle anything in a constant number of insns.
8648 ;; When non-easy constants can go in the TOC, this should use
8649 ;; easy_fp_constant predicate.
8650 (define_split
8651 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8652 (match_operand:DI 1 "const_int_operand" ""))]
8653 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8654 [(set (match_dup 0) (match_dup 2))
8655 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8656 "
8657 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8658
8659 if (tem == operands[0])
8660 DONE;
8661 else
8662 FAIL;
8663 }")
8664
8665 (define_split
8666 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8667 (match_operand:DI 1 "const_double_operand" ""))]
8668 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8669 [(set (match_dup 0) (match_dup 2))
8670 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8671 "
8672 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8673
8674 if (tem == operands[0])
8675 DONE;
8676 else
8677 FAIL;
8678 }")
8679
8680 (define_insn "*movdi_internal2"
8681 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8682 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8683 (const_int 0)))
8684 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8685 "TARGET_64BIT"
8686 "@
8687 cmpdi %2,%0,0
8688 mr. %0,%1
8689 #"
8690 [(set_attr "type" "cmp,compare,cmp")
8691 (set_attr "length" "4,4,8")])
8692
8693 (define_split
8694 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8695 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8696 (const_int 0)))
8697 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8698 "TARGET_POWERPC64 && reload_completed"
8699 [(set (match_dup 0) (match_dup 1))
8700 (set (match_dup 2)
8701 (compare:CC (match_dup 0)
8702 (const_int 0)))]
8703 "")
8704 \f
8705 ;; TImode is similar, except that we usually want to compute the address into
8706 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8707 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8708 (define_expand "movti"
8709 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8710 (match_operand:TI 1 "general_operand" ""))
8711 (clobber (scratch:SI))])]
8712 ""
8713 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8714
8715 ;; We say that MQ is clobbered in the last alternative because the first
8716 ;; alternative would never get used otherwise since it would need a reload
8717 ;; while the 2nd alternative would not. We put memory cases first so they
8718 ;; are preferred. Otherwise, we'd try to reload the output instead of
8719 ;; giving the SCRATCH mq.
8720
8721 (define_insn "*movti_power"
8722 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8723 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8724 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8725 "TARGET_POWER && ! TARGET_POWERPC64
8726 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8727 "*
8728 {
8729 switch (which_alternative)
8730 {
8731 default:
8732 abort ();
8733
8734 case 0:
8735 if (TARGET_STRING)
8736 return \"{stsi|stswi} %1,%P0,16\";
8737 case 1:
8738 case 2:
8739 return \"#\";
8740 case 3:
8741 /* If the address is not used in the output, we can use lsi. Otherwise,
8742 fall through to generating four loads. */
8743 if (TARGET_STRING
8744 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8745 return \"{lsi|lswi} %0,%P1,16\";
8746 /* ... fall through ... */
8747 case 4:
8748 return \"#\";
8749 }
8750 }"
8751 [(set_attr "type" "store,store,*,load,load")])
8752
8753 (define_insn "*movti_string"
8754 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8755 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8756 "! TARGET_POWER && ! TARGET_POWERPC64
8757 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8758 "*
8759 {
8760 switch (which_alternative)
8761 {
8762 default:
8763 abort ();
8764 case 0:
8765 if (TARGET_STRING)
8766 return \"{stsi|stswi} %1,%P0,16\";
8767 case 1:
8768 case 2:
8769 return \"#\";
8770 case 3:
8771 /* If the address is not used in the output, we can use lsi. Otherwise,
8772 fall through to generating four loads. */
8773 if (TARGET_STRING
8774 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8775 return \"{lsi|lswi} %0,%P1,16\";
8776 /* ... fall through ... */
8777 case 4:
8778 return \"#\";
8779 }
8780 }"
8781 [(set_attr "type" "store,store,*,load,load")])
8782
8783 (define_insn "*movti_ppc64"
8784 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8785 (match_operand:TI 1 "input_operand" "r,r,o"))]
8786 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8787 || gpc_reg_operand (operands[1], TImode))"
8788 "@
8789 #
8790 #
8791 #"
8792 [(set_attr "type" "*,load,store")])
8793
8794 (define_split
8795 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8796 (match_operand:TI 1 "input_operand" ""))]
8797 "reload_completed
8798 && gpr_or_gpr_p (operands[0], operands[1])"
8799 [(pc)]
8800 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8801 \f
8802 (define_expand "load_multiple"
8803 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8804 (match_operand:SI 1 "" ""))
8805 (use (match_operand:SI 2 "" ""))])]
8806 "TARGET_STRING && !TARGET_POWERPC64"
8807 "
8808 {
8809 int regno;
8810 int count;
8811 rtx op1;
8812 int i;
8813
8814 /* Support only loading a constant number of fixed-point registers from
8815 memory and only bother with this if more than two; the machine
8816 doesn't support more than eight. */
8817 if (GET_CODE (operands[2]) != CONST_INT
8818 || INTVAL (operands[2]) <= 2
8819 || INTVAL (operands[2]) > 8
8820 || GET_CODE (operands[1]) != MEM
8821 || GET_CODE (operands[0]) != REG
8822 || REGNO (operands[0]) >= 32)
8823 FAIL;
8824
8825 count = INTVAL (operands[2]);
8826 regno = REGNO (operands[0]);
8827
8828 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8829 op1 = replace_equiv_address (operands[1],
8830 force_reg (SImode, XEXP (operands[1], 0)));
8831
8832 for (i = 0; i < count; i++)
8833 XVECEXP (operands[3], 0, i)
8834 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8835 adjust_address_nv (op1, SImode, i * 4));
8836 }")
8837
8838 (define_insn "*ldmsi8"
8839 [(match_parallel 0 "load_multiple_operation"
8840 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8841 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8842 (set (match_operand:SI 3 "gpc_reg_operand" "")
8843 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8844 (set (match_operand:SI 4 "gpc_reg_operand" "")
8845 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8846 (set (match_operand:SI 5 "gpc_reg_operand" "")
8847 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8848 (set (match_operand:SI 6 "gpc_reg_operand" "")
8849 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8850 (set (match_operand:SI 7 "gpc_reg_operand" "")
8851 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8852 (set (match_operand:SI 8 "gpc_reg_operand" "")
8853 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8854 (set (match_operand:SI 9 "gpc_reg_operand" "")
8855 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8856 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8857 "*
8858 { return rs6000_output_load_multiple (operands); }"
8859 [(set_attr "type" "load")
8860 (set_attr "length" "32")])
8861
8862 (define_insn "*ldmsi7"
8863 [(match_parallel 0 "load_multiple_operation"
8864 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8865 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8866 (set (match_operand:SI 3 "gpc_reg_operand" "")
8867 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8868 (set (match_operand:SI 4 "gpc_reg_operand" "")
8869 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8870 (set (match_operand:SI 5 "gpc_reg_operand" "")
8871 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8872 (set (match_operand:SI 6 "gpc_reg_operand" "")
8873 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8874 (set (match_operand:SI 7 "gpc_reg_operand" "")
8875 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8876 (set (match_operand:SI 8 "gpc_reg_operand" "")
8877 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8878 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8879 "*
8880 { return rs6000_output_load_multiple (operands); }"
8881 [(set_attr "type" "load")
8882 (set_attr "length" "32")])
8883
8884 (define_insn "*ldmsi6"
8885 [(match_parallel 0 "load_multiple_operation"
8886 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8887 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8888 (set (match_operand:SI 3 "gpc_reg_operand" "")
8889 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8890 (set (match_operand:SI 4 "gpc_reg_operand" "")
8891 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8892 (set (match_operand:SI 5 "gpc_reg_operand" "")
8893 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8894 (set (match_operand:SI 6 "gpc_reg_operand" "")
8895 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8896 (set (match_operand:SI 7 "gpc_reg_operand" "")
8897 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8898 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8899 "*
8900 { return rs6000_output_load_multiple (operands); }"
8901 [(set_attr "type" "load")
8902 (set_attr "length" "32")])
8903
8904 (define_insn "*ldmsi5"
8905 [(match_parallel 0 "load_multiple_operation"
8906 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8907 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8908 (set (match_operand:SI 3 "gpc_reg_operand" "")
8909 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8910 (set (match_operand:SI 4 "gpc_reg_operand" "")
8911 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8912 (set (match_operand:SI 5 "gpc_reg_operand" "")
8913 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8914 (set (match_operand:SI 6 "gpc_reg_operand" "")
8915 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8916 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8917 "*
8918 { return rs6000_output_load_multiple (operands); }"
8919 [(set_attr "type" "load")
8920 (set_attr "length" "32")])
8921
8922 (define_insn "*ldmsi4"
8923 [(match_parallel 0 "load_multiple_operation"
8924 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8925 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8926 (set (match_operand:SI 3 "gpc_reg_operand" "")
8927 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8928 (set (match_operand:SI 4 "gpc_reg_operand" "")
8929 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8930 (set (match_operand:SI 5 "gpc_reg_operand" "")
8931 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8932 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8933 "*
8934 { return rs6000_output_load_multiple (operands); }"
8935 [(set_attr "type" "load")
8936 (set_attr "length" "32")])
8937
8938 (define_insn "*ldmsi3"
8939 [(match_parallel 0 "load_multiple_operation"
8940 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8941 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8942 (set (match_operand:SI 3 "gpc_reg_operand" "")
8943 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8944 (set (match_operand:SI 4 "gpc_reg_operand" "")
8945 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8946 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8947 "*
8948 { return rs6000_output_load_multiple (operands); }"
8949 [(set_attr "type" "load")
8950 (set_attr "length" "32")])
8951
8952 (define_expand "store_multiple"
8953 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8954 (match_operand:SI 1 "" ""))
8955 (clobber (scratch:SI))
8956 (use (match_operand:SI 2 "" ""))])]
8957 "TARGET_STRING && !TARGET_POWERPC64"
8958 "
8959 {
8960 int regno;
8961 int count;
8962 rtx to;
8963 rtx op0;
8964 int i;
8965
8966 /* Support only storing a constant number of fixed-point registers to
8967 memory and only bother with this if more than two; the machine
8968 doesn't support more than eight. */
8969 if (GET_CODE (operands[2]) != CONST_INT
8970 || INTVAL (operands[2]) <= 2
8971 || INTVAL (operands[2]) > 8
8972 || GET_CODE (operands[0]) != MEM
8973 || GET_CODE (operands[1]) != REG
8974 || REGNO (operands[1]) >= 32)
8975 FAIL;
8976
8977 count = INTVAL (operands[2]);
8978 regno = REGNO (operands[1]);
8979
8980 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8981 to = force_reg (SImode, XEXP (operands[0], 0));
8982 op0 = replace_equiv_address (operands[0], to);
8983
8984 XVECEXP (operands[3], 0, 0)
8985 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8986 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8987 gen_rtx_SCRATCH (SImode));
8988
8989 for (i = 1; i < count; i++)
8990 XVECEXP (operands[3], 0, i + 1)
8991 = gen_rtx_SET (VOIDmode,
8992 adjust_address_nv (op0, SImode, i * 4),
8993 gen_rtx_REG (SImode, regno + i));
8994 }")
8995
8996 (define_insn "*store_multiple_power"
8997 [(match_parallel 0 "store_multiple_operation"
8998 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8999 (match_operand:SI 2 "gpc_reg_operand" "r"))
9000 (clobber (match_scratch:SI 3 "=q"))])]
9001 "TARGET_STRING && TARGET_POWER"
9002 "{stsi|stswi} %2,%P1,%O0"
9003 [(set_attr "type" "store")])
9004
9005 (define_insn "*stmsi8"
9006 [(match_parallel 0 "store_multiple_operation"
9007 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9008 (match_operand:SI 2 "gpc_reg_operand" "r"))
9009 (clobber (match_scratch:SI 3 "X"))
9010 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9011 (match_operand:SI 4 "gpc_reg_operand" "r"))
9012 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9013 (match_operand:SI 5 "gpc_reg_operand" "r"))
9014 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9015 (match_operand:SI 6 "gpc_reg_operand" "r"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9017 (match_operand:SI 7 "gpc_reg_operand" "r"))
9018 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9019 (match_operand:SI 8 "gpc_reg_operand" "r"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9021 (match_operand:SI 9 "gpc_reg_operand" "r"))
9022 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9023 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9024 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9025 "{stsi|stswi} %2,%1,%O0"
9026 [(set_attr "type" "store")])
9027
9028 (define_insn "*stmsi7"
9029 [(match_parallel 0 "store_multiple_operation"
9030 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9031 (match_operand:SI 2 "gpc_reg_operand" "r"))
9032 (clobber (match_scratch:SI 3 "X"))
9033 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9034 (match_operand:SI 4 "gpc_reg_operand" "r"))
9035 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9036 (match_operand:SI 5 "gpc_reg_operand" "r"))
9037 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9038 (match_operand:SI 6 "gpc_reg_operand" "r"))
9039 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9040 (match_operand:SI 7 "gpc_reg_operand" "r"))
9041 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9042 (match_operand:SI 8 "gpc_reg_operand" "r"))
9043 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9044 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9045 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9046 "{stsi|stswi} %2,%1,%O0"
9047 [(set_attr "type" "store")])
9048
9049 (define_insn "*stmsi6"
9050 [(match_parallel 0 "store_multiple_operation"
9051 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9052 (match_operand:SI 2 "gpc_reg_operand" "r"))
9053 (clobber (match_scratch:SI 3 "X"))
9054 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9055 (match_operand:SI 4 "gpc_reg_operand" "r"))
9056 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9057 (match_operand:SI 5 "gpc_reg_operand" "r"))
9058 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9059 (match_operand:SI 6 "gpc_reg_operand" "r"))
9060 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9061 (match_operand:SI 7 "gpc_reg_operand" "r"))
9062 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9063 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9064 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9065 "{stsi|stswi} %2,%1,%O0"
9066 [(set_attr "type" "store")])
9067
9068 (define_insn "*stmsi5"
9069 [(match_parallel 0 "store_multiple_operation"
9070 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9071 (match_operand:SI 2 "gpc_reg_operand" "r"))
9072 (clobber (match_scratch:SI 3 "X"))
9073 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9074 (match_operand:SI 4 "gpc_reg_operand" "r"))
9075 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9076 (match_operand:SI 5 "gpc_reg_operand" "r"))
9077 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9078 (match_operand:SI 6 "gpc_reg_operand" "r"))
9079 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9080 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9081 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9082 "{stsi|stswi} %2,%1,%O0"
9083 [(set_attr "type" "store")])
9084
9085 (define_insn "*stmsi4"
9086 [(match_parallel 0 "store_multiple_operation"
9087 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9088 (match_operand:SI 2 "gpc_reg_operand" "r"))
9089 (clobber (match_scratch:SI 3 "X"))
9090 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9091 (match_operand:SI 4 "gpc_reg_operand" "r"))
9092 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9093 (match_operand:SI 5 "gpc_reg_operand" "r"))
9094 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9095 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9096 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9097 "{stsi|stswi} %2,%1,%O0"
9098 [(set_attr "type" "store")])
9099
9100 (define_insn "*stmsi3"
9101 [(match_parallel 0 "store_multiple_operation"
9102 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9103 (match_operand:SI 2 "gpc_reg_operand" "r"))
9104 (clobber (match_scratch:SI 3 "X"))
9105 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9106 (match_operand:SI 4 "gpc_reg_operand" "r"))
9107 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9108 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9109 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9110 "{stsi|stswi} %2,%1,%O0"
9111 [(set_attr "type" "store")])
9112 \f
9113 ;; String/block move insn.
9114 ;; Argument 0 is the destination
9115 ;; Argument 1 is the source
9116 ;; Argument 2 is the length
9117 ;; Argument 3 is the alignment
9118
9119 (define_expand "movmemsi"
9120 [(parallel [(set (match_operand:BLK 0 "" "")
9121 (match_operand:BLK 1 "" ""))
9122 (use (match_operand:SI 2 "" ""))
9123 (use (match_operand:SI 3 "" ""))])]
9124 ""
9125 "
9126 {
9127 if (expand_block_move (operands))
9128 DONE;
9129 else
9130 FAIL;
9131 }")
9132
9133 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9134 ;; register allocator doesn't have a clue about allocating 8 word registers.
9135 ;; rD/rS = r5 is preferred, efficient form.
9136 (define_expand "movmemsi_8reg"
9137 [(parallel [(set (match_operand 0 "" "")
9138 (match_operand 1 "" ""))
9139 (use (match_operand 2 "" ""))
9140 (use (match_operand 3 "" ""))
9141 (clobber (reg:SI 5))
9142 (clobber (reg:SI 6))
9143 (clobber (reg:SI 7))
9144 (clobber (reg:SI 8))
9145 (clobber (reg:SI 9))
9146 (clobber (reg:SI 10))
9147 (clobber (reg:SI 11))
9148 (clobber (reg:SI 12))
9149 (clobber (match_scratch:SI 4 ""))])]
9150 "TARGET_STRING"
9151 "")
9152
9153 (define_insn ""
9154 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9155 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9156 (use (match_operand:SI 2 "immediate_operand" "i"))
9157 (use (match_operand:SI 3 "immediate_operand" "i"))
9158 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9159 (clobber (reg:SI 6))
9160 (clobber (reg:SI 7))
9161 (clobber (reg:SI 8))
9162 (clobber (reg:SI 9))
9163 (clobber (reg:SI 10))
9164 (clobber (reg:SI 11))
9165 (clobber (reg:SI 12))
9166 (clobber (match_scratch:SI 5 "=q"))]
9167 "TARGET_STRING && TARGET_POWER
9168 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9169 || INTVAL (operands[2]) == 0)
9170 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9171 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9172 && REGNO (operands[4]) == 5"
9173 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9174 [(set_attr "type" "load")
9175 (set_attr "length" "8")])
9176
9177 (define_insn ""
9178 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9179 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9180 (use (match_operand:SI 2 "immediate_operand" "i"))
9181 (use (match_operand:SI 3 "immediate_operand" "i"))
9182 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9183 (clobber (reg:SI 6))
9184 (clobber (reg:SI 7))
9185 (clobber (reg:SI 8))
9186 (clobber (reg:SI 9))
9187 (clobber (reg:SI 10))
9188 (clobber (reg:SI 11))
9189 (clobber (reg:SI 12))
9190 (clobber (match_scratch:SI 5 "X"))]
9191 "TARGET_STRING && ! TARGET_POWER
9192 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9193 || INTVAL (operands[2]) == 0)
9194 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9195 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9196 && REGNO (operands[4]) == 5"
9197 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9198 [(set_attr "type" "load")
9199 (set_attr "length" "8")])
9200
9201 (define_insn ""
9202 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9203 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9204 (use (match_operand:SI 2 "immediate_operand" "i"))
9205 (use (match_operand:SI 3 "immediate_operand" "i"))
9206 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9207 (clobber (reg:SI 6))
9208 (clobber (reg:SI 7))
9209 (clobber (reg:SI 8))
9210 (clobber (reg:SI 9))
9211 (clobber (reg:SI 10))
9212 (clobber (reg:SI 11))
9213 (clobber (reg:SI 12))
9214 (clobber (match_scratch:SI 5 "X"))]
9215 "TARGET_STRING && TARGET_POWERPC64
9216 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9217 || INTVAL (operands[2]) == 0)
9218 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9219 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9220 && REGNO (operands[4]) == 5"
9221 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9222 [(set_attr "type" "load")
9223 (set_attr "length" "8")])
9224
9225 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9226 ;; register allocator doesn't have a clue about allocating 6 word registers.
9227 ;; rD/rS = r5 is preferred, efficient form.
9228 (define_expand "movmemsi_6reg"
9229 [(parallel [(set (match_operand 0 "" "")
9230 (match_operand 1 "" ""))
9231 (use (match_operand 2 "" ""))
9232 (use (match_operand 3 "" ""))
9233 (clobber (reg:SI 5))
9234 (clobber (reg:SI 6))
9235 (clobber (reg:SI 7))
9236 (clobber (reg:SI 8))
9237 (clobber (reg:SI 9))
9238 (clobber (reg:SI 10))
9239 (clobber (match_scratch:SI 4 ""))])]
9240 "TARGET_STRING"
9241 "")
9242
9243 (define_insn ""
9244 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9245 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9246 (use (match_operand:SI 2 "immediate_operand" "i"))
9247 (use (match_operand:SI 3 "immediate_operand" "i"))
9248 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9249 (clobber (reg:SI 6))
9250 (clobber (reg:SI 7))
9251 (clobber (reg:SI 8))
9252 (clobber (reg:SI 9))
9253 (clobber (reg:SI 10))
9254 (clobber (match_scratch:SI 5 "=q"))]
9255 "TARGET_STRING && TARGET_POWER
9256 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9257 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9258 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9259 && REGNO (operands[4]) == 5"
9260 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9261 [(set_attr "type" "load")
9262 (set_attr "length" "8")])
9263
9264 (define_insn ""
9265 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9266 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9267 (use (match_operand:SI 2 "immediate_operand" "i"))
9268 (use (match_operand:SI 3 "immediate_operand" "i"))
9269 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9270 (clobber (reg:SI 6))
9271 (clobber (reg:SI 7))
9272 (clobber (reg:SI 8))
9273 (clobber (reg:SI 9))
9274 (clobber (reg:SI 10))
9275 (clobber (match_scratch:SI 5 "X"))]
9276 "TARGET_STRING && ! TARGET_POWER
9277 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9278 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9279 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9280 && REGNO (operands[4]) == 5"
9281 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9282 [(set_attr "type" "load")
9283 (set_attr "length" "8")])
9284
9285 (define_insn ""
9286 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9287 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9288 (use (match_operand:SI 2 "immediate_operand" "i"))
9289 (use (match_operand:SI 3 "immediate_operand" "i"))
9290 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9291 (clobber (reg:SI 6))
9292 (clobber (reg:SI 7))
9293 (clobber (reg:SI 8))
9294 (clobber (reg:SI 9))
9295 (clobber (reg:SI 10))
9296 (clobber (match_scratch:SI 5 "X"))]
9297 "TARGET_STRING && TARGET_POWERPC64
9298 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9299 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9300 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9301 && REGNO (operands[4]) == 5"
9302 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9303 [(set_attr "type" "load")
9304 (set_attr "length" "8")])
9305
9306 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9307 ;; problems with TImode.
9308 ;; rD/rS = r5 is preferred, efficient form.
9309 (define_expand "movmemsi_4reg"
9310 [(parallel [(set (match_operand 0 "" "")
9311 (match_operand 1 "" ""))
9312 (use (match_operand 2 "" ""))
9313 (use (match_operand 3 "" ""))
9314 (clobber (reg:SI 5))
9315 (clobber (reg:SI 6))
9316 (clobber (reg:SI 7))
9317 (clobber (reg:SI 8))
9318 (clobber (match_scratch:SI 4 ""))])]
9319 "TARGET_STRING"
9320 "")
9321
9322 (define_insn ""
9323 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9324 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9325 (use (match_operand:SI 2 "immediate_operand" "i"))
9326 (use (match_operand:SI 3 "immediate_operand" "i"))
9327 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9328 (clobber (reg:SI 6))
9329 (clobber (reg:SI 7))
9330 (clobber (reg:SI 8))
9331 (clobber (match_scratch:SI 5 "=q"))]
9332 "TARGET_STRING && TARGET_POWER
9333 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9334 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9335 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9336 && REGNO (operands[4]) == 5"
9337 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9338 [(set_attr "type" "load")
9339 (set_attr "length" "8")])
9340
9341 (define_insn ""
9342 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9343 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9344 (use (match_operand:SI 2 "immediate_operand" "i"))
9345 (use (match_operand:SI 3 "immediate_operand" "i"))
9346 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9347 (clobber (reg:SI 6))
9348 (clobber (reg:SI 7))
9349 (clobber (reg:SI 8))
9350 (clobber (match_scratch:SI 5 "X"))]
9351 "TARGET_STRING && ! TARGET_POWER
9352 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9353 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9354 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9355 && REGNO (operands[4]) == 5"
9356 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9357 [(set_attr "type" "load")
9358 (set_attr "length" "8")])
9359
9360 (define_insn ""
9361 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9362 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9363 (use (match_operand:SI 2 "immediate_operand" "i"))
9364 (use (match_operand:SI 3 "immediate_operand" "i"))
9365 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9366 (clobber (reg:SI 6))
9367 (clobber (reg:SI 7))
9368 (clobber (reg:SI 8))
9369 (clobber (match_scratch:SI 5 "X"))]
9370 "TARGET_STRING && TARGET_POWERPC64
9371 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9372 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9373 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9374 && REGNO (operands[4]) == 5"
9375 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9376 [(set_attr "type" "load")
9377 (set_attr "length" "8")])
9378
9379 ;; Move up to 8 bytes at a time.
9380 (define_expand "movmemsi_2reg"
9381 [(parallel [(set (match_operand 0 "" "")
9382 (match_operand 1 "" ""))
9383 (use (match_operand 2 "" ""))
9384 (use (match_operand 3 "" ""))
9385 (clobber (match_scratch:DI 4 ""))
9386 (clobber (match_scratch:SI 5 ""))])]
9387 "TARGET_STRING && ! TARGET_POWERPC64"
9388 "")
9389
9390 (define_insn ""
9391 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9392 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9393 (use (match_operand:SI 2 "immediate_operand" "i"))
9394 (use (match_operand:SI 3 "immediate_operand" "i"))
9395 (clobber (match_scratch:DI 4 "=&r"))
9396 (clobber (match_scratch:SI 5 "=q"))]
9397 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9398 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9399 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9400 [(set_attr "type" "load")
9401 (set_attr "length" "8")])
9402
9403 (define_insn ""
9404 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9405 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9406 (use (match_operand:SI 2 "immediate_operand" "i"))
9407 (use (match_operand:SI 3 "immediate_operand" "i"))
9408 (clobber (match_scratch:DI 4 "=&r"))
9409 (clobber (match_scratch:SI 5 "X"))]
9410 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9411 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9412 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9413 [(set_attr "type" "load")
9414 (set_attr "length" "8")])
9415
9416 ;; Move up to 4 bytes at a time.
9417 (define_expand "movmemsi_1reg"
9418 [(parallel [(set (match_operand 0 "" "")
9419 (match_operand 1 "" ""))
9420 (use (match_operand 2 "" ""))
9421 (use (match_operand 3 "" ""))
9422 (clobber (match_scratch:SI 4 ""))
9423 (clobber (match_scratch:SI 5 ""))])]
9424 "TARGET_STRING"
9425 "")
9426
9427 (define_insn ""
9428 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9429 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9430 (use (match_operand:SI 2 "immediate_operand" "i"))
9431 (use (match_operand:SI 3 "immediate_operand" "i"))
9432 (clobber (match_scratch:SI 4 "=&r"))
9433 (clobber (match_scratch:SI 5 "=q"))]
9434 "TARGET_STRING && TARGET_POWER
9435 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9436 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9437 [(set_attr "type" "load")
9438 (set_attr "length" "8")])
9439
9440 (define_insn ""
9441 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9442 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9443 (use (match_operand:SI 2 "immediate_operand" "i"))
9444 (use (match_operand:SI 3 "immediate_operand" "i"))
9445 (clobber (match_scratch:SI 4 "=&r"))
9446 (clobber (match_scratch:SI 5 "X"))]
9447 "TARGET_STRING && ! TARGET_POWER
9448 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9449 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9450 [(set_attr "type" "load")
9451 (set_attr "length" "8")])
9452
9453 (define_insn ""
9454 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9455 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9456 (use (match_operand:SI 2 "immediate_operand" "i"))
9457 (use (match_operand:SI 3 "immediate_operand" "i"))
9458 (clobber (match_scratch:SI 4 "=&r"))
9459 (clobber (match_scratch:SI 5 "X"))]
9460 "TARGET_STRING && TARGET_POWERPC64
9461 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9462 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9463 [(set_attr "type" "load")
9464 (set_attr "length" "8")])
9465
9466 \f
9467 ;; Define insns that do load or store with update. Some of these we can
9468 ;; get by using pre-decrement or pre-increment, but the hardware can also
9469 ;; do cases where the increment is not the size of the object.
9470 ;;
9471 ;; In all these cases, we use operands 0 and 1 for the register being
9472 ;; incremented because those are the operands that local-alloc will
9473 ;; tie and these are the pair most likely to be tieable (and the ones
9474 ;; that will benefit the most).
9475
9476 (define_insn "*movdi_update1"
9477 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9478 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9479 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9480 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9481 (plus:DI (match_dup 1) (match_dup 2)))]
9482 "TARGET_POWERPC64 && TARGET_UPDATE"
9483 "@
9484 ldux %3,%0,%2
9485 ldu %3,%2(%0)"
9486 [(set_attr "type" "load_ux,load_u")])
9487
9488 (define_insn "movdi_update"
9489 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9490 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9491 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9492 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9493 (plus:DI (match_dup 1) (match_dup 2)))]
9494 "TARGET_POWERPC64 && TARGET_UPDATE"
9495 "@
9496 stdux %3,%0,%2
9497 stdu %3,%2(%0)"
9498 [(set_attr "type" "store_ux,store_u")])
9499
9500 (define_insn "*movsi_update1"
9501 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9502 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9503 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9504 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9505 (plus:SI (match_dup 1) (match_dup 2)))]
9506 "TARGET_UPDATE"
9507 "@
9508 {lux|lwzux} %3,%0,%2
9509 {lu|lwzu} %3,%2(%0)"
9510 [(set_attr "type" "load_ux,load_u")])
9511
9512 (define_insn "*movsi_update2"
9513 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9514 (sign_extend:DI
9515 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9516 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9517 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9518 (plus:DI (match_dup 1) (match_dup 2)))]
9519 "TARGET_POWERPC64"
9520 "lwaux %3,%0,%2"
9521 [(set_attr "type" "load_ext_ux")])
9522
9523 (define_insn "movsi_update"
9524 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9525 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9526 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9527 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9528 (plus:SI (match_dup 1) (match_dup 2)))]
9529 "TARGET_UPDATE"
9530 "@
9531 {stux|stwux} %3,%0,%2
9532 {stu|stwu} %3,%2(%0)"
9533 [(set_attr "type" "store_ux,store_u")])
9534
9535 (define_insn "*movhi_update1"
9536 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9537 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9538 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9539 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9540 (plus:SI (match_dup 1) (match_dup 2)))]
9541 "TARGET_UPDATE"
9542 "@
9543 lhzux %3,%0,%2
9544 lhzu %3,%2(%0)"
9545 [(set_attr "type" "load_ux,load_u")])
9546
9547 (define_insn "*movhi_update2"
9548 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9549 (zero_extend:SI
9550 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9551 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9552 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9553 (plus:SI (match_dup 1) (match_dup 2)))]
9554 "TARGET_UPDATE"
9555 "@
9556 lhzux %3,%0,%2
9557 lhzu %3,%2(%0)"
9558 [(set_attr "type" "load_ux,load_u")])
9559
9560 (define_insn "*movhi_update3"
9561 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9562 (sign_extend:SI
9563 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9564 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9565 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9566 (plus:SI (match_dup 1) (match_dup 2)))]
9567 "TARGET_UPDATE"
9568 "@
9569 lhaux %3,%0,%2
9570 lhau %3,%2(%0)"
9571 [(set_attr "type" "load_ext_ux,load_ext_u")])
9572
9573 (define_insn "*movhi_update4"
9574 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9575 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9576 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9577 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9578 (plus:SI (match_dup 1) (match_dup 2)))]
9579 "TARGET_UPDATE"
9580 "@
9581 sthux %3,%0,%2
9582 sthu %3,%2(%0)"
9583 [(set_attr "type" "store_ux,store_u")])
9584
9585 (define_insn "*movqi_update1"
9586 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9587 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9588 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9589 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9590 (plus:SI (match_dup 1) (match_dup 2)))]
9591 "TARGET_UPDATE"
9592 "@
9593 lbzux %3,%0,%2
9594 lbzu %3,%2(%0)"
9595 [(set_attr "type" "load_ux,load_u")])
9596
9597 (define_insn "*movqi_update2"
9598 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9599 (zero_extend:SI
9600 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9601 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9602 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9603 (plus:SI (match_dup 1) (match_dup 2)))]
9604 "TARGET_UPDATE"
9605 "@
9606 lbzux %3,%0,%2
9607 lbzu %3,%2(%0)"
9608 [(set_attr "type" "load_ux,load_u")])
9609
9610 (define_insn "*movqi_update3"
9611 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9612 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9613 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9614 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9615 (plus:SI (match_dup 1) (match_dup 2)))]
9616 "TARGET_UPDATE"
9617 "@
9618 stbux %3,%0,%2
9619 stbu %3,%2(%0)"
9620 [(set_attr "type" "store_ux,store_u")])
9621
9622 (define_insn "*movsf_update1"
9623 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9624 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9625 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9626 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9627 (plus:SI (match_dup 1) (match_dup 2)))]
9628 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9629 "@
9630 lfsux %3,%0,%2
9631 lfsu %3,%2(%0)"
9632 [(set_attr "type" "fpload_ux,fpload_u")])
9633
9634 (define_insn "*movsf_update2"
9635 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9636 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9637 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9638 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9639 (plus:SI (match_dup 1) (match_dup 2)))]
9640 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9641 "@
9642 stfsux %3,%0,%2
9643 stfsu %3,%2(%0)"
9644 [(set_attr "type" "fpstore_ux,fpstore_u")])
9645
9646 (define_insn "*movsf_update3"
9647 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9648 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9649 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9650 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9651 (plus:SI (match_dup 1) (match_dup 2)))]
9652 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9653 "@
9654 {lux|lwzux} %3,%0,%2
9655 {lu|lwzu} %3,%2(%0)"
9656 [(set_attr "type" "load_ux,load_u")])
9657
9658 (define_insn "*movsf_update4"
9659 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9660 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9661 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9662 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9663 (plus:SI (match_dup 1) (match_dup 2)))]
9664 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9665 "@
9666 {stux|stwux} %3,%0,%2
9667 {stu|stwu} %3,%2(%0)"
9668 [(set_attr "type" "store_ux,store_u")])
9669
9670 (define_insn "*movdf_update1"
9671 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9672 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9673 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9674 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9675 (plus:SI (match_dup 1) (match_dup 2)))]
9676 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9677 "@
9678 lfdux %3,%0,%2
9679 lfdu %3,%2(%0)"
9680 [(set_attr "type" "fpload_ux,fpload_u")])
9681
9682 (define_insn "*movdf_update2"
9683 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9684 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9685 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9686 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9687 (plus:SI (match_dup 1) (match_dup 2)))]
9688 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9689 "@
9690 stfdux %3,%0,%2
9691 stfdu %3,%2(%0)"
9692 [(set_attr "type" "fpstore_ux,fpstore_u")])
9693
9694 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9695
9696 (define_insn "*lfq_power2"
9697 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9698 (match_operand:TF 1 "memory_operand" ""))]
9699 "TARGET_POWER2
9700 && TARGET_HARD_FLOAT && TARGET_FPRS"
9701 "lfq%U1%X1 %0,%1")
9702
9703 (define_peephole2
9704 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9705 (match_operand:DF 1 "memory_operand" ""))
9706 (set (match_operand:DF 2 "gpc_reg_operand" "")
9707 (match_operand:DF 3 "memory_operand" ""))]
9708 "TARGET_POWER2
9709 && TARGET_HARD_FLOAT && TARGET_FPRS
9710 && registers_ok_for_quad_peep (operands[0], operands[2])
9711 && mems_ok_for_quad_peep (operands[1], operands[3])"
9712 [(set (match_dup 0)
9713 (match_dup 1))]
9714 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9715 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9716
9717 (define_insn "*stfq_power2"
9718 [(set (match_operand:TF 0 "memory_operand" "")
9719 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9720 "TARGET_POWER2
9721 && TARGET_HARD_FLOAT && TARGET_FPRS"
9722 "stfq%U0%X0 %1,%0")
9723
9724
9725 (define_peephole2
9726 [(set (match_operand:DF 0 "memory_operand" "")
9727 (match_operand:DF 1 "gpc_reg_operand" ""))
9728 (set (match_operand:DF 2 "memory_operand" "")
9729 (match_operand:DF 3 "gpc_reg_operand" ""))]
9730 "TARGET_POWER2
9731 && TARGET_HARD_FLOAT && TARGET_FPRS
9732 && registers_ok_for_quad_peep (operands[1], operands[3])
9733 && mems_ok_for_quad_peep (operands[0], operands[2])"
9734 [(set (match_dup 0)
9735 (match_dup 1))]
9736 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9737 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9738 \f
9739 ;; TLS support.
9740
9741 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9742 (define_insn "tls_gd_32"
9743 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9744 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9745 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9746 UNSPEC_TLSGD))]
9747 "HAVE_AS_TLS && !TARGET_64BIT"
9748 "addi %0,%1,%2@got@tlsgd")
9749
9750 (define_insn "tls_gd_64"
9751 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9752 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9753 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9754 UNSPEC_TLSGD))]
9755 "HAVE_AS_TLS && TARGET_64BIT"
9756 "addi %0,%1,%2@got@tlsgd")
9757
9758 (define_insn "tls_ld_32"
9759 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9760 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9761 UNSPEC_TLSLD))]
9762 "HAVE_AS_TLS && !TARGET_64BIT"
9763 "addi %0,%1,%&@got@tlsld")
9764
9765 (define_insn "tls_ld_64"
9766 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9767 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9768 UNSPEC_TLSLD))]
9769 "HAVE_AS_TLS && TARGET_64BIT"
9770 "addi %0,%1,%&@got@tlsld")
9771
9772 (define_insn "tls_dtprel_32"
9773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9774 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9775 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9776 UNSPEC_TLSDTPREL))]
9777 "HAVE_AS_TLS && !TARGET_64BIT"
9778 "addi %0,%1,%2@dtprel")
9779
9780 (define_insn "tls_dtprel_64"
9781 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9782 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9783 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9784 UNSPEC_TLSDTPREL))]
9785 "HAVE_AS_TLS && TARGET_64BIT"
9786 "addi %0,%1,%2@dtprel")
9787
9788 (define_insn "tls_dtprel_ha_32"
9789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9790 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9791 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9792 UNSPEC_TLSDTPRELHA))]
9793 "HAVE_AS_TLS && !TARGET_64BIT"
9794 "addis %0,%1,%2@dtprel@ha")
9795
9796 (define_insn "tls_dtprel_ha_64"
9797 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9798 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9799 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9800 UNSPEC_TLSDTPRELHA))]
9801 "HAVE_AS_TLS && TARGET_64BIT"
9802 "addis %0,%1,%2@dtprel@ha")
9803
9804 (define_insn "tls_dtprel_lo_32"
9805 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9806 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9807 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9808 UNSPEC_TLSDTPRELLO))]
9809 "HAVE_AS_TLS && !TARGET_64BIT"
9810 "addi %0,%1,%2@dtprel@l")
9811
9812 (define_insn "tls_dtprel_lo_64"
9813 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9814 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9815 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9816 UNSPEC_TLSDTPRELLO))]
9817 "HAVE_AS_TLS && TARGET_64BIT"
9818 "addi %0,%1,%2@dtprel@l")
9819
9820 (define_insn "tls_got_dtprel_32"
9821 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9822 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9823 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9824 UNSPEC_TLSGOTDTPREL))]
9825 "HAVE_AS_TLS && !TARGET_64BIT"
9826 "lwz %0,%2@got@dtprel(%1)")
9827
9828 (define_insn "tls_got_dtprel_64"
9829 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9830 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9831 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9832 UNSPEC_TLSGOTDTPREL))]
9833 "HAVE_AS_TLS && TARGET_64BIT"
9834 "ld %0,%2@got@dtprel(%1)")
9835
9836 (define_insn "tls_tprel_32"
9837 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9838 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9839 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9840 UNSPEC_TLSTPREL))]
9841 "HAVE_AS_TLS && !TARGET_64BIT"
9842 "addi %0,%1,%2@tprel")
9843
9844 (define_insn "tls_tprel_64"
9845 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9846 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9847 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9848 UNSPEC_TLSTPREL))]
9849 "HAVE_AS_TLS && TARGET_64BIT"
9850 "addi %0,%1,%2@tprel")
9851
9852 (define_insn "tls_tprel_ha_32"
9853 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9854 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9855 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9856 UNSPEC_TLSTPRELHA))]
9857 "HAVE_AS_TLS && !TARGET_64BIT"
9858 "addis %0,%1,%2@tprel@ha")
9859
9860 (define_insn "tls_tprel_ha_64"
9861 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9862 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9863 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9864 UNSPEC_TLSTPRELHA))]
9865 "HAVE_AS_TLS && TARGET_64BIT"
9866 "addis %0,%1,%2@tprel@ha")
9867
9868 (define_insn "tls_tprel_lo_32"
9869 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9870 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9871 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9872 UNSPEC_TLSTPRELLO))]
9873 "HAVE_AS_TLS && !TARGET_64BIT"
9874 "addi %0,%1,%2@tprel@l")
9875
9876 (define_insn "tls_tprel_lo_64"
9877 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9878 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9879 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9880 UNSPEC_TLSTPRELLO))]
9881 "HAVE_AS_TLS && TARGET_64BIT"
9882 "addi %0,%1,%2@tprel@l")
9883
9884 ;; "b" output constraint here and on tls_tls input to support linker tls
9885 ;; optimization. The linker may edit the instructions emitted by a
9886 ;; tls_got_tprel/tls_tls pair to addis,addi.
9887 (define_insn "tls_got_tprel_32"
9888 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9889 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9890 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9891 UNSPEC_TLSGOTTPREL))]
9892 "HAVE_AS_TLS && !TARGET_64BIT"
9893 "lwz %0,%2@got@tprel(%1)")
9894
9895 (define_insn "tls_got_tprel_64"
9896 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9897 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9898 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9899 UNSPEC_TLSGOTTPREL))]
9900 "HAVE_AS_TLS && TARGET_64BIT"
9901 "ld %0,%2@got@tprel(%1)")
9902
9903 (define_insn "tls_tls_32"
9904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9905 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9906 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9907 UNSPEC_TLSTLS))]
9908 "HAVE_AS_TLS && !TARGET_64BIT"
9909 "add %0,%1,%2@tls")
9910
9911 (define_insn "tls_tls_64"
9912 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9913 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9914 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9915 UNSPEC_TLSTLS))]
9916 "HAVE_AS_TLS && TARGET_64BIT"
9917 "add %0,%1,%2@tls")
9918 \f
9919 ;; Next come insns related to the calling sequence.
9920 ;;
9921 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9922 ;; We move the back-chain and decrement the stack pointer.
9923
9924 (define_expand "allocate_stack"
9925 [(set (match_operand 0 "gpc_reg_operand" "=r")
9926 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9927 (set (reg 1)
9928 (minus (reg 1) (match_dup 1)))]
9929 ""
9930 "
9931 { rtx chain = gen_reg_rtx (Pmode);
9932 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9933 rtx neg_op0;
9934
9935 emit_move_insn (chain, stack_bot);
9936
9937 /* Check stack bounds if necessary. */
9938 if (current_function_limit_stack)
9939 {
9940 rtx available;
9941 available = expand_binop (Pmode, sub_optab,
9942 stack_pointer_rtx, stack_limit_rtx,
9943 NULL_RTX, 1, OPTAB_WIDEN);
9944 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9945 }
9946
9947 if (GET_CODE (operands[1]) != CONST_INT
9948 || INTVAL (operands[1]) < -32767
9949 || INTVAL (operands[1]) > 32768)
9950 {
9951 neg_op0 = gen_reg_rtx (Pmode);
9952 if (TARGET_32BIT)
9953 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9954 else
9955 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9956 }
9957 else
9958 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9959
9960 if (TARGET_UPDATE)
9961 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9962 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9963
9964 else
9965 {
9966 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9967 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9968 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9969 }
9970
9971 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9972 DONE;
9973 }")
9974
9975 ;; These patterns say how to save and restore the stack pointer. We need not
9976 ;; save the stack pointer at function level since we are careful to
9977 ;; preserve the backchain. At block level, we have to restore the backchain
9978 ;; when we restore the stack pointer.
9979 ;;
9980 ;; For nonlocal gotos, we must save both the stack pointer and its
9981 ;; backchain and restore both. Note that in the nonlocal case, the
9982 ;; save area is a memory location.
9983
9984 (define_expand "save_stack_function"
9985 [(match_operand 0 "any_operand" "")
9986 (match_operand 1 "any_operand" "")]
9987 ""
9988 "DONE;")
9989
9990 (define_expand "restore_stack_function"
9991 [(match_operand 0 "any_operand" "")
9992 (match_operand 1 "any_operand" "")]
9993 ""
9994 "DONE;")
9995
9996 (define_expand "restore_stack_block"
9997 [(use (match_operand 0 "register_operand" ""))
9998 (set (match_dup 2) (match_dup 3))
9999 (set (match_dup 0) (match_operand 1 "register_operand" ""))
10000 (set (match_dup 3) (match_dup 2))]
10001 ""
10002 "
10003 {
10004 operands[2] = gen_reg_rtx (Pmode);
10005 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
10006 }")
10007
10008 (define_expand "save_stack_nonlocal"
10009 [(match_operand 0 "memory_operand" "")
10010 (match_operand 1 "register_operand" "")]
10011 ""
10012 "
10013 {
10014 rtx temp = gen_reg_rtx (Pmode);
10015 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10016
10017 /* Copy the backchain to the first word, sp to the second. */
10018 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
10019 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
10020 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
10021 operands[1]);
10022 DONE;
10023 }")
10024
10025 (define_expand "restore_stack_nonlocal"
10026 [(match_operand 0 "register_operand" "")
10027 (match_operand 1 "memory_operand" "")]
10028 ""
10029 "
10030 {
10031 rtx temp = gen_reg_rtx (Pmode);
10032 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10033
10034 /* Restore the backchain from the first word, sp from the second. */
10035 emit_move_insn (temp,
10036 adjust_address_nv (operands[1], Pmode, 0));
10037 emit_move_insn (operands[0],
10038 adjust_address_nv (operands[1], Pmode, units_per_word));
10039 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
10040 DONE;
10041 }")
10042 \f
10043 ;; TOC register handling.
10044
10045 ;; Code to initialize the TOC register...
10046
10047 (define_insn "load_toc_aix_si"
10048 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10049 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10050 (use (reg:SI 2))])]
10051 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10052 "*
10053 {
10054 char buf[30];
10055 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10056 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10057 operands[2] = gen_rtx_REG (Pmode, 2);
10058 return \"{l|lwz} %0,%1(%2)\";
10059 }"
10060 [(set_attr "type" "load")])
10061
10062 (define_insn "load_toc_aix_di"
10063 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10064 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10065 (use (reg:DI 2))])]
10066 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10067 "*
10068 {
10069 char buf[30];
10070 #ifdef TARGET_RELOCATABLE
10071 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10072 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10073 #else
10074 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10075 #endif
10076 if (TARGET_ELF)
10077 strcat (buf, \"@toc\");
10078 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10079 operands[2] = gen_rtx_REG (Pmode, 2);
10080 return \"ld %0,%1(%2)\";
10081 }"
10082 [(set_attr "type" "load")])
10083
10084 (define_insn "load_toc_v4_pic_si"
10085 [(set (match_operand:SI 0 "register_operand" "=l")
10086 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10087 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10088 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10089 [(set_attr "type" "branch")
10090 (set_attr "length" "4")])
10091
10092 (define_insn "load_toc_v4_PIC_1"
10093 [(set (match_operand:SI 0 "register_operand" "=l")
10094 (match_operand:SI 1 "immediate_operand" "s"))
10095 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10096 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10097 "bcl 20,31,%1\\n%1:"
10098 [(set_attr "type" "branch")
10099 (set_attr "length" "4")])
10100
10101 (define_insn "load_toc_v4_PIC_1b"
10102 [(set (match_operand:SI 0 "register_operand" "=l")
10103 (match_operand:SI 1 "immediate_operand" "s"))
10104 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10105 UNSPEC_TOCPTR))]
10106 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10107 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
10108 [(set_attr "type" "branch")
10109 (set_attr "length" "8")])
10110
10111 (define_insn "load_toc_v4_PIC_2"
10112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10113 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10114 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10115 (match_operand:SI 3 "immediate_operand" "s")))))]
10116 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10117 "{l|lwz} %0,%2-%3(%1)"
10118 [(set_attr "type" "load")])
10119
10120 (define_insn "load_macho_picbase"
10121 [(set (match_operand:SI 0 "register_operand" "=l")
10122 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10123 UNSPEC_LD_MPIC))]
10124 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
10125 "bcl 20,31,%1\\n%1:"
10126 [(set_attr "type" "branch")
10127 (set_attr "length" "4")])
10128
10129 (define_insn "macho_correct_pic"
10130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10131 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10132 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10133 (match_operand:SI 3 "immediate_operand" "s")]
10134 UNSPEC_MPIC_CORRECT)))]
10135 "DEFAULT_ABI == ABI_DARWIN"
10136 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
10137 [(set_attr "length" "8")])
10138
10139 ;; If the TOC is shared over a translation unit, as happens with all
10140 ;; the kinds of PIC that we support, we need to restore the TOC
10141 ;; pointer only when jumping over units of translation.
10142 ;; On Darwin, we need to reload the picbase.
10143
10144 (define_expand "builtin_setjmp_receiver"
10145 [(use (label_ref (match_operand 0 "" "")))]
10146 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10147 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10148 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10149 "
10150 {
10151 #if TARGET_MACHO
10152 if (DEFAULT_ABI == ABI_DARWIN)
10153 {
10154 const char *picbase = machopic_function_base_name ();
10155 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10156 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10157 rtx tmplabrtx;
10158 char tmplab[20];
10159
10160 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10161 CODE_LABEL_NUMBER (operands[0]));
10162 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10163
10164 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10165 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10166 }
10167 else
10168 #endif
10169 rs6000_emit_load_toc_table (FALSE);
10170 DONE;
10171 }")
10172 \f
10173 ;; A function pointer under AIX is a pointer to a data area whose first word
10174 ;; contains the actual address of the function, whose second word contains a
10175 ;; pointer to its TOC, and whose third word contains a value to place in the
10176 ;; static chain register (r11). Note that if we load the static chain, our
10177 ;; "trampoline" need not have any executable code.
10178
10179 (define_expand "call_indirect_aix32"
10180 [(set (match_dup 2)
10181 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10182 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10183 (reg:SI 2))
10184 (set (reg:SI 2)
10185 (mem:SI (plus:SI (match_dup 0)
10186 (const_int 4))))
10187 (set (reg:SI 11)
10188 (mem:SI (plus:SI (match_dup 0)
10189 (const_int 8))))
10190 (parallel [(call (mem:SI (match_dup 2))
10191 (match_operand 1 "" ""))
10192 (use (reg:SI 2))
10193 (use (reg:SI 11))
10194 (set (reg:SI 2)
10195 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10196 (clobber (scratch:SI))])]
10197 "TARGET_32BIT"
10198 "
10199 { operands[2] = gen_reg_rtx (SImode); }")
10200
10201 (define_expand "call_indirect_aix64"
10202 [(set (match_dup 2)
10203 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10204 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10205 (reg:DI 2))
10206 (set (reg:DI 2)
10207 (mem:DI (plus:DI (match_dup 0)
10208 (const_int 8))))
10209 (set (reg:DI 11)
10210 (mem:DI (plus:DI (match_dup 0)
10211 (const_int 16))))
10212 (parallel [(call (mem:SI (match_dup 2))
10213 (match_operand 1 "" ""))
10214 (use (reg:DI 2))
10215 (use (reg:DI 11))
10216 (set (reg:DI 2)
10217 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10218 (clobber (scratch:SI))])]
10219 "TARGET_64BIT"
10220 "
10221 { operands[2] = gen_reg_rtx (DImode); }")
10222
10223 (define_expand "call_value_indirect_aix32"
10224 [(set (match_dup 3)
10225 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10226 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10227 (reg:SI 2))
10228 (set (reg:SI 2)
10229 (mem:SI (plus:SI (match_dup 1)
10230 (const_int 4))))
10231 (set (reg:SI 11)
10232 (mem:SI (plus:SI (match_dup 1)
10233 (const_int 8))))
10234 (parallel [(set (match_operand 0 "" "")
10235 (call (mem:SI (match_dup 3))
10236 (match_operand 2 "" "")))
10237 (use (reg:SI 2))
10238 (use (reg:SI 11))
10239 (set (reg:SI 2)
10240 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10241 (clobber (scratch:SI))])]
10242 "TARGET_32BIT"
10243 "
10244 { operands[3] = gen_reg_rtx (SImode); }")
10245
10246 (define_expand "call_value_indirect_aix64"
10247 [(set (match_dup 3)
10248 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10249 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10250 (reg:DI 2))
10251 (set (reg:DI 2)
10252 (mem:DI (plus:DI (match_dup 1)
10253 (const_int 8))))
10254 (set (reg:DI 11)
10255 (mem:DI (plus:DI (match_dup 1)
10256 (const_int 16))))
10257 (parallel [(set (match_operand 0 "" "")
10258 (call (mem:SI (match_dup 3))
10259 (match_operand 2 "" "")))
10260 (use (reg:DI 2))
10261 (use (reg:DI 11))
10262 (set (reg:DI 2)
10263 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10264 (clobber (scratch:SI))])]
10265 "TARGET_64BIT"
10266 "
10267 { operands[3] = gen_reg_rtx (DImode); }")
10268
10269 ;; Now the definitions for the call and call_value insns
10270 (define_expand "call"
10271 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10272 (match_operand 1 "" ""))
10273 (use (match_operand 2 "" ""))
10274 (clobber (scratch:SI))])]
10275 ""
10276 "
10277 {
10278 #if TARGET_MACHO
10279 if (MACHOPIC_INDIRECT)
10280 operands[0] = machopic_indirect_call_target (operands[0]);
10281 #endif
10282
10283 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10284 abort ();
10285
10286 operands[0] = XEXP (operands[0], 0);
10287
10288 if (GET_CODE (operands[0]) != SYMBOL_REF
10289 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10290 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10291 {
10292 if (INTVAL (operands[2]) & CALL_LONG)
10293 operands[0] = rs6000_longcall_ref (operands[0]);
10294
10295 if (DEFAULT_ABI == ABI_V4
10296 || DEFAULT_ABI == ABI_DARWIN)
10297 operands[0] = force_reg (Pmode, operands[0]);
10298
10299 else if (DEFAULT_ABI == ABI_AIX)
10300 {
10301 /* AIX function pointers are really pointers to a three word
10302 area. */
10303 emit_call_insn (TARGET_32BIT
10304 ? gen_call_indirect_aix32 (force_reg (SImode,
10305 operands[0]),
10306 operands[1])
10307 : gen_call_indirect_aix64 (force_reg (DImode,
10308 operands[0]),
10309 operands[1]));
10310 DONE;
10311 }
10312 else
10313 abort ();
10314 }
10315 }")
10316
10317 (define_expand "call_value"
10318 [(parallel [(set (match_operand 0 "" "")
10319 (call (mem:SI (match_operand 1 "address_operand" ""))
10320 (match_operand 2 "" "")))
10321 (use (match_operand 3 "" ""))
10322 (clobber (scratch:SI))])]
10323 ""
10324 "
10325 {
10326 #if TARGET_MACHO
10327 if (MACHOPIC_INDIRECT)
10328 operands[1] = machopic_indirect_call_target (operands[1]);
10329 #endif
10330
10331 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10332 abort ();
10333
10334 operands[1] = XEXP (operands[1], 0);
10335
10336 if (GET_CODE (operands[1]) != SYMBOL_REF
10337 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10338 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10339 {
10340 if (INTVAL (operands[3]) & CALL_LONG)
10341 operands[1] = rs6000_longcall_ref (operands[1]);
10342
10343 if (DEFAULT_ABI == ABI_V4
10344 || DEFAULT_ABI == ABI_DARWIN)
10345 operands[1] = force_reg (Pmode, operands[1]);
10346
10347 else if (DEFAULT_ABI == ABI_AIX)
10348 {
10349 /* AIX function pointers are really pointers to a three word
10350 area. */
10351 emit_call_insn (TARGET_32BIT
10352 ? gen_call_value_indirect_aix32 (operands[0],
10353 force_reg (SImode,
10354 operands[1]),
10355 operands[2])
10356 : gen_call_value_indirect_aix64 (operands[0],
10357 force_reg (DImode,
10358 operands[1]),
10359 operands[2]));
10360 DONE;
10361 }
10362 else
10363 abort ();
10364 }
10365 }")
10366
10367 ;; Call to function in current module. No TOC pointer reload needed.
10368 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10369 ;; either the function was not prototyped, or it was prototyped as a
10370 ;; variable argument function. It is > 0 if FP registers were passed
10371 ;; and < 0 if they were not.
10372
10373 (define_insn "*call_local32"
10374 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10375 (match_operand 1 "" "g,g"))
10376 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10377 (clobber (match_scratch:SI 3 "=l,l"))]
10378 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10379 "*
10380 {
10381 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10382 output_asm_insn (\"crxor 6,6,6\", operands);
10383
10384 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10385 output_asm_insn (\"creqv 6,6,6\", operands);
10386
10387 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10388 }"
10389 [(set_attr "type" "branch")
10390 (set_attr "length" "4,8")])
10391
10392 (define_insn "*call_local64"
10393 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10394 (match_operand 1 "" "g,g"))
10395 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10396 (clobber (match_scratch:SI 3 "=l,l"))]
10397 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10398 "*
10399 {
10400 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10401 output_asm_insn (\"crxor 6,6,6\", operands);
10402
10403 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10404 output_asm_insn (\"creqv 6,6,6\", operands);
10405
10406 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10407 }"
10408 [(set_attr "type" "branch")
10409 (set_attr "length" "4,8")])
10410
10411 (define_insn "*call_value_local32"
10412 [(set (match_operand 0 "" "")
10413 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10414 (match_operand 2 "" "g,g")))
10415 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10416 (clobber (match_scratch:SI 4 "=l,l"))]
10417 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10418 "*
10419 {
10420 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10421 output_asm_insn (\"crxor 6,6,6\", operands);
10422
10423 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10424 output_asm_insn (\"creqv 6,6,6\", operands);
10425
10426 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10427 }"
10428 [(set_attr "type" "branch")
10429 (set_attr "length" "4,8")])
10430
10431
10432 (define_insn "*call_value_local64"
10433 [(set (match_operand 0 "" "")
10434 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10435 (match_operand 2 "" "g,g")))
10436 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10437 (clobber (match_scratch:SI 4 "=l,l"))]
10438 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10439 "*
10440 {
10441 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10442 output_asm_insn (\"crxor 6,6,6\", operands);
10443
10444 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10445 output_asm_insn (\"creqv 6,6,6\", operands);
10446
10447 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10448 }"
10449 [(set_attr "type" "branch")
10450 (set_attr "length" "4,8")])
10451
10452 ;; Call to function which may be in another module. Restore the TOC
10453 ;; pointer (r2) after the call unless this is System V.
10454 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10455 ;; either the function was not prototyped, or it was prototyped as a
10456 ;; variable argument function. It is > 0 if FP registers were passed
10457 ;; and < 0 if they were not.
10458
10459 (define_insn "*call_indirect_nonlocal_aix32"
10460 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10461 (match_operand 1 "" "g"))
10462 (use (reg:SI 2))
10463 (use (reg:SI 11))
10464 (set (reg:SI 2)
10465 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10466 (clobber (match_scratch:SI 2 "=l"))]
10467 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10468 "b%T0l\;{l|lwz} 2,20(1)"
10469 [(set_attr "type" "jmpreg")
10470 (set_attr "length" "8")])
10471
10472 (define_insn "*call_nonlocal_aix32"
10473 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10474 (match_operand 1 "" "g"))
10475 (use (match_operand:SI 2 "immediate_operand" "O"))
10476 (clobber (match_scratch:SI 3 "=l"))]
10477 "TARGET_32BIT
10478 && DEFAULT_ABI == ABI_AIX
10479 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10480 "bl %z0\;%."
10481 [(set_attr "type" "branch")
10482 (set_attr "length" "8")])
10483
10484 (define_insn "*call_indirect_nonlocal_aix64"
10485 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10486 (match_operand 1 "" "g"))
10487 (use (reg:DI 2))
10488 (use (reg:DI 11))
10489 (set (reg:DI 2)
10490 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10491 (clobber (match_scratch:SI 2 "=l"))]
10492 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10493 "b%T0l\;ld 2,40(1)"
10494 [(set_attr "type" "jmpreg")
10495 (set_attr "length" "8")])
10496
10497 (define_insn "*call_nonlocal_aix64"
10498 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10499 (match_operand 1 "" "g"))
10500 (use (match_operand:SI 2 "immediate_operand" "O"))
10501 (clobber (match_scratch:SI 3 "=l"))]
10502 "TARGET_64BIT
10503 && DEFAULT_ABI == ABI_AIX
10504 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10505 "bl %z0\;%."
10506 [(set_attr "type" "branch")
10507 (set_attr "length" "8")])
10508
10509 (define_insn "*call_value_indirect_nonlocal_aix32"
10510 [(set (match_operand 0 "" "")
10511 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10512 (match_operand 2 "" "g")))
10513 (use (reg:SI 2))
10514 (use (reg:SI 11))
10515 (set (reg:SI 2)
10516 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10517 (clobber (match_scratch:SI 3 "=l"))]
10518 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10519 "b%T1l\;{l|lwz} 2,20(1)"
10520 [(set_attr "type" "jmpreg")
10521 (set_attr "length" "8")])
10522
10523 (define_insn "*call_value_nonlocal_aix32"
10524 [(set (match_operand 0 "" "")
10525 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10526 (match_operand 2 "" "g")))
10527 (use (match_operand:SI 3 "immediate_operand" "O"))
10528 (clobber (match_scratch:SI 4 "=l"))]
10529 "TARGET_32BIT
10530 && DEFAULT_ABI == ABI_AIX
10531 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10532 "bl %z1\;%."
10533 [(set_attr "type" "branch")
10534 (set_attr "length" "8")])
10535
10536 (define_insn "*call_value_indirect_nonlocal_aix64"
10537 [(set (match_operand 0 "" "")
10538 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10539 (match_operand 2 "" "g")))
10540 (use (reg:DI 2))
10541 (use (reg:DI 11))
10542 (set (reg:DI 2)
10543 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10544 (clobber (match_scratch:SI 3 "=l"))]
10545 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10546 "b%T1l\;ld 2,40(1)"
10547 [(set_attr "type" "jmpreg")
10548 (set_attr "length" "8")])
10549
10550 (define_insn "*call_value_nonlocal_aix64"
10551 [(set (match_operand 0 "" "")
10552 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10553 (match_operand 2 "" "g")))
10554 (use (match_operand:SI 3 "immediate_operand" "O"))
10555 (clobber (match_scratch:SI 4 "=l"))]
10556 "TARGET_64BIT
10557 && DEFAULT_ABI == ABI_AIX
10558 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10559 "bl %z1\;%."
10560 [(set_attr "type" "branch")
10561 (set_attr "length" "8")])
10562
10563 ;; A function pointer under System V is just a normal pointer
10564 ;; operands[0] is the function pointer
10565 ;; operands[1] is the stack size to clean up
10566 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10567 ;; which indicates how to set cr1
10568
10569 (define_insn "*call_indirect_nonlocal_sysv"
10570 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10571 (match_operand 1 "" "g,g"))
10572 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10573 (clobber (match_scratch:SI 3 "=l,l"))]
10574 "DEFAULT_ABI == ABI_V4
10575 || DEFAULT_ABI == ABI_DARWIN"
10576 {
10577 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10578 output_asm_insn ("crxor 6,6,6", operands);
10579
10580 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10581 output_asm_insn ("creqv 6,6,6", operands);
10582
10583 return "b%T0l";
10584 }
10585 [(set_attr "type" "jmpreg,jmpreg")
10586 (set_attr "length" "4,8")])
10587
10588 (define_insn "*call_nonlocal_sysv"
10589 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10590 (match_operand 1 "" "g,g"))
10591 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10592 (clobber (match_scratch:SI 3 "=l,l"))]
10593 "(DEFAULT_ABI == ABI_DARWIN
10594 || (DEFAULT_ABI == ABI_V4
10595 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10596 {
10597 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10598 output_asm_insn ("crxor 6,6,6", operands);
10599
10600 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10601 output_asm_insn ("creqv 6,6,6", operands);
10602
10603 #if TARGET_MACHO
10604 return output_call(insn, operands, 0, 2);
10605 #else
10606 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10607 #endif
10608 }
10609 [(set_attr "type" "branch,branch")
10610 (set_attr "length" "4,8")])
10611
10612 (define_insn "*call_value_indirect_nonlocal_sysv"
10613 [(set (match_operand 0 "" "")
10614 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10615 (match_operand 2 "" "g,g")))
10616 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10617 (clobber (match_scratch:SI 4 "=l,l"))]
10618 "DEFAULT_ABI == ABI_V4
10619 || DEFAULT_ABI == ABI_DARWIN"
10620 {
10621 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10622 output_asm_insn ("crxor 6,6,6", operands);
10623
10624 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10625 output_asm_insn ("creqv 6,6,6", operands);
10626
10627 return "b%T1l";
10628 }
10629 [(set_attr "type" "jmpreg,jmpreg")
10630 (set_attr "length" "4,8")])
10631
10632 (define_insn "*call_value_nonlocal_sysv"
10633 [(set (match_operand 0 "" "")
10634 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10635 (match_operand 2 "" "g,g")))
10636 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10637 (clobber (match_scratch:SI 4 "=l,l"))]
10638 "(DEFAULT_ABI == ABI_DARWIN
10639 || (DEFAULT_ABI == ABI_V4
10640 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10641 {
10642 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10643 output_asm_insn ("crxor 6,6,6", operands);
10644
10645 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10646 output_asm_insn ("creqv 6,6,6", operands);
10647
10648 #if TARGET_MACHO
10649 return output_call(insn, operands, 1, 3);
10650 #else
10651 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10652 #endif
10653 }
10654 [(set_attr "type" "branch,branch")
10655 (set_attr "length" "4,8")])
10656
10657 ;; Call subroutine returning any type.
10658 (define_expand "untyped_call"
10659 [(parallel [(call (match_operand 0 "" "")
10660 (const_int 0))
10661 (match_operand 1 "" "")
10662 (match_operand 2 "" "")])]
10663 ""
10664 "
10665 {
10666 int i;
10667
10668 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10669
10670 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10671 {
10672 rtx set = XVECEXP (operands[2], 0, i);
10673 emit_move_insn (SET_DEST (set), SET_SRC (set));
10674 }
10675
10676 /* The optimizer does not know that the call sets the function value
10677 registers we stored in the result block. We avoid problems by
10678 claiming that all hard registers are used and clobbered at this
10679 point. */
10680 emit_insn (gen_blockage ());
10681
10682 DONE;
10683 }")
10684
10685 ;; sibling call patterns
10686 (define_expand "sibcall"
10687 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10688 (match_operand 1 "" ""))
10689 (use (match_operand 2 "" ""))
10690 (use (match_operand 3 "" ""))
10691 (return)])]
10692 ""
10693 "
10694 {
10695 #if TARGET_MACHO
10696 if (MACHOPIC_INDIRECT)
10697 operands[0] = machopic_indirect_call_target (operands[0]);
10698 #endif
10699
10700 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10701 abort ();
10702
10703 operands[0] = XEXP (operands[0], 0);
10704 operands[3] = gen_reg_rtx (SImode);
10705
10706 }")
10707
10708 ;; this and similar patterns must be marked as using LR, otherwise
10709 ;; dataflow will try to delete the store into it. This is true
10710 ;; even when the actual reg to jump to is in CTR, when LR was
10711 ;; saved and restored around the PIC-setting BCL.
10712 (define_insn "*sibcall_local32"
10713 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10714 (match_operand 1 "" "g,g"))
10715 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10716 (use (match_operand:SI 3 "register_operand" "l,l"))
10717 (return)]
10718 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10719 "*
10720 {
10721 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10722 output_asm_insn (\"crxor 6,6,6\", operands);
10723
10724 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10725 output_asm_insn (\"creqv 6,6,6\", operands);
10726
10727 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10728 }"
10729 [(set_attr "type" "branch")
10730 (set_attr "length" "4,8")])
10731
10732 (define_insn "*sibcall_local64"
10733 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10734 (match_operand 1 "" "g,g"))
10735 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10736 (use (match_operand:SI 3 "register_operand" "l,l"))
10737 (return)]
10738 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10739 "*
10740 {
10741 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10742 output_asm_insn (\"crxor 6,6,6\", operands);
10743
10744 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10745 output_asm_insn (\"creqv 6,6,6\", operands);
10746
10747 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10748 }"
10749 [(set_attr "type" "branch")
10750 (set_attr "length" "4,8")])
10751
10752 (define_insn "*sibcall_value_local32"
10753 [(set (match_operand 0 "" "")
10754 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10755 (match_operand 2 "" "g,g")))
10756 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10757 (use (match_operand:SI 4 "register_operand" "l,l"))
10758 (return)]
10759 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10760 "*
10761 {
10762 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10763 output_asm_insn (\"crxor 6,6,6\", operands);
10764
10765 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10766 output_asm_insn (\"creqv 6,6,6\", operands);
10767
10768 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10769 }"
10770 [(set_attr "type" "branch")
10771 (set_attr "length" "4,8")])
10772
10773
10774 (define_insn "*sibcall_value_local64"
10775 [(set (match_operand 0 "" "")
10776 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10777 (match_operand 2 "" "g,g")))
10778 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10779 (use (match_operand:SI 4 "register_operand" "l,l"))
10780 (return)]
10781 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10782 "*
10783 {
10784 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10785 output_asm_insn (\"crxor 6,6,6\", operands);
10786
10787 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10788 output_asm_insn (\"creqv 6,6,6\", operands);
10789
10790 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10791 }"
10792 [(set_attr "type" "branch")
10793 (set_attr "length" "4,8")])
10794
10795 (define_insn "*sibcall_nonlocal_aix32"
10796 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10797 (match_operand 1 "" "g"))
10798 (use (match_operand:SI 2 "immediate_operand" "O"))
10799 (use (match_operand:SI 3 "register_operand" "l"))
10800 (return)]
10801 "TARGET_32BIT
10802 && DEFAULT_ABI == ABI_AIX
10803 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10804 "b %z0"
10805 [(set_attr "type" "branch")
10806 (set_attr "length" "4")])
10807
10808 (define_insn "*sibcall_nonlocal_aix64"
10809 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10810 (match_operand 1 "" "g"))
10811 (use (match_operand:SI 2 "immediate_operand" "O"))
10812 (use (match_operand:SI 3 "register_operand" "l"))
10813 (return)]
10814 "TARGET_64BIT
10815 && DEFAULT_ABI == ABI_AIX
10816 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10817 "b %z0"
10818 [(set_attr "type" "branch")
10819 (set_attr "length" "4")])
10820
10821 (define_insn "*sibcall_value_nonlocal_aix32"
10822 [(set (match_operand 0 "" "")
10823 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10824 (match_operand 2 "" "g")))
10825 (use (match_operand:SI 3 "immediate_operand" "O"))
10826 (use (match_operand:SI 4 "register_operand" "l"))
10827 (return)]
10828 "TARGET_32BIT
10829 && DEFAULT_ABI == ABI_AIX
10830 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10831 "b %z1"
10832 [(set_attr "type" "branch")
10833 (set_attr "length" "4")])
10834
10835 (define_insn "*sibcall_value_nonlocal_aix64"
10836 [(set (match_operand 0 "" "")
10837 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10838 (match_operand 2 "" "g")))
10839 (use (match_operand:SI 3 "immediate_operand" "O"))
10840 (use (match_operand:SI 4 "register_operand" "l"))
10841 (return)]
10842 "TARGET_64BIT
10843 && DEFAULT_ABI == ABI_AIX
10844 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10845 "b %z1"
10846 [(set_attr "type" "branch")
10847 (set_attr "length" "4")])
10848
10849 (define_insn "*sibcall_nonlocal_sysv"
10850 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10851 (match_operand 1 "" ""))
10852 (use (match_operand 2 "immediate_operand" "O,n"))
10853 (use (match_operand:SI 3 "register_operand" "l,l"))
10854 (return)]
10855 "(DEFAULT_ABI == ABI_DARWIN
10856 || DEFAULT_ABI == ABI_V4)
10857 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10858 "*
10859 {
10860 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10861 output_asm_insn (\"crxor 6,6,6\", operands);
10862
10863 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10864 output_asm_insn (\"creqv 6,6,6\", operands);
10865
10866 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10867 }"
10868 [(set_attr "type" "branch,branch")
10869 (set_attr "length" "4,8")])
10870
10871 (define_expand "sibcall_value"
10872 [(parallel [(set (match_operand 0 "register_operand" "")
10873 (call (mem:SI (match_operand 1 "address_operand" ""))
10874 (match_operand 2 "" "")))
10875 (use (match_operand 3 "" ""))
10876 (use (match_operand 4 "" ""))
10877 (return)])]
10878 ""
10879 "
10880 {
10881 #if TARGET_MACHO
10882 if (MACHOPIC_INDIRECT)
10883 operands[1] = machopic_indirect_call_target (operands[1]);
10884 #endif
10885
10886 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10887 abort ();
10888
10889 operands[1] = XEXP (operands[1], 0);
10890 operands[4] = gen_reg_rtx (SImode);
10891
10892 }")
10893
10894 (define_insn "*sibcall_value_nonlocal_sysv"
10895 [(set (match_operand 0 "" "")
10896 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10897 (match_operand 2 "" "")))
10898 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10899 (use (match_operand:SI 4 "register_operand" "l,l"))
10900 (return)]
10901 "(DEFAULT_ABI == ABI_DARWIN
10902 || DEFAULT_ABI == ABI_V4)
10903 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10904 "*
10905 {
10906 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10907 output_asm_insn (\"crxor 6,6,6\", operands);
10908
10909 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10910 output_asm_insn (\"creqv 6,6,6\", operands);
10911
10912 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10913 }"
10914 [(set_attr "type" "branch,branch")
10915 (set_attr "length" "4,8")])
10916
10917 (define_expand "sibcall_epilogue"
10918 [(use (const_int 0))]
10919 "TARGET_SCHED_PROLOG"
10920 "
10921 {
10922 rs6000_emit_epilogue (TRUE);
10923 DONE;
10924 }")
10925
10926 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10927 ;; all of memory. This blocks insns from being moved across this point.
10928
10929 (define_insn "blockage"
10930 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10931 ""
10932 "")
10933 \f
10934 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10935 ;; signed & unsigned, and one type of branch.
10936 ;;
10937 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10938 ;; insns, and branches. We store the operands of compares until we see
10939 ;; how it is used.
10940 (define_expand "cmpsi"
10941 [(set (cc0)
10942 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10943 (match_operand:SI 1 "reg_or_short_operand" "")))]
10944 ""
10945 "
10946 {
10947 /* Take care of the possibility that operands[1] might be negative but
10948 this might be a logical operation. That insn doesn't exist. */
10949 if (GET_CODE (operands[1]) == CONST_INT
10950 && INTVAL (operands[1]) < 0)
10951 operands[1] = force_reg (SImode, operands[1]);
10952
10953 rs6000_compare_op0 = operands[0];
10954 rs6000_compare_op1 = operands[1];
10955 rs6000_compare_fp_p = 0;
10956 DONE;
10957 }")
10958
10959 (define_expand "cmpdi"
10960 [(set (cc0)
10961 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10962 (match_operand:DI 1 "reg_or_short_operand" "")))]
10963 "TARGET_POWERPC64"
10964 "
10965 {
10966 /* Take care of the possibility that operands[1] might be negative but
10967 this might be a logical operation. That insn doesn't exist. */
10968 if (GET_CODE (operands[1]) == CONST_INT
10969 && INTVAL (operands[1]) < 0)
10970 operands[1] = force_reg (DImode, operands[1]);
10971
10972 rs6000_compare_op0 = operands[0];
10973 rs6000_compare_op1 = operands[1];
10974 rs6000_compare_fp_p = 0;
10975 DONE;
10976 }")
10977
10978 (define_expand "cmpsf"
10979 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10980 (match_operand:SF 1 "gpc_reg_operand" "")))]
10981 "TARGET_HARD_FLOAT"
10982 "
10983 {
10984 rs6000_compare_op0 = operands[0];
10985 rs6000_compare_op1 = operands[1];
10986 rs6000_compare_fp_p = 1;
10987 DONE;
10988 }")
10989
10990 (define_expand "cmpdf"
10991 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10992 (match_operand:DF 1 "gpc_reg_operand" "")))]
10993 "TARGET_HARD_FLOAT && TARGET_FPRS"
10994 "
10995 {
10996 rs6000_compare_op0 = operands[0];
10997 rs6000_compare_op1 = operands[1];
10998 rs6000_compare_fp_p = 1;
10999 DONE;
11000 }")
11001
11002 (define_expand "cmptf"
11003 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
11004 (match_operand:TF 1 "gpc_reg_operand" "")))]
11005 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11006 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11007 "
11008 {
11009 rs6000_compare_op0 = operands[0];
11010 rs6000_compare_op1 = operands[1];
11011 rs6000_compare_fp_p = 1;
11012 DONE;
11013 }")
11014
11015 (define_expand "beq"
11016 [(use (match_operand 0 "" ""))]
11017 ""
11018 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11019
11020 (define_expand "bne"
11021 [(use (match_operand 0 "" ""))]
11022 ""
11023 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11024
11025 (define_expand "bge"
11026 [(use (match_operand 0 "" ""))]
11027 ""
11028 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11029
11030 (define_expand "bgt"
11031 [(use (match_operand 0 "" ""))]
11032 ""
11033 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11034
11035 (define_expand "ble"
11036 [(use (match_operand 0 "" ""))]
11037 ""
11038 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11039
11040 (define_expand "blt"
11041 [(use (match_operand 0 "" ""))]
11042 ""
11043 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11044
11045 (define_expand "bgeu"
11046 [(use (match_operand 0 "" ""))]
11047 ""
11048 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11049
11050 (define_expand "bgtu"
11051 [(use (match_operand 0 "" ""))]
11052 ""
11053 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11054
11055 (define_expand "bleu"
11056 [(use (match_operand 0 "" ""))]
11057 ""
11058 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11059
11060 (define_expand "bltu"
11061 [(use (match_operand 0 "" ""))]
11062 ""
11063 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11064
11065 (define_expand "bunordered"
11066 [(use (match_operand 0 "" ""))]
11067 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11068 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11069
11070 (define_expand "bordered"
11071 [(use (match_operand 0 "" ""))]
11072 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11073 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11074
11075 (define_expand "buneq"
11076 [(use (match_operand 0 "" ""))]
11077 ""
11078 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11079
11080 (define_expand "bunge"
11081 [(use (match_operand 0 "" ""))]
11082 ""
11083 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11084
11085 (define_expand "bungt"
11086 [(use (match_operand 0 "" ""))]
11087 ""
11088 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11089
11090 (define_expand "bunle"
11091 [(use (match_operand 0 "" ""))]
11092 ""
11093 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11094
11095 (define_expand "bunlt"
11096 [(use (match_operand 0 "" ""))]
11097 ""
11098 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11099
11100 (define_expand "bltgt"
11101 [(use (match_operand 0 "" ""))]
11102 ""
11103 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11104
11105 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11106 ;; For SEQ, likewise, except that comparisons with zero should be done
11107 ;; with an scc insns. However, due to the order that combine see the
11108 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11109 ;; the cases we don't want to handle.
11110 (define_expand "seq"
11111 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11112 ""
11113 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11114
11115 (define_expand "sne"
11116 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11117 ""
11118 "
11119 {
11120 if (! rs6000_compare_fp_p)
11121 FAIL;
11122
11123 rs6000_emit_sCOND (NE, operands[0]);
11124 DONE;
11125 }")
11126
11127 ;; A >= 0 is best done the portable way for A an integer.
11128 (define_expand "sge"
11129 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11130 ""
11131 "
11132 {
11133 if (! rs6000_compare_fp_p
11134 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11135 FAIL;
11136
11137 rs6000_emit_sCOND (GE, operands[0]);
11138 DONE;
11139 }")
11140
11141 ;; A > 0 is best done using the portable sequence, so fail in that case.
11142 (define_expand "sgt"
11143 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11144 ""
11145 "
11146 {
11147 if (! rs6000_compare_fp_p
11148 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11149 FAIL;
11150
11151 rs6000_emit_sCOND (GT, operands[0]);
11152 DONE;
11153 }")
11154
11155 ;; A <= 0 is best done the portable way for A an integer.
11156 (define_expand "sle"
11157 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11158 ""
11159 "
11160 {
11161 if (! rs6000_compare_fp_p
11162 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11163 FAIL;
11164
11165 rs6000_emit_sCOND (LE, operands[0]);
11166 DONE;
11167 }")
11168
11169 ;; A < 0 is best done in the portable way for A an integer.
11170 (define_expand "slt"
11171 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11172 ""
11173 "
11174 {
11175 if (! rs6000_compare_fp_p
11176 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11177 FAIL;
11178
11179 rs6000_emit_sCOND (LT, operands[0]);
11180 DONE;
11181 }")
11182
11183 (define_expand "sgeu"
11184 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11185 ""
11186 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11187
11188 (define_expand "sgtu"
11189 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11190 ""
11191 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11192
11193 (define_expand "sleu"
11194 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11195 ""
11196 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11197
11198 (define_expand "sltu"
11199 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11200 ""
11201 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11202
11203 (define_expand "sunordered"
11204 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11205 ""
11206 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11207
11208 (define_expand "sordered"
11209 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11210 ""
11211 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11212
11213 (define_expand "suneq"
11214 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11215 ""
11216 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11217
11218 (define_expand "sunge"
11219 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11220 ""
11221 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11222
11223 (define_expand "sungt"
11224 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11225 ""
11226 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11227
11228 (define_expand "sunle"
11229 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11230 ""
11231 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11232
11233 (define_expand "sunlt"
11234 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11235 ""
11236 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11237
11238 (define_expand "sltgt"
11239 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11240 ""
11241 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11242
11243 \f
11244 ;; Here are the actual compare insns.
11245 (define_insn "*cmpsi_internal1"
11246 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11247 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11248 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11249 ""
11250 "{cmp%I2|cmpw%I2} %0,%1,%2"
11251 [(set_attr "type" "cmp")])
11252
11253 (define_insn "*cmpdi_internal1"
11254 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11255 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11256 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11257 "TARGET_POWERPC64"
11258 "cmpd%I2 %0,%1,%2"
11259 [(set_attr "type" "cmp")])
11260
11261 ;; If we are comparing a register for equality with a large constant,
11262 ;; we can do this with an XOR followed by a compare. But we need a scratch
11263 ;; register for the result of the XOR.
11264
11265 (define_split
11266 [(set (match_operand:CC 0 "cc_reg_operand" "")
11267 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11268 (match_operand:SI 2 "non_short_cint_operand" "")))
11269 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11270 "find_single_use (operands[0], insn, 0)
11271 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11272 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11273 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11274 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11275 "
11276 {
11277 /* Get the constant we are comparing against, C, and see what it looks like
11278 sign-extended to 16 bits. Then see what constant could be XOR'ed
11279 with C to get the sign-extended value. */
11280
11281 HOST_WIDE_INT c = INTVAL (operands[2]);
11282 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11283 HOST_WIDE_INT xorv = c ^ sextc;
11284
11285 operands[4] = GEN_INT (xorv);
11286 operands[5] = GEN_INT (sextc);
11287 }")
11288
11289 (define_insn "*cmpsi_internal2"
11290 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11291 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11292 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11293 ""
11294 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11295 [(set_attr "type" "cmp")])
11296
11297 (define_insn "*cmpdi_internal2"
11298 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11299 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11300 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11301 ""
11302 "cmpld%I2 %0,%1,%b2"
11303 [(set_attr "type" "cmp")])
11304
11305 ;; The following two insns don't exist as single insns, but if we provide
11306 ;; them, we can swap an add and compare, which will enable us to overlap more
11307 ;; of the required delay between a compare and branch. We generate code for
11308 ;; them by splitting.
11309
11310 (define_insn ""
11311 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11312 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11313 (match_operand:SI 2 "short_cint_operand" "i")))
11314 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11315 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11316 ""
11317 "#"
11318 [(set_attr "length" "8")])
11319
11320 (define_insn ""
11321 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11322 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11323 (match_operand:SI 2 "u_short_cint_operand" "i")))
11324 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11325 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11326 ""
11327 "#"
11328 [(set_attr "length" "8")])
11329
11330 (define_split
11331 [(set (match_operand:CC 3 "cc_reg_operand" "")
11332 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11333 (match_operand:SI 2 "short_cint_operand" "")))
11334 (set (match_operand:SI 0 "gpc_reg_operand" "")
11335 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11336 ""
11337 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11338 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11339
11340 (define_split
11341 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11342 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11343 (match_operand:SI 2 "u_short_cint_operand" "")))
11344 (set (match_operand:SI 0 "gpc_reg_operand" "")
11345 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11346 ""
11347 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11348 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11349
11350 (define_insn "*cmpsf_internal1"
11351 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11352 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11353 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11354 "TARGET_HARD_FLOAT && TARGET_FPRS"
11355 "fcmpu %0,%1,%2"
11356 [(set_attr "type" "fpcompare")])
11357
11358 (define_insn "*cmpdf_internal1"
11359 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11360 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11361 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11362 "TARGET_HARD_FLOAT && TARGET_FPRS"
11363 "fcmpu %0,%1,%2"
11364 [(set_attr "type" "fpcompare")])
11365
11366 ;; Only need to compare second words if first words equal
11367 (define_insn "*cmptf_internal1"
11368 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11369 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11370 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11371 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11372 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11373 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11374 [(set_attr "type" "fpcompare")
11375 (set_attr "length" "12")])
11376 \f
11377 ;; Now we have the scc insns. We can do some combinations because of the
11378 ;; way the machine works.
11379 ;;
11380 ;; Note that this is probably faster if we can put an insn between the
11381 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11382 ;; cases the insns below which don't use an intermediate CR field will
11383 ;; be used instead.
11384 (define_insn ""
11385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11386 (match_operator:SI 1 "scc_comparison_operator"
11387 [(match_operand 2 "cc_reg_operand" "y")
11388 (const_int 0)]))]
11389 ""
11390 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11391 [(set (attr "type")
11392 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11393 (const_string "mfcrf")
11394 ]
11395 (const_string "mfcr")))
11396 (set_attr "length" "12")])
11397
11398 ;; Same as above, but get the GT bit.
11399 (define_insn "move_from_CR_gt_bit"
11400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11401 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11402 "TARGET_E500"
11403 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
11404 [(set_attr "type" "mfcr")
11405 (set_attr "length" "12")])
11406
11407 ;; Same as above, but get the OV/ORDERED bit.
11408 (define_insn "move_from_CR_ov_bit"
11409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11410 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11411 "TARGET_ISEL"
11412 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11413 [(set_attr "type" "mfcr")
11414 (set_attr "length" "12")])
11415
11416 (define_insn ""
11417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11418 (match_operator:DI 1 "scc_comparison_operator"
11419 [(match_operand 2 "cc_reg_operand" "y")
11420 (const_int 0)]))]
11421 "TARGET_POWERPC64"
11422 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11423 [(set (attr "type")
11424 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11425 (const_string "mfcrf")
11426 ]
11427 (const_string "mfcr")))
11428 (set_attr "length" "12")])
11429
11430 (define_insn ""
11431 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11432 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11433 [(match_operand 2 "cc_reg_operand" "y,y")
11434 (const_int 0)])
11435 (const_int 0)))
11436 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11437 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11438 "TARGET_32BIT"
11439 "@
11440 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11441 #"
11442 [(set_attr "type" "delayed_compare")
11443 (set_attr "length" "12,16")])
11444
11445 (define_split
11446 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11447 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11448 [(match_operand 2 "cc_reg_operand" "")
11449 (const_int 0)])
11450 (const_int 0)))
11451 (set (match_operand:SI 3 "gpc_reg_operand" "")
11452 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11453 "TARGET_32BIT && reload_completed"
11454 [(set (match_dup 3)
11455 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11456 (set (match_dup 0)
11457 (compare:CC (match_dup 3)
11458 (const_int 0)))]
11459 "")
11460
11461 (define_insn ""
11462 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11463 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11464 [(match_operand 2 "cc_reg_operand" "y")
11465 (const_int 0)])
11466 (match_operand:SI 3 "const_int_operand" "n")))]
11467 ""
11468 "*
11469 {
11470 int is_bit = ccr_bit (operands[1], 1);
11471 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11472 int count;
11473
11474 if (is_bit >= put_bit)
11475 count = is_bit - put_bit;
11476 else
11477 count = 32 - (put_bit - is_bit);
11478
11479 operands[4] = GEN_INT (count);
11480 operands[5] = GEN_INT (put_bit);
11481
11482 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11483 }"
11484 [(set (attr "type")
11485 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11486 (const_string "mfcrf")
11487 ]
11488 (const_string "mfcr")))
11489 (set_attr "length" "12")])
11490
11491 (define_insn ""
11492 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11493 (compare:CC
11494 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11495 [(match_operand 2 "cc_reg_operand" "y,y")
11496 (const_int 0)])
11497 (match_operand:SI 3 "const_int_operand" "n,n"))
11498 (const_int 0)))
11499 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11500 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11501 (match_dup 3)))]
11502 ""
11503 "*
11504 {
11505 int is_bit = ccr_bit (operands[1], 1);
11506 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11507 int count;
11508
11509 /* Force split for non-cc0 compare. */
11510 if (which_alternative == 1)
11511 return \"#\";
11512
11513 if (is_bit >= put_bit)
11514 count = is_bit - put_bit;
11515 else
11516 count = 32 - (put_bit - is_bit);
11517
11518 operands[5] = GEN_INT (count);
11519 operands[6] = GEN_INT (put_bit);
11520
11521 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11522 }"
11523 [(set_attr "type" "delayed_compare")
11524 (set_attr "length" "12,16")])
11525
11526 (define_split
11527 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11528 (compare:CC
11529 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11530 [(match_operand 2 "cc_reg_operand" "")
11531 (const_int 0)])
11532 (match_operand:SI 3 "const_int_operand" ""))
11533 (const_int 0)))
11534 (set (match_operand:SI 4 "gpc_reg_operand" "")
11535 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11536 (match_dup 3)))]
11537 "reload_completed"
11538 [(set (match_dup 4)
11539 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11540 (match_dup 3)))
11541 (set (match_dup 0)
11542 (compare:CC (match_dup 4)
11543 (const_int 0)))]
11544 "")
11545
11546 ;; There is a 3 cycle delay between consecutive mfcr instructions
11547 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11548
11549 (define_peephole
11550 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11551 (match_operator:SI 1 "scc_comparison_operator"
11552 [(match_operand 2 "cc_reg_operand" "y")
11553 (const_int 0)]))
11554 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11555 (match_operator:SI 4 "scc_comparison_operator"
11556 [(match_operand 5 "cc_reg_operand" "y")
11557 (const_int 0)]))]
11558 "REGNO (operands[2]) != REGNO (operands[5])"
11559 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11560 [(set_attr "type" "mfcr")
11561 (set_attr "length" "20")])
11562
11563 (define_peephole
11564 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11565 (match_operator:DI 1 "scc_comparison_operator"
11566 [(match_operand 2 "cc_reg_operand" "y")
11567 (const_int 0)]))
11568 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11569 (match_operator:DI 4 "scc_comparison_operator"
11570 [(match_operand 5 "cc_reg_operand" "y")
11571 (const_int 0)]))]
11572 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11573 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11574 [(set_attr "type" "mfcr")
11575 (set_attr "length" "20")])
11576
11577 ;; There are some scc insns that can be done directly, without a compare.
11578 ;; These are faster because they don't involve the communications between
11579 ;; the FXU and branch units. In fact, we will be replacing all of the
11580 ;; integer scc insns here or in the portable methods in emit_store_flag.
11581 ;;
11582 ;; Also support (neg (scc ..)) since that construct is used to replace
11583 ;; branches, (plus (scc ..) ..) since that construct is common and
11584 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11585 ;; cases where it is no more expensive than (neg (scc ..)).
11586
11587 ;; Have reload force a constant into a register for the simple insns that
11588 ;; otherwise won't accept constants. We do this because it is faster than
11589 ;; the cmp/mfcr sequence we would otherwise generate.
11590
11591 (define_insn ""
11592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11593 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11594 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11595 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11596 "TARGET_32BIT"
11597 "@
11598 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11599 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11600 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11601 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11602 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11603 [(set_attr "length" "12,8,12,12,12")])
11604
11605 (define_insn ""
11606 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11607 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11608 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11609 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11610 "TARGET_64BIT"
11611 "@
11612 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11613 subfic %3,%1,0\;adde %0,%3,%1
11614 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11615 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11616 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11617 [(set_attr "length" "12,8,12,12,12")])
11618
11619 (define_insn ""
11620 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11621 (compare:CC
11622 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11623 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11624 (const_int 0)))
11625 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11626 (eq:SI (match_dup 1) (match_dup 2)))
11627 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11628 "TARGET_32BIT"
11629 "@
11630 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11631 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11632 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11633 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11634 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11635 #
11636 #
11637 #
11638 #
11639 #"
11640 [(set_attr "type" "compare")
11641 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11642
11643 (define_split
11644 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11645 (compare:CC
11646 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11647 (match_operand:SI 2 "reg_or_cint_operand" ""))
11648 (const_int 0)))
11649 (set (match_operand:SI 0 "gpc_reg_operand" "")
11650 (eq:SI (match_dup 1) (match_dup 2)))
11651 (clobber (match_scratch:SI 3 ""))]
11652 "TARGET_32BIT && reload_completed"
11653 [(parallel [(set (match_dup 0)
11654 (eq:SI (match_dup 1) (match_dup 2)))
11655 (clobber (match_dup 3))])
11656 (set (match_dup 4)
11657 (compare:CC (match_dup 0)
11658 (const_int 0)))]
11659 "")
11660
11661 (define_insn ""
11662 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11663 (compare:CC
11664 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11665 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11666 (const_int 0)))
11667 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11668 (eq:DI (match_dup 1) (match_dup 2)))
11669 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11670 "TARGET_64BIT"
11671 "@
11672 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11673 subfic %3,%1,0\;adde. %0,%3,%1
11674 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11675 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11676 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11677 #
11678 #
11679 #
11680 #
11681 #"
11682 [(set_attr "type" "compare")
11683 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11684
11685 (define_split
11686 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11687 (compare:CC
11688 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11689 (match_operand:DI 2 "reg_or_cint_operand" ""))
11690 (const_int 0)))
11691 (set (match_operand:DI 0 "gpc_reg_operand" "")
11692 (eq:DI (match_dup 1) (match_dup 2)))
11693 (clobber (match_scratch:DI 3 ""))]
11694 "TARGET_64BIT && reload_completed"
11695 [(parallel [(set (match_dup 0)
11696 (eq:DI (match_dup 1) (match_dup 2)))
11697 (clobber (match_dup 3))])
11698 (set (match_dup 4)
11699 (compare:CC (match_dup 0)
11700 (const_int 0)))]
11701 "")
11702
11703 ;; We have insns of the form shown by the first define_insn below. If
11704 ;; there is something inside the comparison operation, we must split it.
11705 (define_split
11706 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11707 (plus:SI (match_operator 1 "comparison_operator"
11708 [(match_operand:SI 2 "" "")
11709 (match_operand:SI 3
11710 "reg_or_cint_operand" "")])
11711 (match_operand:SI 4 "gpc_reg_operand" "")))
11712 (clobber (match_operand:SI 5 "register_operand" ""))]
11713 "! gpc_reg_operand (operands[2], SImode)"
11714 [(set (match_dup 5) (match_dup 2))
11715 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11716 (match_dup 4)))])
11717
11718 (define_insn ""
11719 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11720 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11721 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11722 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11723 "TARGET_32BIT"
11724 "@
11725 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11726 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11727 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11728 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11729 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11730 [(set_attr "length" "12,8,12,12,12")])
11731
11732 (define_insn ""
11733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11734 (compare:CC
11735 (plus:SI
11736 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11737 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11738 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11739 (const_int 0)))
11740 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11741 "TARGET_32BIT"
11742 "@
11743 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11744 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11745 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11746 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11747 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11748 #
11749 #
11750 #
11751 #
11752 #"
11753 [(set_attr "type" "compare")
11754 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11755
11756 (define_split
11757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11758 (compare:CC
11759 (plus:SI
11760 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11761 (match_operand:SI 2 "reg_or_cint_operand" ""))
11762 (match_operand:SI 3 "gpc_reg_operand" ""))
11763 (const_int 0)))
11764 (clobber (match_scratch:SI 4 ""))]
11765 "TARGET_32BIT && reload_completed"
11766 [(set (match_dup 4)
11767 (plus:SI (eq:SI (match_dup 1)
11768 (match_dup 2))
11769 (match_dup 3)))
11770 (set (match_dup 0)
11771 (compare:CC (match_dup 4)
11772 (const_int 0)))]
11773 "")
11774
11775 (define_insn ""
11776 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11777 (compare:CC
11778 (plus:SI
11779 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11780 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11781 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11782 (const_int 0)))
11783 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11784 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11785 "TARGET_32BIT"
11786 "@
11787 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11788 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11789 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11790 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11791 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11792 #
11793 #
11794 #
11795 #
11796 #"
11797 [(set_attr "type" "compare")
11798 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11799
11800 (define_split
11801 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11802 (compare:CC
11803 (plus:SI
11804 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11805 (match_operand:SI 2 "reg_or_cint_operand" ""))
11806 (match_operand:SI 3 "gpc_reg_operand" ""))
11807 (const_int 0)))
11808 (set (match_operand:SI 0 "gpc_reg_operand" "")
11809 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11810 "TARGET_32BIT && reload_completed"
11811 [(set (match_dup 0)
11812 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11813 (set (match_dup 4)
11814 (compare:CC (match_dup 0)
11815 (const_int 0)))]
11816 "")
11817
11818 (define_insn ""
11819 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11820 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11821 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11822 "TARGET_32BIT"
11823 "@
11824 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11825 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11826 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11827 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11828 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11829 [(set_attr "length" "12,8,12,12,12")])
11830
11831 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11832 ;; since it nabs/sr is just as fast.
11833 (define_insn "*ne0"
11834 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11835 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11836 (const_int 31)))
11837 (clobber (match_scratch:SI 2 "=&r"))]
11838 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11839 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11840 [(set_attr "length" "8")])
11841
11842 (define_insn ""
11843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11844 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11845 (const_int 63)))
11846 (clobber (match_scratch:DI 2 "=&r"))]
11847 "TARGET_64BIT"
11848 "addic %2,%1,-1\;subfe %0,%2,%1"
11849 [(set_attr "length" "8")])
11850
11851 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11852 (define_insn ""
11853 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11854 (plus:SI (lshiftrt:SI
11855 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11856 (const_int 31))
11857 (match_operand:SI 2 "gpc_reg_operand" "r")))
11858 (clobber (match_scratch:SI 3 "=&r"))]
11859 "TARGET_32BIT"
11860 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11861 [(set_attr "length" "8")])
11862
11863 (define_insn ""
11864 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11865 (plus:DI (lshiftrt:DI
11866 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11867 (const_int 63))
11868 (match_operand:DI 2 "gpc_reg_operand" "r")))
11869 (clobber (match_scratch:DI 3 "=&r"))]
11870 "TARGET_64BIT"
11871 "addic %3,%1,-1\;addze %0,%2"
11872 [(set_attr "length" "8")])
11873
11874 (define_insn ""
11875 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11876 (compare:CC
11877 (plus:SI (lshiftrt:SI
11878 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11879 (const_int 31))
11880 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11881 (const_int 0)))
11882 (clobber (match_scratch:SI 3 "=&r,&r"))
11883 (clobber (match_scratch:SI 4 "=X,&r"))]
11884 "TARGET_32BIT"
11885 "@
11886 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11887 #"
11888 [(set_attr "type" "compare")
11889 (set_attr "length" "8,12")])
11890
11891 (define_split
11892 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11893 (compare:CC
11894 (plus:SI (lshiftrt:SI
11895 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11896 (const_int 31))
11897 (match_operand:SI 2 "gpc_reg_operand" ""))
11898 (const_int 0)))
11899 (clobber (match_scratch:SI 3 ""))
11900 (clobber (match_scratch:SI 4 ""))]
11901 "TARGET_32BIT && reload_completed"
11902 [(parallel [(set (match_dup 3)
11903 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11904 (const_int 31))
11905 (match_dup 2)))
11906 (clobber (match_dup 4))])
11907 (set (match_dup 0)
11908 (compare:CC (match_dup 3)
11909 (const_int 0)))]
11910 "")
11911
11912 (define_insn ""
11913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11914 (compare:CC
11915 (plus:DI (lshiftrt:DI
11916 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11917 (const_int 63))
11918 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11919 (const_int 0)))
11920 (clobber (match_scratch:DI 3 "=&r,&r"))]
11921 "TARGET_64BIT"
11922 "@
11923 addic %3,%1,-1\;addze. %3,%2
11924 #"
11925 [(set_attr "type" "compare")
11926 (set_attr "length" "8,12")])
11927
11928 (define_split
11929 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11930 (compare:CC
11931 (plus:DI (lshiftrt:DI
11932 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11933 (const_int 63))
11934 (match_operand:DI 2 "gpc_reg_operand" ""))
11935 (const_int 0)))
11936 (clobber (match_scratch:DI 3 ""))]
11937 "TARGET_64BIT && reload_completed"
11938 [(set (match_dup 3)
11939 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11940 (const_int 63))
11941 (match_dup 2)))
11942 (set (match_dup 0)
11943 (compare:CC (match_dup 3)
11944 (const_int 0)))]
11945 "")
11946
11947 (define_insn ""
11948 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11949 (compare:CC
11950 (plus:SI (lshiftrt:SI
11951 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11952 (const_int 31))
11953 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11954 (const_int 0)))
11955 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11956 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11957 (match_dup 2)))
11958 (clobber (match_scratch:SI 3 "=&r,&r"))]
11959 "TARGET_32BIT"
11960 "@
11961 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11962 #"
11963 [(set_attr "type" "compare")
11964 (set_attr "length" "8,12")])
11965
11966 (define_split
11967 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11968 (compare:CC
11969 (plus:SI (lshiftrt:SI
11970 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11971 (const_int 31))
11972 (match_operand:SI 2 "gpc_reg_operand" ""))
11973 (const_int 0)))
11974 (set (match_operand:SI 0 "gpc_reg_operand" "")
11975 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11976 (match_dup 2)))
11977 (clobber (match_scratch:SI 3 ""))]
11978 "TARGET_32BIT && reload_completed"
11979 [(parallel [(set (match_dup 0)
11980 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11981 (match_dup 2)))
11982 (clobber (match_dup 3))])
11983 (set (match_dup 4)
11984 (compare:CC (match_dup 0)
11985 (const_int 0)))]
11986 "")
11987
11988 (define_insn ""
11989 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11990 (compare:CC
11991 (plus:DI (lshiftrt:DI
11992 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11993 (const_int 63))
11994 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11995 (const_int 0)))
11996 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11997 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11998 (match_dup 2)))
11999 (clobber (match_scratch:DI 3 "=&r,&r"))]
12000 "TARGET_64BIT"
12001 "@
12002 addic %3,%1,-1\;addze. %0,%2
12003 #"
12004 [(set_attr "type" "compare")
12005 (set_attr "length" "8,12")])
12006
12007 (define_split
12008 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12009 (compare:CC
12010 (plus:DI (lshiftrt:DI
12011 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12012 (const_int 63))
12013 (match_operand:DI 2 "gpc_reg_operand" ""))
12014 (const_int 0)))
12015 (set (match_operand:DI 0 "gpc_reg_operand" "")
12016 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12017 (match_dup 2)))
12018 (clobber (match_scratch:DI 3 ""))]
12019 "TARGET_64BIT && reload_completed"
12020 [(parallel [(set (match_dup 0)
12021 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12022 (match_dup 2)))
12023 (clobber (match_dup 3))])
12024 (set (match_dup 4)
12025 (compare:CC (match_dup 0)
12026 (const_int 0)))]
12027 "")
12028
12029 (define_insn ""
12030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12031 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12032 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12033 (clobber (match_scratch:SI 3 "=r,X"))]
12034 "TARGET_POWER"
12035 "@
12036 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12037 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12038 [(set_attr "length" "12")])
12039
12040 (define_insn ""
12041 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12042 (compare:CC
12043 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12044 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12045 (const_int 0)))
12046 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12047 (le:SI (match_dup 1) (match_dup 2)))
12048 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12049 "TARGET_POWER"
12050 "@
12051 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12052 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12053 #
12054 #"
12055 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12056 (set_attr "length" "12,12,16,16")])
12057
12058 (define_split
12059 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12060 (compare:CC
12061 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12062 (match_operand:SI 2 "reg_or_short_operand" ""))
12063 (const_int 0)))
12064 (set (match_operand:SI 0 "gpc_reg_operand" "")
12065 (le:SI (match_dup 1) (match_dup 2)))
12066 (clobber (match_scratch:SI 3 ""))]
12067 "TARGET_POWER && reload_completed"
12068 [(parallel [(set (match_dup 0)
12069 (le:SI (match_dup 1) (match_dup 2)))
12070 (clobber (match_dup 3))])
12071 (set (match_dup 4)
12072 (compare:CC (match_dup 0)
12073 (const_int 0)))]
12074 "")
12075
12076 (define_insn ""
12077 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12078 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12079 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12080 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12081 "TARGET_POWER"
12082 "@
12083 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12084 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12085 [(set_attr "length" "12")])
12086
12087 (define_insn ""
12088 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12089 (compare:CC
12090 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12091 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12092 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12093 (const_int 0)))
12094 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12095 "TARGET_POWER"
12096 "@
12097 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12098 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12099 #
12100 #"
12101 [(set_attr "type" "compare")
12102 (set_attr "length" "12,12,16,16")])
12103
12104 (define_split
12105 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12106 (compare:CC
12107 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12108 (match_operand:SI 2 "reg_or_short_operand" ""))
12109 (match_operand:SI 3 "gpc_reg_operand" ""))
12110 (const_int 0)))
12111 (clobber (match_scratch:SI 4 ""))]
12112 "TARGET_POWER && reload_completed"
12113 [(set (match_dup 4)
12114 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12115 (match_dup 3)))
12116 (set (match_dup 0)
12117 (compare:CC (match_dup 4)
12118 (const_int 0)))]
12119 "")
12120
12121 (define_insn ""
12122 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12123 (compare:CC
12124 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12125 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12126 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12127 (const_int 0)))
12128 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12129 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12130 "TARGET_POWER"
12131 "@
12132 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12133 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12134 #
12135 #"
12136 [(set_attr "type" "compare")
12137 (set_attr "length" "12,12,16,16")])
12138
12139 (define_split
12140 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12141 (compare:CC
12142 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12143 (match_operand:SI 2 "reg_or_short_operand" ""))
12144 (match_operand:SI 3 "gpc_reg_operand" ""))
12145 (const_int 0)))
12146 (set (match_operand:SI 0 "gpc_reg_operand" "")
12147 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12148 "TARGET_POWER && reload_completed"
12149 [(set (match_dup 0)
12150 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12151 (set (match_dup 4)
12152 (compare:CC (match_dup 0)
12153 (const_int 0)))]
12154 "")
12155
12156 (define_insn ""
12157 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12158 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12159 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12160 "TARGET_POWER"
12161 "@
12162 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12163 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12164 [(set_attr "length" "12")])
12165
12166 (define_insn ""
12167 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12168 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12169 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12170 "TARGET_32BIT"
12171 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12172 [(set_attr "length" "12")])
12173
12174 (define_insn ""
12175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12176 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12177 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12178 "TARGET_64BIT"
12179 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12180 [(set_attr "length" "12")])
12181
12182 (define_insn ""
12183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12184 (compare:CC
12185 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12186 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12187 (const_int 0)))
12188 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12189 (leu:DI (match_dup 1) (match_dup 2)))]
12190 "TARGET_64BIT"
12191 "@
12192 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12193 #"
12194 [(set_attr "type" "compare")
12195 (set_attr "length" "12,16")])
12196
12197 (define_split
12198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12199 (compare:CC
12200 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12201 (match_operand:DI 2 "reg_or_short_operand" ""))
12202 (const_int 0)))
12203 (set (match_operand:DI 0 "gpc_reg_operand" "")
12204 (leu:DI (match_dup 1) (match_dup 2)))]
12205 "TARGET_64BIT && reload_completed"
12206 [(set (match_dup 0)
12207 (leu:DI (match_dup 1) (match_dup 2)))
12208 (set (match_dup 3)
12209 (compare:CC (match_dup 0)
12210 (const_int 0)))]
12211 "")
12212
12213 (define_insn ""
12214 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12215 (compare:CC
12216 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12217 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12218 (const_int 0)))
12219 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12220 (leu:SI (match_dup 1) (match_dup 2)))]
12221 "TARGET_32BIT"
12222 "@
12223 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12224 #"
12225 [(set_attr "type" "compare")
12226 (set_attr "length" "12,16")])
12227
12228 (define_split
12229 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12230 (compare:CC
12231 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12232 (match_operand:SI 2 "reg_or_short_operand" ""))
12233 (const_int 0)))
12234 (set (match_operand:SI 0 "gpc_reg_operand" "")
12235 (leu:SI (match_dup 1) (match_dup 2)))]
12236 "TARGET_32BIT && reload_completed"
12237 [(set (match_dup 0)
12238 (leu:SI (match_dup 1) (match_dup 2)))
12239 (set (match_dup 3)
12240 (compare:CC (match_dup 0)
12241 (const_int 0)))]
12242 "")
12243
12244 (define_insn ""
12245 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12246 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12247 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12248 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12249 "TARGET_32BIT"
12250 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12251 [(set_attr "length" "8")])
12252
12253 (define_insn ""
12254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12255 (compare:CC
12256 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12257 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12258 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12259 (const_int 0)))
12260 (clobber (match_scratch:SI 4 "=&r,&r"))]
12261 "TARGET_32BIT"
12262 "@
12263 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12264 #"
12265 [(set_attr "type" "compare")
12266 (set_attr "length" "8,12")])
12267
12268 (define_split
12269 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12270 (compare:CC
12271 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12272 (match_operand:SI 2 "reg_or_short_operand" ""))
12273 (match_operand:SI 3 "gpc_reg_operand" ""))
12274 (const_int 0)))
12275 (clobber (match_scratch:SI 4 ""))]
12276 "TARGET_32BIT && reload_completed"
12277 [(set (match_dup 4)
12278 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12279 (match_dup 3)))
12280 (set (match_dup 0)
12281 (compare:CC (match_dup 4)
12282 (const_int 0)))]
12283 "")
12284
12285 (define_insn ""
12286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12287 (compare:CC
12288 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12289 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12290 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12291 (const_int 0)))
12292 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12293 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12294 "TARGET_32BIT"
12295 "@
12296 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12297 #"
12298 [(set_attr "type" "compare")
12299 (set_attr "length" "8,12")])
12300
12301 (define_split
12302 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12303 (compare:CC
12304 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12305 (match_operand:SI 2 "reg_or_short_operand" ""))
12306 (match_operand:SI 3 "gpc_reg_operand" ""))
12307 (const_int 0)))
12308 (set (match_operand:SI 0 "gpc_reg_operand" "")
12309 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12310 "TARGET_32BIT && reload_completed"
12311 [(set (match_dup 0)
12312 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12313 (set (match_dup 4)
12314 (compare:CC (match_dup 0)
12315 (const_int 0)))]
12316 "")
12317
12318 (define_insn ""
12319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12320 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12321 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12322 "TARGET_32BIT"
12323 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12324 [(set_attr "length" "12")])
12325
12326 (define_insn ""
12327 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12328 (and:SI (neg:SI
12329 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12330 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12331 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12332 "TARGET_32BIT"
12333 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12334 [(set_attr "length" "12")])
12335
12336 (define_insn ""
12337 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12338 (compare:CC
12339 (and:SI (neg:SI
12340 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12341 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12342 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12343 (const_int 0)))
12344 (clobber (match_scratch:SI 4 "=&r,&r"))]
12345 "TARGET_32BIT"
12346 "@
12347 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12348 #"
12349 [(set_attr "type" "compare")
12350 (set_attr "length" "12,16")])
12351
12352 (define_split
12353 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12354 (compare:CC
12355 (and:SI (neg:SI
12356 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12357 (match_operand:SI 2 "reg_or_short_operand" "")))
12358 (match_operand:SI 3 "gpc_reg_operand" ""))
12359 (const_int 0)))
12360 (clobber (match_scratch:SI 4 ""))]
12361 "TARGET_32BIT && reload_completed"
12362 [(set (match_dup 4)
12363 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12364 (match_dup 3)))
12365 (set (match_dup 0)
12366 (compare:CC (match_dup 4)
12367 (const_int 0)))]
12368 "")
12369
12370 (define_insn ""
12371 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12372 (compare:CC
12373 (and:SI (neg:SI
12374 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12375 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12376 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12377 (const_int 0)))
12378 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12379 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12380 "TARGET_32BIT"
12381 "@
12382 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12383 #"
12384 [(set_attr "type" "compare")
12385 (set_attr "length" "12,16")])
12386
12387 (define_split
12388 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12389 (compare:CC
12390 (and:SI (neg:SI
12391 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12392 (match_operand:SI 2 "reg_or_short_operand" "")))
12393 (match_operand:SI 3 "gpc_reg_operand" ""))
12394 (const_int 0)))
12395 (set (match_operand:SI 0 "gpc_reg_operand" "")
12396 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12397 "TARGET_32BIT && reload_completed"
12398 [(set (match_dup 0)
12399 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12400 (match_dup 3)))
12401 (set (match_dup 4)
12402 (compare:CC (match_dup 0)
12403 (const_int 0)))]
12404 "")
12405
12406 (define_insn ""
12407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12408 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12409 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12410 "TARGET_POWER"
12411 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12412 [(set_attr "length" "12")])
12413
12414 (define_insn ""
12415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12416 (compare:CC
12417 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12418 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12419 (const_int 0)))
12420 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12421 (lt:SI (match_dup 1) (match_dup 2)))]
12422 "TARGET_POWER"
12423 "@
12424 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12425 #"
12426 [(set_attr "type" "delayed_compare")
12427 (set_attr "length" "12,16")])
12428
12429 (define_split
12430 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12431 (compare:CC
12432 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12433 (match_operand:SI 2 "reg_or_short_operand" ""))
12434 (const_int 0)))
12435 (set (match_operand:SI 0 "gpc_reg_operand" "")
12436 (lt:SI (match_dup 1) (match_dup 2)))]
12437 "TARGET_POWER && reload_completed"
12438 [(set (match_dup 0)
12439 (lt:SI (match_dup 1) (match_dup 2)))
12440 (set (match_dup 3)
12441 (compare:CC (match_dup 0)
12442 (const_int 0)))]
12443 "")
12444
12445 (define_insn ""
12446 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12447 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12448 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12449 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12450 "TARGET_POWER"
12451 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12452 [(set_attr "length" "12")])
12453
12454 (define_insn ""
12455 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12456 (compare:CC
12457 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12458 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12459 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12460 (const_int 0)))
12461 (clobber (match_scratch:SI 4 "=&r,&r"))]
12462 "TARGET_POWER"
12463 "@
12464 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12465 #"
12466 [(set_attr "type" "compare")
12467 (set_attr "length" "12,16")])
12468
12469 (define_split
12470 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12471 (compare:CC
12472 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12473 (match_operand:SI 2 "reg_or_short_operand" ""))
12474 (match_operand:SI 3 "gpc_reg_operand" ""))
12475 (const_int 0)))
12476 (clobber (match_scratch:SI 4 ""))]
12477 "TARGET_POWER && reload_completed"
12478 [(set (match_dup 4)
12479 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12480 (match_dup 3)))
12481 (set (match_dup 0)
12482 (compare:CC (match_dup 4)
12483 (const_int 0)))]
12484 "")
12485
12486 (define_insn ""
12487 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12488 (compare:CC
12489 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12490 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12491 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12492 (const_int 0)))
12493 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12494 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12495 "TARGET_POWER"
12496 "@
12497 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12498 #"
12499 [(set_attr "type" "compare")
12500 (set_attr "length" "12,16")])
12501
12502 (define_split
12503 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12504 (compare:CC
12505 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12506 (match_operand:SI 2 "reg_or_short_operand" ""))
12507 (match_operand:SI 3 "gpc_reg_operand" ""))
12508 (const_int 0)))
12509 (set (match_operand:SI 0 "gpc_reg_operand" "")
12510 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12511 "TARGET_POWER && reload_completed"
12512 [(set (match_dup 0)
12513 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12514 (set (match_dup 4)
12515 (compare:CC (match_dup 0)
12516 (const_int 0)))]
12517 "")
12518
12519 (define_insn ""
12520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12521 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12522 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12523 "TARGET_POWER"
12524 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12525 [(set_attr "length" "12")])
12526
12527 (define_insn ""
12528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12529 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12530 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12531 "TARGET_32BIT"
12532 "@
12533 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12534 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12535 [(set_attr "length" "12")])
12536
12537 (define_insn ""
12538 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12539 (compare:CC
12540 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12541 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12542 (const_int 0)))
12543 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12544 (ltu:SI (match_dup 1) (match_dup 2)))]
12545 "TARGET_32BIT"
12546 "@
12547 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12548 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12549 #
12550 #"
12551 [(set_attr "type" "compare")
12552 (set_attr "length" "12,12,16,16")])
12553
12554 (define_split
12555 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12556 (compare:CC
12557 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12558 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12559 (const_int 0)))
12560 (set (match_operand:SI 0 "gpc_reg_operand" "")
12561 (ltu:SI (match_dup 1) (match_dup 2)))]
12562 "TARGET_32BIT && reload_completed"
12563 [(set (match_dup 0)
12564 (ltu:SI (match_dup 1) (match_dup 2)))
12565 (set (match_dup 3)
12566 (compare:CC (match_dup 0)
12567 (const_int 0)))]
12568 "")
12569
12570 (define_insn ""
12571 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12572 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12573 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12574 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12575 "TARGET_32BIT"
12576 "@
12577 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12578 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12579 [(set_attr "length" "12")])
12580
12581 (define_insn ""
12582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12583 (compare:CC
12584 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12585 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12586 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12587 (const_int 0)))
12588 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12589 "TARGET_32BIT"
12590 "@
12591 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12592 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12593 #
12594 #"
12595 [(set_attr "type" "compare")
12596 (set_attr "length" "12,12,16,16")])
12597
12598 (define_split
12599 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12600 (compare:CC
12601 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12602 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12603 (match_operand:SI 3 "gpc_reg_operand" ""))
12604 (const_int 0)))
12605 (clobber (match_scratch:SI 4 ""))]
12606 "TARGET_32BIT && reload_completed"
12607 [(set (match_dup 4)
12608 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12609 (match_dup 3)))
12610 (set (match_dup 0)
12611 (compare:CC (match_dup 4)
12612 (const_int 0)))]
12613 "")
12614
12615 (define_insn ""
12616 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12617 (compare:CC
12618 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12619 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12620 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12621 (const_int 0)))
12622 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12623 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12624 "TARGET_32BIT"
12625 "@
12626 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12627 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12628 #
12629 #"
12630 [(set_attr "type" "compare")
12631 (set_attr "length" "12,12,16,16")])
12632
12633 (define_split
12634 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12635 (compare:CC
12636 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12637 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12638 (match_operand:SI 3 "gpc_reg_operand" ""))
12639 (const_int 0)))
12640 (set (match_operand:SI 0 "gpc_reg_operand" "")
12641 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12642 "TARGET_32BIT && reload_completed"
12643 [(set (match_dup 0)
12644 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12645 (set (match_dup 4)
12646 (compare:CC (match_dup 0)
12647 (const_int 0)))]
12648 "")
12649
12650 (define_insn ""
12651 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12652 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12653 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12654 "TARGET_32BIT"
12655 "@
12656 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12657 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12658 [(set_attr "length" "8")])
12659
12660 (define_insn ""
12661 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12662 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12663 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12664 (clobber (match_scratch:SI 3 "=r"))]
12665 "TARGET_POWER"
12666 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12667 [(set_attr "length" "12")])
12668
12669 (define_insn ""
12670 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12671 (compare:CC
12672 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12673 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12674 (const_int 0)))
12675 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12676 (ge:SI (match_dup 1) (match_dup 2)))
12677 (clobber (match_scratch:SI 3 "=r,r"))]
12678 "TARGET_POWER"
12679 "@
12680 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12681 #"
12682 [(set_attr "type" "compare")
12683 (set_attr "length" "12,16")])
12684
12685 (define_split
12686 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12687 (compare:CC
12688 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12689 (match_operand:SI 2 "reg_or_short_operand" ""))
12690 (const_int 0)))
12691 (set (match_operand:SI 0 "gpc_reg_operand" "")
12692 (ge:SI (match_dup 1) (match_dup 2)))
12693 (clobber (match_scratch:SI 3 ""))]
12694 "TARGET_POWER && reload_completed"
12695 [(parallel [(set (match_dup 0)
12696 (ge:SI (match_dup 1) (match_dup 2)))
12697 (clobber (match_dup 3))])
12698 (set (match_dup 4)
12699 (compare:CC (match_dup 0)
12700 (const_int 0)))]
12701 "")
12702
12703 (define_insn ""
12704 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12705 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12706 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12707 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12708 "TARGET_POWER"
12709 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12710 [(set_attr "length" "12")])
12711
12712 (define_insn ""
12713 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12714 (compare:CC
12715 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12716 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12717 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12718 (const_int 0)))
12719 (clobber (match_scratch:SI 4 "=&r,&r"))]
12720 "TARGET_POWER"
12721 "@
12722 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12723 #"
12724 [(set_attr "type" "compare")
12725 (set_attr "length" "12,16")])
12726
12727 (define_split
12728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12729 (compare:CC
12730 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12731 (match_operand:SI 2 "reg_or_short_operand" ""))
12732 (match_operand:SI 3 "gpc_reg_operand" ""))
12733 (const_int 0)))
12734 (clobber (match_scratch:SI 4 ""))]
12735 "TARGET_POWER && reload_completed"
12736 [(set (match_dup 4)
12737 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12738 (match_dup 3)))
12739 (set (match_dup 0)
12740 (compare:CC (match_dup 4)
12741 (const_int 0)))]
12742 "")
12743
12744 (define_insn ""
12745 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12746 (compare:CC
12747 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12748 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12749 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12750 (const_int 0)))
12751 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12752 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12753 "TARGET_POWER"
12754 "@
12755 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12756 #"
12757 [(set_attr "type" "compare")
12758 (set_attr "length" "12,16")])
12759
12760 (define_split
12761 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12762 (compare:CC
12763 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12764 (match_operand:SI 2 "reg_or_short_operand" ""))
12765 (match_operand:SI 3 "gpc_reg_operand" ""))
12766 (const_int 0)))
12767 (set (match_operand:SI 0 "gpc_reg_operand" "")
12768 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12769 "TARGET_POWER && reload_completed"
12770 [(set (match_dup 0)
12771 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12772 (set (match_dup 4)
12773 (compare:CC (match_dup 0)
12774 (const_int 0)))]
12775 "")
12776
12777 (define_insn ""
12778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12779 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12780 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12781 "TARGET_POWER"
12782 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12783 [(set_attr "length" "12")])
12784
12785 (define_insn ""
12786 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12787 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12788 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12789 "TARGET_32BIT"
12790 "@
12791 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12792 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12793 [(set_attr "length" "12")])
12794
12795 (define_insn ""
12796 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12797 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12798 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12799 "TARGET_64BIT"
12800 "@
12801 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12802 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12803 [(set_attr "length" "12")])
12804
12805 (define_insn ""
12806 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12807 (compare:CC
12808 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12809 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12810 (const_int 0)))
12811 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12812 (geu:SI (match_dup 1) (match_dup 2)))]
12813 "TARGET_32BIT"
12814 "@
12815 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12816 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12817 #
12818 #"
12819 [(set_attr "type" "compare")
12820 (set_attr "length" "12,12,16,16")])
12821
12822 (define_split
12823 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12824 (compare:CC
12825 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12826 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12827 (const_int 0)))
12828 (set (match_operand:SI 0 "gpc_reg_operand" "")
12829 (geu:SI (match_dup 1) (match_dup 2)))]
12830 "TARGET_32BIT && reload_completed"
12831 [(set (match_dup 0)
12832 (geu:SI (match_dup 1) (match_dup 2)))
12833 (set (match_dup 3)
12834 (compare:CC (match_dup 0)
12835 (const_int 0)))]
12836 "")
12837
12838 (define_insn ""
12839 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12840 (compare:CC
12841 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12842 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12843 (const_int 0)))
12844 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12845 (geu:DI (match_dup 1) (match_dup 2)))]
12846 "TARGET_64BIT"
12847 "@
12848 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12849 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12850 #
12851 #"
12852 [(set_attr "type" "compare")
12853 (set_attr "length" "12,12,16,16")])
12854
12855 (define_split
12856 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12857 (compare:CC
12858 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12859 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12860 (const_int 0)))
12861 (set (match_operand:DI 0 "gpc_reg_operand" "")
12862 (geu:DI (match_dup 1) (match_dup 2)))]
12863 "TARGET_64BIT && reload_completed"
12864 [(set (match_dup 0)
12865 (geu:DI (match_dup 1) (match_dup 2)))
12866 (set (match_dup 3)
12867 (compare:CC (match_dup 0)
12868 (const_int 0)))]
12869 "")
12870
12871 (define_insn ""
12872 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12873 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12874 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12875 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12876 "TARGET_32BIT"
12877 "@
12878 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12879 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12880 [(set_attr "length" "8")])
12881
12882 (define_insn ""
12883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12884 (compare:CC
12885 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12886 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12887 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12888 (const_int 0)))
12889 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12890 "TARGET_32BIT"
12891 "@
12892 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12893 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12894 #
12895 #"
12896 [(set_attr "type" "compare")
12897 (set_attr "length" "8,8,12,12")])
12898
12899 (define_split
12900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12901 (compare:CC
12902 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12903 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12904 (match_operand:SI 3 "gpc_reg_operand" ""))
12905 (const_int 0)))
12906 (clobber (match_scratch:SI 4 ""))]
12907 "TARGET_32BIT && reload_completed"
12908 [(set (match_dup 4)
12909 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12910 (match_dup 3)))
12911 (set (match_dup 0)
12912 (compare:CC (match_dup 4)
12913 (const_int 0)))]
12914 "")
12915
12916 (define_insn ""
12917 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12918 (compare:CC
12919 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12920 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12921 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12922 (const_int 0)))
12923 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12924 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12925 "TARGET_32BIT"
12926 "@
12927 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12928 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12929 #
12930 #"
12931 [(set_attr "type" "compare")
12932 (set_attr "length" "8,8,12,12")])
12933
12934 (define_split
12935 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12936 (compare:CC
12937 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12938 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12939 (match_operand:SI 3 "gpc_reg_operand" ""))
12940 (const_int 0)))
12941 (set (match_operand:SI 0 "gpc_reg_operand" "")
12942 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12943 "TARGET_32BIT && reload_completed"
12944 [(set (match_dup 0)
12945 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12946 (set (match_dup 4)
12947 (compare:CC (match_dup 0)
12948 (const_int 0)))]
12949 "")
12950
12951 (define_insn ""
12952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12953 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12954 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12955 "TARGET_32BIT"
12956 "@
12957 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12958 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12959 [(set_attr "length" "12")])
12960
12961 (define_insn ""
12962 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12963 (and:SI (neg:SI
12964 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12965 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12966 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12967 "TARGET_32BIT"
12968 "@
12969 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12970 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12971 [(set_attr "length" "12")])
12972
12973 (define_insn ""
12974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12975 (compare:CC
12976 (and:SI (neg:SI
12977 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12978 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12979 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12980 (const_int 0)))
12981 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12982 "TARGET_32BIT"
12983 "@
12984 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12985 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12986 #
12987 #"
12988 [(set_attr "type" "compare")
12989 (set_attr "length" "12,12,16,16")])
12990
12991 (define_split
12992 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12993 (compare:CC
12994 (and:SI (neg:SI
12995 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12996 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12997 (match_operand:SI 3 "gpc_reg_operand" ""))
12998 (const_int 0)))
12999 (clobber (match_scratch:SI 4 ""))]
13000 "TARGET_32BIT && reload_completed"
13001 [(set (match_dup 4)
13002 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13003 (match_dup 3)))
13004 (set (match_dup 0)
13005 (compare:CC (match_dup 4)
13006 (const_int 0)))]
13007 "")
13008
13009 (define_insn ""
13010 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13011 (compare:CC
13012 (and:SI (neg:SI
13013 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13014 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13015 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13016 (const_int 0)))
13017 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13018 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13019 "TARGET_32BIT"
13020 "@
13021 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13022 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13023 #
13024 #"
13025 [(set_attr "type" "compare")
13026 (set_attr "length" "12,12,16,16")])
13027
13028 (define_split
13029 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13030 (compare:CC
13031 (and:SI (neg:SI
13032 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13033 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13034 (match_operand:SI 3 "gpc_reg_operand" ""))
13035 (const_int 0)))
13036 (set (match_operand:SI 0 "gpc_reg_operand" "")
13037 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13038 "TARGET_32BIT && reload_completed"
13039 [(set (match_dup 0)
13040 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13041 (set (match_dup 4)
13042 (compare:CC (match_dup 0)
13043 (const_int 0)))]
13044 "")
13045
13046 (define_insn ""
13047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13048 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13049 (const_int 0)))]
13050 "TARGET_32BIT"
13051 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13052 [(set_attr "length" "12")])
13053
13054 (define_insn ""
13055 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13056 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13057 (const_int 0)))]
13058 "TARGET_64BIT"
13059 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13060 [(set_attr "length" "12")])
13061
13062 (define_insn ""
13063 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13064 (compare:CC
13065 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13066 (const_int 0))
13067 (const_int 0)))
13068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13069 (gt:SI (match_dup 1) (const_int 0)))]
13070 "TARGET_32BIT"
13071 "@
13072 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13073 #"
13074 [(set_attr "type" "delayed_compare")
13075 (set_attr "length" "12,16")])
13076
13077 (define_split
13078 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13079 (compare:CC
13080 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13081 (const_int 0))
13082 (const_int 0)))
13083 (set (match_operand:SI 0 "gpc_reg_operand" "")
13084 (gt:SI (match_dup 1) (const_int 0)))]
13085 "TARGET_32BIT && reload_completed"
13086 [(set (match_dup 0)
13087 (gt:SI (match_dup 1) (const_int 0)))
13088 (set (match_dup 2)
13089 (compare:CC (match_dup 0)
13090 (const_int 0)))]
13091 "")
13092
13093 (define_insn ""
13094 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13095 (compare:CC
13096 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13097 (const_int 0))
13098 (const_int 0)))
13099 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13100 (gt:DI (match_dup 1) (const_int 0)))]
13101 "TARGET_64BIT"
13102 "@
13103 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13104 #"
13105 [(set_attr "type" "delayed_compare")
13106 (set_attr "length" "12,16")])
13107
13108 (define_split
13109 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13110 (compare:CC
13111 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13112 (const_int 0))
13113 (const_int 0)))
13114 (set (match_operand:DI 0 "gpc_reg_operand" "")
13115 (gt:DI (match_dup 1) (const_int 0)))]
13116 "TARGET_64BIT && reload_completed"
13117 [(set (match_dup 0)
13118 (gt:DI (match_dup 1) (const_int 0)))
13119 (set (match_dup 2)
13120 (compare:CC (match_dup 0)
13121 (const_int 0)))]
13122 "")
13123
13124 (define_insn ""
13125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13126 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13127 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13128 "TARGET_POWER"
13129 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13130 [(set_attr "length" "12")])
13131
13132 (define_insn ""
13133 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13134 (compare:CC
13135 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13136 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13137 (const_int 0)))
13138 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13139 (gt:SI (match_dup 1) (match_dup 2)))]
13140 "TARGET_POWER"
13141 "@
13142 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13143 #"
13144 [(set_attr "type" "delayed_compare")
13145 (set_attr "length" "12,16")])
13146
13147 (define_split
13148 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13149 (compare:CC
13150 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13151 (match_operand:SI 2 "reg_or_short_operand" ""))
13152 (const_int 0)))
13153 (set (match_operand:SI 0 "gpc_reg_operand" "")
13154 (gt:SI (match_dup 1) (match_dup 2)))]
13155 "TARGET_POWER && reload_completed"
13156 [(set (match_dup 0)
13157 (gt:SI (match_dup 1) (match_dup 2)))
13158 (set (match_dup 3)
13159 (compare:CC (match_dup 0)
13160 (const_int 0)))]
13161 "")
13162
13163 (define_insn ""
13164 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13165 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13166 (const_int 0))
13167 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13168 "TARGET_32BIT"
13169 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13170 [(set_attr "length" "12")])
13171
13172 (define_insn ""
13173 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13174 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13175 (const_int 0))
13176 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13177 "TARGET_64BIT"
13178 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13179 [(set_attr "length" "12")])
13180
13181 (define_insn ""
13182 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13183 (compare:CC
13184 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13185 (const_int 0))
13186 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13187 (const_int 0)))
13188 (clobber (match_scratch:SI 3 "=&r,&r"))]
13189 "TARGET_32BIT"
13190 "@
13191 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13192 #"
13193 [(set_attr "type" "compare")
13194 (set_attr "length" "12,16")])
13195
13196 (define_split
13197 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13198 (compare:CC
13199 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13200 (const_int 0))
13201 (match_operand:SI 2 "gpc_reg_operand" ""))
13202 (const_int 0)))
13203 (clobber (match_scratch:SI 3 ""))]
13204 "TARGET_32BIT && reload_completed"
13205 [(set (match_dup 3)
13206 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13207 (match_dup 2)))
13208 (set (match_dup 0)
13209 (compare:CC (match_dup 3)
13210 (const_int 0)))]
13211 "")
13212
13213 (define_insn ""
13214 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13215 (compare:CC
13216 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13217 (const_int 0))
13218 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13219 (const_int 0)))
13220 (clobber (match_scratch:DI 3 "=&r,&r"))]
13221 "TARGET_64BIT"
13222 "@
13223 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13224 #"
13225 [(set_attr "type" "compare")
13226 (set_attr "length" "12,16")])
13227
13228 (define_split
13229 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13230 (compare:CC
13231 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13232 (const_int 0))
13233 (match_operand:DI 2 "gpc_reg_operand" ""))
13234 (const_int 0)))
13235 (clobber (match_scratch:DI 3 ""))]
13236 "TARGET_64BIT && reload_completed"
13237 [(set (match_dup 3)
13238 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13239 (match_dup 2)))
13240 (set (match_dup 0)
13241 (compare:CC (match_dup 3)
13242 (const_int 0)))]
13243 "")
13244
13245 (define_insn ""
13246 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13247 (compare:CC
13248 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13249 (const_int 0))
13250 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13251 (const_int 0)))
13252 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13253 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13254 "TARGET_32BIT"
13255 "@
13256 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13257 #"
13258 [(set_attr "type" "compare")
13259 (set_attr "length" "12,16")])
13260
13261 (define_split
13262 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13263 (compare:CC
13264 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13265 (const_int 0))
13266 (match_operand:SI 2 "gpc_reg_operand" ""))
13267 (const_int 0)))
13268 (set (match_operand:SI 0 "gpc_reg_operand" "")
13269 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13270 "TARGET_32BIT && reload_completed"
13271 [(set (match_dup 0)
13272 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13273 (set (match_dup 3)
13274 (compare:CC (match_dup 0)
13275 (const_int 0)))]
13276 "")
13277
13278 (define_insn ""
13279 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13280 (compare:CC
13281 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13282 (const_int 0))
13283 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13284 (const_int 0)))
13285 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13286 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13287 "TARGET_64BIT"
13288 "@
13289 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13290 #"
13291 [(set_attr "type" "compare")
13292 (set_attr "length" "12,16")])
13293
13294 (define_split
13295 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13296 (compare:CC
13297 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13298 (const_int 0))
13299 (match_operand:DI 2 "gpc_reg_operand" ""))
13300 (const_int 0)))
13301 (set (match_operand:DI 0 "gpc_reg_operand" "")
13302 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13303 "TARGET_64BIT && reload_completed"
13304 [(set (match_dup 0)
13305 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13306 (set (match_dup 3)
13307 (compare:CC (match_dup 0)
13308 (const_int 0)))]
13309 "")
13310
13311 (define_insn ""
13312 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13313 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13314 (match_operand:SI 2 "reg_or_short_operand" "r"))
13315 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13316 "TARGET_POWER"
13317 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13318 [(set_attr "length" "12")])
13319
13320 (define_insn ""
13321 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13322 (compare:CC
13323 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13324 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13325 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13326 (const_int 0)))
13327 (clobber (match_scratch:SI 4 "=&r,&r"))]
13328 "TARGET_POWER"
13329 "@
13330 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13331 #"
13332 [(set_attr "type" "compare")
13333 (set_attr "length" "12,16")])
13334
13335 (define_split
13336 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13337 (compare:CC
13338 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13339 (match_operand:SI 2 "reg_or_short_operand" ""))
13340 (match_operand:SI 3 "gpc_reg_operand" ""))
13341 (const_int 0)))
13342 (clobber (match_scratch:SI 4 ""))]
13343 "TARGET_POWER && reload_completed"
13344 [(set (match_dup 4)
13345 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13346 (set (match_dup 0)
13347 (compare:CC (match_dup 4)
13348 (const_int 0)))]
13349 "")
13350
13351 (define_insn ""
13352 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13353 (compare:CC
13354 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13355 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13356 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13357 (const_int 0)))
13358 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13359 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13360 "TARGET_POWER"
13361 "@
13362 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13363 #"
13364 [(set_attr "type" "compare")
13365 (set_attr "length" "12,16")])
13366
13367 (define_split
13368 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13369 (compare:CC
13370 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13371 (match_operand:SI 2 "reg_or_short_operand" ""))
13372 (match_operand:SI 3 "gpc_reg_operand" ""))
13373 (const_int 0)))
13374 (set (match_operand:SI 0 "gpc_reg_operand" "")
13375 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13376 "TARGET_POWER && reload_completed"
13377 [(set (match_dup 0)
13378 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13379 (set (match_dup 4)
13380 (compare:CC (match_dup 0)
13381 (const_int 0)))]
13382 "")
13383
13384 (define_insn ""
13385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13386 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13387 (const_int 0))))]
13388 "TARGET_32BIT"
13389 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13390 [(set_attr "length" "12")])
13391
13392 (define_insn ""
13393 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13394 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13395 (const_int 0))))]
13396 "TARGET_64BIT"
13397 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13398 [(set_attr "length" "12")])
13399
13400 (define_insn ""
13401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13402 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13403 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13404 "TARGET_POWER"
13405 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13406 [(set_attr "length" "12")])
13407
13408 (define_insn ""
13409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13410 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13411 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13412 "TARGET_32BIT"
13413 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13414 [(set_attr "length" "12")])
13415
13416 (define_insn ""
13417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13418 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13419 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13420 "TARGET_64BIT"
13421 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13422 [(set_attr "length" "12")])
13423
13424 (define_insn ""
13425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13426 (compare:CC
13427 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13428 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13429 (const_int 0)))
13430 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13431 (gtu:SI (match_dup 1) (match_dup 2)))]
13432 "TARGET_32BIT"
13433 "@
13434 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13435 #"
13436 [(set_attr "type" "compare")
13437 (set_attr "length" "12,16")])
13438
13439 (define_split
13440 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13441 (compare:CC
13442 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13443 (match_operand:SI 2 "reg_or_short_operand" ""))
13444 (const_int 0)))
13445 (set (match_operand:SI 0 "gpc_reg_operand" "")
13446 (gtu:SI (match_dup 1) (match_dup 2)))]
13447 "TARGET_32BIT && reload_completed"
13448 [(set (match_dup 0)
13449 (gtu:SI (match_dup 1) (match_dup 2)))
13450 (set (match_dup 3)
13451 (compare:CC (match_dup 0)
13452 (const_int 0)))]
13453 "")
13454
13455 (define_insn ""
13456 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13457 (compare:CC
13458 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13459 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13460 (const_int 0)))
13461 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13462 (gtu:DI (match_dup 1) (match_dup 2)))]
13463 "TARGET_64BIT"
13464 "@
13465 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13466 #"
13467 [(set_attr "type" "compare")
13468 (set_attr "length" "12,16")])
13469
13470 (define_split
13471 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13472 (compare:CC
13473 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13474 (match_operand:DI 2 "reg_or_short_operand" ""))
13475 (const_int 0)))
13476 (set (match_operand:DI 0 "gpc_reg_operand" "")
13477 (gtu:DI (match_dup 1) (match_dup 2)))]
13478 "TARGET_64BIT && reload_completed"
13479 [(set (match_dup 0)
13480 (gtu:DI (match_dup 1) (match_dup 2)))
13481 (set (match_dup 3)
13482 (compare:CC (match_dup 0)
13483 (const_int 0)))]
13484 "")
13485
13486 (define_insn ""
13487 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13488 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13489 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13490 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13491 "TARGET_32BIT"
13492 "@
13493 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13494 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13495 [(set_attr "length" "8,12")])
13496
13497 (define_insn ""
13498 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13499 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13500 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13501 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13502 "TARGET_64BIT"
13503 "@
13504 addic %0,%1,%k2\;addze %0,%3
13505 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13506 [(set_attr "length" "8,12")])
13507
13508 (define_insn ""
13509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13510 (compare:CC
13511 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13512 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13513 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13514 (const_int 0)))
13515 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13516 "TARGET_32BIT"
13517 "@
13518 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13519 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13520 #
13521 #"
13522 [(set_attr "type" "compare")
13523 (set_attr "length" "8,12,12,16")])
13524
13525 (define_split
13526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13527 (compare:CC
13528 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13529 (match_operand:SI 2 "reg_or_short_operand" ""))
13530 (match_operand:SI 3 "gpc_reg_operand" ""))
13531 (const_int 0)))
13532 (clobber (match_scratch:SI 4 ""))]
13533 "TARGET_32BIT && reload_completed"
13534 [(set (match_dup 4)
13535 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13536 (match_dup 3)))
13537 (set (match_dup 0)
13538 (compare:CC (match_dup 4)
13539 (const_int 0)))]
13540 "")
13541
13542 (define_insn ""
13543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13544 (compare:CC
13545 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13546 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13547 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13548 (const_int 0)))
13549 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13550 "TARGET_64BIT"
13551 "@
13552 addic %4,%1,%k2\;addze. %4,%3
13553 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13554 #
13555 #"
13556 [(set_attr "type" "compare")
13557 (set_attr "length" "8,12,12,16")])
13558
13559 (define_split
13560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13561 (compare:CC
13562 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13563 (match_operand:DI 2 "reg_or_short_operand" ""))
13564 (match_operand:DI 3 "gpc_reg_operand" ""))
13565 (const_int 0)))
13566 (clobber (match_scratch:DI 4 ""))]
13567 "TARGET_64BIT && reload_completed"
13568 [(set (match_dup 4)
13569 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13570 (match_dup 3)))
13571 (set (match_dup 0)
13572 (compare:CC (match_dup 4)
13573 (const_int 0)))]
13574 "")
13575
13576 (define_insn ""
13577 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13578 (compare:CC
13579 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13580 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13581 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13582 (const_int 0)))
13583 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13584 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13585 "TARGET_32BIT"
13586 "@
13587 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13588 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13589 #
13590 #"
13591 [(set_attr "type" "compare")
13592 (set_attr "length" "8,12,12,16")])
13593
13594 (define_split
13595 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13596 (compare:CC
13597 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13598 (match_operand:SI 2 "reg_or_short_operand" ""))
13599 (match_operand:SI 3 "gpc_reg_operand" ""))
13600 (const_int 0)))
13601 (set (match_operand:SI 0 "gpc_reg_operand" "")
13602 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13603 "TARGET_32BIT && reload_completed"
13604 [(set (match_dup 0)
13605 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13606 (set (match_dup 4)
13607 (compare:CC (match_dup 0)
13608 (const_int 0)))]
13609 "")
13610
13611 (define_insn ""
13612 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13613 (compare:CC
13614 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13615 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13616 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13617 (const_int 0)))
13618 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13619 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13620 "TARGET_64BIT"
13621 "@
13622 addic %0,%1,%k2\;addze. %0,%3
13623 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13624 #
13625 #"
13626 [(set_attr "type" "compare")
13627 (set_attr "length" "8,12,12,16")])
13628
13629 (define_split
13630 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13631 (compare:CC
13632 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13633 (match_operand:DI 2 "reg_or_short_operand" ""))
13634 (match_operand:DI 3 "gpc_reg_operand" ""))
13635 (const_int 0)))
13636 (set (match_operand:DI 0 "gpc_reg_operand" "")
13637 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13638 "TARGET_64BIT && reload_completed"
13639 [(set (match_dup 0)
13640 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13641 (set (match_dup 4)
13642 (compare:CC (match_dup 0)
13643 (const_int 0)))]
13644 "")
13645
13646 (define_insn ""
13647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13648 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13649 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13650 "TARGET_32BIT"
13651 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13652 [(set_attr "length" "8")])
13653
13654 (define_insn ""
13655 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13656 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13657 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13658 "TARGET_64BIT"
13659 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13660 [(set_attr "length" "8")])
13661 \f
13662 ;; Define both directions of branch and return. If we need a reload
13663 ;; register, we'd rather use CR0 since it is much easier to copy a
13664 ;; register CC value to there.
13665
13666 (define_insn ""
13667 [(set (pc)
13668 (if_then_else (match_operator 1 "branch_comparison_operator"
13669 [(match_operand 2
13670 "cc_reg_operand" "y")
13671 (const_int 0)])
13672 (label_ref (match_operand 0 "" ""))
13673 (pc)))]
13674 ""
13675 "*
13676 {
13677 return output_cbranch (operands[1], \"%l0\", 0, insn);
13678 }"
13679 [(set_attr "type" "branch")])
13680
13681 (define_insn ""
13682 [(set (pc)
13683 (if_then_else (match_operator 0 "branch_comparison_operator"
13684 [(match_operand 1
13685 "cc_reg_operand" "y")
13686 (const_int 0)])
13687 (return)
13688 (pc)))]
13689 "direct_return ()"
13690 "*
13691 {
13692 return output_cbranch (operands[0], NULL, 0, insn);
13693 }"
13694 [(set_attr "type" "branch")
13695 (set_attr "length" "4")])
13696
13697 (define_insn ""
13698 [(set (pc)
13699 (if_then_else (match_operator 1 "branch_comparison_operator"
13700 [(match_operand 2
13701 "cc_reg_operand" "y")
13702 (const_int 0)])
13703 (pc)
13704 (label_ref (match_operand 0 "" ""))))]
13705 ""
13706 "*
13707 {
13708 return output_cbranch (operands[1], \"%l0\", 1, insn);
13709 }"
13710 [(set_attr "type" "branch")])
13711
13712 (define_insn ""
13713 [(set (pc)
13714 (if_then_else (match_operator 0 "branch_comparison_operator"
13715 [(match_operand 1
13716 "cc_reg_operand" "y")
13717 (const_int 0)])
13718 (pc)
13719 (return)))]
13720 "direct_return ()"
13721 "*
13722 {
13723 return output_cbranch (operands[0], NULL, 1, insn);
13724 }"
13725 [(set_attr "type" "branch")
13726 (set_attr "length" "4")])
13727
13728 ;; Logic on condition register values.
13729
13730 ; This pattern matches things like
13731 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13732 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13733 ; (const_int 1)))
13734 ; which are generated by the branch logic.
13735 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13736
13737 (define_insn "*cceq_ior_compare"
13738 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13739 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13740 [(match_operator:SI 2
13741 "branch_positive_comparison_operator"
13742 [(match_operand 3
13743 "cc_reg_operand" "y,y")
13744 (const_int 0)])
13745 (match_operator:SI 4
13746 "branch_positive_comparison_operator"
13747 [(match_operand 5
13748 "cc_reg_operand" "0,y")
13749 (const_int 0)])])
13750 (const_int 1)))]
13751 ""
13752 "cr%q1 %E0,%j2,%j4"
13753 [(set_attr "type" "cr_logical,delayed_cr")])
13754
13755 ; Why is the constant -1 here, but 1 in the previous pattern?
13756 ; Because ~1 has all but the low bit set.
13757 (define_insn ""
13758 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13759 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13760 [(not:SI (match_operator:SI 2
13761 "branch_positive_comparison_operator"
13762 [(match_operand 3
13763 "cc_reg_operand" "y,y")
13764 (const_int 0)]))
13765 (match_operator:SI 4
13766 "branch_positive_comparison_operator"
13767 [(match_operand 5
13768 "cc_reg_operand" "0,y")
13769 (const_int 0)])])
13770 (const_int -1)))]
13771 ""
13772 "cr%q1 %E0,%j2,%j4"
13773 [(set_attr "type" "cr_logical,delayed_cr")])
13774
13775 (define_insn "*cceq_rev_compare"
13776 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13777 (compare:CCEQ (match_operator:SI 1
13778 "branch_positive_comparison_operator"
13779 [(match_operand 2
13780 "cc_reg_operand" "0,y")
13781 (const_int 0)])
13782 (const_int 0)))]
13783 ""
13784 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13785 [(set_attr "type" "cr_logical,delayed_cr")])
13786
13787 ;; If we are comparing the result of two comparisons, this can be done
13788 ;; using creqv or crxor.
13789
13790 (define_insn_and_split ""
13791 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13792 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13793 [(match_operand 2 "cc_reg_operand" "y")
13794 (const_int 0)])
13795 (match_operator 3 "branch_comparison_operator"
13796 [(match_operand 4 "cc_reg_operand" "y")
13797 (const_int 0)])))]
13798 ""
13799 "#"
13800 ""
13801 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13802 (match_dup 5)))]
13803 "
13804 {
13805 int positive_1, positive_2;
13806
13807 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13808 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13809
13810 if (! positive_1)
13811 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13812 GET_CODE (operands[1])),
13813 SImode,
13814 operands[2], const0_rtx);
13815 else if (GET_MODE (operands[1]) != SImode)
13816 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13817 operands[2], const0_rtx);
13818
13819 if (! positive_2)
13820 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13821 GET_CODE (operands[3])),
13822 SImode,
13823 operands[4], const0_rtx);
13824 else if (GET_MODE (operands[3]) != SImode)
13825 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13826 operands[4], const0_rtx);
13827
13828 if (positive_1 == positive_2)
13829 {
13830 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13831 operands[5] = constm1_rtx;
13832 }
13833 else
13834 {
13835 operands[5] = const1_rtx;
13836 }
13837 }")
13838
13839 ;; Unconditional branch and return.
13840
13841 (define_insn "jump"
13842 [(set (pc)
13843 (label_ref (match_operand 0 "" "")))]
13844 ""
13845 "b %l0"
13846 [(set_attr "type" "branch")])
13847
13848 (define_insn "return"
13849 [(return)]
13850 "direct_return ()"
13851 "{br|blr}"
13852 [(set_attr "type" "jmpreg")])
13853
13854 (define_expand "indirect_jump"
13855 [(set (pc) (match_operand 0 "register_operand" ""))]
13856 ""
13857 "
13858 {
13859 if (TARGET_32BIT)
13860 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13861 else
13862 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13863 DONE;
13864 }")
13865
13866 (define_insn "indirect_jumpsi"
13867 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13868 "TARGET_32BIT"
13869 "@
13870 bctr
13871 {br|blr}"
13872 [(set_attr "type" "jmpreg")])
13873
13874 (define_insn "indirect_jumpdi"
13875 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13876 "TARGET_64BIT"
13877 "@
13878 bctr
13879 blr"
13880 [(set_attr "type" "jmpreg")])
13881
13882 ;; Table jump for switch statements:
13883 (define_expand "tablejump"
13884 [(use (match_operand 0 "" ""))
13885 (use (label_ref (match_operand 1 "" "")))]
13886 ""
13887 "
13888 {
13889 if (TARGET_32BIT)
13890 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13891 else
13892 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13893 DONE;
13894 }")
13895
13896 (define_expand "tablejumpsi"
13897 [(set (match_dup 3)
13898 (plus:SI (match_operand:SI 0 "" "")
13899 (match_dup 2)))
13900 (parallel [(set (pc) (match_dup 3))
13901 (use (label_ref (match_operand 1 "" "")))])]
13902 "TARGET_32BIT"
13903 "
13904 { operands[0] = force_reg (SImode, operands[0]);
13905 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13906 operands[3] = gen_reg_rtx (SImode);
13907 }")
13908
13909 (define_expand "tablejumpdi"
13910 [(set (match_dup 4)
13911 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13912 (set (match_dup 3)
13913 (plus:DI (match_dup 4)
13914 (match_dup 2)))
13915 (parallel [(set (pc) (match_dup 3))
13916 (use (label_ref (match_operand 1 "" "")))])]
13917 "TARGET_64BIT"
13918 "
13919 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13920 operands[3] = gen_reg_rtx (DImode);
13921 operands[4] = gen_reg_rtx (DImode);
13922 }")
13923
13924 (define_insn ""
13925 [(set (pc)
13926 (match_operand:SI 0 "register_operand" "c,*l"))
13927 (use (label_ref (match_operand 1 "" "")))]
13928 "TARGET_32BIT"
13929 "@
13930 bctr
13931 {br|blr}"
13932 [(set_attr "type" "jmpreg")])
13933
13934 (define_insn ""
13935 [(set (pc)
13936 (match_operand:DI 0 "register_operand" "c,*l"))
13937 (use (label_ref (match_operand 1 "" "")))]
13938 "TARGET_64BIT"
13939 "@
13940 bctr
13941 blr"
13942 [(set_attr "type" "jmpreg")])
13943
13944 (define_insn "nop"
13945 [(const_int 0)]
13946 ""
13947 "{cror 0,0,0|nop}")
13948 \f
13949 ;; Define the subtract-one-and-jump insns, starting with the template
13950 ;; so loop.c knows what to generate.
13951
13952 (define_expand "doloop_end"
13953 [(use (match_operand 0 "" "")) ; loop pseudo
13954 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13955 (use (match_operand 2 "" "")) ; max iterations
13956 (use (match_operand 3 "" "")) ; loop level
13957 (use (match_operand 4 "" ""))] ; label
13958 ""
13959 "
13960 {
13961 /* Only use this on innermost loops. */
13962 if (INTVAL (operands[3]) > 1)
13963 FAIL;
13964 if (TARGET_64BIT)
13965 {
13966 if (GET_MODE (operands[0]) != DImode)
13967 FAIL;
13968 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13969 }
13970 else
13971 {
13972 if (GET_MODE (operands[0]) != SImode)
13973 FAIL;
13974 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13975 }
13976 DONE;
13977 }")
13978
13979 (define_expand "ctrsi"
13980 [(parallel [(set (pc)
13981 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13982 (const_int 1))
13983 (label_ref (match_operand 1 "" ""))
13984 (pc)))
13985 (set (match_dup 0)
13986 (plus:SI (match_dup 0)
13987 (const_int -1)))
13988 (clobber (match_scratch:CC 2 ""))
13989 (clobber (match_scratch:SI 3 ""))])]
13990 "TARGET_32BIT"
13991 "")
13992
13993 (define_expand "ctrdi"
13994 [(parallel [(set (pc)
13995 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13996 (const_int 1))
13997 (label_ref (match_operand 1 "" ""))
13998 (pc)))
13999 (set (match_dup 0)
14000 (plus:DI (match_dup 0)
14001 (const_int -1)))
14002 (clobber (match_scratch:CC 2 ""))
14003 (clobber (match_scratch:DI 3 ""))])]
14004 "TARGET_64BIT"
14005 "")
14006
14007 ;; We need to be able to do this for any operand, including MEM, or we
14008 ;; will cause reload to blow up since we don't allow output reloads on
14009 ;; JUMP_INSNs.
14010 ;; For the length attribute to be calculated correctly, the
14011 ;; label MUST be operand 0.
14012
14013 (define_insn "*ctrsi_internal1"
14014 [(set (pc)
14015 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14016 (const_int 1))
14017 (label_ref (match_operand 0 "" ""))
14018 (pc)))
14019 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14020 (plus:SI (match_dup 1)
14021 (const_int -1)))
14022 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14023 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14024 "TARGET_32BIT"
14025 "*
14026 {
14027 if (which_alternative != 0)
14028 return \"#\";
14029 else if (get_attr_length (insn) == 4)
14030 return \"{bdn|bdnz} %l0\";
14031 else
14032 return \"bdz $+8\;b %l0\";
14033 }"
14034 [(set_attr "type" "branch")
14035 (set_attr "length" "*,12,16,16")])
14036
14037 (define_insn "*ctrsi_internal2"
14038 [(set (pc)
14039 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14040 (const_int 1))
14041 (pc)
14042 (label_ref (match_operand 0 "" ""))))
14043 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14044 (plus:SI (match_dup 1)
14045 (const_int -1)))
14046 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14047 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14048 "TARGET_32BIT"
14049 "*
14050 {
14051 if (which_alternative != 0)
14052 return \"#\";
14053 else if (get_attr_length (insn) == 4)
14054 return \"bdz %l0\";
14055 else
14056 return \"{bdn|bdnz} $+8\;b %l0\";
14057 }"
14058 [(set_attr "type" "branch")
14059 (set_attr "length" "*,12,16,16")])
14060
14061 (define_insn "*ctrdi_internal1"
14062 [(set (pc)
14063 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14064 (const_int 1))
14065 (label_ref (match_operand 0 "" ""))
14066 (pc)))
14067 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14068 (plus:DI (match_dup 1)
14069 (const_int -1)))
14070 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14071 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14072 "TARGET_64BIT"
14073 "*
14074 {
14075 if (which_alternative != 0)
14076 return \"#\";
14077 else if (get_attr_length (insn) == 4)
14078 return \"{bdn|bdnz} %l0\";
14079 else
14080 return \"bdz $+8\;b %l0\";
14081 }"
14082 [(set_attr "type" "branch")
14083 (set_attr "length" "*,12,16,16")])
14084
14085 (define_insn "*ctrdi_internal2"
14086 [(set (pc)
14087 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14088 (const_int 1))
14089 (pc)
14090 (label_ref (match_operand 0 "" ""))))
14091 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14092 (plus:DI (match_dup 1)
14093 (const_int -1)))
14094 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14095 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14096 "TARGET_64BIT"
14097 "*
14098 {
14099 if (which_alternative != 0)
14100 return \"#\";
14101 else if (get_attr_length (insn) == 4)
14102 return \"bdz %l0\";
14103 else
14104 return \"{bdn|bdnz} $+8\;b %l0\";
14105 }"
14106 [(set_attr "type" "branch")
14107 (set_attr "length" "*,12,16,16")])
14108
14109 ;; Similar but use EQ
14110
14111 (define_insn "*ctrsi_internal5"
14112 [(set (pc)
14113 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14114 (const_int 1))
14115 (label_ref (match_operand 0 "" ""))
14116 (pc)))
14117 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14118 (plus:SI (match_dup 1)
14119 (const_int -1)))
14120 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14121 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14122 "TARGET_32BIT"
14123 "*
14124 {
14125 if (which_alternative != 0)
14126 return \"#\";
14127 else if (get_attr_length (insn) == 4)
14128 return \"bdz %l0\";
14129 else
14130 return \"{bdn|bdnz} $+8\;b %l0\";
14131 }"
14132 [(set_attr "type" "branch")
14133 (set_attr "length" "*,12,16,16")])
14134
14135 (define_insn "*ctrsi_internal6"
14136 [(set (pc)
14137 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14138 (const_int 1))
14139 (pc)
14140 (label_ref (match_operand 0 "" ""))))
14141 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14142 (plus:SI (match_dup 1)
14143 (const_int -1)))
14144 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14145 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14146 "TARGET_32BIT"
14147 "*
14148 {
14149 if (which_alternative != 0)
14150 return \"#\";
14151 else if (get_attr_length (insn) == 4)
14152 return \"{bdn|bdnz} %l0\";
14153 else
14154 return \"bdz $+8\;b %l0\";
14155 }"
14156 [(set_attr "type" "branch")
14157 (set_attr "length" "*,12,16,16")])
14158
14159 (define_insn "*ctrdi_internal5"
14160 [(set (pc)
14161 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14162 (const_int 1))
14163 (label_ref (match_operand 0 "" ""))
14164 (pc)))
14165 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14166 (plus:DI (match_dup 1)
14167 (const_int -1)))
14168 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14169 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14170 "TARGET_64BIT"
14171 "*
14172 {
14173 if (which_alternative != 0)
14174 return \"#\";
14175 else if (get_attr_length (insn) == 4)
14176 return \"bdz %l0\";
14177 else
14178 return \"{bdn|bdnz} $+8\;b %l0\";
14179 }"
14180 [(set_attr "type" "branch")
14181 (set_attr "length" "*,12,16,16")])
14182
14183 (define_insn "*ctrdi_internal6"
14184 [(set (pc)
14185 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14186 (const_int 1))
14187 (pc)
14188 (label_ref (match_operand 0 "" ""))))
14189 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14190 (plus:DI (match_dup 1)
14191 (const_int -1)))
14192 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14193 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14194 "TARGET_64BIT"
14195 "*
14196 {
14197 if (which_alternative != 0)
14198 return \"#\";
14199 else if (get_attr_length (insn) == 4)
14200 return \"{bdn|bdnz} %l0\";
14201 else
14202 return \"bdz $+8\;b %l0\";
14203 }"
14204 [(set_attr "type" "branch")
14205 (set_attr "length" "*,12,16,16")])
14206
14207 ;; Now the splitters if we could not allocate the CTR register
14208
14209 (define_split
14210 [(set (pc)
14211 (if_then_else (match_operator 2 "comparison_operator"
14212 [(match_operand:SI 1 "gpc_reg_operand" "")
14213 (const_int 1)])
14214 (match_operand 5 "" "")
14215 (match_operand 6 "" "")))
14216 (set (match_operand:SI 0 "gpc_reg_operand" "")
14217 (plus:SI (match_dup 1)
14218 (const_int -1)))
14219 (clobber (match_scratch:CC 3 ""))
14220 (clobber (match_scratch:SI 4 ""))]
14221 "TARGET_32BIT && reload_completed"
14222 [(parallel [(set (match_dup 3)
14223 (compare:CC (plus:SI (match_dup 1)
14224 (const_int -1))
14225 (const_int 0)))
14226 (set (match_dup 0)
14227 (plus:SI (match_dup 1)
14228 (const_int -1)))])
14229 (set (pc) (if_then_else (match_dup 7)
14230 (match_dup 5)
14231 (match_dup 6)))]
14232 "
14233 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14234 operands[3], const0_rtx); }")
14235
14236 (define_split
14237 [(set (pc)
14238 (if_then_else (match_operator 2 "comparison_operator"
14239 [(match_operand:SI 1 "gpc_reg_operand" "")
14240 (const_int 1)])
14241 (match_operand 5 "" "")
14242 (match_operand 6 "" "")))
14243 (set (match_operand:SI 0 "nonimmediate_operand" "")
14244 (plus:SI (match_dup 1) (const_int -1)))
14245 (clobber (match_scratch:CC 3 ""))
14246 (clobber (match_scratch:SI 4 ""))]
14247 "TARGET_32BIT && reload_completed
14248 && ! gpc_reg_operand (operands[0], SImode)"
14249 [(parallel [(set (match_dup 3)
14250 (compare:CC (plus:SI (match_dup 1)
14251 (const_int -1))
14252 (const_int 0)))
14253 (set (match_dup 4)
14254 (plus:SI (match_dup 1)
14255 (const_int -1)))])
14256 (set (match_dup 0)
14257 (match_dup 4))
14258 (set (pc) (if_then_else (match_dup 7)
14259 (match_dup 5)
14260 (match_dup 6)))]
14261 "
14262 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14263 operands[3], const0_rtx); }")
14264 (define_split
14265 [(set (pc)
14266 (if_then_else (match_operator 2 "comparison_operator"
14267 [(match_operand:DI 1 "gpc_reg_operand" "")
14268 (const_int 1)])
14269 (match_operand 5 "" "")
14270 (match_operand 6 "" "")))
14271 (set (match_operand:DI 0 "gpc_reg_operand" "")
14272 (plus:DI (match_dup 1)
14273 (const_int -1)))
14274 (clobber (match_scratch:CC 3 ""))
14275 (clobber (match_scratch:DI 4 ""))]
14276 "TARGET_64BIT && reload_completed"
14277 [(parallel [(set (match_dup 3)
14278 (compare:CC (plus:DI (match_dup 1)
14279 (const_int -1))
14280 (const_int 0)))
14281 (set (match_dup 0)
14282 (plus:DI (match_dup 1)
14283 (const_int -1)))])
14284 (set (pc) (if_then_else (match_dup 7)
14285 (match_dup 5)
14286 (match_dup 6)))]
14287 "
14288 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14289 operands[3], const0_rtx); }")
14290
14291 (define_split
14292 [(set (pc)
14293 (if_then_else (match_operator 2 "comparison_operator"
14294 [(match_operand:DI 1 "gpc_reg_operand" "")
14295 (const_int 1)])
14296 (match_operand 5 "" "")
14297 (match_operand 6 "" "")))
14298 (set (match_operand:DI 0 "nonimmediate_operand" "")
14299 (plus:DI (match_dup 1) (const_int -1)))
14300 (clobber (match_scratch:CC 3 ""))
14301 (clobber (match_scratch:DI 4 ""))]
14302 "TARGET_64BIT && reload_completed
14303 && ! gpc_reg_operand (operands[0], DImode)"
14304 [(parallel [(set (match_dup 3)
14305 (compare:CC (plus:DI (match_dup 1)
14306 (const_int -1))
14307 (const_int 0)))
14308 (set (match_dup 4)
14309 (plus:DI (match_dup 1)
14310 (const_int -1)))])
14311 (set (match_dup 0)
14312 (match_dup 4))
14313 (set (pc) (if_then_else (match_dup 7)
14314 (match_dup 5)
14315 (match_dup 6)))]
14316 "
14317 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14318 operands[3], const0_rtx); }")
14319 \f
14320 (define_insn "trap"
14321 [(trap_if (const_int 1) (const_int 0))]
14322 ""
14323 "{t 31,0,0|trap}")
14324
14325 (define_expand "conditional_trap"
14326 [(trap_if (match_operator 0 "trap_comparison_operator"
14327 [(match_dup 2) (match_dup 3)])
14328 (match_operand 1 "const_int_operand" ""))]
14329 ""
14330 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14331 operands[2] = rs6000_compare_op0;
14332 operands[3] = rs6000_compare_op1;")
14333
14334 (define_insn ""
14335 [(trap_if (match_operator 0 "trap_comparison_operator"
14336 [(match_operand:SI 1 "register_operand" "r")
14337 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14338 (const_int 0))]
14339 ""
14340 "{t|tw}%V0%I2 %1,%2")
14341
14342 (define_insn ""
14343 [(trap_if (match_operator 0 "trap_comparison_operator"
14344 [(match_operand:DI 1 "register_operand" "r")
14345 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14346 (const_int 0))]
14347 "TARGET_POWERPC64"
14348 "td%V0%I2 %1,%2")
14349 \f
14350 ;; Insns related to generating the function prologue and epilogue.
14351
14352 (define_expand "prologue"
14353 [(use (const_int 0))]
14354 "TARGET_SCHED_PROLOG"
14355 "
14356 {
14357 rs6000_emit_prologue ();
14358 DONE;
14359 }")
14360
14361 (define_insn "*movesi_from_cr_one"
14362 [(match_parallel 0 "mfcr_operation"
14363 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14364 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14365 (match_operand 3 "immediate_operand" "n")]
14366 UNSPEC_MOVESI_FROM_CR))])]
14367 "TARGET_MFCRF"
14368 "*
14369 {
14370 int mask = 0;
14371 int i;
14372 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14373 {
14374 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14375 operands[4] = GEN_INT (mask);
14376 output_asm_insn (\"mfcr %1,%4\", operands);
14377 }
14378 return \"\";
14379 }"
14380 [(set_attr "type" "mfcrf")])
14381
14382 (define_insn "movesi_from_cr"
14383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14384 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14385 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14386 UNSPEC_MOVESI_FROM_CR))]
14387 ""
14388 "mfcr %0"
14389 [(set_attr "type" "mfcr")])
14390
14391 (define_insn "*stmw"
14392 [(match_parallel 0 "stmw_operation"
14393 [(set (match_operand:SI 1 "memory_operand" "=m")
14394 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14395 "TARGET_MULTIPLE"
14396 "{stm|stmw} %2,%1")
14397
14398 (define_insn "*save_fpregs_si"
14399 [(match_parallel 0 "any_operand"
14400 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14401 (use (match_operand:SI 2 "call_operand" "s"))
14402 (set (match_operand:DF 3 "memory_operand" "=m")
14403 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14404 "TARGET_32BIT"
14405 "bl %z2"
14406 [(set_attr "type" "branch")
14407 (set_attr "length" "4")])
14408
14409 (define_insn "*save_fpregs_di"
14410 [(match_parallel 0 "any_operand"
14411 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14412 (use (match_operand:DI 2 "call_operand" "s"))
14413 (set (match_operand:DF 3 "memory_operand" "=m")
14414 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14415 "TARGET_64BIT"
14416 "bl %z2"
14417 [(set_attr "type" "branch")
14418 (set_attr "length" "4")])
14419
14420 ; These are to explain that changes to the stack pointer should
14421 ; not be moved over stores to stack memory.
14422 (define_insn "stack_tie"
14423 [(set (match_operand:BLK 0 "memory_operand" "+m")
14424 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14425 ""
14426 ""
14427 [(set_attr "length" "0")])
14428
14429
14430 (define_expand "epilogue"
14431 [(use (const_int 0))]
14432 "TARGET_SCHED_PROLOG"
14433 "
14434 {
14435 rs6000_emit_epilogue (FALSE);
14436 DONE;
14437 }")
14438
14439 ; On some processors, doing the mtcrf one CC register at a time is
14440 ; faster (like on the 604e). On others, doing them all at once is
14441 ; faster; for instance, on the 601 and 750.
14442
14443 (define_expand "movsi_to_cr_one"
14444 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14445 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14446 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14447 ""
14448 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14449
14450 (define_insn "*movsi_to_cr"
14451 [(match_parallel 0 "mtcrf_operation"
14452 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14453 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14454 (match_operand 3 "immediate_operand" "n")]
14455 UNSPEC_MOVESI_TO_CR))])]
14456 ""
14457 "*
14458 {
14459 int mask = 0;
14460 int i;
14461 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14462 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14463 operands[4] = GEN_INT (mask);
14464 return \"mtcrf %4,%2\";
14465 }"
14466 [(set_attr "type" "mtcr")])
14467
14468 (define_insn "*mtcrfsi"
14469 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14470 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14471 (match_operand 2 "immediate_operand" "n")]
14472 UNSPEC_MOVESI_TO_CR))]
14473 "GET_CODE (operands[0]) == REG
14474 && CR_REGNO_P (REGNO (operands[0]))
14475 && GET_CODE (operands[2]) == CONST_INT
14476 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14477 "mtcrf %R0,%1"
14478 [(set_attr "type" "mtcr")])
14479
14480 ; The load-multiple instructions have similar properties.
14481 ; Note that "load_multiple" is a name known to the machine-independent
14482 ; code that actually corresponds to the powerpc load-string.
14483
14484 (define_insn "*lmw"
14485 [(match_parallel 0 "lmw_operation"
14486 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14487 (match_operand:SI 2 "memory_operand" "m"))])]
14488 "TARGET_MULTIPLE"
14489 "{lm|lmw} %1,%2")
14490
14491 (define_insn "*return_internal_si"
14492 [(return)
14493 (use (match_operand:SI 0 "register_operand" "lc"))]
14494 "TARGET_32BIT"
14495 "b%T0"
14496 [(set_attr "type" "jmpreg")])
14497
14498 (define_insn "*return_internal_di"
14499 [(return)
14500 (use (match_operand:DI 0 "register_operand" "lc"))]
14501 "TARGET_64BIT"
14502 "b%T0"
14503 [(set_attr "type" "jmpreg")])
14504
14505 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14506 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14507
14508 (define_insn "*return_and_restore_fpregs_si"
14509 [(match_parallel 0 "any_operand"
14510 [(return)
14511 (use (match_operand:SI 1 "register_operand" "l"))
14512 (use (match_operand:SI 2 "call_operand" "s"))
14513 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14514 (match_operand:DF 4 "memory_operand" "m"))])]
14515 "TARGET_32BIT"
14516 "b %z2")
14517
14518 (define_insn "*return_and_restore_fpregs_di"
14519 [(match_parallel 0 "any_operand"
14520 [(return)
14521 (use (match_operand:DI 1 "register_operand" "l"))
14522 (use (match_operand:DI 2 "call_operand" "s"))
14523 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14524 (match_operand:DF 4 "memory_operand" "m"))])]
14525 "TARGET_64BIT"
14526 "b %z2")
14527
14528 ; This is used in compiling the unwind routines.
14529 (define_expand "eh_return"
14530 [(use (match_operand 0 "general_operand" ""))]
14531 ""
14532 "
14533 {
14534 if (TARGET_32BIT)
14535 emit_insn (gen_eh_set_lr_si (operands[0]));
14536 else
14537 emit_insn (gen_eh_set_lr_di (operands[0]));
14538 DONE;
14539 }")
14540
14541 ; We can't expand this before we know where the link register is stored.
14542 (define_insn "eh_set_lr_si"
14543 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14544 UNSPECV_EH_RR)
14545 (clobber (match_scratch:SI 1 "=&b"))]
14546 "TARGET_32BIT"
14547 "#")
14548
14549 (define_insn "eh_set_lr_di"
14550 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14551 UNSPECV_EH_RR)
14552 (clobber (match_scratch:DI 1 "=&b"))]
14553 "TARGET_64BIT"
14554 "#")
14555
14556 (define_split
14557 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14558 (clobber (match_scratch 1 ""))]
14559 "reload_completed"
14560 [(const_int 0)]
14561 "
14562 {
14563 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14564 DONE;
14565 }")
14566
14567 (define_insn "prefetch"
14568 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14569 (match_operand:SI 1 "const_int_operand" "n")
14570 (match_operand:SI 2 "const_int_operand" "n"))]
14571 "TARGET_POWERPC"
14572 "*
14573 {
14574 if (GET_CODE (operands[0]) == REG)
14575 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14576 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14577 }"
14578 [(set_attr "type" "load")])
14579
14580 (include "altivec.md")
14581 (include "spe.md")