1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; `unspec' values used in rs6000.md:
27 ;; 0 frsp for POWER machines
29 ;; 5 used to tie the stack contents and the stack pointer
30 ;; 6 address of a word pointing to the TOC
31 ;; 7 address of the TOC (more-or-less)
38 ;; Define an insn type attribute. This is used in function unit delay
40 (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec"
41 (const_string "integer"))
44 ; '(pc)' in the following doesn't include the instruction itself; it is
45 ; calculated as if the instruction had zero size.
46 (define_attr "length" ""
47 (if_then_else (eq_attr "type" "branch")
48 (if_then_else (and (ge (minus (match_dup 0) (pc))
50 (lt (minus (match_dup 0) (pc))
56 ;; Processor type -- this attribute must exactly match the processor_type
57 ;; enumeration in rs6000.h.
59 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"
60 (const (symbol_ref "rs6000_cpu_attr")))
62 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
63 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
65 ; Load/Store Unit -- pure PowerPC only
66 ; (POWER and 601 use Integer Unit)
67 (define_function_unit "lsu" 1 0
68 (and (eq_attr "type" "load")
69 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
72 (define_function_unit "lsu" 1 0
73 (and (eq_attr "type" "load,vecload")
74 (eq_attr "cpu" "ppc7450"))
77 (define_function_unit "lsu" 1 0
78 (and (eq_attr "type" "store,fpstore")
79 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630"))
82 (define_function_unit "lsu" 1 0
83 (and (eq_attr "type" "store,fpstore")
84 (eq_attr "cpu" "ppc750,ppc7400"))
87 (define_function_unit "lsu" 1 0
88 (and (eq_attr "type" "store,vecstore")
89 (eq_attr "cpu" "ppc7450"))
92 (define_function_unit "lsu" 1 0
93 (and (eq_attr "type" "fpstore")
94 (eq_attr "cpu" "ppc7450"))
97 (define_function_unit "lsu" 1 0
98 (and (eq_attr "type" "fpload")
99 (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400"))
102 (define_function_unit "lsu" 1 0
103 (and (eq_attr "type" "fpload")
104 (eq_attr "cpu" "ppc7450"))
107 (define_function_unit "lsu" 1 0
108 (and (eq_attr "type" "fpload")
109 (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
112 (define_function_unit "iu" 1 0
113 (and (eq_attr "type" "load")
114 (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
117 (define_function_unit "iu" 1 0
118 (and (eq_attr "type" "store,fpstore")
119 (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
122 (define_function_unit "fpu" 1 0
123 (and (eq_attr "type" "fpstore")
124 (eq_attr "cpu" "rios1,ppc601"))
127 (define_function_unit "iu" 1 0
128 (and (eq_attr "type" "fpload")
129 (eq_attr "cpu" "rios1"))
132 (define_function_unit "iu" 1 0
133 (and (eq_attr "type" "fpload")
134 (eq_attr "cpu" "ppc601"))
137 (define_function_unit "iu2" 2 0
138 (and (eq_attr "type" "load,fpload")
139 (eq_attr "cpu" "rios2"))
142 (define_function_unit "iu2" 2 0
143 (and (eq_attr "type" "store,fpstore")
144 (eq_attr "cpu" "rios2"))
147 ; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
148 (define_function_unit "iu" 1 0
149 (and (eq_attr "type" "integer")
150 (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603"))
153 (define_function_unit "iu" 1 0
154 (and (eq_attr "type" "cr_logical")
155 (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601"))
158 (define_function_unit "iu" 1 0
159 (and (eq_attr "type" "imul,imul2,imul3")
160 (eq_attr "cpu" "ppc403"))
163 (define_function_unit "iu" 1 0
164 (and (eq_attr "type" "imul")
165 (eq_attr "cpu" "ppc405"))
168 (define_function_unit "iu" 1 0
169 (and (eq_attr "type" "imul2,imul3")
170 (eq_attr "cpu" "ppc405"))
173 (define_function_unit "iu" 1 0
174 (and (eq_attr "type" "imul")
175 (eq_attr "cpu" "rios1"))
178 (define_function_unit "iu" 1 0
179 (and (eq_attr "type" "imul2")
180 (eq_attr "cpu" "rios1"))
183 (define_function_unit "iu" 1 0
184 (and (eq_attr "type" "imul3")
185 (eq_attr "cpu" "rios1"))
188 (define_function_unit "iu" 1 0
189 (and (eq_attr "type" "imul,imul2,imul3")
190 (eq_attr "cpu" "ppc601,ppc603"))
193 (define_function_unit "iu" 1 0
194 (and (eq_attr "type" "imul")
195 (eq_attr "cpu" "rs64a"))
198 (define_function_unit "iu" 1 0
199 (and (eq_attr "type" "imul2")
200 (eq_attr "cpu" "rs64a"))
203 (define_function_unit "iu" 1 0
204 (and (eq_attr "type" "imul3")
205 (eq_attr "cpu" "rs64a"))
208 (define_function_unit "iu" 1 0
209 (and (eq_attr "type" "lmul")
210 (eq_attr "cpu" "rs64a"))
213 (define_function_unit "iu" 1 0
214 (and (eq_attr "type" "idiv")
215 (eq_attr "cpu" "rios1"))
218 (define_function_unit "iu" 1 0
219 (and (eq_attr "type" "idiv")
220 (eq_attr "cpu" "rs64a"))
223 (define_function_unit "iu" 1 0
224 (and (eq_attr "type" "ldiv")
225 (eq_attr "cpu" "rs64a"))
228 (define_function_unit "iu" 1 0
229 (and (eq_attr "type" "idiv")
230 (eq_attr "cpu" "ppc403"))
233 (define_function_unit "iu" 1 0
234 (and (eq_attr "type" "idiv")
235 (eq_attr "cpu" "ppc405"))
238 (define_function_unit "iu" 1 0
239 (and (eq_attr "type" "idiv")
240 (eq_attr "cpu" "ppc601"))
243 (define_function_unit "iu" 1 0
244 (and (eq_attr "type" "idiv")
245 (eq_attr "cpu" "ppc603"))
248 ; RIOS2 has two integer units: a primary one which can perform all
249 ; operations and a secondary one which is fed in lock step with the first
250 ; and can perform "simple" integer operations.
251 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
252 ; for the complex insns.
253 (define_function_unit "iu2" 2 0
254 (and (eq_attr "type" "integer")
255 (eq_attr "cpu" "rios2"))
258 (define_function_unit "iu2" 2 0
259 (and (eq_attr "type" "imul,imul2,imul3")
260 (eq_attr "cpu" "rios2"))
263 (define_function_unit "iu2" 2 0
264 (and (eq_attr "type" "idiv")
265 (eq_attr "cpu" "rios2"))
268 (define_function_unit "imuldiv" 1 0
269 (and (eq_attr "type" "imul,imul2,imul3")
270 (eq_attr "cpu" "rios2"))
273 (define_function_unit "imuldiv" 1 0
274 (and (eq_attr "type" "idiv")
275 (eq_attr "cpu" "rios2"))
278 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
279 ; Divide latency varies greatly from 2-11, use 6 as average
280 (define_function_unit "imuldiv" 1 0
281 (and (eq_attr "type" "imul,imul2,imul3")
282 (eq_attr "cpu" "mpccore"))
285 (define_function_unit "imuldiv" 1 0
286 (and (eq_attr "type" "idiv")
287 (eq_attr "cpu" "mpccore"))
290 ; PPC604{,e} has two units that perform integer operations
291 ; and one unit for divide/multiply operations (and move
293 (define_function_unit "iu2" 2 0
294 (and (eq_attr "type" "integer")
295 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
298 (define_function_unit "imuldiv" 1 0
299 (and (eq_attr "type" "imul,imul2,imul3")
300 (eq_attr "cpu" "ppc604"))
303 (define_function_unit "imuldiv" 1 0
304 (and (eq_attr "type" "imul,imul2,imul3")
305 (eq_attr "cpu" "ppc604e"))
308 (define_function_unit "imuldiv" 1 0
309 (and (eq_attr "type" "imul")
310 (eq_attr "cpu" "ppc620,ppc630"))
313 (define_function_unit "imuldiv" 1 0
314 (and (eq_attr "type" "imul2")
315 (eq_attr "cpu" "ppc620,ppc630"))
318 (define_function_unit "imuldiv" 1 0
319 (and (eq_attr "type" "imul3")
320 (eq_attr "cpu" "ppc620,ppc630"))
323 (define_function_unit "imuldiv" 1 0
324 (and (eq_attr "type" "lmul")
325 (eq_attr "cpu" "ppc620,ppc630"))
328 (define_function_unit "imuldiv" 1 0
329 (and (eq_attr "type" "idiv")
330 (eq_attr "cpu" "ppc604,ppc604e"))
333 (define_function_unit "imuldiv" 1 0
334 (and (eq_attr "type" "idiv")
335 (eq_attr "cpu" "ppc620"))
338 (define_function_unit "imuldiv" 1 0
339 (and (eq_attr "type" "idiv")
340 (eq_attr "cpu" "ppc630"))
343 (define_function_unit "imuldiv" 1 0
344 (and (eq_attr "type" "ldiv")
345 (eq_attr "cpu" "ppc620,ppc630"))
348 ; PPC7450 has 3 integer units (for most integer insns) and one mul/div
349 ; unit, which also does CR-logical insns and move to/from SPR.
350 ; It also has 4 vector units, one for each type of vector instruction.
351 ; However, we can only dispatch 2 instructions per cycle.
352 ; We model this as saying that dispatching two of the same type of instruction
353 ; in a row incurs a single cycle delay.
354 (define_function_unit "iu3" 3 0
355 (and (eq_attr "type" "integer")
356 (eq_attr "cpu" "ppc7450"))
359 (define_function_unit "imuldiv" 1 0
360 (and (eq_attr "type" "imul")
361 (eq_attr "cpu" "ppc7450"))
364 (define_function_unit "imuldiv" 1 0
365 (and (eq_attr "type" "imul2,imul3")
366 (eq_attr "cpu" "ppc7450"))
369 (define_function_unit "imuldiv" 1 0
370 (and (eq_attr "type" "idiv")
371 (eq_attr "cpu" "ppc7450"))
374 (define_function_unit "imuldiv" 1 0
375 (and (eq_attr "type" "cr_logical")
376 (eq_attr "cpu" "ppc7450"))
378 (define_function_unit "vec_alu2" 2 0
379 (and (eq_attr "type" "vecsimple")
380 (eq_attr "cpu" "ppc7450"))
381 1 2 [(eq_attr "type" "vecsimple")])
382 (define_function_unit "vec_alu2" 2 0
383 (and (eq_attr "type" "vecsimple")
384 (eq_attr "cpu" "ppc7450"))
385 1 1 [(eq_attr "type" "!vecsimple")])
386 (define_function_unit "vec_alu2" 2 0
387 (and (eq_attr "type" "veccomplex")
388 (eq_attr "cpu" "ppc7450"))
389 4 2 [(eq_attr "type" "veccomplex")])
390 (define_function_unit "vec_alu2" 2 0
391 (and (eq_attr "type" "veccomplex")
392 (eq_attr "cpu" "ppc7450"))
393 4 1 [(eq_attr "type" "!veccomplex")])
394 (define_function_unit "vec_alu2" 2 0
395 (and (eq_attr "type" "veccmp")
396 (eq_attr "cpu" "ppc7450"))
397 2 2 [(eq_attr "type" "veccmp")])
398 (define_function_unit "vec_alu2" 2 0
399 (and (eq_attr "type" "veccmp")
400 (eq_attr "cpu" "ppc7450"))
401 2 1 [(eq_attr "type" "!veccmp")])
402 (define_function_unit "vec_alu2" 2 0
403 (and (eq_attr "type" "vecfloat")
404 (eq_attr "cpu" "ppc7450"))
405 4 2 [(eq_attr "type" "vecfloat")])
406 (define_function_unit "vec_alu2" 2 0
407 (and (eq_attr "type" "vecfloat")
408 (eq_attr "cpu" "ppc7450"))
409 4 1 [(eq_attr "type" "!vecfloat")])
410 (define_function_unit "vec_alu2" 2 0
411 (and (eq_attr "type" "vecperm")
412 (eq_attr "cpu" "ppc7450"))
413 2 2 [(eq_attr "type" "vecperm")])
414 (define_function_unit "vec_alu2" 2 0
415 (and (eq_attr "type" "vecperm")
416 (eq_attr "cpu" "ppc7450"))
417 2 1 [(eq_attr "type" "!vecperm")])
419 ; PPC750 has two integer units: a primary one which can perform all
420 ; operations and a secondary one which is fed in lock step with the first
421 ; and can perform "simple" integer operations.
422 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
423 ; for the complex insns.
424 (define_function_unit "iu2" 2 0
425 (and (eq_attr "type" "integer")
426 (eq_attr "cpu" "ppc750,ppc7400"))
429 (define_function_unit "iu2" 2 0
430 (and (eq_attr "type" "imul")
431 (eq_attr "cpu" "ppc750,ppc7400"))
434 (define_function_unit "iu2" 2 0
435 (and (eq_attr "type" "imul2")
436 (eq_attr "cpu" "ppc750,ppc7400"))
439 (define_function_unit "iu2" 2 0
440 (and (eq_attr "type" "imul3")
441 (eq_attr "cpu" "ppc750,ppc7400"))
444 (define_function_unit "iu2" 2 0
445 (and (eq_attr "type" "idiv")
446 (eq_attr "cpu" "ppc750,ppc7400"))
449 (define_function_unit "imuldiv" 1 0
450 (and (eq_attr "type" "imul")
451 (eq_attr "cpu" "ppc750,ppc7400"))
454 (define_function_unit "imuldiv" 1 0
455 (and (eq_attr "type" "imul2")
456 (eq_attr "cpu" "ppc750,ppc7400"))
459 (define_function_unit "imuldiv" 1 0
460 (and (eq_attr "type" "imul3")
461 (eq_attr "cpu" "ppc750,ppc7400"))
464 (define_function_unit "imuldiv" 1 0
465 (and (eq_attr "type" "idiv")
466 (eq_attr "cpu" "ppc750,ppc7400"))
469 ; CR-logical operations are execute-serialized, that is they don't
470 ; start (and block the function unit) until all preceding operations
471 ; have finished. They don't block dispatch of other insns, though.
472 ; I've imitated this by giving them longer latency.
473 (define_function_unit "sru" 1 0
474 (and (eq_attr "type" "cr_logical")
475 (eq_attr "cpu" "ppc603,ppc750,ppc7400"))
478 ; compare is done on integer unit, but feeds insns which
479 ; execute on the branch unit.
480 (define_function_unit "iu" 1 0
481 (and (eq_attr "type" "compare")
482 (eq_attr "cpu" "rios1"))
485 (define_function_unit "iu" 1 0
486 (and (eq_attr "type" "delayed_compare")
487 (eq_attr "cpu" "rios1"))
490 (define_function_unit "iu" 1 0
491 (and (eq_attr "type" "compare,delayed_compare")
492 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
495 ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare
496 ; and a following branch, to reduce mispredicts
497 (define_function_unit "iu3" 3 0
498 (and (eq_attr "type" "compare,delayed_compare")
499 (eq_attr "cpu" "ppc7450"))
502 (define_function_unit "iu2" 2 0
503 (and (eq_attr "type" "compare,delayed_compare")
504 (eq_attr "cpu" "rios2"))
507 (define_function_unit "iu2" 2 0
508 (and (eq_attr "type" "compare,delayed_compare")
509 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
512 ; fp compare uses fp unit
513 (define_function_unit "fpu" 1 0
514 (and (eq_attr "type" "fpcompare")
515 (eq_attr "cpu" "rios1"))
518 ; rios1 and rios2 have different fpcompare delays
519 (define_function_unit "fpu2" 2 0
520 (and (eq_attr "type" "fpcompare")
521 (eq_attr "cpu" "rios2,ppc630"))
524 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
526 ; here we do not define delays, just occupy the unit. The dependencies
527 ; will be assigned by the fpcompare definition in the fpu.
528 (define_function_unit "iu" 1 0
529 (and (eq_attr "type" "fpcompare")
530 (eq_attr "cpu" "ppc601,ppc603"))
533 ; fp compare uses fp unit
534 (define_function_unit "fpu" 1 0
535 (and (eq_attr "type" "fpcompare")
536 (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
539 (define_function_unit "fpu" 1 0
540 (and (eq_attr "type" "fpcompare")
541 (eq_attr "cpu" "ppc750,ppc7400,ppc7450"))
544 (define_function_unit "fpu" 1 0
545 (and (eq_attr "type" "fpcompare")
546 (eq_attr "cpu" "mpccore"))
549 (define_function_unit "bpu" 1 0
550 (and (eq_attr "type" "mtjmpr")
551 (eq_attr "cpu" "rios1,rios2,rs64a"))
554 (define_function_unit "bpu" 1 0
555 (and (eq_attr "type" "mtjmpr")
556 (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
559 (define_function_unit "sru" 1 0
560 (and (eq_attr "type" "mtjmpr")
561 (eq_attr "cpu" "ppc750,ppc7400"))
564 (define_function_unit "imuldiv" 1 0
565 (and (eq_attr "type" "mtjmpr")
566 (eq_attr "cpu" "ppc7450"))
569 (define_function_unit "bpu" 1 0
570 (and (eq_attr "type" "cr_logical")
571 (eq_attr "cpu" "rios1,rios2,ppc604"))
574 (define_function_unit "cru" 1 0
575 (and (eq_attr "type" "cr_logical")
576 (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a"))
579 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
580 (define_function_unit "bpu" 1 0
581 (eq_attr "type" "jmpreg")
584 (define_function_unit "bpu" 1 0
585 (eq_attr "type" "branch")
588 ; Floating Point Unit
589 (define_function_unit "fpu" 1 0
590 (and (eq_attr "type" "fp,dmul")
591 (eq_attr "cpu" "rios1"))
594 (define_function_unit "fpu" 1 0
595 (and (eq_attr "type" "fp")
596 (eq_attr "cpu" "rs64a,mpccore"))
599 (define_function_unit "fpu" 1 0
600 (and (eq_attr "type" "fp")
601 (eq_attr "cpu" "ppc601"))
604 (define_function_unit "fpu" 1 0
605 (and (eq_attr "type" "fp")
606 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400"))
609 (define_function_unit "fpu" 1 0
610 (and (eq_attr "type" "fp,dmul")
611 (eq_attr "cpu" "ppc7450"))
614 (define_function_unit "fpu" 1 0
615 (and (eq_attr "type" "dmul")
616 (eq_attr "cpu" "rs64a"))
619 (define_function_unit "fpu" 1 0
620 (and (eq_attr "type" "dmul")
621 (eq_attr "cpu" "mpccore"))
624 (define_function_unit "fpu" 1 0
625 (and (eq_attr "type" "dmul")
626 (eq_attr "cpu" "ppc601"))
630 (define_function_unit "fpu" 1 0
631 (and (eq_attr "type" "dmul")
632 (eq_attr "cpu" "ppc603,ppc750"))
635 (define_function_unit "fpu" 1 0
636 (and (eq_attr "type" "dmul")
637 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400"))
640 (define_function_unit "fpu" 1 0
641 (and (eq_attr "type" "sdiv,ddiv")
642 (eq_attr "cpu" "rios1"))
645 (define_function_unit "fpu" 1 0
646 (and (eq_attr "type" "sdiv")
647 (eq_attr "cpu" "rs64a"))
650 (define_function_unit "fpu" 1 0
651 (and (eq_attr "type" "sdiv")
652 (eq_attr "cpu" "ppc601,ppc750,ppc7400"))
655 (define_function_unit "fpu" 1 0
656 (and (eq_attr "type" "sdiv")
657 (eq_attr "cpu" "ppc7450"))
660 (define_function_unit "fpu" 1 0
661 (and (eq_attr "type" "sdiv")
662 (eq_attr "cpu" "mpccore"))
665 (define_function_unit "fpu" 1 0
666 (and (eq_attr "type" "sdiv")
667 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
670 (define_function_unit "fpu" 1 0
671 (and (eq_attr "type" "ddiv")
672 (eq_attr "cpu" "mpccore"))
675 (define_function_unit "fpu" 1 0
676 (and (eq_attr "type" "ddiv")
677 (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400"))
680 (define_function_unit "fpu" 1 0
681 (and (eq_attr "type" "ddiv")
682 (eq_attr "cpu" "ppc7450"))
685 (define_function_unit "fpu" 1 0
686 (and (eq_attr "type" "ddiv")
687 (eq_attr "cpu" "ppc603"))
690 (define_function_unit "fpu" 1 0
691 (and (eq_attr "type" "ssqrt")
692 (eq_attr "cpu" "ppc620"))
695 (define_function_unit "fpu" 1 0
696 (and (eq_attr "type" "dsqrt")
697 (eq_attr "cpu" "ppc620"))
700 ; RIOS2 has two symmetric FPUs.
701 (define_function_unit "fpu2" 2 0
702 (and (eq_attr "type" "fp")
703 (eq_attr "cpu" "rios2"))
706 (define_function_unit "fpu2" 2 0
707 (and (eq_attr "type" "fp")
708 (eq_attr "cpu" "ppc630"))
711 (define_function_unit "fpu2" 2 0
712 (and (eq_attr "type" "dmul")
713 (eq_attr "cpu" "rios2"))
716 (define_function_unit "fpu2" 2 0
717 (and (eq_attr "type" "dmul")
718 (eq_attr "cpu" "ppc630"))
721 (define_function_unit "fpu2" 2 0
722 (and (eq_attr "type" "sdiv,ddiv")
723 (eq_attr "cpu" "rios2"))
726 (define_function_unit "fpu2" 2 0
727 (and (eq_attr "type" "sdiv")
728 (eq_attr "cpu" "ppc630"))
731 (define_function_unit "fpu2" 2 0
732 (and (eq_attr "type" "ddiv")
733 (eq_attr "cpu" "ppc630"))
736 (define_function_unit "fpu2" 2 0
737 (and (eq_attr "type" "ssqrt,dsqrt")
738 (eq_attr "cpu" "rios2"))
741 (define_function_unit "fpu2" 2 0
742 (and (eq_attr "type" "ssqrt")
743 (eq_attr "cpu" "ppc630"))
746 (define_function_unit "fpu2" 2 0
747 (and (eq_attr "type" "dsqrt")
748 (eq_attr "cpu" "ppc630"))
752 ;; Start with fixed-point load and store insns. Here we put only the more
753 ;; complex forms. Basic data transfer is done later.
755 (define_expand "zero_extendqidi2"
756 [(set (match_operand:DI 0 "gpc_reg_operand" "")
757 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
762 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
763 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
768 [(set_attr "type" "load,*")])
771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
772 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
774 (clobber (match_scratch:DI 2 "=r,r"))]
779 [(set_attr "type" "compare")
780 (set_attr "length" "4,8")])
783 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
784 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
786 (clobber (match_scratch:DI 2 ""))]
787 "TARGET_POWERPC64 && reload_completed"
789 (zero_extend:DI (match_dup 1)))
791 (compare:CC (match_dup 2)
796 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
797 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
799 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
800 (zero_extend:DI (match_dup 1)))]
805 [(set_attr "type" "compare")
806 (set_attr "length" "4,8")])
809 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
810 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
812 (set (match_operand:DI 0 "gpc_reg_operand" "")
813 (zero_extend:DI (match_dup 1)))]
814 "TARGET_POWERPC64 && reload_completed"
816 (zero_extend:DI (match_dup 1)))
818 (compare:CC (match_dup 0)
822 (define_insn "extendqidi2"
823 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
824 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
829 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
830 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
832 (clobber (match_scratch:DI 2 "=r,r"))]
837 [(set_attr "type" "compare")
838 (set_attr "length" "4,8")])
841 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
842 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
844 (clobber (match_scratch:DI 2 ""))]
845 "TARGET_POWERPC64 && reload_completed"
847 (sign_extend:DI (match_dup 1)))
849 (compare:CC (match_dup 2)
854 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
855 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
857 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
858 (sign_extend:DI (match_dup 1)))]
863 [(set_attr "type" "compare")
864 (set_attr "length" "4,8")])
867 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
868 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
870 (set (match_operand:DI 0 "gpc_reg_operand" "")
871 (sign_extend:DI (match_dup 1)))]
872 "TARGET_POWERPC64 && reload_completed"
874 (sign_extend:DI (match_dup 1)))
876 (compare:CC (match_dup 0)
880 (define_expand "zero_extendhidi2"
881 [(set (match_operand:DI 0 "gpc_reg_operand" "")
882 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
887 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
888 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
893 [(set_attr "type" "load,*")])
896 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
897 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
899 (clobber (match_scratch:DI 2 "=r,r"))]
904 [(set_attr "type" "compare")
905 (set_attr "length" "4,8")])
908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
909 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
911 (clobber (match_scratch:DI 2 ""))]
912 "TARGET_POWERPC64 && reload_completed"
914 (zero_extend:DI (match_dup 1)))
916 (compare:CC (match_dup 2)
921 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
922 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
924 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
925 (zero_extend:DI (match_dup 1)))]
930 [(set_attr "type" "compare")
931 (set_attr "length" "4,8")])
934 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
935 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
937 (set (match_operand:DI 0 "gpc_reg_operand" "")
938 (zero_extend:DI (match_dup 1)))]
939 "TARGET_POWERPC64 && reload_completed"
941 (zero_extend:DI (match_dup 1)))
943 (compare:CC (match_dup 0)
947 (define_expand "extendhidi2"
948 [(set (match_operand:DI 0 "gpc_reg_operand" "")
949 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
954 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
955 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
960 [(set_attr "type" "load,*")])
963 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
964 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
966 (clobber (match_scratch:DI 2 "=r,r"))]
971 [(set_attr "type" "compare")
972 (set_attr "length" "4,8")])
975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
976 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
978 (clobber (match_scratch:DI 2 ""))]
979 "TARGET_POWERPC64 && reload_completed"
981 (sign_extend:DI (match_dup 1)))
983 (compare:CC (match_dup 2)
988 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
989 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
991 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
992 (sign_extend:DI (match_dup 1)))]
997 [(set_attr "type" "compare")
998 (set_attr "length" "4,8")])
1001 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1002 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
1004 (set (match_operand:DI 0 "gpc_reg_operand" "")
1005 (sign_extend:DI (match_dup 1)))]
1006 "TARGET_POWERPC64 && reload_completed"
1008 (sign_extend:DI (match_dup 1)))
1010 (compare:CC (match_dup 0)
1014 (define_expand "zero_extendsidi2"
1015 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1016 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
1021 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1022 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
1027 [(set_attr "type" "load,*")])
1030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1031 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1033 (clobber (match_scratch:DI 2 "=r,r"))]
1038 [(set_attr "type" "compare")
1039 (set_attr "length" "4,8")])
1042 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1043 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1045 (clobber (match_scratch:DI 2 ""))]
1046 "TARGET_POWERPC64 && reload_completed"
1048 (zero_extend:DI (match_dup 1)))
1050 (compare:CC (match_dup 2)
1055 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1056 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1058 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1059 (zero_extend:DI (match_dup 1)))]
1064 [(set_attr "type" "compare")
1065 (set_attr "length" "4,8")])
1068 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1069 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1071 (set (match_operand:DI 0 "gpc_reg_operand" "")
1072 (zero_extend:DI (match_dup 1)))]
1073 "TARGET_POWERPC64 && reload_completed"
1075 (zero_extend:DI (match_dup 1)))
1077 (compare:CC (match_dup 0)
1081 (define_expand "extendsidi2"
1082 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1083 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
1088 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1089 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
1094 [(set_attr "type" "load,*")])
1097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1098 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1100 (clobber (match_scratch:DI 2 "=r,r"))]
1105 [(set_attr "type" "compare")
1106 (set_attr "length" "4,8")])
1109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1110 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1112 (clobber (match_scratch:DI 2 ""))]
1113 "TARGET_POWERPC64 && reload_completed"
1115 (sign_extend:DI (match_dup 1)))
1117 (compare:CC (match_dup 2)
1122 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1123 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1125 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1126 (sign_extend:DI (match_dup 1)))]
1131 [(set_attr "type" "compare")
1132 (set_attr "length" "4,8")])
1135 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1136 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1138 (set (match_operand:DI 0 "gpc_reg_operand" "")
1139 (sign_extend:DI (match_dup 1)))]
1140 "TARGET_POWERPC64 && reload_completed"
1142 (sign_extend:DI (match_dup 1)))
1144 (compare:CC (match_dup 0)
1148 (define_expand "zero_extendqisi2"
1149 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1150 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1156 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1160 {rlinm|rlwinm} %0,%1,0,0xff"
1161 [(set_attr "type" "load,*")])
1164 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1165 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1167 (clobber (match_scratch:SI 2 "=r,r"))]
1170 {andil.|andi.} %2,%1,0xff
1172 [(set_attr "type" "compare")
1173 (set_attr "length" "4,8")])
1176 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1177 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1179 (clobber (match_scratch:SI 2 ""))]
1182 (zero_extend:SI (match_dup 1)))
1184 (compare:CC (match_dup 2)
1189 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1190 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1193 (zero_extend:SI (match_dup 1)))]
1196 {andil.|andi.} %0,%1,0xff
1198 [(set_attr "type" "compare")
1199 (set_attr "length" "4,8")])
1202 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1203 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1205 (set (match_operand:SI 0 "gpc_reg_operand" "")
1206 (zero_extend:SI (match_dup 1)))]
1209 (zero_extend:SI (match_dup 1)))
1211 (compare:CC (match_dup 0)
1215 (define_expand "extendqisi2"
1216 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1217 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1222 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
1223 else if (TARGET_POWER)
1224 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
1226 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
1230 (define_insn "extendqisi2_ppc"
1231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1232 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1238 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1240 (clobber (match_scratch:SI 2 "=r,r"))]
1245 [(set_attr "type" "compare")
1246 (set_attr "length" "4,8")])
1249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1250 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1252 (clobber (match_scratch:SI 2 ""))]
1253 "TARGET_POWERPC && reload_completed"
1255 (sign_extend:SI (match_dup 1)))
1257 (compare:CC (match_dup 2)
1262 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1263 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1265 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1266 (sign_extend:SI (match_dup 1)))]
1271 [(set_attr "type" "compare")
1272 (set_attr "length" "4,8")])
1275 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1276 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1278 (set (match_operand:SI 0 "gpc_reg_operand" "")
1279 (sign_extend:SI (match_dup 1)))]
1280 "TARGET_POWERPC && reload_completed"
1282 (sign_extend:SI (match_dup 1)))
1284 (compare:CC (match_dup 0)
1288 (define_expand "extendqisi2_power"
1289 [(parallel [(set (match_dup 2)
1290 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1292 (clobber (scratch:SI))])
1293 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1294 (ashiftrt:SI (match_dup 2)
1296 (clobber (scratch:SI))])]
1299 { operands[1] = gen_lowpart (SImode, operands[1]);
1300 operands[2] = gen_reg_rtx (SImode); }")
1302 (define_expand "extendqisi2_no_power"
1304 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1306 (set (match_operand:SI 0 "gpc_reg_operand" "")
1307 (ashiftrt:SI (match_dup 2)
1309 "! TARGET_POWER && ! TARGET_POWERPC"
1311 { operands[1] = gen_lowpart (SImode, operands[1]);
1312 operands[2] = gen_reg_rtx (SImode); }")
1314 (define_expand "zero_extendqihi2"
1315 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1316 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1321 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1322 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1326 {rlinm|rlwinm} %0,%1,0,0xff"
1327 [(set_attr "type" "load,*")])
1330 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1331 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1333 (clobber (match_scratch:HI 2 "=r,r"))]
1336 {andil.|andi.} %2,%1,0xff
1338 [(set_attr "type" "compare")
1339 (set_attr "length" "4,8")])
1342 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1343 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1345 (clobber (match_scratch:HI 2 ""))]
1348 (zero_extend:HI (match_dup 1)))
1350 (compare:CC (match_dup 2)
1355 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1356 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1358 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1359 (zero_extend:HI (match_dup 1)))]
1362 {andil.|andi.} %0,%1,0xff
1364 [(set_attr "type" "compare")
1365 (set_attr "length" "4,8")])
1368 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1369 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1371 (set (match_operand:HI 0 "gpc_reg_operand" "")
1372 (zero_extend:HI (match_dup 1)))]
1375 (zero_extend:HI (match_dup 1)))
1377 (compare:CC (match_dup 0)
1381 (define_expand "extendqihi2"
1382 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
1383 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1388 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
1389 else if (TARGET_POWER)
1390 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
1392 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
1396 (define_insn "extendqihi2_ppc"
1397 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1398 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1404 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1406 (clobber (match_scratch:HI 2 "=r,r"))]
1411 [(set_attr "type" "compare")
1412 (set_attr "length" "4,8")])
1415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1416 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1418 (clobber (match_scratch:HI 2 ""))]
1419 "TARGET_POWERPC && reload_completed"
1421 (sign_extend:HI (match_dup 1)))
1423 (compare:CC (match_dup 2)
1428 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1429 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1431 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1432 (sign_extend:HI (match_dup 1)))]
1437 [(set_attr "type" "compare")
1438 (set_attr "length" "4,8")])
1441 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1442 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1444 (set (match_operand:HI 0 "gpc_reg_operand" "")
1445 (sign_extend:HI (match_dup 1)))]
1446 "TARGET_POWERPC && reload_completed"
1448 (sign_extend:HI (match_dup 1)))
1450 (compare:CC (match_dup 0)
1454 (define_expand "extendqihi2_power"
1455 [(parallel [(set (match_dup 2)
1456 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1458 (clobber (scratch:SI))])
1459 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1460 (ashiftrt:SI (match_dup 2)
1462 (clobber (scratch:SI))])]
1465 { operands[0] = gen_lowpart (SImode, operands[0]);
1466 operands[1] = gen_lowpart (SImode, operands[1]);
1467 operands[2] = gen_reg_rtx (SImode); }")
1469 (define_expand "extendqihi2_no_power"
1471 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1473 (set (match_operand:HI 0 "gpc_reg_operand" "")
1474 (ashiftrt:SI (match_dup 2)
1476 "! TARGET_POWER && ! TARGET_POWERPC"
1478 { operands[0] = gen_lowpart (SImode, operands[0]);
1479 operands[1] = gen_lowpart (SImode, operands[1]);
1480 operands[2] = gen_reg_rtx (SImode); }")
1482 (define_expand "zero_extendhisi2"
1483 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1484 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1490 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1494 {rlinm|rlwinm} %0,%1,0,0xffff"
1495 [(set_attr "type" "load,*")])
1498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1499 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1501 (clobber (match_scratch:SI 2 "=r,r"))]
1504 {andil.|andi.} %2,%1,0xffff
1506 [(set_attr "type" "compare")
1507 (set_attr "length" "4,8")])
1510 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1511 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1513 (clobber (match_scratch:SI 2 ""))]
1516 (zero_extend:SI (match_dup 1)))
1518 (compare:CC (match_dup 2)
1523 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1524 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1526 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1527 (zero_extend:SI (match_dup 1)))]
1530 {andil.|andi.} %0,%1,0xffff
1532 [(set_attr "type" "compare")
1533 (set_attr "length" "4,8")])
1536 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1537 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1539 (set (match_operand:SI 0 "gpc_reg_operand" "")
1540 (zero_extend:SI (match_dup 1)))]
1543 (zero_extend:SI (match_dup 1)))
1545 (compare:CC (match_dup 0)
1549 (define_expand "extendhisi2"
1550 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1551 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1557 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1562 [(set_attr "type" "load,*")])
1565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1566 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1568 (clobber (match_scratch:SI 2 "=r,r"))]
1571 {exts.|extsh.} %2,%1
1573 [(set_attr "type" "compare")
1574 (set_attr "length" "4,8")])
1577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1578 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1580 (clobber (match_scratch:SI 2 ""))]
1583 (sign_extend:SI (match_dup 1)))
1585 (compare:CC (match_dup 2)
1590 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1591 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1594 (sign_extend:SI (match_dup 1)))]
1597 {exts.|extsh.} %0,%1
1599 [(set_attr "type" "compare")
1600 (set_attr "length" "4,8")])
1603 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1604 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1606 (set (match_operand:SI 0 "gpc_reg_operand" "")
1607 (sign_extend:SI (match_dup 1)))]
1610 (sign_extend:SI (match_dup 1)))
1612 (compare:CC (match_dup 0)
1616 ;; Fixed-point arithmetic insns.
1618 ;; Discourage ai/addic because of carry but provide it in an alternative
1619 ;; allowing register zero as source.
1620 (define_expand "addsi3"
1621 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1622 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1623 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1627 if (GET_CODE (operands[2]) == CONST_INT
1628 && ! add_operand (operands[2], SImode))
1630 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1631 ? operands[0] : gen_reg_rtx (SImode));
1633 HOST_WIDE_INT val = INTVAL (operands[2]);
1634 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1635 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1637 /* The ordering here is important for the prolog expander.
1638 When space is allocated from the stack, adding 'low' first may
1639 produce a temporary deallocation (which would be bad). */
1640 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1641 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1646 (define_insn "*addsi3_internal1"
1647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1648 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1649 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1653 {cal %0,%2(%1)|addi %0,%1,%2}
1655 {cau|addis} %0,%1,%v2"
1656 [(set_attr "length" "4,4,4,4")])
1658 (define_insn "addsi3_high"
1659 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1660 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1661 (high:SI (match_operand 2 "" ""))))]
1662 "TARGET_MACHO && !TARGET_64BIT"
1663 "{cau|addis} %0,%1,ha16(%2)"
1664 [(set_attr "length" "4")])
1666 (define_insn "*addsi3_internal2"
1667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1668 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1669 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1671 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1672 "! TARGET_POWERPC64"
1674 {cax.|add.} %3,%1,%2
1675 {ai.|addic.} %3,%1,%2
1678 [(set_attr "type" "compare")
1679 (set_attr "length" "4,4,8,8")])
1682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1683 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1684 (match_operand:SI 2 "reg_or_short_operand" ""))
1686 (clobber (match_scratch:SI 3 ""))]
1687 "! TARGET_POWERPC64 && reload_completed"
1689 (plus:SI (match_dup 1)
1692 (compare:CC (match_dup 3)
1696 (define_insn "*addsi3_internal3"
1697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1698 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1699 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1702 (plus:SI (match_dup 1)
1704 "! TARGET_POWERPC64"
1706 {cax.|add.} %0,%1,%2
1707 {ai.|addic.} %0,%1,%2
1710 [(set_attr "type" "compare")
1711 (set_attr "length" "4,4,8,8")])
1714 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1715 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1716 (match_operand:SI 2 "reg_or_short_operand" ""))
1718 (set (match_operand:SI 0 "gpc_reg_operand" "")
1719 (plus:SI (match_dup 1) (match_dup 2)))]
1720 "! TARGET_POWERPC64 && reload_completed"
1722 (plus:SI (match_dup 1)
1725 (compare:CC (match_dup 0)
1729 ;; Split an add that we can't do in one insn into two insns, each of which
1730 ;; does one 16-bit part. This is used by combine. Note that the low-order
1731 ;; add should be last in case the result gets used in an address.
1734 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1735 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1736 (match_operand:SI 2 "non_add_cint_operand" "")))]
1738 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1739 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1742 HOST_WIDE_INT val = INTVAL (operands[2]);
1743 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1744 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1746 operands[3] = GEN_INT (rest);
1747 operands[4] = GEN_INT (low);
1750 (define_insn "one_cmplsi2"
1751 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1752 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1758 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1760 (clobber (match_scratch:SI 2 "=r,r"))]
1761 "! TARGET_POWERPC64"
1765 [(set_attr "type" "compare")
1766 (set_attr "length" "4,8")])
1769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1770 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1772 (clobber (match_scratch:SI 2 ""))]
1773 "! TARGET_POWERPC64 && reload_completed"
1775 (not:SI (match_dup 1)))
1777 (compare:CC (match_dup 2)
1782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1783 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1785 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1786 (not:SI (match_dup 1)))]
1787 "! TARGET_POWERPC64"
1791 [(set_attr "type" "compare")
1792 (set_attr "length" "4,8")])
1795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1796 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1798 (set (match_operand:SI 0 "gpc_reg_operand" "")
1799 (not:SI (match_dup 1)))]
1800 "! TARGET_POWERPC64 && reload_completed"
1802 (not:SI (match_dup 1)))
1804 (compare:CC (match_dup 0)
1809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1810 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1811 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1813 "{sf%I1|subf%I1c} %0,%2,%1")
1816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1817 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1818 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1825 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1826 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1827 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1829 (clobber (match_scratch:SI 3 "=r,r"))]
1832 {sf.|subfc.} %3,%2,%1
1834 [(set_attr "type" "compare")
1835 (set_attr "length" "4,8")])
1838 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1839 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1840 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1842 (clobber (match_scratch:SI 3 "=r,r"))]
1843 "TARGET_POWERPC && ! TARGET_POWERPC64"
1847 [(set_attr "type" "compare")
1848 (set_attr "length" "4,8")])
1851 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1852 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1853 (match_operand:SI 2 "gpc_reg_operand" ""))
1855 (clobber (match_scratch:SI 3 ""))]
1856 "! TARGET_POWERPC64 && reload_completed"
1858 (minus:SI (match_dup 1)
1861 (compare:CC (match_dup 3)
1866 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1867 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1868 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1870 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1871 (minus:SI (match_dup 1) (match_dup 2)))]
1874 {sf.|subfc.} %0,%2,%1
1876 [(set_attr "type" "compare")
1877 (set_attr "length" "4,8")])
1880 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1881 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1882 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1884 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1885 (minus:SI (match_dup 1)
1887 "TARGET_POWERPC && ! TARGET_POWERPC64"
1891 [(set_attr "type" "compare")
1892 (set_attr "length" "4,8")])
1895 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1896 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1897 (match_operand:SI 2 "gpc_reg_operand" ""))
1899 (set (match_operand:SI 0 "gpc_reg_operand" "")
1900 (minus:SI (match_dup 1)
1902 "! TARGET_POWERPC64 && reload_completed"
1904 (minus:SI (match_dup 1)
1907 (compare:CC (match_dup 0)
1911 (define_expand "subsi3"
1912 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1913 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1914 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1918 if (GET_CODE (operands[2]) == CONST_INT)
1920 emit_insn (gen_addsi3 (operands[0], operands[1],
1921 negate_rtx (SImode, operands[2])));
1926 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1927 ;; instruction and some auxiliary computations. Then we just have a single
1928 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1931 (define_expand "sminsi3"
1933 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1934 (match_operand:SI 2 "reg_or_short_operand" ""))
1936 (minus:SI (match_dup 2) (match_dup 1))))
1937 (set (match_operand:SI 0 "gpc_reg_operand" "")
1938 (minus:SI (match_dup 2) (match_dup 3)))]
1941 { operands[3] = gen_reg_rtx (SImode); }")
1944 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1945 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1946 (match_operand:SI 2 "reg_or_short_operand" "")))
1947 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1950 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1952 (minus:SI (match_dup 2) (match_dup 1))))
1953 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1956 (define_expand "smaxsi3"
1958 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1959 (match_operand:SI 2 "reg_or_short_operand" ""))
1961 (minus:SI (match_dup 2) (match_dup 1))))
1962 (set (match_operand:SI 0 "gpc_reg_operand" "")
1963 (plus:SI (match_dup 3) (match_dup 1)))]
1966 { operands[3] = gen_reg_rtx (SImode); }")
1969 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1970 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1971 (match_operand:SI 2 "reg_or_short_operand" "")))
1972 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1975 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1977 (minus:SI (match_dup 2) (match_dup 1))))
1978 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1981 (define_expand "uminsi3"
1982 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1984 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1986 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1988 (minus:SI (match_dup 4) (match_dup 3))))
1989 (set (match_operand:SI 0 "gpc_reg_operand" "")
1990 (minus:SI (match_dup 2) (match_dup 3)))]
1994 operands[3] = gen_reg_rtx (SImode);
1995 operands[4] = gen_reg_rtx (SImode);
1996 operands[5] = GEN_INT (-2147483647 - 1);
1999 (define_expand "umaxsi3"
2000 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2002 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2004 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2006 (minus:SI (match_dup 4) (match_dup 3))))
2007 (set (match_operand:SI 0 "gpc_reg_operand" "")
2008 (plus:SI (match_dup 3) (match_dup 1)))]
2012 operands[3] = gen_reg_rtx (SImode);
2013 operands[4] = gen_reg_rtx (SImode);
2014 operands[5] = GEN_INT (-2147483647 - 1);
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2019 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2020 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2022 (minus:SI (match_dup 2) (match_dup 1))))]
2027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2029 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2030 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2032 (minus:SI (match_dup 2) (match_dup 1)))
2034 (clobber (match_scratch:SI 3 "=r,r"))]
2039 [(set_attr "type" "delayed_compare")
2040 (set_attr "length" "4,8")])
2043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2045 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2046 (match_operand:SI 2 "reg_or_short_operand" ""))
2048 (minus:SI (match_dup 2) (match_dup 1)))
2050 (clobber (match_scratch:SI 3 ""))]
2051 "TARGET_POWER && reload_completed"
2053 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2055 (minus:SI (match_dup 2) (match_dup 1))))
2057 (compare:CC (match_dup 3)
2062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2064 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2065 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2067 (minus:SI (match_dup 2) (match_dup 1)))
2069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2070 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2072 (minus:SI (match_dup 2) (match_dup 1))))]
2077 [(set_attr "type" "delayed_compare")
2078 (set_attr "length" "4,8")])
2081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2083 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2084 (match_operand:SI 2 "reg_or_short_operand" ""))
2086 (minus:SI (match_dup 2) (match_dup 1)))
2088 (set (match_operand:SI 0 "gpc_reg_operand" "")
2089 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2091 (minus:SI (match_dup 2) (match_dup 1))))]
2092 "TARGET_POWER && reload_completed"
2094 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2096 (minus:SI (match_dup 2) (match_dup 1))))
2098 (compare:CC (match_dup 0)
2102 ;; We don't need abs with condition code because such comparisons should
2104 (define_expand "abssi2"
2105 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2106 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2112 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2117 (define_insn "*abssi2_power"
2118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2119 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2123 (define_insn_and_split "abssi2_nopower"
2124 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2125 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2126 (clobber (match_scratch:SI 2 "=&r,&r"))]
2129 "&& reload_completed"
2130 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2131 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2132 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2135 (define_insn "*nabs_power"
2136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2137 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2141 (define_insn_and_split "*nabs_nopower"
2142 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2143 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2144 (clobber (match_scratch:SI 2 "=&r,&r"))]
2147 "&& reload_completed"
2148 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2149 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2150 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2153 (define_insn "negsi2"
2154 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2155 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2160 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2161 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2163 (clobber (match_scratch:SI 2 "=r,r"))]
2164 "! TARGET_POWERPC64"
2168 [(set_attr "type" "compare")
2169 (set_attr "length" "4,8")])
2172 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2173 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2175 (clobber (match_scratch:SI 2 ""))]
2176 "! TARGET_POWERPC64 && reload_completed"
2178 (neg:SI (match_dup 1)))
2180 (compare:CC (match_dup 2)
2185 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2186 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2188 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2189 (neg:SI (match_dup 1)))]
2190 "! TARGET_POWERPC64"
2194 [(set_attr "type" "compare")
2195 (set_attr "length" "4,8")])
2198 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2199 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2201 (set (match_operand:SI 0 "gpc_reg_operand" "")
2202 (neg:SI (match_dup 1)))]
2203 "! TARGET_POWERPC64 && reload_completed"
2205 (neg:SI (match_dup 1)))
2207 (compare:CC (match_dup 0)
2211 (define_insn "ffssi2"
2212 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
2213 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2215 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
2216 [(set_attr "length" "16")])
2218 (define_expand "mulsi3"
2219 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2220 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2221 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2226 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2228 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2232 (define_insn "mulsi3_mq"
2233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2234 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2235 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2236 (clobber (match_scratch:SI 3 "=q,q"))]
2239 {muls|mullw} %0,%1,%2
2240 {muli|mulli} %0,%1,%2"
2242 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2243 (const_string "imul3")
2244 (match_operand:SI 2 "short_cint_operand" "")
2245 (const_string "imul2")]
2246 (const_string "imul")))])
2248 (define_insn "mulsi3_no_mq"
2249 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2250 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2251 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2254 {muls|mullw} %0,%1,%2
2255 {muli|mulli} %0,%1,%2"
2257 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2258 (const_string "imul3")
2259 (match_operand:SI 2 "short_cint_operand" "")
2260 (const_string "imul2")]
2261 (const_string "imul")))])
2264 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2265 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2266 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2268 (clobber (match_scratch:SI 3 "=r,r"))
2269 (clobber (match_scratch:SI 4 "=q,q"))]
2272 {muls.|mullw.} %3,%1,%2
2274 [(set_attr "type" "delayed_compare")
2275 (set_attr "length" "4,8")])
2278 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2279 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2280 (match_operand:SI 2 "gpc_reg_operand" ""))
2282 (clobber (match_scratch:SI 3 ""))
2283 (clobber (match_scratch:SI 4 ""))]
2284 "TARGET_POWER && reload_completed"
2285 [(parallel [(set (match_dup 3)
2286 (mult:SI (match_dup 1) (match_dup 2)))
2287 (clobber (match_dup 4))])
2289 (compare:CC (match_dup 3)
2294 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2295 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2296 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2298 (clobber (match_scratch:SI 3 "=r,r"))]
2301 {muls.|mullw.} %3,%1,%2
2303 [(set_attr "type" "delayed_compare")
2304 (set_attr "length" "4,8")])
2307 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2308 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2309 (match_operand:SI 2 "gpc_reg_operand" ""))
2311 (clobber (match_scratch:SI 3 ""))]
2312 "! TARGET_POWER && reload_completed"
2314 (mult:SI (match_dup 1) (match_dup 2)))
2316 (compare:CC (match_dup 3)
2321 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2322 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2323 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2325 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2326 (mult:SI (match_dup 1) (match_dup 2)))
2327 (clobber (match_scratch:SI 4 "=q,q"))]
2330 {muls.|mullw.} %0,%1,%2
2332 [(set_attr "type" "delayed_compare")
2333 (set_attr "length" "4,8")])
2336 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2337 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2338 (match_operand:SI 2 "gpc_reg_operand" ""))
2340 (set (match_operand:SI 0 "gpc_reg_operand" "")
2341 (mult:SI (match_dup 1) (match_dup 2)))
2342 (clobber (match_scratch:SI 4 ""))]
2343 "TARGET_POWER && reload_completed"
2344 [(parallel [(set (match_dup 0)
2345 (mult:SI (match_dup 1) (match_dup 2)))
2346 (clobber (match_dup 4))])
2348 (compare:CC (match_dup 0)
2353 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2354 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2355 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2357 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2358 (mult:SI (match_dup 1) (match_dup 2)))]
2361 {muls.|mullw.} %0,%1,%2
2363 [(set_attr "type" "delayed_compare")
2364 (set_attr "length" "4,8")])
2367 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2368 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2369 (match_operand:SI 2 "gpc_reg_operand" ""))
2371 (set (match_operand:SI 0 "gpc_reg_operand" "")
2372 (mult:SI (match_dup 1) (match_dup 2)))]
2373 "! TARGET_POWER && reload_completed"
2375 (mult:SI (match_dup 1) (match_dup 2)))
2377 (compare:CC (match_dup 0)
2381 ;; Operand 1 is divided by operand 2; quotient goes to operand
2382 ;; 0 and remainder to operand 3.
2383 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2385 (define_expand "divmodsi4"
2386 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2387 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2388 (match_operand:SI 2 "gpc_reg_operand" "")))
2389 (set (match_operand:SI 3 "gpc_reg_operand" "")
2390 (mod:SI (match_dup 1) (match_dup 2)))])]
2391 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2394 if (! TARGET_POWER && ! TARGET_POWERPC)
2396 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2397 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2398 emit_insn (gen_divss_call ());
2399 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2400 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2407 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2408 (match_operand:SI 2 "gpc_reg_operand" "r")))
2409 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
2410 (mod:SI (match_dup 1) (match_dup 2)))]
2413 [(set_attr "type" "idiv")])
2415 (define_expand "udivsi3"
2416 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2417 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2418 (match_operand:SI 2 "gpc_reg_operand" "")))]
2419 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2422 if (! TARGET_POWER && ! TARGET_POWERPC)
2424 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2425 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2426 emit_insn (gen_quous_call ());
2427 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2430 else if (TARGET_POWER)
2432 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2437 (define_insn "udivsi3_mq"
2438 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2439 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2440 (match_operand:SI 2 "gpc_reg_operand" "r")))
2441 (clobber (match_scratch:SI 3 "=q"))]
2442 "TARGET_POWERPC && TARGET_POWER"
2444 [(set_attr "type" "idiv")])
2446 (define_insn "*udivsi3_no_mq"
2447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2448 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2449 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2450 "TARGET_POWERPC && ! TARGET_POWER"
2452 [(set_attr "type" "idiv")])
2454 ;; For powers of two we can do srai/aze for divide and then adjust for
2455 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2456 ;; used; for PowerPC, force operands into register and do a normal divide;
2457 ;; for AIX common-mode, use quoss call on register operands.
2458 (define_expand "divsi3"
2459 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2460 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2461 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2465 if (GET_CODE (operands[2]) == CONST_INT
2466 && INTVAL (operands[2]) > 0
2467 && exact_log2 (INTVAL (operands[2])) >= 0)
2469 else if (TARGET_POWERPC)
2471 operands[2] = force_reg (SImode, operands[2]);
2474 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2478 else if (TARGET_POWER)
2482 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2483 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2484 emit_insn (gen_quoss_call ());
2485 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2490 (define_insn "divsi3_mq"
2491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2492 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2493 (match_operand:SI 2 "gpc_reg_operand" "r")))
2494 (clobber (match_scratch:SI 3 "=q"))]
2495 "TARGET_POWERPC && TARGET_POWER"
2497 [(set_attr "type" "idiv")])
2499 (define_insn "*divsi3_no_mq"
2500 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2501 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2502 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2503 "TARGET_POWERPC && ! TARGET_POWER"
2505 [(set_attr "type" "idiv")])
2507 (define_expand "modsi3"
2508 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2509 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2510 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2518 if (GET_CODE (operands[2]) != CONST_INT
2519 || INTVAL (operands[2]) <= 0
2520 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2523 temp1 = gen_reg_rtx (SImode);
2524 temp2 = gen_reg_rtx (SImode);
2526 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2527 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2528 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2534 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2535 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2537 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2538 [(set_attr "length" "8")])
2541 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2542 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2543 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2545 (clobber (match_scratch:SI 3 "=r,r"))]
2548 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2550 [(set_attr "type" "compare")
2551 (set_attr "length" "8,12")])
2554 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2555 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2556 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2558 (clobber (match_scratch:SI 3 ""))]
2561 (div:SI (match_dup 1) (match_dup 2)))
2563 (compare:CC (match_dup 3)
2568 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2569 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2570 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2572 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2573 (div:SI (match_dup 1) (match_dup 2)))]
2576 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2578 [(set_attr "type" "compare")
2579 (set_attr "length" "8,12")])
2582 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2583 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2584 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2586 (set (match_operand:SI 0 "gpc_reg_operand" "")
2587 (div:SI (match_dup 1) (match_dup 2)))]
2590 (div:SI (match_dup 1) (match_dup 2)))
2592 (compare:CC (match_dup 0)
2597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2600 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2602 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2603 (match_operand:SI 3 "gpc_reg_operand" "r")))
2604 (set (match_operand:SI 2 "register_operand" "=*q")
2607 (zero_extend:DI (match_dup 1)) (const_int 32))
2608 (zero_extend:DI (match_dup 4)))
2612 [(set_attr "type" "idiv")])
2614 ;; To do unsigned divide we handle the cases of the divisor looking like a
2615 ;; negative number. If it is a constant that is less than 2**31, we don't
2616 ;; have to worry about the branches. So make a few subroutines here.
2618 ;; First comes the normal case.
2619 (define_expand "udivmodsi4_normal"
2620 [(set (match_dup 4) (const_int 0))
2621 (parallel [(set (match_operand:SI 0 "" "")
2622 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2624 (zero_extend:DI (match_operand:SI 1 "" "")))
2625 (match_operand:SI 2 "" "")))
2626 (set (match_operand:SI 3 "" "")
2627 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2629 (zero_extend:DI (match_dup 1)))
2633 { operands[4] = gen_reg_rtx (SImode); }")
2635 ;; This handles the branches.
2636 (define_expand "udivmodsi4_tests"
2637 [(set (match_operand:SI 0 "" "") (const_int 0))
2638 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2639 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2640 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2641 (label_ref (match_operand:SI 4 "" "")) (pc)))
2642 (set (match_dup 0) (const_int 1))
2643 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2644 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2645 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2646 (label_ref (match_dup 4)) (pc)))]
2649 { operands[5] = gen_reg_rtx (CCUNSmode);
2650 operands[6] = gen_reg_rtx (CCmode);
2653 (define_expand "udivmodsi4"
2654 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2655 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2656 (match_operand:SI 2 "reg_or_cint_operand" "")))
2657 (set (match_operand:SI 3 "gpc_reg_operand" "")
2658 (umod:SI (match_dup 1) (match_dup 2)))])]
2666 if (! TARGET_POWERPC)
2668 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2669 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2670 emit_insn (gen_divus_call ());
2671 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2672 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2679 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2681 operands[2] = force_reg (SImode, operands[2]);
2682 label = gen_label_rtx ();
2683 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2684 operands[3], label));
2687 operands[2] = force_reg (SImode, operands[2]);
2689 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2697 ;; AIX architecture-independent common-mode multiply (DImode),
2698 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2699 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2700 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2701 ;; assumed unused if generating common-mode, so ignore.
2702 (define_insn "mulh_call"
2705 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2706 (sign_extend:DI (reg:SI 4)))
2708 (clobber (match_scratch:SI 0 "=l"))]
2709 "! TARGET_POWER && ! TARGET_POWERPC"
2711 [(set_attr "type" "imul")])
2713 (define_insn "mull_call"
2715 (mult:DI (sign_extend:DI (reg:SI 3))
2716 (sign_extend:DI (reg:SI 4))))
2717 (clobber (match_scratch:SI 0 "=l"))
2718 (clobber (reg:SI 0))]
2719 "! TARGET_POWER && ! TARGET_POWERPC"
2721 [(set_attr "type" "imul")])
2723 (define_insn "divss_call"
2725 (div:SI (reg:SI 3) (reg:SI 4)))
2727 (mod:SI (reg:SI 3) (reg:SI 4)))
2728 (clobber (match_scratch:SI 0 "=l"))
2729 (clobber (reg:SI 0))]
2730 "! TARGET_POWER && ! TARGET_POWERPC"
2732 [(set_attr "type" "idiv")])
2734 (define_insn "divus_call"
2736 (udiv:SI (reg:SI 3) (reg:SI 4)))
2738 (umod:SI (reg:SI 3) (reg:SI 4)))
2739 (clobber (match_scratch:SI 0 "=l"))
2740 (clobber (reg:SI 0))
2741 (clobber (match_scratch:CC 1 "=x"))
2742 (clobber (reg:CC 69))]
2743 "! TARGET_POWER && ! TARGET_POWERPC"
2745 [(set_attr "type" "idiv")])
2747 (define_insn "quoss_call"
2749 (div:SI (reg:SI 3) (reg:SI 4)))
2750 (clobber (match_scratch:SI 0 "=l"))]
2751 "! TARGET_POWER && ! TARGET_POWERPC"
2753 [(set_attr "type" "idiv")])
2755 (define_insn "quous_call"
2757 (udiv:SI (reg:SI 3) (reg:SI 4)))
2758 (clobber (match_scratch:SI 0 "=l"))
2759 (clobber (reg:SI 0))
2760 (clobber (match_scratch:CC 1 "=x"))
2761 (clobber (reg:CC 69))]
2762 "! TARGET_POWER && ! TARGET_POWERPC"
2764 [(set_attr "type" "idiv")])
2766 ;; Logical instructions
2767 ;; The logical instructions are mostly combined by using match_operator,
2768 ;; but the plain AND insns are somewhat different because there is no
2769 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2770 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2772 (define_insn "andsi3"
2773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2774 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2775 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2776 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2780 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2781 {andil.|andi.} %0,%1,%b2
2782 {andiu.|andis.} %0,%1,%u2")
2784 ;; Note to set cr's other than cr0 we do the and immediate and then
2785 ;; the test again -- this avoids a mcrf which on the higher end
2786 ;; machines causes an execution serialization
2788 (define_insn "*andsi3_internal2"
2789 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2790 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2791 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2793 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2794 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2795 "! TARGET_POWERPC64"
2798 {andil.|andi.} %3,%1,%b2
2799 {andiu.|andis.} %3,%1,%u2
2800 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2805 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2806 (set_attr "length" "4,4,4,4,8,8,8,8")])
2809 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2810 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2811 (match_operand:SI 2 "and_operand" ""))
2813 (clobber (match_scratch:SI 3 ""))
2814 (clobber (match_scratch:CC 4 ""))]
2815 "! TARGET_POWERPC64 && reload_completed"
2816 [(parallel [(set (match_dup 3)
2817 (and:SI (match_dup 1)
2819 (clobber (match_dup 4))])
2821 (compare:CC (match_dup 3)
2825 (define_insn "*andsi3_internal3"
2826 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2827 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2828 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2830 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2831 (and:SI (match_dup 1)
2833 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2834 "! TARGET_POWERPC64"
2837 {andil.|andi.} %0,%1,%b2
2838 {andiu.|andis.} %0,%1,%u2
2839 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2844 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2845 (set_attr "length" "4,4,4,4,8,8,8,8")])
2848 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2849 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2850 (match_operand:SI 2 "and_operand" ""))
2852 (set (match_operand:SI 0 "gpc_reg_operand" "")
2853 (and:SI (match_dup 1)
2855 (clobber (match_scratch:CC 4 ""))]
2856 "! TARGET_POWERPC64 && reload_completed"
2857 [(parallel [(set (match_dup 0)
2858 (and:SI (match_dup 1)
2860 (clobber (match_dup 4))])
2862 (compare:CC (match_dup 0)
2866 (define_expand "iorsi3"
2867 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2868 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2869 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2873 if (GET_CODE (operands[2]) == CONST_INT
2874 && ! logical_operand (operands[2], SImode))
2876 HOST_WIDE_INT value = INTVAL (operands[2]);
2877 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2878 ? operands[0] : gen_reg_rtx (SImode));
2880 emit_insn (gen_iorsi3 (tmp, operands[1],
2881 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2882 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2887 (define_expand "xorsi3"
2888 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2889 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2890 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2894 if (GET_CODE (operands[2]) == CONST_INT
2895 && ! logical_operand (operands[2], SImode))
2897 HOST_WIDE_INT value = INTVAL (operands[2]);
2898 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2899 ? operands[0] : gen_reg_rtx (SImode));
2901 emit_insn (gen_xorsi3 (tmp, operands[1],
2902 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2903 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2908 (define_insn "*boolsi3_internal1"
2909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2910 (match_operator:SI 3 "boolean_or_operator"
2911 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2912 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2916 {%q3il|%q3i} %0,%1,%b2
2917 {%q3iu|%q3is} %0,%1,%u2")
2919 (define_insn "*boolsi3_internal2"
2920 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2921 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2922 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2923 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2925 (clobber (match_scratch:SI 3 "=r,r"))]
2926 "! TARGET_POWERPC64"
2930 [(set_attr "type" "compare")
2931 (set_attr "length" "4,8")])
2934 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2935 (compare:CC (match_operator:SI 4 "boolean_operator"
2936 [(match_operand:SI 1 "gpc_reg_operand" "")
2937 (match_operand:SI 2 "gpc_reg_operand" "")])
2939 (clobber (match_scratch:SI 3 ""))]
2940 "! TARGET_POWERPC64 && reload_completed"
2941 [(set (match_dup 3) (match_dup 4))
2943 (compare:CC (match_dup 3)
2947 (define_insn "*boolsi3_internal3"
2948 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2949 (compare:CC (match_operator:SI 4 "boolean_operator"
2950 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2951 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2955 "! TARGET_POWERPC64"
2959 [(set_attr "type" "compare")
2960 (set_attr "length" "4,8")])
2963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2964 (compare:CC (match_operator:SI 4 "boolean_operator"
2965 [(match_operand:SI 1 "gpc_reg_operand" "")
2966 (match_operand:SI 2 "gpc_reg_operand" "")])
2968 (set (match_operand:SI 0 "gpc_reg_operand" "")
2970 "! TARGET_POWERPC64 && reload_completed"
2971 [(set (match_dup 0) (match_dup 4))
2973 (compare:CC (match_dup 0)
2977 ;; Split an logical operation that we can't do in one insn into two insns,
2978 ;; each of which does one 16-bit part. This is used by combine.
2981 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2982 (match_operator:SI 3 "boolean_or_operator"
2983 [(match_operand:SI 1 "gpc_reg_operand" "")
2984 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2986 [(set (match_dup 0) (match_dup 4))
2987 (set (match_dup 0) (match_dup 5))]
2991 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2992 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2994 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2995 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2999 (define_insn "*boolcsi3_internal1"
3000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3001 (match_operator:SI 3 "boolean_operator"
3002 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3003 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3007 (define_insn "*boolcsi3_internal2"
3008 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3009 (compare:CC (match_operator:SI 4 "boolean_operator"
3010 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3011 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3013 (clobber (match_scratch:SI 3 "=r,r"))]
3014 "! TARGET_POWERPC64"
3018 [(set_attr "type" "compare")
3019 (set_attr "length" "4,8")])
3022 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3023 (compare:CC (match_operator:SI 4 "boolean_operator"
3024 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3025 (match_operand:SI 2 "gpc_reg_operand" "")])
3027 (clobber (match_scratch:SI 3 ""))]
3028 "! TARGET_POWERPC64 && reload_completed"
3029 [(set (match_dup 3) (match_dup 4))
3031 (compare:CC (match_dup 3)
3035 (define_insn "*boolcsi3_internal3"
3036 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3037 (compare:CC (match_operator:SI 4 "boolean_operator"
3038 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3039 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3041 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3043 "! TARGET_POWERPC64"
3047 [(set_attr "type" "compare")
3048 (set_attr "length" "4,8")])
3051 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3052 (compare:CC (match_operator:SI 4 "boolean_operator"
3053 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3054 (match_operand:SI 2 "gpc_reg_operand" "")])
3056 (set (match_operand:SI 0 "gpc_reg_operand" "")
3058 "! TARGET_POWERPC64 && reload_completed"
3059 [(set (match_dup 0) (match_dup 4))
3061 (compare:CC (match_dup 0)
3065 (define_insn "*boolccsi3_internal1"
3066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3067 (match_operator:SI 3 "boolean_operator"
3068 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3069 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3073 (define_insn "*boolccsi3_internal2"
3074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3075 (compare:CC (match_operator:SI 4 "boolean_operator"
3076 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3077 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3079 (clobber (match_scratch:SI 3 "=r,r"))]
3080 "! TARGET_POWERPC64"
3084 [(set_attr "type" "compare")
3085 (set_attr "length" "4,8")])
3088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3089 (compare:CC (match_operator:SI 4 "boolean_operator"
3090 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3091 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3093 (clobber (match_scratch:SI 3 ""))]
3094 "! TARGET_POWERPC64 && reload_completed"
3095 [(set (match_dup 3) (match_dup 4))
3097 (compare:CC (match_dup 3)
3101 (define_insn "*boolccsi3_internal3"
3102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3103 (compare:CC (match_operator:SI 4 "boolean_operator"
3104 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3105 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3107 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3109 "! TARGET_POWERPC64"
3113 [(set_attr "type" "compare")
3114 (set_attr "length" "4,8")])
3117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3118 (compare:CC (match_operator:SI 4 "boolean_operator"
3119 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3120 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3122 (set (match_operand:SI 0 "gpc_reg_operand" "")
3124 "! TARGET_POWERPC64 && reload_completed"
3125 [(set (match_dup 0) (match_dup 4))
3127 (compare:CC (match_dup 0)
3131 ;; maskir insn. We need four forms because things might be in arbitrary
3132 ;; orders. Don't define forms that only set CR fields because these
3133 ;; would modify an input register.
3135 (define_insn "*maskir_internal1"
3136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3137 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3138 (match_operand:SI 1 "gpc_reg_operand" "0"))
3139 (and:SI (match_dup 2)
3140 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3144 (define_insn "*maskir_internal2"
3145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3146 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3147 (match_operand:SI 1 "gpc_reg_operand" "0"))
3148 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3153 (define_insn "*maskir_internal3"
3154 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3155 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3156 (match_operand:SI 3 "gpc_reg_operand" "r"))
3157 (and:SI (not:SI (match_dup 2))
3158 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3162 (define_insn "*maskir_internal4"
3163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3164 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3165 (match_operand:SI 2 "gpc_reg_operand" "r"))
3166 (and:SI (not:SI (match_dup 2))
3167 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3171 (define_insn "*maskir_internal5"
3172 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3174 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3175 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3176 (and:SI (match_dup 2)
3177 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3179 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3180 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3181 (and:SI (match_dup 2) (match_dup 3))))]
3186 [(set_attr "type" "compare")
3187 (set_attr "length" "4,8")])
3190 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3192 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3193 (match_operand:SI 1 "gpc_reg_operand" ""))
3194 (and:SI (match_dup 2)
3195 (match_operand:SI 3 "gpc_reg_operand" "")))
3197 (set (match_operand:SI 0 "gpc_reg_operand" "")
3198 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3199 (and:SI (match_dup 2) (match_dup 3))))]
3200 "TARGET_POWER && reload_completed"
3202 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3203 (and:SI (match_dup 2) (match_dup 3))))
3205 (compare:CC (match_dup 0)
3209 (define_insn "*maskir_internal6"
3210 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3212 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3213 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3214 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3217 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3218 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3219 (and:SI (match_dup 3) (match_dup 2))))]
3224 [(set_attr "type" "compare")
3225 (set_attr "length" "4,8")])
3228 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3230 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3231 (match_operand:SI 1 "gpc_reg_operand" ""))
3232 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3235 (set (match_operand:SI 0 "gpc_reg_operand" "")
3236 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3237 (and:SI (match_dup 3) (match_dup 2))))]
3238 "TARGET_POWER && reload_completed"
3240 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3241 (and:SI (match_dup 3) (match_dup 2))))
3243 (compare:CC (match_dup 0)
3247 (define_insn "*maskir_internal7"
3248 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3250 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3251 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3252 (and:SI (not:SI (match_dup 2))
3253 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3255 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3256 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3257 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3262 [(set_attr "type" "compare")
3263 (set_attr "length" "4,8")])
3266 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3268 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3269 (match_operand:SI 3 "gpc_reg_operand" ""))
3270 (and:SI (not:SI (match_dup 2))
3271 (match_operand:SI 1 "gpc_reg_operand" "")))
3273 (set (match_operand:SI 0 "gpc_reg_operand" "")
3274 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3275 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3276 "TARGET_POWER && reload_completed"
3278 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3279 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3281 (compare:CC (match_dup 0)
3285 (define_insn "*maskir_internal8"
3286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3288 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3289 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3290 (and:SI (not:SI (match_dup 2))
3291 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3293 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3294 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3295 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3300 [(set_attr "type" "compare")
3301 (set_attr "length" "4,8")])
3304 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3306 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3307 (match_operand:SI 2 "gpc_reg_operand" ""))
3308 (and:SI (not:SI (match_dup 2))
3309 (match_operand:SI 1 "gpc_reg_operand" "")))
3311 (set (match_operand:SI 0 "gpc_reg_operand" "")
3312 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3313 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3314 "TARGET_POWER && reload_completed"
3316 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3317 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3319 (compare:CC (match_dup 0)
3323 ;; Rotate and shift insns, in all their variants. These support shifts,
3324 ;; field inserts and extracts, and various combinations thereof.
3325 (define_expand "insv"
3326 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3327 (match_operand:SI 1 "const_int_operand" "")
3328 (match_operand:SI 2 "const_int_operand" ""))
3329 (match_operand 3 "gpc_reg_operand" ""))]
3333 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3334 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3335 compiler if the address of the structure is taken later. */
3336 if (GET_CODE (operands[0]) == SUBREG
3337 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3340 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3341 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3343 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3347 (define_insn "insvsi"
3348 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3349 (match_operand:SI 1 "const_int_operand" "i")
3350 (match_operand:SI 2 "const_int_operand" "i"))
3351 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3355 int start = INTVAL (operands[2]) & 31;
3356 int size = INTVAL (operands[1]) & 31;
3358 operands[4] = GEN_INT (32 - start - size);
3359 operands[1] = GEN_INT (start + size - 1);
3360 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3363 (define_insn "*insvsi_internal1"
3364 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3365 (match_operand:SI 1 "const_int_operand" "i")
3366 (match_operand:SI 2 "const_int_operand" "i"))
3367 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3368 (match_operand:SI 4 "const_int_operand" "i")))]
3369 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3372 int shift = INTVAL (operands[4]) & 31;
3373 int start = INTVAL (operands[2]) & 31;
3374 int size = INTVAL (operands[1]) & 31;
3376 operands[4] = GEN_INT (shift - start - size);
3377 operands[1] = GEN_INT (start + size - 1);
3378 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3381 (define_insn "*insvsi_internal2"
3382 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3383 (match_operand:SI 1 "const_int_operand" "i")
3384 (match_operand:SI 2 "const_int_operand" "i"))
3385 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3386 (match_operand:SI 4 "const_int_operand" "i")))]
3387 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3390 int shift = INTVAL (operands[4]) & 31;
3391 int start = INTVAL (operands[2]) & 31;
3392 int size = INTVAL (operands[1]) & 31;
3394 operands[4] = GEN_INT (32 - shift - start - size);
3395 operands[1] = GEN_INT (start + size - 1);
3396 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3399 (define_insn "*insvsi_internal3"
3400 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3401 (match_operand:SI 1 "const_int_operand" "i")
3402 (match_operand:SI 2 "const_int_operand" "i"))
3403 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3404 (match_operand:SI 4 "const_int_operand" "i")))]
3405 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3408 int shift = INTVAL (operands[4]) & 31;
3409 int start = INTVAL (operands[2]) & 31;
3410 int size = INTVAL (operands[1]) & 31;
3412 operands[4] = GEN_INT (32 - shift - start - size);
3413 operands[1] = GEN_INT (start + size - 1);
3414 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3417 (define_insn "*insvsi_internal4"
3418 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3419 (match_operand:SI 1 "const_int_operand" "i")
3420 (match_operand:SI 2 "const_int_operand" "i"))
3421 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3422 (match_operand:SI 4 "const_int_operand" "i")
3423 (match_operand:SI 5 "const_int_operand" "i")))]
3424 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3427 int extract_start = INTVAL (operands[5]) & 31;
3428 int extract_size = INTVAL (operands[4]) & 31;
3429 int insert_start = INTVAL (operands[2]) & 31;
3430 int insert_size = INTVAL (operands[1]) & 31;
3432 /* Align extract field with insert field */
3433 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3434 operands[1] = GEN_INT (insert_start + insert_size - 1);
3435 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3438 (define_insn "insvdi"
3439 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3440 (match_operand:SI 1 "const_int_operand" "i")
3441 (match_operand:SI 2 "const_int_operand" "i"))
3442 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3446 int start = INTVAL (operands[2]) & 63;
3447 int size = INTVAL (operands[1]) & 63;
3449 operands[1] = GEN_INT (64 - start - size);
3450 return \"rldimi %0,%3,%H1,%H2\";
3453 (define_expand "extzv"
3454 [(set (match_operand 0 "gpc_reg_operand" "")
3455 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3456 (match_operand:SI 2 "const_int_operand" "")
3457 (match_operand:SI 3 "const_int_operand" "")))]
3461 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3462 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3463 compiler if the address of the structure is taken later. */
3464 if (GET_CODE (operands[0]) == SUBREG
3465 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3468 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3469 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3471 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3475 (define_insn "extzvsi"
3476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3477 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3478 (match_operand:SI 2 "const_int_operand" "i")
3479 (match_operand:SI 3 "const_int_operand" "i")))]
3483 int start = INTVAL (operands[3]) & 31;
3484 int size = INTVAL (operands[2]) & 31;
3486 if (start + size >= 32)
3487 operands[3] = const0_rtx;
3489 operands[3] = GEN_INT (start + size);
3490 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3493 (define_insn "*extzvsi_internal1"
3494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3495 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3496 (match_operand:SI 2 "const_int_operand" "i,i")
3497 (match_operand:SI 3 "const_int_operand" "i,i"))
3499 (clobber (match_scratch:SI 4 "=r,r"))]
3500 "! TARGET_POWERPC64"
3503 int start = INTVAL (operands[3]) & 31;
3504 int size = INTVAL (operands[2]) & 31;
3506 /* Force split for non-cc0 compare. */
3507 if (which_alternative == 1)
3510 /* If the bitfield being tested fits in the upper or lower half of a
3511 word, it is possible to use andiu. or andil. to test it. This is
3512 useful because the condition register set-use delay is smaller for
3513 andi[ul]. than for rlinm. This doesn't work when the starting bit
3514 position is 0 because the LT and GT bits may be set wrong. */
3516 if ((start > 0 && start + size <= 16) || start >= 16)
3518 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3519 - (1 << (16 - (start & 15) - size))));
3521 return \"{andiu.|andis.} %4,%1,%3\";
3523 return \"{andil.|andi.} %4,%1,%3\";
3526 if (start + size >= 32)
3527 operands[3] = const0_rtx;
3529 operands[3] = GEN_INT (start + size);
3530 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3532 [(set_attr "type" "compare")
3533 (set_attr "length" "4,8")])
3536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3537 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3538 (match_operand:SI 2 "const_int_operand" "")
3539 (match_operand:SI 3 "const_int_operand" ""))
3541 (clobber (match_scratch:SI 4 ""))]
3542 "! TARGET_POWERPC64 && reload_completed"
3544 (zero_extract:SI (match_dup 1) (match_dup 2)
3547 (compare:CC (match_dup 4)
3551 (define_insn "*extzvsi_internal2"
3552 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3553 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3554 (match_operand:SI 2 "const_int_operand" "i,i")
3555 (match_operand:SI 3 "const_int_operand" "i,i"))
3557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3558 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3559 "! TARGET_POWERPC64"
3562 int start = INTVAL (operands[3]) & 31;
3563 int size = INTVAL (operands[2]) & 31;
3565 /* Force split for non-cc0 compare. */
3566 if (which_alternative == 1)
3569 if (start >= 16 && start + size == 32)
3571 operands[3] = GEN_INT ((1 << (32 - start)) - 1);
3572 return \"{andil.|andi.} %0,%1,%3\";
3575 if (start + size >= 32)
3576 operands[3] = const0_rtx;
3578 operands[3] = GEN_INT (start + size);
3579 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3581 [(set_attr "type" "delayed_compare")
3582 (set_attr "length" "4,8")])
3585 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3586 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3587 (match_operand:SI 2 "const_int_operand" "")
3588 (match_operand:SI 3 "const_int_operand" ""))
3590 (set (match_operand:SI 0 "gpc_reg_operand" "")
3591 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3592 "! TARGET_POWERPC64 && reload_completed"
3594 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3596 (compare:CC (match_dup 0)
3600 (define_insn "extzvdi"
3601 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3602 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3603 (match_operand:SI 2 "const_int_operand" "i")
3604 (match_operand:SI 3 "const_int_operand" "i")))]
3608 int start = INTVAL (operands[3]) & 63;
3609 int size = INTVAL (operands[2]) & 63;
3611 if (start + size >= 64)
3612 operands[3] = const0_rtx;
3614 operands[3] = GEN_INT (start + size);
3615 operands[2] = GEN_INT (64 - size);
3616 return \"rldicl %0,%1,%3,%2\";
3619 (define_insn "*extzvdi_internal1"
3620 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3621 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3622 (match_operand:SI 2 "const_int_operand" "i")
3623 (match_operand:SI 3 "const_int_operand" "i"))
3625 (clobber (match_scratch:DI 4 "=r"))]
3629 int start = INTVAL (operands[3]) & 63;
3630 int size = INTVAL (operands[2]) & 63;
3632 if (start + size >= 64)
3633 operands[3] = const0_rtx;
3635 operands[3] = GEN_INT (start + size);
3636 operands[2] = GEN_INT (64 - size);
3637 return \"rldicl. %4,%1,%3,%2\";
3640 (define_insn "*extzvdi_internal2"
3641 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3642 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3643 (match_operand:SI 2 "const_int_operand" "i")
3644 (match_operand:SI 3 "const_int_operand" "i"))
3646 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3647 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3651 int start = INTVAL (operands[3]) & 63;
3652 int size = INTVAL (operands[2]) & 63;
3654 if (start + size >= 64)
3655 operands[3] = const0_rtx;
3657 operands[3] = GEN_INT (start + size);
3658 operands[2] = GEN_INT (64 - size);
3659 return \"rldicl. %0,%1,%3,%2\";
3662 (define_insn "rotlsi3"
3663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3664 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3665 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3667 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3669 (define_insn "*rotlsi3_internal2"
3670 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3671 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3672 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3674 (clobber (match_scratch:SI 3 "=r,r"))]
3675 "! TARGET_POWERPC64"
3677 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3679 [(set_attr "type" "delayed_compare")
3680 (set_attr "length" "4,8")])
3683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3684 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3685 (match_operand:SI 2 "reg_or_cint_operand" ""))
3687 (clobber (match_scratch:SI 3 ""))]
3688 "! TARGET_POWERPC64 && reload_completed"
3690 (rotate:SI (match_dup 1) (match_dup 2)))
3692 (compare:CC (match_dup 3)
3696 (define_insn "*rotlsi3_internal3"
3697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3698 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3699 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3702 (rotate:SI (match_dup 1) (match_dup 2)))]
3703 "! TARGET_POWERPC64"
3705 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3707 [(set_attr "type" "delayed_compare")
3708 (set_attr "length" "4,8")])
3711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3712 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3713 (match_operand:SI 2 "reg_or_cint_operand" ""))
3715 (set (match_operand:SI 0 "gpc_reg_operand" "")
3716 (rotate:SI (match_dup 1) (match_dup 2)))]
3717 "! TARGET_POWERPC64 && reload_completed"
3719 (rotate:SI (match_dup 1) (match_dup 2)))
3721 (compare:CC (match_dup 0)
3725 (define_insn "*rotlsi3_internal4"
3726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3727 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3728 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3729 (match_operand:SI 3 "mask_operand" "T")))]
3731 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3733 (define_insn "*rotlsi3_internal5"
3734 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3736 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3737 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3738 (match_operand:SI 3 "mask_operand" "T,T"))
3740 (clobber (match_scratch:SI 4 "=r,r"))]
3741 "! TARGET_POWERPC64"
3743 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3745 [(set_attr "type" "delayed_compare")
3746 (set_attr "length" "4,8")])
3749 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3751 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3752 (match_operand:SI 2 "reg_or_cint_operand" ""))
3753 (match_operand:SI 3 "mask_operand" ""))
3755 (clobber (match_scratch:SI 4 ""))]
3756 "! TARGET_POWERPC64 && reload_completed"
3758 (and:SI (rotate:SI (match_dup 1)
3762 (compare:CC (match_dup 4)
3766 (define_insn "*rotlsi3_internal6"
3767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3769 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3770 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3771 (match_operand:SI 3 "mask_operand" "T,T"))
3773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3774 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3775 "! TARGET_POWERPC64"
3777 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3779 [(set_attr "type" "delayed_compare")
3780 (set_attr "length" "4,8")])
3783 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3785 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3786 (match_operand:SI 2 "reg_or_cint_operand" ""))
3787 (match_operand:SI 3 "mask_operand" ""))
3789 (set (match_operand:SI 0 "gpc_reg_operand" "")
3790 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3791 "! TARGET_POWERPC64 && reload_completed"
3793 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3795 (compare:CC (match_dup 0)
3799 (define_insn "*rotlsi3_internal7"
3800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3803 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3804 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3806 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3808 (define_insn "*rotlsi3_internal8"
3809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3810 (compare:CC (zero_extend:SI
3812 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3813 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3815 (clobber (match_scratch:SI 3 "=r,r"))]
3818 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3820 [(set_attr "type" "delayed_compare")
3821 (set_attr "length" "4,8")])
3824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3825 (compare:CC (zero_extend:SI
3827 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3828 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3830 (clobber (match_scratch:SI 3 ""))]
3833 (zero_extend:SI (subreg:QI
3834 (rotate:SI (match_dup 1)
3837 (compare:CC (match_dup 3)
3841 (define_insn "*rotlsi3_internal9"
3842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3843 (compare:CC (zero_extend:SI
3845 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3846 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3848 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3849 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3852 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3854 [(set_attr "type" "delayed_compare")
3855 (set_attr "length" "4,8")])
3858 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3859 (compare:CC (zero_extend:SI
3861 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3862 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3864 (set (match_operand:SI 0 "gpc_reg_operand" "")
3865 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3868 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3870 (compare:CC (match_dup 0)
3874 (define_insn "*rotlsi3_internal10"
3875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3878 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3879 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3881 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3883 (define_insn "*rotlsi3_internal11"
3884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3885 (compare:CC (zero_extend:SI
3887 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3888 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3890 (clobber (match_scratch:SI 3 "=r,r"))]
3893 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3895 [(set_attr "type" "delayed_compare")
3896 (set_attr "length" "4,8")])
3899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3900 (compare:CC (zero_extend:SI
3902 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3903 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3905 (clobber (match_scratch:SI 3 ""))]
3908 (zero_extend:SI (subreg:HI
3909 (rotate:SI (match_dup 1)
3912 (compare:CC (match_dup 3)
3916 (define_insn "*rotlsi3_internal12"
3917 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3918 (compare:CC (zero_extend:SI
3920 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3921 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3923 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3924 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3927 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3929 [(set_attr "type" "delayed_compare")
3930 (set_attr "length" "4,8")])
3933 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3934 (compare:CC (zero_extend:SI
3936 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3937 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3939 (set (match_operand:SI 0 "gpc_reg_operand" "")
3940 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3943 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3945 (compare:CC (match_dup 0)
3949 ;; Note that we use "sle." instead of "sl." so that we can set
3950 ;; SHIFT_COUNT_TRUNCATED.
3952 (define_expand "ashlsi3"
3953 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3954 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3955 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3960 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3962 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3966 (define_insn "ashlsi3_power"
3967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3968 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3969 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3970 (clobber (match_scratch:SI 3 "=q,X"))]
3974 {sli|slwi} %0,%1,%h2")
3976 (define_insn "ashlsi3_no_power"
3977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3978 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3979 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3981 "{sl|slw}%I2 %0,%1,%h2")
3984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3985 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3986 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3988 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3989 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3993 {sli.|slwi.} %3,%1,%h2
3996 [(set_attr "type" "delayed_compare")
3997 (set_attr "length" "4,4,8,8")])
4000 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4001 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4002 (match_operand:SI 2 "reg_or_cint_operand" ""))
4004 (clobber (match_scratch:SI 3 ""))
4005 (clobber (match_scratch:SI 4 ""))]
4006 "TARGET_POWER && reload_completed"
4007 [(parallel [(set (match_dup 3)
4008 (ashift:SI (match_dup 1) (match_dup 2)))
4009 (clobber (match_dup 4))])
4011 (compare:CC (match_dup 3)
4016 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4017 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4018 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4020 (clobber (match_scratch:SI 3 "=r,r"))]
4021 "! TARGET_POWER && ! TARGET_POWERPC64"
4023 {sl|slw}%I2. %3,%1,%h2
4025 [(set_attr "type" "delayed_compare")
4026 (set_attr "length" "4,8")])
4029 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4030 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4031 (match_operand:SI 2 "reg_or_cint_operand" ""))
4033 (clobber (match_scratch:SI 3 ""))]
4034 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4036 (ashift:SI (match_dup 1) (match_dup 2)))
4038 (compare:CC (match_dup 3)
4043 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4044 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4045 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4047 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4048 (ashift:SI (match_dup 1) (match_dup 2)))
4049 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4053 {sli.|slwi.} %0,%1,%h2
4056 [(set_attr "type" "delayed_compare")
4057 (set_attr "length" "4,4,8,8")])
4060 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4061 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4062 (match_operand:SI 2 "reg_or_cint_operand" ""))
4064 (set (match_operand:SI 0 "gpc_reg_operand" "")
4065 (ashift:SI (match_dup 1) (match_dup 2)))
4066 (clobber (match_scratch:SI 4 ""))]
4067 "TARGET_POWER && reload_completed"
4068 [(parallel [(set (match_dup 0)
4069 (ashift:SI (match_dup 1) (match_dup 2)))
4070 (clobber (match_dup 4))])
4072 (compare:CC (match_dup 0)
4077 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4078 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4079 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4081 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4082 (ashift:SI (match_dup 1) (match_dup 2)))]
4083 "! TARGET_POWER && ! TARGET_POWERPC64"
4085 {sl|slw}%I2. %0,%1,%h2
4087 [(set_attr "type" "delayed_compare")
4088 (set_attr "length" "4,8")])
4091 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4092 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4093 (match_operand:SI 2 "reg_or_cint_operand" ""))
4095 (set (match_operand:SI 0 "gpc_reg_operand" "")
4096 (ashift:SI (match_dup 1) (match_dup 2)))]
4097 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4099 (ashift:SI (match_dup 1) (match_dup 2)))
4101 (compare:CC (match_dup 0)
4106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4107 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4108 (match_operand:SI 2 "const_int_operand" "i"))
4109 (match_operand:SI 3 "mask_operand" "T")))]
4110 "includes_lshift_p (operands[2], operands[3])"
4111 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4114 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4116 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4117 (match_operand:SI 2 "const_int_operand" "i,i"))
4118 (match_operand:SI 3 "mask_operand" "T,T"))
4120 (clobber (match_scratch:SI 4 "=r,r"))]
4121 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
4123 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4129 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4131 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4132 (match_operand:SI 2 "const_int_operand" ""))
4133 (match_operand:SI 3 "mask_operand" ""))
4135 (clobber (match_scratch:SI 4 ""))]
4136 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
4138 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4141 (compare:CC (match_dup 4)
4146 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4148 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4149 (match_operand:SI 2 "const_int_operand" "i,i"))
4150 (match_operand:SI 3 "mask_operand" "T,T"))
4152 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4153 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4154 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
4156 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4158 [(set_attr "type" "delayed_compare")
4159 (set_attr "length" "4,8")])
4162 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4164 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4165 (match_operand:SI 2 "const_int_operand" ""))
4166 (match_operand:SI 3 "mask_operand" ""))
4168 (set (match_operand:SI 0 "gpc_reg_operand" "")
4169 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4170 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
4172 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4174 (compare:CC (match_dup 0)
4178 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4180 (define_expand "lshrsi3"
4181 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4182 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4183 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4188 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4190 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4194 (define_insn "lshrsi3_power"
4195 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4196 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4197 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4198 (clobber (match_scratch:SI 3 "=q,X,X"))]
4203 {s%A2i|s%A2wi} %0,%1,%h2")
4205 (define_insn "lshrsi3_no_power"
4206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4207 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4208 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4212 {sr|srw}%I2 %0,%1,%h2")
4215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4216 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4217 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4219 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4220 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4225 {s%A2i.|s%A2wi.} %3,%1,%h2
4229 [(set_attr "type" "delayed_compare")
4230 (set_attr "length" "4,4,4,8,8,8")])
4233 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4234 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4235 (match_operand:SI 2 "reg_or_cint_operand" ""))
4237 (clobber (match_scratch:SI 3 ""))
4238 (clobber (match_scratch:SI 4 ""))]
4239 "TARGET_POWER && reload_completed"
4240 [(parallel [(set (match_dup 3)
4241 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4242 (clobber (match_dup 4))])
4244 (compare:CC (match_dup 3)
4249 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4250 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4251 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4253 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4254 "! TARGET_POWER && ! TARGET_POWERPC64"
4257 {sr|srw}%I2. %3,%1,%h2
4260 [(set_attr "type" "delayed_compare")
4261 (set_attr "length" "4,4,8,8")])
4264 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4265 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4266 (match_operand:SI 2 "reg_or_cint_operand" ""))
4268 (clobber (match_scratch:SI 3 ""))]
4269 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4271 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4273 (compare:CC (match_dup 3)
4278 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4279 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4280 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4282 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4283 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4284 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4289 {s%A2i.|s%A2wi.} %0,%1,%h2
4293 [(set_attr "type" "delayed_compare")
4294 (set_attr "length" "4,4,4,8,8,8")])
4297 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4298 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4299 (match_operand:SI 2 "reg_or_cint_operand" ""))
4301 (set (match_operand:SI 0 "gpc_reg_operand" "")
4302 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4303 (clobber (match_scratch:SI 4 ""))]
4304 "TARGET_POWER && reload_completed"
4305 [(parallel [(set (match_dup 0)
4306 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4307 (clobber (match_dup 4))])
4309 (compare:CC (match_dup 0)
4314 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4315 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4316 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4319 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4320 "! TARGET_POWER && ! TARGET_POWERPC64"
4323 {sr|srw}%I2. %0,%1,%h2
4326 [(set_attr "type" "delayed_compare")
4327 (set_attr "length" "4,4,8,8")])
4330 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4331 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4332 (match_operand:SI 2 "reg_or_cint_operand" ""))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "")
4335 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4336 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4338 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4340 (compare:CC (match_dup 0)
4345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4346 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4347 (match_operand:SI 2 "const_int_operand" "i"))
4348 (match_operand:SI 3 "mask_operand" "T")))]
4349 "includes_rshift_p (operands[2], operands[3])"
4350 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4353 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4355 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "const_int_operand" "i,i"))
4357 (match_operand:SI 3 "mask_operand" "T,T"))
4359 (clobber (match_scratch:SI 4 "=r,r"))]
4360 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4362 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4364 [(set_attr "type" "delayed_compare")
4365 (set_attr "length" "4,8")])
4368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4370 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4371 (match_operand:SI 2 "const_int_operand" ""))
4372 (match_operand:SI 3 "mask_operand" ""))
4374 (clobber (match_scratch:SI 4 ""))]
4375 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4377 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4380 (compare:CC (match_dup 4)
4385 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4387 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4388 (match_operand:SI 2 "const_int_operand" "i,i"))
4389 (match_operand:SI 3 "mask_operand" "T,T"))
4391 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4392 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4393 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4395 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4397 [(set_attr "type" "delayed_compare")
4398 (set_attr "length" "4,8")])
4401 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4403 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4404 (match_operand:SI 2 "const_int_operand" ""))
4405 (match_operand:SI 3 "mask_operand" ""))
4407 (set (match_operand:SI 0 "gpc_reg_operand" "")
4408 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4409 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4411 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4413 (compare:CC (match_dup 0)
4418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4421 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4422 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4423 "includes_rshift_p (operands[2], GEN_INT (255))"
4424 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4427 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4431 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4432 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4434 (clobber (match_scratch:SI 3 "=r,r"))]
4435 "includes_rshift_p (operands[2], GEN_INT (255))"
4437 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4439 [(set_attr "type" "delayed_compare")
4440 (set_attr "length" "4,8")])
4443 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4447 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4448 (match_operand:SI 2 "const_int_operand" "")) 0))
4450 (clobber (match_scratch:SI 3 ""))]
4451 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4453 (zero_extend:SI (subreg:QI
4454 (lshiftrt:SI (match_dup 1)
4457 (compare:CC (match_dup 3)
4462 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4466 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4467 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4469 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4470 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4471 "includes_rshift_p (operands[2], GEN_INT (255))"
4473 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4475 [(set_attr "type" "delayed_compare")
4476 (set_attr "length" "4,8")])
4479 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4483 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4484 (match_operand:SI 2 "const_int_operand" "")) 0))
4486 (set (match_operand:SI 0 "gpc_reg_operand" "")
4487 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4488 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4490 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4492 (compare:CC (match_dup 0)
4497 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4500 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4501 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4502 "includes_rshift_p (operands[2], GEN_INT (65535))"
4503 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4506 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4510 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4511 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4513 (clobber (match_scratch:SI 3 "=r,r"))]
4514 "includes_rshift_p (operands[2], GEN_INT (65535))"
4516 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4518 [(set_attr "type" "delayed_compare")
4519 (set_attr "length" "4,8")])
4522 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4526 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4527 (match_operand:SI 2 "const_int_operand" "")) 0))
4529 (clobber (match_scratch:SI 3 ""))]
4530 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4532 (zero_extend:SI (subreg:HI
4533 (lshiftrt:SI (match_dup 1)
4536 (compare:CC (match_dup 3)
4541 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4545 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4546 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4548 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4549 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4550 "includes_rshift_p (operands[2], GEN_INT (65535))"
4552 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4554 [(set_attr "type" "delayed_compare")
4555 (set_attr "length" "4,8")])
4558 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4562 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4563 (match_operand:SI 2 "const_int_operand" "")) 0))
4565 (set (match_operand:SI 0 "gpc_reg_operand" "")
4566 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4567 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4569 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4571 (compare:CC (match_dup 0)
4576 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4578 (match_operand:SI 1 "gpc_reg_operand" "r"))
4579 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4585 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4587 (match_operand:SI 1 "gpc_reg_operand" "r"))
4588 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4594 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4596 (match_operand:SI 1 "gpc_reg_operand" "r"))
4597 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4603 (define_expand "ashrsi3"
4604 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4605 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4606 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4611 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4613 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4617 (define_insn "ashrsi3_power"
4618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4619 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4620 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4621 (clobber (match_scratch:SI 3 "=q,X"))]
4625 {srai|srawi} %0,%1,%h2")
4627 (define_insn "ashrsi3_no_power"
4628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4629 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4630 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4632 "{sra|sraw}%I2 %0,%1,%h2")
4635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4636 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4637 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4639 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4640 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4644 {srai.|srawi.} %3,%1,%h2
4647 [(set_attr "type" "delayed_compare")
4648 (set_attr "length" "4,4,8,8")])
4651 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4652 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4653 (match_operand:SI 2 "reg_or_cint_operand" ""))
4655 (clobber (match_scratch:SI 3 ""))
4656 (clobber (match_scratch:SI 4 ""))]
4657 "TARGET_POWER && reload_completed"
4658 [(parallel [(set (match_dup 3)
4659 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4660 (clobber (match_dup 4))])
4662 (compare:CC (match_dup 3)
4667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4668 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4669 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4671 (clobber (match_scratch:SI 3 "=r,r"))]
4674 {sra|sraw}%I2. %3,%1,%h2
4676 [(set_attr "type" "delayed_compare")
4677 (set_attr "length" "4,8")])
4680 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4681 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4682 (match_operand:SI 2 "reg_or_cint_operand" ""))
4684 (clobber (match_scratch:SI 3 ""))]
4685 "! TARGET_POWER && reload_completed"
4687 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4689 (compare:CC (match_dup 3)
4694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4695 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4696 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4699 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4700 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4704 {srai.|srawi.} %0,%1,%h2
4707 [(set_attr "type" "delayed_compare")
4708 (set_attr "length" "4,4,8,8")])
4711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4712 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4713 (match_operand:SI 2 "reg_or_cint_operand" ""))
4715 (set (match_operand:SI 0 "gpc_reg_operand" "")
4716 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4717 (clobber (match_scratch:SI 4 ""))]
4718 "TARGET_POWER && reload_completed"
4719 [(parallel [(set (match_dup 0)
4720 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4721 (clobber (match_dup 4))])
4723 (compare:CC (match_dup 0)
4728 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4729 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4730 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4732 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4733 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4736 {sra|sraw}%I2. %0,%1,%h2
4738 [(set_attr "type" "delayed_compare")
4739 (set_attr "length" "4,8")])
4742 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4743 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4744 (match_operand:SI 2 "reg_or_cint_operand" ""))
4746 (set (match_operand:SI 0 "gpc_reg_operand" "")
4747 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4748 "! TARGET_POWER && reload_completed"
4750 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4752 (compare:CC (match_dup 0)
4756 ;; Floating-point insns, excluding normal data motion.
4758 ;; PowerPC has a full set of single-precision floating point instructions.
4760 ;; For the POWER architecture, we pretend that we have both SFmode and
4761 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4762 ;; The only conversions we will do will be when storing to memory. In that
4763 ;; case, we will use the "frsp" instruction before storing.
4765 ;; Note that when we store into a single-precision memory location, we need to
4766 ;; use the frsp insn first. If the register being stored isn't dead, we
4767 ;; need a scratch register for the frsp. But this is difficult when the store
4768 ;; is done by reload. It is not incorrect to do the frsp on the register in
4769 ;; this case, we just lose precision that we would have otherwise gotten but
4770 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4772 (define_insn "extendsfdf2"
4773 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4774 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4778 if (REGNO (operands[0]) == REGNO (operands[1]))
4781 return \"fmr %0,%1\";
4783 [(set_attr "type" "fp")])
4785 (define_insn "truncdfsf2"
4786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4787 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4790 [(set_attr "type" "fp")])
4792 (define_insn "aux_truncdfsf2"
4793 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4794 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
4795 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4797 [(set_attr "type" "fp")])
4799 (define_insn "negsf2"
4800 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4801 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4804 [(set_attr "type" "fp")])
4806 (define_insn "abssf2"
4807 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4808 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4811 [(set_attr "type" "fp")])
4814 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4815 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4818 [(set_attr "type" "fp")])
4820 (define_expand "addsf3"
4821 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4822 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4823 (match_operand:SF 2 "gpc_reg_operand" "")))]
4828 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4829 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4830 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4831 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4833 [(set_attr "type" "fp")])
4836 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4837 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4838 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4839 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4840 "{fa|fadd} %0,%1,%2"
4841 [(set_attr "type" "fp")])
4843 (define_expand "subsf3"
4844 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4845 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4846 (match_operand:SF 2 "gpc_reg_operand" "")))]
4851 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4852 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4853 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4854 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4856 [(set_attr "type" "fp")])
4859 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4860 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4861 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4862 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4863 "{fs|fsub} %0,%1,%2"
4864 [(set_attr "type" "fp")])
4866 (define_expand "mulsf3"
4867 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4868 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4869 (match_operand:SF 2 "gpc_reg_operand" "")))]
4874 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4875 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4876 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4877 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4879 [(set_attr "type" "fp")])
4882 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4883 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4884 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4885 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4886 "{fm|fmul} %0,%1,%2"
4887 [(set_attr "type" "dmul")])
4889 (define_expand "divsf3"
4890 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4891 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4892 (match_operand:SF 2 "gpc_reg_operand" "")))]
4897 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4898 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4899 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4900 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4902 [(set_attr "type" "sdiv")])
4905 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4906 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4907 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4908 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4909 "{fd|fdiv} %0,%1,%2"
4910 [(set_attr "type" "ddiv")])
4913 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4914 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4915 (match_operand:SF 2 "gpc_reg_operand" "f"))
4916 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4917 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4918 "fmadds %0,%1,%2,%3"
4919 [(set_attr "type" "fp")])
4922 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4923 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4924 (match_operand:SF 2 "gpc_reg_operand" "f"))
4925 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4926 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4927 "{fma|fmadd} %0,%1,%2,%3"
4928 [(set_attr "type" "dmul")])
4931 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4932 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4933 (match_operand:SF 2 "gpc_reg_operand" "f"))
4934 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4935 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4936 "fmsubs %0,%1,%2,%3"
4937 [(set_attr "type" "fp")])
4940 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4941 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4942 (match_operand:SF 2 "gpc_reg_operand" "f"))
4943 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4944 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4945 "{fms|fmsub} %0,%1,%2,%3"
4946 [(set_attr "type" "dmul")])
4949 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4950 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4951 (match_operand:SF 2 "gpc_reg_operand" "f"))
4952 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4953 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4954 "fnmadds %0,%1,%2,%3"
4955 [(set_attr "type" "fp")])
4958 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4959 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4960 (match_operand:SF 2 "gpc_reg_operand" "f"))
4961 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4962 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4963 "{fnma|fnmadd} %0,%1,%2,%3"
4964 [(set_attr "type" "dmul")])
4967 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4968 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4969 (match_operand:SF 2 "gpc_reg_operand" "f"))
4970 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4971 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4972 "fnmsubs %0,%1,%2,%3"
4973 [(set_attr "type" "fp")])
4976 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4977 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4978 (match_operand:SF 2 "gpc_reg_operand" "f"))
4979 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4980 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4981 "{fnms|fnmsub} %0,%1,%2,%3"
4982 [(set_attr "type" "dmul")])
4984 (define_expand "sqrtsf2"
4985 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4986 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4987 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
4991 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4992 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4993 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
4995 [(set_attr "type" "ssqrt")])
4998 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4999 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5000 "TARGET_POWER2 && TARGET_HARD_FLOAT"
5002 [(set_attr "type" "dsqrt")])
5004 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5005 ;; fsel instruction and some auxiliary computations. Then we just have a
5006 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5008 (define_expand "maxsf3"
5009 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5010 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5011 (match_operand:SF 2 "gpc_reg_operand" ""))
5014 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5015 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5017 (define_expand "minsf3"
5018 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5019 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5020 (match_operand:SF 2 "gpc_reg_operand" ""))
5023 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5024 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5027 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5028 (match_operator:SF 3 "min_max_operator"
5029 [(match_operand:SF 1 "gpc_reg_operand" "")
5030 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5031 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5034 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5035 operands[1], operands[2]);
5039 (define_expand "movsfcc"
5040 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5041 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5042 (match_operand:SF 2 "gpc_reg_operand" "")
5043 (match_operand:SF 3 "gpc_reg_operand" "")))]
5044 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5047 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5053 (define_insn "*fselsfsf4"
5054 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5055 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5056 (match_operand:SF 4 "zero_fp_constant" "F"))
5057 (match_operand:SF 2 "gpc_reg_operand" "f")
5058 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5059 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5061 [(set_attr "type" "fp")])
5063 (define_insn "*fseldfsf4"
5064 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5065 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5066 (match_operand:DF 4 "zero_fp_constant" "F"))
5067 (match_operand:SF 2 "gpc_reg_operand" "f")
5068 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5069 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5071 [(set_attr "type" "fp")])
5073 (define_insn "negdf2"
5074 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5075 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5078 [(set_attr "type" "fp")])
5080 (define_insn "absdf2"
5081 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5082 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5085 [(set_attr "type" "fp")])
5088 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5089 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5092 [(set_attr "type" "fp")])
5094 (define_insn "adddf3"
5095 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5096 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5097 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5099 "{fa|fadd} %0,%1,%2"
5100 [(set_attr "type" "fp")])
5102 (define_insn "subdf3"
5103 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5104 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5105 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5107 "{fs|fsub} %0,%1,%2"
5108 [(set_attr "type" "fp")])
5110 (define_insn "muldf3"
5111 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5112 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5113 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5115 "{fm|fmul} %0,%1,%2"
5116 [(set_attr "type" "dmul")])
5118 (define_insn "divdf3"
5119 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5120 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5121 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5123 "{fd|fdiv} %0,%1,%2"
5124 [(set_attr "type" "ddiv")])
5127 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5128 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5129 (match_operand:DF 2 "gpc_reg_operand" "f"))
5130 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5131 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5132 "{fma|fmadd} %0,%1,%2,%3"
5133 [(set_attr "type" "dmul")])
5136 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5137 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5138 (match_operand:DF 2 "gpc_reg_operand" "f"))
5139 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5140 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5141 "{fms|fmsub} %0,%1,%2,%3"
5142 [(set_attr "type" "dmul")])
5145 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5146 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5147 (match_operand:DF 2 "gpc_reg_operand" "f"))
5148 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5149 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5150 "{fnma|fnmadd} %0,%1,%2,%3"
5151 [(set_attr "type" "dmul")])
5154 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5155 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5156 (match_operand:DF 2 "gpc_reg_operand" "f"))
5157 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5158 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5159 "{fnms|fnmsub} %0,%1,%2,%3"
5160 [(set_attr "type" "dmul")])
5162 (define_insn "sqrtdf2"
5163 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5164 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5165 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
5167 [(set_attr "type" "dsqrt")])
5169 ;; The conditional move instructions allow us to perform max and min
5170 ;; operations even when
5172 (define_expand "maxdf3"
5173 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5174 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5175 (match_operand:DF 2 "gpc_reg_operand" ""))
5178 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5179 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5181 (define_expand "mindf3"
5182 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5183 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5184 (match_operand:DF 2 "gpc_reg_operand" ""))
5187 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5188 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5191 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5192 (match_operator:DF 3 "min_max_operator"
5193 [(match_operand:DF 1 "gpc_reg_operand" "")
5194 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5195 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5198 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5199 operands[1], operands[2]);
5203 (define_expand "movdfcc"
5204 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5205 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5206 (match_operand:DF 2 "gpc_reg_operand" "")
5207 (match_operand:DF 3 "gpc_reg_operand" "")))]
5208 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5211 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5217 (define_insn "*fseldfdf4"
5218 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5219 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5220 (match_operand:DF 4 "zero_fp_constant" "F"))
5221 (match_operand:DF 2 "gpc_reg_operand" "f")
5222 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5223 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5225 [(set_attr "type" "fp")])
5227 (define_insn "*fselsfdf4"
5228 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5229 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5230 (match_operand:SF 4 "zero_fp_constant" "F"))
5231 (match_operand:DF 2 "gpc_reg_operand" "f")
5232 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5235 [(set_attr "type" "fp")])
5237 ;; Conversions to and from floating-point.
5239 ; For each of these conversions, there is a define_expand, a define_insn
5240 ; with a '#' template, and a define_split (with C code). The idea is
5241 ; to allow constant folding with the template of the define_insn,
5242 ; then to have the insns split later (between sched1 and final).
5244 (define_expand "floatsidf2"
5245 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5246 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5249 (clobber (match_dup 4))
5250 (clobber (match_dup 5))
5251 (clobber (match_dup 6))])]
5252 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5255 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5256 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
5257 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5258 operands[5] = gen_reg_rtx (DFmode);
5259 operands[6] = gen_reg_rtx (SImode);
5262 (define_insn "*floatsidf2_internal"
5263 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5264 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5265 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5266 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5267 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5268 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))
5269 (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))]
5270 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5272 [(set_attr "length" "24")])
5275 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5276 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5277 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5278 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5279 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5280 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5281 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5282 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5283 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5284 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5285 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5286 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5287 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5288 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5289 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5292 rtx lowword, highword;
5293 if (GET_CODE (operands[4]) != MEM)
5295 highword = XEXP (operands[4], 0);
5296 lowword = plus_constant (highword, 4);
5297 if (! WORDS_BIG_ENDIAN)
5300 tmp = highword; highword = lowword; lowword = tmp;
5303 emit_insn (gen_xorsi3 (operands[6], operands[1],
5304 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5305 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5306 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5307 emit_move_insn (operands[5], operands[4]);
5308 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5312 (define_expand "floatunssidf2"
5313 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5314 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5317 (clobber (match_dup 4))
5318 (clobber (match_dup 5))])]
5319 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5322 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5323 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
5324 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5325 operands[5] = gen_reg_rtx (DFmode);
5328 (define_insn "*floatunssidf2_internal"
5329 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5330 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5331 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5332 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5333 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5334 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))]
5335 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5337 [(set_attr "length" "20")])
5340 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5341 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5342 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5343 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5344 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5345 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5346 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5347 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5348 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5349 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5350 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5351 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5352 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5355 rtx lowword, highword;
5356 if (GET_CODE (operands[4]) != MEM)
5358 highword = XEXP (operands[4], 0);
5359 lowword = plus_constant (highword, 4);
5360 if (! WORDS_BIG_ENDIAN)
5363 tmp = highword; highword = lowword; lowword = tmp;
5366 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5367 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5368 emit_move_insn (operands[5], operands[4]);
5369 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5373 (define_expand "fix_truncdfsi2"
5374 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5375 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5376 (clobber (match_dup 2))
5377 (clobber (match_dup 3))])]
5378 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5381 operands[2] = gen_reg_rtx (DImode);
5382 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5385 (define_insn "*fix_truncdfsi2_internal"
5386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5387 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5388 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5389 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5390 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5392 [(set_attr "length" "16")])
5395 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5396 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5397 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5398 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5399 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5400 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5401 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5402 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5403 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5407 if (GET_CODE (operands[3]) != MEM)
5409 lowword = XEXP (operands[3], 0);
5410 if (WORDS_BIG_ENDIAN)
5411 lowword = plus_constant (lowword, 4);
5413 emit_insn (gen_fctiwz (operands[2], operands[1]));
5414 emit_move_insn (operands[3], operands[2]);
5415 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5419 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5420 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5421 ; because the first makes it clear that operand 0 is not live
5422 ; before the instruction.
5423 (define_insn "fctiwz"
5424 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5425 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
5426 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5427 "{fcirz|fctiwz} %0,%1"
5428 [(set_attr "type" "fp")])
5430 (define_insn "floatdidf2"
5431 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5432 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
5433 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5435 [(set_attr "type" "fp")])
5437 (define_insn "fix_truncdfdi2"
5438 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5439 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5440 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5442 [(set_attr "type" "fp")])
5444 ;; This only is safe if rounding mode set appropriately.
5445 (define_insn_and_split "floatdisf2"
5446 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5447 (float:SF (match_operand:DI 1 "gpc_reg_operand" "f")))
5448 (clobber (match_scratch:DF 2 "=f"))]
5449 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
5451 "&& reload_completed"
5453 (float:DF (match_dup 1)))
5455 (float_truncate:SF (match_dup 2)))]
5458 ;; Define the DImode operations that can be done in a small number
5459 ;; of instructions. The & constraints are to prevent the register
5460 ;; allocator from allocating registers that overlap with the inputs
5461 ;; (for example, having an input in 7,8 and an output in 6,7). We
5462 ;; also allow for the output being the same as one of the inputs.
5464 (define_insn "*adddi3_noppc64"
5465 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5466 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5467 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5468 "! TARGET_POWERPC64"
5471 if (WORDS_BIG_ENDIAN)
5472 return (GET_CODE (operands[2])) != CONST_INT
5473 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5474 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5476 return (GET_CODE (operands[2])) != CONST_INT
5477 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5478 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5480 [(set_attr "length" "8")])
5482 (define_insn "*subdi3_noppc64"
5483 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5484 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5485 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5486 "! TARGET_POWERPC64"
5489 if (WORDS_BIG_ENDIAN)
5490 return (GET_CODE (operands[1]) != CONST_INT)
5491 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5492 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5494 return (GET_CODE (operands[1]) != CONST_INT)
5495 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5496 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5498 [(set_attr "length" "8")])
5500 (define_insn "*negdi2_noppc64"
5501 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5502 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5503 "! TARGET_POWERPC64"
5506 return (WORDS_BIG_ENDIAN)
5507 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5508 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5510 [(set_attr "length" "8")])
5512 (define_expand "mulsidi3"
5513 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5514 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5515 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5516 "! TARGET_POWERPC64"
5519 if (! TARGET_POWER && ! TARGET_POWERPC)
5521 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5522 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5523 emit_insn (gen_mull_call ());
5524 if (WORDS_BIG_ENDIAN)
5525 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5528 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5529 gen_rtx_REG (SImode, 3));
5530 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5531 gen_rtx_REG (SImode, 4));
5535 else if (TARGET_POWER)
5537 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5542 (define_insn "mulsidi3_mq"
5543 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5544 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5545 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5546 (clobber (match_scratch:SI 3 "=q"))]
5548 "mul %0,%1,%2\;mfmq %L0"
5549 [(set_attr "type" "imul")
5550 (set_attr "length" "8")])
5552 (define_insn "*mulsidi3_no_mq"
5553 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5554 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5555 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5556 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5559 return (WORDS_BIG_ENDIAN)
5560 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5561 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5563 [(set_attr "type" "imul")
5564 (set_attr "length" "8")])
5567 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5568 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5569 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5570 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5573 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5574 (sign_extend:DI (match_dup 2)))
5577 (mult:SI (match_dup 1)
5581 int endian = (WORDS_BIG_ENDIAN == 0);
5582 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5583 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5586 (define_expand "umulsidi3"
5587 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5588 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5589 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5590 "TARGET_POWERPC && ! TARGET_POWERPC64"
5595 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5600 (define_insn "umulsidi3_mq"
5601 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5602 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5603 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5604 (clobber (match_scratch:SI 3 "=q"))]
5605 "TARGET_POWERPC && TARGET_POWER"
5608 return (WORDS_BIG_ENDIAN)
5609 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5610 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5612 [(set_attr "type" "imul")
5613 (set_attr "length" "8")])
5615 (define_insn "*umulsidi3_no_mq"
5616 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5617 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5618 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5619 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5622 return (WORDS_BIG_ENDIAN)
5623 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5624 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5626 [(set_attr "type" "imul")
5627 (set_attr "length" "8")])
5630 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5631 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5632 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5633 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5636 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5637 (zero_extend:DI (match_dup 2)))
5640 (mult:SI (match_dup 1)
5644 int endian = (WORDS_BIG_ENDIAN == 0);
5645 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5646 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5649 (define_expand "smulsi3_highpart"
5650 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5652 (lshiftrt:DI (mult:DI (sign_extend:DI
5653 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5655 (match_operand:SI 2 "gpc_reg_operand" "r")))
5660 if (! TARGET_POWER && ! TARGET_POWERPC)
5662 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5663 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5664 emit_insn (gen_mulh_call ());
5665 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5668 else if (TARGET_POWER)
5670 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5675 (define_insn "smulsi3_highpart_mq"
5676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5678 (lshiftrt:DI (mult:DI (sign_extend:DI
5679 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5681 (match_operand:SI 2 "gpc_reg_operand" "r")))
5683 (clobber (match_scratch:SI 3 "=q"))]
5686 [(set_attr "type" "imul")])
5688 (define_insn "*smulsi3_highpart_no_mq"
5689 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5691 (lshiftrt:DI (mult:DI (sign_extend:DI
5692 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5694 (match_operand:SI 2 "gpc_reg_operand" "r")))
5696 "TARGET_POWERPC && ! TARGET_POWER"
5698 [(set_attr "type" "imul")])
5700 (define_expand "umulsi3_highpart"
5701 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5703 (lshiftrt:DI (mult:DI (zero_extend:DI
5704 (match_operand:SI 1 "gpc_reg_operand" ""))
5706 (match_operand:SI 2 "gpc_reg_operand" "")))
5713 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5718 (define_insn "umulsi3_highpart_mq"
5719 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5721 (lshiftrt:DI (mult:DI (zero_extend:DI
5722 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5724 (match_operand:SI 2 "gpc_reg_operand" "r")))
5726 (clobber (match_scratch:SI 3 "=q"))]
5727 "TARGET_POWERPC && TARGET_POWER"
5729 [(set_attr "type" "imul")])
5731 (define_insn "*umulsi3_highpart_no_mq"
5732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5734 (lshiftrt:DI (mult:DI (zero_extend:DI
5735 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5737 (match_operand:SI 2 "gpc_reg_operand" "r")))
5739 "TARGET_POWERPC && ! TARGET_POWER"
5741 [(set_attr "type" "imul")])
5743 ;; If operands 0 and 2 are in the same register, we have a problem. But
5744 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5745 ;; why we have the strange constraints below.
5746 (define_insn "ashldi3_power"
5747 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5748 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5749 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5750 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5753 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5754 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5755 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5756 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5757 [(set_attr "length" "8")])
5759 (define_insn "lshrdi3_power"
5760 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5761 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5762 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5763 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5766 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5767 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5768 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5769 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5770 [(set_attr "length" "8")])
5772 ;; Shift by a variable amount is too complex to be worth open-coding. We
5773 ;; just handle shifts by constants.
5774 (define_insn "ashrdi3_power"
5775 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5776 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5777 (match_operand:SI 2 "const_int_operand" "M,i")))
5778 (clobber (match_scratch:SI 3 "=X,q"))]
5781 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5782 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5783 [(set_attr "length" "8")])
5785 ;; PowerPC64 DImode operations.
5787 (define_expand "adddi3"
5788 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5789 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5790 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5794 if (! TARGET_POWERPC64)
5796 if (non_short_cint_operand (operands[2], DImode))
5800 if (GET_CODE (operands[2]) == CONST_INT
5801 && ! add_operand (operands[2], DImode))
5803 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5804 ? operands[0] : gen_reg_rtx (DImode));
5806 HOST_WIDE_INT val = INTVAL (operands[2]);
5807 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5808 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5810 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5813 /* The ordering here is important for the prolog expander.
5814 When space is allocated from the stack, adding 'low' first may
5815 produce a temporary deallocation (which would be bad). */
5816 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5817 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5822 ;; Discourage ai/addic because of carry but provide it in an alternative
5823 ;; allowing register zero as source.
5825 (define_insn "*adddi3_internal1"
5826 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5827 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5828 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5836 (define_insn "*adddi3_internal2"
5837 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5838 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5839 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5841 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5848 [(set_attr "type" "compare")
5849 (set_attr "length" "4,4,8,8")])
5852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5853 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5854 (match_operand:DI 2 "reg_or_short_operand" ""))
5856 (clobber (match_scratch:DI 3 ""))]
5857 "TARGET_POWERPC64 && reload_completed"
5859 (plus:DI (match_dup 1) (match_dup 2)))
5861 (compare:CC (match_dup 3)
5865 (define_insn "*adddi3_internal3"
5866 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5867 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5868 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5870 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5871 (plus:DI (match_dup 1) (match_dup 2)))]
5878 [(set_attr "type" "compare")
5879 (set_attr "length" "4,4,8,8")])
5882 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5883 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5884 (match_operand:DI 2 "reg_or_short_operand" ""))
5886 (set (match_operand:DI 0 "gpc_reg_operand" "")
5887 (plus:DI (match_dup 1) (match_dup 2)))]
5888 "TARGET_POWERPC64 && reload_completed"
5890 (plus:DI (match_dup 1) (match_dup 2)))
5892 (compare:CC (match_dup 0)
5896 ;; Split an add that we can't do in one insn into two insns, each of which
5897 ;; does one 16-bit part. This is used by combine. Note that the low-order
5898 ;; add should be last in case the result gets used in an address.
5901 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5902 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5903 (match_operand:DI 2 "non_add_cint_operand" "")))]
5905 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5906 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5909 HOST_WIDE_INT val = INTVAL (operands[2]);
5910 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5911 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5913 operands[4] = GEN_INT (low);
5914 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5915 operands[3] = GEN_INT (rest);
5916 else if (! no_new_pseudos)
5918 operands[3] = gen_reg_rtx (DImode);
5919 emit_move_insn (operands[3], operands[2]);
5920 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5927 (define_insn "one_cmpldi2"
5928 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5929 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5934 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5935 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5937 (clobber (match_scratch:DI 2 "=r,r"))]
5942 [(set_attr "type" "compare")
5943 (set_attr "length" "4,8")])
5946 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5947 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5949 (clobber (match_scratch:DI 2 ""))]
5950 "TARGET_POWERPC64 && reload_completed"
5952 (not:DI (match_dup 1)))
5954 (compare:CC (match_dup 2)
5959 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5960 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5962 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5963 (not:DI (match_dup 1)))]
5968 [(set_attr "type" "compare")
5969 (set_attr "length" "4,8")])
5972 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5973 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5975 (set (match_operand:DI 0 "gpc_reg_operand" "")
5976 (not:DI (match_dup 1)))]
5977 "TARGET_POWERPC64 && reload_completed"
5979 (not:DI (match_dup 1)))
5981 (compare:CC (match_dup 0)
5986 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5987 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5988 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5996 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5997 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5999 (clobber (match_scratch:DI 3 "=r,r"))]
6004 [(set_attr "type" "compare")
6005 (set_attr "length" "4,8")])
6008 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6009 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6010 (match_operand:DI 2 "gpc_reg_operand" ""))
6012 (clobber (match_scratch:DI 3 ""))]
6013 "TARGET_POWERPC64 && reload_completed"
6015 (minus:DI (match_dup 1) (match_dup 2)))
6017 (compare:CC (match_dup 3)
6022 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6023 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6024 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6026 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6027 (minus:DI (match_dup 1) (match_dup 2)))]
6032 [(set_attr "type" "compare")
6033 (set_attr "length" "4,8")])
6036 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6037 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6038 (match_operand:DI 2 "gpc_reg_operand" ""))
6040 (set (match_operand:DI 0 "gpc_reg_operand" "")
6041 (minus:DI (match_dup 1) (match_dup 2)))]
6042 "TARGET_POWERPC64 && reload_completed"
6044 (minus:DI (match_dup 1) (match_dup 2)))
6046 (compare:CC (match_dup 0)
6050 (define_expand "subdi3"
6051 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6052 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6053 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6057 if (GET_CODE (operands[2]) == CONST_INT)
6059 emit_insn (gen_adddi3 (operands[0], operands[1],
6060 negate_rtx (DImode, operands[2])));
6065 (define_insn_and_split "absdi2"
6066 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6067 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6068 (clobber (match_scratch:DI 2 "=&r,&r"))]
6071 "&& reload_completed"
6072 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6073 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6074 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6077 (define_insn_and_split "*nabsdi2"
6078 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6079 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6080 (clobber (match_scratch:DI 2 "=&r,&r"))]
6083 "&& reload_completed"
6084 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6085 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6086 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6089 (define_expand "negdi2"
6090 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6091 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6096 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6097 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6102 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6103 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6105 (clobber (match_scratch:DI 2 "=r,r"))]
6110 [(set_attr "type" "compare")
6111 (set_attr "length" "4,8")])
6114 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6115 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6117 (clobber (match_scratch:DI 2 ""))]
6118 "TARGET_POWERPC64 && reload_completed"
6120 (neg:DI (match_dup 1)))
6122 (compare:CC (match_dup 2)
6127 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6128 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6130 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6131 (neg:DI (match_dup 1)))]
6136 [(set_attr "type" "compare")
6137 (set_attr "length" "4,8")])
6140 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6141 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6143 (set (match_operand:DI 0 "gpc_reg_operand" "")
6144 (neg:DI (match_dup 1)))]
6145 "TARGET_POWERPC64 && reload_completed"
6147 (neg:DI (match_dup 1)))
6149 (compare:CC (match_dup 0)
6153 (define_insn "ffsdi2"
6154 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6155 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6157 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
6158 [(set_attr "length" "16")])
6160 (define_insn "muldi3"
6161 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6162 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6163 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6166 [(set_attr "type" "lmul")])
6168 (define_insn "smuldi3_highpart"
6169 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6171 (lshiftrt:TI (mult:TI (sign_extend:TI
6172 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6174 (match_operand:DI 2 "gpc_reg_operand" "r")))
6178 [(set_attr "type" "lmul")])
6180 (define_insn "umuldi3_highpart"
6181 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6183 (lshiftrt:TI (mult:TI (zero_extend:TI
6184 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6186 (match_operand:DI 2 "gpc_reg_operand" "r")))
6190 [(set_attr "type" "lmul")])
6192 (define_expand "divdi3"
6193 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6194 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6195 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6199 if (GET_CODE (operands[2]) == CONST_INT
6200 && INTVAL (operands[2]) > 0
6201 && exact_log2 (INTVAL (operands[2])) >= 0)
6204 operands[2] = force_reg (DImode, operands[2]);
6207 (define_expand "moddi3"
6208 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6209 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6210 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6218 if (GET_CODE (operands[2]) != CONST_INT
6219 || INTVAL (operands[2]) <= 0
6220 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6223 temp1 = gen_reg_rtx (DImode);
6224 temp2 = gen_reg_rtx (DImode);
6226 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6227 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6228 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6233 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6234 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6235 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6237 "sradi %0,%1,%p2\;addze %0,%0"
6238 [(set_attr "length" "8")])
6241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6242 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6243 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6245 (clobber (match_scratch:DI 3 "=r,r"))]
6248 sradi %3,%1,%p2\;addze. %3,%3
6250 [(set_attr "type" "compare")
6251 (set_attr "length" "8,12")])
6254 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6255 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6256 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6258 (clobber (match_scratch:DI 3 ""))]
6259 "TARGET_POWERPC64 && reload_completed"
6261 (div:DI (match_dup 1) (match_dup 2)))
6263 (compare:CC (match_dup 3)
6268 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6269 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6270 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6272 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6273 (div:DI (match_dup 1) (match_dup 2)))]
6276 sradi %0,%1,%p2\;addze. %0,%0
6278 [(set_attr "type" "compare")
6279 (set_attr "length" "8,12")])
6282 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6283 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6284 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6286 (set (match_operand:DI 0 "gpc_reg_operand" "")
6287 (div:DI (match_dup 1) (match_dup 2)))]
6288 "TARGET_POWERPC64 && reload_completed"
6290 (div:DI (match_dup 1) (match_dup 2)))
6292 (compare:CC (match_dup 0)
6297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6298 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6299 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6302 [(set_attr "type" "ldiv")])
6304 (define_insn "udivdi3"
6305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6306 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6307 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6310 [(set_attr "type" "ldiv")])
6312 (define_insn "rotldi3"
6313 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6314 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6315 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6317 "rld%I2cl %0,%1,%H2,0")
6319 (define_insn "*rotldi3_internal2"
6320 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6321 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6322 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6324 (clobber (match_scratch:DI 3 "=r,r"))]
6327 rld%I2cl. %3,%1,%H2,0
6329 [(set_attr "type" "delayed_compare")
6330 (set_attr "length" "4,8")])
6333 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6334 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6335 (match_operand:DI 2 "reg_or_cint_operand" ""))
6337 (clobber (match_scratch:DI 3 ""))]
6338 "TARGET_POWERPC64 && reload_completed"
6340 (rotate:DI (match_dup 1) (match_dup 2)))
6342 (compare:CC (match_dup 3)
6346 (define_insn "*rotldi3_internal3"
6347 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6348 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6349 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6351 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6352 (rotate:DI (match_dup 1) (match_dup 2)))]
6355 rld%I2cl. %0,%1,%H2,0
6357 [(set_attr "type" "delayed_compare")
6358 (set_attr "length" "4,8")])
6361 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6362 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6363 (match_operand:DI 2 "reg_or_cint_operand" ""))
6365 (set (match_operand:DI 0 "gpc_reg_operand" "")
6366 (rotate:DI (match_dup 1) (match_dup 2)))]
6367 "TARGET_POWERPC64 && reload_completed"
6369 (rotate:DI (match_dup 1) (match_dup 2)))
6371 (compare:CC (match_dup 0)
6375 (define_insn "*rotldi3_internal4"
6376 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6377 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6378 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6379 (match_operand:DI 3 "mask64_operand" "S")))]
6381 "rld%I2c%B3 %0,%1,%H2,%S3")
6383 (define_insn "*rotldi3_internal5"
6384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6386 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6387 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6388 (match_operand:DI 3 "mask64_operand" "S,S"))
6390 (clobber (match_scratch:DI 4 "=r,r"))]
6393 rld%I2c%B3. %4,%1,%H2,%S3
6395 [(set_attr "type" "delayed_compare")
6396 (set_attr "length" "4,8")])
6399 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6401 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6402 (match_operand:DI 2 "reg_or_cint_operand" ""))
6403 (match_operand:DI 3 "mask64_operand" ""))
6405 (clobber (match_scratch:DI 4 ""))]
6406 "TARGET_POWERPC64 && reload_completed"
6408 (and:DI (rotate:DI (match_dup 1)
6412 (compare:CC (match_dup 4)
6416 (define_insn "*rotldi3_internal6"
6417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6419 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6420 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6421 (match_operand:DI 3 "mask64_operand" "S,S"))
6423 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6424 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6427 rld%I2c%B3. %0,%1,%H2,%S3
6429 [(set_attr "type" "delayed_compare")
6430 (set_attr "length" "4,8")])
6433 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6435 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6436 (match_operand:DI 2 "reg_or_cint_operand" ""))
6437 (match_operand:DI 3 "mask64_operand" ""))
6439 (set (match_operand:DI 0 "gpc_reg_operand" "")
6440 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6441 "TARGET_POWERPC64 && reload_completed"
6443 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6445 (compare:CC (match_dup 0)
6449 (define_insn "*rotldi3_internal7"
6450 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6453 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6454 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6456 "rld%I2cl %0,%1,%H2,56")
6458 (define_insn "*rotldi3_internal8"
6459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6460 (compare:CC (zero_extend:DI
6462 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6463 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6465 (clobber (match_scratch:DI 3 "=r,r"))]
6468 rld%I2cl. %3,%1,%H2,56
6470 [(set_attr "type" "delayed_compare")
6471 (set_attr "length" "4,8")])
6474 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6475 (compare:CC (zero_extend:DI
6477 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6478 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6480 (clobber (match_scratch:DI 3 ""))]
6481 "TARGET_POWERPC64 && reload_completed"
6483 (zero_extend:DI (subreg:QI
6484 (rotate:DI (match_dup 1)
6487 (compare:CC (match_dup 3)
6491 (define_insn "*rotldi3_internal9"
6492 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6493 (compare:CC (zero_extend:DI
6495 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6496 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6498 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6499 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6502 rld%I2cl. %0,%1,%H2,56
6504 [(set_attr "type" "delayed_compare")
6505 (set_attr "length" "4,8")])
6508 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6509 (compare:CC (zero_extend:DI
6511 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6512 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6514 (set (match_operand:DI 0 "gpc_reg_operand" "")
6515 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6516 "TARGET_POWERPC64 && reload_completed"
6518 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6520 (compare:CC (match_dup 0)
6524 (define_insn "*rotldi3_internal10"
6525 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6528 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6529 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6531 "rld%I2cl %0,%1,%H2,48")
6533 (define_insn "*rotldi3_internal11"
6534 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6535 (compare:CC (zero_extend:DI
6537 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6538 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6540 (clobber (match_scratch:DI 3 "=r,r"))]
6543 rld%I2cl. %3,%1,%H2,48
6545 [(set_attr "type" "delayed_compare")
6546 (set_attr "length" "4,8")])
6549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6550 (compare:CC (zero_extend:DI
6552 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6553 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6555 (clobber (match_scratch:DI 3 ""))]
6556 "TARGET_POWERPC64 && reload_completed"
6558 (zero_extend:DI (subreg:HI
6559 (rotate:DI (match_dup 1)
6562 (compare:CC (match_dup 3)
6566 (define_insn "*rotldi3_internal12"
6567 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6568 (compare:CC (zero_extend:DI
6570 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6571 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6573 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6574 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6577 rld%I2cl. %0,%1,%H2,48
6579 [(set_attr "type" "delayed_compare")
6580 (set_attr "length" "4,8")])
6583 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6584 (compare:CC (zero_extend:DI
6586 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6587 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6589 (set (match_operand:DI 0 "gpc_reg_operand" "")
6590 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6591 "TARGET_POWERPC64 && reload_completed"
6593 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6595 (compare:CC (match_dup 0)
6599 (define_insn "*rotldi3_internal13"
6600 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6603 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6604 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6606 "rld%I2cl %0,%1,%H2,32")
6608 (define_insn "*rotldi3_internal14"
6609 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6610 (compare:CC (zero_extend:DI
6612 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6613 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6615 (clobber (match_scratch:DI 3 "=r,r"))]
6618 rld%I2cl. %3,%1,%H2,32
6620 [(set_attr "type" "delayed_compare")
6621 (set_attr "length" "4,8")])
6624 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6625 (compare:CC (zero_extend:DI
6627 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6628 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6630 (clobber (match_scratch:DI 3 ""))]
6631 "TARGET_POWERPC64 && reload_completed"
6633 (zero_extend:DI (subreg:SI
6634 (rotate:DI (match_dup 1)
6637 (compare:CC (match_dup 3)
6641 (define_insn "*rotldi3_internal15"
6642 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6643 (compare:CC (zero_extend:DI
6645 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6646 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6648 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6649 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6652 rld%I2cl. %0,%1,%H2,32
6654 [(set_attr "type" "delayed_compare")
6655 (set_attr "length" "4,8")])
6658 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6659 (compare:CC (zero_extend:DI
6661 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6662 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6664 (set (match_operand:DI 0 "gpc_reg_operand" "")
6665 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6666 "TARGET_POWERPC64 && reload_completed"
6668 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6670 (compare:CC (match_dup 0)
6674 (define_expand "ashldi3"
6675 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6676 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6677 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6678 "TARGET_POWERPC64 || TARGET_POWER"
6681 if (TARGET_POWERPC64)
6683 else if (TARGET_POWER)
6685 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6692 (define_insn "*ashldi3_internal1"
6693 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6694 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6695 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6698 [(set_attr "length" "8")])
6700 (define_insn "*ashldi3_internal2"
6701 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6702 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6703 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6705 (clobber (match_scratch:DI 3 "=r,r"))]
6710 [(set_attr "type" "delayed_compare")
6711 (set_attr "length" "4,8")])
6714 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6715 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6716 (match_operand:SI 2 "reg_or_cint_operand" ""))
6718 (clobber (match_scratch:DI 3 ""))]
6719 "TARGET_POWERPC64 && reload_completed"
6721 (ashift:DI (match_dup 1) (match_dup 2)))
6723 (compare:CC (match_dup 3)
6727 (define_insn "*ashldi3_internal3"
6728 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6729 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6730 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6732 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6733 (ashift:DI (match_dup 1) (match_dup 2)))]
6738 [(set_attr "type" "delayed_compare")
6739 (set_attr "length" "4,8")])
6742 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6743 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6744 (match_operand:SI 2 "reg_or_cint_operand" ""))
6746 (set (match_operand:DI 0 "gpc_reg_operand" "")
6747 (ashift:DI (match_dup 1) (match_dup 2)))]
6748 "TARGET_POWERPC64 && reload_completed"
6750 (ashift:DI (match_dup 1) (match_dup 2)))
6752 (compare:CC (match_dup 0)
6756 (define_insn "*ashldi3_internal4"
6757 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6758 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6759 (match_operand:SI 2 "const_int_operand" "i"))
6760 (match_operand:DI 3 "const_int_operand" "n")))]
6761 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6762 "rldic %0,%1,%H2,%W3")
6764 (define_insn "ashldi3_internal5"
6765 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6767 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6768 (match_operand:SI 2 "const_int_operand" "i,i"))
6769 (match_operand:DI 3 "const_int_operand" "n,n"))
6771 (clobber (match_scratch:DI 4 "=r,r"))]
6772 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6774 rldic. %4,%1,%H2,%W3
6776 [(set_attr "type" "delayed_compare")
6777 (set_attr "length" "4,8")])
6780 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6782 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6783 (match_operand:SI 2 "const_int_operand" ""))
6784 (match_operand:DI 3 "const_int_operand" ""))
6786 (clobber (match_scratch:DI 4 ""))]
6787 "TARGET_POWERPC64 && reload_completed
6788 && includes_rldic_lshift_p (operands[2], operands[3])"
6790 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6793 (compare:CC (match_dup 4)
6797 (define_insn "*ashldi3_internal6"
6798 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6800 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6801 (match_operand:SI 2 "const_int_operand" "i,i"))
6802 (match_operand:DI 3 "const_int_operand" "n,n"))
6804 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6805 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6806 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6808 rldic. %0,%1,%H2,%W3
6810 [(set_attr "type" "delayed_compare")
6811 (set_attr "length" "4,8")])
6814 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6816 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6817 (match_operand:SI 2 "const_int_operand" ""))
6818 (match_operand:DI 3 "const_int_operand" ""))
6820 (set (match_operand:DI 0 "gpc_reg_operand" "")
6821 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6822 "TARGET_POWERPC64 && reload_completed
6823 && includes_rldic_lshift_p (operands[2], operands[3])"
6825 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6828 (compare:CC (match_dup 0)
6832 (define_insn "*ashldi3_internal7"
6833 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6834 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6835 (match_operand:SI 2 "const_int_operand" "i"))
6836 (match_operand:DI 3 "mask64_operand" "S")))]
6837 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6838 "rldicr %0,%1,%H2,%S3")
6840 (define_insn "ashldi3_internal8"
6841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6843 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6844 (match_operand:SI 2 "const_int_operand" "i,i"))
6845 (match_operand:DI 3 "mask64_operand" "S,S"))
6847 (clobber (match_scratch:DI 4 "=r,r"))]
6848 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6850 rldicr. %4,%1,%H2,%S3
6852 [(set_attr "type" "delayed_compare")
6853 (set_attr "length" "4,8")])
6856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6858 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6859 (match_operand:SI 2 "const_int_operand" ""))
6860 (match_operand:DI 3 "mask64_operand" ""))
6862 (clobber (match_scratch:DI 4 ""))]
6863 "TARGET_POWERPC64 && reload_completed
6864 && includes_rldicr_lshift_p (operands[2], operands[3])"
6866 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6869 (compare:CC (match_dup 4)
6873 (define_insn "*ashldi3_internal9"
6874 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6876 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6877 (match_operand:SI 2 "const_int_operand" "i,i"))
6878 (match_operand:DI 3 "mask64_operand" "S,S"))
6880 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6881 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6882 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6884 rldicr. %0,%1,%H2,%S3
6886 [(set_attr "type" "delayed_compare")
6887 (set_attr "length" "4,8")])
6890 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6892 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6893 (match_operand:SI 2 "const_int_operand" ""))
6894 (match_operand:DI 3 "mask64_operand" ""))
6896 (set (match_operand:DI 0 "gpc_reg_operand" "")
6897 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6898 "TARGET_POWERPC64 && reload_completed
6899 && includes_rldicr_lshift_p (operands[2], operands[3])"
6901 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6904 (compare:CC (match_dup 0)
6908 (define_expand "lshrdi3"
6909 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6910 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6911 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6912 "TARGET_POWERPC64 || TARGET_POWER"
6915 if (TARGET_POWERPC64)
6917 else if (TARGET_POWER)
6919 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6926 (define_insn "*lshrdi3_internal1"
6927 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6928 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6929 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6933 (define_insn "*lshrdi3_internal2"
6934 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6935 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6936 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6938 (clobber (match_scratch:DI 3 "=r,r"))]
6943 [(set_attr "type" "delayed_compare")
6944 (set_attr "length" "4,8")])
6947 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6948 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6949 (match_operand:SI 2 "reg_or_cint_operand" ""))
6951 (clobber (match_scratch:DI 3 ""))]
6952 "TARGET_POWERPC64 && reload_completed"
6954 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6956 (compare:CC (match_dup 3)
6960 (define_insn "*lshrdi3_internal3"
6961 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6962 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6963 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6965 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6966 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6971 [(set_attr "type" "delayed_compare")
6972 (set_attr "length" "4,8")])
6975 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6976 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6977 (match_operand:SI 2 "reg_or_cint_operand" ""))
6979 (set (match_operand:DI 0 "gpc_reg_operand" "")
6980 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6981 "TARGET_POWERPC64 && reload_completed"
6983 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6985 (compare:CC (match_dup 0)
6989 (define_expand "ashrdi3"
6990 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6991 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6993 "TARGET_POWERPC64 || TARGET_POWER"
6996 if (TARGET_POWERPC64)
6998 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7000 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7007 (define_insn "*ashrdi3_internal1"
7008 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7009 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7010 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7012 "srad%I2 %0,%1,%H2")
7014 (define_insn "*ashrdi3_internal2"
7015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7016 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7017 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7019 (clobber (match_scratch:DI 3 "=r,r"))]
7024 [(set_attr "type" "delayed_compare")
7025 (set_attr "length" "4,8")])
7028 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7029 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7030 (match_operand:SI 2 "reg_or_cint_operand" ""))
7032 (clobber (match_scratch:DI 3 ""))]
7033 "TARGET_POWERPC64 && reload_completed"
7035 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7037 (compare:CC (match_dup 3)
7041 (define_insn "*ashrdi3_internal3"
7042 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7043 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7044 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7046 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7047 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7052 [(set_attr "type" "delayed_compare")
7053 (set_attr "length" "4,8")])
7056 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7057 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7058 (match_operand:SI 2 "reg_or_cint_operand" ""))
7060 (set (match_operand:DI 0 "gpc_reg_operand" "")
7061 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7062 "TARGET_POWERPC64 && reload_completed"
7064 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7066 (compare:CC (match_dup 0)
7070 (define_insn "anddi3"
7071 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7072 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7073 (match_operand:DI 2 "and64_operand" "?r,S,K,J")))
7074 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
7078 rldic%B2 %0,%1,0,%S2
7082 (define_insn "*anddi3_internal2"
7083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
7084 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,")
7085 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
7087 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r"))
7088 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
7092 rldic%B2. %3,%1,0,%S2
7099 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
7100 (set_attr "length" "4,4,4,4,8,8,8,8")])
7103 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7104 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7105 (match_operand:DI 2 "and64_operand" ""))
7107 (clobber (match_scratch:DI 3 ""))
7108 (clobber (match_scratch:CC 4 ""))]
7109 "TARGET_POWERPC64 && reload_completed"
7110 [(parallel [(set (match_dup 3)
7111 (and:DI (match_dup 1)
7113 (clobber (match_dup 4))])
7115 (compare:CC (match_dup 3)
7119 (define_insn "*anddi3_internal3"
7120 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
7121 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
7122 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
7124 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
7125 (and:DI (match_dup 1) (match_dup 2)))
7126 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
7130 rldic%B2. %0,%1,0,%S2
7137 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
7138 (set_attr "length" "4,4,4,4,8,8,8,8")])
7141 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7142 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7143 (match_operand:DI 2 "and64_operand" ""))
7145 (set (match_operand:DI 0 "gpc_reg_operand" "")
7146 (and:DI (match_dup 1) (match_dup 2)))
7147 (clobber (match_scratch:CC 4 ""))]
7148 "TARGET_POWERPC64 && reload_completed"
7149 [(parallel [(set (match_dup 0)
7150 (and:DI (match_dup 1) (match_dup 2)))
7151 (clobber (match_dup 4))])
7153 (compare:CC (match_dup 0)
7157 (define_expand "iordi3"
7158 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7159 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7160 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7164 if (non_logical_cint_operand (operands[2], DImode))
7166 HOST_WIDE_INT value;
7167 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7168 ? operands[0] : gen_reg_rtx (DImode));
7170 if (GET_CODE (operands[2]) == CONST_INT)
7172 value = INTVAL (operands[2]);
7173 emit_insn (gen_iordi3 (tmp, operands[1],
7174 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7178 value = CONST_DOUBLE_LOW (operands[2]);
7179 emit_insn (gen_iordi3 (tmp, operands[1],
7180 immed_double_const (value
7181 & (~ (HOST_WIDE_INT) 0xffff),
7185 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7190 (define_expand "xordi3"
7191 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7192 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7193 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7197 if (non_logical_cint_operand (operands[2], DImode))
7199 HOST_WIDE_INT value;
7200 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7201 ? operands[0] : gen_reg_rtx (DImode));
7203 if (GET_CODE (operands[2]) == CONST_INT)
7205 value = INTVAL (operands[2]);
7206 emit_insn (gen_xordi3 (tmp, operands[1],
7207 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7211 value = CONST_DOUBLE_LOW (operands[2]);
7212 emit_insn (gen_xordi3 (tmp, operands[1],
7213 immed_double_const (value
7214 & (~ (HOST_WIDE_INT) 0xffff),
7218 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7223 (define_insn "*booldi3_internal1"
7224 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7225 (match_operator:DI 3 "boolean_or_operator"
7226 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7227 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7234 (define_insn "*booldi3_internal2"
7235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7236 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7237 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7238 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7240 (clobber (match_scratch:DI 3 "=r,r"))]
7245 [(set_attr "type" "compare")
7246 (set_attr "length" "4,8")])
7249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7250 (compare:CC (match_operator:DI 4 "boolean_operator"
7251 [(match_operand:DI 1 "gpc_reg_operand" "")
7252 (match_operand:DI 2 "gpc_reg_operand" "")])
7254 (clobber (match_scratch:DI 3 ""))]
7255 "TARGET_POWERPC64 && reload_completed"
7256 [(set (match_dup 3) (match_dup 4))
7258 (compare:CC (match_dup 3)
7262 (define_insn "*booldi3_internal3"
7263 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7264 (compare:CC (match_operator:DI 4 "boolean_operator"
7265 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7266 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7268 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7274 [(set_attr "type" "compare")
7275 (set_attr "length" "4,8")])
7278 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7279 (compare:CC (match_operator:DI 4 "boolean_operator"
7280 [(match_operand:DI 1 "gpc_reg_operand" "")
7281 (match_operand:DI 2 "gpc_reg_operand" "")])
7283 (set (match_operand:DI 0 "gpc_reg_operand" "")
7285 "TARGET_POWERPC64 && reload_completed"
7286 [(set (match_dup 0) (match_dup 4))
7288 (compare:CC (match_dup 0)
7292 ;; Split an logical operation that we can't do in one insn into two insns,
7293 ;; each of which does one 16-bit part. This is used by combine.
7296 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7297 (match_operator:DI 3 "boolean_or_operator"
7298 [(match_operand:DI 1 "gpc_reg_operand" "")
7299 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7301 [(set (match_dup 0) (match_dup 4))
7302 (set (match_dup 0) (match_dup 5))]
7307 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7309 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7310 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7312 i4 = GEN_INT (value & 0xffff);
7316 i3 = GEN_INT (INTVAL (operands[2])
7317 & (~ (HOST_WIDE_INT) 0xffff));
7318 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7320 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7322 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7326 (define_insn "*boolcdi3_internal1"
7327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7328 (match_operator:DI 3 "boolean_operator"
7329 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7330 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7334 (define_insn "*boolcdi3_internal2"
7335 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7336 (compare:CC (match_operator:DI 4 "boolean_operator"
7337 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7338 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7340 (clobber (match_scratch:DI 3 "=r,r"))]
7345 [(set_attr "type" "compare")
7346 (set_attr "length" "4,8")])
7349 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7350 (compare:CC (match_operator:DI 4 "boolean_operator"
7351 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7352 (match_operand:DI 2 "gpc_reg_operand" "")])
7354 (clobber (match_scratch:DI 3 ""))]
7355 "TARGET_POWERPC64 && reload_completed"
7356 [(set (match_dup 3) (match_dup 4))
7358 (compare:CC (match_dup 3)
7362 (define_insn "*boolcdi3_internal3"
7363 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7364 (compare:CC (match_operator:DI 4 "boolean_operator"
7365 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7366 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7368 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7374 [(set_attr "type" "compare")
7375 (set_attr "length" "4,8")])
7378 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7379 (compare:CC (match_operator:DI 4 "boolean_operator"
7380 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7381 (match_operand:DI 2 "gpc_reg_operand" "")])
7383 (set (match_operand:DI 0 "gpc_reg_operand" "")
7385 "TARGET_POWERPC64 && reload_completed"
7386 [(set (match_dup 0) (match_dup 4))
7388 (compare:CC (match_dup 0)
7392 (define_insn "*boolccdi3_internal1"
7393 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7394 (match_operator:DI 3 "boolean_operator"
7395 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7396 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7400 (define_insn "*boolccdi3_internal2"
7401 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7402 (compare:CC (match_operator:DI 4 "boolean_operator"
7403 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7404 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7406 (clobber (match_scratch:DI 3 "=r,r"))]
7411 [(set_attr "type" "compare")
7412 (set_attr "length" "4,8")])
7415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7416 (compare:CC (match_operator:DI 4 "boolean_operator"
7417 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7418 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7420 (clobber (match_scratch:DI 3 ""))]
7421 "TARGET_POWERPC64 && reload_completed"
7422 [(set (match_dup 3) (match_dup 4))
7424 (compare:CC (match_dup 3)
7428 (define_insn "*boolccdi3_internal3"
7429 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7430 (compare:CC (match_operator:DI 4 "boolean_operator"
7431 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7432 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7434 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7440 [(set_attr "type" "compare")
7441 (set_attr "length" "4,8")])
7444 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7445 (compare:CC (match_operator:DI 4 "boolean_operator"
7446 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7447 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7449 (set (match_operand:DI 0 "gpc_reg_operand" "")
7451 "TARGET_POWERPC64 && reload_completed"
7452 [(set (match_dup 0) (match_dup 4))
7454 (compare:CC (match_dup 0)
7458 ;; Now define ways of moving data around.
7460 ;; Elf specific ways of loading addresses for non-PIC code.
7461 ;; The output of this could be r0, but we make a very strong
7462 ;; preference for a base register because it will usually
7464 (define_insn "elf_high"
7465 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7466 (high:SI (match_operand 1 "" "")))]
7467 "TARGET_ELF && ! TARGET_64BIT"
7468 "{liu|lis} %0,%1@ha")
7470 (define_insn "elf_low"
7471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7472 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7473 (match_operand 2 "" "")))]
7474 "TARGET_ELF && ! TARGET_64BIT"
7476 {cal|la} %0,%2@l(%1)
7477 {ai|addic} %0,%1,%K2")
7479 ;; Mach-O PIC trickery.
7480 (define_insn "macho_high"
7481 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7482 (high:SI (match_operand 1 "" "")))]
7483 "TARGET_MACHO && ! TARGET_64BIT"
7484 "{liu|lis} %0,ha16(%1)")
7486 (define_insn "macho_low"
7487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7488 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7489 (match_operand 2 "" "")))]
7490 "TARGET_MACHO && ! TARGET_64BIT"
7492 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7493 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7495 ;; Set up a register with a value from the GOT table
7497 (define_expand "movsi_got"
7498 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7499 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7501 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7504 if (GET_CODE (operands[1]) == CONST)
7506 rtx offset = const0_rtx;
7507 HOST_WIDE_INT value;
7509 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7510 value = INTVAL (offset);
7513 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7514 emit_insn (gen_movsi_got (tmp, operands[1]));
7515 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7520 operands[2] = rs6000_got_register (operands[1]);
7523 (define_insn "*movsi_got_internal"
7524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7525 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7526 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
7527 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7528 "{l|lwz} %0,%a1@got(%2)"
7529 [(set_attr "type" "load")])
7531 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7532 ;; didn't get allocated to a hard register.
7534 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7535 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7536 (match_operand:SI 2 "memory_operand" "")] 8))]
7537 "DEFAULT_ABI == ABI_V4
7539 && (reload_in_progress || reload_completed)"
7540 [(set (match_dup 0) (match_dup 2))
7541 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
7544 ;; For SI, we special-case integers that can't be loaded in one insn. We
7545 ;; do the load 16-bits at a time. We could do this by loading from memory,
7546 ;; and this is even supposed to be faster, but it is simpler not to get
7547 ;; integers in the TOC.
7548 (define_expand "movsi"
7549 [(set (match_operand:SI 0 "general_operand" "")
7550 (match_operand:SI 1 "any_operand" ""))]
7552 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7554 (define_insn "movsi_low"
7555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7556 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7557 (match_operand 2 "" ""))))]
7558 "TARGET_MACHO && ! TARGET_64BIT"
7559 "{l|lwz} %0,lo16(%2)(%1)"
7560 [(set_attr "type" "load")
7561 (set_attr "length" "4")])
7563 (define_insn "movsi_low_st"
7564 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7565 (match_operand 2 "" "")))
7566 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7567 "TARGET_MACHO && ! TARGET_64BIT"
7568 "{st|stw} %0,lo16(%2)(%1)"
7569 [(set_attr "type" "store")
7570 (set_attr "length" "4")])
7572 (define_insn "movdf_low"
7573 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7574 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7575 (match_operand 2 "" ""))))]
7576 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
7579 switch (which_alternative)
7582 return \"lfd %0,lo16(%2)(%1)\";
7586 operands2[0] = operands[0];
7587 operands2[1] = operands[1];
7588 operands2[2] = operands[2];
7589 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7590 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7591 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7592 although in practice it almost always is. */
7593 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7594 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7600 [(set_attr "type" "load")
7601 (set_attr "length" "4,12")])
7603 (define_insn "movdf_low_st"
7604 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7605 (match_operand 2 "" "")))
7606 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7607 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
7608 "stfd %0,lo16(%2)(%1)"
7609 [(set_attr "type" "store")
7610 (set_attr "length" "4")])
7612 (define_insn "movsf_low"
7613 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7614 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7615 (match_operand 2 "" ""))))]
7616 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
7619 {l|lwz} %0,lo16(%2)(%1)"
7620 [(set_attr "type" "load")
7621 (set_attr "length" "4")])
7623 (define_insn "movsf_low_st"
7624 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7625 (match_operand 2 "" "")))
7626 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7627 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
7629 stfs %0,lo16(%2)(%1)
7630 {st|stw} %0,lo16(%2)(%1)"
7631 [(set_attr "type" "store")
7632 (set_attr "length" "4")])
7634 (define_insn "*movsi_internal1"
7635 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7636 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7637 "gpc_reg_operand (operands[0], SImode)
7638 || gpc_reg_operand (operands[1], SImode)"
7642 {l%U1%X1|lwz%U1%X1} %0,%1
7643 {st%U0%X0|stw%U0%X0} %1,%0
7653 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
7654 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7656 ;; Split a load of a large constant into the appropriate two-insn
7660 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7661 (match_operand:SI 1 "const_int_operand" ""))]
7662 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7663 && (INTVAL (operands[1]) & 0xffff) != 0"
7667 (ior:SI (match_dup 0)
7671 operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff));
7672 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
7675 (define_insn "*movsi_internal2"
7676 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
7677 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
7679 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
7680 "! TARGET_POWERPC64"
7684 [(set_attr "type" "compare")
7685 (set_attr "length" "4,8")])
7688 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7689 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7691 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7692 "! TARGET_POWERPC64 && reload_completed"
7693 [(set (match_dup 0) (match_dup 1))
7695 (compare:CC (match_dup 0)
7699 (define_expand "movhi"
7700 [(set (match_operand:HI 0 "general_operand" "")
7701 (match_operand:HI 1 "any_operand" ""))]
7703 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7706 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7707 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7708 "gpc_reg_operand (operands[0], HImode)
7709 || gpc_reg_operand (operands[1], HImode)"
7719 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7721 (define_expand "movqi"
7722 [(set (match_operand:QI 0 "general_operand" "")
7723 (match_operand:QI 1 "any_operand" ""))]
7725 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7728 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7729 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7730 "gpc_reg_operand (operands[0], QImode)
7731 || gpc_reg_operand (operands[1], QImode)"
7741 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7743 ;; Here is how to move condition codes around. When we store CC data in
7744 ;; an integer register or memory, we store just the high-order 4 bits.
7745 ;; This lets us not shift in the most common case of CR0.
7746 (define_expand "movcc"
7747 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7748 (match_operand:CC 1 "nonimmediate_operand" ""))]
7752 (define_insn "*movcc_internal1"
7753 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
7754 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
7755 "register_operand (operands[0], CCmode)
7756 || register_operand (operands[1], CCmode)"
7760 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7762 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7764 {l%U1%X1|lwz%U1%X1} %0,%1
7765 {st%U0%U1|stw%U0%U1} %1,%0"
7766 [(set_attr "type" "*,*,*,compare,*,*,load,store")
7767 (set_attr "length" "*,*,12,*,8,*,*,*")])
7769 ;; For floating-point, we normally deal with the floating-point registers
7770 ;; unless -msoft-float is used. The sole exception is that parameter passing
7771 ;; can produce floating-point values in fixed-point registers. Unless the
7772 ;; value is a simple constant or already in memory, we deal with this by
7773 ;; allocating memory and copying the value explicitly via that memory location.
7774 (define_expand "movsf"
7775 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7776 (match_operand:SF 1 "any_operand" ""))]
7778 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7781 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7782 (match_operand:SF 1 "const_double_operand" ""))]
7784 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7785 || (GET_CODE (operands[0]) == SUBREG
7786 && GET_CODE (SUBREG_REG (operands[0])) == REG
7787 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7788 [(set (match_dup 2) (match_dup 3))]
7794 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7795 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7797 if (! TARGET_POWERPC64)
7798 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7800 operands[2] = gen_lowpart (SImode, operands[0]);
7802 operands[3] = gen_int_mode (l, SImode);
7805 (define_insn "*movsf_hardfloat"
7806 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
7807 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
7808 "(gpc_reg_operand (operands[0], SFmode)
7809 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
7812 {l%U1%X1|lwz%U1%X1} %0,%1
7813 {st%U0%X0|stw%U0%X0} %1,%0
7819 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
7820 (set_attr "length" "4,4,4,4,4,4,4,8")])
7822 (define_insn "*movsf_softfloat"
7823 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
7824 (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
7825 "(gpc_reg_operand (operands[0], SFmode)
7826 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
7829 {l%U1%X1|lwz%U1%X1} %0,%1
7830 {st%U0%X0|stw%U0%X0} %1,%0
7836 [(set_attr "type" "*,load,store,*,*,*,*,*")
7837 (set_attr "length" "4,4,4,4,4,4,4,8")])
7840 (define_expand "movdf"
7841 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7842 (match_operand:DF 1 "any_operand" ""))]
7844 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7847 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7848 (match_operand:DF 1 "const_int_operand" ""))]
7849 "! TARGET_POWERPC64 && reload_completed
7850 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7851 || (GET_CODE (operands[0]) == SUBREG
7852 && GET_CODE (SUBREG_REG (operands[0])) == REG
7853 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7854 [(set (match_dup 2) (match_dup 4))
7855 (set (match_dup 3) (match_dup 1))]
7858 int endian = (WORDS_BIG_ENDIAN == 0);
7859 HOST_WIDE_INT value = INTVAL (operands[1]);
7861 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7862 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7863 #if HOST_BITS_PER_WIDE_INT == 32
7864 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7866 operands[4] = GEN_INT (value >> 32);
7867 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7872 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7873 (match_operand:DF 1 "const_double_operand" ""))]
7874 "! TARGET_POWERPC64 && reload_completed
7875 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7876 || (GET_CODE (operands[0]) == SUBREG
7877 && GET_CODE (SUBREG_REG (operands[0])) == REG
7878 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7879 [(set (match_dup 2) (match_dup 4))
7880 (set (match_dup 3) (match_dup 5))]
7883 int endian = (WORDS_BIG_ENDIAN == 0);
7887 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7888 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7890 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7891 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7892 operands[4] = gen_int_mode (l[endian], SImode);
7893 operands[5] = gen_int_mode (l[1 - endian], SImode);
7897 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7898 (match_operand:DF 1 "easy_fp_constant" ""))]
7899 "TARGET_POWERPC64 && reload_completed
7900 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7901 || (GET_CODE (operands[0]) == SUBREG
7902 && GET_CODE (SUBREG_REG (operands[0])) == REG
7903 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7904 [(set (match_dup 2) (match_dup 3))]
7907 int endian = (WORDS_BIG_ENDIAN == 0);
7912 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7913 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7915 operands[2] = gen_lowpart (DImode, operands[0]);
7916 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7917 #if HOST_BITS_PER_WIDE_INT >= 64
7918 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
7919 ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7921 operands[3] = immed_double_const (val, -(val < 0), DImode);
7923 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7927 ;; Don't have reload use general registers to load a constant. First,
7928 ;; it might not work if the output operand is the equivalent of
7929 ;; a non-offsettable memref, but also it is less efficient than loading
7930 ;; the constant into an FP register, since it will probably be used there.
7931 ;; The "??" is a kludge until we can figure out a more reasonable way
7932 ;; of handling these non-offsettable values.
7933 (define_insn "*movdf_hardfloat32"
7934 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
7935 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
7936 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
7937 && (gpc_reg_operand (operands[0], DFmode)
7938 || gpc_reg_operand (operands[1], DFmode))"
7941 switch (which_alternative)
7946 /* We normally copy the low-numbered register first. However, if
7947 the first register operand 0 is the same as the second register
7948 of operand 1, we must copy in the opposite order. */
7949 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7950 return \"mr %L0,%L1\;mr %0,%1\";
7952 return \"mr %0,%1\;mr %L0,%L1\";
7954 if (offsettable_memref_p (operands[1])
7955 || (GET_CODE (operands[1]) == MEM
7956 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7957 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7958 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
7960 /* If the low-address word is used in the address, we must load
7961 it last. Otherwise, load it first. Note that we cannot have
7962 auto-increment in that case since the address register is
7963 known to be dead. */
7964 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7966 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7968 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7974 addreg = find_addr_reg (XEXP (operands[1], 0));
7975 if (refers_to_regno_p (REGNO (operands[0]),
7976 REGNO (operands[0]) + 1,
7979 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7980 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7981 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7982 return \"{lx|lwzx} %0,%1\";
7986 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7987 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7988 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7989 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7994 if (offsettable_memref_p (operands[0])
7995 || (GET_CODE (operands[0]) == MEM
7996 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7997 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7998 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
7999 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8004 addreg = find_addr_reg (XEXP (operands[0], 0));
8005 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8006 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8007 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8008 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8016 return \"fmr %0,%1\";
8018 return \"lfd%U1%X1 %0,%1\";
8020 return \"stfd%U0%X0 %1,%0\";
8023 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
8024 (set_attr "length" "8,16,16,8,12,16,*,*,*")])
8026 (define_insn "*movdf_softfloat32"
8027 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8028 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8029 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
8030 && (gpc_reg_operand (operands[0], DFmode)
8031 || gpc_reg_operand (operands[1], DFmode))"
8034 switch (which_alternative)
8039 /* We normally copy the low-numbered register first. However, if
8040 the first register operand 0 is the same as the second register of
8041 operand 1, we must copy in the opposite order. */
8042 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8043 return \"mr %L0,%L1\;mr %0,%1\";
8045 return \"mr %0,%1\;mr %L0,%L1\";
8047 /* If the low-address word is used in the address, we must load
8048 it last. Otherwise, load it first. Note that we cannot have
8049 auto-increment in that case since the address register is
8050 known to be dead. */
8051 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8053 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8055 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8057 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8064 [(set_attr "type" "*,load,store,*,*,*")
8065 (set_attr "length" "8,8,8,8,12,16")])
8067 (define_insn "*movdf_hardfloat64"
8068 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
8069 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
8070 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
8071 && (gpc_reg_operand (operands[0], DFmode)
8072 || gpc_reg_operand (operands[1], DFmode))"
8083 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
8084 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
8086 (define_insn "*movdf_softfloat64"
8087 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8088 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8089 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
8090 && (gpc_reg_operand (operands[0], DFmode)
8091 || gpc_reg_operand (operands[1], DFmode))"
8099 [(set_attr "type" "*,load,store,*,*,*")
8100 (set_attr "length" "*,*,*,8,12,16")])
8102 (define_expand "movtf"
8103 [(set (match_operand:TF 0 "general_operand" "")
8104 (match_operand:TF 1 "any_operand" ""))]
8105 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8106 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8108 (define_insn "*movtf_internal"
8109 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r")
8110 (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))]
8111 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128
8112 && (gpc_reg_operand (operands[0], TFmode)
8113 || gpc_reg_operand (operands[1], TFmode))"
8116 switch (which_alternative)
8121 /* We normally copy the low-numbered register first. However, if
8122 the first register operand 0 is the same as the second register of
8123 operand 1, we must copy in the opposite order. */
8124 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8125 return \"fmr %L0,%L1\;fmr %0,%1\";
8127 return \"fmr %0,%1\;fmr %L0,%L1\";
8129 return \"lfd %0,%1\;lfd %L0,%L1\";
8131 return \"stfd %1,%0\;stfd %L1,%L0\";
8138 [(set_attr "type" "fp,fpload,fpstore,*,*,*")
8139 (set_attr "length" "8,8,8,12,16,20")])
8142 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8143 (match_operand:TF 1 "const_double_operand" ""))]
8144 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8145 [(set (match_dup 3) (match_dup 1))
8147 (float_extend:TF (match_dup 3)))]
8150 operands[2] = operand_subword (operands[1], 0, 0, DFmode);
8151 operands[3] = gen_reg_rtx (DFmode);
8154 (define_insn_and_split "extenddftf2"
8155 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8156 (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
8157 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8160 [(set (match_dup 2) (match_dup 3))]
8163 operands[2] = gen_rtx_REG (DFmode, REGNO (operands[0] + 1));
8164 operands[3] = CONST0_RTX (DFmode);
8167 (define_insn_and_split "extendsftf2"
8168 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8169 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
8170 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8173 [(set (match_dup 2) (match_dup 3))]
8176 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0] + 1));
8177 operands[3] = CONST0_RTX (SFmode);
8180 (define_insn "trunctfdf2"
8181 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8182 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8183 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8185 [(set_attr "type" "fp")
8186 (set_attr "length" "8")])
8188 (define_insn_and_split "trunctfsf2"
8189 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8190 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8191 (clobber (match_scratch:DF 2 "=f"))]
8192 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8194 "&& reload_completed"
8196 (float_truncate:DF (match_dup 1)))
8198 (float_truncate:SF (match_dup 2)))]
8201 (define_insn_and_split "floatditf2"
8202 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8203 (float:TF (match_operand:DI 1 "gpc_reg_operand" "f")))
8204 (clobber (match_scratch:DF 2 "=f"))]
8205 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
8206 && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8208 "&& reload_completed"
8210 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))
8211 (set (match_operand:TF 0 "gpc_reg_operand" "")
8212 (float_extend:TF (match_dup 2)))]
8215 (define_insn_and_split "floatsitf2"
8216 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8217 (float:TF (match_operand:SI 1 "gpc_reg_operand" "f")))
8218 (clobber (match_scratch:DF 2 "=f"))]
8219 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8221 "&& reload_completed"
8223 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
8224 (set (match_operand:TF 0 "gpc_reg_operand" "")
8225 (float_extend:TF (match_dup 2)))]
8228 (define_insn_and_split "fix_trunctfdi2"
8229 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
8230 (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
8231 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
8232 && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8234 "&& reload_completed"
8236 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
8237 (set (match_operand:DI 0 "gpc_reg_operand" "")
8238 (fix:SI (match_dup 2)))]
8241 (define_insn_and_split "fix_trunctfsi2"
8242 [(set (match_operand:SI 0 "gpc_reg_operand" "=f")
8243 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
8244 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8246 "&& reload_completed"
8248 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
8249 (set (match_operand:SI 0 "gpc_reg_operand" "")
8250 (fix:SI (match_dup 2)))]
8253 (define_insn "negtf2"
8254 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8255 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8256 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8259 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8260 return \"fneg %L0,%L1\;fneg %0,%1\";
8262 return \"fneg %0,%1\;fneg %L0,%L1\";
8264 [(set_attr "type" "fp")
8265 (set_attr "length" "8")])
8267 (define_insn "abstf2"
8268 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8269 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8270 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8273 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8274 return \"fabs %L0,%L1\;fabs %0,%1\";
8276 return \"fabs %0,%1\;fabs %L0,%L1\";
8278 [(set_attr "type" "fp")
8279 (set_attr "length" "8")])
8282 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8283 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
8284 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8287 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8288 return \"fnabs %L0,%L1\;fnabs %0,%1\";
8290 return \"fnabs %0,%1\;fnabs %L0,%L1\";
8292 [(set_attr "type" "fp")
8293 (set_attr "length" "8")])
8295 ;; Next come the multi-word integer load and store and the load and store
8297 (define_expand "movdi"
8298 [(set (match_operand:DI 0 "general_operand" "")
8299 (match_operand:DI 1 "any_operand" ""))]
8301 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8303 (define_insn "*movdi_internal32"
8304 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8305 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8307 && (gpc_reg_operand (operands[0], DImode)
8308 || gpc_reg_operand (operands[1], DImode))"
8311 switch (which_alternative)
8316 /* We normally copy the low-numbered register first. However, if
8317 the first register operand 0 is the same as the second register of
8318 operand 1, we must copy in the opposite order. */
8319 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8320 return \"mr %L0,%L1\;mr %0,%1\";
8322 return \"mr %0,%1\;mr %L0,%L1\";
8324 /* If the low-address word is used in the address, we must load it
8325 last. Otherwise, load it first. Note that we cannot have
8326 auto-increment in that case since the address register is known to be
8328 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8330 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8332 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8334 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8336 return \"fmr %0,%1\";
8338 return \"lfd%U1%X1 %0,%1\";
8340 return \"stfd%U0%X0 %1,%0\";
8349 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
8350 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
8353 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8354 (match_operand:DI 1 "const_int_operand" ""))]
8355 "! TARGET_POWERPC64 && reload_completed"
8356 [(set (match_dup 2) (match_dup 4))
8357 (set (match_dup 3) (match_dup 1))]
8360 HOST_WIDE_INT value = INTVAL (operands[1]);
8361 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8363 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8365 #if HOST_BITS_PER_WIDE_INT == 32
8366 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8368 operands[4] = GEN_INT (value >> 32);
8369 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8374 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8375 (match_operand:DI 1 "const_double_operand" ""))]
8376 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
8377 [(set (match_dup 2) (match_dup 4))
8378 (set (match_dup 3) (match_dup 5))]
8381 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8383 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8385 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8386 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8389 (define_insn "*movdi_internal64"
8390 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
8391 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8393 && (gpc_reg_operand (operands[0], DImode)
8394 || gpc_reg_operand (operands[1], DImode))"
8409 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
8410 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8412 ;; immediate value valid for a single instruction hiding in a const_double
8414 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8415 (match_operand:DI 1 "const_double_operand" "F"))]
8416 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8417 && GET_CODE (operands[1]) == CONST_DOUBLE
8418 && num_insns_constant (operands[1], DImode) == 1"
8421 return ((unsigned HOST_WIDE_INT)
8422 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8423 ? \"li %0,%1\" : \"lis %0,%v1\";
8426 ;; Generate all one-bits and clear left or right.
8427 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8429 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8430 (match_operand:DI 1 "mask64_operand" ""))]
8431 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8432 [(set (match_dup 0) (const_int -1))
8434 (and:DI (rotate:DI (match_dup 0)
8439 ;; Split a load of a large constant into the appropriate five-instruction
8440 ;; sequence. Handle anything in a constant number of insns.
8441 ;; When non-easy constants can go in the TOC, this should use
8442 ;; easy_fp_constant predicate.
8444 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8445 (match_operand:DI 1 "const_int_operand" ""))]
8446 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8447 [(set (match_dup 0) (match_dup 2))
8448 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8450 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8452 if (tem == operands[0])
8459 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8460 (match_operand:DI 1 "const_double_operand" ""))]
8461 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8462 [(set (match_dup 0) (match_dup 2))
8463 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8465 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8467 if (tem == operands[0])
8473 ;; Split a load of a large constant into the appropriate five-instruction
8474 (define_insn "*movdi_internal2"
8475 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8476 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
8478 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8483 [(set_attr "type" "compare")
8484 (set_attr "length" "4,8")])
8487 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8488 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8490 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8491 "TARGET_POWERPC64 && reload_completed"
8492 [(set (match_dup 0) (match_dup 1))
8494 (compare:CC (match_dup 0)
8498 ;; TImode is similar, except that we usually want to compute the address into
8499 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8500 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8501 (define_expand "movti"
8502 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8503 (match_operand:TI 1 "general_operand" ""))
8504 (clobber (scratch:SI))])]
8505 "TARGET_STRING || TARGET_POWERPC64"
8506 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8508 ;; We say that MQ is clobbered in the last alternative because the first
8509 ;; alternative would never get used otherwise since it would need a reload
8510 ;; while the 2nd alternative would not. We put memory cases first so they
8511 ;; are preferred. Otherwise, we'd try to reload the output instead of
8512 ;; giving the SCRATCH mq.
8513 (define_insn "*movti_power"
8514 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8515 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8516 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8517 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8518 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8521 switch (which_alternative)
8527 return \"{stsi|stswi} %1,%P0,16\";
8530 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8533 /* Normally copy registers with lowest numbered register copied first.
8534 But copy in the other order if the first register of the output
8535 is the second, third, or fourth register in the input. */
8536 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8537 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8538 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8540 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8542 /* If the address is not used in the output, we can use lsi. Otherwise,
8543 fall through to generating four loads. */
8544 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8545 return \"{lsi|lswi} %0,%P1,16\";
8546 /* ... fall through ... */
8548 /* If the address register is the same as the register for the lowest-
8549 addressed word, load it last. Similarly for the next two words.
8550 Otherwise load lowest address to highest. */
8551 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8553 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8554 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8555 REGNO (operands[0]) + 2, operands[1], 0))
8556 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8557 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8558 REGNO (operands[0]) + 3, operands[1], 0))
8559 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8561 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8564 [(set_attr "type" "store,store,*,load,load")
8565 (set_attr "length" "*,16,16,*,16")])
8567 (define_insn "*movti_string"
8568 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
8569 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
8570 (clobber (match_scratch:SI 2 "=X,X,X"))]
8571 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8572 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8575 switch (which_alternative)
8581 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8584 /* Normally copy registers with lowest numbered register copied first.
8585 But copy in the other order if the first register of the output
8586 is the second, third, or fourth register in the input. */
8587 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8588 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8589 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8591 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8593 /* If the address register is the same as the register for the lowest-
8594 addressed word, load it last. Similarly for the next two words.
8595 Otherwise load lowest address to highest. */
8596 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8598 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8599 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8600 REGNO (operands[0]) + 2, operands[1], 0))
8601 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8602 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8603 REGNO (operands[0]) + 3, operands[1], 0))
8604 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8606 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8609 [(set_attr "type" "store,*,load")
8610 (set_attr "length" "16,16,16")])
8612 (define_insn "*movti_ppc64"
8613 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
8614 (match_operand:TI 1 "input_operand" "r,m,r"))]
8615 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8616 || gpc_reg_operand (operands[1], TImode))"
8619 switch (which_alternative)
8624 /* We normally copy the low-numbered register first. However, if
8625 the first register operand 0 is the same as the second register of
8626 operand 1, we must copy in the opposite order. */
8627 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8628 return \"mr %L0,%L1\;mr %0,%1\";
8630 return \"mr %0,%1\;mr %L0,%L1\";
8632 /* If the low-address word is used in the address, we must load it
8633 last. Otherwise, load it first. Note that we cannot have
8634 auto-increment in that case since the address register is known to be
8636 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8638 return \"ld %L0,%L1\;ld %0,%1\";
8640 return \"ld%U1 %0,%1\;ld %L0,%L1\";
8642 return \"std%U0 %1,%0\;std %L1,%L0\";
8645 [(set_attr "type" "*,load,store")
8646 (set_attr "length" "8,8,8")])
8648 (define_expand "load_multiple"
8649 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8650 (match_operand:SI 1 "" ""))
8651 (use (match_operand:SI 2 "" ""))])]
8652 "TARGET_STRING && !TARGET_POWERPC64"
8660 /* Support only loading a constant number of fixed-point registers from
8661 memory and only bother with this if more than two; the machine
8662 doesn't support more than eight. */
8663 if (GET_CODE (operands[2]) != CONST_INT
8664 || INTVAL (operands[2]) <= 2
8665 || INTVAL (operands[2]) > 8
8666 || GET_CODE (operands[1]) != MEM
8667 || GET_CODE (operands[0]) != REG
8668 || REGNO (operands[0]) >= 32)
8671 count = INTVAL (operands[2]);
8672 regno = REGNO (operands[0]);
8674 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8675 op1 = replace_equiv_address (operands[1],
8676 force_reg (SImode, XEXP (operands[1], 0)));
8678 for (i = 0; i < count; i++)
8679 XVECEXP (operands[3], 0, i)
8680 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8681 adjust_address (op1, SImode, i * 4));
8685 [(match_parallel 0 "load_multiple_operation"
8686 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8687 (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])]
8691 /* We have to handle the case where the pseudo used to contain the address
8692 is assigned to one of the output registers. */
8694 int words = XVECLEN (operands[0], 0);
8697 if (XVECLEN (operands[0], 0) == 1)
8698 return \"{l|lwz} %1,0(%2)\";
8700 for (i = 0; i < words; i++)
8701 if (refers_to_regno_p (REGNO (operands[1]) + i,
8702 REGNO (operands[1]) + i + 1, operands[2], 0))
8706 xop[0] = operands[1];
8707 xop[1] = operands[2];
8708 xop[2] = GEN_INT (4 * (words-1));
8709 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
8714 xop[0] = operands[1];
8715 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8716 xop[2] = GEN_INT (4 * (words-1));
8717 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
8722 for (j = 0; j < words; j++)
8725 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
8726 xop[1] = operands[2];
8727 xop[2] = GEN_INT (j * 4);
8728 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
8730 xop[0] = operands[2];
8731 xop[1] = GEN_INT (i * 4);
8732 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
8737 return \"{lsi|lswi} %1,%2,%N0\";
8739 [(set_attr "type" "load")
8740 (set_attr "length" "32")])
8743 (define_expand "store_multiple"
8744 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8745 (match_operand:SI 1 "" ""))
8746 (clobber (scratch:SI))
8747 (use (match_operand:SI 2 "" ""))])]
8748 "TARGET_STRING && !TARGET_POWERPC64"
8757 /* Support only storing a constant number of fixed-point registers to
8758 memory and only bother with this if more than two; the machine
8759 doesn't support more than eight. */
8760 if (GET_CODE (operands[2]) != CONST_INT
8761 || INTVAL (operands[2]) <= 2
8762 || INTVAL (operands[2]) > 8
8763 || GET_CODE (operands[0]) != MEM
8764 || GET_CODE (operands[1]) != REG
8765 || REGNO (operands[1]) >= 32)
8768 count = INTVAL (operands[2]);
8769 regno = REGNO (operands[1]);
8771 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8772 to = force_reg (SImode, XEXP (operands[0], 0));
8773 op0 = replace_equiv_address (operands[0], to);
8775 XVECEXP (operands[3], 0, 0)
8776 = gen_rtx_SET (VOIDmode, adjust_address (op0, SImode, 0), operands[1]);
8777 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8778 gen_rtx_SCRATCH (SImode));
8780 for (i = 1; i < count; i++)
8781 XVECEXP (operands[3], 0, i + 1)
8782 = gen_rtx_SET (VOIDmode,
8783 adjust_address (op0, SImode, i * 4),
8784 gen_rtx_REG (SImode, regno + i));
8788 [(match_parallel 0 "store_multiple_operation"
8789 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8790 (match_operand:SI 2 "gpc_reg_operand" "r"))
8791 (clobber (match_scratch:SI 3 "=q"))])]
8792 "TARGET_STRING && TARGET_POWER"
8793 "{stsi|stswi} %2,%P1,%O0"
8794 [(set_attr "type" "store")])
8797 [(match_parallel 0 "store_multiple_operation"
8798 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8799 (match_operand:SI 2 "gpc_reg_operand" "r"))
8800 (clobber (match_scratch:SI 3 "X"))])]
8801 "TARGET_STRING && ! TARGET_POWER"
8802 "{stsi|stswi} %2,%1,%O0"
8803 [(set_attr "type" "store")])
8806 ;; String/block move insn.
8807 ;; Argument 0 is the destination
8808 ;; Argument 1 is the source
8809 ;; Argument 2 is the length
8810 ;; Argument 3 is the alignment
8812 (define_expand "movstrsi"
8813 [(parallel [(set (match_operand:BLK 0 "" "")
8814 (match_operand:BLK 1 "" ""))
8815 (use (match_operand:SI 2 "" ""))
8816 (use (match_operand:SI 3 "" ""))])]
8820 if (expand_block_move (operands))
8826 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8827 ;; register allocator doesn't have a clue about allocating 8 word registers.
8828 ;; rD/rS = r5 is preferred, efficient form.
8829 (define_expand "movstrsi_8reg"
8830 [(parallel [(set (match_operand 0 "" "")
8831 (match_operand 1 "" ""))
8832 (use (match_operand 2 "" ""))
8833 (use (match_operand 3 "" ""))
8834 (clobber (reg:SI 5))
8835 (clobber (reg:SI 6))
8836 (clobber (reg:SI 7))
8837 (clobber (reg:SI 8))
8838 (clobber (reg:SI 9))
8839 (clobber (reg:SI 10))
8840 (clobber (reg:SI 11))
8841 (clobber (reg:SI 12))
8842 (clobber (match_scratch:SI 4 ""))])]
8847 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8848 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8849 (use (match_operand:SI 2 "immediate_operand" "i"))
8850 (use (match_operand:SI 3 "immediate_operand" "i"))
8851 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8852 (clobber (reg:SI 6))
8853 (clobber (reg:SI 7))
8854 (clobber (reg:SI 8))
8855 (clobber (reg:SI 9))
8856 (clobber (reg:SI 10))
8857 (clobber (reg:SI 11))
8858 (clobber (reg:SI 12))
8859 (clobber (match_scratch:SI 5 "=q"))]
8860 "TARGET_STRING && TARGET_POWER
8861 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8862 || INTVAL (operands[2]) == 0)
8863 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8864 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8865 && REGNO (operands[4]) == 5"
8866 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8867 [(set_attr "type" "load")
8868 (set_attr "length" "8")])
8871 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8872 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8873 (use (match_operand:SI 2 "immediate_operand" "i"))
8874 (use (match_operand:SI 3 "immediate_operand" "i"))
8875 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8876 (clobber (reg:SI 6))
8877 (clobber (reg:SI 7))
8878 (clobber (reg:SI 8))
8879 (clobber (reg:SI 9))
8880 (clobber (reg:SI 10))
8881 (clobber (reg:SI 11))
8882 (clobber (reg:SI 12))
8883 (clobber (match_scratch:SI 5 "X"))]
8884 "TARGET_STRING && ! TARGET_POWER
8885 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8886 || INTVAL (operands[2]) == 0)
8887 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8888 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8889 && REGNO (operands[4]) == 5"
8890 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8891 [(set_attr "type" "load")
8892 (set_attr "length" "8")])
8895 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8896 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8897 (use (match_operand:SI 2 "immediate_operand" "i"))
8898 (use (match_operand:SI 3 "immediate_operand" "i"))
8899 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8900 (clobber (reg:SI 6))
8901 (clobber (reg:SI 7))
8902 (clobber (reg:SI 8))
8903 (clobber (reg:SI 9))
8904 (clobber (reg:SI 10))
8905 (clobber (reg:SI 11))
8906 (clobber (reg:SI 12))
8907 (clobber (match_scratch:SI 5 "X"))]
8908 "TARGET_STRING && TARGET_POWERPC64
8909 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8910 || INTVAL (operands[2]) == 0)
8911 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8912 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8913 && REGNO (operands[4]) == 5"
8914 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8915 [(set_attr "type" "load")
8916 (set_attr "length" "8")])
8918 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8919 ;; register allocator doesn't have a clue about allocating 6 word registers.
8920 ;; rD/rS = r5 is preferred, efficient form.
8921 (define_expand "movstrsi_6reg"
8922 [(parallel [(set (match_operand 0 "" "")
8923 (match_operand 1 "" ""))
8924 (use (match_operand 2 "" ""))
8925 (use (match_operand 3 "" ""))
8926 (clobber (reg:SI 5))
8927 (clobber (reg:SI 6))
8928 (clobber (reg:SI 7))
8929 (clobber (reg:SI 8))
8930 (clobber (reg:SI 9))
8931 (clobber (reg:SI 10))
8932 (clobber (match_scratch:SI 4 ""))])]
8937 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8938 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8939 (use (match_operand:SI 2 "immediate_operand" "i"))
8940 (use (match_operand:SI 3 "immediate_operand" "i"))
8941 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8942 (clobber (reg:SI 6))
8943 (clobber (reg:SI 7))
8944 (clobber (reg:SI 8))
8945 (clobber (reg:SI 9))
8946 (clobber (reg:SI 10))
8947 (clobber (match_scratch:SI 5 "=q"))]
8948 "TARGET_STRING && TARGET_POWER
8949 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8950 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8951 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8952 && REGNO (operands[4]) == 5"
8953 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8954 [(set_attr "type" "load")
8955 (set_attr "length" "8")])
8958 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8959 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8960 (use (match_operand:SI 2 "immediate_operand" "i"))
8961 (use (match_operand:SI 3 "immediate_operand" "i"))
8962 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8963 (clobber (reg:SI 6))
8964 (clobber (reg:SI 7))
8965 (clobber (reg:SI 8))
8966 (clobber (reg:SI 9))
8967 (clobber (reg:SI 10))
8968 (clobber (match_scratch:SI 5 "X"))]
8969 "TARGET_STRING && ! TARGET_POWER
8970 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8971 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8972 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8973 && REGNO (operands[4]) == 5"
8974 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8975 [(set_attr "type" "load")
8976 (set_attr "length" "8")])
8979 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8980 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8981 (use (match_operand:SI 2 "immediate_operand" "i"))
8982 (use (match_operand:SI 3 "immediate_operand" "i"))
8983 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8984 (clobber (reg:SI 6))
8985 (clobber (reg:SI 7))
8986 (clobber (reg:SI 8))
8987 (clobber (reg:SI 9))
8988 (clobber (reg:SI 10))
8989 (clobber (match_scratch:SI 5 "X"))]
8990 "TARGET_STRING && TARGET_POWERPC64
8991 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8992 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8993 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8994 && REGNO (operands[4]) == 5"
8995 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8996 [(set_attr "type" "load")
8997 (set_attr "length" "8")])
8999 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9000 ;; problems with TImode.
9001 ;; rD/rS = r5 is preferred, efficient form.
9002 (define_expand "movstrsi_4reg"
9003 [(parallel [(set (match_operand 0 "" "")
9004 (match_operand 1 "" ""))
9005 (use (match_operand 2 "" ""))
9006 (use (match_operand 3 "" ""))
9007 (clobber (reg:SI 5))
9008 (clobber (reg:SI 6))
9009 (clobber (reg:SI 7))
9010 (clobber (reg:SI 8))
9011 (clobber (match_scratch:SI 4 ""))])]
9016 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9017 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9018 (use (match_operand:SI 2 "immediate_operand" "i"))
9019 (use (match_operand:SI 3 "immediate_operand" "i"))
9020 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9021 (clobber (reg:SI 6))
9022 (clobber (reg:SI 7))
9023 (clobber (reg:SI 8))
9024 (clobber (match_scratch:SI 5 "=q"))]
9025 "TARGET_STRING && TARGET_POWER
9026 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9027 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9028 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9029 && REGNO (operands[4]) == 5"
9030 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9031 [(set_attr "type" "load")
9032 (set_attr "length" "8")])
9035 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9036 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9037 (use (match_operand:SI 2 "immediate_operand" "i"))
9038 (use (match_operand:SI 3 "immediate_operand" "i"))
9039 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9040 (clobber (reg:SI 6))
9041 (clobber (reg:SI 7))
9042 (clobber (reg:SI 8))
9043 (clobber (match_scratch:SI 5 "X"))]
9044 "TARGET_STRING && ! TARGET_POWER
9045 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9046 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9047 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9048 && REGNO (operands[4]) == 5"
9049 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9050 [(set_attr "type" "load")
9051 (set_attr "length" "8")])
9054 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9055 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9056 (use (match_operand:SI 2 "immediate_operand" "i"))
9057 (use (match_operand:SI 3 "immediate_operand" "i"))
9058 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9059 (clobber (reg:SI 6))
9060 (clobber (reg:SI 7))
9061 (clobber (reg:SI 8))
9062 (clobber (match_scratch:SI 5 "X"))]
9063 "TARGET_STRING && TARGET_POWERPC64
9064 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9065 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9066 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9067 && REGNO (operands[4]) == 5"
9068 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9069 [(set_attr "type" "load")
9070 (set_attr "length" "8")])
9072 ;; Move up to 8 bytes at a time.
9073 (define_expand "movstrsi_2reg"
9074 [(parallel [(set (match_operand 0 "" "")
9075 (match_operand 1 "" ""))
9076 (use (match_operand 2 "" ""))
9077 (use (match_operand 3 "" ""))
9078 (clobber (match_scratch:DI 4 ""))
9079 (clobber (match_scratch:SI 5 ""))])]
9080 "TARGET_STRING && ! TARGET_POWERPC64"
9084 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9085 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9086 (use (match_operand:SI 2 "immediate_operand" "i"))
9087 (use (match_operand:SI 3 "immediate_operand" "i"))
9088 (clobber (match_scratch:DI 4 "=&r"))
9089 (clobber (match_scratch:SI 5 "=q"))]
9090 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9091 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9092 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9093 [(set_attr "type" "load")
9094 (set_attr "length" "8")])
9097 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9098 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9099 (use (match_operand:SI 2 "immediate_operand" "i"))
9100 (use (match_operand:SI 3 "immediate_operand" "i"))
9101 (clobber (match_scratch:DI 4 "=&r"))
9102 (clobber (match_scratch:SI 5 "X"))]
9103 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9104 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9105 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9106 [(set_attr "type" "load")
9107 (set_attr "length" "8")])
9109 ;; Move up to 4 bytes at a time.
9110 (define_expand "movstrsi_1reg"
9111 [(parallel [(set (match_operand 0 "" "")
9112 (match_operand 1 "" ""))
9113 (use (match_operand 2 "" ""))
9114 (use (match_operand 3 "" ""))
9115 (clobber (match_scratch:SI 4 ""))
9116 (clobber (match_scratch:SI 5 ""))])]
9121 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9122 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9123 (use (match_operand:SI 2 "immediate_operand" "i"))
9124 (use (match_operand:SI 3 "immediate_operand" "i"))
9125 (clobber (match_scratch:SI 4 "=&r"))
9126 (clobber (match_scratch:SI 5 "=q"))]
9127 "TARGET_STRING && TARGET_POWER
9128 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9129 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9130 [(set_attr "type" "load")
9131 (set_attr "length" "8")])
9134 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9135 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9136 (use (match_operand:SI 2 "immediate_operand" "i"))
9137 (use (match_operand:SI 3 "immediate_operand" "i"))
9138 (clobber (match_scratch:SI 4 "=&r"))
9139 (clobber (match_scratch:SI 5 "X"))]
9140 "TARGET_STRING && ! TARGET_POWER
9141 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9142 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9143 [(set_attr "type" "load")
9144 (set_attr "length" "8")])
9147 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9148 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9149 (use (match_operand:SI 2 "immediate_operand" "i"))
9150 (use (match_operand:SI 3 "immediate_operand" "i"))
9151 (clobber (match_scratch:SI 4 "=&r"))
9152 (clobber (match_scratch:SI 5 "X"))]
9153 "TARGET_STRING && TARGET_POWERPC64
9154 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9155 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9156 [(set_attr "type" "load")
9157 (set_attr "length" "8")])
9160 ;; Define insns that do load or store with update. Some of these we can
9161 ;; get by using pre-decrement or pre-increment, but the hardware can also
9162 ;; do cases where the increment is not the size of the object.
9164 ;; In all these cases, we use operands 0 and 1 for the register being
9165 ;; incremented because those are the operands that local-alloc will
9166 ;; tie and these are the pair most likely to be tieable (and the ones
9167 ;; that will benefit the most).
9169 (define_insn "*movdi_update1"
9170 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9171 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9172 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9173 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9174 (plus:DI (match_dup 1) (match_dup 2)))]
9175 "TARGET_POWERPC64 && TARGET_UPDATE"
9179 [(set_attr "type" "load")])
9181 (define_insn "*movdi_update2"
9182 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9184 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9185 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9186 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9187 (plus:DI (match_dup 1) (match_dup 2)))]
9190 [(set_attr "type" "load")])
9192 (define_insn "movdi_update"
9193 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9194 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9195 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9196 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9197 (plus:DI (match_dup 1) (match_dup 2)))]
9198 "TARGET_POWERPC64 && TARGET_UPDATE"
9202 [(set_attr "type" "store")])
9204 (define_insn "*movsi_update1"
9205 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9206 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9207 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9208 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9209 (plus:SI (match_dup 1) (match_dup 2)))]
9212 {lux|lwzux} %3,%0,%2
9213 {lu|lwzu} %3,%2(%0)"
9214 [(set_attr "type" "load")])
9216 (define_insn "movsi_update"
9217 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9218 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9219 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9220 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9221 (plus:SI (match_dup 1) (match_dup 2)))]
9224 {stux|stwux} %3,%0,%2
9225 {stu|stwu} %3,%2(%0)"
9226 [(set_attr "type" "store")])
9228 (define_insn "*movhi_update"
9229 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9230 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9231 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9232 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9233 (plus:SI (match_dup 1) (match_dup 2)))]
9238 [(set_attr "type" "load")])
9240 (define_insn "*movhi_update2"
9241 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9243 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9244 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9245 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9246 (plus:SI (match_dup 1) (match_dup 2)))]
9251 [(set_attr "type" "load")])
9253 (define_insn "*movhi_update3"
9254 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9256 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9257 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9258 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9259 (plus:SI (match_dup 1) (match_dup 2)))]
9264 [(set_attr "type" "load")])
9266 (define_insn "*movhi_update4"
9267 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9268 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9269 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9270 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9271 (plus:SI (match_dup 1) (match_dup 2)))]
9276 [(set_attr "type" "store")])
9278 (define_insn "*movqi_update1"
9279 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9280 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9281 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9282 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9283 (plus:SI (match_dup 1) (match_dup 2)))]
9288 [(set_attr "type" "load")])
9290 (define_insn "*movqi_update2"
9291 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9293 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9294 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9295 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9296 (plus:SI (match_dup 1) (match_dup 2)))]
9301 [(set_attr "type" "load")])
9303 (define_insn "*movqi_update3"
9304 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9305 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9306 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9307 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9308 (plus:SI (match_dup 1) (match_dup 2)))]
9313 [(set_attr "type" "store")])
9315 (define_insn "*movsf_update1"
9316 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9317 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9318 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9319 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9320 (plus:SI (match_dup 1) (match_dup 2)))]
9321 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9325 [(set_attr "type" "fpload")])
9327 (define_insn "*movsf_update2"
9328 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9329 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9330 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9331 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9332 (plus:SI (match_dup 1) (match_dup 2)))]
9333 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9337 [(set_attr "type" "fpstore")])
9339 (define_insn "*movsf_update3"
9340 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9341 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9342 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9343 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9344 (plus:SI (match_dup 1) (match_dup 2)))]
9345 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
9347 {lux|lwzux} %3,%0,%2
9348 {lu|lwzu} %3,%2(%0)"
9349 [(set_attr "type" "load")])
9351 (define_insn "*movsf_update4"
9352 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9353 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9354 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9355 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9356 (plus:SI (match_dup 1) (match_dup 2)))]
9357 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
9359 {stux|stwux} %3,%0,%2
9360 {stu|stwu} %3,%2(%0)"
9361 [(set_attr "type" "store")])
9363 (define_insn "*movdf_update1"
9364 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9365 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9366 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9367 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9368 (plus:SI (match_dup 1) (match_dup 2)))]
9369 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9373 [(set_attr "type" "fpload")])
9375 (define_insn "*movdf_update2"
9376 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9377 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9378 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9379 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9380 (plus:SI (match_dup 1) (match_dup 2)))]
9381 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9385 [(set_attr "type" "fpstore")])
9387 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9390 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9391 (match_operand:DF 1 "memory_operand" ""))
9392 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9393 (match_operand:DF 3 "memory_operand" ""))]
9395 && TARGET_HARD_FLOAT
9396 && registers_ok_for_quad_peep (operands[0], operands[2])
9397 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9398 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9402 [(set (match_operand:DF 0 "memory_operand" "")
9403 (match_operand:DF 1 "gpc_reg_operand" "f"))
9404 (set (match_operand:DF 2 "memory_operand" "")
9405 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9407 && TARGET_HARD_FLOAT
9408 && registers_ok_for_quad_peep (operands[1], operands[3])
9409 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9410 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9413 ;; Next come insns related to the calling sequence.
9415 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9416 ;; We move the back-chain and decrement the stack pointer.
9418 (define_expand "allocate_stack"
9419 [(set (match_operand 0 "gpc_reg_operand" "=r")
9420 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9422 (minus (reg 1) (match_dup 1)))]
9425 { rtx chain = gen_reg_rtx (Pmode);
9426 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9429 emit_move_insn (chain, stack_bot);
9431 /* Check stack bounds if necessary. */
9432 if (current_function_limit_stack)
9435 available = expand_binop (Pmode, sub_optab,
9436 stack_pointer_rtx, stack_limit_rtx,
9437 NULL_RTX, 1, OPTAB_WIDEN);
9438 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9441 if (GET_CODE (operands[1]) != CONST_INT
9442 || INTVAL (operands[1]) < -32767
9443 || INTVAL (operands[1]) > 32768)
9445 neg_op0 = gen_reg_rtx (Pmode);
9447 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9449 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9452 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9455 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9456 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9460 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9461 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9462 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9465 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9469 ;; These patterns say how to save and restore the stack pointer. We need not
9470 ;; save the stack pointer at function level since we are careful to
9471 ;; preserve the backchain. At block level, we have to restore the backchain
9472 ;; when we restore the stack pointer.
9474 ;; For nonlocal gotos, we must save both the stack pointer and its
9475 ;; backchain and restore both. Note that in the nonlocal case, the
9476 ;; save area is a memory location.
9478 (define_expand "save_stack_function"
9479 [(match_operand 0 "any_operand" "")
9480 (match_operand 1 "any_operand" "")]
9484 (define_expand "restore_stack_function"
9485 [(match_operand 0 "any_operand" "")
9486 (match_operand 1 "any_operand" "")]
9490 (define_expand "restore_stack_block"
9491 [(use (match_operand 0 "register_operand" ""))
9492 (set (match_dup 2) (match_dup 3))
9493 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9494 (set (match_dup 3) (match_dup 2))]
9498 operands[2] = gen_reg_rtx (Pmode);
9499 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9502 (define_expand "save_stack_nonlocal"
9503 [(match_operand 0 "memory_operand" "")
9504 (match_operand 1 "register_operand" "")]
9508 rtx temp = gen_reg_rtx (Pmode);
9510 /* Copy the backchain to the first word, sp to the second. */
9511 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9512 emit_move_insn (operand_subword (operands[0], 0, 0,
9513 (TARGET_32BIT ? DImode : TImode)),
9515 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
9520 (define_expand "restore_stack_nonlocal"
9521 [(match_operand 0 "register_operand" "")
9522 (match_operand 1 "memory_operand" "")]
9526 rtx temp = gen_reg_rtx (Pmode);
9528 /* Restore the backchain from the first word, sp from the second. */
9529 emit_move_insn (temp,
9530 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
9531 emit_move_insn (operands[0],
9532 operand_subword (operands[1], 1, 0,
9533 (TARGET_32BIT ? DImode : TImode)));
9534 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9538 ;; TOC register handling.
9540 ;; Code to initialize the TOC register...
9542 (define_insn "load_toc_aix_si"
9543 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9544 (unspec:SI [(const_int 0)] 7))
9546 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9550 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9551 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9552 operands[2] = gen_rtx_REG (Pmode, 2);
9553 return \"{l|lwz} %0,%1(%2)\";
9555 [(set_attr "type" "load")])
9557 (define_insn "load_toc_aix_di"
9558 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9559 (unspec:DI [(const_int 0)] 7))
9561 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9565 #ifdef TARGET_RELOCATABLE
9566 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9567 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9569 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9572 strcat (buf, \"@toc\");
9573 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9574 operands[2] = gen_rtx_REG (Pmode, 2);
9575 return \"ld %0,%1(%2)\";
9577 [(set_attr "type" "load")])
9579 (define_insn "load_toc_v4_pic_si"
9580 [(set (match_operand:SI 0 "register_operand" "=l")
9581 (unspec:SI [(const_int 0)] 7))]
9582 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9583 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9584 [(set_attr "type" "branch")
9585 (set_attr "length" "4")])
9587 (define_insn "load_toc_v4_PIC_1"
9588 [(set (match_operand:SI 0 "register_operand" "=l")
9589 (match_operand:SI 1 "immediate_operand" "s"))
9590 (unspec [(match_dup 1)] 7)]
9591 "TARGET_ELF && flag_pic == 2"
9593 [(set_attr "type" "branch")
9594 (set_attr "length" "4")])
9596 (define_insn "load_toc_v4_PIC_1b"
9597 [(set (match_operand:SI 0 "register_operand" "=l")
9598 (match_operand:SI 1 "immediate_operand" "s"))
9599 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
9600 "TARGET_ELF && flag_pic == 2"
9601 "bl %1\\n\\t.long %2-%1+4\\n%1:"
9602 [(set_attr "type" "branch")
9603 (set_attr "length" "8")])
9605 (define_insn "load_toc_v4_PIC_2"
9606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9607 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9608 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9609 (match_operand:SI 3 "immediate_operand" "s")))))]
9610 "TARGET_ELF && flag_pic == 2"
9611 "{l|lwz} %0,%2-%3(%1)"
9612 [(set_attr "type" "load")])
9614 (define_insn "load_macho_picbase"
9615 [(set (match_operand:SI 0 "register_operand" "=l")
9616 (unspec:SI [(const_int 0)] 15))]
9617 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
9621 char *picbase = machopic_function_base_name ();
9622 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
9624 return \"bcl 20,31,%1\\n%1:\";
9626 [(set_attr "type" "branch")
9627 (set_attr "length" "4")])
9629 ;; If the TOC is shared over a translation unit, as happens with all
9630 ;; the kinds of PIC that we support, we need to restore the TOC
9631 ;; pointer only when jumping over units of translation.
9633 (define_expand "builtin_setjmp_receiver"
9634 [(use (label_ref (match_operand 0 "" "")))]
9635 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9636 || (TARGET_TOC && TARGET_MINIMAL_TOC)"
9639 rs6000_emit_load_toc_table (FALSE);
9643 ;; A function pointer under AIX is a pointer to a data area whose first word
9644 ;; contains the actual address of the function, whose second word contains a
9645 ;; pointer to its TOC, and whose third word contains a value to place in the
9646 ;; static chain register (r11). Note that if we load the static chain, our
9647 ;; "trampoline" need not have any executable code.
9649 (define_expand "call_indirect_aix32"
9651 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9652 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9655 (mem:SI (plus:SI (match_dup 0)
9658 (mem:SI (plus:SI (match_dup 0)
9660 (parallel [(call (mem:SI (match_dup 2))
9661 (match_operand 1 "" ""))
9665 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9666 (clobber (scratch:SI))])]
9669 { operands[2] = gen_reg_rtx (SImode); }")
9671 (define_expand "call_indirect_aix64"
9673 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9674 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9677 (mem:DI (plus:DI (match_dup 0)
9680 (mem:DI (plus:DI (match_dup 0)
9682 (parallel [(call (mem:SI (match_dup 2))
9683 (match_operand 1 "" ""))
9687 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9688 (clobber (scratch:SI))])]
9691 { operands[2] = gen_reg_rtx (DImode); }")
9693 (define_expand "call_value_indirect_aix32"
9695 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9696 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9699 (mem:SI (plus:SI (match_dup 1)
9702 (mem:SI (plus:SI (match_dup 1)
9704 (parallel [(set (match_operand 0 "" "")
9705 (call (mem:SI (match_dup 3))
9706 (match_operand 2 "" "")))
9710 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9711 (clobber (scratch:SI))])]
9714 { operands[3] = gen_reg_rtx (SImode); }")
9716 (define_expand "call_value_indirect_aix64"
9718 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9719 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9722 (mem:DI (plus:DI (match_dup 1)
9725 (mem:DI (plus:DI (match_dup 1)
9727 (parallel [(set (match_operand 0 "" "")
9728 (call (mem:SI (match_dup 3))
9729 (match_operand 2 "" "")))
9733 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9734 (clobber (scratch:SI))])]
9737 { operands[3] = gen_reg_rtx (DImode); }")
9739 ;; Now the definitions for the call and call_value insns
9740 (define_expand "call"
9741 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9742 (match_operand 1 "" ""))
9743 (use (match_operand 2 "" ""))
9744 (clobber (scratch:SI))])]
9750 operands[0] = machopic_indirect_call_target (operands[0]);
9753 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
9756 operands[0] = XEXP (operands[0], 0);
9758 if (GET_CODE (operands[0]) != SYMBOL_REF
9759 || (INTVAL (operands[2]) & CALL_LONG) != 0)
9761 if (INTVAL (operands[2]) & CALL_LONG)
9762 operands[0] = rs6000_longcall_ref (operands[0]);
9764 if (DEFAULT_ABI == ABI_V4
9765 || DEFAULT_ABI == ABI_AIX_NODESC
9766 || DEFAULT_ABI == ABI_DARWIN)
9767 operands[0] = force_reg (Pmode, operands[0]);
9769 else if (DEFAULT_ABI == ABI_AIX)
9771 /* AIX function pointers are really pointers to a three word
9773 emit_call_insn (TARGET_32BIT
9774 ? gen_call_indirect_aix32 (force_reg (SImode,
9777 : gen_call_indirect_aix64 (force_reg (DImode,
9787 (define_expand "call_value"
9788 [(parallel [(set (match_operand 0 "" "")
9789 (call (mem:SI (match_operand 1 "address_operand" ""))
9790 (match_operand 2 "" "")))
9791 (use (match_operand 3 "" ""))
9792 (clobber (scratch:SI))])]
9798 operands[1] = machopic_indirect_call_target (operands[1]);
9801 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
9804 operands[1] = XEXP (operands[1], 0);
9806 if (GET_CODE (operands[1]) != SYMBOL_REF
9807 || (INTVAL (operands[3]) & CALL_LONG) != 0)
9809 if (INTVAL (operands[3]) & CALL_LONG)
9810 operands[1] = rs6000_longcall_ref (operands[1]);
9812 if (DEFAULT_ABI == ABI_V4
9813 || DEFAULT_ABI == ABI_AIX_NODESC
9814 || DEFAULT_ABI == ABI_DARWIN)
9815 operands[0] = force_reg (Pmode, operands[0]);
9817 else if (DEFAULT_ABI == ABI_AIX)
9819 /* AIX function pointers are really pointers to a three word
9821 emit_call_insn (TARGET_32BIT
9822 ? gen_call_value_indirect_aix32 (operands[0],
9826 : gen_call_value_indirect_aix64 (operands[0],
9837 ;; Call to function in current module. No TOC pointer reload needed.
9838 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9839 ;; either the function was not prototyped, or it was prototyped as a
9840 ;; variable argument function. It is > 0 if FP registers were passed
9841 ;; and < 0 if they were not.
9843 (define_insn "*call_local32"
9844 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9845 (match_operand 1 "" "g,g"))
9846 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9847 (clobber (match_scratch:SI 3 "=l,l"))]
9848 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9851 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9852 output_asm_insn (\"crxor 6,6,6\", operands);
9854 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9855 output_asm_insn (\"creqv 6,6,6\", operands);
9857 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9859 [(set_attr "type" "branch")
9860 (set_attr "length" "4,8")])
9862 (define_insn "*call_local64"
9863 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9864 (match_operand 1 "" "g,g"))
9865 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9866 (clobber (match_scratch:SI 3 "=l,l"))]
9867 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9870 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9871 output_asm_insn (\"crxor 6,6,6\", operands);
9873 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9874 output_asm_insn (\"creqv 6,6,6\", operands);
9876 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9878 [(set_attr "type" "branch")
9879 (set_attr "length" "4,8")])
9881 (define_insn "*call_value_local32"
9882 [(set (match_operand 0 "" "")
9883 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9884 (match_operand 2 "" "g,g")))
9885 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9886 (clobber (match_scratch:SI 4 "=l,l"))]
9887 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9890 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9891 output_asm_insn (\"crxor 6,6,6\", operands);
9893 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9894 output_asm_insn (\"creqv 6,6,6\", operands);
9896 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9898 [(set_attr "type" "branch")
9899 (set_attr "length" "4,8")])
9902 (define_insn "*call_value_local64"
9903 [(set (match_operand 0 "" "")
9904 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9905 (match_operand 2 "" "g,g")))
9906 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9907 (clobber (match_scratch:SI 4 "=l,l"))]
9908 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9911 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9912 output_asm_insn (\"crxor 6,6,6\", operands);
9914 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9915 output_asm_insn (\"creqv 6,6,6\", operands);
9917 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9919 [(set_attr "type" "branch")
9920 (set_attr "length" "4,8")])
9922 ;; Call to function which may be in another module. Restore the TOC
9923 ;; pointer (r2) after the call unless this is System V.
9924 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9925 ;; either the function was not prototyped, or it was prototyped as a
9926 ;; variable argument function. It is > 0 if FP registers were passed
9927 ;; and < 0 if they were not.
9929 (define_insn "*call_indirect_nonlocal_aix32"
9930 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
9931 (match_operand 1 "" "g"))
9935 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9936 (clobber (match_scratch:SI 2 "=l"))]
9937 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9938 "b%T0l\;{l|lwz} 2,20(1)"
9939 [(set_attr "type" "jmpreg")
9940 (set_attr "length" "8")])
9942 (define_insn "*call_nonlocal_aix32"
9943 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
9944 (match_operand 1 "" "g"))
9945 (use (match_operand:SI 2 "immediate_operand" "O"))
9946 (clobber (match_scratch:SI 3 "=l"))]
9948 && DEFAULT_ABI == ABI_AIX
9949 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9951 [(set_attr "type" "branch")
9952 (set_attr "length" "8")])
9954 (define_insn "*call_indirect_nonlocal_aix64"
9955 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
9956 (match_operand 1 "" "g"))
9960 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9961 (clobber (match_scratch:SI 2 "=l"))]
9962 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9964 [(set_attr "type" "jmpreg")
9965 (set_attr "length" "8")])
9967 (define_insn "*call_nonlocal_aix64"
9968 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
9969 (match_operand 1 "" "g"))
9970 (use (match_operand:SI 2 "immediate_operand" "O"))
9971 (clobber (match_scratch:SI 3 "=l"))]
9973 && DEFAULT_ABI == ABI_AIX
9974 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9976 [(set_attr "type" "branch")
9977 (set_attr "length" "8")])
9979 (define_insn "*call_value_indirect_nonlocal_aix32"
9980 [(set (match_operand 0 "" "")
9981 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
9982 (match_operand 2 "" "g")))
9986 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9987 (clobber (match_scratch:SI 3 "=l"))]
9988 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9989 "b%T1l\;{l|lwz} 2,20(1)"
9990 [(set_attr "type" "jmpreg")
9991 (set_attr "length" "8")])
9993 (define_insn "*call_value_nonlocal_aix32"
9994 [(set (match_operand 0 "" "")
9995 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
9996 (match_operand 2 "" "g")))
9997 (use (match_operand:SI 3 "immediate_operand" "O"))
9998 (clobber (match_scratch:SI 4 "=l"))]
10000 && DEFAULT_ABI == ABI_AIX
10001 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10003 [(set_attr "type" "branch")
10004 (set_attr "length" "8")])
10006 (define_insn "*call_value_indirect_nonlocal_aix64"
10007 [(set (match_operand 0 "" "")
10008 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10009 (match_operand 2 "" "g")))
10013 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10014 (clobber (match_scratch:SI 3 "=l"))]
10015 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10016 "b%T1l\;ld 2,40(1)"
10017 [(set_attr "type" "jmpreg")
10018 (set_attr "length" "8")])
10020 (define_insn "*call_value_nonlocal_aix64"
10021 [(set (match_operand 0 "" "")
10022 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10023 (match_operand 2 "" "g")))
10024 (use (match_operand:SI 3 "immediate_operand" "O"))
10025 (clobber (match_scratch:SI 4 "=l"))]
10027 && DEFAULT_ABI == ABI_AIX
10028 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10030 [(set_attr "type" "branch")
10031 (set_attr "length" "8")])
10033 ;; A function pointer under System V is just a normal pointer
10034 ;; operands[0] is the function pointer
10035 ;; operands[1] is the stack size to clean up
10036 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10037 ;; which indicates how to set cr1
10039 (define_insn "*call_nonlocal_sysv"
10040 [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s"))
10041 (match_operand 1 "" "g,g,g,g"))
10042 (use (match_operand:SI 2 "immediate_operand" "O,n,O,n"))
10043 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10044 "DEFAULT_ABI == ABI_AIX_NODESC
10045 || DEFAULT_ABI == ABI_V4
10046 || DEFAULT_ABI == ABI_DARWIN"
10049 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10050 output_asm_insn (\"crxor 6,6,6\", operands);
10052 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10053 output_asm_insn (\"creqv 6,6,6\", operands);
10055 switch (which_alternative)
10064 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
10067 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
10068 (set_attr "length" "4,8,4,8")])
10070 (define_insn "*call_value_nonlocal_sysv"
10071 [(set (match_operand 0 "" "")
10072 (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s"))
10073 (match_operand 2 "" "g,g,g,g")))
10074 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
10075 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10076 "DEFAULT_ABI == ABI_AIX_NODESC
10077 || DEFAULT_ABI == ABI_V4
10078 || DEFAULT_ABI == ABI_DARWIN"
10081 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10082 output_asm_insn (\"crxor 6,6,6\", operands);
10084 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10085 output_asm_insn (\"creqv 6,6,6\", operands);
10087 switch (which_alternative)
10096 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
10099 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
10100 (set_attr "length" "4,8,4,8")])
10102 ;; Call subroutine returning any type.
10103 (define_expand "untyped_call"
10104 [(parallel [(call (match_operand 0 "" "")
10106 (match_operand 1 "" "")
10107 (match_operand 2 "" "")])]
10113 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10115 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10117 rtx set = XVECEXP (operands[2], 0, i);
10118 emit_move_insn (SET_DEST (set), SET_SRC (set));
10121 /* The optimizer does not know that the call sets the function value
10122 registers we stored in the result block. We avoid problems by
10123 claiming that all hard registers are used and clobbered at this
10125 emit_insn (gen_blockage ());
10130 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10131 ;; all of memory. This blocks insns from being moved across this point.
10133 (define_insn "blockage"
10134 [(unspec_volatile [(const_int 0)] 0)]
10138 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10139 ;; signed & unsigned, and one type of branch.
10141 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10142 ;; insns, and branches. We store the operands of compares until we see
10144 (define_expand "cmpsi"
10146 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10147 (match_operand:SI 1 "reg_or_short_operand" "")))]
10151 /* Take care of the possibility that operands[1] might be negative but
10152 this might be a logical operation. That insn doesn't exist. */
10153 if (GET_CODE (operands[1]) == CONST_INT
10154 && INTVAL (operands[1]) < 0)
10155 operands[1] = force_reg (SImode, operands[1]);
10157 rs6000_compare_op0 = operands[0];
10158 rs6000_compare_op1 = operands[1];
10159 rs6000_compare_fp_p = 0;
10163 (define_expand "cmpdi"
10165 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10166 (match_operand:DI 1 "reg_or_short_operand" "")))]
10170 /* Take care of the possibility that operands[1] might be negative but
10171 this might be a logical operation. That insn doesn't exist. */
10172 if (GET_CODE (operands[1]) == CONST_INT
10173 && INTVAL (operands[1]) < 0)
10174 operands[1] = force_reg (DImode, operands[1]);
10176 rs6000_compare_op0 = operands[0];
10177 rs6000_compare_op1 = operands[1];
10178 rs6000_compare_fp_p = 0;
10182 (define_expand "cmpsf"
10183 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10184 (match_operand:SF 1 "gpc_reg_operand" "")))]
10185 "TARGET_HARD_FLOAT"
10188 rs6000_compare_op0 = operands[0];
10189 rs6000_compare_op1 = operands[1];
10190 rs6000_compare_fp_p = 1;
10194 (define_expand "cmpdf"
10195 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10196 (match_operand:DF 1 "gpc_reg_operand" "")))]
10197 "TARGET_HARD_FLOAT"
10200 rs6000_compare_op0 = operands[0];
10201 rs6000_compare_op1 = operands[1];
10202 rs6000_compare_fp_p = 1;
10206 (define_expand "cmptf"
10207 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10208 (match_operand:TF 1 "gpc_reg_operand" "")))]
10209 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
10212 rs6000_compare_op0 = operands[0];
10213 rs6000_compare_op1 = operands[1];
10214 rs6000_compare_fp_p = 1;
10218 (define_expand "beq"
10219 [(use (match_operand 0 "" ""))]
10221 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10223 (define_expand "bne"
10224 [(use (match_operand 0 "" ""))]
10226 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10228 (define_expand "bge"
10229 [(use (match_operand 0 "" ""))]
10231 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10233 (define_expand "bgt"
10234 [(use (match_operand 0 "" ""))]
10236 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10238 (define_expand "ble"
10239 [(use (match_operand 0 "" ""))]
10241 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10243 (define_expand "blt"
10244 [(use (match_operand 0 "" ""))]
10246 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10248 (define_expand "bgeu"
10249 [(use (match_operand 0 "" ""))]
10251 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10253 (define_expand "bgtu"
10254 [(use (match_operand 0 "" ""))]
10256 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10258 (define_expand "bleu"
10259 [(use (match_operand 0 "" ""))]
10261 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10263 (define_expand "bltu"
10264 [(use (match_operand 0 "" ""))]
10266 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10268 (define_expand "bunordered"
10269 [(use (match_operand 0 "" ""))]
10271 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10273 (define_expand "bordered"
10274 [(use (match_operand 0 "" ""))]
10276 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10278 (define_expand "buneq"
10279 [(use (match_operand 0 "" ""))]
10281 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10283 (define_expand "bunge"
10284 [(use (match_operand 0 "" ""))]
10286 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10288 (define_expand "bungt"
10289 [(use (match_operand 0 "" ""))]
10291 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10293 (define_expand "bunle"
10294 [(use (match_operand 0 "" ""))]
10296 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10298 (define_expand "bunlt"
10299 [(use (match_operand 0 "" ""))]
10301 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10303 (define_expand "bltgt"
10304 [(use (match_operand 0 "" ""))]
10306 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10308 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10309 ;; For SEQ, likewise, except that comparisons with zero should be done
10310 ;; with an scc insns. However, due to the order that combine see the
10311 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10312 ;; the cases we don't want to handle.
10313 (define_expand "seq"
10314 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10316 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10318 (define_expand "sne"
10319 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10323 if (! rs6000_compare_fp_p)
10326 rs6000_emit_sCOND (NE, operands[0]);
10330 ;; A > 0 is best done using the portable sequence, so fail in that case.
10331 (define_expand "sgt"
10332 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10336 if (! rs6000_compare_fp_p
10337 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10340 rs6000_emit_sCOND (GT, operands[0]);
10344 ;; A < 0 is best done in the portable way for A an integer.
10345 (define_expand "slt"
10346 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10350 if (! rs6000_compare_fp_p
10351 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10354 rs6000_emit_sCOND (LT, operands[0]);
10358 ;; A >= 0 is best done the portable way for A an integer.
10359 (define_expand "sge"
10360 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10364 if (! rs6000_compare_fp_p
10365 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10368 rs6000_emit_sCOND (GE, operands[0]);
10372 ;; A <= 0 is best done the portable way for A an integer.
10373 (define_expand "sle"
10374 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10378 if (! rs6000_compare_fp_p
10379 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10382 rs6000_emit_sCOND (LE, operands[0]);
10386 (define_expand "sgtu"
10387 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10389 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10391 (define_expand "sltu"
10392 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10394 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10396 (define_expand "sgeu"
10397 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10399 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10401 (define_expand "sleu"
10402 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10404 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10406 ;; Here are the actual compare insns.
10407 (define_insn "*cmpsi_internal1"
10408 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10409 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10410 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10412 "{cmp%I2|cmpw%I2} %0,%1,%2"
10413 [(set_attr "type" "compare")])
10415 (define_insn "*cmpdi_internal1"
10416 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10417 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
10418 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10421 [(set_attr "type" "compare")])
10423 ;; If we are comparing a register for equality with a large constant,
10424 ;; we can do this with an XOR followed by a compare. But we need a scratch
10425 ;; register for the result of the XOR.
10428 [(set (match_operand:CC 0 "cc_reg_operand" "")
10429 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10430 (match_operand:SI 2 "non_short_cint_operand" "")))
10431 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10432 "find_single_use (operands[0], insn, 0)
10433 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10434 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10435 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10436 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10439 /* Get the constant we are comparing against, C, and see what it looks like
10440 sign-extended to 16 bits. Then see what constant could be XOR'ed
10441 with C to get the sign-extended value. */
10443 HOST_WIDE_INT c = INTVAL (operands[2]);
10444 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10445 HOST_WIDE_INT xorv = c ^ sextc;
10447 operands[4] = GEN_INT (xorv);
10448 operands[5] = GEN_INT (sextc);
10451 (define_insn "*cmpsi_internal2"
10452 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10453 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10454 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10456 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10457 [(set_attr "type" "compare")])
10459 (define_insn "*cmpdi_internal2"
10460 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10461 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10462 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10464 "cmpld%I2 %0,%1,%b2"
10465 [(set_attr "type" "compare")])
10467 ;; The following two insns don't exist as single insns, but if we provide
10468 ;; them, we can swap an add and compare, which will enable us to overlap more
10469 ;; of the required delay between a compare and branch. We generate code for
10470 ;; them by splitting.
10473 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10474 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10475 (match_operand:SI 2 "short_cint_operand" "i")))
10476 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10477 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10480 [(set_attr "length" "8")])
10483 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10484 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10485 (match_operand:SI 2 "u_short_cint_operand" "i")))
10486 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10487 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10490 [(set_attr "length" "8")])
10493 [(set (match_operand:CC 3 "cc_reg_operand" "")
10494 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10495 (match_operand:SI 2 "short_cint_operand" "")))
10496 (set (match_operand:SI 0 "gpc_reg_operand" "")
10497 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10499 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10500 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10503 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10504 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10505 (match_operand:SI 2 "u_short_cint_operand" "")))
10506 (set (match_operand:SI 0 "gpc_reg_operand" "")
10507 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10509 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10510 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10512 (define_insn "*cmpsf_internal1"
10513 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10514 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10515 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10516 "TARGET_HARD_FLOAT"
10518 [(set_attr "type" "fpcompare")])
10520 (define_insn "*cmpdf_internal1"
10521 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10522 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10523 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10524 "TARGET_HARD_FLOAT"
10526 [(set_attr "type" "fpcompare")])
10528 ;; Only need to compare second words if first words equal
10529 (define_insn "*cmptf_internal1"
10530 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10531 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10532 (match_operand:TF 2 "gpc_reg_operand" "f")))]
10533 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
10534 "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2"
10535 [(set_attr "type" "fpcompare")
10536 (set_attr "length" "12")])
10538 ;; Now we have the scc insns. We can do some combinations because of the
10539 ;; way the machine works.
10541 ;; Note that this is probably faster if we can put an insn between the
10542 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10543 ;; cases the insns below which don't use an intermediate CR field will
10544 ;; be used instead.
10546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10547 (match_operator:SI 1 "scc_comparison_operator"
10548 [(match_operand 2 "cc_reg_operand" "y")
10551 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
10552 [(set_attr "length" "12")])
10555 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10556 (match_operator:DI 1 "scc_comparison_operator"
10557 [(match_operand 2 "cc_reg_operand" "y")
10560 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
10561 [(set_attr "length" "12")])
10564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10565 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10566 [(match_operand 2 "cc_reg_operand" "y,y")
10569 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10570 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10571 "! TARGET_POWERPC64"
10573 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
10575 [(set_attr "type" "delayed_compare")
10576 (set_attr "length" "12,16")])
10579 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10580 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10581 [(match_operand 2 "cc_reg_operand" "")
10584 (set (match_operand:SI 3 "gpc_reg_operand" "")
10585 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10586 "! TARGET_POWERPC64 && reload_completed"
10587 [(set (match_dup 3)
10588 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
10590 (compare:CC (match_dup 3)
10595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10596 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10597 [(match_operand 2 "cc_reg_operand" "y")
10599 (match_operand:SI 3 "const_int_operand" "n")))]
10603 int is_bit = ccr_bit (operands[1], 1);
10604 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10607 if (is_bit >= put_bit)
10608 count = is_bit - put_bit;
10610 count = 32 - (put_bit - is_bit);
10612 operands[4] = GEN_INT (count);
10613 operands[5] = GEN_INT (put_bit);
10615 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
10617 [(set_attr "length" "12")])
10620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10622 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10623 [(match_operand 2 "cc_reg_operand" "y,y")
10625 (match_operand:SI 3 "const_int_operand" "n,n"))
10627 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
10628 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10630 "! TARGET_POWERPC64"
10633 int is_bit = ccr_bit (operands[1], 1);
10634 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10637 /* Force split for non-cc0 compare. */
10638 if (which_alternative == 1)
10641 if (is_bit >= put_bit)
10642 count = is_bit - put_bit;
10644 count = 32 - (put_bit - is_bit);
10646 operands[5] = GEN_INT (count);
10647 operands[6] = GEN_INT (put_bit);
10649 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
10651 [(set_attr "type" "delayed_compare")
10652 (set_attr "length" "12,16")])
10655 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10657 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10658 [(match_operand 2 "cc_reg_operand" "")
10660 (match_operand:SI 3 "const_int_operand" ""))
10662 (set (match_operand:SI 4 "gpc_reg_operand" "")
10663 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10665 "! TARGET_POWERPC64 && reload_completed"
10666 [(set (match_dup 4)
10667 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10670 (compare:CC (match_dup 4)
10674 ;; There is a 3 cycle delay between consecutive mfcr instructions
10675 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
10678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10679 (match_operator:SI 1 "scc_comparison_operator"
10680 [(match_operand 2 "cc_reg_operand" "y")
10682 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
10683 (match_operator:SI 4 "scc_comparison_operator"
10684 [(match_operand 5 "cc_reg_operand" "y")
10686 "REGNO (operands[2]) != REGNO (operands[5])"
10687 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10688 [(set_attr "length" "20")])
10691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10692 (match_operator:DI 1 "scc_comparison_operator"
10693 [(match_operand 2 "cc_reg_operand" "y")
10695 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
10696 (match_operator:DI 4 "scc_comparison_operator"
10697 [(match_operand 5 "cc_reg_operand" "y")
10699 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
10700 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10701 [(set_attr "length" "20")])
10703 ;; There are some scc insns that can be done directly, without a compare.
10704 ;; These are faster because they don't involve the communications between
10705 ;; the FXU and branch units. In fact, we will be replacing all of the
10706 ;; integer scc insns here or in the portable methods in emit_store_flag.
10708 ;; Also support (neg (scc ..)) since that construct is used to replace
10709 ;; branches, (plus (scc ..) ..) since that construct is common and
10710 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
10711 ;; cases where it is no more expensive than (neg (scc ..)).
10713 ;; Have reload force a constant into a register for the simple insns that
10714 ;; otherwise won't accept constants. We do this because it is faster than
10715 ;; the cmp/mfcr sequence we would otherwise generate.
10718 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10719 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10720 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
10721 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
10722 "! TARGET_POWERPC64"
10724 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10725 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
10726 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10727 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10728 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
10729 [(set_attr "length" "12,8,12,12,12")])
10732 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
10733 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
10734 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
10735 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
10738 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
10739 subfic %3,%1,0\;adde %0,%3,%1
10740 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
10741 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
10742 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
10743 [(set_attr "length" "12,8,12,12,12")])
10746 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10748 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10749 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10751 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10752 (eq:SI (match_dup 1) (match_dup 2)))
10753 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10754 "! TARGET_POWERPC64"
10756 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10757 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
10758 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10759 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10760 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10766 [(set_attr "type" "compare")
10767 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10770 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10772 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10773 (match_operand:SI 2 "reg_or_cint_operand" ""))
10775 (set (match_operand:SI 0 "gpc_reg_operand" "")
10776 (eq:SI (match_dup 1) (match_dup 2)))
10777 (clobber (match_scratch:SI 3 ""))]
10778 "! TARGET_POWERPC64 && reload_completed"
10779 [(parallel [(set (match_dup 0)
10780 (eq:SI (match_dup 1) (match_dup 2)))
10781 (clobber (match_dup 3))])
10783 (compare:CC (match_dup 0)
10788 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10790 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10791 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
10793 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10794 (eq:DI (match_dup 1) (match_dup 2)))
10795 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10798 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10799 subfic %3,%1,0\;adde. %0,%3,%1
10800 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
10801 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
10802 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10808 [(set_attr "type" "compare")
10809 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10812 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10814 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
10815 (match_operand:DI 2 "reg_or_cint_operand" ""))
10817 (set (match_operand:DI 0 "gpc_reg_operand" "")
10818 (eq:DI (match_dup 1) (match_dup 2)))
10819 (clobber (match_scratch:DI 3 ""))]
10820 "TARGET_POWERPC64 && reload_completed"
10821 [(parallel [(set (match_dup 0)
10822 (eq:DI (match_dup 1) (match_dup 2)))
10823 (clobber (match_dup 3))])
10825 (compare:CC (match_dup 0)
10829 ;; We have insns of the form shown by the first define_insn below. If
10830 ;; there is something inside the comparison operation, we must split it.
10832 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10833 (plus:SI (match_operator 1 "comparison_operator"
10834 [(match_operand:SI 2 "" "")
10835 (match_operand:SI 3
10836 "reg_or_cint_operand" "")])
10837 (match_operand:SI 4 "gpc_reg_operand" "")))
10838 (clobber (match_operand:SI 5 "register_operand" ""))]
10839 "! gpc_reg_operand (operands[2], SImode)"
10840 [(set (match_dup 5) (match_dup 2))
10841 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
10845 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
10846 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10847 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
10848 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
10849 "! TARGET_POWERPC64"
10851 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
10852 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
10853 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
10854 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
10855 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
10856 [(set_attr "length" "12,8,12,12,12")])
10859 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10862 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10863 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10864 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10866 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
10867 "! TARGET_POWERPC64"
10869 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10870 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
10871 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10872 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10873 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10879 [(set_attr "type" "compare")
10880 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10886 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10887 (match_operand:SI 2 "reg_or_cint_operand" ""))
10888 (match_operand:SI 3 "gpc_reg_operand" ""))
10890 (clobber (match_scratch:SI 4 ""))]
10891 "! TARGET_POWERPC64 && reload_completed"
10892 [(set (match_dup 4)
10893 (plus:SI (eq:SI (match_dup 1)
10897 (compare:CC (match_dup 4)
10902 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10905 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10906 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10907 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10909 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
10910 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
10911 "! TARGET_POWERPC64"
10913 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
10914 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
10915 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
10916 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
10917 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
10923 [(set_attr "type" "compare")
10924 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10927 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10930 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10931 (match_operand:SI 2 "reg_or_cint_operand" ""))
10932 (match_operand:SI 3 "gpc_reg_operand" ""))
10934 (set (match_operand:SI 0 "gpc_reg_operand" "")
10935 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
10936 "! TARGET_POWERPC64 && reload_completed"
10937 [(set (match_dup 0)
10938 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10940 (compare:CC (match_dup 0)
10945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10946 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10947 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
10948 "! TARGET_POWERPC64"
10950 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10951 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
10952 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10953 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10954 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
10955 [(set_attr "length" "12,8,12,12,12")])
10957 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
10958 ;; since it nabs/sr is just as fast.
10959 (define_insn "*ne0"
10960 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
10961 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10963 (clobber (match_scratch:SI 2 "=&r"))]
10964 "! TARGET_POWER && ! TARGET_POWERPC64"
10965 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
10966 [(set_attr "length" "8")])
10969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10970 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10972 (clobber (match_scratch:DI 2 "=&r"))]
10974 "addic %2,%1,-1\;subfe %0,%2,%1"
10975 [(set_attr "length" "8")])
10977 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
10979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10980 (plus:SI (lshiftrt:SI
10981 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10983 (match_operand:SI 2 "gpc_reg_operand" "r")))
10984 (clobber (match_scratch:SI 3 "=&r"))]
10985 "! TARGET_POWERPC64"
10986 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
10987 [(set_attr "length" "8")])
10990 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10991 (plus:DI (lshiftrt:DI
10992 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10994 (match_operand:DI 2 "gpc_reg_operand" "r")))
10995 (clobber (match_scratch:DI 3 "=&r"))]
10997 "addic %3,%1,-1\;addze %0,%2"
10998 [(set_attr "length" "8")])
11001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11003 (plus:SI (lshiftrt:SI
11004 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11006 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11008 (clobber (match_scratch:SI 3 "=&r,&r"))
11009 (clobber (match_scratch:SI 4 "=X,&r"))]
11010 "! TARGET_POWERPC64"
11012 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11014 [(set_attr "type" "compare")
11015 (set_attr "length" "8,12")])
11018 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11020 (plus:SI (lshiftrt:SI
11021 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11023 (match_operand:SI 2 "gpc_reg_operand" ""))
11025 (clobber (match_scratch:SI 3 ""))
11026 (clobber (match_scratch:SI 4 ""))]
11027 "! TARGET_POWERPC64 && reload_completed"
11028 [(parallel [(set (match_dup 3)
11029 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11032 (clobber (match_dup 4))])
11034 (compare:CC (match_dup 3)
11039 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11041 (plus:DI (lshiftrt:DI
11042 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11044 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11046 (clobber (match_scratch:DI 3 "=&r,&r"))]
11049 addic %3,%1,-1\;addze. %3,%2
11051 [(set_attr "type" "compare")
11052 (set_attr "length" "8,12")])
11055 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11057 (plus:DI (lshiftrt:DI
11058 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11060 (match_operand:DI 2 "gpc_reg_operand" ""))
11062 (clobber (match_scratch:DI 3 ""))]
11063 "TARGET_POWERPC64 && reload_completed"
11064 [(set (match_dup 3)
11065 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11069 (compare:CC (match_dup 3)
11074 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11076 (plus:SI (lshiftrt:SI
11077 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11079 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11081 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11082 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11084 (clobber (match_scratch:SI 3 "=&r,&r"))]
11085 "! TARGET_POWERPC64"
11087 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11089 [(set_attr "type" "compare")
11090 (set_attr "length" "8,12")])
11093 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11095 (plus:SI (lshiftrt:SI
11096 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11098 (match_operand:SI 2 "gpc_reg_operand" ""))
11100 (set (match_operand:SI 0 "gpc_reg_operand" "")
11101 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11103 (clobber (match_scratch:SI 3 ""))]
11104 "! TARGET_POWERPC64 && reload_completed"
11105 [(parallel [(set (match_dup 0)
11106 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11108 (clobber (match_dup 3))])
11110 (compare:CC (match_dup 0)
11115 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11117 (plus:DI (lshiftrt:DI
11118 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11120 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11122 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11123 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11125 (clobber (match_scratch:DI 3 "=&r,&r"))]
11128 addic %3,%1,-1\;addze. %0,%2
11130 [(set_attr "type" "compare")
11131 (set_attr "length" "8,12")])
11134 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11136 (plus:DI (lshiftrt:DI
11137 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11139 (match_operand:DI 2 "gpc_reg_operand" ""))
11141 (set (match_operand:DI 0 "gpc_reg_operand" "")
11142 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11144 (clobber (match_scratch:DI 3 ""))]
11145 "TARGET_POWERPC64 && reload_completed"
11146 [(parallel [(set (match_dup 0)
11147 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11149 (clobber (match_dup 3))])
11151 (compare:CC (match_dup 0)
11156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11157 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11158 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11159 (clobber (match_scratch:SI 3 "=r,X"))]
11162 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11163 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11164 [(set_attr "length" "12")])
11167 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11169 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11170 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11172 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11173 (le:SI (match_dup 1) (match_dup 2)))
11174 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11177 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11178 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11181 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11182 (set_attr "length" "12,12,16,16")])
11185 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11187 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11188 (match_operand:SI 2 "reg_or_short_operand" ""))
11190 (set (match_operand:SI 0 "gpc_reg_operand" "")
11191 (le:SI (match_dup 1) (match_dup 2)))
11192 (clobber (match_scratch:SI 3 ""))]
11193 "TARGET_POWER && reload_completed"
11194 [(parallel [(set (match_dup 0)
11195 (le:SI (match_dup 1) (match_dup 2)))
11196 (clobber (match_dup 3))])
11198 (compare:CC (match_dup 0)
11203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11204 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11205 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11206 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11207 (clobber (match_scratch:SI 4 "=&r,&r"))]
11210 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
11211 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
11212 [(set_attr "length" "12")])
11215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11217 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11218 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11219 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11221 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11224 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11225 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11228 [(set_attr "type" "compare")
11229 (set_attr "length" "12,12,16,16")])
11232 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11234 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11235 (match_operand:SI 2 "reg_or_short_operand" ""))
11236 (match_operand:SI 3 "gpc_reg_operand" ""))
11238 (clobber (match_scratch:SI 4 ""))]
11239 "TARGET_POWER && reload_completed"
11240 [(set (match_dup 4)
11241 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11244 (compare:CC (match_dup 4)
11249 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11251 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11252 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11253 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11255 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11256 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11257 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11260 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11261 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
11264 [(set_attr "type" "compare")
11265 (set_attr "length" "12,12,16,16")])
11268 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11270 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11271 (match_operand:SI 2 "reg_or_short_operand" ""))
11272 (match_operand:SI 3 "gpc_reg_operand" ""))
11274 (set (match_operand:SI 0 "gpc_reg_operand" "")
11275 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11276 (clobber (match_scratch:SI 4 ""))]
11277 "TARGET_POWER && reload_completed"
11278 [(parallel [(set (match_dup 0)
11279 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11280 (clobber (match_dup 4))])
11282 (compare:CC (match_dup 0)
11287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11288 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11289 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11292 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11293 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11294 [(set_attr "length" "12")])
11297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11298 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11299 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11300 "! TARGET_POWERPC64"
11301 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11302 [(set_attr "length" "12")])
11305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11306 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11307 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11309 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11310 [(set_attr "length" "12")])
11313 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11315 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11316 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11318 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11319 (leu:DI (match_dup 1) (match_dup 2)))]
11322 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11324 [(set_attr "type" "compare")
11325 (set_attr "length" "12,16")])
11328 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11330 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11331 (match_operand:DI 2 "reg_or_short_operand" ""))
11333 (set (match_operand:DI 0 "gpc_reg_operand" "")
11334 (leu:DI (match_dup 1) (match_dup 2)))]
11335 "TARGET_POWERPC64 && reload_completed"
11336 [(set (match_dup 0)
11337 (leu:DI (match_dup 1) (match_dup 2)))
11339 (compare:CC (match_dup 0)
11344 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11346 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11347 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11349 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11350 (leu:SI (match_dup 1) (match_dup 2)))]
11351 "! TARGET_POWERPC64"
11353 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11355 [(set_attr "type" "compare")
11356 (set_attr "length" "12,16")])
11359 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11361 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11362 (match_operand:SI 2 "reg_or_short_operand" ""))
11364 (set (match_operand:SI 0 "gpc_reg_operand" "")
11365 (leu:SI (match_dup 1) (match_dup 2)))]
11366 "! TARGET_POWERPC64 && reload_completed"
11367 [(set (match_dup 0)
11368 (leu:SI (match_dup 1) (match_dup 2)))
11370 (compare:CC (match_dup 0)
11375 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11377 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11378 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11380 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11381 (leu:DI (match_dup 1) (match_dup 2)))]
11384 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11386 [(set_attr "type" "compare")
11387 (set_attr "length" "12,16")])
11390 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11391 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11392 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11393 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11394 "! TARGET_POWERPC64"
11395 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11396 [(set_attr "length" "8")])
11399 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11401 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11402 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11403 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11405 (clobber (match_scratch:SI 4 "=&r,&r"))]
11406 "! TARGET_POWERPC64"
11408 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11410 [(set_attr "type" "compare")
11411 (set_attr "length" "8,12")])
11414 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11416 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11417 (match_operand:SI 2 "reg_or_short_operand" ""))
11418 (match_operand:SI 3 "gpc_reg_operand" ""))
11420 (clobber (match_scratch:SI 4 ""))]
11421 "! TARGET_POWERPC64 && reload_completed"
11422 [(set (match_dup 4)
11423 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11426 (compare:CC (match_dup 4)
11431 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11433 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11434 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11435 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11437 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11438 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11439 (clobber (match_scratch:SI 4 "=&r,&r"))]
11440 "! TARGET_POWERPC64"
11442 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
11444 [(set_attr "type" "compare")
11445 (set_attr "length" "8,12")])
11448 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11450 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11451 (match_operand:SI 2 "reg_or_short_operand" ""))
11452 (match_operand:SI 3 "gpc_reg_operand" ""))
11454 (set (match_operand:SI 0 "gpc_reg_operand" "")
11455 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11456 (clobber (match_scratch:SI 4 ""))]
11457 "! TARGET_POWERPC64 && reload_completed"
11458 [(parallel [(set (match_dup 0)
11459 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11460 (clobber (match_dup 4))])
11462 (compare:CC (match_dup 0)
11467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11468 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11469 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11470 "! TARGET_POWERPC64"
11471 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11472 [(set_attr "length" "12")])
11475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11477 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11478 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11479 (match_operand:SI 3 "gpc_reg_operand" "r")))
11480 (clobber (match_scratch:SI 4 "=&r"))]
11481 "! TARGET_POWERPC64"
11482 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
11483 [(set_attr "length" "12")])
11486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11489 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11490 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11491 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11493 (clobber (match_scratch:SI 4 "=&r,&r"))]
11494 "! TARGET_POWERPC64"
11496 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11498 [(set_attr "type" "compare")
11499 (set_attr "length" "12,16")])
11502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11505 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11506 (match_operand:SI 2 "reg_or_short_operand" "")))
11507 (match_operand:SI 3 "gpc_reg_operand" ""))
11509 (clobber (match_scratch:SI 4 ""))]
11510 "! TARGET_POWERPC64 && reload_completed"
11511 [(set (match_dup 4)
11512 (and:SI (neg:SI (leu:SI (match_dup 1)
11516 (compare:CC (match_dup 4)
11521 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11524 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11525 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11526 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11528 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11529 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11530 (clobber (match_scratch:SI 4 "=&r,&r"))]
11531 "! TARGET_POWERPC64"
11533 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11535 [(set_attr "type" "compare")
11536 (set_attr "length" "12,16")])
11539 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11542 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11543 (match_operand:SI 2 "reg_or_short_operand" "")))
11544 (match_operand:SI 3 "gpc_reg_operand" ""))
11546 (set (match_operand:SI 0 "gpc_reg_operand" "")
11547 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11548 (clobber (match_scratch:SI 4 ""))]
11549 "! TARGET_POWERPC64 && reload_completed"
11550 [(parallel [(set (match_dup 0)
11551 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11552 (clobber (match_dup 4))])
11554 (compare:CC (match_dup 0)
11559 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11560 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11561 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11563 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11564 [(set_attr "length" "12")])
11567 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11569 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11570 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11572 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11573 (lt:SI (match_dup 1) (match_dup 2)))]
11576 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11578 [(set_attr "type" "delayed_compare")
11579 (set_attr "length" "12,16")])
11582 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11584 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11585 (match_operand:SI 2 "reg_or_short_operand" ""))
11587 (set (match_operand:SI 0 "gpc_reg_operand" "")
11588 (lt:SI (match_dup 1) (match_dup 2)))]
11589 "TARGET_POWER && reload_completed"
11590 [(set (match_dup 0)
11591 (lt:SI (match_dup 1) (match_dup 2)))
11593 (compare:CC (match_dup 0)
11598 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11599 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11600 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11601 (match_operand:SI 3 "gpc_reg_operand" "r")))
11602 (clobber (match_scratch:SI 4 "=&r"))]
11604 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
11605 [(set_attr "length" "12")])
11608 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11610 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11611 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11612 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11614 (clobber (match_scratch:SI 4 "=&r,&r"))]
11617 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11619 [(set_attr "type" "compare")
11620 (set_attr "length" "12,16")])
11623 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11625 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11626 (match_operand:SI 2 "reg_or_short_operand" ""))
11627 (match_operand:SI 3 "gpc_reg_operand" ""))
11629 (clobber (match_scratch:SI 4 ""))]
11630 "TARGET_POWER && reload_completed"
11631 [(set (match_dup 4)
11632 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
11635 (compare:CC (match_dup 4)
11640 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11642 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11643 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11644 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11646 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11647 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11648 (clobber (match_scratch:SI 4 "=&r,&r"))]
11651 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
11653 [(set_attr "type" "compare")
11654 (set_attr "length" "12,16")])
11657 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11659 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11660 (match_operand:SI 2 "reg_or_short_operand" ""))
11661 (match_operand:SI 3 "gpc_reg_operand" ""))
11663 (set (match_operand:SI 0 "gpc_reg_operand" "")
11664 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11665 (clobber (match_scratch:SI 4 ""))]
11666 "TARGET_POWER && reload_completed"
11667 [(parallel [(set (match_dup 0)
11668 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11669 (clobber (match_dup 4))])
11671 (compare:CC (match_dup 0)
11676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11677 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11678 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11680 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
11681 [(set_attr "length" "12")])
11684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11685 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11686 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11687 "! TARGET_POWERPC64"
11689 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
11690 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
11691 [(set_attr "length" "12")])
11694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11696 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11697 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11699 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11700 (ltu:SI (match_dup 1) (match_dup 2)))]
11701 "! TARGET_POWERPC64"
11703 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11704 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11707 [(set_attr "type" "compare")
11708 (set_attr "length" "12,12,16,16")])
11711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11713 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11714 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11716 (set (match_operand:SI 0 "gpc_reg_operand" "")
11717 (ltu:SI (match_dup 1) (match_dup 2)))]
11718 "! TARGET_POWERPC64 && reload_completed"
11719 [(set (match_dup 0)
11720 (ltu:SI (match_dup 1) (match_dup 2)))
11722 (compare:CC (match_dup 0)
11727 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11728 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11729 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
11730 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
11731 "! TARGET_POWERPC64"
11733 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
11734 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
11735 [(set_attr "length" "12")])
11738 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11740 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11741 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11742 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11744 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11745 "! TARGET_POWERPC64"
11747 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11748 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11751 [(set_attr "type" "compare")
11752 (set_attr "length" "12,12,16,16")])
11755 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11757 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11758 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11759 (match_operand:SI 3 "gpc_reg_operand" ""))
11761 (clobber (match_scratch:SI 4 ""))]
11762 "! TARGET_POWERPC64 && reload_completed"
11763 [(set (match_dup 4)
11764 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
11767 (compare:CC (match_dup 4)
11772 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11774 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11775 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11776 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11778 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11779 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11780 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11781 "! TARGET_POWERPC64"
11783 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11784 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11787 [(set_attr "type" "compare")
11788 (set_attr "length" "12,12,16,16")])
11791 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11793 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11794 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11795 (match_operand:SI 3 "gpc_reg_operand" ""))
11797 (set (match_operand:SI 0 "gpc_reg_operand" "")
11798 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11799 (clobber (match_scratch:SI 4 ""))]
11800 "! TARGET_POWERPC64 && reload_completed"
11801 [(parallel [(set (match_dup 0)
11802 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11803 (clobber (match_dup 4))])
11805 (compare:CC (match_dup 0)
11810 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11811 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11812 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
11813 "! TARGET_POWERPC64"
11815 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
11816 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
11817 [(set_attr "length" "8")])
11820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11821 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11822 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11823 (clobber (match_scratch:SI 3 "=r"))]
11825 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
11826 [(set_attr "length" "12")])
11829 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11831 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11832 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11835 (ge:SI (match_dup 1) (match_dup 2)))
11836 (clobber (match_scratch:SI 3 "=r,r"))]
11839 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11841 [(set_attr "type" "compare")
11842 (set_attr "length" "12,16")])
11845 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11847 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11848 (match_operand:SI 2 "reg_or_short_operand" ""))
11850 (set (match_operand:SI 0 "gpc_reg_operand" "")
11851 (ge:SI (match_dup 1) (match_dup 2)))
11852 (clobber (match_scratch:SI 3 ""))]
11853 "TARGET_POWER && reload_completed"
11854 [(parallel [(set (match_dup 0)
11855 (ge:SI (match_dup 1) (match_dup 2)))
11856 (clobber (match_dup 3))])
11858 (compare:CC (match_dup 0)
11863 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11864 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11865 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11866 (match_operand:SI 3 "gpc_reg_operand" "r")))
11867 (clobber (match_scratch:SI 4 "=&r"))]
11869 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
11870 [(set_attr "length" "12")])
11873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11875 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11876 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11877 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11879 (clobber (match_scratch:SI 4 "=&r,&r"))]
11882 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11884 [(set_attr "type" "compare")
11885 (set_attr "length" "12,16")])
11888 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11890 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11891 (match_operand:SI 2 "reg_or_short_operand" ""))
11892 (match_operand:SI 3 "gpc_reg_operand" ""))
11894 (clobber (match_scratch:SI 4 ""))]
11895 "TARGET_POWER && reload_completed"
11896 [(set (match_dup 4)
11897 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
11900 (compare:CC (match_dup 4)
11905 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11907 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11908 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11909 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11911 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11912 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11913 (clobber (match_scratch:SI 4 "=&r,&r"))]
11916 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11918 [(set_attr "type" "compare")
11919 (set_attr "length" "12,16")])
11922 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11924 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11925 (match_operand:SI 2 "reg_or_short_operand" ""))
11926 (match_operand:SI 3 "gpc_reg_operand" ""))
11928 (set (match_operand:SI 0 "gpc_reg_operand" "")
11929 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11930 (clobber (match_scratch:SI 4 ""))]
11931 "TARGET_POWER && reload_completed"
11932 [(parallel [(set (match_dup 0)
11933 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11934 (clobber (match_dup 4))])
11936 (compare:CC (match_dup 0)
11941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11942 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11943 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11945 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11946 [(set_attr "length" "12")])
11949 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11950 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11951 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11952 "! TARGET_POWERPC64"
11954 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
11955 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11956 [(set_attr "length" "12")])
11959 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11960 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11961 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
11964 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
11965 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
11966 [(set_attr "length" "12")])
11969 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11971 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11972 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11974 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11975 (geu:SI (match_dup 1) (match_dup 2)))]
11976 "! TARGET_POWERPC64"
11978 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11979 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11982 [(set_attr "type" "compare")
11983 (set_attr "length" "12,12,16,16")])
11986 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11988 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11989 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11991 (set (match_operand:SI 0 "gpc_reg_operand" "")
11992 (geu:SI (match_dup 1) (match_dup 2)))]
11993 "! TARGET_POWERPC64 && reload_completed"
11994 [(set (match_dup 0)
11995 (geu:SI (match_dup 1) (match_dup 2)))
11997 (compare:CC (match_dup 0)
12002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12004 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12005 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12007 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12008 (geu:DI (match_dup 1) (match_dup 2)))]
12011 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12012 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12015 [(set_attr "type" "compare")
12016 (set_attr "length" "12,12,16,16")])
12019 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12021 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12022 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12024 (set (match_operand:DI 0 "gpc_reg_operand" "")
12025 (geu:DI (match_dup 1) (match_dup 2)))]
12026 "TARGET_POWERPC64 && reload_completed"
12027 [(set (match_dup 0)
12028 (geu:DI (match_dup 1) (match_dup 2)))
12030 (compare:CC (match_dup 0)
12035 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12036 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12037 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12038 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12039 "! TARGET_POWERPC64"
12041 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12042 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12043 [(set_attr "length" "8")])
12046 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12048 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12049 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12050 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12052 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12053 "! TARGET_POWERPC64"
12055 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12056 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12059 [(set_attr "type" "compare")
12060 (set_attr "length" "8,8,12,12")])
12063 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12065 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12066 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12067 (match_operand:SI 3 "gpc_reg_operand" ""))
12069 (clobber (match_scratch:SI 4 ""))]
12070 "! TARGET_POWERPC64 && reload_completed"
12071 [(set (match_dup 4)
12072 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12075 (compare:CC (match_dup 4)
12080 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12082 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12083 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12084 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12086 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12087 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12088 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12089 "! TARGET_POWERPC64"
12091 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
12092 {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3
12095 [(set_attr "type" "compare")
12096 (set_attr "length" "8,8,12,12")])
12099 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12101 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12102 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12103 (match_operand:SI 3 "gpc_reg_operand" ""))
12105 (set (match_operand:SI 0 "gpc_reg_operand" "")
12106 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12107 (clobber (match_scratch:SI 4 ""))]
12108 "! TARGET_POWERPC64 && reload_completed"
12109 [(parallel [(set (match_dup 0)
12110 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12111 (clobber (match_dup 4))])
12113 (compare:CC (match_dup 0)
12118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12119 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12120 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12121 "! TARGET_POWERPC64"
12123 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12124 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12125 [(set_attr "length" "12")])
12128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12130 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12131 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12132 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
12133 (clobber (match_scratch:SI 4 "=&r,&r"))]
12134 "! TARGET_POWERPC64"
12136 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
12137 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
12138 [(set_attr "length" "12")])
12141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12144 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12145 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12146 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12148 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12149 "! TARGET_POWERPC64"
12151 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12152 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12155 [(set_attr "type" "compare")
12156 (set_attr "length" "12,12,16,16")])
12159 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12162 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12163 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12164 (match_operand:SI 3 "gpc_reg_operand" ""))
12166 (clobber (match_scratch:SI 4 ""))]
12167 "! TARGET_POWERPC64 && reload_completed"
12168 [(set (match_dup 4)
12169 (and:SI (neg:SI (geu:SI (match_dup 1)
12173 (compare:CC (match_dup 4)
12178 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12181 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12182 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12183 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12185 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12186 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12187 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12188 "! TARGET_POWERPC64"
12190 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
12191 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
12194 [(set_attr "type" "compare")
12195 (set_attr "length" "12,12,16,16")])
12198 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12201 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12202 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12203 (match_operand:SI 3 "gpc_reg_operand" ""))
12205 (set (match_operand:SI 0 "gpc_reg_operand" "")
12206 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12207 (clobber (match_scratch:SI 4 ""))]
12208 "! TARGET_POWERPC64 && reload_completed"
12209 [(parallel [(set (match_dup 0)
12210 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12211 (clobber (match_dup 4))])
12213 (compare:CC (match_dup 0)
12218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12219 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12221 "! TARGET_POWERPC64"
12222 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12223 [(set_attr "length" "12")])
12226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12227 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12230 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12231 [(set_attr "length" "12")])
12234 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12236 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12239 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12240 (gt:SI (match_dup 1) (const_int 0)))]
12241 "! TARGET_POWERPC64"
12243 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12245 [(set_attr "type" "delayed_compare")
12246 (set_attr "length" "12,16")])
12249 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12251 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12254 (set (match_operand:SI 0 "gpc_reg_operand" "")
12255 (gt:SI (match_dup 1) (const_int 0)))]
12256 "! TARGET_POWERPC64 && reload_completed"
12257 [(set (match_dup 0)
12258 (gt:SI (match_dup 1) (const_int 0)))
12260 (compare:CC (match_dup 0)
12265 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12267 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12270 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12271 (gt:DI (match_dup 1) (const_int 0)))]
12274 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12276 [(set_attr "type" "delayed_compare")
12277 (set_attr "length" "12,16")])
12280 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12282 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12285 (set (match_operand:DI 0 "gpc_reg_operand" "")
12286 (gt:DI (match_dup 1) (const_int 0)))]
12287 "TARGET_POWERPC64 && reload_completed"
12288 [(set (match_dup 0)
12289 (gt:DI (match_dup 1) (const_int 0)))
12291 (compare:CC (match_dup 0)
12296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12297 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12298 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12300 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12301 [(set_attr "length" "12")])
12304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12306 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12307 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12309 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12310 (gt:SI (match_dup 1) (match_dup 2)))]
12313 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12315 [(set_attr "type" "delayed_compare")
12316 (set_attr "length" "12,16")])
12319 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12321 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12322 (match_operand:SI 2 "reg_or_short_operand" ""))
12324 (set (match_operand:SI 0 "gpc_reg_operand" "")
12325 (gt:SI (match_dup 1) (match_dup 2)))]
12326 "TARGET_POWER && reload_completed"
12327 [(set (match_dup 0)
12328 (gt:SI (match_dup 1) (match_dup 2)))
12330 (compare:CC (match_dup 0)
12335 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12336 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12338 (match_operand:SI 2 "gpc_reg_operand" "r")))]
12339 "! TARGET_POWERPC64"
12340 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12341 [(set_attr "length" "12")])
12344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12345 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12347 (match_operand:DI 2 "gpc_reg_operand" "r")))
12348 (clobber (match_scratch:DI 3 "=&r"))]
12350 "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
12351 [(set_attr "length" "12")])
12354 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12356 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12358 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12360 (clobber (match_scratch:SI 3 "=&r,&r"))]
12361 "! TARGET_POWERPC64"
12363 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12365 [(set_attr "type" "compare")
12366 (set_attr "length" "12,16")])
12369 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12371 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12373 (match_operand:SI 2 "gpc_reg_operand" ""))
12375 (clobber (match_scratch:SI 3 ""))]
12376 "! TARGET_POWERPC64 && reload_completed"
12377 [(set (match_dup 3)
12378 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12381 (compare:CC (match_dup 3)
12386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12388 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12390 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12392 (clobber (match_scratch:DI 3 "=&r,&r"))]
12395 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12397 [(set_attr "type" "compare")
12398 (set_attr "length" "12,16")])
12401 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12403 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12405 (match_operand:DI 2 "gpc_reg_operand" ""))
12407 (clobber (match_scratch:DI 3 ""))]
12408 "TARGET_POWERPC64 && reload_completed"
12409 [(set (match_dup 3)
12410 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12413 (compare:CC (match_dup 3)
12418 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12420 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12422 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12424 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12425 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12426 (clobber (match_scratch:SI 3 "=&r,&r"))]
12427 "! TARGET_POWERPC64"
12429 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2
12431 [(set_attr "type" "compare")
12432 (set_attr "length" "12,16")])
12435 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12437 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12439 (match_operand:SI 2 "gpc_reg_operand" ""))
12441 (set (match_operand:SI 0 "gpc_reg_operand" "")
12442 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12443 (clobber (match_scratch:SI 3 ""))]
12444 "! TARGET_POWERPC64 && reload_completed"
12445 [(parallel [(set (match_dup 0)
12446 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12447 (clobber (match_dup 3))])
12449 (compare:CC (match_dup 0)
12454 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12456 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12458 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12460 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12461 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12462 (clobber (match_scratch:DI 3 "=&r,&r"))]
12465 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2
12467 [(set_attr "type" "compare")
12468 (set_attr "length" "12,16")])
12471 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12473 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12475 (match_operand:DI 2 "gpc_reg_operand" ""))
12477 (set (match_operand:DI 0 "gpc_reg_operand" "")
12478 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12479 (clobber (match_scratch:DI 3 ""))]
12480 "TARGET_POWERPC64 && reload_completed"
12481 [(parallel [(set (match_dup 0)
12482 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12483 (clobber (match_dup 3))])
12485 (compare:CC (match_dup 0)
12490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12491 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12492 (match_operand:SI 2 "reg_or_short_operand" "r"))
12493 (match_operand:SI 3 "gpc_reg_operand" "r")))
12494 (clobber (match_scratch:SI 4 "=&r"))]
12496 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
12497 [(set_attr "length" "12")])
12500 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12502 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12503 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12504 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12506 (clobber (match_scratch:SI 4 "=&r,&r"))]
12509 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12511 [(set_attr "type" "compare")
12512 (set_attr "length" "12,16")])
12515 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12517 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12518 (match_operand:SI 2 "reg_or_short_operand" ""))
12519 (match_operand:SI 3 "gpc_reg_operand" ""))
12521 (clobber (match_scratch:SI 4 ""))]
12522 "TARGET_POWER && reload_completed"
12523 [(set (match_dup 4)
12524 (plus:SI (gt:SI (match_dup 1) (match_dup 2))
12527 (compare:CC (match_dup 4)
12532 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
12534 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12535 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12536 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12538 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12539 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12540 (clobber (match_scratch:SI 4 "=&r,&r"))]
12543 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
12545 [(set_attr "type" "compare")
12546 (set_attr "length" "12,16")])
12549 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12551 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12552 (match_operand:SI 2 "reg_or_short_operand" ""))
12553 (match_operand:SI 3 "gpc_reg_operand" ""))
12555 (set (match_operand:SI 0 "gpc_reg_operand" "")
12556 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12557 (clobber (match_scratch:SI 4 ""))]
12558 "TARGET_POWER && reload_completed"
12559 [(parallel [(set (match_dup 0)
12560 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12561 (clobber (match_dup 4))])
12563 (compare:CC (match_dup 0)
12568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12569 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12571 "! TARGET_POWERPC64"
12572 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
12573 [(set_attr "length" "12")])
12576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12577 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12580 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
12581 [(set_attr "length" "12")])
12584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12585 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12586 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12588 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12589 [(set_attr "length" "12")])
12592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12593 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12594 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12595 "! TARGET_POWERPC64"
12596 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12597 [(set_attr "length" "12")])
12600 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12601 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12602 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12604 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
12605 [(set_attr "length" "12")])
12608 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12610 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12611 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12613 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12614 (gtu:SI (match_dup 1) (match_dup 2)))]
12615 "! TARGET_POWERPC64"
12617 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12619 [(set_attr "type" "compare")
12620 (set_attr "length" "12,16")])
12623 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12625 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12626 (match_operand:SI 2 "reg_or_short_operand" ""))
12628 (set (match_operand:SI 0 "gpc_reg_operand" "")
12629 (gtu:SI (match_dup 1) (match_dup 2)))]
12630 "! TARGET_POWERPC64 && reload_completed"
12631 [(set (match_dup 0)
12632 (gtu:SI (match_dup 1) (match_dup 2)))
12634 (compare:CC (match_dup 0)
12639 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12641 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12642 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12644 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12645 (gtu:DI (match_dup 1) (match_dup 2)))]
12648 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
12650 [(set_attr "type" "compare")
12651 (set_attr "length" "12,16")])
12654 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12656 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12657 (match_operand:DI 2 "reg_or_short_operand" ""))
12659 (set (match_operand:DI 0 "gpc_reg_operand" "")
12660 (gtu:DI (match_dup 1) (match_dup 2)))]
12661 "TARGET_POWERPC64 && reload_completed"
12662 [(set (match_dup 0)
12663 (gtu:DI (match_dup 1) (match_dup 2)))
12665 (compare:CC (match_dup 0)
12670 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12671 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12672 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
12673 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
12674 "! TARGET_POWERPC64"
12676 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
12677 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12678 [(set_attr "length" "8,12")])
12681 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12682 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12683 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
12684 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))
12685 (clobber (match_scratch:DI 4 "=&r,&r"))]
12688 addic %4,%1,%k2\;addze %0,%3
12689 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
12690 [(set_attr "length" "8,12")])
12693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12695 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12696 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12697 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12699 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12700 "! TARGET_POWERPC64"
12702 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
12703 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12706 [(set_attr "type" "compare")
12707 (set_attr "length" "8,12,12,16")])
12710 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12712 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12713 (match_operand:SI 2 "reg_or_short_operand" ""))
12714 (match_operand:SI 3 "gpc_reg_operand" ""))
12716 (clobber (match_scratch:SI 4 ""))]
12717 "! TARGET_POWERPC64 && reload_completed"
12718 [(set (match_dup 4)
12719 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
12722 (compare:CC (match_dup 4)
12727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12729 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12730 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12731 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12733 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12736 addic %4,%1,%k2\;addze. %4,%3
12737 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
12740 [(set_attr "type" "compare")
12741 (set_attr "length" "8,12,12,16")])
12744 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12746 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12747 (match_operand:DI 2 "reg_or_short_operand" ""))
12748 (match_operand:DI 3 "gpc_reg_operand" ""))
12750 (clobber (match_scratch:DI 4 ""))]
12751 "TARGET_POWERPC64 && reload_completed"
12752 [(set (match_dup 4)
12753 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
12756 (compare:CC (match_dup 4)
12761 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12763 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12764 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12765 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12767 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12768 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12769 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12770 "! TARGET_POWERPC64"
12772 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
12773 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
12776 [(set_attr "type" "compare")
12777 (set_attr "length" "8,12,12,16")])
12780 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12782 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12783 (match_operand:SI 2 "reg_or_short_operand" ""))
12784 (match_operand:SI 3 "gpc_reg_operand" ""))
12786 (set (match_operand:SI 0 "gpc_reg_operand" "")
12787 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12788 (clobber (match_scratch:SI 4 ""))]
12789 "! TARGET_POWERPC64 && reload_completed"
12790 [(parallel [(set (match_dup 0)
12791 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12792 (clobber (match_dup 4))])
12794 (compare:CC (match_dup 0)
12799 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12801 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12802 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12803 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12805 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12806 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12807 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12810 addic %4,%1,%k2\;addze. %0,%3
12811 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3
12814 [(set_attr "type" "compare")
12815 (set_attr "length" "8,12,12,16")])
12818 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12820 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12821 (match_operand:DI 2 "reg_or_short_operand" ""))
12822 (match_operand:DI 3 "gpc_reg_operand" ""))
12824 (set (match_operand:DI 0 "gpc_reg_operand" "")
12825 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12826 (clobber (match_scratch:DI 4 ""))]
12827 "TARGET_POWERPC64 && reload_completed"
12828 [(parallel [(set (match_dup 0)
12829 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12830 (clobber (match_dup 4))])
12832 (compare:CC (match_dup 0)
12837 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12838 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12839 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12840 "! TARGET_POWERPC64"
12841 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12842 [(set_attr "length" "8")])
12845 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12846 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12847 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
12849 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12850 [(set_attr "length" "8")])
12852 ;; Define both directions of branch and return. If we need a reload
12853 ;; register, we'd rather use CR0 since it is much easier to copy a
12854 ;; register CC value to there.
12858 (if_then_else (match_operator 1 "branch_comparison_operator"
12860 "cc_reg_operand" "x,?y")
12862 (label_ref (match_operand 0 "" ""))
12867 return output_cbranch (operands[1], \"%l0\", 0, insn);
12869 [(set_attr "type" "branch")])
12873 (if_then_else (match_operator 0 "branch_comparison_operator"
12875 "cc_reg_operand" "x,?y")
12882 return output_cbranch (operands[0], NULL, 0, insn);
12884 [(set_attr "type" "branch")
12885 (set_attr "length" "4")])
12889 (if_then_else (match_operator 1 "branch_comparison_operator"
12891 "cc_reg_operand" "x,?y")
12894 (label_ref (match_operand 0 "" ""))))]
12898 return output_cbranch (operands[1], \"%l0\", 1, insn);
12900 [(set_attr "type" "branch")])
12904 (if_then_else (match_operator 0 "branch_comparison_operator"
12906 "cc_reg_operand" "x,?y")
12913 return output_cbranch (operands[0], NULL, 1, insn);
12915 [(set_attr "type" "branch")
12916 (set_attr "length" "4")])
12918 ;; Logic on condition register values.
12920 ; This pattern matches things like
12921 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12922 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12924 ; which are generated by the branch logic.
12927 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12928 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12929 [(match_operator:SI 2
12930 "branch_positive_comparison_operator"
12932 "cc_reg_operand" "y")
12934 (match_operator:SI 4
12935 "branch_positive_comparison_operator"
12937 "cc_reg_operand" "y")
12941 "cr%q1 %E0,%j2,%j4"
12942 [(set_attr "type" "cr_logical")])
12944 ; Why is the constant -1 here, but 1 in the previous pattern?
12945 ; Because ~1 has all but the low bit set.
12947 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12948 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12949 [(not:SI (match_operator:SI 2
12950 "branch_positive_comparison_operator"
12952 "cc_reg_operand" "y")
12954 (match_operator:SI 4
12955 "branch_positive_comparison_operator"
12957 "cc_reg_operand" "y")
12961 "cr%q1 %E0,%j2,%j4"
12962 [(set_attr "type" "cr_logical")])
12965 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12966 (compare:CCEQ (match_operator:SI 1
12967 "branch_positive_comparison_operator"
12969 "cc_reg_operand" "y")
12973 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
12974 [(set_attr "type" "cr_logical")])
12976 ;; If we are comparing the result of two comparisons, this can be done
12977 ;; using creqv or crxor.
12979 (define_insn_and_split ""
12980 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12981 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12982 [(match_operand 2 "cc_reg_operand" "y")
12984 (match_operator 3 "branch_comparison_operator"
12985 [(match_operand 4 "cc_reg_operand" "y")
12990 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12994 int positive_1, positive_2;
12996 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
12997 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13000 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
13001 GET_CODE (operands[1])),
13003 operands[2], const0_rtx);
13004 else if (GET_MODE (operands[1]) != SImode)
13005 operands[1] = gen_rtx (GET_CODE (operands[1]),
13007 operands[2], const0_rtx);
13010 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
13011 GET_CODE (operands[3])),
13013 operands[4], const0_rtx);
13014 else if (GET_MODE (operands[3]) != SImode)
13015 operands[3] = gen_rtx (GET_CODE (operands[3]),
13017 operands[4], const0_rtx);
13019 if (positive_1 == positive_2)
13021 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13022 operands[5] = constm1_rtx;
13026 operands[5] = const1_rtx;
13030 ;; Unconditional branch and return.
13032 (define_insn "jump"
13034 (label_ref (match_operand 0 "" "")))]
13037 [(set_attr "type" "branch")])
13039 (define_insn "return"
13043 [(set_attr "type" "jmpreg")])
13045 (define_expand "indirect_jump"
13046 [(set (pc) (match_operand 0 "register_operand" ""))]
13051 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13053 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13057 (define_insn "indirect_jumpsi"
13058 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13063 [(set_attr "type" "jmpreg")])
13065 (define_insn "indirect_jumpdi"
13066 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13071 [(set_attr "type" "jmpreg")])
13073 ;; Table jump for switch statements:
13074 (define_expand "tablejump"
13075 [(use (match_operand 0 "" ""))
13076 (use (label_ref (match_operand 1 "" "")))]
13081 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13083 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13087 (define_expand "tablejumpsi"
13088 [(set (match_dup 3)
13089 (plus:SI (match_operand:SI 0 "" "")
13091 (parallel [(set (pc) (match_dup 3))
13092 (use (label_ref (match_operand 1 "" "")))])]
13095 { operands[0] = force_reg (SImode, operands[0]);
13096 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13097 operands[3] = gen_reg_rtx (SImode);
13100 (define_expand "tablejumpdi"
13101 [(set (match_dup 4)
13102 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13104 (plus:DI (match_dup 4)
13106 (parallel [(set (pc) (match_dup 3))
13107 (use (label_ref (match_operand 1 "" "")))])]
13110 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13111 operands[3] = gen_reg_rtx (DImode);
13112 operands[4] = gen_reg_rtx (DImode);
13117 (match_operand:SI 0 "register_operand" "c,*l"))
13118 (use (label_ref (match_operand 1 "" "")))]
13123 [(set_attr "type" "jmpreg")])
13127 (match_operand:DI 0 "register_operand" "c,*l"))
13128 (use (label_ref (match_operand 1 "" "")))]
13133 [(set_attr "type" "jmpreg")])
13138 "{cror 0,0,0|nop}")
13140 ;; Define the subtract-one-and-jump insns, starting with the template
13141 ;; so loop.c knows what to generate.
13143 (define_expand "doloop_end"
13144 [(use (match_operand 0 "" "")) ; loop pseudo
13145 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13146 (use (match_operand 2 "" "")) ; max iterations
13147 (use (match_operand 3 "" "")) ; loop level
13148 (use (match_operand 4 "" ""))] ; label
13152 /* Only use this on innermost loops. */
13153 if (INTVAL (operands[3]) > 1)
13155 if (TARGET_POWERPC64)
13157 if (GET_MODE (operands[0]) != DImode)
13159 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13163 if (GET_MODE (operands[0]) != SImode)
13165 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13170 (define_expand "ctrsi"
13171 [(parallel [(set (pc)
13172 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13174 (label_ref (match_operand 1 "" ""))
13177 (plus:SI (match_dup 0)
13179 (clobber (match_scratch:CC 2 ""))
13180 (clobber (match_scratch:SI 3 ""))])]
13181 "! TARGET_POWERPC64"
13184 (define_expand "ctrdi"
13185 [(parallel [(set (pc)
13186 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13188 (label_ref (match_operand 1 "" ""))
13191 (plus:DI (match_dup 0)
13193 (clobber (match_scratch:CC 2 ""))
13194 (clobber (match_scratch:DI 3 ""))])]
13198 ;; We need to be able to do this for any operand, including MEM, or we
13199 ;; will cause reload to blow up since we don't allow output reloads on
13201 ;; For the length attribute to be calculated correctly, the
13202 ;; label MUST be operand 0.
13204 (define_insn "*ctrsi_internal1"
13206 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
13208 (label_ref (match_operand 0 "" ""))
13210 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13211 (plus:SI (match_dup 1)
13213 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13214 (clobber (match_scratch:SI 4 "=X,X,r"))]
13215 "! TARGET_POWERPC64"
13218 if (which_alternative != 0)
13220 else if (get_attr_length (insn) == 4)
13221 return \"{bdn|bdnz} %l0\";
13223 return \"bdz $+8\;b %l0\";
13225 [(set_attr "type" "branch")
13226 (set_attr "length" "*,12,16")])
13228 (define_insn "*ctrsi_internal2"
13230 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
13233 (label_ref (match_operand 0 "" ""))))
13234 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13235 (plus:SI (match_dup 1)
13237 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13238 (clobber (match_scratch:SI 4 "=X,X,r"))]
13239 "! TARGET_POWERPC64"
13242 if (which_alternative != 0)
13244 else if (get_attr_length (insn) == 4)
13245 return \"bdz %l0\";
13247 return \"{bdn|bdnz} $+8\;b %l0\";
13249 [(set_attr "type" "branch")
13250 (set_attr "length" "*,12,16")])
13252 (define_insn "*ctrdi_internal1"
13254 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
13256 (label_ref (match_operand 0 "" ""))
13258 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
13259 (plus:DI (match_dup 1)
13261 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13262 (clobber (match_scratch:DI 4 "=X,X,r,r"))]
13266 if (which_alternative != 0)
13268 else if (get_attr_length (insn) == 4)
13269 return \"{bdn|bdnz} %l0\";
13271 return \"bdz $+8\;b %l0\";
13273 [(set_attr "type" "branch")
13274 (set_attr "length" "*,12,16,24")])
13276 (define_insn "*ctrdi_internal2"
13278 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
13281 (label_ref (match_operand 0 "" ""))))
13282 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
13283 (plus:DI (match_dup 1)
13285 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13286 (clobber (match_scratch:DI 4 "=X,X,r,r"))]
13290 if (which_alternative != 0)
13292 else if (get_attr_length (insn) == 4)
13293 return \"bdz %l0\";
13295 return \"{bdn|bdnz} $+8\;b %l0\";
13297 [(set_attr "type" "branch")
13298 (set_attr "length" "*,12,16,24")])
13300 ;; Similar, but we can use GE since we have a REG_NONNEG.
13302 (define_insn "*ctrsi_internal3"
13304 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
13306 (label_ref (match_operand 0 "" ""))
13308 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13309 (plus:SI (match_dup 1)
13311 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13312 (clobber (match_scratch:SI 4 "=X,X,r"))]
13313 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13316 if (which_alternative != 0)
13318 else if (get_attr_length (insn) == 4)
13319 return \"{bdn|bdnz} %l0\";
13321 return \"bdz $+8\;b %l0\";
13323 [(set_attr "type" "branch")
13324 (set_attr "length" "*,12,16")])
13326 (define_insn "*ctrsi_internal4"
13328 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
13331 (label_ref (match_operand 0 "" ""))))
13332 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13333 (plus:SI (match_dup 1)
13335 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13336 (clobber (match_scratch:SI 4 "=X,X,r"))]
13337 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13340 if (which_alternative != 0)
13342 else if (get_attr_length (insn) == 4)
13343 return \"bdz %l0\";
13345 return \"{bdn|bdnz} $+8\;b %l0\";
13347 [(set_attr "type" "branch")
13348 (set_attr "length" "*,12,16")])
13350 (define_insn "*ctrdi_internal3"
13352 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
13354 (label_ref (match_operand 0 "" ""))
13356 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
13357 (plus:DI (match_dup 1)
13359 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13360 (clobber (match_scratch:DI 4 "=X,X,r,r"))]
13361 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13364 if (which_alternative != 0)
13366 else if (get_attr_length (insn) == 4)
13367 return \"{bdn|bdnz} %l0\";
13369 return \"bdz $+8\;b %l0\";
13371 [(set_attr "type" "branch")
13372 (set_attr "length" "*,12,16,24")])
13374 (define_insn "*ctrdi_internal4"
13376 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
13379 (label_ref (match_operand 0 "" ""))))
13380 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
13381 (plus:DI (match_dup 1)
13383 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13384 (clobber (match_scratch:DI 4 "=X,X,r,r"))]
13385 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13388 if (which_alternative != 0)
13390 else if (get_attr_length (insn) == 4)
13391 return \"bdz %l0\";
13393 return \"{bdn|bdnz} $+8\;b %l0\";
13395 [(set_attr "type" "branch")
13396 (set_attr "length" "*,12,16,24")])
13398 ;; Similar but use EQ
13400 (define_insn "*ctrsi_internal5"
13402 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13404 (label_ref (match_operand 0 "" ""))
13406 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13407 (plus:SI (match_dup 1)
13409 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13410 (clobber (match_scratch:SI 4 "=X,X,r"))]
13411 "! TARGET_POWERPC64"
13414 if (which_alternative != 0)
13416 else if (get_attr_length (insn) == 4)
13417 return \"bdz %l0\";
13419 return \"{bdn|bdnz} $+8\;b %l0\";
13421 [(set_attr "type" "branch")
13422 (set_attr "length" "*,12,16")])
13424 (define_insn "*ctrsi_internal6"
13426 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13429 (label_ref (match_operand 0 "" ""))))
13430 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13431 (plus:SI (match_dup 1)
13433 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13434 (clobber (match_scratch:SI 4 "=X,X,r"))]
13435 "! TARGET_POWERPC64"
13438 if (which_alternative != 0)
13440 else if (get_attr_length (insn) == 4)
13441 return \"{bdn|bdnz} %l0\";
13443 return \"bdz $+8\;b %l0\";
13445 [(set_attr "type" "branch")
13446 (set_attr "length" "*,12,16")])
13448 (define_insn "*ctrdi_internal5"
13450 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
13452 (label_ref (match_operand 0 "" ""))
13454 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
13455 (plus:DI (match_dup 1)
13457 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13458 (clobber (match_scratch:DI 4 "=X,X,r,r"))]
13462 if (which_alternative != 0)
13464 else if (get_attr_length (insn) == 4)
13465 return \"bdz %l0\";
13467 return \"{bdn|bdnz} $+8\;b %l0\";
13469 [(set_attr "type" "branch")
13470 (set_attr "length" "*,12,16,24")])
13472 (define_insn "*ctrdi_internal6"
13474 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
13477 (label_ref (match_operand 0 "" ""))))
13478 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
13479 (plus:DI (match_dup 1)
13481 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13482 (clobber (match_scratch:DI 4 "=X,X,r,r"))]
13486 if (which_alternative != 0)
13488 else if (get_attr_length (insn) == 4)
13489 return \"{bdn|bdnz} %l0\";
13491 return \"bdz $+8\;b %l0\";
13493 [(set_attr "type" "branch")
13494 (set_attr "length" "*,12,16,24")])
13496 ;; Now the splitters if we could not allocate the CTR register
13500 (if_then_else (match_operator 2 "comparison_operator"
13501 [(match_operand:SI 1 "gpc_reg_operand" "")
13503 (match_operand 5 "" "")
13504 (match_operand 6 "" "")))
13505 (set (match_operand:SI 0 "gpc_reg_operand" "")
13506 (plus:SI (match_dup 1)
13508 (clobber (match_scratch:CC 3 ""))
13509 (clobber (match_scratch:SI 4 ""))]
13510 "! TARGET_POWERPC64 && reload_completed"
13511 [(parallel [(set (match_dup 3)
13512 (compare:CC (plus:SI (match_dup 1)
13516 (plus:SI (match_dup 1)
13518 (set (pc) (if_then_else (match_dup 7)
13522 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13527 (if_then_else (match_operator 2 "comparison_operator"
13528 [(match_operand:SI 1 "gpc_reg_operand" "")
13530 (match_operand 5 "" "")
13531 (match_operand 6 "" "")))
13532 (set (match_operand:SI 0 "nonimmediate_operand" "")
13533 (plus:SI (match_dup 1) (const_int -1)))
13534 (clobber (match_scratch:CC 3 ""))
13535 (clobber (match_scratch:SI 4 ""))]
13536 "! TARGET_POWERPC64 && reload_completed
13537 && ! gpc_reg_operand (operands[0], SImode)"
13538 [(parallel [(set (match_dup 3)
13539 (compare:CC (plus:SI (match_dup 1)
13543 (plus:SI (match_dup 1)
13547 (set (pc) (if_then_else (match_dup 7)
13551 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13555 (if_then_else (match_operator 2 "comparison_operator"
13556 [(match_operand:DI 1 "gpc_reg_operand" "")
13558 (match_operand 5 "" "")
13559 (match_operand 6 "" "")))
13560 (set (match_operand:DI 0 "gpc_reg_operand" "")
13561 (plus:DI (match_dup 1)
13563 (clobber (match_scratch:CC 3 ""))
13564 (clobber (match_scratch:DI 4 ""))]
13565 "TARGET_POWERPC64 && reload_completed && INT_REGNO_P (REGNO (operands[0]))"
13566 [(parallel [(set (match_dup 3)
13567 (compare:CC (plus:DI (match_dup 1)
13571 (plus:DI (match_dup 1)
13573 (set (pc) (if_then_else (match_dup 7)
13577 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13582 (if_then_else (match_operator 2 "comparison_operator"
13583 [(match_operand:DI 1 "gpc_reg_operand" "")
13585 (match_operand 5 "" "")
13586 (match_operand 6 "" "")))
13587 (set (match_operand:DI 0 "nonimmediate_operand" "")
13588 (plus:DI (match_dup 1) (const_int -1)))
13589 (clobber (match_scratch:CC 3 ""))
13590 (clobber (match_scratch:DI 4 ""))]
13591 "TARGET_POWERPC64 && reload_completed
13592 && ! gpc_reg_operand (operands[0], DImode)"
13593 [(parallel [(set (match_dup 3)
13594 (compare:CC (plus:DI (match_dup 1)
13598 (plus:DI (match_dup 1)
13602 (set (pc) (if_then_else (match_dup 7)
13606 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13611 (if_then_else (match_operator 2 "comparison_operator"
13612 [(match_operand:DI 1 "gpc_reg_operand" "")
13614 (match_operand 5 "" "")
13615 (match_operand 6 "" "")))
13616 (set (match_operand:DI 0 "gpc_reg_operand" "")
13617 (plus:DI (match_dup 1)
13619 (clobber (match_scratch:CC 3 ""))
13620 (clobber (match_scratch:DI 4 ""))]
13621 "TARGET_POWERPC64 && reload_completed && FP_REGNO_P (REGNO (operands[0]))"
13622 [(set (match_dup 8)
13626 (parallel [(set (match_dup 3)
13627 (compare:CC (plus:DI (match_dup 4)
13631 (plus:DI (match_dup 4)
13637 (set (pc) (if_then_else (match_dup 7)
13642 operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13644 operands[8] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
13648 (define_insn "trap"
13649 [(trap_if (const_int 1) (const_int 0))]
13653 (define_expand "conditional_trap"
13654 [(trap_if (match_operator 0 "trap_comparison_operator"
13655 [(match_dup 2) (match_dup 3)])
13656 (match_operand 1 "const_int_operand" ""))]
13658 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13659 operands[2] = rs6000_compare_op0;
13660 operands[3] = rs6000_compare_op1;")
13663 [(trap_if (match_operator 0 "trap_comparison_operator"
13664 [(match_operand:SI 1 "register_operand" "r")
13665 (match_operand:SI 2 "reg_or_short_operand" "rI")])
13668 "{t|tw}%V0%I2 %1,%2")
13671 [(trap_if (match_operator 0 "trap_comparison_operator"
13672 [(match_operand:DI 1 "register_operand" "r")
13673 (match_operand:DI 2 "reg_or_short_operand" "rI")])
13678 ;; Insns related to generating the function prologue and epilogue.
13680 (define_expand "prologue"
13681 [(use (const_int 0))]
13682 "TARGET_SCHED_PROLOG"
13685 rs6000_emit_prologue ();
13689 (define_insn "movesi_from_cr"
13690 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13691 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13692 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
13696 (define_insn "*stmw"
13697 [(match_parallel 0 "stmw_operation"
13698 [(set (match_operand:SI 1 "memory_operand" "=m")
13699 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13701 "{stm|stmw} %2,%1")
13703 (define_insn "*save_fpregs_si"
13704 [(match_parallel 0 "any_operand"
13705 [(clobber (match_operand:SI 1 "register_operand" "=l"))
13706 (use (match_operand:SI 2 "call_operand" "s"))
13707 (set (match_operand:DF 3 "memory_operand" "=m")
13708 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13712 (define_insn "*save_fpregs_di"
13713 [(match_parallel 0 "any_operand"
13714 [(clobber (match_operand:DI 1 "register_operand" "=l"))
13715 (use (match_operand:DI 2 "call_operand" "s"))
13716 (set (match_operand:DF 3 "memory_operand" "=m")
13717 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13721 ; These are to explain that changes to the stack pointer should
13722 ; not be moved over stores to stack memory.
13723 (define_insn "stack_tie"
13724 [(set (match_operand:BLK 0 "memory_operand" "+m")
13725 (unspec:BLK [(match_dup 0)] 5))]
13728 [(set_attr "length" "0")])
13731 (define_expand "epilogue"
13732 [(use (const_int 0))]
13733 "TARGET_SCHED_PROLOG"
13736 rs6000_emit_epilogue (FALSE);
13740 ; On some processors, doing the mtcrf one CC register at a time is
13741 ; faster (like on the 604e). On others, doing them all at once is
13742 ; faster; for instance, on the 601 and 750.
13744 (define_expand "movsi_to_cr_one"
13745 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13746 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13747 (match_dup 2)] 20))]
13749 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13751 (define_insn "*movsi_to_cr"
13752 [(match_parallel 0 "mtcrf_operation"
13753 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13754 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13755 (match_operand 3 "immediate_operand" "n")]
13762 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13763 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13764 operands[4] = GEN_INT (mask);
13765 return \"mtcrf %4,%2\";
13769 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13770 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13771 (match_operand 2 "immediate_operand" "n")] 20))]
13772 "GET_CODE (operands[0]) == REG
13773 && CR_REGNO_P (REGNO (operands[0]))
13774 && GET_CODE (operands[2]) == CONST_INT
13775 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13778 ; The load-multiple instructions have similar properties.
13779 ; Note that "load_multiple" is a name known to the machine-independent
13780 ; code that actually corresponds to the powerpc load-string.
13782 (define_insn "*lmw"
13783 [(match_parallel 0 "lmw_operation"
13784 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13785 (match_operand:SI 2 "memory_operand" "m"))])]
13789 (define_insn "*return_internal_si"
13791 (use (match_operand:SI 0 "register_operand" "lc"))]
13794 [(set_attr "type" "jmpreg")])
13796 (define_insn "*return_internal_di"
13798 (use (match_operand:DI 0 "register_operand" "lc"))]
13801 [(set_attr "type" "jmpreg")])
13803 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13804 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
13806 (define_insn "*return_and_restore_fpregs_si"
13807 [(match_parallel 0 "any_operand"
13809 (use (match_operand:SI 1 "register_operand" "l"))
13810 (use (match_operand:SI 2 "call_operand" "s"))
13811 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13812 (match_operand:DF 4 "memory_operand" "m"))])]
13816 (define_insn "*return_and_restore_fpregs_di"
13817 [(match_parallel 0 "any_operand"
13819 (use (match_operand:DI 1 "register_operand" "l"))
13820 (use (match_operand:DI 2 "call_operand" "s"))
13821 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13822 (match_operand:DF 4 "memory_operand" "m"))])]
13826 ; This is used in compiling the unwind routines.
13827 (define_expand "eh_return"
13828 [(use (match_operand 0 "general_operand" ""))
13829 (use (match_operand 1 "general_operand" ""))]
13834 rs6000_emit_eh_toc_restore (operands[0]);
13837 emit_insn (gen_eh_set_lr_si (operands[1]));
13839 emit_insn (gen_eh_set_lr_di (operands[1]));
13840 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
13844 ; We can't expand this before we know where the link register is stored.
13845 (define_insn "eh_set_lr_si"
13846 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
13847 (clobber (match_scratch:SI 1 "=&b"))]
13851 (define_insn "eh_set_lr_di"
13852 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
13853 (clobber (match_scratch:DI 1 "=&b"))]
13858 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
13859 (clobber (match_scratch 1 ""))]
13864 rs6000_stack_t *info = rs6000_stack_info ();
13866 if (info->lr_save_p)
13868 rtx frame_rtx = stack_pointer_rtx;
13872 if (frame_pointer_needed
13873 || current_function_calls_alloca
13874 || info->total_size > 32767)
13876 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13877 frame_rtx = operands[1];
13879 else if (info->push_p)
13880 sp_offset = info->total_size;
13882 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13883 tmp = gen_rtx_MEM (Pmode, tmp);
13884 emit_move_insn (tmp, operands[0]);
13887 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13891 (define_insn "prefetch"
13892 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
13893 (match_operand:SI 1 "const_int_operand" "n")
13894 (match_operand:SI 2 "const_int_operand" "n"))]
13898 if (GET_CODE (operands[0]) == REG)
13899 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13900 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13902 [(set_attr "type" "load")])
13904 ;; AltiVec patterns
13906 ;; Generic LVX load instruction.
13907 (define_insn "altivec_lvx_4si"
13908 [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
13909 (match_operand:V4SI 1 "memory_operand" "m"))]
13912 [(set_attr "type" "vecload")])
13914 (define_insn "altivec_lvx_8hi"
13915 [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
13916 (match_operand:V8HI 1 "memory_operand" "m"))]
13919 [(set_attr "type" "vecload")])
13921 (define_insn "altivec_lvx_16qi"
13922 [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
13923 (match_operand:V16QI 1 "memory_operand" "m"))]
13926 [(set_attr "type" "vecload")])
13928 (define_insn "altivec_lvx_4sf"
13929 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
13930 (match_operand:V4SF 1 "memory_operand" "m"))]
13933 [(set_attr "type" "vecload")])
13935 ;; Generic STVX store instruction.
13936 (define_insn "altivec_stvx_4si"
13937 [(set (match_operand:V4SI 0 "memory_operand" "=m")
13938 (match_operand:V4SI 1 "altivec_register_operand" "v"))]
13941 [(set_attr "type" "vecstore")])
13943 (define_insn "altivec_stvx_8hi"
13944 [(set (match_operand:V8HI 0 "memory_operand" "=m")
13945 (match_operand:V8HI 1 "altivec_register_operand" "v"))]
13948 [(set_attr "type" "vecstore")])
13950 (define_insn "altivec_stvx_16qi"
13951 [(set (match_operand:V16QI 0 "memory_operand" "=m")
13952 (match_operand:V16QI 1 "altivec_register_operand" "v"))]
13955 [(set_attr "type" "vecstore")])
13957 (define_insn "altivec_stvx_4sf"
13958 [(set (match_operand:V4SF 0 "memory_operand" "=m")
13959 (match_operand:V4SF 1 "altivec_register_operand" "v"))]
13962 [(set_attr "type" "vecstore")])
13964 ;; Vector move instructions.
13965 (define_expand "movv4si"
13966 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
13967 (match_operand:V4SI 1 "any_operand" ""))]
13969 "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
13971 (define_insn "*movv4si_internal"
13972 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r")
13973 (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))]
13979 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
13980 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
13981 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
13982 [(set_attr "type" "altivec")
13983 (set_attr "length" "*,*,*,16,16,16")])
13985 (define_expand "movv8hi"
13986 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
13987 (match_operand:V8HI 1 "any_operand" ""))]
13989 "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
13991 (define_insn "*movv8hi_internal1"
13992 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r")
13993 (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))]
13999 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
14000 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
14001 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
14002 [(set_attr "type" "altivec")
14003 (set_attr "length" "*,*,*,16,16,16")])
14005 (define_expand "movv16qi"
14006 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
14007 (match_operand:V16QI 1 "any_operand" ""))]
14009 "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
14011 (define_insn "*movv16qi_internal1"
14012 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r")
14013 (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))]
14019 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
14020 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
14021 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
14022 [(set_attr "type" "altivec")
14023 (set_attr "length" "*,*,*,16,16,16")])
14025 (define_expand "movv4sf"
14026 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
14027 (match_operand:V4SF 1 "any_operand" ""))]
14029 "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
14031 (define_insn "*movv4sf_internal1"
14032 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r")
14033 (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))]
14039 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0
14040 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1
14041 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1"
14042 [(set_attr "type" "altivec")
14043 (set_attr "length" "*,*,*,16,16,16")])
14045 (define_insn "get_vrsave_internal"
14046 [(set (match_operand:SI 0 "register_operand" "=r")
14047 (unspec:SI [(reg:SI 109)] 214))]
14052 return \"mfspr %0,256\";
14054 return \"mfvrsave %0\";
14056 [(set_attr "type" "altivec")])
14058 (define_insn "*set_vrsave_internal"
14059 [(match_parallel 0 "vrsave_operation"
14061 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
14062 (reg:SI 109)] 30))])]
14067 return \"mtspr 256,%1\";
14069 return \"mtvrsave %1\";
14071 [(set_attr "type" "altivec")])
14074 (define_insn "*movv4si_const0"
14075 [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
14076 (match_operand:V4SI 1 "zero_constant" ""))]
14079 [(set_attr "type" "vecsimple")])
14081 (define_insn "*movv4sf_const0"
14082 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
14083 (match_operand:V4SF 1 "zero_constant" ""))]
14087 [(set_attr "type" "vecsimple")])
14089 (define_insn "*movv8hi_const0"
14090 [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
14091 (match_operand:V8HI 1 "zero_constant" ""))]
14094 [(set_attr "type" "vecsimple")])
14096 (define_insn "*movv16qi_const0"
14097 [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
14098 (match_operand:V16QI 1 "zero_constant" ""))]
14101 [(set_attr "type" "vecsimple")])
14103 ;; Simple binary operations.
14105 (define_insn "addv16qi3"
14106 [(set (match_operand:V16QI 0 "register_operand" "=v")
14107 (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
14108 (match_operand:V16QI 2 "register_operand" "v")))]
14111 [(set_attr "type" "vecsimple")])
14113 (define_insn "addv8hi3"
14114 [(set (match_operand:V8HI 0 "register_operand" "=v")
14115 (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
14116 (match_operand:V8HI 2 "register_operand" "v")))]
14119 [(set_attr "type" "vecsimple")])
14121 (define_insn "addv4si3"
14122 [(set (match_operand:V4SI 0 "register_operand" "=v")
14123 (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
14124 (match_operand:V4SI 2 "register_operand" "v")))]
14127 [(set_attr "type" "vecsimple")])
14129 (define_insn "addv4sf3"
14130 [(set (match_operand:V4SF 0 "register_operand" "=v")
14131 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
14132 (match_operand:V4SF 2 "register_operand" "v")))]
14135 [(set_attr "type" "vecfloat")])
14137 (define_insn "altivec_vaddcuw"
14138 [(set (match_operand:V4SI 0 "register_operand" "=v")
14139 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14140 (match_operand:V4SI 2 "register_operand" "v")] 35))]
14143 [(set_attr "type" "vecsimple")])
14145 (define_insn "altivec_vaddubs"
14146 [(set (match_operand:V16QI 0 "register_operand" "=v")
14147 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14148 (match_operand:V16QI 2 "register_operand" "v")] 36))]
14151 [(set_attr "type" "vecsimple")])
14153 (define_insn "altivec_vaddsbs"
14154 [(set (match_operand:V16QI 0 "register_operand" "=v")
14155 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14156 (match_operand:V16QI 2 "register_operand" "v")] 37))]
14159 [(set_attr "type" "vecsimple")])
14161 (define_insn "altivec_vadduhs"
14162 [(set (match_operand:V8HI 0 "register_operand" "=v")
14163 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14164 (match_operand:V8HI 2 "register_operand" "v")] 38))]
14167 [(set_attr "type" "vecsimple")])
14169 (define_insn "altivec_vaddshs"
14170 [(set (match_operand:V8HI 0 "register_operand" "=v")
14171 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14172 (match_operand:V8HI 2 "register_operand" "v")] 39))]
14175 [(set_attr "type" "vecsimple")])
14177 (define_insn "altivec_vadduws"
14178 [(set (match_operand:V4SI 0 "register_operand" "=v")
14179 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14180 (match_operand:V4SI 2 "register_operand" "v")] 40))]
14183 [(set_attr "type" "vecsimple")])
14185 (define_insn "altivec_vaddsws"
14186 [(set (match_operand:V4SI 0 "register_operand" "=v")
14187 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14188 (match_operand:V4SI 2 "register_operand" "v")] 41))]
14191 [(set_attr "type" "vecsimple")])
14193 (define_insn "andv4si3"
14194 [(set (match_operand:V4SI 0 "register_operand" "=v")
14195 (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
14196 (match_operand:V4SI 2 "register_operand" "v")))]
14199 [(set_attr "type" "vecsimple")])
14201 (define_insn "altivec_vandc"
14202 [(set (match_operand:V4SI 0 "register_operand" "=v")
14203 (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
14204 (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
14207 [(set_attr "type" "vecsimple")])
14209 (define_insn "altivec_vavgub"
14210 [(set (match_operand:V16QI 0 "register_operand" "=v")
14211 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14212 (match_operand:V16QI 2 "register_operand" "v")] 44))]
14215 [(set_attr "type" "vecsimple")])
14217 (define_insn "altivec_vavgsb"
14218 [(set (match_operand:V16QI 0 "register_operand" "=v")
14219 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14220 (match_operand:V16QI 2 "register_operand" "v")] 45))]
14223 [(set_attr "type" "vecsimple")])
14225 (define_insn "altivec_vavguh"
14226 [(set (match_operand:V8HI 0 "register_operand" "=v")
14227 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14228 (match_operand:V8HI 2 "register_operand" "v")] 46))]
14231 [(set_attr "type" "vecsimple")])
14233 (define_insn "altivec_vavgsh"
14234 [(set (match_operand:V8HI 0 "register_operand" "=v")
14235 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14236 (match_operand:V8HI 2 "register_operand" "v")] 47))]
14239 [(set_attr "type" "vecsimple")])
14241 (define_insn "altivec_vavguw"
14242 [(set (match_operand:V4SI 0 "register_operand" "=v")
14243 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14244 (match_operand:V4SI 2 "register_operand" "v")] 48))]
14247 [(set_attr "type" "vecsimple")])
14249 (define_insn "altivec_vavgsw"
14250 [(set (match_operand:V4SI 0 "register_operand" "=v")
14251 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14252 (match_operand:V4SI 2 "register_operand" "v")] 49))]
14255 [(set_attr "type" "vecsimple")])
14257 (define_insn "altivec_vcmpbfp"
14258 [(set (match_operand:V4SI 0 "register_operand" "=v")
14259 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
14260 (match_operand:V4SF 2 "register_operand" "v")] 50))]
14263 [(set_attr "type" "veccmp")])
14265 (define_insn "altivec_vcmpequb"
14266 [(set (match_operand:V16QI 0 "register_operand" "=v")
14267 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14268 (match_operand:V16QI 2 "register_operand" "v")] 51))]
14270 "vcmpequb %0,%1,%2"
14271 [(set_attr "type" "vecsimple")])
14273 (define_insn "altivec_vcmpequh"
14274 [(set (match_operand:V8HI 0 "register_operand" "=v")
14275 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14276 (match_operand:V8HI 2 "register_operand" "v")] 52))]
14278 "vcmpequh %0,%1,%2"
14279 [(set_attr "type" "vecsimple")])
14281 (define_insn "altivec_vcmpequw"
14282 [(set (match_operand:V4SI 0 "register_operand" "=v")
14283 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14284 (match_operand:V4SI 2 "register_operand" "v")] 53))]
14286 "vcmpequw %0,%1,%2"
14287 [(set_attr "type" "vecsimple")])
14289 (define_insn "altivec_vcmpeqfp"
14290 [(set (match_operand:V4SI 0 "register_operand" "=v")
14291 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
14292 (match_operand:V4SF 2 "register_operand" "v")] 54))]
14294 "vcmpeqfp %0,%1,%2"
14295 [(set_attr "type" "veccmp")])
14297 (define_insn "altivec_vcmpgefp"
14298 [(set (match_operand:V4SI 0 "register_operand" "=v")
14299 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
14300 (match_operand:V4SF 2 "register_operand" "v")] 55))]
14302 "vcmpgefp %0,%1,%2"
14303 [(set_attr "type" "veccmp")])
14305 (define_insn "altivec_vcmpgtub"
14306 [(set (match_operand:V16QI 0 "register_operand" "=v")
14307 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14308 (match_operand:V16QI 2 "register_operand" "v")] 56))]
14310 "vcmpgtub %0,%1,%2"
14311 [(set_attr "type" "vecsimple")])
14313 (define_insn "altivec_vcmpgtsb"
14314 [(set (match_operand:V16QI 0 "register_operand" "=v")
14315 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14316 (match_operand:V16QI 2 "register_operand" "v")] 57))]
14318 "vcmpgtsb %0,%1,%2"
14319 [(set_attr "type" "vecsimple")])
14321 (define_insn "altivec_vcmpgtuh"
14322 [(set (match_operand:V8HI 0 "register_operand" "=v")
14323 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14324 (match_operand:V8HI 2 "register_operand" "v")] 58))]
14326 "vcmpgtuh %0,%1,%2"
14327 [(set_attr "type" "vecsimple")])
14329 (define_insn "altivec_vcmpgtsh"
14330 [(set (match_operand:V8HI 0 "register_operand" "=v")
14331 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14332 (match_operand:V8HI 2 "register_operand" "v")] 59))]
14334 "vcmpgtsh %0,%1,%2"
14335 [(set_attr "type" "vecsimple")])
14337 (define_insn "altivec_vcmpgtuw"
14338 [(set (match_operand:V4SI 0 "register_operand" "=v")
14339 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14340 (match_operand:V4SI 2 "register_operand" "v")] 60))]
14342 "vcmpgtuw %0,%1,%2"
14343 [(set_attr "type" "vecsimple")])
14345 (define_insn "altivec_vcmpgtsw"
14346 [(set (match_operand:V4SI 0 "register_operand" "=v")
14347 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14348 (match_operand:V4SI 2 "register_operand" "v")] 61))]
14350 "vcmpgtsw %0,%1,%2"
14351 [(set_attr "type" "vecsimple")])
14353 (define_insn "altivec_vcmpgtfp"
14354 [(set (match_operand:V4SI 0 "register_operand" "=v")
14355 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
14356 (match_operand:V4SF 2 "register_operand" "v")] 62))]
14358 "vcmpgtfp %0,%1,%2"
14359 [(set_attr "type" "veccmp")])
14361 ;; Fused multiply add
14362 (define_insn "altivec_vmaddfp"
14363 [(set (match_operand:V4SF 0 "register_operand" "=v")
14364 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
14365 (match_operand:V4SF 2 "register_operand" "v"))
14366 (match_operand:V4SF 3 "register_operand" "v")))]
14368 "vmaddfp %0,%1,%2,%3"
14369 [(set_attr "type" "vecfloat")])
14371 ;; The unspec here is a vec splat of 0. We do multiply as a fused
14372 ;; multiply-add with an add of a 0 vector.
14374 (define_expand "mulv4sf3"
14375 [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142))
14376 (set (match_operand:V4SF 0 "register_operand" "=v")
14377 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
14378 (match_operand:V4SF 2 "register_operand" "v"))
14380 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
14382 { operands[3] = gen_reg_rtx (V4SFmode); }")
14384 ;; Fused multiply subtract
14385 (define_insn "altivec_vnmsubfp"
14386 [(set (match_operand:V4SF 0 "register_operand" "=v")
14387 (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
14388 (match_operand:V4SF 2 "register_operand" "v"))
14389 (match_operand:V4SF 3 "register_operand" "v")))]
14391 "vnmsubfp %0,%1,%2,%3"
14392 [(set_attr "type" "vecfloat")])
14395 (define_insn "altivec_vmsumubm"
14396 [(set (match_operand:V4SI 0 "register_operand" "=v")
14397 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
14398 (match_operand:V16QI 2 "register_operand" "v")
14399 (match_operand:V4SI 3 "register_operand" "v")] 65))]
14401 "vmsumubm %0, %1, %2, %3"
14402 [(set_attr "type" "veccomplex")])
14404 (define_insn "altivec_vmsummbm"
14405 [(set (match_operand:V4SI 0 "register_operand" "=v")
14406 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
14407 (match_operand:V16QI 2 "register_operand" "v")
14408 (match_operand:V4SI 3 "register_operand" "v")] 66))]
14410 "vmsumubm %0, %1, %2, %3"
14411 [(set_attr "type" "veccomplex")])
14413 (define_insn "altivec_vmsumuhm"
14414 [(set (match_operand:V4SI 0 "register_operand" "=v")
14415 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14416 (match_operand:V8HI 2 "register_operand" "v")
14417 (match_operand:V4SI 3 "register_operand" "v")] 67))]
14419 "vmsumuhm %0, %1, %2, %3"
14420 [(set_attr "type" "veccomplex")])
14422 (define_insn "altivec_vmsumshm"
14423 [(set (match_operand:V4SI 0 "register_operand" "=v")
14424 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14425 (match_operand:V8HI 2 "register_operand" "v")
14426 (match_operand:V4SI 3 "register_operand" "v")] 68))]
14428 "vmsumshm %0, %1, %2, %3"
14429 [(set_attr "type" "veccomplex")])
14431 (define_insn "altivec_vmsumuhs"
14432 [(set (match_operand:V4SI 0 "register_operand" "=v")
14433 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14434 (match_operand:V8HI 2 "register_operand" "v")
14435 (match_operand:V4SI 3 "register_operand" "v")] 69))]
14437 "vmsumuhs %0, %1, %2, %3"
14438 [(set_attr "type" "veccomplex")])
14440 (define_insn "altivec_vmsumshs"
14441 [(set (match_operand:V4SI 0 "register_operand" "=v")
14442 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14443 (match_operand:V8HI 2 "register_operand" "v")
14444 (match_operand:V4SI 3 "register_operand" "v")] 70))]
14446 "vmsumshs %0, %1, %2, %3"
14447 [(set_attr "type" "veccomplex")])
14449 (define_insn "umaxv16qi3"
14450 [(set (match_operand:V16QI 0 "register_operand" "=v")
14451 (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
14452 (match_operand:V16QI 2 "register_operand" "v")))]
14455 [(set_attr "type" "vecsimple")])
14457 (define_insn "smaxv16qi3"
14458 [(set (match_operand:V16QI 0 "register_operand" "=v")
14459 (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
14460 (match_operand:V16QI 2 "register_operand" "v")))]
14463 [(set_attr "type" "vecsimple")])
14465 (define_insn "umaxv8hi3"
14466 [(set (match_operand:V8HI 0 "register_operand" "=v")
14467 (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
14468 (match_operand:V8HI 2 "register_operand" "v")))]
14471 [(set_attr "type" "vecsimple")])
14473 (define_insn "smaxv8hi3"
14474 [(set (match_operand:V8HI 0 "register_operand" "=v")
14475 (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
14476 (match_operand:V8HI 2 "register_operand" "v")))]
14479 [(set_attr "type" "vecsimple")])
14481 (define_insn "umaxv4si3"
14482 [(set (match_operand:V4SI 0 "register_operand" "=v")
14483 (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
14484 (match_operand:V4SI 2 "register_operand" "v")))]
14487 [(set_attr "type" "vecsimple")])
14489 (define_insn "smaxv4si3"
14490 [(set (match_operand:V4SI 0 "register_operand" "=v")
14491 (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
14492 (match_operand:V4SI 2 "register_operand" "v")))]
14495 [(set_attr "type" "vecsimple")])
14497 (define_insn "smaxv4sf3"
14498 [(set (match_operand:V4SF 0 "register_operand" "=v")
14499 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
14500 (match_operand:V4SF 2 "register_operand" "v")))]
14503 [(set_attr "type" "veccmp")])
14505 (define_insn "altivec_vmhaddshs"
14506 [(set (match_operand:V8HI 0 "register_operand" "=v")
14507 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14508 (match_operand:V8HI 2 "register_operand" "v")
14509 (match_operand:V8HI 3 "register_operand" "v")] 71))]
14511 "vmhaddshs %0, %1, %2, %3"
14512 [(set_attr "type" "veccomplex")])
14513 (define_insn "altivec_vmhraddshs"
14514 [(set (match_operand:V8HI 0 "register_operand" "=v")
14515 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14516 (match_operand:V8HI 2 "register_operand" "v")
14517 (match_operand:V8HI 3 "register_operand" "v")] 72))]
14519 "vmhraddshs %0, %1, %2, %3"
14520 [(set_attr "type" "veccomplex")])
14521 (define_insn "altivec_vmladduhm"
14522 [(set (match_operand:V8HI 0 "register_operand" "=v")
14523 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14524 (match_operand:V8HI 2 "register_operand" "v")
14525 (match_operand:V8HI 3 "register_operand" "v")] 73))]
14527 "vmladduhm %0, %1, %2, %3"
14528 [(set_attr "type" "veccomplex")])
14530 (define_insn "altivec_vmrghb"
14531 [(set (match_operand:V16QI 0 "register_operand" "=v")
14532 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
14533 (parallel [(const_int 8)
14549 (match_operand:V16QI 2 "register_operand" "v")
14553 [(set_attr "type" "vecperm")])
14555 (define_insn "altivec_vmrghh"
14556 [(set (match_operand:V8HI 0 "register_operand" "=v")
14557 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
14558 (parallel [(const_int 4)
14566 (match_operand:V8HI 2 "register_operand" "v")
14570 [(set_attr "type" "vecperm")])
14572 (define_insn "altivec_vmrghw"
14573 [(set (match_operand:V4SI 0 "register_operand" "=v")
14574 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
14575 (parallel [(const_int 2)
14579 (match_operand:V4SI 2 "register_operand" "v")
14583 [(set_attr "type" "vecperm")])
14585 (define_insn "altivec_vmrglb"
14586 [(set (match_operand:V16QI 0 "register_operand" "=v")
14587 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
14589 (parallel [(const_int 0)
14605 (match_operand:V16QI 1 "register_operand" "v")
14609 [(set_attr "type" "vecperm")])
14611 (define_insn "altivec_vmrglh"
14612 [(set (match_operand:V8HI 0 "register_operand" "=v")
14613 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
14614 (parallel [(const_int 0)
14622 (match_operand:V8HI 1 "register_operand" "v")
14626 [(set_attr "type" "vecperm")])
14628 (define_insn "altivec_vmrglw"
14629 [(set (match_operand:V4SI 0 "register_operand" "=v")
14630 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
14631 (parallel [(const_int 0)
14635 (match_operand:V4SI 1 "register_operand" "v")
14639 [(set_attr "type" "vecperm")])
14641 (define_insn "uminv16qi3"
14642 [(set (match_operand:V16QI 0 "register_operand" "=v")
14643 (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
14644 (match_operand:V16QI 2 "register_operand" "v")))]
14647 [(set_attr "type" "vecsimple")])
14649 (define_insn "sminv16qi3"
14650 [(set (match_operand:V16QI 0 "register_operand" "=v")
14651 (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
14652 (match_operand:V16QI 2 "register_operand" "v")))]
14655 [(set_attr "type" "vecsimple")])
14657 (define_insn "uminv8hi3"
14658 [(set (match_operand:V8HI 0 "register_operand" "=v")
14659 (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
14660 (match_operand:V8HI 2 "register_operand" "v")))]
14663 [(set_attr "type" "vecsimple")])
14665 (define_insn "sminv8hi3"
14666 [(set (match_operand:V8HI 0 "register_operand" "=v")
14667 (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
14668 (match_operand:V8HI 2 "register_operand" "v")))]
14671 [(set_attr "type" "vecsimple")])
14673 (define_insn "uminv4si3"
14674 [(set (match_operand:V4SI 0 "register_operand" "=v")
14675 (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
14676 (match_operand:V4SI 2 "register_operand" "v")))]
14679 [(set_attr "type" "vecsimple")])
14681 (define_insn "sminv4si3"
14682 [(set (match_operand:V4SI 0 "register_operand" "=v")
14683 (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
14684 (match_operand:V4SI 2 "register_operand" "v")))]
14687 [(set_attr "type" "vecsimple")])
14689 (define_insn "sminv4sf3"
14690 [(set (match_operand:V4SF 0 "register_operand" "=v")
14691 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
14692 (match_operand:V4SF 2 "register_operand" "v")))]
14695 [(set_attr "type" "veccmp")])
14697 (define_insn "altivec_vmuleub"
14698 [(set (match_operand:V8HI 0 "register_operand" "=v")
14699 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
14700 (match_operand:V16QI 2 "register_operand" "v")] 83))]
14703 [(set_attr "type" "veccomplex")])
14705 (define_insn "altivec_vmulesb"
14706 [(set (match_operand:V8HI 0 "register_operand" "=v")
14707 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
14708 (match_operand:V16QI 2 "register_operand" "v")] 84))]
14711 [(set_attr "type" "veccomplex")])
14713 (define_insn "altivec_vmuleuh"
14714 [(set (match_operand:V4SI 0 "register_operand" "=v")
14715 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14716 (match_operand:V8HI 2 "register_operand" "v")] 85))]
14719 [(set_attr "type" "veccomplex")])
14721 (define_insn "altivec_vmulesh"
14722 [(set (match_operand:V4SI 0 "register_operand" "=v")
14723 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14724 (match_operand:V8HI 2 "register_operand" "v")] 86))]
14727 [(set_attr "type" "veccomplex")])
14729 (define_insn "altivec_vmuloub"
14730 [(set (match_operand:V8HI 0 "register_operand" "=v")
14731 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
14732 (match_operand:V16QI 2 "register_operand" "v")] 87))]
14735 [(set_attr "type" "veccomplex")])
14737 (define_insn "altivec_vmulosb"
14738 [(set (match_operand:V8HI 0 "register_operand" "=v")
14739 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
14740 (match_operand:V16QI 2 "register_operand" "v")] 88))]
14743 [(set_attr "type" "veccomplex")])
14745 (define_insn "altivec_vmulouh"
14746 [(set (match_operand:V4SI 0 "register_operand" "=v")
14747 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14748 (match_operand:V8HI 2 "register_operand" "v")] 89))]
14751 [(set_attr "type" "veccomplex")])
14753 (define_insn "altivec_vmulosh"
14754 [(set (match_operand:V4SI 0 "register_operand" "=v")
14755 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
14756 (match_operand:V8HI 2 "register_operand" "v")] 90))]
14759 [(set_attr "type" "veccomplex")])
14761 (define_insn "altivec_vnor"
14762 [(set (match_operand:V4SI 0 "register_operand" "=v")
14763 (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
14764 (match_operand:V4SI 2 "register_operand" "v"))))]
14767 [(set_attr "type" "vecsimple")])
14769 (define_insn "iorv4si3"
14770 [(set (match_operand:V4SI 0 "register_operand" "=v")
14771 (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
14772 (match_operand:V4SI 2 "register_operand" "v")))]
14775 [(set_attr "type" "vecsimple")])
14777 (define_insn "altivec_vpkuhum"
14778 [(set (match_operand:V16QI 0 "register_operand" "=v")
14779 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
14780 (match_operand:V8HI 2 "register_operand" "v")] 93))]
14783 [(set_attr "type" "vecperm")])
14785 (define_insn "altivec_vpkuwum"
14786 [(set (match_operand:V8HI 0 "register_operand" "=v")
14787 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
14788 (match_operand:V4SI 2 "register_operand" "v")] 94))]
14791 [(set_attr "type" "vecperm")])
14793 (define_insn "altivec_vpkpx"
14794 [(set (match_operand:V8HI 0 "register_operand" "=v")
14795 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
14796 (match_operand:V4SI 2 "register_operand" "v")] 95))]
14799 [(set_attr "type" "vecperm")])
14801 (define_insn "altivec_vpkuhss"
14802 [(set (match_operand:V16QI 0 "register_operand" "=v")
14803 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
14804 (match_operand:V8HI 2 "register_operand" "v")] 96))]
14807 [(set_attr "type" "vecperm")])
14809 (define_insn "altivec_vpkshss"
14810 [(set (match_operand:V16QI 0 "register_operand" "=v")
14811 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
14812 (match_operand:V8HI 2 "register_operand" "v")] 97))]
14815 [(set_attr "type" "vecperm")])
14817 (define_insn "altivec_vpkuwss"
14818 [(set (match_operand:V8HI 0 "register_operand" "=v")
14819 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
14820 (match_operand:V4SI 2 "register_operand" "v")] 98))]
14823 [(set_attr "type" "vecperm")])
14825 (define_insn "altivec_vpkswss"
14826 [(set (match_operand:V8HI 0 "register_operand" "=v")
14827 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
14828 (match_operand:V4SI 2 "register_operand" "v")] 99))]
14831 [(set_attr "type" "vecperm")])
14833 (define_insn "altivec_vpkuhus"
14834 [(set (match_operand:V16QI 0 "register_operand" "=v")
14835 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
14836 (match_operand:V8HI 2 "register_operand" "v")] 100))]
14839 [(set_attr "type" "vecperm")])
14841 (define_insn "altivec_vpkshus"
14842 [(set (match_operand:V16QI 0 "register_operand" "=v")
14843 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
14844 (match_operand:V8HI 2 "register_operand" "v")] 101))]
14847 [(set_attr "type" "vecperm")])
14849 (define_insn "altivec_vpkuwus"
14850 [(set (match_operand:V8HI 0 "register_operand" "=v")
14851 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
14852 (match_operand:V4SI 2 "register_operand" "v")] 102))]
14855 [(set_attr "type" "vecperm")])
14857 (define_insn "altivec_vpkswus"
14858 [(set (match_operand:V8HI 0 "register_operand" "=v")
14859 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
14860 (match_operand:V4SI 2 "register_operand" "v")] 103))]
14863 [(set_attr "type" "vecperm")])
14865 (define_insn "altivec_vrlb"
14866 [(set (match_operand:V16QI 0 "register_operand" "=v")
14867 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14868 (match_operand:V16QI 2 "register_operand" "v")] 104))]
14871 [(set_attr "type" "vecsimple")])
14873 (define_insn "altivec_vrlh"
14874 [(set (match_operand:V8HI 0 "register_operand" "=v")
14875 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14876 (match_operand:V8HI 2 "register_operand" "v")] 105))]
14879 [(set_attr "type" "vecsimple")])
14881 (define_insn "altivec_vrlw"
14882 [(set (match_operand:V4SI 0 "register_operand" "=v")
14883 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14884 (match_operand:V4SI 2 "register_operand" "v")] 106))]
14887 [(set_attr "type" "vecsimple")])
14889 (define_insn "altivec_vslb"
14890 [(set (match_operand:V16QI 0 "register_operand" "=v")
14891 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14892 (match_operand:V16QI 2 "register_operand" "v")] 107))]
14895 [(set_attr "type" "vecsimple")])
14897 (define_insn "altivec_vslh"
14898 [(set (match_operand:V8HI 0 "register_operand" "=v")
14899 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14900 (match_operand:V8HI 2 "register_operand" "v")] 108))]
14903 [(set_attr "type" "vecsimple")])
14905 (define_insn "altivec_vslw"
14906 [(set (match_operand:V4SI 0 "register_operand" "=v")
14907 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14908 (match_operand:V4SI 2 "register_operand" "v")] 109))]
14911 [(set_attr "type" "vecsimple")])
14913 (define_insn "altivec_vsl"
14914 [(set (match_operand:V4SI 0 "register_operand" "=v")
14915 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14916 (match_operand:V4SI 2 "register_operand" "v")] 110))]
14919 [(set_attr "type" "vecperm")])
14921 (define_insn "altivec_vslo"
14922 [(set (match_operand:V4SI 0 "register_operand" "=v")
14923 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14924 (match_operand:V4SI 2 "register_operand" "v")] 111))]
14927 [(set_attr "type" "vecperm")])
14929 (define_insn "altivec_vsrb"
14930 [(set (match_operand:V16QI 0 "register_operand" "=v")
14931 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14932 (match_operand:V16QI 2 "register_operand" "v")] 112))]
14935 [(set_attr "type" "vecsimple")])
14937 (define_insn "altivec_vsrh"
14938 [(set (match_operand:V8HI 0 "register_operand" "=v")
14939 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14940 (match_operand:V8HI 2 "register_operand" "v")] 113))]
14943 [(set_attr "type" "vecsimple")])
14945 (define_insn "altivec_vsrw"
14946 [(set (match_operand:V4SI 0 "register_operand" "=v")
14947 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14948 (match_operand:V4SI 2 "register_operand" "v")] 114))]
14951 [(set_attr "type" "vecsimple")])
14953 (define_insn "altivec_vsrab"
14954 [(set (match_operand:V16QI 0 "register_operand" "=v")
14955 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
14956 (match_operand:V16QI 2 "register_operand" "v")] 115))]
14959 [(set_attr "type" "vecsimple")])
14961 (define_insn "altivec_vsrah"
14962 [(set (match_operand:V8HI 0 "register_operand" "=v")
14963 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
14964 (match_operand:V8HI 2 "register_operand" "v")] 116))]
14967 [(set_attr "type" "vecsimple")])
14969 (define_insn "altivec_vsraw"
14970 [(set (match_operand:V4SI 0 "register_operand" "=v")
14971 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14972 (match_operand:V4SI 2 "register_operand" "v")] 117))]
14975 [(set_attr "type" "vecsimple")])
14977 (define_insn "altivec_vsr"
14978 [(set (match_operand:V4SI 0 "register_operand" "=v")
14979 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14980 (match_operand:V4SI 2 "register_operand" "v")] 118))]
14983 [(set_attr "type" "vecperm")])
14985 (define_insn "altivec_vsro"
14986 [(set (match_operand:V4SI 0 "register_operand" "=v")
14987 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
14988 (match_operand:V4SI 2 "register_operand" "v")] 119))]
14991 [(set_attr "type" "vecperm")])
14993 (define_insn "subv16qi3"
14994 [(set (match_operand:V16QI 0 "register_operand" "=v")
14995 (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
14996 (match_operand:V16QI 2 "register_operand" "v")))]
14999 [(set_attr "type" "vecsimple")])
15001 (define_insn "subv8hi3"
15002 [(set (match_operand:V8HI 0 "register_operand" "=v")
15003 (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
15004 (match_operand:V8HI 2 "register_operand" "v")))]
15007 [(set_attr "type" "vecsimple")])
15009 (define_insn "subv4si3"
15010 [(set (match_operand:V4SI 0 "register_operand" "=v")
15011 (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
15012 (match_operand:V4SI 2 "register_operand" "v")))]
15015 [(set_attr "type" "vecsimple")])
15017 (define_insn "subv4sf3"
15018 [(set (match_operand:V4SF 0 "register_operand" "=v")
15019 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
15020 (match_operand:V4SF 2 "register_operand" "v")))]
15023 [(set_attr "type" "vecfloat")])
15025 (define_insn "altivec_vsubcuw"
15026 [(set (match_operand:V4SI 0 "register_operand" "=v")
15027 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15028 (match_operand:V4SI 2 "register_operand" "v")] 124))]
15031 [(set_attr "type" "vecsimple")])
15033 (define_insn "altivec_vsububs"
15034 [(set (match_operand:V16QI 0 "register_operand" "=v")
15035 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
15036 (match_operand:V16QI 2 "register_operand" "v")] 125))]
15039 [(set_attr "type" "vecsimple")])
15041 (define_insn "altivec_vsubsbs"
15042 [(set (match_operand:V16QI 0 "register_operand" "=v")
15043 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
15044 (match_operand:V16QI 2 "register_operand" "v")] 126))]
15047 [(set_attr "type" "vecsimple")])
15049 (define_insn "altivec_vsubuhs"
15050 [(set (match_operand:V8HI 0 "register_operand" "=v")
15051 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
15052 (match_operand:V8HI 2 "register_operand" "v")] 127))]
15055 [(set_attr "type" "vecsimple")])
15057 (define_insn "altivec_vsubshs"
15058 [(set (match_operand:V8HI 0 "register_operand" "=v")
15059 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
15060 (match_operand:V8HI 2 "register_operand" "v")] 128))]
15063 [(set_attr "type" "vecsimple")])
15065 (define_insn "altivec_vsubuws"
15066 [(set (match_operand:V4SI 0 "register_operand" "=v")
15067 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15068 (match_operand:V4SI 2 "register_operand" "v")] 129))]
15071 [(set_attr "type" "vecsimple")])
15073 (define_insn "altivec_vsubsws"
15074 [(set (match_operand:V4SI 0 "register_operand" "=v")
15075 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15076 (match_operand:V4SI 2 "register_operand" "v")] 130))]
15079 [(set_attr "type" "vecsimple")])
15081 (define_insn "altivec_vsum4ubs"
15082 [(set (match_operand:V4SI 0 "register_operand" "=v")
15083 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
15084 (match_operand:V4SI 2 "register_operand" "v")] 131))]
15086 "vsum4ubs %0,%1,%2"
15087 [(set_attr "type" "veccomplex")])
15089 (define_insn "altivec_vsum4sbs"
15090 [(set (match_operand:V4SI 0 "register_operand" "=v")
15091 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
15092 (match_operand:V4SI 2 "register_operand" "v")] 132))]
15094 "vsum4sbs %0,%1,%2"
15095 [(set_attr "type" "veccomplex")])
15097 (define_insn "altivec_vsum4shs"
15098 [(set (match_operand:V4SI 0 "register_operand" "=v")
15099 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
15100 (match_operand:V4SI 2 "register_operand" "v")] 133))]
15102 "vsum4shs %0,%1,%2"
15103 [(set_attr "type" "veccomplex")])
15105 (define_insn "altivec_vsum2sws"
15106 [(set (match_operand:V4SI 0 "register_operand" "=v")
15107 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15108 (match_operand:V4SI 2 "register_operand" "v")] 134))]
15110 "vsum2sws %0,%1,%2"
15111 [(set_attr "type" "veccomplex")])
15113 (define_insn "altivec_vsumsws"
15114 [(set (match_operand:V4SI 0 "register_operand" "=v")
15115 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15116 (match_operand:V4SI 2 "register_operand" "v")] 135))]
15119 [(set_attr "type" "veccomplex")])
15121 (define_insn "xorv4si3"
15122 [(set (match_operand:V4SI 0 "register_operand" "=v")
15123 (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
15124 (match_operand:V4SI 2 "register_operand" "v")))]
15127 [(set_attr "type" "vecsimple")])
15129 (define_insn "altivec_vspltb"
15130 [(set (match_operand:V16QI 0 "register_operand" "=v")
15131 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
15132 (match_operand:QI 2 "immediate_operand" "i")] 136))]
15135 [(set_attr "type" "vecperm")])
15137 (define_insn "altivec_vsplth"
15138 [(set (match_operand:V8HI 0 "register_operand" "=v")
15139 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
15140 (match_operand:QI 2 "immediate_operand" "i")] 137))]
15143 [(set_attr "type" "vecperm")])
15145 (define_insn "altivec_vspltw"
15146 [(set (match_operand:V4SI 0 "register_operand" "=v")
15147 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15148 (match_operand:QI 2 "immediate_operand" "i")] 138))]
15151 [(set_attr "type" "vecperm")])
15153 (define_insn "altivec_vspltisb"
15154 [(set (match_operand:V16QI 0 "register_operand" "=v")
15155 (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))]
15158 [(set_attr "type" "vecsimple")])
15161 (define_insn "altivec_vspltish"
15162 [(set (match_operand:V8HI 0 "register_operand" "=v")
15163 (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))]
15166 [(set_attr "type" "vecsimple")])
15168 (define_insn "altivec_vspltisw"
15169 [(set (match_operand:V4SI 0 "register_operand" "=v")
15170 (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))]
15173 [(set_attr "type" "vecsimple")])
15176 [(set (match_operand:V4SF 0 "register_operand" "=v")
15177 (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
15180 [(set_attr "type" "vecsimple")])
15182 (define_insn "ftruncv4sf2"
15183 [(set (match_operand:V4SF 0 "register_operand" "=v")
15184 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
15187 [(set_attr "type" "vecfloat")])
15189 (define_insn "altivec_vperm_4si"
15190 [(set (match_operand:V4SI 0 "register_operand" "=v")
15191 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15192 (match_operand:V4SI 2 "register_operand" "v")
15193 (match_operand:V16QI 3 "register_operand" "v")] 144))]
15195 "vperm %0,%1,%2,%3"
15196 [(set_attr "type" "vecperm")])
15198 (define_insn "altivec_vperm_4sf"
15199 [(set (match_operand:V4SF 0 "register_operand" "=v")
15200 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
15201 (match_operand:V4SF 2 "register_operand" "v")
15202 (match_operand:V16QI 3 "register_operand" "v")] 145))]
15204 "vperm %0,%1,%2,%3"
15205 [(set_attr "type" "vecperm")])
15207 (define_insn "altivec_vperm_8hi"
15208 [(set (match_operand:V8HI 0 "register_operand" "=v")
15209 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
15210 (match_operand:V8HI 2 "register_operand" "v")
15211 (match_operand:V16QI 3 "register_operand" "v")] 146))]
15213 "vperm %0,%1,%2,%3"
15214 [(set_attr "type" "vecperm")])
15216 (define_insn "altivec_vperm_16qi"
15217 [(set (match_operand:V16QI 0 "register_operand" "=v")
15218 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
15219 (match_operand:V16QI 2 "register_operand" "v")
15220 (match_operand:V16QI 3 "register_operand" "v")] 147))]
15222 "vperm %0,%1,%2,%3"
15223 [(set_attr "type" "vecperm")])
15225 (define_insn "altivec_vrfip"
15226 [(set (match_operand:V4SF 0 "register_operand" "=v")
15227 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
15230 [(set_attr "type" "vecfloat")])
15232 (define_insn "altivec_vrfin"
15233 [(set (match_operand:V4SF 0 "register_operand" "=v")
15234 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
15237 [(set_attr "type" "vecfloat")])
15239 (define_insn "altivec_vrfim"
15240 [(set (match_operand:V4SF 0 "register_operand" "=v")
15241 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
15244 [(set_attr "type" "vecfloat")])
15246 (define_insn "altivec_vcfux"
15247 [(set (match_operand:V4SF 0 "register_operand" "=v")
15248 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
15249 (match_operand:QI 2 "immediate_operand" "i")] 151))]
15252 [(set_attr "type" "vecfloat")])
15254 (define_insn "altivec_vcfsx"
15255 [(set (match_operand:V4SF 0 "register_operand" "=v")
15256 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
15257 (match_operand:QI 2 "immediate_operand" "i")] 152))]
15260 [(set_attr "type" "vecfloat")])
15262 (define_insn "altivec_vctuxs"
15263 [(set (match_operand:V4SI 0 "register_operand" "=v")
15264 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
15265 (match_operand:QI 2 "immediate_operand" "i")] 153))]
15267 "vctuxs %0, %1, %2"
15268 [(set_attr "type" "vecfloat")])
15270 (define_insn "altivec_vctsxs"
15271 [(set (match_operand:V4SI 0 "register_operand" "=v")
15272 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
15273 (match_operand:QI 2 "immediate_operand" "i")] 154))]
15275 "vctsxs %0, %1, %2"
15276 [(set_attr "type" "vecfloat")])
15278 (define_insn "altivec_vlogefp"
15279 [(set (match_operand:V4SF 0 "register_operand" "=v")
15280 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
15283 [(set_attr "type" "vecfloat")])
15285 (define_insn "altivec_vexptefp"
15286 [(set (match_operand:V4SF 0 "register_operand" "=v")
15287 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
15290 [(set_attr "type" "vecfloat")])
15292 (define_insn "altivec_vrsqrtefp"
15293 [(set (match_operand:V4SF 0 "register_operand" "=v")
15294 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
15297 [(set_attr "type" "vecfloat")])
15299 (define_insn "altivec_vrefp"
15300 [(set (match_operand:V4SF 0 "register_operand" "=v")
15301 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
15304 [(set_attr "type" "vecfloat")])
15306 (define_insn "altivec_vsel_4si"
15307 [(set (match_operand:V4SI 0 "register_operand" "=v")
15308 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15309 (match_operand:V4SI 2 "register_operand" "v")
15310 (match_operand:V4SI 3 "register_operand" "v")] 159))]
15313 [(set_attr "type" "vecperm")])
15315 (define_insn "altivec_vsel_4sf"
15316 [(set (match_operand:V4SF 0 "register_operand" "=v")
15317 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
15318 (match_operand:V4SF 2 "register_operand" "v")
15319 (match_operand:V4SI 3 "register_operand" "v")] 160))]
15322 [(set_attr "type" "vecperm")])
15324 (define_insn "altivec_vsel_8hi"
15325 [(set (match_operand:V8HI 0 "register_operand" "=v")
15326 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
15327 (match_operand:V8HI 2 "register_operand" "v")
15328 (match_operand:V8HI 3 "register_operand" "v")] 161))]
15331 [(set_attr "type" "vecperm")])
15333 (define_insn "altivec_vsel_16qi"
15334 [(set (match_operand:V16QI 0 "register_operand" "=v")
15335 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
15336 (match_operand:V16QI 2 "register_operand" "v")
15337 (match_operand:V16QI 3 "register_operand" "v")] 162))]
15340 [(set_attr "type" "vecperm")])
15342 (define_insn "altivec_vsldoi_4si"
15343 [(set (match_operand:V4SI 0 "register_operand" "=v")
15344 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
15345 (match_operand:V4SI 2 "register_operand" "v")
15346 (match_operand:QI 3 "immediate_operand" "i")] 163))]
15348 "vsldoi %0, %1, %2, %3"
15349 [(set_attr "type" "vecperm")])
15351 (define_insn "altivec_vsldoi_4sf"
15352 [(set (match_operand:V4SF 0 "register_operand" "=v")
15353 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
15354 (match_operand:V4SF 2 "register_operand" "v")
15355 (match_operand:QI 3 "immediate_operand" "i")] 164))]
15357 "vsldoi %0, %1, %2, %3"
15358 [(set_attr "type" "vecperm")])
15360 (define_insn "altivec_vsldoi_8hi"
15361 [(set (match_operand:V8HI 0 "register_operand" "=v")
15362 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
15363 (match_operand:V8HI 2 "register_operand" "v")
15364 (match_operand:QI 3 "immediate_operand" "i")] 165))]
15366 "vsldoi %0, %1, %2, %3"
15367 [(set_attr "type" "vecperm")])
15369 (define_insn "altivec_vsldoi_16qi"
15370 [(set (match_operand:V16QI 0 "register_operand" "=v")
15371 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
15372 (match_operand:V16QI 2 "register_operand" "v")
15373 (match_operand:QI 3 "immediate_operand" "i")] 166))]
15375 "vsldoi %0, %1, %2, %3"
15376 [(set_attr "type" "vecperm")])
15378 (define_insn "altivec_vupkhsb"
15379 [(set (match_operand:V8HI 0 "register_operand" "=v")
15380 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
15383 [(set_attr "type" "vecperm")])
15385 (define_insn "altivec_vupkhpx"
15386 [(set (match_operand:V4SI 0 "register_operand" "=v")
15387 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
15390 [(set_attr "type" "vecperm")])
15392 (define_insn "altivec_vupkhsh"
15393 [(set (match_operand:V4SI 0 "register_operand" "=v")
15394 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
15397 [(set_attr "type" "vecperm")])
15399 (define_insn "altivec_vupklsb"
15400 [(set (match_operand:V8HI 0 "register_operand" "=v")
15401 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
15404 [(set_attr "type" "vecperm")])
15406 (define_insn "altivec_vupklpx"
15407 [(set (match_operand:V4SI 0 "register_operand" "=v")
15408 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
15411 [(set_attr "type" "vecperm")])
15413 (define_insn "altivec_vupklsh"
15414 [(set (match_operand:V4SI 0 "register_operand" "=v")
15415 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
15418 [(set_attr "type" "vecperm")])
15420 ;; AltiVec predicates.
15422 (define_expand "cr6_test_for_zero"
15423 [(set (match_operand:SI 0 "register_operand" "=r")
15429 (define_expand "cr6_test_for_zero_reverse"
15430 [(set (match_operand:SI 0 "register_operand" "=r")
15433 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
15437 (define_expand "cr6_test_for_lt"
15438 [(set (match_operand:SI 0 "register_operand" "=r")
15444 (define_expand "cr6_test_for_lt_reverse"
15445 [(set (match_operand:SI 0 "register_operand" "=r")
15448 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
15452 ;; We can get away with generating the opcode on the fly (%3 below)
15453 ;; because all the predicates have the same scheduling parameters.
15455 (define_insn "altivec_predicate_v4si"
15457 (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
15458 (match_operand:V4SI 2 "register_operand" "v")
15459 (match_operand 3 "any_operand" "")] 173))
15460 (clobber (match_scratch:V4SI 0 "=v"))]
15463 [(set_attr "type" "veccmp")])
15465 (define_insn "altivec_predicate_v4sf"
15467 (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
15468 (match_operand:V4SF 2 "register_operand" "v")
15469 (match_operand 3 "any_operand" "")] 174))
15470 (clobber (match_scratch:V4SF 0 "=v"))]
15473 [(set_attr "type" "veccmp")])
15475 (define_insn "altivec_predicate_v8hi"
15477 (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
15478 (match_operand:V8HI 2 "register_operand" "v")
15479 (match_operand 3 "any_operand" "")] 175))
15480 (clobber (match_scratch:V8HI 0 "=v"))]
15483 [(set_attr "type" "veccmp")])
15485 (define_insn "altivec_predicate_v16qi"
15487 (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
15488 (match_operand:V16QI 2 "register_operand" "v")
15489 (match_operand 3 "any_operand" "")] 175))
15490 (clobber (match_scratch:V16QI 0 "=v"))]
15493 [(set_attr "type" "veccmp")])
15495 (define_insn "altivec_mtvscr"
15496 [(unspec_volatile [(match_operand:V4SI 0 "register_operand" "v")] 186)]
15499 [(set_attr "type" "vecsimple")])
15501 (define_insn "altivec_mfvscr"
15502 [(set (match_operand:V8HI 0 "register_operand" "=v")
15503 (unspec_volatile:V8HI [(const_int 0)] 187))]
15506 [(set_attr "type" "vecsimple")])
15508 (define_insn "altivec_dssall"
15509 [(unspec [(const_int 0)] 188)]
15512 [(set_attr "type" "vecsimple")])
15514 (define_insn "altivec_dss"
15515 [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
15518 [(set_attr "type" "vecsimple")])
15520 (define_insn "altivec_dst"
15521 [(unspec [(match_operand:SI 0 "register_operand" "b")
15522 (match_operand:SI 1 "register_operand" "r")
15523 (match_operand:QI 2 "immediate_operand" "i")] 190)]
15526 [(set_attr "type" "vecsimple")])
15528 (define_insn "altivec_dstt"
15529 [(unspec [(match_operand:SI 0 "register_operand" "b")
15530 (match_operand:SI 1 "register_operand" "r")
15531 (match_operand:QI 2 "immediate_operand" "i")] 191)]
15534 [(set_attr "type" "vecsimple")])
15536 (define_insn "altivec_dstst"
15537 [(unspec [(match_operand:SI 0 "register_operand" "b")
15538 (match_operand:SI 1 "register_operand" "r")
15539 (match_operand:QI 2 "immediate_operand" "i")] 192)]
15542 [(set_attr "type" "vecsimple")])
15544 (define_insn "altivec_dststt"
15545 [(unspec [(match_operand:SI 0 "register_operand" "b")
15546 (match_operand:SI 1 "register_operand" "r")
15547 (match_operand:QI 2 "immediate_operand" "i")] 193)]
15550 [(set_attr "type" "vecsimple")])
15552 (define_insn "altivec_lvsl"
15553 [(set (match_operand:V16QI 0 "register_operand" "=v")
15554 (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
15555 (match_operand:SI 2 "register_operand" "r")] 194))]
15558 [(set_attr "type" "vecload")])
15560 (define_insn "altivec_lvsr"
15561 [(set (match_operand:V16QI 0 "register_operand" "=v")
15562 (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
15563 (match_operand:SI 2 "register_operand" "r")] 195))]
15566 [(set_attr "type" "vecload")])
15568 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
15569 ;; identical rtl but different instructions-- and gcc gets confused.
15571 (define_insn "altivec_lvebx"
15573 [(set (match_operand:V16QI 0 "register_operand" "=v")
15574 (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b")
15575 (match_operand:SI 2 "register_operand" "r"))))
15576 (unspec [(const_int 0)] 196)])]
15579 [(set_attr "type" "vecload")])
15581 (define_insn "altivec_lvehx"
15583 [(set (match_operand:V8HI 0 "register_operand" "=v")
15585 (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
15586 (match_operand:SI 2 "register_operand" "r"))
15588 (unspec [(const_int 0)] 197)])]
15591 [(set_attr "type" "vecload")])
15593 (define_insn "altivec_lvewx"
15595 [(set (match_operand:V4SI 0 "register_operand" "=v")
15597 (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
15598 (match_operand:SI 2 "register_operand" "r"))
15600 (unspec [(const_int 0)] 198)])]
15603 [(set_attr "type" "vecload")])
15605 (define_insn "altivec_lvxl"
15607 [(set (match_operand:V4SI 0 "register_operand" "=v")
15608 (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
15609 (match_operand:SI 2 "register_operand" "r"))))
15610 (unspec [(const_int 0)] 213)])]
15613 [(set_attr "type" "vecload")])
15615 (define_insn "altivec_lvx"
15616 [(set (match_operand:V4SI 0 "register_operand" "=v")
15617 (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
15618 (match_operand:SI 2 "register_operand" "r"))))]
15621 [(set_attr "type" "vecload")])
15623 (define_insn "altivec_stvx"
15626 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
15627 (match_operand:SI 1 "register_operand" "r"))
15629 (match_operand:V4SI 2 "register_operand" "v"))
15630 (unspec [(const_int 0)] 201)])]
15633 [(set_attr "type" "vecstore")])
15635 (define_insn "altivec_stvxl"
15638 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
15639 (match_operand:SI 1 "register_operand" "r"))
15641 (match_operand:V4SI 2 "register_operand" "v"))
15642 (unspec [(const_int 0)] 202)])]
15645 [(set_attr "type" "vecstore")])
15647 (define_insn "altivec_stvebx"
15650 (plus:SI (match_operand:SI 0 "register_operand" "b")
15651 (match_operand:SI 1 "register_operand" "r")))
15652 (match_operand:V16QI 2 "register_operand" "v"))
15653 (unspec [(const_int 0)] 203)])]
15656 [(set_attr "type" "vecstore")])
15658 (define_insn "altivec_stvehx"
15661 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
15662 (match_operand:SI 1 "register_operand" "r"))
15664 (match_operand:V8HI 2 "register_operand" "v"))
15665 (unspec [(const_int 0)] 204)])]
15668 [(set_attr "type" "vecstore")])
15670 (define_insn "altivec_stvewx"
15673 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
15674 (match_operand:SI 1 "register_operand" "r"))
15676 (match_operand:V4SI 2 "register_operand" "v"))
15677 (unspec [(const_int 0)] 205)])]
15680 [(set_attr "type" "vecstore")])
15682 (define_insn "absv16qi2"
15683 [(set (match_operand:V16QI 0 "register_operand" "=v")
15684 (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
15685 (clobber (match_scratch:V16QI 2 "=v"))
15686 (clobber (match_scratch:V16QI 3 "=v"))]
15688 "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
15689 [(set_attr "type" "altivec")
15690 (set_attr "length" "12")])
15692 (define_insn "absv8hi2"
15693 [(set (match_operand:V8HI 0 "register_operand" "=v")
15694 (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
15695 (clobber (match_scratch:V8HI 2 "=v"))
15696 (clobber (match_scratch:V8HI 3 "=v"))]
15698 "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
15699 [(set_attr "type" "altivec")
15700 (set_attr "length" "12")])
15702 (define_insn "absv4si2"
15703 [(set (match_operand:V4SI 0 "register_operand" "=v")
15704 (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
15705 (clobber (match_scratch:V4SI 2 "=v"))
15706 (clobber (match_scratch:V4SI 3 "=v"))]
15708 "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
15709 [(set_attr "type" "altivec")
15710 (set_attr "length" "12")])
15712 (define_insn "absv4sf2"
15713 [(set (match_operand:V4SF 0 "register_operand" "=v")
15714 (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
15715 (clobber (match_scratch:V4SF 2 "=v"))
15716 (clobber (match_scratch:V4SF 3 "=v"))]
15718 "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3"
15719 [(set_attr "type" "altivec")
15720 (set_attr "length" "12")])
15722 (define_insn "altivec_abss_v16qi"
15723 [(set (match_operand:V16QI 0 "register_operand" "=v")
15724 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
15725 (clobber (match_scratch:V16QI 2 "=v"))
15726 (clobber (match_scratch:V16QI 3 "=v"))]
15728 "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
15729 [(set_attr "type" "altivec")
15730 (set_attr "length" "12")])
15732 (define_insn "altivec_abss_v8hi"
15733 [(set (match_operand:V8HI 0 "register_operand" "=v")
15734 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
15735 (clobber (match_scratch:V8HI 2 "=v"))
15736 (clobber (match_scratch:V8HI 3 "=v"))]
15738 "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
15739 [(set_attr "type" "altivec")
15740 (set_attr "length" "12")])
15742 (define_insn "altivec_abss_v4si"
15743 [(set (match_operand:V4SI 0 "register_operand" "=v")
15744 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
15745 (clobber (match_scratch:V4SI 2 "=v"))
15746 (clobber (match_scratch:V4SI 3 "=v"))]
15748 "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
15749 [(set_attr "type" "altivec")
15750 (set_attr "length" "12")])